diff --git a/.gitattributes b/.gitattributes index a6344aac8c09253b3b630fb776ae94478aa0275b..4757fc72cdd035b666e98c371a99a93801e2da93 100644 --- a/.gitattributes +++ b/.gitattributes @@ -33,3 +33,4 @@ saved_model/**/* filter=lfs diff=lfs merge=lfs -text *.zip filter=lfs diff=lfs merge=lfs -text *.zst filter=lfs diff=lfs merge=lfs -text *tfevents* filter=lfs diff=lfs merge=lfs -text +*.jsonl filter=lfs diff=lfs merge=lfs -text diff --git a/LICENSE b/LICENSE new file mode 100644 index 0000000000000000000000000000000000000000..63447fd8bbbf720abce8bb9794177779c8fb5bb1 --- /dev/null +++ b/LICENSE @@ -0,0 +1,21 @@ +Copyright (c) Microsoft Corporation. + +MIT License + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED *AS IS*, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE. \ No newline at end of file diff --git a/README.md b/README.md new file mode 100644 index 0000000000000000000000000000000000000000..74db9e81080f8b61cafa74998c24b9e4c6b812e7 --- /dev/null +++ b/README.md @@ -0,0 +1,318 @@ +--- +pretty_name: "VEGA" +language: + - code +tags: + - C++/C Code + - Compiler Backend +license: "cc-by-4.0" +--- + +# VEGA: Automatically Generating Compiler Backends Using a Pre-Trained Transformer Model + +VEGA is an AI-driven system aimed at easing the development burden of compiler backends for new targets. + +This repository contains code and data for reproducing experimental results. + +For detailed description of each script, please refer to the Artifact Appendix of our paper. + + +## 1. Directory Structure +``` +VEGA_AE +|──dataset +|──saved_models +| |──Fine_Tuned_Model +| |──New_Fine_Tuned_Model +| └──UnixCoder +|——Scripts +| |──Exp +| | |──Accuracy +| | |──Correction +| | |──ForkFlow +| | |──Performance +| | └──Time +| └──UnixCoder +└──Fixed_VEGA_LLVM + |──llvm-riscv + |──llvm-ri5cy + └──llvm-xcore +``` +## 2. Hardware Dependency + +- Intel(R)Xeon(R)Gold 6132 CPU @ 2.60GHz +- 8 Nvidia Tesla V100 GPU, each with 16 GB Memory + +## 3. Software Dependency +- CUDA == 11.4 +- python version == 3.8.1 +- pip install -r requirements.txt + + +## 4. Fine-Tuning + +Run fine-tuning with: +``` +$ bash run_fine_tuning.sh +``` +Customize parameters for fine-tuning by modifying following options in the ```run_fine_tuning.sh```. +``` + --model_name_or_path ../../saved_models/UnixCoder \ + --train_filename ../../dataset/train.jsonl \ + --dev_filename ../../dataset/valid.jsonl \ + --output_dir ../../saved_models/New_Fine_Tuned_Model \ + --beam_size 4 \ + --train_batch_size 96 \ + --eval_batch_size 80 \ + --learning_rate 6e-5 \ + --num_train_epochs 50 \ + --mse_loss_weight 0.9 \ + --ce_loss_weight 0.1 +``` +The fine-tuned model will be saved in ```--output_dir```. + +## 5. Code Generation + +We have provided a fine-tuned model in ```./saved_models/Fine_Tuned_Model```. + +We have also provided a script fot function test, which only generates a single function for RI5CY, taking less than 3 minutes with 8 V100 GPU. + + + +Run function test with: + +``` +$ bash run_function_test.sh +``` + +When the ```run_function_test.sh``` script begins execution, the command line displays +``` +$ " Start Function Inferencing !" +``` +Upon completion of the code generation, the script outputs +``` +$ " Finished Function Inferencing : xxx secs" +``` + +The inference result will be saved in ```--output_dir/result.jsonl```. + +Run code generation with: + +``` +$ bash run_test.sh +``` + +Customize parameters for inferencing by modifying following options in the ```run_test.sh```. +``` + --model_name_or_path ../../saved_models/UnixCoder \ + --test_filename ../../dataset/test.jsonl \ + --output_dir ../../saved_models/Fine_Tuned_Model \ + --beam_size 4 \ + --train_batch_size 256 \ + --eval_batch_size 256 \ + --learning_rate 6e-5 \ + --gradient_accumulation_steps 2 \ + --num_train_epochs 10 \ + --mse_loss_weight 0.9 \ + --ce_loss_weight 0.1 +``` +Users can inference with their own fine-tuned model by changing the ```--output_dir``` option. + + + +When the ```run_test.sh``` script begins execution, the command line displays +``` +$ " Start Inferencing !" +``` +Upon completion of the code generation, the script outputs +``` +$ " Finished Inferencing : xxx secs" +``` + +The inference result will be saved in ```--output_dir/result.jsonl```. + +The ```--output_dir``` parameter specifies the directory where the fine-tuned model is saved, such as ```./saved_models/Fine_Tuned_Model```. + +## 6. Reproducing Results in the Experiment + +We provide the scripts to reproduce each Figure/Table from the paper, along with the corresponding output result files, in the following table: + + +| Script | Description | Output | Figure/Table | +| ---------------------------------------------- | ----------------------------------------------------------------------------------------------------------------------------------------- | ------------------------------------------------------ | -------------- | +| ./Scripts/Exp/Time/calculate_time.py | Calculate the time overhead. | ./Scripts/Exp/Time/time_overhead.csv | Fig.7 | +| ./Scripts/Exp/Accuracy/calculate_accuracy.py | Calculate the function-level accuracy. | ./Scripts/Exp/Accuracy/vega_result.csv | Fig.8 | +| ./Scripts/Exp/Accuracy/calculate_purple.py | Calculate the the percentage of functions accurately synthesized from the statements of various existing targets (Purple Bar in Fig.8). | ./Scripts/Exp/Accuracy/fig8_purple.csv | Fig.8 | +| ./Scripts/Exp/Accuracy/calculate_accuracy.py | Calculate the percentage of three types of error. | ./Scripts/Exp/Accuracy/err_percentage.csv | Table.2 | +| ./Scripts/Exp/ForkFlow/calculate_forkflow.py | Calculate the statement-level accracy of VEGA and ForkFlow. | ./Scripts/Exp/ForkFlow/forkflow_result.csv | Fig.9 | +| ./Scripts/Exp/ForkFlow/calculate_forkflow.py | Calculate the number of accurate statements of VEGA and ForkFlow. | ./Scripts/Exp/ForkFlow/mod_lines.csv | Table.3 | +| - | Recorded time required by Developer A and B to modify the VEGA-generated RISC-V backend. | ./Scripts/Exp/Correction/Correction_Time.xlsx | Table. 4 | +| - | Recorded time required for LLVM-Base (-O0), LLVM-Base (-O3), and LLVM-VEGA (-O3) to pass benchmarks. | ./Scripts/Exp/Performance/BenchMark.xlsx | Fig. 10 | +### 6.1 Results for Fig. 7 in Sec. 4.2 + +In the code generation process, we set a batch size of 256 on 8 Nvidia Tesla V100 GPU (each with 16GB memory), meaning each batch contains 256 statements. Since each batch may include statements from different function modules, we did not directly measure the generation time for each function modules of three targets (RISC-V, RI5CY, xCORE) during execution. Instead, we calculated the average inference time of each batch (25 seconds) and then derived the inference time of each statement (25/256 seconds). With the total number of statements within each function module of each target, we subsequently calculated the total inference time required for each function module of each target. + + +- Command: +``` +$ python ./Scripts/Exp/Time/calculate_time.py +``` + + +- Results: +``` +./Scripts/Exp/Time/time_overhead.csv +``` + +### 6.2 Results for Fig. 8 in Sec. 4.2 + + +In our experiment, we employed the Pass@1 evaluation metric, which involves replacing each VEGA-generated function individually within the official LLVM (LLVM-Base), then running regression tests to verify the correctness of the replaced function. This process is highly time-intensive, as a single regression test run generally takes about half an hour. Thus, sequentially testing all 1,454 VEGA-generated functions across three targets would require approximately 727 hours. + +To simplify this process, we recorded the ground truth for each statement based on the Pass@1 experiment results. Additionally, we documented a list of functions containing Err-Def errors (i.e., errors due to missing necessary statements in the function template; functions with Err-Def can not pass all regression tests). This allowed us to transform the Pass@1 testing process into an Exact Match evaluation. + +In this Exact Match evaluation, each statement is deemed correct if the VEGA-generated code matches the ground truth and the confidence score aligns. A function is considered correct if all statements within it are accurate and it is free from Err-Def errors. + +- Command: +``` +$ cp --output_dir/result.jsonl ./Scripts/Exp/Accuracy +$ python ./Scripts/Exp/Accuracy/calculate_accuracy.py +``` + +This script will automatically analyze the VEGA's output from "result.jsonl" and compare the generated code and confidence scores with the ground truth. Based on this comparison, it will determine whether each function is correct. + +- Accuracy Results: +``` +./Scripts/Exp/Accuracy/vega_result.csv +``` + + +We also provide a script for calculating the proportion of "Accurate Functions with Integrated Statements Across Multiple Targets". The value corresponding to the purple bar in Fig. 8. + + +- Command: +``` +$ python ./Scripts/Exp/Accuracy/calculate_purple.py +``` + + +- Results: +``` +./Scripts/Exp/Accuracy/fig8_purple.csv +``` + + +We also provided manually fixed VEGA-generated RISC-V, RI5CY and xCORE backend, which can be used to run regression tests and pass@1 experiments. **Note that the compilation of llvm-riscv and llvm-ri5cy requires gcc-9.5.0 version, and the compilation of llvm-xcore requires gcc-4.0.0 version.** + +``` +Download from Google Drive: https://drive.google.com/file/d/1VD3H60vMvtnRtMkS6h0qZWTKkjcUzLsw/view?usp=drive_link +$ unzip Fixed_VEGA_LLVM.zip +``` + +- Command for Running RISC-V Backend: +``` +$ cd ./Fixed_VEGA_LLVM +$ bash run_llvm_riscv.sh +``` +- Results for Regression Tests of the RISC-V Backend: +``` +$ Testing Time: xxx s +$ Passed : 16005 +``` + +- Command for Running RI5CY Backend: +``` +$ cd ./Fixed_VEGA_LLVM +$ bash run_llvm_ri5cy.sh +``` +- Results for Regression Tests of the RI5CY Backend: +``` +$ Testing Time: xxx s +$ Passed : 16040 +``` + +- Command for Running xCORE Backend: +``` +$ cd ./Fixed_VEGA_LLVM +$ vim run_llvm_xcore.sh +$ Set the prefix option to the path where you want to install LLVM. +$ Set the CC and llvmgccdir option to the path of gcc-4.0.0 version, change the CXX option to the path of g++-4.0.0 version. +$ bash run_llvm_xcore.sh +``` +- Results for Regression Tests of the xCORE Backend: +``` +$ Testing Time: xxx s +$ Passed : 5466 +``` + +### 6.3 Results for Table. 2 in Sec. 4.2 + +Executing the script in (2) will also yield the proportion of the three types of errors for each target. + + +- Command: +``` +$ python ./Scripts/Exp/Accuracy/calculate_accuracy.py +``` + + +- Results: +``` +./Scripts/Exp/Accuracy/err_percentage.csv +``` + + +### 6.4 Results for Fig. 9 in Sec. 4.2 + +We modified the functions generated by VEGA and functions in the MIPS backend (ForkFlow) to ensure they can correctly run on the RISC-V, RI5CY, and xCORE backends respectively. By executing the following script, the proportion of accurate and modified statements of the VEGA-generated functions and ForkFlow processes will be automatically calculated. + +- Command: +``` +$ python ./Scripts/Exp/ForkFlow/calculate_forkflow.py +``` + + +- Results: +``` +./Scripts/Exp/ForkFlow/forkflow_result.csv +``` + +### 6.5 Results for Table. 3 in Sec. 4.2 + +Executing the script in 6.4 will also output the number of statements accurately generated and requiring manual correction by VEGA across seven function modules for RISC-V, RI5CY, and xCORE. + + +- Command: +``` +$ python ./Scripts/Exp/ForkFlow/calculate_forkflow.py +``` + + +- Results: +``` +./Scripts/Exp/ForkFlow/mod_lines.csv +``` + + +### 6.6 Results for Table. 4 in Sec. 4.2 + +The data in Table. 4 record the time required by two developers to modify the VEGA-generated RISC-V backend. As this is a human-based experiment, we can only provide the recorded time for modifying each function within the VEGA-generated RISC-V backend. + +- Results: +``` +./Scripts/Exp/Correction/Correction_Time.xlsx +``` + +This file contains two sheets, each corresponding to the time required by Developer A and Developer B to modify the VEGA-generated RISC-V backend. Each sheet includes four columns: the first three indicate the function module, file, and function name of each function in the VEGA-generated RISC-V backend, while the final column specifies the time spent modifying each function, measured in seconds. By summing the data in each sheet according to function modules, we calculated the total time (in hours) that Developer A and Developer B spent on each module. + +### 6.7 Results for Fig. 10 in Sec. 4.3 + +Due to restrictions associated with the commercial license, we are unable to provide the source code of the SPEC 2017 CPU benchmark directly used in this experiment. Furthermore, the testing duration for SPEC 2017 CPU is highly time-consuming, requiring approximately 565 hours. To address these constraints, we provide our recorded experimental data, which can be accessed at: + + +- Results: +``` +./Scripts/Exp/Performance/BenchMark.xlsx +``` + +Each sheet in this recorded data is named with the experimental target and benchmark tested, e.g., "RISCV (SPEC 2017CPU)". We recorded the time required for LLVM-Base (-O0), LLVM-Base (-O3), and LLVM-VEGA (-O3) to successfully pass each test case, and calculated the corresponding speedup ratios respectively. diff --git a/Scripts/Exp/Accuracy/Accurate_Func_Merged.csv b/Scripts/Exp/Accuracy/Accurate_Func_Merged.csv new file mode 100644 index 0000000000000000000000000000000000000000..3486f4b48baf1d28ea789af82a6147b31fcc6c2d --- /dev/null +++ b/Scripts/Exp/Accuracy/Accurate_Func_Merged.csv @@ -0,0 +1,171 @@ +Allocation,RegisterInfo,getCalleeSavedRegs,PULP +Allocation,RegisterInfo,getFrameRegister,PULP +Assembler,AsmParser,isRV64,PULP +Assembler,AsmParser,isRV64-2,PULP +Assembler,AsmParser,isSImm6NonZero,PULP +Assembler,AsmParser,isSImm9Lsb0,PULP +Assembler,AsmParser,parseImmediate,PULP +Assembler,AsmParser,validateTargetOperandClass,PULP +Assembler,AsmPrinter,isSImm12Lsb0,PULP +Disassembler,Disassembler,addImplySP,PULP +Disassembler,Disassembler,DecodePulpV2RegisterClass,PULP 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+import csv +import copy + + +import pathlib +import time + +folder = str(pathlib.Path(__file__).parent.resolve()) +#Total_encas + +func_num_dic = { + "riscv" : 568, + "pulp" : 698, + "xcore" : 188 +} + + + +wrong_lis_all = [] +wrong_stmt = [] +err_def_dic = {} +def get_wrong_list(): + global wrong_stmt + global wrong_lis_all + global err_def_dic + with open(folder+"/wrong_func_list_def.csv", 'r', encoding='utf-8') as fcsv: + reader = csv.reader(fcsv) + for row in reader: + if row[0] == "idx": + continue + wrong_stmt.append(row[0].strip().lower() + " " + row[1].strip().lower() + " " + row[2].strip().lower()) + wrong_lis_all.append(" ".join(row)) + if " ".join([row[2], row[3]]) not in err_def_dic.keys(): + err_def_dic[" ".join([row[2], row[3]])]= 1 + else: + err_def_dic[" ".join([row[2], row[3]])] += 1 + +def calculate_accuracy(): + func_res = {} + stable_stmt_dic = {} + all_func_lis = [] + global wrong_stmt + global wrong_lis_all + global err_def_dic + total_dic = {} + wrong_dic = {} + asm_file = [] + for line in open(folder+"/result.jsonl", 'r', encoding="utf-8"): + dic = json.loads(line) + all_func_lis.append(dic["File"].strip().lower() + " " + dic["Func"].strip().lower() + " " + dic["Target"].strip().lower()) + + if int(dic["vega_pre"]) == 1: + if " ".join([dic["Target"], dic["Module"], dic["File"], dic["Func"]]) not in func_res.keys(): + func_res[" ".join([dic["Target"], dic["Module"], dic["File"], dic["Func"]])] = [dic["vega_code"].replace("zmtarzm", dic["Target"])] + else: + func_res[" ".join([dic["Target"], dic["Module"], dic["File"], dic["Func"]])].append(dic["vega_code"].replace("zmtarzm", dic["Target"])) + if " ".join([dic["Target"], dic["Module"]]) not in stable_stmt_dic.keys(): + stable_stmt_dic[" ".join([dic["Target"], dic["Module"]])] = [0, 0] + if dic["Stable"].lower() == "true": + stable_stmt_dic[" ".join([dic["Target"], dic["Module"]])][0] += 1 + stable_stmt_dic[" ".join([dic["Target"], dic["Module"]])][1] += 1 + else: + stable_stmt_dic[" ".join([dic["Target"], dic["Module"]])][1] += 1 + + if dic["Target"] + " " + dic["Module"] not in total_dic.keys(): + total_dic[dic["Target"] + " " + dic["Module"]] = [dic["File"].strip() + " " + dic["Func"].strip() + " " + dic["Target"].strip()] + wrong_dic[dic["Target"] + " " + dic["Module"]] = [] + else: + total_dic[dic["Target"] + " " + dic["Module"]].append(dic["File"].strip() + " " + dic["Func"].strip() + " " + dic["Target"].strip()) + if dic["File"].strip().lower() + " " + dic["Func"].strip().lower() + " " + dic["Target"].strip().lower() in wrong_stmt: + #print(dic["File"].strip() + " " + dic["Func"].strip() + " " + dic["Target"].strip()) + wrong_dic[dic["Target"] + " " + dic["Module"]].append(dic["File"].strip() + " " + dic["Func"].strip() + " " + dic["Target"].strip()) + if dic["ans_code"].replace(" ", "") != dic["vega_code"].replace(" ", "") or dic["ans_pre"] != dic["vega_pre"]: + wrong_dic[dic["Target"] + " " + dic["Module"]].append(dic["File"].strip() + " " + dic["Func"].strip() + " " + dic["Target"].strip()) + if dic["ans_code"] != dic["vega_code"]: + wrong_lis_all.append(" ".join([dic["File"], dic["Func"], dic["Target"], dic["Module"], "Err_V"])) + if dic["ans_pre"] != dic["vega_pre"]: + wrong_lis_all.append(" ".join([dic["File"], dic["Func"], dic["Target"], dic["Module"], "Err_CS"])) + + all_func_lis = list(set(all_func_lis)) + + with open(folder+"/vega_result.csv", 'a', encoding='utf-8', newline="") as f: + f_csv = csv.writer(f) + avg_dic = {} + all_dic = {} + for k in total_dic.keys(): + Correct_Func_Num = len(list(set(total_dic[k])))-len(list(set(wrong_dic[k]))) + Total_Func_Num = len(list(set(total_dic[k]))) + Accuracy_Func = 1-round(len(list(set(wrong_dic[k]))) * 1.0 / len(list(set(total_dic[k]))), 3) + Wrong_Func_Percentage = round(len(list(set(wrong_dic[k]))) * 1.0 / len(list(set(total_dic[k]))), 3) + Pre_Equal_1_Stmt_Percentage = round(stable_stmt_dic[k][0]/stable_stmt_dic[k][1], 3) + Pre_Less_1_Stmt_Percentage = 1 - round(stable_stmt_dic[k][0]/stable_stmt_dic[k][1], 3) + if k.split(" ")[0] not in avg_dic.keys(): + avg_dic[k.split(" ")[0]] = Accuracy_Func + all_dic[k.split(" ")[0]] = Correct_Func_Num + else: + avg_dic[k.split(" ")[0]] += Accuracy_Func + all_dic[k.split(" ")[0]] += Correct_Func_Num + tem_k = k.replace("PULP", "RI5CY") + f_csv.writerow(tem_k.split(" ") + [Correct_Func_Num, Total_Func_Num, Accuracy_Func, Wrong_Func_Percentage, Pre_Equal_1_Stmt_Percentage, Pre_Less_1_Stmt_Percentage]) + + for k in avg_dic: + if k.lower() == "riscv": + f_csv.writerow([k, "AVG", round(avg_dic[k] / 7.0, 3)]) + f_csv.writerow([k, "ALL", round(all_dic[k] / func_num_dic[k.lower()], 3)]) + elif k.lower() == "pulp": + f_csv.writerow(["RI5CY", "AVG", round(avg_dic[k] / 7.0, 3)]) + f_csv.writerow(["RI5CY", "ALL", round(all_dic[k] / func_num_dic[k.lower()], 3)]) + else: + f_csv.writerow([k, "AVG", round(avg_dic[k] / 6.0, 3)]) + f_csv.writerow([k, "ALL", round(all_dic[k] / func_num_dic[k.lower()], 3)]) + + + + for k in func_res.keys(): + Tar_Path = folder + "/../ForkFlow/VEGA_Code/" + "/".join(k.split(" ")) + ".cpp" + Tar_Path = Tar_Path.replace("enum/NodeType", "enum NodeType") + Tar_Path = Tar_Path.replace("enum/CondCode", "enum CondCode") + Tar_Path = Tar_Path.replace("ExpandSSRInsts/ExpandPseudo", "ExpandSSRInsts/ExpandSSRInsts") + if os.path.exists(Tar_Path): + with open(Tar_Path, 'w') as file: + for idx, l in enumerate(func_res[k]): + if idx < len(func_res[k])-1: + file.write(l) + file.write("\n") + else: + file.write(l) + else: + print(Tar_Path) + + return total_dic + + +if __name__ == '__main__': + get_wrong_list() + with open(folder+"/vega_result.csv", 'w', encoding='utf-8', newline="") as f: + f_csv = csv.writer(f) + f_csv.writerow(["Target", "Module", "Correct", "Total", "Accurate", "Inaccurate", "Confidence Score≈1.00", "Confidence Score in [0.50, 1.00)"]) + total_dic = calculate_accuracy() + wrong_lis_all = list(set(wrong_lis_all)) + with open(folder+"/wrong_list_all.csv", 'w', encoding='utf-8', newline="") as f: + f_csv = csv.writer(f) + for err in wrong_lis_all: + f_csv.writerow(err.split(" ")) + with open(folder+"/../ForkFlow/wrong_list_all.csv", 'w', encoding='utf-8', newline="") as f: + f_csv = csv.writer(f) + for err in wrong_lis_all: + f_csv.writerow(err.split(" ")) + + wrong_dic = {} + with open(folder+"/wrong_list_all.csv", 'r', encoding='utf-8') as f: + f_csv = csv.reader(f) + for row in f_csv: + if " ".join([row[-3].lower(), row[-1].lower()]) not in wrong_dic.keys(): + wrong_dic[" ".join([row[-3].lower(), row[-1].lower()])] = 1 + else: + wrong_dic[" ".join([row[-3].lower(), row[-1].lower()])] += 1 + #print(wrong_dic) + target_func_num_dic = {} + for k in total_dic: + if k.split(" ")[0].lower() not in target_func_num_dic: + target_func_num_dic[k.split(" ")[0].lower()] = len(list(set(total_dic[k]))) + else: + target_func_num_dic[k.split(" ")[0].lower()] += len(list(set(total_dic[k]))) + + with open(folder+"/err_percentage.csv", 'w', encoding='utf-8', newline = "") as f: + f_csv = csv.writer(f) + for k in target_func_num_dic: + #print(target_func_num_dic[k]) + for err_type in ["err_v", "err_cs", "err_def"]: + if k + " " + err_type in wrong_dic.keys(): + + f_csv.writerow([k.replace("pulp", "ri5cy"), err_type, round(float(wrong_dic[k + " " + err_type]) / float(target_func_num_dic[k]), 3)]) + else: + f_csv.writerow([k.replace("pulp", "ri5cy"), err_type, 0]) diff --git a/Scripts/Exp/Accuracy/calculate_purple.py b/Scripts/Exp/Accuracy/calculate_purple.py new file mode 100644 index 0000000000000000000000000000000000000000..4b982e368ec848bdee337383f9bb35cccbe8d428 --- /dev/null +++ b/Scripts/Exp/Accuracy/calculate_purple.py @@ -0,0 +1,42 @@ +import os, sys,string,re,glob + +import json +import csv +import copy + + +import pathlib +import time + +folder = str(pathlib.Path(__file__).parent.resolve()) +#Total_encas + + + +def calculate_template(): + total_dic = {} + for line in open(folder+"/result.jsonl", 'r', encoding="utf-8"): + dic = json.loads(line) + if dic["Target"].lower() + " " + dic["Module"].lower() not in total_dic.keys(): + total_dic[dic["Target"].lower() + " " + dic["Module"].lower()] = set() + total_dic[dic["Target"].lower() + " " + dic["Module"].lower()].add(dic["File"].strip() + " " + dic["Func"].strip() + " " + dic["Target"].strip()) + + + res_dic = {} + with open(folder+"/Accurate_Func_Merged.csv", 'r', encoding='utf-8') as f: + f_csv = csv.reader(f) + for row in f_csv: + if " ".join([row[-1], row[0]]).lower() not in res_dic: + res_dic[" ".join([row[-1], row[0]]).lower()] = 1 + else: + res_dic[" ".join([row[-1], row[0]]).lower()] += 1 + with open(folder+"/fig8_purple.csv", 'w', encoding='utf-8', newline="") as f: + f_csv = csv.writer(f) + for k in res_dic.keys(): + f_csv.writerow([k.split(' ')[0].replace("pulp", "ri5cy"), k.split(' ')[1], round(float(res_dic[k])/float(len(list(total_dic[k]))), 3)]) + + + +if __name__ == '__main__': + calculate_template() + \ No newline at end of file diff --git a/Scripts/Exp/Accuracy/wrong_func_list_def.csv b/Scripts/Exp/Accuracy/wrong_func_list_def.csv new file mode 100644 index 0000000000000000000000000000000000000000..71d80463d23a5f4d32a5356158a365687a834c26 --- /dev/null +++ b/Scripts/Exp/Accuracy/wrong_func_list_def.csv @@ -0,0 +1,366 @@ +RegisterInfo,eliminateFrameIndex,PULP,Allocation,Err_Def +RegisterInfo,getReservedRegs,PULP,Allocation,Err_Def +RegisterInfo,hasReservedSpillSlot,PULP,Allocation,Err_Def +AsmParser,addFenceArgOperands,PULP,Assembler,Err_Def +AsmParser,AsmParser,PULP,Assembler,Err_Def +AsmParser,classifySymbolRef,PULP,Assembler,Err_Def +AsmParser,defaultMaskRegOp,PULP,Assembler,Err_Def +AsmParser,getFeatureBits,PULP,Assembler,Err_Def +AsmParser,getRoundingMode,PULP,Assembler,Err_Def +AsmParser,isFenceArg,PULP,Assembler,Err_Def +AsmParser,isFRMArg,PULP,Assembler,Err_Def +AsmParser,MatchAndEmitInstruction,PULP,Assembler,Err_Def +AsmParser,matchRegisterNameHelper,PULP,Assembler,Err_Def +AsmParser,Operand2,PULP,Assembler,Err_Def +AsmParser,parseAtomicMemOp,PULP,Assembler,Err_Def +AsmParser,parseCallSymbol,PULP,Assembler,Err_Def +AsmParser,parseCSRSyestemRegister,PULP,Assembler,Err_Def +AsmParser,ParseDirective,PULP,Assembler,Err_Def +AsmParser,ParseInstruction,PULP,Assembler,Err_Def +AsmParser,parseJALOffset,PULP,Assembler,Err_Def +AsmParser,parseMaskReg,PULP,Assembler,Err_Def +AsmParser,parseMemOpBaseReg,PULP,Assembler,Err_Def +AsmParser,parseOperand,PULP,Assembler,Err_Def +AsmParser,parsePseudoJumpSymbol,PULP,Assembler,Err_Def +AsmParser,parseRegister2,PULP,Assembler,Err_Def +AsmParser,parseVTypeI,PULP,Assembler,Err_Def +AsmParser,print,PULP,Assembler,Err_Def +Disassembler,decodeFRMArg,PULP,Disassembler,Err_Def +Disassembler,DecodeGPRRegisterClass,PULP,Disassembler,Err_Def +Disassembler,decodeRVCInstrRdRs1UImm,PULP,Disassembler,Err_Def +Disassembler,decodeRVCInstrRdSImm,PULP,Disassembler,Err_Def +Disassembler,decodeRVCInstrSImm,PULP,Disassembler,Err_Def +Disassembler,getInstruction,PULP,Disassembler,Err_Def +AsmBackend,AsmBackend,PULP,Emission,Err_Def +AsmBackend,evaluateTargetFixup,PULP,Emission,Err_Def +AsmBackend,relaxInstruction,PULP,Emission,Err_Def +AsmBackend,requiresDiffExpressionRelocations,PULP,Emission,Err_Def +AsmBackend,shouldForceRelocation,PULP,Emission,Err_Def +AsmBackend,shouldInsertExtraNopBytesForCodeAlign,PULP,Emission,Err_Def +AsmBackend,shouldInsertFixupForCodeAlign,PULP,Emission,Err_Def +AsmBackend,willForceRelocations,PULP,Emission,Err_Def +BaseInfo,computeTargetABI,PULP,Emission,Err_Def +BaseInfo,validate,PULP,Emission,Err_Def +BaseInfo,VMTs,PULP,Emission,Err_Def +ELFStreamer,TargetELFStreamer,PULP,Emission,Err_Def +InstPrinter,printAtomicMemOp,PULP,Emission,Err_Def +InstPrinter,printCSRSystemRegister,PULP,Emission,Err_Def +InstPrinter,printFenceArg,PULP,Emission,Err_Def +InstPrinter,printFRMArg,PULP,Emission,Err_Def +InstPrinter,printInst,PULP,Emission,Err_Def +InstPrinter,printVMaskReg,PULP,Emission,Err_Def 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+PULPHardwareLoops,checkForImmediate,PULP,Optimization,Err_Def +PULPHardwareLoops,convertToHardwareLoop,PULP,Optimization,Err_Def +PULPHardwareLoops,findInductionRegister,PULP,Optimization,Err_Def +PULPHardwareLoops,getLoopTripCount,PULP,Optimization,Err_Def +PULPHardwareLoops,isInvalidLoopOperation,PULP,Optimization,Err_Def +PULPHardwareLoops,runOnMachineFunction,PULP,Optimization,Err_Def +SNITCHFrepLoops,checkForImmediate,PULP,Optimization,Err_Def +SNITCHFrepLoops,containsInvalidInstruction,PULP,Optimization,Err_Def +SNITCHFrepLoops,convertToHardwareLoop,PULP,Optimization,Err_Def +SNITCHFrepLoops,findBranchInstruction,PULP,Optimization,Err_Def +SNITCHFrepLoops,findInductionRegister,PULP,Optimization,Err_Def +SNITCHFrepLoops,getLoopTripCount,PULP,Optimization,Err_Def +SNITCHFrepLoops,isInvalidLoopOperation,PULP,Optimization,Err_Def +SNITCHFrepLoops,runOnMachineFunction,PULP,Optimization,Err_Def +InstrInfo,buildOutlinedFrame,PULP,Scheduling,Err_Def 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+AsmParser,MatchAndEmitInstruction,RISCV,Assembler,Err_Def +AsmParser,matchRegisterNameHelper,RISCV,Assembler,Err_Def +AsmParser,Operand2,RISCV,Assembler,Err_Def +AsmParser,parseAtomicMemOp,RISCV,Assembler,Err_Def +AsmParser,parseCallSymbol,RISCV,Assembler,Err_Def +AsmParser,parseCSRSyestemRegister,RISCV,Assembler,Err_Def +AsmParser,ParseDirective,RISCV,Assembler,Err_Def +AsmParser,ParseInstruction,RISCV,Assembler,Err_Def +AsmParser,parseJALOffset,RISCV,Assembler,Err_Def +AsmParser,parseMaskReg,RISCV,Assembler,Err_Def +AsmParser,parsePseudoJumpSymbol,RISCV,Assembler,Err_Def +AsmParser,parseRegister2,RISCV,Assembler,Err_Def +AsmParser,parseVTypeI,RISCV,Assembler,Err_Def +AsmParser,print,RISCV,Assembler,Err_Def +Disassembler,decodeFRMArg,RISCV,Disassembler,Err_Def +Disassembler,DecodeGPRRegisterClass,RISCV,Disassembler,Err_Def +Disassembler,decodeRVCInstrRdRs1UImm,RISCV,Disassembler,Err_Def +Disassembler,decodeRVCInstrRdSImm,RISCV,Disassembler,Err_Def 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+InstPrinter,printInst,RISCV,Emission,Err_Def +InstPrinter,printVMaskReg,RISCV,Emission,Err_Def +InstPrinter,printVTypeI,RISCV,Emission,Err_Def +MatInt,generateInstSeq,RISCV,Emission,Err_Def +MatInt,getIntMatCost,RISCV,Emission,Err_Def +MCCodeEmitter,encodeInstruction,RISCV,Emission,Err_Def +MCCodeEmitter,getImmOpValue,RISCV,Emission,Err_Def +MCCodeEmitter,getImmOpValueAsr1,RISCV,Emission,Err_Def +MCExpr,evaluateAsConstant,RISCV,Emission,Err_Def +MCExpr,getPCRelHiFixup,RISCV,Emission,Err_Def +TargetStreamer,emitTargetAttributes,RISCV,Emission,Err_Def +CleanupVSETVLI,runOnMachineBasicBlock,RISCV,Optimization,Err_Def +ExpandAtomicPseudoInsts,expandMI,RISCV,Optimization,Err_Def +ExpandPseudoInsts,expandMI,RISCV,Optimization,Err_Def +MergeBaseOffset,runOnMachineFunction,RISCV,Optimization,Err_Def +InstrInfo,buildOutlinedFrame,RISCV,Scheduling,Err_Def +InstrInfo,copyPhysReg,RISCV,Scheduling,Err_Def +InstrInfo,getInstSizeInBytes,RISCV,Scheduling,Err_Def +InstrInfo,getOutliningCandidateInfo,RISCV,Scheduling,Err_Def +InstrInfo,getOutliningType,RISCV,Scheduling,Err_Def +InstrInfo,insertIndirectBranch,RISCV,Scheduling,Err_Def +InstrInfo,insertOutlinedCall,RISCV,Scheduling,Err_Def +InstrInfo,isAsCheapAsAMove,RISCV,Scheduling,Err_Def +InstrInfo,isCopyInstrImpl,RISCV,Scheduling,Err_Def +InstrInfo,movImm,RISCV,Scheduling,Err_Def +InstrInfo,verifyInstruction,RISCV,Scheduling,Err_Def +MachineFunctionInfo,getMoveF64FrameIndex,RISCV,Scheduling,Err_Def +MachineFunctionInfo,useSaveRestoreLibCalls,RISCV,Scheduling,Err_Def +Subtarget,initializeSubtargetDependencies,RISCV,Scheduling,Err_Def +TargetMachine,addPreRegAlloc,RISCV,Scheduling,Err_Def +TargetMachine,TargetMachine,RISCV,Scheduling,Err_Def +TargetObjectFile,getModuleMetadata,RISCV,Scheduling,Err_Def +TargetObjectFile,isGlobalInSmallSection,RISCV,Scheduling,Err_Def +TargetTransformInfo,getIntImmCost,RISCV,Scheduling,Err_Def +TargetTransformInfo,getIntImmCostInst,RISCV,Scheduling,Err_Def +FrameLowering,canUseAsEpilogue,RISCV,Selection,Err_Def +FrameLowering,canUseAsPrologue,RISCV,Selection,Err_Def +FrameLowering,determineCalleeSaves,RISCV,Selection,Err_Def +FrameLowering,emitEpilogue,RISCV,Selection,Err_Def +FrameLowering,emitPrologue,RISCV,Selection,Err_Def +FrameLowering,getFrameIndexReference,RISCV,Selection,Err_Def +FrameLowering,restoreCalleeSavedRegisters,RISCV,Selection,Err_Def +FrameLowering,spillCalleeSavedRegisters,RISCV,Selection,Err_Def +ISelDAGtoDAG,MatchSLLIUW,RISCV,Selection,Err_Def +ISelDAGtoDAG,MatchSRLIUW,RISCV,Selection,Err_Def +ISelDAGtoDAG,PostprocessISelDAG,RISCV,Selection,Err_Def +ISelDAGtoDAG,Select,RISCV,Selection,Err_Def +ISelDAGtoDAG,selectVLOp,RISCV,Selection,Err_Def +ISelDAGtoDAG,selectVSplat,RISCV,Selection,Err_Def +ISelDAGtoDAG,selectVSplatSimm5,RISCV,Selection,Err_Def +ISelDAGtoDAG,selectVSplatUimm5,RISCV,Selection,Err_Def +ISelLowering,analyzeInputArgs,RISCV,Selection,Err_Def +ISelLowering,analyzeOutputArgs,RISCV,Selection,Err_Def +ISelLowering,CanLowerReturn,RISCV,Selection,Err_Def +ISelLowering,computeKnownBitsForTargetNode,RISCV,Selection,Err_Def +ISelLowering,ComputeNumSignBitsForTargetNode,RISCV,Selection,Err_Def +ISelLowering,decomposeMulByConstant,RISCV,Selection,Err_Def +ISelLowering,EmitInstrWithCustomInserter,RISCV,Selection,Err_Def +ISelLowering,emitLeadingFence,RISCV,Selection,Err_Def +ISelLowering,emitMaskedAtomicCmpXchgIntrinsic,RISCV,Selection,Err_Def +ISelLowering,emitMaskedAtomicRMWIntrinsic,RISCV,Selection,Err_Def +ISelLowering,emitTrailingFence,RISCV,Selection,Err_Def +ISelLowering,getAddr,RISCV,Selection,Err_Def +ISelLowering,getRegForInlineAsmConstraint,RISCV,Selection,Err_Def +ISelLowering,getRegisterByName,RISCV,Selection,Err_Def +ISelLowering,getStaticTLSAddr,RISCV,Selection,Err_Def +ISelLowering,getTgtMemIntrinsic,RISCV,Selection,Err_Def +ISelLowering,isDesirableToCommuteWithShift,RISCV,Selection,Err_Def +ISelLowering,isEligibleForTailCallOptimization,RISCV,Selection,Err_Def +ISelLowering,isFPImmLegal,RISCV,Selection,Err_Def +ISelLowering,LowerCall,RISCV,Selection,Err_Def +ISelLowering,lowerEXTRACT_VECTOR_ELT,RISCV,Selection,Err_Def +ISelLowering,LowerFormalArguments,RISCV,Selection,Err_Def +ISelLowering,lowerINSERT_VECTOR_ELT,RISCV,Selection,Err_Def +ISelLowering,LowerINTRINSIC_W_CHAIN,RISCV,Selection,Err_Def +ISelLowering,LowerINTRINSIC_WO_CHAIN,RISCV,Selection,Err_Def +ISelLowering,LowerOperation,RISCV,Selection,Err_Def +ISelLowering,LowerReturn,RISCV,Selection,Err_Def +ISelLowering,lowerShiftLeftParts,RISCV,Selection,Err_Def +ISelLowering,lowerShiftRightParts,RISCV,Selection,Err_Def +ISelLowering,lowerSPLATVECTOR,RISCV,Selection,Err_Def +ISelLowering,lowerVectorMaskExt,RISCV,Selection,Err_Def +ISelLowering,lowerVectorMaskTrunc,RISCV,Selection,Err_Def +ISelLowering,PerformDAGCombine,RISCV,Selection,Err_Def +ISelLowering,ReplaceNodeResults,RISCV,Selection,Err_Def +ISelLowering,shouldExtendTypeInLibCall,RISCV,Selection,Err_Def +ISelLowering,TargetLowering,RISCV,Selection,Err_Def +ISelLowering,targetShrinkDemandedConstant,RISCV,Selection,Err_Def +ISelLowering,validateCCReservedRegs,RISCV,Selection,Err_Def +MCInstLower,lowerMachineInstrToMCInst,RISCV,Selection,Err_Def +RegisterInfo,eliminateCallFramePseudoInstr,XCore,Allocation,Err_Def +RegisterInfo,eliminateFrameIndex,XCore,Allocation,Err_Def +RegisterInfo,getCalleeSavedRegs,XCore,Allocation,Err_Def +AsmPrinter,AsmPrinter,XCore,Assembler,Err_Def +AsmPrinter,EmitBasicBlockStart,XCore,Assembler,Err_Def +AsmPrinter,EmitConstantPool,XCore,Assembler,Err_Def +AsmPrinter,EmitEndOfAsmFile,XCore,Assembler,Err_Def +AsmPrinter,EmitFunctionEntryLabel,XCore,Assembler,Err_Def +AsmPrinter,EmitGlobalVariable,XCore,Assembler,Err_Def +AsmPrinter,EmitInstruction,XCore,Assembler,Err_Def +AsmPrinter,EmitStartOfAsmFile,XCore,Assembler,Err_Def +AsmPrinter,printInlineJT,XCore,Assembler,Err_Def +AsmPrinter,printInlineJT32,XCore,Assembler,Err_Def +AsmPrinter,PrintSpecial,XCore,Assembler,Err_Def +AsmPrinter,runOnMachineFunction,XCore,Assembler,Err_Def +FrameToArgsOffsetElim,runOnMachineFunction,XCore,Optimization,Err_Def +LoopMetadataLowering,runOnFunction,XCore,Optimization,Err_Def +SimpleBranchOpt,runOnMachineFunction,XCore,Optimization,Err_Def +StackAnalysisPrepare,runOnFunction,XCore,Optimization,Err_Def +StackUsage,runOnMachineFunction,XCore,Optimization,Err_Def +InstrInfo,analyzeBranch,XCore,Scheduling,Err_Def +InstrInfo,copyPhysReg,XCore,Scheduling,Err_Def +InstrInfo,GetInstSizeInBytes,XCore,Scheduling,Err_Def +InstrInfo,insertBranch,XCore,Scheduling,Err_Def +MachineFunctionInfo,~FunctionInfo,XCore,Scheduling,Err_Def +MachineFunctionInfo,Call,XCore,Scheduling,Err_Def +MachineFunctionInfo,ExternalSymbolCall,XCore,Scheduling,Err_Def +MachineFunctionInfo,FunctionCall,XCore,Scheduling,Err_Def +MachineFunctionInfo,FunctionInfo,XCore,Scheduling,Err_Def +MachineFunctionInfo,FunctionInfo2,XCore,Scheduling,Err_Def +TargetObjectFile,getExplicitSectionGlobal,XCore,Scheduling,Err_Def +TargetObjectFile,getSectionForConstant,XCore,Scheduling,Err_Def +TargetObjectFile,Initialize,XCore,Scheduling,Err_Def +TargetObjectFile,SelectSectionForGlobal,XCore,Scheduling,Err_Def +FrameLowering,emitEpilogue,XCore,Selection,Err_Def +FrameLowering,emitPrologue,XCore,Selection,Err_Def +FrameLowering,processFunctionBeforeCalleeSavedScan,XCore,Selection,Err_Def +FrameLowering,restoreCalleeSavedRegisters,XCore,Selection,Err_Def +FrameLowering,spillCalleeSavedRegisters,XCore,Selection,Err_Def +ISelDAGToDAG,immBitp,XCore,Selection,Err_Def +ISelDAGToDAG,immMskBitp,XCore,Selection,Err_Def +ISelDAGToDAG,Select,XCore,Selection,Err_Def +ISelDAGToDAG,SelectInlineAsmMemoryOperand,XCore,Selection,Err_Def +ISelLowering,computeMaskedBitsForTargetNode,XCore,Selection,Err_Def +ISelLowering,ExpandADDSUB,XCore,Selection,Err_Def +ISelLowering,isLegalAddImmediate,XCore,Selection,Err_Def +ISelLowering,isLegalAddressingMode,XCore,Selection,Err_Def +ISelLowering,LowerBR_JT,XCore,Selection,Err_Def +ISelLowering,LowerCall,XCore,Selection,Err_Def +ISelLowering,LowerDYNAMIC_STACKALLOC,XCore,Selection,Err_Def +ISelLowering,LowerEH_RETURN,XCore,Selection,Err_Def +ISelLowering,LowerFormalArguments,XCore,Selection,Err_Def +ISelLowering,LowerFRAME_TO_ARGS_OFFSET,XCore,Selection,Err_Def +ISelLowering,LowerFRAMEADDR,XCore,Selection,Err_Def +ISelLowering,LowerGlobalAddress,XCore,Selection,Err_Def +ISelLowering,LowerGlobalTLSAddress,XCore,Selection,Err_Def +ISelLowering,LowerINIT_TRAMPOLINE,XCore,Selection,Err_Def +ISelLowering,LowerINTRINSIC_WO_CHAIN,XCore,Selection,Err_Def +ISelLowering,LowerLOAD,XCore,Selection,Err_Def +ISelLowering,LowerOperation,XCore,Selection,Err_Def +ISelLowering,LowerReturn,XCore,Selection,Err_Def +ISelLowering,LowerRETURNADDR,XCore,Selection,Err_Def +ISelLowering,LowerSMUL_LOHI,XCore,Selection,Err_Def +ISelLowering,LowerSTACKSAVE,XCore,Selection,Err_Def +ISelLowering,LowerSTORE,XCore,Selection,Err_Def +ISelLowering,LowerUMUL_LOHI,XCore,Selection,Err_Def +ISelLowering,PerformDAGCombine,XCore,Selection,Err_Def +ISelLowering,ReplaceNodeResults,XCore,Selection,Err_Def +ISelLowering,TargetLowering,XCore,Selection,Err_Def +SelectionDAGInfo,EmitTargetCodeForMemcpy,XCore,Selection,Err_Def diff --git a/Scripts/Exp/Correction/Correction_Time.xlsx b/Scripts/Exp/Correction/Correction_Time.xlsx new file mode 100644 index 0000000000000000000000000000000000000000..f2817f3b9061217fc31d4dc21c4a2ae7dda57ddc Binary files /dev/null and b/Scripts/Exp/Correction/Correction_Time.xlsx differ diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Allocation/RegisterBankInfo/RegisterBankInfo.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Allocation/RegisterBankInfo/RegisterBankInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..154620e398d7f0953efcca93ed80eb3382eec4d0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Allocation/RegisterBankInfo/RegisterBankInfo.cpp @@ -0,0 +1,2 @@ +MipsRegisterBankInfo::MipsRegisterBankInfo(const TargetRegisterInfo &TRI) : MipsGenRegisterBankInfo() { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Allocation/RegisterInfo/RegisterInfo.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Allocation/RegisterInfo/RegisterInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9e6f816b7f0ea865a533d9408fcc407f4cc146f4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Allocation/RegisterInfo/RegisterInfo.cpp @@ -0,0 +1,2 @@ +MipsRegisterInfo::MipsRegisterInfo() : MipsGenRegisterInfo(Mips::RA) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Allocation/RegisterInfo/eliminateFrameIndex.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Allocation/RegisterInfo/eliminateFrameIndex.cpp new file mode 100644 index 0000000000000000000000000000000000000000..80dcd82832876ef68c5dac162843caf8d669a919 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Allocation/RegisterInfo/eliminateFrameIndex.cpp @@ -0,0 +1,10 @@ +void MipsRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const { + MachineInstr &MI = *II; + MachineFunction &MF = *MI.getParent()->getParent(); + LLVM_DEBUG(errs() << "\nFunction : " << MF.getName() << "\n"; errs() << "<--------->\n" << MI); + int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); + uint64_t stackSize = MF.getFrameInfo().getStackSize(); + int64_t spOffset = MF.getFrameInfo().getObjectOffset(FrameIndex); + LLVM_DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n" << "spOffset : " << spOffset << "\n" << "stackSize : " << stackSize << "\n" << "alignment : " << DebugStr(MF.getFrameInfo().getObjectAlign(FrameIndex)) << "\n"); + eliminateFI(MI, FIOperandNum, FrameIndex, stackSize, spOffset); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Allocation/RegisterInfo/getCallPreservedMask.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Allocation/RegisterInfo/getCallPreservedMask.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c237e572ddf1fb74501680c681b1277c0f939faa --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Allocation/RegisterInfo/getCallPreservedMask.cpp @@ -0,0 +1,14 @@ +const uint32_t *MipsRegisterInfo::getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const { + const MipsSubtarget &Subtarget = MF.getSubtarget(); + if (Subtarget.isSingleFloat()) + return CSR_SingleFloatOnly_RegMask; + if (Subtarget.isABI_N64()) + return CSR_N64_RegMask; + if (Subtarget.isABI_N32()) + return CSR_N32_RegMask; + if (Subtarget.isFP64bit()) + return CSR_O32_FP64_RegMask; + if (Subtarget.isFPXX()) + return CSR_O32_FPXX_RegMask; + return CSR_O32_RegMask; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Allocation/RegisterInfo/getCalleeSavedRegs.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Allocation/RegisterInfo/getCalleeSavedRegs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ee86b1ec364747b2b7adec2f4c7503435563ae61 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Allocation/RegisterInfo/getCalleeSavedRegs.cpp @@ -0,0 +1,21 @@ +const MCPhysReg *MipsRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { + const MipsSubtarget &Subtarget = MF->getSubtarget(); + const Function &F = MF->getFunction(); + if (F.hasFnAttribute("interrupt")) { + if (Subtarget.hasMips64()) + return Subtarget.hasMips64r6() ? CSR_Interrupt_64R6_SaveList : CSR_Interrupt_64_SaveList; + else + return Subtarget.hasMips32r6() ? CSR_Interrupt_32R6_SaveList : CSR_Interrupt_32_SaveList; + } + if (Subtarget.isSingleFloat()) + return CSR_SingleFloatOnly_SaveList; + if (Subtarget.isABI_N64()) + return CSR_N64_SaveList; + if (Subtarget.isABI_N32()) + return CSR_N32_SaveList; + if (Subtarget.isFP64bit()) + return CSR_O32_FP64_SaveList; + if (Subtarget.isFPXX()) + return CSR_O32_FPXX_SaveList; + return CSR_O32_SaveList; +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Allocation/RegisterInfo/getFrameRegister.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Allocation/RegisterInfo/getFrameRegister.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b5f8f103812c92122b87cb59e13c69048c13c8d7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Allocation/RegisterInfo/getFrameRegister.cpp @@ -0,0 +1,9 @@ +Register MipsRegisterInfo::getFrameRegister(const MachineFunction &MF) const { + const MipsSubtarget &Subtarget = MF.getSubtarget(); + const TargetFrameLowering *TFI = Subtarget.getFrameLowering(); + bool IsN64 = static_cast(MF.getTarget()).getABI().IsN64(); + if (Subtarget.inMips16Mode()) + return TFI->hasFP(MF) ? Mips::S0 : Mips::SP; + else + return TFI->hasFP(MF) ? (IsN64 ? Mips::FP_64 : Mips::FP) : (IsN64 ? Mips::SP_64 : Mips::SP); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Allocation/RegisterInfo/getNoPreservedMask.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Allocation/RegisterInfo/getNoPreservedMask.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Allocation/RegisterInfo/getNoPreservedMask.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Allocation/RegisterInfo/getPointerRegClass.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Allocation/RegisterInfo/getPointerRegClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..768c66e1a51386be2f8f561bf3a64986f6b8ec80 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Allocation/RegisterInfo/getPointerRegClass.cpp @@ -0,0 +1,15 @@ +const TargetRegisterClass *MipsRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind) const { + MipsABIInfo ABI = MF.getSubtarget().getABI(); + MipsPtrClass PtrClassKind = static_cast(Kind); + switch (PtrClassKind) { + case MipsPtrClass::Default: + return ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; + case MipsPtrClass::GPR16MM: + return &Mips::GPRMM16RegClass; + case MipsPtrClass::StackPointer: + return ABI.ArePtrs64bit() ? &Mips::SP64RegClass : &Mips::SP32RegClass; + case MipsPtrClass::GlobalPointer: + return ABI.ArePtrs64bit() ? &Mips::GP64RegClass : &Mips::GP32RegClass; + } + llvm_unreachable("Unknown pointer kind"); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Allocation/RegisterInfo/getReservedRegs.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Allocation/RegisterInfo/getReservedRegs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e54fad41cb6792bb287045716ad70601b8ede981 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Allocation/RegisterInfo/getReservedRegs.cpp @@ -0,0 +1,65 @@ +BitVector MipsRegisterInfo::getReservedRegs(const MachineFunction &MF) const { + static const MCPhysReg ReservedGPR32[] = { + Mips::ZERO, Mips::K0, Mips::K1, Mips::SP + }; + static const MCPhysReg ReservedGPR64[] = { + Mips::ZERO_64, Mips::K0_64, Mips::K1_64, Mips::SP_64 + }; + BitVector Reserved(getNumRegs()); + const MipsSubtarget &Subtarget = MF.getSubtarget(); + for (unsigned I = 0; I < array_lengthof(ReservedGPR32); ++I) + Reserved.set(ReservedGPR32[I]); + if (Subtarget.isTargetNaCl()) { + Reserved.set(Mips::T6); + Reserved.set(Mips::T7); + Reserved.set(Mips::T8); + } + for (unsigned I = 0; I < array_lengthof(ReservedGPR64); ++I) + Reserved.set(ReservedGPR64[I]); + if (!Subtarget.isABICalls()) { + Reserved.set(Mips::GP); + Reserved.set(Mips::GP_64); + } + if (Subtarget.isFP64bit()) { + for (MCPhysReg Reg : Mips::AFGR64RegClass) + Reserved.set(Reg); + } + else { + for (MCPhysReg Reg : Mips::FGR64RegClass) + Reserved.set(Reg); + } + if (Subtarget.getFrameLowering()->hasFP(MF)) { + if (Subtarget.inMips16Mode()) + Reserved.set(Mips::S0); + else { + Reserved.set(Mips::FP); + Reserved.set(Mips::FP_64); + if (needsStackRealignment(MF) && MF.getFrameInfo().hasVarSizedObjects()) { + Reserved.set(Mips::S7); + Reserved.set(Mips::S7_64); + } + } + } + Reserved.set(Mips::HWR29); + Reserved.set(Mips::DSPPos); + Reserved.set(Mips::DSPSCount); + Reserved.set(Mips::DSPCarry); + Reserved.set(Mips::DSPEFI); + Reserved.set(Mips::DSPOutFlag); + for (MCPhysReg Reg : Mips::MSACtrlRegClass) + Reserved.set(Reg); + if (Subtarget.inMips16Mode()) { + const MipsFunctionInfo *MipsFI = MF.getInfo(); + Reserved.set(Mips::RA); + Reserved.set(Mips::RA_64); + Reserved.set(Mips::T0); + Reserved.set(Mips::T1); + if (MF.getFunction().hasFnAttribute("saveS2") || MipsFI->hasSaveS2()) + Reserved.set(Mips::S2); + } + if (Subtarget.useSmallSection()) { + Reserved.set(Mips::GP); + Reserved.set(Mips::GP_64); + } + return Reserved; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Allocation/RegisterInfo/hasReservedSpillSlot.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Allocation/RegisterInfo/hasReservedSpillSlot.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Allocation/RegisterInfo/hasReservedSpillSlot.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Allocation/RegisterInfo/isAsmClobberable.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Allocation/RegisterInfo/isAsmClobberable.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Allocation/RegisterInfo/isAsmClobberable.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Allocation/RegisterInfo/isConstantPhysReg.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Allocation/RegisterInfo/isConstantPhysReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Allocation/RegisterInfo/isConstantPhysReg.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Allocation/RegisterInfo/requiresFrameIndexScavenging.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Allocation/RegisterInfo/requiresFrameIndexScavenging.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e1497c8af968f9fb8df0d24aa0ec03d295b89d0b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Allocation/RegisterInfo/requiresFrameIndexScavenging.cpp @@ -0,0 +1,3 @@ +bool Mips16RegisterInfo::requiresFrameIndexScavenging(const MachineFunction &MF) const { + return false; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Allocation/RegisterInfo/requiresRegisterScavenging.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Allocation/RegisterInfo/requiresRegisterScavenging.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2682c40f6351c32f0b694fd849308d114c3a623b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Allocation/RegisterInfo/requiresRegisterScavenging.cpp @@ -0,0 +1,3 @@ +bool MipsRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const { + return true; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/AsmParser.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/AsmParser.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0024f46337cf0a1788c8f6d813e7962cf06aec64 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/AsmParser.cpp @@ -0,0 +1,24 @@ +MipsAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser, const MCInstrInfo &MII, const MCTargetOptions &Options) : MCTargetAsmParser(Options, sti, MII), ABI(MipsABIInfo::computeTargetABI(Triple(sti.getTargetTriple()), sti.getCPU(), Options)) { + MCAsmParserExtension::Initialize(parser); + parser.addAliasForDirective(".asciiz", ".asciz"); + parser.addAliasForDirective(".hword", ".2byte"); + parser.addAliasForDirective(".word", ".4byte"); + parser.addAliasForDirective(".dword", ".8byte"); + setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits())); + AssemblerOptions.push_back(std::make_unique(getSTI().getFeatureBits())); + AssemblerOptions.push_back(std::make_unique(getSTI().getFeatureBits())); + getTargetStreamer().updateABIInfo(*this); + if (!isABI_O32() && !useOddSPReg() != 0) + report_fatal_error("-mno-odd-spreg requires the O32 ABI"); + CurrentFn = nullptr; + IsPicEnabled = getContext().getObjectFileInfo()->isPositionIndependent(); + IsCpRestoreSet = false; + CpRestoreOffset = -1; + GPReg = ABI.GetGlobalPtr(); + const Triple &TheTriple = sti.getTargetTriple(); + IsLittleEndian = TheTriple.isLittleEndian(); + if (getSTI().getCPU() == "mips64r6" && inMicroMipsMode()) + report_fatal_error("microMIPS64R6 is not supported", false); + if (!isABI_O32() && inMicroMipsMode()) + report_fatal_error("microMIPS64 is not supported", false); + } \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/KindTy.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/KindTy.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9f4c302b6b8fa3a780b93821daa1a44f0536c32c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/KindTy.cpp @@ -0,0 +1,7 @@ +enum KindTy { + k_Immediate, + k_Memory, + k_RegisterIndex, + k_Token, + k_RegList, +} Kind; \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/LLVMInitializeAsmParser.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/LLVMInitializeAsmParser.cpp new file mode 100644 index 0000000000000000000000000000000000000000..03817d477c15f4208d1f063c8f12a417d900e788 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/LLVMInitializeAsmParser.cpp @@ -0,0 +1,6 @@ +extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMipsAsmParser() { + RegisterMCAsmParser X(getTheMipsTarget()); + RegisterMCAsmParser Y(getTheMipselTarget()); + RegisterMCAsmParser A(getTheMips64Target()); + RegisterMCAsmParser B(getTheMips64elTarget()); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/MatchAndEmitInstruction.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/MatchAndEmitInstruction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d5d91e4524a97a5a07f08a46e5da9ac9048942a4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/MatchAndEmitInstruction.cpp @@ -0,0 +1,142 @@ +bool MipsAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, OperandVector &Operands, MCStreamer &Out, uint64_t &ErrorInfo, bool MatchingInlineAsm) { + MCInst Inst; + unsigned MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm); + switch (MatchResult) { + case Match_Success: + if (processInstruction(Inst, IDLoc, Out, STI)) + return true; + return false; + case Match_MissingFeature: + Error(IDLoc, "instruction requires a CPU feature not currently enabled"); + return true; + case Match_InvalidOperand: { + SMLoc ErrorLoc = IDLoc; + if (ErrorInfo != ~0ULL) { + if (ErrorInfo >= Operands.size()) + return Error(IDLoc, "too few operands for instruction"); + ErrorLoc = Operands[ErrorInfo]->getStartLoc(); + if (ErrorLoc == SMLoc()) + ErrorLoc = IDLoc; + } + return Error(ErrorLoc, "invalid operand for instruction"); + } + case Match_NonZeroOperandForSync: + return Error(IDLoc, "s-type must be zero or unspecified for pre-MIPS32 ISAs"); + case Match_NonZeroOperandForMTCX: + return Error(IDLoc, "selector must be zero for pre-MIPS32 ISAs"); + case Match_MnemonicFail: + return Error(IDLoc, "invalid instruction"); + case Match_RequiresDifferentSrcAndDst: + return Error(IDLoc, "source and destination must be different"); + case Match_RequiresDifferentOperands: + return Error(IDLoc, "registers must be different"); + case Match_RequiresNoZeroRegister: + return Error(IDLoc, "invalid operand ($zero) for instruction"); + case Match_RequiresSameSrcAndDst: + return Error(IDLoc, "source and destination must match"); + case Match_NoFCCRegisterForCurrentISA: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "non-zero fcc register doesn't exist in current ISA level"); + case Match_Immz: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected '0'"); + case Match_UImm1_0: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 1-bit unsigned immediate"); + case Match_UImm2_0: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 2-bit unsigned immediate"); + case Match_UImm2_1: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected immediate in range 1 .. 4"); + case Match_UImm3_0: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 3-bit unsigned immediate"); + case Match_UImm4_0: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 4-bit unsigned immediate"); + case Match_SImm4_0: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 4-bit signed immediate"); + case Match_UImm5_0: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 5-bit unsigned immediate"); + case Match_SImm5_0: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 5-bit signed immediate"); + case Match_UImm5_1: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected immediate in range 1 .. 32"); + case Match_UImm5_32: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected immediate in range 32 .. 63"); + case Match_UImm5_33: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected immediate in range 33 .. 64"); + case Match_UImm5_0_Report_UImm6: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 6-bit unsigned immediate"); + case Match_UImm5_Lsl2: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected both 7-bit unsigned immediate and multiple of 4"); + case Match_UImmRange2_64: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected immediate in range 2 .. 64"); + case Match_UImm6_0: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 6-bit unsigned immediate"); + case Match_UImm6_Lsl2: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected both 8-bit unsigned immediate and multiple of 4"); + case Match_SImm6_0: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 6-bit signed immediate"); + case Match_UImm7_0: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 7-bit unsigned immediate"); + case Match_UImm7_N1: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected immediate in range -1 .. 126"); + case Match_SImm7_Lsl2: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected both 9-bit signed immediate and multiple of 4"); + case Match_UImm8_0: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 8-bit unsigned immediate"); + case Match_UImm10_0: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 10-bit unsigned immediate"); + case Match_SImm10_0: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 10-bit signed immediate"); + case Match_SImm11_0: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 11-bit signed immediate"); + case Match_UImm16: + case Match_UImm16_Relaxed: + case Match_UImm16_AltRelaxed: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 16-bit unsigned immediate"); + case Match_SImm16: + case Match_SImm16_Relaxed: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 16-bit signed immediate"); + case Match_SImm19_Lsl2: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected both 19-bit signed immediate and multiple of 4"); + case Match_UImm20_0: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 20-bit unsigned immediate"); + case Match_UImm26_0: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 26-bit unsigned immediate"); + case Match_SImm32: + case Match_SImm32_Relaxed: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 32-bit signed immediate"); + case Match_UImm32_Coerced: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 32-bit immediate"); + case Match_MemSImm9: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected memory with 9-bit signed offset"); + case Match_MemSImm10: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected memory with 10-bit signed offset"); + case Match_MemSImm10Lsl1: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected memory with 11-bit signed offset and multiple of 2"); + case Match_MemSImm10Lsl2: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected memory with 12-bit signed offset and multiple of 4"); + case Match_MemSImm10Lsl3: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected memory with 13-bit signed offset and multiple of 8"); + case Match_MemSImm11: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected memory with 11-bit signed offset"); + case Match_MemSImm12: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected memory with 12-bit signed offset"); + case Match_MemSImm16: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected memory with 16-bit signed offset"); + case Match_MemSImmPtr: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected memory with 32-bit signed offset"); + case Match_RequiresPosSizeRange0_32: { + SMLoc ErrorStart = Operands[3]->getStartLoc(); + SMLoc ErrorEnd = Operands[4]->getEndLoc(); + return Error(ErrorStart, "size plus position are not in the range 0 .. 32", SMRange(ErrorStart, ErrorEnd)); + } + case Match_RequiresPosSizeUImm6: { + SMLoc ErrorStart = Operands[3]->getStartLoc(); + SMLoc ErrorEnd = Operands[4]->getEndLoc(); + return Error(ErrorStart, "size plus position are not in the range 1 .. 63", SMRange(ErrorStart, ErrorEnd)); + } + case Match_RequiresPosSizeRange33_64: { + SMLoc ErrorStart = Operands[3]->getStartLoc(); + SMLoc ErrorEnd = Operands[4]->getEndLoc(); + return Error(ErrorStart, "size plus position are not in the range 33 .. 64", SMRange(ErrorStart, ErrorEnd)); + } +} + llvm_unreachable("Implement any new match types added!"); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/Operand.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/Operand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3ea6992dcf8df85c16752926355da897ce7de63a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/Operand.cpp @@ -0,0 +1,2 @@ +MipsOperand(KindTy K, MipsAsmParser &Parser) : MCParsedAsmOperand(), Kind(K), AsmParser(Parser) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/Operand2.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/Operand2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3ea6992dcf8df85c16752926355da897ce7de63a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/Operand2.cpp @@ -0,0 +1,2 @@ +MipsOperand(KindTy K, MipsAsmParser &Parser) : MCParsedAsmOperand(), Kind(K), AsmParser(Parser) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/ParseDirective.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/ParseDirective.cpp new file mode 100644 index 0000000000000000000000000000000000000000..759b5538a90a0648a7e34b1e218abc61944b5841 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/ParseDirective.cpp @@ -0,0 +1,243 @@ +bool MipsAsmParser::ParseDirective(AsmToken DirectiveID) { + MCAsmParser &Parser = getParser(); + StringRef IDVal = DirectiveID.getString(); + if (IDVal == ".cpadd") { + parseDirectiveCpAdd(DirectiveID.getLoc()); + return false; + } + if (IDVal == ".cpload") { + parseDirectiveCpLoad(DirectiveID.getLoc()); + return false; + } + if (IDVal == ".cprestore") { + parseDirectiveCpRestore(DirectiveID.getLoc()); + return false; + } + if (IDVal == ".cplocal") { + parseDirectiveCpLocal(DirectiveID.getLoc()); + return false; + } + if (IDVal == ".ent") { + StringRef SymbolName; + if (Parser.parseIdentifier(SymbolName)) { + reportParseError("expected identifier after .ent"); + return false; + } + if (getLexer().isNot(AsmToken::EndOfStatement)) { + if (getLexer().isNot(AsmToken::Comma)) { + reportParseError("unexpected token, expected end of statement"); + return false; + } + Parser.Lex(); + const MCExpr *DummyNumber; + int64_t DummyNumberVal; + if (Parser.parseExpression(DummyNumber)) { + reportParseError("expected number after comma"); + return false; + } + if (!DummyNumber->evaluateAsAbsolute(DummyNumberVal)) { + reportParseError("expected an absolute expression after comma"); + return false; + } + } + if (getLexer().isNot(AsmToken::EndOfStatement)) { + reportParseError("unexpected token, expected end of statement"); + return false; + } + MCSymbol *Sym = getContext().getOrCreateSymbol(SymbolName); + getTargetStreamer().emitDirectiveEnt(*Sym); + CurrentFn = Sym; + IsCpRestoreSet = false; + return false; + } + if (IDVal == ".end") { + StringRef SymbolName; + if (Parser.parseIdentifier(SymbolName)) { + reportParseError("expected identifier after .end"); + return false; + } + if (getLexer().isNot(AsmToken::EndOfStatement)) { + reportParseError("unexpected token, expected end of statement"); + return false; + } + if (CurrentFn == nullptr) { + reportParseError(".end used without .ent"); + return false; + } + if ((SymbolName != CurrentFn->getName())) { + reportParseError(".end symbol does not match .ent symbol"); + return false; + } + getTargetStreamer().emitDirectiveEnd(SymbolName); + CurrentFn = nullptr; + IsCpRestoreSet = false; + return false; + } + if (IDVal == ".frame") { + SmallVector, 1> TmpReg; + OperandMatchResultTy ResTy = parseAnyRegister(TmpReg); + if (ResTy == MatchOperand_NoMatch || ResTy == MatchOperand_ParseFail) { + reportParseError("expected stack register"); + return false; + } + MipsOperand &StackRegOpnd = static_cast(*TmpReg[0]); + if (!StackRegOpnd.isGPRAsmReg()) { + reportParseError(StackRegOpnd.getStartLoc(), "expected general purpose register"); + return false; + } + unsigned StackReg = StackRegOpnd.getGPR32Reg(); + if (Parser.getTok().is(AsmToken::Comma)) + Parser.Lex(); + else { + reportParseError("unexpected token, expected comma"); + return false; + } + const MCExpr *FrameSize; + int64_t FrameSizeVal; + if (Parser.parseExpression(FrameSize)) { + reportParseError("expected frame size value"); + return false; + } + if (!FrameSize->evaluateAsAbsolute(FrameSizeVal)) { + reportParseError("frame size not an absolute expression"); + return false; + } + if (Parser.getTok().is(AsmToken::Comma)) + Parser.Lex(); + else { + reportParseError("unexpected token, expected comma"); + return false; + } + TmpReg.clear(); + ResTy = parseAnyRegister(TmpReg); + if (ResTy == MatchOperand_NoMatch || ResTy == MatchOperand_ParseFail) { + reportParseError("expected return register"); + return false; + } + MipsOperand &ReturnRegOpnd = static_cast(*TmpReg[0]); + if (!ReturnRegOpnd.isGPRAsmReg()) { + reportParseError(ReturnRegOpnd.getStartLoc(), "expected general purpose register"); + return false; + } + if (getLexer().isNot(AsmToken::EndOfStatement)) { + reportParseError("unexpected token, expected end of statement"); + return false; + } + getTargetStreamer().emitFrame(StackReg, FrameSizeVal, ReturnRegOpnd.getGPR32Reg()); + IsCpRestoreSet = false; + return false; + } + if (IDVal == ".set") { + parseDirectiveSet(); + return false; + } + if (IDVal == ".mask" || IDVal == ".fmask") { + const MCExpr *BitMask; + int64_t BitMaskVal; + if (Parser.parseExpression(BitMask)) { + reportParseError("expected bitmask value"); + return false; + } + if (!BitMask->evaluateAsAbsolute(BitMaskVal)) { + reportParseError("bitmask not an absolute expression"); + return false; + } + if (Parser.getTok().is(AsmToken::Comma)) + Parser.Lex(); + else { + reportParseError("unexpected token, expected comma"); + return false; + } + const MCExpr *FrameOffset; + int64_t FrameOffsetVal; + if (Parser.parseExpression(FrameOffset)) { + reportParseError("expected frame offset value"); + return false; + } + if (!FrameOffset->evaluateAsAbsolute(FrameOffsetVal)) { + reportParseError("frame offset not an absolute expression"); + return false; + } + if (getLexer().isNot(AsmToken::EndOfStatement)) { + reportParseError("unexpected token, expected end of statement"); + return false; + } + if (IDVal == ".mask") + getTargetStreamer().emitMask(BitMaskVal, FrameOffsetVal); + else + getTargetStreamer().emitFMask(BitMaskVal, FrameOffsetVal); + return false; + } + if (IDVal == ".nan") + return parseDirectiveNaN(); + + if (IDVal == ".gpword") { + parseDirectiveGpWord(); + return false; + } + if (IDVal == ".gpdword") { + parseDirectiveGpDWord(); + return false; + } + + if (IDVal == ".dtprelword") { + parseDirectiveDtpRelWord(); + return false; + } + if (IDVal == ".dtpreldword") { + parseDirectiveDtpRelDWord(); + return false; + } + if (IDVal == ".tprelword") { + parseDirectiveTpRelWord(); + return false; + } + if (IDVal == ".tpreldword") { + parseDirectiveTpRelDWord(); + return false; + } + if (IDVal == ".option") { + parseDirectiveOption(); + return false; + } + if (IDVal == ".abicalls") { + getTargetStreamer().emitDirectiveAbiCalls(); + if (Parser.getTok().isNot(AsmToken::EndOfStatement)) { + Error(Parser.getTok().getLoc(), "unexpected token, expected end of statement"); + } + return false; + } + if (IDVal == ".cpsetup") { + parseDirectiveCPSetup(); + return false; + } + if (IDVal == ".cpreturn") { + parseDirectiveCPReturn(); + return false; + } + if (IDVal == ".module") { + parseDirectiveModule(); + return false; + } + if (IDVal == ".llvm_internal_mips_reallow_module_directive") { + parseInternalDirectiveReallowModule(); + return false; + } + if (IDVal == ".insn") { + parseInsnDirective(); + return false; + } + if (IDVal == ".rdata") { + parseRSectionDirective(".rodata"); + return false; + } + if (IDVal == ".sbss") { + parseSSectionDirective(IDVal, ELF::SHT_NOBITS); + return false; + } + if (IDVal == ".sdata") { + parseSSectionDirective(IDVal, ELF::SHT_PROGBITS); + return false; + } + return true; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/ParseInstruction.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/ParseInstruction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2a508ccdd7784c61a69914df68dd816e913dd917 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/ParseInstruction.cpp @@ -0,0 +1,38 @@ +bool MipsAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, OperandVector &Operands) { + MCAsmParser &Parser = getParser(); + LLVM_DEBUG(dbgs() << "ParseInstruction\n"); + getTargetStreamer().forbidModuleDirective(); + if (!mnemonicIsValid(Name, 0)) { + FeatureBitset FBS = ComputeAvailableFeatures(getSTI().getFeatureBits()); + std::string Suggestion = MipsMnemonicSpellCheck(Name, FBS); + return Error(NameLoc, "unknown instruction" + Suggestion); + } + Operands.push_back(MipsOperand::CreateToken(Name, NameLoc, *this)); + if (getLexer().isNot(AsmToken::EndOfStatement)) { + if (parseOperand(Operands, Name)) { + SMLoc Loc = getLexer().getLoc(); + return Error(Loc, "unexpected token in argument list"); + } + if (getLexer().is(AsmToken::LBrac) && parseBracketSuffix(Name, Operands)) + return true; + while (getLexer().is(AsmToken::Comma)) { + Parser.Lex(); + if (parseOperand(Operands, Name)) { + SMLoc Loc = getLexer().getLoc(); + return Error(Loc, "unexpected token in argument list"); + } + if (getLexer().is(AsmToken::LBrac)) { + if (parseBracketSuffix(Name, Operands)) + return true; + } + else if (getLexer().is(AsmToken::LParen) && parseParenSuffix(Name, Operands)) + return true; + } + } + if (getLexer().isNot(AsmToken::EndOfStatement)) { + SMLoc Loc = getLexer().getLoc(); + return Error(Loc, "unexpected token in argument list"); + } + Parser.Lex(); + return false; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/ParseRegister.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/ParseRegister.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c1c007833f59929cb9d0324e00d3040998464996 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/ParseRegister.cpp @@ -0,0 +1,3 @@ +bool MipsAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) { + return tryParseRegister(RegNo, StartLoc, EndLoc) != MatchOperand_Success; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/addCSRSystemRegisterOperands.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/addCSRSystemRegisterOperands.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/addCSRSystemRegisterOperands.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/addExpr.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/addExpr.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1d2a064b7a9d4fb757645ce723c9d45a4e21f59f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/addExpr.cpp @@ -0,0 +1,8 @@ +void addExpr(MCInst &Inst, const MCExpr *Expr) const { + if (!Expr) + Inst.addOperand(MCOperand::createImm(0)); + else if (const MCConstantExpr *CE = dyn_cast(Expr)) + Inst.addOperand(MCOperand::createImm(CE->getValue())); + else + Inst.addOperand(MCOperand::createExpr(Expr)); + } \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/addFRMArgOperands.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/addFRMArgOperands.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/addFRMArgOperands.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/addFenceArgOperands.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/addFenceArgOperands.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/addFenceArgOperands.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/addImmOperands.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/addImmOperands.cpp new file mode 100644 index 0000000000000000000000000000000000000000..99f9c831995140cddadc166fd097ee368b5c5f2d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/addImmOperands.cpp @@ -0,0 +1,4 @@ +void addImmOperands(MCInst &Inst, unsigned N) const { + assert(N == 1 && "Invalid number of operands!"); + addExpr(Inst, getImm()); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/addRegOperands.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/addRegOperands.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5b5826e8ee5f4576985c9fdb509c547c63f4ec8b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/addRegOperands.cpp @@ -0,0 +1,3 @@ +void addRegOperands(MCInst &Inst, unsigned N) const { + llvm_unreachable("Use a custom parser instead"); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/addVTypeIOperands.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/addVTypeIOperands.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/addVTypeIOperands.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/classifySymbolRef.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/classifySymbolRef.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/classifySymbolRef.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/convertFPR64ToFPR16.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/convertFPR64ToFPR16.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/convertFPR64ToFPR16.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/convertFPR64ToFPR32.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/convertFPR64ToFPR32.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/convertFPR64ToFPR32.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/createImm.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/createImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3da1052dc575118e5bbe16ca357f8c8a15196bdf --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/createImm.cpp @@ -0,0 +1,7 @@ +static std::unique_ptr createImm(const MCExpr *Val, SMLoc S, SMLoc E, MipsAsmParser &Parser) { + auto Op = std::make_unique(k_Immediate, Parser); + Op->Imm.Val = Val; + Op->StartLoc = S; + Op->EndLoc = E; + return Op; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/createReg.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/createReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e3abcdf12ae77e0a78c900564055206a22187242 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/createReg.cpp @@ -0,0 +1,11 @@ +static std::unique_ptr CreateReg(unsigned Index, StringRef Str, RegKind RegKind, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E, MipsAsmParser &Parser) { + auto Op = std::make_unique(k_RegisterIndex, Parser); + Op->RegIdx.Index = Index; + Op->RegIdx.RegInfo = RegInfo; + Op->RegIdx.Kind = RegKind; + Op->RegIdx.Tok.Data = Str.data(); + Op->RegIdx.Tok.Length = Str.size(); + Op->StartLoc = S; + Op->EndLoc = E; + return Op; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/createSysReg.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/createSysReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/createSysReg.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/createToken.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/createToken.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b32d17dd87c68e6be83414d2394197c68d1245e5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/createToken.cpp @@ -0,0 +1,8 @@ +static std::unique_ptr CreateToken(StringRef Str, SMLoc S, MipsAsmParser &Parser) { + auto Op = std::make_unique(k_Token, Parser); + Op->Tok.Data = Str.data(); + Op->Tok.Length = Str.size(); + Op->StartLoc = S; + Op->EndLoc = S; + return Op; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/createVType.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/createVType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/createVType.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/defaultMaskRegOp.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/defaultMaskRegOp.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/defaultMaskRegOp.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/emitToStreamer.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/emitToStreamer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/emitToStreamer.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/evaluateConstantImm.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/evaluateConstantImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/evaluateConstantImm.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/generateImmOutOfRangeError.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/generateImmOutOfRangeError.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/generateImmOutOfRangeError.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/getEndLoc.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/getEndLoc.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e9075c3fe891637688ed0ec5409f13457d6bbdd7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/getEndLoc.cpp @@ -0,0 +1,3 @@ +SMLoc getEndLoc() const override { + return EndLoc; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/getFeatureBits.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/getFeatureBits.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/getFeatureBits.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/getImm.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/getImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..92325c487a33c523dd5549a7a6d810023646c31d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/getImm.cpp @@ -0,0 +1,4 @@ +const MCExpr *getImm() const { + assert((Kind == k_Immediate) && "Invalid access!"); + return Imm.Val; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/getLoc.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/getLoc.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/getLoc.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/getReg.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/getReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..561fb299f3424c0fccbf96c162cdbc182753d4d9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/getReg.cpp @@ -0,0 +1,6 @@ +unsigned getReg() const override { + if (Kind == k_RegisterIndex && RegIdx.Index == 0 && RegIdx.Kind & RegKind_GPR) + return getGPR32Reg(); + llvm_unreachable("Invalid access!"); + return 0; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/getRoundingMode.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/getRoundingMode.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/getRoundingMode.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/getStartLoc.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/getStartLoc.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e36379a2af7e3a50c3295ec879be99ded34a75f7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/getStartLoc.cpp @@ -0,0 +1,3 @@ +SMLoc getStartLoc() const override { + return StartLoc; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/getSysReg.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/getSysReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/getSysReg.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/getTargetStreamer.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/getTargetStreamer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f0702cf4d0fc4fe32fcfe3d6382149cf4456f1ef --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/getTargetStreamer.cpp @@ -0,0 +1,5 @@ +MipsTargetStreamer &getTargetStreamer() { + assert(getParser().getStreamer().getTargetStreamer() && "do not have a target streamer"); + MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer(); + return static_cast(TS); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/getToken.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/getToken.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e40c78da1e88d4186d87ae697481e4458dc6d09f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/getToken.cpp @@ -0,0 +1,4 @@ +StringRef getToken() const { + assert(Kind == k_Token && "Invalid access!"); + return StringRef(Tok.Data, Tok.Length); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/getVType.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/getVType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/getVType.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isBareSimmNLsb0.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isBareSimmNLsb0.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e4f3881c631162a15ddab6b7d7c34cc1d2b97656 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isBareSimmNLsb0.cpp @@ -0,0 +1,3 @@ +template bool isSImm() const { + return isConstantImm() ? isInt(getConstantImm()) : isImm(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isBareSymbol.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isBareSymbol.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e4f3881c631162a15ddab6b7d7c34cc1d2b97656 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isBareSymbol.cpp @@ -0,0 +1,3 @@ +template bool isSImm() const { + return isConstantImm() ? isInt(getConstantImm()) : isImm(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isCLUIImm.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isCLUIImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e4f3881c631162a15ddab6b7d7c34cc1d2b97656 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isCLUIImm.cpp @@ -0,0 +1,3 @@ +template bool isSImm() const { + return isConstantImm() ? isInt(getConstantImm()) : isImm(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isCSRSystemRegister.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isCSRSystemRegister.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isCSRSystemRegister.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isCallSymbol.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isCallSymbol.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e4f3881c631162a15ddab6b7d7c34cc1d2b97656 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isCallSymbol.cpp @@ -0,0 +1,3 @@ +template bool isSImm() const { + return isConstantImm() ? isInt(getConstantImm()) : isImm(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isFRMArg.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isFRMArg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e4f3881c631162a15ddab6b7d7c34cc1d2b97656 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isFRMArg.cpp @@ -0,0 +1,3 @@ +template bool isSImm() const { + return isConstantImm() ? isInt(getConstantImm()) : isImm(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isFenceArg.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isFenceArg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e4f3881c631162a15ddab6b7d7c34cc1d2b97656 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isFenceArg.cpp @@ -0,0 +1,3 @@ +template bool isSImm() const { + return isConstantImm() ? isInt(getConstantImm()) : isImm(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isGPR.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isGPR.cpp new file mode 100644 index 0000000000000000000000000000000000000000..97325e19a5f38a3dc2992126c618d96f7d7813b7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isGPR.cpp @@ -0,0 +1,3 @@ +bool isGPRAsmReg() const { + return isRegIdx() && RegIdx.Kind & RegKind_GPR && RegIdx.Index <= 31; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isImm.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e028f1acc0adc990eaaa7cd33412bb583aa50693 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isImm.cpp @@ -0,0 +1,3 @@ +bool isImm() const override { + return Kind == k_Immediate; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isImmXLenLI.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isImmXLenLI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isImmXLenLI.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isMem.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isMem.cpp new file mode 100644 index 0000000000000000000000000000000000000000..433c1871fb3ee7ace6d97413913de43c8c9fba2a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isMem.cpp @@ -0,0 +1,3 @@ +bool isMem() const override { + return Kind == k_Memory; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isPseudoJumpSymbol.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isPseudoJumpSymbol.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isPseudoJumpSymbol.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isRV32E.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isRV32E.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isRV32E.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isRV64-2.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isRV64-2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isRV64-2.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isRV64.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isRV64.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isRV64.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isReg.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d367df6e72a1916e56ea13412e32c693d1dd119b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isReg.cpp @@ -0,0 +1,3 @@ +bool isReg() const override { + return isGPRAsmReg() && RegIdx.Index == 0; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isSImm10Lsb0000NonZero.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isSImm10Lsb0000NonZero.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e4f3881c631162a15ddab6b7d7c34cc1d2b97656 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isSImm10Lsb0000NonZero.cpp @@ -0,0 +1,3 @@ +template bool isSImm() const { + return isConstantImm() ? isInt(getConstantImm()) : isImm(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isSImm12.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isSImm12.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e4f3881c631162a15ddab6b7d7c34cc1d2b97656 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isSImm12.cpp @@ -0,0 +1,3 @@ +template bool isSImm() const { + return isConstantImm() ? isInt(getConstantImm()) : isImm(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isSImm12Lsb0.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isSImm12Lsb0.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e4f3881c631162a15ddab6b7d7c34cc1d2b97656 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isSImm12Lsb0.cpp @@ -0,0 +1,3 @@ +template bool isSImm() const { + return isConstantImm() ? isInt(getConstantImm()) : isImm(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isSImm13Lsb0.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isSImm13Lsb0.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e4f3881c631162a15ddab6b7d7c34cc1d2b97656 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isSImm13Lsb0.cpp @@ -0,0 +1,3 @@ +template bool isSImm() const { + return isConstantImm() ? isInt(getConstantImm()) : isImm(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isSImm21Lsb0JAL.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isSImm21Lsb0JAL.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e4f3881c631162a15ddab6b7d7c34cc1d2b97656 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isSImm21Lsb0JAL.cpp @@ -0,0 +1,3 @@ +template bool isSImm() const { + return isConstantImm() ? isInt(getConstantImm()) : isImm(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isSImm5.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isSImm5.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e4f3881c631162a15ddab6b7d7c34cc1d2b97656 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isSImm5.cpp @@ -0,0 +1,3 @@ +template bool isSImm() const { + return isConstantImm() ? isInt(getConstantImm()) : isImm(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isSImm5Plus1.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isSImm5Plus1.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e4f3881c631162a15ddab6b7d7c34cc1d2b97656 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isSImm5Plus1.cpp @@ -0,0 +1,3 @@ +template bool isSImm() const { + return isConstantImm() ? isInt(getConstantImm()) : isImm(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isSImm6.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isSImm6.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e4f3881c631162a15ddab6b7d7c34cc1d2b97656 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isSImm6.cpp @@ -0,0 +1,3 @@ +template bool isSImm() const { + return isConstantImm() ? isInt(getConstantImm()) : isImm(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isSImm6NonZero.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isSImm6NonZero.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e4f3881c631162a15ddab6b7d7c34cc1d2b97656 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isSImm6NonZero.cpp @@ -0,0 +1,3 @@ +template bool isSImm() const { + return isConstantImm() ? isInt(getConstantImm()) : isImm(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isSImm9Lsb0.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isSImm9Lsb0.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e4f3881c631162a15ddab6b7d7c34cc1d2b97656 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isSImm9Lsb0.cpp @@ -0,0 +1,3 @@ +template bool isSImm() const { + return isConstantImm() ? isInt(getConstantImm()) : isImm(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isSystemRegister.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isSystemRegister.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isSystemRegister.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isTPRelAddSymbol.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isTPRelAddSymbol.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isTPRelAddSymbol.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isToken.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isToken.cpp new file mode 100644 index 0000000000000000000000000000000000000000..434a02a9965ade469608f0cf55d543128efbe8ff --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isToken.cpp @@ -0,0 +1,3 @@ +bool isToken() const override { + return Kind == k_Token; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isUImm1.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isUImm1.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4482a7535ca80791bde428caeead9df38241b40b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isUImm1.cpp @@ -0,0 +1,3 @@ +template bool isUImm() const { + return isConstantImm() ? isUInt(getConstantImm()) : isImm(); +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isUImm10Lsb00NonZero.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isUImm10Lsb00NonZero.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f7832961be9a3b8db581ef5ae22be8705c597938 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isUImm10Lsb00NonZero.cpp @@ -0,0 +1,3 @@ +template bool isUImm() const { + return isConstantImm() ? isUInt(getConstantImm()) : isImm(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isUImm12.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isUImm12.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4482a7535ca80791bde428caeead9df38241b40b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isUImm12.cpp @@ -0,0 +1,3 @@ +template bool isUImm() const { + return isConstantImm() ? isUInt(getConstantImm()) : isImm(); +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isUImm12M1.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isUImm12M1.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4482a7535ca80791bde428caeead9df38241b40b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isUImm12M1.cpp @@ -0,0 +1,3 @@ +template bool isUImm() const { + return isConstantImm() ? isUInt(getConstantImm()) : isImm(); +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isUImm13Lsb0.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isUImm13Lsb0.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f7832961be9a3b8db581ef5ae22be8705c597938 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isUImm13Lsb0.cpp @@ -0,0 +1,3 @@ +template bool isUImm() const { + return isConstantImm() ? isUInt(getConstantImm()) : isImm(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isUImm20AUIPC.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isUImm20AUIPC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f7832961be9a3b8db581ef5ae22be8705c597938 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isUImm20AUIPC.cpp @@ -0,0 +1,3 @@ +template bool isUImm() const { + return isConstantImm() ? isUInt(getConstantImm()) : isImm(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isUImm20LUI.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isUImm20LUI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f7832961be9a3b8db581ef5ae22be8705c597938 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isUImm20LUI.cpp @@ -0,0 +1,3 @@ +template bool isUImm() const { + return isConstantImm() ? isUInt(getConstantImm()) : isImm(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isUImm3.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isUImm3.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4482a7535ca80791bde428caeead9df38241b40b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isUImm3.cpp @@ -0,0 +1,3 @@ +template bool isUImm() const { + return isConstantImm() ? isUInt(getConstantImm()) : isImm(); +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isUImm4.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isUImm4.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4482a7535ca80791bde428caeead9df38241b40b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isUImm4.cpp @@ -0,0 +1,3 @@ +template bool isUImm() const { + return isConstantImm() ? isUInt(getConstantImm()) : isImm(); +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isUImm5.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isUImm5.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4482a7535ca80791bde428caeead9df38241b40b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isUImm5.cpp @@ -0,0 +1,3 @@ +template bool isUImm() const { + return isConstantImm() ? isUInt(getConstantImm()) : isImm(); +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isUImm6.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isUImm6.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4482a7535ca80791bde428caeead9df38241b40b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isUImm6.cpp @@ -0,0 +1,3 @@ +template bool isUImm() const { + return isConstantImm() ? isUInt(getConstantImm()) : isImm(); +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isUImm6Lsb0.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isUImm6Lsb0.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f7832961be9a3b8db581ef5ae22be8705c597938 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isUImm6Lsb0.cpp @@ -0,0 +1,3 @@ +template bool isUImm() const { + return isConstantImm() ? isUInt(getConstantImm()) : isImm(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isUImm7Lsb00.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isUImm7Lsb00.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f7832961be9a3b8db581ef5ae22be8705c597938 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isUImm7Lsb00.cpp @@ -0,0 +1,3 @@ +template bool isUImm() const { + return isConstantImm() ? isUInt(getConstantImm()) : isImm(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isUImm8Lsb00.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isUImm8Lsb00.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f7832961be9a3b8db581ef5ae22be8705c597938 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isUImm8Lsb00.cpp @@ -0,0 +1,3 @@ +template bool isUImm() const { + return isConstantImm() ? isUInt(getConstantImm()) : isImm(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isUImm8Lsb000.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isUImm8Lsb000.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f7832961be9a3b8db581ef5ae22be8705c597938 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isUImm8Lsb000.cpp @@ -0,0 +1,3 @@ +template bool isUImm() const { + return isConstantImm() ? isUInt(getConstantImm()) : isImm(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isUImm9Lsb000.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isUImm9Lsb000.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f7832961be9a3b8db581ef5ae22be8705c597938 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isUImm9Lsb000.cpp @@ -0,0 +1,3 @@ +template bool isUImm() const { + return isConstantImm() ? isUInt(getConstantImm()) : isImm(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isUImmLog2XLen.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isUImmLog2XLen.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f7832961be9a3b8db581ef5ae22be8705c597938 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isUImmLog2XLen.cpp @@ -0,0 +1,3 @@ +template bool isUImm() const { + return isConstantImm() ? isUInt(getConstantImm()) : isImm(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isUImmLog2XLenHalf.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isUImmLog2XLenHalf.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f7832961be9a3b8db581ef5ae22be8705c597938 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isUImmLog2XLenHalf.cpp @@ -0,0 +1,3 @@ +template bool isUImm() const { + return isConstantImm() ? isUInt(getConstantImm()) : isImm(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isUImmLog2XLenNonZero.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isUImmLog2XLenNonZero.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f7832961be9a3b8db581ef5ae22be8705c597938 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isUImmLog2XLenNonZero.cpp @@ -0,0 +1,3 @@ +template bool isUImm() const { + return isConstantImm() ? isUInt(getConstantImm()) : isImm(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isV0Reg.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isV0Reg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isV0Reg.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isVType.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isVType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isVType.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isVTypeI.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isVTypeI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/isVTypeI.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/matchRegisterNameHelper.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/matchRegisterNameHelper.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/matchRegisterNameHelper.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/parseAtomicMemOp.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/parseAtomicMemOp.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/parseAtomicMemOp.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/parseBareSymbol.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/parseBareSymbol.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/parseBareSymbol.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/parseCSRSyestemRegister.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/parseCSRSyestemRegister.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/parseCSRSyestemRegister.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/parseCallSymbol.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/parseCallSymbol.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/parseCallSymbol.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/parseImmediate.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/parseImmediate.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/parseImmediate.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/parseJALOffset.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/parseJALOffset.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/parseJALOffset.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/parseMaskReg.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/parseMaskReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/parseMaskReg.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/parseMemOpBaseReg.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/parseMemOpBaseReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/parseMemOpBaseReg.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/parseOperand.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/parseOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fa71ede088179ac896028ca527da6898ad8c02dd --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/parseOperand.cpp @@ -0,0 +1,36 @@ +bool MipsAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) { + MCAsmParser &Parser = getParser(); + LLVM_DEBUG(dbgs() << "parseOperand\n"); + OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic); + if (ResTy == MatchOperand_Success) + return false; + if (ResTy == MatchOperand_ParseFail) + return true; + LLVM_DEBUG(dbgs() << ".. Generic Parser\n"); + switch (getLexer().getKind()) { + case AsmToken::Dollar: { + SMLoc S = Parser.getTok().getLoc(); + if (parseAnyRegister(Operands) != MatchOperand_NoMatch) + return false; + StringRef Identifier; + if (Parser.parseIdentifier(Identifier)) + return true; + SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); + MCSymbol *Sym = getContext().getOrCreateSymbol("$" + Identifier); + const MCExpr *Res = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext()); + Operands.push_back(MipsOperand::CreateImm(Res, S, E, *this)); + return false; + } + default: { + LLVM_DEBUG(dbgs() << ".. generic integer expression\n"); + const MCExpr *Expr; + SMLoc S = Parser.getTok().getLoc(); + if (getParser().parseExpression(Expr)) + return true; + SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); + Operands.push_back(MipsOperand::CreateImm(Expr, S, E, *this)); + return false; + } + } + return true; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/parseOperandWithModifier.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/parseOperandWithModifier.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/parseOperandWithModifier.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/parsePseudoJumpSymbol.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/parsePseudoJumpSymbol.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/parsePseudoJumpSymbol.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/parseRegister2.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/parseRegister2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/parseRegister2.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/parseVTypeI.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/parseVTypeI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/parseVTypeI.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/print.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/print.cpp new file mode 100644 index 0000000000000000000000000000000000000000..84efdd1c18cb87d13ff89482402cbc6dadca4b57 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/print.cpp @@ -0,0 +1,29 @@ +void print(raw_ostream &OS) const override { + switch (Kind) { + case k_Immediate: + OS << "Imm<"; + OS << *Imm.Val; + OS << ">"; + break; + case k_Memory: + OS << "Mem<"; + Mem.Base->print(OS); + OS << ", "; + OS << *Mem.Off; + OS << ">"; + break; + case k_RegisterIndex: + OS << "RegIdx<" << RegIdx.Index << ":" << RegIdx.Kind << ", " + << StringRef(RegIdx.Tok.Data, RegIdx.Tok.Length) << ">"; + break; + case k_Token: + OS << getToken(); + break; + case k_RegList: + OS << "RegList< "; + for (auto Reg : (*RegList.List)) + OS << Reg << " "; + OS << ">"; + break; + } +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/setFeatureBits.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/setFeatureBits.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bd1a8cbc7b97359b66a58cc455ce07f739cf6627 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/setFeatureBits.cpp @@ -0,0 +1,7 @@ +void setFeatureBits(uint64_t Feature, StringRef FeatureString) { + if (!(getSTI().getFeatureBits()[Feature])) { + MCSubtargetInfo &STI = copySTI(); + setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature(FeatureString))); + AssemblerOptions.back()->setFeatures(STI.getFeatureBits()); + } +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/tryParseRegister.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/tryParseRegister.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0b7da7ddacfdef727bd3c1256963779f4610d80b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/tryParseRegister.cpp @@ -0,0 +1,16 @@ +OperandMatchResultTy MipsAsmParser::tryParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) { + SmallVector, 1> Operands; + OperandMatchResultTy ResTy = parseAnyRegister(Operands); + if (ResTy == MatchOperand_Success) { + assert(Operands.size() == 1); + MipsOperand &Operand = static_cast(*Operands.front()); + StartLoc = Operand.getStartLoc(); + EndLoc = Operand.getEndLoc(); + if (Operand.isGPRAsmReg()) { + RegNo = isGP64bit() ? Operand.getGPR64Reg() : Operand.getGPR32Reg(); + } + return (RegNo == (unsigned)-1) ? MatchOperand_NoMatch : MatchOperand_Success; + } + assert(Operands.size() == 0); + return (RegNo == (unsigned)-1) ? MatchOperand_NoMatch : MatchOperand_Success; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/validateTargetOperandClass.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/validateTargetOperandClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/validateTargetOperandClass.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmPrinter/AsmPrinter.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmPrinter/AsmPrinter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..69363c6c07ac6569bb6adaa08ef2328e96b8a16f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmPrinter/AsmPrinter.cpp @@ -0,0 +1,2 @@ +explicit MipsAsmPrinter(TargetMachine &TM, std::unique_ptr Streamer) : AsmPrinter(TM, std::move(Streamer)), MCInstLowering(*this) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmPrinter/EmitToStreamer.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmPrinter/EmitToStreamer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmPrinter/EmitToStreamer.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmPrinter/LLVMInitializeAsmPrinter.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmPrinter/LLVMInitializeAsmPrinter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4d4ab5bf715e86e02b908fb3cab0a9fd1fecee42 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmPrinter/LLVMInitializeAsmPrinter.cpp @@ -0,0 +1,6 @@ +extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMipsAsmPrinter() { + RegisterAsmPrinter X(getTheMipsTarget()); + RegisterAsmPrinter Y(getTheMipselTarget()); + RegisterAsmPrinter A(getTheMips64Target()); + RegisterAsmPrinter B(getTheMips64elTarget()); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmPrinter/PrintAsmMemoryOperand.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmPrinter/PrintAsmMemoryOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..13d636aa596545eb1d4a0b5e90251d6ac7d5200a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmPrinter/PrintAsmMemoryOperand.cpp @@ -0,0 +1,27 @@ +bool MipsAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum, const char *ExtraCode, raw_ostream &O) { + assert(OpNum + 1 < MI->getNumOperands() && "Insufficient operands"); + const MachineOperand &BaseMO = MI->getOperand(OpNum); + const MachineOperand &OffsetMO = MI->getOperand(OpNum + 1); + assert(BaseMO.isReg() && "Unexpected base pointer for inline asm memory operand."); + assert(OffsetMO.isImm() && "Unexpected offset for inline asm memory operand."); + int Offset = OffsetMO.getImm(); + if (ExtraCode) { + switch (ExtraCode[0]) { + case 'D': + Offset += 4; + break; + case 'M': + if (Subtarget->isLittle()) + Offset += 4; + break; + case 'L': + if (!Subtarget->isLittle()) + Offset += 4; + break; + default: + return true; + } + } + O << Offset << "($" << MipsInstPrinter::getRegisterName(BaseMO.getReg()) << ")"; + return false; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmPrinter/PrintAsmOperand.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmPrinter/PrintAsmOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..79f3c9422c159809396fc8b54c7323732a4efe88 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmPrinter/PrintAsmOperand.cpp @@ -0,0 +1,89 @@ +bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, const char *ExtraCode, raw_ostream &O) { + if (ExtraCode && ExtraCode[0]) { + if (ExtraCode[1] != 0) return true; + const MachineOperand &MO = MI->getOperand(OpNum); + switch (ExtraCode[0]) { + default: + return AsmPrinter::PrintAsmOperand(MI, OpNum, ExtraCode, O); + case 'X': + if ((MO.getType()) != MachineOperand::MO_Immediate) + return true; + O << "0x" << Twine::utohexstr(MO.getImm()); + return false; + case 'x': + if ((MO.getType()) != MachineOperand::MO_Immediate) + return true; + O << "0x" << Twine::utohexstr(MO.getImm() & 0xffff); + return false; + case 'd': + if ((MO.getType()) != MachineOperand::MO_Immediate) + return true; + O << MO.getImm(); + return false; + case 'm': + if ((MO.getType()) != MachineOperand::MO_Immediate) + return true; + O << MO.getImm() - 1; + return false; + case 'y': + if ((MO.getType()) != MachineOperand::MO_Immediate) + return true; + if (!isPowerOf2_64(MO.getImm())) + return true; + O << Log2_64(MO.getImm()); + return false; + case 'z': + if (MO.getType() == MachineOperand::MO_Immediate && MO.getImm() == 0) { + O << "$0"; + return false; + } + break; + case 'D': + case 'L': + case 'M': + { + if (OpNum == 0) + return true; + const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1); + if (!FlagsOP.isImm()) + return true; + unsigned Flags = FlagsOP.getImm(); + unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags); + if (NumVals != 2) { + if (Subtarget->isGP64bit() && NumVals == 1 && MO.isReg()) { + Register Reg = MO.getReg(); + O << '$' << MipsInstPrinter::getRegisterName(Reg); + return false; + } + return true; + } + unsigned RegOp = OpNum; + if (!Subtarget->isGP64bit()){ + switch(ExtraCode[0]) { + case 'M': + RegOp = (Subtarget->isLittle()) ? OpNum + 1 : OpNum; + break; + case 'L': + RegOp = (Subtarget->isLittle()) ? OpNum : OpNum + 1; + break; + case 'D': + RegOp = OpNum + 1; + } + if (RegOp >= MI->getNumOperands()) + return true; + const MachineOperand &MO = MI->getOperand(RegOp); + if (!MO.isReg()) + return true; + Register Reg = MO.getReg(); + O << '$' << MipsInstPrinter::getRegisterName(Reg); + return false; + } + break; + } + case 'w': + break; + } + } + printOperand(MI, OpNum, O); + return false; +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmPrinter/emitAttributes.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmPrinter/emitAttributes.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmPrinter/emitAttributes.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmPrinter/emitEndOfAsmFile.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmPrinter/emitEndOfAsmFile.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c7146d50f3a4b68a80abd13882286d1c3d617f2b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmPrinter/emitEndOfAsmFile.cpp @@ -0,0 +1,8 @@ +void MipsAsmPrinter::emitEndOfAsmFile(Module &M) { + for (std::map::const_iterator it = StubsNeeded.begin(); it != StubsNeeded.end(); ++it) { + const char *Symbol = it->first; + const Mips16HardFloatInfo::FuncSignature *Signature = it->second; + EmitFPCallStub(Symbol, Signature); + } + OutStreamer->SwitchSection(OutContext.getObjectFileInfo()->getTextSection()); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmPrinter/emitInstruction.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmPrinter/emitInstruction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..52d759a06f0cc7d92fe9b7e4c9454e2fb460d219 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmPrinter/emitInstruction.cpp @@ -0,0 +1,63 @@ +void MipsAsmPrinter::emitInstruction(const MachineInstr *MI) { + MipsTargetStreamer &TS = getTargetStreamer(); + unsigned Opc = MI->getOpcode(); + TS.forbidModuleDirective(); + if (MI->isDebugValue()) { + SmallString<128> Str; + raw_svector_ostream OS(Str); + PrintDebugValueComment(MI, OS); + return; + } + if (MI->isDebugLabel()) + return; + if (InConstantPool && Opc != Mips::CONSTPOOL_ENTRY) { + OutStreamer->emitDataRegion(MCDR_DataRegionEnd); + InConstantPool = false; + } + if (Opc == Mips::CONSTPOOL_ENTRY) { + unsigned LabelId = (unsigned)MI->getOperand(0).getImm(); + unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex(); + if (!InConstantPool) { + OutStreamer->emitDataRegion(MCDR_DataRegion); + InConstantPool = true; + } + OutStreamer->emitLabel(GetCPISymbol(LabelId)); + const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx]; + if (MCPE.isMachineConstantPoolEntry()) + emitMachineConstantPoolValue(MCPE.Val.MachineCPVal); + else + emitGlobalConstant(MF->getDataLayout(), MCPE.Val.ConstVal); + return; + } + switch (Opc) { + case Mips::PATCHABLE_FUNCTION_ENTER: + LowerPATCHABLE_FUNCTION_ENTER(*MI); + return; + case Mips::PATCHABLE_FUNCTION_EXIT: + LowerPATCHABLE_FUNCTION_EXIT(*MI); + return; + case Mips::PATCHABLE_TAIL_CALL: + LowerPATCHABLE_TAIL_CALL(*MI); + return; + } + if (EmitJalrReloc && (MI->isReturn() || MI->isCall() || MI->isIndirectBranch())) { + emitDirectiveRelocJalr(*MI, OutContext, TM, *OutStreamer, *Subtarget); + } + MachineBasicBlock::const_instr_iterator I = MI->getIterator(); + MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end(); + do { + if (emitPseudoExpansionLowering(*OutStreamer, &*I)) + continue; + if (I->isBundle()) + continue; + if (I->getOpcode() == Mips::PseudoReturn || I->getOpcode() == Mips::PseudoReturn64 || I->getOpcode() == Mips::PseudoIndirectBranch || I->getOpcode() == Mips::PseudoIndirectBranch64 || I->getOpcode() == Mips::TAILCALLREG || I->getOpcode() == Mips::TAILCALLREG64) { + emitPseudoIndirectBranch(*OutStreamer, &*I); + continue; + } + if (I->isPseudo() && !Subtarget->inMips16Mode() && !isLongBranchPseudo(I->getOpcode())) + llvm_unreachable("Pseudo opcode found in emitInstruction()"); + MCInst TmpInst0; + MCInstLowering.Lower(&*I, TmpInst0); + EmitToStreamer(*OutStreamer, TmpInst0); + } while ((++I != E) && I->isInsideBundle()); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmPrinter/emitStartOfAsmFile.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmPrinter/emitStartOfAsmFile.cpp new file mode 100644 index 0000000000000000000000000000000000000000..67253a3102205d65b0ab1e07350da6cc883fc27d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmPrinter/emitStartOfAsmFile.cpp @@ -0,0 +1,8 @@ +void MipsAsmPrinter::emitInlineAsmStart() const { + MipsTargetStreamer &TS = getTargetStreamer(); + TS.emitDirectiveSetPush(); + TS.emitDirectiveSetAt(); + TS.emitDirectiveSetMacro(); + TS.emitDirectiveSetReorder(); + OutStreamer->AddBlankLine(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmPrinter/getPassName.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmPrinter/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..39ec07ec3d83ebefc05c0f7f720dba157cb08bb7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmPrinter/getPassName.cpp @@ -0,0 +1,3 @@ +StringRef getPassName() const override { + return "Mips Assembly Printer"; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmPrinter/lowerOperand.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmPrinter/lowerOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..217416888da6098c0f3f5d5d508fa79919629b53 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmPrinter/lowerOperand.cpp @@ -0,0 +1,4 @@ +bool MipsAsmPrinter::lowerOperand(const MachineOperand &MO, MCOperand &MCOp) { + MCOp = MCInstLowering.LowerOperand(MO); + return MCOp.isValid(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmPrinter/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmPrinter/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1ea4e69b88d62186a605cf374ec7eb5204d98196 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmPrinter/runOnMachineFunction.cpp @@ -0,0 +1,17 @@ +bool MipsAsmPrinter::runOnMachineFunction(MachineFunction &MF) { + Subtarget = &MF.getSubtarget(); + MipsFI = MF.getInfo(); + if (Subtarget->inMips16Mode()) + for (std::map::const_iterator it = MipsFI->StubsNeeded.begin(); it != MipsFI->StubsNeeded.end(); ++it) { + const char *Symbol = it->first; + const Mips16HardFloatInfo::FuncSignature *Signature = it->second; + if (StubsNeeded.find(Symbol) == StubsNeeded.end()) + StubsNeeded[Symbol] = Signature; + } + MCP = MF.getConstantPool(); + if (Subtarget->isTargetNaCl()) + NaClAlignIndirectJumpTargets(MF); + AsmPrinter::runOnMachineFunction(MF); + emitXRayTable(); + return true; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/DecodeFPR16RegisterClass.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/DecodeFPR16RegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..61b2928a98a3b89735c62a0242d23f47844cecbb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/DecodeFPR16RegisterClass.cpp @@ -0,0 +1,7 @@ +static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { + if (RegNo > 31) + return MCDisassembler::Fail; + unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo); + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/DecodeFPR32CRegisterClass.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/DecodeFPR32CRegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..61b2928a98a3b89735c62a0242d23f47844cecbb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/DecodeFPR32CRegisterClass.cpp @@ -0,0 +1,7 @@ +static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { + if (RegNo > 31) + return MCDisassembler::Fail; + unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo); + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/DecodeFPR32RegisterClass.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/DecodeFPR32RegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..61b2928a98a3b89735c62a0242d23f47844cecbb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/DecodeFPR32RegisterClass.cpp @@ -0,0 +1,7 @@ +static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { + if (RegNo > 31) + return MCDisassembler::Fail; + unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo); + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/DecodeFPR64CRegisterClass.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/DecodeFPR64CRegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..950f52d398b103964a07e02830d6937798200f64 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/DecodeFPR64CRegisterClass.cpp @@ -0,0 +1,7 @@ +static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { + if (RegNo > 31) + return MCDisassembler::Fail; + unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo); + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/DecodeFPR64RegisterClass.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/DecodeFPR64RegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..40fd65a586b4b9459534d9dadd3e4fad80e94d91 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/DecodeFPR64RegisterClass.cpp @@ -0,0 +1,7 @@ +static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { + if (RegNo > 31) + return MCDisassembler::Fail; + unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo); + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/DecodeGPRCRegisterClass.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/DecodeGPRCRegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b8ff7c7c69fefcdedcff7ad87e852bc482b75b52 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/DecodeGPRCRegisterClass.cpp @@ -0,0 +1,7 @@ +static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { + if (RegNo > 7) + return MCDisassembler::Fail; + unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo); + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/DecodeGPRNoX0RegisterClass.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/DecodeGPRNoX0RegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b8ff7c7c69fefcdedcff7ad87e852bc482b75b52 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/DecodeGPRNoX0RegisterClass.cpp @@ -0,0 +1,7 @@ +static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { + if (RegNo > 7) + return MCDisassembler::Fail; + unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo); + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/DecodeGPRNoX0X2RegisterClass.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/DecodeGPRNoX0X2RegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b8ff7c7c69fefcdedcff7ad87e852bc482b75b52 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/DecodeGPRNoX0X2RegisterClass.cpp @@ -0,0 +1,7 @@ +static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { + if (RegNo > 7) + return MCDisassembler::Fail; + unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo); + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/DecodeGPRRegisterClass.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/DecodeGPRRegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fa54d4bfd9313a9f0a99641dacadf1e355216ffb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/DecodeGPRRegisterClass.cpp @@ -0,0 +1,7 @@ +static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { + if (RegNo > 31) + return MCDisassembler::Fail; + unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/DecodePulpV2RegisterClass.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/DecodePulpV2RegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b8ff7c7c69fefcdedcff7ad87e852bc482b75b52 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/DecodePulpV2RegisterClass.cpp @@ -0,0 +1,7 @@ +static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { + if (RegNo > 7) + return MCDisassembler::Fail; + unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo); + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/DecodePulpV4RegisterClass.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/DecodePulpV4RegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b8ff7c7c69fefcdedcff7ad87e852bc482b75b52 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/DecodePulpV4RegisterClass.cpp @@ -0,0 +1,7 @@ +static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { + if (RegNo > 7) + return MCDisassembler::Fail; + unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo); + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/DecodeVRRegisterClass.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/DecodeVRRegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a030e0d8da7f3ccce562c0f64f602a27fac68994 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/DecodeVRRegisterClass.cpp @@ -0,0 +1,6 @@ +template static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder) { + Value &= ((1 << Bits) - 1); + Value *= Scale; + Inst.addOperand(MCOperand::createImm(Value + Offset)); + return MCDisassembler::Success; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/Disassembler.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/Disassembler.cpp new file mode 100644 index 0000000000000000000000000000000000000000..289bc27b55c7aa92cbcaaaafea3aa7bfec1dc351 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/Disassembler.cpp @@ -0,0 +1,2 @@ +MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian) : MCDisassembler(STI, Ctx), IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]), IsBigEndian(IsBigEndian) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/LLVMInitializeDisassembler.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/LLVMInitializeDisassembler.cpp new file mode 100644 index 0000000000000000000000000000000000000000..aac362f8290944c06ffebaf290b8b64edc748283 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/LLVMInitializeDisassembler.cpp @@ -0,0 +1,6 @@ +extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMipsDisassembler() { + TargetRegistry::RegisterMCDisassembler(getTheMipsTarget(), createMipsDisassembler); + TargetRegistry::RegisterMCDisassembler(getTheMipselTarget(), createMipselDisassembler); + TargetRegistry::RegisterMCDisassembler(getTheMips64Target(), createMipsDisassembler); + TargetRegistry::RegisterMCDisassembler(getTheMips64elTarget(), createMipselDisassembler); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/addImplySP.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/addImplySP.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/addImplySP.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/createDisassembler.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/createDisassembler.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c9f23dc4c3675d6d55e1ff1b1517fc2d45acc8ea --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/createDisassembler.cpp @@ -0,0 +1,3 @@ +static MCDisassembler *createMipsDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx) { + return new MipsDisassembler(STI, Ctx, true); +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/decodeCLUIImmOperand.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/decodeCLUIImmOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8dc5ce568523000d9e6a9d150a81ec69f1c4be78 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/decodeCLUIImmOperand.cpp @@ -0,0 +1,7 @@ +static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { + if (RegNo > 31) + return MCDisassembler::Fail; + unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo); + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/decodeFRMArg.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/decodeFRMArg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f4c2cab7aa576d3436889701317d4baac06b9654 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/decodeFRMArg.cpp @@ -0,0 +1,8 @@ +static DecodeStatus DecodeSyncI(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { + int Offset = SignExtend32<16>(Insn & 0xffff); + unsigned Base = fieldFromInstruction(Insn, 21, 5); + Base = getReg(Decoder, Mips::GPR32RegClassID, Base); + Inst.addOperand(MCOperand::createReg(Base)); + Inst.addOperand(MCOperand::createImm(Offset)); + return MCDisassembler::Success; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/decodeRVCInstrRdRs1Rs2.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/decodeRVCInstrRdRs1Rs2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0c23a00c41dc130ecb77e4891a914a978975a57e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/decodeRVCInstrRdRs1Rs2.cpp @@ -0,0 +1,8 @@ +template static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address, const void *Decoder) { + InsnType Rs = fieldFromInstruction(Insn, 21, 5); + InsnType Rt = fieldFromInstruction(Insn, 16, 5); + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); + return MCDisassembler::Success; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/decodeRVCInstrRdRs1UImm.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/decodeRVCInstrRdRs1UImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0c23a00c41dc130ecb77e4891a914a978975a57e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/decodeRVCInstrRdRs1UImm.cpp @@ -0,0 +1,8 @@ +template static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address, const void *Decoder) { + InsnType Rs = fieldFromInstruction(Insn, 21, 5); + InsnType Rt = fieldFromInstruction(Insn, 16, 5); + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); + return MCDisassembler::Success; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/decodeRVCInstrRdRs2.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/decodeRVCInstrRdRs2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0c23a00c41dc130ecb77e4891a914a978975a57e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/decodeRVCInstrRdRs2.cpp @@ -0,0 +1,8 @@ +template static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address, const void *Decoder) { + InsnType Rs = fieldFromInstruction(Insn, 21, 5); + InsnType Rt = fieldFromInstruction(Insn, 16, 5); + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); + return MCDisassembler::Success; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/decodeRVCInstrRdSImm.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/decodeRVCInstrRdSImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0c23a00c41dc130ecb77e4891a914a978975a57e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/decodeRVCInstrRdSImm.cpp @@ -0,0 +1,8 @@ +template static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address, const void *Decoder) { + InsnType Rs = fieldFromInstruction(Insn, 21, 5); + InsnType Rt = fieldFromInstruction(Insn, 16, 5); + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); + return MCDisassembler::Success; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/decodeRVCInstrSImm.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/decodeRVCInstrSImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0c23a00c41dc130ecb77e4891a914a978975a57e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/decodeRVCInstrSImm.cpp @@ -0,0 +1,8 @@ +template static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address, const void *Decoder) { + InsnType Rs = fieldFromInstruction(Insn, 21, 5); + InsnType Rt = fieldFromInstruction(Insn, 16, 5); + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); + return MCDisassembler::Success; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/decodeSImmNonZeroOperand.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/decodeSImmNonZeroOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0282ae9b186c226781e9e8e2f3cc39a828d3ef17 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/decodeSImmNonZeroOperand.cpp @@ -0,0 +1,5 @@ +template static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder) { + int32_t Imm = SignExtend32(Value) * ScaleBy; + Inst.addOperand(MCOperand::createImm(Imm + Offset)); + return MCDisassembler::Success; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/decodeSImmOperand.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/decodeSImmOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0282ae9b186c226781e9e8e2f3cc39a828d3ef17 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/decodeSImmOperand.cpp @@ -0,0 +1,5 @@ +template static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder) { + int32_t Imm = SignExtend32(Value) * ScaleBy; + Inst.addOperand(MCOperand::createImm(Imm + Offset)); + return MCDisassembler::Success; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/decodeSImmOperandAndLsl1.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/decodeSImmOperandAndLsl1.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0282ae9b186c226781e9e8e2f3cc39a828d3ef17 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/decodeSImmOperandAndLsl1.cpp @@ -0,0 +1,5 @@ +template static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder) { + int32_t Imm = SignExtend32(Value) * ScaleBy; + Inst.addOperand(MCOperand::createImm(Imm + Offset)); + return MCDisassembler::Success; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/decodeUImmMinus1Operand.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/decodeUImmMinus1Operand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0c23a00c41dc130ecb77e4891a914a978975a57e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/decodeUImmMinus1Operand.cpp @@ -0,0 +1,8 @@ +template static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address, const void *Decoder) { + InsnType Rs = fieldFromInstruction(Insn, 21, 5); + InsnType Rt = fieldFromInstruction(Insn, 16, 5); + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); + return MCDisassembler::Success; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/decodeUImmNonZeroOperand.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/decodeUImmNonZeroOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a030e0d8da7f3ccce562c0f64f602a27fac68994 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/decodeUImmNonZeroOperand.cpp @@ -0,0 +1,6 @@ +template static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder) { + Value &= ((1 << Bits) - 1); + Value *= Scale; + Inst.addOperand(MCOperand::createImm(Value + Offset)); + return MCDisassembler::Success; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/decodeUImmOperand.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/decodeUImmOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a030e0d8da7f3ccce562c0f64f602a27fac68994 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/decodeUImmOperand.cpp @@ -0,0 +1,6 @@ +template static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder) { + Value &= ((1 << Bits) - 1); + Value *= Scale; + Inst.addOperand(MCOperand::createImm(Value + Offset)); + return MCDisassembler::Success; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/decodeVMaskReg.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/decodeVMaskReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a030e0d8da7f3ccce562c0f64f602a27fac68994 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/decodeVMaskReg.cpp @@ -0,0 +1,6 @@ +template static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder) { + Value &= ((1 << Bits) - 1); + Value *= Scale; + Inst.addOperand(MCOperand::createImm(Value + Offset)); + return MCDisassembler::Success; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/getInstruction.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/getInstruction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..97a894caca0ae1138b9d72b7014c73e34494b18c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Disassembler/Disassembler/getInstruction.cpp @@ -0,0 +1,114 @@ +DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef Bytes, uint64_t Address, raw_ostream &CStream) const { + uint32_t Insn; + DecodeStatus Result; + Size = 0; + if (IsMicroMips) { + Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian); + if (Result == MCDisassembler::Fail) + return MCDisassembler::Fail; + if (hasMips32r6()) { + LLVM_DEBUG(dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n"); + Result = decodeInstruction(DecoderTableMicroMipsR616, Instr, Insn, Address, this, STI); + if (Result != MCDisassembler::Fail) { + Size = 2; + return Result; + } + } + LLVM_DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n"); + Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address, this, STI); + if (Result != MCDisassembler::Fail) { + Size = 2; + return Result; + } + Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true); + if (Result == MCDisassembler::Fail) + return MCDisassembler::Fail; + if (hasMips32r6()) { + LLVM_DEBUG(dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n"); + Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn, Address, this, STI); + if (Result != MCDisassembler::Fail) { + Size = 4; + return Result; + } + } + LLVM_DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n"); + Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address, this, STI); + if (Result != MCDisassembler::Fail) { + Size = 4; + return Result; + } + if (isFP64()) { + LLVM_DEBUG(dbgs() << "Trying MicroMipsFP64 table (32-bit opcodes):\n"); + Result = decodeInstruction(DecoderTableMicroMipsFP6432, Instr, Insn, Address, this, STI); + if (Result != MCDisassembler::Fail) { + Size = 4; + return Result; + } + } + Size = 2; + return MCDisassembler::Fail; + } + Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false); + if (Result == MCDisassembler::Fail) + return MCDisassembler::Fail; + Size = 4; + if (hasCOP3()) { + LLVM_DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n"); + Result = decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI); + if (Result != MCDisassembler::Fail) + return Result; + } + if (hasMips32r6() && isGP64()) { + LLVM_DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n"); + Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn, Address, this, STI); + if (Result != MCDisassembler::Fail) + return Result; + } + if (hasMips32r6() && isPTR64()) { + LLVM_DEBUG(dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n"); + Result = decodeInstruction(DecoderTableMips32r6_64r6_PTR6432, Instr, Insn, Address, this, STI); + if (Result != MCDisassembler::Fail) + return Result; + } + if (hasMips32r6()) { + LLVM_DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n"); + Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn, Address, this, STI); + if (Result != MCDisassembler::Fail) + return Result; + } + if (hasMips2() && isPTR64()) { + LLVM_DEBUG(dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n"); + Result = decodeInstruction(DecoderTableMips32_64_PTR6432, Instr, Insn, Address, this, STI); + if (Result != MCDisassembler::Fail) + return Result; + } + if (hasCnMips()) { + LLVM_DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n"); + Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn, Address, this, STI); + if (Result != MCDisassembler::Fail) + return Result; + } + if (hasCnMipsP()) { + LLVM_DEBUG(dbgs() << "Trying CnMipsP table (32-bit opcodes):\n"); + Result = decodeInstruction(DecoderTableCnMipsP32, Instr, Insn, Address, this, STI); + if (Result != MCDisassembler::Fail) + return Result; + } + if (isGP64()) { + LLVM_DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n"); + Result = decodeInstruction(DecoderTableMips6432, Instr, Insn, Address, this, STI); + if (Result != MCDisassembler::Fail) + return Result; + } + if (isFP64()) { + LLVM_DEBUG(dbgs() << "Trying MipsFP64 (64 bit FPU) table (32-bit opcodes):\n"); + Result = decodeInstruction(DecoderTableMipsFP6432, Instr, Insn, Address, this, STI); + if (Result != MCDisassembler::Fail) + return Result; + } + LLVM_DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n"); + Result = decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI); + if (Result != MCDisassembler::Fail) + return Result; + return MCDisassembler::Fail; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/AsmBackend.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/AsmBackend.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7ae0321d2626e19fa5446eb52df8fbb49738d2df --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/AsmBackend.cpp @@ -0,0 +1,2 @@ +MipsAsmBackend(const Target &T, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU, bool N32) : MCAsmBackend(TT.isLittleEndian() ? support::little : support::big), TheTriple(TT), IsN32(N32) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/adjustFixupValue.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/adjustFixupValue.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e955e760b17b32c034de715643494327c2cb575e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/adjustFixupValue.cpp @@ -0,0 +1,144 @@ +static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value, MCContext &Ctx) { + unsigned Kind = Fixup.getKind(); + switch (Kind) { + default: + return 0; + case FK_Data_2: + case Mips::fixup_Mips_LO16: + case Mips::fixup_Mips_GPREL16: + case Mips::fixup_Mips_GPOFF_HI: + case Mips::fixup_Mips_GPOFF_LO: + case Mips::fixup_Mips_GOT_PAGE: + case Mips::fixup_Mips_GOT_OFST: + case Mips::fixup_Mips_GOT_DISP: + case Mips::fixup_Mips_GOT_LO16: + case Mips::fixup_Mips_CALL_LO16: + case Mips::fixup_MICROMIPS_GPOFF_HI: + case Mips::fixup_MICROMIPS_GPOFF_LO: + case Mips::fixup_MICROMIPS_LO16: + case Mips::fixup_MICROMIPS_GOT_PAGE: + case Mips::fixup_MICROMIPS_GOT_OFST: + case Mips::fixup_MICROMIPS_GOT_DISP: + case Mips::fixup_MIPS_PCLO16: + Value &= 0xffff; + break; + case FK_DTPRel_4: + case FK_DTPRel_8: + case FK_TPRel_4: + case FK_TPRel_8: + case FK_GPRel_4: + case FK_Data_4: + case FK_Data_8: + case Mips::fixup_Mips_SUB: + case Mips::fixup_MICROMIPS_SUB: + break; + case Mips::fixup_Mips_PC16: + Value = (int64_t)Value / 4; + if (!isInt<16>(Value)) { + Ctx.reportError(Fixup.getLoc(), "out of range PC16 fixup"); + return 0; + } + break; + case Mips::fixup_MIPS_PC19_S2: + case Mips::fixup_MICROMIPS_PC19_S2: + Value = (int64_t)Value / 4; + if (!isInt<19>(Value)) { + Ctx.reportError(Fixup.getLoc(), "out of range PC19 fixup"); + return 0; + } + break; + case Mips::fixup_Mips_26: + Value >>= 2; + break; + case Mips::fixup_Mips_HI16: + case Mips::fixup_Mips_GOT: + case Mips::fixup_MICROMIPS_GOT16: + case Mips::fixup_Mips_GOT_HI16: + case Mips::fixup_Mips_CALL_HI16: + case Mips::fixup_MICROMIPS_HI16: + case Mips::fixup_MIPS_PCHI16: + Value = ((Value + 0x8000) >> 16) & 0xffff; + break; + case Mips::fixup_Mips_HIGHER: + case Mips::fixup_MICROMIPS_HIGHER: + Value = ((Value + 0x80008000LL) >> 32) & 0xffff; + break; + case Mips::fixup_Mips_HIGHEST: + case Mips::fixup_MICROMIPS_HIGHEST: + Value = ((Value + 0x800080008000LL) >> 48) & 0xffff; + break; + case Mips::fixup_MICROMIPS_26_S1: + Value >>= 1; + break; + case Mips::fixup_MICROMIPS_PC7_S1: + Value -= 4; + Value = (int64_t) Value / 2; + if (!isInt<7>(Value)) { + Ctx.reportError(Fixup.getLoc(), "out of range PC7 fixup"); + return 0; + } + break; + case Mips::fixup_MICROMIPS_PC10_S1: + Value -= 2; + Value = (int64_t) Value / 2; + if (!isInt<10>(Value)) { + Ctx.reportError(Fixup.getLoc(), "out of range PC10 fixup"); + return 0; + } + break; + case Mips::fixup_MICROMIPS_PC16_S1: + Value -= 4; + Value = (int64_t)Value / 2; + if (!isInt<16>(Value)) { + Ctx.reportError(Fixup.getLoc(), "out of range PC16 fixup"); + return 0; + } + break; + case Mips::fixup_MIPS_PC18_S3: + Value = (int64_t)Value / 8; + if (!isInt<18>(Value)) { + Ctx.reportError(Fixup.getLoc(), "out of range PC18 fixup"); + return 0; + } + break; + case Mips::fixup_MICROMIPS_PC18_S3: + if ((Value & 7)) { + Ctx.reportError(Fixup.getLoc(), "out of range PC18 fixup"); + } + Value = (int64_t)Value / 8; + if (!isInt<18>(Value)) { + Ctx.reportError(Fixup.getLoc(), "out of range PC18 fixup"); + return 0; + } + break; + case Mips::fixup_MIPS_PC21_S2: + Value = (int64_t) Value / 4; + if (!isInt<21>(Value)) { + Ctx.reportError(Fixup.getLoc(), "out of range PC21 fixup"); + return 0; + } + break; + case Mips::fixup_MIPS_PC26_S2: + Value = (int64_t) Value / 4; + if (!isInt<26>(Value)) { + Ctx.reportError(Fixup.getLoc(), "out of range PC26 fixup"); + return 0; + } + break; + case Mips::fixup_MICROMIPS_PC26_S1: + Value = (int64_t)Value / 2; + if (!isInt<26>(Value)) { + Ctx.reportFatalError(Fixup.getLoc(), "out of range PC26 fixup"); + return 0; + } + break; + case Mips::fixup_MICROMIPS_PC21_S1: + Value = (int64_t)Value / 2; + if (!isInt<21>(Value)) { + Ctx.reportError(Fixup.getLoc(), "out of range PC21 fixup"); + return 0; + } + break; + } + return Value; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/applyFixup.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/applyFixup.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d9211dcecd9d0b897b105d23d99f75b18563bee0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/applyFixup.cpp @@ -0,0 +1,37 @@ +void MipsAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, MutableArrayRef Data, uint64_t Value, bool IsResolved, const MCSubtargetInfo *STI) const { + MCFixupKind Kind = Fixup.getKind(); + MCContext &Ctx = Asm.getContext(); + Value = adjustFixupValue(Fixup, Value, Ctx); + if (!Value) + return; + unsigned Offset = Fixup.getOffset(); + unsigned NumBytes = (getFixupKindInfo(Kind).TargetSize + 7) / 8; + unsigned FullSize; + switch ((unsigned)Kind) { + case FK_Data_2: + case Mips::fixup_Mips_16: + case Mips::fixup_MICROMIPS_PC10_S1: + FullSize = 2; + break; + case FK_Data_8: + case Mips::fixup_Mips_64: + FullSize = 8; + break; + case FK_Data_4: + default: + FullSize = 4; + break; + } + uint64_t CurVal = 0; + bool microMipsLEByteOrder = needsMMLEByteOrder((unsigned) Kind); + for (unsigned i = 0; i != NumBytes; ++i) { + unsigned Idx = Endian == support::little ? (microMipsLEByteOrder ? calculateMMLEIndex(i) : i) : (FullSize - 1 - i); + CurVal |= (uint64_t)((uint8_t)Data[Offset + Idx]) << (i*8); + } + uint64_t Mask = ((uint64_t)(-1) >> (64 - getFixupKindInfo(Kind).TargetSize)); + CurVal |= Value & Mask; + for (unsigned i = 0; i != NumBytes; ++i) { + unsigned Idx = Endian == support::little ? (microMipsLEByteOrder ? calculateMMLEIndex(i) : i): (FullSize - 1 - i); + Data[Offset + Idx] = (uint8_t)((CurVal >> (i*8)) & 0xff); + } +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/createAsmBackend.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/createAsmBackend.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ea5dcd4a2c2d8d9b3c9e7a32fdfd9f44242047f1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/createAsmBackend.cpp @@ -0,0 +1,4 @@ +MCAsmBackend *llvm::createMipsAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options) { + MipsABIInfo ABI = MipsABIInfo::computeTargetABI(STI.getTargetTriple(), STI.getCPU(), Options); + return new MipsAsmBackend(T, MRI, STI.getTargetTriple(), STI.getCPU(), ABI.IsN32()); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/createObjectTargetWriter.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/createObjectTargetWriter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..00f1fa1f26067758af5e13abbd8903b7c44a4d89 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/createObjectTargetWriter.cpp @@ -0,0 +1,4 @@ +std::unique_ptr MipsAsmBackend::createObjectTargetWriter() const { + return createMipsELFObjectWriter(TheTriple, IsN32); +} + diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/evaluateTargetFixup.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/evaluateTargetFixup.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/evaluateTargetFixup.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/fixupNeedsRelaxation.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/fixupNeedsRelaxation.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/fixupNeedsRelaxation.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/fixupNeedsRelaxationAdvanced.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/fixupNeedsRelaxationAdvanced.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/fixupNeedsRelaxationAdvanced.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/getFixupKind.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/getFixupKind.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1a92b79f89ec89f4e0b16dfd5b04b822a41bfa98 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/getFixupKind.cpp @@ -0,0 +1,36 @@ +Optional MipsAsmBackend::getFixupKind(StringRef Name) const { + return StringSwitch>(Name) + .Case("R_MIPS_NONE", FK_NONE) + .Case("R_MIPS_32", FK_Data_4) + .Case("R_MIPS_CALL_HI16", (MCFixupKind)Mips::fixup_Mips_CALL_HI16) + .Case("R_MIPS_CALL_LO16", (MCFixupKind)Mips::fixup_Mips_CALL_LO16) + .Case("R_MIPS_CALL16", (MCFixupKind)Mips::fixup_Mips_CALL16) + .Case("R_MIPS_GOT16", (MCFixupKind)Mips::fixup_Mips_GOT) + .Case("R_MIPS_GOT_PAGE", (MCFixupKind)Mips::fixup_Mips_GOT_PAGE) + .Case("R_MIPS_GOT_OFST", (MCFixupKind)Mips::fixup_Mips_GOT_OFST) + .Case("R_MIPS_GOT_DISP", (MCFixupKind)Mips::fixup_Mips_GOT_DISP) + .Case("R_MIPS_GOT_HI16", (MCFixupKind)Mips::fixup_Mips_GOT_HI16) + .Case("R_MIPS_GOT_LO16", (MCFixupKind)Mips::fixup_Mips_GOT_LO16) + .Case("R_MIPS_TLS_GOTTPREL", (MCFixupKind)Mips::fixup_Mips_GOTTPREL) + .Case("R_MIPS_TLS_DTPREL_HI16", (MCFixupKind)Mips::fixup_Mips_DTPREL_HI) + .Case("R_MIPS_TLS_DTPREL_LO16", (MCFixupKind)Mips::fixup_Mips_DTPREL_LO) + .Case("R_MIPS_TLS_GD", (MCFixupKind)Mips::fixup_Mips_TLSGD) + .Case("R_MIPS_TLS_LDM", (MCFixupKind)Mips::fixup_Mips_TLSLDM) + .Case("R_MIPS_TLS_TPREL_HI16", (MCFixupKind)Mips::fixup_Mips_TPREL_HI) + .Case("R_MIPS_TLS_TPREL_LO16", (MCFixupKind)Mips::fixup_Mips_TPREL_LO) + .Case("R_MICROMIPS_CALL16", (MCFixupKind)Mips::fixup_MICROMIPS_CALL16) + .Case("R_MICROMIPS_GOT_DISP", (MCFixupKind)Mips::fixup_MICROMIPS_GOT_DISP) + .Case("R_MICROMIPS_GOT_PAGE", (MCFixupKind)Mips::fixup_MICROMIPS_GOT_PAGE) + .Case("R_MICROMIPS_GOT_OFST", (MCFixupKind)Mips::fixup_MICROMIPS_GOT_OFST) + .Case("R_MICROMIPS_GOT16", (MCFixupKind)Mips::fixup_MICROMIPS_GOT16) + .Case("R_MICROMIPS_TLS_GOTTPREL", (MCFixupKind)Mips::fixup_MICROMIPS_GOTTPREL) + .Case("R_MICROMIPS_TLS_DTPREL_HI16", (MCFixupKind)Mips::fixup_MICROMIPS_TLS_DTPREL_HI16) + .Case("R_MICROMIPS_TLS_DTPREL_LO16", (MCFixupKind)Mips::fixup_MICROMIPS_TLS_DTPREL_LO16) + .Case("R_MICROMIPS_TLS_GD", (MCFixupKind)Mips::fixup_MICROMIPS_TLS_GD) + .Case("R_MICROMIPS_TLS_LDM", (MCFixupKind)Mips::fixup_MICROMIPS_TLS_LDM) + .Case("R_MICROMIPS_TLS_TPREL_HI16", (MCFixupKind)Mips::fixup_MICROMIPS_TLS_TPREL_HI16) + .Case("R_MICROMIPS_TLS_TPREL_LO16", (MCFixupKind)Mips::fixup_MICROMIPS_TLS_TPREL_LO16) + .Case("R_MIPS_JALR", (MCFixupKind)Mips::fixup_Mips_JALR) + .Case("R_MICROMIPS_JALR", (MCFixupKind)Mips::fixup_MICROMIPS_JALR) + .Default(MCAsmBackend::getFixupKind(Name)); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/getFixupKindInfo.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/getFixupKindInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..63f50b02cd845c04f7ac393ce134edd753ac4c6e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/getFixupKindInfo.cpp @@ -0,0 +1,154 @@ +const MCFixupKindInfo &MipsAsmBackend::getFixupKindInfo(MCFixupKind Kind) const { + const static MCFixupKindInfo LittleEndianInfos[] = { + { "fixup_Mips_16", 0, 16, 0 }, + { "fixup_Mips_32", 0, 32, 0 }, + { "fixup_Mips_REL32", 0, 32, 0 }, + { "fixup_Mips_26", 0, 26, 0 }, + { "fixup_Mips_HI16", 0, 16, 0 }, + { "fixup_Mips_LO16", 0, 16, 0 }, + { "fixup_Mips_GPREL16", 0, 16, 0 }, + { "fixup_Mips_LITERAL", 0, 16, 0 }, + { "fixup_Mips_GOT", 0, 16, 0 }, + { "fixup_Mips_PC16", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_Mips_CALL16", 0, 16, 0 }, + { "fixup_Mips_GPREL32", 0, 32, 0 }, + { "fixup_Mips_SHIFT5", 6, 5, 0 }, + { "fixup_Mips_SHIFT6", 6, 5, 0 }, + { "fixup_Mips_64", 0, 64, 0 }, + { "fixup_Mips_TLSGD", 0, 16, 0 }, + { "fixup_Mips_GOTTPREL", 0, 16, 0 }, + { "fixup_Mips_TPREL_HI", 0, 16, 0 }, + { "fixup_Mips_TPREL_LO", 0, 16, 0 }, + { "fixup_Mips_TLSLDM", 0, 16, 0 }, + { "fixup_Mips_DTPREL_HI", 0, 16, 0 }, + { "fixup_Mips_DTPREL_LO", 0, 16, 0 }, + { "fixup_Mips_Branch_PCRel", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_Mips_GPOFF_HI", 0, 16, 0 }, + { "fixup_MICROMIPS_GPOFF_HI",0, 16, 0 }, + { "fixup_Mips_GPOFF_LO", 0, 16, 0 }, + { "fixup_MICROMIPS_GPOFF_LO",0, 16, 0 }, + { "fixup_Mips_GOT_PAGE", 0, 16, 0 }, + { "fixup_Mips_GOT_OFST", 0, 16, 0 }, + { "fixup_Mips_GOT_DISP", 0, 16, 0 }, + { "fixup_Mips_HIGHER", 0, 16, 0 }, + { "fixup_MICROMIPS_HIGHER", 0, 16, 0 }, + { "fixup_Mips_HIGHEST", 0, 16, 0 }, + { "fixup_MICROMIPS_HIGHEST", 0, 16, 0 }, + { "fixup_Mips_GOT_HI16", 0, 16, 0 }, + { "fixup_Mips_GOT_LO16", 0, 16, 0 }, + { "fixup_Mips_CALL_HI16", 0, 16, 0 }, + { "fixup_Mips_CALL_LO16", 0, 16, 0 }, + { "fixup_Mips_PC18_S3", 0, 18, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_MIPS_PC19_S2", 0, 19, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_MIPS_PC21_S2", 0, 21, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_MIPS_PC26_S2", 0, 26, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_MIPS_PCHI16", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_MIPS_PCLO16", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_MICROMIPS_26_S1", 0, 26, 0 }, + { "fixup_MICROMIPS_HI16", 0, 16, 0 }, + { "fixup_MICROMIPS_LO16", 0, 16, 0 }, + { "fixup_MICROMIPS_GOT16", 0, 16, 0 }, + { "fixup_MICROMIPS_PC7_S1", 0, 7, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_MICROMIPS_PC10_S1", 0, 10, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_MICROMIPS_PC16_S1", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_MICROMIPS_PC26_S1", 0, 26, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_MICROMIPS_PC19_S2", 0, 19, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_MICROMIPS_PC18_S3", 0, 18, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_MICROMIPS_PC21_S1", 0, 21, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_MICROMIPS_CALL16", 0, 16, 0 }, + { "fixup_MICROMIPS_GOT_DISP", 0, 16, 0 }, + { "fixup_MICROMIPS_GOT_PAGE", 0, 16, 0 }, + { "fixup_MICROMIPS_GOT_OFST", 0, 16, 0 }, + { "fixup_MICROMIPS_TLS_GD", 0, 16, 0 }, + { "fixup_MICROMIPS_TLS_LDM", 0, 16, 0 }, + { "fixup_MICROMIPS_TLS_DTPREL_HI16", 0, 16, 0 }, + { "fixup_MICROMIPS_TLS_DTPREL_LO16", 0, 16, 0 }, + { "fixup_MICROMIPS_GOTTPREL", 0, 16, 0 }, + { "fixup_MICROMIPS_TLS_TPREL_HI16", 0, 16, 0 }, + { "fixup_MICROMIPS_TLS_TPREL_LO16", 0, 16, 0 }, + { "fixup_Mips_SUB", 0, 64, 0 }, + { "fixup_MICROMIPS_SUB", 0, 64, 0 }, + { "fixup_Mips_JALR", 0, 32, 0 }, + { "fixup_MICROMIPS_JALR", 0, 32, 0 } + }; + static_assert(array_lengthof(LittleEndianInfos) == Mips::NumTargetFixupKinds, "Not all MIPS little endian fixup kinds added!"); + const static MCFixupKindInfo BigEndianInfos[] = { + { "fixup_Mips_16", 16, 16, 0 }, + { "fixup_Mips_32", 0, 32, 0 }, + { "fixup_Mips_REL32", 0, 32, 0 }, + { "fixup_Mips_26", 6, 26, 0 }, + { "fixup_Mips_HI16", 16, 16, 0 }, + { "fixup_Mips_LO16", 16, 16, 0 }, + { "fixup_Mips_GPREL16", 16, 16, 0 }, + { "fixup_Mips_LITERAL", 16, 16, 0 }, + { "fixup_Mips_GOT", 16, 16, 0 }, + { "fixup_Mips_PC16", 16, 16, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_Mips_CALL16", 16, 16, 0 }, + { "fixup_Mips_GPREL32", 0, 32, 0 }, + { "fixup_Mips_SHIFT5", 21, 5, 0 }, + { "fixup_Mips_SHIFT6", 21, 5, 0 }, + { "fixup_Mips_64", 0, 64, 0 }, + { "fixup_Mips_TLSGD", 16, 16, 0 }, + { "fixup_Mips_GOTTPREL", 16, 16, 0 }, + { "fixup_Mips_TPREL_HI", 16, 16, 0 }, + { "fixup_Mips_TPREL_LO", 16, 16, 0 }, + { "fixup_Mips_TLSLDM", 16, 16, 0 }, + { "fixup_Mips_DTPREL_HI", 16, 16, 0 }, + { "fixup_Mips_DTPREL_LO", 16, 16, 0 }, + { "fixup_Mips_Branch_PCRel",16, 16, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_Mips_GPOFF_HI", 16, 16, 0 }, + { "fixup_MICROMIPS_GPOFF_HI", 16, 16, 0 }, + { "fixup_Mips_GPOFF_LO", 16, 16, 0 }, + { "fixup_MICROMIPS_GPOFF_LO", 16, 16, 0 }, + { "fixup_Mips_GOT_PAGE", 16, 16, 0 }, + { "fixup_Mips_GOT_OFST", 16, 16, 0 }, + { "fixup_Mips_GOT_DISP", 16, 16, 0 }, + { "fixup_Mips_HIGHER", 16, 16, 0 }, + { "fixup_MICROMIPS_HIGHER", 16, 16, 0 }, + { "fixup_Mips_HIGHEST", 16, 16, 0 }, + { "fixup_MICROMIPS_HIGHEST",16, 16, 0 }, + { "fixup_Mips_GOT_HI16", 16, 16, 0 }, + { "fixup_Mips_GOT_LO16", 16, 16, 0 }, + { "fixup_Mips_CALL_HI16", 16, 16, 0 }, + { "fixup_Mips_CALL_LO16", 16, 16, 0 }, + { "fixup_Mips_PC18_S3", 14, 18, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_MIPS_PC19_S2", 13, 19, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_MIPS_PC21_S2", 11, 21, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_MIPS_PC26_S2", 6, 26, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_MIPS_PCHI16", 16, 16, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_MIPS_PCLO16", 16, 16, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_MICROMIPS_26_S1", 6, 26, 0 }, + { "fixup_MICROMIPS_HI16", 16, 16, 0 }, + { "fixup_MICROMIPS_LO16", 16, 16, 0 }, + { "fixup_MICROMIPS_GOT16", 16, 16, 0 }, + { "fixup_MICROMIPS_PC7_S1", 9, 7, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_MICROMIPS_PC10_S1", 6, 10, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_MICROMIPS_PC16_S1",16, 16, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_MICROMIPS_PC26_S1", 6, 26, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_MICROMIPS_PC19_S2",13, 19, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_MICROMIPS_PC18_S3",14, 18, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_MICROMIPS_PC21_S1",11, 21, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_MICROMIPS_CALL16", 16, 16, 0 }, + { "fixup_MICROMIPS_GOT_DISP", 16, 16, 0 }, + { "fixup_MICROMIPS_GOT_PAGE", 16, 16, 0 }, + { "fixup_MICROMIPS_GOT_OFST", 16, 16, 0 }, + { "fixup_MICROMIPS_TLS_GD", 16, 16, 0 }, + { "fixup_MICROMIPS_TLS_LDM", 16, 16, 0 }, + { "fixup_MICROMIPS_TLS_DTPREL_HI16", 16, 16, 0 }, + { "fixup_MICROMIPS_TLS_DTPREL_LO16", 16, 16, 0 }, + { "fixup_MICROMIPS_GOTTPREL", 16, 16, 0 }, + { "fixup_MICROMIPS_TLS_TPREL_HI16", 16, 16, 0 }, + { "fixup_MICROMIPS_TLS_TPREL_LO16", 16, 16, 0 }, + { "fixup_Mips_SUB", 0, 64, 0 }, + { "fixup_MICROMIPS_SUB", 0, 64, 0 }, + { "fixup_Mips_JALR", 0, 32, 0 }, + { "fixup_MICROMIPS_JALR", 0, 32, 0 } + }; + static_assert(array_lengthof(BigEndianInfos) == Mips::NumTargetFixupKinds, "Not all MIPS big endian fixup kinds added!"); + if (Kind < FirstTargetFixupKind) + return MCAsmBackend::getFixupKindInfo(Kind); + assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && "Invalid kind!"); + if (Endian == support::little) + return LittleEndianInfos[Kind - FirstTargetFixupKind]; + return BigEndianInfos[Kind - FirstTargetFixupKind]; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/getNumFixupKinds.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/getNumFixupKinds.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/getNumFixupKinds.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/getRelaxedOpcode.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/getRelaxedOpcode.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/getRelaxedOpcode.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/getTargetABI.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/getTargetABI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/getTargetABI.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/getTargetOptions.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/getTargetOptions.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/getTargetOptions.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/mayNeedRelaxation.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/mayNeedRelaxation.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/mayNeedRelaxation.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/relaxInstruction.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/relaxInstruction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/relaxInstruction.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/requiresDiffExpressionRelocations.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/requiresDiffExpressionRelocations.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/requiresDiffExpressionRelocations.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/setForceRelocs.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/setForceRelocs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/setForceRelocs.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/shouldForceRelocation.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/shouldForceRelocation.cpp new file mode 100644 index 0000000000000000000000000000000000000000..707ad9a7adfa30dd4cdbb7e4406787776f6689a8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/shouldForceRelocation.cpp @@ -0,0 +1,38 @@ +bool MipsAsmBackend::shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target) { + const unsigned FixupKind = Fixup.getKind(); + switch (FixupKind) { + default: + return false; + case Mips::fixup_Mips_CALL_HI16: + case Mips::fixup_Mips_CALL_LO16: + case Mips::fixup_Mips_CALL16: + case Mips::fixup_Mips_GOT: + case Mips::fixup_Mips_GOT_PAGE: + case Mips::fixup_Mips_GOT_OFST: + case Mips::fixup_Mips_GOT_DISP: + case Mips::fixup_Mips_GOT_HI16: + case Mips::fixup_Mips_GOT_LO16: + case Mips::fixup_Mips_GOTTPREL: + case Mips::fixup_Mips_DTPREL_HI: + case Mips::fixup_Mips_DTPREL_LO: + case Mips::fixup_Mips_TLSGD: + case Mips::fixup_Mips_TLSLDM: + case Mips::fixup_Mips_TPREL_HI: + case Mips::fixup_Mips_TPREL_LO: + case Mips::fixup_Mips_JALR: + case Mips::fixup_MICROMIPS_CALL16: + case Mips::fixup_MICROMIPS_GOT_DISP: + case Mips::fixup_MICROMIPS_GOT_PAGE: + case Mips::fixup_MICROMIPS_GOT_OFST: + case Mips::fixup_MICROMIPS_GOT16: + case Mips::fixup_MICROMIPS_GOTTPREL: + case Mips::fixup_MICROMIPS_TLS_DTPREL_HI16: + case Mips::fixup_MICROMIPS_TLS_DTPREL_LO16: + case Mips::fixup_MICROMIPS_TLS_GD: + case Mips::fixup_MICROMIPS_TLS_LDM: + case Mips::fixup_MICROMIPS_TLS_TPREL_HI16: + case Mips::fixup_MICROMIPS_TLS_TPREL_LO16: + case Mips::fixup_MICROMIPS_JALR: + return true; + } +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/shouldInsertExtraNopBytesForCodeAlign.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/shouldInsertExtraNopBytesForCodeAlign.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d24252a436720a3ccdecb69c990fff58341ff97c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/shouldInsertExtraNopBytesForCodeAlign.cpp @@ -0,0 +1,2 @@ +None + diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/shouldInsertFixupForCodeAlign.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/shouldInsertFixupForCodeAlign.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/shouldInsertFixupForCodeAlign.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/willForceRelocations.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/willForceRelocations.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/willForceRelocations.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/writeNopData.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/writeNopData.cpp new file mode 100644 index 0000000000000000000000000000000000000000..624acfd8a76919adf6444d864bc4f6716cb589bc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/writeNopData.cpp @@ -0,0 +1,4 @@ +bool MipsAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const { + OS.write_zeros(Count); + return true; +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/~AsmBackend.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/~AsmBackend.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmBackend/~AsmBackend.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmInfo/MCAsmInfo.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmInfo/MCAsmInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3dbf2eaf5993d301dc8ae0720319683c2860d3d1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmInfo/MCAsmInfo.cpp @@ -0,0 +1,28 @@ +MipsMCAsmInfo::MipsMCAsmInfo(const Triple &TheTriple, const MCTargetOptions &Options) { + IsLittleEndian = TheTriple.isLittleEndian(); + MipsABIInfo ABI = MipsABIInfo::computeTargetABI(TheTriple, "", Options); + if (TheTriple.isMIPS64() && !ABI.IsN32()) + CodePointerSize = CalleeSaveStackSlotSize = 8; + if (ABI.IsO32()) + PrivateGlobalPrefix = "$"; + else if (ABI.IsN32() || ABI.IsN64()) + PrivateGlobalPrefix = ".L"; + PrivateLabelPrefix = PrivateGlobalPrefix; + AlignmentIsInBytes = false; + Data16bitsDirective = "\t.2byte\t"; + Data32bitsDirective = "\t.4byte\t"; + Data64bitsDirective = "\t.8byte\t"; + CommentString = "#"; + ZeroDirective = "\t.space\t"; + GPRel32Directive = "\t.gpword\t"; + GPRel64Directive = "\t.gpdword\t"; + DTPRel32Directive = "\t.dtprelword\t"; + DTPRel64Directive = "\t.dtpreldword\t"; + TPRel32Directive = "\t.tprelword\t"; + TPRel64Directive = "\t.tpreldword\t"; + UseAssignmentForEHBegin = true; + SupportsDebugInformation = true; + ExceptionsType = ExceptionHandling::DwarfCFI; + DwarfRegNumForCFI = true; + HasMipsExpressions = true; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmInfo/anchor.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmInfo/anchor.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6f2b70e5a457a170f552b5d40557e5769efd425f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmInfo/anchor.cpp @@ -0,0 +1,2 @@ +void MipsMCAsmInfo::anchor() { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmInfo/getExprForFDESymbol.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmInfo/getExprForFDESymbol.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/AsmInfo/getExprForFDESymbol.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/BaseInfo/ABI.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/BaseInfo/ABI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/BaseInfo/ABI.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/BaseInfo/FenceField.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/BaseInfo/FenceField.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/BaseInfo/FenceField.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/BaseInfo/II.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/BaseInfo/II.cpp new file mode 100644 index 0000000000000000000000000000000000000000..daadf4bba15edd51d62b76f8a5f2922cd3dfb63b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/BaseInfo/II.cpp @@ -0,0 +1,42 @@ +namespace MipsII { + enum TOF { + MO_NO_FLAG, + MO_GOT, + MO_GOT_CALL, + MO_GPREL, + MO_ABS_HI, + MO_ABS_LO, + MO_TLSGD, + MO_TLSLDM, + MO_DTPREL_HI, + MO_DTPREL_LO, + MO_GOTTPREL, + MO_TPREL_HI, + MO_TPREL_LO, + MO_GPOFF_HI, + MO_GPOFF_LO, + MO_GOT_DISP, + MO_GOT_PAGE, + MO_GOT_OFST, + MO_HIGHER, + MO_HIGHEST, + MO_GOT_HI16, + MO_GOT_LO16, + MO_CALL_HI16, + MO_CALL_LO16, + MO_JALR + }; + enum { + Pseudo = 0, + FrmR = 1, + FrmI = 2, + FrmJ = 3, + FrmFR = 4, + FrmFI = 5, + FrmOther = 6, + FormMask = 15, + IsCTI = 1 << 4, + HasForbiddenSlot = 1 << 5, + HasFCCRegOperand = 1 << 6 + }; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/BaseInfo/OperandType.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/BaseInfo/OperandType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..19db91538f2257839ecb2a14d1c12740760ec25d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/BaseInfo/OperandType.cpp @@ -0,0 +1,5 @@ +enum OperandType : unsigned { + OPERAND_FIRST_MIPS_MEM_IMM = MCOI::OPERAND_FIRST_TARGET, + OPERAND_MEM_SIMM9 = OPERAND_FIRST_MIPS_MEM_IMM, + OPERAND_LAST_MIPS_MEM_IMM = OPERAND_MEM_SIMM9 +}; diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/BaseInfo/RISCVVSEW.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/BaseInfo/RISCVVSEW.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/BaseInfo/RISCVVSEW.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/BaseInfo/RVVConstraintType.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/BaseInfo/RVVConstraintType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/BaseInfo/RVVConstraintType.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/BaseInfo/RoundingMode.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/BaseInfo/RoundingMode.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/BaseInfo/RoundingMode.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/BaseInfo/VLMUL.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/BaseInfo/VLMUL.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/BaseInfo/VLMUL.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/BaseInfo/VMTs.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/BaseInfo/VMTs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/BaseInfo/VMTs.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/BaseInfo/computeTargetABI.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/BaseInfo/computeTargetABI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4d6853920e499f673dd13662b1ce142b45fd480d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/BaseInfo/computeTargetABI.cpp @@ -0,0 +1,14 @@ +MipsABIInfo MipsABIInfo::computeTargetABI(const Triple &TT, StringRef CPU, const MCTargetOptions &Options) { + if (Options.getABIName().startswith("o32")) + return MipsABIInfo::O32(); + if (Options.getABIName().startswith("n32")) + return MipsABIInfo::N32(); + if (Options.getABIName().startswith("n64")) + return MipsABIInfo::N64(); + if (TT.getEnvironment() == llvm::Triple::GNUABIN32) + return MipsABIInfo::N32(); + assert(Options.getABIName().empty() && "Unknown ABI option for MIPS"); + if (TT.isMIPS64()) + return MipsABIInfo::N64(); + return MipsABIInfo::O32(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/BaseInfo/getTargetABI.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/BaseInfo/getTargetABI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/BaseInfo/getTargetABI.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/BaseInfo/roundingModeToString.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/BaseInfo/roundingModeToString.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/BaseInfo/roundingModeToString.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/BaseInfo/stringToRoundingMode.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/BaseInfo/stringToRoundingMode.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/BaseInfo/stringToRoundingMode.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/BaseInfo/validate.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/BaseInfo/validate.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/BaseInfo/validate.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFObjectWriter/ELFObjectWriter.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFObjectWriter/ELFObjectWriter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..88f55f07a55f5d6e27aacf8f610dbab4444a2d20 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFObjectWriter/ELFObjectWriter.cpp @@ -0,0 +1,2 @@ +MipsELFObjectWriter::MipsELFObjectWriter(uint8_t OSABI, bool HasRelocationAddend, bool Is64) : MCELFObjectTargetWriter(Is64, OSABI, ELF::EM_MIPS, HasRelocationAddend) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFObjectWriter/createELFObjectWriter.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFObjectWriter/createELFObjectWriter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..86e17ba3612af05cf31412d2f7693b9925ecc958 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFObjectWriter/createELFObjectWriter.cpp @@ -0,0 +1,6 @@ +std::unique_ptrllvm::createMipsELFObjectWriter(const Triple &TT, bool IsN32) { + uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS()); + bool IsN64 = TT.isArch64Bit() && !IsN32; + bool HasRelocationAddend = TT.isArch64Bit(); + return std::make_unique(OSABI, HasRelocationAddend, IsN64); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFObjectWriter/getRelocType.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFObjectWriter/getRelocType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7d8b4ed83f6a2bbf608dac997f973ba4486b27c3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFObjectWriter/getRelocType.cpp @@ -0,0 +1,160 @@ +unsigned MipsELFObjectWriter::getRelocType(MCContext &Ctx, const MCValue &Target, const MCFixup &Fixup, bool IsPCRel) const { + unsigned Kind = Fixup.getTargetKind(); + switch (Kind) { + case FK_NONE: + return ELF::R_MIPS_NONE; + case FK_Data_1: + Ctx.reportError(Fixup.getLoc(), "MIPS does not support one byte relocations"); + return ELF::R_MIPS_NONE; + case Mips::fixup_Mips_16: + case FK_Data_2: + return IsPCRel ? ELF::R_MIPS_PC16 : ELF::R_MIPS_16; + case Mips::fixup_Mips_32: + case FK_Data_4: + return IsPCRel ? ELF::R_MIPS_PC32 : ELF::R_MIPS_32; + case Mips::fixup_Mips_64: + case FK_Data_8: + return IsPCRel ? setRTypes(ELF::R_MIPS_PC32, ELF::R_MIPS_64, ELF::R_MIPS_NONE) : (unsigned)ELF::R_MIPS_64; + } + if (IsPCRel) { + switch (Kind) { + case Mips::fixup_Mips_Branch_PCRel: + case Mips::fixup_Mips_PC16: + return ELF::R_MIPS_PC16; + case Mips::fixup_MICROMIPS_PC7_S1: + return ELF::R_MICROMIPS_PC7_S1; + case Mips::fixup_MICROMIPS_PC10_S1: + return ELF::R_MICROMIPS_PC10_S1; + case Mips::fixup_MICROMIPS_PC16_S1: + return ELF::R_MICROMIPS_PC16_S1; + case Mips::fixup_MICROMIPS_PC26_S1: + return ELF::R_MICROMIPS_PC26_S1; + case Mips::fixup_MICROMIPS_PC19_S2: + return ELF::R_MICROMIPS_PC19_S2; + case Mips::fixup_MICROMIPS_PC18_S3: + return ELF::R_MICROMIPS_PC18_S3; + case Mips::fixup_MICROMIPS_PC21_S1: + return ELF::R_MICROMIPS_PC21_S1; + case Mips::fixup_MIPS_PC19_S2: + return ELF::R_MIPS_PC19_S2; + case Mips::fixup_MIPS_PC18_S3: + return ELF::R_MIPS_PC18_S3; + case Mips::fixup_MIPS_PC21_S2: + return ELF::R_MIPS_PC21_S2; + case Mips::fixup_MIPS_PC26_S2: + return ELF::R_MIPS_PC26_S2; + case Mips::fixup_MIPS_PCHI16: + return ELF::R_MIPS_PCHI16; + case Mips::fixup_MIPS_PCLO16: + return ELF::R_MIPS_PCLO16; + } + llvm_unreachable("invalid PC-relative fixup kind!"); + } + switch (Kind) { + case FK_DTPRel_4: + return ELF::R_MIPS_TLS_DTPREL32; + case FK_DTPRel_8: + return ELF::R_MIPS_TLS_DTPREL64; + case FK_TPRel_4: + return ELF::R_MIPS_TLS_TPREL32; + case FK_TPRel_8: + return ELF::R_MIPS_TLS_TPREL64; + case FK_GPRel_4: + return setRTypes(ELF::R_MIPS_GPREL32, is64Bit() ? ELF::R_MIPS_64 : ELF::R_MIPS_NONE, ELF::R_MIPS_NONE); + case Mips::fixup_Mips_GPREL16: + return ELF::R_MIPS_GPREL16; + case Mips::fixup_Mips_26: + return ELF::R_MIPS_26; + case Mips::fixup_Mips_CALL16: + return ELF::R_MIPS_CALL16; + case Mips::fixup_Mips_GOT: + return ELF::R_MIPS_GOT16; + case Mips::fixup_Mips_HI16: + return ELF::R_MIPS_HI16; + case Mips::fixup_Mips_LO16: + return ELF::R_MIPS_LO16; + case Mips::fixup_Mips_TLSGD: + return ELF::R_MIPS_TLS_GD; + case Mips::fixup_Mips_GOTTPREL: + return ELF::R_MIPS_TLS_GOTTPREL; + case Mips::fixup_Mips_TPREL_HI: + return ELF::R_MIPS_TLS_TPREL_HI16; + case Mips::fixup_Mips_TPREL_LO: + return ELF::R_MIPS_TLS_TPREL_LO16; + case Mips::fixup_Mips_TLSLDM: + return ELF::R_MIPS_TLS_LDM; + case Mips::fixup_Mips_DTPREL_HI: + return ELF::R_MIPS_TLS_DTPREL_HI16; + case Mips::fixup_Mips_DTPREL_LO: + return ELF::R_MIPS_TLS_DTPREL_LO16; + case Mips::fixup_Mips_GOT_PAGE: + return ELF::R_MIPS_GOT_PAGE; + case Mips::fixup_Mips_GOT_OFST: + return ELF::R_MIPS_GOT_OFST; + case Mips::fixup_Mips_GOT_DISP: + return ELF::R_MIPS_GOT_DISP; + case Mips::fixup_Mips_GPOFF_HI: + return setRTypes(ELF::R_MIPS_GPREL16, ELF::R_MIPS_SUB, ELF::R_MIPS_HI16); + case Mips::fixup_MICROMIPS_GPOFF_HI: + return setRTypes(ELF::R_MICROMIPS_GPREL16, ELF::R_MICROMIPS_SUB, ELF::R_MICROMIPS_HI16); + case Mips::fixup_Mips_GPOFF_LO: + return setRTypes(ELF::R_MIPS_GPREL16, ELF::R_MIPS_SUB, ELF::R_MIPS_LO16); + case Mips::fixup_MICROMIPS_GPOFF_LO: + return setRTypes(ELF::R_MICROMIPS_GPREL16, ELF::R_MICROMIPS_SUB, ELF::R_MICROMIPS_LO16); + case Mips::fixup_Mips_HIGHER: + return ELF::R_MIPS_HIGHER; + case Mips::fixup_Mips_HIGHEST: + return ELF::R_MIPS_HIGHEST; + case Mips::fixup_Mips_SUB: + return ELF::R_MIPS_SUB; + case Mips::fixup_Mips_GOT_HI16: + return ELF::R_MIPS_GOT_HI16; + case Mips::fixup_Mips_GOT_LO16: + return ELF::R_MIPS_GOT_LO16; + case Mips::fixup_Mips_CALL_HI16: + return ELF::R_MIPS_CALL_HI16; + case Mips::fixup_Mips_CALL_LO16: + return ELF::R_MIPS_CALL_LO16; + case Mips::fixup_MICROMIPS_26_S1: + return ELF::R_MICROMIPS_26_S1; + case Mips::fixup_MICROMIPS_HI16: + return ELF::R_MICROMIPS_HI16; + case Mips::fixup_MICROMIPS_LO16: + return ELF::R_MICROMIPS_LO16; + case Mips::fixup_MICROMIPS_GOT16: + return ELF::R_MICROMIPS_GOT16; + case Mips::fixup_MICROMIPS_CALL16: + return ELF::R_MICROMIPS_CALL16; + case Mips::fixup_MICROMIPS_GOT_DISP: + return ELF::R_MICROMIPS_GOT_DISP; + case Mips::fixup_MICROMIPS_GOT_PAGE: + return ELF::R_MICROMIPS_GOT_PAGE; + case Mips::fixup_MICROMIPS_GOT_OFST: + return ELF::R_MICROMIPS_GOT_OFST; + case Mips::fixup_MICROMIPS_TLS_GD: + return ELF::R_MICROMIPS_TLS_GD; + case Mips::fixup_MICROMIPS_TLS_LDM: + return ELF::R_MICROMIPS_TLS_LDM; + case Mips::fixup_MICROMIPS_TLS_DTPREL_HI16: + return ELF::R_MICROMIPS_TLS_DTPREL_HI16; + case Mips::fixup_MICROMIPS_TLS_DTPREL_LO16: + return ELF::R_MICROMIPS_TLS_DTPREL_LO16; + case Mips::fixup_MICROMIPS_GOTTPREL: + return ELF::R_MICROMIPS_TLS_GOTTPREL; + case Mips::fixup_MICROMIPS_TLS_TPREL_HI16: + return ELF::R_MICROMIPS_TLS_TPREL_HI16; + case Mips::fixup_MICROMIPS_TLS_TPREL_LO16: + return ELF::R_MICROMIPS_TLS_TPREL_LO16; + case Mips::fixup_MICROMIPS_SUB: + return ELF::R_MICROMIPS_SUB; + case Mips::fixup_MICROMIPS_HIGHER: + return ELF::R_MICROMIPS_HIGHER; + case Mips::fixup_MICROMIPS_HIGHEST: + return ELF::R_MICROMIPS_HIGHEST; + case Mips::fixup_Mips_JALR: + return ELF::R_MIPS_JALR; + case Mips::fixup_MICROMIPS_JALR: + return ELF::R_MICROMIPS_JALR; + } + llvm_unreachable("invalid fixup kind!"); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFObjectWriter/needsRelocateWithSymbol.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFObjectWriter/needsRelocateWithSymbol.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7f531ea4250537c4a6213a42e7766c1c17828d3f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFObjectWriter/needsRelocateWithSymbol.cpp @@ -0,0 +1,130 @@ +bool MipsELFObjectWriter::needsRelocateWithSymbol(const MCSymbol &Sym, unsigned Type) const { + if (!isUInt<8>(Type)) + return needsRelocateWithSymbol(Sym, Type & 0xff) || needsRelocateWithSymbol(Sym, (Type >> 8) & 0xff) || needsRelocateWithSymbol(Sym, (Type >> 16) & 0xff); + switch (Type) { + default: + errs() << Type << "\n"; + llvm_unreachable("Unexpected relocation"); + return true; + case ELF::R_MIPS_NONE: + return false; + case ELF::R_MIPS_GOT16: + case ELF::R_MIPS16_GOT16: + case ELF::R_MICROMIPS_GOT16: + case ELF::R_MIPS_HIGHER: + case ELF::R_MIPS_HIGHEST: + case ELF::R_MIPS_HI16: + case ELF::R_MIPS16_HI16: + case ELF::R_MICROMIPS_HI16: + case ELF::R_MIPS_LO16: + case ELF::R_MIPS16_LO16: + case ELF::R_MICROMIPS_LO16: + if (cast(Sym).getOther() & ELF::STO_MIPS_MICROMIPS) + return true; + return false; + case ELF::R_MIPS_GOT_PAGE: + case ELF::R_MICROMIPS_GOT_PAGE: + case ELF::R_MIPS_GOT_OFST: + case ELF::R_MICROMIPS_GOT_OFST: + case ELF::R_MIPS_16: + case ELF::R_MIPS_32: + case ELF::R_MIPS_GPREL32: + if (cast(Sym).getOther() & ELF::STO_MIPS_MICROMIPS) + return true; + LLVM_FALLTHROUGH; + case ELF::R_MIPS_26: + case ELF::R_MIPS_64: + case ELF::R_MIPS_GPREL16: + case ELF::R_MIPS_PC16: + case ELF::R_MIPS_SUB: + return false; + case ELF::R_MIPS_REL32: + case ELF::R_MIPS_LITERAL: + case ELF::R_MIPS_CALL16: + case ELF::R_MIPS_SHIFT5: + case ELF::R_MIPS_SHIFT6: + case ELF::R_MIPS_GOT_DISP: + case ELF::R_MIPS_GOT_HI16: + case ELF::R_MIPS_GOT_LO16: + case ELF::R_MIPS_INSERT_A: + case ELF::R_MIPS_INSERT_B: + case ELF::R_MIPS_DELETE: + case ELF::R_MIPS_CALL_HI16: + case ELF::R_MIPS_CALL_LO16: + case ELF::R_MIPS_SCN_DISP: + case ELF::R_MIPS_REL16: + case ELF::R_MIPS_ADD_IMMEDIATE: + case ELF::R_MIPS_PJUMP: + case ELF::R_MIPS_RELGOT: + case ELF::R_MIPS_JALR: + case ELF::R_MIPS_TLS_DTPMOD32: + case ELF::R_MIPS_TLS_DTPREL32: + case ELF::R_MIPS_TLS_DTPMOD64: + case ELF::R_MIPS_TLS_DTPREL64: + case ELF::R_MIPS_TLS_GD: + case ELF::R_MIPS_TLS_LDM: + case ELF::R_MIPS_TLS_DTPREL_HI16: + case ELF::R_MIPS_TLS_DTPREL_LO16: + case ELF::R_MIPS_TLS_GOTTPREL: + case ELF::R_MIPS_TLS_TPREL32: + case ELF::R_MIPS_TLS_TPREL64: + case ELF::R_MIPS_TLS_TPREL_HI16: + case ELF::R_MIPS_TLS_TPREL_LO16: + case ELF::R_MIPS_GLOB_DAT: + case ELF::R_MIPS_PC21_S2: + case ELF::R_MIPS_PC26_S2: + case ELF::R_MIPS_PC18_S3: + case ELF::R_MIPS_PC19_S2: + case ELF::R_MIPS_PCHI16: + case ELF::R_MIPS_PCLO16: + case ELF::R_MIPS_COPY: + case ELF::R_MIPS_JUMP_SLOT: + case ELF::R_MIPS_NUM: + case ELF::R_MIPS_PC32: + case ELF::R_MIPS_EH: + case ELF::R_MICROMIPS_26_S1: + case ELF::R_MICROMIPS_GPREL16: + case ELF::R_MICROMIPS_LITERAL: + case ELF::R_MICROMIPS_PC7_S1: + case ELF::R_MICROMIPS_PC10_S1: + case ELF::R_MICROMIPS_PC16_S1: + case ELF::R_MICROMIPS_CALL16: + case ELF::R_MICROMIPS_GOT_DISP: + case ELF::R_MICROMIPS_GOT_HI16: + case ELF::R_MICROMIPS_GOT_LO16: + case ELF::R_MICROMIPS_SUB: + case ELF::R_MICROMIPS_HIGHER: + case ELF::R_MICROMIPS_HIGHEST: + case ELF::R_MICROMIPS_CALL_HI16: + case ELF::R_MICROMIPS_CALL_LO16: + case ELF::R_MICROMIPS_SCN_DISP: + case ELF::R_MICROMIPS_JALR: + case ELF::R_MICROMIPS_HI0_LO16: + case ELF::R_MICROMIPS_TLS_GD: + case ELF::R_MICROMIPS_TLS_LDM: + case ELF::R_MICROMIPS_TLS_DTPREL_HI16: + case ELF::R_MICROMIPS_TLS_DTPREL_LO16: + case ELF::R_MICROMIPS_TLS_GOTTPREL: + case ELF::R_MICROMIPS_TLS_TPREL_HI16: + case ELF::R_MICROMIPS_TLS_TPREL_LO16: + case ELF::R_MICROMIPS_GPREL7_S2: + case ELF::R_MICROMIPS_PC23_S2: + case ELF::R_MICROMIPS_PC21_S1: + case ELF::R_MICROMIPS_PC26_S1: + case ELF::R_MICROMIPS_PC18_S3: + case ELF::R_MICROMIPS_PC19_S2: + return true; + case ELF::R_MIPS16_26: + case ELF::R_MIPS16_GPREL: + case ELF::R_MIPS16_CALL16: + case ELF::R_MIPS16_TLS_GD: + case ELF::R_MIPS16_TLS_LDM: + case ELF::R_MIPS16_TLS_DTPREL_HI16: + case ELF::R_MIPS16_TLS_DTPREL_LO16: + case ELF::R_MIPS16_TLS_GOTTPREL: + case ELF::R_MIPS16_TLS_TPREL_HI16: + case ELF::R_MIPS16_TLS_TPREL_LO16: + llvm_unreachable("Unsupported MIPS16 relocation"); + return true; + } +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFObjectWriter/~ELFObjectWriter.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFObjectWriter/~ELFObjectWriter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFObjectWriter/~ELFObjectWriter.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/AttributeItem.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/AttributeItem.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/AttributeItem.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/AttributeType.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/AttributeType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/AttributeType.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/TargetELFStreamer.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/TargetELFStreamer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8dba92c27146b58cdb0e204902db70262196e9b1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/TargetELFStreamer.cpp @@ -0,0 +1,34 @@ +MipsTargetELFStreamer::MipsTargetELFStreamer(MCStreamer &S, const MCSubtargetInfo &STI) : MipsTargetStreamer(S), MicroMipsEnabled(false), STI(STI) { + MCAssembler &MCA = getStreamer().getAssembler(); + Pic = MCA.getContext().getObjectFileInfo()->isPositionIndependent(); + const FeatureBitset &Features = STI.getFeatureBits(); + unsigned EFlags = MCA.getELFHeaderEFlags(); + ABI = MipsABIInfo(STI.getTargetTriple().getArch() == Triple::ArchType::mipsel || STI.getTargetTriple().getArch() == Triple::ArchType::mips ? MipsABIInfo::O32() : MipsABIInfo::N64()); + if (Features[Mips::FeatureMips64r6]) + EFlags |= ELF::EF_MIPS_ARCH_64R6; + else if (Features[Mips::FeatureMips64r2] || Features[Mips::FeatureMips64r3] || Features[Mips::FeatureMips64r5]) + EFlags |= ELF::EF_MIPS_ARCH_64R2; + else if (Features[Mips::FeatureMips64]) + EFlags |= ELF::EF_MIPS_ARCH_64; + else if (Features[Mips::FeatureMips5]) + EFlags |= ELF::EF_MIPS_ARCH_5; + else if (Features[Mips::FeatureMips4]) + EFlags |= ELF::EF_MIPS_ARCH_4; + else if (Features[Mips::FeatureMips3]) + EFlags |= ELF::EF_MIPS_ARCH_3; + else if (Features[Mips::FeatureMips32r6]) + EFlags |= ELF::EF_MIPS_ARCH_32R6; + else if (Features[Mips::FeatureMips32r2] || Features[Mips::FeatureMips32r3] || Features[Mips::FeatureMips32r5]) + EFlags |= ELF::EF_MIPS_ARCH_32R2; + else if (Features[Mips::FeatureMips32]) + EFlags |= ELF::EF_MIPS_ARCH_32; + else if (Features[Mips::FeatureMips2]) + EFlags |= ELF::EF_MIPS_ARCH_2; + else + EFlags |= ELF::EF_MIPS_ARCH_1; + if (Features[Mips::FeatureCnMips]) + EFlags |= ELF::EF_MIPS_MACH_OCTEON; + if (Features[Mips::FeatureNaN2008]) + EFlags |= ELF::EF_MIPS_NAN2008; + MCA.setELFHeaderEFlags(EFlags); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/calculateContentSize.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/calculateContentSize.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/calculateContentSize.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/emitAttribute.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/emitAttribute.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/emitAttribute.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionNoPIC.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionNoPIC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4e5832effab9cb77d0b82db906e766fed26e295c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionNoPIC.cpp @@ -0,0 +1,2 @@ +void MipsTargetStreamer::emitDirectiveSetMicroMips() { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionNoRVC.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionNoRVC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4e5832effab9cb77d0b82db906e766fed26e295c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionNoRVC.cpp @@ -0,0 +1,2 @@ +void MipsTargetStreamer::emitDirectiveSetMicroMips() { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionNoRelax.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionNoRelax.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4e5832effab9cb77d0b82db906e766fed26e295c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionNoRelax.cpp @@ -0,0 +1,2 @@ +void MipsTargetStreamer::emitDirectiveSetMicroMips() { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionPIC.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionPIC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4e5832effab9cb77d0b82db906e766fed26e295c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionPIC.cpp @@ -0,0 +1,2 @@ +void MipsTargetStreamer::emitDirectiveSetMicroMips() { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionPop.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionPop.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4e5832effab9cb77d0b82db906e766fed26e295c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionPop.cpp @@ -0,0 +1,2 @@ +void MipsTargetStreamer::emitDirectiveSetMicroMips() { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionPush.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionPush.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4e5832effab9cb77d0b82db906e766fed26e295c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionPush.cpp @@ -0,0 +1,2 @@ +void MipsTargetStreamer::emitDirectiveSetMicroMips() { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionRVC.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionRVC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4e5832effab9cb77d0b82db906e766fed26e295c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionRVC.cpp @@ -0,0 +1,2 @@ +void MipsTargetStreamer::emitDirectiveSetMicroMips() { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionRelax.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionRelax.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4e5832effab9cb77d0b82db906e766fed26e295c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionRelax.cpp @@ -0,0 +1,2 @@ +void MipsTargetStreamer::emitDirectiveSetMicroMips() { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/emitIntTextAttribute.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/emitIntTextAttribute.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4e5832effab9cb77d0b82db906e766fed26e295c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/emitIntTextAttribute.cpp @@ -0,0 +1,2 @@ +void MipsTargetStreamer::emitDirectiveSetMicroMips() { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/emitTextAttribute.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/emitTextAttribute.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4e5832effab9cb77d0b82db906e766fed26e295c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/emitTextAttribute.cpp @@ -0,0 +1,2 @@ +void MipsTargetStreamer::emitDirectiveSetMicroMips() { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/finishAttributeSection.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/finishAttributeSection.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/finishAttributeSection.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/getAttributeItem.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/getAttributeItem.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/getAttributeItem.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/getStreamer.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/getStreamer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..169a904a234aa96ead39b9536240237025564fdf --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/getStreamer.cpp @@ -0,0 +1,3 @@ +MCELFStreamer &MipsTargetELFStreamer::getStreamer() { + return static_cast(Streamer); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/setAttributeItem1.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/setAttributeItem1.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/setAttributeItem1.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/setAttributeItem2.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/setAttributeItem2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/setAttributeItem2.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/setAttributeItems.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/setAttributeItems.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/ELFStreamer/setAttributeItems.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/FixupKind/enumFixups.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/FixupKind/enumFixups.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d35d8d0bcb890e7cd11ff4ce19ee49ce8fd56641 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/FixupKind/enumFixups.cpp @@ -0,0 +1,74 @@ +enum Fixups { + fixup_Mips_16 = FirstTargetFixupKind, + fixup_Mips_32, + fixup_Mips_REL32, + fixup_Mips_26, + fixup_Mips_HI16, + fixup_Mips_LO16, + fixup_Mips_GPREL16, + fixup_Mips_LITERAL, + fixup_Mips_GOT, + fixup_Mips_PC16, + fixup_Mips_CALL16, + fixup_Mips_GPREL32, + fixup_Mips_SHIFT5, + fixup_Mips_SHIFT6, + fixup_Mips_64, + fixup_Mips_TLSGD, + fixup_Mips_GOTTPREL, + fixup_Mips_TPREL_HI, + fixup_Mips_TPREL_LO, + fixup_Mips_TLSLDM, + fixup_Mips_DTPREL_HI, + fixup_Mips_DTPREL_LO, + fixup_Mips_Branch_PCRel, + fixup_Mips_GPOFF_HI, + fixup_MICROMIPS_GPOFF_HI, + fixup_Mips_GPOFF_LO, + fixup_MICROMIPS_GPOFF_LO, + fixup_Mips_GOT_PAGE, + fixup_Mips_GOT_OFST, + fixup_Mips_GOT_DISP, + fixup_Mips_HIGHER, + fixup_MICROMIPS_HIGHER, + fixup_Mips_HIGHEST, + fixup_MICROMIPS_HIGHEST, + fixup_Mips_GOT_HI16, + fixup_Mips_GOT_LO16, + fixup_Mips_CALL_HI16, + fixup_Mips_CALL_LO16, + fixup_MIPS_PC18_S3, + fixup_MIPS_PC19_S2, + fixup_MIPS_PC21_S2, + fixup_MIPS_PC26_S2, + fixup_MIPS_PCHI16, + fixup_MIPS_PCLO16, + fixup_MICROMIPS_26_S1, + fixup_MICROMIPS_HI16, + fixup_MICROMIPS_LO16, + fixup_MICROMIPS_GOT16, + fixup_MICROMIPS_PC7_S1, + fixup_MICROMIPS_PC10_S1, + fixup_MICROMIPS_PC16_S1, + fixup_MICROMIPS_PC26_S1, + fixup_MICROMIPS_PC19_S2, + fixup_MICROMIPS_PC18_S3, + fixup_MICROMIPS_PC21_S1, + fixup_MICROMIPS_CALL16, + fixup_MICROMIPS_GOT_DISP, + fixup_MICROMIPS_GOT_PAGE, + fixup_MICROMIPS_GOT_OFST, + fixup_MICROMIPS_TLS_GD, + fixup_MICROMIPS_TLS_LDM, + fixup_MICROMIPS_TLS_DTPREL_HI16, + fixup_MICROMIPS_TLS_DTPREL_LO16, + fixup_MICROMIPS_GOTTPREL, + fixup_MICROMIPS_TLS_TPREL_HI16, + fixup_MICROMIPS_TLS_TPREL_LO16, + fixup_Mips_SUB, + fixup_MICROMIPS_SUB, + fixup_Mips_JALR, + fixup_MICROMIPS_JALR, + LastTargetFixupKind, + NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind + }; \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/InstPrinter/InstPrinter.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/InstPrinter/InstPrinter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8c883a428f10b83a397704285295212b9d6aa78f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/InstPrinter/InstPrinter.cpp @@ -0,0 +1,2 @@ +MipsInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI) : MCInstPrinter(MAI, MII, MRI) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/InstPrinter/applyTargetSpecificCLOption.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/InstPrinter/applyTargetSpecificCLOption.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/InstPrinter/applyTargetSpecificCLOption.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/InstPrinter/getRegisterName.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/InstPrinter/getRegisterName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/InstPrinter/getRegisterName.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/InstPrinter/printAtomicMemOp.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/InstPrinter/printAtomicMemOp.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f6febf95d372d6ef3759047b96191a4f8d15d48d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/InstPrinter/printAtomicMemOp.cpp @@ -0,0 +1,4 @@ +void MipsInstPrinter::printFCCOperand(const MCInst *MI, int opNum, raw_ostream &O) { + const MCOperand& MO = MI->getOperand(opNum); + O << MipsFCCToString((Mips::CondCode)MO.getImm()); +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/InstPrinter/printBranchOperand.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/InstPrinter/printBranchOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8c2e2fe2d155616e4b721b21af96e900ec321a28 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/InstPrinter/printBranchOperand.cpp @@ -0,0 +1,5 @@ +void MipsInstPrinter::printFCCOperand(const MCInst *MI, int opNum, raw_ostream &O) { + const MCOperand& MO = MI->getOperand(opNum); + O << MipsFCCToString((Mips::CondCode)MO.getImm()); +} + diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/InstPrinter/printCSRSystemRegister.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/InstPrinter/printCSRSystemRegister.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9f7f9d577eb80771550e1b6a37ed0e03a59a19c3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/InstPrinter/printCSRSystemRegister.cpp @@ -0,0 +1,4 @@ +void MipsInstPrinter::printFCCOperand(const MCInst *MI, int opNum, raw_ostream &O) { + const MCOperand& MO = MI->getOperand(opNum); + O << MipsFCCToString((Mips::CondCode)MO.getImm()); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/InstPrinter/printFRMArg.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/InstPrinter/printFRMArg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9f7f9d577eb80771550e1b6a37ed0e03a59a19c3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/InstPrinter/printFRMArg.cpp @@ -0,0 +1,4 @@ +void MipsInstPrinter::printFCCOperand(const MCInst *MI, int opNum, raw_ostream &O) { + const MCOperand& MO = MI->getOperand(opNum); + O << MipsFCCToString((Mips::CondCode)MO.getImm()); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/InstPrinter/printFenceArg.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/InstPrinter/printFenceArg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9f7f9d577eb80771550e1b6a37ed0e03a59a19c3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/InstPrinter/printFenceArg.cpp @@ -0,0 +1,4 @@ +void MipsInstPrinter::printFCCOperand(const MCInst *MI, int opNum, raw_ostream &O) { + const MCOperand& MO = MI->getOperand(opNum); + O << MipsFCCToString((Mips::CondCode)MO.getImm()); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/InstPrinter/printInst.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/InstPrinter/printInst.cpp new file mode 100644 index 0000000000000000000000000000000000000000..70f5f37e80cc471496d5af941591d8998271fd72 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/InstPrinter/printInst.cpp @@ -0,0 +1,41 @@ +void MipsInstPrinter::printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) { + switch (MI->getOpcode()) { + default: + break; + case Mips::RDHWR: + case Mips::RDHWR64: + O << "\t.set\tpush\n"; + O << "\t.set\tmips32r2\n"; + break; + case Mips::Save16: + O << "\tsave\t"; + printSaveRestore(MI, O); + O << " # 16 bit inst\n"; + return; + case Mips::SaveX16: + O << "\tsave\t"; + printSaveRestore(MI, O); + O << "\n"; + return; + case Mips::Restore16: + O << "\trestore\t"; + printSaveRestore(MI, O); + O << " # 16 bit inst\n"; + return; + case Mips::RestoreX16: + O << "\trestore\t"; + printSaveRestore(MI, O); + O << "\n"; + return; + } + if (!printAliasInstr(MI, Address, O) && !printAlias(*MI, O)) + printInstruction(MI, Address, O); + printAnnotation(O, Annot); + switch (MI->getOpcode()) { + default: + break; + case Mips::RDHWR: + case Mips::RDHWR64: + O << "\n\t.set\tpop"; + } +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/InstPrinter/printOperand.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/InstPrinter/printOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ca8f19bc8f4f6fc50ae215ec71e28772be6a4589 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/InstPrinter/printOperand.cpp @@ -0,0 +1,13 @@ +void MipsInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) { + const MCOperand &Op = MI->getOperand(OpNo); + if (Op.isReg()) { + printRegName(O, Op.getReg()); + return; + } + if (Op.isImm()) { + O << formatImm(Op.getImm()); + return; + } + assert(Op.isExpr() && "unknown operand kind in printOperand"); + Op.getExpr()->print(O, &MAI, true); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/InstPrinter/printRegName.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/InstPrinter/printRegName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..26b28de5ee26164ed0644e6397f6fe42a83f0610 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/InstPrinter/printRegName.cpp @@ -0,0 +1,3 @@ +void MipsInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { + OS << '$' << StringRef(getRegisterName(RegNo)).lower(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/InstPrinter/printVMaskReg.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/InstPrinter/printVMaskReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9f7f9d577eb80771550e1b6a37ed0e03a59a19c3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/InstPrinter/printVMaskReg.cpp @@ -0,0 +1,4 @@ +void MipsInstPrinter::printFCCOperand(const MCInst *MI, int opNum, raw_ostream &O) { + const MCOperand& MO = MI->getOperand(opNum); + O << MipsFCCToString((Mips::CondCode)MO.getImm()); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/InstPrinter/printVTypeI.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/InstPrinter/printVTypeI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9f7f9d577eb80771550e1b6a37ed0e03a59a19c3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/InstPrinter/printVTypeI.cpp @@ -0,0 +1,4 @@ +void MipsInstPrinter::printFCCOperand(const MCInst *MI, int opNum, raw_ostream &O) { + const MCOperand& MO = MI->getOperand(opNum); + O << MipsFCCToString((Mips::CondCode)MO.getImm()); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCCodeEmitter/MCCodeEmitter.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCCodeEmitter/MCCodeEmitter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d80f585e9e89d79aa6714d871030005b94ba0ecc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCCodeEmitter/MCCodeEmitter.cpp @@ -0,0 +1,2 @@ +MipsMCCodeEmitter(const MCInstrInfo &mcii, MCContext &Ctx_, bool IsLittle) : MCII(mcii), Ctx(Ctx_), IsLittleEndian(IsLittle) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCCodeEmitter/createMCCodeEmitter.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCCodeEmitter/createMCCodeEmitter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..372156d0e033b36f8cdce99d9225b6cc7cd64e00 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCCodeEmitter/createMCCodeEmitter.cpp @@ -0,0 +1,3 @@ +MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx) { + return new MipsMCCodeEmitter(MCII, Ctx, true); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCCodeEmitter/encodeInstruction.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCCodeEmitter/encodeInstruction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..59427e05cfb3b9c5884cb26981fdac565f23caa6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCCodeEmitter/encodeInstruction.cpp @@ -0,0 +1,52 @@ +void MipsMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const { + MCInst TmpInst = MI; + switch (MI.getOpcode()) { + case Mips::DSLL: + case Mips::DSRL: + case Mips::DSRA: + case Mips::DROTR: + LowerLargeShift(TmpInst); + break; + case Mips::BEQC: + case Mips::BNEC: + case Mips::BEQC64: + case Mips::BNEC64: + case Mips::BOVC: + case Mips::BOVC_MMR6: + case Mips::BNVC: + case Mips::BNVC_MMR6: + LowerCompactBranch(TmpInst); + } + unsigned long N = Fixups.size(); + uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); + const unsigned Opcode = TmpInst.getOpcode(); + if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) && (Opcode != Mips::SLL_MM) && (Opcode != Mips::SLL_MMR6) && !Binary) + llvm_unreachable("unimplemented opcode in encodeInstruction()"); + int NewOpcode = -1; + if (isMicroMips(STI)) { + if (isMips32r6(STI)) { + NewOpcode = Mips::MipsR62MicroMipsR6(Opcode, Mips::Arch_micromipsr6); + if (NewOpcode == -1) + NewOpcode = Mips::Std2MicroMipsR6(Opcode, Mips::Arch_micromipsr6); + } + else + NewOpcode = Mips::Std2MicroMips(Opcode, Mips::Arch_micromips); + if (NewOpcode == -1) + NewOpcode = Mips::Dsp2MicroMips(Opcode, Mips::Arch_mmdsp); + if (NewOpcode != -1) { + if (Fixups.size() > N) + Fixups.pop_back(); + TmpInst.setOpcode (NewOpcode); + Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); + } + if (((MI.getOpcode() == Mips::MOVEP_MM) || (MI.getOpcode() == Mips::MOVEP_MMR6))) { + unsigned RegPair = getMovePRegPairOpValue(MI, 0, Fixups, STI); + Binary = (Binary & 0xFFFFFC7F) | (RegPair << 7); + } + } + const MCInstrDesc &Desc = MCII.get(TmpInst.getOpcode()); + unsigned Size = Desc.getSize(); + if (!Size) + llvm_unreachable("Desc.getSize() returns 0"); + emitInstruction(Binary, Size, STI, OS); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCCodeEmitter/getImmOpValue.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCCodeEmitter/getImmOpValue.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCCodeEmitter/getImmOpValue.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCCodeEmitter/getImmOpValueAsr1.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCCodeEmitter/getImmOpValueAsr1.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCCodeEmitter/getImmOpValueAsr1.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCCodeEmitter/getImmOpValueMinus1.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCCodeEmitter/getImmOpValueMinus1.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCCodeEmitter/getImmOpValueMinus1.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCCodeEmitter/getMachineOpValue.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCCodeEmitter/getMachineOpValue.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cb189232a33043c90a46e56fd801fda68c47150e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCCodeEmitter/getMachineOpValue.cpp @@ -0,0 +1,15 @@ +unsigned MipsMCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const { + if (MO.isReg()) { + unsigned Reg = MO.getReg(); + unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg); + return RegNo; + } + else if (MO.isImm()) { + return static_cast(MO.getImm()); + } + else if (MO.isFPImm()) { + return static_cast(APFloat(MO.getFPImm()).bitcastToAPInt().getHiBits(32).getLimitedValue()); + } + assert(MO.isExpr()); + return getExprOpValue(MO.getExpr(),Fixups, STI); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCCodeEmitter/getVMaskReg.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCCodeEmitter/getVMaskReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCCodeEmitter/getVMaskReg.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCCodeEmitter/~MCCodeEmitter.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCCodeEmitter/~MCCodeEmitter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCCodeEmitter/~MCCodeEmitter.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCExpr/MCExpr.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCExpr/MCExpr.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ebc24eb5d0635cf958da238e89ee965268122ac9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCExpr/MCExpr.cpp @@ -0,0 +1,2 @@ +explicit MipsMCExpr(MipsExprKind Kind, const MCExpr *Expr) : Kind(Kind), Expr(Expr) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCExpr/classof1.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCExpr/classof1.cpp new file mode 100644 index 0000000000000000000000000000000000000000..18efd6eb03d8a873e79039e5a7191354ce092d82 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCExpr/classof1.cpp @@ -0,0 +1,3 @@ +static bool classof(const MCExpr *E) { + return E->getKind() == MCExpr::Target; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCExpr/classof2.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCExpr/classof2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..18efd6eb03d8a873e79039e5a7191354ce092d82 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCExpr/classof2.cpp @@ -0,0 +1,3 @@ +static bool classof(const MCExpr *E) { + return E->getKind() == MCExpr::Target; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCExpr/create.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCExpr/create.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3094fed7f989b1117507901af1e6037af93072b9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCExpr/create.cpp @@ -0,0 +1,3 @@ +const MipsMCExpr *MipsMCExpr::create(MipsMCExpr::MipsExprKind Kind, const MCExpr *Expr, MCContext &Ctx) { + return new (Ctx) MipsMCExpr(Kind, Expr); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCExpr/enumVariantKind.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCExpr/enumVariantKind.cpp new file mode 100644 index 0000000000000000000000000000000000000000..27c457d66a9d950c263ecd8db1e0cc53834ab166 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCExpr/enumVariantKind.cpp @@ -0,0 +1,29 @@ +enum MipsExprKind { + MEK_None, + MEK_CALL_HI16, + MEK_CALL_LO16, + MEK_DTPREL, + MEK_DTPREL_HI, + MEK_DTPREL_LO, + MEK_GOT, + MEK_GOTTPREL, + MEK_GOT_CALL, + MEK_GOT_DISP, + MEK_GOT_HI16, + MEK_GOT_LO16, + MEK_GOT_OFST, + MEK_GOT_PAGE, + MEK_GPREL, + MEK_HI, + MEK_HIGHER, + MEK_HIGHEST, + MEK_LO, + MEK_NEG, + MEK_PCREL_HI16, + MEK_PCREL_LO16, + MEK_TLSGD, + MEK_TLSLDM, + MEK_TPREL_HI, + MEK_TPREL_LO, + MEK_Special, +}; \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCExpr/evaluateAsConstant.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCExpr/evaluateAsConstant.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCExpr/evaluateAsConstant.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCExpr/evaluateAsInt64.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCExpr/evaluateAsInt64.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCExpr/evaluateAsInt64.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCExpr/evaluateAsRelocatableImpl.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCExpr/evaluateAsRelocatableImpl.cpp new file mode 100644 index 0000000000000000000000000000000000000000..670c710ada9b1fb33725c09e83b7683e32a4776f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCExpr/evaluateAsRelocatableImpl.cpp @@ -0,0 +1,62 @@ +bool MipsMCExpr::evaluateAsRelocatableImpl(MCValue &Res, const MCAsmLayout *Layout, const MCFixup *Fixup) const { + if (isGpOff()) { + const MCExpr *SubExpr = cast(cast(getSubExpr())->getSubExpr())->getSubExpr(); + if (!SubExpr->evaluateAsRelocatable(Res, Layout, Fixup)) + return false; + Res = MCValue::get(Res.getSymA(), Res.getSymB(), Res.getConstant(), MEK_Special); + return true; + } + if (!getSubExpr()->evaluateAsRelocatable(Res, Layout, Fixup)) + return false; + if (Res.getRefKind() != MCSymbolRefExpr::VK_None) + return false; + if (Res.isAbsolute() && Fixup == nullptr) { + int64_t AbsVal = Res.getConstant(); + switch (Kind) { + case MEK_None: + case MEK_Special: + llvm_unreachable("MEK_None and MEK_Special are invalid"); + case MEK_DTPREL: + return getSubExpr()->evaluateAsRelocatable(Res, Layout, Fixup); + case MEK_DTPREL_HI: + case MEK_DTPREL_LO: + case MEK_GOT: + case MEK_GOTTPREL: + case MEK_GOT_CALL: + case MEK_GOT_DISP: + case MEK_GOT_HI16: + case MEK_GOT_LO16: + case MEK_GOT_OFST: + case MEK_GOT_PAGE: + case MEK_GPREL: + case MEK_PCREL_HI16: + case MEK_PCREL_LO16: + case MEK_TLSGD: + case MEK_TLSLDM: + case MEK_TPREL_HI: + case MEK_TPREL_LO: + return false; + case MEK_LO: + case MEK_CALL_LO16: + AbsVal = SignExtend64<16>(AbsVal); + break; + case MEK_CALL_HI16: + case MEK_HI: + AbsVal = SignExtend64<16>((AbsVal + 0x8000) >> 16); + break; + case MEK_HIGHER: + AbsVal = SignExtend64<16>((AbsVal + 0x80008000LL) >> 32); + break; + case MEK_HIGHEST: + AbsVal = SignExtend64<16>((AbsVal + 0x800080008000LL) >> 48); + break; + case MEK_NEG: + AbsVal = -AbsVal; + break; + } + Res = MCValue::get(AbsVal); + return true; + } + Res = MCValue::get(Res.getSymA(), Res.getSymB(), Res.getConstant(), getKind()); + return true; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCExpr/findAssociatedFragment.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCExpr/findAssociatedFragment.cpp new file mode 100644 index 0000000000000000000000000000000000000000..08da2eccf295202e12e9442a7e9eb5f68e318ec8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCExpr/findAssociatedFragment.cpp @@ -0,0 +1,3 @@ +MCFragment *findAssociatedFragment() const override { + return getSubExpr()->findAssociatedFragment(); + } \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCExpr/fixELFSymbolsInTLSFixups.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCExpr/fixELFSymbolsInTLSFixups.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cc1b15aad7b4dd5503f3f01be4930b6d0030989f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCExpr/fixELFSymbolsInTLSFixups.cpp @@ -0,0 +1,38 @@ +void MipsMCExpr::fixELFSymbolsInTLSFixups(MCAssembler &Asm) const { + switch (getKind()) { + case MEK_None: + case MEK_Special: + llvm_unreachable("MEK_None and MEK_Special are invalid"); + break; + case MEK_CALL_HI16: + case MEK_CALL_LO16: + case MEK_GOT: + case MEK_GOT_CALL: + case MEK_GOT_DISP: + case MEK_GOT_HI16: + case MEK_GOT_LO16: + case MEK_GOT_OFST: + case MEK_GOT_PAGE: + case MEK_GPREL: + case MEK_HI: + case MEK_HIGHER: + case MEK_HIGHEST: + case MEK_LO: + case MEK_NEG: + case MEK_PCREL_HI16: + case MEK_PCREL_LO16: + if (const MipsMCExpr *E = dyn_cast(getSubExpr())) + E->fixELFSymbolsInTLSFixups(Asm); + break; + case MEK_DTPREL: + case MEK_DTPREL_HI: + case MEK_DTPREL_LO: + case MEK_TLSLDM: + case MEK_TLSGD: + case MEK_GOTTPREL: + case MEK_TPREL_HI: + case MEK_TPREL_LO: + fixELFSymbolsInTLSFixupsImpl(getSubExpr(), Asm); + break; + } +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCExpr/fixELFSymbolsInTLSFixupsImpl.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCExpr/fixELFSymbolsInTLSFixupsImpl.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2e9ca0c40060014e6baba99f4f067c0ffd884676 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCExpr/fixELFSymbolsInTLSFixupsImpl.cpp @@ -0,0 +1,23 @@ +static void fixELFSymbolsInTLSFixupsImpl(const MCExpr *Expr, MCAssembler &Asm) { + switch (Expr->getKind()) { + case MCExpr::Target: + fixELFSymbolsInTLSFixupsImpl(cast(Expr)->getSubExpr(), Asm); + break; + case MCExpr::Constant: + break; + case MCExpr::Binary: { + const MCBinaryExpr *BE = cast(Expr); + fixELFSymbolsInTLSFixupsImpl(BE->getLHS(), Asm); + fixELFSymbolsInTLSFixupsImpl(BE->getRHS(), Asm); + break; + } + case MCExpr::SymbolRef: { + const MCSymbolRefExpr &SymRef = *cast(Expr); + cast(SymRef.getSymbol()).setType(ELF::STT_TLS); + break; + } + case MCExpr::Unary: + fixELFSymbolsInTLSFixupsImpl(cast(Expr)->getSubExpr(), Asm); + break; + } +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCExpr/getKind.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCExpr/getKind.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1fca267923e392a3304df0e777f53b17ec30c814 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCExpr/getKind.cpp @@ -0,0 +1,3 @@ +MipsExprKind getKind() const { + return Kind; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCExpr/getPCRelHiFixup.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCExpr/getPCRelHiFixup.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCExpr/getPCRelHiFixup.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCExpr/getSubExpr.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCExpr/getSubExpr.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c70598c07f1d0625d598037483c5a146ef4feaa5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCExpr/getSubExpr.cpp @@ -0,0 +1,3 @@ +const MCExpr *getSubExpr() const { + return Expr; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCExpr/getVariantKindForName.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCExpr/getVariantKindForName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCExpr/getVariantKindForName.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCExpr/getVariantKindName.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCExpr/getVariantKindName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCExpr/getVariantKindName.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCExpr/printImpl.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCExpr/printImpl.cpp new file mode 100644 index 0000000000000000000000000000000000000000..47538cb3613642553049ed964b24bf4d4b25031d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCExpr/printImpl.cpp @@ -0,0 +1,90 @@ +void MipsMCExpr::printImpl(raw_ostream &OS, const MCAsmInfo *MAI) const { + int64_t AbsVal; + switch (Kind) { + case MEK_None: + case MEK_Special: + llvm_unreachable("MEK_None and MEK_Special are invalid"); + break; + case MEK_DTPREL: + getSubExpr()->print(OS, MAI, true); + return; + case MEK_CALL_HI16: + OS << "%call_hi"; + break; + case MEK_CALL_LO16: + OS << "%call_lo"; + break; + case MEK_DTPREL_HI: + OS << "%dtprel_hi"; + break; + case MEK_DTPREL_LO: + OS << "%dtprel_lo"; + break; + case MEK_GOT: + OS << "%got"; + break; + case MEK_GOTTPREL: + OS << "%gottprel"; + break; + case MEK_GOT_CALL: + OS << "%call16"; + break; + case MEK_GOT_DISP: + OS << "%got_disp"; + break; + case MEK_GOT_HI16: + OS << "%got_hi"; + break; + case MEK_GOT_LO16: + OS << "%got_lo"; + break; + case MEK_GOT_PAGE: + OS << "%got_page"; + break; + case MEK_GOT_OFST: + OS << "%got_ofst"; + break; + case MEK_GPREL: + OS << "%gp_rel"; + break; + case MEK_HI: + OS << "%hi"; + break; + case MEK_HIGHER: + OS << "%higher"; + break; + case MEK_HIGHEST: + OS << "%highest"; + break; + case MEK_LO: + OS << "%lo"; + break; + case MEK_NEG: + OS << "%neg"; + break; + case MEK_PCREL_HI16: + OS << "%pcrel_hi"; + break; + case MEK_PCREL_LO16: + OS << "%pcrel_lo"; + break; + case MEK_TLSGD: + OS << "%tlsgd"; + break; + case MEK_TLSLDM: + OS << "%tlsldm"; + break; + case MEK_TPREL_HI: + OS << "%tprel_hi"; + break; + case MEK_TPREL_LO: + OS << "%tprel_lo"; + break; + } + OS << '('; + if (Expr->evaluateAsAbsolute(AbsVal)) + OS << AbsVal; + else + Expr->print(OS, MAI, true); + OS << ')'; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCExpr/visitUsedExpr.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCExpr/visitUsedExpr.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8372a7ff589eca544f1df8088f54e8b8b2b114fa --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCExpr/visitUsedExpr.cpp @@ -0,0 +1,3 @@ +void MipsMCExpr::visitUsedExpr(MCStreamer &Streamer) const { + Streamer.visitUsedExpr(*getSubExpr()); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCTargetDesc/InstrAnalysis.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCTargetDesc/InstrAnalysis.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5658244ea718376f3d69b7fbc49854fa42668962 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCTargetDesc/InstrAnalysis.cpp @@ -0,0 +1,2 @@ +MipsMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCTargetDesc/LLVMInitializeTargetMC.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCTargetDesc/LLVMInitializeTargetMC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7b01b2aad777f0e33601f9c86bac72b81a8343d6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCTargetDesc/LLVMInitializeTargetMC.cpp @@ -0,0 +1,19 @@ +extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMipsTargetMC() { + for (Target *T : {&getTheMipsTarget(), &getTheMipselTarget(), &getTheMips64Target(), &getTheMips64elTarget()}) { + RegisterMCAsmInfoFn X(*T, createMipsMCAsmInfo); + TargetRegistry::RegisterMCInstrInfo(*T, createMipsMCInstrInfo); + TargetRegistry::RegisterMCRegInfo(*T, createMipsMCRegisterInfo); + TargetRegistry::RegisterELFStreamer(*T, createMCStreamer); + TargetRegistry::RegisterAsmTargetStreamer(*T, createMipsAsmTargetStreamer); + TargetRegistry::RegisterNullTargetStreamer(*T, createMipsNullTargetStreamer); + TargetRegistry::RegisterMCSubtargetInfo(*T, createMipsMCSubtargetInfo); + TargetRegistry::RegisterMCInstrAnalysis(*T, createMipsMCInstrAnalysis); + TargetRegistry::RegisterMCInstPrinter(*T, createMipsMCInstPrinter); + TargetRegistry::RegisterObjectTargetStreamer(*T, createMipsObjectTargetStreamer); + TargetRegistry::RegisterMCAsmBackend(*T, createMipsAsmBackend); + } + for (Target *T : {&getTheMipsTarget(), &getTheMips64Target()}) + TargetRegistry::RegisterMCCodeEmitter(*T, createMipsMCCodeEmitterEB); + for (Target *T : {&getTheMipselTarget(), &getTheMips64elTarget()}) + TargetRegistry::RegisterMCCodeEmitter(*T, createMipsMCCodeEmitterEL); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCTargetDesc/createAsmTargetStreamer.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCTargetDesc/createAsmTargetStreamer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..98ebbf2d49c4647aed8ecd64155f39e30e2d242a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCTargetDesc/createAsmTargetStreamer.cpp @@ -0,0 +1,3 @@ +static MCTargetStreamer *createMipsAsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint, bool isVerboseAsm) { + return new MipsTargetAsmStreamer(S, OS); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCTargetDesc/createInstrAnalysis.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCTargetDesc/createInstrAnalysis.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b2a5cba504ed7a086ff506e9d8e6bc2f4fde5991 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCTargetDesc/createInstrAnalysis.cpp @@ -0,0 +1,3 @@ +static MCInstrAnalysis *createMipsMCInstrAnalysis(const MCInstrInfo *Info) { + return new MipsMCInstrAnalysis(Info); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCTargetDesc/createMCAsmInfo.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCTargetDesc/createMCAsmInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..837b9167e024dfc0068281dbe50fc9ad3064ca21 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCTargetDesc/createMCAsmInfo.cpp @@ -0,0 +1,7 @@ +static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI, const Triple &TT, const MCTargetOptions &Options) { + MCAsmInfo *MAI = new MipsMCAsmInfo(TT, Options); + unsigned SP = MRI.getDwarfRegNum(Mips::SP, true); + MCCFIInstruction Inst = MCCFIInstruction::createDefCfaRegister(nullptr, SP); + MAI->addInitialFrameState(Inst); + return MAI; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCTargetDesc/createMCInstPrinter.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCTargetDesc/createMCInstPrinter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..df05a3cab536755996ee2967e89aee556fc9d7aa --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCTargetDesc/createMCInstPrinter.cpp @@ -0,0 +1,3 @@ +static MCInstPrinter *createMipsMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI) { + return new MipsInstPrinter(MAI, MII, MRI); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCTargetDesc/createMCInstrInfo.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCTargetDesc/createMCInstrInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d50ca24c8cac1fc0d6821b37c8cea1728525d7a4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCTargetDesc/createMCInstrInfo.cpp @@ -0,0 +1,5 @@ +static MCInstrInfo *createMipsMCInstrInfo() { + MCInstrInfo *X = new MCInstrInfo(); + InitMipsMCInstrInfo(X); + return X; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCTargetDesc/createMCRegisterInfo.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCTargetDesc/createMCRegisterInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..39b142645d1a74904b92b3d82dd3360575145767 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCTargetDesc/createMCRegisterInfo.cpp @@ -0,0 +1,5 @@ +static MCRegisterInfo *createMipsMCRegisterInfo(const Triple &TT) { + MCRegisterInfo *X = new MCRegisterInfo(); + InitMipsMCRegisterInfo(X, Mips::RA); + return X; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCTargetDesc/createMCSubtargetInfo.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCTargetDesc/createMCSubtargetInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c05371de5a90f36670a3dbf3f15208b2ffbee21f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCTargetDesc/createMCSubtargetInfo.cpp @@ -0,0 +1,4 @@ +static MCSubtargetInfo *createMipsMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { + CPU = MIPS_MC::selectMipsCPU(TT, CPU); + return createMipsMCSubtargetInfoImpl(TT, CPU, CPU, FS); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCTargetDesc/createNullTargetStreamer.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCTargetDesc/createNullTargetStreamer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cf2f5e7108d8aa4cf1b43892131f3f21abecdd36 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCTargetDesc/createNullTargetStreamer.cpp @@ -0,0 +1,3 @@ +static MCTargetStreamer *createMipsNullTargetStreamer(MCStreamer &S) { + return new MipsTargetStreamer(S); +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCTargetDesc/createObjectTargetStreamer.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCTargetDesc/createObjectTargetStreamer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..10ee25d3af46cc3570b3f04fcd7ca01c661f6f81 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCTargetDesc/createObjectTargetStreamer.cpp @@ -0,0 +1,3 @@ +static MCTargetStreamer *createMipsObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) { + return new MipsTargetELFStreamer(S, STI); +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCTargetDesc/evaluateBranch.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCTargetDesc/evaluateBranch.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6b84c6fb1759fb7beed2dd8b743d221a44f24ed8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MCTargetDesc/evaluateBranch.cpp @@ -0,0 +1,18 @@ +bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size, uint64_t &Target) const override { + unsigned NumOps = Inst.getNumOperands(); + if (NumOps == 0) + return false; + switch (Info->get(Inst.getOpcode()).OpInfo[NumOps - 1].OperandType) { + case MCOI::OPERAND_UNKNOWN: + case MCOI::OPERAND_IMMEDIATE: { + uint64_t Region = Addr & ~uint64_t(0xfffffff); + Target = Region + Inst.getOperand(NumOps - 1).getImm(); + return true; + } + case MCOI::OPERAND_PCREL: + Target = Addr + Inst.getOperand(NumOps - 1).getImm(); + return true; + default: + return false; + } +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MatInt/generateInstSeq.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MatInt/generateInstSeq.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MatInt/generateInstSeq.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MatInt/getIntMatCost.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MatInt/getIntMatCost.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MatInt/getIntMatCost.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MatInt/structInst.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MatInt/structInst.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/MatInt/structInst.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/TargetAsmStreamer.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/TargetAsmStreamer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ee43d3cfc20af7f5ce81d111b7c1eb270406abca --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/TargetAsmStreamer.cpp @@ -0,0 +1,2 @@ +MipsTargetAsmStreamer::MipsTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS) : MipsTargetStreamer(S), OS(OS) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/TargetStreamer.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/TargetStreamer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6e217f82aee591bb534adeb6d7253244f98d5f09 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/TargetStreamer.cpp @@ -0,0 +1,3 @@ +MipsTargetStreamer::MipsTargetStreamer(MCStreamer &S) : MCTargetStreamer(S), GPReg(Mips::GP), ModuleDirectiveAllowed(true) { + GPRInfoSet = FPRInfoSet = FrameInfoSet = false; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitAttribute.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitAttribute.cpp new file mode 100644 index 0000000000000000000000000000000000000000..23a6029df8553c9ec55644c6e53170c37b3cf87d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitAttribute.cpp @@ -0,0 +1,3 @@ +void MipsTargetAsmStreamer::emitDirectiveOptionPic0() { + OS << "\t.option\tpic0\n"; +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitAttribute2.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitAttribute2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4bf64c8323e7b7238f06effee213a19639b43ba4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitAttribute2.cpp @@ -0,0 +1,2 @@ +void MipsTargetStreamer::emitDirectiveModuleCRC() { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionNoPIC.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionNoPIC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..23a6029df8553c9ec55644c6e53170c37b3cf87d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionNoPIC.cpp @@ -0,0 +1,3 @@ +void MipsTargetAsmStreamer::emitDirectiveOptionPic0() { + OS << "\t.option\tpic0\n"; +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionNoPIC2.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionNoPIC2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4bf64c8323e7b7238f06effee213a19639b43ba4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionNoPIC2.cpp @@ -0,0 +1,2 @@ +void MipsTargetStreamer::emitDirectiveModuleCRC() { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionNoRVC.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionNoRVC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..23a6029df8553c9ec55644c6e53170c37b3cf87d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionNoRVC.cpp @@ -0,0 +1,3 @@ +void MipsTargetAsmStreamer::emitDirectiveOptionPic0() { + OS << "\t.option\tpic0\n"; +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionNoRVC2.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionNoRVC2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4bf64c8323e7b7238f06effee213a19639b43ba4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionNoRVC2.cpp @@ -0,0 +1,2 @@ +void MipsTargetStreamer::emitDirectiveModuleCRC() { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionNoRelax.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionNoRelax.cpp new file mode 100644 index 0000000000000000000000000000000000000000..23a6029df8553c9ec55644c6e53170c37b3cf87d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionNoRelax.cpp @@ -0,0 +1,3 @@ +void MipsTargetAsmStreamer::emitDirectiveOptionPic0() { + OS << "\t.option\tpic0\n"; +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionNoRelax2.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionNoRelax2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4bf64c8323e7b7238f06effee213a19639b43ba4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionNoRelax2.cpp @@ -0,0 +1,2 @@ +void MipsTargetStreamer::emitDirectiveModuleCRC() { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionPIC.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionPIC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..23a6029df8553c9ec55644c6e53170c37b3cf87d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionPIC.cpp @@ -0,0 +1,3 @@ +void MipsTargetAsmStreamer::emitDirectiveOptionPic0() { + OS << "\t.option\tpic0\n"; +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionPIC2.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionPIC2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4bf64c8323e7b7238f06effee213a19639b43ba4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionPIC2.cpp @@ -0,0 +1,2 @@ +void MipsTargetStreamer::emitDirectiveModuleCRC() { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionPop.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionPop.cpp new file mode 100644 index 0000000000000000000000000000000000000000..23a6029df8553c9ec55644c6e53170c37b3cf87d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionPop.cpp @@ -0,0 +1,3 @@ +void MipsTargetAsmStreamer::emitDirectiveOptionPic0() { + OS << "\t.option\tpic0\n"; +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionPop2.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionPop2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4bf64c8323e7b7238f06effee213a19639b43ba4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionPop2.cpp @@ -0,0 +1,2 @@ +void MipsTargetStreamer::emitDirectiveModuleCRC() { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionPush.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionPush.cpp new file mode 100644 index 0000000000000000000000000000000000000000..23a6029df8553c9ec55644c6e53170c37b3cf87d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionPush.cpp @@ -0,0 +1,3 @@ +void MipsTargetAsmStreamer::emitDirectiveOptionPic0() { + OS << "\t.option\tpic0\n"; +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionPush2.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionPush2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4bf64c8323e7b7238f06effee213a19639b43ba4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionPush2.cpp @@ -0,0 +1,2 @@ +void MipsTargetStreamer::emitDirectiveModuleCRC() { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionRVC.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionRVC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..23a6029df8553c9ec55644c6e53170c37b3cf87d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionRVC.cpp @@ -0,0 +1,3 @@ +void MipsTargetAsmStreamer::emitDirectiveOptionPic0() { + OS << "\t.option\tpic0\n"; +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionRVC2.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionRVC2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4bf64c8323e7b7238f06effee213a19639b43ba4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionRVC2.cpp @@ -0,0 +1,2 @@ +void MipsTargetStreamer::emitDirectiveModuleCRC() { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionRelax.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionRelax.cpp new file mode 100644 index 0000000000000000000000000000000000000000..23a6029df8553c9ec55644c6e53170c37b3cf87d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionRelax.cpp @@ -0,0 +1,3 @@ +void MipsTargetAsmStreamer::emitDirectiveOptionPic0() { + OS << "\t.option\tpic0\n"; +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionRelax2.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionRelax2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4bf64c8323e7b7238f06effee213a19639b43ba4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionRelax2.cpp @@ -0,0 +1,2 @@ +void MipsTargetStreamer::emitDirectiveModuleCRC() { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitIntTextAttribute.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitIntTextAttribute.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4bf64c8323e7b7238f06effee213a19639b43ba4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitIntTextAttribute.cpp @@ -0,0 +1,2 @@ +void MipsTargetStreamer::emitDirectiveModuleCRC() { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitIntTextAttribute2.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitIntTextAttribute2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4bf64c8323e7b7238f06effee213a19639b43ba4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitIntTextAttribute2.cpp @@ -0,0 +1,2 @@ +void MipsTargetStreamer::emitDirectiveModuleCRC() { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitTargetAttributes.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitTargetAttributes.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4bf64c8323e7b7238f06effee213a19639b43ba4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitTargetAttributes.cpp @@ -0,0 +1,2 @@ +void MipsTargetStreamer::emitDirectiveModuleCRC() { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitTextAttribute.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitTextAttribute.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4bf64c8323e7b7238f06effee213a19639b43ba4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitTextAttribute.cpp @@ -0,0 +1,2 @@ +void MipsTargetStreamer::emitDirectiveModuleCRC() { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitTextAttribute2.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitTextAttribute2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..23a6029df8553c9ec55644c6e53170c37b3cf87d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/emitTextAttribute2.cpp @@ -0,0 +1,3 @@ +void MipsTargetAsmStreamer::emitDirectiveOptionPic0() { + OS << "\t.option\tpic0\n"; +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/finish.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/finish.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d532f0f886a4e984cb24aea1e0b94a27c8f44b31 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/finish.cpp @@ -0,0 +1,47 @@ +void MipsTargetELFStreamer::finish() { + MCAssembler &MCA = getStreamer().getAssembler(); + const MCObjectFileInfo &OFI = *MCA.getContext().getObjectFileInfo(); + MCSection &TextSection = *OFI.getTextSection(); + MCA.registerSection(TextSection); + MCSection &DataSection = *OFI.getDataSection(); + MCA.registerSection(DataSection); + MCSection &BSSSection = *OFI.getBSSSection(); + MCA.registerSection(BSSSection); + TextSection.setAlignment(Align(std::max(16u, TextSection.getAlignment()))); + DataSection.setAlignment(Align(std::max(16u, DataSection.getAlignment()))); + BSSSection.setAlignment(Align(std::max(16u, BSSSection.getAlignment()))); + if (RoundSectionSizes) { + MCStreamer &OS = getStreamer(); + for (MCSection &S : MCA) { + MCSectionELF &Section = static_cast(S); + unsigned Alignment = Section.getAlignment(); + if (Alignment) { + OS.SwitchSection(&Section); + if (Section.UseCodeAlign()) + OS.emitCodeAlignment(Alignment, Alignment); + else + OS.emitValueToAlignment(Alignment, 0, 1, Alignment); + } + } + } + const FeatureBitset &Features = STI.getFeatureBits(); + unsigned EFlags = MCA.getELFHeaderEFlags(); + if (getABI().IsO32()) + EFlags |= ELF::EF_MIPS_ABI_O32; + else if (getABI().IsN32()) + EFlags |= ELF::EF_MIPS_ABI2; + if (Features[Mips::FeatureGP64Bit]) { + if (getABI().IsO32()) + EFlags |= ELF::EF_MIPS_32BITMODE; /* Compatibility Mode */ + } + else if (Features[Mips::FeatureMips64r2] || Features[Mips::FeatureMips64]) + EFlags |= ELF::EF_MIPS_32BITMODE; + if (!Features[Mips::FeatureNoABICalls]) + EFlags |= ELF::EF_MIPS_CPIC; + if (Pic) + EFlags |= ELF::EF_MIPS_PIC | ELF::EF_MIPS_CPIC; + MCA.setELFHeaderEFlags(EFlags); + MipsELFStreamer &MEF = static_cast(Streamer); + MEF.EmitMipsOptionRecords(); + emitMipsAbiFlags(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/finishAttributeSection.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/finishAttributeSection.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/finishAttributeSection.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/finishAttributeSection2.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/finishAttributeSection2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Emission/TargetStreamer/finishAttributeSection2.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/CleanupVSETVLI/CleanupVSETVLI.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/CleanupVSETVLI/CleanupVSETVLI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..57aeffd0e2e2e5bb1200734269fc42fb5b8f16c9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/CleanupVSETVLI/CleanupVSETVLI.cpp @@ -0,0 +1,2 @@ +MipsModuleDAGToDAGISel() : MachineFunctionPass(ID) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/CleanupVSETVLI/createPass.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/CleanupVSETVLI/createPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..66bbc81adf0ef98fff67099cd474312163d2ef95 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/CleanupVSETVLI/createPass.cpp @@ -0,0 +1,3 @@ +llvm::FunctionPass *llvm::createMipsModuleISelDagPass() { + return new MipsModuleDAGToDAGISel(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/CleanupVSETVLI/getAnalysisUsage.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/CleanupVSETVLI/getAnalysisUsage.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3f3e70065dbb1b3bcc423b768c1c4c1713ba4da5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/CleanupVSETVLI/getAnalysisUsage.cpp @@ -0,0 +1,4 @@ +void getAnalysisUsage(AnalysisUsage &AU) const override { + AU.addRequired(); + MachineFunctionPass::getAnalysisUsage(AU); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/CleanupVSETVLI/getPassName.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/CleanupVSETVLI/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..90c890951e14cd0629d6e0878884a87bb8c79386 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/CleanupVSETVLI/getPassName.cpp @@ -0,0 +1,3 @@ +StringRef getPassName() const override { + return "Mips Branch Expansion Pass"; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/CleanupVSETVLI/getRequiredProperties.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/CleanupVSETVLI/getRequiredProperties.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c75653867ef66dd435b2ea7205493d823d8fbb30 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/CleanupVSETVLI/getRequiredProperties.cpp @@ -0,0 +1,3 @@ +MachineFunctionProperties getRequiredProperties() const override { + return MachineFunctionProperties().set(MachineFunctionProperties::Property::NoVRegs); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/CleanupVSETVLI/runOnMachineBasicBlock.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/CleanupVSETVLI/runOnMachineBasicBlock.cpp new file mode 100644 index 0000000000000000000000000000000000000000..77e28c673af82e311aad8811a99167bc300e4849 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/CleanupVSETVLI/runOnMachineBasicBlock.cpp @@ -0,0 +1,49 @@ +bool MipsDelaySlotFiller::runOnMachineBasicBlock(MachineBasicBlock &MBB) { + bool Changed = false; + const MipsSubtarget &STI = MBB.getParent()->getSubtarget(); + bool InMicroMipsMode = STI.inMicroMipsMode(); + const MipsInstrInfo *TII = STI.getInstrInfo(); + for (Iter I = MBB.begin(); I != MBB.end(); ++I) { + if (!hasUnoccupiedSlot(&*I)) + continue; + if (!DisableDelaySlotFiller && (TM->getOptLevel() != CodeGenOpt::None) && !(InMicroMipsMode && STI.hasMips32r6())) { + bool Filled = false; + if (MipsCompactBranchPolicy.getValue() != CB_Always || !TII->getEquivalentCompactForm(I)) { + if (searchBackward(MBB, *I)) { + LLVM_DEBUG(dbgs() << DEBUG_TYPE ": found instruction for delay slot in backwards search.\n"); + Filled = true; + } + else if (I->isTerminator()) { + if (searchSuccBBs(MBB, I)) { + Filled = true; + LLVM_DEBUG(dbgs() << DEBUG_TYPE ": found instruction for delay slot in successor BB search.\n"); + } + } + else if (searchForward(MBB, I)) { + LLVM_DEBUG(dbgs() << DEBUG_TYPE ": found instruction for delay slot in forwards search.\n"); + Filled = true; + } + } + if (Filled) { + MachineBasicBlock::instr_iterator DSI = I.getInstrIterator(); + if (InMicroMipsMode && TII->getInstSizeInBytes(*std::next(DSI)) == 2 && DSI->isCall()) { + DSI->setDesc(TII->get(getEquivalentCallShort(DSI->getOpcode()))); + } + ++FilledSlots; + Changed = true; + continue; + } + } + if ((InMicroMipsMode || (STI.hasMips32r6() && MipsCompactBranchPolicy != CB_Never)) && TII->getEquivalentCompactForm(I)) { + I = replaceWithCompactBranch(MBB, I, I->getDebugLoc()); + Changed = true; + continue; + } + LLVM_DEBUG(dbgs() << DEBUG_TYPE << ": could not fill delay slot for "; I->dump()); + BuildMI(MBB, std::next(I), I->getDebugLoc(), TII->get(Mips::NOP)); + MIBundleBuilder(MBB, I, std::next(I, 2)); + ++FilledSlots; + Changed = true; + } + return Changed; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/CleanupVSETVLI/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/CleanupVSETVLI/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..62edb7f880dc7a87d5437717d542d7ef50894acb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/CleanupVSETVLI/runOnMachineFunction.cpp @@ -0,0 +1,21 @@ +bool MipsBranchExpansion::runOnMachineFunction(MachineFunction &MF) { + const TargetMachine &TM = MF.getTarget(); + IsPIC = TM.isPositionIndependent(); + ABI = static_cast(TM).getABI(); + STI = &static_cast(MF.getSubtarget()); + TII = static_cast(STI->getInstrInfo()); + if (IsPIC && ABI.IsO32() && MF.getInfo()->globalBaseRegSet()) + emitGPDisp(MF, TII); + MFp = &MF; + ForceLongBranchFirstPass = ForceLongBranch; + bool longBranchChanged = handlePossibleLongBranch(); + bool forbiddenSlotChanged = handleForbiddenSlot(); + bool Changed = longBranchChanged || forbiddenSlotChanged; + while (forbiddenSlotChanged) { + longBranchChanged = handlePossibleLongBranch(); + if (!longBranchChanged) + break; + forbiddenSlotChanged = handleForbiddenSlot(); + } + return Changed; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandAtomicPseudoInsts/ExpandAtomicPseudo.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandAtomicPseudoInsts/ExpandAtomicPseudo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..57aeffd0e2e2e5bb1200734269fc42fb5b8f16c9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandAtomicPseudoInsts/ExpandAtomicPseudo.cpp @@ -0,0 +1,2 @@ +MipsModuleDAGToDAGISel() : MachineFunctionPass(ID) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandAtomicPseudoInsts/createPass.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandAtomicPseudoInsts/createPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..66bbc81adf0ef98fff67099cd474312163d2ef95 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandAtomicPseudoInsts/createPass.cpp @@ -0,0 +1,3 @@ +llvm::FunctionPass *llvm::createMipsModuleISelDagPass() { + return new MipsModuleDAGToDAGISel(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandAtomicPseudoInsts/expandMBB.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandAtomicPseudoInsts/expandMBB.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e591da793babbe33581e2a658ea7c9a09e93dedb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandAtomicPseudoInsts/expandMBB.cpp @@ -0,0 +1,10 @@ +bool MipsExpandPseudo::expandMBB(MachineBasicBlock &MBB) { + bool Modified = false; + MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end(); + while (MBBI != E) { + MachineBasicBlock::iterator NMBBI = std::next(MBBI); + Modified |= expandMI(MBB, MBBI, NMBBI); + MBBI = NMBBI; + } + return Modified; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandAtomicPseudoInsts/expandMI.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandAtomicPseudoInsts/expandMI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..687810462f4fad5e6d8ad2e77820cb9e1a0aac2e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandAtomicPseudoInsts/expandMI.cpp @@ -0,0 +1,60 @@ +bool MipsExpandPseudo::expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, MachineBasicBlock::iterator &NMBB) { + bool Modified = false; + switch (MBBI->getOpcode()) { + case Mips::ATOMIC_CMP_SWAP_I32_POSTRA: + case Mips::ATOMIC_CMP_SWAP_I64_POSTRA: + return expandAtomicCmpSwap(MBB, MBBI, NMBB); + case Mips::ATOMIC_CMP_SWAP_I8_POSTRA: + case Mips::ATOMIC_CMP_SWAP_I16_POSTRA: + return expandAtomicCmpSwapSubword(MBB, MBBI, NMBB); + case Mips::ATOMIC_SWAP_I8_POSTRA: + case Mips::ATOMIC_SWAP_I16_POSTRA: + case Mips::ATOMIC_LOAD_NAND_I8_POSTRA: + case Mips::ATOMIC_LOAD_NAND_I16_POSTRA: + case Mips::ATOMIC_LOAD_ADD_I8_POSTRA: + case Mips::ATOMIC_LOAD_ADD_I16_POSTRA: + case Mips::ATOMIC_LOAD_SUB_I8_POSTRA: + case Mips::ATOMIC_LOAD_SUB_I16_POSTRA: + case Mips::ATOMIC_LOAD_AND_I8_POSTRA: + case Mips::ATOMIC_LOAD_AND_I16_POSTRA: + case Mips::ATOMIC_LOAD_OR_I8_POSTRA: + case Mips::ATOMIC_LOAD_OR_I16_POSTRA: + case Mips::ATOMIC_LOAD_XOR_I8_POSTRA: + case Mips::ATOMIC_LOAD_XOR_I16_POSTRA: + case Mips::ATOMIC_LOAD_MIN_I8_POSTRA: + case Mips::ATOMIC_LOAD_MIN_I16_POSTRA: + case Mips::ATOMIC_LOAD_MAX_I8_POSTRA: + case Mips::ATOMIC_LOAD_MAX_I16_POSTRA: + case Mips::ATOMIC_LOAD_UMIN_I8_POSTRA: + case Mips::ATOMIC_LOAD_UMIN_I16_POSTRA: + case Mips::ATOMIC_LOAD_UMAX_I8_POSTRA: + case Mips::ATOMIC_LOAD_UMAX_I16_POSTRA: + return expandAtomicBinOpSubword(MBB, MBBI, NMBB); + case Mips::ATOMIC_LOAD_ADD_I32_POSTRA: + case Mips::ATOMIC_LOAD_SUB_I32_POSTRA: + case Mips::ATOMIC_LOAD_AND_I32_POSTRA: + case Mips::ATOMIC_LOAD_OR_I32_POSTRA: + case Mips::ATOMIC_LOAD_XOR_I32_POSTRA: + case Mips::ATOMIC_LOAD_NAND_I32_POSTRA: + case Mips::ATOMIC_SWAP_I32_POSTRA: + case Mips::ATOMIC_LOAD_MIN_I32_POSTRA: + case Mips::ATOMIC_LOAD_MAX_I32_POSTRA: + case Mips::ATOMIC_LOAD_UMIN_I32_POSTRA: + case Mips::ATOMIC_LOAD_UMAX_I32_POSTRA: + return expandAtomicBinOp(MBB, MBBI, NMBB, 4); + case Mips::ATOMIC_LOAD_ADD_I64_POSTRA: + case Mips::ATOMIC_LOAD_SUB_I64_POSTRA: + case Mips::ATOMIC_LOAD_AND_I64_POSTRA: + case Mips::ATOMIC_LOAD_OR_I64_POSTRA: + case Mips::ATOMIC_LOAD_XOR_I64_POSTRA: + case Mips::ATOMIC_LOAD_NAND_I64_POSTRA: + case Mips::ATOMIC_SWAP_I64_POSTRA: + case Mips::ATOMIC_LOAD_MIN_I64_POSTRA: + case Mips::ATOMIC_LOAD_MAX_I64_POSTRA: + case Mips::ATOMIC_LOAD_UMIN_I64_POSTRA: + case Mips::ATOMIC_LOAD_UMAX_I64_POSTRA: + return expandAtomicBinOp(MBB, MBBI, NMBB, 8); + default: + return Modified; + } +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandAtomicPseudoInsts/getPassName.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandAtomicPseudoInsts/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..90c890951e14cd0629d6e0878884a87bb8c79386 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandAtomicPseudoInsts/getPassName.cpp @@ -0,0 +1,3 @@ +StringRef getPassName() const override { + return "Mips Branch Expansion Pass"; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandAtomicPseudoInsts/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandAtomicPseudoInsts/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..62edb7f880dc7a87d5437717d542d7ef50894acb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandAtomicPseudoInsts/runOnMachineFunction.cpp @@ -0,0 +1,21 @@ +bool MipsBranchExpansion::runOnMachineFunction(MachineFunction &MF) { + const TargetMachine &TM = MF.getTarget(); + IsPIC = TM.isPositionIndependent(); + ABI = static_cast(TM).getABI(); + STI = &static_cast(MF.getSubtarget()); + TII = static_cast(STI->getInstrInfo()); + if (IsPIC && ABI.IsO32() && MF.getInfo()->globalBaseRegSet()) + emitGPDisp(MF, TII); + MFp = &MF; + ForceLongBranchFirstPass = ForceLongBranch; + bool longBranchChanged = handlePossibleLongBranch(); + bool forbiddenSlotChanged = handleForbiddenSlot(); + bool Changed = longBranchChanged || forbiddenSlotChanged; + while (forbiddenSlotChanged) { + longBranchChanged = handlePossibleLongBranch(); + if (!longBranchChanged) + break; + forbiddenSlotChanged = handleForbiddenSlot(); + } + return Changed; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandPseudoInsts/ExpandPseudo.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandPseudoInsts/ExpandPseudo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..57aeffd0e2e2e5bb1200734269fc42fb5b8f16c9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandPseudoInsts/ExpandPseudo.cpp @@ -0,0 +1,2 @@ +MipsModuleDAGToDAGISel() : MachineFunctionPass(ID) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandPseudoInsts/createPass.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandPseudoInsts/createPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..66bbc81adf0ef98fff67099cd474312163d2ef95 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandPseudoInsts/createPass.cpp @@ -0,0 +1,3 @@ +llvm::FunctionPass *llvm::createMipsModuleISelDagPass() { + return new MipsModuleDAGToDAGISel(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandPseudoInsts/expandMBB.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandPseudoInsts/expandMBB.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e591da793babbe33581e2a658ea7c9a09e93dedb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandPseudoInsts/expandMBB.cpp @@ -0,0 +1,10 @@ +bool MipsExpandPseudo::expandMBB(MachineBasicBlock &MBB) { + bool Modified = false; + MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end(); + while (MBBI != E) { + MachineBasicBlock::iterator NMBBI = std::next(MBBI); + Modified |= expandMI(MBB, MBBI, NMBBI); + MBBI = NMBBI; + } + return Modified; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandPseudoInsts/expandMI.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandPseudoInsts/expandMI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..687810462f4fad5e6d8ad2e77820cb9e1a0aac2e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandPseudoInsts/expandMI.cpp @@ -0,0 +1,60 @@ +bool MipsExpandPseudo::expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, MachineBasicBlock::iterator &NMBB) { + bool Modified = false; + switch (MBBI->getOpcode()) { + case Mips::ATOMIC_CMP_SWAP_I32_POSTRA: + case Mips::ATOMIC_CMP_SWAP_I64_POSTRA: + return expandAtomicCmpSwap(MBB, MBBI, NMBB); + case Mips::ATOMIC_CMP_SWAP_I8_POSTRA: + case Mips::ATOMIC_CMP_SWAP_I16_POSTRA: + return expandAtomicCmpSwapSubword(MBB, MBBI, NMBB); + case Mips::ATOMIC_SWAP_I8_POSTRA: + case Mips::ATOMIC_SWAP_I16_POSTRA: + case Mips::ATOMIC_LOAD_NAND_I8_POSTRA: + case Mips::ATOMIC_LOAD_NAND_I16_POSTRA: + case Mips::ATOMIC_LOAD_ADD_I8_POSTRA: + case Mips::ATOMIC_LOAD_ADD_I16_POSTRA: + case Mips::ATOMIC_LOAD_SUB_I8_POSTRA: + case Mips::ATOMIC_LOAD_SUB_I16_POSTRA: + case Mips::ATOMIC_LOAD_AND_I8_POSTRA: + case Mips::ATOMIC_LOAD_AND_I16_POSTRA: + case Mips::ATOMIC_LOAD_OR_I8_POSTRA: + case Mips::ATOMIC_LOAD_OR_I16_POSTRA: + case Mips::ATOMIC_LOAD_XOR_I8_POSTRA: + case Mips::ATOMIC_LOAD_XOR_I16_POSTRA: + case Mips::ATOMIC_LOAD_MIN_I8_POSTRA: + case Mips::ATOMIC_LOAD_MIN_I16_POSTRA: + case Mips::ATOMIC_LOAD_MAX_I8_POSTRA: + case Mips::ATOMIC_LOAD_MAX_I16_POSTRA: + case Mips::ATOMIC_LOAD_UMIN_I8_POSTRA: + case Mips::ATOMIC_LOAD_UMIN_I16_POSTRA: + case Mips::ATOMIC_LOAD_UMAX_I8_POSTRA: + case Mips::ATOMIC_LOAD_UMAX_I16_POSTRA: + return expandAtomicBinOpSubword(MBB, MBBI, NMBB); + case Mips::ATOMIC_LOAD_ADD_I32_POSTRA: + case Mips::ATOMIC_LOAD_SUB_I32_POSTRA: + case Mips::ATOMIC_LOAD_AND_I32_POSTRA: + case Mips::ATOMIC_LOAD_OR_I32_POSTRA: + case Mips::ATOMIC_LOAD_XOR_I32_POSTRA: + case Mips::ATOMIC_LOAD_NAND_I32_POSTRA: + case Mips::ATOMIC_SWAP_I32_POSTRA: + case Mips::ATOMIC_LOAD_MIN_I32_POSTRA: + case Mips::ATOMIC_LOAD_MAX_I32_POSTRA: + case Mips::ATOMIC_LOAD_UMIN_I32_POSTRA: + case Mips::ATOMIC_LOAD_UMAX_I32_POSTRA: + return expandAtomicBinOp(MBB, MBBI, NMBB, 4); + case Mips::ATOMIC_LOAD_ADD_I64_POSTRA: + case Mips::ATOMIC_LOAD_SUB_I64_POSTRA: + case Mips::ATOMIC_LOAD_AND_I64_POSTRA: + case Mips::ATOMIC_LOAD_OR_I64_POSTRA: + case Mips::ATOMIC_LOAD_XOR_I64_POSTRA: + case Mips::ATOMIC_LOAD_NAND_I64_POSTRA: + case Mips::ATOMIC_SWAP_I64_POSTRA: + case Mips::ATOMIC_LOAD_MIN_I64_POSTRA: + case Mips::ATOMIC_LOAD_MAX_I64_POSTRA: + case Mips::ATOMIC_LOAD_UMIN_I64_POSTRA: + case Mips::ATOMIC_LOAD_UMAX_I64_POSTRA: + return expandAtomicBinOp(MBB, MBBI, NMBB, 8); + default: + return Modified; + } +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandPseudoInsts/getPassName.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandPseudoInsts/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..90c890951e14cd0629d6e0878884a87bb8c79386 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandPseudoInsts/getPassName.cpp @@ -0,0 +1,3 @@ +StringRef getPassName() const override { + return "Mips Branch Expansion Pass"; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandPseudoInsts/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandPseudoInsts/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..62edb7f880dc7a87d5437717d542d7ef50894acb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandPseudoInsts/runOnMachineFunction.cpp @@ -0,0 +1,21 @@ +bool MipsBranchExpansion::runOnMachineFunction(MachineFunction &MF) { + const TargetMachine &TM = MF.getTarget(); + IsPIC = TM.isPositionIndependent(); + ABI = static_cast(TM).getABI(); + STI = &static_cast(MF.getSubtarget()); + TII = static_cast(STI->getInstrInfo()); + if (IsPIC && ABI.IsO32() && MF.getInfo()->globalBaseRegSet()) + emitGPDisp(MF, TII); + MFp = &MF; + ForceLongBranchFirstPass = ForceLongBranch; + bool longBranchChanged = handlePossibleLongBranch(); + bool forbiddenSlotChanged = handleForbiddenSlot(); + bool Changed = longBranchChanged || forbiddenSlotChanged; + while (forbiddenSlotChanged) { + longBranchChanged = handlePossibleLongBranch(); + if (!longBranchChanged) + break; + forbiddenSlotChanged = handleForbiddenSlot(); + } + return Changed; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandSDMAInsts/ExpandSDMA.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandSDMAInsts/ExpandSDMA.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bfd690f83227cf797a5122869053bdf61b88b080 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandSDMAInsts/ExpandSDMA.cpp @@ -0,0 +1,4 @@ +//zmCorrectzm +RISCVExpandSDMA() : MachineFunctionPass(ID) { + initializeRISCVExpandSDMAPass(*PassRegistry::getPassRegistry()); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandSDMAInsts/ExpandSDMAInsts.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandSDMAInsts/ExpandSDMAInsts.cpp new file mode 100644 index 0000000000000000000000000000000000000000..57aeffd0e2e2e5bb1200734269fc42fb5b8f16c9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandSDMAInsts/ExpandSDMAInsts.cpp @@ -0,0 +1,2 @@ +MipsModuleDAGToDAGISel() : MachineFunctionPass(ID) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandSDMAInsts/createPass.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandSDMAInsts/createPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..66bbc81adf0ef98fff67099cd474312163d2ef95 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandSDMAInsts/createPass.cpp @@ -0,0 +1,3 @@ +llvm::FunctionPass *llvm::createMipsModuleISelDagPass() { + return new MipsModuleDAGToDAGISel(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandSDMAInsts/expandMBB.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandSDMAInsts/expandMBB.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e591da793babbe33581e2a658ea7c9a09e93dedb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandSDMAInsts/expandMBB.cpp @@ -0,0 +1,10 @@ +bool MipsExpandPseudo::expandMBB(MachineBasicBlock &MBB) { + bool Modified = false; + MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end(); + while (MBBI != E) { + MachineBasicBlock::iterator NMBBI = std::next(MBBI); + Modified |= expandMI(MBB, MBBI, NMBBI); + MBBI = NMBBI; + } + return Modified; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandSDMAInsts/expandMI.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandSDMAInsts/expandMI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..687810462f4fad5e6d8ad2e77820cb9e1a0aac2e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandSDMAInsts/expandMI.cpp @@ -0,0 +1,60 @@ +bool MipsExpandPseudo::expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, MachineBasicBlock::iterator &NMBB) { + bool Modified = false; + switch (MBBI->getOpcode()) { + case Mips::ATOMIC_CMP_SWAP_I32_POSTRA: + case Mips::ATOMIC_CMP_SWAP_I64_POSTRA: + return expandAtomicCmpSwap(MBB, MBBI, NMBB); + case Mips::ATOMIC_CMP_SWAP_I8_POSTRA: + case Mips::ATOMIC_CMP_SWAP_I16_POSTRA: + return expandAtomicCmpSwapSubword(MBB, MBBI, NMBB); + case Mips::ATOMIC_SWAP_I8_POSTRA: + case Mips::ATOMIC_SWAP_I16_POSTRA: + case Mips::ATOMIC_LOAD_NAND_I8_POSTRA: + case Mips::ATOMIC_LOAD_NAND_I16_POSTRA: + case Mips::ATOMIC_LOAD_ADD_I8_POSTRA: + case Mips::ATOMIC_LOAD_ADD_I16_POSTRA: + case Mips::ATOMIC_LOAD_SUB_I8_POSTRA: + case Mips::ATOMIC_LOAD_SUB_I16_POSTRA: + case Mips::ATOMIC_LOAD_AND_I8_POSTRA: + case Mips::ATOMIC_LOAD_AND_I16_POSTRA: + case Mips::ATOMIC_LOAD_OR_I8_POSTRA: + case Mips::ATOMIC_LOAD_OR_I16_POSTRA: + case Mips::ATOMIC_LOAD_XOR_I8_POSTRA: + case Mips::ATOMIC_LOAD_XOR_I16_POSTRA: + case Mips::ATOMIC_LOAD_MIN_I8_POSTRA: + case Mips::ATOMIC_LOAD_MIN_I16_POSTRA: + case Mips::ATOMIC_LOAD_MAX_I8_POSTRA: + case Mips::ATOMIC_LOAD_MAX_I16_POSTRA: + case Mips::ATOMIC_LOAD_UMIN_I8_POSTRA: + case Mips::ATOMIC_LOAD_UMIN_I16_POSTRA: + case Mips::ATOMIC_LOAD_UMAX_I8_POSTRA: + case Mips::ATOMIC_LOAD_UMAX_I16_POSTRA: + return expandAtomicBinOpSubword(MBB, MBBI, NMBB); + case Mips::ATOMIC_LOAD_ADD_I32_POSTRA: + case Mips::ATOMIC_LOAD_SUB_I32_POSTRA: + case Mips::ATOMIC_LOAD_AND_I32_POSTRA: + case Mips::ATOMIC_LOAD_OR_I32_POSTRA: + case Mips::ATOMIC_LOAD_XOR_I32_POSTRA: + case Mips::ATOMIC_LOAD_NAND_I32_POSTRA: + case Mips::ATOMIC_SWAP_I32_POSTRA: + case Mips::ATOMIC_LOAD_MIN_I32_POSTRA: + case Mips::ATOMIC_LOAD_MAX_I32_POSTRA: + case Mips::ATOMIC_LOAD_UMIN_I32_POSTRA: + case Mips::ATOMIC_LOAD_UMAX_I32_POSTRA: + return expandAtomicBinOp(MBB, MBBI, NMBB, 4); + case Mips::ATOMIC_LOAD_ADD_I64_POSTRA: + case Mips::ATOMIC_LOAD_SUB_I64_POSTRA: + case Mips::ATOMIC_LOAD_AND_I64_POSTRA: + case Mips::ATOMIC_LOAD_OR_I64_POSTRA: + case Mips::ATOMIC_LOAD_XOR_I64_POSTRA: + case Mips::ATOMIC_LOAD_NAND_I64_POSTRA: + case Mips::ATOMIC_SWAP_I64_POSTRA: + case Mips::ATOMIC_LOAD_MIN_I64_POSTRA: + case Mips::ATOMIC_LOAD_MAX_I64_POSTRA: + case Mips::ATOMIC_LOAD_UMIN_I64_POSTRA: + case Mips::ATOMIC_LOAD_UMAX_I64_POSTRA: + return expandAtomicBinOp(MBB, MBBI, NMBB, 8); + default: + return Modified; + } +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandSDMAInsts/getPassName.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandSDMAInsts/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..90c890951e14cd0629d6e0878884a87bb8c79386 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandSDMAInsts/getPassName.cpp @@ -0,0 +1,3 @@ +StringRef getPassName() const override { + return "Mips Branch Expansion Pass"; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandSDMAInsts/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandSDMAInsts/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..62edb7f880dc7a87d5437717d542d7ef50894acb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandSDMAInsts/runOnMachineFunction.cpp @@ -0,0 +1,21 @@ +bool MipsBranchExpansion::runOnMachineFunction(MachineFunction &MF) { + const TargetMachine &TM = MF.getTarget(); + IsPIC = TM.isPositionIndependent(); + ABI = static_cast(TM).getABI(); + STI = &static_cast(MF.getSubtarget()); + TII = static_cast(STI->getInstrInfo()); + if (IsPIC && ABI.IsO32() && MF.getInfo()->globalBaseRegSet()) + emitGPDisp(MF, TII); + MFp = &MF; + ForceLongBranchFirstPass = ForceLongBranch; + bool longBranchChanged = handlePossibleLongBranch(); + bool forbiddenSlotChanged = handleForbiddenSlot(); + bool Changed = longBranchChanged || forbiddenSlotChanged; + while (forbiddenSlotChanged) { + longBranchChanged = handlePossibleLongBranch(); + if (!longBranchChanged) + break; + forbiddenSlotChanged = handleForbiddenSlot(); + } + return Changed; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandSSRInsts/ExpandSSR.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandSSRInsts/ExpandSSR.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fa757aa1fd9eaedaca391e3d7e85b7cbdce96b27 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandSSRInsts/ExpandSSR.cpp @@ -0,0 +1,4 @@ +//zmCorrectzm +RISCVExpandSSR() : MachineFunctionPass(ID) { + initializeRISCVExpandSSRPass(*PassRegistry::getPassRegistry()); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandSSRInsts/ExpandSSRInsts.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandSSRInsts/ExpandSSRInsts.cpp new file mode 100644 index 0000000000000000000000000000000000000000..57aeffd0e2e2e5bb1200734269fc42fb5b8f16c9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandSSRInsts/ExpandSSRInsts.cpp @@ -0,0 +1,2 @@ +MipsModuleDAGToDAGISel() : MachineFunctionPass(ID) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandSSRInsts/createPass.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandSSRInsts/createPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..66bbc81adf0ef98fff67099cd474312163d2ef95 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandSSRInsts/createPass.cpp @@ -0,0 +1,3 @@ +llvm::FunctionPass *llvm::createMipsModuleISelDagPass() { + return new MipsModuleDAGToDAGISel(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandSSRInsts/expandMBB.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandSSRInsts/expandMBB.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e591da793babbe33581e2a658ea7c9a09e93dedb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandSSRInsts/expandMBB.cpp @@ -0,0 +1,10 @@ +bool MipsExpandPseudo::expandMBB(MachineBasicBlock &MBB) { + bool Modified = false; + MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end(); + while (MBBI != E) { + MachineBasicBlock::iterator NMBBI = std::next(MBBI); + Modified |= expandMI(MBB, MBBI, NMBBI); + MBBI = NMBBI; + } + return Modified; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandSSRInsts/expandMI.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandSSRInsts/expandMI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..687810462f4fad5e6d8ad2e77820cb9e1a0aac2e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandSSRInsts/expandMI.cpp @@ -0,0 +1,60 @@ +bool MipsExpandPseudo::expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, MachineBasicBlock::iterator &NMBB) { + bool Modified = false; + switch (MBBI->getOpcode()) { + case Mips::ATOMIC_CMP_SWAP_I32_POSTRA: + case Mips::ATOMIC_CMP_SWAP_I64_POSTRA: + return expandAtomicCmpSwap(MBB, MBBI, NMBB); + case Mips::ATOMIC_CMP_SWAP_I8_POSTRA: + case Mips::ATOMIC_CMP_SWAP_I16_POSTRA: + return expandAtomicCmpSwapSubword(MBB, MBBI, NMBB); + case Mips::ATOMIC_SWAP_I8_POSTRA: + case Mips::ATOMIC_SWAP_I16_POSTRA: + case Mips::ATOMIC_LOAD_NAND_I8_POSTRA: + case Mips::ATOMIC_LOAD_NAND_I16_POSTRA: + case Mips::ATOMIC_LOAD_ADD_I8_POSTRA: + case Mips::ATOMIC_LOAD_ADD_I16_POSTRA: + case Mips::ATOMIC_LOAD_SUB_I8_POSTRA: + case Mips::ATOMIC_LOAD_SUB_I16_POSTRA: + case Mips::ATOMIC_LOAD_AND_I8_POSTRA: + case Mips::ATOMIC_LOAD_AND_I16_POSTRA: + case Mips::ATOMIC_LOAD_OR_I8_POSTRA: + case Mips::ATOMIC_LOAD_OR_I16_POSTRA: + case Mips::ATOMIC_LOAD_XOR_I8_POSTRA: + case Mips::ATOMIC_LOAD_XOR_I16_POSTRA: + case Mips::ATOMIC_LOAD_MIN_I8_POSTRA: + case Mips::ATOMIC_LOAD_MIN_I16_POSTRA: + case Mips::ATOMIC_LOAD_MAX_I8_POSTRA: + case Mips::ATOMIC_LOAD_MAX_I16_POSTRA: + case Mips::ATOMIC_LOAD_UMIN_I8_POSTRA: + case Mips::ATOMIC_LOAD_UMIN_I16_POSTRA: + case Mips::ATOMIC_LOAD_UMAX_I8_POSTRA: + case Mips::ATOMIC_LOAD_UMAX_I16_POSTRA: + return expandAtomicBinOpSubword(MBB, MBBI, NMBB); + case Mips::ATOMIC_LOAD_ADD_I32_POSTRA: + case Mips::ATOMIC_LOAD_SUB_I32_POSTRA: + case Mips::ATOMIC_LOAD_AND_I32_POSTRA: + case Mips::ATOMIC_LOAD_OR_I32_POSTRA: + case Mips::ATOMIC_LOAD_XOR_I32_POSTRA: + case Mips::ATOMIC_LOAD_NAND_I32_POSTRA: + case Mips::ATOMIC_SWAP_I32_POSTRA: + case Mips::ATOMIC_LOAD_MIN_I32_POSTRA: + case Mips::ATOMIC_LOAD_MAX_I32_POSTRA: + case Mips::ATOMIC_LOAD_UMIN_I32_POSTRA: + case Mips::ATOMIC_LOAD_UMAX_I32_POSTRA: + return expandAtomicBinOp(MBB, MBBI, NMBB, 4); + case Mips::ATOMIC_LOAD_ADD_I64_POSTRA: + case Mips::ATOMIC_LOAD_SUB_I64_POSTRA: + case Mips::ATOMIC_LOAD_AND_I64_POSTRA: + case Mips::ATOMIC_LOAD_OR_I64_POSTRA: + case Mips::ATOMIC_LOAD_XOR_I64_POSTRA: + case Mips::ATOMIC_LOAD_NAND_I64_POSTRA: + case Mips::ATOMIC_SWAP_I64_POSTRA: + case Mips::ATOMIC_LOAD_MIN_I64_POSTRA: + case Mips::ATOMIC_LOAD_MAX_I64_POSTRA: + case Mips::ATOMIC_LOAD_UMIN_I64_POSTRA: + case Mips::ATOMIC_LOAD_UMAX_I64_POSTRA: + return expandAtomicBinOp(MBB, MBBI, NMBB, 8); + default: + return Modified; + } +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandSSRInsts/getPassName.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandSSRInsts/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..90c890951e14cd0629d6e0878884a87bb8c79386 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandSSRInsts/getPassName.cpp @@ -0,0 +1,3 @@ +StringRef getPassName() const override { + return "Mips Branch Expansion Pass"; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandSSRInsts/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandSSRInsts/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..62edb7f880dc7a87d5437717d542d7ef50894acb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/ExpandSSRInsts/runOnMachineFunction.cpp @@ -0,0 +1,21 @@ +bool MipsBranchExpansion::runOnMachineFunction(MachineFunction &MF) { + const TargetMachine &TM = MF.getTarget(); + IsPIC = TM.isPositionIndependent(); + ABI = static_cast(TM).getABI(); + STI = &static_cast(MF.getSubtarget()); + TII = static_cast(STI->getInstrInfo()); + if (IsPIC && ABI.IsO32() && MF.getInfo()->globalBaseRegSet()) + emitGPDisp(MF, TII); + MFp = &MF; + ForceLongBranchFirstPass = ForceLongBranch; + bool longBranchChanged = handlePossibleLongBranch(); + bool forbiddenSlotChanged = handleForbiddenSlot(); + bool Changed = longBranchChanged || forbiddenSlotChanged; + while (forbiddenSlotChanged) { + longBranchChanged = handlePossibleLongBranch(); + if (!longBranchChanged) + break; + forbiddenSlotChanged = handleForbiddenSlot(); + } + return Changed; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/MergeBaseOffset/MergeBaseOffsetOpt.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/MergeBaseOffset/MergeBaseOffsetOpt.cpp new file mode 100644 index 0000000000000000000000000000000000000000..57aeffd0e2e2e5bb1200734269fc42fb5b8f16c9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/MergeBaseOffset/MergeBaseOffsetOpt.cpp @@ -0,0 +1,2 @@ +MipsModuleDAGToDAGISel() : MachineFunctionPass(ID) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/MergeBaseOffset/createPass.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/MergeBaseOffset/createPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..66bbc81adf0ef98fff67099cd474312163d2ef95 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/MergeBaseOffset/createPass.cpp @@ -0,0 +1,3 @@ +llvm::FunctionPass *llvm::createMipsModuleISelDagPass() { + return new MipsModuleDAGToDAGISel(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/MergeBaseOffset/getPassName.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/MergeBaseOffset/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..90c890951e14cd0629d6e0878884a87bb8c79386 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/MergeBaseOffset/getPassName.cpp @@ -0,0 +1,3 @@ +StringRef getPassName() const override { + return "Mips Branch Expansion Pass"; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/MergeBaseOffset/getRequiredProperties.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/MergeBaseOffset/getRequiredProperties.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c75653867ef66dd435b2ea7205493d823d8fbb30 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/MergeBaseOffset/getRequiredProperties.cpp @@ -0,0 +1,3 @@ +MachineFunctionProperties getRequiredProperties() const override { + return MachineFunctionProperties().set(MachineFunctionProperties::Property::NoVRegs); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/MergeBaseOffset/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/MergeBaseOffset/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..66c7b3864fbc88610507a3b57469c33cbe7067a8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/MergeBaseOffset/runOnMachineFunction.cpp @@ -0,0 +1,21 @@ +bool MipsBranchExpansion::runOnMachineFunction(MachineFunction &MF) { + const TargetMachine &TM = MF.getTarget(); + IsPIC = TM.isPositionIndependent(); + ABI = static_cast(TM).getABI(); + STI = &static_cast(MF.getSubtarget()); + TII = static_cast(STI->getInstrInfo()); + if (IsPIC && ABI.IsO32() && MF.getInfo()->globalBaseRegSet()) + emitGPDisp(MF, TII); + MFp = &MF; + ForceLongBranchFirstPass = ForceLongBranch; + bool longBranchChanged = handlePossibleLongBranch(); + bool forbiddenSlotChanged = handleForbiddenSlot(); + bool Changed = longBranchChanged || forbiddenSlotChanged; + while (forbiddenSlotChanged) { + longBranchChanged = handlePossibleLongBranch(); + if (!longBranchChanged) + break; + forbiddenSlotChanged = handleForbiddenSlot(); + } + return Changed; +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPFixupHwLoops/FixupHwLoops.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPFixupHwLoops/FixupHwLoops.cpp new file mode 100644 index 0000000000000000000000000000000000000000..57aeffd0e2e2e5bb1200734269fc42fb5b8f16c9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPFixupHwLoops/FixupHwLoops.cpp @@ -0,0 +1,2 @@ +MipsModuleDAGToDAGISel() : MachineFunctionPass(ID) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPFixupHwLoops/PULPFixupHwLoops.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPFixupHwLoops/PULPFixupHwLoops.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7c17fd5a279439a187f60893c6e3615c047d045e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPFixupHwLoops/PULPFixupHwLoops.cpp @@ -0,0 +1,4 @@ +//zmCorrectzm +PULPFixupHwLoops() : MachineFunctionPass(ID) { + initializePULPFixupHwLoopsPass(*PassRegistry::getPassRegistry()); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPFixupHwLoops/createPULPFixupHwLoops.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPFixupHwLoops/createPULPFixupHwLoops.cpp new file mode 100644 index 0000000000000000000000000000000000000000..66bbc81adf0ef98fff67099cd474312163d2ef95 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPFixupHwLoops/createPULPFixupHwLoops.cpp @@ -0,0 +1,3 @@ +llvm::FunctionPass *llvm::createMipsModuleISelDagPass() { + return new MipsModuleDAGToDAGISel(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPFixupHwLoops/createPass.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPFixupHwLoops/createPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b12c744298f9d869e8fc2ee963c1702dfb79d52e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPFixupHwLoops/createPass.cpp @@ -0,0 +1,4 @@ +//zmcorrectzm +FunctionPass *llvm::createPULPFixupHwLoops() { + return new PULPFixupHwLoops(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPFixupHwLoops/getAnalysisUsage.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPFixupHwLoops/getAnalysisUsage.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3f3e70065dbb1b3bcc423b768c1c4c1713ba4da5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPFixupHwLoops/getAnalysisUsage.cpp @@ -0,0 +1,4 @@ +void getAnalysisUsage(AnalysisUsage &AU) const override { + AU.addRequired(); + MachineFunctionPass::getAnalysisUsage(AU); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPFixupHwLoops/getPassName.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPFixupHwLoops/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..90c890951e14cd0629d6e0878884a87bb8c79386 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPFixupHwLoops/getPassName.cpp @@ -0,0 +1,3 @@ +StringRef getPassName() const override { + return "Mips Branch Expansion Pass"; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPFixupHwLoops/getRequiredProperties.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPFixupHwLoops/getRequiredProperties.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c75653867ef66dd435b2ea7205493d823d8fbb30 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPFixupHwLoops/getRequiredProperties.cpp @@ -0,0 +1,3 @@ +MachineFunctionProperties getRequiredProperties() const override { + return MachineFunctionProperties().set(MachineFunctionProperties::Property::NoVRegs); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPFixupHwLoops/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPFixupHwLoops/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..62edb7f880dc7a87d5437717d542d7ef50894acb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPFixupHwLoops/runOnMachineFunction.cpp @@ -0,0 +1,21 @@ +bool MipsBranchExpansion::runOnMachineFunction(MachineFunction &MF) { + const TargetMachine &TM = MF.getTarget(); + IsPIC = TM.isPositionIndependent(); + ABI = static_cast(TM).getABI(); + STI = &static_cast(MF.getSubtarget()); + TII = static_cast(STI->getInstrInfo()); + if (IsPIC && ABI.IsO32() && MF.getInfo()->globalBaseRegSet()) + emitGPDisp(MF, TII); + MFp = &MF; + ForceLongBranchFirstPass = ForceLongBranch; + bool longBranchChanged = handlePossibleLongBranch(); + bool forbiddenSlotChanged = handleForbiddenSlot(); + bool Changed = longBranchChanged || forbiddenSlotChanged; + while (forbiddenSlotChanged) { + longBranchChanged = handlePossibleLongBranch(); + if (!longBranchChanged) + break; + forbiddenSlotChanged = handleForbiddenSlot(); + } + return Changed; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/CountValue.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/CountValue.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/CountValue.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/HardWareLoops.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/HardWareLoops.cpp new file mode 100644 index 0000000000000000000000000000000000000000..58d2e084d50b83358610cdea163f6b7531686fa5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/HardWareLoops.cpp @@ -0,0 +1,3 @@ +PULPHardwareLoops() : MachineFunctionPass(ID) { + initializePULPHardwareLoopsPass(*PassRegistry::getPassRegistry()); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/PULPHardwareLoops.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/PULPHardwareLoops.cpp new file mode 100644 index 0000000000000000000000000000000000000000..57aeffd0e2e2e5bb1200734269fc42fb5b8f16c9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/PULPHardwareLoops.cpp @@ -0,0 +1,2 @@ +MipsModuleDAGToDAGISel() : MachineFunctionPass(ID) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/checkForImmediate.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/checkForImmediate.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/checkForImmediate.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/containsInvalidInstruction.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/containsInvalidInstruction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/containsInvalidInstruction.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/convertToHardwareLoop.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/convertToHardwareLoop.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/convertToHardwareLoop.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/createPULPHardwareLoops.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/createPULPHardwareLoops.cpp new file mode 100644 index 0000000000000000000000000000000000000000..66bbc81adf0ef98fff67099cd474312163d2ef95 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/createPULPHardwareLoops.cpp @@ -0,0 +1,3 @@ +llvm::FunctionPass *llvm::createMipsModuleISelDagPass() { + return new MipsModuleDAGToDAGISel(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/createPass.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/createPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..863945051646c9f1c5aa4d13b92798567cf74358 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/createPass.cpp @@ -0,0 +1,4 @@ +//zmcorrectzm +FunctionPass *llvm::createPULPHardwareLoops() { + return new PULPHardwareLoops(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/enumCountValueType.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/enumCountValueType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/enumCountValueType.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/enumKind.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/enumKind.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/enumKind.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/findInductionRegister.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/findInductionRegister.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d24252a436720a3ccdecb69c990fff58341ff97c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/findInductionRegister.cpp @@ -0,0 +1,2 @@ +None + diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/getAnalysisUsage.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/getAnalysisUsage.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3f3e70065dbb1b3bcc423b768c1c4c1713ba4da5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/getAnalysisUsage.cpp @@ -0,0 +1,4 @@ +void getAnalysisUsage(AnalysisUsage &AU) const override { + AU.addRequired(); + MachineFunctionPass::getAnalysisUsage(AU); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/getComparisonKind.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/getComparisonKind.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/getComparisonKind.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/getImm.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/getImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/getImm.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/getLoopTripCount.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/getLoopTripCount.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/getLoopTripCount.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/getNegatedComparison.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/getNegatedComparison.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/getNegatedComparison.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/getPassName.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..90c890951e14cd0629d6e0878884a87bb8c79386 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/getPassName.cpp @@ -0,0 +1,3 @@ +StringRef getPassName() const override { + return "Mips Branch Expansion Pass"; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/getReg.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/getReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1dab4ca6570e40abe996369fb6a7b1dfa1b32b52 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/getReg.cpp @@ -0,0 +1,4 @@ +unsigned getReg() const { + assert(isRegBase() && "Invalid base register access!"); + return Base.Reg; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/getSubReg.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/getSubReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1dab4ca6570e40abe996369fb6a7b1dfa1b32b52 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/getSubReg.cpp @@ -0,0 +1,4 @@ +unsigned getReg() const { + assert(isRegBase() && "Invalid base register access!"); + return Base.Reg; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/getSwappedComparison.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/getSwappedComparison.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/getSwappedComparison.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/isDead.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/isDead.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/isDead.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/isImm.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/isImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e028f1acc0adc990eaaa7cd33412bb583aa50693 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/isImm.cpp @@ -0,0 +1,3 @@ +bool isImm() const override { + return Kind == k_Immediate; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/isInvalidLoopOperation.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/isInvalidLoopOperation.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/isInvalidLoopOperation.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/isLoopFeeder.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/isLoopFeeder.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/isLoopFeeder.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/isReg.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/isReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d367df6e72a1916e56ea13412e32c693d1dd119b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/isReg.cpp @@ -0,0 +1,3 @@ +bool isReg() const override { + return isGPRAsmReg() && RegIdx.Index == 0; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/isSigned.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/isSigned.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/isSigned.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/isUnsigned.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/isUnsigned.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/isUnsigned.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/loopCountMayWrapOrUnderFlow.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/loopCountMayWrapOrUnderFlow.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/loopCountMayWrapOrUnderFlow.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/phiMayWrapOrUnderflow.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/phiMayWrapOrUnderflow.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/phiMayWrapOrUnderflow.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/print.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/print.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/print.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/removeIfDead.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/removeIfDead.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/removeIfDead.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..62edb7f880dc7a87d5437717d542d7ef50894acb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/runOnMachineFunction.cpp @@ -0,0 +1,21 @@ +bool MipsBranchExpansion::runOnMachineFunction(MachineFunction &MF) { + const TargetMachine &TM = MF.getTarget(); + IsPIC = TM.isPositionIndependent(); + ABI = static_cast(TM).getABI(); + STI = &static_cast(MF.getSubtarget()); + TII = static_cast(STI->getInstrInfo()); + if (IsPIC && ABI.IsO32() && MF.getInfo()->globalBaseRegSet()) + emitGPDisp(MF, TII); + MFp = &MF; + ForceLongBranchFirstPass = ForceLongBranch; + bool longBranchChanged = handlePossibleLongBranch(); + bool forbiddenSlotChanged = handleForbiddenSlot(); + bool Changed = longBranchChanged || forbiddenSlotChanged; + while (forbiddenSlotChanged) { + longBranchChanged = handlePossibleLongBranch(); + if (!longBranchChanged) + break; + forbiddenSlotChanged = handleForbiddenSlot(); + } + return Changed; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/unionValues.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/unionValues.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/PULPHardWareLoops/unionValues.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/CountValue.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/CountValue.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/CountValue.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/FrepLoop.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/FrepLoop.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/FrepLoop.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/FrepLoopsPass.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/FrepLoopsPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a57ba5865dbb3f7dd0933b0843eda5372b9d3171 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/FrepLoopsPass.cpp @@ -0,0 +1,4 @@ +//zmCorrectzm +SNITCHFrepLoops() : MachineFunctionPass(ID) { + initializeSNITCHFrepLoopsPass(*PassRegistry::getPassRegistry()); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/SNITCHFrepLoops.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/SNITCHFrepLoops.cpp new file mode 100644 index 0000000000000000000000000000000000000000..57aeffd0e2e2e5bb1200734269fc42fb5b8f16c9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/SNITCHFrepLoops.cpp @@ -0,0 +1,2 @@ +MipsModuleDAGToDAGISel() : MachineFunctionPass(ID) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/checkForImmediate.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/checkForImmediate.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/checkForImmediate.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/containsInvalidInstruction.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/containsInvalidInstruction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/containsInvalidInstruction.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/convertToHardwareLoop.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/convertToHardwareLoop.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/convertToHardwareLoop.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/createPass.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/createPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..13afedbcaa1d50da9013e6346335c6c9abec58a3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/createPass.cpp @@ -0,0 +1,4 @@ +//zmcorrectzm +FunctionPass *createSNITCHFrepLoopsPass() { + return new SNITCHFrepLoops(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/createSNITCHFrepLoopsPass.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/createSNITCHFrepLoopsPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..66bbc81adf0ef98fff67099cd474312163d2ef95 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/createSNITCHFrepLoopsPass.cpp @@ -0,0 +1,3 @@ +llvm::FunctionPass *llvm::createMipsModuleISelDagPass() { + return new MipsModuleDAGToDAGISel(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/enumCountValueType.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/enumCountValueType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/enumCountValueType.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/enumKind.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/enumKind.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/enumKind.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/findBranchInstruction.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/findBranchInstruction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/findBranchInstruction.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/findInductionRegister.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/findInductionRegister.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/findInductionRegister.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/getAnalysisUsage.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/getAnalysisUsage.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/getComparisonKind.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/getComparisonKind.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/getComparisonKind.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/getImm.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/getImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/getImm.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/getLoopTripCount.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/getLoopTripCount.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/getLoopTripCount.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/getNegatedComparison.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/getNegatedComparison.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/getNegatedComparison.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/getPassName.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..90c890951e14cd0629d6e0878884a87bb8c79386 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/getPassName.cpp @@ -0,0 +1,3 @@ +StringRef getPassName() const override { + return "Mips Branch Expansion Pass"; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/getReg.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/getReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1dab4ca6570e40abe996369fb6a7b1dfa1b32b52 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/getReg.cpp @@ -0,0 +1,4 @@ +unsigned getReg() const { + assert(isRegBase() && "Invalid base register access!"); + return Base.Reg; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/getSubReg.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/getSubReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1dab4ca6570e40abe996369fb6a7b1dfa1b32b52 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/getSubReg.cpp @@ -0,0 +1,4 @@ +unsigned getReg() const { + assert(isRegBase() && "Invalid base register access!"); + return Base.Reg; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/getSwappedComparison.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/getSwappedComparison.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/getSwappedComparison.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/isDead.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/isDead.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/isDead.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/isImm.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/isImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e028f1acc0adc990eaaa7cd33412bb583aa50693 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/isImm.cpp @@ -0,0 +1,3 @@ +bool isImm() const override { + return Kind == k_Immediate; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/isInvalidLoopOperation.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/isInvalidLoopOperation.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/isInvalidLoopOperation.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/isReg.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/isReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d367df6e72a1916e56ea13412e32c693d1dd119b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/isReg.cpp @@ -0,0 +1,3 @@ +bool isReg() const override { + return isGPRAsmReg() && RegIdx.Index == 0; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/isSigned.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/isSigned.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/isSigned.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/isUnsigned.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/isUnsigned.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/isUnsigned.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/print.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/print.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/print.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/removeIfDead.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/removeIfDead.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/removeIfDead.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..62edb7f880dc7a87d5437717d542d7ef50894acb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/runOnMachineFunction.cpp @@ -0,0 +1,21 @@ +bool MipsBranchExpansion::runOnMachineFunction(MachineFunction &MF) { + const TargetMachine &TM = MF.getTarget(); + IsPIC = TM.isPositionIndependent(); + ABI = static_cast(TM).getABI(); + STI = &static_cast(MF.getSubtarget()); + TII = static_cast(STI->getInstrInfo()); + if (IsPIC && ABI.IsO32() && MF.getInfo()->globalBaseRegSet()) + emitGPDisp(MF, TII); + MFp = &MF; + ForceLongBranchFirstPass = ForceLongBranch; + bool longBranchChanged = handlePossibleLongBranch(); + bool forbiddenSlotChanged = handleForbiddenSlot(); + bool Changed = longBranchChanged || forbiddenSlotChanged; + while (forbiddenSlotChanged) { + longBranchChanged = handlePossibleLongBranch(); + if (!longBranchChanged) + break; + forbiddenSlotChanged = handleForbiddenSlot(); + } + return Changed; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/unionValues.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/unionValues.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Optimization/SNITCHFrepLoops/unionValues.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/InstrInfo.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/InstrInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..89ef265a73d366c9fe3f2c94f235af727e8b5dcd --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/InstrInfo.cpp @@ -0,0 +1,2 @@ +MipsInstrInfo::MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBr) : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP), Subtarget(STI), UncondBrOpc(UncondBr) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/analyzeBranch.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/analyzeBranch.cpp new file mode 100644 index 0000000000000000000000000000000000000000..492da016718b9b6f818e0f34a01596e175c6affb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/analyzeBranch.cpp @@ -0,0 +1,5 @@ +bool MipsInstrInfo::analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl &Cond, bool AllowModify) const { + SmallVector BranchInstrs; + BranchType BT = analyzeBranch(MBB, TBB, FBB, Cond, AllowModify, BranchInstrs); + return (BT == BT_None) || (BT == BT_Indirect); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/areMemAccessesTriviallyDisjoint.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/areMemAccessesTriviallyDisjoint.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d24252a436720a3ccdecb69c990fff58341ff97c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/areMemAccessesTriviallyDisjoint.cpp @@ -0,0 +1,2 @@ +None + diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/buildOutlinedFrame.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/buildOutlinedFrame.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/buildOutlinedFrame.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/copyPhysReg.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/copyPhysReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a5fc2c1a67373b362485a1ac80c16cbe10ca55a9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/copyPhysReg.cpp @@ -0,0 +1,92 @@ +void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const { + unsigned Opc = 0, ZeroReg = 0; + bool isMicroMips = Subtarget.inMicroMipsMode(); + if (Mips::GPR32RegClass.contains(DestReg)) { + if (Mips::GPR32RegClass.contains(SrcReg)) { + if (isMicroMips) + Opc = Mips::MOVE16_MM; + else + Opc = Mips::OR, ZeroReg = Mips::ZERO; + } + else if (Mips::CCRRegClass.contains(SrcReg)) + Opc = Mips::CFC1; + else if (Mips::FGR32RegClass.contains(SrcReg)) + Opc = Mips::MFC1; + else if (Mips::HI32RegClass.contains(SrcReg)) { + Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI; + SrcReg = 0; + } + else if (Mips::LO32RegClass.contains(SrcReg)) { + Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO; + SrcReg = 0; + } + else if (Mips::HI32DSPRegClass.contains(SrcReg)) + Opc = Mips::MFHI_DSP; + else if (Mips::LO32DSPRegClass.contains(SrcReg)) + Opc = Mips::MFLO_DSP; + else if (Mips::DSPCCRegClass.contains(SrcReg)) { + BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4).addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc)); + return; + } + else if (Mips::MSACtrlRegClass.contains(SrcReg)) + Opc = Mips::CFCMSA; + } + else if (Mips::GPR32RegClass.contains(SrcReg)) { + if (Mips::CCRRegClass.contains(DestReg)) + Opc = Mips::CTC1; + else if (Mips::FGR32RegClass.contains(DestReg)) + Opc = Mips::MTC1; + else if (Mips::HI32RegClass.contains(DestReg)) + Opc = Mips::MTHI, DestReg = 0; + else if (Mips::LO32RegClass.contains(DestReg)) + Opc = Mips::MTLO, DestReg = 0; + else if (Mips::HI32DSPRegClass.contains(DestReg)) + Opc = Mips::MTHI_DSP; + else if (Mips::LO32DSPRegClass.contains(DestReg)) + Opc = Mips::MTLO_DSP; + else if (Mips::DSPCCRegClass.contains(DestReg)) { + BuildMI(MBB, I, DL, get(Mips::WRDSP)).addReg(SrcReg, getKillRegState(KillSrc)).addImm(1 << 4).addReg(DestReg, RegState::ImplicitDefine); + return; + } + else if (Mips::MSACtrlRegClass.contains(DestReg)) { + BuildMI(MBB, I, DL, get(Mips::CTCMSA)).addReg(DestReg).addReg(SrcReg, getKillRegState(KillSrc)); + return; + } + } + else if (Mips::FGR32RegClass.contains(DestReg, SrcReg)) + Opc = Mips::FMOV_S; + else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg)) + Opc = Mips::FMOV_D32; + else if (Mips::FGR64RegClass.contains(DestReg, SrcReg)) + Opc = Mips::FMOV_D64; + else if (Mips::GPR64RegClass.contains(DestReg)) { + if (Mips::GPR64RegClass.contains(SrcReg)) + Opc = Mips::OR64, ZeroReg = Mips::ZERO_64; + else if (Mips::HI64RegClass.contains(SrcReg)) + Opc = Mips::MFHI64, SrcReg = 0; + else if (Mips::LO64RegClass.contains(SrcReg)) + Opc = Mips::MFLO64, SrcReg = 0; + else if (Mips::FGR64RegClass.contains(SrcReg)) + Opc = Mips::DMFC1; + } + else if (Mips::GPR64RegClass.contains(SrcReg)) { + if (Mips::HI64RegClass.contains(DestReg)) + Opc = Mips::MTHI64, DestReg = 0; + else if (Mips::LO64RegClass.contains(DestReg)) + Opc = Mips::MTLO64, DestReg = 0; + else if (Mips::FGR64RegClass.contains(DestReg)) + Opc = Mips::DMTC1; + } + else if (Mips::MSA128BRegClass.contains(DestReg)) { + if (Mips::MSA128BRegClass.contains(SrcReg)) + Opc = Mips::MOVE_V; + } + assert(Opc && "Cannot copy registers"); + MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc)); + if (DestReg) + MIB.addReg(DestReg, RegState::Define); + if (SrcReg) + MIB.addReg(SrcReg, getKillRegState(KillSrc)); + if (ZeroReg) + MIB.addReg(ZeroReg); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/decomposeMachineOperandsTargetFlags.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/decomposeMachineOperandsTargetFlags.cpp new file mode 100644 index 0000000000000000000000000000000000000000..597c42a46327b8073dd001d24e93dda00be2781e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/decomposeMachineOperandsTargetFlags.cpp @@ -0,0 +1,3 @@ +std::pair MipsInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const { + return std::make_pair(TF, 0u); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/getBranchDestBlock.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/getBranchDestBlock.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/getBranchDestBlock.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/getInstSizeInBytes.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/getInstSizeInBytes.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/getInstSizeInBytes.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/getMemOperandWithOffsetWidth.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/getMemOperandWithOffsetWidth.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/getMemOperandWithOffsetWidth.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/getOutliningCandidateInfo.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/getOutliningCandidateInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d24252a436720a3ccdecb69c990fff58341ff97c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/getOutliningCandidateInfo.cpp @@ -0,0 +1,2 @@ +None + diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/getOutliningType.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/getOutliningType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/getOutliningType.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/getSerializableDirectMachineOperandTargetFlags.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/getSerializableDirectMachineOperandTargetFlags.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d6a73118f0d98feb321a30df73ba2e80992df4ab --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/getSerializableDirectMachineOperandTargetFlags.cpp @@ -0,0 +1,5 @@ +ArrayRef> MipsInstrInfo::getSerializableDirectMachineOperandTargetFlags() const { + using namespace MipsII; + static const std::pair Flags[] = {{MO_GOT, "mips-got"}, {MO_GOT_CALL, "mips-got-call"}, {MO_GPREL, "mips-gprel"}, {MO_ABS_HI, "mips-abs-hi"}, {MO_ABS_LO, "mips-abs-lo"}, {MO_TLSGD, "mips-tlsgd"}, {MO_TLSLDM, "mips-tlsldm"}, {MO_DTPREL_HI, "mips-dtprel-hi"}, {MO_DTPREL_LO, "mips-dtprel-lo"}, {MO_GOTTPREL, "mips-gottprel"}, {MO_TPREL_HI, "mips-tprel-hi"}, {MO_TPREL_LO, "mips-tprel-lo"}, {MO_GPOFF_HI, "mips-gpoff-hi"}, {MO_GPOFF_LO, "mips-gpoff-lo"}, {MO_GOT_DISP, "mips-got-disp"}, {MO_GOT_PAGE, "mips-got-page"}, {MO_GOT_OFST, "mips-got-ofst"}, {MO_HIGHER, "mips-higher"}, {MO_HIGHEST, "mips-highest"}, {MO_GOT_HI16, "mips-got-hi16"}, {MO_GOT_LO16, "mips-got-lo16"}, {MO_CALL_HI16, "mips-call-hi16"}, {MO_CALL_LO16, "mips-call-lo16"}, {MO_JALR, "mips-jalr"}}; + return makeArrayRef(Flags); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/insertBranch.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/insertBranch.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7aadd2573c6e9b7e1703c86ae78cd84d2f384d34 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/insertBranch.cpp @@ -0,0 +1,15 @@ +unsigned MipsInstrInfo::insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, const DebugLoc &DL, int *BytesAdded) const { + assert(TBB && "insertBranch must not be told to insert a fallthrough"); + assert(!BytesAdded && "code size not handled"); + assert((Cond.size() <= 3) && "# of Mips branch conditions must be <= 3!"); + if (FBB) { + BuildCondBr(MBB, TBB, DL, Cond); + BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(FBB); + return 2; + } + if (Cond.empty()) + BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(TBB); + else + BuildCondBr(MBB, TBB, DL, Cond); + return 1; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/insertIndirectBranch.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/insertIndirectBranch.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/insertIndirectBranch.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/insertOutlinedCall.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/insertOutlinedCall.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/insertOutlinedCall.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/isAsCheapAsAMove.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/isAsCheapAsAMove.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/isAsCheapAsAMove.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/isBranchOffsetInRange.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/isBranchOffsetInRange.cpp new file mode 100644 index 0000000000000000000000000000000000000000..387646d147fa990d12248ab10485109553457415 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/isBranchOffsetInRange.cpp @@ -0,0 +1,134 @@ +bool MipsInstrInfo::isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const { + switch (BranchOpc) { + case Mips::B: + case Mips::BAL: + case Mips::BAL_BR: + case Mips::BAL_BR_MM: + case Mips::BC1F: + case Mips::BC1FL: + case Mips::BC1T: + case Mips::BC1TL: + case Mips::BEQ: case Mips::BEQ64: + case Mips::BEQL: + case Mips::BGEZ: case Mips::BGEZ64: + case Mips::BGEZL: + case Mips::BGEZAL: + case Mips::BGEZALL: + case Mips::BGTZ: case Mips::BGTZ64: + case Mips::BGTZL: + case Mips::BLEZ: case Mips::BLEZ64: + case Mips::BLEZL: + case Mips::BLTZ: case Mips::BLTZ64: + case Mips::BLTZL: + case Mips::BLTZAL: + case Mips::BLTZALL: + case Mips::BNE: case Mips::BNE64: + case Mips::BNEL: + return isInt<18>(BrOffset); + case Mips::B_MM: + case Mips::BC1F_MM: + case Mips::BC1T_MM: + case Mips::BEQ_MM: + case Mips::BGEZ_MM: + case Mips::BGEZAL_MM: + case Mips::BGTZ_MM: + case Mips::BLEZ_MM: + case Mips::BLTZ_MM: + case Mips::BLTZAL_MM: + case Mips::BNE_MM: + case Mips::BEQZC_MM: + case Mips::BNEZC_MM: + return isInt<17>(BrOffset); + case Mips::B16_MM: + return isInt<11>(BrOffset); + case Mips::BEQZ16_MM: + case Mips::BNEZ16_MM: + return isInt<8>(BrOffset); + case Mips::BALC: + case Mips::BC: + return isInt<28>(BrOffset); + case Mips::BC1EQZ: + case Mips::BC1NEZ: + case Mips::BC2EQZ: + case Mips::BC2NEZ: + case Mips::BEQC: case Mips::BEQC64: + case Mips::BNEC: case Mips::BNEC64: + case Mips::BGEC: case Mips::BGEC64: + case Mips::BGEUC: case Mips::BGEUC64: + case Mips::BGEZC: case Mips::BGEZC64: + case Mips::BGTZC: case Mips::BGTZC64: + case Mips::BLEZC: case Mips::BLEZC64: + case Mips::BLTC: case Mips::BLTC64: + case Mips::BLTUC: case Mips::BLTUC64: + case Mips::BLTZC: case Mips::BLTZC64: + case Mips::BNVC: + case Mips::BOVC: + case Mips::BGEZALC: + case Mips::BEQZALC: + case Mips::BGTZALC: + case Mips::BLEZALC: + case Mips::BLTZALC: + case Mips::BNEZALC: + return isInt<18>(BrOffset); + case Mips::BEQZC: case Mips::BEQZC64: + case Mips::BNEZC: case Mips::BNEZC64: + return isInt<23>(BrOffset); + case Mips::BC16_MMR6: + return isInt<11>(BrOffset); + case Mips::BEQZC16_MMR6: + case Mips::BNEZC16_MMR6: + return isInt<8>(BrOffset); + case Mips::BALC_MMR6: + case Mips::BC_MMR6: + return isInt<27>(BrOffset); + case Mips::BC1EQZC_MMR6: + case Mips::BC1NEZC_MMR6: + case Mips::BC2EQZC_MMR6: + case Mips::BC2NEZC_MMR6: + case Mips::BGEZALC_MMR6: + case Mips::BEQZALC_MMR6: + case Mips::BGTZALC_MMR6: + case Mips::BLEZALC_MMR6: + case Mips::BLTZALC_MMR6: + case Mips::BNEZALC_MMR6: + case Mips::BNVC_MMR6: + case Mips::BOVC_MMR6: + return isInt<17>(BrOffset); + case Mips::BEQC_MMR6: + case Mips::BNEC_MMR6: + case Mips::BGEC_MMR6: + case Mips::BGEUC_MMR6: + case Mips::BGEZC_MMR6: + case Mips::BGTZC_MMR6: + case Mips::BLEZC_MMR6: + case Mips::BLTC_MMR6: + case Mips::BLTUC_MMR6: + case Mips::BLTZC_MMR6: + return isInt<18>(BrOffset); + case Mips::BEQZC_MMR6: + case Mips::BNEZC_MMR6: + return isInt<23>(BrOffset); + case Mips::BPOSGE32: + return isInt<18>(BrOffset); + case Mips::BPOSGE32_MM: + case Mips::BPOSGE32C_MMR3: + return isInt<17>(BrOffset); + case Mips::BBIT0: + case Mips::BBIT032: + case Mips::BBIT1: + case Mips::BBIT132: + return isInt<18>(BrOffset); + case Mips::BZ_B: + case Mips::BZ_H: + case Mips::BZ_W: + case Mips::BZ_D: + case Mips::BZ_V: + case Mips::BNZ_B: + case Mips::BNZ_H: + case Mips::BNZ_W: + case Mips::BNZ_D: + case Mips::BNZ_V: + return isInt<18>(BrOffset); + } + llvm_unreachable("Unknown branch instruction!"); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/isCopyInstrImpl.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/isCopyInstrImpl.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fcd4b976e92def26b6c872ee0f07b832132ded3e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/isCopyInstrImpl.cpp @@ -0,0 +1,17 @@ +Optional MipsSEInstrInfo::isCopyInstrImpl(const MachineInstr &MI) const { + bool isDSPControlWrite = false; + if (isReadOrWriteToDSPReg(MI, isDSPControlWrite)) { + if (!MI.getOperand(1).isImm() || MI.getOperand(1).getImm() != (1 << 4)) + return None; + else if (isDSPControlWrite) { + return DestSourcePair{MI.getOperand(2), MI.getOperand(0)}; + } + else { + return DestSourcePair{MI.getOperand(0), MI.getOperand(2)}; + } + } + else if (MI.isMoveReg() || isORCopyInst(MI)) { + return DestSourcePair{MI.getOperand(0), MI.getOperand(1)}; + } + return None; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/isFunctionSafeToOutlineFrom.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/isFunctionSafeToOutlineFrom.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/isFunctionSafeToOutlineFrom.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/isLoadFromStackSlot.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/isLoadFromStackSlot.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e2d8d63900cd69f173695b130359cfe1d18aa693 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/isLoadFromStackSlot.cpp @@ -0,0 +1,10 @@ +unsigned MipsSEInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const { + unsigned Opc = MI.getOpcode(); + if ((Opc == Mips::LW) || (Opc == Mips::LD) || (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) { + if ((MI.getOperand(1).isFI()) && (MI.getOperand(2).isImm()) && (isZeroImm(MI.getOperand(2)))) { + FrameIndex = MI.getOperand(1).getIndex(); + return MI.getOperand(0).getReg(); + } + } + return 0; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/isMBBSafeToOutlineFrom.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/isMBBSafeToOutlineFrom.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/isMBBSafeToOutlineFrom.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/isSchedulingBoundary.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/isSchedulingBoundary.cpp new file mode 100644 index 0000000000000000000000000000000000000000..dc4822b4dace5d5d62f234df92749f851e92acbc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/isSchedulingBoundary.cpp @@ -0,0 +1,3 @@ +None + + diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/isStoreToStackSlot.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/isStoreToStackSlot.cpp new file mode 100644 index 0000000000000000000000000000000000000000..049c3f11016793dd29d3fb81bb7172132b37b96d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/isStoreToStackSlot.cpp @@ -0,0 +1,11 @@ +unsigned MipsSEInstrInfo::isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const { + unsigned Opc = MI.getOpcode(); + if ((Opc == Mips::SW) || (Opc == Mips::SD) || (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) { + if ((MI.getOperand(1).isFI()) && (MI.getOperand(2).isImm()) && (isZeroImm(MI.getOperand(2)))) { + FrameIndex = MI.getOperand(1).getIndex(); + return MI.getOperand(0).getReg(); + } + } + return 0; +} + diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/loadRegFromStackSlot.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/loadRegFromStackSlot.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0dbe9a6a32e51bc601900a9635c3d6376933a144 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/loadRegFromStackSlot.cpp @@ -0,0 +1,62 @@ +void MipsSEInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const { + DebugLoc DL; + if (I != MBB.end()) DL = I->getDebugLoc(); + MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad); + unsigned Opc = 0; + const Function &Func = MBB.getParent()->getFunction(); + bool ReqIndirectLoad = Func.hasFnAttribute("interrupt") && (DestReg == Mips::LO0 || DestReg == Mips::LO0_64 || DestReg == Mips::HI0 || DestReg == Mips::HI0_64); + if (Mips::GPR32RegClass.hasSubClassEq(RC)) + Opc = Mips::LW; + else if (Mips::GPR64RegClass.hasSubClassEq(RC)) + Opc = Mips::LD; + else if (Mips::ACC64RegClass.hasSubClassEq(RC)) + Opc = Mips::LOAD_ACC64; + else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC)) + Opc = Mips::LOAD_ACC64DSP; + else if (Mips::ACC128RegClass.hasSubClassEq(RC)) + Opc = Mips::LOAD_ACC128; + else if (Mips::DSPCCRegClass.hasSubClassEq(RC)) + Opc = Mips::LOAD_CCOND_DSP; + else if (Mips::FGR32RegClass.hasSubClassEq(RC)) + Opc = Mips::LWC1; + else if (Mips::AFGR64RegClass.hasSubClassEq(RC)) + Opc = Mips::LDC1; + else if (Mips::FGR64RegClass.hasSubClassEq(RC)) + Opc = Mips::LDC164; + else if (TRI->isTypeLegalForClass(*RC, MVT::v16i8)) + Opc = Mips::LD_B; + else if (TRI->isTypeLegalForClass(*RC, MVT::v8i16) || TRI->isTypeLegalForClass(*RC, MVT::v8f16)) + Opc = Mips::LD_H; + else if (TRI->isTypeLegalForClass(*RC, MVT::v4i32) || TRI->isTypeLegalForClass(*RC, MVT::v4f32)) + Opc = Mips::LD_W; + else if (TRI->isTypeLegalForClass(*RC, MVT::v2i64) || TRI->isTypeLegalForClass(*RC, MVT::v2f64)) + Opc = Mips::LD_D; + else if (Mips::HI32RegClass.hasSubClassEq(RC)) + Opc = Mips::LW; + else if (Mips::HI64RegClass.hasSubClassEq(RC)) + Opc = Mips::LD; + else if (Mips::LO32RegClass.hasSubClassEq(RC)) + Opc = Mips::LW; + else if (Mips::LO64RegClass.hasSubClassEq(RC)) + Opc = Mips::LD; + else if (Mips::DSPRRegClass.hasSubClassEq(RC)) + Opc = Mips::LWDSP; + assert(Opc && "Register class not handled!"); + if (!ReqIndirectLoad) + BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(Offset).addMemOperand(MMO); + else { + unsigned Reg = Mips::K0; + unsigned LdOp = Mips::MTLO; + if (DestReg == Mips::HI0) + LdOp = Mips::MTHI; + if (Subtarget.getABI().ArePtrs64bit()) { + Reg = Mips::K0_64; + if (DestReg == Mips::HI0_64) + LdOp = Mips::MTHI64; + else + LdOp = Mips::MTLO64; + } + BuildMI(MBB, I, DL, get(Opc), Reg).addFrameIndex(FI).addImm(Offset).addMemOperand(MMO); + BuildMI(MBB, I, DL, get(LdOp)).addReg(Reg); + } +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/movImm.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/movImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/movImm.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/parseCondBranch.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/parseCondBranch.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/parseCondBranch.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/removeBranch.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/removeBranch.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cef1e08a42cd47a219a08a7b03df1b62305453b3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/removeBranch.cpp @@ -0,0 +1,17 @@ +unsigned MipsInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved) const { + assert(!BytesRemoved && "code size not handled"); + MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend(); + unsigned removed = 0; + while (I != REnd && removed < 2) { + if (I->isDebugInstr()) { + ++I; + continue; + } + if (!getAnalyzableBrOpc(I->getOpcode())) + break; + I->eraseFromParent(); + I = MBB.rbegin(); + ++removed; + } + return removed; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/reverseBranchCondition.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/reverseBranchCondition.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bf4c73519980083d2273651b2680171851c4d0a1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/reverseBranchCondition.cpp @@ -0,0 +1,5 @@ +bool MipsInstrInfo::reverseBranchCondition(SmallVectorImpl &Cond) const { + assert( (Cond.size() && Cond.size() <= 3) && "Invalid Mips branch condition!"); + Cond[0].setImm(getOppositeBranchOpc(Cond[0].getImm())); + return false; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/storeRegToStackSlot.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/storeRegToStackSlot.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b46bd40f8ae60038cbce551cc210dfdc0d86cc72 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/storeRegToStackSlot.cpp @@ -0,0 +1,10 @@ +void Mips16InstrInfo::storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const { + DebugLoc DL; + if (I != MBB.end()) DL = I->getDebugLoc(); + MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore); + unsigned Opc = 0; + if (Mips::CPU16RegsRegClass.hasSubClassEq(RC)) + Opc = Mips::SwRxSpImmX16; + assert(Opc && "Register class not handled!"); + BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)).addFrameIndex(FI).addImm(Offset).addMemOperand(MMO); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/verifyInstruction.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/verifyInstruction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f4e70d6cfccd0aae1635f5ad95610e11da64d4f0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/InstrInfo/verifyInstruction.cpp @@ -0,0 +1,34 @@ +bool MipsInstrInfo::verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const { + switch (MI.getOpcode()) { + case Mips::EXT: + case Mips::EXT_MM: + case Mips::INS: + case Mips::INS_MM: + case Mips::DINS: + return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 0, 32, 0, 32); + case Mips::DINSM: + return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 1, 64, 32, 64); + case Mips::DINSU: + return verifyInsExtInstruction(MI, ErrInfo, 32, 64, 0, 32, 32, 64); + case Mips::DEXT: + return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 0, 32, 0, 63); + case Mips::DEXTM: + return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 32, 64, 32, 64); + case Mips::DEXTU: + return verifyInsExtInstruction(MI, ErrInfo, 32, 64, 0, 32, 32, 64); + case Mips::TAILCALLREG: + case Mips::PseudoIndirectBranch: + case Mips::JR: + case Mips::JR64: + case Mips::JALR: + case Mips::JALR64: + case Mips::JALRPseudo: + if (!Subtarget.useIndirectJumpsHazard()) + return true; + ErrInfo = "invalid instruction when using jump guards!"; + return false; + default: + return true; + } + return true; +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/MachineFunctionInfo/MachineFunctionInfo.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/MachineFunctionInfo/MachineFunctionInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2f7bafbb1b297ac62ef58faf3ebbc3ba088ae838 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/MachineFunctionInfo/MachineFunctionInfo.cpp @@ -0,0 +1,2 @@ +MipsFunctionInfo(MachineFunction &MF) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/MachineFunctionInfo/getLibCallStackSize.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/MachineFunctionInfo/getLibCallStackSize.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/MachineFunctionInfo/getLibCallStackSize.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/MachineFunctionInfo/getMoveF64FrameIndex.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/MachineFunctionInfo/getMoveF64FrameIndex.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/MachineFunctionInfo/getMoveF64FrameIndex.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/MachineFunctionInfo/getUsedSSR.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/MachineFunctionInfo/getUsedSSR.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/MachineFunctionInfo/getUsedSSR.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/MachineFunctionInfo/getVarArgsFrameIndex.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/MachineFunctionInfo/getVarArgsFrameIndex.cpp new file mode 100644 index 0000000000000000000000000000000000000000..815700881400f3e2610e1d74e0907493d5ea7898 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/MachineFunctionInfo/getVarArgsFrameIndex.cpp @@ -0,0 +1,3 @@ +int getVarArgsFrameIndex() const { + return VarArgsFrameIndex; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/MachineFunctionInfo/getVarArgsSaveSize.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/MachineFunctionInfo/getVarArgsSaveSize.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/MachineFunctionInfo/getVarArgsSaveSize.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/MachineFunctionInfo/setLibCallStackSize.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/MachineFunctionInfo/setLibCallStackSize.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/MachineFunctionInfo/setLibCallStackSize.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/MachineFunctionInfo/setUsedSSR.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/MachineFunctionInfo/setUsedSSR.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/MachineFunctionInfo/setUsedSSR.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/MachineFunctionInfo/setVarArgsFrameIndex.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/MachineFunctionInfo/setVarArgsFrameIndex.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f453600ffb2d2bf1e86883efc8373719fb63f8ae --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/MachineFunctionInfo/setVarArgsFrameIndex.cpp @@ -0,0 +1,3 @@ +void setVarArgsFrameIndex(int Index) { + VarArgsFrameIndex = Index; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/MachineFunctionInfo/setVarArgsSaveSize.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/MachineFunctionInfo/setVarArgsSaveSize.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/MachineFunctionInfo/setVarArgsSaveSize.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/MachineFunctionInfo/useSaveRestoreLibCalls.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/MachineFunctionInfo/useSaveRestoreLibCalls.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/MachineFunctionInfo/useSaveRestoreLibCalls.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/Subtarget.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/Subtarget.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f8dbe9393d5f502927a51bf3bd6e31b2ef5a0ed3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/Subtarget.cpp @@ -0,0 +1,89 @@ +MipsSubtarget::MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS, bool little, const MipsTargetMachine &TM, MaybeAlign StackAlignOverride): MipsGenSubtargetInfo(TT, CPU, CPU, FS), MipsArchVersion(MipsDefault), IsLittle(little), IsSoftFloat(false), IsSingleFloat(false), IsFPXX(false), NoABICalls(false), Abs2008(false), IsFP64bit(false), UseOddSPReg(true), IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false), HasCnMips(false), HasCnMipsP(false), HasMips3_32(false), HasMips3_32r2(false), HasMips4_32(false), HasMips4_32r2(false), HasMips5_32r2(false), InMips16Mode(false), InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false), HasDSPR2(false), HasDSPR3(false), AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16), HasMSA(false), UseTCCInDIV(false), HasSym32(false), HasEVA(false), DisableMadd4(false), HasMT(false), HasCRC(false), HasVirt(false), HasGINV(false), UseIndirectJumpsHazard(false), StackAlignOverride(StackAlignOverride), TM(TM), TargetTriple(TT), TSInfo(), InstrInfo(MipsInstrInfo::create( initializeSubtargetDependencies(CPU, FS, TM))), FrameLowering(MipsFrameLowering::create(*this)), TLInfo(MipsTargetLowering::create(TM, *this)) { + if (MipsArchVersion == MipsDefault) + MipsArchVersion = Mips32; + if (MipsArchVersion == Mips1) + report_fatal_error("Code generation for MIPS-I is not implemented", false); + if (MipsArchVersion == Mips5) + report_fatal_error("Code generation for MIPS-V is not implemented", false); + assert(((!isGP64bit() && isABI_O32()) || (isGP64bit() && (isABI_N32() || isABI_N64()))) && "Invalid Arch & ABI pair."); + if (hasMSA() && !isFP64bit()) + report_fatal_error("MSA requires a 64-bit FPU register file (FR=1 mode). See -mattr=+fp64.", false); + if (isFP64bit() && !hasMips64() && hasMips32() && !hasMips32r2()) + report_fatal_error("FPU with 64-bit registers is not available on MIPS32 pre revision 2. Use -mcpu=mips32r2 or greater."); + if (!isABI_O32() && !useOddSPReg()) + report_fatal_error("-mattr=+nooddspreg requires the O32 ABI.", false); + if (IsFPXX && (isABI_N32() || isABI_N64())) + report_fatal_error("FPXX is not permitted for the N32/N64 ABI's.", false); + if (hasMips64r6() && InMicroMipsMode) + report_fatal_error("microMIPS64R6 is not supported", false); + if (!isABI_O32() && InMicroMipsMode) + report_fatal_error("microMIPS64 is not supported.", false); + if (UseIndirectJumpsHazard) { + if (InMicroMipsMode) + report_fatal_error("cannot combine indirect jumps with hazard barriers and microMIPS"); + if (!hasMips32r2()) + report_fatal_error("indirect jumps with hazard barriers requires MIPS32R2 or later"); + } + if (inAbs2008Mode() && hasMips32() && !hasMips32r2()) { + report_fatal_error("IEEE 754-2008 abs.fmt is not supported for the given architecture.", false); + } + if (hasMips32r6()) { + StringRef ISA = hasMips64r6() ? "MIPS64r6" : "MIPS32r6"; + assert(isFP64bit()); + assert(isNaN2008()); + assert(inAbs2008Mode()); + if (hasDSP()) + report_fatal_error(ISA + " is not compatible with the DSP ASE", false); + } + if (NoABICalls && TM.isPositionIndependent()) + report_fatal_error("position-independent code requires '-mabicalls'"); + if (isABI_N64() && !TM.isPositionIndependent() && !hasSym32()) + NoABICalls = true; + UseSmallSection = GPOpt; + if (!NoABICalls && GPOpt) { + errs() << "warning: cannot use small-data accesses for '-mabicalls'" << "\n"; + UseSmallSection = false; + } + if (hasDSPR2() && !DspWarningPrinted) { + if (hasMips64() && !hasMips64r2()) { + errs() << "warning: the 'dspr2' ASE requires MIPS64 revision 2 or " << "greater\n"; + DspWarningPrinted = true; + } + else if (hasMips32() && !hasMips32r2()) { + errs() << "warning: the 'dspr2' ASE requires MIPS32 revision 2 or " << "greater\n"; + DspWarningPrinted = true; + } + } + else if (hasDSP() && !DspWarningPrinted) { + if (hasMips64() && !hasMips64r2()) { + errs() << "warning: the 'dsp' ASE requires MIPS64 revision 2 or " << "greater\n"; + DspWarningPrinted = true; + } + else if (hasMips32() && !hasMips32r2()) { + errs() << "warning: the 'dsp' ASE requires MIPS32 revision 2 or " << "greater\n"; + DspWarningPrinted = true; + } + } + StringRef ArchName = hasMips64() ? "MIPS64" : "MIPS32"; + if (!hasMips32r5() && hasMSA() && !MSAWarningPrinted) { + errs() << "warning: the 'msa' ASE requires " << ArchName << " revision 5 or greater\n"; + MSAWarningPrinted = true; + } + if (!hasMips32r5() && hasVirt() && !VirtWarningPrinted) { + errs() << "warning: the 'virt' ASE requires " << ArchName << " revision 5 or greater\n"; + VirtWarningPrinted = true; + } + if (!hasMips32r6() && hasCRC() && !CRCWarningPrinted) { + errs() << "warning: the 'crc' ASE requires " << ArchName << " revision 6 or greater\n"; + CRCWarningPrinted = true; + } + if (!hasMips32r6() && hasGINV() && !GINVWarningPrinted) { + errs() << "warning: the 'ginv' ASE requires " << ArchName << " revision 6 or greater\n"; + GINVWarningPrinted = true; + } + CallLoweringInfo.reset(new MipsCallLowering(*getTargetLowering())); + Legalizer.reset(new MipsLegalizerInfo(*this)); + auto *RBI = new MipsRegisterBankInfo(*getRegisterInfo()); + RegBankInfo.reset(RBI); + InstSelector.reset(createMipsInstructionSelector(*static_cast(&TM), *this, *RBI)); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/anchor.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/anchor.cpp new file mode 100644 index 0000000000000000000000000000000000000000..436736c15924b75b84b927d41c944ede3edceaa0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/anchor.cpp @@ -0,0 +1,2 @@ +void MipsSubtarget::anchor() { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/enableLinkerRelax.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/enableLinkerRelax.cpp new file mode 100644 index 0000000000000000000000000000000000000000..430d9de4ff5dc9452edc2d5d727d8f5bf4687563 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/enableLinkerRelax.cpp @@ -0,0 +1,3 @@ +bool MipsSubtarget::enablePostRAScheduler() const { + return true; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/enableMachineScheduler.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/enableMachineScheduler.cpp new file mode 100644 index 0000000000000000000000000000000000000000..430d9de4ff5dc9452edc2d5d727d8f5bf4687563 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/enableMachineScheduler.cpp @@ -0,0 +1,3 @@ +bool MipsSubtarget::enablePostRAScheduler() const { + return true; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/enableRVCHintInstrs.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/enableRVCHintInstrs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..430d9de4ff5dc9452edc2d5d727d8f5bf4687563 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/enableRVCHintInstrs.cpp @@ -0,0 +1,3 @@ +bool MipsSubtarget::enablePostRAScheduler() const { + return true; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/enableSaveRestore.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/enableSaveRestore.cpp new file mode 100644 index 0000000000000000000000000000000000000000..430d9de4ff5dc9452edc2d5d727d8f5bf4687563 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/enableSaveRestore.cpp @@ -0,0 +1,3 @@ +bool MipsSubtarget::enablePostRAScheduler() const { + return true; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/getCallLowering.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/getCallLowering.cpp new file mode 100644 index 0000000000000000000000000000000000000000..aa3fad473e1b3246c8f94087b5fbbd169058d219 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/getCallLowering.cpp @@ -0,0 +1,3 @@ +const CallLowering *MipsSubtarget::getCallLowering() const { + return CallLoweringInfo.get(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/getFrameLowering.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/getFrameLowering.cpp new file mode 100644 index 0000000000000000000000000000000000000000..46facc9d53d8ed20463a68f1486618473e216322 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/getFrameLowering.cpp @@ -0,0 +1,3 @@ +const TargetFrameLowering *getFrameLowering() const override { + return FrameLowering.get(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/getInstrInfo.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/getInstrInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e800e2a8b4f1864f21678597f1942ae03a8a6ab2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/getInstrInfo.cpp @@ -0,0 +1,3 @@ +const MipsInstrInfo *getInstrInfo() const override { + return InstrInfo.get(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/getInstructionSelector.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/getInstructionSelector.cpp new file mode 100644 index 0000000000000000000000000000000000000000..62e906d17d51ea4764241fa71a10f28d9159bfbd --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/getInstructionSelector.cpp @@ -0,0 +1,3 @@ +InstructionSelector *MipsSubtarget::getInstructionSelector() const { + return InstSelector.get(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/getLegalizerInfo.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/getLegalizerInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fe91271b193b048bfbdd2a0096116ff7350be978 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/getLegalizerInfo.cpp @@ -0,0 +1,3 @@ +const LegalizerInfo *MipsSubtarget::getLegalizerInfo() const { + return Legalizer.get(); +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/getRegBankInfo.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/getRegBankInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a5417d779e8304c5adaad1f053b6982c7a2dcd37 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/getRegBankInfo.cpp @@ -0,0 +1,3 @@ +const RegisterBankInfo *MipsSubtarget::getRegBankInfo() const { + return RegBankInfo.get(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/getRegisterInfo.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/getRegisterInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..70e4b467269f9a62a119d78ba8756d15153967e2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/getRegisterInfo.cpp @@ -0,0 +1,3 @@ +const MipsRegisterInfo *getRegisterInfo() const override { + return &InstrInfo->getRegisterInfo(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/getSelectionDAGInfo.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/getSelectionDAGInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d9cec09b2f3127f3d36917798ff8d808237620f9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/getSelectionDAGInfo.cpp @@ -0,0 +1,3 @@ +const SelectionDAGTargetInfo *getSelectionDAGInfo() const override { + return &TSInfo; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/getTargetABI.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/getTargetABI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/getTargetABI.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/getTargetLowering.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/getTargetLowering.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f6a80a497f8d2bee84fc660d8e8cdfcfe7048369 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/getTargetLowering.cpp @@ -0,0 +1,3 @@ +const MipsTargetLowering *getTargetLowering() const override { + return TLInfo.get(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/getXLen.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/getXLen.cpp new file mode 100644 index 0000000000000000000000000000000000000000..619cc9eaf53f1510ccde851e748b819574304f6d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/getXLen.cpp @@ -0,0 +1,3 @@ +MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override { + return MVT::i32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/getXLenVT.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/getXLenVT.cpp new file mode 100644 index 0000000000000000000000000000000000000000..619cc9eaf53f1510ccde851e748b819574304f6d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/getXLenVT.cpp @@ -0,0 +1,3 @@ +MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override { + return MVT::i32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXdma.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXdma.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXdma.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfalthalf.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfalthalf.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfalthalf.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfaltquarter.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfaltquarter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfaltquarter.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfauxalthalf.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfauxalthalf.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfauxalthalf.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfauxaltquarter.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfauxaltquarter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfauxaltquarter.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfauxhalf.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfauxhalf.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfauxhalf.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfauxquarter.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfauxquarter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfauxquarter.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfauxvecalthalf.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfauxvecalthalf.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfauxvecalthalf.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfauxvecaltquarter.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfauxvecaltquarter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfauxvecaltquarter.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfauxvechalf.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfauxvechalf.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfauxvechalf.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfauxvecquarter.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfauxvecquarter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfauxvecquarter.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfauxvecsingle.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfauxvecsingle.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfauxvecsingle.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfexpauxvecalthalf.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfexpauxvecalthalf.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfexpauxvecalthalf.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfexpauxvecaltquarter.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfexpauxvecaltquarter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfexpauxvecaltquarter.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfexpauxvechalf.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfexpauxvechalf.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfexpauxvechalf.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfexpauxvecquarter.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfexpauxvecquarter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfexpauxvecquarter.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfquarter.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfquarter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfquarter.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfrep.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfrep.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfrep.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfvecalthalf.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfvecalthalf.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfvecalthalf.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfvecaltquarter.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfvecaltquarter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfvecaltquarter.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfvechalf.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfvechalf.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfvechalf.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfvecquarter.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfvecquarter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfvecquarter.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfvecsingle.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfvecsingle.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXfvecsingle.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXmempool.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXmempool.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXmempool.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXsmallfloat.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXsmallfloat.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXsmallfloat.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXssr.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXssr.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasExtXssr.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasPULPExtV2.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasPULPExtV2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasPULPExtV2.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtA.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtA.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtA.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtB.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtB.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtB.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtC.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtC.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtD.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtD.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtD.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtF.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtF.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtF.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtM.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtM.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtM.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtV.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtV.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtV.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtZba.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtZba.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtZba.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtZbb.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtZbb.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtZbb.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtZbc.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtZbc.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtZbc.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtZbe.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtZbe.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtZbe.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtZbf.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtZbf.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtZbf.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtZbm.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtZbm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtZbm.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtZbp.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtZbp.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtZbp.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtZbproposedc.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtZbproposedc.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtZbproposedc.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtZbr.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtZbr.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtZbr.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtZbs.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtZbs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtZbs.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtZbt.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtZbt.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtZbt.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtZfh.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtZfh.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtZfh.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtZvamo.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtZvamo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtZvamo.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtZvlsseg.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtZvlsseg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/hasStdExtZvlsseg.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/initializeSubtargetDependencies.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/initializeSubtargetDependencies.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a9e9e37c3feac2354466675ef429eee1bf53c525 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/initializeSubtargetDependencies.cpp @@ -0,0 +1,18 @@ +MipsSubtarget &MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS, const TargetMachine &TM) { + StringRef CPUName = MIPS_MC::selectMipsCPU(TM.getTargetTriple(), CPU); + ParseSubtargetFeatures(CPUName, CPUName, FS); + InstrItins = getInstrItineraryForCPU(CPUName); + if (InMips16Mode && !IsSoftFloat) + InMips16HardFloat = true; + if (StackAlignOverride) + stackAlignment = *StackAlignOverride; + else if (isABI_N32() || isABI_N64()) + stackAlignment = Align(16); + else { + assert(isABI_O32() && "Unknown ABI for stack alignment!"); + stackAlignment = Align(8); + } + if ((isABI_N32() || isABI_N64()) && !isGP64bit()) + report_fatal_error("64-bit code requested on a subtarget that doesn't support it!"); + return *this; +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/is64Bit.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/is64Bit.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b2d28ef868387af51863de445769ffa8d848320d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/is64Bit.cpp @@ -0,0 +1,3 @@ +bool isPTR64bit() const { + return IsPTR64bit; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/isPULP.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/isPULP.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b2d28ef868387af51863de445769ffa8d848320d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/isPULP.cpp @@ -0,0 +1,3 @@ +bool isPTR64bit() const { + return IsPTR64bit; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/isRV32E.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/isRV32E.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1f93561d2032e25cd18ca3d71c412c8891819cf5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/isRV32E.cpp @@ -0,0 +1,3 @@ +bool isGP32bit() const { + return !IsGP64bit; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/isRegisterReservedByUser.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/isRegisterReservedByUser.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/Subtarget/isRegisterReservedByUser.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetInfo/LLVMInitializeTargetInfo.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetInfo/LLVMInitializeTargetInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..aa19b102fcb9d571a36a08f83de9e63d0dad45af --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetInfo/LLVMInitializeTargetInfo.cpp @@ -0,0 +1,6 @@ +extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMipsTargetInfo() { + RegisterTarget X(getTheMipsTarget(), "mips", "MIPS (32-bit big endian)", "Mips"); + RegisterTarget Y(getTheMipselTarget(), "mipsel", "MIPS (32-bit little endian)", "Mips"); + RegisterTarget A(getTheMips64Target(), "mips64", "MIPS (64-bit big endian)", "Mips"); + RegisterTarget B(getTheMips64elTarget(), "mips64el", "MIPS (64-bit little endian)","Mips"); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetInfo/getThe32Target.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetInfo/getThe32Target.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d029fee31d59b7b7e4c2d46eb1753cc207e1a386 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetInfo/getThe32Target.cpp @@ -0,0 +1,4 @@ +Target &llvm::getTheMipsTarget() { + static Target TheMipsTarget; + return TheMipsTarget; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetInfo/getThe64Target.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetInfo/getThe64Target.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a203a8b0cb4ad6485ee57f457ac01c93bb38bca7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetInfo/getThe64Target.cpp @@ -0,0 +1,4 @@ +Target &llvm::getTheMips64Target() { + static Target TheMips64Target; + return TheMips64Target; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/LLVMInitializeTarget.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/LLVMInitializeTarget.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cebec48b8e7e252d90044f50cbef0210c65c5fa2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/LLVMInitializeTarget.cpp @@ -0,0 +1,13 @@ +extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMipsTarget() { + RegisterTargetMachine X(getTheMipsTarget()); + RegisterTargetMachine Y(getTheMipselTarget()); + RegisterTargetMachine A(getTheMips64Target()); + RegisterTargetMachine B(getTheMips64elTarget()); + PassRegistry *PR = PassRegistry::getPassRegistry(); + initializeGlobalISel(*PR); + initializeMipsDelaySlotFillerPass(*PR); + initializeMipsBranchExpansionPass(*PR); + initializeMicroMipsSizeReducePass(*PR); + initializeMipsPreLegalizerCombinerPass(*PR); +} + diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/PassConfig.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/PassConfig.cpp new file mode 100644 index 0000000000000000000000000000000000000000..20da95a9d216fe1c9fd7a5ecdd41da237b1d474b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/PassConfig.cpp @@ -0,0 +1,3 @@ +MipsPassConfig(MipsTargetMachine &TM, PassManagerBase &PM) : TargetPassConfig(TM, PM) { + EnableTailMerge = !getMipsSubtarget().enableLongBranchPass(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/TargetMachine.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/TargetMachine.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bb7a4b12d46b90e267a11d089bac3205f01c869d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/TargetMachine.cpp @@ -0,0 +1,5 @@ +MipsTargetMachine::MipsTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional RM, Optional CM, CodeGenOpt::Level OL, bool JIT, bool isLittle) : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT, CPU, FS, Options, getEffectiveRelocModel(JIT, RM), getEffectiveCodeModel(CM, CodeModel::Small), OL), isLittle(isLittle), TLOF(std::make_unique()), ABI(MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions)), Subtarget(nullptr), DefaultSubtarget(TT, CPU, FS, isLittle, *this, MaybeAlign(Options.StackAlignmentOverride)), NoMips16Subtarget(TT, CPU, FS.empty() ? "-mips16" : FS.str() + ",-mips16", isLittle, *this, MaybeAlign(Options.StackAlignmentOverride)), Mips16Subtarget(TT, CPU, FS.empty() ? "+mips16" : FS.str() + ",+mips16", isLittle, *this, MaybeAlign(Options.StackAlignmentOverride)) { + Subtarget = &DefaultSubtarget; + initAsmInfo(); + setSupportsDebugEntryValues(true); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/addGlobalInstructionSelect.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/addGlobalInstructionSelect.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8a5d768ad0a3e96bbc37e8565f6c69e6eb507228 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/addGlobalInstructionSelect.cpp @@ -0,0 +1,4 @@ +bool MipsPassConfig::addGlobalInstructionSelect() { + addPass(new InstructionSelect()); + return false; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/addIRPasses.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/addIRPasses.cpp new file mode 100644 index 0000000000000000000000000000000000000000..33f91a1a415e698013c6df506516503925f5c3c5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/addIRPasses.cpp @@ -0,0 +1,8 @@ +void MipsPassConfig::addIRPasses() { + TargetPassConfig::addIRPasses(); + addPass(createAtomicExpandPass()); + if (getMipsSubtarget().os16()) + addPass(createMipsOs16Pass()); + if (getMipsSubtarget().inMips16HardFloat()) + addPass(createMips16HardFloatPass()); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/addIRTranslator.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/addIRTranslator.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4a41c67c0603be6e9b5672f4fc565ac21ee5ce3e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/addIRTranslator.cpp @@ -0,0 +1,4 @@ +bool MipsPassConfig::addIRTranslator() { + addPass(new IRTranslator(getOptLevel())); + return false; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/addInstSelector.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/addInstSelector.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fed7400583c9fc2fb0ebb7485b3e4058b93f7c8b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/addInstSelector.cpp @@ -0,0 +1,6 @@ +bool MipsPassConfig::addInstSelector() { + addPass(createMipsModuleISelDagPass()); + addPass(createMips16ISelDag(getMipsTargetMachine(), getOptLevel())); + addPass(createMipsSEISelDag(getMipsTargetMachine(), getOptLevel())); + return false; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/addLegalizeMachineIR.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/addLegalizeMachineIR.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4c0f208a88cac1846e74f7f3e819d7d6bf6406f4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/addLegalizeMachineIR.cpp @@ -0,0 +1,4 @@ +bool MipsPassConfig::addLegalizeMachineIR() { + addPass(new Legalizer()); + return false; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/addPreEmitPass.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/addPreEmitPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..06d033e3b1fed3f9944e982215833add08185065 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/addPreEmitPass.cpp @@ -0,0 +1,7 @@ +void MipsPassConfig::addPreEmitPass() { + addPass(createMipsExpandPseudoPass()); + addPass(createMicroMipsSizeReducePass()); + addPass(createMipsDelaySlotFillerPass()); + addPass(createMipsBranchExpansion()); + addPass(createMipsConstantIslandPass()); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/addPreEmitPass2.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/addPreEmitPass2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..06d033e3b1fed3f9944e982215833add08185065 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/addPreEmitPass2.cpp @@ -0,0 +1,7 @@ +void MipsPassConfig::addPreEmitPass() { + addPass(createMipsExpandPseudoPass()); + addPass(createMicroMipsSizeReducePass()); + addPass(createMipsDelaySlotFillerPass()); + addPass(createMipsBranchExpansion()); + addPass(createMipsConstantIslandPass()); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/addPreRegAlloc.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/addPreRegAlloc.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d4fd1e966f2f6f1aa1e1720c3be90df4ac59f83e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/addPreRegAlloc.cpp @@ -0,0 +1,3 @@ +void MipsPassConfig::addPreRegAlloc() { + addPass(createMipsOptimizePICCallPass()); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/addPreSched2.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/addPreSched2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/addPreSched2.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/addRegBankSelect.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/addRegBankSelect.cpp new file mode 100644 index 0000000000000000000000000000000000000000..496fa0d237ac7a067970ee6482c4710e8643aa15 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/addRegBankSelect.cpp @@ -0,0 +1,4 @@ +bool MipsPassConfig::addRegBankSelect() { + addPass(new RegBankSelect()); + return false; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/computeDataLayout.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/computeDataLayout.cpp new file mode 100644 index 0000000000000000000000000000000000000000..779e0541abcede80b44734c783ecdbab4e2a47ea --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/computeDataLayout.cpp @@ -0,0 +1,20 @@ +static std::string computeDataLayout(const Triple &TT, StringRef CPU, const TargetOptions &Options, bool isLittle) { + std::string Ret; + MipsABIInfo ABI = MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions); + if (isLittle) + Ret += "e"; + else + Ret += "E"; + if (ABI.IsO32()) + Ret += "-m:m"; + else + Ret += "-m:e"; + if (!ABI.IsN64()) + Ret += "-p:32:32"; + Ret += "-i8:8:32-i16:16:32-i64:64"; + if (ABI.IsN64() || ABI.IsN32()) + Ret += "-n32:64-S128"; + else + Ret += "-n32-S64"; + return Ret; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/createPassConfig.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/createPassConfig.cpp new file mode 100644 index 0000000000000000000000000000000000000000..28c6d90decc8dea3f4e8ff897e48ef6d66908345 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/createPassConfig.cpp @@ -0,0 +1,3 @@ +TargetPassConfig *MipsTargetMachine::createPassConfig(PassManagerBase &PM) { + return new MipsPassConfig(*this, PM); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/getEffectiveRelocModel.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/getEffectiveRelocModel.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5e25a02cd5a11b44924270ee2dfbdb9e9292cf63 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/getEffectiveRelocModel.cpp @@ -0,0 +1,5 @@ +static Reloc::Model getEffectiveRelocModel(bool JIT, Optional RM) { + if (!RM.hasValue() || JIT) + return Reloc::Static; + return *RM; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/getObjFileLowering.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/getObjFileLowering.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c1c1365ba51f49fb7fb122c5b7afd2635513e01d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/getObjFileLowering.cpp @@ -0,0 +1,3 @@ +TargetLoweringObjectFile *getObjFileLowering() const override { + return TLOF.get(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/getSubtargetImpl.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/getSubtargetImpl.cpp new file mode 100644 index 0000000000000000000000000000000000000000..72a6aa9b0b63f9e9fcc02d673c5a32c466330d21 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/getSubtargetImpl.cpp @@ -0,0 +1,27 @@ +const MipsSubtarget *MipsTargetMachine::getSubtargetImpl(const Function &F) const { + Attribute CPUAttr = F.getFnAttribute("target-cpu"); + Attribute FSAttr = F.getFnAttribute("target-features"); + std::string CPU = CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU; + std::string FS = FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS; + bool hasMips16Attr = F.getFnAttribute("mips16").isValid(); + bool hasNoMips16Attr = F.getFnAttribute("nomips16").isValid(); + bool HasMicroMipsAttr = F.getFnAttribute("micromips").isValid(); + bool HasNoMicroMipsAttr = F.getFnAttribute("nomicromips").isValid(); + bool softFloat = F.hasFnAttribute("use-soft-float") && F.getFnAttribute("use-soft-float").getValueAsString() == "true"; + if (hasMips16Attr) + FS += FS.empty() ? "+mips16" : ",+mips16"; + else if (hasNoMips16Attr) + FS += FS.empty() ? "-mips16" : ",-mips16"; + if (HasMicroMipsAttr) + FS += FS.empty() ? "+micromips" : ",+micromips"; + else if (HasNoMicroMipsAttr) + FS += FS.empty() ? "-micromips" : ",-micromips"; + if (softFloat) + FS += FS.empty() ? "+soft-float" : ",+soft-float"; + auto &I = SubtargetMap[CPU + FS]; + if (!I) { + resetTargetOptions(F); + I = std::make_unique(TargetTriple, CPU, FS, isLittle, *this, MaybeAlign(Options.StackAlignmentOverride)); + } + return I.get(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/getTargetMachine.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/getTargetMachine.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3dc48d3b86556ea44b4a72126e4ab9c2dde73782 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/getTargetMachine.cpp @@ -0,0 +1,3 @@ +MipsTargetMachine &getMipsTargetMachine() const { + return getTM(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/getTargetTransformInfo.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/getTargetTransformInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..65f11723367b31e66f2c9629d33d19297544e2f8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/getTargetTransformInfo.cpp @@ -0,0 +1,8 @@ +TargetTransformInfo MipsTargetMachine::getTargetTransformInfo(const Function &F) { + if (Subtarget->allowMixed16_32()) { + LLVM_DEBUG(errs() << "No Target Transform Info Pass Added\n"); + return TargetTransformInfo(F.getParent()->getDataLayout()); + } + LLVM_DEBUG(errs() << "Target Transform Info Pass Added\n"); + return TargetTransformInfo(BasicTTIImpl(this, F)); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/isNoopAddrSpaceCast.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/isNoopAddrSpaceCast.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e50de996547528d432f64de320d37eb30e46f396 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/isNoopAddrSpaceCast.cpp @@ -0,0 +1,3 @@ +bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override { + return SrcAS < 256 && DestAS < 256; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/setTargetOptionsWithModuleMetadata.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/setTargetOptionsWithModuleMetadata.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetMachine/setTargetOptionsWithModuleMetadata.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetObjectFile/Initialize.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetObjectFile/Initialize.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a0d8533856448921babe3c7b5cab65e7ceeebca3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetObjectFile/Initialize.cpp @@ -0,0 +1,6 @@ +void MipsTargetObjectFile::Initialize(MCContext &Ctx, const TargetMachine &TM){ + TargetLoweringObjectFileELF::Initialize(Ctx, TM); + SmallDataSection = getContext().getELFSection(".sdata", ELF::SHT_PROGBITS, ELF::SHF_WRITE | ELF::SHF_ALLOC | ELF::SHF_MIPS_GPREL); + SmallBSSSection = getContext().getELFSection(".sbss", ELF::SHT_NOBITS, ELF::SHF_WRITE | ELF::SHF_ALLOC | ELF::SHF_MIPS_GPREL); + this->TM = &static_cast(TM); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetObjectFile/SelectSectionForGlobal.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetObjectFile/SelectSectionForGlobal.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bcb179748f251dd885c72ec65ea012aa51523e27 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetObjectFile/SelectSectionForGlobal.cpp @@ -0,0 +1,12 @@ +MCSection *MipsTargetObjectFile::SelectSectionForGlobal(const GlobalObject *GO, SectionKind Kind, const TargetMachine &TM) const { + if (Kind.isBSS() && IsGlobalInSmallSection(GO, TM, Kind)) { + return SmallBSSSection; + } + if (Kind.isData() && IsGlobalInSmallSection(GO, TM, Kind)) { + return SmallDataSection; + } + if (Kind.isReadOnly() && IsGlobalInSmallSection(GO, TM, Kind)) { + return SmallDataSection; + } + return TargetLoweringObjectFileELF::SelectSectionForGlobal(GO, Kind, TM); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetObjectFile/getModuleMetadata.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetObjectFile/getModuleMetadata.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetObjectFile/getModuleMetadata.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetObjectFile/getSectionForConstant.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetObjectFile/getSectionForConstant.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2aa9fc13963d18be314c20bb620b4fea6a394505 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetObjectFile/getSectionForConstant.cpp @@ -0,0 +1,5 @@ +MCSection *MipsTargetObjectFile::getSectionForConstant(const DataLayout &DL, SectionKind Kind, const Constant *C, Align &Alignment) const { + if (IsConstantInSmallSection(DL, C, *TM)) + return SmallDataSection; + return TargetLoweringObjectFileELF::getSectionForConstant(DL, Kind, C, Alignment); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetObjectFile/isConstantInSmallSection.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetObjectFile/isConstantInSmallSection.cpp new file mode 100644 index 0000000000000000000000000000000000000000..58b216236a3eef9c2fcf8becb5197f101875eb40 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetObjectFile/isConstantInSmallSection.cpp @@ -0,0 +1,3 @@ +bool MipsTargetObjectFile::IsConstantInSmallSection(const DataLayout &DL, const Constant *CN, const TargetMachine &TM) const { + return (static_cast(TM).getSubtargetImpl()->useSmallSection() && LocalSData && IsInSmallSection(DL.getTypeAllocSize(CN->getType()))); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetObjectFile/isGlobalInSmallSection.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetObjectFile/isGlobalInSmallSection.cpp new file mode 100644 index 0000000000000000000000000000000000000000..69f774302db816d7d0bc6b0b821abfc8a844636a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetObjectFile/isGlobalInSmallSection.cpp @@ -0,0 +1,5 @@ +bool MipsTargetObjectFile::IsGlobalInSmallSection(const GlobalObject *GO, const TargetMachine &TM) const { + if (GO->isDeclaration() || GO->hasAvailableExternallyLinkage()) + return IsGlobalInSmallSectionImpl(GO, TM); + return IsGlobalInSmallSection(GO, TM, getKindForGlobal(GO, TM)); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetObjectFile/isInSmallSection.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetObjectFile/isInSmallSection.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3bf6ffdc320b495882842e7acb341a1969b06a0c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetObjectFile/isInSmallSection.cpp @@ -0,0 +1,3 @@ +static bool IsInSmallSection(uint64_t Size) { + return Size > 0 && Size <= SSThreshold; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetTransformInfo/TTIImpl.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetTransformInfo/TTIImpl.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetTransformInfo/TTIImpl.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetTransformInfo/getIntImmCost.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetTransformInfo/getIntImmCost.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetTransformInfo/getIntImmCost.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetTransformInfo/getIntImmCostInst.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetTransformInfo/getIntImmCostInst.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetTransformInfo/getIntImmCostInst.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetTransformInfo/getIntImmCostIntrin.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetTransformInfo/getIntImmCostIntrin.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetTransformInfo/getIntImmCostIntrin.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetTransformInfo/getST.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetTransformInfo/getST.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetTransformInfo/getST.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetTransformInfo/getTLI.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetTransformInfo/getTLI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetTransformInfo/getTLI.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetTransformInfo/isLoweredToCall.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetTransformInfo/isLoweredToCall.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetTransformInfo/isLoweredToCall.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetTransformInfo/shouldFavorPostInc.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetTransformInfo/shouldFavorPostInc.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Scheduling/TargetTransformInfo/shouldFavorPostInc.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/CallLowering/CallLowering.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/CallLowering/CallLowering.cpp new file mode 100644 index 0000000000000000000000000000000000000000..90829bbc2f32e1f7018b1e63e73338c2bb6df8d3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/CallLowering/CallLowering.cpp @@ -0,0 +1,2 @@ +MipsCallLowering::MipsCallLowering(const MipsTargetLowering &TLI) : CallLowering(&TLI) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/CallLowering/lowerCall.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/CallLowering/lowerCall.cpp new file mode 100644 index 0000000000000000000000000000000000000000..99874c4d2466cbcdbe62fc4abe7ad4b4a0994fb8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/CallLowering/lowerCall.cpp @@ -0,0 +1,95 @@ +bool MipsCallLowering::lowerCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info) const { + if (Info.CallConv != CallingConv::C) + return false; + for (auto &Arg : Info.OrigArgs) { + if (!isSupportedArgumentType(Arg.Ty)) + return false; + if (Arg.Flags[0].isByVal()) + return false; + if (Arg.Flags[0].isSRet() && !Arg.Ty->isPointerTy()) + return false; + } + if (!Info.OrigRet.Ty->isVoidTy() && !isSupportedReturnType(Info.OrigRet.Ty)) + return false; + MachineFunction &MF = MIRBuilder.getMF(); + const Function &F = MF.getFunction(); + const DataLayout &DL = MF.getDataLayout(); + const MipsTargetLowering &TLI = *getTLI(); + const MipsTargetMachine &TM = static_cast(MF.getTarget()); + const MipsABIInfo &ABI = TM.getABI(); + MachineInstrBuilder CallSeqStart = MIRBuilder.buildInstr(Mips::ADJCALLSTACKDOWN); + const bool IsCalleeGlobalPIC = Info.Callee.isGlobal() && TM.isPositionIndependent(); + MachineInstrBuilder MIB = MIRBuilder.buildInstrNoInsert(Info.Callee.isReg() || IsCalleeGlobalPIC ? Mips::JALRPseudo : Mips::JAL); + MIB.addDef(Mips::SP, RegState::Implicit); + if (IsCalleeGlobalPIC) { + Register CalleeReg = MF.getRegInfo().createGenericVirtualRegister(LLT::pointer(0, 32)); + MachineInstr *CalleeGlobalValue = MIRBuilder.buildGlobalValue(CalleeReg, Info.Callee.getGlobal()); + if (!Info.Callee.getGlobal()->hasLocalLinkage()) + CalleeGlobalValue->getOperand(1).setTargetFlags(MipsII::MO_GOT_CALL); + MIB.addUse(CalleeReg); + } + else + MIB.add(Info.Callee); + const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); + MIB.addRegMask(TRI->getCallPreservedMask(MF, F.getCallingConv())); + TargetLowering::ArgListTy FuncOrigArgs; + FuncOrigArgs.reserve(Info.OrigArgs.size()); + SmallVector ArgInfos; + SmallVector OrigArgIndices; + unsigned i = 0; + for (auto &Arg : Info.OrigArgs) { + TargetLowering::ArgListEntry Entry; + Entry.Ty = Arg.Ty; + FuncOrigArgs.push_back(Entry); + ArgInfos.push_back(Arg); + OrigArgIndices.push_back(i); + ++i; + } + SmallVector Outs; + subTargetRegTypeForCallingConv(F, ArgInfos, OrigArgIndices, Outs); + SmallVector ArgLocs; + bool IsCalleeVarArg = false; + if (Info.Callee.isGlobal()) { + const Function *CF = static_cast(Info.Callee.getGlobal()); + IsCalleeVarArg = CF->isVarArg(); + } + MipsCCState CCInfo(F.getCallingConv(), IsCalleeVarArg, MF, ArgLocs, F.getContext()); + CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(Info.CallConv), Align(1)); + const char *Call = Info.Callee.isSymbol() ? Info.Callee.getSymbolName() : nullptr; + CCInfo.AnalyzeCallOperands(Outs, TLI.CCAssignFnForCall(), FuncOrigArgs, Call); + setLocInfo(ArgLocs, Outs); + MipsOutgoingValueHandler RetHandler(MIRBuilder, MF.getRegInfo(), MIB); + if (!RetHandler.handle(ArgLocs, ArgInfos)) { + return false; + } + unsigned NextStackOffset = CCInfo.getNextStackOffset(); + const TargetFrameLowering *TFL = MF.getSubtarget().getFrameLowering(); + unsigned StackAlignment = TFL->getStackAlignment(); + NextStackOffset = alignTo(NextStackOffset, StackAlignment); + CallSeqStart.addImm(NextStackOffset).addImm(0); + if (IsCalleeGlobalPIC) { + MIRBuilder.buildCopy(Register(Mips::GP), MF.getInfo()->getGlobalBaseRegForGlobalISel(MF)); + MIB.addDef(Mips::GP, RegState::Implicit); + } + MIRBuilder.insertInstr(MIB); + if (MIB->getOpcode() == Mips::JALRPseudo) { + const MipsSubtarget &STI = static_cast(MIRBuilder.getMF().getSubtarget()); + MIB.constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(), *STI.getRegBankInfo()); + } + if (!Info.OrigRet.Ty->isVoidTy()) { + ArgInfos.clear(); + SmallVector OrigRetIndices; + splitToValueTypes(DL, Info.OrigRet, 0, ArgInfos, OrigRetIndices); + SmallVector Ins; + subTargetRegTypeForCallingConv(F, ArgInfos, OrigRetIndices, Ins); + SmallVector ArgLocs; + MipsCCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs, F.getContext()); + CCInfo.AnalyzeCallResult(Ins, TLI.CCAssignFnForReturn(), Info.OrigRet.Ty, Call); + setLocInfo(ArgLocs, Ins); + CallReturnHandler Handler(MIRBuilder, MF.getRegInfo(), MIB); + if (!Handler.handle(ArgLocs, ArgInfos)) + return false; + } + MIRBuilder.buildInstr(Mips::ADJCALLSTACKUP).addImm(NextStackOffset).addImm(0); + return true; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/CallLowering/lowerFormalArguments.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/CallLowering/lowerFormalArguments.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4868c10586ca16cd0b682161b6b5ac7e1e639036 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/CallLowering/lowerFormalArguments.cpp @@ -0,0 +1,57 @@ +bool MipsCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef> VRegs, FunctionLoweringInfo &FLI) const { + if (F.arg_empty()) + return true; + for (auto &Arg : F.args()) { + if (!isSupportedArgumentType(Arg.getType())) + return false; + } + MachineFunction &MF = MIRBuilder.getMF(); + const DataLayout &DL = MF.getDataLayout(); + const MipsTargetLowering &TLI = *getTLI(); + SmallVector ArgInfos; + SmallVector OrigArgIndices; + unsigned i = 0; + for (auto &Arg : F.args()) { + ArgInfo AInfo(VRegs[i], Arg.getType()); + setArgFlags(AInfo, i + AttributeList::FirstArgIndex, DL, F); + ArgInfos.push_back(AInfo); + OrigArgIndices.push_back(i); + ++i; + } + SmallVector Ins; + subTargetRegTypeForCallingConv(F, ArgInfos, OrigArgIndices, Ins); + SmallVector ArgLocs; + MipsCCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs, F.getContext()); + const MipsTargetMachine &TM = static_cast(MF.getTarget()); + const MipsABIInfo &ABI = TM.getABI(); + CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(F.getCallingConv()), Align(1)); + CCInfo.AnalyzeFormalArguments(Ins, TLI.CCAssignFnForCall()); + setLocInfo(ArgLocs, Ins); + MipsIncomingValueHandler Handler(MIRBuilder, MF.getRegInfo()); + if (!Handler.handle(ArgLocs, ArgInfos)) + return false; + if (F.isVarArg()) { + ArrayRef ArgRegs = ABI.GetVarArgRegs(); + unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs); + int VaArgOffset; + unsigned RegSize = 4; + if (ArgRegs.size() == Idx) + VaArgOffset = alignTo(CCInfo.getNextStackOffset(), RegSize); + else { + VaArgOffset = (int)ABI.GetCalleeAllocdArgSizeInBytes(CCInfo.getCallingConv()) - (int)(RegSize * (ArgRegs.size() - Idx)); + } + MachineFrameInfo &MFI = MF.getFrameInfo(); + int FI = MFI.CreateFixedObject(RegSize, VaArgOffset, true); + MF.getInfo()->setVarArgsFrameIndex(FI); + for (unsigned I = Idx; I < ArgRegs.size(); ++I, VaArgOffset += RegSize) { + MIRBuilder.getMBB().addLiveIn(ArgRegs[I]); + MachineInstrBuilder Copy = MIRBuilder.buildCopy(LLT::scalar(RegSize * 8), Register(ArgRegs[I])); + FI = MFI.CreateFixedObject(RegSize, VaArgOffset, true); + MachinePointerInfo MPO = MachinePointerInfo::getFixedStack(MF, FI); + MachineInstrBuilder FrameIndex = MIRBuilder.buildFrameIndex(LLT::pointer(MPO.getAddrSpace(), 32), FI); + MachineMemOperand *MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOStore, RegSize, Align(RegSize)); + MIRBuilder.buildStore(Copy, FrameIndex, *MMO); + } + } + return true; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/CallLowering/lowerReturn.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/CallLowering/lowerReturn.cpp new file mode 100644 index 0000000000000000000000000000000000000000..66034aff8f85ce0f2fd76b08013c3be1992ec37d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/CallLowering/lowerReturn.cpp @@ -0,0 +1,28 @@ +bool MipsCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val, ArrayRef VRegs, FunctionLoweringInfo &FLI) const { + MachineInstrBuilder Ret = MIRBuilder.buildInstrNoInsert(Mips::RetRA); + if (Val != nullptr && !isSupportedReturnType(Val->getType())) + return false; + if (!VRegs.empty()) { + MachineFunction &MF = MIRBuilder.getMF(); + const Function &F = MF.getFunction(); + const DataLayout &DL = MF.getDataLayout(); + const MipsTargetLowering &TLI = *getTLI(); + SmallVector RetInfos; + SmallVector OrigArgIndices; + ArgInfo ArgRetInfo(VRegs, Val->getType()); + setArgFlags(ArgRetInfo, AttributeList::ReturnIndex, DL, F); + splitToValueTypes(DL, ArgRetInfo, 0, RetInfos, OrigArgIndices); + SmallVector Outs; + subTargetRegTypeForCallingConv(F, RetInfos, OrigArgIndices, Outs); + SmallVector ArgLocs; + MipsCCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs, F.getContext()); + CCInfo.AnalyzeReturn(Outs, TLI.CCAssignFnForReturn()); + setLocInfo(ArgLocs, Outs); + MipsOutgoingValueHandler RetHandler(MIRBuilder, MF.getRegInfo(), Ret); + if (!RetHandler.handle(ArgLocs, RetInfos)) { + return false; + } + } + MIRBuilder.insertInstr(Ret); + return true; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/FrameLowering/FrameLowering.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/FrameLowering/FrameLowering.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b384d32685bad5866f04b66f1bea348030208c0d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/FrameLowering/FrameLowering.cpp @@ -0,0 +1,2 @@ +explicit MipsFrameLowering(const MipsSubtarget &sti, Align Alignment) : TargetFrameLowering(StackGrowsDown, Alignment, 0, Alignment), STI(sti) { +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/FrameLowering/adjustReg.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/FrameLowering/adjustReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/FrameLowering/adjustReg.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/FrameLowering/canUseAsEpilogue.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/FrameLowering/canUseAsEpilogue.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/FrameLowering/canUseAsEpilogue.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/FrameLowering/canUseAsPrologue.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/FrameLowering/canUseAsPrologue.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d24252a436720a3ccdecb69c990fff58341ff97c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/FrameLowering/canUseAsPrologue.cpp @@ -0,0 +1,2 @@ +None + diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/FrameLowering/determineCalleeSaves.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/FrameLowering/determineCalleeSaves.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0c7be3a46a081dd318f6d9cb6c1c8652f9ee3d8a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/FrameLowering/determineCalleeSaves.cpp @@ -0,0 +1,31 @@ +void MipsSEFrameLowering::determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS) const { + TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS); + const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); + MipsFunctionInfo *MipsFI = MF.getInfo(); + MipsABIInfo ABI = STI.getABI(); + unsigned RA = ABI.IsN64() ? Mips::RA_64 : Mips::RA; + unsigned FP = ABI.GetFramePtr(); + unsigned BP = ABI.IsN64() ? Mips::S7_64 : Mips::S7; + if (hasFP(MF)) { + setAliasRegs(MF, SavedRegs, RA); + setAliasRegs(MF, SavedRegs, FP); + } + if (hasBP(MF)) + setAliasRegs(MF, SavedRegs, BP); + if (MipsFI->callsEhReturn()) + MipsFI->createEhDataRegsFI(MF); + if (MipsFI->isISR()) + MipsFI->createISRRegFI(MF); + if (ExpandPseudo(MF).expand()) { + const TargetRegisterClass &RC = STI.isGP64bit() ? Mips::GPR64RegClass : Mips::GPR32RegClass; + int FI = MF.getFrameInfo().CreateStackObject(TRI->getSpillSize(RC), TRI->getSpillAlign(RC), false); + RS->addScavengingFrameIndex(FI); + } + uint64_t MaxSPOffset = estimateStackSize(MF); + if (isIntN(STI.hasMSA() ? 10 : 16, MaxSPOffset) && !MF.getFrameInfo().hasVarSizedObjects()) + return; + const TargetRegisterClass &RC = ABI.ArePtrs64bit() ? Mips::GPR64RegClass : Mips::GPR32RegClass; + int FI = MF.getFrameInfo().CreateStackObject(TRI->getSpillSize(RC),TRI->getSpillAlign(RC), false); + RS->addScavengingFrameIndex(FI); +} + diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/FrameLowering/eliminateCallFramePseudoInstr.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/FrameLowering/eliminateCallFramePseudoInstr.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6b1f59ca8eacf87fd0c630d96c6589f6dca5e270 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/FrameLowering/eliminateCallFramePseudoInstr.cpp @@ -0,0 +1,10 @@ +MachineBasicBlock::iterator MipsFrameLowering::eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const { + unsigned SP = STI.getABI().IsN64() ? Mips::SP_64 : Mips::SP; + if (!hasReservedCallFrame(MF)) { + int64_t Amount = I->getOperand(0).getImm(); + if (I->getOpcode() == Mips::ADJCALLSTACKDOWN) + Amount = -Amount; + STI.getInstrInfo()->adjustStackPtr(SP, Amount, MBB, I); + } + return MBB.erase(I); +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/FrameLowering/emitEpilogue.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/FrameLowering/emitEpilogue.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fecd648fee2494cb011a5cd242be9efbd0d7efe2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/FrameLowering/emitEpilogue.cpp @@ -0,0 +1,35 @@ +void MipsSEFrameLowering::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { + MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator(); + MachineFrameInfo &MFI = MF.getFrameInfo(); + MipsFunctionInfo *MipsFI = MF.getInfo(); + const MipsSEInstrInfo &TII = *static_cast(STI.getInstrInfo()); + const MipsRegisterInfo &RegInfo = *static_cast(STI.getRegisterInfo()); + DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); + MipsABIInfo ABI = STI.getABI(); + unsigned SP = ABI.GetStackPtr(); + unsigned FP = ABI.GetFramePtr(); + unsigned ZERO = ABI.GetNullPtr(); + unsigned MOVE = ABI.GetGPRMoveOp(); + if (hasFP(MF)) { + MachineBasicBlock::iterator I = MBBI; + for (unsigned i = 0; i < MFI.getCalleeSavedInfo().size(); ++i) + --I; + BuildMI(MBB, I, DL, TII.get(MOVE), SP).addReg(FP).addReg(ZERO); + } + if (MipsFI->callsEhReturn()) { + const TargetRegisterClass *RC = ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; + MachineBasicBlock::iterator I = MBBI; + for (unsigned i = 0; i < MFI.getCalleeSavedInfo().size(); ++i) + --I; + for (int J = 0; J < 4; ++J) { + TII.loadRegFromStackSlot(MBB, I, ABI.GetEhDataReg(J), MipsFI->getEhDataRegFI(J), RC, &RegInfo); + } + } + if (MF.getFunction().hasFnAttribute("interrupt")) + emitInterruptEpilogueStub(MF, MBB); + uint64_t StackSize = MFI.getStackSize(); + if (!StackSize) + return; + TII.adjustStackPtr(SP, StackSize, MBB, MBBI); +} + diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/FrameLowering/emitPrologue.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/FrameLowering/emitPrologue.cpp new file mode 100644 index 0000000000000000000000000000000000000000..04cc5f5bac4d52157c1c5891a8c7a3810d0c6ef0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/FrameLowering/emitPrologue.cpp @@ -0,0 +1,88 @@ +void MipsSEFrameLowering::emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const { + MachineFrameInfo &MFI = MF.getFrameInfo(); + MipsFunctionInfo *MipsFI = MF.getInfo(); + const MipsSEInstrInfo &TII = *static_cast(STI.getInstrInfo()); + const MipsRegisterInfo &RegInfo = *static_cast(STI.getRegisterInfo()); + MachineBasicBlock::iterator MBBI = MBB.begin(); + DebugLoc dl; + MipsABIInfo ABI = STI.getABI(); + unsigned SP = ABI.GetStackPtr(); + unsigned FP = ABI.GetFramePtr(); + unsigned ZERO = ABI.GetNullPtr(); + unsigned MOVE = ABI.GetGPRMoveOp(); + unsigned ADDiu = ABI.GetPtrAddiuOp(); + unsigned AND = ABI.IsN64() ? Mips::AND64 : Mips::AND; + const TargetRegisterClass *RC = ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; + uint64_t StackSize = MFI.getStackSize(); + if (StackSize == 0 && !MFI.adjustsStack()) + return; + MachineModuleInfo &MMI = MF.getMMI(); + const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); + TII.adjustStackPtr(SP, -StackSize, MBB, MBBI); + unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, StackSize)); + BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)).addCFIIndex(CFIIndex); + if (MF.getFunction().hasFnAttribute("interrupt")) + emitInterruptPrologueStub(MF, MBB); + const std::vector &CSI = MFI.getCalleeSavedInfo(); + if (!CSI.empty()) { + for (unsigned i = 0; i < CSI.size(); ++i) + ++MBBI; + for (std::vector::const_iterator I = CSI.begin(), E = CSI.end(); I != E; ++I) { + int64_t Offset = MFI.getObjectOffset(I->getFrameIdx()); + unsigned Reg = I->getReg(); + if (Mips::AFGR64RegClass.contains(Reg)) { + unsigned Reg0 = MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_lo), true); + unsigned Reg1 = MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_hi), true); + if (!STI.isLittle()) + std::swap(Reg0, Reg1); + unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(nullptr, Reg0, Offset)); + BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)).addCFIIndex(CFIIndex); + CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4)); + BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)).addCFIIndex(CFIIndex); + } + else if (Mips::FGR64RegClass.contains(Reg)) { + unsigned Reg0 = MRI->getDwarfRegNum(Reg, true); + unsigned Reg1 = MRI->getDwarfRegNum(Reg, true) + 1; + if (!STI.isLittle()) + std::swap(Reg0, Reg1); + unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(nullptr, Reg0, Offset)); + BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)).addCFIIndex(CFIIndex); + CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4)); + BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)).addCFIIndex(CFIIndex); + } + else { + unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(nullptr, MRI->getDwarfRegNum(Reg, true), Offset)); + BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)).addCFIIndex(CFIIndex); + } + } + } + if (MipsFI->callsEhReturn()) { + for (int I = 0; I < 4; ++I) { + if (!MBB.isLiveIn(ABI.GetEhDataReg(I))) + MBB.addLiveIn(ABI.GetEhDataReg(I)); + TII.storeRegToStackSlot(MBB, MBBI, ABI.GetEhDataReg(I), false, MipsFI->getEhDataRegFI(I), RC, &RegInfo); + } + for (int I = 0; I < 4; ++I) { + int64_t Offset = MFI.getObjectOffset(MipsFI->getEhDataRegFI(I)); + unsigned Reg = MRI->getDwarfRegNum(ABI.GetEhDataReg(I), true); + unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(nullptr, Reg, Offset)); + BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)).addCFIIndex(CFIIndex); + } + } + if (hasFP(MF)) { + BuildMI(MBB, MBBI, dl, TII.get(MOVE), FP).addReg(SP).addReg(ZERO).setMIFlag(MachineInstr::FrameSetup); + unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfaRegister( nullptr, MRI->getDwarfRegNum(FP, true))); + BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)).addCFIIndex(CFIIndex); + if (RegInfo.needsStackRealignment(MF)) { + Register VR = MF.getRegInfo().createVirtualRegister(RC); + assert((Log2(MFI.getMaxAlign()) < 16) && "Function's alignment size requirement is not supported."); + int64_t MaxAlign = -(int64_t)MFI.getMaxAlign().value(); + BuildMI(MBB, MBBI, dl, TII.get(ADDiu), VR).addReg(ZERO).addImm(MaxAlign); + BuildMI(MBB, MBBI, dl, TII.get(AND), SP).addReg(SP).addReg(VR); + if (hasBP(MF)) { + unsigned BP = STI.isABI_N64() ? Mips::S7_64 : Mips::S7; + BuildMI(MBB, MBBI, dl, TII.get(MOVE), BP).addReg(SP).addReg(ZERO); + } + } + } +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/FrameLowering/getFrameIndexReference.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/FrameLowering/getFrameIndexReference.cpp new file mode 100644 index 0000000000000000000000000000000000000000..96cd6c3b3e00e732bf4cc98667e6b6cc7d664c40 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/FrameLowering/getFrameIndexReference.cpp @@ -0,0 +1,9 @@ +StackOffset MipsSEFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg) const { + const MachineFrameInfo &MFI = MF.getFrameInfo(); + MipsABIInfo ABI = STI.getABI(); + if (MFI.isFixedObjectIndex(FI)) + FrameReg = hasFP(MF) ? ABI.GetFramePtr() : ABI.GetStackPtr(); + else + FrameReg = hasBP(MF) ? ABI.GetBasePtr() : ABI.GetStackPtr(); + return StackOffset::getFixed(MFI.getObjectOffset(FI) + MFI.getStackSize() - getOffsetOfLocalArea() + MFI.getOffsetAdjustment()); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/FrameLowering/hasBP.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/FrameLowering/hasBP.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a6469c7a278c038c82567ff8856bedb6dadf7202 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/FrameLowering/hasBP.cpp @@ -0,0 +1,5 @@ +bool MipsFrameLowering::hasBP(const MachineFunction &MF) const { + const MachineFrameInfo &MFI = MF.getFrameInfo(); + const TargetRegisterInfo *TRI = STI.getRegisterInfo(); + return MFI.hasVarSizedObjects() && TRI->needsStackRealignment(MF); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/FrameLowering/hasFP.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/FrameLowering/hasFP.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2984a24fb87e41d561111fe745a031a4ae00d2f8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/FrameLowering/hasFP.cpp @@ -0,0 +1,5 @@ +bool MipsFrameLowering::hasFP(const MachineFunction &MF) const { + const MachineFrameInfo &MFI = MF.getFrameInfo(); + const TargetRegisterInfo *TRI = STI.getRegisterInfo(); + return MF.getTarget().Options.DisableFramePointerElim(MF) || MFI.hasVarSizedObjects() || MFI.isFrameAddressTaken() || TRI->needsStackRealignment(MF); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/FrameLowering/hasReservedCallFrame.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/FrameLowering/hasReservedCallFrame.cpp new file mode 100644 index 0000000000000000000000000000000000000000..97a97d73efcd689066a40c08ef80ad03f0f94706 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/FrameLowering/hasReservedCallFrame.cpp @@ -0,0 +1,4 @@ +bool MipsSEFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const { + const MachineFrameInfo &MFI = MF.getFrameInfo(); + return isInt<16>(MFI.getMaxCallFrameSize() + getStackAlignment()) && !MFI.hasVarSizedObjects(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/FrameLowering/processFunctionBeforeFrameFinalized.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/FrameLowering/processFunctionBeforeFrameFinalized.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/FrameLowering/processFunctionBeforeFrameFinalized.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/FrameLowering/restoreCalleeSavedRegisters.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/FrameLowering/restoreCalleeSavedRegisters.cpp new file mode 100644 index 0000000000000000000000000000000000000000..39a52f6a3ffb6bddaec5669406257eaaf8382c20 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/FrameLowering/restoreCalleeSavedRegisters.cpp @@ -0,0 +1,3 @@ +bool Mips16FrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, MutableArrayRef CSI, const TargetRegisterInfo *TRI) const { + return true; +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/FrameLowering/spillCalleeSavedRegisters.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/FrameLowering/spillCalleeSavedRegisters.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d7ccdfa1edf7514e9f46b468c4a170614877a6c7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/FrameLowering/spillCalleeSavedRegisters.cpp @@ -0,0 +1,29 @@ +bool MipsSEFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef CSI, const TargetRegisterInfo *TRI) const { + MachineFunction *MF = MBB.getParent(); + const TargetInstrInfo &TII = *STI.getInstrInfo(); + for (unsigned i = 0, e = CSI.size(); i != e; ++i) { + unsigned Reg = CSI[i].getReg(); + bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA || Reg == Mips::RA_64) && MF->getFrameInfo().isReturnAddressTaken(); + if (!IsRAAndRetAddrIsTaken) + MBB.addLiveIn(Reg); + bool IsLOHI = (Reg == Mips::LO0 || Reg == Mips::LO0_64 || Reg == Mips::HI0 || Reg == Mips::HI0_64); + const Function &Func = MBB.getParent()->getFunction(); + if (IsLOHI && Func.hasFnAttribute("interrupt")) { + DebugLoc DL = MI->getDebugLoc(); + unsigned Op = 0; + if (!STI.getABI().ArePtrs64bit()) { + Op = (Reg == Mips::HI0) ? Mips::MFHI : Mips::MFLO; + Reg = Mips::K0; + } + else { + Op = (Reg == Mips::HI0) ? Mips::MFHI64 : Mips::MFLO64; + Reg = Mips::K0_64; + } + BuildMI(MBB, MI, DL, TII.get(Op), Mips::K0).setMIFlag(MachineInstr::FrameSetup); + } + bool IsKill = !IsRAAndRetAddrIsTaken; + const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); + TII.storeRegToStackSlot(MBB, MI, Reg, IsKill, CSI[i].getFrameIdx(), RC, TRI); + } + return true; +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelDAGToDAG/DAGToDAGISel.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelDAGToDAG/DAGToDAGISel.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5a7fcbbf66a18053cbb09eb170938804acb78987 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelDAGToDAG/DAGToDAGISel.cpp @@ -0,0 +1,2 @@ +explicit MipsSEDAGToDAGISel(MipsTargetMachine &TM, CodeGenOpt::Level OL) : MipsDAGToDAGISel(TM, OL) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelDAGToDAG/MatchSLLIUW.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelDAGToDAG/MatchSLLIUW.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelDAGToDAG/MatchSLLIUW.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelDAGToDAG/MatchSRLIUW.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelDAGToDAG/MatchSRLIUW.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelDAGToDAG/MatchSRLIUW.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelDAGToDAG/PostprocessISelDAG.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelDAGToDAG/PostprocessISelDAG.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelDAGToDAG/PostprocessISelDAG.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelDAGToDAG/Select.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelDAGToDAG/Select.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelDAGToDAG/Select.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelDAGToDAG/SelectAddrFI.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelDAGToDAG/SelectAddrFI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelDAGToDAG/SelectAddrFI.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelDAGToDAG/SelectInlineAsmMemoryOperand.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelDAGToDAG/SelectInlineAsmMemoryOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d342f74eef8e6835cb6a33677db55fb78cb5d785 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelDAGToDAG/SelectInlineAsmMemoryOperand.cpp @@ -0,0 +1,50 @@ +bool MipsSEDAGToDAGISel::SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, std::vector &OutOps) { + SDValue Base, Offset; + switch(ConstraintID) { + default: + llvm_unreachable("Unexpected asm memory constraint"); + case InlineAsm::Constraint_m: + case InlineAsm::Constraint_o: + if (selectAddrRegImm16(Op, Base, Offset)) { + OutOps.push_back(Base); + OutOps.push_back(Offset); + return false; + } + OutOps.push_back(Op); + OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32)); + return false; + case InlineAsm::Constraint_R: + if (selectAddrRegImm9(Op, Base, Offset)) { + OutOps.push_back(Base); + OutOps.push_back(Offset); + return false; + } + OutOps.push_back(Op); + OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32)); + return false; + case InlineAsm::Constraint_ZC: + if (Subtarget->inMicroMipsMode()) { + if (selectAddrRegImm12(Op, Base, Offset)) { + OutOps.push_back(Base); + OutOps.push_back(Offset); + return false; + } + } + else if (Subtarget->hasMips32r6()) { + if (selectAddrRegImm9(Op, Base, Offset)) { + OutOps.push_back(Base); + OutOps.push_back(Offset); + return false; + } + } + else if (selectAddrRegImm16(Op, Base, Offset)) { + OutOps.push_back(Base); + OutOps.push_back(Offset); + return false; + } + OutOps.push_back(Op); + OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32)); + return false; + } + return true; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelDAGToDAG/createISelDag.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelDAGToDAG/createISelDag.cpp new file mode 100644 index 0000000000000000000000000000000000000000..36e8855eb544200582451f8c21a565df6b7b9a48 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelDAGToDAG/createISelDag.cpp @@ -0,0 +1,3 @@ +FunctionPass *llvm::createMipsSEISelDag(MipsTargetMachine &TM, CodeGenOpt::Level OptLevel) { + return new MipsSEDAGToDAGISel(TM, OptLevel); +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelDAGToDAG/getPassName.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelDAGToDAG/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5049e898a5b33a064ed6484e2e7cf1667997bef8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelDAGToDAG/getPassName.cpp @@ -0,0 +1,3 @@ +StringRef getPassName() const override { + return "MIPS DAG->DAG Pattern Instruction Selection"; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelDAGToDAG/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelDAGToDAG/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..23043d2db6c9d6e9b1f35cdf3b44609cf5975340 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelDAGToDAG/runOnMachineFunction.cpp @@ -0,0 +1,7 @@ +bool MipsModuleDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) { + LLVM_DEBUG(errs() << "In MipsModuleDAGToDAGISel::runMachineFunction\n"); + auto &TPC = getAnalysis(); + auto &TM = TPC.getTM(); + TM.resetSubtarget(&MF); + return false; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelDAGToDAG/selectVLOp.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelDAGToDAG/selectVLOp.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d24252a436720a3ccdecb69c990fff58341ff97c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelDAGToDAG/selectVLOp.cpp @@ -0,0 +1,2 @@ +None + diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelDAGToDAG/selectVSplat.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelDAGToDAG/selectVSplat.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3ddc959d5cec6fb8668b07d516cd6e866a0989a0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelDAGToDAG/selectVSplat.cpp @@ -0,0 +1,14 @@ +bool MipsSEDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm, unsigned MinSizeInBits) const { + if (!Subtarget->hasMSA()) + return false; + BuildVectorSDNode *Node = dyn_cast(N); + if (!Node) + return false; + APInt SplatValue, SplatUndef; + unsigned SplatBitSize; + bool HasAnyUndefs; + if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs, MinSizeInBits, !Subtarget->isLittle())) + return false; + Imm = SplatValue; + return true; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelDAGToDAG/selectVSplatSimm5.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelDAGToDAG/selectVSplatSimm5.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e86a8153fbab9c79b9ea14bfbc050c061ff370fd --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelDAGToDAG/selectVSplatSimm5.cpp @@ -0,0 +1,4 @@ +bool MipsDAGToDAGISel::selectVSplatSimm5(SDValue N, SDValue &Imm) const { + llvm_unreachable("Unimplemented function."); + return false; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelDAGToDAG/selectVSplatUimm5.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelDAGToDAG/selectVSplatUimm5.cpp new file mode 100644 index 0000000000000000000000000000000000000000..02c4b950f0aa45a72a3ed3b1bce2af4f5eb6cd6a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelDAGToDAG/selectVSplatUimm5.cpp @@ -0,0 +1,4 @@ +bool MipsDAGToDAGISel::selectVSplatUimm5(SDValue N, SDValue &Imm) const { + llvm_unreachable("Unimplemented function."); + return false; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/CanLowerReturn.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/CanLowerReturn.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e857257cc58f086519f5aa8fb47b84c794ac83d0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/CanLowerReturn.cpp @@ -0,0 +1,5 @@ +bool MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg, const SmallVectorImpl &Outs, LLVMContext &Context) const { + SmallVector RVLocs; + MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context); + return CCInfo.CheckReturn(Outs, RetCC_Mips); +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/ComputeNumSignBitsForTargetNode.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/ComputeNumSignBitsForTargetNode.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/ComputeNumSignBitsForTargetNode.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/EmitInstrWithCustomInserter.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/EmitInstrWithCustomInserter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c7a577133ff50ac6ce86af208c82aec90f270744 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/EmitInstrWithCustomInserter.cpp @@ -0,0 +1,154 @@ +MachineBasicBlock *MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const { + switch (MI.getOpcode()) { + default: + llvm_unreachable("Unexpected instr type to insert"); + case Mips::ATOMIC_LOAD_ADD_I8: + return emitAtomicBinaryPartword(MI, BB, 1); + case Mips::ATOMIC_LOAD_ADD_I16: + return emitAtomicBinaryPartword(MI, BB, 2); + case Mips::ATOMIC_LOAD_ADD_I32: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_LOAD_ADD_I64: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_LOAD_AND_I8: + return emitAtomicBinaryPartword(MI, BB, 1); + case Mips::ATOMIC_LOAD_AND_I16: + return emitAtomicBinaryPartword(MI, BB, 2); + case Mips::ATOMIC_LOAD_AND_I32: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_LOAD_AND_I64: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_LOAD_OR_I8: + return emitAtomicBinaryPartword(MI, BB, 1); + case Mips::ATOMIC_LOAD_OR_I16: + return emitAtomicBinaryPartword(MI, BB, 2); + case Mips::ATOMIC_LOAD_OR_I32: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_LOAD_OR_I64: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_LOAD_XOR_I8: + return emitAtomicBinaryPartword(MI, BB, 1); + case Mips::ATOMIC_LOAD_XOR_I16: + return emitAtomicBinaryPartword(MI, BB, 2); + case Mips::ATOMIC_LOAD_XOR_I32: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_LOAD_XOR_I64: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_LOAD_NAND_I8: + return emitAtomicBinaryPartword(MI, BB, 1); + case Mips::ATOMIC_LOAD_NAND_I16: + return emitAtomicBinaryPartword(MI, BB, 2); + case Mips::ATOMIC_LOAD_NAND_I32: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_LOAD_NAND_I64: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_LOAD_SUB_I8: + return emitAtomicBinaryPartword(MI, BB, 1); + case Mips::ATOMIC_LOAD_SUB_I16: + return emitAtomicBinaryPartword(MI, BB, 2); + case Mips::ATOMIC_LOAD_SUB_I32: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_LOAD_SUB_I64: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_SWAP_I8: + return emitAtomicBinaryPartword(MI, BB, 1); + case Mips::ATOMIC_SWAP_I16: + return emitAtomicBinaryPartword(MI, BB, 2); + case Mips::ATOMIC_SWAP_I32: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_SWAP_I64: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_CMP_SWAP_I8: + return emitAtomicCmpSwapPartword(MI, BB, 1); + case Mips::ATOMIC_CMP_SWAP_I16: + return emitAtomicCmpSwapPartword(MI, BB, 2); + case Mips::ATOMIC_CMP_SWAP_I32: + return emitAtomicCmpSwap(MI, BB); + case Mips::ATOMIC_CMP_SWAP_I64: + return emitAtomicCmpSwap(MI, BB); + case Mips::ATOMIC_LOAD_MIN_I8: + return emitAtomicBinaryPartword(MI, BB, 1); + case Mips::ATOMIC_LOAD_MIN_I16: + return emitAtomicBinaryPartword(MI, BB, 2); + case Mips::ATOMIC_LOAD_MIN_I32: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_LOAD_MIN_I64: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_LOAD_MAX_I8: + return emitAtomicBinaryPartword(MI, BB, 1); + case Mips::ATOMIC_LOAD_MAX_I16: + return emitAtomicBinaryPartword(MI, BB, 2); + case Mips::ATOMIC_LOAD_MAX_I32: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_LOAD_MAX_I64: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_LOAD_UMIN_I8: + return emitAtomicBinaryPartword(MI, BB, 1); + case Mips::ATOMIC_LOAD_UMIN_I16: + return emitAtomicBinaryPartword(MI, BB, 2); + case Mips::ATOMIC_LOAD_UMIN_I32: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_LOAD_UMIN_I64: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_LOAD_UMAX_I8: + return emitAtomicBinaryPartword(MI, BB, 1); + case Mips::ATOMIC_LOAD_UMAX_I16: + return emitAtomicBinaryPartword(MI, BB, 2); + case Mips::ATOMIC_LOAD_UMAX_I32: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_LOAD_UMAX_I64: + return emitAtomicBinary(MI, BB); + case Mips::PseudoSDIV: + case Mips::PseudoUDIV: + case Mips::DIV: + case Mips::DIVU: + case Mips::MOD: + case Mips::MODU: + return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, false); + case Mips::SDIV_MM_Pseudo: + case Mips::UDIV_MM_Pseudo: + case Mips::SDIV_MM: + case Mips::UDIV_MM: + case Mips::DIV_MMR6: + case Mips::DIVU_MMR6: + case Mips::MOD_MMR6: + case Mips::MODU_MMR6: + return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, true); + case Mips::PseudoDSDIV: + case Mips::PseudoDUDIV: + case Mips::DDIV: + case Mips::DDIVU: + case Mips::DMOD: + case Mips::DMODU: + return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, false); + case Mips::PseudoSELECT_I: + case Mips::PseudoSELECT_I64: + case Mips::PseudoSELECT_S: + case Mips::PseudoSELECT_D32: + case Mips::PseudoSELECT_D64: + return emitPseudoSELECT(MI, BB, false, Mips::BNE); + case Mips::PseudoSELECTFP_F_I: + case Mips::PseudoSELECTFP_F_I64: + case Mips::PseudoSELECTFP_F_S: + case Mips::PseudoSELECTFP_F_D32: + case Mips::PseudoSELECTFP_F_D64: + return emitPseudoSELECT(MI, BB, true, Mips::BC1F); + case Mips::PseudoSELECTFP_T_I: + case Mips::PseudoSELECTFP_T_I64: + case Mips::PseudoSELECTFP_T_S: + case Mips::PseudoSELECTFP_T_D32: + case Mips::PseudoSELECTFP_T_D64: + return emitPseudoSELECT(MI, BB, true, Mips::BC1T); + case Mips::PseudoD_SELECT_I: + case Mips::PseudoD_SELECT_I64: + return emitPseudoD_SELECT(MI, BB); + case Mips::LDR_W: + return emitLDR_W(MI, BB); + case Mips::LDR_D: + return emitLDR_D(MI, BB); + case Mips::STR_W: + return emitSTR_W(MI, BB); + case Mips::STR_D: + return emitSTR_D(MI, BB); + } +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/LowerAsmOperandForConstraint.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/LowerAsmOperandForConstraint.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1a35f0f7b2528752ec8bf1cb35bc8dac3d13de61 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/LowerAsmOperandForConstraint.cpp @@ -0,0 +1,86 @@ +void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector&Ops, SelectionDAG &DAG) const { + SDLoc DL(Op); + SDValue Result; + if (Constraint.length() > 1) + return; + char ConstraintLetter = Constraint[0]; + switch (ConstraintLetter) { + default: + break; + case 'I': + if (ConstantSDNode *C = dyn_cast(Op)) { + EVT Type = Op.getValueType(); + int64_t Val = C->getSExtValue(); + if (isInt<16>(Val)) { + Result = DAG.getTargetConstant(Val, DL, Type); + break; + } + } + return; + case 'J': + if (ConstantSDNode *C = dyn_cast(Op)) { + EVT Type = Op.getValueType(); + int64_t Val = C->getZExtValue(); + if (Val == 0) { + Result = DAG.getTargetConstant(0, DL, Type); + break; + } + } + return; + case 'K': + if (ConstantSDNode *C = dyn_cast(Op)) { + EVT Type = Op.getValueType(); + uint64_t Val = (uint64_t)C->getZExtValue(); + if (isUInt<16>(Val)) { + Result = DAG.getTargetConstant(Val, DL, Type); + break; + } + } + return; + case 'L': + if (ConstantSDNode *C = dyn_cast(Op)) { + EVT Type = Op.getValueType(); + int64_t Val = C->getSExtValue(); + if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){ + Result = DAG.getTargetConstant(Val, DL, Type); + break; + } + } + return; + case 'N': + if (ConstantSDNode *C = dyn_cast(Op)) { + EVT Type = Op.getValueType(); + int64_t Val = C->getSExtValue(); + if ((Val >= -65535) && (Val <= -1)) { + Result = DAG.getTargetConstant(Val, DL, Type); + break; + } + } + return; + case 'O': + if (ConstantSDNode *C = dyn_cast(Op)) { + EVT Type = Op.getValueType(); + int64_t Val = C->getSExtValue(); + if ((isInt<15>(Val))) { + Result = DAG.getTargetConstant(Val, DL, Type); + break; + } + } + return; + case 'P': + if (ConstantSDNode *C = dyn_cast(Op)) { + EVT Type = Op.getValueType(); + int64_t Val = C->getSExtValue(); + if ((Val <= 65535) && (Val >= 1)) { + Result = DAG.getTargetConstant(Val, DL, Type); + break; + } + } + return; + } + if (Result.getNode()) { + Ops.push_back(Result); + return; + } + TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/LowerBlockAddress.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/LowerBlockAddress.cpp new file mode 100644 index 0000000000000000000000000000000000000000..63faa865e7326bef8f45aeceafcb0fa0a1c608eb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/LowerBlockAddress.cpp @@ -0,0 +1,7 @@ +SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const { + BlockAddressSDNode *N = cast(Op); + EVT Ty = Op.getValueType(); + if (!isPositionIndependent()) + return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); + return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/LowerCall.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/LowerCall.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e452e8db8b1f84d438f35752f0c4f697f1ca6bd3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/LowerCall.cpp @@ -0,0 +1,194 @@ +SDValue MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl &InVals) const { + SelectionDAG &DAG = CLI.DAG; + SDLoc DL = CLI.DL; + SmallVectorImpl &Outs = CLI.Outs; + SmallVectorImpl &OutVals = CLI.OutVals; + SmallVectorImpl &Ins = CLI.Ins; + SDValue Chain = CLI.Chain; + SDValue Callee = CLI.Callee; + bool &IsTailCall = CLI.IsTailCall; + CallingConv::ID CallConv = CLI.CallConv; + bool IsVarArg = CLI.IsVarArg; + MachineFunction &MF = DAG.getMachineFunction(); + MachineFrameInfo &MFI = MF.getFrameInfo(); + const TargetFrameLowering *TFL = Subtarget.getFrameLowering(); + MipsFunctionInfo *FuncInfo = MF.getInfo(); + bool IsPIC = isPositionIndependent(); + SmallVector ArgLocs; + MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext(), MipsCCState::getSpecialCallingConvForCallee(Callee.getNode(), Subtarget)); + const ExternalSymbolSDNode *ES = dyn_cast_or_null(Callee.getNode()); + bool MemcpyInByVal = ES && StringRef(ES->getSymbol()) == StringRef("memcpy") && CallConv != CallingConv::Fast && Chain.getOpcode() == ISD::CALLSEQ_START; + unsigned ReservedArgArea = MemcpyInByVal ? 0 : ABI.GetCalleeAllocdArgSizeInBytes(CallConv); + CCInfo.AllocateStack(ReservedArgArea, Align(1)); + CCInfo.AnalyzeCallOperands(Outs, CC_Mips, CLI.getArgs(), ES ? ES->getSymbol() : nullptr); + unsigned NextStackOffset = CCInfo.getNextStackOffset(); + MachineFunction::CallSiteInfo CSInfo; + bool InternalLinkage = false; + if (IsTailCall) { + IsTailCall = isEligibleForTailCallOptimization(CCInfo, NextStackOffset, *MF.getInfo()); + if (GlobalAddressSDNode *G = dyn_cast(Callee)) { + InternalLinkage = G->getGlobal()->hasInternalLinkage(); + IsTailCall &= (InternalLinkage || G->getGlobal()->hasLocalLinkage() || G->getGlobal()->hasPrivateLinkage() || G->getGlobal()->hasHiddenVisibility() || G->getGlobal()->hasProtectedVisibility()); + } + } + if (!IsTailCall && CLI.CB && CLI.CB->isMustTailCall()) + report_fatal_error("failed to perform tail call elimination on a call site marked musttail"); + if (IsTailCall) + ++NumTailCalls; + unsigned StackAlignment = TFL->getStackAlignment(); + NextStackOffset = alignTo(NextStackOffset, StackAlignment); + SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, DL, true); + if (!(IsTailCall || MemcpyInByVal)) + Chain = DAG.getCALLSEQ_START(Chain, NextStackOffset, 0, DL); + SDValue StackPtr = DAG.getCopyFromReg(Chain, DL, ABI.IsN64() ? Mips::SP_64 : Mips::SP, getPointerTy(DAG.getDataLayout())); + std::deque> RegsToPass; + SmallVector MemOpChains; + CCInfo.rewindByValRegsInfo(); + for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { + SDValue Arg = OutVals[i]; + CCValAssign &VA = ArgLocs[i]; + MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT(); + ISD::ArgFlagsTy Flags = Outs[i].Flags; + bool UseUpperBits = false; + if (Flags.isByVal()) { + unsigned FirstByValReg, LastByValReg; + unsigned ByValIdx = CCInfo.getInRegsParamsProcessed(); + CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg); + assert(Flags.getByValSize() && "ByVal args of size 0 should have been ignored by front-end."); + assert(ByValIdx < CCInfo.getInRegsParamsCount()); + assert(!IsTailCall && "Do not tail-call optimize if there is a byval argument."); + passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg, FirstByValReg, LastByValReg, Flags, Subtarget.isLittle(), VA); + CCInfo.nextInRegsParam(); + continue; + } + switch (VA.getLocInfo()) { + default: + llvm_unreachable("Unknown loc info!"); + case CCValAssign::Full: + if (VA.isRegLoc()) { + if ((ValVT == MVT::f32 && LocVT == MVT::i32) || (ValVT == MVT::f64 && LocVT == MVT::i64) || (ValVT == MVT::i64 && LocVT == MVT::f64)) + Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg); + else if (ValVT == MVT::f64 && LocVT == MVT::i32) { + SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Arg, DAG.getConstant(0, DL, MVT::i32)); + SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Arg, DAG.getConstant(1, DL, MVT::i32)); + if (!Subtarget.isLittle()) + std::swap(Lo, Hi); + Register LocRegLo = VA.getLocReg(); + unsigned LocRegHigh = getNextIntArgReg(LocRegLo); + RegsToPass.push_back(std::make_pair(LocRegLo, Lo)); + RegsToPass.push_back(std::make_pair(LocRegHigh, Hi)); + continue; + } + } + break; + case CCValAssign::BCvt: + Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg); + break; + case CCValAssign::SExtUpper: + UseUpperBits = true; + LLVM_FALLTHROUGH; + case CCValAssign::SExt: + Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg); + break; + case CCValAssign::ZExtUpper: + UseUpperBits = true; + LLVM_FALLTHROUGH; + case CCValAssign::ZExt: + Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg); + break; + case CCValAssign::AExtUpper: + UseUpperBits = true; + LLVM_FALLTHROUGH; + case CCValAssign::AExt: + Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg); + break; + } + if (UseUpperBits) { + unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits(); + unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); + Arg = DAG.getNode(ISD::SHL, DL, VA.getLocVT(), Arg, DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); + } + if (VA.isRegLoc()) { + RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); + if (Mips::AFGR64RegClass.contains(VA.getLocReg())) + continue; + const TargetOptions &Options = DAG.getTarget().Options; + if (Options.SupportsDebugEntryValues) + CSInfo.emplace_back(VA.getLocReg(), i); + continue; + } + assert(VA.isMemLoc()); + MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(), Chain, Arg, DL, IsTailCall, DAG)); + } + if (!MemOpChains.empty()) + Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains); + EVT Ty = Callee.getValueType(); + bool GlobalOrExternal = false, IsCallReloc = false; + if (!Subtarget.isABICalls() && !IsPIC) { + if (auto *N = dyn_cast(Callee)) { + if (Subtarget.useLongCalls()) + Callee = Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); + } + else if (auto *N = dyn_cast(Callee)) { + bool UseLongCalls = Subtarget.useLongCalls(); + if (auto *F = dyn_cast(N->getGlobal())) { + if (F->hasFnAttribute("long-call")) + UseLongCalls = true; + else if (F->hasFnAttribute("short-call")) + UseLongCalls = false; + } + if (UseLongCalls) + Callee = Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); + } + } + if (GlobalAddressSDNode *G = dyn_cast(Callee)) { + if (IsPIC) { + const GlobalValue *Val = G->getGlobal(); + InternalLinkage = Val->hasInternalLinkage(); + if (InternalLinkage) + Callee = getAddrLocal(G, DL, Ty, DAG, ABI.IsN32() || ABI.IsN64()); + else if (Subtarget.useXGOT()) { + Callee = getAddrGlobalLargeGOT(G, DL, Ty, DAG, MipsII::MO_CALL_HI16, MipsII::MO_CALL_LO16, Chain, FuncInfo->callPtrInfo(MF, Val)); + IsCallReloc = true; + } + else { + Callee = getAddrGlobal(G, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain, FuncInfo->callPtrInfo(MF, Val)); + IsCallReloc = true; + } + } + else + Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, getPointerTy(DAG.getDataLayout()), 0, MipsII::MO_NO_FLAG); + GlobalOrExternal = true; + } + else if (ExternalSymbolSDNode *S = dyn_cast(Callee)) { + const char *Sym = S->getSymbol(); + if (!IsPIC) + Callee = DAG.getTargetExternalSymbol( Sym, getPointerTy(DAG.getDataLayout()), MipsII::MO_NO_FLAG); + else if (Subtarget.useXGOT()) { + Callee = getAddrGlobalLargeGOT(S, DL, Ty, DAG, MipsII::MO_CALL_HI16, MipsII::MO_CALL_LO16, Chain, FuncInfo->callPtrInfo(MF, Sym)); + IsCallReloc = true; + } + else { + Callee = getAddrGlobal(S, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain, FuncInfo->callPtrInfo(MF, Sym)); + IsCallReloc = true; + } + GlobalOrExternal = true; + } + SmallVector Ops(1, Chain); + SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); + getOpndList(Ops, RegsToPass, IsPIC, GlobalOrExternal, InternalLinkage, IsCallReloc, CLI, Callee, Chain); + if (IsTailCall) { + MF.getFrameInfo().setHasTailCall(); + SDValue Ret = DAG.getNode(MipsISD::TailCall, DL, MVT::Other, Ops); + DAG.addCallSiteInfo(Ret.getNode(), std::move(CSInfo)); + return Ret; + } + Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, Ops); + SDValue InFlag = Chain.getValue(1); + DAG.addCallSiteInfo(Chain.getNode(), std::move(CSInfo)); + if (!(MemcpyInByVal)) { + Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal, DAG.getIntPtrConstant(0, DL, true), InFlag, DL); + InFlag = Chain.getValue(1); + } + return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG, InVals, CLI); +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/LowerConstantPool.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/LowerConstantPool.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0a118c8fea23e323e770a810738ac56de09cca15 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/LowerConstantPool.cpp @@ -0,0 +1,11 @@ +SDValue MipsTargetLowering::lowerConstantPool(SDValue Op, SelectionDAG &DAG) const { + ConstantPoolSDNode *N = cast(Op); + EVT Ty = Op.getValueType(); + if (!isPositionIndependent()) { + const MipsTargetObjectFile *TLOF = static_cast(getTargetMachine().getObjFileLowering()); + if (TLOF->IsConstantInSmallSection(DAG.getDataLayout(), N->getConstVal(), getTargetMachine())) + return getAddrGPRel(N, SDLoc(N), Ty, DAG, ABI.IsN64()); + return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); + } + return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/LowerFRAMEADDR.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/LowerFRAMEADDR.cpp new file mode 100644 index 0000000000000000000000000000000000000000..55304c0e002c25426cac915e340d397c57564694 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/LowerFRAMEADDR.cpp @@ -0,0 +1,12 @@ +SDValue MipsTargetLowering::lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { + if (cast(Op.getOperand(0))->getZExtValue() != 0) { + DAG.getContext()->emitError("return address can be determined only for current frame"); + return SDValue(); + } + MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); + MFI.setFrameAddressIsTaken(true); + EVT VT = Op.getValueType(); + SDLoc DL(Op); + SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), DL, ABI.IsN64() ? Mips::FP_64 : Mips::FP, VT); + return FrameAddr; +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/LowerFormalArguments.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/LowerFormalArguments.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bbb9efff7eb46b474008aab70f4ce03c006a5618 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/LowerFormalArguments.cpp @@ -0,0 +1,90 @@ +SDValue MipsTargetLowering::LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl &InVals) const { + MachineFunction &MF = DAG.getMachineFunction(); + MachineFrameInfo &MFI = MF.getFrameInfo(); + MipsFunctionInfo *MipsFI = MF.getInfo(); + MipsFI->setVarArgsFrameIndex(0); + std::vector OutChains; + SmallVector ArgLocs; + MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext()); + CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), Align(1)); + const Function &Func = DAG.getMachineFunction().getFunction(); + Function::const_arg_iterator FuncArg = Func.arg_begin(); + if (Func.hasFnAttribute("interrupt") && !Func.arg_empty()) + report_fatal_error("Functions with the interrupt attribute cannot have arguments!"); + CCInfo.AnalyzeFormalArguments(Ins, CC_Mips_FixedArg); + MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(), CCInfo.getInRegsParamsCount() > 0); + unsigned CurArgIdx = 0; + CCInfo.rewindByValRegsInfo(); + for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { + CCValAssign &VA = ArgLocs[i]; + if (Ins[i].isOrigArg()) { + std::advance(FuncArg, Ins[i].getOrigArgIndex() - CurArgIdx); + CurArgIdx = Ins[i].getOrigArgIndex(); + } + EVT ValVT = VA.getValVT(); + ISD::ArgFlagsTy Flags = Ins[i].Flags; + bool IsRegLoc = VA.isRegLoc(); + if (Flags.isByVal()) { + assert(Ins[i].isOrigArg() && "Byval arguments cannot be implicit"); + unsigned FirstByValReg, LastByValReg; + unsigned ByValIdx = CCInfo.getInRegsParamsProcessed(); + CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg); + assert(Flags.getByValSize() && "ByVal args of size 0 should have been ignored by front-end."); + assert(ByValIdx < CCInfo.getInRegsParamsCount()); + copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg, FirstByValReg, LastByValReg, VA, CCInfo); + CCInfo.nextInRegsParam(); + continue; + } + if (IsRegLoc) { + MVT RegVT = VA.getLocVT(); + Register ArgReg = VA.getLocReg(); + const TargetRegisterClass *RC = getRegClassFor(RegVT); + unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC); + SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); + ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG); + if ((RegVT == MVT::i32 && ValVT == MVT::f32) || (RegVT == MVT::i64 && ValVT == MVT::f64) || (RegVT == MVT::f64 && ValVT == MVT::i64)) + ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue); + else if (ABI.IsO32() && RegVT == MVT::i32 && ValVT == MVT::f64) { + unsigned Reg2 = addLiveIn(DAG.getMachineFunction(), getNextIntArgReg(ArgReg), RC); + SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT); + if (!Subtarget.isLittle()) + std::swap(ArgValue, ArgValue2); + ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, ArgValue, ArgValue2); + } + InVals.push_back(ArgValue); + } + else { + MVT LocVT = VA.getLocVT(); + if (ABI.IsO32()) { + if (VA.getValVT().isFloatingPoint() && !Subtarget.useSoftFloat()) + LocVT = VA.getValVT(); + } + assert(VA.isMemLoc()); + int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8, VA.getLocMemOffset(), true); + SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); + SDValue ArgValue = DAG.getLoad(LocVT, DL, Chain, FIN, MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI)); + OutChains.push_back(ArgValue.getValue(1)); + ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG); + InVals.push_back(ArgValue); + } + } + for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { + if (Ins[i].Flags.isSRet()) { + unsigned Reg = MipsFI->getSRetReturnReg(); + if (!Reg) { + Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(ABI.IsN64() ? MVT::i64 : MVT::i32)); + MipsFI->setSRetReturnReg(Reg); + } + SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[i]); + Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain); + break; + } + } + if (IsVarArg) + writeVarArgRegs(OutChains, Chain, DL, DAG, CCInfo); + if (!OutChains.empty()) { + OutChains.push_back(Chain); + Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains); + } + return Chain; +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/LowerGlobalAddress.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/LowerGlobalAddress.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3bc241861141aeaf0155e6e05b289a3c4232fdc8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/LowerGlobalAddress.cpp @@ -0,0 +1,17 @@ +SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const { + EVT Ty = Op.getValueType(); + GlobalAddressSDNode *N = cast(Op); + const GlobalValue *GV = N->getGlobal(); + if (!isPositionIndependent()) { + const MipsTargetObjectFile *TLOF = static_cast(getTargetMachine().getObjFileLowering()); + const GlobalObject *GO = GV->getBaseObject(); + if (GO && TLOF->IsGlobalInSmallSection(GO, getTargetMachine())) + return getAddrGPRel(N, SDLoc(N), Ty, DAG, ABI.IsN64()); + return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); + } + if (GV->hasLocalLinkage()) + return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); + if (Subtarget.useXGOT()) + return getAddrGlobalLargeGOT(N, SDLoc(N), Ty, DAG, MipsII::MO_GOT_HI16, MipsII::MO_GOT_LO16, DAG.getEntryNode(), MachinePointerInfo::getGOT(DAG.getMachineFunction())); + return getAddrGlobal(N, SDLoc(N), Ty, DAG, (ABI.IsN32() || ABI.IsN64()) ? MipsII::MO_GOT_DISP : MipsII::MO_GOT, DAG.getEntryNode(), MachinePointerInfo::getGOT(DAG.getMachineFunction())); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/LowerGlobalTLSAddress.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/LowerGlobalTLSAddress.cpp new file mode 100644 index 0000000000000000000000000000000000000000..40d4302abbe9ff053b9574dac4d63cd2fbc144cf --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/LowerGlobalTLSAddress.cpp @@ -0,0 +1,50 @@ +SDValue MipsTargetLowering::lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { + GlobalAddressSDNode *GA = cast(Op); + if (DAG.getTarget().useEmulatedTLS()) + return LowerToTLSEmulatedModel(GA, DAG); + SDLoc DL(GA); + const GlobalValue *GV = GA->getGlobal(); + EVT PtrVT = getPointerTy(DAG.getDataLayout()); + TLSModel::Model model = getTargetMachine().getTLSModel(GV); + if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) { + unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM : MipsII::MO_TLSGD; + SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, Flag); + SDValue Argument = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT), TGA); + unsigned PtrSize = PtrVT.getSizeInBits(); + IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize); + SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT); + ArgListTy Args; + ArgListEntry Entry; + Entry.Node = Argument; + Entry.Ty = PtrTy; + Args.push_back(Entry); + TargetLowering::CallLoweringInfo CLI(DAG); + CLI.setDebugLoc(DL).setChain(DAG.getEntryNode()).setLibCallee(CallingConv::C, PtrTy, TlsGetAddr, std::move(Args)); + std::pair CallResult = LowerCallTo(CLI); + SDValue Ret = CallResult.first; + if (model != TLSModel::LocalDynamic) + return Ret; + SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, MipsII::MO_DTPREL_HI); + SDValue Hi = DAG.getNode(MipsISD::TlsHi, DL, PtrVT, TGAHi); + SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, MipsII::MO_DTPREL_LO); + SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); + SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret); + return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo); + } + SDValue Offset; + if (model == TLSModel::InitialExec) { + SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, MipsII::MO_GOTTPREL); + TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT),TGA); + Offset = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), TGA, MachinePointerInfo()); + } + else { + assert(model == TLSModel::LocalExec); + SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, MipsII::MO_TPREL_HI); + SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, MipsII::MO_TPREL_LO); + SDValue Hi = DAG.getNode(MipsISD::TlsHi, DL, PtrVT, TGAHi); + SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); + Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo); + } + SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT); + return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset); +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/LowerINTRINSIC_WO_CHAIN.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/LowerINTRINSIC_WO_CHAIN.cpp new file mode 100644 index 0000000000000000000000000000000000000000..150e8c0e72027acdaeeb3a046260a9210d8c6e7c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/LowerINTRINSIC_WO_CHAIN.cpp @@ -0,0 +1,601 @@ +SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const { + SDLoc DL(Op); + unsigned Intrinsic = cast(Op->getOperand(0))->getZExtValue(); + switch (Intrinsic) { + default: + return SDValue(); + case Intrinsic::mips_shilo: + return lowerDSPIntr(Op, DAG, MipsISD::SHILO); + case Intrinsic::mips_dpau_h_qbl: + return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL); + case Intrinsic::mips_dpau_h_qbr: + return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR); + case Intrinsic::mips_dpsu_h_qbl: + return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL); + case Intrinsic::mips_dpsu_h_qbr: + return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR); + case Intrinsic::mips_dpa_w_ph: + return lowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH); + case Intrinsic::mips_dps_w_ph: + return lowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH); + case Intrinsic::mips_dpax_w_ph: + return lowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH); + case Intrinsic::mips_dpsx_w_ph: + return lowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH); + case Intrinsic::mips_mulsa_w_ph: + return lowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH); + case Intrinsic::mips_mult: + return lowerDSPIntr(Op, DAG, MipsISD::Mult); + case Intrinsic::mips_multu: + return lowerDSPIntr(Op, DAG, MipsISD::Multu); + case Intrinsic::mips_madd: + return lowerDSPIntr(Op, DAG, MipsISD::MAdd); + case Intrinsic::mips_maddu: + return lowerDSPIntr(Op, DAG, MipsISD::MAddu); + case Intrinsic::mips_msub: + return lowerDSPIntr(Op, DAG, MipsISD::MSub); + case Intrinsic::mips_msubu: + return lowerDSPIntr(Op, DAG, MipsISD::MSubu); + case Intrinsic::mips_addv_b: + case Intrinsic::mips_addv_h: + case Intrinsic::mips_addv_w: + case Intrinsic::mips_addv_d: + return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_addvi_b: + case Intrinsic::mips_addvi_h: + case Intrinsic::mips_addvi_w: + case Intrinsic::mips_addvi_d: + return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); + case Intrinsic::mips_and_v: + return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_andi_b: + return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); + case Intrinsic::mips_bclr_b: + case Intrinsic::mips_bclr_h: + case Intrinsic::mips_bclr_w: + case Intrinsic::mips_bclr_d: + return lowerMSABitClear(Op, DAG); + case Intrinsic::mips_bclri_b: + case Intrinsic::mips_bclri_h: + case Intrinsic::mips_bclri_w: + case Intrinsic::mips_bclri_d: + return lowerMSABitClearImm(Op, DAG); + case Intrinsic::mips_binsli_b: + case Intrinsic::mips_binsli_h: + case Intrinsic::mips_binsli_w: + case Intrinsic::mips_binsli_d: { + EVT VecTy = Op->getValueType(0); + EVT EltTy = VecTy.getVectorElementType(); + if (Op->getConstantOperandVal(3) >= EltTy.getSizeInBits()) + report_fatal_error("Immediate out of range"); + APInt Mask = APInt::getHighBitsSet(EltTy.getSizeInBits(), Op->getConstantOperandVal(3) + 1); + return DAG.getNode(ISD::VSELECT, DL, VecTy, DAG.getConstant(Mask, DL, VecTy, true), Op->getOperand(2), Op->getOperand(1)); + } + case Intrinsic::mips_binsri_b: + case Intrinsic::mips_binsri_h: + case Intrinsic::mips_binsri_w: + case Intrinsic::mips_binsri_d: { + EVT VecTy = Op->getValueType(0); + EVT EltTy = VecTy.getVectorElementType(); + if (Op->getConstantOperandVal(3) >= EltTy.getSizeInBits()) + report_fatal_error("Immediate out of range"); + APInt Mask = APInt::getLowBitsSet(EltTy.getSizeInBits(), Op->getConstantOperandVal(3) + 1); + return DAG.getNode(ISD::VSELECT, DL, VecTy, DAG.getConstant(Mask, DL, VecTy, true), Op->getOperand(2), Op->getOperand(1)); + } + case Intrinsic::mips_bmnz_v: + return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3), Op->getOperand(2), Op->getOperand(1)); + case Intrinsic::mips_bmnzi_b: + return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), lowerMSASplatImm(Op, 3, DAG), Op->getOperand(2), Op->getOperand(1)); + case Intrinsic::mips_bmz_v: + return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_bmzi_b: + return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), lowerMSASplatImm(Op, 3, DAG), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_bneg_b: + case Intrinsic::mips_bneg_h: + case Intrinsic::mips_bneg_w: + case Intrinsic::mips_bneg_d: { + EVT VecTy = Op->getValueType(0); + SDValue One = DAG.getConstant(1, DL, VecTy); + return DAG.getNode(ISD::XOR, DL, VecTy, Op->getOperand(1), DAG.getNode(ISD::SHL, DL, VecTy, One, truncateVecElts(Op, DAG))); + } + case Intrinsic::mips_bnegi_b: + case Intrinsic::mips_bnegi_h: + case Intrinsic::mips_bnegi_w: + case Intrinsic::mips_bnegi_d: + return lowerMSABinaryBitImmIntr(Op, DAG, ISD::XOR, Op->getOperand(2), !Subtarget.isLittle()); + case Intrinsic::mips_bnz_b: + case Intrinsic::mips_bnz_h: + case Intrinsic::mips_bnz_w: + case Intrinsic::mips_bnz_d: + return DAG.getNode(MipsISD::VALL_NONZERO, DL, Op->getValueType(0), Op->getOperand(1)); + case Intrinsic::mips_bnz_v: + return DAG.getNode(MipsISD::VANY_NONZERO, DL, Op->getValueType(0), Op->getOperand(1)); + case Intrinsic::mips_bsel_v: + return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(3), Op->getOperand(2)); + case Intrinsic::mips_bseli_b: + return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 3, DAG), Op->getOperand(2)); + case Intrinsic::mips_bset_b: + case Intrinsic::mips_bset_h: + case Intrinsic::mips_bset_w: + case Intrinsic::mips_bset_d: { + EVT VecTy = Op->getValueType(0); + SDValue One = DAG.getConstant(1, DL, VecTy); + return DAG.getNode(ISD::OR, DL, VecTy, Op->getOperand(1), DAG.getNode(ISD::SHL, DL, VecTy, One, truncateVecElts(Op, DAG))); + } + case Intrinsic::mips_bseti_b: + case Intrinsic::mips_bseti_h: + case Intrinsic::mips_bseti_w: + case Intrinsic::mips_bseti_d: + return lowerMSABinaryBitImmIntr(Op, DAG, ISD::OR, Op->getOperand(2), !Subtarget.isLittle()); + case Intrinsic::mips_bz_b: + case Intrinsic::mips_bz_h: + case Intrinsic::mips_bz_w: + case Intrinsic::mips_bz_d: + return DAG.getNode(MipsISD::VALL_ZERO, DL, Op->getValueType(0), Op->getOperand(1)); + case Intrinsic::mips_bz_v: + return DAG.getNode(MipsISD::VANY_ZERO, DL, Op->getValueType(0), Op->getOperand(1)); + case Intrinsic::mips_ceq_b: + case Intrinsic::mips_ceq_h: + case Intrinsic::mips_ceq_w: + case Intrinsic::mips_ceq_d: + return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2), ISD::SETEQ); + case Intrinsic::mips_ceqi_b: + case Intrinsic::mips_ceqi_h: + case Intrinsic::mips_ceqi_w: + case Intrinsic::mips_ceqi_d: + return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG, true), ISD::SETEQ); + case Intrinsic::mips_cle_s_b: + case Intrinsic::mips_cle_s_h: + case Intrinsic::mips_cle_s_w: + case Intrinsic::mips_cle_s_d: + return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2), ISD::SETLE); + case Intrinsic::mips_clei_s_b: + case Intrinsic::mips_clei_s_h: + case Intrinsic::mips_clei_s_w: + case Intrinsic::mips_clei_s_d: + return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG, true), ISD::SETLE); + case Intrinsic::mips_cle_u_b: + case Intrinsic::mips_cle_u_h: + case Intrinsic::mips_cle_u_w: + case Intrinsic::mips_cle_u_d: + return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2), ISD::SETULE); + case Intrinsic::mips_clei_u_b: + case Intrinsic::mips_clei_u_h: + case Intrinsic::mips_clei_u_w: + case Intrinsic::mips_clei_u_d: + return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG), ISD::SETULE); + case Intrinsic::mips_clt_s_b: + case Intrinsic::mips_clt_s_h: + case Intrinsic::mips_clt_s_w: + case Intrinsic::mips_clt_s_d: + return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2), ISD::SETLT); + case Intrinsic::mips_clti_s_b: + case Intrinsic::mips_clti_s_h: + case Intrinsic::mips_clti_s_w: + case Intrinsic::mips_clti_s_d: + return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG, true), ISD::SETLT); + case Intrinsic::mips_clt_u_b: + case Intrinsic::mips_clt_u_h: + case Intrinsic::mips_clt_u_w: + case Intrinsic::mips_clt_u_d: + return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2), ISD::SETULT); + case Intrinsic::mips_clti_u_b: + case Intrinsic::mips_clti_u_h: + case Intrinsic::mips_clti_u_w: + case Intrinsic::mips_clti_u_d: + return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG), ISD::SETULT); + case Intrinsic::mips_copy_s_b: + case Intrinsic::mips_copy_s_h: + case Intrinsic::mips_copy_s_w: + return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT); + case Intrinsic::mips_copy_s_d: + if (Subtarget.hasMips64()) + return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT); + else { + return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + } + case Intrinsic::mips_copy_u_b: + case Intrinsic::mips_copy_u_h: + case Intrinsic::mips_copy_u_w: + return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT); + case Intrinsic::mips_copy_u_d: + if (Subtarget.hasMips64()) + return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT); + else { + return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + } + case Intrinsic::mips_div_s_b: + case Intrinsic::mips_div_s_h: + case Intrinsic::mips_div_s_w: + case Intrinsic::mips_div_s_d: + return DAG.getNode(ISD::SDIV, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_div_u_b: + case Intrinsic::mips_div_u_h: + case Intrinsic::mips_div_u_w: + case Intrinsic::mips_div_u_d: + return DAG.getNode(ISD::UDIV, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_fadd_w: + case Intrinsic::mips_fadd_d: + return DAG.getNode(ISD::FADD, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_fceq_w: + case Intrinsic::mips_fceq_d: + return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2), ISD::SETOEQ); + case Intrinsic::mips_fcle_w: + case Intrinsic::mips_fcle_d: + return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2), ISD::SETOLE); + case Intrinsic::mips_fclt_w: + case Intrinsic::mips_fclt_d: + return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2), ISD::SETOLT); + case Intrinsic::mips_fcne_w: + case Intrinsic::mips_fcne_d: + return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2), ISD::SETONE); + case Intrinsic::mips_fcor_w: + case Intrinsic::mips_fcor_d: + return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2), ISD::SETO); + case Intrinsic::mips_fcueq_w: + case Intrinsic::mips_fcueq_d: + return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2), ISD::SETUEQ); + case Intrinsic::mips_fcule_w: + case Intrinsic::mips_fcule_d: + return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2), ISD::SETULE); + case Intrinsic::mips_fcult_w: + case Intrinsic::mips_fcult_d: + return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2), ISD::SETULT); + case Intrinsic::mips_fcun_w: + case Intrinsic::mips_fcun_d: + return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2), ISD::SETUO); + case Intrinsic::mips_fcune_w: + case Intrinsic::mips_fcune_d: + return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2), ISD::SETUNE); + case Intrinsic::mips_fdiv_w: + case Intrinsic::mips_fdiv_d: + return DAG.getNode(ISD::FDIV, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_ffint_u_w: + case Intrinsic::mips_ffint_u_d: + return DAG.getNode(ISD::UINT_TO_FP, DL, Op->getValueType(0), Op->getOperand(1)); + case Intrinsic::mips_ffint_s_w: + case Intrinsic::mips_ffint_s_d: + return DAG.getNode(ISD::SINT_TO_FP, DL, Op->getValueType(0), Op->getOperand(1)); + case Intrinsic::mips_fill_b: + case Intrinsic::mips_fill_h: + case Intrinsic::mips_fill_w: + case Intrinsic::mips_fill_d: { + EVT ResTy = Op->getValueType(0); + SmallVector Ops(ResTy.getVectorNumElements(), Op->getOperand(1)); + return DAG.getBuildVector(ResTy, DL, Ops); + } + case Intrinsic::mips_fexp2_w: + case Intrinsic::mips_fexp2_d: { + EVT ResTy = Op->getValueType(0); + return DAG.getNode(ISD::FMUL, SDLoc(Op), ResTy, Op->getOperand(1), DAG.getNode(ISD::FEXP2, SDLoc(Op), ResTy, Op->getOperand(2))); + } + case Intrinsic::mips_flog2_w: + case Intrinsic::mips_flog2_d: + return DAG.getNode(ISD::FLOG2, DL, Op->getValueType(0), Op->getOperand(1)); + case Intrinsic::mips_fmadd_w: + case Intrinsic::mips_fmadd_d: + return DAG.getNode(ISD::FMA, SDLoc(Op), Op->getValueType(0), Op->getOperand(1), Op->getOperand(2), Op->getOperand(3)); + case Intrinsic::mips_fmul_w: + case Intrinsic::mips_fmul_d: + return DAG.getNode(ISD::FMUL, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_fmsub_w: + case Intrinsic::mips_fmsub_d: { + return DAG.getNode(MipsISD::FMS, SDLoc(Op), Op->getValueType(0), Op->getOperand(1), Op->getOperand(2), Op->getOperand(3)); + } + case Intrinsic::mips_frint_w: + case Intrinsic::mips_frint_d: + return DAG.getNode(ISD::FRINT, DL, Op->getValueType(0), Op->getOperand(1)); + case Intrinsic::mips_fsqrt_w: + case Intrinsic::mips_fsqrt_d: + return DAG.getNode(ISD::FSQRT, DL, Op->getValueType(0), Op->getOperand(1)); + case Intrinsic::mips_fsub_w: + case Intrinsic::mips_fsub_d: + return DAG.getNode(ISD::FSUB, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_ftrunc_u_w: + case Intrinsic::mips_ftrunc_u_d: + return DAG.getNode(ISD::FP_TO_UINT, DL, Op->getValueType(0), Op->getOperand(1)); + case Intrinsic::mips_ftrunc_s_w: + case Intrinsic::mips_ftrunc_s_d: + return DAG.getNode(ISD::FP_TO_SINT, DL, Op->getValueType(0), Op->getOperand(1)); + case Intrinsic::mips_ilvev_b: + case Intrinsic::mips_ilvev_h: + case Intrinsic::mips_ilvev_w: + case Intrinsic::mips_ilvev_d: + return DAG.getNode(MipsISD::ILVEV, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_ilvl_b: + case Intrinsic::mips_ilvl_h: + case Intrinsic::mips_ilvl_w: + case Intrinsic::mips_ilvl_d: + return DAG.getNode(MipsISD::ILVL, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_ilvod_b: + case Intrinsic::mips_ilvod_h: + case Intrinsic::mips_ilvod_w: + case Intrinsic::mips_ilvod_d: + return DAG.getNode(MipsISD::ILVOD, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_ilvr_b: + case Intrinsic::mips_ilvr_h: + case Intrinsic::mips_ilvr_w: + case Intrinsic::mips_ilvr_d: + return DAG.getNode(MipsISD::ILVR, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_insert_b: + case Intrinsic::mips_insert_h: + case Intrinsic::mips_insert_w: + case Intrinsic::mips_insert_d: + return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0), Op->getOperand(1), Op->getOperand(3), Op->getOperand(2)); + case Intrinsic::mips_insve_b: + case Intrinsic::mips_insve_h: + case Intrinsic::mips_insve_w: + case Intrinsic::mips_insve_d: { + int64_t Max; + switch (Intrinsic) { + case Intrinsic::mips_insve_b: Max = 15; break; + case Intrinsic::mips_insve_h: Max = 7; break; + case Intrinsic::mips_insve_w: Max = 3; break; + case Intrinsic::mips_insve_d: Max = 1; break; + default: llvm_unreachable("Unmatched intrinsic"); + } + int64_t Value = cast(Op->getOperand(2))->getSExtValue(); + if (Value < 0 || Value > Max) + report_fatal_error("Immediate out of range"); + return DAG.getNode(MipsISD::INSVE, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2), Op->getOperand(3), DAG.getConstant(0, DL, MVT::i32)); + } + case Intrinsic::mips_ldi_b: + case Intrinsic::mips_ldi_h: + case Intrinsic::mips_ldi_w: + case Intrinsic::mips_ldi_d: + return lowerMSASplatImm(Op, 1, DAG, true); + case Intrinsic::mips_lsa: + case Intrinsic::mips_dlsa: { + EVT ResTy = Op->getValueType(0); + return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1), DAG.getNode(ISD::SHL, SDLoc(Op), ResTy, Op->getOperand(2), Op->getOperand(3))); + } + case Intrinsic::mips_maddv_b: + case Intrinsic::mips_maddv_h: + case Intrinsic::mips_maddv_w: + case Intrinsic::mips_maddv_d: { + EVT ResTy = Op->getValueType(0); + return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1), DAG.getNode(ISD::MUL, SDLoc(Op), ResTy, Op->getOperand(2), Op->getOperand(3))); + } + case Intrinsic::mips_max_s_b: + case Intrinsic::mips_max_s_h: + case Intrinsic::mips_max_s_w: + case Intrinsic::mips_max_s_d: + return DAG.getNode(ISD::SMAX, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_max_u_b: + case Intrinsic::mips_max_u_h: + case Intrinsic::mips_max_u_w: + case Intrinsic::mips_max_u_d: + return DAG.getNode(ISD::UMAX, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_maxi_s_b: + case Intrinsic::mips_maxi_s_h: + case Intrinsic::mips_maxi_s_w: + case Intrinsic::mips_maxi_s_d: + return DAG.getNode(ISD::SMAX, DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG, true)); + case Intrinsic::mips_maxi_u_b: + case Intrinsic::mips_maxi_u_h: + case Intrinsic::mips_maxi_u_w: + case Intrinsic::mips_maxi_u_d: + return DAG.getNode(ISD::UMAX, DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); + case Intrinsic::mips_min_s_b: + case Intrinsic::mips_min_s_h: + case Intrinsic::mips_min_s_w: + case Intrinsic::mips_min_s_d: + return DAG.getNode(ISD::SMIN, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_min_u_b: + case Intrinsic::mips_min_u_h: + case Intrinsic::mips_min_u_w: + case Intrinsic::mips_min_u_d: + return DAG.getNode(ISD::UMIN, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_mini_s_b: + case Intrinsic::mips_mini_s_h: + case Intrinsic::mips_mini_s_w: + case Intrinsic::mips_mini_s_d: + return DAG.getNode(ISD::SMIN, DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG, true)); + case Intrinsic::mips_mini_u_b: + case Intrinsic::mips_mini_u_h: + case Intrinsic::mips_mini_u_w: + case Intrinsic::mips_mini_u_d: + return DAG.getNode(ISD::UMIN, DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); + case Intrinsic::mips_mod_s_b: + case Intrinsic::mips_mod_s_h: + case Intrinsic::mips_mod_s_w: + case Intrinsic::mips_mod_s_d: + return DAG.getNode(ISD::SREM, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_mod_u_b: + case Intrinsic::mips_mod_u_h: + case Intrinsic::mips_mod_u_w: + case Intrinsic::mips_mod_u_d: + return DAG.getNode(ISD::UREM, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_mulv_b: + case Intrinsic::mips_mulv_h: + case Intrinsic::mips_mulv_w: + case Intrinsic::mips_mulv_d: + return DAG.getNode(ISD::MUL, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_msubv_b: + case Intrinsic::mips_msubv_h: + case Intrinsic::mips_msubv_w: + case Intrinsic::mips_msubv_d: { + EVT ResTy = Op->getValueType(0); + return DAG.getNode(ISD::SUB, SDLoc(Op), ResTy, Op->getOperand(1), DAG.getNode(ISD::MUL, SDLoc(Op), ResTy, Op->getOperand(2), Op->getOperand(3))); + } + case Intrinsic::mips_nlzc_b: + case Intrinsic::mips_nlzc_h: + case Intrinsic::mips_nlzc_w: + case Intrinsic::mips_nlzc_d: + return DAG.getNode(ISD::CTLZ, DL, Op->getValueType(0), Op->getOperand(1)); + case Intrinsic::mips_nor_v: { + SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + return DAG.getNOT(DL, Res, Res->getValueType(0)); + } + case Intrinsic::mips_nori_b: { + SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); + return DAG.getNOT(DL, Res, Res->getValueType(0)); + } + case Intrinsic::mips_or_v: + return DAG.getNode(ISD::OR, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_ori_b: + return DAG.getNode(ISD::OR, DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); + case Intrinsic::mips_pckev_b: + case Intrinsic::mips_pckev_h: + case Intrinsic::mips_pckev_w: + case Intrinsic::mips_pckev_d: + return DAG.getNode(MipsISD::PCKEV, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_pckod_b: + case Intrinsic::mips_pckod_h: + case Intrinsic::mips_pckod_w: + case Intrinsic::mips_pckod_d: + return DAG.getNode(MipsISD::PCKOD, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_pcnt_b: + case Intrinsic::mips_pcnt_h: + case Intrinsic::mips_pcnt_w: + case Intrinsic::mips_pcnt_d: + return DAG.getNode(ISD::CTPOP, DL, Op->getValueType(0), Op->getOperand(1)); + case Intrinsic::mips_sat_s_b: + case Intrinsic::mips_sat_s_h: + case Intrinsic::mips_sat_s_w: + case Intrinsic::mips_sat_s_d: + case Intrinsic::mips_sat_u_b: + case Intrinsic::mips_sat_u_h: + case Intrinsic::mips_sat_u_w: + case Intrinsic::mips_sat_u_d: { + int64_t Max; + switch (Intrinsic) { + case Intrinsic::mips_sat_s_b: + case Intrinsic::mips_sat_u_b: Max = 7; break; + case Intrinsic::mips_sat_s_h: + case Intrinsic::mips_sat_u_h: Max = 15; break; + case Intrinsic::mips_sat_s_w: + case Intrinsic::mips_sat_u_w: Max = 31; break; + case Intrinsic::mips_sat_s_d: + case Intrinsic::mips_sat_u_d: Max = 63; break; + default: llvm_unreachable("Unmatched intrinsic"); + } + int64_t Value = cast(Op->getOperand(2))->getSExtValue(); + if (Value < 0 || Value > Max) + report_fatal_error("Immediate out of range"); + return SDValue(); + } + case Intrinsic::mips_shf_b: + case Intrinsic::mips_shf_h: + case Intrinsic::mips_shf_w: { + int64_t Value = cast(Op->getOperand(2))->getSExtValue(); + if (Value < 0 || Value > 255) + report_fatal_error("Immediate out of range"); + return DAG.getNode(MipsISD::SHF, DL, Op->getValueType(0), Op->getOperand(2), Op->getOperand(1)); + } + case Intrinsic::mips_sldi_b: + case Intrinsic::mips_sldi_h: + case Intrinsic::mips_sldi_w: + case Intrinsic::mips_sldi_d: { + int64_t Max; + switch (Intrinsic) { + case Intrinsic::mips_sldi_b: Max = 15; break; + case Intrinsic::mips_sldi_h: Max = 7; break; + case Intrinsic::mips_sldi_w: Max = 3; break; + case Intrinsic::mips_sldi_d: Max = 1; break; + default: llvm_unreachable("Unmatched intrinsic"); + } + int64_t Value = cast(Op->getOperand(3))->getSExtValue(); + if (Value < 0 || Value > Max) + report_fatal_error("Immediate out of range"); + return SDValue(); + } + case Intrinsic::mips_sll_b: + case Intrinsic::mips_sll_h: + case Intrinsic::mips_sll_w: + case Intrinsic::mips_sll_d: + return DAG.getNode(ISD::SHL, DL, Op->getValueType(0), Op->getOperand(1), truncateVecElts(Op, DAG)); + case Intrinsic::mips_slli_b: + case Intrinsic::mips_slli_h: + case Intrinsic::mips_slli_w: + case Intrinsic::mips_slli_d: + return DAG.getNode(ISD::SHL, DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); + case Intrinsic::mips_splat_b: + case Intrinsic::mips_splat_h: + case Intrinsic::mips_splat_w: + case Intrinsic::mips_splat_d: + return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0), lowerMSASplatZExt(Op, 2, DAG), Op->getOperand(1), Op->getOperand(1)); + case Intrinsic::mips_splati_b: + case Intrinsic::mips_splati_h: + case Intrinsic::mips_splati_w: + case Intrinsic::mips_splati_d: + return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0), lowerMSASplatImm(Op, 2, DAG), Op->getOperand(1), Op->getOperand(1)); + case Intrinsic::mips_sra_b: + case Intrinsic::mips_sra_h: + case Intrinsic::mips_sra_w: + case Intrinsic::mips_sra_d: + return DAG.getNode(ISD::SRA, DL, Op->getValueType(0), Op->getOperand(1), truncateVecElts(Op, DAG)); + case Intrinsic::mips_srai_b: + case Intrinsic::mips_srai_h: + case Intrinsic::mips_srai_w: + case Intrinsic::mips_srai_d: + return DAG.getNode(ISD::SRA, DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); + case Intrinsic::mips_srari_b: + case Intrinsic::mips_srari_h: + case Intrinsic::mips_srari_w: + case Intrinsic::mips_srari_d: { + int64_t Max; + switch (Intrinsic) { + case Intrinsic::mips_srari_b: Max = 7; break; + case Intrinsic::mips_srari_h: Max = 15; break; + case Intrinsic::mips_srari_w: Max = 31; break; + case Intrinsic::mips_srari_d: Max = 63; break; + default: llvm_unreachable("Unmatched intrinsic"); + } + int64_t Value = cast(Op->getOperand(2))->getSExtValue(); + if (Value < 0 || Value > Max) + report_fatal_error("Immediate out of range"); + return SDValue(); + } + case Intrinsic::mips_srl_b: + case Intrinsic::mips_srl_h: + case Intrinsic::mips_srl_w: + case Intrinsic::mips_srl_d: + return DAG.getNode(ISD::SRL, DL, Op->getValueType(0), Op->getOperand(1), truncateVecElts(Op, DAG)); + case Intrinsic::mips_srli_b: + case Intrinsic::mips_srli_h: + case Intrinsic::mips_srli_w: + case Intrinsic::mips_srli_d: + return DAG.getNode(ISD::SRL, DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); + case Intrinsic::mips_srlri_b: + case Intrinsic::mips_srlri_h: + case Intrinsic::mips_srlri_w: + case Intrinsic::mips_srlri_d: { + int64_t Max; + switch (Intrinsic) { + case Intrinsic::mips_srlri_b: Max = 7; break; + case Intrinsic::mips_srlri_h: Max = 15; break; + case Intrinsic::mips_srlri_w: Max = 31; break; + case Intrinsic::mips_srlri_d: Max = 63; break; + default: llvm_unreachable("Unmatched intrinsic"); + } + int64_t Value = cast(Op->getOperand(2))->getSExtValue(); + if (Value < 0 || Value > Max) + report_fatal_error("Immediate out of range"); + return SDValue(); + } + case Intrinsic::mips_subv_b: + case Intrinsic::mips_subv_h: + case Intrinsic::mips_subv_w: + case Intrinsic::mips_subv_d: + return DAG.getNode(ISD::SUB, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_subvi_b: + case Intrinsic::mips_subvi_h: + case Intrinsic::mips_subvi_w: + case Intrinsic::mips_subvi_d: + return DAG.getNode(ISD::SUB, DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); + case Intrinsic::mips_vshf_b: + case Intrinsic::mips_vshf_h: + case Intrinsic::mips_vshf_w: + case Intrinsic::mips_vshf_d: + return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2), Op->getOperand(3)); + case Intrinsic::mips_xor_v: + return DAG.getNode(ISD::XOR, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_xori_b: + return DAG.getNode(ISD::XOR, DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); + case Intrinsic::thread_pointer: { + EVT PtrVT = getPointerTy(DAG.getDataLayout()); + return DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT); + } + } +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/LowerINTRINSIC_W_CHAIN.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/LowerINTRINSIC_W_CHAIN.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4be9f6092250b32fead2a9800ea16544544f58f7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/LowerINTRINSIC_W_CHAIN.cpp @@ -0,0 +1,52 @@ +SDValue MipsSETargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const { + unsigned Intr = cast(Op->getOperand(1))->getZExtValue(); + switch (Intr) { + default: + return SDValue(); + case Intrinsic::mips_extp: + return lowerDSPIntr(Op, DAG, MipsISD::EXTP); + case Intrinsic::mips_extpdp: + return lowerDSPIntr(Op, DAG, MipsISD::EXTPDP); + case Intrinsic::mips_extr_w: + return lowerDSPIntr(Op, DAG, MipsISD::EXTR_W); + case Intrinsic::mips_extr_r_w: + return lowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W); + case Intrinsic::mips_extr_rs_w: + return lowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W); + case Intrinsic::mips_extr_s_h: + return lowerDSPIntr(Op, DAG, MipsISD::EXTR_S_H); + case Intrinsic::mips_mthlip: + return lowerDSPIntr(Op, DAG, MipsISD::MTHLIP); + case Intrinsic::mips_mulsaq_s_w_ph: + return lowerDSPIntr(Op, DAG, MipsISD::MULSAQ_S_W_PH); + case Intrinsic::mips_maq_s_w_phl: + return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL); + case Intrinsic::mips_maq_s_w_phr: + return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR); + case Intrinsic::mips_maq_sa_w_phl: + return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHL); + case Intrinsic::mips_maq_sa_w_phr: + return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHR); + case Intrinsic::mips_dpaq_s_w_ph: + return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_S_W_PH); + case Intrinsic::mips_dpsq_s_w_ph: + return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_S_W_PH); + case Intrinsic::mips_dpaq_sa_l_w: + return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_SA_L_W); + case Intrinsic::mips_dpsq_sa_l_w: + return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_SA_L_W); + case Intrinsic::mips_dpaqx_s_w_ph: + return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_S_W_PH); + case Intrinsic::mips_dpaqx_sa_w_ph: + return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_SA_W_PH); + case Intrinsic::mips_dpsqx_s_w_ph: + return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH); + case Intrinsic::mips_dpsqx_sa_w_ph: + return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH); + case Intrinsic::mips_ld_b: + case Intrinsic::mips_ld_h: + case Intrinsic::mips_ld_w: + case Intrinsic::mips_ld_d: + return lowerMSALoadIntr(Op, DAG, Intr, Subtarget); + } +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/LowerJumpTable.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/LowerJumpTable.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c445b62394d8dd7ca699b85e09abca470d7e9eef --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/LowerJumpTable.cpp @@ -0,0 +1,7 @@ +SDValue MipsTargetLowering::lowerJumpTable(SDValue Op, SelectionDAG &DAG) const { + JumpTableSDNode *N = cast(Op); + EVT Ty = Op.getValueType(); + if (!isPositionIndependent()) + return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); + return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/LowerOperation.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/LowerOperation.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fbfe3d2f0ef29923975a86d495e1dd2120dba454 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/LowerOperation.cpp @@ -0,0 +1,22 @@ +SDValue MipsSETargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { + switch(Op.getOpcode()) { + case ISD::LOAD: return lowerLOAD(Op, DAG); + case ISD::STORE: return lowerSTORE(Op, DAG); + case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG); + case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG); + case ISD::MULHS: return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG); + case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG); + case ISD::MUL: return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG); + case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG); + case ISD::UDIVREM: return lowerMulDiv(Op, MipsISD::DivRemU, true, true, DAG); + case ISD::INTRINSIC_WO_CHAIN: return lowerINTRINSIC_WO_CHAIN(Op, DAG); + case ISD::INTRINSIC_W_CHAIN: return lowerINTRINSIC_W_CHAIN(Op, DAG); + case ISD::INTRINSIC_VOID: return lowerINTRINSIC_VOID(Op, DAG); + case ISD::EXTRACT_VECTOR_ELT: return lowerEXTRACT_VECTOR_ELT(Op, DAG); + case ISD::BUILD_VECTOR: return lowerBUILD_VECTOR(Op, DAG); + case ISD::VECTOR_SHUFFLE: return lowerVECTOR_SHUFFLE(Op, DAG); + case ISD::SELECT: return lowerSELECT(Op, DAG); + case ISD::BITCAST: return lowerBITCAST(Op, DAG); + } + return MipsTargetLowering::LowerOperation(Op, DAG); +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/LowerRETURNADDR.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/LowerRETURNADDR.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ded637a4455513a16d891e39639e269a720641e3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/LowerRETURNADDR.cpp @@ -0,0 +1,15 @@ +SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const { + if (verifyReturnAddressArgumentIsConstant(Op, DAG)) + return SDValue(); + if (cast(Op.getOperand(0))->getZExtValue() != 0) { + DAG.getContext()->emitError("return address can be determined only for current frame"); + return SDValue(); + } + MachineFunction &MF = DAG.getMachineFunction(); + MachineFrameInfo &MFI = MF.getFrameInfo(); + MVT VT = Op.getSimpleValueType(); + unsigned RA = ABI.IsN64() ? Mips::RA_64 : Mips::RA; + MFI.setReturnAddressIsTaken(true); + unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT)); + return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/LowerReturn.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/LowerReturn.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1ed075e6ccf9610456191789f39cad7dd5b16736 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/LowerReturn.cpp @@ -0,0 +1,66 @@ +SDValue MipsTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl &Outs, const SmallVectorImpl &OutVals, const SDLoc &DL, SelectionDAG &DAG) const { + SmallVector RVLocs; + MachineFunction &MF = DAG.getMachineFunction(); + MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext()); + CCInfo.AnalyzeReturn(Outs, RetCC_Mips); + SDValue Flag; + SmallVector RetOps(1, Chain); + for (unsigned i = 0; i != RVLocs.size(); ++i) { + SDValue Val = OutVals[i]; + CCValAssign &VA = RVLocs[i]; + assert(VA.isRegLoc() && "Can only return in registers!"); + bool UseUpperBits = false; + switch (VA.getLocInfo()) { + default: + llvm_unreachable("Unknown loc info!"); + case CCValAssign::Full: + break; + case CCValAssign::BCvt: + Val = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Val); + break; + case CCValAssign::AExtUpper: + UseUpperBits = true; + LLVM_FALLTHROUGH; + case CCValAssign::AExt: + Val = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Val); + break; + case CCValAssign::ZExtUpper: + UseUpperBits = true; + LLVM_FALLTHROUGH; + case CCValAssign::ZExt: + Val = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Val); + break; + case CCValAssign::SExtUpper: + UseUpperBits = true; + LLVM_FALLTHROUGH; + case CCValAssign::SExt: + Val = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Val); + break; + } + if (UseUpperBits) { + unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits(); + unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); + Val = DAG.getNode(ISD::SHL, DL, VA.getLocVT(), Val, DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); + } + Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag); + Flag = Chain.getValue(1); + RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); + } + if (MF.getFunction().hasStructRetAttr()) { + MipsFunctionInfo *MipsFI = MF.getInfo(); + unsigned Reg = MipsFI->getSRetReturnReg(); + if (!Reg) + llvm_unreachable("sret virtual register not created in the entry block"); + SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout())); + unsigned V0 = ABI.IsN64() ? Mips::V0_64 : Mips::V0; + Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag); + Flag = Chain.getValue(1); + RetOps.push_back(DAG.getRegister(V0, getPointerTy(DAG.getDataLayout()))); + } + RetOps[0] = Chain;. + if (Flag.getNode()) + RetOps.push_back(Flag); + if (DAG.getMachineFunction().getFunction().hasFnAttribute("interrupt")) + return LowerInterruptReturn(RetOps, DL, DAG); + return DAG.getNode(MipsISD::Ret, DL, MVT::Other, RetOps); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/LowerVASTART.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/LowerVASTART.cpp new file mode 100644 index 0000000000000000000000000000000000000000..82c750e52dc286a4e812e266e95aad7444d81f06 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/LowerVASTART.cpp @@ -0,0 +1,8 @@ +SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const { + MachineFunction &MF = DAG.getMachineFunction(); + MipsFunctionInfo *FuncInfo = MF.getInfo(); + SDLoc DL(Op); + SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), getPointerTy(MF.getDataLayout())); + const Value *SV = cast(Op.getOperand(2))->getValue(); + return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1), MachinePointerInfo(SV)); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/NodeType.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/NodeType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a38352825f56aab99f061204881b1757052b6041 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/NodeType.cpp @@ -0,0 +1,115 @@ +enum NodeType : unsigned { + FIRST_NUMBER = ISD::BUILTIN_OP_END, + JmpLink, + TailCall, + Highest, + Higher, + Hi, + Lo, + GotHi, + TlsHi, + GPRel, + ThreadPointer, + FMS, + FPBrcond, + FPCmp, + FSELECT, + MTC1_D64, + CMovFP_T, + CMovFP_F, + TruncIntFP, + Ret, + ERet, + EH_RETURN, + MFHI, + MFLO, + MTLOHI, + Mult, + Multu, + MAdd, + MAddu, + MSub, + MSubu, + DivRem, + DivRemU, + DivRem16, + DivRemU16, + BuildPairF64, + ExtractElementF64, + Wrapper, + DynAlloc, + Sync, + Ext, + Ins, + CIns, + EXTP, + EXTPDP, + EXTR_S_H, + EXTR_W, + EXTR_R_W, + EXTR_RS_W, + SHILO, + MTHLIP, + MULSAQ_S_W_PH, + MAQ_S_W_PHL, + MAQ_S_W_PHR, + MAQ_SA_W_PHL, + MAQ_SA_W_PHR, + DPAU_H_QBL, + DPAU_H_QBR, + DPSU_H_QBL, + DPSU_H_QBR, + DPAQ_S_W_PH, + DPSQ_S_W_PH, + DPAQ_SA_L_W, + DPSQ_SA_L_W, + DPA_W_PH, + DPS_W_PH, + DPAQX_S_W_PH, + DPAQX_SA_W_PH, + DPAX_W_PH, + DPSX_W_PH, + DPSQX_S_W_PH, + DPSQX_SA_W_PH, + MULSA_W_PH, + MULT, + MULTU, + MADD_DSP, + MADDU_DSP, + MSUB_DSP, + MSUBU_DSP, + SHLL_DSP, + SHRA_DSP, + SHRL_DSP, + SETCC_DSP, + SELECT_CC_DSP, + VALL_ZERO, + VANY_ZERO, + VALL_NONZERO, + VANY_NONZERO, + VCEQ, + VCLE_S, + VCLE_U, + VCLT_S, + VCLT_U, + VSHF, + SHF, + ILVEV, + ILVOD, + ILVL, + ILVR, + PCKEV, + PCKOD, + INSVE, + VNOR, + VEXTRACT_SEXT_ELT, + VEXTRACT_ZEXT_ELT, + LWL = ISD::FIRST_TARGET_MEMORY_OPCODE, + LWR, + SWL, + SWR, + LDL, + LDR, + SDL, + SDR +}; \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/PerformDAGCombine.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/PerformDAGCombine.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b4c27aab8d97ef85c9947073d81e7dab0609a8e5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/PerformDAGCombine.cpp @@ -0,0 +1,34 @@ +SDValue MipsSETargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { + SelectionDAG &DAG = DCI.DAG; + SDValue Val; + switch (N->getOpcode()) { + case ISD::AND: + Val = performANDCombine(N, DAG, DCI, Subtarget); + break; + case ISD::OR: + Val = performORCombine(N, DAG, DCI, Subtarget); + break; + case ISD::MUL: + return performMULCombine(N, DAG, DCI, this, Subtarget); + case ISD::SHL: + Val = performSHLCombine(N, DAG, DCI, Subtarget); + break; + case ISD::SRA: + return performSRACombine(N, DAG, DCI, Subtarget); + case ISD::SRL: + return performSRLCombine(N, DAG, DCI, Subtarget); + case ISD::VSELECT: + return performVSELECTCombine(N, DAG); + case ISD::XOR: + Val = performXORCombine(N, DAG, Subtarget); + break; + case ISD::SETCC: + Val = performSETCCCombine(N, DAG); + break; + } + if (Val.getNode()) { + LLVM_DEBUG(dbgs() << "\nMipsSE DAG Combine:\n"; N->printrWithDepth(dbgs(), &DAG); dbgs() << "\n=> \n"; Val.getNode()->printrWithDepth(dbgs(), &DAG); dbgs() << "\n"); + return Val; + } + return MipsTargetLowering::PerformDAGCombine(N, DCI); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/ReplaceNodeResults.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/ReplaceNodeResults.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8e0b70bb9b6952f3748f9c7143aec894bfccf9c8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/ReplaceNodeResults.cpp @@ -0,0 +1,3 @@ +void MipsTargetLowering::ReplaceNodeResults(SDNode *N, SmallVectorImpl &Results, SelectionDAG &DAG) const { + return LowerOperationWrapper(N, Results, DAG); +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/TargetLowering.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/TargetLowering.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b374c388335c1101e9b9313b761335931a0abe3a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/TargetLowering.cpp @@ -0,0 +1,173 @@ +MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI) : TargetLowering(TM), Subtarget(STI), ABI(TM.getABI()) { + setBooleanContents(ZeroOrOneBooleanContent); + setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); + if (Subtarget.hasMips32r6()) + setBooleanContents(ZeroOrOneBooleanContent, ZeroOrNegativeOneBooleanContent); + for (MVT VT : MVT::integer_valuetypes()) { + setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); + setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); + setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); + } + for (MVT VT : MVT::fp_valuetypes()) { + setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); + setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand); + } + for (MVT VT : MVT::fp_fixedlen_vector_valuetypes()) { + MVT F16VT = MVT::getVectorVT(MVT::f16, VT.getVectorNumElements()); + if (F16VT.isValid()) + setLoadExtAction(ISD::EXTLOAD, VT, F16VT, Expand); + } + setTruncStoreAction(MVT::f32, MVT::f16, Expand); + setTruncStoreAction(MVT::f64, MVT::f16, Expand); + setTruncStoreAction(MVT::f64, MVT::f32, Expand); + AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); + setOperationAction(ISD::BR_JT, MVT::Other, Expand); + setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); + setOperationAction(ISD::BlockAddress, MVT::i32, Custom); + setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); + setOperationAction(ISD::JumpTable, MVT::i32, Custom); + setOperationAction(ISD::ConstantPool, MVT::i32, Custom); + setOperationAction(ISD::SELECT, MVT::f32, Custom); + setOperationAction(ISD::SELECT, MVT::f64, Custom); + setOperationAction(ISD::SELECT, MVT::i32, Custom); + setOperationAction(ISD::SETCC, MVT::f32, Custom); + setOperationAction(ISD::SETCC, MVT::f64, Custom); + setOperationAction(ISD::BRCOND, MVT::Other, Custom); + setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); + setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); + setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); + if (!(TM.Options.NoNaNsFPMath || Subtarget.inAbs2008Mode())) { + setOperationAction(ISD::FABS, MVT::f32, Custom); + setOperationAction(ISD::FABS, MVT::f64, Custom); + } + if (Subtarget.isGP64bit()) { + setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); + setOperationAction(ISD::BlockAddress, MVT::i64, Custom); + setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); + setOperationAction(ISD::JumpTable, MVT::i64, Custom); + setOperationAction(ISD::ConstantPool, MVT::i64, Custom); + setOperationAction(ISD::SELECT, MVT::i64, Custom); + setOperationAction(ISD::LOAD, MVT::i64, Custom); + setOperationAction(ISD::STORE, MVT::i64, Custom); + setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); + setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom); + setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom); + setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom); + } + if (!Subtarget.isGP64bit()) { + setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); + setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); + setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); + } + setOperationAction(ISD::EH_DWARF_CFA, MVT::i32, Custom); + if (Subtarget.isGP64bit()) + setOperationAction(ISD::EH_DWARF_CFA, MVT::i64, Custom); + setOperationAction(ISD::SDIV, MVT::i32, Expand); + setOperationAction(ISD::SREM, MVT::i32, Expand); + setOperationAction(ISD::UDIV, MVT::i32, Expand); + setOperationAction(ISD::UREM, MVT::i32, Expand); + setOperationAction(ISD::SDIV, MVT::i64, Expand); + setOperationAction(ISD::SREM, MVT::i64, Expand); + setOperationAction(ISD::UDIV, MVT::i64, Expand); + setOperationAction(ISD::UREM, MVT::i64, Expand); + setOperationAction(ISD::BR_CC, MVT::f32, Expand); + setOperationAction(ISD::BR_CC, MVT::f64, Expand); + setOperationAction(ISD::BR_CC, MVT::i32, Expand); + setOperationAction(ISD::BR_CC, MVT::i64, Expand); + setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); + setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); + setOperationAction(ISD::SELECT_CC, MVT::f32, Expand); + setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); + setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); + setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); + setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); + setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); + setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); + if (Subtarget.hasCnMips()) { + setOperationAction(ISD::CTPOP, MVT::i32, Legal); + setOperationAction(ISD::CTPOP, MVT::i64, Legal); + } + else { + setOperationAction(ISD::CTPOP, MVT::i32, Expand); + setOperationAction(ISD::CTPOP, MVT::i64, Expand); + } + setOperationAction(ISD::CTTZ, MVT::i32, Expand); + setOperationAction(ISD::CTTZ, MVT::i64, Expand); + setOperationAction(ISD::ROTL, MVT::i32, Expand); + setOperationAction(ISD::ROTL, MVT::i64, Expand); + setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); + setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); + if (!Subtarget.hasMips32r2()) + setOperationAction(ISD::ROTR, MVT::i32, Expand); + if (!Subtarget.hasMips64r2()) + setOperationAction(ISD::ROTR, MVT::i64, Expand); + setOperationAction(ISD::FSIN, MVT::f32, Expand); + setOperationAction(ISD::FSIN, MVT::f64, Expand); + setOperationAction(ISD::FCOS, MVT::f32, Expand); + setOperationAction(ISD::FCOS, MVT::f64, Expand); + setOperationAction(ISD::FSINCOS, MVT::f32, Expand); + setOperationAction(ISD::FSINCOS, MVT::f64, Expand); + setOperationAction(ISD::FPOW, MVT::f32, Expand); + setOperationAction(ISD::FPOW, MVT::f64, Expand); + setOperationAction(ISD::FLOG, MVT::f32, Expand); + setOperationAction(ISD::FLOG2, MVT::f32, Expand); + setOperationAction(ISD::FLOG10, MVT::f32, Expand); + setOperationAction(ISD::FEXP, MVT::f32, Expand); + setOperationAction(ISD::FMA, MVT::f32, Expand); + setOperationAction(ISD::FMA, MVT::f64, Expand); + setOperationAction(ISD::FREM, MVT::f32, Expand); + setOperationAction(ISD::FREM, MVT::f64, Expand); + setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand); + setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand); + setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand); + setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand); + setOperationAction(ISD::EH_RETURN, MVT::Other, Custom); + setOperationAction(ISD::VASTART, MVT::Other, Custom); + setOperationAction(ISD::VAARG, MVT::Other, Custom); + setOperationAction(ISD::VACOPY, MVT::Other, Expand); + setOperationAction(ISD::VAEND, MVT::Other, Expand); + setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); + setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); + if (!Subtarget.isGP64bit()) { + setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand); + setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand); + } + if (!Subtarget.hasMips32r2()) { + setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); + setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); + } + if (!Subtarget.hasMips32() || Subtarget.inMips16Mode()) + setOperationAction(ISD::CTLZ, MVT::i32, Expand); + if (!Subtarget.hasMips64()) + setOperationAction(ISD::CTLZ, MVT::i64, Expand); + if (!Subtarget.hasMips32r2()) + setOperationAction(ISD::BSWAP, MVT::i32, Expand); + if (!Subtarget.hasMips64r2()) + setOperationAction(ISD::BSWAP, MVT::i64, Expand); + if (Subtarget.isGP64bit()) { + setLoadExtAction(ISD::SEXTLOAD, MVT::i64, MVT::i32, Custom); + setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, MVT::i32, Custom); + setLoadExtAction(ISD::EXTLOAD, MVT::i64, MVT::i32, Custom); + setTruncStoreAction(MVT::i64, MVT::i32, Custom); + } + setOperationAction(ISD::TRAP, MVT::Other, Legal); + setTargetDAGCombine(ISD::SDIVREM); + setTargetDAGCombine(ISD::UDIVREM); + setTargetDAGCombine(ISD::SELECT); + setTargetDAGCombine(ISD::AND); + setTargetDAGCombine(ISD::OR); + setTargetDAGCombine(ISD::ADD); + setTargetDAGCombine(ISD::SUB); + setTargetDAGCombine(ISD::AssertZext); + setTargetDAGCombine(ISD::SHL); + if (ABI.IsO32()) { + setLibcallName(RTLIB::SHL_I128, nullptr); + setLibcallName(RTLIB::SRL_I128, nullptr); + setLibcallName(RTLIB::SRA_I128, nullptr); + } + setMinFunctionAlignment(Subtarget.isGP64bit() ? Align(8) : Align(4)); + setMinStackArgumentAlignment((ABI.IsN32() || ABI.IsN64()) ? Align(8) : Align(4)); + setStackPointerRegisterToSaveRestore(ABI.IsN64() ? Mips::SP_64 : Mips::SP); + MaxStoresPerMemcpy = 16; + isMicroMips = Subtarget.inMicroMipsMode(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/allowsMisalignedMemoryAccesses.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/allowsMisalignedMemoryAccesses.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2e8b488397e8ffb971cb7c540a8516a91a44a93d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/allowsMisalignedMemoryAccesses.cpp @@ -0,0 +1,17 @@ +bool MipsSETargetLowering::allowsMisalignedMemoryAccesses(EVT VT, unsigned, unsigned, MachineMemOperand::Flags, bool *Fast) const { + MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy; + if (Subtarget.systemSupportsUnalignedAccess()) { + if (Fast) + *Fast = true; + return true; + } + switch (SVT) { + case MVT::i64: + case MVT::i32: + if (Fast) + *Fast = true; + return true; + default: + return false; + } +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/analyzeInputArgs.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/analyzeInputArgs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/analyzeInputArgs.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/analyzeOutputArgs.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/analyzeOutputArgs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/analyzeOutputArgs.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/computeKnownBitsForTargetNode.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/computeKnownBitsForTargetNode.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/computeKnownBitsForTargetNode.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/convertSelectOfConstantsToMath.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/convertSelectOfConstantsToMath.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/convertSelectOfConstantsToMath.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/convertSetCCLogicToBitwiseLogic.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/convertSetCCLogicToBitwiseLogic.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/convertSetCCLogicToBitwiseLogic.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/decomposeMulByConstant.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/decomposeMulByConstant.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/decomposeMulByConstant.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/emitLeadingFence.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/emitLeadingFence.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/emitLeadingFence.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/emitMaskedAtomicCmpXchgIntrinsic.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/emitMaskedAtomicCmpXchgIntrinsic.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d24252a436720a3ccdecb69c990fff58341ff97c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/emitMaskedAtomicCmpXchgIntrinsic.cpp @@ -0,0 +1,2 @@ +None + diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/emitMaskedAtomicRMWIntrinsic.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/emitMaskedAtomicRMWIntrinsic.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/emitMaskedAtomicRMWIntrinsic.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/emitTrailingFence.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/emitTrailingFence.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/emitTrailingFence.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/getAddr.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/getAddr.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/getAddr.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/getConstraintType.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/getConstraintType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d8529203a68b93db156ea88f4c58badf30013605 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/getConstraintType.cpp @@ -0,0 +1,19 @@ +MipsTargetLowering::ConstraintType MipsTargetLowering::getConstraintType(StringRef Constraint) const { + if (Constraint.size() == 1) { + switch (Constraint[0]) { + default : break; + case 'd': + case 'y': + case 'f': + case 'c': + case 'l': + case 'x': + return C_RegisterClass; + case 'R': + return C_Memory; + } + } + if (Constraint == "ZC") + return C_Memory; + return TargetLowering::getConstraintType(Constraint); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/getDynamicTLSAddr.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/getDynamicTLSAddr.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/getDynamicTLSAddr.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/getExceptionPointerRegister.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/getExceptionPointerRegister.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2e1945b520bebcf77f44fd1b55ba871b480d9979 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/getExceptionPointerRegister.cpp @@ -0,0 +1,3 @@ +Register getExceptionPointerRegister(const Constant *PersonalityFn) const override { + return ABI.IsN64() ? Mips::A0_64 : Mips::A0; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/getExceptionSelectorRegister.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/getExceptionSelectorRegister.cpp new file mode 100644 index 0000000000000000000000000000000000000000..524ffc7c7a6f16e757f2bce1263a2c3b76aa8e7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/getExceptionSelectorRegister.cpp @@ -0,0 +1,3 @@ +Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override { + return ABI.IsN64() ? Mips::A1_64 : Mips::A1; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/getExtendForAtomicCmpSwapArg.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/getExtendForAtomicCmpSwapArg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/getExtendForAtomicCmpSwapArg.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/getExtendForAtomicOps.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/getExtendForAtomicOps.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2bdaa6084dd596ee35663f176faa01eba5d98abc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/getExtendForAtomicOps.cpp @@ -0,0 +1,3 @@ +ISD::NodeType getExtendForAtomicOps() const override { + return ISD::SIGN_EXTEND; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/getInlineAsmMemConstraint.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/getInlineAsmMemConstraint.cpp new file mode 100644 index 0000000000000000000000000000000000000000..04c12c2b8a5307ff84006a5e7df9df7f9f5c5066 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/getInlineAsmMemConstraint.cpp @@ -0,0 +1,9 @@ +unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override { + if (ConstraintCode == "o") + return InlineAsm::Constraint_o; + if (ConstraintCode == "R") + return InlineAsm::Constraint_R; + if (ConstraintCode == "ZC") + return InlineAsm::Constraint_ZC; + return TargetLowering::getInlineAsmMemConstraint(ConstraintCode); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/getPointerMemTy.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/getPointerMemTy.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/getPointerMemTy.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/getPointerTy.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/getPointerTy.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/getPointerTy.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/getPostIndexedAddressParts.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/getPostIndexedAddressParts.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/getPostIndexedAddressParts.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/getRegForInlineAsmConstraint.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/getRegForInlineAsmConstraint.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c4d6cb04cdaf5d170a432c7141d5bcd31383559f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/getRegForInlineAsmConstraint.cpp @@ -0,0 +1,56 @@ +std::pair MipsTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const { + if (Constraint.size() == 1) { + switch (Constraint[0]) { + case 'd': + case 'y': + case 'r': + if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) { + if (Subtarget.inMips16Mode()) + return std::make_pair(0U, &Mips::CPU16RegsRegClass); + return std::make_pair(0U, &Mips::GPR32RegClass); + } + if (VT == MVT::i64 && !Subtarget.isGP64bit()) + return std::make_pair(0U, &Mips::GPR32RegClass); + if (VT == MVT::i64 && Subtarget.isGP64bit()) + return std::make_pair(0U, &Mips::GPR64RegClass); + return std::make_pair(0U, nullptr); + case 'f': + if (VT == MVT::v16i8) + return std::make_pair(0U, &Mips::MSA128BRegClass); + else if (VT == MVT::v8i16 || VT == MVT::v8f16) + return std::make_pair(0U, &Mips::MSA128HRegClass); + else if (VT == MVT::v4i32 || VT == MVT::v4f32) + return std::make_pair(0U, &Mips::MSA128WRegClass); + else if (VT == MVT::v2i64 || VT == MVT::v2f64) + return std::make_pair(0U, &Mips::MSA128DRegClass); + else if (VT == MVT::f32) + return std::make_pair(0U, &Mips::FGR32RegClass); + else if ((VT == MVT::f64) && (!Subtarget.isSingleFloat())) { + if (Subtarget.isFP64bit()) + return std::make_pair(0U, &Mips::FGR64RegClass); + return std::make_pair(0U, &Mips::AFGR64RegClass); + } + break; + case 'c': + if (VT == MVT::i32) + return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass); + if (VT == MVT::i64) + return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass); + return std::make_pair(0U, nullptr); + case 'l': + if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) + return std::make_pair((unsigned)Mips::LO0, &Mips::LO32RegClass); + return std::make_pair((unsigned)Mips::LO0_64, &Mips::LO64RegClass); + case 'x': + return std::make_pair(0U, nullptr); + } + } + if (!Constraint.empty()) { + std::pair R; + R = parseRegForInlineAsmConstraint(Constraint, VT); + if (R.second) + return R; + } + return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT); +} + diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/getRegisterByName.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/getRegisterByName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1c5d4d71ea246662da31c1159df7bf2f85432788 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/getRegisterByName.cpp @@ -0,0 +1,13 @@ +Register MipsTargetLowering::getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const { + if (Subtarget.isGP64bit()) { + Register Reg = StringSwitch(RegName).Case("$28", Mips::GP_64).Default(Register()); + if (Reg) + return Reg; + } + else { + Register Reg = StringSwitch(RegName).Case("$28", Mips::GP).Default(Register()); + if (Reg) + return Reg; + } + report_fatal_error("Invalid register name global variable"); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/getScalarShiftAmountTy.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/getScalarShiftAmountTy.cpp new file mode 100644 index 0000000000000000000000000000000000000000..619cc9eaf53f1510ccde851e748b819574304f6d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/getScalarShiftAmountTy.cpp @@ -0,0 +1,3 @@ +MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override { + return MVT::i32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/getSetCCResultType.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/getSetCCResultType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fe00ebaa7cd5963c92ec9096a55e880e01f1a0fc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/getSetCCResultType.cpp @@ -0,0 +1,6 @@ +EVT MipsTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &, EVT VT) const { + if (!VT.isVector()) { + return MVT::i32; + } + return VT.changeVectorElementTypeToInteger(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/getStaticTLSAddr.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/getStaticTLSAddr.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/getStaticTLSAddr.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/getSubtarget.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/getSubtarget.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/getSubtarget.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/getTargetNodeName.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/getTargetNodeName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..999d3eb5bc14010c14260323f1dcec49e3115019 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/getTargetNodeName.cpp @@ -0,0 +1,118 @@ +const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const { + switch ((MipsISD::NodeType)Opcode) { + case MipsISD::FIRST_NUMBER: break; + case MipsISD::JmpLink: return "MipsISD::JmpLink"; + case MipsISD::TailCall: return "MipsISD::TailCall"; + case MipsISD::Highest: return "MipsISD::Highest"; + case MipsISD::Higher: return "MipsISD::Higher"; + case MipsISD::Hi: return "MipsISD::Hi"; + case MipsISD::Lo: return "MipsISD::Lo"; + case MipsISD::GotHi: return "MipsISD::GotHi"; + case MipsISD::TlsHi: return "MipsISD::TlsHi"; + case MipsISD::GPRel: return "MipsISD::GPRel"; + case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer"; + case MipsISD::Ret: return "MipsISD::Ret"; + case MipsISD::ERet: return "MipsISD::ERet"; + case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN"; + case MipsISD::FMS: return "MipsISD::FMS"; + case MipsISD::FPBrcond: return "MipsISD::FPBrcond"; + case MipsISD::FPCmp: return "MipsISD::FPCmp"; + case MipsISD::FSELECT: return "MipsISD::FSELECT"; + case MipsISD::MTC1_D64: return "MipsISD::MTC1_D64"; + case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T"; + case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F"; + case MipsISD::TruncIntFP: return "MipsISD::TruncIntFP"; + case MipsISD::MFHI: return "MipsISD::MFHI"; + case MipsISD::MFLO: return "MipsISD::MFLO"; + case MipsISD::MTLOHI: return "MipsISD::MTLOHI"; + case MipsISD::Mult: return "MipsISD::Mult"; + case MipsISD::Multu: return "MipsISD::Multu"; + case MipsISD::MAdd: return "MipsISD::MAdd"; + case MipsISD::MAddu: return "MipsISD::MAddu"; + case MipsISD::MSub: return "MipsISD::MSub"; + case MipsISD::MSubu: return "MipsISD::MSubu"; + case MipsISD::DivRem: return "MipsISD::DivRem"; + case MipsISD::DivRemU: return "MipsISD::DivRemU"; + case MipsISD::DivRem16: return "MipsISD::DivRem16"; + case MipsISD::DivRemU16: return "MipsISD::DivRemU16"; + case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64"; + case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64"; + case MipsISD::Wrapper: return "MipsISD::Wrapper"; + case MipsISD::DynAlloc: return "MipsISD::DynAlloc"; + case MipsISD::Sync: return "MipsISD::Sync"; + case MipsISD::Ext: return "MipsISD::Ext"; + case MipsISD::Ins: return "MipsISD::Ins"; + case MipsISD::CIns: return "MipsISD::CIns"; + case MipsISD::LWL: return "MipsISD::LWL"; + case MipsISD::LWR: return "MipsISD::LWR"; + case MipsISD::SWL: return "MipsISD::SWL"; + case MipsISD::SWR: return "MipsISD::SWR"; + case MipsISD::LDL: return "MipsISD::LDL"; + case MipsISD::LDR: return "MipsISD::LDR"; + case MipsISD::SDL: return "MipsISD::SDL"; + case MipsISD::SDR: return "MipsISD::SDR"; + case MipsISD::EXTP: return "MipsISD::EXTP"; + case MipsISD::EXTPDP: return "MipsISD::EXTPDP"; + case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H"; + case MipsISD::EXTR_W: return "MipsISD::EXTR_W"; + case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W"; + case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W"; + case MipsISD::SHILO: return "MipsISD::SHILO"; + case MipsISD::MTHLIP: return "MipsISD::MTHLIP"; + case MipsISD::MULSAQ_S_W_PH: return "MipsISD::MULSAQ_S_W_PH"; + case MipsISD::MAQ_S_W_PHL: return "MipsISD::MAQ_S_W_PHL"; + case MipsISD::MAQ_S_W_PHR: return "MipsISD::MAQ_S_W_PHR"; + case MipsISD::MAQ_SA_W_PHL: return "MipsISD::MAQ_SA_W_PHL"; + case MipsISD::MAQ_SA_W_PHR: return "MipsISD::MAQ_SA_W_PHR"; + case MipsISD::DPAU_H_QBL: return "MipsISD::DPAU_H_QBL"; + case MipsISD::DPAU_H_QBR: return "MipsISD::DPAU_H_QBR"; + case MipsISD::DPSU_H_QBL: return "MipsISD::DPSU_H_QBL"; + case MipsISD::DPSU_H_QBR: return "MipsISD::DPSU_H_QBR"; + case MipsISD::DPAQ_S_W_PH: return "MipsISD::DPAQ_S_W_PH"; + case MipsISD::DPSQ_S_W_PH: return "MipsISD::DPSQ_S_W_PH"; + case MipsISD::DPAQ_SA_L_W: return "MipsISD::DPAQ_SA_L_W"; + case MipsISD::DPSQ_SA_L_W: return "MipsISD::DPSQ_SA_L_W"; + case MipsISD::DPA_W_PH: return "MipsISD::DPA_W_PH"; + case MipsISD::DPS_W_PH: return "MipsISD::DPS_W_PH"; + case MipsISD::DPAQX_S_W_PH: return "MipsISD::DPAQX_S_W_PH"; + case MipsISD::DPAQX_SA_W_PH: return "MipsISD::DPAQX_SA_W_PH"; + case MipsISD::DPAX_W_PH: return "MipsISD::DPAX_W_PH"; + case MipsISD::DPSX_W_PH: return "MipsISD::DPSX_W_PH"; + case MipsISD::DPSQX_S_W_PH: return "MipsISD::DPSQX_S_W_PH"; + case MipsISD::DPSQX_SA_W_PH: return "MipsISD::DPSQX_SA_W_PH"; + case MipsISD::MULSA_W_PH: return "MipsISD::MULSA_W_PH"; + case MipsISD::MULT: return "MipsISD::MULT"; + case MipsISD::MULTU: return "MipsISD::MULTU"; + case MipsISD::MADD_DSP: return "MipsISD::MADD_DSP"; + case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP"; + case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP"; + case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP"; + case MipsISD::SHLL_DSP: return "MipsISD::SHLL_DSP"; + case MipsISD::SHRA_DSP: return "MipsISD::SHRA_DSP"; + case MipsISD::SHRL_DSP: return "MipsISD::SHRL_DSP"; + case MipsISD::SETCC_DSP: return "MipsISD::SETCC_DSP"; + case MipsISD::SELECT_CC_DSP: return "MipsISD::SELECT_CC_DSP"; + case MipsISD::VALL_ZERO: return "MipsISD::VALL_ZERO"; + case MipsISD::VANY_ZERO: return "MipsISD::VANY_ZERO"; + case MipsISD::VALL_NONZERO: return "MipsISD::VALL_NONZERO"; + case MipsISD::VANY_NONZERO: return "MipsISD::VANY_NONZERO"; + case MipsISD::VCEQ: return "MipsISD::VCEQ"; + case MipsISD::VCLE_S: return "MipsISD::VCLE_S"; + case MipsISD::VCLE_U: return "MipsISD::VCLE_U"; + case MipsISD::VCLT_S: return "MipsISD::VCLT_S"; + case MipsISD::VCLT_U: return "MipsISD::VCLT_U"; + case MipsISD::VEXTRACT_SEXT_ELT: return "MipsISD::VEXTRACT_SEXT_ELT"; + case MipsISD::VEXTRACT_ZEXT_ELT: return "MipsISD::VEXTRACT_ZEXT_ELT"; + case MipsISD::VNOR: return "MipsISD::VNOR"; + case MipsISD::VSHF: return "MipsISD::VSHF"; + case MipsISD::SHF: return "MipsISD::SHF"; + case MipsISD::ILVEV: return "MipsISD::ILVEV"; + case MipsISD::ILVOD: return "MipsISD::ILVOD"; + case MipsISD::ILVL: return "MipsISD::ILVL"; + case MipsISD::ILVR: return "MipsISD::ILVR"; + case MipsISD::PCKEV: return "MipsISD::PCKEV"; + case MipsISD::PCKOD: return "MipsISD::PCKOD"; + case MipsISD::INSVE: return "MipsISD::INSVE"; + } + return nullptr; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/getTgtMemIntrinsic.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/getTgtMemIntrinsic.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/getTgtMemIntrinsic.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/hasBitPreservingFPLogic.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/hasBitPreservingFPLogic.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/hasBitPreservingFPLogic.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/isCheapToSpeculateCtlz.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/isCheapToSpeculateCtlz.cpp new file mode 100644 index 0000000000000000000000000000000000000000..427f606640a0f495babbc3c5472fed65979665f6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/isCheapToSpeculateCtlz.cpp @@ -0,0 +1,3 @@ +bool MipsTargetLowering::isCheapToSpeculateCtlz() const { + return Subtarget.hasMips32(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/isCheapToSpeculateCttz.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/isCheapToSpeculateCttz.cpp new file mode 100644 index 0000000000000000000000000000000000000000..169d4b4109f983c5149a60aca7d2757d876881b3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/isCheapToSpeculateCttz.cpp @@ -0,0 +1,3 @@ +bool MipsTargetLowering::isCheapToSpeculateCttz() const { + return Subtarget.hasMips32(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/isDesirableToCommuteWithShift.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/isDesirableToCommuteWithShift.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/isDesirableToCommuteWithShift.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/isEligibleForTailCallOptimization.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/isEligibleForTailCallOptimization.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a11da12c981206c45489e9ede21981c97f116aba --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/isEligibleForTailCallOptimization.cpp @@ -0,0 +1,9 @@ +bool MipsSETargetLowering::isEligibleForTailCallOptimization(const CCState &CCInfo, unsigned NextStackOffset, const MipsFunctionInfo &FI) const { + if (!UseMipsTailCalls) + return false; + if (FI.isISR()) + return false; + if (CCInfo.getInRegsParamsCount() > 0 || FI.hasByvalArg()) + return false; + return NextStackOffset <= FI.getIncomingArgSize(); +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/isFMAFasterThanFMulAndFAdd.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/isFMAFasterThanFMulAndFAdd.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/isFMAFasterThanFMulAndFAdd.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/isFPImmLegal.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/isFPImmLegal.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9419a0fddfba1adb1a506c85ee0e7d6b360839c5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/isFPImmLegal.cpp @@ -0,0 +1,7 @@ +bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const { + if (VT != MVT::f32 && VT != MVT::f64) + return false; + if (Imm.isNegZero()) + return false; + return Imm.isZero(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/isLegalAddImmediate.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/isLegalAddImmediate.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/isLegalAddImmediate.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/isLegalAddressingMode.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/isLegalAddressingMode.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bce29b2aa473dfb01a1adc6b39d25eec12f141ab --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/isLegalAddressingMode.cpp @@ -0,0 +1,15 @@ +bool MipsTargetLowering::isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I) const { + if (AM.BaseGV) + return false; + switch (AM.Scale) { + case 0: + break; + case 1: + if (!AM.HasBaseReg) + break; + return false; + default: + return false; + } + return true; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/isLegalICmpImmediate.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/isLegalICmpImmediate.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/isLegalICmpImmediate.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/isSExtCheaperThanZExt.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/isSExtCheaperThanZExt.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/isSExtCheaperThanZExt.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/isTruncateFree.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/isTruncateFree.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/isTruncateFree.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/isTruncateFree2.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/isTruncateFree2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/isTruncateFree2.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/isZExtFree.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/isZExtFree.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/isZExtFree.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/lowerEXTRACT_VECTOR_ELT.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/lowerEXTRACT_VECTOR_ELT.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c7f0b8be13658b20f7e13eee561be03722d32593 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/lowerEXTRACT_VECTOR_ELT.cpp @@ -0,0 +1,14 @@ +SDValue MipsSETargetLowering::lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const { + SDLoc DL(Op); + EVT ResTy = Op->getValueType(0); + SDValue Op0 = Op->getOperand(0); + EVT VecTy = Op0->getValueType(0); + if (!VecTy.is128BitVector()) + return SDValue(); + if (ResTy.isInteger()) { + SDValue Op1 = Op->getOperand(1); + EVT EltTy = VecTy.getVectorElementType(); + return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, DL, ResTy, Op0, Op1, DAG.getValueType(EltTy)); + } + return Op; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/lowerINSERT_VECTOR_ELT.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/lowerINSERT_VECTOR_ELT.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/lowerINSERT_VECTOR_ELT.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/lowerSELECT.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/lowerSELECT.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8ccc7415a4e7fc3ff6f6faf8cb2df39facab5474 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/lowerSELECT.cpp @@ -0,0 +1,7 @@ +SDValue MipsTargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const { + assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); + SDValue Cond = createFPCmp(DAG, Op.getOperand(0)); + if (Cond.getOpcode() != MipsISD::FPCmp) + return Op; + return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2), SDLoc(Op)); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/lowerSPLATVECTOR.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/lowerSPLATVECTOR.cpp new file mode 100644 index 0000000000000000000000000000000000000000..dc4822b4dace5d5d62f234df92749f851e92acbc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/lowerSPLATVECTOR.cpp @@ -0,0 +1,3 @@ +None + + diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/lowerShiftLeftParts.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/lowerShiftLeftParts.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1fa999e2c8ce2bc3c16770b5abd0a2f1aa9900a0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/lowerShiftLeftParts.cpp @@ -0,0 +1,17 @@ +SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const { + SDLoc DL(Op); + MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32; + SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); + SDValue Shamt = Op.getOperand(2); + SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, DAG.getConstant(-1, DL, MVT::i32)); + SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo, DAG.getConstant(1, DL, VT)); + SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, Not); + SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt); + SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo); + SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt); + SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32)); + Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, DAG.getConstant(0, DL, VT), ShiftLeftLo); + Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or); + SDValue Ops[2] = {Lo, Hi}; + return DAG.getMergeValues(Ops, DL); +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/lowerShiftRightParts.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/lowerShiftRightParts.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b15ec88f4c37aaf44b6a8c2e28d3acfcac6e939a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/lowerShiftRightParts.cpp @@ -0,0 +1,22 @@ +SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const { + SDLoc DL(Op); + SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); + SDValue Shamt = Op.getOperand(2); + MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32; + SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, DAG.getConstant(-1, DL, MVT::i32)); + SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, DAG.getConstant(1, DL, VT)); + SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeft1Hi, Not); + SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt); + SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo); + SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, Shamt); + SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32)); + SDValue Ext = DAG.getNode(ISD::SRA, DL, VT, Hi, DAG.getConstant(VT.getSizeInBits() - 1, DL, VT)); + if (!(Subtarget.hasMips4() || Subtarget.hasMips32())) { + SDVTList VTList = DAG.getVTList(VT, VT); + return DAG.getNode(Subtarget.isGP64bit() ? Mips::PseudoD_SELECT_I64 : Mips::PseudoD_SELECT_I, DL, VTList, Cond, ShiftRightHi, IsSRA ? Ext : DAG.getConstant(0, DL, VT), Or, ShiftRightHi); + } + Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or); + Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, IsSRA ? Ext : DAG.getConstant(0, DL, VT), ShiftRightHi); + SDValue Ops[2] = {Lo, Hi}; + return DAG.getMergeValues(Ops, DL); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/lowerVectorMaskExt.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/lowerVectorMaskExt.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/lowerVectorMaskExt.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/lowerVectorMaskTrunc.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/lowerVectorMaskTrunc.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/lowerVectorMaskTrunc.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/mayBeEmittedAsTailCall.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/mayBeEmittedAsTailCall.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/mayBeEmittedAsTailCall.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/normaliseSetCC.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/normaliseSetCC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/normaliseSetCC.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/normalizeSetCC.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/normalizeSetCC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f68f25a787d6d9d179404a12f57ee6bc55abf05a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/normalizeSetCC.cpp @@ -0,0 +1,2 @@ +static void normaliseSetCC(SDValue &LHS, SDValue &RHS, ISD::CondCode &CC) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/shouldConsiderGEPOffsetSplit.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/shouldConsiderGEPOffsetSplit.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/shouldConsiderGEPOffsetSplit.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/shouldConvertConstantLoadToIntImm.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/shouldConvertConstantLoadToIntImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/shouldConvertConstantLoadToIntImm.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/shouldExpandAtomicCmpXchgInIR.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/shouldExpandAtomicCmpXchgInIR.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/shouldExpandAtomicCmpXchgInIR.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/shouldExpandAtomicRMWInIR.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/shouldExpandAtomicRMWInIR.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/shouldExpandAtomicRMWInIR.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/shouldExpandShift.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/shouldExpandShift.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/shouldExpandShift.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/shouldExtendTypeInLibCall.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/shouldExtendTypeInLibCall.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/shouldExtendTypeInLibCall.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/shouldInsertFencesForAtomic.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/shouldInsertFencesForAtomic.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8633411d86591074b31a54b78e3486a650b9eb13 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/shouldInsertFencesForAtomic.cpp @@ -0,0 +1,3 @@ +bool shouldInsertFencesForAtomic(const Instruction *I) const override { + return true; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/shouldSignExtendTypeInLibCall.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/shouldSignExtendTypeInLibCall.cpp new file mode 100644 index 0000000000000000000000000000000000000000..959ee62f318ee63e3f1f4208c95ae43a1a6e7761 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/shouldSignExtendTypeInLibCall.cpp @@ -0,0 +1,5 @@ +bool MipsTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const { + if ((ABI.IsN32() || ABI.IsN64()) && Type == MVT::i32) + return true; + return IsSigned; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/targetShrinkDemandedConstant.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/targetShrinkDemandedConstant.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/targetShrinkDemandedConstant.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/validateCCReservedRegs.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/validateCCReservedRegs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/ISelLowering/validateCCReservedRegs.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/InstructionSelector/InstructionSelector.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/InstructionSelector/InstructionSelector.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4dec9cfa317b44f43b2ec7db58442782f2df351e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/InstructionSelector/InstructionSelector.cpp @@ -0,0 +1,9 @@ +MipsInstructionSelector::MipsInstructionSelector(const MipsTargetMachine &TM, const MipsSubtarget &STI, const MipsRegisterBankInfo &RBI) : InstructionSelector(), TM(TM), STI(STI), TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()), RBI(RBI), +#define GET_GLOBALISEL_PREDICATES_INIT +#include "MipsGenGlobalISel.inc" +#undef GET_GLOBALISEL_PREDICATES_INIT +#define GET_GLOBALISEL_TEMPORARIES_INIT +#include "MipsGenGlobalISel.inc" +#undef GET_GLOBALISEL_TEMPORARIES_INIT +{ +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/InstructionSelector/createInstructionSelector.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/InstructionSelector/createInstructionSelector.cpp new file mode 100644 index 0000000000000000000000000000000000000000..dad172a8ea90b139f00256911eedcffbae14848d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/InstructionSelector/createInstructionSelector.cpp @@ -0,0 +1,3 @@ +InstructionSelector *createMipsInstructionSelector(const MipsTargetMachine &TM, MipsSubtarget &Subtarget, MipsRegisterBankInfo &RBI) { + return new MipsInstructionSelector(TM, Subtarget, RBI); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/InstructionSelector/getName.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/InstructionSelector/getName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3070f67f8b2d72c6473a6bf2cc4639c82757caaa --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/InstructionSelector/getName.cpp @@ -0,0 +1,3 @@ +static const char *getName() { + return DEBUG_TYPE; +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/InstructionSelector/select.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/InstructionSelector/select.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5a17b427bb0cd822697fc1bb9f4a5c2c68b1a435 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/InstructionSelector/select.cpp @@ -0,0 +1,443 @@ +bool MipsInstructionSelector::select(MachineInstr &I) { + MachineBasicBlock &MBB = *I.getParent(); + MachineFunction &MF = *MBB.getParent(); + MachineRegisterInfo &MRI = MF.getRegInfo(); + if (!isPreISelGenericOpcode(I.getOpcode())) { + if (I.isCopy()) + return selectCopy(I, MRI); + return true; + } + if (I.getOpcode() == Mips::G_MUL && isRegInGprb(I.getOperand(0).getReg(), MRI)) { + MachineInstr *Mul = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MUL)).add(I.getOperand(0)).add(I.getOperand(1)).add(I.getOperand(2)); + if (!constrainSelectedInstRegOperands(*Mul, TII, TRI, RBI)) + return false; + Mul->getOperand(3).setIsDead(true); + Mul->getOperand(4).setIsDead(true); + I.eraseFromParent(); + return true; + } + if (selectImpl(I, *CoverageInfo)) + return true; + MachineInstr *MI = nullptr; + using namespace TargetOpcode; + switch (I.getOpcode()) { + case G_UMULH: { + Register PseudoMULTuReg = MRI.createVirtualRegister(&Mips::ACC64RegClass); + MachineInstr *PseudoMULTu, *PseudoMove; + PseudoMULTu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoMULTu)).addDef(PseudoMULTuReg).add(I.getOperand(1)).add(I.getOperand(2)); + if (!constrainSelectedInstRegOperands(*PseudoMULTu, TII, TRI, RBI)) + return false; + PseudoMove = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoMFHI)).addDef(I.getOperand(0).getReg()).addUse(PseudoMULTuReg); + if (!constrainSelectedInstRegOperands(*PseudoMove, TII, TRI, RBI)) + return false; + + I.eraseFromParent(); + return true; + } + case G_PTR_ADD: { + MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu)).add(I.getOperand(0)).add(I.getOperand(1)).add(I.getOperand(2)); + break; + } + case G_INTTOPTR: + case G_PTRTOINT: { + I.setDesc(TII.get(COPY)); + return selectCopy(I, MRI); + } + case G_FRAME_INDEX: { + MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu)).add(I.getOperand(0)).add(I.getOperand(1)).addImm(0); + break; + } + case G_BRCOND: { + MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::BNE)).add(I.getOperand(0)).addUse(Mips::ZERO).add(I.getOperand(1)); + break; + } + case G_BRJT: { + unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize(MF.getDataLayout()); + assert(isPowerOf2_32(EntrySize) && "Non-power-of-two jump-table entry size not supported."); + Register JTIndex = MRI.createVirtualRegister(&Mips::GPR32RegClass); + MachineInstr *SLL = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::SLL)).addDef(JTIndex).addUse(I.getOperand(2).getReg()).addImm(Log2_32(EntrySize)); + if (!constrainSelectedInstRegOperands(*SLL, TII, TRI, RBI)) + return false; + Register DestAddress = MRI.createVirtualRegister(&Mips::GPR32RegClass); + MachineInstr *ADDu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu)).addDef(DestAddress).addUse(I.getOperand(0).getReg()).addUse(JTIndex); + if (!constrainSelectedInstRegOperands(*ADDu, TII, TRI, RBI)) + return false; + Register Dest = MRI.createVirtualRegister(&Mips::GPR32RegClass); + MachineInstr *LW = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW)).addDef(Dest).addUse(DestAddress).addJumpTableIndex(I.getOperand(1).getIndex(), MipsII::MO_ABS_LO).addMemOperand(MF.getMachineMemOperand(MachinePointerInfo(), MachineMemOperand::MOLoad, 4, Align(4))); + if (!constrainSelectedInstRegOperands(*LW, TII, TRI, RBI)) + return false; + if (MF.getTarget().isPositionIndependent()) { + Register DestTmp = MRI.createVirtualRegister(&Mips::GPR32RegClass); + LW->getOperand(0).setReg(DestTmp); + MachineInstr *ADDu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu)).addDef(Dest).addUse(DestTmp).addUse(MF.getInfo()->getGlobalBaseRegForGlobalISel(MF)); + if (!constrainSelectedInstRegOperands(*ADDu, TII, TRI, RBI)) + return false; + } + MachineInstr *Branch = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoIndirectBranch)).addUse(Dest); + if (!constrainSelectedInstRegOperands(*Branch, TII, TRI, RBI)) + return false; + I.eraseFromParent(); + return true; + } + case G_BRINDIRECT: { + MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoIndirectBranch)).add(I.getOperand(0)); + break; + } + case G_PHI: { + const Register DestReg = I.getOperand(0).getReg(); + const TargetRegisterClass *DefRC = nullptr; + if (Register::isPhysicalRegister(DestReg)) + DefRC = TRI.getRegClass(DestReg); + else + DefRC = getRegClassForTypeOnBank(DestReg, MRI); + I.setDesc(TII.get(TargetOpcode::PHI)); + return RBI.constrainGenericRegister(DestReg, *DefRC, MRI); + } + case G_STORE: + case G_LOAD: + case G_ZEXTLOAD: + case G_SEXTLOAD: { + auto MMO = *I.memoperands_begin(); + MachineOperand BaseAddr = I.getOperand(1); + int64_t SignedOffset = 0; + MachineInstr *Addr = MRI.getVRegDef(I.getOperand(1).getReg()); + if (Addr->getOpcode() == G_PTR_ADD) { + MachineInstr *Offset = MRI.getVRegDef(Addr->getOperand(2).getReg()); + if (Offset->getOpcode() == G_CONSTANT) { + APInt OffsetValue = Offset->getOperand(1).getCImm()->getValue(); + if (OffsetValue.isSignedIntN(16)) { + BaseAddr = Addr->getOperand(1); + SignedOffset = OffsetValue.getSExtValue(); + } + } + } + if (MMO->getAlign() < MMO->getSize() && + !STI.systemSupportsUnalignedAccess()) { + if (MMO->getSize() != 4 || !isRegInGprb(I.getOperand(0).getReg(), MRI)) + return false; + if (I.getOpcode() == G_STORE) { + if (!buildUnalignedStore(I, Mips::SWL, BaseAddr, SignedOffset + 3, MMO)) + return false; + if (!buildUnalignedStore(I, Mips::SWR, BaseAddr, SignedOffset, MMO)) + return false; + I.eraseFromParent(); + return true; + } + if (I.getOpcode() == G_LOAD) { + Register ImplDef = MRI.createVirtualRegister(&Mips::GPR32RegClass); + BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::IMPLICIT_DEF)).addDef(ImplDef); + Register Tmp = MRI.createVirtualRegister(&Mips::GPR32RegClass); + if (!buildUnalignedLoad(I, Mips::LWL, Tmp, BaseAddr, SignedOffset + 3,ImplDef, MMO)) + return false; + if (!buildUnalignedLoad(I, Mips::LWR, I.getOperand(0).getReg(), BaseAddr, SignedOffset, Tmp, MMO)) + return false; + I.eraseFromParent(); + return true; + } + return false; + } + const unsigned NewOpc = selectLoadStoreOpCode(I, MRI); + if (NewOpc == I.getOpcode()) + return false; + MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(NewOpc)).add(I.getOperand(0)).add(BaseAddr).addImm(SignedOffset).addMemOperand(MMO); + break; + } + case G_UDIV: + case G_UREM: + case G_SDIV: + case G_SREM: { + Register HILOReg = MRI.createVirtualRegister(&Mips::ACC64RegClass); + bool IsSigned = I.getOpcode() == G_SREM || I.getOpcode() == G_SDIV; + bool IsDiv = I.getOpcode() == G_UDIV || I.getOpcode() == G_SDIV; + MachineInstr *PseudoDIV, *PseudoMove; + PseudoDIV = BuildMI(MBB, I, I.getDebugLoc(), TII.get(IsSigned ? Mips::PseudoSDIV : Mips::PseudoUDIV)).addDef(HILOReg).add(I.getOperand(1)).add(I.getOperand(2)); + if (!constrainSelectedInstRegOperands(*PseudoDIV, TII, TRI, RBI)) + return false; + PseudoMove = BuildMI(MBB, I, I.getDebugLoc(), TII.get(IsDiv ? Mips::PseudoMFLO : Mips::PseudoMFHI)).addDef(I.getOperand(0).getReg()).addUse(HILOReg); + if (!constrainSelectedInstRegOperands(*PseudoMove, TII, TRI, RBI)) + return false; + I.eraseFromParent(); + return true; + } + case G_SELECT: { + MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MOVN_I_I)).add(I.getOperand(0)).add(I.getOperand(2)).add(I.getOperand(1)).add(I.getOperand(3)); + break; + } + case G_UNMERGE_VALUES: { + if (I.getNumOperands() != 3) + return false; + Register Src = I.getOperand(2).getReg(); + Register Lo = I.getOperand(0).getReg(); + Register Hi = I.getOperand(1).getReg(); + if (!isRegInFprb(Src, MRI) || !(isRegInGprb(Lo, MRI) && isRegInGprb(Hi, MRI))) + return false; + unsigned Opcode = STI.isFP64bit() ? Mips::ExtractElementF64_64 : Mips::ExtractElementF64; + MachineInstr *ExtractLo = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Opcode)).addDef(Lo).addUse(Src).addImm(0); + if (!constrainSelectedInstRegOperands(*ExtractLo, TII, TRI, RBI)) + return false; + MachineInstr *ExtractHi = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Opcode)).addDef(Hi).addUse(Src).addImm(1); + if (!constrainSelectedInstRegOperands(*ExtractHi, TII, TRI, RBI)) + return false; + I.eraseFromParent(); + return true; + } + case G_IMPLICIT_DEF: { + Register Dst = I.getOperand(0).getReg(); + MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::IMPLICIT_DEF)).addDef(Dst); + MRI.setRegClass(Dst, getRegClassForTypeOnBank(Dst, MRI)); + break; + } + case G_CONSTANT: { + MachineIRBuilder B(I); + if (!materialize32BitImm(I.getOperand(0).getReg(), I.getOperand(1).getCImm()->getValue(), B)) + return false; + I.eraseFromParent(); + return true; + } + case G_FCONSTANT: { + const APFloat &FPimm = I.getOperand(1).getFPImm()->getValueAPF(); + APInt APImm = FPimm.bitcastToAPInt(); + unsigned Size = MRI.getType(I.getOperand(0).getReg()).getSizeInBits(); + if (Size == 32) { + Register GPRReg = MRI.createVirtualRegister(&Mips::GPR32RegClass); + MachineIRBuilder B(I); + if (!materialize32BitImm(GPRReg, APImm, B)) + return false; + MachineInstrBuilder MTC1 = B.buildInstr(Mips::MTC1, {I.getOperand(0).getReg()}, {GPRReg}); + if (!MTC1.constrainAllUses(TII, TRI, RBI)) + return false; + } + if (Size == 64) { + Register GPRRegHigh = MRI.createVirtualRegister(&Mips::GPR32RegClass); + Register GPRRegLow = MRI.createVirtualRegister(&Mips::GPR32RegClass); + MachineIRBuilder B(I); + if (!materialize32BitImm(GPRRegHigh, APImm.getHiBits(32).trunc(32), B)) + return false; + if (!materialize32BitImm(GPRRegLow, APImm.getLoBits(32).trunc(32), B)) + return false; + MachineInstrBuilder PairF64 = B.buildInstr(STI.isFP64bit() ? Mips::BuildPairF64_64 : Mips::BuildPairF64, {I.getOperand(0).getReg()}, {GPRRegLow, GPRRegHigh}); + if (!PairF64.constrainAllUses(TII, TRI, RBI)) + return false; + } + I.eraseFromParent(); + return true; + } + case G_FABS: { + unsigned Size = MRI.getType(I.getOperand(0).getReg()).getSizeInBits(); + unsigned FABSOpcode = Size == 32 ? Mips::FABS_S : STI.isFP64bit() ? Mips::FABS_D64 : Mips::FABS_D32; + MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(FABSOpcode)).add(I.getOperand(0)).add(I.getOperand(1)); + break; + } + case G_FPTOSI: { + unsigned FromSize = MRI.getType(I.getOperand(1).getReg()).getSizeInBits(); + unsigned ToSize = MRI.getType(I.getOperand(0).getReg()).getSizeInBits(); + (void)ToSize; + assert((ToSize == 32) && "Unsupported integer size for G_FPTOSI"); + assert((FromSize == 32 || FromSize == 64) && "Unsupported floating point size for G_FPTOSI"); + unsigned Opcode; + if (FromSize == 32) + Opcode = Mips::TRUNC_W_S; + else + Opcode = STI.isFP64bit() ? Mips::TRUNC_W_D64 : Mips::TRUNC_W_D32; + Register ResultInFPR = MRI.createVirtualRegister(&Mips::FGR32RegClass); + MachineInstr *Trunc = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Opcode)).addDef(ResultInFPR).addUse(I.getOperand(1).getReg()); + if (!constrainSelectedInstRegOperands(*Trunc, TII, TRI, RBI)) + return false; + MachineInstr *Move = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MFC1)).addDef(I.getOperand(0).getReg()).addUse(ResultInFPR); + if (!constrainSelectedInstRegOperands(*Move, TII, TRI, RBI)) + return false; + I.eraseFromParent(); + return true; + } + case G_GLOBAL_VALUE: { + const llvm::GlobalValue *GVal = I.getOperand(1).getGlobal(); + if (MF.getTarget().isPositionIndependent()) { + MachineInstr *LWGOT = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW)).addDef(I.getOperand(0).getReg()).addReg(MF.getInfo()->getGlobalBaseRegForGlobalISel(MF)).addGlobalAddress(GVal); + if (I.getOperand(1).getTargetFlags() == MipsII::MO_GOT_CALL) + LWGOT->getOperand(2).setTargetFlags(MipsII::MO_GOT_CALL); + else + LWGOT->getOperand(2).setTargetFlags(MipsII::MO_GOT); + LWGOT->addMemOperand(MF, MF.getMachineMemOperand(MachinePointerInfo::getGOT(MF), MachineMemOperand::MOLoad, 4, Align(4))); + if (!constrainSelectedInstRegOperands(*LWGOT, TII, TRI, RBI)) + return false; + if (GVal->hasLocalLinkage()) { + Register LWGOTDef = MRI.createVirtualRegister(&Mips::GPR32RegClass); + LWGOT->getOperand(0).setReg(LWGOTDef); + MachineInstr *ADDiu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu)).addDef(I.getOperand(0).getReg()).addReg(LWGOTDef).addGlobalAddress(GVal); + ADDiu->getOperand(2).setTargetFlags(MipsII::MO_ABS_LO); + if (!constrainSelectedInstRegOperands(*ADDiu, TII, TRI, RBI)) + return false; + } + } + else { + Register LUiReg = MRI.createVirtualRegister(&Mips::GPR32RegClass); + MachineInstr *LUi = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LUi)).addDef(LUiReg).addGlobalAddress(GVal); + LUi->getOperand(1).setTargetFlags(MipsII::MO_ABS_HI); + if (!constrainSelectedInstRegOperands(*LUi, TII, TRI, RBI)) + return false; + MachineInstr *ADDiu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu)).addDef(I.getOperand(0).getReg()).addUse(LUiReg).addGlobalAddress(GVal); + ADDiu->getOperand(2).setTargetFlags(MipsII::MO_ABS_LO); + if (!constrainSelectedInstRegOperands(*ADDiu, TII, TRI, RBI)) + return false; + } + I.eraseFromParent(); + return true; + } + case G_JUMP_TABLE: { + if (MF.getTarget().isPositionIndependent()) { + MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW)).addDef(I.getOperand(0).getReg()).addReg(MF.getInfo()->getGlobalBaseRegForGlobalISel(MF)).addJumpTableIndex(I.getOperand(1).getIndex(), MipsII::MO_GOT).addMemOperand(MF.getMachineMemOperand( MachinePointerInfo::getGOT(MF), MachineMemOperand::MOLoad, 4, Align(4))); + } + else { + MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LUi)).addDef(I.getOperand(0).getReg()).addJumpTableIndex(I.getOperand(1).getIndex(), MipsII::MO_ABS_HI); + } + break; + } + case G_ICMP: { + struct Instr { + unsigned Opcode; + Register Def, LHS, RHS; + Instr(unsigned Opcode, Register Def, Register LHS, Register RHS) : Opcode(Opcode), Def(Def), LHS(LHS), RHS(RHS){}; + bool hasImm() const { + if (Opcode == Mips::SLTiu || Opcode == Mips::XORi) + return true; + return false; + } + }; + SmallVector Instructions; + Register ICMPReg = I.getOperand(0).getReg(); + Register Temp = MRI.createVirtualRegister(&Mips::GPR32RegClass); + Register LHS = I.getOperand(2).getReg(); + Register RHS = I.getOperand(3).getReg(); + CmpInst::Predicate Cond = static_cast(I.getOperand(1).getPredicate()); + switch (Cond) { + case CmpInst::ICMP_EQ: + Instructions.emplace_back(Mips::XOR, Temp, LHS, RHS); + Instructions.emplace_back(Mips::SLTiu, ICMPReg, Temp, 1); + break; + case CmpInst::ICMP_NE: + Instructions.emplace_back(Mips::XOR, Temp, LHS, RHS); + Instructions.emplace_back(Mips::SLTu, ICMPReg, Mips::ZERO, Temp); + break; + case CmpInst::ICMP_UGT: + Instructions.emplace_back(Mips::SLTu, ICMPReg, RHS, LHS); + break; + case CmpInst::ICMP_UGE: + Instructions.emplace_back(Mips::SLTu, Temp, LHS, RHS); + Instructions.emplace_back(Mips::XORi, ICMPReg, Temp, 1); + break; + case CmpInst::ICMP_ULT: + Instructions.emplace_back(Mips::SLTu, ICMPReg, LHS, RHS); + break; + case CmpInst::ICMP_ULE: + Instructions.emplace_back(Mips::SLTu, Temp, RHS, LHS); + Instructions.emplace_back(Mips::XORi, ICMPReg, Temp, 1); + break; + case CmpInst::ICMP_SGT: + Instructions.emplace_back(Mips::SLT, ICMPReg, RHS, LHS); + break; + case CmpInst::ICMP_SGE: + Instructions.emplace_back(Mips::SLT, Temp, LHS, RHS); + Instructions.emplace_back(Mips::XORi, ICMPReg, Temp, 1); + break; + case CmpInst::ICMP_SLT: + Instructions.emplace_back(Mips::SLT, ICMPReg, LHS, RHS); + break; + case CmpInst::ICMP_SLE: + Instructions.emplace_back(Mips::SLT, Temp, RHS, LHS); + Instructions.emplace_back(Mips::XORi, ICMPReg, Temp, 1); + break; + default: + return false; + } + MachineIRBuilder B(I); + for (const struct Instr &Instruction : Instructions) { + MachineInstrBuilder MIB = B.buildInstr(Instruction.Opcode, {Instruction.Def}, {Instruction.LHS}); + if (Instruction.hasImm()) + MIB.addImm(Instruction.RHS); + else + MIB.addUse(Instruction.RHS); + if (!MIB.constrainAllUses(TII, TRI, RBI)) + return false; + } + I.eraseFromParent(); + return true; + } + case G_FCMP: { + unsigned MipsFCMPCondCode; + bool isLogicallyNegated; + switch (CmpInst::Predicate Cond = static_cast( I.getOperand(1).getPredicate())) { + case CmpInst::FCMP_UNO: + case CmpInst::FCMP_ORD: + MipsFCMPCondCode = Mips::FCOND_UN; + isLogicallyNegated = Cond != CmpInst::FCMP_UNO; + break; + case CmpInst::FCMP_OEQ: + case CmpInst::FCMP_UNE: + MipsFCMPCondCode = Mips::FCOND_OEQ; + isLogicallyNegated = Cond != CmpInst::FCMP_OEQ; + break; + case CmpInst::FCMP_UEQ: + case CmpInst::FCMP_ONE: + MipsFCMPCondCode = Mips::FCOND_UEQ; + isLogicallyNegated = Cond != CmpInst::FCMP_UEQ; + break; + case CmpInst::FCMP_OLT: + case CmpInst::FCMP_UGE: + MipsFCMPCondCode = Mips::FCOND_OLT; + isLogicallyNegated = Cond != CmpInst::FCMP_OLT; + break; + case CmpInst::FCMP_ULT: + case CmpInst::FCMP_OGE: + MipsFCMPCondCode = Mips::FCOND_ULT; + isLogicallyNegated = Cond != CmpInst::FCMP_ULT; + break; + case CmpInst::FCMP_OLE: + case CmpInst::FCMP_UGT: + MipsFCMPCondCode = Mips::FCOND_OLE; + isLogicallyNegated = Cond != CmpInst::FCMP_OLE; + break; + case CmpInst::FCMP_ULE: + case CmpInst::FCMP_OGT: + MipsFCMPCondCode = Mips::FCOND_ULE; + isLogicallyNegated = Cond != CmpInst::FCMP_ULE; + break; + default: + return false; + } + unsigned MoveOpcode = isLogicallyNegated ? Mips::MOVT_I : Mips::MOVF_I; + Register TrueInReg = MRI.createVirtualRegister(&Mips::GPR32RegClass); + BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu)).addDef(TrueInReg).addUse(Mips::ZERO).addImm(1); + unsigned Size = MRI.getType(I.getOperand(2).getReg()).getSizeInBits(); + unsigned FCMPOpcode = Size == 32 ? Mips::FCMP_S32 : STI.isFP64bit() ? Mips::FCMP_D64 : Mips::FCMP_D32; + MachineInstr *FCMP = BuildMI(MBB, I, I.getDebugLoc(), TII.get(FCMPOpcode)).addUse(I.getOperand(2).getReg()).addUse(I.getOperand(3).getReg()).addImm(MipsFCMPCondCode); + if (!constrainSelectedInstRegOperands(*FCMP, TII, TRI, RBI)) + return false; + MachineInstr *Move = BuildMI(MBB, I, I.getDebugLoc(), TII.get(MoveOpcode)).addDef(I.getOperand(0).getReg()).addUse(Mips::ZERO).addUse(Mips::FCC0).addUse(TrueInReg); + if (!constrainSelectedInstRegOperands(*Move, TII, TRI, RBI)) + return false; + I.eraseFromParent(); + return true; + } + case G_FENCE: { + MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::SYNC)).addImm(0); + break; + } + case G_VASTART: { + MipsFunctionInfo *FuncInfo = MF.getInfo(); + int FI = FuncInfo->getVarArgsFrameIndex(); + Register LeaReg = MRI.createVirtualRegister(&Mips::GPR32RegClass); + MachineInstr *LEA_ADDiu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LEA_ADDiu)).addDef(LeaReg).addFrameIndex(FI).addImm(0); + if (!constrainSelectedInstRegOperands(*LEA_ADDiu, TII, TRI, RBI)) + return false; + MachineInstr *Store = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::SW)).addUse(LeaReg).addUse(I.getOperand(0).getReg()).addImm(0); + if (!constrainSelectedInstRegOperands(*Store, TII, TRI, RBI)) + return false; + I.eraseFromParent(); + return true; + } + default: + return false; + } + I.eraseFromParent(); + return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/LegalizeInfo/LegalizerInfo.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/LegalizeInfo/LegalizerInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..69fc5775fe04877af2fc98196e855a0a7b386a11 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/LegalizeInfo/LegalizerInfo.cpp @@ -0,0 +1,62 @@ +MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) { + using namespace TargetOpcode; + const LLT s1 = LLT::scalar(1); + const LLT s32 = LLT::scalar(32); + const LLT s64 = LLT::scalar(64); + const LLT v16s8 = LLT::vector(16, 8); + const LLT v8s16 = LLT::vector(8, 16); + const LLT v4s32 = LLT::vector(4, 32); + const LLT v2s64 = LLT::vector(2, 64); + const LLT p0 = LLT::pointer(0, 32); + getActionDefinitionsBuilder({G_ADD, G_SUB, G_MUL}).legalIf([=, &ST](const LegalityQuery &Query) { if (CheckTyN(0, Query, {s32})) return true; if (ST.hasMSA() && CheckTyN(0, Query, {v16s8, v8s16, v4s32, v2s64})) return true; return false;}).clampScalar(0, s32, s32); + getActionDefinitionsBuilder({G_UADDO, G_UADDE, G_USUBO, G_USUBE, G_UMULO}).lowerFor({{s32, s1}}); + getActionDefinitionsBuilder(G_UMULH).legalFor({s32}).maxScalar(0, s32); + bool NoAlignRequirements = true; + unsigned Size = Query.Types[0].getSizeInBits(); unsigned QueryMemSize = Query.MMODescrs[0].SizeInBits; assert(QueryMemSize <= Size && "Scalar can't hold MemSize"); + if (Size > 64 || QueryMemSize > 64) return false; + if (!isPowerOf2_64(Query.MMODescrs[0].SizeInBits)) return true; + if (!ST.systemSupportsUnalignedAccess() && isUnalignedMemmoryAccess(QueryMemSize, Query.MMODescrs[0].AlignInBits)) { assert(QueryMemSize != 32 && "4 byte load and store are legal"); return true; } return false;}).minScalar(0, s32); + getActionDefinitionsBuilder(G_IMPLICIT_DEF).legalFor({s32, s64}); + getActionDefinitionsBuilder(G_UNMERGE_VALUES).legalFor({{s32, s64}}); + getActionDefinitionsBuilder(G_MERGE_VALUES).legalFor({{s64, s32}}); + getActionDefinitionsBuilder({G_ZEXTLOAD, G_SEXTLOAD}).legalForTypesWithMemDesc({{s32, p0, 8, 8}, {s32, p0, 16, 8}}).clampScalar(0, s32, s32); + getActionDefinitionsBuilder({G_ZEXT, G_SEXT, G_ANYEXT}).legalIf([](const LegalityQuery &Query) { return false; }).maxScalar(0, s32); + getActionDefinitionsBuilder(G_TRUNC).legalIf([](const LegalityQuery &Query) { return false; }).maxScalar(1, s32); + getActionDefinitionsBuilder(G_SELECT).legalForCartesianProduct({p0, s32, s64}, {s32}).minScalar(0, s32).minScalar(1, s32); + getActionDefinitionsBuilder(G_BRCOND).legalFor({s32}).minScalar(0, s32); + getActionDefinitionsBuilder(G_BRJT).legalFor({{p0, s32}}); + getActionDefinitionsBuilder(G_BRINDIRECT).legalFor({p0}); + getActionDefinitionsBuilder(G_PHI).legalFor({p0, s32, s64}).minScalar(0, s32); + getActionDefinitionsBuilder({G_AND, G_OR, G_XOR}).legalFor({s32}).clampScalar(0, s32, s32); + getActionDefinitionsBuilder({G_SDIV, G_SREM, G_UDIV, G_UREM}).legalIf([=, &ST](const LegalityQuery &Query) { if (CheckTyN(0, Query, {s32})) return true; if (ST.hasMSA() && CheckTyN(0, Query, {v16s8, v8s16, v4s32, v2s64})) return true; return false;}).minScalar(0, s32).libcallFor({s64}); + getActionDefinitionsBuilder({G_SHL, G_ASHR, G_LSHR}).legalFor({{s32, s32}}).clampScalar(1, s32, s32).clampScalar(0, s32, s32); + getActionDefinitionsBuilder(G_ICMP).legalForCartesianProduct({s32}, {s32, p0}).clampScalar(1, s32, s32).minScalar(0, s32); + getActionDefinitionsBuilder(G_CONSTANT).legalFor({s32}).clampScalar(0, s32, s32); + getActionDefinitionsBuilder({G_PTR_ADD, G_INTTOPTR}).legalFor({{p0, s32}}); + getActionDefinitionsBuilder(G_PTRTOINT).legalFor({{s32, p0}}); + getActionDefinitionsBuilder(G_FRAME_INDEX).legalFor({p0}); + getActionDefinitionsBuilder({G_GLOBAL_VALUE, G_JUMP_TABLE}).legalFor({p0}); + getActionDefinitionsBuilder(G_DYN_STACKALLOC).lowerFor({{p0, s32}}); + getActionDefinitionsBuilder(G_VASTART).legalFor({p0}); + getActionDefinitionsBuilder(G_BSWAP).legalIf([=, &ST](const LegalityQuery &Query) { if (ST.hasMips32r2() && CheckTyN(0, Query, {s32})) return true; return false;}).lowerIf([=, &ST](const LegalityQuery &Query) { if (!ST.hasMips32r2() && CheckTyN(0, Query, {s32})) return true; return false;}).maxScalar(0, s32); + getActionDefinitionsBuilder(G_BITREVERSE).lowerFor({s32}).maxScalar(0, s32); + getActionDefinitionsBuilder(G_CTLZ).legalFor({{s32, s32}}).maxScalar(0, s32).maxScalar(1, s32); + getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF).lowerFor({{s32, s32}}); + getActionDefinitionsBuilder(G_CTTZ).lowerFor({{s32, s32}}).maxScalar(0, s32).maxScalar(1, s32); + getActionDefinitionsBuilder(G_CTTZ_ZERO_UNDEF).lowerFor({{s32, s32}, {s64, s64}}); + getActionDefinitionsBuilder(G_CTPOP).lowerFor({{s32, s32}}).clampScalar(0, s32, s32).clampScalar(1, s32, s32) + getActionDefinitionsBuilder(G_FCONSTANT).legalFor({s32, s64}); + getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FABS, G_FSQRT}).legalIf([=, &ST](const LegalityQuery &Query) { if (CheckTyN(0, Query, {s32, s64})) return true; if (ST.hasMSA() && CheckTyN(0, Query, {v16s8, v8s16, v4s32, v2s64})) return true; return false;}); + getActionDefinitionsBuilder(G_FCMP).legalFor({{s32, s32}, {s32, s64}}).minScalar(0, s32); + getActionDefinitionsBuilder({G_FCEIL, G_FFLOOR}).libcallFor({s32, s64}); + getActionDefinitionsBuilder(G_FPEXT).legalFor({{s64, s32}}); + getActionDefinitionsBuilder(G_FPTRUNC).legalFor({{s32, s64}}); + getActionDefinitionsBuilder(G_FPTOSI).legalForCartesianProduct({s32}, {s64, s32}).libcallForCartesianProduct({s64}, {s64, s32}).minScalar(0, s32); + getActionDefinitionsBuilder(G_FPTOUI).libcallForCartesianProduct({s64}, {s64, s32}).lowerForCartesianProduct({s32}, {s64, s32}).minScalar(0, s32); + getActionDefinitionsBuilder(G_SITOFP).legalForCartesianProduct({s64, s32}, {s32}).libcallForCartesianProduct({s64, s32}, {s64}).minScalar(1, s32); + getActionDefinitionsBuilder(G_UITOFP).libcallForCartesianProduct({s64, s32}, {s64}).customForCartesianProduct({s64, s32}, {s32}).minScalar(1, s32); + getActionDefinitionsBuilder(G_SEXT_INREG).lower(); + getActionDefinitionsBuilder({G_MEMCPY, G_MEMMOVE, G_MEMSET}).libcall(); + computeTables(); + verify(*ST.getInstrInfo()); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/MCInstLower/lowerMachineInstrToMCInst.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/MCInstLower/lowerMachineInstrToMCInst.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/MCInstLower/lowerMachineInstrToMCInst.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/MCInstLower/lowerMachineOperandToMCOperand.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/MCInstLower/lowerMachineOperandToMCOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/MCInstLower/lowerMachineOperandToMCOperand.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/MCInstLower/lowerSymbolOperand.cpp b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/MCInstLower/lowerSymbolOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..815432f210488b2944aa43d51c6807b23840236b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/PULP/Selection/MCInstLower/lowerSymbolOperand.cpp @@ -0,0 +1,124 @@ +MCOperand MipsMCInstLower::LowerSymbolOperand(const MachineOperand &MO, MachineOperandType MOTy, int64_t Offset) const { + MCSymbolRefExpr::VariantKind Kind = MCSymbolRefExpr::VK_None; + MipsMCExpr::MipsExprKind TargetKind = MipsMCExpr::MEK_None; + bool IsGpOff = false; + const MCSymbol *Symbol; + switch(MO.getTargetFlags()) { + default: + llvm_unreachable("Invalid target flag!"); + case MipsII::MO_NO_FLAG: + break; + case MipsII::MO_GPREL: + TargetKind = MipsMCExpr::MEK_GPREL; + break; + case MipsII::MO_GOT_CALL: + TargetKind = MipsMCExpr::MEK_GOT_CALL; + break; + case MipsII::MO_GOT: + TargetKind = MipsMCExpr::MEK_GOT; + break; + case MipsII::MO_ABS_HI: + TargetKind = MipsMCExpr::MEK_HI; + break; + case MipsII::MO_ABS_LO: + TargetKind = MipsMCExpr::MEK_LO; + break; + case MipsII::MO_TLSGD: + TargetKind = MipsMCExpr::MEK_TLSGD; + break; + case MipsII::MO_TLSLDM: + TargetKind = MipsMCExpr::MEK_TLSLDM; + break; + case MipsII::MO_DTPREL_HI: + TargetKind = MipsMCExpr::MEK_DTPREL_HI; + break; + case MipsII::MO_DTPREL_LO: + TargetKind = MipsMCExpr::MEK_DTPREL_LO; + break; + case MipsII::MO_GOTTPREL: + TargetKind = MipsMCExpr::MEK_GOTTPREL; + break; + case MipsII::MO_TPREL_HI: + TargetKind = MipsMCExpr::MEK_TPREL_HI; + break; + case MipsII::MO_TPREL_LO: + TargetKind = MipsMCExpr::MEK_TPREL_LO; + break; + case MipsII::MO_GPOFF_HI: + TargetKind = MipsMCExpr::MEK_HI; + IsGpOff = true; + break; + case MipsII::MO_GPOFF_LO: + TargetKind = MipsMCExpr::MEK_LO; + IsGpOff = true; + break; + case MipsII::MO_GOT_DISP: + TargetKind = MipsMCExpr::MEK_GOT_DISP; + break; + case MipsII::MO_GOT_HI16: + TargetKind = MipsMCExpr::MEK_GOT_HI16; + break; + case MipsII::MO_GOT_LO16: + TargetKind = MipsMCExpr::MEK_GOT_LO16; + break; + case MipsII::MO_GOT_PAGE: + TargetKind = MipsMCExpr::MEK_GOT_PAGE; + break; + case MipsII::MO_GOT_OFST: + TargetKind = MipsMCExpr::MEK_GOT_OFST; + break; + case MipsII::MO_HIGHER: + TargetKind = MipsMCExpr::MEK_HIGHER; + break; + case MipsII::MO_HIGHEST: + TargetKind = MipsMCExpr::MEK_HIGHEST; + break; + case MipsII::MO_CALL_HI16: + TargetKind = MipsMCExpr::MEK_CALL_HI16; + break; + case MipsII::MO_CALL_LO16: + TargetKind = MipsMCExpr::MEK_CALL_LO16; + break; + case MipsII::MO_JALR: + return MCOperand(); + } + switch (MOTy) { + case MachineOperand::MO_MachineBasicBlock: + Symbol = MO.getMBB()->getSymbol(); + break; + case MachineOperand::MO_GlobalAddress: + Symbol = AsmPrinter.getSymbol(MO.getGlobal()); + Offset += MO.getOffset(); + break; + case MachineOperand::MO_BlockAddress: + Symbol = AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress()); + Offset += MO.getOffset(); + break; + case MachineOperand::MO_ExternalSymbol: + Symbol = AsmPrinter.GetExternalSymbolSymbol(MO.getSymbolName()); + Offset += MO.getOffset(); + break; + case MachineOperand::MO_MCSymbol: + Symbol = MO.getMCSymbol(); + Offset += MO.getOffset(); + break; + case MachineOperand::MO_JumpTableIndex: + Symbol = AsmPrinter.GetJTISymbol(MO.getIndex()); + break; + case MachineOperand::MO_ConstantPoolIndex: + Symbol = AsmPrinter.GetCPISymbol(MO.getIndex()); + Offset += MO.getOffset(); + break; + default: + llvm_unreachable(""); + } + const MCExpr *Expr = MCSymbolRefExpr::create(Symbol, Kind, *Ctx); + if (Offset) { + Expr = MCBinaryExpr::createAdd(Expr, MCConstantExpr::create(Offset, *Ctx), *Ctx); + } + if (IsGpOff) + Expr = MipsMCExpr::createGpOff(TargetKind, Expr, *Ctx); + else if (TargetKind != MipsMCExpr::MEK_None) + Expr = MipsMCExpr::create(TargetKind, Expr, *Ctx); + return MCOperand::createExpr(Expr); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Allocation/RegisterBankInfo/RegisterBankInfo.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Allocation/RegisterBankInfo/RegisterBankInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..154620e398d7f0953efcca93ed80eb3382eec4d0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Allocation/RegisterBankInfo/RegisterBankInfo.cpp @@ -0,0 +1,2 @@ +MipsRegisterBankInfo::MipsRegisterBankInfo(const TargetRegisterInfo &TRI) : MipsGenRegisterBankInfo() { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Allocation/RegisterInfo/RegisterInfo.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Allocation/RegisterInfo/RegisterInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9e6f816b7f0ea865a533d9408fcc407f4cc146f4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Allocation/RegisterInfo/RegisterInfo.cpp @@ -0,0 +1,2 @@ +MipsRegisterInfo::MipsRegisterInfo() : MipsGenRegisterInfo(Mips::RA) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Allocation/RegisterInfo/eliminateFrameIndex.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Allocation/RegisterInfo/eliminateFrameIndex.cpp new file mode 100644 index 0000000000000000000000000000000000000000..80dcd82832876ef68c5dac162843caf8d669a919 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Allocation/RegisterInfo/eliminateFrameIndex.cpp @@ -0,0 +1,10 @@ +void MipsRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const { + MachineInstr &MI = *II; + MachineFunction &MF = *MI.getParent()->getParent(); + LLVM_DEBUG(errs() << "\nFunction : " << MF.getName() << "\n"; errs() << "<--------->\n" << MI); + int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); + uint64_t stackSize = MF.getFrameInfo().getStackSize(); + int64_t spOffset = MF.getFrameInfo().getObjectOffset(FrameIndex); + LLVM_DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n" << "spOffset : " << spOffset << "\n" << "stackSize : " << stackSize << "\n" << "alignment : " << DebugStr(MF.getFrameInfo().getObjectAlign(FrameIndex)) << "\n"); + eliminateFI(MI, FIOperandNum, FrameIndex, stackSize, spOffset); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Allocation/RegisterInfo/getCallPreservedMask.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Allocation/RegisterInfo/getCallPreservedMask.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c237e572ddf1fb74501680c681b1277c0f939faa --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Allocation/RegisterInfo/getCallPreservedMask.cpp @@ -0,0 +1,14 @@ +const uint32_t *MipsRegisterInfo::getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const { + const MipsSubtarget &Subtarget = MF.getSubtarget(); + if (Subtarget.isSingleFloat()) + return CSR_SingleFloatOnly_RegMask; + if (Subtarget.isABI_N64()) + return CSR_N64_RegMask; + if (Subtarget.isABI_N32()) + return CSR_N32_RegMask; + if (Subtarget.isFP64bit()) + return CSR_O32_FP64_RegMask; + if (Subtarget.isFPXX()) + return CSR_O32_FPXX_RegMask; + return CSR_O32_RegMask; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Allocation/RegisterInfo/getCalleeSavedRegs.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Allocation/RegisterInfo/getCalleeSavedRegs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ee86b1ec364747b2b7adec2f4c7503435563ae61 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Allocation/RegisterInfo/getCalleeSavedRegs.cpp @@ -0,0 +1,21 @@ +const MCPhysReg *MipsRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { + const MipsSubtarget &Subtarget = MF->getSubtarget(); + const Function &F = MF->getFunction(); + if (F.hasFnAttribute("interrupt")) { + if (Subtarget.hasMips64()) + return Subtarget.hasMips64r6() ? CSR_Interrupt_64R6_SaveList : CSR_Interrupt_64_SaveList; + else + return Subtarget.hasMips32r6() ? CSR_Interrupt_32R6_SaveList : CSR_Interrupt_32_SaveList; + } + if (Subtarget.isSingleFloat()) + return CSR_SingleFloatOnly_SaveList; + if (Subtarget.isABI_N64()) + return CSR_N64_SaveList; + if (Subtarget.isABI_N32()) + return CSR_N32_SaveList; + if (Subtarget.isFP64bit()) + return CSR_O32_FP64_SaveList; + if (Subtarget.isFPXX()) + return CSR_O32_FPXX_SaveList; + return CSR_O32_SaveList; +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Allocation/RegisterInfo/getFrameRegister.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Allocation/RegisterInfo/getFrameRegister.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b5f8f103812c92122b87cb59e13c69048c13c8d7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Allocation/RegisterInfo/getFrameRegister.cpp @@ -0,0 +1,9 @@ +Register MipsRegisterInfo::getFrameRegister(const MachineFunction &MF) const { + const MipsSubtarget &Subtarget = MF.getSubtarget(); + const TargetFrameLowering *TFI = Subtarget.getFrameLowering(); + bool IsN64 = static_cast(MF.getTarget()).getABI().IsN64(); + if (Subtarget.inMips16Mode()) + return TFI->hasFP(MF) ? Mips::S0 : Mips::SP; + else + return TFI->hasFP(MF) ? (IsN64 ? Mips::FP_64 : Mips::FP) : (IsN64 ? Mips::SP_64 : Mips::SP); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Allocation/RegisterInfo/getNoPreservedMask.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Allocation/RegisterInfo/getNoPreservedMask.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Allocation/RegisterInfo/getNoPreservedMask.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Allocation/RegisterInfo/getPointerRegClass.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Allocation/RegisterInfo/getPointerRegClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..768c66e1a51386be2f8f561bf3a64986f6b8ec80 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Allocation/RegisterInfo/getPointerRegClass.cpp @@ -0,0 +1,15 @@ +const TargetRegisterClass *MipsRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind) const { + MipsABIInfo ABI = MF.getSubtarget().getABI(); + MipsPtrClass PtrClassKind = static_cast(Kind); + switch (PtrClassKind) { + case MipsPtrClass::Default: + return ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; + case MipsPtrClass::GPR16MM: + return &Mips::GPRMM16RegClass; + case MipsPtrClass::StackPointer: + return ABI.ArePtrs64bit() ? &Mips::SP64RegClass : &Mips::SP32RegClass; + case MipsPtrClass::GlobalPointer: + return ABI.ArePtrs64bit() ? &Mips::GP64RegClass : &Mips::GP32RegClass; + } + llvm_unreachable("Unknown pointer kind"); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Allocation/RegisterInfo/getReservedRegs.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Allocation/RegisterInfo/getReservedRegs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e54fad41cb6792bb287045716ad70601b8ede981 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Allocation/RegisterInfo/getReservedRegs.cpp @@ -0,0 +1,65 @@ +BitVector MipsRegisterInfo::getReservedRegs(const MachineFunction &MF) const { + static const MCPhysReg ReservedGPR32[] = { + Mips::ZERO, Mips::K0, Mips::K1, Mips::SP + }; + static const MCPhysReg ReservedGPR64[] = { + Mips::ZERO_64, Mips::K0_64, Mips::K1_64, Mips::SP_64 + }; + BitVector Reserved(getNumRegs()); + const MipsSubtarget &Subtarget = MF.getSubtarget(); + for (unsigned I = 0; I < array_lengthof(ReservedGPR32); ++I) + Reserved.set(ReservedGPR32[I]); + if (Subtarget.isTargetNaCl()) { + Reserved.set(Mips::T6); + Reserved.set(Mips::T7); + Reserved.set(Mips::T8); + } + for (unsigned I = 0; I < array_lengthof(ReservedGPR64); ++I) + Reserved.set(ReservedGPR64[I]); + if (!Subtarget.isABICalls()) { + Reserved.set(Mips::GP); + Reserved.set(Mips::GP_64); + } + if (Subtarget.isFP64bit()) { + for (MCPhysReg Reg : Mips::AFGR64RegClass) + Reserved.set(Reg); + } + else { + for (MCPhysReg Reg : Mips::FGR64RegClass) + Reserved.set(Reg); + } + if (Subtarget.getFrameLowering()->hasFP(MF)) { + if (Subtarget.inMips16Mode()) + Reserved.set(Mips::S0); + else { + Reserved.set(Mips::FP); + Reserved.set(Mips::FP_64); + if (needsStackRealignment(MF) && MF.getFrameInfo().hasVarSizedObjects()) { + Reserved.set(Mips::S7); + Reserved.set(Mips::S7_64); + } + } + } + Reserved.set(Mips::HWR29); + Reserved.set(Mips::DSPPos); + Reserved.set(Mips::DSPSCount); + Reserved.set(Mips::DSPCarry); + Reserved.set(Mips::DSPEFI); + Reserved.set(Mips::DSPOutFlag); + for (MCPhysReg Reg : Mips::MSACtrlRegClass) + Reserved.set(Reg); + if (Subtarget.inMips16Mode()) { + const MipsFunctionInfo *MipsFI = MF.getInfo(); + Reserved.set(Mips::RA); + Reserved.set(Mips::RA_64); + Reserved.set(Mips::T0); + Reserved.set(Mips::T1); + if (MF.getFunction().hasFnAttribute("saveS2") || MipsFI->hasSaveS2()) + Reserved.set(Mips::S2); + } + if (Subtarget.useSmallSection()) { + Reserved.set(Mips::GP); + Reserved.set(Mips::GP_64); + } + return Reserved; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Allocation/RegisterInfo/hasReservedSpillSlot.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Allocation/RegisterInfo/hasReservedSpillSlot.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Allocation/RegisterInfo/hasReservedSpillSlot.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Allocation/RegisterInfo/isAsmClobberable.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Allocation/RegisterInfo/isAsmClobberable.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Allocation/RegisterInfo/isAsmClobberable.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Allocation/RegisterInfo/isConstantPhysReg.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Allocation/RegisterInfo/isConstantPhysReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Allocation/RegisterInfo/isConstantPhysReg.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Allocation/RegisterInfo/requiresFrameIndexScavenging.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Allocation/RegisterInfo/requiresFrameIndexScavenging.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e1497c8af968f9fb8df0d24aa0ec03d295b89d0b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Allocation/RegisterInfo/requiresFrameIndexScavenging.cpp @@ -0,0 +1,3 @@ +bool Mips16RegisterInfo::requiresFrameIndexScavenging(const MachineFunction &MF) const { + return false; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Allocation/RegisterInfo/requiresRegisterScavenging.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Allocation/RegisterInfo/requiresRegisterScavenging.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2682c40f6351c32f0b694fd849308d114c3a623b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Allocation/RegisterInfo/requiresRegisterScavenging.cpp @@ -0,0 +1,3 @@ +bool MipsRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const { + return true; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/AsmParser.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/AsmParser.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0024f46337cf0a1788c8f6d813e7962cf06aec64 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/AsmParser.cpp @@ -0,0 +1,24 @@ +MipsAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser, const MCInstrInfo &MII, const MCTargetOptions &Options) : MCTargetAsmParser(Options, sti, MII), ABI(MipsABIInfo::computeTargetABI(Triple(sti.getTargetTriple()), sti.getCPU(), Options)) { + MCAsmParserExtension::Initialize(parser); + parser.addAliasForDirective(".asciiz", ".asciz"); + parser.addAliasForDirective(".hword", ".2byte"); + parser.addAliasForDirective(".word", ".4byte"); + parser.addAliasForDirective(".dword", ".8byte"); + setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits())); + AssemblerOptions.push_back(std::make_unique(getSTI().getFeatureBits())); + AssemblerOptions.push_back(std::make_unique(getSTI().getFeatureBits())); + getTargetStreamer().updateABIInfo(*this); + if (!isABI_O32() && !useOddSPReg() != 0) + report_fatal_error("-mno-odd-spreg requires the O32 ABI"); + CurrentFn = nullptr; + IsPicEnabled = getContext().getObjectFileInfo()->isPositionIndependent(); + IsCpRestoreSet = false; + CpRestoreOffset = -1; + GPReg = ABI.GetGlobalPtr(); + const Triple &TheTriple = sti.getTargetTriple(); + IsLittleEndian = TheTriple.isLittleEndian(); + if (getSTI().getCPU() == "mips64r6" && inMicroMipsMode()) + report_fatal_error("microMIPS64R6 is not supported", false); + if (!isABI_O32() && inMicroMipsMode()) + report_fatal_error("microMIPS64 is not supported", false); + } \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/KindTy.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/KindTy.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9f4c302b6b8fa3a780b93821daa1a44f0536c32c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/KindTy.cpp @@ -0,0 +1,7 @@ +enum KindTy { + k_Immediate, + k_Memory, + k_RegisterIndex, + k_Token, + k_RegList, +} Kind; \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/LLVMInitializeAsmParser.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/LLVMInitializeAsmParser.cpp new file mode 100644 index 0000000000000000000000000000000000000000..03817d477c15f4208d1f063c8f12a417d900e788 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/LLVMInitializeAsmParser.cpp @@ -0,0 +1,6 @@ +extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMipsAsmParser() { + RegisterMCAsmParser X(getTheMipsTarget()); + RegisterMCAsmParser Y(getTheMipselTarget()); + RegisterMCAsmParser A(getTheMips64Target()); + RegisterMCAsmParser B(getTheMips64elTarget()); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/MatchAndEmitInstruction.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/MatchAndEmitInstruction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d5d91e4524a97a5a07f08a46e5da9ac9048942a4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/MatchAndEmitInstruction.cpp @@ -0,0 +1,142 @@ +bool MipsAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, OperandVector &Operands, MCStreamer &Out, uint64_t &ErrorInfo, bool MatchingInlineAsm) { + MCInst Inst; + unsigned MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm); + switch (MatchResult) { + case Match_Success: + if (processInstruction(Inst, IDLoc, Out, STI)) + return true; + return false; + case Match_MissingFeature: + Error(IDLoc, "instruction requires a CPU feature not currently enabled"); + return true; + case Match_InvalidOperand: { + SMLoc ErrorLoc = IDLoc; + if (ErrorInfo != ~0ULL) { + if (ErrorInfo >= Operands.size()) + return Error(IDLoc, "too few operands for instruction"); + ErrorLoc = Operands[ErrorInfo]->getStartLoc(); + if (ErrorLoc == SMLoc()) + ErrorLoc = IDLoc; + } + return Error(ErrorLoc, "invalid operand for instruction"); + } + case Match_NonZeroOperandForSync: + return Error(IDLoc, "s-type must be zero or unspecified for pre-MIPS32 ISAs"); + case Match_NonZeroOperandForMTCX: + return Error(IDLoc, "selector must be zero for pre-MIPS32 ISAs"); + case Match_MnemonicFail: + return Error(IDLoc, "invalid instruction"); + case Match_RequiresDifferentSrcAndDst: + return Error(IDLoc, "source and destination must be different"); + case Match_RequiresDifferentOperands: + return Error(IDLoc, "registers must be different"); + case Match_RequiresNoZeroRegister: + return Error(IDLoc, "invalid operand ($zero) for instruction"); + case Match_RequiresSameSrcAndDst: + return Error(IDLoc, "source and destination must match"); + case Match_NoFCCRegisterForCurrentISA: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "non-zero fcc register doesn't exist in current ISA level"); + case Match_Immz: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected '0'"); + case Match_UImm1_0: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 1-bit unsigned immediate"); + case Match_UImm2_0: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 2-bit unsigned immediate"); + case Match_UImm2_1: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected immediate in range 1 .. 4"); + case Match_UImm3_0: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 3-bit unsigned immediate"); + case Match_UImm4_0: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 4-bit unsigned immediate"); + case Match_SImm4_0: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 4-bit signed immediate"); + case Match_UImm5_0: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 5-bit unsigned immediate"); + case Match_SImm5_0: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 5-bit signed immediate"); + case Match_UImm5_1: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected immediate in range 1 .. 32"); + case Match_UImm5_32: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected immediate in range 32 .. 63"); + case Match_UImm5_33: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected immediate in range 33 .. 64"); + case Match_UImm5_0_Report_UImm6: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 6-bit unsigned immediate"); + case Match_UImm5_Lsl2: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected both 7-bit unsigned immediate and multiple of 4"); + case Match_UImmRange2_64: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected immediate in range 2 .. 64"); + case Match_UImm6_0: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 6-bit unsigned immediate"); + case Match_UImm6_Lsl2: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected both 8-bit unsigned immediate and multiple of 4"); + case Match_SImm6_0: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 6-bit signed immediate"); + case Match_UImm7_0: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 7-bit unsigned immediate"); + case Match_UImm7_N1: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected immediate in range -1 .. 126"); + case Match_SImm7_Lsl2: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected both 9-bit signed immediate and multiple of 4"); + case Match_UImm8_0: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 8-bit unsigned immediate"); + case Match_UImm10_0: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 10-bit unsigned immediate"); + case Match_SImm10_0: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 10-bit signed immediate"); + case Match_SImm11_0: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 11-bit signed immediate"); + case Match_UImm16: + case Match_UImm16_Relaxed: + case Match_UImm16_AltRelaxed: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 16-bit unsigned immediate"); + case Match_SImm16: + case Match_SImm16_Relaxed: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 16-bit signed immediate"); + case Match_SImm19_Lsl2: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected both 19-bit signed immediate and multiple of 4"); + case Match_UImm20_0: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 20-bit unsigned immediate"); + case Match_UImm26_0: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 26-bit unsigned immediate"); + case Match_SImm32: + case Match_SImm32_Relaxed: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 32-bit signed immediate"); + case Match_UImm32_Coerced: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 32-bit immediate"); + case Match_MemSImm9: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected memory with 9-bit signed offset"); + case Match_MemSImm10: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected memory with 10-bit signed offset"); + case Match_MemSImm10Lsl1: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected memory with 11-bit signed offset and multiple of 2"); + case Match_MemSImm10Lsl2: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected memory with 12-bit signed offset and multiple of 4"); + case Match_MemSImm10Lsl3: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected memory with 13-bit signed offset and multiple of 8"); + case Match_MemSImm11: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected memory with 11-bit signed offset"); + case Match_MemSImm12: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected memory with 12-bit signed offset"); + case Match_MemSImm16: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected memory with 16-bit signed offset"); + case Match_MemSImmPtr: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected memory with 32-bit signed offset"); + case Match_RequiresPosSizeRange0_32: { + SMLoc ErrorStart = Operands[3]->getStartLoc(); + SMLoc ErrorEnd = Operands[4]->getEndLoc(); + return Error(ErrorStart, "size plus position are not in the range 0 .. 32", SMRange(ErrorStart, ErrorEnd)); + } + case Match_RequiresPosSizeUImm6: { + SMLoc ErrorStart = Operands[3]->getStartLoc(); + SMLoc ErrorEnd = Operands[4]->getEndLoc(); + return Error(ErrorStart, "size plus position are not in the range 1 .. 63", SMRange(ErrorStart, ErrorEnd)); + } + case Match_RequiresPosSizeRange33_64: { + SMLoc ErrorStart = Operands[3]->getStartLoc(); + SMLoc ErrorEnd = Operands[4]->getEndLoc(); + return Error(ErrorStart, "size plus position are not in the range 33 .. 64", SMRange(ErrorStart, ErrorEnd)); + } +} + llvm_unreachable("Implement any new match types added!"); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/Operand.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/Operand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3ea6992dcf8df85c16752926355da897ce7de63a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/Operand.cpp @@ -0,0 +1,2 @@ +MipsOperand(KindTy K, MipsAsmParser &Parser) : MCParsedAsmOperand(), Kind(K), AsmParser(Parser) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/Operand2.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/Operand2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3ea6992dcf8df85c16752926355da897ce7de63a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/Operand2.cpp @@ -0,0 +1,2 @@ +MipsOperand(KindTy K, MipsAsmParser &Parser) : MCParsedAsmOperand(), Kind(K), AsmParser(Parser) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/ParseDirective.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/ParseDirective.cpp new file mode 100644 index 0000000000000000000000000000000000000000..759b5538a90a0648a7e34b1e218abc61944b5841 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/ParseDirective.cpp @@ -0,0 +1,243 @@ +bool MipsAsmParser::ParseDirective(AsmToken DirectiveID) { + MCAsmParser &Parser = getParser(); + StringRef IDVal = DirectiveID.getString(); + if (IDVal == ".cpadd") { + parseDirectiveCpAdd(DirectiveID.getLoc()); + return false; + } + if (IDVal == ".cpload") { + parseDirectiveCpLoad(DirectiveID.getLoc()); + return false; + } + if (IDVal == ".cprestore") { + parseDirectiveCpRestore(DirectiveID.getLoc()); + return false; + } + if (IDVal == ".cplocal") { + parseDirectiveCpLocal(DirectiveID.getLoc()); + return false; + } + if (IDVal == ".ent") { + StringRef SymbolName; + if (Parser.parseIdentifier(SymbolName)) { + reportParseError("expected identifier after .ent"); + return false; + } + if (getLexer().isNot(AsmToken::EndOfStatement)) { + if (getLexer().isNot(AsmToken::Comma)) { + reportParseError("unexpected token, expected end of statement"); + return false; + } + Parser.Lex(); + const MCExpr *DummyNumber; + int64_t DummyNumberVal; + if (Parser.parseExpression(DummyNumber)) { + reportParseError("expected number after comma"); + return false; + } + if (!DummyNumber->evaluateAsAbsolute(DummyNumberVal)) { + reportParseError("expected an absolute expression after comma"); + return false; + } + } + if (getLexer().isNot(AsmToken::EndOfStatement)) { + reportParseError("unexpected token, expected end of statement"); + return false; + } + MCSymbol *Sym = getContext().getOrCreateSymbol(SymbolName); + getTargetStreamer().emitDirectiveEnt(*Sym); + CurrentFn = Sym; + IsCpRestoreSet = false; + return false; + } + if (IDVal == ".end") { + StringRef SymbolName; + if (Parser.parseIdentifier(SymbolName)) { + reportParseError("expected identifier after .end"); + return false; + } + if (getLexer().isNot(AsmToken::EndOfStatement)) { + reportParseError("unexpected token, expected end of statement"); + return false; + } + if (CurrentFn == nullptr) { + reportParseError(".end used without .ent"); + return false; + } + if ((SymbolName != CurrentFn->getName())) { + reportParseError(".end symbol does not match .ent symbol"); + return false; + } + getTargetStreamer().emitDirectiveEnd(SymbolName); + CurrentFn = nullptr; + IsCpRestoreSet = false; + return false; + } + if (IDVal == ".frame") { + SmallVector, 1> TmpReg; + OperandMatchResultTy ResTy = parseAnyRegister(TmpReg); + if (ResTy == MatchOperand_NoMatch || ResTy == MatchOperand_ParseFail) { + reportParseError("expected stack register"); + return false; + } + MipsOperand &StackRegOpnd = static_cast(*TmpReg[0]); + if (!StackRegOpnd.isGPRAsmReg()) { + reportParseError(StackRegOpnd.getStartLoc(), "expected general purpose register"); + return false; + } + unsigned StackReg = StackRegOpnd.getGPR32Reg(); + if (Parser.getTok().is(AsmToken::Comma)) + Parser.Lex(); + else { + reportParseError("unexpected token, expected comma"); + return false; + } + const MCExpr *FrameSize; + int64_t FrameSizeVal; + if (Parser.parseExpression(FrameSize)) { + reportParseError("expected frame size value"); + return false; + } + if (!FrameSize->evaluateAsAbsolute(FrameSizeVal)) { + reportParseError("frame size not an absolute expression"); + return false; + } + if (Parser.getTok().is(AsmToken::Comma)) + Parser.Lex(); + else { + reportParseError("unexpected token, expected comma"); + return false; + } + TmpReg.clear(); + ResTy = parseAnyRegister(TmpReg); + if (ResTy == MatchOperand_NoMatch || ResTy == MatchOperand_ParseFail) { + reportParseError("expected return register"); + return false; + } + MipsOperand &ReturnRegOpnd = static_cast(*TmpReg[0]); + if (!ReturnRegOpnd.isGPRAsmReg()) { + reportParseError(ReturnRegOpnd.getStartLoc(), "expected general purpose register"); + return false; + } + if (getLexer().isNot(AsmToken::EndOfStatement)) { + reportParseError("unexpected token, expected end of statement"); + return false; + } + getTargetStreamer().emitFrame(StackReg, FrameSizeVal, ReturnRegOpnd.getGPR32Reg()); + IsCpRestoreSet = false; + return false; + } + if (IDVal == ".set") { + parseDirectiveSet(); + return false; + } + if (IDVal == ".mask" || IDVal == ".fmask") { + const MCExpr *BitMask; + int64_t BitMaskVal; + if (Parser.parseExpression(BitMask)) { + reportParseError("expected bitmask value"); + return false; + } + if (!BitMask->evaluateAsAbsolute(BitMaskVal)) { + reportParseError("bitmask not an absolute expression"); + return false; + } + if (Parser.getTok().is(AsmToken::Comma)) + Parser.Lex(); + else { + reportParseError("unexpected token, expected comma"); + return false; + } + const MCExpr *FrameOffset; + int64_t FrameOffsetVal; + if (Parser.parseExpression(FrameOffset)) { + reportParseError("expected frame offset value"); + return false; + } + if (!FrameOffset->evaluateAsAbsolute(FrameOffsetVal)) { + reportParseError("frame offset not an absolute expression"); + return false; + } + if (getLexer().isNot(AsmToken::EndOfStatement)) { + reportParseError("unexpected token, expected end of statement"); + return false; + } + if (IDVal == ".mask") + getTargetStreamer().emitMask(BitMaskVal, FrameOffsetVal); + else + getTargetStreamer().emitFMask(BitMaskVal, FrameOffsetVal); + return false; + } + if (IDVal == ".nan") + return parseDirectiveNaN(); + + if (IDVal == ".gpword") { + parseDirectiveGpWord(); + return false; + } + if (IDVal == ".gpdword") { + parseDirectiveGpDWord(); + return false; + } + + if (IDVal == ".dtprelword") { + parseDirectiveDtpRelWord(); + return false; + } + if (IDVal == ".dtpreldword") { + parseDirectiveDtpRelDWord(); + return false; + } + if (IDVal == ".tprelword") { + parseDirectiveTpRelWord(); + return false; + } + if (IDVal == ".tpreldword") { + parseDirectiveTpRelDWord(); + return false; + } + if (IDVal == ".option") { + parseDirectiveOption(); + return false; + } + if (IDVal == ".abicalls") { + getTargetStreamer().emitDirectiveAbiCalls(); + if (Parser.getTok().isNot(AsmToken::EndOfStatement)) { + Error(Parser.getTok().getLoc(), "unexpected token, expected end of statement"); + } + return false; + } + if (IDVal == ".cpsetup") { + parseDirectiveCPSetup(); + return false; + } + if (IDVal == ".cpreturn") { + parseDirectiveCPReturn(); + return false; + } + if (IDVal == ".module") { + parseDirectiveModule(); + return false; + } + if (IDVal == ".llvm_internal_mips_reallow_module_directive") { + parseInternalDirectiveReallowModule(); + return false; + } + if (IDVal == ".insn") { + parseInsnDirective(); + return false; + } + if (IDVal == ".rdata") { + parseRSectionDirective(".rodata"); + return false; + } + if (IDVal == ".sbss") { + parseSSectionDirective(IDVal, ELF::SHT_NOBITS); + return false; + } + if (IDVal == ".sdata") { + parseSSectionDirective(IDVal, ELF::SHT_PROGBITS); + return false; + } + return true; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/ParseInstruction.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/ParseInstruction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2a508ccdd7784c61a69914df68dd816e913dd917 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/ParseInstruction.cpp @@ -0,0 +1,38 @@ +bool MipsAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, OperandVector &Operands) { + MCAsmParser &Parser = getParser(); + LLVM_DEBUG(dbgs() << "ParseInstruction\n"); + getTargetStreamer().forbidModuleDirective(); + if (!mnemonicIsValid(Name, 0)) { + FeatureBitset FBS = ComputeAvailableFeatures(getSTI().getFeatureBits()); + std::string Suggestion = MipsMnemonicSpellCheck(Name, FBS); + return Error(NameLoc, "unknown instruction" + Suggestion); + } + Operands.push_back(MipsOperand::CreateToken(Name, NameLoc, *this)); + if (getLexer().isNot(AsmToken::EndOfStatement)) { + if (parseOperand(Operands, Name)) { + SMLoc Loc = getLexer().getLoc(); + return Error(Loc, "unexpected token in argument list"); + } + if (getLexer().is(AsmToken::LBrac) && parseBracketSuffix(Name, Operands)) + return true; + while (getLexer().is(AsmToken::Comma)) { + Parser.Lex(); + if (parseOperand(Operands, Name)) { + SMLoc Loc = getLexer().getLoc(); + return Error(Loc, "unexpected token in argument list"); + } + if (getLexer().is(AsmToken::LBrac)) { + if (parseBracketSuffix(Name, Operands)) + return true; + } + else if (getLexer().is(AsmToken::LParen) && parseParenSuffix(Name, Operands)) + return true; + } + } + if (getLexer().isNot(AsmToken::EndOfStatement)) { + SMLoc Loc = getLexer().getLoc(); + return Error(Loc, "unexpected token in argument list"); + } + Parser.Lex(); + return false; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/ParseRegister.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/ParseRegister.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c1c007833f59929cb9d0324e00d3040998464996 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/ParseRegister.cpp @@ -0,0 +1,3 @@ +bool MipsAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) { + return tryParseRegister(RegNo, StartLoc, EndLoc) != MatchOperand_Success; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/addCSRSystemRegisterOperands.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/addCSRSystemRegisterOperands.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/addCSRSystemRegisterOperands.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/addExpr.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/addExpr.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1d2a064b7a9d4fb757645ce723c9d45a4e21f59f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/addExpr.cpp @@ -0,0 +1,8 @@ +void addExpr(MCInst &Inst, const MCExpr *Expr) const { + if (!Expr) + Inst.addOperand(MCOperand::createImm(0)); + else if (const MCConstantExpr *CE = dyn_cast(Expr)) + Inst.addOperand(MCOperand::createImm(CE->getValue())); + else + Inst.addOperand(MCOperand::createExpr(Expr)); + } \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/addFRMArgOperands.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/addFRMArgOperands.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/addFRMArgOperands.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/addFenceArgOperands.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/addFenceArgOperands.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/addFenceArgOperands.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/addImmOperands.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/addImmOperands.cpp new file mode 100644 index 0000000000000000000000000000000000000000..99f9c831995140cddadc166fd097ee368b5c5f2d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/addImmOperands.cpp @@ -0,0 +1,4 @@ +void addImmOperands(MCInst &Inst, unsigned N) const { + assert(N == 1 && "Invalid number of operands!"); + addExpr(Inst, getImm()); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/addRegOperands.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/addRegOperands.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5b5826e8ee5f4576985c9fdb509c547c63f4ec8b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/addRegOperands.cpp @@ -0,0 +1,3 @@ +void addRegOperands(MCInst &Inst, unsigned N) const { + llvm_unreachable("Use a custom parser instead"); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/addVTypeIOperands.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/addVTypeIOperands.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/addVTypeIOperands.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/classifySymbolRef.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/classifySymbolRef.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/classifySymbolRef.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/convertFPR64ToFPR16.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/convertFPR64ToFPR16.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/convertFPR64ToFPR16.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/convertFPR64ToFPR32.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/convertFPR64ToFPR32.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/convertFPR64ToFPR32.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/createImm.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/createImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3da1052dc575118e5bbe16ca357f8c8a15196bdf --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/createImm.cpp @@ -0,0 +1,7 @@ +static std::unique_ptr createImm(const MCExpr *Val, SMLoc S, SMLoc E, MipsAsmParser &Parser) { + auto Op = std::make_unique(k_Immediate, Parser); + Op->Imm.Val = Val; + Op->StartLoc = S; + Op->EndLoc = E; + return Op; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/createReg.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/createReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e3abcdf12ae77e0a78c900564055206a22187242 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/createReg.cpp @@ -0,0 +1,11 @@ +static std::unique_ptr CreateReg(unsigned Index, StringRef Str, RegKind RegKind, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E, MipsAsmParser &Parser) { + auto Op = std::make_unique(k_RegisterIndex, Parser); + Op->RegIdx.Index = Index; + Op->RegIdx.RegInfo = RegInfo; + Op->RegIdx.Kind = RegKind; + Op->RegIdx.Tok.Data = Str.data(); + Op->RegIdx.Tok.Length = Str.size(); + Op->StartLoc = S; + Op->EndLoc = E; + return Op; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/createSysReg.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/createSysReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/createSysReg.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/createToken.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/createToken.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b32d17dd87c68e6be83414d2394197c68d1245e5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/createToken.cpp @@ -0,0 +1,8 @@ +static std::unique_ptr CreateToken(StringRef Str, SMLoc S, MipsAsmParser &Parser) { + auto Op = std::make_unique(k_Token, Parser); + Op->Tok.Data = Str.data(); + Op->Tok.Length = Str.size(); + Op->StartLoc = S; + Op->EndLoc = S; + return Op; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/createVType.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/createVType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/createVType.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/defaultMaskRegOp.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/defaultMaskRegOp.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/defaultMaskRegOp.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/emitToStreamer.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/emitToStreamer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/emitToStreamer.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/evaluateConstantImm.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/evaluateConstantImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/evaluateConstantImm.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/generateImmOutOfRangeError.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/generateImmOutOfRangeError.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/generateImmOutOfRangeError.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/getEndLoc.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/getEndLoc.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e9075c3fe891637688ed0ec5409f13457d6bbdd7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/getEndLoc.cpp @@ -0,0 +1,3 @@ +SMLoc getEndLoc() const override { + return EndLoc; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/getFeatureBits.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/getFeatureBits.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/getFeatureBits.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/getImm.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/getImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..92325c487a33c523dd5549a7a6d810023646c31d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/getImm.cpp @@ -0,0 +1,4 @@ +const MCExpr *getImm() const { + assert((Kind == k_Immediate) && "Invalid access!"); + return Imm.Val; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/getLoc.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/getLoc.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/getLoc.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/getReg.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/getReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..561fb299f3424c0fccbf96c162cdbc182753d4d9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/getReg.cpp @@ -0,0 +1,6 @@ +unsigned getReg() const override { + if (Kind == k_RegisterIndex && RegIdx.Index == 0 && RegIdx.Kind & RegKind_GPR) + return getGPR32Reg(); + llvm_unreachable("Invalid access!"); + return 0; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/getRoundingMode.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/getRoundingMode.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/getRoundingMode.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/getStartLoc.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/getStartLoc.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e36379a2af7e3a50c3295ec879be99ded34a75f7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/getStartLoc.cpp @@ -0,0 +1,3 @@ +SMLoc getStartLoc() const override { + return StartLoc; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/getSysReg.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/getSysReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/getSysReg.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/getTargetStreamer.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/getTargetStreamer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f0702cf4d0fc4fe32fcfe3d6382149cf4456f1ef --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/getTargetStreamer.cpp @@ -0,0 +1,5 @@ +MipsTargetStreamer &getTargetStreamer() { + assert(getParser().getStreamer().getTargetStreamer() && "do not have a target streamer"); + MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer(); + return static_cast(TS); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/getToken.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/getToken.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e40c78da1e88d4186d87ae697481e4458dc6d09f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/getToken.cpp @@ -0,0 +1,4 @@ +StringRef getToken() const { + assert(Kind == k_Token && "Invalid access!"); + return StringRef(Tok.Data, Tok.Length); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/getVType.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/getVType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/getVType.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isBareSimmNLsb0.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isBareSimmNLsb0.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e4f3881c631162a15ddab6b7d7c34cc1d2b97656 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isBareSimmNLsb0.cpp @@ -0,0 +1,3 @@ +template bool isSImm() const { + return isConstantImm() ? isInt(getConstantImm()) : isImm(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isBareSymbol.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isBareSymbol.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e4f3881c631162a15ddab6b7d7c34cc1d2b97656 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isBareSymbol.cpp @@ -0,0 +1,3 @@ +template bool isSImm() const { + return isConstantImm() ? isInt(getConstantImm()) : isImm(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isCLUIImm.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isCLUIImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e4f3881c631162a15ddab6b7d7c34cc1d2b97656 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isCLUIImm.cpp @@ -0,0 +1,3 @@ +template bool isSImm() const { + return isConstantImm() ? isInt(getConstantImm()) : isImm(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isCSRSystemRegister.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isCSRSystemRegister.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isCSRSystemRegister.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isCallSymbol.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isCallSymbol.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e4f3881c631162a15ddab6b7d7c34cc1d2b97656 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isCallSymbol.cpp @@ -0,0 +1,3 @@ +template bool isSImm() const { + return isConstantImm() ? isInt(getConstantImm()) : isImm(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isFRMArg.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isFRMArg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e4f3881c631162a15ddab6b7d7c34cc1d2b97656 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isFRMArg.cpp @@ -0,0 +1,3 @@ +template bool isSImm() const { + return isConstantImm() ? isInt(getConstantImm()) : isImm(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isFenceArg.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isFenceArg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e4f3881c631162a15ddab6b7d7c34cc1d2b97656 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isFenceArg.cpp @@ -0,0 +1,3 @@ +template bool isSImm() const { + return isConstantImm() ? isInt(getConstantImm()) : isImm(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isGPR.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isGPR.cpp new file mode 100644 index 0000000000000000000000000000000000000000..97325e19a5f38a3dc2992126c618d96f7d7813b7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isGPR.cpp @@ -0,0 +1,3 @@ +bool isGPRAsmReg() const { + return isRegIdx() && RegIdx.Kind & RegKind_GPR && RegIdx.Index <= 31; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isImm.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e028f1acc0adc990eaaa7cd33412bb583aa50693 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isImm.cpp @@ -0,0 +1,3 @@ +bool isImm() const override { + return Kind == k_Immediate; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isImmXLenLI.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isImmXLenLI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isImmXLenLI.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isMem.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isMem.cpp new file mode 100644 index 0000000000000000000000000000000000000000..433c1871fb3ee7ace6d97413913de43c8c9fba2a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isMem.cpp @@ -0,0 +1,3 @@ +bool isMem() const override { + return Kind == k_Memory; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isPseudoJumpSymbol.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isPseudoJumpSymbol.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isPseudoJumpSymbol.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isRV32E.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isRV32E.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isRV32E.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isRV64-2.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isRV64-2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isRV64-2.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isRV64.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isRV64.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isRV64.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isReg.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d367df6e72a1916e56ea13412e32c693d1dd119b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isReg.cpp @@ -0,0 +1,3 @@ +bool isReg() const override { + return isGPRAsmReg() && RegIdx.Index == 0; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isSImm10Lsb0000NonZero.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isSImm10Lsb0000NonZero.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e4f3881c631162a15ddab6b7d7c34cc1d2b97656 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isSImm10Lsb0000NonZero.cpp @@ -0,0 +1,3 @@ +template bool isSImm() const { + return isConstantImm() ? isInt(getConstantImm()) : isImm(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isSImm12.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isSImm12.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e4f3881c631162a15ddab6b7d7c34cc1d2b97656 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isSImm12.cpp @@ -0,0 +1,3 @@ +template bool isSImm() const { + return isConstantImm() ? isInt(getConstantImm()) : isImm(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isSImm12Lsb0.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isSImm12Lsb0.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e4f3881c631162a15ddab6b7d7c34cc1d2b97656 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isSImm12Lsb0.cpp @@ -0,0 +1,3 @@ +template bool isSImm() const { + return isConstantImm() ? isInt(getConstantImm()) : isImm(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isSImm13Lsb0.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isSImm13Lsb0.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e4f3881c631162a15ddab6b7d7c34cc1d2b97656 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isSImm13Lsb0.cpp @@ -0,0 +1,3 @@ +template bool isSImm() const { + return isConstantImm() ? isInt(getConstantImm()) : isImm(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isSImm21Lsb0JAL.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isSImm21Lsb0JAL.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e4f3881c631162a15ddab6b7d7c34cc1d2b97656 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isSImm21Lsb0JAL.cpp @@ -0,0 +1,3 @@ +template bool isSImm() const { + return isConstantImm() ? isInt(getConstantImm()) : isImm(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isSImm5.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isSImm5.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e4f3881c631162a15ddab6b7d7c34cc1d2b97656 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isSImm5.cpp @@ -0,0 +1,3 @@ +template bool isSImm() const { + return isConstantImm() ? isInt(getConstantImm()) : isImm(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isSImm5Plus1.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isSImm5Plus1.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e4f3881c631162a15ddab6b7d7c34cc1d2b97656 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isSImm5Plus1.cpp @@ -0,0 +1,3 @@ +template bool isSImm() const { + return isConstantImm() ? isInt(getConstantImm()) : isImm(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isSImm6.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isSImm6.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e4f3881c631162a15ddab6b7d7c34cc1d2b97656 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isSImm6.cpp @@ -0,0 +1,3 @@ +template bool isSImm() const { + return isConstantImm() ? isInt(getConstantImm()) : isImm(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isSImm6NonZero.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isSImm6NonZero.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e4f3881c631162a15ddab6b7d7c34cc1d2b97656 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isSImm6NonZero.cpp @@ -0,0 +1,3 @@ +template bool isSImm() const { + return isConstantImm() ? isInt(getConstantImm()) : isImm(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isSImm9Lsb0.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isSImm9Lsb0.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e4f3881c631162a15ddab6b7d7c34cc1d2b97656 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isSImm9Lsb0.cpp @@ -0,0 +1,3 @@ +template bool isSImm() const { + return isConstantImm() ? isInt(getConstantImm()) : isImm(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isSystemRegister.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isSystemRegister.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isSystemRegister.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isTPRelAddSymbol.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isTPRelAddSymbol.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isTPRelAddSymbol.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isToken.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isToken.cpp new file mode 100644 index 0000000000000000000000000000000000000000..434a02a9965ade469608f0cf55d543128efbe8ff --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isToken.cpp @@ -0,0 +1,3 @@ +bool isToken() const override { + return Kind == k_Token; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isUImm10Lsb00NonZero.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isUImm10Lsb00NonZero.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f7832961be9a3b8db581ef5ae22be8705c597938 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isUImm10Lsb00NonZero.cpp @@ -0,0 +1,3 @@ +template bool isUImm() const { + return isConstantImm() ? isUInt(getConstantImm()) : isImm(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isUImm20AUIPC.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isUImm20AUIPC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f7832961be9a3b8db581ef5ae22be8705c597938 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isUImm20AUIPC.cpp @@ -0,0 +1,3 @@ +template bool isUImm() const { + return isConstantImm() ? isUInt(getConstantImm()) : isImm(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isUImm20LUI.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isUImm20LUI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f7832961be9a3b8db581ef5ae22be8705c597938 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isUImm20LUI.cpp @@ -0,0 +1,3 @@ +template bool isUImm() const { + return isConstantImm() ? isUInt(getConstantImm()) : isImm(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isUImm5.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isUImm5.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4482a7535ca80791bde428caeead9df38241b40b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isUImm5.cpp @@ -0,0 +1,3 @@ +template bool isUImm() const { + return isConstantImm() ? isUInt(getConstantImm()) : isImm(); +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isUImm7Lsb00.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isUImm7Lsb00.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f7832961be9a3b8db581ef5ae22be8705c597938 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isUImm7Lsb00.cpp @@ -0,0 +1,3 @@ +template bool isUImm() const { + return isConstantImm() ? isUInt(getConstantImm()) : isImm(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isUImm8Lsb00.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isUImm8Lsb00.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f7832961be9a3b8db581ef5ae22be8705c597938 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isUImm8Lsb00.cpp @@ -0,0 +1,3 @@ +template bool isUImm() const { + return isConstantImm() ? isUInt(getConstantImm()) : isImm(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isUImm8Lsb000.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isUImm8Lsb000.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f7832961be9a3b8db581ef5ae22be8705c597938 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isUImm8Lsb000.cpp @@ -0,0 +1,3 @@ +template bool isUImm() const { + return isConstantImm() ? isUInt(getConstantImm()) : isImm(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isUImm9Lsb000.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isUImm9Lsb000.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f7832961be9a3b8db581ef5ae22be8705c597938 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isUImm9Lsb000.cpp @@ -0,0 +1,3 @@ +template bool isUImm() const { + return isConstantImm() ? isUInt(getConstantImm()) : isImm(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isUImmLog2XLen.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isUImmLog2XLen.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f7832961be9a3b8db581ef5ae22be8705c597938 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isUImmLog2XLen.cpp @@ -0,0 +1,3 @@ +template bool isUImm() const { + return isConstantImm() ? isUInt(getConstantImm()) : isImm(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isUImmLog2XLenHalf.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isUImmLog2XLenHalf.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f7832961be9a3b8db581ef5ae22be8705c597938 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isUImmLog2XLenHalf.cpp @@ -0,0 +1,3 @@ +template bool isUImm() const { + return isConstantImm() ? isUInt(getConstantImm()) : isImm(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isUImmLog2XLenNonZero.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isUImmLog2XLenNonZero.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f7832961be9a3b8db581ef5ae22be8705c597938 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isUImmLog2XLenNonZero.cpp @@ -0,0 +1,3 @@ +template bool isUImm() const { + return isConstantImm() ? isUInt(getConstantImm()) : isImm(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isV0Reg.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isV0Reg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isV0Reg.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isVType.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isVType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isVType.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isVTypeI.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isVTypeI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/isVTypeI.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/matchRegisterNameHelper.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/matchRegisterNameHelper.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/matchRegisterNameHelper.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/parseAtomicMemOp.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/parseAtomicMemOp.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/parseAtomicMemOp.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/parseBareSymbol.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/parseBareSymbol.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/parseBareSymbol.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/parseCSRSyestemRegister.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/parseCSRSyestemRegister.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/parseCSRSyestemRegister.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/parseCallSymbol.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/parseCallSymbol.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/parseCallSymbol.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/parseImmediate.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/parseImmediate.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/parseImmediate.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/parseJALOffset.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/parseJALOffset.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/parseJALOffset.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/parseMaskReg.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/parseMaskReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/parseMaskReg.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/parseMemOpBaseReg.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/parseMemOpBaseReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/parseMemOpBaseReg.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/parseOperand.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/parseOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fa71ede088179ac896028ca527da6898ad8c02dd --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/parseOperand.cpp @@ -0,0 +1,36 @@ +bool MipsAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) { + MCAsmParser &Parser = getParser(); + LLVM_DEBUG(dbgs() << "parseOperand\n"); + OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic); + if (ResTy == MatchOperand_Success) + return false; + if (ResTy == MatchOperand_ParseFail) + return true; + LLVM_DEBUG(dbgs() << ".. Generic Parser\n"); + switch (getLexer().getKind()) { + case AsmToken::Dollar: { + SMLoc S = Parser.getTok().getLoc(); + if (parseAnyRegister(Operands) != MatchOperand_NoMatch) + return false; + StringRef Identifier; + if (Parser.parseIdentifier(Identifier)) + return true; + SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); + MCSymbol *Sym = getContext().getOrCreateSymbol("$" + Identifier); + const MCExpr *Res = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext()); + Operands.push_back(MipsOperand::CreateImm(Res, S, E, *this)); + return false; + } + default: { + LLVM_DEBUG(dbgs() << ".. generic integer expression\n"); + const MCExpr *Expr; + SMLoc S = Parser.getTok().getLoc(); + if (getParser().parseExpression(Expr)) + return true; + SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); + Operands.push_back(MipsOperand::CreateImm(Expr, S, E, *this)); + return false; + } + } + return true; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/parseOperandWithModifier.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/parseOperandWithModifier.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/parseOperandWithModifier.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/parsePseudoJumpSymbol.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/parsePseudoJumpSymbol.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/parsePseudoJumpSymbol.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/parseRegister2.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/parseRegister2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/parseRegister2.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/parseVTypeI.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/parseVTypeI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/parseVTypeI.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/print.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/print.cpp new file mode 100644 index 0000000000000000000000000000000000000000..84efdd1c18cb87d13ff89482402cbc6dadca4b57 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/print.cpp @@ -0,0 +1,29 @@ +void print(raw_ostream &OS) const override { + switch (Kind) { + case k_Immediate: + OS << "Imm<"; + OS << *Imm.Val; + OS << ">"; + break; + case k_Memory: + OS << "Mem<"; + Mem.Base->print(OS); + OS << ", "; + OS << *Mem.Off; + OS << ">"; + break; + case k_RegisterIndex: + OS << "RegIdx<" << RegIdx.Index << ":" << RegIdx.Kind << ", " + << StringRef(RegIdx.Tok.Data, RegIdx.Tok.Length) << ">"; + break; + case k_Token: + OS << getToken(); + break; + case k_RegList: + OS << "RegList< "; + for (auto Reg : (*RegList.List)) + OS << Reg << " "; + OS << ">"; + break; + } +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/setFeatureBits.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/setFeatureBits.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bd1a8cbc7b97359b66a58cc455ce07f739cf6627 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/setFeatureBits.cpp @@ -0,0 +1,7 @@ +void setFeatureBits(uint64_t Feature, StringRef FeatureString) { + if (!(getSTI().getFeatureBits()[Feature])) { + MCSubtargetInfo &STI = copySTI(); + setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature(FeatureString))); + AssemblerOptions.back()->setFeatures(STI.getFeatureBits()); + } +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/tryParseRegister.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/tryParseRegister.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0b7da7ddacfdef727bd3c1256963779f4610d80b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/tryParseRegister.cpp @@ -0,0 +1,16 @@ +OperandMatchResultTy MipsAsmParser::tryParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) { + SmallVector, 1> Operands; + OperandMatchResultTy ResTy = parseAnyRegister(Operands); + if (ResTy == MatchOperand_Success) { + assert(Operands.size() == 1); + MipsOperand &Operand = static_cast(*Operands.front()); + StartLoc = Operand.getStartLoc(); + EndLoc = Operand.getEndLoc(); + if (Operand.isGPRAsmReg()) { + RegNo = isGP64bit() ? Operand.getGPR64Reg() : Operand.getGPR32Reg(); + } + return (RegNo == (unsigned)-1) ? MatchOperand_NoMatch : MatchOperand_Success; + } + assert(Operands.size() == 0); + return (RegNo == (unsigned)-1) ? MatchOperand_NoMatch : MatchOperand_Success; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/validateTargetOperandClass.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/validateTargetOperandClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmParser/validateTargetOperandClass.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmPrinter/AsmPrinter.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmPrinter/AsmPrinter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..69363c6c07ac6569bb6adaa08ef2328e96b8a16f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmPrinter/AsmPrinter.cpp @@ -0,0 +1,2 @@ +explicit MipsAsmPrinter(TargetMachine &TM, std::unique_ptr Streamer) : AsmPrinter(TM, std::move(Streamer)), MCInstLowering(*this) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmPrinter/EmitToStreamer.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmPrinter/EmitToStreamer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmPrinter/EmitToStreamer.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmPrinter/LLVMInitializeAsmPrinter.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmPrinter/LLVMInitializeAsmPrinter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4d4ab5bf715e86e02b908fb3cab0a9fd1fecee42 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmPrinter/LLVMInitializeAsmPrinter.cpp @@ -0,0 +1,6 @@ +extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMipsAsmPrinter() { + RegisterAsmPrinter X(getTheMipsTarget()); + RegisterAsmPrinter Y(getTheMipselTarget()); + RegisterAsmPrinter A(getTheMips64Target()); + RegisterAsmPrinter B(getTheMips64elTarget()); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmPrinter/PrintAsmMemoryOperand.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmPrinter/PrintAsmMemoryOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..13d636aa596545eb1d4a0b5e90251d6ac7d5200a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmPrinter/PrintAsmMemoryOperand.cpp @@ -0,0 +1,27 @@ +bool MipsAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum, const char *ExtraCode, raw_ostream &O) { + assert(OpNum + 1 < MI->getNumOperands() && "Insufficient operands"); + const MachineOperand &BaseMO = MI->getOperand(OpNum); + const MachineOperand &OffsetMO = MI->getOperand(OpNum + 1); + assert(BaseMO.isReg() && "Unexpected base pointer for inline asm memory operand."); + assert(OffsetMO.isImm() && "Unexpected offset for inline asm memory operand."); + int Offset = OffsetMO.getImm(); + if (ExtraCode) { + switch (ExtraCode[0]) { + case 'D': + Offset += 4; + break; + case 'M': + if (Subtarget->isLittle()) + Offset += 4; + break; + case 'L': + if (!Subtarget->isLittle()) + Offset += 4; + break; + default: + return true; + } + } + O << Offset << "($" << MipsInstPrinter::getRegisterName(BaseMO.getReg()) << ")"; + return false; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmPrinter/PrintAsmOperand.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmPrinter/PrintAsmOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..79f3c9422c159809396fc8b54c7323732a4efe88 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmPrinter/PrintAsmOperand.cpp @@ -0,0 +1,89 @@ +bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, const char *ExtraCode, raw_ostream &O) { + if (ExtraCode && ExtraCode[0]) { + if (ExtraCode[1] != 0) return true; + const MachineOperand &MO = MI->getOperand(OpNum); + switch (ExtraCode[0]) { + default: + return AsmPrinter::PrintAsmOperand(MI, OpNum, ExtraCode, O); + case 'X': + if ((MO.getType()) != MachineOperand::MO_Immediate) + return true; + O << "0x" << Twine::utohexstr(MO.getImm()); + return false; + case 'x': + if ((MO.getType()) != MachineOperand::MO_Immediate) + return true; + O << "0x" << Twine::utohexstr(MO.getImm() & 0xffff); + return false; + case 'd': + if ((MO.getType()) != MachineOperand::MO_Immediate) + return true; + O << MO.getImm(); + return false; + case 'm': + if ((MO.getType()) != MachineOperand::MO_Immediate) + return true; + O << MO.getImm() - 1; + return false; + case 'y': + if ((MO.getType()) != MachineOperand::MO_Immediate) + return true; + if (!isPowerOf2_64(MO.getImm())) + return true; + O << Log2_64(MO.getImm()); + return false; + case 'z': + if (MO.getType() == MachineOperand::MO_Immediate && MO.getImm() == 0) { + O << "$0"; + return false; + } + break; + case 'D': + case 'L': + case 'M': + { + if (OpNum == 0) + return true; + const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1); + if (!FlagsOP.isImm()) + return true; + unsigned Flags = FlagsOP.getImm(); + unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags); + if (NumVals != 2) { + if (Subtarget->isGP64bit() && NumVals == 1 && MO.isReg()) { + Register Reg = MO.getReg(); + O << '$' << MipsInstPrinter::getRegisterName(Reg); + return false; + } + return true; + } + unsigned RegOp = OpNum; + if (!Subtarget->isGP64bit()){ + switch(ExtraCode[0]) { + case 'M': + RegOp = (Subtarget->isLittle()) ? OpNum + 1 : OpNum; + break; + case 'L': + RegOp = (Subtarget->isLittle()) ? OpNum : OpNum + 1; + break; + case 'D': + RegOp = OpNum + 1; + } + if (RegOp >= MI->getNumOperands()) + return true; + const MachineOperand &MO = MI->getOperand(RegOp); + if (!MO.isReg()) + return true; + Register Reg = MO.getReg(); + O << '$' << MipsInstPrinter::getRegisterName(Reg); + return false; + } + break; + } + case 'w': + break; + } + } + printOperand(MI, OpNum, O); + return false; +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmPrinter/emitAttributes.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmPrinter/emitAttributes.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmPrinter/emitAttributes.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmPrinter/emitEndOfAsmFile.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmPrinter/emitEndOfAsmFile.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c7146d50f3a4b68a80abd13882286d1c3d617f2b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmPrinter/emitEndOfAsmFile.cpp @@ -0,0 +1,8 @@ +void MipsAsmPrinter::emitEndOfAsmFile(Module &M) { + for (std::map::const_iterator it = StubsNeeded.begin(); it != StubsNeeded.end(); ++it) { + const char *Symbol = it->first; + const Mips16HardFloatInfo::FuncSignature *Signature = it->second; + EmitFPCallStub(Symbol, Signature); + } + OutStreamer->SwitchSection(OutContext.getObjectFileInfo()->getTextSection()); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmPrinter/emitInstruction.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmPrinter/emitInstruction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..52d759a06f0cc7d92fe9b7e4c9454e2fb460d219 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmPrinter/emitInstruction.cpp @@ -0,0 +1,63 @@ +void MipsAsmPrinter::emitInstruction(const MachineInstr *MI) { + MipsTargetStreamer &TS = getTargetStreamer(); + unsigned Opc = MI->getOpcode(); + TS.forbidModuleDirective(); + if (MI->isDebugValue()) { + SmallString<128> Str; + raw_svector_ostream OS(Str); + PrintDebugValueComment(MI, OS); + return; + } + if (MI->isDebugLabel()) + return; + if (InConstantPool && Opc != Mips::CONSTPOOL_ENTRY) { + OutStreamer->emitDataRegion(MCDR_DataRegionEnd); + InConstantPool = false; + } + if (Opc == Mips::CONSTPOOL_ENTRY) { + unsigned LabelId = (unsigned)MI->getOperand(0).getImm(); + unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex(); + if (!InConstantPool) { + OutStreamer->emitDataRegion(MCDR_DataRegion); + InConstantPool = true; + } + OutStreamer->emitLabel(GetCPISymbol(LabelId)); + const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx]; + if (MCPE.isMachineConstantPoolEntry()) + emitMachineConstantPoolValue(MCPE.Val.MachineCPVal); + else + emitGlobalConstant(MF->getDataLayout(), MCPE.Val.ConstVal); + return; + } + switch (Opc) { + case Mips::PATCHABLE_FUNCTION_ENTER: + LowerPATCHABLE_FUNCTION_ENTER(*MI); + return; + case Mips::PATCHABLE_FUNCTION_EXIT: + LowerPATCHABLE_FUNCTION_EXIT(*MI); + return; + case Mips::PATCHABLE_TAIL_CALL: + LowerPATCHABLE_TAIL_CALL(*MI); + return; + } + if (EmitJalrReloc && (MI->isReturn() || MI->isCall() || MI->isIndirectBranch())) { + emitDirectiveRelocJalr(*MI, OutContext, TM, *OutStreamer, *Subtarget); + } + MachineBasicBlock::const_instr_iterator I = MI->getIterator(); + MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end(); + do { + if (emitPseudoExpansionLowering(*OutStreamer, &*I)) + continue; + if (I->isBundle()) + continue; + if (I->getOpcode() == Mips::PseudoReturn || I->getOpcode() == Mips::PseudoReturn64 || I->getOpcode() == Mips::PseudoIndirectBranch || I->getOpcode() == Mips::PseudoIndirectBranch64 || I->getOpcode() == Mips::TAILCALLREG || I->getOpcode() == Mips::TAILCALLREG64) { + emitPseudoIndirectBranch(*OutStreamer, &*I); + continue; + } + if (I->isPseudo() && !Subtarget->inMips16Mode() && !isLongBranchPseudo(I->getOpcode())) + llvm_unreachable("Pseudo opcode found in emitInstruction()"); + MCInst TmpInst0; + MCInstLowering.Lower(&*I, TmpInst0); + EmitToStreamer(*OutStreamer, TmpInst0); + } while ((++I != E) && I->isInsideBundle()); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmPrinter/emitStartOfAsmFile.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmPrinter/emitStartOfAsmFile.cpp new file mode 100644 index 0000000000000000000000000000000000000000..67253a3102205d65b0ab1e07350da6cc883fc27d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmPrinter/emitStartOfAsmFile.cpp @@ -0,0 +1,8 @@ +void MipsAsmPrinter::emitInlineAsmStart() const { + MipsTargetStreamer &TS = getTargetStreamer(); + TS.emitDirectiveSetPush(); + TS.emitDirectiveSetAt(); + TS.emitDirectiveSetMacro(); + TS.emitDirectiveSetReorder(); + OutStreamer->AddBlankLine(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmPrinter/getPassName.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmPrinter/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..39ec07ec3d83ebefc05c0f7f720dba157cb08bb7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmPrinter/getPassName.cpp @@ -0,0 +1,3 @@ +StringRef getPassName() const override { + return "Mips Assembly Printer"; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmPrinter/lowerOperand.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmPrinter/lowerOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..217416888da6098c0f3f5d5d508fa79919629b53 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmPrinter/lowerOperand.cpp @@ -0,0 +1,4 @@ +bool MipsAsmPrinter::lowerOperand(const MachineOperand &MO, MCOperand &MCOp) { + MCOp = MCInstLowering.LowerOperand(MO); + return MCOp.isValid(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmPrinter/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmPrinter/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1ea4e69b88d62186a605cf374ec7eb5204d98196 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Assembler/AsmPrinter/runOnMachineFunction.cpp @@ -0,0 +1,17 @@ +bool MipsAsmPrinter::runOnMachineFunction(MachineFunction &MF) { + Subtarget = &MF.getSubtarget(); + MipsFI = MF.getInfo(); + if (Subtarget->inMips16Mode()) + for (std::map::const_iterator it = MipsFI->StubsNeeded.begin(); it != MipsFI->StubsNeeded.end(); ++it) { + const char *Symbol = it->first; + const Mips16HardFloatInfo::FuncSignature *Signature = it->second; + if (StubsNeeded.find(Symbol) == StubsNeeded.end()) + StubsNeeded[Symbol] = Signature; + } + MCP = MF.getConstantPool(); + if (Subtarget->isTargetNaCl()) + NaClAlignIndirectJumpTargets(MF); + AsmPrinter::runOnMachineFunction(MF); + emitXRayTable(); + return true; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/DecodeFPR16RegisterClass.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/DecodeFPR16RegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..61b2928a98a3b89735c62a0242d23f47844cecbb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/DecodeFPR16RegisterClass.cpp @@ -0,0 +1,7 @@ +static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { + if (RegNo > 31) + return MCDisassembler::Fail; + unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo); + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/DecodeFPR32CRegisterClass.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/DecodeFPR32CRegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..61b2928a98a3b89735c62a0242d23f47844cecbb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/DecodeFPR32CRegisterClass.cpp @@ -0,0 +1,7 @@ +static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { + if (RegNo > 31) + return MCDisassembler::Fail; + unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo); + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/DecodeFPR32RegisterClass.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/DecodeFPR32RegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..61b2928a98a3b89735c62a0242d23f47844cecbb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/DecodeFPR32RegisterClass.cpp @@ -0,0 +1,7 @@ +static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { + if (RegNo > 31) + return MCDisassembler::Fail; + unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo); + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/DecodeFPR64CRegisterClass.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/DecodeFPR64CRegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..950f52d398b103964a07e02830d6937798200f64 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/DecodeFPR64CRegisterClass.cpp @@ -0,0 +1,7 @@ +static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { + if (RegNo > 31) + return MCDisassembler::Fail; + unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo); + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/DecodeFPR64RegisterClass.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/DecodeFPR64RegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..40fd65a586b4b9459534d9dadd3e4fad80e94d91 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/DecodeFPR64RegisterClass.cpp @@ -0,0 +1,7 @@ +static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { + if (RegNo > 31) + return MCDisassembler::Fail; + unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo); + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/DecodeGPRCRegisterClass.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/DecodeGPRCRegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b8ff7c7c69fefcdedcff7ad87e852bc482b75b52 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/DecodeGPRCRegisterClass.cpp @@ -0,0 +1,7 @@ +static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { + if (RegNo > 7) + return MCDisassembler::Fail; + unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo); + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/DecodeGPRNoX0RegisterClass.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/DecodeGPRNoX0RegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b8ff7c7c69fefcdedcff7ad87e852bc482b75b52 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/DecodeGPRNoX0RegisterClass.cpp @@ -0,0 +1,7 @@ +static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { + if (RegNo > 7) + return MCDisassembler::Fail; + unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo); + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/DecodeGPRNoX0X2RegisterClass.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/DecodeGPRNoX0X2RegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b8ff7c7c69fefcdedcff7ad87e852bc482b75b52 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/DecodeGPRNoX0X2RegisterClass.cpp @@ -0,0 +1,7 @@ +static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { + if (RegNo > 7) + return MCDisassembler::Fail; + unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo); + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/DecodeGPRRegisterClass.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/DecodeGPRRegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fa54d4bfd9313a9f0a99641dacadf1e355216ffb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/DecodeGPRRegisterClass.cpp @@ -0,0 +1,7 @@ +static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { + if (RegNo > 31) + return MCDisassembler::Fail; + unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/DecodeVRRegisterClass.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/DecodeVRRegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a030e0d8da7f3ccce562c0f64f602a27fac68994 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/DecodeVRRegisterClass.cpp @@ -0,0 +1,6 @@ +template static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder) { + Value &= ((1 << Bits) - 1); + Value *= Scale; + Inst.addOperand(MCOperand::createImm(Value + Offset)); + return MCDisassembler::Success; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/Disassembler.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/Disassembler.cpp new file mode 100644 index 0000000000000000000000000000000000000000..289bc27b55c7aa92cbcaaaafea3aa7bfec1dc351 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/Disassembler.cpp @@ -0,0 +1,2 @@ +MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian) : MCDisassembler(STI, Ctx), IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]), IsBigEndian(IsBigEndian) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/LLVMInitializeDisassembler.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/LLVMInitializeDisassembler.cpp new file mode 100644 index 0000000000000000000000000000000000000000..aac362f8290944c06ffebaf290b8b64edc748283 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/LLVMInitializeDisassembler.cpp @@ -0,0 +1,6 @@ +extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMipsDisassembler() { + TargetRegistry::RegisterMCDisassembler(getTheMipsTarget(), createMipsDisassembler); + TargetRegistry::RegisterMCDisassembler(getTheMipselTarget(), createMipselDisassembler); + TargetRegistry::RegisterMCDisassembler(getTheMips64Target(), createMipsDisassembler); + TargetRegistry::RegisterMCDisassembler(getTheMips64elTarget(), createMipselDisassembler); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/addImplySP.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/addImplySP.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/addImplySP.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/createDisassembler.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/createDisassembler.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c9f23dc4c3675d6d55e1ff1b1517fc2d45acc8ea --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/createDisassembler.cpp @@ -0,0 +1,3 @@ +static MCDisassembler *createMipsDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx) { + return new MipsDisassembler(STI, Ctx, true); +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/decodeCLUIImmOperand.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/decodeCLUIImmOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8dc5ce568523000d9e6a9d150a81ec69f1c4be78 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/decodeCLUIImmOperand.cpp @@ -0,0 +1,7 @@ +static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { + if (RegNo > 31) + return MCDisassembler::Fail; + unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo); + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/decodeFRMArg.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/decodeFRMArg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f4c2cab7aa576d3436889701317d4baac06b9654 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/decodeFRMArg.cpp @@ -0,0 +1,8 @@ +static DecodeStatus DecodeSyncI(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { + int Offset = SignExtend32<16>(Insn & 0xffff); + unsigned Base = fieldFromInstruction(Insn, 21, 5); + Base = getReg(Decoder, Mips::GPR32RegClassID, Base); + Inst.addOperand(MCOperand::createReg(Base)); + Inst.addOperand(MCOperand::createImm(Offset)); + return MCDisassembler::Success; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/decodeRVCInstrRdRs1Rs2.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/decodeRVCInstrRdRs1Rs2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0c23a00c41dc130ecb77e4891a914a978975a57e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/decodeRVCInstrRdRs1Rs2.cpp @@ -0,0 +1,8 @@ +template static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address, const void *Decoder) { + InsnType Rs = fieldFromInstruction(Insn, 21, 5); + InsnType Rt = fieldFromInstruction(Insn, 16, 5); + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); + return MCDisassembler::Success; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/decodeRVCInstrRdRs1UImm.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/decodeRVCInstrRdRs1UImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0c23a00c41dc130ecb77e4891a914a978975a57e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/decodeRVCInstrRdRs1UImm.cpp @@ -0,0 +1,8 @@ +template static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address, const void *Decoder) { + InsnType Rs = fieldFromInstruction(Insn, 21, 5); + InsnType Rt = fieldFromInstruction(Insn, 16, 5); + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); + return MCDisassembler::Success; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/decodeRVCInstrRdRs2.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/decodeRVCInstrRdRs2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0c23a00c41dc130ecb77e4891a914a978975a57e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/decodeRVCInstrRdRs2.cpp @@ -0,0 +1,8 @@ +template static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address, const void *Decoder) { + InsnType Rs = fieldFromInstruction(Insn, 21, 5); + InsnType Rt = fieldFromInstruction(Insn, 16, 5); + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); + return MCDisassembler::Success; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/decodeRVCInstrRdSImm.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/decodeRVCInstrRdSImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0c23a00c41dc130ecb77e4891a914a978975a57e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/decodeRVCInstrRdSImm.cpp @@ -0,0 +1,8 @@ +template static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address, const void *Decoder) { + InsnType Rs = fieldFromInstruction(Insn, 21, 5); + InsnType Rt = fieldFromInstruction(Insn, 16, 5); + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); + return MCDisassembler::Success; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/decodeRVCInstrSImm.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/decodeRVCInstrSImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0c23a00c41dc130ecb77e4891a914a978975a57e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/decodeRVCInstrSImm.cpp @@ -0,0 +1,8 @@ +template static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address, const void *Decoder) { + InsnType Rs = fieldFromInstruction(Insn, 21, 5); + InsnType Rt = fieldFromInstruction(Insn, 16, 5); + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); + return MCDisassembler::Success; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/decodeSImmNonZeroOperand.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/decodeSImmNonZeroOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0282ae9b186c226781e9e8e2f3cc39a828d3ef17 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/decodeSImmNonZeroOperand.cpp @@ -0,0 +1,5 @@ +template static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder) { + int32_t Imm = SignExtend32(Value) * ScaleBy; + Inst.addOperand(MCOperand::createImm(Imm + Offset)); + return MCDisassembler::Success; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/decodeSImmOperand.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/decodeSImmOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0282ae9b186c226781e9e8e2f3cc39a828d3ef17 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/decodeSImmOperand.cpp @@ -0,0 +1,5 @@ +template static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder) { + int32_t Imm = SignExtend32(Value) * ScaleBy; + Inst.addOperand(MCOperand::createImm(Imm + Offset)); + return MCDisassembler::Success; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/decodeSImmOperandAndLsl1.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/decodeSImmOperandAndLsl1.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0282ae9b186c226781e9e8e2f3cc39a828d3ef17 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/decodeSImmOperandAndLsl1.cpp @@ -0,0 +1,5 @@ +template static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder) { + int32_t Imm = SignExtend32(Value) * ScaleBy; + Inst.addOperand(MCOperand::createImm(Imm + Offset)); + return MCDisassembler::Success; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/decodeUImmNonZeroOperand.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/decodeUImmNonZeroOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a030e0d8da7f3ccce562c0f64f602a27fac68994 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/decodeUImmNonZeroOperand.cpp @@ -0,0 +1,6 @@ +template static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder) { + Value &= ((1 << Bits) - 1); + Value *= Scale; + Inst.addOperand(MCOperand::createImm(Value + Offset)); + return MCDisassembler::Success; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/decodeUImmOperand.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/decodeUImmOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a030e0d8da7f3ccce562c0f64f602a27fac68994 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/decodeUImmOperand.cpp @@ -0,0 +1,6 @@ +template static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder) { + Value &= ((1 << Bits) - 1); + Value *= Scale; + Inst.addOperand(MCOperand::createImm(Value + Offset)); + return MCDisassembler::Success; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/decodeVMaskReg.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/decodeVMaskReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a030e0d8da7f3ccce562c0f64f602a27fac68994 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/decodeVMaskReg.cpp @@ -0,0 +1,6 @@ +template static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder) { + Value &= ((1 << Bits) - 1); + Value *= Scale; + Inst.addOperand(MCOperand::createImm(Value + Offset)); + return MCDisassembler::Success; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/getInstruction.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/getInstruction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..97a894caca0ae1138b9d72b7014c73e34494b18c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Disassembler/Disassembler/getInstruction.cpp @@ -0,0 +1,114 @@ +DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef Bytes, uint64_t Address, raw_ostream &CStream) const { + uint32_t Insn; + DecodeStatus Result; + Size = 0; + if (IsMicroMips) { + Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian); + if (Result == MCDisassembler::Fail) + return MCDisassembler::Fail; + if (hasMips32r6()) { + LLVM_DEBUG(dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n"); + Result = decodeInstruction(DecoderTableMicroMipsR616, Instr, Insn, Address, this, STI); + if (Result != MCDisassembler::Fail) { + Size = 2; + return Result; + } + } + LLVM_DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n"); + Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address, this, STI); + if (Result != MCDisassembler::Fail) { + Size = 2; + return Result; + } + Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true); + if (Result == MCDisassembler::Fail) + return MCDisassembler::Fail; + if (hasMips32r6()) { + LLVM_DEBUG(dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n"); + Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn, Address, this, STI); + if (Result != MCDisassembler::Fail) { + Size = 4; + return Result; + } + } + LLVM_DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n"); + Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address, this, STI); + if (Result != MCDisassembler::Fail) { + Size = 4; + return Result; + } + if (isFP64()) { + LLVM_DEBUG(dbgs() << "Trying MicroMipsFP64 table (32-bit opcodes):\n"); + Result = decodeInstruction(DecoderTableMicroMipsFP6432, Instr, Insn, Address, this, STI); + if (Result != MCDisassembler::Fail) { + Size = 4; + return Result; + } + } + Size = 2; + return MCDisassembler::Fail; + } + Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false); + if (Result == MCDisassembler::Fail) + return MCDisassembler::Fail; + Size = 4; + if (hasCOP3()) { + LLVM_DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n"); + Result = decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI); + if (Result != MCDisassembler::Fail) + return Result; + } + if (hasMips32r6() && isGP64()) { + LLVM_DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n"); + Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn, Address, this, STI); + if (Result != MCDisassembler::Fail) + return Result; + } + if (hasMips32r6() && isPTR64()) { + LLVM_DEBUG(dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n"); + Result = decodeInstruction(DecoderTableMips32r6_64r6_PTR6432, Instr, Insn, Address, this, STI); + if (Result != MCDisassembler::Fail) + return Result; + } + if (hasMips32r6()) { + LLVM_DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n"); + Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn, Address, this, STI); + if (Result != MCDisassembler::Fail) + return Result; + } + if (hasMips2() && isPTR64()) { + LLVM_DEBUG(dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n"); + Result = decodeInstruction(DecoderTableMips32_64_PTR6432, Instr, Insn, Address, this, STI); + if (Result != MCDisassembler::Fail) + return Result; + } + if (hasCnMips()) { + LLVM_DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n"); + Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn, Address, this, STI); + if (Result != MCDisassembler::Fail) + return Result; + } + if (hasCnMipsP()) { + LLVM_DEBUG(dbgs() << "Trying CnMipsP table (32-bit opcodes):\n"); + Result = decodeInstruction(DecoderTableCnMipsP32, Instr, Insn, Address, this, STI); + if (Result != MCDisassembler::Fail) + return Result; + } + if (isGP64()) { + LLVM_DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n"); + Result = decodeInstruction(DecoderTableMips6432, Instr, Insn, Address, this, STI); + if (Result != MCDisassembler::Fail) + return Result; + } + if (isFP64()) { + LLVM_DEBUG(dbgs() << "Trying MipsFP64 (64 bit FPU) table (32-bit opcodes):\n"); + Result = decodeInstruction(DecoderTableMipsFP6432, Instr, Insn, Address, this, STI); + if (Result != MCDisassembler::Fail) + return Result; + } + LLVM_DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n"); + Result = decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI); + if (Result != MCDisassembler::Fail) + return Result; + return MCDisassembler::Fail; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/AsmBackend.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/AsmBackend.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7ae0321d2626e19fa5446eb52df8fbb49738d2df --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/AsmBackend.cpp @@ -0,0 +1,2 @@ +MipsAsmBackend(const Target &T, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU, bool N32) : MCAsmBackend(TT.isLittleEndian() ? support::little : support::big), TheTriple(TT), IsN32(N32) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/adjustFixupValue.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/adjustFixupValue.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e955e760b17b32c034de715643494327c2cb575e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/adjustFixupValue.cpp @@ -0,0 +1,144 @@ +static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value, MCContext &Ctx) { + unsigned Kind = Fixup.getKind(); + switch (Kind) { + default: + return 0; + case FK_Data_2: + case Mips::fixup_Mips_LO16: + case Mips::fixup_Mips_GPREL16: + case Mips::fixup_Mips_GPOFF_HI: + case Mips::fixup_Mips_GPOFF_LO: + case Mips::fixup_Mips_GOT_PAGE: + case Mips::fixup_Mips_GOT_OFST: + case Mips::fixup_Mips_GOT_DISP: + case Mips::fixup_Mips_GOT_LO16: + case Mips::fixup_Mips_CALL_LO16: + case Mips::fixup_MICROMIPS_GPOFF_HI: + case Mips::fixup_MICROMIPS_GPOFF_LO: + case Mips::fixup_MICROMIPS_LO16: + case Mips::fixup_MICROMIPS_GOT_PAGE: + case Mips::fixup_MICROMIPS_GOT_OFST: + case Mips::fixup_MICROMIPS_GOT_DISP: + case Mips::fixup_MIPS_PCLO16: + Value &= 0xffff; + break; + case FK_DTPRel_4: + case FK_DTPRel_8: + case FK_TPRel_4: + case FK_TPRel_8: + case FK_GPRel_4: + case FK_Data_4: + case FK_Data_8: + case Mips::fixup_Mips_SUB: + case Mips::fixup_MICROMIPS_SUB: + break; + case Mips::fixup_Mips_PC16: + Value = (int64_t)Value / 4; + if (!isInt<16>(Value)) { + Ctx.reportError(Fixup.getLoc(), "out of range PC16 fixup"); + return 0; + } + break; + case Mips::fixup_MIPS_PC19_S2: + case Mips::fixup_MICROMIPS_PC19_S2: + Value = (int64_t)Value / 4; + if (!isInt<19>(Value)) { + Ctx.reportError(Fixup.getLoc(), "out of range PC19 fixup"); + return 0; + } + break; + case Mips::fixup_Mips_26: + Value >>= 2; + break; + case Mips::fixup_Mips_HI16: + case Mips::fixup_Mips_GOT: + case Mips::fixup_MICROMIPS_GOT16: + case Mips::fixup_Mips_GOT_HI16: + case Mips::fixup_Mips_CALL_HI16: + case Mips::fixup_MICROMIPS_HI16: + case Mips::fixup_MIPS_PCHI16: + Value = ((Value + 0x8000) >> 16) & 0xffff; + break; + case Mips::fixup_Mips_HIGHER: + case Mips::fixup_MICROMIPS_HIGHER: + Value = ((Value + 0x80008000LL) >> 32) & 0xffff; + break; + case Mips::fixup_Mips_HIGHEST: + case Mips::fixup_MICROMIPS_HIGHEST: + Value = ((Value + 0x800080008000LL) >> 48) & 0xffff; + break; + case Mips::fixup_MICROMIPS_26_S1: + Value >>= 1; + break; + case Mips::fixup_MICROMIPS_PC7_S1: + Value -= 4; + Value = (int64_t) Value / 2; + if (!isInt<7>(Value)) { + Ctx.reportError(Fixup.getLoc(), "out of range PC7 fixup"); + return 0; + } + break; + case Mips::fixup_MICROMIPS_PC10_S1: + Value -= 2; + Value = (int64_t) Value / 2; + if (!isInt<10>(Value)) { + Ctx.reportError(Fixup.getLoc(), "out of range PC10 fixup"); + return 0; + } + break; + case Mips::fixup_MICROMIPS_PC16_S1: + Value -= 4; + Value = (int64_t)Value / 2; + if (!isInt<16>(Value)) { + Ctx.reportError(Fixup.getLoc(), "out of range PC16 fixup"); + return 0; + } + break; + case Mips::fixup_MIPS_PC18_S3: + Value = (int64_t)Value / 8; + if (!isInt<18>(Value)) { + Ctx.reportError(Fixup.getLoc(), "out of range PC18 fixup"); + return 0; + } + break; + case Mips::fixup_MICROMIPS_PC18_S3: + if ((Value & 7)) { + Ctx.reportError(Fixup.getLoc(), "out of range PC18 fixup"); + } + Value = (int64_t)Value / 8; + if (!isInt<18>(Value)) { + Ctx.reportError(Fixup.getLoc(), "out of range PC18 fixup"); + return 0; + } + break; + case Mips::fixup_MIPS_PC21_S2: + Value = (int64_t) Value / 4; + if (!isInt<21>(Value)) { + Ctx.reportError(Fixup.getLoc(), "out of range PC21 fixup"); + return 0; + } + break; + case Mips::fixup_MIPS_PC26_S2: + Value = (int64_t) Value / 4; + if (!isInt<26>(Value)) { + Ctx.reportError(Fixup.getLoc(), "out of range PC26 fixup"); + return 0; + } + break; + case Mips::fixup_MICROMIPS_PC26_S1: + Value = (int64_t)Value / 2; + if (!isInt<26>(Value)) { + Ctx.reportFatalError(Fixup.getLoc(), "out of range PC26 fixup"); + return 0; + } + break; + case Mips::fixup_MICROMIPS_PC21_S1: + Value = (int64_t)Value / 2; + if (!isInt<21>(Value)) { + Ctx.reportError(Fixup.getLoc(), "out of range PC21 fixup"); + return 0; + } + break; + } + return Value; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/applyFixup.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/applyFixup.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d9211dcecd9d0b897b105d23d99f75b18563bee0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/applyFixup.cpp @@ -0,0 +1,37 @@ +void MipsAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, MutableArrayRef Data, uint64_t Value, bool IsResolved, const MCSubtargetInfo *STI) const { + MCFixupKind Kind = Fixup.getKind(); + MCContext &Ctx = Asm.getContext(); + Value = adjustFixupValue(Fixup, Value, Ctx); + if (!Value) + return; + unsigned Offset = Fixup.getOffset(); + unsigned NumBytes = (getFixupKindInfo(Kind).TargetSize + 7) / 8; + unsigned FullSize; + switch ((unsigned)Kind) { + case FK_Data_2: + case Mips::fixup_Mips_16: + case Mips::fixup_MICROMIPS_PC10_S1: + FullSize = 2; + break; + case FK_Data_8: + case Mips::fixup_Mips_64: + FullSize = 8; + break; + case FK_Data_4: + default: + FullSize = 4; + break; + } + uint64_t CurVal = 0; + bool microMipsLEByteOrder = needsMMLEByteOrder((unsigned) Kind); + for (unsigned i = 0; i != NumBytes; ++i) { + unsigned Idx = Endian == support::little ? (microMipsLEByteOrder ? calculateMMLEIndex(i) : i) : (FullSize - 1 - i); + CurVal |= (uint64_t)((uint8_t)Data[Offset + Idx]) << (i*8); + } + uint64_t Mask = ((uint64_t)(-1) >> (64 - getFixupKindInfo(Kind).TargetSize)); + CurVal |= Value & Mask; + for (unsigned i = 0; i != NumBytes; ++i) { + unsigned Idx = Endian == support::little ? (microMipsLEByteOrder ? calculateMMLEIndex(i) : i): (FullSize - 1 - i); + Data[Offset + Idx] = (uint8_t)((CurVal >> (i*8)) & 0xff); + } +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/createAsmBackend.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/createAsmBackend.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ea5dcd4a2c2d8d9b3c9e7a32fdfd9f44242047f1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/createAsmBackend.cpp @@ -0,0 +1,4 @@ +MCAsmBackend *llvm::createMipsAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options) { + MipsABIInfo ABI = MipsABIInfo::computeTargetABI(STI.getTargetTriple(), STI.getCPU(), Options); + return new MipsAsmBackend(T, MRI, STI.getTargetTriple(), STI.getCPU(), ABI.IsN32()); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/createObjectTargetWriter.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/createObjectTargetWriter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..00f1fa1f26067758af5e13abbd8903b7c44a4d89 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/createObjectTargetWriter.cpp @@ -0,0 +1,4 @@ +std::unique_ptr MipsAsmBackend::createObjectTargetWriter() const { + return createMipsELFObjectWriter(TheTriple, IsN32); +} + diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/evaluateTargetFixup.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/evaluateTargetFixup.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/evaluateTargetFixup.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/fixupNeedsRelaxation.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/fixupNeedsRelaxation.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/fixupNeedsRelaxation.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/fixupNeedsRelaxationAdvanced.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/fixupNeedsRelaxationAdvanced.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/fixupNeedsRelaxationAdvanced.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/getFixupKind.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/getFixupKind.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1a92b79f89ec89f4e0b16dfd5b04b822a41bfa98 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/getFixupKind.cpp @@ -0,0 +1,36 @@ +Optional MipsAsmBackend::getFixupKind(StringRef Name) const { + return StringSwitch>(Name) + .Case("R_MIPS_NONE", FK_NONE) + .Case("R_MIPS_32", FK_Data_4) + .Case("R_MIPS_CALL_HI16", (MCFixupKind)Mips::fixup_Mips_CALL_HI16) + .Case("R_MIPS_CALL_LO16", (MCFixupKind)Mips::fixup_Mips_CALL_LO16) + .Case("R_MIPS_CALL16", (MCFixupKind)Mips::fixup_Mips_CALL16) + .Case("R_MIPS_GOT16", (MCFixupKind)Mips::fixup_Mips_GOT) + .Case("R_MIPS_GOT_PAGE", (MCFixupKind)Mips::fixup_Mips_GOT_PAGE) + .Case("R_MIPS_GOT_OFST", (MCFixupKind)Mips::fixup_Mips_GOT_OFST) + .Case("R_MIPS_GOT_DISP", (MCFixupKind)Mips::fixup_Mips_GOT_DISP) + .Case("R_MIPS_GOT_HI16", (MCFixupKind)Mips::fixup_Mips_GOT_HI16) + .Case("R_MIPS_GOT_LO16", (MCFixupKind)Mips::fixup_Mips_GOT_LO16) + .Case("R_MIPS_TLS_GOTTPREL", (MCFixupKind)Mips::fixup_Mips_GOTTPREL) + .Case("R_MIPS_TLS_DTPREL_HI16", (MCFixupKind)Mips::fixup_Mips_DTPREL_HI) + .Case("R_MIPS_TLS_DTPREL_LO16", (MCFixupKind)Mips::fixup_Mips_DTPREL_LO) + .Case("R_MIPS_TLS_GD", (MCFixupKind)Mips::fixup_Mips_TLSGD) + .Case("R_MIPS_TLS_LDM", (MCFixupKind)Mips::fixup_Mips_TLSLDM) + .Case("R_MIPS_TLS_TPREL_HI16", (MCFixupKind)Mips::fixup_Mips_TPREL_HI) + .Case("R_MIPS_TLS_TPREL_LO16", (MCFixupKind)Mips::fixup_Mips_TPREL_LO) + .Case("R_MICROMIPS_CALL16", (MCFixupKind)Mips::fixup_MICROMIPS_CALL16) + .Case("R_MICROMIPS_GOT_DISP", (MCFixupKind)Mips::fixup_MICROMIPS_GOT_DISP) + .Case("R_MICROMIPS_GOT_PAGE", (MCFixupKind)Mips::fixup_MICROMIPS_GOT_PAGE) + .Case("R_MICROMIPS_GOT_OFST", (MCFixupKind)Mips::fixup_MICROMIPS_GOT_OFST) + .Case("R_MICROMIPS_GOT16", (MCFixupKind)Mips::fixup_MICROMIPS_GOT16) + .Case("R_MICROMIPS_TLS_GOTTPREL", (MCFixupKind)Mips::fixup_MICROMIPS_GOTTPREL) + .Case("R_MICROMIPS_TLS_DTPREL_HI16", (MCFixupKind)Mips::fixup_MICROMIPS_TLS_DTPREL_HI16) + .Case("R_MICROMIPS_TLS_DTPREL_LO16", (MCFixupKind)Mips::fixup_MICROMIPS_TLS_DTPREL_LO16) + .Case("R_MICROMIPS_TLS_GD", (MCFixupKind)Mips::fixup_MICROMIPS_TLS_GD) + .Case("R_MICROMIPS_TLS_LDM", (MCFixupKind)Mips::fixup_MICROMIPS_TLS_LDM) + .Case("R_MICROMIPS_TLS_TPREL_HI16", (MCFixupKind)Mips::fixup_MICROMIPS_TLS_TPREL_HI16) + .Case("R_MICROMIPS_TLS_TPREL_LO16", (MCFixupKind)Mips::fixup_MICROMIPS_TLS_TPREL_LO16) + .Case("R_MIPS_JALR", (MCFixupKind)Mips::fixup_Mips_JALR) + .Case("R_MICROMIPS_JALR", (MCFixupKind)Mips::fixup_MICROMIPS_JALR) + .Default(MCAsmBackend::getFixupKind(Name)); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/getFixupKindInfo.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/getFixupKindInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..63f50b02cd845c04f7ac393ce134edd753ac4c6e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/getFixupKindInfo.cpp @@ -0,0 +1,154 @@ +const MCFixupKindInfo &MipsAsmBackend::getFixupKindInfo(MCFixupKind Kind) const { + const static MCFixupKindInfo LittleEndianInfos[] = { + { "fixup_Mips_16", 0, 16, 0 }, + { "fixup_Mips_32", 0, 32, 0 }, + { "fixup_Mips_REL32", 0, 32, 0 }, + { "fixup_Mips_26", 0, 26, 0 }, + { "fixup_Mips_HI16", 0, 16, 0 }, + { "fixup_Mips_LO16", 0, 16, 0 }, + { "fixup_Mips_GPREL16", 0, 16, 0 }, + { "fixup_Mips_LITERAL", 0, 16, 0 }, + { "fixup_Mips_GOT", 0, 16, 0 }, + { "fixup_Mips_PC16", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_Mips_CALL16", 0, 16, 0 }, + { "fixup_Mips_GPREL32", 0, 32, 0 }, + { "fixup_Mips_SHIFT5", 6, 5, 0 }, + { "fixup_Mips_SHIFT6", 6, 5, 0 }, + { "fixup_Mips_64", 0, 64, 0 }, + { "fixup_Mips_TLSGD", 0, 16, 0 }, + { "fixup_Mips_GOTTPREL", 0, 16, 0 }, + { "fixup_Mips_TPREL_HI", 0, 16, 0 }, + { "fixup_Mips_TPREL_LO", 0, 16, 0 }, + { "fixup_Mips_TLSLDM", 0, 16, 0 }, + { "fixup_Mips_DTPREL_HI", 0, 16, 0 }, + { "fixup_Mips_DTPREL_LO", 0, 16, 0 }, + { "fixup_Mips_Branch_PCRel", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_Mips_GPOFF_HI", 0, 16, 0 }, + { "fixup_MICROMIPS_GPOFF_HI",0, 16, 0 }, + { "fixup_Mips_GPOFF_LO", 0, 16, 0 }, + { "fixup_MICROMIPS_GPOFF_LO",0, 16, 0 }, + { "fixup_Mips_GOT_PAGE", 0, 16, 0 }, + { "fixup_Mips_GOT_OFST", 0, 16, 0 }, + { "fixup_Mips_GOT_DISP", 0, 16, 0 }, + { "fixup_Mips_HIGHER", 0, 16, 0 }, + { "fixup_MICROMIPS_HIGHER", 0, 16, 0 }, + { "fixup_Mips_HIGHEST", 0, 16, 0 }, + { "fixup_MICROMIPS_HIGHEST", 0, 16, 0 }, + { "fixup_Mips_GOT_HI16", 0, 16, 0 }, + { "fixup_Mips_GOT_LO16", 0, 16, 0 }, + { "fixup_Mips_CALL_HI16", 0, 16, 0 }, + { "fixup_Mips_CALL_LO16", 0, 16, 0 }, + { "fixup_Mips_PC18_S3", 0, 18, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_MIPS_PC19_S2", 0, 19, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_MIPS_PC21_S2", 0, 21, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_MIPS_PC26_S2", 0, 26, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_MIPS_PCHI16", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_MIPS_PCLO16", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_MICROMIPS_26_S1", 0, 26, 0 }, + { "fixup_MICROMIPS_HI16", 0, 16, 0 }, + { "fixup_MICROMIPS_LO16", 0, 16, 0 }, + { "fixup_MICROMIPS_GOT16", 0, 16, 0 }, + { "fixup_MICROMIPS_PC7_S1", 0, 7, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_MICROMIPS_PC10_S1", 0, 10, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_MICROMIPS_PC16_S1", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_MICROMIPS_PC26_S1", 0, 26, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_MICROMIPS_PC19_S2", 0, 19, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_MICROMIPS_PC18_S3", 0, 18, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_MICROMIPS_PC21_S1", 0, 21, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_MICROMIPS_CALL16", 0, 16, 0 }, + { "fixup_MICROMIPS_GOT_DISP", 0, 16, 0 }, + { "fixup_MICROMIPS_GOT_PAGE", 0, 16, 0 }, + { "fixup_MICROMIPS_GOT_OFST", 0, 16, 0 }, + { "fixup_MICROMIPS_TLS_GD", 0, 16, 0 }, + { "fixup_MICROMIPS_TLS_LDM", 0, 16, 0 }, + { "fixup_MICROMIPS_TLS_DTPREL_HI16", 0, 16, 0 }, + { "fixup_MICROMIPS_TLS_DTPREL_LO16", 0, 16, 0 }, + { "fixup_MICROMIPS_GOTTPREL", 0, 16, 0 }, + { "fixup_MICROMIPS_TLS_TPREL_HI16", 0, 16, 0 }, + { "fixup_MICROMIPS_TLS_TPREL_LO16", 0, 16, 0 }, + { "fixup_Mips_SUB", 0, 64, 0 }, + { "fixup_MICROMIPS_SUB", 0, 64, 0 }, + { "fixup_Mips_JALR", 0, 32, 0 }, + { "fixup_MICROMIPS_JALR", 0, 32, 0 } + }; + static_assert(array_lengthof(LittleEndianInfos) == Mips::NumTargetFixupKinds, "Not all MIPS little endian fixup kinds added!"); + const static MCFixupKindInfo BigEndianInfos[] = { + { "fixup_Mips_16", 16, 16, 0 }, + { "fixup_Mips_32", 0, 32, 0 }, + { "fixup_Mips_REL32", 0, 32, 0 }, + { "fixup_Mips_26", 6, 26, 0 }, + { "fixup_Mips_HI16", 16, 16, 0 }, + { "fixup_Mips_LO16", 16, 16, 0 }, + { "fixup_Mips_GPREL16", 16, 16, 0 }, + { "fixup_Mips_LITERAL", 16, 16, 0 }, + { "fixup_Mips_GOT", 16, 16, 0 }, + { "fixup_Mips_PC16", 16, 16, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_Mips_CALL16", 16, 16, 0 }, + { "fixup_Mips_GPREL32", 0, 32, 0 }, + { "fixup_Mips_SHIFT5", 21, 5, 0 }, + { "fixup_Mips_SHIFT6", 21, 5, 0 }, + { "fixup_Mips_64", 0, 64, 0 }, + { "fixup_Mips_TLSGD", 16, 16, 0 }, + { "fixup_Mips_GOTTPREL", 16, 16, 0 }, + { "fixup_Mips_TPREL_HI", 16, 16, 0 }, + { "fixup_Mips_TPREL_LO", 16, 16, 0 }, + { "fixup_Mips_TLSLDM", 16, 16, 0 }, + { "fixup_Mips_DTPREL_HI", 16, 16, 0 }, + { "fixup_Mips_DTPREL_LO", 16, 16, 0 }, + { "fixup_Mips_Branch_PCRel",16, 16, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_Mips_GPOFF_HI", 16, 16, 0 }, + { "fixup_MICROMIPS_GPOFF_HI", 16, 16, 0 }, + { "fixup_Mips_GPOFF_LO", 16, 16, 0 }, + { "fixup_MICROMIPS_GPOFF_LO", 16, 16, 0 }, + { "fixup_Mips_GOT_PAGE", 16, 16, 0 }, + { "fixup_Mips_GOT_OFST", 16, 16, 0 }, + { "fixup_Mips_GOT_DISP", 16, 16, 0 }, + { "fixup_Mips_HIGHER", 16, 16, 0 }, + { "fixup_MICROMIPS_HIGHER", 16, 16, 0 }, + { "fixup_Mips_HIGHEST", 16, 16, 0 }, + { "fixup_MICROMIPS_HIGHEST",16, 16, 0 }, + { "fixup_Mips_GOT_HI16", 16, 16, 0 }, + { "fixup_Mips_GOT_LO16", 16, 16, 0 }, + { "fixup_Mips_CALL_HI16", 16, 16, 0 }, + { "fixup_Mips_CALL_LO16", 16, 16, 0 }, + { "fixup_Mips_PC18_S3", 14, 18, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_MIPS_PC19_S2", 13, 19, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_MIPS_PC21_S2", 11, 21, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_MIPS_PC26_S2", 6, 26, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_MIPS_PCHI16", 16, 16, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_MIPS_PCLO16", 16, 16, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_MICROMIPS_26_S1", 6, 26, 0 }, + { "fixup_MICROMIPS_HI16", 16, 16, 0 }, + { "fixup_MICROMIPS_LO16", 16, 16, 0 }, + { "fixup_MICROMIPS_GOT16", 16, 16, 0 }, + { "fixup_MICROMIPS_PC7_S1", 9, 7, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_MICROMIPS_PC10_S1", 6, 10, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_MICROMIPS_PC16_S1",16, 16, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_MICROMIPS_PC26_S1", 6, 26, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_MICROMIPS_PC19_S2",13, 19, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_MICROMIPS_PC18_S3",14, 18, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_MICROMIPS_PC21_S1",11, 21, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_MICROMIPS_CALL16", 16, 16, 0 }, + { "fixup_MICROMIPS_GOT_DISP", 16, 16, 0 }, + { "fixup_MICROMIPS_GOT_PAGE", 16, 16, 0 }, + { "fixup_MICROMIPS_GOT_OFST", 16, 16, 0 }, + { "fixup_MICROMIPS_TLS_GD", 16, 16, 0 }, + { "fixup_MICROMIPS_TLS_LDM", 16, 16, 0 }, + { "fixup_MICROMIPS_TLS_DTPREL_HI16", 16, 16, 0 }, + { "fixup_MICROMIPS_TLS_DTPREL_LO16", 16, 16, 0 }, + { "fixup_MICROMIPS_GOTTPREL", 16, 16, 0 }, + { "fixup_MICROMIPS_TLS_TPREL_HI16", 16, 16, 0 }, + { "fixup_MICROMIPS_TLS_TPREL_LO16", 16, 16, 0 }, + { "fixup_Mips_SUB", 0, 64, 0 }, + { "fixup_MICROMIPS_SUB", 0, 64, 0 }, + { "fixup_Mips_JALR", 0, 32, 0 }, + { "fixup_MICROMIPS_JALR", 0, 32, 0 } + }; + static_assert(array_lengthof(BigEndianInfos) == Mips::NumTargetFixupKinds, "Not all MIPS big endian fixup kinds added!"); + if (Kind < FirstTargetFixupKind) + return MCAsmBackend::getFixupKindInfo(Kind); + assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && "Invalid kind!"); + if (Endian == support::little) + return LittleEndianInfos[Kind - FirstTargetFixupKind]; + return BigEndianInfos[Kind - FirstTargetFixupKind]; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/getNumFixupKinds.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/getNumFixupKinds.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/getNumFixupKinds.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/getRelaxedOpcode.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/getRelaxedOpcode.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/getRelaxedOpcode.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/getTargetABI.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/getTargetABI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/getTargetABI.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/getTargetOptions.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/getTargetOptions.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/getTargetOptions.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/mayNeedRelaxation.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/mayNeedRelaxation.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/mayNeedRelaxation.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/relaxInstruction.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/relaxInstruction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/relaxInstruction.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/requiresDiffExpressionRelocations.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/requiresDiffExpressionRelocations.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/requiresDiffExpressionRelocations.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/setForceRelocs.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/setForceRelocs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/setForceRelocs.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/shouldForceRelocation.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/shouldForceRelocation.cpp new file mode 100644 index 0000000000000000000000000000000000000000..707ad9a7adfa30dd4cdbb7e4406787776f6689a8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/shouldForceRelocation.cpp @@ -0,0 +1,38 @@ +bool MipsAsmBackend::shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target) { + const unsigned FixupKind = Fixup.getKind(); + switch (FixupKind) { + default: + return false; + case Mips::fixup_Mips_CALL_HI16: + case Mips::fixup_Mips_CALL_LO16: + case Mips::fixup_Mips_CALL16: + case Mips::fixup_Mips_GOT: + case Mips::fixup_Mips_GOT_PAGE: + case Mips::fixup_Mips_GOT_OFST: + case Mips::fixup_Mips_GOT_DISP: + case Mips::fixup_Mips_GOT_HI16: + case Mips::fixup_Mips_GOT_LO16: + case Mips::fixup_Mips_GOTTPREL: + case Mips::fixup_Mips_DTPREL_HI: + case Mips::fixup_Mips_DTPREL_LO: + case Mips::fixup_Mips_TLSGD: + case Mips::fixup_Mips_TLSLDM: + case Mips::fixup_Mips_TPREL_HI: + case Mips::fixup_Mips_TPREL_LO: + case Mips::fixup_Mips_JALR: + case Mips::fixup_MICROMIPS_CALL16: + case Mips::fixup_MICROMIPS_GOT_DISP: + case Mips::fixup_MICROMIPS_GOT_PAGE: + case Mips::fixup_MICROMIPS_GOT_OFST: + case Mips::fixup_MICROMIPS_GOT16: + case Mips::fixup_MICROMIPS_GOTTPREL: + case Mips::fixup_MICROMIPS_TLS_DTPREL_HI16: + case Mips::fixup_MICROMIPS_TLS_DTPREL_LO16: + case Mips::fixup_MICROMIPS_TLS_GD: + case Mips::fixup_MICROMIPS_TLS_LDM: + case Mips::fixup_MICROMIPS_TLS_TPREL_HI16: + case Mips::fixup_MICROMIPS_TLS_TPREL_LO16: + case Mips::fixup_MICROMIPS_JALR: + return true; + } +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/shouldInsertExtraNopBytesForCodeAlign.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/shouldInsertExtraNopBytesForCodeAlign.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d24252a436720a3ccdecb69c990fff58341ff97c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/shouldInsertExtraNopBytesForCodeAlign.cpp @@ -0,0 +1,2 @@ +None + diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/shouldInsertFixupForCodeAlign.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/shouldInsertFixupForCodeAlign.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/shouldInsertFixupForCodeAlign.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/willForceRelocations.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/willForceRelocations.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/willForceRelocations.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/writeNopData.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/writeNopData.cpp new file mode 100644 index 0000000000000000000000000000000000000000..624acfd8a76919adf6444d864bc4f6716cb589bc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/writeNopData.cpp @@ -0,0 +1,4 @@ +bool MipsAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const { + OS.write_zeros(Count); + return true; +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/~AsmBackend.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/~AsmBackend.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmBackend/~AsmBackend.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmInfo/MCAsmInfo.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmInfo/MCAsmInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3dbf2eaf5993d301dc8ae0720319683c2860d3d1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmInfo/MCAsmInfo.cpp @@ -0,0 +1,28 @@ +MipsMCAsmInfo::MipsMCAsmInfo(const Triple &TheTriple, const MCTargetOptions &Options) { + IsLittleEndian = TheTriple.isLittleEndian(); + MipsABIInfo ABI = MipsABIInfo::computeTargetABI(TheTriple, "", Options); + if (TheTriple.isMIPS64() && !ABI.IsN32()) + CodePointerSize = CalleeSaveStackSlotSize = 8; + if (ABI.IsO32()) + PrivateGlobalPrefix = "$"; + else if (ABI.IsN32() || ABI.IsN64()) + PrivateGlobalPrefix = ".L"; + PrivateLabelPrefix = PrivateGlobalPrefix; + AlignmentIsInBytes = false; + Data16bitsDirective = "\t.2byte\t"; + Data32bitsDirective = "\t.4byte\t"; + Data64bitsDirective = "\t.8byte\t"; + CommentString = "#"; + ZeroDirective = "\t.space\t"; + GPRel32Directive = "\t.gpword\t"; + GPRel64Directive = "\t.gpdword\t"; + DTPRel32Directive = "\t.dtprelword\t"; + DTPRel64Directive = "\t.dtpreldword\t"; + TPRel32Directive = "\t.tprelword\t"; + TPRel64Directive = "\t.tpreldword\t"; + UseAssignmentForEHBegin = true; + SupportsDebugInformation = true; + ExceptionsType = ExceptionHandling::DwarfCFI; + DwarfRegNumForCFI = true; + HasMipsExpressions = true; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmInfo/anchor.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmInfo/anchor.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6f2b70e5a457a170f552b5d40557e5769efd425f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmInfo/anchor.cpp @@ -0,0 +1,2 @@ +void MipsMCAsmInfo::anchor() { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmInfo/getExprForFDESymbol.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmInfo/getExprForFDESymbol.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/AsmInfo/getExprForFDESymbol.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/BaseInfo/ABI.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/BaseInfo/ABI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/BaseInfo/ABI.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/BaseInfo/FenceField.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/BaseInfo/FenceField.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/BaseInfo/FenceField.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/BaseInfo/II.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/BaseInfo/II.cpp new file mode 100644 index 0000000000000000000000000000000000000000..daadf4bba15edd51d62b76f8a5f2922cd3dfb63b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/BaseInfo/II.cpp @@ -0,0 +1,42 @@ +namespace MipsII { + enum TOF { + MO_NO_FLAG, + MO_GOT, + MO_GOT_CALL, + MO_GPREL, + MO_ABS_HI, + MO_ABS_LO, + MO_TLSGD, + MO_TLSLDM, + MO_DTPREL_HI, + MO_DTPREL_LO, + MO_GOTTPREL, + MO_TPREL_HI, + MO_TPREL_LO, + MO_GPOFF_HI, + MO_GPOFF_LO, + MO_GOT_DISP, + MO_GOT_PAGE, + MO_GOT_OFST, + MO_HIGHER, + MO_HIGHEST, + MO_GOT_HI16, + MO_GOT_LO16, + MO_CALL_HI16, + MO_CALL_LO16, + MO_JALR + }; + enum { + Pseudo = 0, + FrmR = 1, + FrmI = 2, + FrmJ = 3, + FrmFR = 4, + FrmFI = 5, + FrmOther = 6, + FormMask = 15, + IsCTI = 1 << 4, + HasForbiddenSlot = 1 << 5, + HasFCCRegOperand = 1 << 6 + }; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/BaseInfo/OperandType.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/BaseInfo/OperandType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..19db91538f2257839ecb2a14d1c12740760ec25d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/BaseInfo/OperandType.cpp @@ -0,0 +1,5 @@ +enum OperandType : unsigned { + OPERAND_FIRST_MIPS_MEM_IMM = MCOI::OPERAND_FIRST_TARGET, + OPERAND_MEM_SIMM9 = OPERAND_FIRST_MIPS_MEM_IMM, + OPERAND_LAST_MIPS_MEM_IMM = OPERAND_MEM_SIMM9 +}; diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/BaseInfo/RISCVVSEW.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/BaseInfo/RISCVVSEW.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/BaseInfo/RISCVVSEW.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/BaseInfo/RVVConstraintType.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/BaseInfo/RVVConstraintType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/BaseInfo/RVVConstraintType.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/BaseInfo/RoundingMode.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/BaseInfo/RoundingMode.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/BaseInfo/RoundingMode.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/BaseInfo/VLMUL.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/BaseInfo/VLMUL.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/BaseInfo/VLMUL.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/BaseInfo/VMTs.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/BaseInfo/VMTs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/BaseInfo/VMTs.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/BaseInfo/computeTargetABI.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/BaseInfo/computeTargetABI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4d6853920e499f673dd13662b1ce142b45fd480d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/BaseInfo/computeTargetABI.cpp @@ -0,0 +1,14 @@ +MipsABIInfo MipsABIInfo::computeTargetABI(const Triple &TT, StringRef CPU, const MCTargetOptions &Options) { + if (Options.getABIName().startswith("o32")) + return MipsABIInfo::O32(); + if (Options.getABIName().startswith("n32")) + return MipsABIInfo::N32(); + if (Options.getABIName().startswith("n64")) + return MipsABIInfo::N64(); + if (TT.getEnvironment() == llvm::Triple::GNUABIN32) + return MipsABIInfo::N32(); + assert(Options.getABIName().empty() && "Unknown ABI option for MIPS"); + if (TT.isMIPS64()) + return MipsABIInfo::N64(); + return MipsABIInfo::O32(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/BaseInfo/getTargetABI.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/BaseInfo/getTargetABI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/BaseInfo/getTargetABI.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/BaseInfo/roundingModeToString.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/BaseInfo/roundingModeToString.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/BaseInfo/roundingModeToString.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/BaseInfo/stringToRoundingMode.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/BaseInfo/stringToRoundingMode.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/BaseInfo/stringToRoundingMode.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/BaseInfo/validate.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/BaseInfo/validate.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/BaseInfo/validate.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFObjectWriter/ELFObjectWriter.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFObjectWriter/ELFObjectWriter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..88f55f07a55f5d6e27aacf8f610dbab4444a2d20 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFObjectWriter/ELFObjectWriter.cpp @@ -0,0 +1,2 @@ +MipsELFObjectWriter::MipsELFObjectWriter(uint8_t OSABI, bool HasRelocationAddend, bool Is64) : MCELFObjectTargetWriter(Is64, OSABI, ELF::EM_MIPS, HasRelocationAddend) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFObjectWriter/createELFObjectWriter.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFObjectWriter/createELFObjectWriter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..86e17ba3612af05cf31412d2f7693b9925ecc958 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFObjectWriter/createELFObjectWriter.cpp @@ -0,0 +1,6 @@ +std::unique_ptrllvm::createMipsELFObjectWriter(const Triple &TT, bool IsN32) { + uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS()); + bool IsN64 = TT.isArch64Bit() && !IsN32; + bool HasRelocationAddend = TT.isArch64Bit(); + return std::make_unique(OSABI, HasRelocationAddend, IsN64); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFObjectWriter/getRelocType.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFObjectWriter/getRelocType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7d8b4ed83f6a2bbf608dac997f973ba4486b27c3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFObjectWriter/getRelocType.cpp @@ -0,0 +1,160 @@ +unsigned MipsELFObjectWriter::getRelocType(MCContext &Ctx, const MCValue &Target, const MCFixup &Fixup, bool IsPCRel) const { + unsigned Kind = Fixup.getTargetKind(); + switch (Kind) { + case FK_NONE: + return ELF::R_MIPS_NONE; + case FK_Data_1: + Ctx.reportError(Fixup.getLoc(), "MIPS does not support one byte relocations"); + return ELF::R_MIPS_NONE; + case Mips::fixup_Mips_16: + case FK_Data_2: + return IsPCRel ? ELF::R_MIPS_PC16 : ELF::R_MIPS_16; + case Mips::fixup_Mips_32: + case FK_Data_4: + return IsPCRel ? ELF::R_MIPS_PC32 : ELF::R_MIPS_32; + case Mips::fixup_Mips_64: + case FK_Data_8: + return IsPCRel ? setRTypes(ELF::R_MIPS_PC32, ELF::R_MIPS_64, ELF::R_MIPS_NONE) : (unsigned)ELF::R_MIPS_64; + } + if (IsPCRel) { + switch (Kind) { + case Mips::fixup_Mips_Branch_PCRel: + case Mips::fixup_Mips_PC16: + return ELF::R_MIPS_PC16; + case Mips::fixup_MICROMIPS_PC7_S1: + return ELF::R_MICROMIPS_PC7_S1; + case Mips::fixup_MICROMIPS_PC10_S1: + return ELF::R_MICROMIPS_PC10_S1; + case Mips::fixup_MICROMIPS_PC16_S1: + return ELF::R_MICROMIPS_PC16_S1; + case Mips::fixup_MICROMIPS_PC26_S1: + return ELF::R_MICROMIPS_PC26_S1; + case Mips::fixup_MICROMIPS_PC19_S2: + return ELF::R_MICROMIPS_PC19_S2; + case Mips::fixup_MICROMIPS_PC18_S3: + return ELF::R_MICROMIPS_PC18_S3; + case Mips::fixup_MICROMIPS_PC21_S1: + return ELF::R_MICROMIPS_PC21_S1; + case Mips::fixup_MIPS_PC19_S2: + return ELF::R_MIPS_PC19_S2; + case Mips::fixup_MIPS_PC18_S3: + return ELF::R_MIPS_PC18_S3; + case Mips::fixup_MIPS_PC21_S2: + return ELF::R_MIPS_PC21_S2; + case Mips::fixup_MIPS_PC26_S2: + return ELF::R_MIPS_PC26_S2; + case Mips::fixup_MIPS_PCHI16: + return ELF::R_MIPS_PCHI16; + case Mips::fixup_MIPS_PCLO16: + return ELF::R_MIPS_PCLO16; + } + llvm_unreachable("invalid PC-relative fixup kind!"); + } + switch (Kind) { + case FK_DTPRel_4: + return ELF::R_MIPS_TLS_DTPREL32; + case FK_DTPRel_8: + return ELF::R_MIPS_TLS_DTPREL64; + case FK_TPRel_4: + return ELF::R_MIPS_TLS_TPREL32; + case FK_TPRel_8: + return ELF::R_MIPS_TLS_TPREL64; + case FK_GPRel_4: + return setRTypes(ELF::R_MIPS_GPREL32, is64Bit() ? ELF::R_MIPS_64 : ELF::R_MIPS_NONE, ELF::R_MIPS_NONE); + case Mips::fixup_Mips_GPREL16: + return ELF::R_MIPS_GPREL16; + case Mips::fixup_Mips_26: + return ELF::R_MIPS_26; + case Mips::fixup_Mips_CALL16: + return ELF::R_MIPS_CALL16; + case Mips::fixup_Mips_GOT: + return ELF::R_MIPS_GOT16; + case Mips::fixup_Mips_HI16: + return ELF::R_MIPS_HI16; + case Mips::fixup_Mips_LO16: + return ELF::R_MIPS_LO16; + case Mips::fixup_Mips_TLSGD: + return ELF::R_MIPS_TLS_GD; + case Mips::fixup_Mips_GOTTPREL: + return ELF::R_MIPS_TLS_GOTTPREL; + case Mips::fixup_Mips_TPREL_HI: + return ELF::R_MIPS_TLS_TPREL_HI16; + case Mips::fixup_Mips_TPREL_LO: + return ELF::R_MIPS_TLS_TPREL_LO16; + case Mips::fixup_Mips_TLSLDM: + return ELF::R_MIPS_TLS_LDM; + case Mips::fixup_Mips_DTPREL_HI: + return ELF::R_MIPS_TLS_DTPREL_HI16; + case Mips::fixup_Mips_DTPREL_LO: + return ELF::R_MIPS_TLS_DTPREL_LO16; + case Mips::fixup_Mips_GOT_PAGE: + return ELF::R_MIPS_GOT_PAGE; + case Mips::fixup_Mips_GOT_OFST: + return ELF::R_MIPS_GOT_OFST; + case Mips::fixup_Mips_GOT_DISP: + return ELF::R_MIPS_GOT_DISP; + case Mips::fixup_Mips_GPOFF_HI: + return setRTypes(ELF::R_MIPS_GPREL16, ELF::R_MIPS_SUB, ELF::R_MIPS_HI16); + case Mips::fixup_MICROMIPS_GPOFF_HI: + return setRTypes(ELF::R_MICROMIPS_GPREL16, ELF::R_MICROMIPS_SUB, ELF::R_MICROMIPS_HI16); + case Mips::fixup_Mips_GPOFF_LO: + return setRTypes(ELF::R_MIPS_GPREL16, ELF::R_MIPS_SUB, ELF::R_MIPS_LO16); + case Mips::fixup_MICROMIPS_GPOFF_LO: + return setRTypes(ELF::R_MICROMIPS_GPREL16, ELF::R_MICROMIPS_SUB, ELF::R_MICROMIPS_LO16); + case Mips::fixup_Mips_HIGHER: + return ELF::R_MIPS_HIGHER; + case Mips::fixup_Mips_HIGHEST: + return ELF::R_MIPS_HIGHEST; + case Mips::fixup_Mips_SUB: + return ELF::R_MIPS_SUB; + case Mips::fixup_Mips_GOT_HI16: + return ELF::R_MIPS_GOT_HI16; + case Mips::fixup_Mips_GOT_LO16: + return ELF::R_MIPS_GOT_LO16; + case Mips::fixup_Mips_CALL_HI16: + return ELF::R_MIPS_CALL_HI16; + case Mips::fixup_Mips_CALL_LO16: + return ELF::R_MIPS_CALL_LO16; + case Mips::fixup_MICROMIPS_26_S1: + return ELF::R_MICROMIPS_26_S1; + case Mips::fixup_MICROMIPS_HI16: + return ELF::R_MICROMIPS_HI16; + case Mips::fixup_MICROMIPS_LO16: + return ELF::R_MICROMIPS_LO16; + case Mips::fixup_MICROMIPS_GOT16: + return ELF::R_MICROMIPS_GOT16; + case Mips::fixup_MICROMIPS_CALL16: + return ELF::R_MICROMIPS_CALL16; + case Mips::fixup_MICROMIPS_GOT_DISP: + return ELF::R_MICROMIPS_GOT_DISP; + case Mips::fixup_MICROMIPS_GOT_PAGE: + return ELF::R_MICROMIPS_GOT_PAGE; + case Mips::fixup_MICROMIPS_GOT_OFST: + return ELF::R_MICROMIPS_GOT_OFST; + case Mips::fixup_MICROMIPS_TLS_GD: + return ELF::R_MICROMIPS_TLS_GD; + case Mips::fixup_MICROMIPS_TLS_LDM: + return ELF::R_MICROMIPS_TLS_LDM; + case Mips::fixup_MICROMIPS_TLS_DTPREL_HI16: + return ELF::R_MICROMIPS_TLS_DTPREL_HI16; + case Mips::fixup_MICROMIPS_TLS_DTPREL_LO16: + return ELF::R_MICROMIPS_TLS_DTPREL_LO16; + case Mips::fixup_MICROMIPS_GOTTPREL: + return ELF::R_MICROMIPS_TLS_GOTTPREL; + case Mips::fixup_MICROMIPS_TLS_TPREL_HI16: + return ELF::R_MICROMIPS_TLS_TPREL_HI16; + case Mips::fixup_MICROMIPS_TLS_TPREL_LO16: + return ELF::R_MICROMIPS_TLS_TPREL_LO16; + case Mips::fixup_MICROMIPS_SUB: + return ELF::R_MICROMIPS_SUB; + case Mips::fixup_MICROMIPS_HIGHER: + return ELF::R_MICROMIPS_HIGHER; + case Mips::fixup_MICROMIPS_HIGHEST: + return ELF::R_MICROMIPS_HIGHEST; + case Mips::fixup_Mips_JALR: + return ELF::R_MIPS_JALR; + case Mips::fixup_MICROMIPS_JALR: + return ELF::R_MICROMIPS_JALR; + } + llvm_unreachable("invalid fixup kind!"); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFObjectWriter/needsRelocateWithSymbol.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFObjectWriter/needsRelocateWithSymbol.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7f531ea4250537c4a6213a42e7766c1c17828d3f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFObjectWriter/needsRelocateWithSymbol.cpp @@ -0,0 +1,130 @@ +bool MipsELFObjectWriter::needsRelocateWithSymbol(const MCSymbol &Sym, unsigned Type) const { + if (!isUInt<8>(Type)) + return needsRelocateWithSymbol(Sym, Type & 0xff) || needsRelocateWithSymbol(Sym, (Type >> 8) & 0xff) || needsRelocateWithSymbol(Sym, (Type >> 16) & 0xff); + switch (Type) { + default: + errs() << Type << "\n"; + llvm_unreachable("Unexpected relocation"); + return true; + case ELF::R_MIPS_NONE: + return false; + case ELF::R_MIPS_GOT16: + case ELF::R_MIPS16_GOT16: + case ELF::R_MICROMIPS_GOT16: + case ELF::R_MIPS_HIGHER: + case ELF::R_MIPS_HIGHEST: + case ELF::R_MIPS_HI16: + case ELF::R_MIPS16_HI16: + case ELF::R_MICROMIPS_HI16: + case ELF::R_MIPS_LO16: + case ELF::R_MIPS16_LO16: + case ELF::R_MICROMIPS_LO16: + if (cast(Sym).getOther() & ELF::STO_MIPS_MICROMIPS) + return true; + return false; + case ELF::R_MIPS_GOT_PAGE: + case ELF::R_MICROMIPS_GOT_PAGE: + case ELF::R_MIPS_GOT_OFST: + case ELF::R_MICROMIPS_GOT_OFST: + case ELF::R_MIPS_16: + case ELF::R_MIPS_32: + case ELF::R_MIPS_GPREL32: + if (cast(Sym).getOther() & ELF::STO_MIPS_MICROMIPS) + return true; + LLVM_FALLTHROUGH; + case ELF::R_MIPS_26: + case ELF::R_MIPS_64: + case ELF::R_MIPS_GPREL16: + case ELF::R_MIPS_PC16: + case ELF::R_MIPS_SUB: + return false; + case ELF::R_MIPS_REL32: + case ELF::R_MIPS_LITERAL: + case ELF::R_MIPS_CALL16: + case ELF::R_MIPS_SHIFT5: + case ELF::R_MIPS_SHIFT6: + case ELF::R_MIPS_GOT_DISP: + case ELF::R_MIPS_GOT_HI16: + case ELF::R_MIPS_GOT_LO16: + case ELF::R_MIPS_INSERT_A: + case ELF::R_MIPS_INSERT_B: + case ELF::R_MIPS_DELETE: + case ELF::R_MIPS_CALL_HI16: + case ELF::R_MIPS_CALL_LO16: + case ELF::R_MIPS_SCN_DISP: + case ELF::R_MIPS_REL16: + case ELF::R_MIPS_ADD_IMMEDIATE: + case ELF::R_MIPS_PJUMP: + case ELF::R_MIPS_RELGOT: + case ELF::R_MIPS_JALR: + case ELF::R_MIPS_TLS_DTPMOD32: + case ELF::R_MIPS_TLS_DTPREL32: + case ELF::R_MIPS_TLS_DTPMOD64: + case ELF::R_MIPS_TLS_DTPREL64: + case ELF::R_MIPS_TLS_GD: + case ELF::R_MIPS_TLS_LDM: + case ELF::R_MIPS_TLS_DTPREL_HI16: + case ELF::R_MIPS_TLS_DTPREL_LO16: + case ELF::R_MIPS_TLS_GOTTPREL: + case ELF::R_MIPS_TLS_TPREL32: + case ELF::R_MIPS_TLS_TPREL64: + case ELF::R_MIPS_TLS_TPREL_HI16: + case ELF::R_MIPS_TLS_TPREL_LO16: + case ELF::R_MIPS_GLOB_DAT: + case ELF::R_MIPS_PC21_S2: + case ELF::R_MIPS_PC26_S2: + case ELF::R_MIPS_PC18_S3: + case ELF::R_MIPS_PC19_S2: + case ELF::R_MIPS_PCHI16: + case ELF::R_MIPS_PCLO16: + case ELF::R_MIPS_COPY: + case ELF::R_MIPS_JUMP_SLOT: + case ELF::R_MIPS_NUM: + case ELF::R_MIPS_PC32: + case ELF::R_MIPS_EH: + case ELF::R_MICROMIPS_26_S1: + case ELF::R_MICROMIPS_GPREL16: + case ELF::R_MICROMIPS_LITERAL: + case ELF::R_MICROMIPS_PC7_S1: + case ELF::R_MICROMIPS_PC10_S1: + case ELF::R_MICROMIPS_PC16_S1: + case ELF::R_MICROMIPS_CALL16: + case ELF::R_MICROMIPS_GOT_DISP: + case ELF::R_MICROMIPS_GOT_HI16: + case ELF::R_MICROMIPS_GOT_LO16: + case ELF::R_MICROMIPS_SUB: + case ELF::R_MICROMIPS_HIGHER: + case ELF::R_MICROMIPS_HIGHEST: + case ELF::R_MICROMIPS_CALL_HI16: + case ELF::R_MICROMIPS_CALL_LO16: + case ELF::R_MICROMIPS_SCN_DISP: + case ELF::R_MICROMIPS_JALR: + case ELF::R_MICROMIPS_HI0_LO16: + case ELF::R_MICROMIPS_TLS_GD: + case ELF::R_MICROMIPS_TLS_LDM: + case ELF::R_MICROMIPS_TLS_DTPREL_HI16: + case ELF::R_MICROMIPS_TLS_DTPREL_LO16: + case ELF::R_MICROMIPS_TLS_GOTTPREL: + case ELF::R_MICROMIPS_TLS_TPREL_HI16: + case ELF::R_MICROMIPS_TLS_TPREL_LO16: + case ELF::R_MICROMIPS_GPREL7_S2: + case ELF::R_MICROMIPS_PC23_S2: + case ELF::R_MICROMIPS_PC21_S1: + case ELF::R_MICROMIPS_PC26_S1: + case ELF::R_MICROMIPS_PC18_S3: + case ELF::R_MICROMIPS_PC19_S2: + return true; + case ELF::R_MIPS16_26: + case ELF::R_MIPS16_GPREL: + case ELF::R_MIPS16_CALL16: + case ELF::R_MIPS16_TLS_GD: + case ELF::R_MIPS16_TLS_LDM: + case ELF::R_MIPS16_TLS_DTPREL_HI16: + case ELF::R_MIPS16_TLS_DTPREL_LO16: + case ELF::R_MIPS16_TLS_GOTTPREL: + case ELF::R_MIPS16_TLS_TPREL_HI16: + case ELF::R_MIPS16_TLS_TPREL_LO16: + llvm_unreachable("Unsupported MIPS16 relocation"); + return true; + } +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFObjectWriter/~ELFObjectWriter.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFObjectWriter/~ELFObjectWriter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFObjectWriter/~ELFObjectWriter.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/AttributeItem.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/AttributeItem.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/AttributeItem.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/AttributeType.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/AttributeType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/AttributeType.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/TargetELFStreamer.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/TargetELFStreamer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8dba92c27146b58cdb0e204902db70262196e9b1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/TargetELFStreamer.cpp @@ -0,0 +1,34 @@ +MipsTargetELFStreamer::MipsTargetELFStreamer(MCStreamer &S, const MCSubtargetInfo &STI) : MipsTargetStreamer(S), MicroMipsEnabled(false), STI(STI) { + MCAssembler &MCA = getStreamer().getAssembler(); + Pic = MCA.getContext().getObjectFileInfo()->isPositionIndependent(); + const FeatureBitset &Features = STI.getFeatureBits(); + unsigned EFlags = MCA.getELFHeaderEFlags(); + ABI = MipsABIInfo(STI.getTargetTriple().getArch() == Triple::ArchType::mipsel || STI.getTargetTriple().getArch() == Triple::ArchType::mips ? MipsABIInfo::O32() : MipsABIInfo::N64()); + if (Features[Mips::FeatureMips64r6]) + EFlags |= ELF::EF_MIPS_ARCH_64R6; + else if (Features[Mips::FeatureMips64r2] || Features[Mips::FeatureMips64r3] || Features[Mips::FeatureMips64r5]) + EFlags |= ELF::EF_MIPS_ARCH_64R2; + else if (Features[Mips::FeatureMips64]) + EFlags |= ELF::EF_MIPS_ARCH_64; + else if (Features[Mips::FeatureMips5]) + EFlags |= ELF::EF_MIPS_ARCH_5; + else if (Features[Mips::FeatureMips4]) + EFlags |= ELF::EF_MIPS_ARCH_4; + else if (Features[Mips::FeatureMips3]) + EFlags |= ELF::EF_MIPS_ARCH_3; + else if (Features[Mips::FeatureMips32r6]) + EFlags |= ELF::EF_MIPS_ARCH_32R6; + else if (Features[Mips::FeatureMips32r2] || Features[Mips::FeatureMips32r3] || Features[Mips::FeatureMips32r5]) + EFlags |= ELF::EF_MIPS_ARCH_32R2; + else if (Features[Mips::FeatureMips32]) + EFlags |= ELF::EF_MIPS_ARCH_32; + else if (Features[Mips::FeatureMips2]) + EFlags |= ELF::EF_MIPS_ARCH_2; + else + EFlags |= ELF::EF_MIPS_ARCH_1; + if (Features[Mips::FeatureCnMips]) + EFlags |= ELF::EF_MIPS_MACH_OCTEON; + if (Features[Mips::FeatureNaN2008]) + EFlags |= ELF::EF_MIPS_NAN2008; + MCA.setELFHeaderEFlags(EFlags); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/calculateContentSize.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/calculateContentSize.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/calculateContentSize.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/emitAttribute.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/emitAttribute.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/emitAttribute.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionNoPIC.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionNoPIC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4e5832effab9cb77d0b82db906e766fed26e295c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionNoPIC.cpp @@ -0,0 +1,2 @@ +void MipsTargetStreamer::emitDirectiveSetMicroMips() { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionNoRVC.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionNoRVC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4e5832effab9cb77d0b82db906e766fed26e295c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionNoRVC.cpp @@ -0,0 +1,2 @@ +void MipsTargetStreamer::emitDirectiveSetMicroMips() { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionNoRelax.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionNoRelax.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4e5832effab9cb77d0b82db906e766fed26e295c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionNoRelax.cpp @@ -0,0 +1,2 @@ +void MipsTargetStreamer::emitDirectiveSetMicroMips() { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionPIC.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionPIC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4e5832effab9cb77d0b82db906e766fed26e295c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionPIC.cpp @@ -0,0 +1,2 @@ +void MipsTargetStreamer::emitDirectiveSetMicroMips() { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionPop.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionPop.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4e5832effab9cb77d0b82db906e766fed26e295c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionPop.cpp @@ -0,0 +1,2 @@ +void MipsTargetStreamer::emitDirectiveSetMicroMips() { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionPush.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionPush.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4e5832effab9cb77d0b82db906e766fed26e295c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionPush.cpp @@ -0,0 +1,2 @@ +void MipsTargetStreamer::emitDirectiveSetMicroMips() { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionRVC.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionRVC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4e5832effab9cb77d0b82db906e766fed26e295c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionRVC.cpp @@ -0,0 +1,2 @@ +void MipsTargetStreamer::emitDirectiveSetMicroMips() { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionRelax.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionRelax.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4e5832effab9cb77d0b82db906e766fed26e295c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionRelax.cpp @@ -0,0 +1,2 @@ +void MipsTargetStreamer::emitDirectiveSetMicroMips() { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/emitIntTextAttribute.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/emitIntTextAttribute.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4e5832effab9cb77d0b82db906e766fed26e295c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/emitIntTextAttribute.cpp @@ -0,0 +1,2 @@ +void MipsTargetStreamer::emitDirectiveSetMicroMips() { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/emitTextAttribute.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/emitTextAttribute.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4e5832effab9cb77d0b82db906e766fed26e295c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/emitTextAttribute.cpp @@ -0,0 +1,2 @@ +void MipsTargetStreamer::emitDirectiveSetMicroMips() { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/finishAttributeSection.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/finishAttributeSection.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/finishAttributeSection.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/getAttributeItem.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/getAttributeItem.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/getAttributeItem.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/getStreamer.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/getStreamer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..169a904a234aa96ead39b9536240237025564fdf --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/getStreamer.cpp @@ -0,0 +1,3 @@ +MCELFStreamer &MipsTargetELFStreamer::getStreamer() { + return static_cast(Streamer); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/setAttributeItem1.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/setAttributeItem1.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/setAttributeItem1.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/setAttributeItem2.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/setAttributeItem2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/setAttributeItem2.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/setAttributeItems.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/setAttributeItems.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/ELFStreamer/setAttributeItems.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/FixupKind/enumFixups.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/FixupKind/enumFixups.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d35d8d0bcb890e7cd11ff4ce19ee49ce8fd56641 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/FixupKind/enumFixups.cpp @@ -0,0 +1,74 @@ +enum Fixups { + fixup_Mips_16 = FirstTargetFixupKind, + fixup_Mips_32, + fixup_Mips_REL32, + fixup_Mips_26, + fixup_Mips_HI16, + fixup_Mips_LO16, + fixup_Mips_GPREL16, + fixup_Mips_LITERAL, + fixup_Mips_GOT, + fixup_Mips_PC16, + fixup_Mips_CALL16, + fixup_Mips_GPREL32, + fixup_Mips_SHIFT5, + fixup_Mips_SHIFT6, + fixup_Mips_64, + fixup_Mips_TLSGD, + fixup_Mips_GOTTPREL, + fixup_Mips_TPREL_HI, + fixup_Mips_TPREL_LO, + fixup_Mips_TLSLDM, + fixup_Mips_DTPREL_HI, + fixup_Mips_DTPREL_LO, + fixup_Mips_Branch_PCRel, + fixup_Mips_GPOFF_HI, + fixup_MICROMIPS_GPOFF_HI, + fixup_Mips_GPOFF_LO, + fixup_MICROMIPS_GPOFF_LO, + fixup_Mips_GOT_PAGE, + fixup_Mips_GOT_OFST, + fixup_Mips_GOT_DISP, + fixup_Mips_HIGHER, + fixup_MICROMIPS_HIGHER, + fixup_Mips_HIGHEST, + fixup_MICROMIPS_HIGHEST, + fixup_Mips_GOT_HI16, + fixup_Mips_GOT_LO16, + fixup_Mips_CALL_HI16, + fixup_Mips_CALL_LO16, + fixup_MIPS_PC18_S3, + fixup_MIPS_PC19_S2, + fixup_MIPS_PC21_S2, + fixup_MIPS_PC26_S2, + fixup_MIPS_PCHI16, + fixup_MIPS_PCLO16, + fixup_MICROMIPS_26_S1, + fixup_MICROMIPS_HI16, + fixup_MICROMIPS_LO16, + fixup_MICROMIPS_GOT16, + fixup_MICROMIPS_PC7_S1, + fixup_MICROMIPS_PC10_S1, + fixup_MICROMIPS_PC16_S1, + fixup_MICROMIPS_PC26_S1, + fixup_MICROMIPS_PC19_S2, + fixup_MICROMIPS_PC18_S3, + fixup_MICROMIPS_PC21_S1, + fixup_MICROMIPS_CALL16, + fixup_MICROMIPS_GOT_DISP, + fixup_MICROMIPS_GOT_PAGE, + fixup_MICROMIPS_GOT_OFST, + fixup_MICROMIPS_TLS_GD, + fixup_MICROMIPS_TLS_LDM, + fixup_MICROMIPS_TLS_DTPREL_HI16, + fixup_MICROMIPS_TLS_DTPREL_LO16, + fixup_MICROMIPS_GOTTPREL, + fixup_MICROMIPS_TLS_TPREL_HI16, + fixup_MICROMIPS_TLS_TPREL_LO16, + fixup_Mips_SUB, + fixup_MICROMIPS_SUB, + fixup_Mips_JALR, + fixup_MICROMIPS_JALR, + LastTargetFixupKind, + NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind + }; \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/InstPrinter/InstPrinter.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/InstPrinter/InstPrinter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8c883a428f10b83a397704285295212b9d6aa78f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/InstPrinter/InstPrinter.cpp @@ -0,0 +1,2 @@ +MipsInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI) : MCInstPrinter(MAI, MII, MRI) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/InstPrinter/applyTargetSpecificCLOption.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/InstPrinter/applyTargetSpecificCLOption.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/InstPrinter/applyTargetSpecificCLOption.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/InstPrinter/getRegisterName.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/InstPrinter/getRegisterName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/InstPrinter/getRegisterName.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/InstPrinter/printAtomicMemOp.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/InstPrinter/printAtomicMemOp.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f6febf95d372d6ef3759047b96191a4f8d15d48d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/InstPrinter/printAtomicMemOp.cpp @@ -0,0 +1,4 @@ +void MipsInstPrinter::printFCCOperand(const MCInst *MI, int opNum, raw_ostream &O) { + const MCOperand& MO = MI->getOperand(opNum); + O << MipsFCCToString((Mips::CondCode)MO.getImm()); +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/InstPrinter/printBranchOperand.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/InstPrinter/printBranchOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8c2e2fe2d155616e4b721b21af96e900ec321a28 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/InstPrinter/printBranchOperand.cpp @@ -0,0 +1,5 @@ +void MipsInstPrinter::printFCCOperand(const MCInst *MI, int opNum, raw_ostream &O) { + const MCOperand& MO = MI->getOperand(opNum); + O << MipsFCCToString((Mips::CondCode)MO.getImm()); +} + diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/InstPrinter/printCSRSystemRegister.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/InstPrinter/printCSRSystemRegister.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9f7f9d577eb80771550e1b6a37ed0e03a59a19c3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/InstPrinter/printCSRSystemRegister.cpp @@ -0,0 +1,4 @@ +void MipsInstPrinter::printFCCOperand(const MCInst *MI, int opNum, raw_ostream &O) { + const MCOperand& MO = MI->getOperand(opNum); + O << MipsFCCToString((Mips::CondCode)MO.getImm()); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/InstPrinter/printFRMArg.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/InstPrinter/printFRMArg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9f7f9d577eb80771550e1b6a37ed0e03a59a19c3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/InstPrinter/printFRMArg.cpp @@ -0,0 +1,4 @@ +void MipsInstPrinter::printFCCOperand(const MCInst *MI, int opNum, raw_ostream &O) { + const MCOperand& MO = MI->getOperand(opNum); + O << MipsFCCToString((Mips::CondCode)MO.getImm()); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/InstPrinter/printFenceArg.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/InstPrinter/printFenceArg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9f7f9d577eb80771550e1b6a37ed0e03a59a19c3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/InstPrinter/printFenceArg.cpp @@ -0,0 +1,4 @@ +void MipsInstPrinter::printFCCOperand(const MCInst *MI, int opNum, raw_ostream &O) { + const MCOperand& MO = MI->getOperand(opNum); + O << MipsFCCToString((Mips::CondCode)MO.getImm()); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/InstPrinter/printInst.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/InstPrinter/printInst.cpp new file mode 100644 index 0000000000000000000000000000000000000000..70f5f37e80cc471496d5af941591d8998271fd72 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/InstPrinter/printInst.cpp @@ -0,0 +1,41 @@ +void MipsInstPrinter::printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) { + switch (MI->getOpcode()) { + default: + break; + case Mips::RDHWR: + case Mips::RDHWR64: + O << "\t.set\tpush\n"; + O << "\t.set\tmips32r2\n"; + break; + case Mips::Save16: + O << "\tsave\t"; + printSaveRestore(MI, O); + O << " # 16 bit inst\n"; + return; + case Mips::SaveX16: + O << "\tsave\t"; + printSaveRestore(MI, O); + O << "\n"; + return; + case Mips::Restore16: + O << "\trestore\t"; + printSaveRestore(MI, O); + O << " # 16 bit inst\n"; + return; + case Mips::RestoreX16: + O << "\trestore\t"; + printSaveRestore(MI, O); + O << "\n"; + return; + } + if (!printAliasInstr(MI, Address, O) && !printAlias(*MI, O)) + printInstruction(MI, Address, O); + printAnnotation(O, Annot); + switch (MI->getOpcode()) { + default: + break; + case Mips::RDHWR: + case Mips::RDHWR64: + O << "\n\t.set\tpop"; + } +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/InstPrinter/printOperand.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/InstPrinter/printOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ca8f19bc8f4f6fc50ae215ec71e28772be6a4589 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/InstPrinter/printOperand.cpp @@ -0,0 +1,13 @@ +void MipsInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) { + const MCOperand &Op = MI->getOperand(OpNo); + if (Op.isReg()) { + printRegName(O, Op.getReg()); + return; + } + if (Op.isImm()) { + O << formatImm(Op.getImm()); + return; + } + assert(Op.isExpr() && "unknown operand kind in printOperand"); + Op.getExpr()->print(O, &MAI, true); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/InstPrinter/printRegName.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/InstPrinter/printRegName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..26b28de5ee26164ed0644e6397f6fe42a83f0610 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/InstPrinter/printRegName.cpp @@ -0,0 +1,3 @@ +void MipsInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { + OS << '$' << StringRef(getRegisterName(RegNo)).lower(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/InstPrinter/printVMaskReg.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/InstPrinter/printVMaskReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9f7f9d577eb80771550e1b6a37ed0e03a59a19c3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/InstPrinter/printVMaskReg.cpp @@ -0,0 +1,4 @@ +void MipsInstPrinter::printFCCOperand(const MCInst *MI, int opNum, raw_ostream &O) { + const MCOperand& MO = MI->getOperand(opNum); + O << MipsFCCToString((Mips::CondCode)MO.getImm()); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/InstPrinter/printVTypeI.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/InstPrinter/printVTypeI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9f7f9d577eb80771550e1b6a37ed0e03a59a19c3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/InstPrinter/printVTypeI.cpp @@ -0,0 +1,4 @@ +void MipsInstPrinter::printFCCOperand(const MCInst *MI, int opNum, raw_ostream &O) { + const MCOperand& MO = MI->getOperand(opNum); + O << MipsFCCToString((Mips::CondCode)MO.getImm()); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCCodeEmitter/MCCodeEmitter.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCCodeEmitter/MCCodeEmitter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d80f585e9e89d79aa6714d871030005b94ba0ecc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCCodeEmitter/MCCodeEmitter.cpp @@ -0,0 +1,2 @@ +MipsMCCodeEmitter(const MCInstrInfo &mcii, MCContext &Ctx_, bool IsLittle) : MCII(mcii), Ctx(Ctx_), IsLittleEndian(IsLittle) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCCodeEmitter/createMCCodeEmitter.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCCodeEmitter/createMCCodeEmitter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..372156d0e033b36f8cdce99d9225b6cc7cd64e00 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCCodeEmitter/createMCCodeEmitter.cpp @@ -0,0 +1,3 @@ +MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx) { + return new MipsMCCodeEmitter(MCII, Ctx, true); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCCodeEmitter/encodeInstruction.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCCodeEmitter/encodeInstruction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..59427e05cfb3b9c5884cb26981fdac565f23caa6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCCodeEmitter/encodeInstruction.cpp @@ -0,0 +1,52 @@ +void MipsMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const { + MCInst TmpInst = MI; + switch (MI.getOpcode()) { + case Mips::DSLL: + case Mips::DSRL: + case Mips::DSRA: + case Mips::DROTR: + LowerLargeShift(TmpInst); + break; + case Mips::BEQC: + case Mips::BNEC: + case Mips::BEQC64: + case Mips::BNEC64: + case Mips::BOVC: + case Mips::BOVC_MMR6: + case Mips::BNVC: + case Mips::BNVC_MMR6: + LowerCompactBranch(TmpInst); + } + unsigned long N = Fixups.size(); + uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); + const unsigned Opcode = TmpInst.getOpcode(); + if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) && (Opcode != Mips::SLL_MM) && (Opcode != Mips::SLL_MMR6) && !Binary) + llvm_unreachable("unimplemented opcode in encodeInstruction()"); + int NewOpcode = -1; + if (isMicroMips(STI)) { + if (isMips32r6(STI)) { + NewOpcode = Mips::MipsR62MicroMipsR6(Opcode, Mips::Arch_micromipsr6); + if (NewOpcode == -1) + NewOpcode = Mips::Std2MicroMipsR6(Opcode, Mips::Arch_micromipsr6); + } + else + NewOpcode = Mips::Std2MicroMips(Opcode, Mips::Arch_micromips); + if (NewOpcode == -1) + NewOpcode = Mips::Dsp2MicroMips(Opcode, Mips::Arch_mmdsp); + if (NewOpcode != -1) { + if (Fixups.size() > N) + Fixups.pop_back(); + TmpInst.setOpcode (NewOpcode); + Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); + } + if (((MI.getOpcode() == Mips::MOVEP_MM) || (MI.getOpcode() == Mips::MOVEP_MMR6))) { + unsigned RegPair = getMovePRegPairOpValue(MI, 0, Fixups, STI); + Binary = (Binary & 0xFFFFFC7F) | (RegPair << 7); + } + } + const MCInstrDesc &Desc = MCII.get(TmpInst.getOpcode()); + unsigned Size = Desc.getSize(); + if (!Size) + llvm_unreachable("Desc.getSize() returns 0"); + emitInstruction(Binary, Size, STI, OS); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCCodeEmitter/getImmOpValue.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCCodeEmitter/getImmOpValue.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCCodeEmitter/getImmOpValue.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCCodeEmitter/getImmOpValueAsr1.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCCodeEmitter/getImmOpValueAsr1.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCCodeEmitter/getImmOpValueAsr1.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCCodeEmitter/getMachineOpValue.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCCodeEmitter/getMachineOpValue.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cb189232a33043c90a46e56fd801fda68c47150e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCCodeEmitter/getMachineOpValue.cpp @@ -0,0 +1,15 @@ +unsigned MipsMCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const { + if (MO.isReg()) { + unsigned Reg = MO.getReg(); + unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg); + return RegNo; + } + else if (MO.isImm()) { + return static_cast(MO.getImm()); + } + else if (MO.isFPImm()) { + return static_cast(APFloat(MO.getFPImm()).bitcastToAPInt().getHiBits(32).getLimitedValue()); + } + assert(MO.isExpr()); + return getExprOpValue(MO.getExpr(),Fixups, STI); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCCodeEmitter/getVMaskReg.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCCodeEmitter/getVMaskReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCCodeEmitter/getVMaskReg.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCCodeEmitter/~MCCodeEmitter.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCCodeEmitter/~MCCodeEmitter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCCodeEmitter/~MCCodeEmitter.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCExpr/MCExpr.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCExpr/MCExpr.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ebc24eb5d0635cf958da238e89ee965268122ac9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCExpr/MCExpr.cpp @@ -0,0 +1,2 @@ +explicit MipsMCExpr(MipsExprKind Kind, const MCExpr *Expr) : Kind(Kind), Expr(Expr) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCExpr/classof1.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCExpr/classof1.cpp new file mode 100644 index 0000000000000000000000000000000000000000..18efd6eb03d8a873e79039e5a7191354ce092d82 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCExpr/classof1.cpp @@ -0,0 +1,3 @@ +static bool classof(const MCExpr *E) { + return E->getKind() == MCExpr::Target; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCExpr/classof2.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCExpr/classof2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..18efd6eb03d8a873e79039e5a7191354ce092d82 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCExpr/classof2.cpp @@ -0,0 +1,3 @@ +static bool classof(const MCExpr *E) { + return E->getKind() == MCExpr::Target; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCExpr/create.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCExpr/create.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3094fed7f989b1117507901af1e6037af93072b9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCExpr/create.cpp @@ -0,0 +1,3 @@ +const MipsMCExpr *MipsMCExpr::create(MipsMCExpr::MipsExprKind Kind, const MCExpr *Expr, MCContext &Ctx) { + return new (Ctx) MipsMCExpr(Kind, Expr); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCExpr/enumVariantKind.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCExpr/enumVariantKind.cpp new file mode 100644 index 0000000000000000000000000000000000000000..27c457d66a9d950c263ecd8db1e0cc53834ab166 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCExpr/enumVariantKind.cpp @@ -0,0 +1,29 @@ +enum MipsExprKind { + MEK_None, + MEK_CALL_HI16, + MEK_CALL_LO16, + MEK_DTPREL, + MEK_DTPREL_HI, + MEK_DTPREL_LO, + MEK_GOT, + MEK_GOTTPREL, + MEK_GOT_CALL, + MEK_GOT_DISP, + MEK_GOT_HI16, + MEK_GOT_LO16, + MEK_GOT_OFST, + MEK_GOT_PAGE, + MEK_GPREL, + MEK_HI, + MEK_HIGHER, + MEK_HIGHEST, + MEK_LO, + MEK_NEG, + MEK_PCREL_HI16, + MEK_PCREL_LO16, + MEK_TLSGD, + MEK_TLSLDM, + MEK_TPREL_HI, + MEK_TPREL_LO, + MEK_Special, +}; \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCExpr/evaluateAsConstant.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCExpr/evaluateAsConstant.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCExpr/evaluateAsConstant.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCExpr/evaluateAsInt64.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCExpr/evaluateAsInt64.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCExpr/evaluateAsInt64.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCExpr/evaluateAsRelocatableImpl.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCExpr/evaluateAsRelocatableImpl.cpp new file mode 100644 index 0000000000000000000000000000000000000000..670c710ada9b1fb33725c09e83b7683e32a4776f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCExpr/evaluateAsRelocatableImpl.cpp @@ -0,0 +1,62 @@ +bool MipsMCExpr::evaluateAsRelocatableImpl(MCValue &Res, const MCAsmLayout *Layout, const MCFixup *Fixup) const { + if (isGpOff()) { + const MCExpr *SubExpr = cast(cast(getSubExpr())->getSubExpr())->getSubExpr(); + if (!SubExpr->evaluateAsRelocatable(Res, Layout, Fixup)) + return false; + Res = MCValue::get(Res.getSymA(), Res.getSymB(), Res.getConstant(), MEK_Special); + return true; + } + if (!getSubExpr()->evaluateAsRelocatable(Res, Layout, Fixup)) + return false; + if (Res.getRefKind() != MCSymbolRefExpr::VK_None) + return false; + if (Res.isAbsolute() && Fixup == nullptr) { + int64_t AbsVal = Res.getConstant(); + switch (Kind) { + case MEK_None: + case MEK_Special: + llvm_unreachable("MEK_None and MEK_Special are invalid"); + case MEK_DTPREL: + return getSubExpr()->evaluateAsRelocatable(Res, Layout, Fixup); + case MEK_DTPREL_HI: + case MEK_DTPREL_LO: + case MEK_GOT: + case MEK_GOTTPREL: + case MEK_GOT_CALL: + case MEK_GOT_DISP: + case MEK_GOT_HI16: + case MEK_GOT_LO16: + case MEK_GOT_OFST: + case MEK_GOT_PAGE: + case MEK_GPREL: + case MEK_PCREL_HI16: + case MEK_PCREL_LO16: + case MEK_TLSGD: + case MEK_TLSLDM: + case MEK_TPREL_HI: + case MEK_TPREL_LO: + return false; + case MEK_LO: + case MEK_CALL_LO16: + AbsVal = SignExtend64<16>(AbsVal); + break; + case MEK_CALL_HI16: + case MEK_HI: + AbsVal = SignExtend64<16>((AbsVal + 0x8000) >> 16); + break; + case MEK_HIGHER: + AbsVal = SignExtend64<16>((AbsVal + 0x80008000LL) >> 32); + break; + case MEK_HIGHEST: + AbsVal = SignExtend64<16>((AbsVal + 0x800080008000LL) >> 48); + break; + case MEK_NEG: + AbsVal = -AbsVal; + break; + } + Res = MCValue::get(AbsVal); + return true; + } + Res = MCValue::get(Res.getSymA(), Res.getSymB(), Res.getConstant(), getKind()); + return true; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCExpr/findAssociatedFragment.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCExpr/findAssociatedFragment.cpp new file mode 100644 index 0000000000000000000000000000000000000000..08da2eccf295202e12e9442a7e9eb5f68e318ec8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCExpr/findAssociatedFragment.cpp @@ -0,0 +1,3 @@ +MCFragment *findAssociatedFragment() const override { + return getSubExpr()->findAssociatedFragment(); + } \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCExpr/fixELFSymbolsInTLSFixups.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCExpr/fixELFSymbolsInTLSFixups.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cc1b15aad7b4dd5503f3f01be4930b6d0030989f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCExpr/fixELFSymbolsInTLSFixups.cpp @@ -0,0 +1,38 @@ +void MipsMCExpr::fixELFSymbolsInTLSFixups(MCAssembler &Asm) const { + switch (getKind()) { + case MEK_None: + case MEK_Special: + llvm_unreachable("MEK_None and MEK_Special are invalid"); + break; + case MEK_CALL_HI16: + case MEK_CALL_LO16: + case MEK_GOT: + case MEK_GOT_CALL: + case MEK_GOT_DISP: + case MEK_GOT_HI16: + case MEK_GOT_LO16: + case MEK_GOT_OFST: + case MEK_GOT_PAGE: + case MEK_GPREL: + case MEK_HI: + case MEK_HIGHER: + case MEK_HIGHEST: + case MEK_LO: + case MEK_NEG: + case MEK_PCREL_HI16: + case MEK_PCREL_LO16: + if (const MipsMCExpr *E = dyn_cast(getSubExpr())) + E->fixELFSymbolsInTLSFixups(Asm); + break; + case MEK_DTPREL: + case MEK_DTPREL_HI: + case MEK_DTPREL_LO: + case MEK_TLSLDM: + case MEK_TLSGD: + case MEK_GOTTPREL: + case MEK_TPREL_HI: + case MEK_TPREL_LO: + fixELFSymbolsInTLSFixupsImpl(getSubExpr(), Asm); + break; + } +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCExpr/fixELFSymbolsInTLSFixupsImpl.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCExpr/fixELFSymbolsInTLSFixupsImpl.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2e9ca0c40060014e6baba99f4f067c0ffd884676 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCExpr/fixELFSymbolsInTLSFixupsImpl.cpp @@ -0,0 +1,23 @@ +static void fixELFSymbolsInTLSFixupsImpl(const MCExpr *Expr, MCAssembler &Asm) { + switch (Expr->getKind()) { + case MCExpr::Target: + fixELFSymbolsInTLSFixupsImpl(cast(Expr)->getSubExpr(), Asm); + break; + case MCExpr::Constant: + break; + case MCExpr::Binary: { + const MCBinaryExpr *BE = cast(Expr); + fixELFSymbolsInTLSFixupsImpl(BE->getLHS(), Asm); + fixELFSymbolsInTLSFixupsImpl(BE->getRHS(), Asm); + break; + } + case MCExpr::SymbolRef: { + const MCSymbolRefExpr &SymRef = *cast(Expr); + cast(SymRef.getSymbol()).setType(ELF::STT_TLS); + break; + } + case MCExpr::Unary: + fixELFSymbolsInTLSFixupsImpl(cast(Expr)->getSubExpr(), Asm); + break; + } +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCExpr/getKind.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCExpr/getKind.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1fca267923e392a3304df0e777f53b17ec30c814 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCExpr/getKind.cpp @@ -0,0 +1,3 @@ +MipsExprKind getKind() const { + return Kind; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCExpr/getPCRelHiFixup.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCExpr/getPCRelHiFixup.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCExpr/getPCRelHiFixup.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCExpr/getSubExpr.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCExpr/getSubExpr.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c70598c07f1d0625d598037483c5a146ef4feaa5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCExpr/getSubExpr.cpp @@ -0,0 +1,3 @@ +const MCExpr *getSubExpr() const { + return Expr; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCExpr/getVariantKindForName.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCExpr/getVariantKindForName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCExpr/getVariantKindForName.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCExpr/getVariantKindName.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCExpr/getVariantKindName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCExpr/getVariantKindName.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCExpr/printImpl.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCExpr/printImpl.cpp new file mode 100644 index 0000000000000000000000000000000000000000..47538cb3613642553049ed964b24bf4d4b25031d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCExpr/printImpl.cpp @@ -0,0 +1,90 @@ +void MipsMCExpr::printImpl(raw_ostream &OS, const MCAsmInfo *MAI) const { + int64_t AbsVal; + switch (Kind) { + case MEK_None: + case MEK_Special: + llvm_unreachable("MEK_None and MEK_Special are invalid"); + break; + case MEK_DTPREL: + getSubExpr()->print(OS, MAI, true); + return; + case MEK_CALL_HI16: + OS << "%call_hi"; + break; + case MEK_CALL_LO16: + OS << "%call_lo"; + break; + case MEK_DTPREL_HI: + OS << "%dtprel_hi"; + break; + case MEK_DTPREL_LO: + OS << "%dtprel_lo"; + break; + case MEK_GOT: + OS << "%got"; + break; + case MEK_GOTTPREL: + OS << "%gottprel"; + break; + case MEK_GOT_CALL: + OS << "%call16"; + break; + case MEK_GOT_DISP: + OS << "%got_disp"; + break; + case MEK_GOT_HI16: + OS << "%got_hi"; + break; + case MEK_GOT_LO16: + OS << "%got_lo"; + break; + case MEK_GOT_PAGE: + OS << "%got_page"; + break; + case MEK_GOT_OFST: + OS << "%got_ofst"; + break; + case MEK_GPREL: + OS << "%gp_rel"; + break; + case MEK_HI: + OS << "%hi"; + break; + case MEK_HIGHER: + OS << "%higher"; + break; + case MEK_HIGHEST: + OS << "%highest"; + break; + case MEK_LO: + OS << "%lo"; + break; + case MEK_NEG: + OS << "%neg"; + break; + case MEK_PCREL_HI16: + OS << "%pcrel_hi"; + break; + case MEK_PCREL_LO16: + OS << "%pcrel_lo"; + break; + case MEK_TLSGD: + OS << "%tlsgd"; + break; + case MEK_TLSLDM: + OS << "%tlsldm"; + break; + case MEK_TPREL_HI: + OS << "%tprel_hi"; + break; + case MEK_TPREL_LO: + OS << "%tprel_lo"; + break; + } + OS << '('; + if (Expr->evaluateAsAbsolute(AbsVal)) + OS << AbsVal; + else + Expr->print(OS, MAI, true); + OS << ')'; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCExpr/visitUsedExpr.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCExpr/visitUsedExpr.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8372a7ff589eca544f1df8088f54e8b8b2b114fa --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCExpr/visitUsedExpr.cpp @@ -0,0 +1,3 @@ +void MipsMCExpr::visitUsedExpr(MCStreamer &Streamer) const { + Streamer.visitUsedExpr(*getSubExpr()); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCTargetDesc/InstrAnalysis.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCTargetDesc/InstrAnalysis.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5658244ea718376f3d69b7fbc49854fa42668962 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCTargetDesc/InstrAnalysis.cpp @@ -0,0 +1,2 @@ +MipsMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCTargetDesc/LLVMInitializeTargetMC.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCTargetDesc/LLVMInitializeTargetMC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7b01b2aad777f0e33601f9c86bac72b81a8343d6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCTargetDesc/LLVMInitializeTargetMC.cpp @@ -0,0 +1,19 @@ +extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMipsTargetMC() { + for (Target *T : {&getTheMipsTarget(), &getTheMipselTarget(), &getTheMips64Target(), &getTheMips64elTarget()}) { + RegisterMCAsmInfoFn X(*T, createMipsMCAsmInfo); + TargetRegistry::RegisterMCInstrInfo(*T, createMipsMCInstrInfo); + TargetRegistry::RegisterMCRegInfo(*T, createMipsMCRegisterInfo); + TargetRegistry::RegisterELFStreamer(*T, createMCStreamer); + TargetRegistry::RegisterAsmTargetStreamer(*T, createMipsAsmTargetStreamer); + TargetRegistry::RegisterNullTargetStreamer(*T, createMipsNullTargetStreamer); + TargetRegistry::RegisterMCSubtargetInfo(*T, createMipsMCSubtargetInfo); + TargetRegistry::RegisterMCInstrAnalysis(*T, createMipsMCInstrAnalysis); + TargetRegistry::RegisterMCInstPrinter(*T, createMipsMCInstPrinter); + TargetRegistry::RegisterObjectTargetStreamer(*T, createMipsObjectTargetStreamer); + TargetRegistry::RegisterMCAsmBackend(*T, createMipsAsmBackend); + } + for (Target *T : {&getTheMipsTarget(), &getTheMips64Target()}) + TargetRegistry::RegisterMCCodeEmitter(*T, createMipsMCCodeEmitterEB); + for (Target *T : {&getTheMipselTarget(), &getTheMips64elTarget()}) + TargetRegistry::RegisterMCCodeEmitter(*T, createMipsMCCodeEmitterEL); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCTargetDesc/createAsmTargetStreamer.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCTargetDesc/createAsmTargetStreamer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..98ebbf2d49c4647aed8ecd64155f39e30e2d242a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCTargetDesc/createAsmTargetStreamer.cpp @@ -0,0 +1,3 @@ +static MCTargetStreamer *createMipsAsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint, bool isVerboseAsm) { + return new MipsTargetAsmStreamer(S, OS); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCTargetDesc/createInstrAnalysis.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCTargetDesc/createInstrAnalysis.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b2a5cba504ed7a086ff506e9d8e6bc2f4fde5991 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCTargetDesc/createInstrAnalysis.cpp @@ -0,0 +1,3 @@ +static MCInstrAnalysis *createMipsMCInstrAnalysis(const MCInstrInfo *Info) { + return new MipsMCInstrAnalysis(Info); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCTargetDesc/createMCAsmInfo.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCTargetDesc/createMCAsmInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..837b9167e024dfc0068281dbe50fc9ad3064ca21 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCTargetDesc/createMCAsmInfo.cpp @@ -0,0 +1,7 @@ +static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI, const Triple &TT, const MCTargetOptions &Options) { + MCAsmInfo *MAI = new MipsMCAsmInfo(TT, Options); + unsigned SP = MRI.getDwarfRegNum(Mips::SP, true); + MCCFIInstruction Inst = MCCFIInstruction::createDefCfaRegister(nullptr, SP); + MAI->addInitialFrameState(Inst); + return MAI; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCTargetDesc/createMCInstPrinter.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCTargetDesc/createMCInstPrinter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..df05a3cab536755996ee2967e89aee556fc9d7aa --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCTargetDesc/createMCInstPrinter.cpp @@ -0,0 +1,3 @@ +static MCInstPrinter *createMipsMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI) { + return new MipsInstPrinter(MAI, MII, MRI); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCTargetDesc/createMCInstrInfo.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCTargetDesc/createMCInstrInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d50ca24c8cac1fc0d6821b37c8cea1728525d7a4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCTargetDesc/createMCInstrInfo.cpp @@ -0,0 +1,5 @@ +static MCInstrInfo *createMipsMCInstrInfo() { + MCInstrInfo *X = new MCInstrInfo(); + InitMipsMCInstrInfo(X); + return X; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCTargetDesc/createMCRegisterInfo.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCTargetDesc/createMCRegisterInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..39b142645d1a74904b92b3d82dd3360575145767 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCTargetDesc/createMCRegisterInfo.cpp @@ -0,0 +1,5 @@ +static MCRegisterInfo *createMipsMCRegisterInfo(const Triple &TT) { + MCRegisterInfo *X = new MCRegisterInfo(); + InitMipsMCRegisterInfo(X, Mips::RA); + return X; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCTargetDesc/createMCSubtargetInfo.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCTargetDesc/createMCSubtargetInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c05371de5a90f36670a3dbf3f15208b2ffbee21f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCTargetDesc/createMCSubtargetInfo.cpp @@ -0,0 +1,4 @@ +static MCSubtargetInfo *createMipsMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { + CPU = MIPS_MC::selectMipsCPU(TT, CPU); + return createMipsMCSubtargetInfoImpl(TT, CPU, CPU, FS); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCTargetDesc/createNullTargetStreamer.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCTargetDesc/createNullTargetStreamer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cf2f5e7108d8aa4cf1b43892131f3f21abecdd36 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCTargetDesc/createNullTargetStreamer.cpp @@ -0,0 +1,3 @@ +static MCTargetStreamer *createMipsNullTargetStreamer(MCStreamer &S) { + return new MipsTargetStreamer(S); +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCTargetDesc/createObjectTargetStreamer.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCTargetDesc/createObjectTargetStreamer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..10ee25d3af46cc3570b3f04fcd7ca01c661f6f81 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCTargetDesc/createObjectTargetStreamer.cpp @@ -0,0 +1,3 @@ +static MCTargetStreamer *createMipsObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) { + return new MipsTargetELFStreamer(S, STI); +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCTargetDesc/evaluateBranch.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCTargetDesc/evaluateBranch.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6b84c6fb1759fb7beed2dd8b743d221a44f24ed8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MCTargetDesc/evaluateBranch.cpp @@ -0,0 +1,18 @@ +bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size, uint64_t &Target) const override { + unsigned NumOps = Inst.getNumOperands(); + if (NumOps == 0) + return false; + switch (Info->get(Inst.getOpcode()).OpInfo[NumOps - 1].OperandType) { + case MCOI::OPERAND_UNKNOWN: + case MCOI::OPERAND_IMMEDIATE: { + uint64_t Region = Addr & ~uint64_t(0xfffffff); + Target = Region + Inst.getOperand(NumOps - 1).getImm(); + return true; + } + case MCOI::OPERAND_PCREL: + Target = Addr + Inst.getOperand(NumOps - 1).getImm(); + return true; + default: + return false; + } +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MatInt/generateInstSeq.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MatInt/generateInstSeq.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MatInt/generateInstSeq.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MatInt/getIntMatCost.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MatInt/getIntMatCost.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MatInt/getIntMatCost.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MatInt/structInst.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MatInt/structInst.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/MatInt/structInst.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/TargetAsmStreamer.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/TargetAsmStreamer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ee43d3cfc20af7f5ce81d111b7c1eb270406abca --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/TargetAsmStreamer.cpp @@ -0,0 +1,2 @@ +MipsTargetAsmStreamer::MipsTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS) : MipsTargetStreamer(S), OS(OS) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/TargetStreamer.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/TargetStreamer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6e217f82aee591bb534adeb6d7253244f98d5f09 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/TargetStreamer.cpp @@ -0,0 +1,3 @@ +MipsTargetStreamer::MipsTargetStreamer(MCStreamer &S) : MCTargetStreamer(S), GPReg(Mips::GP), ModuleDirectiveAllowed(true) { + GPRInfoSet = FPRInfoSet = FrameInfoSet = false; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitAttribute.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitAttribute.cpp new file mode 100644 index 0000000000000000000000000000000000000000..23a6029df8553c9ec55644c6e53170c37b3cf87d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitAttribute.cpp @@ -0,0 +1,3 @@ +void MipsTargetAsmStreamer::emitDirectiveOptionPic0() { + OS << "\t.option\tpic0\n"; +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitAttribute2.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitAttribute2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4bf64c8323e7b7238f06effee213a19639b43ba4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitAttribute2.cpp @@ -0,0 +1,2 @@ +void MipsTargetStreamer::emitDirectiveModuleCRC() { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionNoPIC.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionNoPIC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..23a6029df8553c9ec55644c6e53170c37b3cf87d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionNoPIC.cpp @@ -0,0 +1,3 @@ +void MipsTargetAsmStreamer::emitDirectiveOptionPic0() { + OS << "\t.option\tpic0\n"; +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionNoPIC2.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionNoPIC2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4bf64c8323e7b7238f06effee213a19639b43ba4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionNoPIC2.cpp @@ -0,0 +1,2 @@ +void MipsTargetStreamer::emitDirectiveModuleCRC() { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionNoRVC.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionNoRVC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..23a6029df8553c9ec55644c6e53170c37b3cf87d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionNoRVC.cpp @@ -0,0 +1,3 @@ +void MipsTargetAsmStreamer::emitDirectiveOptionPic0() { + OS << "\t.option\tpic0\n"; +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionNoRVC2.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionNoRVC2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4bf64c8323e7b7238f06effee213a19639b43ba4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionNoRVC2.cpp @@ -0,0 +1,2 @@ +void MipsTargetStreamer::emitDirectiveModuleCRC() { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionNoRelax.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionNoRelax.cpp new file mode 100644 index 0000000000000000000000000000000000000000..23a6029df8553c9ec55644c6e53170c37b3cf87d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionNoRelax.cpp @@ -0,0 +1,3 @@ +void MipsTargetAsmStreamer::emitDirectiveOptionPic0() { + OS << "\t.option\tpic0\n"; +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionNoRelax2.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionNoRelax2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4bf64c8323e7b7238f06effee213a19639b43ba4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionNoRelax2.cpp @@ -0,0 +1,2 @@ +void MipsTargetStreamer::emitDirectiveModuleCRC() { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionPIC.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionPIC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..23a6029df8553c9ec55644c6e53170c37b3cf87d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionPIC.cpp @@ -0,0 +1,3 @@ +void MipsTargetAsmStreamer::emitDirectiveOptionPic0() { + OS << "\t.option\tpic0\n"; +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionPIC2.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionPIC2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4bf64c8323e7b7238f06effee213a19639b43ba4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionPIC2.cpp @@ -0,0 +1,2 @@ +void MipsTargetStreamer::emitDirectiveModuleCRC() { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionPop.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionPop.cpp new file mode 100644 index 0000000000000000000000000000000000000000..23a6029df8553c9ec55644c6e53170c37b3cf87d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionPop.cpp @@ -0,0 +1,3 @@ +void MipsTargetAsmStreamer::emitDirectiveOptionPic0() { + OS << "\t.option\tpic0\n"; +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionPop2.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionPop2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4bf64c8323e7b7238f06effee213a19639b43ba4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionPop2.cpp @@ -0,0 +1,2 @@ +void MipsTargetStreamer::emitDirectiveModuleCRC() { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionPush.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionPush.cpp new file mode 100644 index 0000000000000000000000000000000000000000..23a6029df8553c9ec55644c6e53170c37b3cf87d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionPush.cpp @@ -0,0 +1,3 @@ +void MipsTargetAsmStreamer::emitDirectiveOptionPic0() { + OS << "\t.option\tpic0\n"; +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionPush2.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionPush2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4bf64c8323e7b7238f06effee213a19639b43ba4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionPush2.cpp @@ -0,0 +1,2 @@ +void MipsTargetStreamer::emitDirectiveModuleCRC() { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionRVC.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionRVC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..23a6029df8553c9ec55644c6e53170c37b3cf87d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionRVC.cpp @@ -0,0 +1,3 @@ +void MipsTargetAsmStreamer::emitDirectiveOptionPic0() { + OS << "\t.option\tpic0\n"; +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionRVC2.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionRVC2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4bf64c8323e7b7238f06effee213a19639b43ba4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionRVC2.cpp @@ -0,0 +1,2 @@ +void MipsTargetStreamer::emitDirectiveModuleCRC() { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionRelax.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionRelax.cpp new file mode 100644 index 0000000000000000000000000000000000000000..23a6029df8553c9ec55644c6e53170c37b3cf87d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionRelax.cpp @@ -0,0 +1,3 @@ +void MipsTargetAsmStreamer::emitDirectiveOptionPic0() { + OS << "\t.option\tpic0\n"; +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionRelax2.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionRelax2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4bf64c8323e7b7238f06effee213a19639b43ba4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionRelax2.cpp @@ -0,0 +1,2 @@ +void MipsTargetStreamer::emitDirectiveModuleCRC() { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitIntTextAttribute.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitIntTextAttribute.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4bf64c8323e7b7238f06effee213a19639b43ba4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitIntTextAttribute.cpp @@ -0,0 +1,2 @@ +void MipsTargetStreamer::emitDirectiveModuleCRC() { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitIntTextAttribute2.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitIntTextAttribute2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4bf64c8323e7b7238f06effee213a19639b43ba4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitIntTextAttribute2.cpp @@ -0,0 +1,2 @@ +void MipsTargetStreamer::emitDirectiveModuleCRC() { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitTargetAttributes.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitTargetAttributes.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4bf64c8323e7b7238f06effee213a19639b43ba4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitTargetAttributes.cpp @@ -0,0 +1,2 @@ +void MipsTargetStreamer::emitDirectiveModuleCRC() { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitTextAttribute.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitTextAttribute.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4bf64c8323e7b7238f06effee213a19639b43ba4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitTextAttribute.cpp @@ -0,0 +1,2 @@ +void MipsTargetStreamer::emitDirectiveModuleCRC() { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitTextAttribute2.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitTextAttribute2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..23a6029df8553c9ec55644c6e53170c37b3cf87d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/emitTextAttribute2.cpp @@ -0,0 +1,3 @@ +void MipsTargetAsmStreamer::emitDirectiveOptionPic0() { + OS << "\t.option\tpic0\n"; +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/finish.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/finish.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d532f0f886a4e984cb24aea1e0b94a27c8f44b31 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/finish.cpp @@ -0,0 +1,47 @@ +void MipsTargetELFStreamer::finish() { + MCAssembler &MCA = getStreamer().getAssembler(); + const MCObjectFileInfo &OFI = *MCA.getContext().getObjectFileInfo(); + MCSection &TextSection = *OFI.getTextSection(); + MCA.registerSection(TextSection); + MCSection &DataSection = *OFI.getDataSection(); + MCA.registerSection(DataSection); + MCSection &BSSSection = *OFI.getBSSSection(); + MCA.registerSection(BSSSection); + TextSection.setAlignment(Align(std::max(16u, TextSection.getAlignment()))); + DataSection.setAlignment(Align(std::max(16u, DataSection.getAlignment()))); + BSSSection.setAlignment(Align(std::max(16u, BSSSection.getAlignment()))); + if (RoundSectionSizes) { + MCStreamer &OS = getStreamer(); + for (MCSection &S : MCA) { + MCSectionELF &Section = static_cast(S); + unsigned Alignment = Section.getAlignment(); + if (Alignment) { + OS.SwitchSection(&Section); + if (Section.UseCodeAlign()) + OS.emitCodeAlignment(Alignment, Alignment); + else + OS.emitValueToAlignment(Alignment, 0, 1, Alignment); + } + } + } + const FeatureBitset &Features = STI.getFeatureBits(); + unsigned EFlags = MCA.getELFHeaderEFlags(); + if (getABI().IsO32()) + EFlags |= ELF::EF_MIPS_ABI_O32; + else if (getABI().IsN32()) + EFlags |= ELF::EF_MIPS_ABI2; + if (Features[Mips::FeatureGP64Bit]) { + if (getABI().IsO32()) + EFlags |= ELF::EF_MIPS_32BITMODE; /* Compatibility Mode */ + } + else if (Features[Mips::FeatureMips64r2] || Features[Mips::FeatureMips64]) + EFlags |= ELF::EF_MIPS_32BITMODE; + if (!Features[Mips::FeatureNoABICalls]) + EFlags |= ELF::EF_MIPS_CPIC; + if (Pic) + EFlags |= ELF::EF_MIPS_PIC | ELF::EF_MIPS_CPIC; + MCA.setELFHeaderEFlags(EFlags); + MipsELFStreamer &MEF = static_cast(Streamer); + MEF.EmitMipsOptionRecords(); + emitMipsAbiFlags(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/finishAttributeSection.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/finishAttributeSection.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/finishAttributeSection.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/finishAttributeSection2.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/finishAttributeSection2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Emission/TargetStreamer/finishAttributeSection2.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/CleanupVSETVLI/CleanupVSETVLI.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/CleanupVSETVLI/CleanupVSETVLI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..57aeffd0e2e2e5bb1200734269fc42fb5b8f16c9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/CleanupVSETVLI/CleanupVSETVLI.cpp @@ -0,0 +1,2 @@ +MipsModuleDAGToDAGISel() : MachineFunctionPass(ID) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/CleanupVSETVLI/createPass.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/CleanupVSETVLI/createPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..66bbc81adf0ef98fff67099cd474312163d2ef95 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/CleanupVSETVLI/createPass.cpp @@ -0,0 +1,3 @@ +llvm::FunctionPass *llvm::createMipsModuleISelDagPass() { + return new MipsModuleDAGToDAGISel(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/CleanupVSETVLI/getAnalysisUsage.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/CleanupVSETVLI/getAnalysisUsage.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3f3e70065dbb1b3bcc423b768c1c4c1713ba4da5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/CleanupVSETVLI/getAnalysisUsage.cpp @@ -0,0 +1,4 @@ +void getAnalysisUsage(AnalysisUsage &AU) const override { + AU.addRequired(); + MachineFunctionPass::getAnalysisUsage(AU); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/CleanupVSETVLI/getPassName.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/CleanupVSETVLI/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..90c890951e14cd0629d6e0878884a87bb8c79386 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/CleanupVSETVLI/getPassName.cpp @@ -0,0 +1,3 @@ +StringRef getPassName() const override { + return "Mips Branch Expansion Pass"; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/CleanupVSETVLI/getRequiredProperties.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/CleanupVSETVLI/getRequiredProperties.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c75653867ef66dd435b2ea7205493d823d8fbb30 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/CleanupVSETVLI/getRequiredProperties.cpp @@ -0,0 +1,3 @@ +MachineFunctionProperties getRequiredProperties() const override { + return MachineFunctionProperties().set(MachineFunctionProperties::Property::NoVRegs); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/CleanupVSETVLI/runOnMachineBasicBlock.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/CleanupVSETVLI/runOnMachineBasicBlock.cpp new file mode 100644 index 0000000000000000000000000000000000000000..77e28c673af82e311aad8811a99167bc300e4849 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/CleanupVSETVLI/runOnMachineBasicBlock.cpp @@ -0,0 +1,49 @@ +bool MipsDelaySlotFiller::runOnMachineBasicBlock(MachineBasicBlock &MBB) { + bool Changed = false; + const MipsSubtarget &STI = MBB.getParent()->getSubtarget(); + bool InMicroMipsMode = STI.inMicroMipsMode(); + const MipsInstrInfo *TII = STI.getInstrInfo(); + for (Iter I = MBB.begin(); I != MBB.end(); ++I) { + if (!hasUnoccupiedSlot(&*I)) + continue; + if (!DisableDelaySlotFiller && (TM->getOptLevel() != CodeGenOpt::None) && !(InMicroMipsMode && STI.hasMips32r6())) { + bool Filled = false; + if (MipsCompactBranchPolicy.getValue() != CB_Always || !TII->getEquivalentCompactForm(I)) { + if (searchBackward(MBB, *I)) { + LLVM_DEBUG(dbgs() << DEBUG_TYPE ": found instruction for delay slot in backwards search.\n"); + Filled = true; + } + else if (I->isTerminator()) { + if (searchSuccBBs(MBB, I)) { + Filled = true; + LLVM_DEBUG(dbgs() << DEBUG_TYPE ": found instruction for delay slot in successor BB search.\n"); + } + } + else if (searchForward(MBB, I)) { + LLVM_DEBUG(dbgs() << DEBUG_TYPE ": found instruction for delay slot in forwards search.\n"); + Filled = true; + } + } + if (Filled) { + MachineBasicBlock::instr_iterator DSI = I.getInstrIterator(); + if (InMicroMipsMode && TII->getInstSizeInBytes(*std::next(DSI)) == 2 && DSI->isCall()) { + DSI->setDesc(TII->get(getEquivalentCallShort(DSI->getOpcode()))); + } + ++FilledSlots; + Changed = true; + continue; + } + } + if ((InMicroMipsMode || (STI.hasMips32r6() && MipsCompactBranchPolicy != CB_Never)) && TII->getEquivalentCompactForm(I)) { + I = replaceWithCompactBranch(MBB, I, I->getDebugLoc()); + Changed = true; + continue; + } + LLVM_DEBUG(dbgs() << DEBUG_TYPE << ": could not fill delay slot for "; I->dump()); + BuildMI(MBB, std::next(I), I->getDebugLoc(), TII->get(Mips::NOP)); + MIBundleBuilder(MBB, I, std::next(I, 2)); + ++FilledSlots; + Changed = true; + } + return Changed; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/CleanupVSETVLI/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/CleanupVSETVLI/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..62edb7f880dc7a87d5437717d542d7ef50894acb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/CleanupVSETVLI/runOnMachineFunction.cpp @@ -0,0 +1,21 @@ +bool MipsBranchExpansion::runOnMachineFunction(MachineFunction &MF) { + const TargetMachine &TM = MF.getTarget(); + IsPIC = TM.isPositionIndependent(); + ABI = static_cast(TM).getABI(); + STI = &static_cast(MF.getSubtarget()); + TII = static_cast(STI->getInstrInfo()); + if (IsPIC && ABI.IsO32() && MF.getInfo()->globalBaseRegSet()) + emitGPDisp(MF, TII); + MFp = &MF; + ForceLongBranchFirstPass = ForceLongBranch; + bool longBranchChanged = handlePossibleLongBranch(); + bool forbiddenSlotChanged = handleForbiddenSlot(); + bool Changed = longBranchChanged || forbiddenSlotChanged; + while (forbiddenSlotChanged) { + longBranchChanged = handlePossibleLongBranch(); + if (!longBranchChanged) + break; + forbiddenSlotChanged = handleForbiddenSlot(); + } + return Changed; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/ExpandAtomicPseudoInsts/ExpandAtomicPseudo.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/ExpandAtomicPseudoInsts/ExpandAtomicPseudo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..57aeffd0e2e2e5bb1200734269fc42fb5b8f16c9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/ExpandAtomicPseudoInsts/ExpandAtomicPseudo.cpp @@ -0,0 +1,2 @@ +MipsModuleDAGToDAGISel() : MachineFunctionPass(ID) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/ExpandAtomicPseudoInsts/createPass.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/ExpandAtomicPseudoInsts/createPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..66bbc81adf0ef98fff67099cd474312163d2ef95 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/ExpandAtomicPseudoInsts/createPass.cpp @@ -0,0 +1,3 @@ +llvm::FunctionPass *llvm::createMipsModuleISelDagPass() { + return new MipsModuleDAGToDAGISel(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/ExpandAtomicPseudoInsts/expandMBB.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/ExpandAtomicPseudoInsts/expandMBB.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e591da793babbe33581e2a658ea7c9a09e93dedb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/ExpandAtomicPseudoInsts/expandMBB.cpp @@ -0,0 +1,10 @@ +bool MipsExpandPseudo::expandMBB(MachineBasicBlock &MBB) { + bool Modified = false; + MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end(); + while (MBBI != E) { + MachineBasicBlock::iterator NMBBI = std::next(MBBI); + Modified |= expandMI(MBB, MBBI, NMBBI); + MBBI = NMBBI; + } + return Modified; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/ExpandAtomicPseudoInsts/expandMI.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/ExpandAtomicPseudoInsts/expandMI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..687810462f4fad5e6d8ad2e77820cb9e1a0aac2e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/ExpandAtomicPseudoInsts/expandMI.cpp @@ -0,0 +1,60 @@ +bool MipsExpandPseudo::expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, MachineBasicBlock::iterator &NMBB) { + bool Modified = false; + switch (MBBI->getOpcode()) { + case Mips::ATOMIC_CMP_SWAP_I32_POSTRA: + case Mips::ATOMIC_CMP_SWAP_I64_POSTRA: + return expandAtomicCmpSwap(MBB, MBBI, NMBB); + case Mips::ATOMIC_CMP_SWAP_I8_POSTRA: + case Mips::ATOMIC_CMP_SWAP_I16_POSTRA: + return expandAtomicCmpSwapSubword(MBB, MBBI, NMBB); + case Mips::ATOMIC_SWAP_I8_POSTRA: + case Mips::ATOMIC_SWAP_I16_POSTRA: + case Mips::ATOMIC_LOAD_NAND_I8_POSTRA: + case Mips::ATOMIC_LOAD_NAND_I16_POSTRA: + case Mips::ATOMIC_LOAD_ADD_I8_POSTRA: + case Mips::ATOMIC_LOAD_ADD_I16_POSTRA: + case Mips::ATOMIC_LOAD_SUB_I8_POSTRA: + case Mips::ATOMIC_LOAD_SUB_I16_POSTRA: + case Mips::ATOMIC_LOAD_AND_I8_POSTRA: + case Mips::ATOMIC_LOAD_AND_I16_POSTRA: + case Mips::ATOMIC_LOAD_OR_I8_POSTRA: + case Mips::ATOMIC_LOAD_OR_I16_POSTRA: + case Mips::ATOMIC_LOAD_XOR_I8_POSTRA: + case Mips::ATOMIC_LOAD_XOR_I16_POSTRA: + case Mips::ATOMIC_LOAD_MIN_I8_POSTRA: + case Mips::ATOMIC_LOAD_MIN_I16_POSTRA: + case Mips::ATOMIC_LOAD_MAX_I8_POSTRA: + case Mips::ATOMIC_LOAD_MAX_I16_POSTRA: + case Mips::ATOMIC_LOAD_UMIN_I8_POSTRA: + case Mips::ATOMIC_LOAD_UMIN_I16_POSTRA: + case Mips::ATOMIC_LOAD_UMAX_I8_POSTRA: + case Mips::ATOMIC_LOAD_UMAX_I16_POSTRA: + return expandAtomicBinOpSubword(MBB, MBBI, NMBB); + case Mips::ATOMIC_LOAD_ADD_I32_POSTRA: + case Mips::ATOMIC_LOAD_SUB_I32_POSTRA: + case Mips::ATOMIC_LOAD_AND_I32_POSTRA: + case Mips::ATOMIC_LOAD_OR_I32_POSTRA: + case Mips::ATOMIC_LOAD_XOR_I32_POSTRA: + case Mips::ATOMIC_LOAD_NAND_I32_POSTRA: + case Mips::ATOMIC_SWAP_I32_POSTRA: + case Mips::ATOMIC_LOAD_MIN_I32_POSTRA: + case Mips::ATOMIC_LOAD_MAX_I32_POSTRA: + case Mips::ATOMIC_LOAD_UMIN_I32_POSTRA: + case Mips::ATOMIC_LOAD_UMAX_I32_POSTRA: + return expandAtomicBinOp(MBB, MBBI, NMBB, 4); + case Mips::ATOMIC_LOAD_ADD_I64_POSTRA: + case Mips::ATOMIC_LOAD_SUB_I64_POSTRA: + case Mips::ATOMIC_LOAD_AND_I64_POSTRA: + case Mips::ATOMIC_LOAD_OR_I64_POSTRA: + case Mips::ATOMIC_LOAD_XOR_I64_POSTRA: + case Mips::ATOMIC_LOAD_NAND_I64_POSTRA: + case Mips::ATOMIC_SWAP_I64_POSTRA: + case Mips::ATOMIC_LOAD_MIN_I64_POSTRA: + case Mips::ATOMIC_LOAD_MAX_I64_POSTRA: + case Mips::ATOMIC_LOAD_UMIN_I64_POSTRA: + case Mips::ATOMIC_LOAD_UMAX_I64_POSTRA: + return expandAtomicBinOp(MBB, MBBI, NMBB, 8); + default: + return Modified; + } +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/ExpandAtomicPseudoInsts/getPassName.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/ExpandAtomicPseudoInsts/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..90c890951e14cd0629d6e0878884a87bb8c79386 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/ExpandAtomicPseudoInsts/getPassName.cpp @@ -0,0 +1,3 @@ +StringRef getPassName() const override { + return "Mips Branch Expansion Pass"; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/ExpandAtomicPseudoInsts/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/ExpandAtomicPseudoInsts/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..62edb7f880dc7a87d5437717d542d7ef50894acb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/ExpandAtomicPseudoInsts/runOnMachineFunction.cpp @@ -0,0 +1,21 @@ +bool MipsBranchExpansion::runOnMachineFunction(MachineFunction &MF) { + const TargetMachine &TM = MF.getTarget(); + IsPIC = TM.isPositionIndependent(); + ABI = static_cast(TM).getABI(); + STI = &static_cast(MF.getSubtarget()); + TII = static_cast(STI->getInstrInfo()); + if (IsPIC && ABI.IsO32() && MF.getInfo()->globalBaseRegSet()) + emitGPDisp(MF, TII); + MFp = &MF; + ForceLongBranchFirstPass = ForceLongBranch; + bool longBranchChanged = handlePossibleLongBranch(); + bool forbiddenSlotChanged = handleForbiddenSlot(); + bool Changed = longBranchChanged || forbiddenSlotChanged; + while (forbiddenSlotChanged) { + longBranchChanged = handlePossibleLongBranch(); + if (!longBranchChanged) + break; + forbiddenSlotChanged = handleForbiddenSlot(); + } + return Changed; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/ExpandPseudoInsts/ExpandPseudo.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/ExpandPseudoInsts/ExpandPseudo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..57aeffd0e2e2e5bb1200734269fc42fb5b8f16c9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/ExpandPseudoInsts/ExpandPseudo.cpp @@ -0,0 +1,2 @@ +MipsModuleDAGToDAGISel() : MachineFunctionPass(ID) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/ExpandPseudoInsts/createPass.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/ExpandPseudoInsts/createPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..66bbc81adf0ef98fff67099cd474312163d2ef95 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/ExpandPseudoInsts/createPass.cpp @@ -0,0 +1,3 @@ +llvm::FunctionPass *llvm::createMipsModuleISelDagPass() { + return new MipsModuleDAGToDAGISel(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/ExpandPseudoInsts/expandMBB.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/ExpandPseudoInsts/expandMBB.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e591da793babbe33581e2a658ea7c9a09e93dedb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/ExpandPseudoInsts/expandMBB.cpp @@ -0,0 +1,10 @@ +bool MipsExpandPseudo::expandMBB(MachineBasicBlock &MBB) { + bool Modified = false; + MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end(); + while (MBBI != E) { + MachineBasicBlock::iterator NMBBI = std::next(MBBI); + Modified |= expandMI(MBB, MBBI, NMBBI); + MBBI = NMBBI; + } + return Modified; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/ExpandPseudoInsts/expandMI.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/ExpandPseudoInsts/expandMI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..687810462f4fad5e6d8ad2e77820cb9e1a0aac2e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/ExpandPseudoInsts/expandMI.cpp @@ -0,0 +1,60 @@ +bool MipsExpandPseudo::expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, MachineBasicBlock::iterator &NMBB) { + bool Modified = false; + switch (MBBI->getOpcode()) { + case Mips::ATOMIC_CMP_SWAP_I32_POSTRA: + case Mips::ATOMIC_CMP_SWAP_I64_POSTRA: + return expandAtomicCmpSwap(MBB, MBBI, NMBB); + case Mips::ATOMIC_CMP_SWAP_I8_POSTRA: + case Mips::ATOMIC_CMP_SWAP_I16_POSTRA: + return expandAtomicCmpSwapSubword(MBB, MBBI, NMBB); + case Mips::ATOMIC_SWAP_I8_POSTRA: + case Mips::ATOMIC_SWAP_I16_POSTRA: + case Mips::ATOMIC_LOAD_NAND_I8_POSTRA: + case Mips::ATOMIC_LOAD_NAND_I16_POSTRA: + case Mips::ATOMIC_LOAD_ADD_I8_POSTRA: + case Mips::ATOMIC_LOAD_ADD_I16_POSTRA: + case Mips::ATOMIC_LOAD_SUB_I8_POSTRA: + case Mips::ATOMIC_LOAD_SUB_I16_POSTRA: + case Mips::ATOMIC_LOAD_AND_I8_POSTRA: + case Mips::ATOMIC_LOAD_AND_I16_POSTRA: + case Mips::ATOMIC_LOAD_OR_I8_POSTRA: + case Mips::ATOMIC_LOAD_OR_I16_POSTRA: + case Mips::ATOMIC_LOAD_XOR_I8_POSTRA: + case Mips::ATOMIC_LOAD_XOR_I16_POSTRA: + case Mips::ATOMIC_LOAD_MIN_I8_POSTRA: + case Mips::ATOMIC_LOAD_MIN_I16_POSTRA: + case Mips::ATOMIC_LOAD_MAX_I8_POSTRA: + case Mips::ATOMIC_LOAD_MAX_I16_POSTRA: + case Mips::ATOMIC_LOAD_UMIN_I8_POSTRA: + case Mips::ATOMIC_LOAD_UMIN_I16_POSTRA: + case Mips::ATOMIC_LOAD_UMAX_I8_POSTRA: + case Mips::ATOMIC_LOAD_UMAX_I16_POSTRA: + return expandAtomicBinOpSubword(MBB, MBBI, NMBB); + case Mips::ATOMIC_LOAD_ADD_I32_POSTRA: + case Mips::ATOMIC_LOAD_SUB_I32_POSTRA: + case Mips::ATOMIC_LOAD_AND_I32_POSTRA: + case Mips::ATOMIC_LOAD_OR_I32_POSTRA: + case Mips::ATOMIC_LOAD_XOR_I32_POSTRA: + case Mips::ATOMIC_LOAD_NAND_I32_POSTRA: + case Mips::ATOMIC_SWAP_I32_POSTRA: + case Mips::ATOMIC_LOAD_MIN_I32_POSTRA: + case Mips::ATOMIC_LOAD_MAX_I32_POSTRA: + case Mips::ATOMIC_LOAD_UMIN_I32_POSTRA: + case Mips::ATOMIC_LOAD_UMAX_I32_POSTRA: + return expandAtomicBinOp(MBB, MBBI, NMBB, 4); + case Mips::ATOMIC_LOAD_ADD_I64_POSTRA: + case Mips::ATOMIC_LOAD_SUB_I64_POSTRA: + case Mips::ATOMIC_LOAD_AND_I64_POSTRA: + case Mips::ATOMIC_LOAD_OR_I64_POSTRA: + case Mips::ATOMIC_LOAD_XOR_I64_POSTRA: + case Mips::ATOMIC_LOAD_NAND_I64_POSTRA: + case Mips::ATOMIC_SWAP_I64_POSTRA: + case Mips::ATOMIC_LOAD_MIN_I64_POSTRA: + case Mips::ATOMIC_LOAD_MAX_I64_POSTRA: + case Mips::ATOMIC_LOAD_UMIN_I64_POSTRA: + case Mips::ATOMIC_LOAD_UMAX_I64_POSTRA: + return expandAtomicBinOp(MBB, MBBI, NMBB, 8); + default: + return Modified; + } +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/ExpandPseudoInsts/getPassName.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/ExpandPseudoInsts/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..90c890951e14cd0629d6e0878884a87bb8c79386 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/ExpandPseudoInsts/getPassName.cpp @@ -0,0 +1,3 @@ +StringRef getPassName() const override { + return "Mips Branch Expansion Pass"; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/ExpandPseudoInsts/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/ExpandPseudoInsts/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..62edb7f880dc7a87d5437717d542d7ef50894acb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/ExpandPseudoInsts/runOnMachineFunction.cpp @@ -0,0 +1,21 @@ +bool MipsBranchExpansion::runOnMachineFunction(MachineFunction &MF) { + const TargetMachine &TM = MF.getTarget(); + IsPIC = TM.isPositionIndependent(); + ABI = static_cast(TM).getABI(); + STI = &static_cast(MF.getSubtarget()); + TII = static_cast(STI->getInstrInfo()); + if (IsPIC && ABI.IsO32() && MF.getInfo()->globalBaseRegSet()) + emitGPDisp(MF, TII); + MFp = &MF; + ForceLongBranchFirstPass = ForceLongBranch; + bool longBranchChanged = handlePossibleLongBranch(); + bool forbiddenSlotChanged = handleForbiddenSlot(); + bool Changed = longBranchChanged || forbiddenSlotChanged; + while (forbiddenSlotChanged) { + longBranchChanged = handlePossibleLongBranch(); + if (!longBranchChanged) + break; + forbiddenSlotChanged = handleForbiddenSlot(); + } + return Changed; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/MergeBaseOffset/MergeBaseOffsetOpt.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/MergeBaseOffset/MergeBaseOffsetOpt.cpp new file mode 100644 index 0000000000000000000000000000000000000000..57aeffd0e2e2e5bb1200734269fc42fb5b8f16c9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/MergeBaseOffset/MergeBaseOffsetOpt.cpp @@ -0,0 +1,2 @@ +MipsModuleDAGToDAGISel() : MachineFunctionPass(ID) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/MergeBaseOffset/createPass.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/MergeBaseOffset/createPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..66bbc81adf0ef98fff67099cd474312163d2ef95 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/MergeBaseOffset/createPass.cpp @@ -0,0 +1,3 @@ +llvm::FunctionPass *llvm::createMipsModuleISelDagPass() { + return new MipsModuleDAGToDAGISel(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/MergeBaseOffset/getPassName.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/MergeBaseOffset/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..90c890951e14cd0629d6e0878884a87bb8c79386 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/MergeBaseOffset/getPassName.cpp @@ -0,0 +1,3 @@ +StringRef getPassName() const override { + return "Mips Branch Expansion Pass"; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/MergeBaseOffset/getRequiredProperties.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/MergeBaseOffset/getRequiredProperties.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c75653867ef66dd435b2ea7205493d823d8fbb30 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/MergeBaseOffset/getRequiredProperties.cpp @@ -0,0 +1,3 @@ +MachineFunctionProperties getRequiredProperties() const override { + return MachineFunctionProperties().set(MachineFunctionProperties::Property::NoVRegs); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/MergeBaseOffset/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/MergeBaseOffset/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..66c7b3864fbc88610507a3b57469c33cbe7067a8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Optimization/MergeBaseOffset/runOnMachineFunction.cpp @@ -0,0 +1,21 @@ +bool MipsBranchExpansion::runOnMachineFunction(MachineFunction &MF) { + const TargetMachine &TM = MF.getTarget(); + IsPIC = TM.isPositionIndependent(); + ABI = static_cast(TM).getABI(); + STI = &static_cast(MF.getSubtarget()); + TII = static_cast(STI->getInstrInfo()); + if (IsPIC && ABI.IsO32() && MF.getInfo()->globalBaseRegSet()) + emitGPDisp(MF, TII); + MFp = &MF; + ForceLongBranchFirstPass = ForceLongBranch; + bool longBranchChanged = handlePossibleLongBranch(); + bool forbiddenSlotChanged = handleForbiddenSlot(); + bool Changed = longBranchChanged || forbiddenSlotChanged; + while (forbiddenSlotChanged) { + longBranchChanged = handlePossibleLongBranch(); + if (!longBranchChanged) + break; + forbiddenSlotChanged = handleForbiddenSlot(); + } + return Changed; +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/InstrInfo.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/InstrInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..89ef265a73d366c9fe3f2c94f235af727e8b5dcd --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/InstrInfo.cpp @@ -0,0 +1,2 @@ +MipsInstrInfo::MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBr) : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP), Subtarget(STI), UncondBrOpc(UncondBr) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/analyzeBranch.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/analyzeBranch.cpp new file mode 100644 index 0000000000000000000000000000000000000000..492da016718b9b6f818e0f34a01596e175c6affb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/analyzeBranch.cpp @@ -0,0 +1,5 @@ +bool MipsInstrInfo::analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl &Cond, bool AllowModify) const { + SmallVector BranchInstrs; + BranchType BT = analyzeBranch(MBB, TBB, FBB, Cond, AllowModify, BranchInstrs); + return (BT == BT_None) || (BT == BT_Indirect); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/areMemAccessesTriviallyDisjoint.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/areMemAccessesTriviallyDisjoint.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d24252a436720a3ccdecb69c990fff58341ff97c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/areMemAccessesTriviallyDisjoint.cpp @@ -0,0 +1,2 @@ +None + diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/buildOutlinedFrame.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/buildOutlinedFrame.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/buildOutlinedFrame.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/copyPhysReg.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/copyPhysReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a5fc2c1a67373b362485a1ac80c16cbe10ca55a9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/copyPhysReg.cpp @@ -0,0 +1,92 @@ +void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const { + unsigned Opc = 0, ZeroReg = 0; + bool isMicroMips = Subtarget.inMicroMipsMode(); + if (Mips::GPR32RegClass.contains(DestReg)) { + if (Mips::GPR32RegClass.contains(SrcReg)) { + if (isMicroMips) + Opc = Mips::MOVE16_MM; + else + Opc = Mips::OR, ZeroReg = Mips::ZERO; + } + else if (Mips::CCRRegClass.contains(SrcReg)) + Opc = Mips::CFC1; + else if (Mips::FGR32RegClass.contains(SrcReg)) + Opc = Mips::MFC1; + else if (Mips::HI32RegClass.contains(SrcReg)) { + Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI; + SrcReg = 0; + } + else if (Mips::LO32RegClass.contains(SrcReg)) { + Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO; + SrcReg = 0; + } + else if (Mips::HI32DSPRegClass.contains(SrcReg)) + Opc = Mips::MFHI_DSP; + else if (Mips::LO32DSPRegClass.contains(SrcReg)) + Opc = Mips::MFLO_DSP; + else if (Mips::DSPCCRegClass.contains(SrcReg)) { + BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4).addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc)); + return; + } + else if (Mips::MSACtrlRegClass.contains(SrcReg)) + Opc = Mips::CFCMSA; + } + else if (Mips::GPR32RegClass.contains(SrcReg)) { + if (Mips::CCRRegClass.contains(DestReg)) + Opc = Mips::CTC1; + else if (Mips::FGR32RegClass.contains(DestReg)) + Opc = Mips::MTC1; + else if (Mips::HI32RegClass.contains(DestReg)) + Opc = Mips::MTHI, DestReg = 0; + else if (Mips::LO32RegClass.contains(DestReg)) + Opc = Mips::MTLO, DestReg = 0; + else if (Mips::HI32DSPRegClass.contains(DestReg)) + Opc = Mips::MTHI_DSP; + else if (Mips::LO32DSPRegClass.contains(DestReg)) + Opc = Mips::MTLO_DSP; + else if (Mips::DSPCCRegClass.contains(DestReg)) { + BuildMI(MBB, I, DL, get(Mips::WRDSP)).addReg(SrcReg, getKillRegState(KillSrc)).addImm(1 << 4).addReg(DestReg, RegState::ImplicitDefine); + return; + } + else if (Mips::MSACtrlRegClass.contains(DestReg)) { + BuildMI(MBB, I, DL, get(Mips::CTCMSA)).addReg(DestReg).addReg(SrcReg, getKillRegState(KillSrc)); + return; + } + } + else if (Mips::FGR32RegClass.contains(DestReg, SrcReg)) + Opc = Mips::FMOV_S; + else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg)) + Opc = Mips::FMOV_D32; + else if (Mips::FGR64RegClass.contains(DestReg, SrcReg)) + Opc = Mips::FMOV_D64; + else if (Mips::GPR64RegClass.contains(DestReg)) { + if (Mips::GPR64RegClass.contains(SrcReg)) + Opc = Mips::OR64, ZeroReg = Mips::ZERO_64; + else if (Mips::HI64RegClass.contains(SrcReg)) + Opc = Mips::MFHI64, SrcReg = 0; + else if (Mips::LO64RegClass.contains(SrcReg)) + Opc = Mips::MFLO64, SrcReg = 0; + else if (Mips::FGR64RegClass.contains(SrcReg)) + Opc = Mips::DMFC1; + } + else if (Mips::GPR64RegClass.contains(SrcReg)) { + if (Mips::HI64RegClass.contains(DestReg)) + Opc = Mips::MTHI64, DestReg = 0; + else if (Mips::LO64RegClass.contains(DestReg)) + Opc = Mips::MTLO64, DestReg = 0; + else if (Mips::FGR64RegClass.contains(DestReg)) + Opc = Mips::DMTC1; + } + else if (Mips::MSA128BRegClass.contains(DestReg)) { + if (Mips::MSA128BRegClass.contains(SrcReg)) + Opc = Mips::MOVE_V; + } + assert(Opc && "Cannot copy registers"); + MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc)); + if (DestReg) + MIB.addReg(DestReg, RegState::Define); + if (SrcReg) + MIB.addReg(SrcReg, getKillRegState(KillSrc)); + if (ZeroReg) + MIB.addReg(ZeroReg); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/decomposeMachineOperandsTargetFlags.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/decomposeMachineOperandsTargetFlags.cpp new file mode 100644 index 0000000000000000000000000000000000000000..597c42a46327b8073dd001d24e93dda00be2781e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/decomposeMachineOperandsTargetFlags.cpp @@ -0,0 +1,3 @@ +std::pair MipsInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const { + return std::make_pair(TF, 0u); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/getBranchDestBlock.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/getBranchDestBlock.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/getBranchDestBlock.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/getInstSizeInBytes.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/getInstSizeInBytes.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/getInstSizeInBytes.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/getMemOperandWithOffsetWidth.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/getMemOperandWithOffsetWidth.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/getMemOperandWithOffsetWidth.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/getOutliningCandidateInfo.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/getOutliningCandidateInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d24252a436720a3ccdecb69c990fff58341ff97c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/getOutliningCandidateInfo.cpp @@ -0,0 +1,2 @@ +None + diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/getOutliningType.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/getOutliningType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/getOutliningType.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/getSerializableDirectMachineOperandTargetFlags.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/getSerializableDirectMachineOperandTargetFlags.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d6a73118f0d98feb321a30df73ba2e80992df4ab --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/getSerializableDirectMachineOperandTargetFlags.cpp @@ -0,0 +1,5 @@ +ArrayRef> MipsInstrInfo::getSerializableDirectMachineOperandTargetFlags() const { + using namespace MipsII; + static const std::pair Flags[] = {{MO_GOT, "mips-got"}, {MO_GOT_CALL, "mips-got-call"}, {MO_GPREL, "mips-gprel"}, {MO_ABS_HI, "mips-abs-hi"}, {MO_ABS_LO, "mips-abs-lo"}, {MO_TLSGD, "mips-tlsgd"}, {MO_TLSLDM, "mips-tlsldm"}, {MO_DTPREL_HI, "mips-dtprel-hi"}, {MO_DTPREL_LO, "mips-dtprel-lo"}, {MO_GOTTPREL, "mips-gottprel"}, {MO_TPREL_HI, "mips-tprel-hi"}, {MO_TPREL_LO, "mips-tprel-lo"}, {MO_GPOFF_HI, "mips-gpoff-hi"}, {MO_GPOFF_LO, "mips-gpoff-lo"}, {MO_GOT_DISP, "mips-got-disp"}, {MO_GOT_PAGE, "mips-got-page"}, {MO_GOT_OFST, "mips-got-ofst"}, {MO_HIGHER, "mips-higher"}, {MO_HIGHEST, "mips-highest"}, {MO_GOT_HI16, "mips-got-hi16"}, {MO_GOT_LO16, "mips-got-lo16"}, {MO_CALL_HI16, "mips-call-hi16"}, {MO_CALL_LO16, "mips-call-lo16"}, {MO_JALR, "mips-jalr"}}; + return makeArrayRef(Flags); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/insertBranch.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/insertBranch.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7aadd2573c6e9b7e1703c86ae78cd84d2f384d34 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/insertBranch.cpp @@ -0,0 +1,15 @@ +unsigned MipsInstrInfo::insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, const DebugLoc &DL, int *BytesAdded) const { + assert(TBB && "insertBranch must not be told to insert a fallthrough"); + assert(!BytesAdded && "code size not handled"); + assert((Cond.size() <= 3) && "# of Mips branch conditions must be <= 3!"); + if (FBB) { + BuildCondBr(MBB, TBB, DL, Cond); + BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(FBB); + return 2; + } + if (Cond.empty()) + BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(TBB); + else + BuildCondBr(MBB, TBB, DL, Cond); + return 1; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/insertIndirectBranch.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/insertIndirectBranch.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/insertIndirectBranch.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/insertOutlinedCall.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/insertOutlinedCall.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/insertOutlinedCall.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/isAsCheapAsAMove.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/isAsCheapAsAMove.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/isAsCheapAsAMove.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/isBranchOffsetInRange.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/isBranchOffsetInRange.cpp new file mode 100644 index 0000000000000000000000000000000000000000..387646d147fa990d12248ab10485109553457415 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/isBranchOffsetInRange.cpp @@ -0,0 +1,134 @@ +bool MipsInstrInfo::isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const { + switch (BranchOpc) { + case Mips::B: + case Mips::BAL: + case Mips::BAL_BR: + case Mips::BAL_BR_MM: + case Mips::BC1F: + case Mips::BC1FL: + case Mips::BC1T: + case Mips::BC1TL: + case Mips::BEQ: case Mips::BEQ64: + case Mips::BEQL: + case Mips::BGEZ: case Mips::BGEZ64: + case Mips::BGEZL: + case Mips::BGEZAL: + case Mips::BGEZALL: + case Mips::BGTZ: case Mips::BGTZ64: + case Mips::BGTZL: + case Mips::BLEZ: case Mips::BLEZ64: + case Mips::BLEZL: + case Mips::BLTZ: case Mips::BLTZ64: + case Mips::BLTZL: + case Mips::BLTZAL: + case Mips::BLTZALL: + case Mips::BNE: case Mips::BNE64: + case Mips::BNEL: + return isInt<18>(BrOffset); + case Mips::B_MM: + case Mips::BC1F_MM: + case Mips::BC1T_MM: + case Mips::BEQ_MM: + case Mips::BGEZ_MM: + case Mips::BGEZAL_MM: + case Mips::BGTZ_MM: + case Mips::BLEZ_MM: + case Mips::BLTZ_MM: + case Mips::BLTZAL_MM: + case Mips::BNE_MM: + case Mips::BEQZC_MM: + case Mips::BNEZC_MM: + return isInt<17>(BrOffset); + case Mips::B16_MM: + return isInt<11>(BrOffset); + case Mips::BEQZ16_MM: + case Mips::BNEZ16_MM: + return isInt<8>(BrOffset); + case Mips::BALC: + case Mips::BC: + return isInt<28>(BrOffset); + case Mips::BC1EQZ: + case Mips::BC1NEZ: + case Mips::BC2EQZ: + case Mips::BC2NEZ: + case Mips::BEQC: case Mips::BEQC64: + case Mips::BNEC: case Mips::BNEC64: + case Mips::BGEC: case Mips::BGEC64: + case Mips::BGEUC: case Mips::BGEUC64: + case Mips::BGEZC: case Mips::BGEZC64: + case Mips::BGTZC: case Mips::BGTZC64: + case Mips::BLEZC: case Mips::BLEZC64: + case Mips::BLTC: case Mips::BLTC64: + case Mips::BLTUC: case Mips::BLTUC64: + case Mips::BLTZC: case Mips::BLTZC64: + case Mips::BNVC: + case Mips::BOVC: + case Mips::BGEZALC: + case Mips::BEQZALC: + case Mips::BGTZALC: + case Mips::BLEZALC: + case Mips::BLTZALC: + case Mips::BNEZALC: + return isInt<18>(BrOffset); + case Mips::BEQZC: case Mips::BEQZC64: + case Mips::BNEZC: case Mips::BNEZC64: + return isInt<23>(BrOffset); + case Mips::BC16_MMR6: + return isInt<11>(BrOffset); + case Mips::BEQZC16_MMR6: + case Mips::BNEZC16_MMR6: + return isInt<8>(BrOffset); + case Mips::BALC_MMR6: + case Mips::BC_MMR6: + return isInt<27>(BrOffset); + case Mips::BC1EQZC_MMR6: + case Mips::BC1NEZC_MMR6: + case Mips::BC2EQZC_MMR6: + case Mips::BC2NEZC_MMR6: + case Mips::BGEZALC_MMR6: + case Mips::BEQZALC_MMR6: + case Mips::BGTZALC_MMR6: + case Mips::BLEZALC_MMR6: + case Mips::BLTZALC_MMR6: + case Mips::BNEZALC_MMR6: + case Mips::BNVC_MMR6: + case Mips::BOVC_MMR6: + return isInt<17>(BrOffset); + case Mips::BEQC_MMR6: + case Mips::BNEC_MMR6: + case Mips::BGEC_MMR6: + case Mips::BGEUC_MMR6: + case Mips::BGEZC_MMR6: + case Mips::BGTZC_MMR6: + case Mips::BLEZC_MMR6: + case Mips::BLTC_MMR6: + case Mips::BLTUC_MMR6: + case Mips::BLTZC_MMR6: + return isInt<18>(BrOffset); + case Mips::BEQZC_MMR6: + case Mips::BNEZC_MMR6: + return isInt<23>(BrOffset); + case Mips::BPOSGE32: + return isInt<18>(BrOffset); + case Mips::BPOSGE32_MM: + case Mips::BPOSGE32C_MMR3: + return isInt<17>(BrOffset); + case Mips::BBIT0: + case Mips::BBIT032: + case Mips::BBIT1: + case Mips::BBIT132: + return isInt<18>(BrOffset); + case Mips::BZ_B: + case Mips::BZ_H: + case Mips::BZ_W: + case Mips::BZ_D: + case Mips::BZ_V: + case Mips::BNZ_B: + case Mips::BNZ_H: + case Mips::BNZ_W: + case Mips::BNZ_D: + case Mips::BNZ_V: + return isInt<18>(BrOffset); + } + llvm_unreachable("Unknown branch instruction!"); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/isCopyInstrImpl.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/isCopyInstrImpl.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fcd4b976e92def26b6c872ee0f07b832132ded3e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/isCopyInstrImpl.cpp @@ -0,0 +1,17 @@ +Optional MipsSEInstrInfo::isCopyInstrImpl(const MachineInstr &MI) const { + bool isDSPControlWrite = false; + if (isReadOrWriteToDSPReg(MI, isDSPControlWrite)) { + if (!MI.getOperand(1).isImm() || MI.getOperand(1).getImm() != (1 << 4)) + return None; + else if (isDSPControlWrite) { + return DestSourcePair{MI.getOperand(2), MI.getOperand(0)}; + } + else { + return DestSourcePair{MI.getOperand(0), MI.getOperand(2)}; + } + } + else if (MI.isMoveReg() || isORCopyInst(MI)) { + return DestSourcePair{MI.getOperand(0), MI.getOperand(1)}; + } + return None; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/isFunctionSafeToOutlineFrom.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/isFunctionSafeToOutlineFrom.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/isFunctionSafeToOutlineFrom.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/isLoadFromStackSlot.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/isLoadFromStackSlot.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e2d8d63900cd69f173695b130359cfe1d18aa693 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/isLoadFromStackSlot.cpp @@ -0,0 +1,10 @@ +unsigned MipsSEInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const { + unsigned Opc = MI.getOpcode(); + if ((Opc == Mips::LW) || (Opc == Mips::LD) || (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) { + if ((MI.getOperand(1).isFI()) && (MI.getOperand(2).isImm()) && (isZeroImm(MI.getOperand(2)))) { + FrameIndex = MI.getOperand(1).getIndex(); + return MI.getOperand(0).getReg(); + } + } + return 0; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/isMBBSafeToOutlineFrom.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/isMBBSafeToOutlineFrom.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/isMBBSafeToOutlineFrom.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/isStoreToStackSlot.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/isStoreToStackSlot.cpp new file mode 100644 index 0000000000000000000000000000000000000000..049c3f11016793dd29d3fb81bb7172132b37b96d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/isStoreToStackSlot.cpp @@ -0,0 +1,11 @@ +unsigned MipsSEInstrInfo::isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const { + unsigned Opc = MI.getOpcode(); + if ((Opc == Mips::SW) || (Opc == Mips::SD) || (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) { + if ((MI.getOperand(1).isFI()) && (MI.getOperand(2).isImm()) && (isZeroImm(MI.getOperand(2)))) { + FrameIndex = MI.getOperand(1).getIndex(); + return MI.getOperand(0).getReg(); + } + } + return 0; +} + diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/loadRegFromStackSlot.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/loadRegFromStackSlot.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0dbe9a6a32e51bc601900a9635c3d6376933a144 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/loadRegFromStackSlot.cpp @@ -0,0 +1,62 @@ +void MipsSEInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const { + DebugLoc DL; + if (I != MBB.end()) DL = I->getDebugLoc(); + MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad); + unsigned Opc = 0; + const Function &Func = MBB.getParent()->getFunction(); + bool ReqIndirectLoad = Func.hasFnAttribute("interrupt") && (DestReg == Mips::LO0 || DestReg == Mips::LO0_64 || DestReg == Mips::HI0 || DestReg == Mips::HI0_64); + if (Mips::GPR32RegClass.hasSubClassEq(RC)) + Opc = Mips::LW; + else if (Mips::GPR64RegClass.hasSubClassEq(RC)) + Opc = Mips::LD; + else if (Mips::ACC64RegClass.hasSubClassEq(RC)) + Opc = Mips::LOAD_ACC64; + else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC)) + Opc = Mips::LOAD_ACC64DSP; + else if (Mips::ACC128RegClass.hasSubClassEq(RC)) + Opc = Mips::LOAD_ACC128; + else if (Mips::DSPCCRegClass.hasSubClassEq(RC)) + Opc = Mips::LOAD_CCOND_DSP; + else if (Mips::FGR32RegClass.hasSubClassEq(RC)) + Opc = Mips::LWC1; + else if (Mips::AFGR64RegClass.hasSubClassEq(RC)) + Opc = Mips::LDC1; + else if (Mips::FGR64RegClass.hasSubClassEq(RC)) + Opc = Mips::LDC164; + else if (TRI->isTypeLegalForClass(*RC, MVT::v16i8)) + Opc = Mips::LD_B; + else if (TRI->isTypeLegalForClass(*RC, MVT::v8i16) || TRI->isTypeLegalForClass(*RC, MVT::v8f16)) + Opc = Mips::LD_H; + else if (TRI->isTypeLegalForClass(*RC, MVT::v4i32) || TRI->isTypeLegalForClass(*RC, MVT::v4f32)) + Opc = Mips::LD_W; + else if (TRI->isTypeLegalForClass(*RC, MVT::v2i64) || TRI->isTypeLegalForClass(*RC, MVT::v2f64)) + Opc = Mips::LD_D; + else if (Mips::HI32RegClass.hasSubClassEq(RC)) + Opc = Mips::LW; + else if (Mips::HI64RegClass.hasSubClassEq(RC)) + Opc = Mips::LD; + else if (Mips::LO32RegClass.hasSubClassEq(RC)) + Opc = Mips::LW; + else if (Mips::LO64RegClass.hasSubClassEq(RC)) + Opc = Mips::LD; + else if (Mips::DSPRRegClass.hasSubClassEq(RC)) + Opc = Mips::LWDSP; + assert(Opc && "Register class not handled!"); + if (!ReqIndirectLoad) + BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(Offset).addMemOperand(MMO); + else { + unsigned Reg = Mips::K0; + unsigned LdOp = Mips::MTLO; + if (DestReg == Mips::HI0) + LdOp = Mips::MTHI; + if (Subtarget.getABI().ArePtrs64bit()) { + Reg = Mips::K0_64; + if (DestReg == Mips::HI0_64) + LdOp = Mips::MTHI64; + else + LdOp = Mips::MTLO64; + } + BuildMI(MBB, I, DL, get(Opc), Reg).addFrameIndex(FI).addImm(Offset).addMemOperand(MMO); + BuildMI(MBB, I, DL, get(LdOp)).addReg(Reg); + } +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/movImm.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/movImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/movImm.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/parseCondBranch.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/parseCondBranch.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/parseCondBranch.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/removeBranch.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/removeBranch.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cef1e08a42cd47a219a08a7b03df1b62305453b3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/removeBranch.cpp @@ -0,0 +1,17 @@ +unsigned MipsInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved) const { + assert(!BytesRemoved && "code size not handled"); + MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend(); + unsigned removed = 0; + while (I != REnd && removed < 2) { + if (I->isDebugInstr()) { + ++I; + continue; + } + if (!getAnalyzableBrOpc(I->getOpcode())) + break; + I->eraseFromParent(); + I = MBB.rbegin(); + ++removed; + } + return removed; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/reverseBranchCondition.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/reverseBranchCondition.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bf4c73519980083d2273651b2680171851c4d0a1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/reverseBranchCondition.cpp @@ -0,0 +1,5 @@ +bool MipsInstrInfo::reverseBranchCondition(SmallVectorImpl &Cond) const { + assert( (Cond.size() && Cond.size() <= 3) && "Invalid Mips branch condition!"); + Cond[0].setImm(getOppositeBranchOpc(Cond[0].getImm())); + return false; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/storeRegToStackSlot.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/storeRegToStackSlot.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b46bd40f8ae60038cbce551cc210dfdc0d86cc72 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/storeRegToStackSlot.cpp @@ -0,0 +1,10 @@ +void Mips16InstrInfo::storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const { + DebugLoc DL; + if (I != MBB.end()) DL = I->getDebugLoc(); + MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore); + unsigned Opc = 0; + if (Mips::CPU16RegsRegClass.hasSubClassEq(RC)) + Opc = Mips::SwRxSpImmX16; + assert(Opc && "Register class not handled!"); + BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)).addFrameIndex(FI).addImm(Offset).addMemOperand(MMO); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/verifyInstruction.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/verifyInstruction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f4e70d6cfccd0aae1635f5ad95610e11da64d4f0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/InstrInfo/verifyInstruction.cpp @@ -0,0 +1,34 @@ +bool MipsInstrInfo::verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const { + switch (MI.getOpcode()) { + case Mips::EXT: + case Mips::EXT_MM: + case Mips::INS: + case Mips::INS_MM: + case Mips::DINS: + return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 0, 32, 0, 32); + case Mips::DINSM: + return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 1, 64, 32, 64); + case Mips::DINSU: + return verifyInsExtInstruction(MI, ErrInfo, 32, 64, 0, 32, 32, 64); + case Mips::DEXT: + return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 0, 32, 0, 63); + case Mips::DEXTM: + return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 32, 64, 32, 64); + case Mips::DEXTU: + return verifyInsExtInstruction(MI, ErrInfo, 32, 64, 0, 32, 32, 64); + case Mips::TAILCALLREG: + case Mips::PseudoIndirectBranch: + case Mips::JR: + case Mips::JR64: + case Mips::JALR: + case Mips::JALR64: + case Mips::JALRPseudo: + if (!Subtarget.useIndirectJumpsHazard()) + return true; + ErrInfo = "invalid instruction when using jump guards!"; + return false; + default: + return true; + } + return true; +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/MachineFunctionInfo/MachineFunctionInfo.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/MachineFunctionInfo/MachineFunctionInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2f7bafbb1b297ac62ef58faf3ebbc3ba088ae838 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/MachineFunctionInfo/MachineFunctionInfo.cpp @@ -0,0 +1,2 @@ +MipsFunctionInfo(MachineFunction &MF) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/MachineFunctionInfo/getLibCallStackSize.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/MachineFunctionInfo/getLibCallStackSize.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/MachineFunctionInfo/getLibCallStackSize.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/MachineFunctionInfo/getMoveF64FrameIndex.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/MachineFunctionInfo/getMoveF64FrameIndex.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/MachineFunctionInfo/getMoveF64FrameIndex.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/MachineFunctionInfo/getVarArgsFrameIndex.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/MachineFunctionInfo/getVarArgsFrameIndex.cpp new file mode 100644 index 0000000000000000000000000000000000000000..815700881400f3e2610e1d74e0907493d5ea7898 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/MachineFunctionInfo/getVarArgsFrameIndex.cpp @@ -0,0 +1,3 @@ +int getVarArgsFrameIndex() const { + return VarArgsFrameIndex; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/MachineFunctionInfo/getVarArgsSaveSize.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/MachineFunctionInfo/getVarArgsSaveSize.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/MachineFunctionInfo/getVarArgsSaveSize.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/MachineFunctionInfo/setLibCallStackSize.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/MachineFunctionInfo/setLibCallStackSize.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/MachineFunctionInfo/setLibCallStackSize.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/MachineFunctionInfo/setVarArgsFrameIndex.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/MachineFunctionInfo/setVarArgsFrameIndex.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f453600ffb2d2bf1e86883efc8373719fb63f8ae --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/MachineFunctionInfo/setVarArgsFrameIndex.cpp @@ -0,0 +1,3 @@ +void setVarArgsFrameIndex(int Index) { + VarArgsFrameIndex = Index; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/MachineFunctionInfo/setVarArgsSaveSize.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/MachineFunctionInfo/setVarArgsSaveSize.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/MachineFunctionInfo/setVarArgsSaveSize.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/MachineFunctionInfo/useSaveRestoreLibCalls.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/MachineFunctionInfo/useSaveRestoreLibCalls.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/MachineFunctionInfo/useSaveRestoreLibCalls.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/Subtarget.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/Subtarget.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f8dbe9393d5f502927a51bf3bd6e31b2ef5a0ed3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/Subtarget.cpp @@ -0,0 +1,89 @@ +MipsSubtarget::MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS, bool little, const MipsTargetMachine &TM, MaybeAlign StackAlignOverride): MipsGenSubtargetInfo(TT, CPU, CPU, FS), MipsArchVersion(MipsDefault), IsLittle(little), IsSoftFloat(false), IsSingleFloat(false), IsFPXX(false), NoABICalls(false), Abs2008(false), IsFP64bit(false), UseOddSPReg(true), IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false), HasCnMips(false), HasCnMipsP(false), HasMips3_32(false), HasMips3_32r2(false), HasMips4_32(false), HasMips4_32r2(false), HasMips5_32r2(false), InMips16Mode(false), InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false), HasDSPR2(false), HasDSPR3(false), AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16), HasMSA(false), UseTCCInDIV(false), HasSym32(false), HasEVA(false), DisableMadd4(false), HasMT(false), HasCRC(false), HasVirt(false), HasGINV(false), UseIndirectJumpsHazard(false), StackAlignOverride(StackAlignOverride), TM(TM), TargetTriple(TT), TSInfo(), InstrInfo(MipsInstrInfo::create( initializeSubtargetDependencies(CPU, FS, TM))), FrameLowering(MipsFrameLowering::create(*this)), TLInfo(MipsTargetLowering::create(TM, *this)) { + if (MipsArchVersion == MipsDefault) + MipsArchVersion = Mips32; + if (MipsArchVersion == Mips1) + report_fatal_error("Code generation for MIPS-I is not implemented", false); + if (MipsArchVersion == Mips5) + report_fatal_error("Code generation for MIPS-V is not implemented", false); + assert(((!isGP64bit() && isABI_O32()) || (isGP64bit() && (isABI_N32() || isABI_N64()))) && "Invalid Arch & ABI pair."); + if (hasMSA() && !isFP64bit()) + report_fatal_error("MSA requires a 64-bit FPU register file (FR=1 mode). See -mattr=+fp64.", false); + if (isFP64bit() && !hasMips64() && hasMips32() && !hasMips32r2()) + report_fatal_error("FPU with 64-bit registers is not available on MIPS32 pre revision 2. Use -mcpu=mips32r2 or greater."); + if (!isABI_O32() && !useOddSPReg()) + report_fatal_error("-mattr=+nooddspreg requires the O32 ABI.", false); + if (IsFPXX && (isABI_N32() || isABI_N64())) + report_fatal_error("FPXX is not permitted for the N32/N64 ABI's.", false); + if (hasMips64r6() && InMicroMipsMode) + report_fatal_error("microMIPS64R6 is not supported", false); + if (!isABI_O32() && InMicroMipsMode) + report_fatal_error("microMIPS64 is not supported.", false); + if (UseIndirectJumpsHazard) { + if (InMicroMipsMode) + report_fatal_error("cannot combine indirect jumps with hazard barriers and microMIPS"); + if (!hasMips32r2()) + report_fatal_error("indirect jumps with hazard barriers requires MIPS32R2 or later"); + } + if (inAbs2008Mode() && hasMips32() && !hasMips32r2()) { + report_fatal_error("IEEE 754-2008 abs.fmt is not supported for the given architecture.", false); + } + if (hasMips32r6()) { + StringRef ISA = hasMips64r6() ? "MIPS64r6" : "MIPS32r6"; + assert(isFP64bit()); + assert(isNaN2008()); + assert(inAbs2008Mode()); + if (hasDSP()) + report_fatal_error(ISA + " is not compatible with the DSP ASE", false); + } + if (NoABICalls && TM.isPositionIndependent()) + report_fatal_error("position-independent code requires '-mabicalls'"); + if (isABI_N64() && !TM.isPositionIndependent() && !hasSym32()) + NoABICalls = true; + UseSmallSection = GPOpt; + if (!NoABICalls && GPOpt) { + errs() << "warning: cannot use small-data accesses for '-mabicalls'" << "\n"; + UseSmallSection = false; + } + if (hasDSPR2() && !DspWarningPrinted) { + if (hasMips64() && !hasMips64r2()) { + errs() << "warning: the 'dspr2' ASE requires MIPS64 revision 2 or " << "greater\n"; + DspWarningPrinted = true; + } + else if (hasMips32() && !hasMips32r2()) { + errs() << "warning: the 'dspr2' ASE requires MIPS32 revision 2 or " << "greater\n"; + DspWarningPrinted = true; + } + } + else if (hasDSP() && !DspWarningPrinted) { + if (hasMips64() && !hasMips64r2()) { + errs() << "warning: the 'dsp' ASE requires MIPS64 revision 2 or " << "greater\n"; + DspWarningPrinted = true; + } + else if (hasMips32() && !hasMips32r2()) { + errs() << "warning: the 'dsp' ASE requires MIPS32 revision 2 or " << "greater\n"; + DspWarningPrinted = true; + } + } + StringRef ArchName = hasMips64() ? "MIPS64" : "MIPS32"; + if (!hasMips32r5() && hasMSA() && !MSAWarningPrinted) { + errs() << "warning: the 'msa' ASE requires " << ArchName << " revision 5 or greater\n"; + MSAWarningPrinted = true; + } + if (!hasMips32r5() && hasVirt() && !VirtWarningPrinted) { + errs() << "warning: the 'virt' ASE requires " << ArchName << " revision 5 or greater\n"; + VirtWarningPrinted = true; + } + if (!hasMips32r6() && hasCRC() && !CRCWarningPrinted) { + errs() << "warning: the 'crc' ASE requires " << ArchName << " revision 6 or greater\n"; + CRCWarningPrinted = true; + } + if (!hasMips32r6() && hasGINV() && !GINVWarningPrinted) { + errs() << "warning: the 'ginv' ASE requires " << ArchName << " revision 6 or greater\n"; + GINVWarningPrinted = true; + } + CallLoweringInfo.reset(new MipsCallLowering(*getTargetLowering())); + Legalizer.reset(new MipsLegalizerInfo(*this)); + auto *RBI = new MipsRegisterBankInfo(*getRegisterInfo()); + RegBankInfo.reset(RBI); + InstSelector.reset(createMipsInstructionSelector(*static_cast(&TM), *this, *RBI)); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/anchor.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/anchor.cpp new file mode 100644 index 0000000000000000000000000000000000000000..436736c15924b75b84b927d41c944ede3edceaa0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/anchor.cpp @@ -0,0 +1,2 @@ +void MipsSubtarget::anchor() { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/enableLinkerRelax.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/enableLinkerRelax.cpp new file mode 100644 index 0000000000000000000000000000000000000000..430d9de4ff5dc9452edc2d5d727d8f5bf4687563 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/enableLinkerRelax.cpp @@ -0,0 +1,3 @@ +bool MipsSubtarget::enablePostRAScheduler() const { + return true; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/enableMachineScheduler.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/enableMachineScheduler.cpp new file mode 100644 index 0000000000000000000000000000000000000000..430d9de4ff5dc9452edc2d5d727d8f5bf4687563 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/enableMachineScheduler.cpp @@ -0,0 +1,3 @@ +bool MipsSubtarget::enablePostRAScheduler() const { + return true; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/enableRVCHintInstrs.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/enableRVCHintInstrs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..430d9de4ff5dc9452edc2d5d727d8f5bf4687563 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/enableRVCHintInstrs.cpp @@ -0,0 +1,3 @@ +bool MipsSubtarget::enablePostRAScheduler() const { + return true; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/enableSaveRestore.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/enableSaveRestore.cpp new file mode 100644 index 0000000000000000000000000000000000000000..430d9de4ff5dc9452edc2d5d727d8f5bf4687563 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/enableSaveRestore.cpp @@ -0,0 +1,3 @@ +bool MipsSubtarget::enablePostRAScheduler() const { + return true; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/getCallLowering.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/getCallLowering.cpp new file mode 100644 index 0000000000000000000000000000000000000000..aa3fad473e1b3246c8f94087b5fbbd169058d219 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/getCallLowering.cpp @@ -0,0 +1,3 @@ +const CallLowering *MipsSubtarget::getCallLowering() const { + return CallLoweringInfo.get(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/getFrameLowering.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/getFrameLowering.cpp new file mode 100644 index 0000000000000000000000000000000000000000..46facc9d53d8ed20463a68f1486618473e216322 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/getFrameLowering.cpp @@ -0,0 +1,3 @@ +const TargetFrameLowering *getFrameLowering() const override { + return FrameLowering.get(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/getInstrInfo.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/getInstrInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e800e2a8b4f1864f21678597f1942ae03a8a6ab2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/getInstrInfo.cpp @@ -0,0 +1,3 @@ +const MipsInstrInfo *getInstrInfo() const override { + return InstrInfo.get(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/getInstructionSelector.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/getInstructionSelector.cpp new file mode 100644 index 0000000000000000000000000000000000000000..62e906d17d51ea4764241fa71a10f28d9159bfbd --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/getInstructionSelector.cpp @@ -0,0 +1,3 @@ +InstructionSelector *MipsSubtarget::getInstructionSelector() const { + return InstSelector.get(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/getLegalizerInfo.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/getLegalizerInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fe91271b193b048bfbdd2a0096116ff7350be978 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/getLegalizerInfo.cpp @@ -0,0 +1,3 @@ +const LegalizerInfo *MipsSubtarget::getLegalizerInfo() const { + return Legalizer.get(); +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/getRegBankInfo.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/getRegBankInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a5417d779e8304c5adaad1f053b6982c7a2dcd37 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/getRegBankInfo.cpp @@ -0,0 +1,3 @@ +const RegisterBankInfo *MipsSubtarget::getRegBankInfo() const { + return RegBankInfo.get(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/getRegisterInfo.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/getRegisterInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..70e4b467269f9a62a119d78ba8756d15153967e2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/getRegisterInfo.cpp @@ -0,0 +1,3 @@ +const MipsRegisterInfo *getRegisterInfo() const override { + return &InstrInfo->getRegisterInfo(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/getSelectionDAGInfo.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/getSelectionDAGInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d9cec09b2f3127f3d36917798ff8d808237620f9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/getSelectionDAGInfo.cpp @@ -0,0 +1,3 @@ +const SelectionDAGTargetInfo *getSelectionDAGInfo() const override { + return &TSInfo; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/getTargetABI.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/getTargetABI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/getTargetABI.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/getTargetLowering.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/getTargetLowering.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f6a80a497f8d2bee84fc660d8e8cdfcfe7048369 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/getTargetLowering.cpp @@ -0,0 +1,3 @@ +const MipsTargetLowering *getTargetLowering() const override { + return TLInfo.get(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/getXLen.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/getXLen.cpp new file mode 100644 index 0000000000000000000000000000000000000000..619cc9eaf53f1510ccde851e748b819574304f6d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/getXLen.cpp @@ -0,0 +1,3 @@ +MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override { + return MVT::i32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/getXLenVT.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/getXLenVT.cpp new file mode 100644 index 0000000000000000000000000000000000000000..619cc9eaf53f1510ccde851e748b819574304f6d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/getXLenVT.cpp @@ -0,0 +1,3 @@ +MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override { + return MVT::i32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtA.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtA.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtA.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtB.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtB.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtB.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtC.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtC.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtD.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtD.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtD.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtF.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtF.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtF.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtM.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtM.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtM.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtV.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtV.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtV.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtZba.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtZba.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtZba.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtZbb.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtZbb.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtZbb.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtZbc.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtZbc.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtZbc.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtZbe.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtZbe.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtZbe.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtZbf.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtZbf.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtZbf.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtZbm.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtZbm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtZbm.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtZbp.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtZbp.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtZbp.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtZbproposedc.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtZbproposedc.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtZbproposedc.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtZbr.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtZbr.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtZbr.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtZbs.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtZbs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtZbs.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtZbt.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtZbt.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtZbt.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtZfh.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtZfh.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtZfh.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtZvamo.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtZvamo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtZvamo.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtZvlsseg.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtZvlsseg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adfcb499f53835d900b7597d97c88f12f4336b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/hasStdExtZvlsseg.cpp @@ -0,0 +1,3 @@ +bool hasMips4_32() const { + return HasMips4_32; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/initializeSubtargetDependencies.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/initializeSubtargetDependencies.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a9e9e37c3feac2354466675ef429eee1bf53c525 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/initializeSubtargetDependencies.cpp @@ -0,0 +1,18 @@ +MipsSubtarget &MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS, const TargetMachine &TM) { + StringRef CPUName = MIPS_MC::selectMipsCPU(TM.getTargetTriple(), CPU); + ParseSubtargetFeatures(CPUName, CPUName, FS); + InstrItins = getInstrItineraryForCPU(CPUName); + if (InMips16Mode && !IsSoftFloat) + InMips16HardFloat = true; + if (StackAlignOverride) + stackAlignment = *StackAlignOverride; + else if (isABI_N32() || isABI_N64()) + stackAlignment = Align(16); + else { + assert(isABI_O32() && "Unknown ABI for stack alignment!"); + stackAlignment = Align(8); + } + if ((isABI_N32() || isABI_N64()) && !isGP64bit()) + report_fatal_error("64-bit code requested on a subtarget that doesn't support it!"); + return *this; +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/is64Bit.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/is64Bit.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b2d28ef868387af51863de445769ffa8d848320d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/is64Bit.cpp @@ -0,0 +1,3 @@ +bool isPTR64bit() const { + return IsPTR64bit; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/isRV32E.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/isRV32E.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1f93561d2032e25cd18ca3d71c412c8891819cf5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/isRV32E.cpp @@ -0,0 +1,3 @@ +bool isGP32bit() const { + return !IsGP64bit; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/isRegisterReservedByUser.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/isRegisterReservedByUser.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/Subtarget/isRegisterReservedByUser.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetInfo/LLVMInitializeTargetInfo.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetInfo/LLVMInitializeTargetInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..aa19b102fcb9d571a36a08f83de9e63d0dad45af --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetInfo/LLVMInitializeTargetInfo.cpp @@ -0,0 +1,6 @@ +extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMipsTargetInfo() { + RegisterTarget X(getTheMipsTarget(), "mips", "MIPS (32-bit big endian)", "Mips"); + RegisterTarget Y(getTheMipselTarget(), "mipsel", "MIPS (32-bit little endian)", "Mips"); + RegisterTarget A(getTheMips64Target(), "mips64", "MIPS (64-bit big endian)", "Mips"); + RegisterTarget B(getTheMips64elTarget(), "mips64el", "MIPS (64-bit little endian)","Mips"); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetInfo/getThe32Target.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetInfo/getThe32Target.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d029fee31d59b7b7e4c2d46eb1753cc207e1a386 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetInfo/getThe32Target.cpp @@ -0,0 +1,4 @@ +Target &llvm::getTheMipsTarget() { + static Target TheMipsTarget; + return TheMipsTarget; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetInfo/getThe64Target.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetInfo/getThe64Target.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a203a8b0cb4ad6485ee57f457ac01c93bb38bca7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetInfo/getThe64Target.cpp @@ -0,0 +1,4 @@ +Target &llvm::getTheMips64Target() { + static Target TheMips64Target; + return TheMips64Target; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/LLVMInitializeTarget.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/LLVMInitializeTarget.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cebec48b8e7e252d90044f50cbef0210c65c5fa2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/LLVMInitializeTarget.cpp @@ -0,0 +1,13 @@ +extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMipsTarget() { + RegisterTargetMachine X(getTheMipsTarget()); + RegisterTargetMachine Y(getTheMipselTarget()); + RegisterTargetMachine A(getTheMips64Target()); + RegisterTargetMachine B(getTheMips64elTarget()); + PassRegistry *PR = PassRegistry::getPassRegistry(); + initializeGlobalISel(*PR); + initializeMipsDelaySlotFillerPass(*PR); + initializeMipsBranchExpansionPass(*PR); + initializeMicroMipsSizeReducePass(*PR); + initializeMipsPreLegalizerCombinerPass(*PR); +} + diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/PassConfig.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/PassConfig.cpp new file mode 100644 index 0000000000000000000000000000000000000000..20da95a9d216fe1c9fd7a5ecdd41da237b1d474b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/PassConfig.cpp @@ -0,0 +1,3 @@ +MipsPassConfig(MipsTargetMachine &TM, PassManagerBase &PM) : TargetPassConfig(TM, PM) { + EnableTailMerge = !getMipsSubtarget().enableLongBranchPass(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/TargetMachine.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/TargetMachine.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bb7a4b12d46b90e267a11d089bac3205f01c869d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/TargetMachine.cpp @@ -0,0 +1,5 @@ +MipsTargetMachine::MipsTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional RM, Optional CM, CodeGenOpt::Level OL, bool JIT, bool isLittle) : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT, CPU, FS, Options, getEffectiveRelocModel(JIT, RM), getEffectiveCodeModel(CM, CodeModel::Small), OL), isLittle(isLittle), TLOF(std::make_unique()), ABI(MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions)), Subtarget(nullptr), DefaultSubtarget(TT, CPU, FS, isLittle, *this, MaybeAlign(Options.StackAlignmentOverride)), NoMips16Subtarget(TT, CPU, FS.empty() ? "-mips16" : FS.str() + ",-mips16", isLittle, *this, MaybeAlign(Options.StackAlignmentOverride)), Mips16Subtarget(TT, CPU, FS.empty() ? "+mips16" : FS.str() + ",+mips16", isLittle, *this, MaybeAlign(Options.StackAlignmentOverride)) { + Subtarget = &DefaultSubtarget; + initAsmInfo(); + setSupportsDebugEntryValues(true); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/addGlobalInstructionSelect.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/addGlobalInstructionSelect.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8a5d768ad0a3e96bbc37e8565f6c69e6eb507228 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/addGlobalInstructionSelect.cpp @@ -0,0 +1,4 @@ +bool MipsPassConfig::addGlobalInstructionSelect() { + addPass(new InstructionSelect()); + return false; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/addIRPasses.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/addIRPasses.cpp new file mode 100644 index 0000000000000000000000000000000000000000..33f91a1a415e698013c6df506516503925f5c3c5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/addIRPasses.cpp @@ -0,0 +1,8 @@ +void MipsPassConfig::addIRPasses() { + TargetPassConfig::addIRPasses(); + addPass(createAtomicExpandPass()); + if (getMipsSubtarget().os16()) + addPass(createMipsOs16Pass()); + if (getMipsSubtarget().inMips16HardFloat()) + addPass(createMips16HardFloatPass()); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/addIRTranslator.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/addIRTranslator.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4a41c67c0603be6e9b5672f4fc565ac21ee5ce3e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/addIRTranslator.cpp @@ -0,0 +1,4 @@ +bool MipsPassConfig::addIRTranslator() { + addPass(new IRTranslator(getOptLevel())); + return false; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/addInstSelector.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/addInstSelector.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fed7400583c9fc2fb0ebb7485b3e4058b93f7c8b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/addInstSelector.cpp @@ -0,0 +1,6 @@ +bool MipsPassConfig::addInstSelector() { + addPass(createMipsModuleISelDagPass()); + addPass(createMips16ISelDag(getMipsTargetMachine(), getOptLevel())); + addPass(createMipsSEISelDag(getMipsTargetMachine(), getOptLevel())); + return false; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/addLegalizeMachineIR.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/addLegalizeMachineIR.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4c0f208a88cac1846e74f7f3e819d7d6bf6406f4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/addLegalizeMachineIR.cpp @@ -0,0 +1,4 @@ +bool MipsPassConfig::addLegalizeMachineIR() { + addPass(new Legalizer()); + return false; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/addPreEmitPass.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/addPreEmitPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..06d033e3b1fed3f9944e982215833add08185065 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/addPreEmitPass.cpp @@ -0,0 +1,7 @@ +void MipsPassConfig::addPreEmitPass() { + addPass(createMipsExpandPseudoPass()); + addPass(createMicroMipsSizeReducePass()); + addPass(createMipsDelaySlotFillerPass()); + addPass(createMipsBranchExpansion()); + addPass(createMipsConstantIslandPass()); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/addPreEmitPass2.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/addPreEmitPass2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..06d033e3b1fed3f9944e982215833add08185065 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/addPreEmitPass2.cpp @@ -0,0 +1,7 @@ +void MipsPassConfig::addPreEmitPass() { + addPass(createMipsExpandPseudoPass()); + addPass(createMicroMipsSizeReducePass()); + addPass(createMipsDelaySlotFillerPass()); + addPass(createMipsBranchExpansion()); + addPass(createMipsConstantIslandPass()); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/addPreRegAlloc.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/addPreRegAlloc.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d4fd1e966f2f6f1aa1e1720c3be90df4ac59f83e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/addPreRegAlloc.cpp @@ -0,0 +1,3 @@ +void MipsPassConfig::addPreRegAlloc() { + addPass(createMipsOptimizePICCallPass()); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/addPreSched2.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/addPreSched2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/addPreSched2.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/addRegBankSelect.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/addRegBankSelect.cpp new file mode 100644 index 0000000000000000000000000000000000000000..496fa0d237ac7a067970ee6482c4710e8643aa15 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/addRegBankSelect.cpp @@ -0,0 +1,4 @@ +bool MipsPassConfig::addRegBankSelect() { + addPass(new RegBankSelect()); + return false; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/computeDataLayout.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/computeDataLayout.cpp new file mode 100644 index 0000000000000000000000000000000000000000..779e0541abcede80b44734c783ecdbab4e2a47ea --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/computeDataLayout.cpp @@ -0,0 +1,20 @@ +static std::string computeDataLayout(const Triple &TT, StringRef CPU, const TargetOptions &Options, bool isLittle) { + std::string Ret; + MipsABIInfo ABI = MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions); + if (isLittle) + Ret += "e"; + else + Ret += "E"; + if (ABI.IsO32()) + Ret += "-m:m"; + else + Ret += "-m:e"; + if (!ABI.IsN64()) + Ret += "-p:32:32"; + Ret += "-i8:8:32-i16:16:32-i64:64"; + if (ABI.IsN64() || ABI.IsN32()) + Ret += "-n32:64-S128"; + else + Ret += "-n32-S64"; + return Ret; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/createPassConfig.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/createPassConfig.cpp new file mode 100644 index 0000000000000000000000000000000000000000..28c6d90decc8dea3f4e8ff897e48ef6d66908345 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/createPassConfig.cpp @@ -0,0 +1,3 @@ +TargetPassConfig *MipsTargetMachine::createPassConfig(PassManagerBase &PM) { + return new MipsPassConfig(*this, PM); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/getEffectiveRelocModel.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/getEffectiveRelocModel.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5e25a02cd5a11b44924270ee2dfbdb9e9292cf63 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/getEffectiveRelocModel.cpp @@ -0,0 +1,5 @@ +static Reloc::Model getEffectiveRelocModel(bool JIT, Optional RM) { + if (!RM.hasValue() || JIT) + return Reloc::Static; + return *RM; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/getObjFileLowering.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/getObjFileLowering.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c1c1365ba51f49fb7fb122c5b7afd2635513e01d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/getObjFileLowering.cpp @@ -0,0 +1,3 @@ +TargetLoweringObjectFile *getObjFileLowering() const override { + return TLOF.get(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/getSubtargetImpl.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/getSubtargetImpl.cpp new file mode 100644 index 0000000000000000000000000000000000000000..72a6aa9b0b63f9e9fcc02d673c5a32c466330d21 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/getSubtargetImpl.cpp @@ -0,0 +1,27 @@ +const MipsSubtarget *MipsTargetMachine::getSubtargetImpl(const Function &F) const { + Attribute CPUAttr = F.getFnAttribute("target-cpu"); + Attribute FSAttr = F.getFnAttribute("target-features"); + std::string CPU = CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU; + std::string FS = FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS; + bool hasMips16Attr = F.getFnAttribute("mips16").isValid(); + bool hasNoMips16Attr = F.getFnAttribute("nomips16").isValid(); + bool HasMicroMipsAttr = F.getFnAttribute("micromips").isValid(); + bool HasNoMicroMipsAttr = F.getFnAttribute("nomicromips").isValid(); + bool softFloat = F.hasFnAttribute("use-soft-float") && F.getFnAttribute("use-soft-float").getValueAsString() == "true"; + if (hasMips16Attr) + FS += FS.empty() ? "+mips16" : ",+mips16"; + else if (hasNoMips16Attr) + FS += FS.empty() ? "-mips16" : ",-mips16"; + if (HasMicroMipsAttr) + FS += FS.empty() ? "+micromips" : ",+micromips"; + else if (HasNoMicroMipsAttr) + FS += FS.empty() ? "-micromips" : ",-micromips"; + if (softFloat) + FS += FS.empty() ? "+soft-float" : ",+soft-float"; + auto &I = SubtargetMap[CPU + FS]; + if (!I) { + resetTargetOptions(F); + I = std::make_unique(TargetTriple, CPU, FS, isLittle, *this, MaybeAlign(Options.StackAlignmentOverride)); + } + return I.get(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/getTargetMachine.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/getTargetMachine.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3dc48d3b86556ea44b4a72126e4ab9c2dde73782 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/getTargetMachine.cpp @@ -0,0 +1,3 @@ +MipsTargetMachine &getMipsTargetMachine() const { + return getTM(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/getTargetTransformInfo.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/getTargetTransformInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..65f11723367b31e66f2c9629d33d19297544e2f8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/getTargetTransformInfo.cpp @@ -0,0 +1,8 @@ +TargetTransformInfo MipsTargetMachine::getTargetTransformInfo(const Function &F) { + if (Subtarget->allowMixed16_32()) { + LLVM_DEBUG(errs() << "No Target Transform Info Pass Added\n"); + return TargetTransformInfo(F.getParent()->getDataLayout()); + } + LLVM_DEBUG(errs() << "Target Transform Info Pass Added\n"); + return TargetTransformInfo(BasicTTIImpl(this, F)); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/isNoopAddrSpaceCast.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/isNoopAddrSpaceCast.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e50de996547528d432f64de320d37eb30e46f396 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetMachine/isNoopAddrSpaceCast.cpp @@ -0,0 +1,3 @@ +bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override { + return SrcAS < 256 && DestAS < 256; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetObjectFile/Initialize.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetObjectFile/Initialize.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a0d8533856448921babe3c7b5cab65e7ceeebca3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetObjectFile/Initialize.cpp @@ -0,0 +1,6 @@ +void MipsTargetObjectFile::Initialize(MCContext &Ctx, const TargetMachine &TM){ + TargetLoweringObjectFileELF::Initialize(Ctx, TM); + SmallDataSection = getContext().getELFSection(".sdata", ELF::SHT_PROGBITS, ELF::SHF_WRITE | ELF::SHF_ALLOC | ELF::SHF_MIPS_GPREL); + SmallBSSSection = getContext().getELFSection(".sbss", ELF::SHT_NOBITS, ELF::SHF_WRITE | ELF::SHF_ALLOC | ELF::SHF_MIPS_GPREL); + this->TM = &static_cast(TM); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetObjectFile/SelectSectionForGlobal.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetObjectFile/SelectSectionForGlobal.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bcb179748f251dd885c72ec65ea012aa51523e27 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetObjectFile/SelectSectionForGlobal.cpp @@ -0,0 +1,12 @@ +MCSection *MipsTargetObjectFile::SelectSectionForGlobal(const GlobalObject *GO, SectionKind Kind, const TargetMachine &TM) const { + if (Kind.isBSS() && IsGlobalInSmallSection(GO, TM, Kind)) { + return SmallBSSSection; + } + if (Kind.isData() && IsGlobalInSmallSection(GO, TM, Kind)) { + return SmallDataSection; + } + if (Kind.isReadOnly() && IsGlobalInSmallSection(GO, TM, Kind)) { + return SmallDataSection; + } + return TargetLoweringObjectFileELF::SelectSectionForGlobal(GO, Kind, TM); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetObjectFile/getModuleMetadata.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetObjectFile/getModuleMetadata.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetObjectFile/getModuleMetadata.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetObjectFile/getSectionForConstant.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetObjectFile/getSectionForConstant.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2aa9fc13963d18be314c20bb620b4fea6a394505 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetObjectFile/getSectionForConstant.cpp @@ -0,0 +1,5 @@ +MCSection *MipsTargetObjectFile::getSectionForConstant(const DataLayout &DL, SectionKind Kind, const Constant *C, Align &Alignment) const { + if (IsConstantInSmallSection(DL, C, *TM)) + return SmallDataSection; + return TargetLoweringObjectFileELF::getSectionForConstant(DL, Kind, C, Alignment); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetObjectFile/isConstantInSmallSection.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetObjectFile/isConstantInSmallSection.cpp new file mode 100644 index 0000000000000000000000000000000000000000..58b216236a3eef9c2fcf8becb5197f101875eb40 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetObjectFile/isConstantInSmallSection.cpp @@ -0,0 +1,3 @@ +bool MipsTargetObjectFile::IsConstantInSmallSection(const DataLayout &DL, const Constant *CN, const TargetMachine &TM) const { + return (static_cast(TM).getSubtargetImpl()->useSmallSection() && LocalSData && IsInSmallSection(DL.getTypeAllocSize(CN->getType()))); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetObjectFile/isGlobalInSmallSection.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetObjectFile/isGlobalInSmallSection.cpp new file mode 100644 index 0000000000000000000000000000000000000000..69f774302db816d7d0bc6b0b821abfc8a844636a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetObjectFile/isGlobalInSmallSection.cpp @@ -0,0 +1,5 @@ +bool MipsTargetObjectFile::IsGlobalInSmallSection(const GlobalObject *GO, const TargetMachine &TM) const { + if (GO->isDeclaration() || GO->hasAvailableExternallyLinkage()) + return IsGlobalInSmallSectionImpl(GO, TM); + return IsGlobalInSmallSection(GO, TM, getKindForGlobal(GO, TM)); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetObjectFile/isInSmallSection.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetObjectFile/isInSmallSection.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3bf6ffdc320b495882842e7acb341a1969b06a0c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetObjectFile/isInSmallSection.cpp @@ -0,0 +1,3 @@ +static bool IsInSmallSection(uint64_t Size) { + return Size > 0 && Size <= SSThreshold; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetTransformInfo/TTIImpl.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetTransformInfo/TTIImpl.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetTransformInfo/TTIImpl.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetTransformInfo/getIntImmCost.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetTransformInfo/getIntImmCost.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetTransformInfo/getIntImmCost.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetTransformInfo/getIntImmCostInst.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetTransformInfo/getIntImmCostInst.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetTransformInfo/getIntImmCostInst.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetTransformInfo/getIntImmCostIntrin.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetTransformInfo/getIntImmCostIntrin.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetTransformInfo/getIntImmCostIntrin.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetTransformInfo/getST.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetTransformInfo/getST.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetTransformInfo/getST.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetTransformInfo/getTLI.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetTransformInfo/getTLI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Scheduling/TargetTransformInfo/getTLI.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/CallLowering/CallLowering.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/CallLowering/CallLowering.cpp new file mode 100644 index 0000000000000000000000000000000000000000..90829bbc2f32e1f7018b1e63e73338c2bb6df8d3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/CallLowering/CallLowering.cpp @@ -0,0 +1,2 @@ +MipsCallLowering::MipsCallLowering(const MipsTargetLowering &TLI) : CallLowering(&TLI) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/CallLowering/lowerCall.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/CallLowering/lowerCall.cpp new file mode 100644 index 0000000000000000000000000000000000000000..99874c4d2466cbcdbe62fc4abe7ad4b4a0994fb8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/CallLowering/lowerCall.cpp @@ -0,0 +1,95 @@ +bool MipsCallLowering::lowerCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info) const { + if (Info.CallConv != CallingConv::C) + return false; + for (auto &Arg : Info.OrigArgs) { + if (!isSupportedArgumentType(Arg.Ty)) + return false; + if (Arg.Flags[0].isByVal()) + return false; + if (Arg.Flags[0].isSRet() && !Arg.Ty->isPointerTy()) + return false; + } + if (!Info.OrigRet.Ty->isVoidTy() && !isSupportedReturnType(Info.OrigRet.Ty)) + return false; + MachineFunction &MF = MIRBuilder.getMF(); + const Function &F = MF.getFunction(); + const DataLayout &DL = MF.getDataLayout(); + const MipsTargetLowering &TLI = *getTLI(); + const MipsTargetMachine &TM = static_cast(MF.getTarget()); + const MipsABIInfo &ABI = TM.getABI(); + MachineInstrBuilder CallSeqStart = MIRBuilder.buildInstr(Mips::ADJCALLSTACKDOWN); + const bool IsCalleeGlobalPIC = Info.Callee.isGlobal() && TM.isPositionIndependent(); + MachineInstrBuilder MIB = MIRBuilder.buildInstrNoInsert(Info.Callee.isReg() || IsCalleeGlobalPIC ? Mips::JALRPseudo : Mips::JAL); + MIB.addDef(Mips::SP, RegState::Implicit); + if (IsCalleeGlobalPIC) { + Register CalleeReg = MF.getRegInfo().createGenericVirtualRegister(LLT::pointer(0, 32)); + MachineInstr *CalleeGlobalValue = MIRBuilder.buildGlobalValue(CalleeReg, Info.Callee.getGlobal()); + if (!Info.Callee.getGlobal()->hasLocalLinkage()) + CalleeGlobalValue->getOperand(1).setTargetFlags(MipsII::MO_GOT_CALL); + MIB.addUse(CalleeReg); + } + else + MIB.add(Info.Callee); + const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); + MIB.addRegMask(TRI->getCallPreservedMask(MF, F.getCallingConv())); + TargetLowering::ArgListTy FuncOrigArgs; + FuncOrigArgs.reserve(Info.OrigArgs.size()); + SmallVector ArgInfos; + SmallVector OrigArgIndices; + unsigned i = 0; + for (auto &Arg : Info.OrigArgs) { + TargetLowering::ArgListEntry Entry; + Entry.Ty = Arg.Ty; + FuncOrigArgs.push_back(Entry); + ArgInfos.push_back(Arg); + OrigArgIndices.push_back(i); + ++i; + } + SmallVector Outs; + subTargetRegTypeForCallingConv(F, ArgInfos, OrigArgIndices, Outs); + SmallVector ArgLocs; + bool IsCalleeVarArg = false; + if (Info.Callee.isGlobal()) { + const Function *CF = static_cast(Info.Callee.getGlobal()); + IsCalleeVarArg = CF->isVarArg(); + } + MipsCCState CCInfo(F.getCallingConv(), IsCalleeVarArg, MF, ArgLocs, F.getContext()); + CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(Info.CallConv), Align(1)); + const char *Call = Info.Callee.isSymbol() ? Info.Callee.getSymbolName() : nullptr; + CCInfo.AnalyzeCallOperands(Outs, TLI.CCAssignFnForCall(), FuncOrigArgs, Call); + setLocInfo(ArgLocs, Outs); + MipsOutgoingValueHandler RetHandler(MIRBuilder, MF.getRegInfo(), MIB); + if (!RetHandler.handle(ArgLocs, ArgInfos)) { + return false; + } + unsigned NextStackOffset = CCInfo.getNextStackOffset(); + const TargetFrameLowering *TFL = MF.getSubtarget().getFrameLowering(); + unsigned StackAlignment = TFL->getStackAlignment(); + NextStackOffset = alignTo(NextStackOffset, StackAlignment); + CallSeqStart.addImm(NextStackOffset).addImm(0); + if (IsCalleeGlobalPIC) { + MIRBuilder.buildCopy(Register(Mips::GP), MF.getInfo()->getGlobalBaseRegForGlobalISel(MF)); + MIB.addDef(Mips::GP, RegState::Implicit); + } + MIRBuilder.insertInstr(MIB); + if (MIB->getOpcode() == Mips::JALRPseudo) { + const MipsSubtarget &STI = static_cast(MIRBuilder.getMF().getSubtarget()); + MIB.constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(), *STI.getRegBankInfo()); + } + if (!Info.OrigRet.Ty->isVoidTy()) { + ArgInfos.clear(); + SmallVector OrigRetIndices; + splitToValueTypes(DL, Info.OrigRet, 0, ArgInfos, OrigRetIndices); + SmallVector Ins; + subTargetRegTypeForCallingConv(F, ArgInfos, OrigRetIndices, Ins); + SmallVector ArgLocs; + MipsCCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs, F.getContext()); + CCInfo.AnalyzeCallResult(Ins, TLI.CCAssignFnForReturn(), Info.OrigRet.Ty, Call); + setLocInfo(ArgLocs, Ins); + CallReturnHandler Handler(MIRBuilder, MF.getRegInfo(), MIB); + if (!Handler.handle(ArgLocs, ArgInfos)) + return false; + } + MIRBuilder.buildInstr(Mips::ADJCALLSTACKUP).addImm(NextStackOffset).addImm(0); + return true; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/CallLowering/lowerFormalArguments.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/CallLowering/lowerFormalArguments.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4868c10586ca16cd0b682161b6b5ac7e1e639036 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/CallLowering/lowerFormalArguments.cpp @@ -0,0 +1,57 @@ +bool MipsCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef> VRegs, FunctionLoweringInfo &FLI) const { + if (F.arg_empty()) + return true; + for (auto &Arg : F.args()) { + if (!isSupportedArgumentType(Arg.getType())) + return false; + } + MachineFunction &MF = MIRBuilder.getMF(); + const DataLayout &DL = MF.getDataLayout(); + const MipsTargetLowering &TLI = *getTLI(); + SmallVector ArgInfos; + SmallVector OrigArgIndices; + unsigned i = 0; + for (auto &Arg : F.args()) { + ArgInfo AInfo(VRegs[i], Arg.getType()); + setArgFlags(AInfo, i + AttributeList::FirstArgIndex, DL, F); + ArgInfos.push_back(AInfo); + OrigArgIndices.push_back(i); + ++i; + } + SmallVector Ins; + subTargetRegTypeForCallingConv(F, ArgInfos, OrigArgIndices, Ins); + SmallVector ArgLocs; + MipsCCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs, F.getContext()); + const MipsTargetMachine &TM = static_cast(MF.getTarget()); + const MipsABIInfo &ABI = TM.getABI(); + CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(F.getCallingConv()), Align(1)); + CCInfo.AnalyzeFormalArguments(Ins, TLI.CCAssignFnForCall()); + setLocInfo(ArgLocs, Ins); + MipsIncomingValueHandler Handler(MIRBuilder, MF.getRegInfo()); + if (!Handler.handle(ArgLocs, ArgInfos)) + return false; + if (F.isVarArg()) { + ArrayRef ArgRegs = ABI.GetVarArgRegs(); + unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs); + int VaArgOffset; + unsigned RegSize = 4; + if (ArgRegs.size() == Idx) + VaArgOffset = alignTo(CCInfo.getNextStackOffset(), RegSize); + else { + VaArgOffset = (int)ABI.GetCalleeAllocdArgSizeInBytes(CCInfo.getCallingConv()) - (int)(RegSize * (ArgRegs.size() - Idx)); + } + MachineFrameInfo &MFI = MF.getFrameInfo(); + int FI = MFI.CreateFixedObject(RegSize, VaArgOffset, true); + MF.getInfo()->setVarArgsFrameIndex(FI); + for (unsigned I = Idx; I < ArgRegs.size(); ++I, VaArgOffset += RegSize) { + MIRBuilder.getMBB().addLiveIn(ArgRegs[I]); + MachineInstrBuilder Copy = MIRBuilder.buildCopy(LLT::scalar(RegSize * 8), Register(ArgRegs[I])); + FI = MFI.CreateFixedObject(RegSize, VaArgOffset, true); + MachinePointerInfo MPO = MachinePointerInfo::getFixedStack(MF, FI); + MachineInstrBuilder FrameIndex = MIRBuilder.buildFrameIndex(LLT::pointer(MPO.getAddrSpace(), 32), FI); + MachineMemOperand *MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOStore, RegSize, Align(RegSize)); + MIRBuilder.buildStore(Copy, FrameIndex, *MMO); + } + } + return true; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/CallLowering/lowerReturn.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/CallLowering/lowerReturn.cpp new file mode 100644 index 0000000000000000000000000000000000000000..66034aff8f85ce0f2fd76b08013c3be1992ec37d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/CallLowering/lowerReturn.cpp @@ -0,0 +1,28 @@ +bool MipsCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val, ArrayRef VRegs, FunctionLoweringInfo &FLI) const { + MachineInstrBuilder Ret = MIRBuilder.buildInstrNoInsert(Mips::RetRA); + if (Val != nullptr && !isSupportedReturnType(Val->getType())) + return false; + if (!VRegs.empty()) { + MachineFunction &MF = MIRBuilder.getMF(); + const Function &F = MF.getFunction(); + const DataLayout &DL = MF.getDataLayout(); + const MipsTargetLowering &TLI = *getTLI(); + SmallVector RetInfos; + SmallVector OrigArgIndices; + ArgInfo ArgRetInfo(VRegs, Val->getType()); + setArgFlags(ArgRetInfo, AttributeList::ReturnIndex, DL, F); + splitToValueTypes(DL, ArgRetInfo, 0, RetInfos, OrigArgIndices); + SmallVector Outs; + subTargetRegTypeForCallingConv(F, RetInfos, OrigArgIndices, Outs); + SmallVector ArgLocs; + MipsCCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs, F.getContext()); + CCInfo.AnalyzeReturn(Outs, TLI.CCAssignFnForReturn()); + setLocInfo(ArgLocs, Outs); + MipsOutgoingValueHandler RetHandler(MIRBuilder, MF.getRegInfo(), Ret); + if (!RetHandler.handle(ArgLocs, RetInfos)) { + return false; + } + } + MIRBuilder.insertInstr(Ret); + return true; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/FrameLowering/FrameLowering.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/FrameLowering/FrameLowering.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b384d32685bad5866f04b66f1bea348030208c0d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/FrameLowering/FrameLowering.cpp @@ -0,0 +1,2 @@ +explicit MipsFrameLowering(const MipsSubtarget &sti, Align Alignment) : TargetFrameLowering(StackGrowsDown, Alignment, 0, Alignment), STI(sti) { +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/FrameLowering/adjustReg.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/FrameLowering/adjustReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/FrameLowering/adjustReg.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/FrameLowering/canUseAsEpilogue.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/FrameLowering/canUseAsEpilogue.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/FrameLowering/canUseAsEpilogue.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/FrameLowering/canUseAsPrologue.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/FrameLowering/canUseAsPrologue.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d24252a436720a3ccdecb69c990fff58341ff97c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/FrameLowering/canUseAsPrologue.cpp @@ -0,0 +1,2 @@ +None + diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/FrameLowering/determineCalleeSaves.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/FrameLowering/determineCalleeSaves.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0c7be3a46a081dd318f6d9cb6c1c8652f9ee3d8a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/FrameLowering/determineCalleeSaves.cpp @@ -0,0 +1,31 @@ +void MipsSEFrameLowering::determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS) const { + TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS); + const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); + MipsFunctionInfo *MipsFI = MF.getInfo(); + MipsABIInfo ABI = STI.getABI(); + unsigned RA = ABI.IsN64() ? Mips::RA_64 : Mips::RA; + unsigned FP = ABI.GetFramePtr(); + unsigned BP = ABI.IsN64() ? Mips::S7_64 : Mips::S7; + if (hasFP(MF)) { + setAliasRegs(MF, SavedRegs, RA); + setAliasRegs(MF, SavedRegs, FP); + } + if (hasBP(MF)) + setAliasRegs(MF, SavedRegs, BP); + if (MipsFI->callsEhReturn()) + MipsFI->createEhDataRegsFI(MF); + if (MipsFI->isISR()) + MipsFI->createISRRegFI(MF); + if (ExpandPseudo(MF).expand()) { + const TargetRegisterClass &RC = STI.isGP64bit() ? Mips::GPR64RegClass : Mips::GPR32RegClass; + int FI = MF.getFrameInfo().CreateStackObject(TRI->getSpillSize(RC), TRI->getSpillAlign(RC), false); + RS->addScavengingFrameIndex(FI); + } + uint64_t MaxSPOffset = estimateStackSize(MF); + if (isIntN(STI.hasMSA() ? 10 : 16, MaxSPOffset) && !MF.getFrameInfo().hasVarSizedObjects()) + return; + const TargetRegisterClass &RC = ABI.ArePtrs64bit() ? Mips::GPR64RegClass : Mips::GPR32RegClass; + int FI = MF.getFrameInfo().CreateStackObject(TRI->getSpillSize(RC),TRI->getSpillAlign(RC), false); + RS->addScavengingFrameIndex(FI); +} + diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/FrameLowering/eliminateCallFramePseudoInstr.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/FrameLowering/eliminateCallFramePseudoInstr.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6b1f59ca8eacf87fd0c630d96c6589f6dca5e270 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/FrameLowering/eliminateCallFramePseudoInstr.cpp @@ -0,0 +1,10 @@ +MachineBasicBlock::iterator MipsFrameLowering::eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const { + unsigned SP = STI.getABI().IsN64() ? Mips::SP_64 : Mips::SP; + if (!hasReservedCallFrame(MF)) { + int64_t Amount = I->getOperand(0).getImm(); + if (I->getOpcode() == Mips::ADJCALLSTACKDOWN) + Amount = -Amount; + STI.getInstrInfo()->adjustStackPtr(SP, Amount, MBB, I); + } + return MBB.erase(I); +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/FrameLowering/emitEpilogue.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/FrameLowering/emitEpilogue.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fecd648fee2494cb011a5cd242be9efbd0d7efe2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/FrameLowering/emitEpilogue.cpp @@ -0,0 +1,35 @@ +void MipsSEFrameLowering::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { + MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator(); + MachineFrameInfo &MFI = MF.getFrameInfo(); + MipsFunctionInfo *MipsFI = MF.getInfo(); + const MipsSEInstrInfo &TII = *static_cast(STI.getInstrInfo()); + const MipsRegisterInfo &RegInfo = *static_cast(STI.getRegisterInfo()); + DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); + MipsABIInfo ABI = STI.getABI(); + unsigned SP = ABI.GetStackPtr(); + unsigned FP = ABI.GetFramePtr(); + unsigned ZERO = ABI.GetNullPtr(); + unsigned MOVE = ABI.GetGPRMoveOp(); + if (hasFP(MF)) { + MachineBasicBlock::iterator I = MBBI; + for (unsigned i = 0; i < MFI.getCalleeSavedInfo().size(); ++i) + --I; + BuildMI(MBB, I, DL, TII.get(MOVE), SP).addReg(FP).addReg(ZERO); + } + if (MipsFI->callsEhReturn()) { + const TargetRegisterClass *RC = ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; + MachineBasicBlock::iterator I = MBBI; + for (unsigned i = 0; i < MFI.getCalleeSavedInfo().size(); ++i) + --I; + for (int J = 0; J < 4; ++J) { + TII.loadRegFromStackSlot(MBB, I, ABI.GetEhDataReg(J), MipsFI->getEhDataRegFI(J), RC, &RegInfo); + } + } + if (MF.getFunction().hasFnAttribute("interrupt")) + emitInterruptEpilogueStub(MF, MBB); + uint64_t StackSize = MFI.getStackSize(); + if (!StackSize) + return; + TII.adjustStackPtr(SP, StackSize, MBB, MBBI); +} + diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/FrameLowering/emitPrologue.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/FrameLowering/emitPrologue.cpp new file mode 100644 index 0000000000000000000000000000000000000000..04cc5f5bac4d52157c1c5891a8c7a3810d0c6ef0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/FrameLowering/emitPrologue.cpp @@ -0,0 +1,88 @@ +void MipsSEFrameLowering::emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const { + MachineFrameInfo &MFI = MF.getFrameInfo(); + MipsFunctionInfo *MipsFI = MF.getInfo(); + const MipsSEInstrInfo &TII = *static_cast(STI.getInstrInfo()); + const MipsRegisterInfo &RegInfo = *static_cast(STI.getRegisterInfo()); + MachineBasicBlock::iterator MBBI = MBB.begin(); + DebugLoc dl; + MipsABIInfo ABI = STI.getABI(); + unsigned SP = ABI.GetStackPtr(); + unsigned FP = ABI.GetFramePtr(); + unsigned ZERO = ABI.GetNullPtr(); + unsigned MOVE = ABI.GetGPRMoveOp(); + unsigned ADDiu = ABI.GetPtrAddiuOp(); + unsigned AND = ABI.IsN64() ? Mips::AND64 : Mips::AND; + const TargetRegisterClass *RC = ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; + uint64_t StackSize = MFI.getStackSize(); + if (StackSize == 0 && !MFI.adjustsStack()) + return; + MachineModuleInfo &MMI = MF.getMMI(); + const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); + TII.adjustStackPtr(SP, -StackSize, MBB, MBBI); + unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, StackSize)); + BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)).addCFIIndex(CFIIndex); + if (MF.getFunction().hasFnAttribute("interrupt")) + emitInterruptPrologueStub(MF, MBB); + const std::vector &CSI = MFI.getCalleeSavedInfo(); + if (!CSI.empty()) { + for (unsigned i = 0; i < CSI.size(); ++i) + ++MBBI; + for (std::vector::const_iterator I = CSI.begin(), E = CSI.end(); I != E; ++I) { + int64_t Offset = MFI.getObjectOffset(I->getFrameIdx()); + unsigned Reg = I->getReg(); + if (Mips::AFGR64RegClass.contains(Reg)) { + unsigned Reg0 = MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_lo), true); + unsigned Reg1 = MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_hi), true); + if (!STI.isLittle()) + std::swap(Reg0, Reg1); + unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(nullptr, Reg0, Offset)); + BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)).addCFIIndex(CFIIndex); + CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4)); + BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)).addCFIIndex(CFIIndex); + } + else if (Mips::FGR64RegClass.contains(Reg)) { + unsigned Reg0 = MRI->getDwarfRegNum(Reg, true); + unsigned Reg1 = MRI->getDwarfRegNum(Reg, true) + 1; + if (!STI.isLittle()) + std::swap(Reg0, Reg1); + unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(nullptr, Reg0, Offset)); + BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)).addCFIIndex(CFIIndex); + CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4)); + BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)).addCFIIndex(CFIIndex); + } + else { + unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(nullptr, MRI->getDwarfRegNum(Reg, true), Offset)); + BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)).addCFIIndex(CFIIndex); + } + } + } + if (MipsFI->callsEhReturn()) { + for (int I = 0; I < 4; ++I) { + if (!MBB.isLiveIn(ABI.GetEhDataReg(I))) + MBB.addLiveIn(ABI.GetEhDataReg(I)); + TII.storeRegToStackSlot(MBB, MBBI, ABI.GetEhDataReg(I), false, MipsFI->getEhDataRegFI(I), RC, &RegInfo); + } + for (int I = 0; I < 4; ++I) { + int64_t Offset = MFI.getObjectOffset(MipsFI->getEhDataRegFI(I)); + unsigned Reg = MRI->getDwarfRegNum(ABI.GetEhDataReg(I), true); + unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(nullptr, Reg, Offset)); + BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)).addCFIIndex(CFIIndex); + } + } + if (hasFP(MF)) { + BuildMI(MBB, MBBI, dl, TII.get(MOVE), FP).addReg(SP).addReg(ZERO).setMIFlag(MachineInstr::FrameSetup); + unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfaRegister( nullptr, MRI->getDwarfRegNum(FP, true))); + BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)).addCFIIndex(CFIIndex); + if (RegInfo.needsStackRealignment(MF)) { + Register VR = MF.getRegInfo().createVirtualRegister(RC); + assert((Log2(MFI.getMaxAlign()) < 16) && "Function's alignment size requirement is not supported."); + int64_t MaxAlign = -(int64_t)MFI.getMaxAlign().value(); + BuildMI(MBB, MBBI, dl, TII.get(ADDiu), VR).addReg(ZERO).addImm(MaxAlign); + BuildMI(MBB, MBBI, dl, TII.get(AND), SP).addReg(SP).addReg(VR); + if (hasBP(MF)) { + unsigned BP = STI.isABI_N64() ? Mips::S7_64 : Mips::S7; + BuildMI(MBB, MBBI, dl, TII.get(MOVE), BP).addReg(SP).addReg(ZERO); + } + } + } +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/FrameLowering/getFrameIndexReference.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/FrameLowering/getFrameIndexReference.cpp new file mode 100644 index 0000000000000000000000000000000000000000..96cd6c3b3e00e732bf4cc98667e6b6cc7d664c40 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/FrameLowering/getFrameIndexReference.cpp @@ -0,0 +1,9 @@ +StackOffset MipsSEFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg) const { + const MachineFrameInfo &MFI = MF.getFrameInfo(); + MipsABIInfo ABI = STI.getABI(); + if (MFI.isFixedObjectIndex(FI)) + FrameReg = hasFP(MF) ? ABI.GetFramePtr() : ABI.GetStackPtr(); + else + FrameReg = hasBP(MF) ? ABI.GetBasePtr() : ABI.GetStackPtr(); + return StackOffset::getFixed(MFI.getObjectOffset(FI) + MFI.getStackSize() - getOffsetOfLocalArea() + MFI.getOffsetAdjustment()); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/FrameLowering/hasBP.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/FrameLowering/hasBP.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a6469c7a278c038c82567ff8856bedb6dadf7202 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/FrameLowering/hasBP.cpp @@ -0,0 +1,5 @@ +bool MipsFrameLowering::hasBP(const MachineFunction &MF) const { + const MachineFrameInfo &MFI = MF.getFrameInfo(); + const TargetRegisterInfo *TRI = STI.getRegisterInfo(); + return MFI.hasVarSizedObjects() && TRI->needsStackRealignment(MF); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/FrameLowering/hasFP.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/FrameLowering/hasFP.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2984a24fb87e41d561111fe745a031a4ae00d2f8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/FrameLowering/hasFP.cpp @@ -0,0 +1,5 @@ +bool MipsFrameLowering::hasFP(const MachineFunction &MF) const { + const MachineFrameInfo &MFI = MF.getFrameInfo(); + const TargetRegisterInfo *TRI = STI.getRegisterInfo(); + return MF.getTarget().Options.DisableFramePointerElim(MF) || MFI.hasVarSizedObjects() || MFI.isFrameAddressTaken() || TRI->needsStackRealignment(MF); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/FrameLowering/hasReservedCallFrame.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/FrameLowering/hasReservedCallFrame.cpp new file mode 100644 index 0000000000000000000000000000000000000000..97a97d73efcd689066a40c08ef80ad03f0f94706 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/FrameLowering/hasReservedCallFrame.cpp @@ -0,0 +1,4 @@ +bool MipsSEFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const { + const MachineFrameInfo &MFI = MF.getFrameInfo(); + return isInt<16>(MFI.getMaxCallFrameSize() + getStackAlignment()) && !MFI.hasVarSizedObjects(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/FrameLowering/processFunctionBeforeFrameFinalized.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/FrameLowering/processFunctionBeforeFrameFinalized.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/FrameLowering/processFunctionBeforeFrameFinalized.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/FrameLowering/restoreCalleeSavedRegisters.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/FrameLowering/restoreCalleeSavedRegisters.cpp new file mode 100644 index 0000000000000000000000000000000000000000..39a52f6a3ffb6bddaec5669406257eaaf8382c20 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/FrameLowering/restoreCalleeSavedRegisters.cpp @@ -0,0 +1,3 @@ +bool Mips16FrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, MutableArrayRef CSI, const TargetRegisterInfo *TRI) const { + return true; +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/FrameLowering/spillCalleeSavedRegisters.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/FrameLowering/spillCalleeSavedRegisters.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d7ccdfa1edf7514e9f46b468c4a170614877a6c7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/FrameLowering/spillCalleeSavedRegisters.cpp @@ -0,0 +1,29 @@ +bool MipsSEFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef CSI, const TargetRegisterInfo *TRI) const { + MachineFunction *MF = MBB.getParent(); + const TargetInstrInfo &TII = *STI.getInstrInfo(); + for (unsigned i = 0, e = CSI.size(); i != e; ++i) { + unsigned Reg = CSI[i].getReg(); + bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA || Reg == Mips::RA_64) && MF->getFrameInfo().isReturnAddressTaken(); + if (!IsRAAndRetAddrIsTaken) + MBB.addLiveIn(Reg); + bool IsLOHI = (Reg == Mips::LO0 || Reg == Mips::LO0_64 || Reg == Mips::HI0 || Reg == Mips::HI0_64); + const Function &Func = MBB.getParent()->getFunction(); + if (IsLOHI && Func.hasFnAttribute("interrupt")) { + DebugLoc DL = MI->getDebugLoc(); + unsigned Op = 0; + if (!STI.getABI().ArePtrs64bit()) { + Op = (Reg == Mips::HI0) ? Mips::MFHI : Mips::MFLO; + Reg = Mips::K0; + } + else { + Op = (Reg == Mips::HI0) ? Mips::MFHI64 : Mips::MFLO64; + Reg = Mips::K0_64; + } + BuildMI(MBB, MI, DL, TII.get(Op), Mips::K0).setMIFlag(MachineInstr::FrameSetup); + } + bool IsKill = !IsRAAndRetAddrIsTaken; + const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); + TII.storeRegToStackSlot(MBB, MI, Reg, IsKill, CSI[i].getFrameIdx(), RC, TRI); + } + return true; +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelDAGToDAG/DAGToDAGISel.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelDAGToDAG/DAGToDAGISel.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5a7fcbbf66a18053cbb09eb170938804acb78987 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelDAGToDAG/DAGToDAGISel.cpp @@ -0,0 +1,2 @@ +explicit MipsSEDAGToDAGISel(MipsTargetMachine &TM, CodeGenOpt::Level OL) : MipsDAGToDAGISel(TM, OL) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelDAGToDAG/MatchSLLIUW.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelDAGToDAG/MatchSLLIUW.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelDAGToDAG/MatchSLLIUW.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelDAGToDAG/MatchSRLIUW.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelDAGToDAG/MatchSRLIUW.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelDAGToDAG/MatchSRLIUW.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelDAGToDAG/PostprocessISelDAG.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelDAGToDAG/PostprocessISelDAG.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelDAGToDAG/PostprocessISelDAG.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelDAGToDAG/Select.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelDAGToDAG/Select.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelDAGToDAG/Select.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelDAGToDAG/SelectAddrFI.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelDAGToDAG/SelectAddrFI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelDAGToDAG/SelectAddrFI.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelDAGToDAG/SelectInlineAsmMemoryOperand.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelDAGToDAG/SelectInlineAsmMemoryOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d342f74eef8e6835cb6a33677db55fb78cb5d785 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelDAGToDAG/SelectInlineAsmMemoryOperand.cpp @@ -0,0 +1,50 @@ +bool MipsSEDAGToDAGISel::SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, std::vector &OutOps) { + SDValue Base, Offset; + switch(ConstraintID) { + default: + llvm_unreachable("Unexpected asm memory constraint"); + case InlineAsm::Constraint_m: + case InlineAsm::Constraint_o: + if (selectAddrRegImm16(Op, Base, Offset)) { + OutOps.push_back(Base); + OutOps.push_back(Offset); + return false; + } + OutOps.push_back(Op); + OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32)); + return false; + case InlineAsm::Constraint_R: + if (selectAddrRegImm9(Op, Base, Offset)) { + OutOps.push_back(Base); + OutOps.push_back(Offset); + return false; + } + OutOps.push_back(Op); + OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32)); + return false; + case InlineAsm::Constraint_ZC: + if (Subtarget->inMicroMipsMode()) { + if (selectAddrRegImm12(Op, Base, Offset)) { + OutOps.push_back(Base); + OutOps.push_back(Offset); + return false; + } + } + else if (Subtarget->hasMips32r6()) { + if (selectAddrRegImm9(Op, Base, Offset)) { + OutOps.push_back(Base); + OutOps.push_back(Offset); + return false; + } + } + else if (selectAddrRegImm16(Op, Base, Offset)) { + OutOps.push_back(Base); + OutOps.push_back(Offset); + return false; + } + OutOps.push_back(Op); + OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32)); + return false; + } + return true; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelDAGToDAG/createISelDag.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelDAGToDAG/createISelDag.cpp new file mode 100644 index 0000000000000000000000000000000000000000..36e8855eb544200582451f8c21a565df6b7b9a48 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelDAGToDAG/createISelDag.cpp @@ -0,0 +1,3 @@ +FunctionPass *llvm::createMipsSEISelDag(MipsTargetMachine &TM, CodeGenOpt::Level OptLevel) { + return new MipsSEDAGToDAGISel(TM, OptLevel); +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelDAGToDAG/getPassName.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelDAGToDAG/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5049e898a5b33a064ed6484e2e7cf1667997bef8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelDAGToDAG/getPassName.cpp @@ -0,0 +1,3 @@ +StringRef getPassName() const override { + return "MIPS DAG->DAG Pattern Instruction Selection"; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelDAGToDAG/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelDAGToDAG/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..23043d2db6c9d6e9b1f35cdf3b44609cf5975340 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelDAGToDAG/runOnMachineFunction.cpp @@ -0,0 +1,7 @@ +bool MipsModuleDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) { + LLVM_DEBUG(errs() << "In MipsModuleDAGToDAGISel::runMachineFunction\n"); + auto &TPC = getAnalysis(); + auto &TM = TPC.getTM(); + TM.resetSubtarget(&MF); + return false; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelDAGToDAG/selectVLOp.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelDAGToDAG/selectVLOp.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d24252a436720a3ccdecb69c990fff58341ff97c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelDAGToDAG/selectVLOp.cpp @@ -0,0 +1,2 @@ +None + diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelDAGToDAG/selectVSplat.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelDAGToDAG/selectVSplat.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3ddc959d5cec6fb8668b07d516cd6e866a0989a0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelDAGToDAG/selectVSplat.cpp @@ -0,0 +1,14 @@ +bool MipsSEDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm, unsigned MinSizeInBits) const { + if (!Subtarget->hasMSA()) + return false; + BuildVectorSDNode *Node = dyn_cast(N); + if (!Node) + return false; + APInt SplatValue, SplatUndef; + unsigned SplatBitSize; + bool HasAnyUndefs; + if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs, MinSizeInBits, !Subtarget->isLittle())) + return false; + Imm = SplatValue; + return true; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelDAGToDAG/selectVSplatSimm5.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelDAGToDAG/selectVSplatSimm5.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e86a8153fbab9c79b9ea14bfbc050c061ff370fd --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelDAGToDAG/selectVSplatSimm5.cpp @@ -0,0 +1,4 @@ +bool MipsDAGToDAGISel::selectVSplatSimm5(SDValue N, SDValue &Imm) const { + llvm_unreachable("Unimplemented function."); + return false; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelDAGToDAG/selectVSplatUimm5.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelDAGToDAG/selectVSplatUimm5.cpp new file mode 100644 index 0000000000000000000000000000000000000000..02c4b950f0aa45a72a3ed3b1bce2af4f5eb6cd6a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelDAGToDAG/selectVSplatUimm5.cpp @@ -0,0 +1,4 @@ +bool MipsDAGToDAGISel::selectVSplatUimm5(SDValue N, SDValue &Imm) const { + llvm_unreachable("Unimplemented function."); + return false; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/CanLowerReturn.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/CanLowerReturn.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e857257cc58f086519f5aa8fb47b84c794ac83d0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/CanLowerReturn.cpp @@ -0,0 +1,5 @@ +bool MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg, const SmallVectorImpl &Outs, LLVMContext &Context) const { + SmallVector RVLocs; + MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context); + return CCInfo.CheckReturn(Outs, RetCC_Mips); +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/ComputeNumSignBitsForTargetNode.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/ComputeNumSignBitsForTargetNode.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/ComputeNumSignBitsForTargetNode.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/EmitInstrWithCustomInserter.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/EmitInstrWithCustomInserter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c7a577133ff50ac6ce86af208c82aec90f270744 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/EmitInstrWithCustomInserter.cpp @@ -0,0 +1,154 @@ +MachineBasicBlock *MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const { + switch (MI.getOpcode()) { + default: + llvm_unreachable("Unexpected instr type to insert"); + case Mips::ATOMIC_LOAD_ADD_I8: + return emitAtomicBinaryPartword(MI, BB, 1); + case Mips::ATOMIC_LOAD_ADD_I16: + return emitAtomicBinaryPartword(MI, BB, 2); + case Mips::ATOMIC_LOAD_ADD_I32: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_LOAD_ADD_I64: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_LOAD_AND_I8: + return emitAtomicBinaryPartword(MI, BB, 1); + case Mips::ATOMIC_LOAD_AND_I16: + return emitAtomicBinaryPartword(MI, BB, 2); + case Mips::ATOMIC_LOAD_AND_I32: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_LOAD_AND_I64: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_LOAD_OR_I8: + return emitAtomicBinaryPartword(MI, BB, 1); + case Mips::ATOMIC_LOAD_OR_I16: + return emitAtomicBinaryPartword(MI, BB, 2); + case Mips::ATOMIC_LOAD_OR_I32: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_LOAD_OR_I64: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_LOAD_XOR_I8: + return emitAtomicBinaryPartword(MI, BB, 1); + case Mips::ATOMIC_LOAD_XOR_I16: + return emitAtomicBinaryPartword(MI, BB, 2); + case Mips::ATOMIC_LOAD_XOR_I32: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_LOAD_XOR_I64: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_LOAD_NAND_I8: + return emitAtomicBinaryPartword(MI, BB, 1); + case Mips::ATOMIC_LOAD_NAND_I16: + return emitAtomicBinaryPartword(MI, BB, 2); + case Mips::ATOMIC_LOAD_NAND_I32: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_LOAD_NAND_I64: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_LOAD_SUB_I8: + return emitAtomicBinaryPartword(MI, BB, 1); + case Mips::ATOMIC_LOAD_SUB_I16: + return emitAtomicBinaryPartword(MI, BB, 2); + case Mips::ATOMIC_LOAD_SUB_I32: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_LOAD_SUB_I64: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_SWAP_I8: + return emitAtomicBinaryPartword(MI, BB, 1); + case Mips::ATOMIC_SWAP_I16: + return emitAtomicBinaryPartword(MI, BB, 2); + case Mips::ATOMIC_SWAP_I32: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_SWAP_I64: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_CMP_SWAP_I8: + return emitAtomicCmpSwapPartword(MI, BB, 1); + case Mips::ATOMIC_CMP_SWAP_I16: + return emitAtomicCmpSwapPartword(MI, BB, 2); + case Mips::ATOMIC_CMP_SWAP_I32: + return emitAtomicCmpSwap(MI, BB); + case Mips::ATOMIC_CMP_SWAP_I64: + return emitAtomicCmpSwap(MI, BB); + case Mips::ATOMIC_LOAD_MIN_I8: + return emitAtomicBinaryPartword(MI, BB, 1); + case Mips::ATOMIC_LOAD_MIN_I16: + return emitAtomicBinaryPartword(MI, BB, 2); + case Mips::ATOMIC_LOAD_MIN_I32: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_LOAD_MIN_I64: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_LOAD_MAX_I8: + return emitAtomicBinaryPartword(MI, BB, 1); + case Mips::ATOMIC_LOAD_MAX_I16: + return emitAtomicBinaryPartword(MI, BB, 2); + case Mips::ATOMIC_LOAD_MAX_I32: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_LOAD_MAX_I64: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_LOAD_UMIN_I8: + return emitAtomicBinaryPartword(MI, BB, 1); + case Mips::ATOMIC_LOAD_UMIN_I16: + return emitAtomicBinaryPartword(MI, BB, 2); + case Mips::ATOMIC_LOAD_UMIN_I32: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_LOAD_UMIN_I64: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_LOAD_UMAX_I8: + return emitAtomicBinaryPartword(MI, BB, 1); + case Mips::ATOMIC_LOAD_UMAX_I16: + return emitAtomicBinaryPartword(MI, BB, 2); + case Mips::ATOMIC_LOAD_UMAX_I32: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_LOAD_UMAX_I64: + return emitAtomicBinary(MI, BB); + case Mips::PseudoSDIV: + case Mips::PseudoUDIV: + case Mips::DIV: + case Mips::DIVU: + case Mips::MOD: + case Mips::MODU: + return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, false); + case Mips::SDIV_MM_Pseudo: + case Mips::UDIV_MM_Pseudo: + case Mips::SDIV_MM: + case Mips::UDIV_MM: + case Mips::DIV_MMR6: + case Mips::DIVU_MMR6: + case Mips::MOD_MMR6: + case Mips::MODU_MMR6: + return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, true); + case Mips::PseudoDSDIV: + case Mips::PseudoDUDIV: + case Mips::DDIV: + case Mips::DDIVU: + case Mips::DMOD: + case Mips::DMODU: + return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, false); + case Mips::PseudoSELECT_I: + case Mips::PseudoSELECT_I64: + case Mips::PseudoSELECT_S: + case Mips::PseudoSELECT_D32: + case Mips::PseudoSELECT_D64: + return emitPseudoSELECT(MI, BB, false, Mips::BNE); + case Mips::PseudoSELECTFP_F_I: + case Mips::PseudoSELECTFP_F_I64: + case Mips::PseudoSELECTFP_F_S: + case Mips::PseudoSELECTFP_F_D32: + case Mips::PseudoSELECTFP_F_D64: + return emitPseudoSELECT(MI, BB, true, Mips::BC1F); + case Mips::PseudoSELECTFP_T_I: + case Mips::PseudoSELECTFP_T_I64: + case Mips::PseudoSELECTFP_T_S: + case Mips::PseudoSELECTFP_T_D32: + case Mips::PseudoSELECTFP_T_D64: + return emitPseudoSELECT(MI, BB, true, Mips::BC1T); + case Mips::PseudoD_SELECT_I: + case Mips::PseudoD_SELECT_I64: + return emitPseudoD_SELECT(MI, BB); + case Mips::LDR_W: + return emitLDR_W(MI, BB); + case Mips::LDR_D: + return emitLDR_D(MI, BB); + case Mips::STR_W: + return emitSTR_W(MI, BB); + case Mips::STR_D: + return emitSTR_D(MI, BB); + } +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/LowerAsmOperandForConstraint.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/LowerAsmOperandForConstraint.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1a35f0f7b2528752ec8bf1cb35bc8dac3d13de61 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/LowerAsmOperandForConstraint.cpp @@ -0,0 +1,86 @@ +void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector&Ops, SelectionDAG &DAG) const { + SDLoc DL(Op); + SDValue Result; + if (Constraint.length() > 1) + return; + char ConstraintLetter = Constraint[0]; + switch (ConstraintLetter) { + default: + break; + case 'I': + if (ConstantSDNode *C = dyn_cast(Op)) { + EVT Type = Op.getValueType(); + int64_t Val = C->getSExtValue(); + if (isInt<16>(Val)) { + Result = DAG.getTargetConstant(Val, DL, Type); + break; + } + } + return; + case 'J': + if (ConstantSDNode *C = dyn_cast(Op)) { + EVT Type = Op.getValueType(); + int64_t Val = C->getZExtValue(); + if (Val == 0) { + Result = DAG.getTargetConstant(0, DL, Type); + break; + } + } + return; + case 'K': + if (ConstantSDNode *C = dyn_cast(Op)) { + EVT Type = Op.getValueType(); + uint64_t Val = (uint64_t)C->getZExtValue(); + if (isUInt<16>(Val)) { + Result = DAG.getTargetConstant(Val, DL, Type); + break; + } + } + return; + case 'L': + if (ConstantSDNode *C = dyn_cast(Op)) { + EVT Type = Op.getValueType(); + int64_t Val = C->getSExtValue(); + if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){ + Result = DAG.getTargetConstant(Val, DL, Type); + break; + } + } + return; + case 'N': + if (ConstantSDNode *C = dyn_cast(Op)) { + EVT Type = Op.getValueType(); + int64_t Val = C->getSExtValue(); + if ((Val >= -65535) && (Val <= -1)) { + Result = DAG.getTargetConstant(Val, DL, Type); + break; + } + } + return; + case 'O': + if (ConstantSDNode *C = dyn_cast(Op)) { + EVT Type = Op.getValueType(); + int64_t Val = C->getSExtValue(); + if ((isInt<15>(Val))) { + Result = DAG.getTargetConstant(Val, DL, Type); + break; + } + } + return; + case 'P': + if (ConstantSDNode *C = dyn_cast(Op)) { + EVT Type = Op.getValueType(); + int64_t Val = C->getSExtValue(); + if ((Val <= 65535) && (Val >= 1)) { + Result = DAG.getTargetConstant(Val, DL, Type); + break; + } + } + return; + } + if (Result.getNode()) { + Ops.push_back(Result); + return; + } + TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/LowerBlockAddress.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/LowerBlockAddress.cpp new file mode 100644 index 0000000000000000000000000000000000000000..63faa865e7326bef8f45aeceafcb0fa0a1c608eb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/LowerBlockAddress.cpp @@ -0,0 +1,7 @@ +SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const { + BlockAddressSDNode *N = cast(Op); + EVT Ty = Op.getValueType(); + if (!isPositionIndependent()) + return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); + return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/LowerCall.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/LowerCall.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e452e8db8b1f84d438f35752f0c4f697f1ca6bd3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/LowerCall.cpp @@ -0,0 +1,194 @@ +SDValue MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl &InVals) const { + SelectionDAG &DAG = CLI.DAG; + SDLoc DL = CLI.DL; + SmallVectorImpl &Outs = CLI.Outs; + SmallVectorImpl &OutVals = CLI.OutVals; + SmallVectorImpl &Ins = CLI.Ins; + SDValue Chain = CLI.Chain; + SDValue Callee = CLI.Callee; + bool &IsTailCall = CLI.IsTailCall; + CallingConv::ID CallConv = CLI.CallConv; + bool IsVarArg = CLI.IsVarArg; + MachineFunction &MF = DAG.getMachineFunction(); + MachineFrameInfo &MFI = MF.getFrameInfo(); + const TargetFrameLowering *TFL = Subtarget.getFrameLowering(); + MipsFunctionInfo *FuncInfo = MF.getInfo(); + bool IsPIC = isPositionIndependent(); + SmallVector ArgLocs; + MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext(), MipsCCState::getSpecialCallingConvForCallee(Callee.getNode(), Subtarget)); + const ExternalSymbolSDNode *ES = dyn_cast_or_null(Callee.getNode()); + bool MemcpyInByVal = ES && StringRef(ES->getSymbol()) == StringRef("memcpy") && CallConv != CallingConv::Fast && Chain.getOpcode() == ISD::CALLSEQ_START; + unsigned ReservedArgArea = MemcpyInByVal ? 0 : ABI.GetCalleeAllocdArgSizeInBytes(CallConv); + CCInfo.AllocateStack(ReservedArgArea, Align(1)); + CCInfo.AnalyzeCallOperands(Outs, CC_Mips, CLI.getArgs(), ES ? ES->getSymbol() : nullptr); + unsigned NextStackOffset = CCInfo.getNextStackOffset(); + MachineFunction::CallSiteInfo CSInfo; + bool InternalLinkage = false; + if (IsTailCall) { + IsTailCall = isEligibleForTailCallOptimization(CCInfo, NextStackOffset, *MF.getInfo()); + if (GlobalAddressSDNode *G = dyn_cast(Callee)) { + InternalLinkage = G->getGlobal()->hasInternalLinkage(); + IsTailCall &= (InternalLinkage || G->getGlobal()->hasLocalLinkage() || G->getGlobal()->hasPrivateLinkage() || G->getGlobal()->hasHiddenVisibility() || G->getGlobal()->hasProtectedVisibility()); + } + } + if (!IsTailCall && CLI.CB && CLI.CB->isMustTailCall()) + report_fatal_error("failed to perform tail call elimination on a call site marked musttail"); + if (IsTailCall) + ++NumTailCalls; + unsigned StackAlignment = TFL->getStackAlignment(); + NextStackOffset = alignTo(NextStackOffset, StackAlignment); + SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, DL, true); + if (!(IsTailCall || MemcpyInByVal)) + Chain = DAG.getCALLSEQ_START(Chain, NextStackOffset, 0, DL); + SDValue StackPtr = DAG.getCopyFromReg(Chain, DL, ABI.IsN64() ? Mips::SP_64 : Mips::SP, getPointerTy(DAG.getDataLayout())); + std::deque> RegsToPass; + SmallVector MemOpChains; + CCInfo.rewindByValRegsInfo(); + for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { + SDValue Arg = OutVals[i]; + CCValAssign &VA = ArgLocs[i]; + MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT(); + ISD::ArgFlagsTy Flags = Outs[i].Flags; + bool UseUpperBits = false; + if (Flags.isByVal()) { + unsigned FirstByValReg, LastByValReg; + unsigned ByValIdx = CCInfo.getInRegsParamsProcessed(); + CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg); + assert(Flags.getByValSize() && "ByVal args of size 0 should have been ignored by front-end."); + assert(ByValIdx < CCInfo.getInRegsParamsCount()); + assert(!IsTailCall && "Do not tail-call optimize if there is a byval argument."); + passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg, FirstByValReg, LastByValReg, Flags, Subtarget.isLittle(), VA); + CCInfo.nextInRegsParam(); + continue; + } + switch (VA.getLocInfo()) { + default: + llvm_unreachable("Unknown loc info!"); + case CCValAssign::Full: + if (VA.isRegLoc()) { + if ((ValVT == MVT::f32 && LocVT == MVT::i32) || (ValVT == MVT::f64 && LocVT == MVT::i64) || (ValVT == MVT::i64 && LocVT == MVT::f64)) + Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg); + else if (ValVT == MVT::f64 && LocVT == MVT::i32) { + SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Arg, DAG.getConstant(0, DL, MVT::i32)); + SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Arg, DAG.getConstant(1, DL, MVT::i32)); + if (!Subtarget.isLittle()) + std::swap(Lo, Hi); + Register LocRegLo = VA.getLocReg(); + unsigned LocRegHigh = getNextIntArgReg(LocRegLo); + RegsToPass.push_back(std::make_pair(LocRegLo, Lo)); + RegsToPass.push_back(std::make_pair(LocRegHigh, Hi)); + continue; + } + } + break; + case CCValAssign::BCvt: + Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg); + break; + case CCValAssign::SExtUpper: + UseUpperBits = true; + LLVM_FALLTHROUGH; + case CCValAssign::SExt: + Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg); + break; + case CCValAssign::ZExtUpper: + UseUpperBits = true; + LLVM_FALLTHROUGH; + case CCValAssign::ZExt: + Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg); + break; + case CCValAssign::AExtUpper: + UseUpperBits = true; + LLVM_FALLTHROUGH; + case CCValAssign::AExt: + Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg); + break; + } + if (UseUpperBits) { + unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits(); + unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); + Arg = DAG.getNode(ISD::SHL, DL, VA.getLocVT(), Arg, DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); + } + if (VA.isRegLoc()) { + RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); + if (Mips::AFGR64RegClass.contains(VA.getLocReg())) + continue; + const TargetOptions &Options = DAG.getTarget().Options; + if (Options.SupportsDebugEntryValues) + CSInfo.emplace_back(VA.getLocReg(), i); + continue; + } + assert(VA.isMemLoc()); + MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(), Chain, Arg, DL, IsTailCall, DAG)); + } + if (!MemOpChains.empty()) + Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains); + EVT Ty = Callee.getValueType(); + bool GlobalOrExternal = false, IsCallReloc = false; + if (!Subtarget.isABICalls() && !IsPIC) { + if (auto *N = dyn_cast(Callee)) { + if (Subtarget.useLongCalls()) + Callee = Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); + } + else if (auto *N = dyn_cast(Callee)) { + bool UseLongCalls = Subtarget.useLongCalls(); + if (auto *F = dyn_cast(N->getGlobal())) { + if (F->hasFnAttribute("long-call")) + UseLongCalls = true; + else if (F->hasFnAttribute("short-call")) + UseLongCalls = false; + } + if (UseLongCalls) + Callee = Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); + } + } + if (GlobalAddressSDNode *G = dyn_cast(Callee)) { + if (IsPIC) { + const GlobalValue *Val = G->getGlobal(); + InternalLinkage = Val->hasInternalLinkage(); + if (InternalLinkage) + Callee = getAddrLocal(G, DL, Ty, DAG, ABI.IsN32() || ABI.IsN64()); + else if (Subtarget.useXGOT()) { + Callee = getAddrGlobalLargeGOT(G, DL, Ty, DAG, MipsII::MO_CALL_HI16, MipsII::MO_CALL_LO16, Chain, FuncInfo->callPtrInfo(MF, Val)); + IsCallReloc = true; + } + else { + Callee = getAddrGlobal(G, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain, FuncInfo->callPtrInfo(MF, Val)); + IsCallReloc = true; + } + } + else + Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, getPointerTy(DAG.getDataLayout()), 0, MipsII::MO_NO_FLAG); + GlobalOrExternal = true; + } + else if (ExternalSymbolSDNode *S = dyn_cast(Callee)) { + const char *Sym = S->getSymbol(); + if (!IsPIC) + Callee = DAG.getTargetExternalSymbol( Sym, getPointerTy(DAG.getDataLayout()), MipsII::MO_NO_FLAG); + else if (Subtarget.useXGOT()) { + Callee = getAddrGlobalLargeGOT(S, DL, Ty, DAG, MipsII::MO_CALL_HI16, MipsII::MO_CALL_LO16, Chain, FuncInfo->callPtrInfo(MF, Sym)); + IsCallReloc = true; + } + else { + Callee = getAddrGlobal(S, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain, FuncInfo->callPtrInfo(MF, Sym)); + IsCallReloc = true; + } + GlobalOrExternal = true; + } + SmallVector Ops(1, Chain); + SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); + getOpndList(Ops, RegsToPass, IsPIC, GlobalOrExternal, InternalLinkage, IsCallReloc, CLI, Callee, Chain); + if (IsTailCall) { + MF.getFrameInfo().setHasTailCall(); + SDValue Ret = DAG.getNode(MipsISD::TailCall, DL, MVT::Other, Ops); + DAG.addCallSiteInfo(Ret.getNode(), std::move(CSInfo)); + return Ret; + } + Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, Ops); + SDValue InFlag = Chain.getValue(1); + DAG.addCallSiteInfo(Chain.getNode(), std::move(CSInfo)); + if (!(MemcpyInByVal)) { + Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal, DAG.getIntPtrConstant(0, DL, true), InFlag, DL); + InFlag = Chain.getValue(1); + } + return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG, InVals, CLI); +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/LowerConstantPool.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/LowerConstantPool.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0a118c8fea23e323e770a810738ac56de09cca15 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/LowerConstantPool.cpp @@ -0,0 +1,11 @@ +SDValue MipsTargetLowering::lowerConstantPool(SDValue Op, SelectionDAG &DAG) const { + ConstantPoolSDNode *N = cast(Op); + EVT Ty = Op.getValueType(); + if (!isPositionIndependent()) { + const MipsTargetObjectFile *TLOF = static_cast(getTargetMachine().getObjFileLowering()); + if (TLOF->IsConstantInSmallSection(DAG.getDataLayout(), N->getConstVal(), getTargetMachine())) + return getAddrGPRel(N, SDLoc(N), Ty, DAG, ABI.IsN64()); + return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); + } + return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/LowerFRAMEADDR.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/LowerFRAMEADDR.cpp new file mode 100644 index 0000000000000000000000000000000000000000..55304c0e002c25426cac915e340d397c57564694 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/LowerFRAMEADDR.cpp @@ -0,0 +1,12 @@ +SDValue MipsTargetLowering::lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { + if (cast(Op.getOperand(0))->getZExtValue() != 0) { + DAG.getContext()->emitError("return address can be determined only for current frame"); + return SDValue(); + } + MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); + MFI.setFrameAddressIsTaken(true); + EVT VT = Op.getValueType(); + SDLoc DL(Op); + SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), DL, ABI.IsN64() ? Mips::FP_64 : Mips::FP, VT); + return FrameAddr; +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/LowerFormalArguments.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/LowerFormalArguments.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bbb9efff7eb46b474008aab70f4ce03c006a5618 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/LowerFormalArguments.cpp @@ -0,0 +1,90 @@ +SDValue MipsTargetLowering::LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl &InVals) const { + MachineFunction &MF = DAG.getMachineFunction(); + MachineFrameInfo &MFI = MF.getFrameInfo(); + MipsFunctionInfo *MipsFI = MF.getInfo(); + MipsFI->setVarArgsFrameIndex(0); + std::vector OutChains; + SmallVector ArgLocs; + MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext()); + CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), Align(1)); + const Function &Func = DAG.getMachineFunction().getFunction(); + Function::const_arg_iterator FuncArg = Func.arg_begin(); + if (Func.hasFnAttribute("interrupt") && !Func.arg_empty()) + report_fatal_error("Functions with the interrupt attribute cannot have arguments!"); + CCInfo.AnalyzeFormalArguments(Ins, CC_Mips_FixedArg); + MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(), CCInfo.getInRegsParamsCount() > 0); + unsigned CurArgIdx = 0; + CCInfo.rewindByValRegsInfo(); + for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { + CCValAssign &VA = ArgLocs[i]; + if (Ins[i].isOrigArg()) { + std::advance(FuncArg, Ins[i].getOrigArgIndex() - CurArgIdx); + CurArgIdx = Ins[i].getOrigArgIndex(); + } + EVT ValVT = VA.getValVT(); + ISD::ArgFlagsTy Flags = Ins[i].Flags; + bool IsRegLoc = VA.isRegLoc(); + if (Flags.isByVal()) { + assert(Ins[i].isOrigArg() && "Byval arguments cannot be implicit"); + unsigned FirstByValReg, LastByValReg; + unsigned ByValIdx = CCInfo.getInRegsParamsProcessed(); + CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg); + assert(Flags.getByValSize() && "ByVal args of size 0 should have been ignored by front-end."); + assert(ByValIdx < CCInfo.getInRegsParamsCount()); + copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg, FirstByValReg, LastByValReg, VA, CCInfo); + CCInfo.nextInRegsParam(); + continue; + } + if (IsRegLoc) { + MVT RegVT = VA.getLocVT(); + Register ArgReg = VA.getLocReg(); + const TargetRegisterClass *RC = getRegClassFor(RegVT); + unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC); + SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); + ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG); + if ((RegVT == MVT::i32 && ValVT == MVT::f32) || (RegVT == MVT::i64 && ValVT == MVT::f64) || (RegVT == MVT::f64 && ValVT == MVT::i64)) + ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue); + else if (ABI.IsO32() && RegVT == MVT::i32 && ValVT == MVT::f64) { + unsigned Reg2 = addLiveIn(DAG.getMachineFunction(), getNextIntArgReg(ArgReg), RC); + SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT); + if (!Subtarget.isLittle()) + std::swap(ArgValue, ArgValue2); + ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, ArgValue, ArgValue2); + } + InVals.push_back(ArgValue); + } + else { + MVT LocVT = VA.getLocVT(); + if (ABI.IsO32()) { + if (VA.getValVT().isFloatingPoint() && !Subtarget.useSoftFloat()) + LocVT = VA.getValVT(); + } + assert(VA.isMemLoc()); + int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8, VA.getLocMemOffset(), true); + SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); + SDValue ArgValue = DAG.getLoad(LocVT, DL, Chain, FIN, MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI)); + OutChains.push_back(ArgValue.getValue(1)); + ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG); + InVals.push_back(ArgValue); + } + } + for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { + if (Ins[i].Flags.isSRet()) { + unsigned Reg = MipsFI->getSRetReturnReg(); + if (!Reg) { + Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(ABI.IsN64() ? MVT::i64 : MVT::i32)); + MipsFI->setSRetReturnReg(Reg); + } + SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[i]); + Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain); + break; + } + } + if (IsVarArg) + writeVarArgRegs(OutChains, Chain, DL, DAG, CCInfo); + if (!OutChains.empty()) { + OutChains.push_back(Chain); + Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains); + } + return Chain; +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/LowerGlobalAddress.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/LowerGlobalAddress.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3bc241861141aeaf0155e6e05b289a3c4232fdc8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/LowerGlobalAddress.cpp @@ -0,0 +1,17 @@ +SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const { + EVT Ty = Op.getValueType(); + GlobalAddressSDNode *N = cast(Op); + const GlobalValue *GV = N->getGlobal(); + if (!isPositionIndependent()) { + const MipsTargetObjectFile *TLOF = static_cast(getTargetMachine().getObjFileLowering()); + const GlobalObject *GO = GV->getBaseObject(); + if (GO && TLOF->IsGlobalInSmallSection(GO, getTargetMachine())) + return getAddrGPRel(N, SDLoc(N), Ty, DAG, ABI.IsN64()); + return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); + } + if (GV->hasLocalLinkage()) + return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); + if (Subtarget.useXGOT()) + return getAddrGlobalLargeGOT(N, SDLoc(N), Ty, DAG, MipsII::MO_GOT_HI16, MipsII::MO_GOT_LO16, DAG.getEntryNode(), MachinePointerInfo::getGOT(DAG.getMachineFunction())); + return getAddrGlobal(N, SDLoc(N), Ty, DAG, (ABI.IsN32() || ABI.IsN64()) ? MipsII::MO_GOT_DISP : MipsII::MO_GOT, DAG.getEntryNode(), MachinePointerInfo::getGOT(DAG.getMachineFunction())); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/LowerGlobalTLSAddress.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/LowerGlobalTLSAddress.cpp new file mode 100644 index 0000000000000000000000000000000000000000..40d4302abbe9ff053b9574dac4d63cd2fbc144cf --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/LowerGlobalTLSAddress.cpp @@ -0,0 +1,50 @@ +SDValue MipsTargetLowering::lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { + GlobalAddressSDNode *GA = cast(Op); + if (DAG.getTarget().useEmulatedTLS()) + return LowerToTLSEmulatedModel(GA, DAG); + SDLoc DL(GA); + const GlobalValue *GV = GA->getGlobal(); + EVT PtrVT = getPointerTy(DAG.getDataLayout()); + TLSModel::Model model = getTargetMachine().getTLSModel(GV); + if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) { + unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM : MipsII::MO_TLSGD; + SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, Flag); + SDValue Argument = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT), TGA); + unsigned PtrSize = PtrVT.getSizeInBits(); + IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize); + SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT); + ArgListTy Args; + ArgListEntry Entry; + Entry.Node = Argument; + Entry.Ty = PtrTy; + Args.push_back(Entry); + TargetLowering::CallLoweringInfo CLI(DAG); + CLI.setDebugLoc(DL).setChain(DAG.getEntryNode()).setLibCallee(CallingConv::C, PtrTy, TlsGetAddr, std::move(Args)); + std::pair CallResult = LowerCallTo(CLI); + SDValue Ret = CallResult.first; + if (model != TLSModel::LocalDynamic) + return Ret; + SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, MipsII::MO_DTPREL_HI); + SDValue Hi = DAG.getNode(MipsISD::TlsHi, DL, PtrVT, TGAHi); + SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, MipsII::MO_DTPREL_LO); + SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); + SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret); + return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo); + } + SDValue Offset; + if (model == TLSModel::InitialExec) { + SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, MipsII::MO_GOTTPREL); + TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT),TGA); + Offset = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), TGA, MachinePointerInfo()); + } + else { + assert(model == TLSModel::LocalExec); + SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, MipsII::MO_TPREL_HI); + SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, MipsII::MO_TPREL_LO); + SDValue Hi = DAG.getNode(MipsISD::TlsHi, DL, PtrVT, TGAHi); + SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); + Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo); + } + SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT); + return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset); +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/LowerINTRINSIC_WO_CHAIN.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/LowerINTRINSIC_WO_CHAIN.cpp new file mode 100644 index 0000000000000000000000000000000000000000..150e8c0e72027acdaeeb3a046260a9210d8c6e7c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/LowerINTRINSIC_WO_CHAIN.cpp @@ -0,0 +1,601 @@ +SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const { + SDLoc DL(Op); + unsigned Intrinsic = cast(Op->getOperand(0))->getZExtValue(); + switch (Intrinsic) { + default: + return SDValue(); + case Intrinsic::mips_shilo: + return lowerDSPIntr(Op, DAG, MipsISD::SHILO); + case Intrinsic::mips_dpau_h_qbl: + return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL); + case Intrinsic::mips_dpau_h_qbr: + return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR); + case Intrinsic::mips_dpsu_h_qbl: + return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL); + case Intrinsic::mips_dpsu_h_qbr: + return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR); + case Intrinsic::mips_dpa_w_ph: + return lowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH); + case Intrinsic::mips_dps_w_ph: + return lowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH); + case Intrinsic::mips_dpax_w_ph: + return lowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH); + case Intrinsic::mips_dpsx_w_ph: + return lowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH); + case Intrinsic::mips_mulsa_w_ph: + return lowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH); + case Intrinsic::mips_mult: + return lowerDSPIntr(Op, DAG, MipsISD::Mult); + case Intrinsic::mips_multu: + return lowerDSPIntr(Op, DAG, MipsISD::Multu); + case Intrinsic::mips_madd: + return lowerDSPIntr(Op, DAG, MipsISD::MAdd); + case Intrinsic::mips_maddu: + return lowerDSPIntr(Op, DAG, MipsISD::MAddu); + case Intrinsic::mips_msub: + return lowerDSPIntr(Op, DAG, MipsISD::MSub); + case Intrinsic::mips_msubu: + return lowerDSPIntr(Op, DAG, MipsISD::MSubu); + case Intrinsic::mips_addv_b: + case Intrinsic::mips_addv_h: + case Intrinsic::mips_addv_w: + case Intrinsic::mips_addv_d: + return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_addvi_b: + case Intrinsic::mips_addvi_h: + case Intrinsic::mips_addvi_w: + case Intrinsic::mips_addvi_d: + return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); + case Intrinsic::mips_and_v: + return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_andi_b: + return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); + case Intrinsic::mips_bclr_b: + case Intrinsic::mips_bclr_h: + case Intrinsic::mips_bclr_w: + case Intrinsic::mips_bclr_d: + return lowerMSABitClear(Op, DAG); + case Intrinsic::mips_bclri_b: + case Intrinsic::mips_bclri_h: + case Intrinsic::mips_bclri_w: + case Intrinsic::mips_bclri_d: + return lowerMSABitClearImm(Op, DAG); + case Intrinsic::mips_binsli_b: + case Intrinsic::mips_binsli_h: + case Intrinsic::mips_binsli_w: + case Intrinsic::mips_binsli_d: { + EVT VecTy = Op->getValueType(0); + EVT EltTy = VecTy.getVectorElementType(); + if (Op->getConstantOperandVal(3) >= EltTy.getSizeInBits()) + report_fatal_error("Immediate out of range"); + APInt Mask = APInt::getHighBitsSet(EltTy.getSizeInBits(), Op->getConstantOperandVal(3) + 1); + return DAG.getNode(ISD::VSELECT, DL, VecTy, DAG.getConstant(Mask, DL, VecTy, true), Op->getOperand(2), Op->getOperand(1)); + } + case Intrinsic::mips_binsri_b: + case Intrinsic::mips_binsri_h: + case Intrinsic::mips_binsri_w: + case Intrinsic::mips_binsri_d: { + EVT VecTy = Op->getValueType(0); + EVT EltTy = VecTy.getVectorElementType(); + if (Op->getConstantOperandVal(3) >= EltTy.getSizeInBits()) + report_fatal_error("Immediate out of range"); + APInt Mask = APInt::getLowBitsSet(EltTy.getSizeInBits(), Op->getConstantOperandVal(3) + 1); + return DAG.getNode(ISD::VSELECT, DL, VecTy, DAG.getConstant(Mask, DL, VecTy, true), Op->getOperand(2), Op->getOperand(1)); + } + case Intrinsic::mips_bmnz_v: + return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3), Op->getOperand(2), Op->getOperand(1)); + case Intrinsic::mips_bmnzi_b: + return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), lowerMSASplatImm(Op, 3, DAG), Op->getOperand(2), Op->getOperand(1)); + case Intrinsic::mips_bmz_v: + return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_bmzi_b: + return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), lowerMSASplatImm(Op, 3, DAG), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_bneg_b: + case Intrinsic::mips_bneg_h: + case Intrinsic::mips_bneg_w: + case Intrinsic::mips_bneg_d: { + EVT VecTy = Op->getValueType(0); + SDValue One = DAG.getConstant(1, DL, VecTy); + return DAG.getNode(ISD::XOR, DL, VecTy, Op->getOperand(1), DAG.getNode(ISD::SHL, DL, VecTy, One, truncateVecElts(Op, DAG))); + } + case Intrinsic::mips_bnegi_b: + case Intrinsic::mips_bnegi_h: + case Intrinsic::mips_bnegi_w: + case Intrinsic::mips_bnegi_d: + return lowerMSABinaryBitImmIntr(Op, DAG, ISD::XOR, Op->getOperand(2), !Subtarget.isLittle()); + case Intrinsic::mips_bnz_b: + case Intrinsic::mips_bnz_h: + case Intrinsic::mips_bnz_w: + case Intrinsic::mips_bnz_d: + return DAG.getNode(MipsISD::VALL_NONZERO, DL, Op->getValueType(0), Op->getOperand(1)); + case Intrinsic::mips_bnz_v: + return DAG.getNode(MipsISD::VANY_NONZERO, DL, Op->getValueType(0), Op->getOperand(1)); + case Intrinsic::mips_bsel_v: + return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(3), Op->getOperand(2)); + case Intrinsic::mips_bseli_b: + return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 3, DAG), Op->getOperand(2)); + case Intrinsic::mips_bset_b: + case Intrinsic::mips_bset_h: + case Intrinsic::mips_bset_w: + case Intrinsic::mips_bset_d: { + EVT VecTy = Op->getValueType(0); + SDValue One = DAG.getConstant(1, DL, VecTy); + return DAG.getNode(ISD::OR, DL, VecTy, Op->getOperand(1), DAG.getNode(ISD::SHL, DL, VecTy, One, truncateVecElts(Op, DAG))); + } + case Intrinsic::mips_bseti_b: + case Intrinsic::mips_bseti_h: + case Intrinsic::mips_bseti_w: + case Intrinsic::mips_bseti_d: + return lowerMSABinaryBitImmIntr(Op, DAG, ISD::OR, Op->getOperand(2), !Subtarget.isLittle()); + case Intrinsic::mips_bz_b: + case Intrinsic::mips_bz_h: + case Intrinsic::mips_bz_w: + case Intrinsic::mips_bz_d: + return DAG.getNode(MipsISD::VALL_ZERO, DL, Op->getValueType(0), Op->getOperand(1)); + case Intrinsic::mips_bz_v: + return DAG.getNode(MipsISD::VANY_ZERO, DL, Op->getValueType(0), Op->getOperand(1)); + case Intrinsic::mips_ceq_b: + case Intrinsic::mips_ceq_h: + case Intrinsic::mips_ceq_w: + case Intrinsic::mips_ceq_d: + return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2), ISD::SETEQ); + case Intrinsic::mips_ceqi_b: + case Intrinsic::mips_ceqi_h: + case Intrinsic::mips_ceqi_w: + case Intrinsic::mips_ceqi_d: + return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG, true), ISD::SETEQ); + case Intrinsic::mips_cle_s_b: + case Intrinsic::mips_cle_s_h: + case Intrinsic::mips_cle_s_w: + case Intrinsic::mips_cle_s_d: + return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2), ISD::SETLE); + case Intrinsic::mips_clei_s_b: + case Intrinsic::mips_clei_s_h: + case Intrinsic::mips_clei_s_w: + case Intrinsic::mips_clei_s_d: + return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG, true), ISD::SETLE); + case Intrinsic::mips_cle_u_b: + case Intrinsic::mips_cle_u_h: + case Intrinsic::mips_cle_u_w: + case Intrinsic::mips_cle_u_d: + return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2), ISD::SETULE); + case Intrinsic::mips_clei_u_b: + case Intrinsic::mips_clei_u_h: + case Intrinsic::mips_clei_u_w: + case Intrinsic::mips_clei_u_d: + return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG), ISD::SETULE); + case Intrinsic::mips_clt_s_b: + case Intrinsic::mips_clt_s_h: + case Intrinsic::mips_clt_s_w: + case Intrinsic::mips_clt_s_d: + return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2), ISD::SETLT); + case Intrinsic::mips_clti_s_b: + case Intrinsic::mips_clti_s_h: + case Intrinsic::mips_clti_s_w: + case Intrinsic::mips_clti_s_d: + return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG, true), ISD::SETLT); + case Intrinsic::mips_clt_u_b: + case Intrinsic::mips_clt_u_h: + case Intrinsic::mips_clt_u_w: + case Intrinsic::mips_clt_u_d: + return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2), ISD::SETULT); + case Intrinsic::mips_clti_u_b: + case Intrinsic::mips_clti_u_h: + case Intrinsic::mips_clti_u_w: + case Intrinsic::mips_clti_u_d: + return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG), ISD::SETULT); + case Intrinsic::mips_copy_s_b: + case Intrinsic::mips_copy_s_h: + case Intrinsic::mips_copy_s_w: + return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT); + case Intrinsic::mips_copy_s_d: + if (Subtarget.hasMips64()) + return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT); + else { + return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + } + case Intrinsic::mips_copy_u_b: + case Intrinsic::mips_copy_u_h: + case Intrinsic::mips_copy_u_w: + return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT); + case Intrinsic::mips_copy_u_d: + if (Subtarget.hasMips64()) + return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT); + else { + return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + } + case Intrinsic::mips_div_s_b: + case Intrinsic::mips_div_s_h: + case Intrinsic::mips_div_s_w: + case Intrinsic::mips_div_s_d: + return DAG.getNode(ISD::SDIV, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_div_u_b: + case Intrinsic::mips_div_u_h: + case Intrinsic::mips_div_u_w: + case Intrinsic::mips_div_u_d: + return DAG.getNode(ISD::UDIV, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_fadd_w: + case Intrinsic::mips_fadd_d: + return DAG.getNode(ISD::FADD, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_fceq_w: + case Intrinsic::mips_fceq_d: + return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2), ISD::SETOEQ); + case Intrinsic::mips_fcle_w: + case Intrinsic::mips_fcle_d: + return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2), ISD::SETOLE); + case Intrinsic::mips_fclt_w: + case Intrinsic::mips_fclt_d: + return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2), ISD::SETOLT); + case Intrinsic::mips_fcne_w: + case Intrinsic::mips_fcne_d: + return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2), ISD::SETONE); + case Intrinsic::mips_fcor_w: + case Intrinsic::mips_fcor_d: + return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2), ISD::SETO); + case Intrinsic::mips_fcueq_w: + case Intrinsic::mips_fcueq_d: + return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2), ISD::SETUEQ); + case Intrinsic::mips_fcule_w: + case Intrinsic::mips_fcule_d: + return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2), ISD::SETULE); + case Intrinsic::mips_fcult_w: + case Intrinsic::mips_fcult_d: + return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2), ISD::SETULT); + case Intrinsic::mips_fcun_w: + case Intrinsic::mips_fcun_d: + return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2), ISD::SETUO); + case Intrinsic::mips_fcune_w: + case Intrinsic::mips_fcune_d: + return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2), ISD::SETUNE); + case Intrinsic::mips_fdiv_w: + case Intrinsic::mips_fdiv_d: + return DAG.getNode(ISD::FDIV, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_ffint_u_w: + case Intrinsic::mips_ffint_u_d: + return DAG.getNode(ISD::UINT_TO_FP, DL, Op->getValueType(0), Op->getOperand(1)); + case Intrinsic::mips_ffint_s_w: + case Intrinsic::mips_ffint_s_d: + return DAG.getNode(ISD::SINT_TO_FP, DL, Op->getValueType(0), Op->getOperand(1)); + case Intrinsic::mips_fill_b: + case Intrinsic::mips_fill_h: + case Intrinsic::mips_fill_w: + case Intrinsic::mips_fill_d: { + EVT ResTy = Op->getValueType(0); + SmallVector Ops(ResTy.getVectorNumElements(), Op->getOperand(1)); + return DAG.getBuildVector(ResTy, DL, Ops); + } + case Intrinsic::mips_fexp2_w: + case Intrinsic::mips_fexp2_d: { + EVT ResTy = Op->getValueType(0); + return DAG.getNode(ISD::FMUL, SDLoc(Op), ResTy, Op->getOperand(1), DAG.getNode(ISD::FEXP2, SDLoc(Op), ResTy, Op->getOperand(2))); + } + case Intrinsic::mips_flog2_w: + case Intrinsic::mips_flog2_d: + return DAG.getNode(ISD::FLOG2, DL, Op->getValueType(0), Op->getOperand(1)); + case Intrinsic::mips_fmadd_w: + case Intrinsic::mips_fmadd_d: + return DAG.getNode(ISD::FMA, SDLoc(Op), Op->getValueType(0), Op->getOperand(1), Op->getOperand(2), Op->getOperand(3)); + case Intrinsic::mips_fmul_w: + case Intrinsic::mips_fmul_d: + return DAG.getNode(ISD::FMUL, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_fmsub_w: + case Intrinsic::mips_fmsub_d: { + return DAG.getNode(MipsISD::FMS, SDLoc(Op), Op->getValueType(0), Op->getOperand(1), Op->getOperand(2), Op->getOperand(3)); + } + case Intrinsic::mips_frint_w: + case Intrinsic::mips_frint_d: + return DAG.getNode(ISD::FRINT, DL, Op->getValueType(0), Op->getOperand(1)); + case Intrinsic::mips_fsqrt_w: + case Intrinsic::mips_fsqrt_d: + return DAG.getNode(ISD::FSQRT, DL, Op->getValueType(0), Op->getOperand(1)); + case Intrinsic::mips_fsub_w: + case Intrinsic::mips_fsub_d: + return DAG.getNode(ISD::FSUB, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_ftrunc_u_w: + case Intrinsic::mips_ftrunc_u_d: + return DAG.getNode(ISD::FP_TO_UINT, DL, Op->getValueType(0), Op->getOperand(1)); + case Intrinsic::mips_ftrunc_s_w: + case Intrinsic::mips_ftrunc_s_d: + return DAG.getNode(ISD::FP_TO_SINT, DL, Op->getValueType(0), Op->getOperand(1)); + case Intrinsic::mips_ilvev_b: + case Intrinsic::mips_ilvev_h: + case Intrinsic::mips_ilvev_w: + case Intrinsic::mips_ilvev_d: + return DAG.getNode(MipsISD::ILVEV, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_ilvl_b: + case Intrinsic::mips_ilvl_h: + case Intrinsic::mips_ilvl_w: + case Intrinsic::mips_ilvl_d: + return DAG.getNode(MipsISD::ILVL, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_ilvod_b: + case Intrinsic::mips_ilvod_h: + case Intrinsic::mips_ilvod_w: + case Intrinsic::mips_ilvod_d: + return DAG.getNode(MipsISD::ILVOD, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_ilvr_b: + case Intrinsic::mips_ilvr_h: + case Intrinsic::mips_ilvr_w: + case Intrinsic::mips_ilvr_d: + return DAG.getNode(MipsISD::ILVR, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_insert_b: + case Intrinsic::mips_insert_h: + case Intrinsic::mips_insert_w: + case Intrinsic::mips_insert_d: + return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0), Op->getOperand(1), Op->getOperand(3), Op->getOperand(2)); + case Intrinsic::mips_insve_b: + case Intrinsic::mips_insve_h: + case Intrinsic::mips_insve_w: + case Intrinsic::mips_insve_d: { + int64_t Max; + switch (Intrinsic) { + case Intrinsic::mips_insve_b: Max = 15; break; + case Intrinsic::mips_insve_h: Max = 7; break; + case Intrinsic::mips_insve_w: Max = 3; break; + case Intrinsic::mips_insve_d: Max = 1; break; + default: llvm_unreachable("Unmatched intrinsic"); + } + int64_t Value = cast(Op->getOperand(2))->getSExtValue(); + if (Value < 0 || Value > Max) + report_fatal_error("Immediate out of range"); + return DAG.getNode(MipsISD::INSVE, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2), Op->getOperand(3), DAG.getConstant(0, DL, MVT::i32)); + } + case Intrinsic::mips_ldi_b: + case Intrinsic::mips_ldi_h: + case Intrinsic::mips_ldi_w: + case Intrinsic::mips_ldi_d: + return lowerMSASplatImm(Op, 1, DAG, true); + case Intrinsic::mips_lsa: + case Intrinsic::mips_dlsa: { + EVT ResTy = Op->getValueType(0); + return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1), DAG.getNode(ISD::SHL, SDLoc(Op), ResTy, Op->getOperand(2), Op->getOperand(3))); + } + case Intrinsic::mips_maddv_b: + case Intrinsic::mips_maddv_h: + case Intrinsic::mips_maddv_w: + case Intrinsic::mips_maddv_d: { + EVT ResTy = Op->getValueType(0); + return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1), DAG.getNode(ISD::MUL, SDLoc(Op), ResTy, Op->getOperand(2), Op->getOperand(3))); + } + case Intrinsic::mips_max_s_b: + case Intrinsic::mips_max_s_h: + case Intrinsic::mips_max_s_w: + case Intrinsic::mips_max_s_d: + return DAG.getNode(ISD::SMAX, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_max_u_b: + case Intrinsic::mips_max_u_h: + case Intrinsic::mips_max_u_w: + case Intrinsic::mips_max_u_d: + return DAG.getNode(ISD::UMAX, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_maxi_s_b: + case Intrinsic::mips_maxi_s_h: + case Intrinsic::mips_maxi_s_w: + case Intrinsic::mips_maxi_s_d: + return DAG.getNode(ISD::SMAX, DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG, true)); + case Intrinsic::mips_maxi_u_b: + case Intrinsic::mips_maxi_u_h: + case Intrinsic::mips_maxi_u_w: + case Intrinsic::mips_maxi_u_d: + return DAG.getNode(ISD::UMAX, DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); + case Intrinsic::mips_min_s_b: + case Intrinsic::mips_min_s_h: + case Intrinsic::mips_min_s_w: + case Intrinsic::mips_min_s_d: + return DAG.getNode(ISD::SMIN, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_min_u_b: + case Intrinsic::mips_min_u_h: + case Intrinsic::mips_min_u_w: + case Intrinsic::mips_min_u_d: + return DAG.getNode(ISD::UMIN, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_mini_s_b: + case Intrinsic::mips_mini_s_h: + case Intrinsic::mips_mini_s_w: + case Intrinsic::mips_mini_s_d: + return DAG.getNode(ISD::SMIN, DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG, true)); + case Intrinsic::mips_mini_u_b: + case Intrinsic::mips_mini_u_h: + case Intrinsic::mips_mini_u_w: + case Intrinsic::mips_mini_u_d: + return DAG.getNode(ISD::UMIN, DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); + case Intrinsic::mips_mod_s_b: + case Intrinsic::mips_mod_s_h: + case Intrinsic::mips_mod_s_w: + case Intrinsic::mips_mod_s_d: + return DAG.getNode(ISD::SREM, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_mod_u_b: + case Intrinsic::mips_mod_u_h: + case Intrinsic::mips_mod_u_w: + case Intrinsic::mips_mod_u_d: + return DAG.getNode(ISD::UREM, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_mulv_b: + case Intrinsic::mips_mulv_h: + case Intrinsic::mips_mulv_w: + case Intrinsic::mips_mulv_d: + return DAG.getNode(ISD::MUL, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_msubv_b: + case Intrinsic::mips_msubv_h: + case Intrinsic::mips_msubv_w: + case Intrinsic::mips_msubv_d: { + EVT ResTy = Op->getValueType(0); + return DAG.getNode(ISD::SUB, SDLoc(Op), ResTy, Op->getOperand(1), DAG.getNode(ISD::MUL, SDLoc(Op), ResTy, Op->getOperand(2), Op->getOperand(3))); + } + case Intrinsic::mips_nlzc_b: + case Intrinsic::mips_nlzc_h: + case Intrinsic::mips_nlzc_w: + case Intrinsic::mips_nlzc_d: + return DAG.getNode(ISD::CTLZ, DL, Op->getValueType(0), Op->getOperand(1)); + case Intrinsic::mips_nor_v: { + SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + return DAG.getNOT(DL, Res, Res->getValueType(0)); + } + case Intrinsic::mips_nori_b: { + SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); + return DAG.getNOT(DL, Res, Res->getValueType(0)); + } + case Intrinsic::mips_or_v: + return DAG.getNode(ISD::OR, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_ori_b: + return DAG.getNode(ISD::OR, DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); + case Intrinsic::mips_pckev_b: + case Intrinsic::mips_pckev_h: + case Intrinsic::mips_pckev_w: + case Intrinsic::mips_pckev_d: + return DAG.getNode(MipsISD::PCKEV, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_pckod_b: + case Intrinsic::mips_pckod_h: + case Intrinsic::mips_pckod_w: + case Intrinsic::mips_pckod_d: + return DAG.getNode(MipsISD::PCKOD, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_pcnt_b: + case Intrinsic::mips_pcnt_h: + case Intrinsic::mips_pcnt_w: + case Intrinsic::mips_pcnt_d: + return DAG.getNode(ISD::CTPOP, DL, Op->getValueType(0), Op->getOperand(1)); + case Intrinsic::mips_sat_s_b: + case Intrinsic::mips_sat_s_h: + case Intrinsic::mips_sat_s_w: + case Intrinsic::mips_sat_s_d: + case Intrinsic::mips_sat_u_b: + case Intrinsic::mips_sat_u_h: + case Intrinsic::mips_sat_u_w: + case Intrinsic::mips_sat_u_d: { + int64_t Max; + switch (Intrinsic) { + case Intrinsic::mips_sat_s_b: + case Intrinsic::mips_sat_u_b: Max = 7; break; + case Intrinsic::mips_sat_s_h: + case Intrinsic::mips_sat_u_h: Max = 15; break; + case Intrinsic::mips_sat_s_w: + case Intrinsic::mips_sat_u_w: Max = 31; break; + case Intrinsic::mips_sat_s_d: + case Intrinsic::mips_sat_u_d: Max = 63; break; + default: llvm_unreachable("Unmatched intrinsic"); + } + int64_t Value = cast(Op->getOperand(2))->getSExtValue(); + if (Value < 0 || Value > Max) + report_fatal_error("Immediate out of range"); + return SDValue(); + } + case Intrinsic::mips_shf_b: + case Intrinsic::mips_shf_h: + case Intrinsic::mips_shf_w: { + int64_t Value = cast(Op->getOperand(2))->getSExtValue(); + if (Value < 0 || Value > 255) + report_fatal_error("Immediate out of range"); + return DAG.getNode(MipsISD::SHF, DL, Op->getValueType(0), Op->getOperand(2), Op->getOperand(1)); + } + case Intrinsic::mips_sldi_b: + case Intrinsic::mips_sldi_h: + case Intrinsic::mips_sldi_w: + case Intrinsic::mips_sldi_d: { + int64_t Max; + switch (Intrinsic) { + case Intrinsic::mips_sldi_b: Max = 15; break; + case Intrinsic::mips_sldi_h: Max = 7; break; + case Intrinsic::mips_sldi_w: Max = 3; break; + case Intrinsic::mips_sldi_d: Max = 1; break; + default: llvm_unreachable("Unmatched intrinsic"); + } + int64_t Value = cast(Op->getOperand(3))->getSExtValue(); + if (Value < 0 || Value > Max) + report_fatal_error("Immediate out of range"); + return SDValue(); + } + case Intrinsic::mips_sll_b: + case Intrinsic::mips_sll_h: + case Intrinsic::mips_sll_w: + case Intrinsic::mips_sll_d: + return DAG.getNode(ISD::SHL, DL, Op->getValueType(0), Op->getOperand(1), truncateVecElts(Op, DAG)); + case Intrinsic::mips_slli_b: + case Intrinsic::mips_slli_h: + case Intrinsic::mips_slli_w: + case Intrinsic::mips_slli_d: + return DAG.getNode(ISD::SHL, DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); + case Intrinsic::mips_splat_b: + case Intrinsic::mips_splat_h: + case Intrinsic::mips_splat_w: + case Intrinsic::mips_splat_d: + return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0), lowerMSASplatZExt(Op, 2, DAG), Op->getOperand(1), Op->getOperand(1)); + case Intrinsic::mips_splati_b: + case Intrinsic::mips_splati_h: + case Intrinsic::mips_splati_w: + case Intrinsic::mips_splati_d: + return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0), lowerMSASplatImm(Op, 2, DAG), Op->getOperand(1), Op->getOperand(1)); + case Intrinsic::mips_sra_b: + case Intrinsic::mips_sra_h: + case Intrinsic::mips_sra_w: + case Intrinsic::mips_sra_d: + return DAG.getNode(ISD::SRA, DL, Op->getValueType(0), Op->getOperand(1), truncateVecElts(Op, DAG)); + case Intrinsic::mips_srai_b: + case Intrinsic::mips_srai_h: + case Intrinsic::mips_srai_w: + case Intrinsic::mips_srai_d: + return DAG.getNode(ISD::SRA, DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); + case Intrinsic::mips_srari_b: + case Intrinsic::mips_srari_h: + case Intrinsic::mips_srari_w: + case Intrinsic::mips_srari_d: { + int64_t Max; + switch (Intrinsic) { + case Intrinsic::mips_srari_b: Max = 7; break; + case Intrinsic::mips_srari_h: Max = 15; break; + case Intrinsic::mips_srari_w: Max = 31; break; + case Intrinsic::mips_srari_d: Max = 63; break; + default: llvm_unreachable("Unmatched intrinsic"); + } + int64_t Value = cast(Op->getOperand(2))->getSExtValue(); + if (Value < 0 || Value > Max) + report_fatal_error("Immediate out of range"); + return SDValue(); + } + case Intrinsic::mips_srl_b: + case Intrinsic::mips_srl_h: + case Intrinsic::mips_srl_w: + case Intrinsic::mips_srl_d: + return DAG.getNode(ISD::SRL, DL, Op->getValueType(0), Op->getOperand(1), truncateVecElts(Op, DAG)); + case Intrinsic::mips_srli_b: + case Intrinsic::mips_srli_h: + case Intrinsic::mips_srli_w: + case Intrinsic::mips_srli_d: + return DAG.getNode(ISD::SRL, DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); + case Intrinsic::mips_srlri_b: + case Intrinsic::mips_srlri_h: + case Intrinsic::mips_srlri_w: + case Intrinsic::mips_srlri_d: { + int64_t Max; + switch (Intrinsic) { + case Intrinsic::mips_srlri_b: Max = 7; break; + case Intrinsic::mips_srlri_h: Max = 15; break; + case Intrinsic::mips_srlri_w: Max = 31; break; + case Intrinsic::mips_srlri_d: Max = 63; break; + default: llvm_unreachable("Unmatched intrinsic"); + } + int64_t Value = cast(Op->getOperand(2))->getSExtValue(); + if (Value < 0 || Value > Max) + report_fatal_error("Immediate out of range"); + return SDValue(); + } + case Intrinsic::mips_subv_b: + case Intrinsic::mips_subv_h: + case Intrinsic::mips_subv_w: + case Intrinsic::mips_subv_d: + return DAG.getNode(ISD::SUB, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_subvi_b: + case Intrinsic::mips_subvi_h: + case Intrinsic::mips_subvi_w: + case Intrinsic::mips_subvi_d: + return DAG.getNode(ISD::SUB, DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); + case Intrinsic::mips_vshf_b: + case Intrinsic::mips_vshf_h: + case Intrinsic::mips_vshf_w: + case Intrinsic::mips_vshf_d: + return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2), Op->getOperand(3)); + case Intrinsic::mips_xor_v: + return DAG.getNode(ISD::XOR, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_xori_b: + return DAG.getNode(ISD::XOR, DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); + case Intrinsic::thread_pointer: { + EVT PtrVT = getPointerTy(DAG.getDataLayout()); + return DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT); + } + } +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/LowerINTRINSIC_W_CHAIN.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/LowerINTRINSIC_W_CHAIN.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4be9f6092250b32fead2a9800ea16544544f58f7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/LowerINTRINSIC_W_CHAIN.cpp @@ -0,0 +1,52 @@ +SDValue MipsSETargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const { + unsigned Intr = cast(Op->getOperand(1))->getZExtValue(); + switch (Intr) { + default: + return SDValue(); + case Intrinsic::mips_extp: + return lowerDSPIntr(Op, DAG, MipsISD::EXTP); + case Intrinsic::mips_extpdp: + return lowerDSPIntr(Op, DAG, MipsISD::EXTPDP); + case Intrinsic::mips_extr_w: + return lowerDSPIntr(Op, DAG, MipsISD::EXTR_W); + case Intrinsic::mips_extr_r_w: + return lowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W); + case Intrinsic::mips_extr_rs_w: + return lowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W); + case Intrinsic::mips_extr_s_h: + return lowerDSPIntr(Op, DAG, MipsISD::EXTR_S_H); + case Intrinsic::mips_mthlip: + return lowerDSPIntr(Op, DAG, MipsISD::MTHLIP); + case Intrinsic::mips_mulsaq_s_w_ph: + return lowerDSPIntr(Op, DAG, MipsISD::MULSAQ_S_W_PH); + case Intrinsic::mips_maq_s_w_phl: + return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL); + case Intrinsic::mips_maq_s_w_phr: + return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR); + case Intrinsic::mips_maq_sa_w_phl: + return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHL); + case Intrinsic::mips_maq_sa_w_phr: + return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHR); + case Intrinsic::mips_dpaq_s_w_ph: + return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_S_W_PH); + case Intrinsic::mips_dpsq_s_w_ph: + return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_S_W_PH); + case Intrinsic::mips_dpaq_sa_l_w: + return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_SA_L_W); + case Intrinsic::mips_dpsq_sa_l_w: + return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_SA_L_W); + case Intrinsic::mips_dpaqx_s_w_ph: + return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_S_W_PH); + case Intrinsic::mips_dpaqx_sa_w_ph: + return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_SA_W_PH); + case Intrinsic::mips_dpsqx_s_w_ph: + return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH); + case Intrinsic::mips_dpsqx_sa_w_ph: + return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH); + case Intrinsic::mips_ld_b: + case Intrinsic::mips_ld_h: + case Intrinsic::mips_ld_w: + case Intrinsic::mips_ld_d: + return lowerMSALoadIntr(Op, DAG, Intr, Subtarget); + } +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/LowerJumpTable.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/LowerJumpTable.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c445b62394d8dd7ca699b85e09abca470d7e9eef --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/LowerJumpTable.cpp @@ -0,0 +1,7 @@ +SDValue MipsTargetLowering::lowerJumpTable(SDValue Op, SelectionDAG &DAG) const { + JumpTableSDNode *N = cast(Op); + EVT Ty = Op.getValueType(); + if (!isPositionIndependent()) + return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); + return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/LowerOperation.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/LowerOperation.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fbfe3d2f0ef29923975a86d495e1dd2120dba454 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/LowerOperation.cpp @@ -0,0 +1,22 @@ +SDValue MipsSETargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { + switch(Op.getOpcode()) { + case ISD::LOAD: return lowerLOAD(Op, DAG); + case ISD::STORE: return lowerSTORE(Op, DAG); + case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG); + case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG); + case ISD::MULHS: return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG); + case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG); + case ISD::MUL: return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG); + case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG); + case ISD::UDIVREM: return lowerMulDiv(Op, MipsISD::DivRemU, true, true, DAG); + case ISD::INTRINSIC_WO_CHAIN: return lowerINTRINSIC_WO_CHAIN(Op, DAG); + case ISD::INTRINSIC_W_CHAIN: return lowerINTRINSIC_W_CHAIN(Op, DAG); + case ISD::INTRINSIC_VOID: return lowerINTRINSIC_VOID(Op, DAG); + case ISD::EXTRACT_VECTOR_ELT: return lowerEXTRACT_VECTOR_ELT(Op, DAG); + case ISD::BUILD_VECTOR: return lowerBUILD_VECTOR(Op, DAG); + case ISD::VECTOR_SHUFFLE: return lowerVECTOR_SHUFFLE(Op, DAG); + case ISD::SELECT: return lowerSELECT(Op, DAG); + case ISD::BITCAST: return lowerBITCAST(Op, DAG); + } + return MipsTargetLowering::LowerOperation(Op, DAG); +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/LowerRETURNADDR.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/LowerRETURNADDR.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ded637a4455513a16d891e39639e269a720641e3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/LowerRETURNADDR.cpp @@ -0,0 +1,15 @@ +SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const { + if (verifyReturnAddressArgumentIsConstant(Op, DAG)) + return SDValue(); + if (cast(Op.getOperand(0))->getZExtValue() != 0) { + DAG.getContext()->emitError("return address can be determined only for current frame"); + return SDValue(); + } + MachineFunction &MF = DAG.getMachineFunction(); + MachineFrameInfo &MFI = MF.getFrameInfo(); + MVT VT = Op.getSimpleValueType(); + unsigned RA = ABI.IsN64() ? Mips::RA_64 : Mips::RA; + MFI.setReturnAddressIsTaken(true); + unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT)); + return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/LowerReturn.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/LowerReturn.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1ed075e6ccf9610456191789f39cad7dd5b16736 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/LowerReturn.cpp @@ -0,0 +1,66 @@ +SDValue MipsTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl &Outs, const SmallVectorImpl &OutVals, const SDLoc &DL, SelectionDAG &DAG) const { + SmallVector RVLocs; + MachineFunction &MF = DAG.getMachineFunction(); + MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext()); + CCInfo.AnalyzeReturn(Outs, RetCC_Mips); + SDValue Flag; + SmallVector RetOps(1, Chain); + for (unsigned i = 0; i != RVLocs.size(); ++i) { + SDValue Val = OutVals[i]; + CCValAssign &VA = RVLocs[i]; + assert(VA.isRegLoc() && "Can only return in registers!"); + bool UseUpperBits = false; + switch (VA.getLocInfo()) { + default: + llvm_unreachable("Unknown loc info!"); + case CCValAssign::Full: + break; + case CCValAssign::BCvt: + Val = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Val); + break; + case CCValAssign::AExtUpper: + UseUpperBits = true; + LLVM_FALLTHROUGH; + case CCValAssign::AExt: + Val = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Val); + break; + case CCValAssign::ZExtUpper: + UseUpperBits = true; + LLVM_FALLTHROUGH; + case CCValAssign::ZExt: + Val = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Val); + break; + case CCValAssign::SExtUpper: + UseUpperBits = true; + LLVM_FALLTHROUGH; + case CCValAssign::SExt: + Val = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Val); + break; + } + if (UseUpperBits) { + unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits(); + unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); + Val = DAG.getNode(ISD::SHL, DL, VA.getLocVT(), Val, DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); + } + Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag); + Flag = Chain.getValue(1); + RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); + } + if (MF.getFunction().hasStructRetAttr()) { + MipsFunctionInfo *MipsFI = MF.getInfo(); + unsigned Reg = MipsFI->getSRetReturnReg(); + if (!Reg) + llvm_unreachable("sret virtual register not created in the entry block"); + SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout())); + unsigned V0 = ABI.IsN64() ? Mips::V0_64 : Mips::V0; + Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag); + Flag = Chain.getValue(1); + RetOps.push_back(DAG.getRegister(V0, getPointerTy(DAG.getDataLayout()))); + } + RetOps[0] = Chain;. + if (Flag.getNode()) + RetOps.push_back(Flag); + if (DAG.getMachineFunction().getFunction().hasFnAttribute("interrupt")) + return LowerInterruptReturn(RetOps, DL, DAG); + return DAG.getNode(MipsISD::Ret, DL, MVT::Other, RetOps); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/LowerVASTART.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/LowerVASTART.cpp new file mode 100644 index 0000000000000000000000000000000000000000..82c750e52dc286a4e812e266e95aad7444d81f06 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/LowerVASTART.cpp @@ -0,0 +1,8 @@ +SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const { + MachineFunction &MF = DAG.getMachineFunction(); + MipsFunctionInfo *FuncInfo = MF.getInfo(); + SDLoc DL(Op); + SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), getPointerTy(MF.getDataLayout())); + const Value *SV = cast(Op.getOperand(2))->getValue(); + return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1), MachinePointerInfo(SV)); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/NodeType.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/NodeType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a38352825f56aab99f061204881b1757052b6041 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/NodeType.cpp @@ -0,0 +1,115 @@ +enum NodeType : unsigned { + FIRST_NUMBER = ISD::BUILTIN_OP_END, + JmpLink, + TailCall, + Highest, + Higher, + Hi, + Lo, + GotHi, + TlsHi, + GPRel, + ThreadPointer, + FMS, + FPBrcond, + FPCmp, + FSELECT, + MTC1_D64, + CMovFP_T, + CMovFP_F, + TruncIntFP, + Ret, + ERet, + EH_RETURN, + MFHI, + MFLO, + MTLOHI, + Mult, + Multu, + MAdd, + MAddu, + MSub, + MSubu, + DivRem, + DivRemU, + DivRem16, + DivRemU16, + BuildPairF64, + ExtractElementF64, + Wrapper, + DynAlloc, + Sync, + Ext, + Ins, + CIns, + EXTP, + EXTPDP, + EXTR_S_H, + EXTR_W, + EXTR_R_W, + EXTR_RS_W, + SHILO, + MTHLIP, + MULSAQ_S_W_PH, + MAQ_S_W_PHL, + MAQ_S_W_PHR, + MAQ_SA_W_PHL, + MAQ_SA_W_PHR, + DPAU_H_QBL, + DPAU_H_QBR, + DPSU_H_QBL, + DPSU_H_QBR, + DPAQ_S_W_PH, + DPSQ_S_W_PH, + DPAQ_SA_L_W, + DPSQ_SA_L_W, + DPA_W_PH, + DPS_W_PH, + DPAQX_S_W_PH, + DPAQX_SA_W_PH, + DPAX_W_PH, + DPSX_W_PH, + DPSQX_S_W_PH, + DPSQX_SA_W_PH, + MULSA_W_PH, + MULT, + MULTU, + MADD_DSP, + MADDU_DSP, + MSUB_DSP, + MSUBU_DSP, + SHLL_DSP, + SHRA_DSP, + SHRL_DSP, + SETCC_DSP, + SELECT_CC_DSP, + VALL_ZERO, + VANY_ZERO, + VALL_NONZERO, + VANY_NONZERO, + VCEQ, + VCLE_S, + VCLE_U, + VCLT_S, + VCLT_U, + VSHF, + SHF, + ILVEV, + ILVOD, + ILVL, + ILVR, + PCKEV, + PCKOD, + INSVE, + VNOR, + VEXTRACT_SEXT_ELT, + VEXTRACT_ZEXT_ELT, + LWL = ISD::FIRST_TARGET_MEMORY_OPCODE, + LWR, + SWL, + SWR, + LDL, + LDR, + SDL, + SDR +}; \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/PerformDAGCombine.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/PerformDAGCombine.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b4c27aab8d97ef85c9947073d81e7dab0609a8e5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/PerformDAGCombine.cpp @@ -0,0 +1,34 @@ +SDValue MipsSETargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { + SelectionDAG &DAG = DCI.DAG; + SDValue Val; + switch (N->getOpcode()) { + case ISD::AND: + Val = performANDCombine(N, DAG, DCI, Subtarget); + break; + case ISD::OR: + Val = performORCombine(N, DAG, DCI, Subtarget); + break; + case ISD::MUL: + return performMULCombine(N, DAG, DCI, this, Subtarget); + case ISD::SHL: + Val = performSHLCombine(N, DAG, DCI, Subtarget); + break; + case ISD::SRA: + return performSRACombine(N, DAG, DCI, Subtarget); + case ISD::SRL: + return performSRLCombine(N, DAG, DCI, Subtarget); + case ISD::VSELECT: + return performVSELECTCombine(N, DAG); + case ISD::XOR: + Val = performXORCombine(N, DAG, Subtarget); + break; + case ISD::SETCC: + Val = performSETCCCombine(N, DAG); + break; + } + if (Val.getNode()) { + LLVM_DEBUG(dbgs() << "\nMipsSE DAG Combine:\n"; N->printrWithDepth(dbgs(), &DAG); dbgs() << "\n=> \n"; Val.getNode()->printrWithDepth(dbgs(), &DAG); dbgs() << "\n"); + return Val; + } + return MipsTargetLowering::PerformDAGCombine(N, DCI); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/ReplaceNodeResults.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/ReplaceNodeResults.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8e0b70bb9b6952f3748f9c7143aec894bfccf9c8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/ReplaceNodeResults.cpp @@ -0,0 +1,3 @@ +void MipsTargetLowering::ReplaceNodeResults(SDNode *N, SmallVectorImpl &Results, SelectionDAG &DAG) const { + return LowerOperationWrapper(N, Results, DAG); +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/TargetLowering.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/TargetLowering.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b374c388335c1101e9b9313b761335931a0abe3a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/TargetLowering.cpp @@ -0,0 +1,173 @@ +MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI) : TargetLowering(TM), Subtarget(STI), ABI(TM.getABI()) { + setBooleanContents(ZeroOrOneBooleanContent); + setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); + if (Subtarget.hasMips32r6()) + setBooleanContents(ZeroOrOneBooleanContent, ZeroOrNegativeOneBooleanContent); + for (MVT VT : MVT::integer_valuetypes()) { + setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); + setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); + setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); + } + for (MVT VT : MVT::fp_valuetypes()) { + setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); + setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand); + } + for (MVT VT : MVT::fp_fixedlen_vector_valuetypes()) { + MVT F16VT = MVT::getVectorVT(MVT::f16, VT.getVectorNumElements()); + if (F16VT.isValid()) + setLoadExtAction(ISD::EXTLOAD, VT, F16VT, Expand); + } + setTruncStoreAction(MVT::f32, MVT::f16, Expand); + setTruncStoreAction(MVT::f64, MVT::f16, Expand); + setTruncStoreAction(MVT::f64, MVT::f32, Expand); + AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); + setOperationAction(ISD::BR_JT, MVT::Other, Expand); + setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); + setOperationAction(ISD::BlockAddress, MVT::i32, Custom); + setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); + setOperationAction(ISD::JumpTable, MVT::i32, Custom); + setOperationAction(ISD::ConstantPool, MVT::i32, Custom); + setOperationAction(ISD::SELECT, MVT::f32, Custom); + setOperationAction(ISD::SELECT, MVT::f64, Custom); + setOperationAction(ISD::SELECT, MVT::i32, Custom); + setOperationAction(ISD::SETCC, MVT::f32, Custom); + setOperationAction(ISD::SETCC, MVT::f64, Custom); + setOperationAction(ISD::BRCOND, MVT::Other, Custom); + setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); + setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); + setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); + if (!(TM.Options.NoNaNsFPMath || Subtarget.inAbs2008Mode())) { + setOperationAction(ISD::FABS, MVT::f32, Custom); + setOperationAction(ISD::FABS, MVT::f64, Custom); + } + if (Subtarget.isGP64bit()) { + setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); + setOperationAction(ISD::BlockAddress, MVT::i64, Custom); + setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); + setOperationAction(ISD::JumpTable, MVT::i64, Custom); + setOperationAction(ISD::ConstantPool, MVT::i64, Custom); + setOperationAction(ISD::SELECT, MVT::i64, Custom); + setOperationAction(ISD::LOAD, MVT::i64, Custom); + setOperationAction(ISD::STORE, MVT::i64, Custom); + setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); + setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom); + setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom); + setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom); + } + if (!Subtarget.isGP64bit()) { + setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); + setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); + setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); + } + setOperationAction(ISD::EH_DWARF_CFA, MVT::i32, Custom); + if (Subtarget.isGP64bit()) + setOperationAction(ISD::EH_DWARF_CFA, MVT::i64, Custom); + setOperationAction(ISD::SDIV, MVT::i32, Expand); + setOperationAction(ISD::SREM, MVT::i32, Expand); + setOperationAction(ISD::UDIV, MVT::i32, Expand); + setOperationAction(ISD::UREM, MVT::i32, Expand); + setOperationAction(ISD::SDIV, MVT::i64, Expand); + setOperationAction(ISD::SREM, MVT::i64, Expand); + setOperationAction(ISD::UDIV, MVT::i64, Expand); + setOperationAction(ISD::UREM, MVT::i64, Expand); + setOperationAction(ISD::BR_CC, MVT::f32, Expand); + setOperationAction(ISD::BR_CC, MVT::f64, Expand); + setOperationAction(ISD::BR_CC, MVT::i32, Expand); + setOperationAction(ISD::BR_CC, MVT::i64, Expand); + setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); + setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); + setOperationAction(ISD::SELECT_CC, MVT::f32, Expand); + setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); + setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); + setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); + setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); + setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); + setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); + if (Subtarget.hasCnMips()) { + setOperationAction(ISD::CTPOP, MVT::i32, Legal); + setOperationAction(ISD::CTPOP, MVT::i64, Legal); + } + else { + setOperationAction(ISD::CTPOP, MVT::i32, Expand); + setOperationAction(ISD::CTPOP, MVT::i64, Expand); + } + setOperationAction(ISD::CTTZ, MVT::i32, Expand); + setOperationAction(ISD::CTTZ, MVT::i64, Expand); + setOperationAction(ISD::ROTL, MVT::i32, Expand); + setOperationAction(ISD::ROTL, MVT::i64, Expand); + setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); + setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); + if (!Subtarget.hasMips32r2()) + setOperationAction(ISD::ROTR, MVT::i32, Expand); + if (!Subtarget.hasMips64r2()) + setOperationAction(ISD::ROTR, MVT::i64, Expand); + setOperationAction(ISD::FSIN, MVT::f32, Expand); + setOperationAction(ISD::FSIN, MVT::f64, Expand); + setOperationAction(ISD::FCOS, MVT::f32, Expand); + setOperationAction(ISD::FCOS, MVT::f64, Expand); + setOperationAction(ISD::FSINCOS, MVT::f32, Expand); + setOperationAction(ISD::FSINCOS, MVT::f64, Expand); + setOperationAction(ISD::FPOW, MVT::f32, Expand); + setOperationAction(ISD::FPOW, MVT::f64, Expand); + setOperationAction(ISD::FLOG, MVT::f32, Expand); + setOperationAction(ISD::FLOG2, MVT::f32, Expand); + setOperationAction(ISD::FLOG10, MVT::f32, Expand); + setOperationAction(ISD::FEXP, MVT::f32, Expand); + setOperationAction(ISD::FMA, MVT::f32, Expand); + setOperationAction(ISD::FMA, MVT::f64, Expand); + setOperationAction(ISD::FREM, MVT::f32, Expand); + setOperationAction(ISD::FREM, MVT::f64, Expand); + setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand); + setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand); + setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand); + setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand); + setOperationAction(ISD::EH_RETURN, MVT::Other, Custom); + setOperationAction(ISD::VASTART, MVT::Other, Custom); + setOperationAction(ISD::VAARG, MVT::Other, Custom); + setOperationAction(ISD::VACOPY, MVT::Other, Expand); + setOperationAction(ISD::VAEND, MVT::Other, Expand); + setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); + setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); + if (!Subtarget.isGP64bit()) { + setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand); + setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand); + } + if (!Subtarget.hasMips32r2()) { + setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); + setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); + } + if (!Subtarget.hasMips32() || Subtarget.inMips16Mode()) + setOperationAction(ISD::CTLZ, MVT::i32, Expand); + if (!Subtarget.hasMips64()) + setOperationAction(ISD::CTLZ, MVT::i64, Expand); + if (!Subtarget.hasMips32r2()) + setOperationAction(ISD::BSWAP, MVT::i32, Expand); + if (!Subtarget.hasMips64r2()) + setOperationAction(ISD::BSWAP, MVT::i64, Expand); + if (Subtarget.isGP64bit()) { + setLoadExtAction(ISD::SEXTLOAD, MVT::i64, MVT::i32, Custom); + setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, MVT::i32, Custom); + setLoadExtAction(ISD::EXTLOAD, MVT::i64, MVT::i32, Custom); + setTruncStoreAction(MVT::i64, MVT::i32, Custom); + } + setOperationAction(ISD::TRAP, MVT::Other, Legal); + setTargetDAGCombine(ISD::SDIVREM); + setTargetDAGCombine(ISD::UDIVREM); + setTargetDAGCombine(ISD::SELECT); + setTargetDAGCombine(ISD::AND); + setTargetDAGCombine(ISD::OR); + setTargetDAGCombine(ISD::ADD); + setTargetDAGCombine(ISD::SUB); + setTargetDAGCombine(ISD::AssertZext); + setTargetDAGCombine(ISD::SHL); + if (ABI.IsO32()) { + setLibcallName(RTLIB::SHL_I128, nullptr); + setLibcallName(RTLIB::SRL_I128, nullptr); + setLibcallName(RTLIB::SRA_I128, nullptr); + } + setMinFunctionAlignment(Subtarget.isGP64bit() ? Align(8) : Align(4)); + setMinStackArgumentAlignment((ABI.IsN32() || ABI.IsN64()) ? Align(8) : Align(4)); + setStackPointerRegisterToSaveRestore(ABI.IsN64() ? Mips::SP_64 : Mips::SP); + MaxStoresPerMemcpy = 16; + isMicroMips = Subtarget.inMicroMipsMode(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/analyzeInputArgs.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/analyzeInputArgs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/analyzeInputArgs.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/analyzeOutputArgs.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/analyzeOutputArgs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/analyzeOutputArgs.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/computeKnownBitsForTargetNode.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/computeKnownBitsForTargetNode.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/computeKnownBitsForTargetNode.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/convertSelectOfConstantsToMath.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/convertSelectOfConstantsToMath.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/convertSelectOfConstantsToMath.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/convertSetCCLogicToBitwiseLogic.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/convertSetCCLogicToBitwiseLogic.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/convertSetCCLogicToBitwiseLogic.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/decomposeMulByConstant.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/decomposeMulByConstant.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/decomposeMulByConstant.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/emitLeadingFence.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/emitLeadingFence.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/emitLeadingFence.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/emitMaskedAtomicCmpXchgIntrinsic.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/emitMaskedAtomicCmpXchgIntrinsic.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d24252a436720a3ccdecb69c990fff58341ff97c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/emitMaskedAtomicCmpXchgIntrinsic.cpp @@ -0,0 +1,2 @@ +None + diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/emitMaskedAtomicRMWIntrinsic.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/emitMaskedAtomicRMWIntrinsic.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/emitMaskedAtomicRMWIntrinsic.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/emitTrailingFence.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/emitTrailingFence.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/emitTrailingFence.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/getAddr.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/getAddr.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/getAddr.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/getConstraintType.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/getConstraintType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d8529203a68b93db156ea88f4c58badf30013605 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/getConstraintType.cpp @@ -0,0 +1,19 @@ +MipsTargetLowering::ConstraintType MipsTargetLowering::getConstraintType(StringRef Constraint) const { + if (Constraint.size() == 1) { + switch (Constraint[0]) { + default : break; + case 'd': + case 'y': + case 'f': + case 'c': + case 'l': + case 'x': + return C_RegisterClass; + case 'R': + return C_Memory; + } + } + if (Constraint == "ZC") + return C_Memory; + return TargetLowering::getConstraintType(Constraint); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/getDynamicTLSAddr.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/getDynamicTLSAddr.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/getDynamicTLSAddr.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/getExceptionPointerRegister.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/getExceptionPointerRegister.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2e1945b520bebcf77f44fd1b55ba871b480d9979 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/getExceptionPointerRegister.cpp @@ -0,0 +1,3 @@ +Register getExceptionPointerRegister(const Constant *PersonalityFn) const override { + return ABI.IsN64() ? Mips::A0_64 : Mips::A0; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/getExceptionSelectorRegister.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/getExceptionSelectorRegister.cpp new file mode 100644 index 0000000000000000000000000000000000000000..524ffc7c7a6f16e757f2bce1263a2c3b76aa8e7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/getExceptionSelectorRegister.cpp @@ -0,0 +1,3 @@ +Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override { + return ABI.IsN64() ? Mips::A1_64 : Mips::A1; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/getExtendForAtomicCmpSwapArg.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/getExtendForAtomicCmpSwapArg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/getExtendForAtomicCmpSwapArg.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/getExtendForAtomicOps.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/getExtendForAtomicOps.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2bdaa6084dd596ee35663f176faa01eba5d98abc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/getExtendForAtomicOps.cpp @@ -0,0 +1,3 @@ +ISD::NodeType getExtendForAtomicOps() const override { + return ISD::SIGN_EXTEND; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/getInlineAsmMemConstraint.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/getInlineAsmMemConstraint.cpp new file mode 100644 index 0000000000000000000000000000000000000000..04c12c2b8a5307ff84006a5e7df9df7f9f5c5066 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/getInlineAsmMemConstraint.cpp @@ -0,0 +1,9 @@ +unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override { + if (ConstraintCode == "o") + return InlineAsm::Constraint_o; + if (ConstraintCode == "R") + return InlineAsm::Constraint_R; + if (ConstraintCode == "ZC") + return InlineAsm::Constraint_ZC; + return TargetLowering::getInlineAsmMemConstraint(ConstraintCode); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/getRegForInlineAsmConstraint.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/getRegForInlineAsmConstraint.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c4d6cb04cdaf5d170a432c7141d5bcd31383559f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/getRegForInlineAsmConstraint.cpp @@ -0,0 +1,56 @@ +std::pair MipsTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const { + if (Constraint.size() == 1) { + switch (Constraint[0]) { + case 'd': + case 'y': + case 'r': + if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) { + if (Subtarget.inMips16Mode()) + return std::make_pair(0U, &Mips::CPU16RegsRegClass); + return std::make_pair(0U, &Mips::GPR32RegClass); + } + if (VT == MVT::i64 && !Subtarget.isGP64bit()) + return std::make_pair(0U, &Mips::GPR32RegClass); + if (VT == MVT::i64 && Subtarget.isGP64bit()) + return std::make_pair(0U, &Mips::GPR64RegClass); + return std::make_pair(0U, nullptr); + case 'f': + if (VT == MVT::v16i8) + return std::make_pair(0U, &Mips::MSA128BRegClass); + else if (VT == MVT::v8i16 || VT == MVT::v8f16) + return std::make_pair(0U, &Mips::MSA128HRegClass); + else if (VT == MVT::v4i32 || VT == MVT::v4f32) + return std::make_pair(0U, &Mips::MSA128WRegClass); + else if (VT == MVT::v2i64 || VT == MVT::v2f64) + return std::make_pair(0U, &Mips::MSA128DRegClass); + else if (VT == MVT::f32) + return std::make_pair(0U, &Mips::FGR32RegClass); + else if ((VT == MVT::f64) && (!Subtarget.isSingleFloat())) { + if (Subtarget.isFP64bit()) + return std::make_pair(0U, &Mips::FGR64RegClass); + return std::make_pair(0U, &Mips::AFGR64RegClass); + } + break; + case 'c': + if (VT == MVT::i32) + return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass); + if (VT == MVT::i64) + return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass); + return std::make_pair(0U, nullptr); + case 'l': + if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) + return std::make_pair((unsigned)Mips::LO0, &Mips::LO32RegClass); + return std::make_pair((unsigned)Mips::LO0_64, &Mips::LO64RegClass); + case 'x': + return std::make_pair(0U, nullptr); + } + } + if (!Constraint.empty()) { + std::pair R; + R = parseRegForInlineAsmConstraint(Constraint, VT); + if (R.second) + return R; + } + return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT); +} + diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/getRegisterByName.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/getRegisterByName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1c5d4d71ea246662da31c1159df7bf2f85432788 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/getRegisterByName.cpp @@ -0,0 +1,13 @@ +Register MipsTargetLowering::getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const { + if (Subtarget.isGP64bit()) { + Register Reg = StringSwitch(RegName).Case("$28", Mips::GP_64).Default(Register()); + if (Reg) + return Reg; + } + else { + Register Reg = StringSwitch(RegName).Case("$28", Mips::GP).Default(Register()); + if (Reg) + return Reg; + } + report_fatal_error("Invalid register name global variable"); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/getSetCCResultType.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/getSetCCResultType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fe00ebaa7cd5963c92ec9096a55e880e01f1a0fc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/getSetCCResultType.cpp @@ -0,0 +1,6 @@ +EVT MipsTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &, EVT VT) const { + if (!VT.isVector()) { + return MVT::i32; + } + return VT.changeVectorElementTypeToInteger(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/getStaticTLSAddr.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/getStaticTLSAddr.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/getStaticTLSAddr.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/getSubtarget.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/getSubtarget.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/getSubtarget.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/getTargetNodeName.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/getTargetNodeName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..999d3eb5bc14010c14260323f1dcec49e3115019 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/getTargetNodeName.cpp @@ -0,0 +1,118 @@ +const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const { + switch ((MipsISD::NodeType)Opcode) { + case MipsISD::FIRST_NUMBER: break; + case MipsISD::JmpLink: return "MipsISD::JmpLink"; + case MipsISD::TailCall: return "MipsISD::TailCall"; + case MipsISD::Highest: return "MipsISD::Highest"; + case MipsISD::Higher: return "MipsISD::Higher"; + case MipsISD::Hi: return "MipsISD::Hi"; + case MipsISD::Lo: return "MipsISD::Lo"; + case MipsISD::GotHi: return "MipsISD::GotHi"; + case MipsISD::TlsHi: return "MipsISD::TlsHi"; + case MipsISD::GPRel: return "MipsISD::GPRel"; + case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer"; + case MipsISD::Ret: return "MipsISD::Ret"; + case MipsISD::ERet: return "MipsISD::ERet"; + case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN"; + case MipsISD::FMS: return "MipsISD::FMS"; + case MipsISD::FPBrcond: return "MipsISD::FPBrcond"; + case MipsISD::FPCmp: return "MipsISD::FPCmp"; + case MipsISD::FSELECT: return "MipsISD::FSELECT"; + case MipsISD::MTC1_D64: return "MipsISD::MTC1_D64"; + case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T"; + case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F"; + case MipsISD::TruncIntFP: return "MipsISD::TruncIntFP"; + case MipsISD::MFHI: return "MipsISD::MFHI"; + case MipsISD::MFLO: return "MipsISD::MFLO"; + case MipsISD::MTLOHI: return "MipsISD::MTLOHI"; + case MipsISD::Mult: return "MipsISD::Mult"; + case MipsISD::Multu: return "MipsISD::Multu"; + case MipsISD::MAdd: return "MipsISD::MAdd"; + case MipsISD::MAddu: return "MipsISD::MAddu"; + case MipsISD::MSub: return "MipsISD::MSub"; + case MipsISD::MSubu: return "MipsISD::MSubu"; + case MipsISD::DivRem: return "MipsISD::DivRem"; + case MipsISD::DivRemU: return "MipsISD::DivRemU"; + case MipsISD::DivRem16: return "MipsISD::DivRem16"; + case MipsISD::DivRemU16: return "MipsISD::DivRemU16"; + case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64"; + case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64"; + case MipsISD::Wrapper: return "MipsISD::Wrapper"; + case MipsISD::DynAlloc: return "MipsISD::DynAlloc"; + case MipsISD::Sync: return "MipsISD::Sync"; + case MipsISD::Ext: return "MipsISD::Ext"; + case MipsISD::Ins: return "MipsISD::Ins"; + case MipsISD::CIns: return "MipsISD::CIns"; + case MipsISD::LWL: return "MipsISD::LWL"; + case MipsISD::LWR: return "MipsISD::LWR"; + case MipsISD::SWL: return "MipsISD::SWL"; + case MipsISD::SWR: return "MipsISD::SWR"; + case MipsISD::LDL: return "MipsISD::LDL"; + case MipsISD::LDR: return "MipsISD::LDR"; + case MipsISD::SDL: return "MipsISD::SDL"; + case MipsISD::SDR: return "MipsISD::SDR"; + case MipsISD::EXTP: return "MipsISD::EXTP"; + case MipsISD::EXTPDP: return "MipsISD::EXTPDP"; + case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H"; + case MipsISD::EXTR_W: return "MipsISD::EXTR_W"; + case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W"; + case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W"; + case MipsISD::SHILO: return "MipsISD::SHILO"; + case MipsISD::MTHLIP: return "MipsISD::MTHLIP"; + case MipsISD::MULSAQ_S_W_PH: return "MipsISD::MULSAQ_S_W_PH"; + case MipsISD::MAQ_S_W_PHL: return "MipsISD::MAQ_S_W_PHL"; + case MipsISD::MAQ_S_W_PHR: return "MipsISD::MAQ_S_W_PHR"; + case MipsISD::MAQ_SA_W_PHL: return "MipsISD::MAQ_SA_W_PHL"; + case MipsISD::MAQ_SA_W_PHR: return "MipsISD::MAQ_SA_W_PHR"; + case MipsISD::DPAU_H_QBL: return "MipsISD::DPAU_H_QBL"; + case MipsISD::DPAU_H_QBR: return "MipsISD::DPAU_H_QBR"; + case MipsISD::DPSU_H_QBL: return "MipsISD::DPSU_H_QBL"; + case MipsISD::DPSU_H_QBR: return "MipsISD::DPSU_H_QBR"; + case MipsISD::DPAQ_S_W_PH: return "MipsISD::DPAQ_S_W_PH"; + case MipsISD::DPSQ_S_W_PH: return "MipsISD::DPSQ_S_W_PH"; + case MipsISD::DPAQ_SA_L_W: return "MipsISD::DPAQ_SA_L_W"; + case MipsISD::DPSQ_SA_L_W: return "MipsISD::DPSQ_SA_L_W"; + case MipsISD::DPA_W_PH: return "MipsISD::DPA_W_PH"; + case MipsISD::DPS_W_PH: return "MipsISD::DPS_W_PH"; + case MipsISD::DPAQX_S_W_PH: return "MipsISD::DPAQX_S_W_PH"; + case MipsISD::DPAQX_SA_W_PH: return "MipsISD::DPAQX_SA_W_PH"; + case MipsISD::DPAX_W_PH: return "MipsISD::DPAX_W_PH"; + case MipsISD::DPSX_W_PH: return "MipsISD::DPSX_W_PH"; + case MipsISD::DPSQX_S_W_PH: return "MipsISD::DPSQX_S_W_PH"; + case MipsISD::DPSQX_SA_W_PH: return "MipsISD::DPSQX_SA_W_PH"; + case MipsISD::MULSA_W_PH: return "MipsISD::MULSA_W_PH"; + case MipsISD::MULT: return "MipsISD::MULT"; + case MipsISD::MULTU: return "MipsISD::MULTU"; + case MipsISD::MADD_DSP: return "MipsISD::MADD_DSP"; + case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP"; + case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP"; + case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP"; + case MipsISD::SHLL_DSP: return "MipsISD::SHLL_DSP"; + case MipsISD::SHRA_DSP: return "MipsISD::SHRA_DSP"; + case MipsISD::SHRL_DSP: return "MipsISD::SHRL_DSP"; + case MipsISD::SETCC_DSP: return "MipsISD::SETCC_DSP"; + case MipsISD::SELECT_CC_DSP: return "MipsISD::SELECT_CC_DSP"; + case MipsISD::VALL_ZERO: return "MipsISD::VALL_ZERO"; + case MipsISD::VANY_ZERO: return "MipsISD::VANY_ZERO"; + case MipsISD::VALL_NONZERO: return "MipsISD::VALL_NONZERO"; + case MipsISD::VANY_NONZERO: return "MipsISD::VANY_NONZERO"; + case MipsISD::VCEQ: return "MipsISD::VCEQ"; + case MipsISD::VCLE_S: return "MipsISD::VCLE_S"; + case MipsISD::VCLE_U: return "MipsISD::VCLE_U"; + case MipsISD::VCLT_S: return "MipsISD::VCLT_S"; + case MipsISD::VCLT_U: return "MipsISD::VCLT_U"; + case MipsISD::VEXTRACT_SEXT_ELT: return "MipsISD::VEXTRACT_SEXT_ELT"; + case MipsISD::VEXTRACT_ZEXT_ELT: return "MipsISD::VEXTRACT_ZEXT_ELT"; + case MipsISD::VNOR: return "MipsISD::VNOR"; + case MipsISD::VSHF: return "MipsISD::VSHF"; + case MipsISD::SHF: return "MipsISD::SHF"; + case MipsISD::ILVEV: return "MipsISD::ILVEV"; + case MipsISD::ILVOD: return "MipsISD::ILVOD"; + case MipsISD::ILVL: return "MipsISD::ILVL"; + case MipsISD::ILVR: return "MipsISD::ILVR"; + case MipsISD::PCKEV: return "MipsISD::PCKEV"; + case MipsISD::PCKOD: return "MipsISD::PCKOD"; + case MipsISD::INSVE: return "MipsISD::INSVE"; + } + return nullptr; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/getTgtMemIntrinsic.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/getTgtMemIntrinsic.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/getTgtMemIntrinsic.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/hasBitPreservingFPLogic.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/hasBitPreservingFPLogic.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/hasBitPreservingFPLogic.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/isCheapToSpeculateCtlz.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/isCheapToSpeculateCtlz.cpp new file mode 100644 index 0000000000000000000000000000000000000000..427f606640a0f495babbc3c5472fed65979665f6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/isCheapToSpeculateCtlz.cpp @@ -0,0 +1,3 @@ +bool MipsTargetLowering::isCheapToSpeculateCtlz() const { + return Subtarget.hasMips32(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/isCheapToSpeculateCttz.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/isCheapToSpeculateCttz.cpp new file mode 100644 index 0000000000000000000000000000000000000000..169d4b4109f983c5149a60aca7d2757d876881b3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/isCheapToSpeculateCttz.cpp @@ -0,0 +1,3 @@ +bool MipsTargetLowering::isCheapToSpeculateCttz() const { + return Subtarget.hasMips32(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/isDesirableToCommuteWithShift.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/isDesirableToCommuteWithShift.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/isDesirableToCommuteWithShift.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/isEligibleForTailCallOptimization.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/isEligibleForTailCallOptimization.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a11da12c981206c45489e9ede21981c97f116aba --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/isEligibleForTailCallOptimization.cpp @@ -0,0 +1,9 @@ +bool MipsSETargetLowering::isEligibleForTailCallOptimization(const CCState &CCInfo, unsigned NextStackOffset, const MipsFunctionInfo &FI) const { + if (!UseMipsTailCalls) + return false; + if (FI.isISR()) + return false; + if (CCInfo.getInRegsParamsCount() > 0 || FI.hasByvalArg()) + return false; + return NextStackOffset <= FI.getIncomingArgSize(); +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/isFMAFasterThanFMulAndFAdd.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/isFMAFasterThanFMulAndFAdd.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/isFMAFasterThanFMulAndFAdd.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/isFPImmLegal.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/isFPImmLegal.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9419a0fddfba1adb1a506c85ee0e7d6b360839c5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/isFPImmLegal.cpp @@ -0,0 +1,7 @@ +bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const { + if (VT != MVT::f32 && VT != MVT::f64) + return false; + if (Imm.isNegZero()) + return false; + return Imm.isZero(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/isLegalAddImmediate.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/isLegalAddImmediate.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/isLegalAddImmediate.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/isLegalAddressingMode.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/isLegalAddressingMode.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bce29b2aa473dfb01a1adc6b39d25eec12f141ab --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/isLegalAddressingMode.cpp @@ -0,0 +1,15 @@ +bool MipsTargetLowering::isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I) const { + if (AM.BaseGV) + return false; + switch (AM.Scale) { + case 0: + break; + case 1: + if (!AM.HasBaseReg) + break; + return false; + default: + return false; + } + return true; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/isLegalICmpImmediate.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/isLegalICmpImmediate.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/isLegalICmpImmediate.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/isSExtCheaperThanZExt.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/isSExtCheaperThanZExt.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/isSExtCheaperThanZExt.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/isTruncateFree.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/isTruncateFree.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/isTruncateFree.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/isTruncateFree2.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/isTruncateFree2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/isTruncateFree2.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/isZExtFree.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/isZExtFree.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/isZExtFree.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/lowerEXTRACT_VECTOR_ELT.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/lowerEXTRACT_VECTOR_ELT.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c7f0b8be13658b20f7e13eee561be03722d32593 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/lowerEXTRACT_VECTOR_ELT.cpp @@ -0,0 +1,14 @@ +SDValue MipsSETargetLowering::lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const { + SDLoc DL(Op); + EVT ResTy = Op->getValueType(0); + SDValue Op0 = Op->getOperand(0); + EVT VecTy = Op0->getValueType(0); + if (!VecTy.is128BitVector()) + return SDValue(); + if (ResTy.isInteger()) { + SDValue Op1 = Op->getOperand(1); + EVT EltTy = VecTy.getVectorElementType(); + return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, DL, ResTy, Op0, Op1, DAG.getValueType(EltTy)); + } + return Op; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/lowerINSERT_VECTOR_ELT.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/lowerINSERT_VECTOR_ELT.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/lowerINSERT_VECTOR_ELT.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/lowerSELECT.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/lowerSELECT.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8ccc7415a4e7fc3ff6f6faf8cb2df39facab5474 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/lowerSELECT.cpp @@ -0,0 +1,7 @@ +SDValue MipsTargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const { + assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); + SDValue Cond = createFPCmp(DAG, Op.getOperand(0)); + if (Cond.getOpcode() != MipsISD::FPCmp) + return Op; + return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2), SDLoc(Op)); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/lowerSPLATVECTOR.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/lowerSPLATVECTOR.cpp new file mode 100644 index 0000000000000000000000000000000000000000..dc4822b4dace5d5d62f234df92749f851e92acbc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/lowerSPLATVECTOR.cpp @@ -0,0 +1,3 @@ +None + + diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/lowerShiftLeftParts.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/lowerShiftLeftParts.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1fa999e2c8ce2bc3c16770b5abd0a2f1aa9900a0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/lowerShiftLeftParts.cpp @@ -0,0 +1,17 @@ +SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const { + SDLoc DL(Op); + MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32; + SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); + SDValue Shamt = Op.getOperand(2); + SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, DAG.getConstant(-1, DL, MVT::i32)); + SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo, DAG.getConstant(1, DL, VT)); + SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, Not); + SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt); + SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo); + SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt); + SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32)); + Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, DAG.getConstant(0, DL, VT), ShiftLeftLo); + Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or); + SDValue Ops[2] = {Lo, Hi}; + return DAG.getMergeValues(Ops, DL); +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/lowerShiftRightParts.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/lowerShiftRightParts.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b15ec88f4c37aaf44b6a8c2e28d3acfcac6e939a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/lowerShiftRightParts.cpp @@ -0,0 +1,22 @@ +SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const { + SDLoc DL(Op); + SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); + SDValue Shamt = Op.getOperand(2); + MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32; + SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, DAG.getConstant(-1, DL, MVT::i32)); + SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, DAG.getConstant(1, DL, VT)); + SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeft1Hi, Not); + SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt); + SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo); + SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, Shamt); + SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32)); + SDValue Ext = DAG.getNode(ISD::SRA, DL, VT, Hi, DAG.getConstant(VT.getSizeInBits() - 1, DL, VT)); + if (!(Subtarget.hasMips4() || Subtarget.hasMips32())) { + SDVTList VTList = DAG.getVTList(VT, VT); + return DAG.getNode(Subtarget.isGP64bit() ? Mips::PseudoD_SELECT_I64 : Mips::PseudoD_SELECT_I, DL, VTList, Cond, ShiftRightHi, IsSRA ? Ext : DAG.getConstant(0, DL, VT), Or, ShiftRightHi); + } + Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or); + Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, IsSRA ? Ext : DAG.getConstant(0, DL, VT), ShiftRightHi); + SDValue Ops[2] = {Lo, Hi}; + return DAG.getMergeValues(Ops, DL); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/lowerVectorMaskExt.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/lowerVectorMaskExt.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/lowerVectorMaskExt.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/lowerVectorMaskTrunc.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/lowerVectorMaskTrunc.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/lowerVectorMaskTrunc.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/mayBeEmittedAsTailCall.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/mayBeEmittedAsTailCall.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/mayBeEmittedAsTailCall.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/normaliseSetCC.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/normaliseSetCC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/normaliseSetCC.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/normalizeSetCC.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/normalizeSetCC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f68f25a787d6d9d179404a12f57ee6bc55abf05a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/normalizeSetCC.cpp @@ -0,0 +1,2 @@ +static void normaliseSetCC(SDValue &LHS, SDValue &RHS, ISD::CondCode &CC) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/shouldConsiderGEPOffsetSplit.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/shouldConsiderGEPOffsetSplit.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/shouldConsiderGEPOffsetSplit.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/shouldConvertConstantLoadToIntImm.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/shouldConvertConstantLoadToIntImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/shouldConvertConstantLoadToIntImm.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/shouldExpandAtomicCmpXchgInIR.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/shouldExpandAtomicCmpXchgInIR.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/shouldExpandAtomicCmpXchgInIR.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/shouldExpandAtomicRMWInIR.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/shouldExpandAtomicRMWInIR.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/shouldExpandAtomicRMWInIR.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/shouldExpandShift.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/shouldExpandShift.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/shouldExpandShift.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/shouldExtendTypeInLibCall.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/shouldExtendTypeInLibCall.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/shouldExtendTypeInLibCall.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/shouldInsertFencesForAtomic.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/shouldInsertFencesForAtomic.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8633411d86591074b31a54b78e3486a650b9eb13 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/shouldInsertFencesForAtomic.cpp @@ -0,0 +1,3 @@ +bool shouldInsertFencesForAtomic(const Instruction *I) const override { + return true; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/shouldSignExtendTypeInLibCall.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/shouldSignExtendTypeInLibCall.cpp new file mode 100644 index 0000000000000000000000000000000000000000..959ee62f318ee63e3f1f4208c95ae43a1a6e7761 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/shouldSignExtendTypeInLibCall.cpp @@ -0,0 +1,5 @@ +bool MipsTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const { + if ((ABI.IsN32() || ABI.IsN64()) && Type == MVT::i32) + return true; + return IsSigned; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/targetShrinkDemandedConstant.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/targetShrinkDemandedConstant.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/targetShrinkDemandedConstant.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/validateCCReservedRegs.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/validateCCReservedRegs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/ISelLowering/validateCCReservedRegs.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/InstructionSelector/InstructionSelector.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/InstructionSelector/InstructionSelector.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4dec9cfa317b44f43b2ec7db58442782f2df351e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/InstructionSelector/InstructionSelector.cpp @@ -0,0 +1,9 @@ +MipsInstructionSelector::MipsInstructionSelector(const MipsTargetMachine &TM, const MipsSubtarget &STI, const MipsRegisterBankInfo &RBI) : InstructionSelector(), TM(TM), STI(STI), TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()), RBI(RBI), +#define GET_GLOBALISEL_PREDICATES_INIT +#include "MipsGenGlobalISel.inc" +#undef GET_GLOBALISEL_PREDICATES_INIT +#define GET_GLOBALISEL_TEMPORARIES_INIT +#include "MipsGenGlobalISel.inc" +#undef GET_GLOBALISEL_TEMPORARIES_INIT +{ +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/InstructionSelector/createInstructionSelector.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/InstructionSelector/createInstructionSelector.cpp new file mode 100644 index 0000000000000000000000000000000000000000..dad172a8ea90b139f00256911eedcffbae14848d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/InstructionSelector/createInstructionSelector.cpp @@ -0,0 +1,3 @@ +InstructionSelector *createMipsInstructionSelector(const MipsTargetMachine &TM, MipsSubtarget &Subtarget, MipsRegisterBankInfo &RBI) { + return new MipsInstructionSelector(TM, Subtarget, RBI); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/InstructionSelector/getName.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/InstructionSelector/getName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3070f67f8b2d72c6473a6bf2cc4639c82757caaa --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/InstructionSelector/getName.cpp @@ -0,0 +1,3 @@ +static const char *getName() { + return DEBUG_TYPE; +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/InstructionSelector/select.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/InstructionSelector/select.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5a17b427bb0cd822697fc1bb9f4a5c2c68b1a435 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/InstructionSelector/select.cpp @@ -0,0 +1,443 @@ +bool MipsInstructionSelector::select(MachineInstr &I) { + MachineBasicBlock &MBB = *I.getParent(); + MachineFunction &MF = *MBB.getParent(); + MachineRegisterInfo &MRI = MF.getRegInfo(); + if (!isPreISelGenericOpcode(I.getOpcode())) { + if (I.isCopy()) + return selectCopy(I, MRI); + return true; + } + if (I.getOpcode() == Mips::G_MUL && isRegInGprb(I.getOperand(0).getReg(), MRI)) { + MachineInstr *Mul = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MUL)).add(I.getOperand(0)).add(I.getOperand(1)).add(I.getOperand(2)); + if (!constrainSelectedInstRegOperands(*Mul, TII, TRI, RBI)) + return false; + Mul->getOperand(3).setIsDead(true); + Mul->getOperand(4).setIsDead(true); + I.eraseFromParent(); + return true; + } + if (selectImpl(I, *CoverageInfo)) + return true; + MachineInstr *MI = nullptr; + using namespace TargetOpcode; + switch (I.getOpcode()) { + case G_UMULH: { + Register PseudoMULTuReg = MRI.createVirtualRegister(&Mips::ACC64RegClass); + MachineInstr *PseudoMULTu, *PseudoMove; + PseudoMULTu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoMULTu)).addDef(PseudoMULTuReg).add(I.getOperand(1)).add(I.getOperand(2)); + if (!constrainSelectedInstRegOperands(*PseudoMULTu, TII, TRI, RBI)) + return false; + PseudoMove = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoMFHI)).addDef(I.getOperand(0).getReg()).addUse(PseudoMULTuReg); + if (!constrainSelectedInstRegOperands(*PseudoMove, TII, TRI, RBI)) + return false; + + I.eraseFromParent(); + return true; + } + case G_PTR_ADD: { + MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu)).add(I.getOperand(0)).add(I.getOperand(1)).add(I.getOperand(2)); + break; + } + case G_INTTOPTR: + case G_PTRTOINT: { + I.setDesc(TII.get(COPY)); + return selectCopy(I, MRI); + } + case G_FRAME_INDEX: { + MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu)).add(I.getOperand(0)).add(I.getOperand(1)).addImm(0); + break; + } + case G_BRCOND: { + MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::BNE)).add(I.getOperand(0)).addUse(Mips::ZERO).add(I.getOperand(1)); + break; + } + case G_BRJT: { + unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize(MF.getDataLayout()); + assert(isPowerOf2_32(EntrySize) && "Non-power-of-two jump-table entry size not supported."); + Register JTIndex = MRI.createVirtualRegister(&Mips::GPR32RegClass); + MachineInstr *SLL = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::SLL)).addDef(JTIndex).addUse(I.getOperand(2).getReg()).addImm(Log2_32(EntrySize)); + if (!constrainSelectedInstRegOperands(*SLL, TII, TRI, RBI)) + return false; + Register DestAddress = MRI.createVirtualRegister(&Mips::GPR32RegClass); + MachineInstr *ADDu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu)).addDef(DestAddress).addUse(I.getOperand(0).getReg()).addUse(JTIndex); + if (!constrainSelectedInstRegOperands(*ADDu, TII, TRI, RBI)) + return false; + Register Dest = MRI.createVirtualRegister(&Mips::GPR32RegClass); + MachineInstr *LW = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW)).addDef(Dest).addUse(DestAddress).addJumpTableIndex(I.getOperand(1).getIndex(), MipsII::MO_ABS_LO).addMemOperand(MF.getMachineMemOperand(MachinePointerInfo(), MachineMemOperand::MOLoad, 4, Align(4))); + if (!constrainSelectedInstRegOperands(*LW, TII, TRI, RBI)) + return false; + if (MF.getTarget().isPositionIndependent()) { + Register DestTmp = MRI.createVirtualRegister(&Mips::GPR32RegClass); + LW->getOperand(0).setReg(DestTmp); + MachineInstr *ADDu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu)).addDef(Dest).addUse(DestTmp).addUse(MF.getInfo()->getGlobalBaseRegForGlobalISel(MF)); + if (!constrainSelectedInstRegOperands(*ADDu, TII, TRI, RBI)) + return false; + } + MachineInstr *Branch = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoIndirectBranch)).addUse(Dest); + if (!constrainSelectedInstRegOperands(*Branch, TII, TRI, RBI)) + return false; + I.eraseFromParent(); + return true; + } + case G_BRINDIRECT: { + MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoIndirectBranch)).add(I.getOperand(0)); + break; + } + case G_PHI: { + const Register DestReg = I.getOperand(0).getReg(); + const TargetRegisterClass *DefRC = nullptr; + if (Register::isPhysicalRegister(DestReg)) + DefRC = TRI.getRegClass(DestReg); + else + DefRC = getRegClassForTypeOnBank(DestReg, MRI); + I.setDesc(TII.get(TargetOpcode::PHI)); + return RBI.constrainGenericRegister(DestReg, *DefRC, MRI); + } + case G_STORE: + case G_LOAD: + case G_ZEXTLOAD: + case G_SEXTLOAD: { + auto MMO = *I.memoperands_begin(); + MachineOperand BaseAddr = I.getOperand(1); + int64_t SignedOffset = 0; + MachineInstr *Addr = MRI.getVRegDef(I.getOperand(1).getReg()); + if (Addr->getOpcode() == G_PTR_ADD) { + MachineInstr *Offset = MRI.getVRegDef(Addr->getOperand(2).getReg()); + if (Offset->getOpcode() == G_CONSTANT) { + APInt OffsetValue = Offset->getOperand(1).getCImm()->getValue(); + if (OffsetValue.isSignedIntN(16)) { + BaseAddr = Addr->getOperand(1); + SignedOffset = OffsetValue.getSExtValue(); + } + } + } + if (MMO->getAlign() < MMO->getSize() && + !STI.systemSupportsUnalignedAccess()) { + if (MMO->getSize() != 4 || !isRegInGprb(I.getOperand(0).getReg(), MRI)) + return false; + if (I.getOpcode() == G_STORE) { + if (!buildUnalignedStore(I, Mips::SWL, BaseAddr, SignedOffset + 3, MMO)) + return false; + if (!buildUnalignedStore(I, Mips::SWR, BaseAddr, SignedOffset, MMO)) + return false; + I.eraseFromParent(); + return true; + } + if (I.getOpcode() == G_LOAD) { + Register ImplDef = MRI.createVirtualRegister(&Mips::GPR32RegClass); + BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::IMPLICIT_DEF)).addDef(ImplDef); + Register Tmp = MRI.createVirtualRegister(&Mips::GPR32RegClass); + if (!buildUnalignedLoad(I, Mips::LWL, Tmp, BaseAddr, SignedOffset + 3,ImplDef, MMO)) + return false; + if (!buildUnalignedLoad(I, Mips::LWR, I.getOperand(0).getReg(), BaseAddr, SignedOffset, Tmp, MMO)) + return false; + I.eraseFromParent(); + return true; + } + return false; + } + const unsigned NewOpc = selectLoadStoreOpCode(I, MRI); + if (NewOpc == I.getOpcode()) + return false; + MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(NewOpc)).add(I.getOperand(0)).add(BaseAddr).addImm(SignedOffset).addMemOperand(MMO); + break; + } + case G_UDIV: + case G_UREM: + case G_SDIV: + case G_SREM: { + Register HILOReg = MRI.createVirtualRegister(&Mips::ACC64RegClass); + bool IsSigned = I.getOpcode() == G_SREM || I.getOpcode() == G_SDIV; + bool IsDiv = I.getOpcode() == G_UDIV || I.getOpcode() == G_SDIV; + MachineInstr *PseudoDIV, *PseudoMove; + PseudoDIV = BuildMI(MBB, I, I.getDebugLoc(), TII.get(IsSigned ? Mips::PseudoSDIV : Mips::PseudoUDIV)).addDef(HILOReg).add(I.getOperand(1)).add(I.getOperand(2)); + if (!constrainSelectedInstRegOperands(*PseudoDIV, TII, TRI, RBI)) + return false; + PseudoMove = BuildMI(MBB, I, I.getDebugLoc(), TII.get(IsDiv ? Mips::PseudoMFLO : Mips::PseudoMFHI)).addDef(I.getOperand(0).getReg()).addUse(HILOReg); + if (!constrainSelectedInstRegOperands(*PseudoMove, TII, TRI, RBI)) + return false; + I.eraseFromParent(); + return true; + } + case G_SELECT: { + MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MOVN_I_I)).add(I.getOperand(0)).add(I.getOperand(2)).add(I.getOperand(1)).add(I.getOperand(3)); + break; + } + case G_UNMERGE_VALUES: { + if (I.getNumOperands() != 3) + return false; + Register Src = I.getOperand(2).getReg(); + Register Lo = I.getOperand(0).getReg(); + Register Hi = I.getOperand(1).getReg(); + if (!isRegInFprb(Src, MRI) || !(isRegInGprb(Lo, MRI) && isRegInGprb(Hi, MRI))) + return false; + unsigned Opcode = STI.isFP64bit() ? Mips::ExtractElementF64_64 : Mips::ExtractElementF64; + MachineInstr *ExtractLo = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Opcode)).addDef(Lo).addUse(Src).addImm(0); + if (!constrainSelectedInstRegOperands(*ExtractLo, TII, TRI, RBI)) + return false; + MachineInstr *ExtractHi = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Opcode)).addDef(Hi).addUse(Src).addImm(1); + if (!constrainSelectedInstRegOperands(*ExtractHi, TII, TRI, RBI)) + return false; + I.eraseFromParent(); + return true; + } + case G_IMPLICIT_DEF: { + Register Dst = I.getOperand(0).getReg(); + MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::IMPLICIT_DEF)).addDef(Dst); + MRI.setRegClass(Dst, getRegClassForTypeOnBank(Dst, MRI)); + break; + } + case G_CONSTANT: { + MachineIRBuilder B(I); + if (!materialize32BitImm(I.getOperand(0).getReg(), I.getOperand(1).getCImm()->getValue(), B)) + return false; + I.eraseFromParent(); + return true; + } + case G_FCONSTANT: { + const APFloat &FPimm = I.getOperand(1).getFPImm()->getValueAPF(); + APInt APImm = FPimm.bitcastToAPInt(); + unsigned Size = MRI.getType(I.getOperand(0).getReg()).getSizeInBits(); + if (Size == 32) { + Register GPRReg = MRI.createVirtualRegister(&Mips::GPR32RegClass); + MachineIRBuilder B(I); + if (!materialize32BitImm(GPRReg, APImm, B)) + return false; + MachineInstrBuilder MTC1 = B.buildInstr(Mips::MTC1, {I.getOperand(0).getReg()}, {GPRReg}); + if (!MTC1.constrainAllUses(TII, TRI, RBI)) + return false; + } + if (Size == 64) { + Register GPRRegHigh = MRI.createVirtualRegister(&Mips::GPR32RegClass); + Register GPRRegLow = MRI.createVirtualRegister(&Mips::GPR32RegClass); + MachineIRBuilder B(I); + if (!materialize32BitImm(GPRRegHigh, APImm.getHiBits(32).trunc(32), B)) + return false; + if (!materialize32BitImm(GPRRegLow, APImm.getLoBits(32).trunc(32), B)) + return false; + MachineInstrBuilder PairF64 = B.buildInstr(STI.isFP64bit() ? Mips::BuildPairF64_64 : Mips::BuildPairF64, {I.getOperand(0).getReg()}, {GPRRegLow, GPRRegHigh}); + if (!PairF64.constrainAllUses(TII, TRI, RBI)) + return false; + } + I.eraseFromParent(); + return true; + } + case G_FABS: { + unsigned Size = MRI.getType(I.getOperand(0).getReg()).getSizeInBits(); + unsigned FABSOpcode = Size == 32 ? Mips::FABS_S : STI.isFP64bit() ? Mips::FABS_D64 : Mips::FABS_D32; + MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(FABSOpcode)).add(I.getOperand(0)).add(I.getOperand(1)); + break; + } + case G_FPTOSI: { + unsigned FromSize = MRI.getType(I.getOperand(1).getReg()).getSizeInBits(); + unsigned ToSize = MRI.getType(I.getOperand(0).getReg()).getSizeInBits(); + (void)ToSize; + assert((ToSize == 32) && "Unsupported integer size for G_FPTOSI"); + assert((FromSize == 32 || FromSize == 64) && "Unsupported floating point size for G_FPTOSI"); + unsigned Opcode; + if (FromSize == 32) + Opcode = Mips::TRUNC_W_S; + else + Opcode = STI.isFP64bit() ? Mips::TRUNC_W_D64 : Mips::TRUNC_W_D32; + Register ResultInFPR = MRI.createVirtualRegister(&Mips::FGR32RegClass); + MachineInstr *Trunc = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Opcode)).addDef(ResultInFPR).addUse(I.getOperand(1).getReg()); + if (!constrainSelectedInstRegOperands(*Trunc, TII, TRI, RBI)) + return false; + MachineInstr *Move = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MFC1)).addDef(I.getOperand(0).getReg()).addUse(ResultInFPR); + if (!constrainSelectedInstRegOperands(*Move, TII, TRI, RBI)) + return false; + I.eraseFromParent(); + return true; + } + case G_GLOBAL_VALUE: { + const llvm::GlobalValue *GVal = I.getOperand(1).getGlobal(); + if (MF.getTarget().isPositionIndependent()) { + MachineInstr *LWGOT = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW)).addDef(I.getOperand(0).getReg()).addReg(MF.getInfo()->getGlobalBaseRegForGlobalISel(MF)).addGlobalAddress(GVal); + if (I.getOperand(1).getTargetFlags() == MipsII::MO_GOT_CALL) + LWGOT->getOperand(2).setTargetFlags(MipsII::MO_GOT_CALL); + else + LWGOT->getOperand(2).setTargetFlags(MipsII::MO_GOT); + LWGOT->addMemOperand(MF, MF.getMachineMemOperand(MachinePointerInfo::getGOT(MF), MachineMemOperand::MOLoad, 4, Align(4))); + if (!constrainSelectedInstRegOperands(*LWGOT, TII, TRI, RBI)) + return false; + if (GVal->hasLocalLinkage()) { + Register LWGOTDef = MRI.createVirtualRegister(&Mips::GPR32RegClass); + LWGOT->getOperand(0).setReg(LWGOTDef); + MachineInstr *ADDiu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu)).addDef(I.getOperand(0).getReg()).addReg(LWGOTDef).addGlobalAddress(GVal); + ADDiu->getOperand(2).setTargetFlags(MipsII::MO_ABS_LO); + if (!constrainSelectedInstRegOperands(*ADDiu, TII, TRI, RBI)) + return false; + } + } + else { + Register LUiReg = MRI.createVirtualRegister(&Mips::GPR32RegClass); + MachineInstr *LUi = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LUi)).addDef(LUiReg).addGlobalAddress(GVal); + LUi->getOperand(1).setTargetFlags(MipsII::MO_ABS_HI); + if (!constrainSelectedInstRegOperands(*LUi, TII, TRI, RBI)) + return false; + MachineInstr *ADDiu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu)).addDef(I.getOperand(0).getReg()).addUse(LUiReg).addGlobalAddress(GVal); + ADDiu->getOperand(2).setTargetFlags(MipsII::MO_ABS_LO); + if (!constrainSelectedInstRegOperands(*ADDiu, TII, TRI, RBI)) + return false; + } + I.eraseFromParent(); + return true; + } + case G_JUMP_TABLE: { + if (MF.getTarget().isPositionIndependent()) { + MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW)).addDef(I.getOperand(0).getReg()).addReg(MF.getInfo()->getGlobalBaseRegForGlobalISel(MF)).addJumpTableIndex(I.getOperand(1).getIndex(), MipsII::MO_GOT).addMemOperand(MF.getMachineMemOperand( MachinePointerInfo::getGOT(MF), MachineMemOperand::MOLoad, 4, Align(4))); + } + else { + MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LUi)).addDef(I.getOperand(0).getReg()).addJumpTableIndex(I.getOperand(1).getIndex(), MipsII::MO_ABS_HI); + } + break; + } + case G_ICMP: { + struct Instr { + unsigned Opcode; + Register Def, LHS, RHS; + Instr(unsigned Opcode, Register Def, Register LHS, Register RHS) : Opcode(Opcode), Def(Def), LHS(LHS), RHS(RHS){}; + bool hasImm() const { + if (Opcode == Mips::SLTiu || Opcode == Mips::XORi) + return true; + return false; + } + }; + SmallVector Instructions; + Register ICMPReg = I.getOperand(0).getReg(); + Register Temp = MRI.createVirtualRegister(&Mips::GPR32RegClass); + Register LHS = I.getOperand(2).getReg(); + Register RHS = I.getOperand(3).getReg(); + CmpInst::Predicate Cond = static_cast(I.getOperand(1).getPredicate()); + switch (Cond) { + case CmpInst::ICMP_EQ: + Instructions.emplace_back(Mips::XOR, Temp, LHS, RHS); + Instructions.emplace_back(Mips::SLTiu, ICMPReg, Temp, 1); + break; + case CmpInst::ICMP_NE: + Instructions.emplace_back(Mips::XOR, Temp, LHS, RHS); + Instructions.emplace_back(Mips::SLTu, ICMPReg, Mips::ZERO, Temp); + break; + case CmpInst::ICMP_UGT: + Instructions.emplace_back(Mips::SLTu, ICMPReg, RHS, LHS); + break; + case CmpInst::ICMP_UGE: + Instructions.emplace_back(Mips::SLTu, Temp, LHS, RHS); + Instructions.emplace_back(Mips::XORi, ICMPReg, Temp, 1); + break; + case CmpInst::ICMP_ULT: + Instructions.emplace_back(Mips::SLTu, ICMPReg, LHS, RHS); + break; + case CmpInst::ICMP_ULE: + Instructions.emplace_back(Mips::SLTu, Temp, RHS, LHS); + Instructions.emplace_back(Mips::XORi, ICMPReg, Temp, 1); + break; + case CmpInst::ICMP_SGT: + Instructions.emplace_back(Mips::SLT, ICMPReg, RHS, LHS); + break; + case CmpInst::ICMP_SGE: + Instructions.emplace_back(Mips::SLT, Temp, LHS, RHS); + Instructions.emplace_back(Mips::XORi, ICMPReg, Temp, 1); + break; + case CmpInst::ICMP_SLT: + Instructions.emplace_back(Mips::SLT, ICMPReg, LHS, RHS); + break; + case CmpInst::ICMP_SLE: + Instructions.emplace_back(Mips::SLT, Temp, RHS, LHS); + Instructions.emplace_back(Mips::XORi, ICMPReg, Temp, 1); + break; + default: + return false; + } + MachineIRBuilder B(I); + for (const struct Instr &Instruction : Instructions) { + MachineInstrBuilder MIB = B.buildInstr(Instruction.Opcode, {Instruction.Def}, {Instruction.LHS}); + if (Instruction.hasImm()) + MIB.addImm(Instruction.RHS); + else + MIB.addUse(Instruction.RHS); + if (!MIB.constrainAllUses(TII, TRI, RBI)) + return false; + } + I.eraseFromParent(); + return true; + } + case G_FCMP: { + unsigned MipsFCMPCondCode; + bool isLogicallyNegated; + switch (CmpInst::Predicate Cond = static_cast( I.getOperand(1).getPredicate())) { + case CmpInst::FCMP_UNO: + case CmpInst::FCMP_ORD: + MipsFCMPCondCode = Mips::FCOND_UN; + isLogicallyNegated = Cond != CmpInst::FCMP_UNO; + break; + case CmpInst::FCMP_OEQ: + case CmpInst::FCMP_UNE: + MipsFCMPCondCode = Mips::FCOND_OEQ; + isLogicallyNegated = Cond != CmpInst::FCMP_OEQ; + break; + case CmpInst::FCMP_UEQ: + case CmpInst::FCMP_ONE: + MipsFCMPCondCode = Mips::FCOND_UEQ; + isLogicallyNegated = Cond != CmpInst::FCMP_UEQ; + break; + case CmpInst::FCMP_OLT: + case CmpInst::FCMP_UGE: + MipsFCMPCondCode = Mips::FCOND_OLT; + isLogicallyNegated = Cond != CmpInst::FCMP_OLT; + break; + case CmpInst::FCMP_ULT: + case CmpInst::FCMP_OGE: + MipsFCMPCondCode = Mips::FCOND_ULT; + isLogicallyNegated = Cond != CmpInst::FCMP_ULT; + break; + case CmpInst::FCMP_OLE: + case CmpInst::FCMP_UGT: + MipsFCMPCondCode = Mips::FCOND_OLE; + isLogicallyNegated = Cond != CmpInst::FCMP_OLE; + break; + case CmpInst::FCMP_ULE: + case CmpInst::FCMP_OGT: + MipsFCMPCondCode = Mips::FCOND_ULE; + isLogicallyNegated = Cond != CmpInst::FCMP_ULE; + break; + default: + return false; + } + unsigned MoveOpcode = isLogicallyNegated ? Mips::MOVT_I : Mips::MOVF_I; + Register TrueInReg = MRI.createVirtualRegister(&Mips::GPR32RegClass); + BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu)).addDef(TrueInReg).addUse(Mips::ZERO).addImm(1); + unsigned Size = MRI.getType(I.getOperand(2).getReg()).getSizeInBits(); + unsigned FCMPOpcode = Size == 32 ? Mips::FCMP_S32 : STI.isFP64bit() ? Mips::FCMP_D64 : Mips::FCMP_D32; + MachineInstr *FCMP = BuildMI(MBB, I, I.getDebugLoc(), TII.get(FCMPOpcode)).addUse(I.getOperand(2).getReg()).addUse(I.getOperand(3).getReg()).addImm(MipsFCMPCondCode); + if (!constrainSelectedInstRegOperands(*FCMP, TII, TRI, RBI)) + return false; + MachineInstr *Move = BuildMI(MBB, I, I.getDebugLoc(), TII.get(MoveOpcode)).addDef(I.getOperand(0).getReg()).addUse(Mips::ZERO).addUse(Mips::FCC0).addUse(TrueInReg); + if (!constrainSelectedInstRegOperands(*Move, TII, TRI, RBI)) + return false; + I.eraseFromParent(); + return true; + } + case G_FENCE: { + MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::SYNC)).addImm(0); + break; + } + case G_VASTART: { + MipsFunctionInfo *FuncInfo = MF.getInfo(); + int FI = FuncInfo->getVarArgsFrameIndex(); + Register LeaReg = MRI.createVirtualRegister(&Mips::GPR32RegClass); + MachineInstr *LEA_ADDiu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LEA_ADDiu)).addDef(LeaReg).addFrameIndex(FI).addImm(0); + if (!constrainSelectedInstRegOperands(*LEA_ADDiu, TII, TRI, RBI)) + return false; + MachineInstr *Store = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::SW)).addUse(LeaReg).addUse(I.getOperand(0).getReg()).addImm(0); + if (!constrainSelectedInstRegOperands(*Store, TII, TRI, RBI)) + return false; + I.eraseFromParent(); + return true; + } + default: + return false; + } + I.eraseFromParent(); + return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/LegalizeInfo/LegalizerInfo.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/LegalizeInfo/LegalizerInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..69fc5775fe04877af2fc98196e855a0a7b386a11 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/LegalizeInfo/LegalizerInfo.cpp @@ -0,0 +1,62 @@ +MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) { + using namespace TargetOpcode; + const LLT s1 = LLT::scalar(1); + const LLT s32 = LLT::scalar(32); + const LLT s64 = LLT::scalar(64); + const LLT v16s8 = LLT::vector(16, 8); + const LLT v8s16 = LLT::vector(8, 16); + const LLT v4s32 = LLT::vector(4, 32); + const LLT v2s64 = LLT::vector(2, 64); + const LLT p0 = LLT::pointer(0, 32); + getActionDefinitionsBuilder({G_ADD, G_SUB, G_MUL}).legalIf([=, &ST](const LegalityQuery &Query) { if (CheckTyN(0, Query, {s32})) return true; if (ST.hasMSA() && CheckTyN(0, Query, {v16s8, v8s16, v4s32, v2s64})) return true; return false;}).clampScalar(0, s32, s32); + getActionDefinitionsBuilder({G_UADDO, G_UADDE, G_USUBO, G_USUBE, G_UMULO}).lowerFor({{s32, s1}}); + getActionDefinitionsBuilder(G_UMULH).legalFor({s32}).maxScalar(0, s32); + bool NoAlignRequirements = true; + unsigned Size = Query.Types[0].getSizeInBits(); unsigned QueryMemSize = Query.MMODescrs[0].SizeInBits; assert(QueryMemSize <= Size && "Scalar can't hold MemSize"); + if (Size > 64 || QueryMemSize > 64) return false; + if (!isPowerOf2_64(Query.MMODescrs[0].SizeInBits)) return true; + if (!ST.systemSupportsUnalignedAccess() && isUnalignedMemmoryAccess(QueryMemSize, Query.MMODescrs[0].AlignInBits)) { assert(QueryMemSize != 32 && "4 byte load and store are legal"); return true; } return false;}).minScalar(0, s32); + getActionDefinitionsBuilder(G_IMPLICIT_DEF).legalFor({s32, s64}); + getActionDefinitionsBuilder(G_UNMERGE_VALUES).legalFor({{s32, s64}}); + getActionDefinitionsBuilder(G_MERGE_VALUES).legalFor({{s64, s32}}); + getActionDefinitionsBuilder({G_ZEXTLOAD, G_SEXTLOAD}).legalForTypesWithMemDesc({{s32, p0, 8, 8}, {s32, p0, 16, 8}}).clampScalar(0, s32, s32); + getActionDefinitionsBuilder({G_ZEXT, G_SEXT, G_ANYEXT}).legalIf([](const LegalityQuery &Query) { return false; }).maxScalar(0, s32); + getActionDefinitionsBuilder(G_TRUNC).legalIf([](const LegalityQuery &Query) { return false; }).maxScalar(1, s32); + getActionDefinitionsBuilder(G_SELECT).legalForCartesianProduct({p0, s32, s64}, {s32}).minScalar(0, s32).minScalar(1, s32); + getActionDefinitionsBuilder(G_BRCOND).legalFor({s32}).minScalar(0, s32); + getActionDefinitionsBuilder(G_BRJT).legalFor({{p0, s32}}); + getActionDefinitionsBuilder(G_BRINDIRECT).legalFor({p0}); + getActionDefinitionsBuilder(G_PHI).legalFor({p0, s32, s64}).minScalar(0, s32); + getActionDefinitionsBuilder({G_AND, G_OR, G_XOR}).legalFor({s32}).clampScalar(0, s32, s32); + getActionDefinitionsBuilder({G_SDIV, G_SREM, G_UDIV, G_UREM}).legalIf([=, &ST](const LegalityQuery &Query) { if (CheckTyN(0, Query, {s32})) return true; if (ST.hasMSA() && CheckTyN(0, Query, {v16s8, v8s16, v4s32, v2s64})) return true; return false;}).minScalar(0, s32).libcallFor({s64}); + getActionDefinitionsBuilder({G_SHL, G_ASHR, G_LSHR}).legalFor({{s32, s32}}).clampScalar(1, s32, s32).clampScalar(0, s32, s32); + getActionDefinitionsBuilder(G_ICMP).legalForCartesianProduct({s32}, {s32, p0}).clampScalar(1, s32, s32).minScalar(0, s32); + getActionDefinitionsBuilder(G_CONSTANT).legalFor({s32}).clampScalar(0, s32, s32); + getActionDefinitionsBuilder({G_PTR_ADD, G_INTTOPTR}).legalFor({{p0, s32}}); + getActionDefinitionsBuilder(G_PTRTOINT).legalFor({{s32, p0}}); + getActionDefinitionsBuilder(G_FRAME_INDEX).legalFor({p0}); + getActionDefinitionsBuilder({G_GLOBAL_VALUE, G_JUMP_TABLE}).legalFor({p0}); + getActionDefinitionsBuilder(G_DYN_STACKALLOC).lowerFor({{p0, s32}}); + getActionDefinitionsBuilder(G_VASTART).legalFor({p0}); + getActionDefinitionsBuilder(G_BSWAP).legalIf([=, &ST](const LegalityQuery &Query) { if (ST.hasMips32r2() && CheckTyN(0, Query, {s32})) return true; return false;}).lowerIf([=, &ST](const LegalityQuery &Query) { if (!ST.hasMips32r2() && CheckTyN(0, Query, {s32})) return true; return false;}).maxScalar(0, s32); + getActionDefinitionsBuilder(G_BITREVERSE).lowerFor({s32}).maxScalar(0, s32); + getActionDefinitionsBuilder(G_CTLZ).legalFor({{s32, s32}}).maxScalar(0, s32).maxScalar(1, s32); + getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF).lowerFor({{s32, s32}}); + getActionDefinitionsBuilder(G_CTTZ).lowerFor({{s32, s32}}).maxScalar(0, s32).maxScalar(1, s32); + getActionDefinitionsBuilder(G_CTTZ_ZERO_UNDEF).lowerFor({{s32, s32}, {s64, s64}}); + getActionDefinitionsBuilder(G_CTPOP).lowerFor({{s32, s32}}).clampScalar(0, s32, s32).clampScalar(1, s32, s32) + getActionDefinitionsBuilder(G_FCONSTANT).legalFor({s32, s64}); + getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FABS, G_FSQRT}).legalIf([=, &ST](const LegalityQuery &Query) { if (CheckTyN(0, Query, {s32, s64})) return true; if (ST.hasMSA() && CheckTyN(0, Query, {v16s8, v8s16, v4s32, v2s64})) return true; return false;}); + getActionDefinitionsBuilder(G_FCMP).legalFor({{s32, s32}, {s32, s64}}).minScalar(0, s32); + getActionDefinitionsBuilder({G_FCEIL, G_FFLOOR}).libcallFor({s32, s64}); + getActionDefinitionsBuilder(G_FPEXT).legalFor({{s64, s32}}); + getActionDefinitionsBuilder(G_FPTRUNC).legalFor({{s32, s64}}); + getActionDefinitionsBuilder(G_FPTOSI).legalForCartesianProduct({s32}, {s64, s32}).libcallForCartesianProduct({s64}, {s64, s32}).minScalar(0, s32); + getActionDefinitionsBuilder(G_FPTOUI).libcallForCartesianProduct({s64}, {s64, s32}).lowerForCartesianProduct({s32}, {s64, s32}).minScalar(0, s32); + getActionDefinitionsBuilder(G_SITOFP).legalForCartesianProduct({s64, s32}, {s32}).libcallForCartesianProduct({s64, s32}, {s64}).minScalar(1, s32); + getActionDefinitionsBuilder(G_UITOFP).libcallForCartesianProduct({s64, s32}, {s64}).customForCartesianProduct({s64, s32}, {s32}).minScalar(1, s32); + getActionDefinitionsBuilder(G_SEXT_INREG).lower(); + getActionDefinitionsBuilder({G_MEMCPY, G_MEMMOVE, G_MEMSET}).libcall(); + computeTables(); + verify(*ST.getInstrInfo()); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/MCInstLower/lowerMachineInstrToMCInst.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/MCInstLower/lowerMachineInstrToMCInst.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/MCInstLower/lowerMachineInstrToMCInst.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/MCInstLower/lowerMachineOperandToMCOperand.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/MCInstLower/lowerMachineOperandToMCOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/MCInstLower/lowerMachineOperandToMCOperand.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/MCInstLower/lowerSymbolOperand.cpp b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/MCInstLower/lowerSymbolOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..815432f210488b2944aa43d51c6807b23840236b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/RISCV/Selection/MCInstLower/lowerSymbolOperand.cpp @@ -0,0 +1,124 @@ +MCOperand MipsMCInstLower::LowerSymbolOperand(const MachineOperand &MO, MachineOperandType MOTy, int64_t Offset) const { + MCSymbolRefExpr::VariantKind Kind = MCSymbolRefExpr::VK_None; + MipsMCExpr::MipsExprKind TargetKind = MipsMCExpr::MEK_None; + bool IsGpOff = false; + const MCSymbol *Symbol; + switch(MO.getTargetFlags()) { + default: + llvm_unreachable("Invalid target flag!"); + case MipsII::MO_NO_FLAG: + break; + case MipsII::MO_GPREL: + TargetKind = MipsMCExpr::MEK_GPREL; + break; + case MipsII::MO_GOT_CALL: + TargetKind = MipsMCExpr::MEK_GOT_CALL; + break; + case MipsII::MO_GOT: + TargetKind = MipsMCExpr::MEK_GOT; + break; + case MipsII::MO_ABS_HI: + TargetKind = MipsMCExpr::MEK_HI; + break; + case MipsII::MO_ABS_LO: + TargetKind = MipsMCExpr::MEK_LO; + break; + case MipsII::MO_TLSGD: + TargetKind = MipsMCExpr::MEK_TLSGD; + break; + case MipsII::MO_TLSLDM: + TargetKind = MipsMCExpr::MEK_TLSLDM; + break; + case MipsII::MO_DTPREL_HI: + TargetKind = MipsMCExpr::MEK_DTPREL_HI; + break; + case MipsII::MO_DTPREL_LO: + TargetKind = MipsMCExpr::MEK_DTPREL_LO; + break; + case MipsII::MO_GOTTPREL: + TargetKind = MipsMCExpr::MEK_GOTTPREL; + break; + case MipsII::MO_TPREL_HI: + TargetKind = MipsMCExpr::MEK_TPREL_HI; + break; + case MipsII::MO_TPREL_LO: + TargetKind = MipsMCExpr::MEK_TPREL_LO; + break; + case MipsII::MO_GPOFF_HI: + TargetKind = MipsMCExpr::MEK_HI; + IsGpOff = true; + break; + case MipsII::MO_GPOFF_LO: + TargetKind = MipsMCExpr::MEK_LO; + IsGpOff = true; + break; + case MipsII::MO_GOT_DISP: + TargetKind = MipsMCExpr::MEK_GOT_DISP; + break; + case MipsII::MO_GOT_HI16: + TargetKind = MipsMCExpr::MEK_GOT_HI16; + break; + case MipsII::MO_GOT_LO16: + TargetKind = MipsMCExpr::MEK_GOT_LO16; + break; + case MipsII::MO_GOT_PAGE: + TargetKind = MipsMCExpr::MEK_GOT_PAGE; + break; + case MipsII::MO_GOT_OFST: + TargetKind = MipsMCExpr::MEK_GOT_OFST; + break; + case MipsII::MO_HIGHER: + TargetKind = MipsMCExpr::MEK_HIGHER; + break; + case MipsII::MO_HIGHEST: + TargetKind = MipsMCExpr::MEK_HIGHEST; + break; + case MipsII::MO_CALL_HI16: + TargetKind = MipsMCExpr::MEK_CALL_HI16; + break; + case MipsII::MO_CALL_LO16: + TargetKind = MipsMCExpr::MEK_CALL_LO16; + break; + case MipsII::MO_JALR: + return MCOperand(); + } + switch (MOTy) { + case MachineOperand::MO_MachineBasicBlock: + Symbol = MO.getMBB()->getSymbol(); + break; + case MachineOperand::MO_GlobalAddress: + Symbol = AsmPrinter.getSymbol(MO.getGlobal()); + Offset += MO.getOffset(); + break; + case MachineOperand::MO_BlockAddress: + Symbol = AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress()); + Offset += MO.getOffset(); + break; + case MachineOperand::MO_ExternalSymbol: + Symbol = AsmPrinter.GetExternalSymbolSymbol(MO.getSymbolName()); + Offset += MO.getOffset(); + break; + case MachineOperand::MO_MCSymbol: + Symbol = MO.getMCSymbol(); + Offset += MO.getOffset(); + break; + case MachineOperand::MO_JumpTableIndex: + Symbol = AsmPrinter.GetJTISymbol(MO.getIndex()); + break; + case MachineOperand::MO_ConstantPoolIndex: + Symbol = AsmPrinter.GetCPISymbol(MO.getIndex()); + Offset += MO.getOffset(); + break; + default: + llvm_unreachable(""); + } + const MCExpr *Expr = MCSymbolRefExpr::create(Symbol, Kind, *Ctx); + if (Offset) { + Expr = MCBinaryExpr::createAdd(Expr, MCConstantExpr::create(Offset, *Ctx), *Ctx); + } + if (IsGpOff) + Expr = MipsMCExpr::createGpOff(TargetKind, Expr, *Ctx); + else if (TargetKind != MipsMCExpr::MEK_None) + Expr = MipsMCExpr::create(TargetKind, Expr, *Ctx); + return MCOperand::createExpr(Expr); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Allocation/RegisterInfo/RegisterInfo.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Allocation/RegisterInfo/RegisterInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9e6f816b7f0ea865a533d9408fcc407f4cc146f4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Allocation/RegisterInfo/RegisterInfo.cpp @@ -0,0 +1,2 @@ +MipsRegisterInfo::MipsRegisterInfo() : MipsGenRegisterInfo(Mips::RA) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Allocation/RegisterInfo/eliminateCallFramePseudoInstr.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Allocation/RegisterInfo/eliminateCallFramePseudoInstr.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3682cdd04c55d0c6cf22e141dde4992154773492 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Allocation/RegisterInfo/eliminateCallFramePseudoInstr.cpp @@ -0,0 +1,10 @@ +MachineBasicBlock::iterator MipsFrameLowering::eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const { + unsigned SP = STI.getABI().IsN64() ? Mips::SP_64 : Mips::SP; + if (!hasReservedCallFrame(MF)) { + int64_t Amount = I->getOperand(0).getImm(); + if (I->getOpcode() == Mips::ADJCALLSTACKDOWN) + Amount = -Amount; + STI.getInstrInfo()->adjustStackPtr(SP, Amount, MBB, I); + } + return MBB.erase(I); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Allocation/RegisterInfo/eliminateFrameIndex.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Allocation/RegisterInfo/eliminateFrameIndex.cpp new file mode 100644 index 0000000000000000000000000000000000000000..80dcd82832876ef68c5dac162843caf8d669a919 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Allocation/RegisterInfo/eliminateFrameIndex.cpp @@ -0,0 +1,10 @@ +void MipsRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const { + MachineInstr &MI = *II; + MachineFunction &MF = *MI.getParent()->getParent(); + LLVM_DEBUG(errs() << "\nFunction : " << MF.getName() << "\n"; errs() << "<--------->\n" << MI); + int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); + uint64_t stackSize = MF.getFrameInfo().getStackSize(); + int64_t spOffset = MF.getFrameInfo().getObjectOffset(FrameIndex); + LLVM_DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n" << "spOffset : " << spOffset << "\n" << "stackSize : " << stackSize << "\n" << "alignment : " << DebugStr(MF.getFrameInfo().getObjectAlign(FrameIndex)) << "\n"); + eliminateFI(MI, FIOperandNum, FrameIndex, stackSize, spOffset); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Allocation/RegisterInfo/getArgRegs.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Allocation/RegisterInfo/getArgRegs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Allocation/RegisterInfo/getArgRegs.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Allocation/RegisterInfo/getCalleeSavedRegs.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Allocation/RegisterInfo/getCalleeSavedRegs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ee86b1ec364747b2b7adec2f4c7503435563ae61 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Allocation/RegisterInfo/getCalleeSavedRegs.cpp @@ -0,0 +1,21 @@ +const MCPhysReg *MipsRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { + const MipsSubtarget &Subtarget = MF->getSubtarget(); + const Function &F = MF->getFunction(); + if (F.hasFnAttribute("interrupt")) { + if (Subtarget.hasMips64()) + return Subtarget.hasMips64r6() ? CSR_Interrupt_64R6_SaveList : CSR_Interrupt_64_SaveList; + else + return Subtarget.hasMips32r6() ? CSR_Interrupt_32R6_SaveList : CSR_Interrupt_32_SaveList; + } + if (Subtarget.isSingleFloat()) + return CSR_SingleFloatOnly_SaveList; + if (Subtarget.isABI_N64()) + return CSR_N64_SaveList; + if (Subtarget.isABI_N32()) + return CSR_N32_SaveList; + if (Subtarget.isFP64bit()) + return CSR_O32_FP64_SaveList; + if (Subtarget.isFPXX()) + return CSR_O32_FPXX_SaveList; + return CSR_O32_SaveList; +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Allocation/RegisterInfo/getFrameRegister.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Allocation/RegisterInfo/getFrameRegister.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b5f8f103812c92122b87cb59e13c69048c13c8d7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Allocation/RegisterInfo/getFrameRegister.cpp @@ -0,0 +1,9 @@ +Register MipsRegisterInfo::getFrameRegister(const MachineFunction &MF) const { + const MipsSubtarget &Subtarget = MF.getSubtarget(); + const TargetFrameLowering *TFI = Subtarget.getFrameLowering(); + bool IsN64 = static_cast(MF.getTarget()).getABI().IsN64(); + if (Subtarget.inMips16Mode()) + return TFI->hasFP(MF) ? Mips::S0 : Mips::SP; + else + return TFI->hasFP(MF) ? (IsN64 ? Mips::FP_64 : Mips::FP) : (IsN64 ? Mips::SP_64 : Mips::SP); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Allocation/RegisterInfo/getNumArgRegs.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Allocation/RegisterInfo/getNumArgRegs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Allocation/RegisterInfo/getNumArgRegs.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Allocation/RegisterInfo/getReservedRegs.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Allocation/RegisterInfo/getReservedRegs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e54fad41cb6792bb287045716ad70601b8ede981 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Allocation/RegisterInfo/getReservedRegs.cpp @@ -0,0 +1,65 @@ +BitVector MipsRegisterInfo::getReservedRegs(const MachineFunction &MF) const { + static const MCPhysReg ReservedGPR32[] = { + Mips::ZERO, Mips::K0, Mips::K1, Mips::SP + }; + static const MCPhysReg ReservedGPR64[] = { + Mips::ZERO_64, Mips::K0_64, Mips::K1_64, Mips::SP_64 + }; + BitVector Reserved(getNumRegs()); + const MipsSubtarget &Subtarget = MF.getSubtarget(); + for (unsigned I = 0; I < array_lengthof(ReservedGPR32); ++I) + Reserved.set(ReservedGPR32[I]); + if (Subtarget.isTargetNaCl()) { + Reserved.set(Mips::T6); + Reserved.set(Mips::T7); + Reserved.set(Mips::T8); + } + for (unsigned I = 0; I < array_lengthof(ReservedGPR64); ++I) + Reserved.set(ReservedGPR64[I]); + if (!Subtarget.isABICalls()) { + Reserved.set(Mips::GP); + Reserved.set(Mips::GP_64); + } + if (Subtarget.isFP64bit()) { + for (MCPhysReg Reg : Mips::AFGR64RegClass) + Reserved.set(Reg); + } + else { + for (MCPhysReg Reg : Mips::FGR64RegClass) + Reserved.set(Reg); + } + if (Subtarget.getFrameLowering()->hasFP(MF)) { + if (Subtarget.inMips16Mode()) + Reserved.set(Mips::S0); + else { + Reserved.set(Mips::FP); + Reserved.set(Mips::FP_64); + if (needsStackRealignment(MF) && MF.getFrameInfo().hasVarSizedObjects()) { + Reserved.set(Mips::S7); + Reserved.set(Mips::S7_64); + } + } + } + Reserved.set(Mips::HWR29); + Reserved.set(Mips::DSPPos); + Reserved.set(Mips::DSPSCount); + Reserved.set(Mips::DSPCarry); + Reserved.set(Mips::DSPEFI); + Reserved.set(Mips::DSPOutFlag); + for (MCPhysReg Reg : Mips::MSACtrlRegClass) + Reserved.set(Reg); + if (Subtarget.inMips16Mode()) { + const MipsFunctionInfo *MipsFI = MF.getInfo(); + Reserved.set(Mips::RA); + Reserved.set(Mips::RA_64); + Reserved.set(Mips::T0); + Reserved.set(Mips::T1); + if (MF.getFunction().hasFnAttribute("saveS2") || MipsFI->hasSaveS2()) + Reserved.set(Mips::S2); + } + if (Subtarget.useSmallSection()) { + Reserved.set(Mips::GP); + Reserved.set(Mips::GP_64); + } + return Reserved; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Allocation/RegisterInfo/needsFrameMoves.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Allocation/RegisterInfo/needsFrameMoves.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Allocation/RegisterInfo/needsFrameMoves.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Allocation/RegisterInfo/processFunctionBeforeFrameFinalized.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Allocation/RegisterInfo/processFunctionBeforeFrameFinalized.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Allocation/RegisterInfo/processFunctionBeforeFrameFinalized.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Allocation/RegisterInfo/requiresRegisterScavenging.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Allocation/RegisterInfo/requiresRegisterScavenging.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2682c40f6351c32f0b694fd849308d114c3a623b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Allocation/RegisterInfo/requiresRegisterScavenging.cpp @@ -0,0 +1,3 @@ +bool MipsRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const { + return true; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Allocation/RegisterInfo/useFPForScavengingIndex.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Allocation/RegisterInfo/useFPForScavengingIndex.cpp new file mode 100644 index 0000000000000000000000000000000000000000..48b5c513cc442aa7b1b64a950fe261d2459fb318 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Allocation/RegisterInfo/useFPForScavengingIndex.cpp @@ -0,0 +1,3 @@ +bool Mips16RegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const { + return false; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/AsmPrinter.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/AsmPrinter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..69363c6c07ac6569bb6adaa08ef2328e96b8a16f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/AsmPrinter.cpp @@ -0,0 +1,2 @@ +explicit MipsAsmPrinter(TargetMachine &TM, std::unique_ptr Streamer) : AsmPrinter(TM, std::move(Streamer)), MCInstLowering(*this) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/EmitBasicBlockStart.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/EmitBasicBlockStart.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/EmitBasicBlockStart.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/EmitConstantPool.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/EmitConstantPool.cpp new file mode 100644 index 0000000000000000000000000000000000000000..aa1e0e37b48002c0e5e90b0f8d9405646d81b5b7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/EmitConstantPool.cpp @@ -0,0 +1,5 @@ +void emitConstantPool() override { + bool UsingConstantPools = (Subtarget->inMips16Mode() && Subtarget->useConstantIslands()); + if (!UsingConstantPools) + AsmPrinter::emitConstantPool(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/EmitFunctionEntryLabel.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/EmitFunctionEntryLabel.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e6884cf9557c0765a3db634e2a8a29e9099f9eaa --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/EmitFunctionEntryLabel.cpp @@ -0,0 +1,18 @@ +void MipsAsmPrinter::emitFunctionEntryLabel() { + MipsTargetStreamer &TS = getTargetStreamer(); + if (Subtarget->isTargetNaCl()) + emitAlignment(std::max(MF->getAlignment(), MIPS_NACL_BUNDLE_ALIGN)); + if (Subtarget->inMicroMipsMode()) { + TS.emitDirectiveSetMicroMips(); + TS.setUsesMicroMips(); + TS.updateABIInfo(*Subtarget); + } + else + TS.emitDirectiveSetNoMicroMips(); + if (Subtarget->inMips16Mode()) + TS.emitDirectiveSetMips16(); + else + TS.emitDirectiveSetNoMips16(); + TS.emitDirectiveEnt(*CurrentFnSym); + OutStreamer->emitLabel(CurrentFnSym); +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/EmitGlobalVariable.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/EmitGlobalVariable.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/EmitGlobalVariable.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/EmitInstruction.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/EmitInstruction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..52d759a06f0cc7d92fe9b7e4c9454e2fb460d219 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/EmitInstruction.cpp @@ -0,0 +1,63 @@ +void MipsAsmPrinter::emitInstruction(const MachineInstr *MI) { + MipsTargetStreamer &TS = getTargetStreamer(); + unsigned Opc = MI->getOpcode(); + TS.forbidModuleDirective(); + if (MI->isDebugValue()) { + SmallString<128> Str; + raw_svector_ostream OS(Str); + PrintDebugValueComment(MI, OS); + return; + } + if (MI->isDebugLabel()) + return; + if (InConstantPool && Opc != Mips::CONSTPOOL_ENTRY) { + OutStreamer->emitDataRegion(MCDR_DataRegionEnd); + InConstantPool = false; + } + if (Opc == Mips::CONSTPOOL_ENTRY) { + unsigned LabelId = (unsigned)MI->getOperand(0).getImm(); + unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex(); + if (!InConstantPool) { + OutStreamer->emitDataRegion(MCDR_DataRegion); + InConstantPool = true; + } + OutStreamer->emitLabel(GetCPISymbol(LabelId)); + const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx]; + if (MCPE.isMachineConstantPoolEntry()) + emitMachineConstantPoolValue(MCPE.Val.MachineCPVal); + else + emitGlobalConstant(MF->getDataLayout(), MCPE.Val.ConstVal); + return; + } + switch (Opc) { + case Mips::PATCHABLE_FUNCTION_ENTER: + LowerPATCHABLE_FUNCTION_ENTER(*MI); + return; + case Mips::PATCHABLE_FUNCTION_EXIT: + LowerPATCHABLE_FUNCTION_EXIT(*MI); + return; + case Mips::PATCHABLE_TAIL_CALL: + LowerPATCHABLE_TAIL_CALL(*MI); + return; + } + if (EmitJalrReloc && (MI->isReturn() || MI->isCall() || MI->isIndirectBranch())) { + emitDirectiveRelocJalr(*MI, OutContext, TM, *OutStreamer, *Subtarget); + } + MachineBasicBlock::const_instr_iterator I = MI->getIterator(); + MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end(); + do { + if (emitPseudoExpansionLowering(*OutStreamer, &*I)) + continue; + if (I->isBundle()) + continue; + if (I->getOpcode() == Mips::PseudoReturn || I->getOpcode() == Mips::PseudoReturn64 || I->getOpcode() == Mips::PseudoIndirectBranch || I->getOpcode() == Mips::PseudoIndirectBranch64 || I->getOpcode() == Mips::TAILCALLREG || I->getOpcode() == Mips::TAILCALLREG64) { + emitPseudoIndirectBranch(*OutStreamer, &*I); + continue; + } + if (I->isPseudo() && !Subtarget->inMips16Mode() && !isLongBranchPseudo(I->getOpcode())) + llvm_unreachable("Pseudo opcode found in emitInstruction()"); + MCInst TmpInst0; + MCInstLowering.Lower(&*I, TmpInst0); + EmitToStreamer(*OutStreamer, TmpInst0); + } while ((++I != E) && I->isInsideBundle()); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/LLVMInitializeAsmPrinter.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/LLVMInitializeAsmPrinter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4d4ab5bf715e86e02b908fb3cab0a9fd1fecee42 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/LLVMInitializeAsmPrinter.cpp @@ -0,0 +1,6 @@ +extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMipsAsmPrinter() { + RegisterAsmPrinter X(getTheMipsTarget()); + RegisterAsmPrinter Y(getTheMipselTarget()); + RegisterAsmPrinter A(getTheMips64Target()); + RegisterAsmPrinter B(getTheMips64elTarget()); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/PrintAsmMemoryOperand.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/PrintAsmMemoryOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..13d636aa596545eb1d4a0b5e90251d6ac7d5200a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/PrintAsmMemoryOperand.cpp @@ -0,0 +1,27 @@ +bool MipsAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum, const char *ExtraCode, raw_ostream &O) { + assert(OpNum + 1 < MI->getNumOperands() && "Insufficient operands"); + const MachineOperand &BaseMO = MI->getOperand(OpNum); + const MachineOperand &OffsetMO = MI->getOperand(OpNum + 1); + assert(BaseMO.isReg() && "Unexpected base pointer for inline asm memory operand."); + assert(OffsetMO.isImm() && "Unexpected offset for inline asm memory operand."); + int Offset = OffsetMO.getImm(); + if (ExtraCode) { + switch (ExtraCode[0]) { + case 'D': + Offset += 4; + break; + case 'M': + if (Subtarget->isLittle()) + Offset += 4; + break; + case 'L': + if (!Subtarget->isLittle()) + Offset += 4; + break; + default: + return true; + } + } + O << Offset << "($" << MipsInstPrinter::getRegisterName(BaseMO.getReg()) << ")"; + return false; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/PrintAsmOperand.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/PrintAsmOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..79f3c9422c159809396fc8b54c7323732a4efe88 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/PrintAsmOperand.cpp @@ -0,0 +1,89 @@ +bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, const char *ExtraCode, raw_ostream &O) { + if (ExtraCode && ExtraCode[0]) { + if (ExtraCode[1] != 0) return true; + const MachineOperand &MO = MI->getOperand(OpNum); + switch (ExtraCode[0]) { + default: + return AsmPrinter::PrintAsmOperand(MI, OpNum, ExtraCode, O); + case 'X': + if ((MO.getType()) != MachineOperand::MO_Immediate) + return true; + O << "0x" << Twine::utohexstr(MO.getImm()); + return false; + case 'x': + if ((MO.getType()) != MachineOperand::MO_Immediate) + return true; + O << "0x" << Twine::utohexstr(MO.getImm() & 0xffff); + return false; + case 'd': + if ((MO.getType()) != MachineOperand::MO_Immediate) + return true; + O << MO.getImm(); + return false; + case 'm': + if ((MO.getType()) != MachineOperand::MO_Immediate) + return true; + O << MO.getImm() - 1; + return false; + case 'y': + if ((MO.getType()) != MachineOperand::MO_Immediate) + return true; + if (!isPowerOf2_64(MO.getImm())) + return true; + O << Log2_64(MO.getImm()); + return false; + case 'z': + if (MO.getType() == MachineOperand::MO_Immediate && MO.getImm() == 0) { + O << "$0"; + return false; + } + break; + case 'D': + case 'L': + case 'M': + { + if (OpNum == 0) + return true; + const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1); + if (!FlagsOP.isImm()) + return true; + unsigned Flags = FlagsOP.getImm(); + unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags); + if (NumVals != 2) { + if (Subtarget->isGP64bit() && NumVals == 1 && MO.isReg()) { + Register Reg = MO.getReg(); + O << '$' << MipsInstPrinter::getRegisterName(Reg); + return false; + } + return true; + } + unsigned RegOp = OpNum; + if (!Subtarget->isGP64bit()){ + switch(ExtraCode[0]) { + case 'M': + RegOp = (Subtarget->isLittle()) ? OpNum + 1 : OpNum; + break; + case 'L': + RegOp = (Subtarget->isLittle()) ? OpNum : OpNum + 1; + break; + case 'D': + RegOp = OpNum + 1; + } + if (RegOp >= MI->getNumOperands()) + return true; + const MachineOperand &MO = MI->getOperand(RegOp); + if (!MO.isReg()) + return true; + Register Reg = MO.getReg(); + O << '$' << MipsInstPrinter::getRegisterName(Reg); + return false; + } + break; + } + case 'w': + break; + } + } + printOperand(MI, OpNum, O); + return false; +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/PrintSpecial.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/PrintSpecial.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/PrintSpecial.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/emitEndOfAsmFile.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/emitEndOfAsmFile.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c7146d50f3a4b68a80abd13882286d1c3d617f2b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/emitEndOfAsmFile.cpp @@ -0,0 +1,8 @@ +void MipsAsmPrinter::emitEndOfAsmFile(Module &M) { + for (std::map::const_iterator it = StubsNeeded.begin(); it != StubsNeeded.end(); ++it) { + const char *Symbol = it->first; + const Mips16HardFloatInfo::FuncSignature *Signature = it->second; + EmitFPCallStub(Symbol, Signature); + } + OutStreamer->SwitchSection(OutContext.getObjectFileInfo()->getTextSection()); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/emitStartOfAsmFile.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/emitStartOfAsmFile.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b73c68c716fe56a617211b6f9b2ee34637267ab6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/emitStartOfAsmFile.cpp @@ -0,0 +1,25 @@ +void MipsAsmPrinter::emitStartOfAsmFile(Module &M) { + MipsTargetStreamer &TS = getTargetStreamer(); + TS.setPic(OutContext.getObjectFileInfo()->isPositionIndependent()); + const Triple &TT = TM.getTargetTriple(); + StringRef CPU = MIPS_MC::selectMipsCPU(TT, TM.getTargetCPU()); + StringRef FS = TM.getTargetFeatureString(); + const MipsTargetMachine &MTM = static_cast(TM); + const MipsSubtarget STI(TT, CPU, FS, MTM.isLittleEndian(), MTM, None); + bool IsABICalls = STI.isABICalls(); + const MipsABIInfo &ABI = MTM.getABI(); + if (IsABICalls) { + TS.emitDirectiveAbiCalls(); + if (!isPositionIndependent() && STI.hasSym32()) + TS.emitDirectiveOptionPic0(); + } + std::string SectionName = std::string(".mdebug.") + getCurrentABIString(); + OutStreamer->SwitchSection(OutContext.getELFSection(SectionName, ELF::SHT_PROGBITS, 0)); + STI.isNaN2008() ? TS.emitDirectiveNaN2008() : TS.emitDirectiveNaNLegacy(); + TS.updateABIInfo(STI); + if ((ABI.IsO32() && (STI.isABI_FPXX() || STI.isFP64bit())) || STI.useSoftFloat()) + TS.emitDirectiveModuleFP(); + if (ABI.IsO32() && (!STI.useOddSPReg() || STI.isABI_FPXX())) + TS.emitDirectiveModuleOddSPReg(); + OutStreamer->SwitchSection(getObjFileLowering().getTextSection()); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/getAnalysisUsage.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/getAnalysisUsage.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3f3e70065dbb1b3bcc423b768c1c4c1713ba4da5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/getAnalysisUsage.cpp @@ -0,0 +1,4 @@ +void getAnalysisUsage(AnalysisUsage &AU) const override { + AU.addRequired(); + MachineFunctionPass::getAnalysisUsage(AU); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/getDebugValueLocation.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/getDebugValueLocation.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/getDebugValueLocation.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/getPassName.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a02589fc541228804a95dfd11db6146447ce1fcf --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/getPassName.cpp @@ -0,0 +1,3 @@ +StringRef getPassName() const override { + return "Mips Assembly Printer"; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/printInlineJT.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/printInlineJT.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/printInlineJT.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/printInlineJT32.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/printInlineJT32.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/printInlineJT32.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/printMemOperand.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/printMemOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6a3eefbe00918670f234702344103025346cbbee --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/printMemOperand.cpp @@ -0,0 +1,14 @@ +void MipsAsmPrinter::printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O) { + switch (MI->getOpcode()) { + default: + break; + case Mips::SWM32_MM: + case Mips::LWM32_MM: + opNum = MI->getNumOperands() - 2; + break; + } + printOperand(MI, opNum+1, O); + O << "("; + printOperand(MI, opNum, O); + O << ")"; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/printOperand.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/printOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ca8f19bc8f4f6fc50ae215ec71e28772be6a4589 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/printOperand.cpp @@ -0,0 +1,13 @@ +void MipsInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) { + const MCOperand &Op = MI->getOperand(OpNo); + if (Op.isReg()) { + printRegName(O, Op.getReg()); + return; + } + if (Op.isImm()) { + O << formatImm(Op.getImm()); + return; + } + assert(Op.isExpr() && "unknown operand kind in printOperand"); + Op.getExpr()->print(O, &MAI, true); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1ea4e69b88d62186a605cf374ec7eb5204d98196 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/runOnMachineFunction.cpp @@ -0,0 +1,17 @@ +bool MipsAsmPrinter::runOnMachineFunction(MachineFunction &MF) { + Subtarget = &MF.getSubtarget(); + MipsFI = MF.getInfo(); + if (Subtarget->inMips16Mode()) + for (std::map::const_iterator it = MipsFI->StubsNeeded.begin(); it != MipsFI->StubsNeeded.end(); ++it) { + const char *Symbol = it->first; + const Mips16HardFloatInfo::FuncSignature *Signature = it->second; + if (StubsNeeded.find(Symbol) == StubsNeeded.end()) + StubsNeeded[Symbol] = Signature; + } + MCP = MF.getConstantPool(); + if (Subtarget->isTargetNaCl()) + NaClAlignIndirectJumpTargets(MF); + AsmPrinter::runOnMachineFunction(MF); + emitXRayTable(); + return true; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/~AsmPrinter.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/~AsmPrinter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Assembler/AsmPrinter/~AsmPrinter.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Emission/AsmInfo/MCAsmInfo.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Emission/AsmInfo/MCAsmInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3dbf2eaf5993d301dc8ae0720319683c2860d3d1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Emission/AsmInfo/MCAsmInfo.cpp @@ -0,0 +1,28 @@ +MipsMCAsmInfo::MipsMCAsmInfo(const Triple &TheTriple, const MCTargetOptions &Options) { + IsLittleEndian = TheTriple.isLittleEndian(); + MipsABIInfo ABI = MipsABIInfo::computeTargetABI(TheTriple, "", Options); + if (TheTriple.isMIPS64() && !ABI.IsN32()) + CodePointerSize = CalleeSaveStackSlotSize = 8; + if (ABI.IsO32()) + PrivateGlobalPrefix = "$"; + else if (ABI.IsN32() || ABI.IsN64()) + PrivateGlobalPrefix = ".L"; + PrivateLabelPrefix = PrivateGlobalPrefix; + AlignmentIsInBytes = false; + Data16bitsDirective = "\t.2byte\t"; + Data32bitsDirective = "\t.4byte\t"; + Data64bitsDirective = "\t.8byte\t"; + CommentString = "#"; + ZeroDirective = "\t.space\t"; + GPRel32Directive = "\t.gpword\t"; + GPRel64Directive = "\t.gpdword\t"; + DTPRel32Directive = "\t.dtprelword\t"; + DTPRel64Directive = "\t.dtpreldword\t"; + TPRel32Directive = "\t.tprelword\t"; + TPRel64Directive = "\t.tpreldword\t"; + UseAssignmentForEHBegin = true; + SupportsDebugInformation = true; + ExceptionsType = ExceptionHandling::DwarfCFI; + DwarfRegNumForCFI = true; + HasMipsExpressions = true; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Emission/MCTargetDesc/LLVMInitializeTargetMC.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Emission/MCTargetDesc/LLVMInitializeTargetMC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7b01b2aad777f0e33601f9c86bac72b81a8343d6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Emission/MCTargetDesc/LLVMInitializeTargetMC.cpp @@ -0,0 +1,19 @@ +extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMipsTargetMC() { + for (Target *T : {&getTheMipsTarget(), &getTheMipselTarget(), &getTheMips64Target(), &getTheMips64elTarget()}) { + RegisterMCAsmInfoFn X(*T, createMipsMCAsmInfo); + TargetRegistry::RegisterMCInstrInfo(*T, createMipsMCInstrInfo); + TargetRegistry::RegisterMCRegInfo(*T, createMipsMCRegisterInfo); + TargetRegistry::RegisterELFStreamer(*T, createMCStreamer); + TargetRegistry::RegisterAsmTargetStreamer(*T, createMipsAsmTargetStreamer); + TargetRegistry::RegisterNullTargetStreamer(*T, createMipsNullTargetStreamer); + TargetRegistry::RegisterMCSubtargetInfo(*T, createMipsMCSubtargetInfo); + TargetRegistry::RegisterMCInstrAnalysis(*T, createMipsMCInstrAnalysis); + TargetRegistry::RegisterMCInstPrinter(*T, createMipsMCInstPrinter); + TargetRegistry::RegisterObjectTargetStreamer(*T, createMipsObjectTargetStreamer); + TargetRegistry::RegisterMCAsmBackend(*T, createMipsAsmBackend); + } + for (Target *T : {&getTheMipsTarget(), &getTheMips64Target()}) + TargetRegistry::RegisterMCCodeEmitter(*T, createMipsMCCodeEmitterEB); + for (Target *T : {&getTheMipselTarget(), &getTheMips64elTarget()}) + TargetRegistry::RegisterMCCodeEmitter(*T, createMipsMCCodeEmitterEL); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Emission/MCTargetDesc/createMCAsmInfo.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Emission/MCTargetDesc/createMCAsmInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..837b9167e024dfc0068281dbe50fc9ad3064ca21 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Emission/MCTargetDesc/createMCAsmInfo.cpp @@ -0,0 +1,7 @@ +static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI, const Triple &TT, const MCTargetOptions &Options) { + MCAsmInfo *MAI = new MipsMCAsmInfo(TT, Options); + unsigned SP = MRI.getDwarfRegNum(Mips::SP, true); + MCCFIInstruction Inst = MCCFIInstruction::createDefCfaRegister(nullptr, SP); + MAI->addInitialFrameState(Inst); + return MAI; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Emission/MCTargetDesc/createMCCodeGenInfo.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Emission/MCTargetDesc/createMCCodeGenInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Emission/MCTargetDesc/createMCCodeGenInfo.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Emission/MCTargetDesc/createMCInstrInfo.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Emission/MCTargetDesc/createMCInstrInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d50ca24c8cac1fc0d6821b37c8cea1728525d7a4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Emission/MCTargetDesc/createMCInstrInfo.cpp @@ -0,0 +1,5 @@ +static MCInstrInfo *createMipsMCInstrInfo() { + MCInstrInfo *X = new MCInstrInfo(); + InitMipsMCInstrInfo(X); + return X; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Emission/MCTargetDesc/createMCRegisterInfo.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Emission/MCTargetDesc/createMCRegisterInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..39b142645d1a74904b92b3d82dd3360575145767 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Emission/MCTargetDesc/createMCRegisterInfo.cpp @@ -0,0 +1,5 @@ +static MCRegisterInfo *createMipsMCRegisterInfo(const Triple &TT) { + MCRegisterInfo *X = new MCRegisterInfo(); + InitMipsMCRegisterInfo(X, Mips::RA); + return X; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Emission/MCTargetDesc/createMCSubtargetInfo.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Emission/MCTargetDesc/createMCSubtargetInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c05371de5a90f36670a3dbf3f15208b2ffbee21f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Emission/MCTargetDesc/createMCSubtargetInfo.cpp @@ -0,0 +1,4 @@ +static MCSubtargetInfo *createMipsMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { + CPU = MIPS_MC::selectMipsCPU(TT, CPU); + return createMipsMCSubtargetInfoImpl(TT, CPU, CPU, FS); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/FrameToArgsOffsetElim/FTAOElim.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/FrameToArgsOffsetElim/FTAOElim.cpp new file mode 100644 index 0000000000000000000000000000000000000000..246aed2bd7e0440bdeb11d57132d657b58c40e08 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/FrameToArgsOffsetElim/FTAOElim.cpp @@ -0,0 +1,2 @@ +XCoreFTAOElim() : FunctionPass(ID) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/FrameToArgsOffsetElim/XCoreFTAOElim.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/FrameToArgsOffsetElim/XCoreFTAOElim.cpp new file mode 100644 index 0000000000000000000000000000000000000000..57aeffd0e2e2e5bb1200734269fc42fb5b8f16c9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/FrameToArgsOffsetElim/XCoreFTAOElim.cpp @@ -0,0 +1,2 @@ +MipsModuleDAGToDAGISel() : MachineFunctionPass(ID) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/FrameToArgsOffsetElim/createPass.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/FrameToArgsOffsetElim/createPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..66bbc81adf0ef98fff67099cd474312163d2ef95 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/FrameToArgsOffsetElim/createPass.cpp @@ -0,0 +1,3 @@ +llvm::FunctionPass *llvm::createMipsModuleISelDagPass() { + return new MipsModuleDAGToDAGISel(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/FrameToArgsOffsetElim/getPassName.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/FrameToArgsOffsetElim/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..90c890951e14cd0629d6e0878884a87bb8c79386 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/FrameToArgsOffsetElim/getPassName.cpp @@ -0,0 +1,3 @@ +StringRef getPassName() const override { + return "Mips Branch Expansion Pass"; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/FrameToArgsOffsetElim/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/FrameToArgsOffsetElim/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..62edb7f880dc7a87d5437717d542d7ef50894acb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/FrameToArgsOffsetElim/runOnMachineFunction.cpp @@ -0,0 +1,21 @@ +bool MipsBranchExpansion::runOnMachineFunction(MachineFunction &MF) { + const TargetMachine &TM = MF.getTarget(); + IsPIC = TM.isPositionIndependent(); + ABI = static_cast(TM).getABI(); + STI = &static_cast(MF.getSubtarget()); + TII = static_cast(STI->getInstrInfo()); + if (IsPIC && ABI.IsO32() && MF.getInfo()->globalBaseRegSet()) + emitGPDisp(MF, TII); + MFp = &MF; + ForceLongBranchFirstPass = ForceLongBranch; + bool longBranchChanged = handlePossibleLongBranch(); + bool forbiddenSlotChanged = handleForbiddenSlot(); + bool Changed = longBranchChanged || forbiddenSlotChanged; + while (forbiddenSlotChanged) { + longBranchChanged = handlePossibleLongBranch(); + if (!longBranchChanged) + break; + forbiddenSlotChanged = handleForbiddenSlot(); + } + return Changed; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/LoopMetadataLowering/LoopMetadataLowering.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/LoopMetadataLowering/LoopMetadataLowering.cpp new file mode 100644 index 0000000000000000000000000000000000000000..57aeffd0e2e2e5bb1200734269fc42fb5b8f16c9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/LoopMetadataLowering/LoopMetadataLowering.cpp @@ -0,0 +1,2 @@ +MipsModuleDAGToDAGISel() : MachineFunctionPass(ID) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/LoopMetadataLowering/createPass.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/LoopMetadataLowering/createPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..66bbc81adf0ef98fff67099cd474312163d2ef95 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/LoopMetadataLowering/createPass.cpp @@ -0,0 +1,3 @@ +llvm::FunctionPass *llvm::createMipsModuleISelDagPass() { + return new MipsModuleDAGToDAGISel(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/LoopMetadataLowering/getAnalysisUsage.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/LoopMetadataLowering/getAnalysisUsage.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3f3e70065dbb1b3bcc423b768c1c4c1713ba4da5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/LoopMetadataLowering/getAnalysisUsage.cpp @@ -0,0 +1,4 @@ +void getAnalysisUsage(AnalysisUsage &AU) const override { + AU.addRequired(); + MachineFunctionPass::getAnalysisUsage(AU); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/LoopMetadataLowering/runOnFunction.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/LoopMetadataLowering/runOnFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..79ef7cfa96944155e794dbd1ce4ae3d7cc85a8f3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/LoopMetadataLowering/runOnFunction.cpp @@ -0,0 +1,9 @@ +bool runOnMachineFunction(MachineFunction &F) override { + TM = &F.getTarget(); + bool Changed = false; + for (MachineFunction::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI) + Changed |= runOnMachineBasicBlock(*FI); + if (Changed) + F.getRegInfo().invalidateLiveness(); + return Changed; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/LoopMetadataLowering/~LoopMetadataLowering.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/LoopMetadataLowering/~LoopMetadataLowering.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1d221dc7344e31e88ccbd1e8b8b3fbe166b367a6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/LoopMetadataLowering/~LoopMetadataLowering.cpp @@ -0,0 +1,2 @@ +~MipsModuleDAGToDAGISel() { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/SimpleBranchOpt/SimpleBranchOpt.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/SimpleBranchOpt/SimpleBranchOpt.cpp new file mode 100644 index 0000000000000000000000000000000000000000..57aeffd0e2e2e5bb1200734269fc42fb5b8f16c9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/SimpleBranchOpt/SimpleBranchOpt.cpp @@ -0,0 +1,2 @@ +MipsModuleDAGToDAGISel() : MachineFunctionPass(ID) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/SimpleBranchOpt/createPass.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/SimpleBranchOpt/createPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..66bbc81adf0ef98fff67099cd474312163d2ef95 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/SimpleBranchOpt/createPass.cpp @@ -0,0 +1,3 @@ +llvm::FunctionPass *llvm::createMipsModuleISelDagPass() { + return new MipsModuleDAGToDAGISel(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/SimpleBranchOpt/getPassName.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/SimpleBranchOpt/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..90c890951e14cd0629d6e0878884a87bb8c79386 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/SimpleBranchOpt/getPassName.cpp @@ -0,0 +1,3 @@ +StringRef getPassName() const override { + return "Mips Branch Expansion Pass"; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/SimpleBranchOpt/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/SimpleBranchOpt/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..62edb7f880dc7a87d5437717d542d7ef50894acb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/SimpleBranchOpt/runOnMachineFunction.cpp @@ -0,0 +1,21 @@ +bool MipsBranchExpansion::runOnMachineFunction(MachineFunction &MF) { + const TargetMachine &TM = MF.getTarget(); + IsPIC = TM.isPositionIndependent(); + ABI = static_cast(TM).getABI(); + STI = &static_cast(MF.getSubtarget()); + TII = static_cast(STI->getInstrInfo()); + if (IsPIC && ABI.IsO32() && MF.getInfo()->globalBaseRegSet()) + emitGPDisp(MF, TII); + MFp = &MF; + ForceLongBranchFirstPass = ForceLongBranch; + bool longBranchChanged = handlePossibleLongBranch(); + bool forbiddenSlotChanged = handleForbiddenSlot(); + bool Changed = longBranchChanged || forbiddenSlotChanged; + while (forbiddenSlotChanged) { + longBranchChanged = handlePossibleLongBranch(); + if (!longBranchChanged) + break; + forbiddenSlotChanged = handleForbiddenSlot(); + } + return Changed; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/StackAnalysisPrepare/StackAnalysisPrepare.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/StackAnalysisPrepare/StackAnalysisPrepare.cpp new file mode 100644 index 0000000000000000000000000000000000000000..57aeffd0e2e2e5bb1200734269fc42fb5b8f16c9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/StackAnalysisPrepare/StackAnalysisPrepare.cpp @@ -0,0 +1,2 @@ +MipsModuleDAGToDAGISel() : MachineFunctionPass(ID) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/StackAnalysisPrepare/createPass.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/StackAnalysisPrepare/createPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..66bbc81adf0ef98fff67099cd474312163d2ef95 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/StackAnalysisPrepare/createPass.cpp @@ -0,0 +1,3 @@ +llvm::FunctionPass *llvm::createMipsModuleISelDagPass() { + return new MipsModuleDAGToDAGISel(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/StackAnalysisPrepare/getAnalysisUsage.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/StackAnalysisPrepare/getAnalysisUsage.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3f3e70065dbb1b3bcc423b768c1c4c1713ba4da5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/StackAnalysisPrepare/getAnalysisUsage.cpp @@ -0,0 +1,4 @@ +void getAnalysisUsage(AnalysisUsage &AU) const override { + AU.addRequired(); + MachineFunctionPass::getAnalysisUsage(AU); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/StackAnalysisPrepare/runOnFunction.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/StackAnalysisPrepare/runOnFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..66c7b3864fbc88610507a3b57469c33cbe7067a8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/StackAnalysisPrepare/runOnFunction.cpp @@ -0,0 +1,21 @@ +bool MipsBranchExpansion::runOnMachineFunction(MachineFunction &MF) { + const TargetMachine &TM = MF.getTarget(); + IsPIC = TM.isPositionIndependent(); + ABI = static_cast(TM).getABI(); + STI = &static_cast(MF.getSubtarget()); + TII = static_cast(STI->getInstrInfo()); + if (IsPIC && ABI.IsO32() && MF.getInfo()->globalBaseRegSet()) + emitGPDisp(MF, TII); + MFp = &MF; + ForceLongBranchFirstPass = ForceLongBranch; + bool longBranchChanged = handlePossibleLongBranch(); + bool forbiddenSlotChanged = handleForbiddenSlot(); + bool Changed = longBranchChanged || forbiddenSlotChanged; + while (forbiddenSlotChanged) { + longBranchChanged = handlePossibleLongBranch(); + if (!longBranchChanged) + break; + forbiddenSlotChanged = handleForbiddenSlot(); + } + return Changed; +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/StackAnalysisPrepare/~StackAnalysisPrepare.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/StackAnalysisPrepare/~StackAnalysisPrepare.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1d221dc7344e31e88ccbd1e8b8b3fbe166b367a6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/StackAnalysisPrepare/~StackAnalysisPrepare.cpp @@ -0,0 +1,2 @@ +~MipsModuleDAGToDAGISel() { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/StackUsage/StackUsage.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/StackUsage/StackUsage.cpp new file mode 100644 index 0000000000000000000000000000000000000000..57aeffd0e2e2e5bb1200734269fc42fb5b8f16c9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/StackUsage/StackUsage.cpp @@ -0,0 +1,2 @@ +MipsModuleDAGToDAGISel() : MachineFunctionPass(ID) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/StackUsage/createPass.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/StackUsage/createPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..66bbc81adf0ef98fff67099cd474312163d2ef95 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/StackUsage/createPass.cpp @@ -0,0 +1,3 @@ +llvm::FunctionPass *llvm::createMipsModuleISelDagPass() { + return new MipsModuleDAGToDAGISel(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/StackUsage/getAnalysisUsage.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/StackUsage/getAnalysisUsage.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3f3e70065dbb1b3bcc423b768c1c4c1713ba4da5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/StackUsage/getAnalysisUsage.cpp @@ -0,0 +1,4 @@ +void getAnalysisUsage(AnalysisUsage &AU) const override { + AU.addRequired(); + MachineFunctionPass::getAnalysisUsage(AU); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/StackUsage/getPassName.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/StackUsage/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..90c890951e14cd0629d6e0878884a87bb8c79386 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/StackUsage/getPassName.cpp @@ -0,0 +1,3 @@ +StringRef getPassName() const override { + return "Mips Branch Expansion Pass"; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/StackUsage/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/StackUsage/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..62edb7f880dc7a87d5437717d542d7ef50894acb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Optimization/StackUsage/runOnMachineFunction.cpp @@ -0,0 +1,21 @@ +bool MipsBranchExpansion::runOnMachineFunction(MachineFunction &MF) { + const TargetMachine &TM = MF.getTarget(); + IsPIC = TM.isPositionIndependent(); + ABI = static_cast(TM).getABI(); + STI = &static_cast(MF.getSubtarget()); + TII = static_cast(STI->getInstrInfo()); + if (IsPIC && ABI.IsO32() && MF.getInfo()->globalBaseRegSet()) + emitGPDisp(MF, TII); + MFp = &MF; + ForceLongBranchFirstPass = ForceLongBranch; + bool longBranchChanged = handlePossibleLongBranch(); + bool forbiddenSlotChanged = handleForbiddenSlot(); + bool Changed = longBranchChanged || forbiddenSlotChanged; + while (forbiddenSlotChanged) { + longBranchChanged = handlePossibleLongBranch(); + if (!longBranchChanged) + break; + forbiddenSlotChanged = handleForbiddenSlot(); + } + return Changed; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/GetCondBranchFromCond.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/GetCondBranchFromCond.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/GetCondBranchFromCond.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/GetCondFromBranchOpc.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/GetCondFromBranchOpc.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/GetCondFromBranchOpc.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/GetInstSizeInBytes.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/GetInstSizeInBytes.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ccb0f52e6e0ce8474fcd10633894b3f408fc5308 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/GetInstSizeInBytes.cpp @@ -0,0 +1,15 @@ +unsigned MipsInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const { + switch (MI.getOpcode()) { + default: + return MI.getDesc().getSize(); + case TargetOpcode::INLINEASM: + case TargetOpcode::INLINEASM_BR: { + const MachineFunction *MF = MI.getParent()->getParent(); + const char *AsmStr = MI.getOperand(0).getSymbolName(); + return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo()); + } + case Mips::CONSTPOOL_ENTRY: + return MI.getOperand(2).getImm(); + } +} + diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/GetOppositeBranchCondition.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/GetOppositeBranchCondition.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/GetOppositeBranchCondition.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/InstrInfo.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/InstrInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..89ef265a73d366c9fe3f2c94f235af727e8b5dcd --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/InstrInfo.cpp @@ -0,0 +1,2 @@ +MipsInstrInfo::MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBr) : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP), Subtarget(STI), UncondBrOpc(UncondBr) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/IsBRF.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/IsBRF.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/IsBRF.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/IsBRT.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/IsBRT.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/IsBRT.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/IsBRU.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/IsBRU.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/IsBRU.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/IsBR_JT.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/IsBR_JT.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/IsBR_JT.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/IsCondBranch.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/IsCondBranch.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/IsCondBranch.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/analyzeBranch.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/analyzeBranch.cpp new file mode 100644 index 0000000000000000000000000000000000000000..492da016718b9b6f818e0f34a01596e175c6affb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/analyzeBranch.cpp @@ -0,0 +1,5 @@ +bool MipsInstrInfo::analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl &Cond, bool AllowModify) const { + SmallVector BranchInstrs; + BranchType BT = analyzeBranch(MBB, TBB, FBB, Cond, AllowModify, BranchInstrs); + return (BT == BT_None) || (BT == BT_Indirect); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/copyPhysReg.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/copyPhysReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a5fc2c1a67373b362485a1ac80c16cbe10ca55a9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/copyPhysReg.cpp @@ -0,0 +1,92 @@ +void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const { + unsigned Opc = 0, ZeroReg = 0; + bool isMicroMips = Subtarget.inMicroMipsMode(); + if (Mips::GPR32RegClass.contains(DestReg)) { + if (Mips::GPR32RegClass.contains(SrcReg)) { + if (isMicroMips) + Opc = Mips::MOVE16_MM; + else + Opc = Mips::OR, ZeroReg = Mips::ZERO; + } + else if (Mips::CCRRegClass.contains(SrcReg)) + Opc = Mips::CFC1; + else if (Mips::FGR32RegClass.contains(SrcReg)) + Opc = Mips::MFC1; + else if (Mips::HI32RegClass.contains(SrcReg)) { + Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI; + SrcReg = 0; + } + else if (Mips::LO32RegClass.contains(SrcReg)) { + Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO; + SrcReg = 0; + } + else if (Mips::HI32DSPRegClass.contains(SrcReg)) + Opc = Mips::MFHI_DSP; + else if (Mips::LO32DSPRegClass.contains(SrcReg)) + Opc = Mips::MFLO_DSP; + else if (Mips::DSPCCRegClass.contains(SrcReg)) { + BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4).addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc)); + return; + } + else if (Mips::MSACtrlRegClass.contains(SrcReg)) + Opc = Mips::CFCMSA; + } + else if (Mips::GPR32RegClass.contains(SrcReg)) { + if (Mips::CCRRegClass.contains(DestReg)) + Opc = Mips::CTC1; + else if (Mips::FGR32RegClass.contains(DestReg)) + Opc = Mips::MTC1; + else if (Mips::HI32RegClass.contains(DestReg)) + Opc = Mips::MTHI, DestReg = 0; + else if (Mips::LO32RegClass.contains(DestReg)) + Opc = Mips::MTLO, DestReg = 0; + else if (Mips::HI32DSPRegClass.contains(DestReg)) + Opc = Mips::MTHI_DSP; + else if (Mips::LO32DSPRegClass.contains(DestReg)) + Opc = Mips::MTLO_DSP; + else if (Mips::DSPCCRegClass.contains(DestReg)) { + BuildMI(MBB, I, DL, get(Mips::WRDSP)).addReg(SrcReg, getKillRegState(KillSrc)).addImm(1 << 4).addReg(DestReg, RegState::ImplicitDefine); + return; + } + else if (Mips::MSACtrlRegClass.contains(DestReg)) { + BuildMI(MBB, I, DL, get(Mips::CTCMSA)).addReg(DestReg).addReg(SrcReg, getKillRegState(KillSrc)); + return; + } + } + else if (Mips::FGR32RegClass.contains(DestReg, SrcReg)) + Opc = Mips::FMOV_S; + else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg)) + Opc = Mips::FMOV_D32; + else if (Mips::FGR64RegClass.contains(DestReg, SrcReg)) + Opc = Mips::FMOV_D64; + else if (Mips::GPR64RegClass.contains(DestReg)) { + if (Mips::GPR64RegClass.contains(SrcReg)) + Opc = Mips::OR64, ZeroReg = Mips::ZERO_64; + else if (Mips::HI64RegClass.contains(SrcReg)) + Opc = Mips::MFHI64, SrcReg = 0; + else if (Mips::LO64RegClass.contains(SrcReg)) + Opc = Mips::MFLO64, SrcReg = 0; + else if (Mips::FGR64RegClass.contains(SrcReg)) + Opc = Mips::DMFC1; + } + else if (Mips::GPR64RegClass.contains(SrcReg)) { + if (Mips::HI64RegClass.contains(DestReg)) + Opc = Mips::MTHI64, DestReg = 0; + else if (Mips::LO64RegClass.contains(DestReg)) + Opc = Mips::MTLO64, DestReg = 0; + else if (Mips::FGR64RegClass.contains(DestReg)) + Opc = Mips::DMTC1; + } + else if (Mips::MSA128BRegClass.contains(DestReg)) { + if (Mips::MSA128BRegClass.contains(SrcReg)) + Opc = Mips::MOVE_V; + } + assert(Opc && "Cannot copy registers"); + MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc)); + if (DestReg) + MIB.addReg(DestReg, RegState::Define); + if (SrcReg) + MIB.addReg(SrcReg, getKillRegState(KillSrc)); + if (ZeroReg) + MIB.addReg(ZeroReg); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/emitFrameIndexDebugValue.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/emitFrameIndexDebugValue.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/emitFrameIndexDebugValue.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/enum CondCode.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/enum CondCode.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3279dd0d1e31fed87ed756d32f1a675d18d72f87 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/enum CondCode.cpp @@ -0,0 +1,34 @@ +enum CondCode { + FCOND_F, + FCOND_UN, + FCOND_OEQ, + FCOND_UEQ, + FCOND_OLT, + FCOND_ULT, + FCOND_OLE, + FCOND_ULE, + FCOND_SF, + FCOND_NGLE, + FCOND_SEQ, + FCOND_NGL, + FCOND_LT, + FCOND_NGE, + FCOND_LE, + FCOND_NGT, + FCOND_T, + FCOND_OR, + FCOND_UNE, + FCOND_ONE, + FCOND_UGE, + FCOND_OGE, + FCOND_UGT, + FCOND_OGT, + FCOND_ST, + FCOND_GLE, + FCOND_SNE, + FCOND_GL, + FCOND_NLT, + FCOND_GE, + FCOND_NLE, + FCOND_GT +}; \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/getRegisterInfo.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/getRegisterInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4b072526d794d139a2d7a77e15192a44279a4e4f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/getRegisterInfo.cpp @@ -0,0 +1,3 @@ +const MipsRegisterInfo &Mips16InstrInfo::getRegisterInfo() const { + return RI; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/insertBranch.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/insertBranch.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7aadd2573c6e9b7e1703c86ae78cd84d2f384d34 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/insertBranch.cpp @@ -0,0 +1,15 @@ +unsigned MipsInstrInfo::insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, const DebugLoc &DL, int *BytesAdded) const { + assert(TBB && "insertBranch must not be told to insert a fallthrough"); + assert(!BytesAdded && "code size not handled"); + assert((Cond.size() <= 3) && "# of Mips branch conditions must be <= 3!"); + if (FBB) { + BuildCondBr(MBB, TBB, DL, Cond); + BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(FBB); + return 2; + } + if (Cond.empty()) + BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(TBB); + else + BuildCondBr(MBB, TBB, DL, Cond); + return 1; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/isLoadFromStackSlot.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/isLoadFromStackSlot.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e2d8d63900cd69f173695b130359cfe1d18aa693 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/isLoadFromStackSlot.cpp @@ -0,0 +1,10 @@ +unsigned MipsSEInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const { + unsigned Opc = MI.getOpcode(); + if ((Opc == Mips::LW) || (Opc == Mips::LD) || (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) { + if ((MI.getOperand(1).isFI()) && (MI.getOperand(2).isImm()) && (isZeroImm(MI.getOperand(2)))) { + FrameIndex = MI.getOperand(1).getIndex(); + return MI.getOperand(0).getReg(); + } + } + return 0; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/isStoreToStackSlot.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/isStoreToStackSlot.cpp new file mode 100644 index 0000000000000000000000000000000000000000..049c3f11016793dd29d3fb81bb7172132b37b96d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/isStoreToStackSlot.cpp @@ -0,0 +1,11 @@ +unsigned MipsSEInstrInfo::isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const { + unsigned Opc = MI.getOpcode(); + if ((Opc == Mips::SW) || (Opc == Mips::SD) || (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) { + if ((MI.getOperand(1).isFI()) && (MI.getOperand(2).isImm()) && (isZeroImm(MI.getOperand(2)))) { + FrameIndex = MI.getOperand(1).getIndex(); + return MI.getOperand(0).getReg(); + } + } + return 0; +} + diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/isZeroImm.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/isZeroImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..acbba623439a5f57428157ada9c9f62c3fb4073d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/isZeroImm.cpp @@ -0,0 +1,3 @@ +bool MipsInstrInfo::isZeroImm(const MachineOperand &op) const { + return op.isImm() && op.getImm() == 0; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/loadRegFromStackSlot.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/loadRegFromStackSlot.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0dbe9a6a32e51bc601900a9635c3d6376933a144 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/loadRegFromStackSlot.cpp @@ -0,0 +1,62 @@ +void MipsSEInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const { + DebugLoc DL; + if (I != MBB.end()) DL = I->getDebugLoc(); + MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad); + unsigned Opc = 0; + const Function &Func = MBB.getParent()->getFunction(); + bool ReqIndirectLoad = Func.hasFnAttribute("interrupt") && (DestReg == Mips::LO0 || DestReg == Mips::LO0_64 || DestReg == Mips::HI0 || DestReg == Mips::HI0_64); + if (Mips::GPR32RegClass.hasSubClassEq(RC)) + Opc = Mips::LW; + else if (Mips::GPR64RegClass.hasSubClassEq(RC)) + Opc = Mips::LD; + else if (Mips::ACC64RegClass.hasSubClassEq(RC)) + Opc = Mips::LOAD_ACC64; + else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC)) + Opc = Mips::LOAD_ACC64DSP; + else if (Mips::ACC128RegClass.hasSubClassEq(RC)) + Opc = Mips::LOAD_ACC128; + else if (Mips::DSPCCRegClass.hasSubClassEq(RC)) + Opc = Mips::LOAD_CCOND_DSP; + else if (Mips::FGR32RegClass.hasSubClassEq(RC)) + Opc = Mips::LWC1; + else if (Mips::AFGR64RegClass.hasSubClassEq(RC)) + Opc = Mips::LDC1; + else if (Mips::FGR64RegClass.hasSubClassEq(RC)) + Opc = Mips::LDC164; + else if (TRI->isTypeLegalForClass(*RC, MVT::v16i8)) + Opc = Mips::LD_B; + else if (TRI->isTypeLegalForClass(*RC, MVT::v8i16) || TRI->isTypeLegalForClass(*RC, MVT::v8f16)) + Opc = Mips::LD_H; + else if (TRI->isTypeLegalForClass(*RC, MVT::v4i32) || TRI->isTypeLegalForClass(*RC, MVT::v4f32)) + Opc = Mips::LD_W; + else if (TRI->isTypeLegalForClass(*RC, MVT::v2i64) || TRI->isTypeLegalForClass(*RC, MVT::v2f64)) + Opc = Mips::LD_D; + else if (Mips::HI32RegClass.hasSubClassEq(RC)) + Opc = Mips::LW; + else if (Mips::HI64RegClass.hasSubClassEq(RC)) + Opc = Mips::LD; + else if (Mips::LO32RegClass.hasSubClassEq(RC)) + Opc = Mips::LW; + else if (Mips::LO64RegClass.hasSubClassEq(RC)) + Opc = Mips::LD; + else if (Mips::DSPRRegClass.hasSubClassEq(RC)) + Opc = Mips::LWDSP; + assert(Opc && "Register class not handled!"); + if (!ReqIndirectLoad) + BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(Offset).addMemOperand(MMO); + else { + unsigned Reg = Mips::K0; + unsigned LdOp = Mips::MTLO; + if (DestReg == Mips::HI0) + LdOp = Mips::MTHI; + if (Subtarget.getABI().ArePtrs64bit()) { + Reg = Mips::K0_64; + if (DestReg == Mips::HI0_64) + LdOp = Mips::MTHI64; + else + LdOp = Mips::MTLO64; + } + BuildMI(MBB, I, DL, get(Opc), Reg).addFrameIndex(FI).addImm(Offset).addMemOperand(MMO); + BuildMI(MBB, I, DL, get(LdOp)).addReg(Reg); + } +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/removeBranch.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/removeBranch.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cef1e08a42cd47a219a08a7b03df1b62305453b3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/removeBranch.cpp @@ -0,0 +1,17 @@ +unsigned MipsInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved) const { + assert(!BytesRemoved && "code size not handled"); + MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend(); + unsigned removed = 0; + while (I != REnd && removed < 2) { + if (I->isDebugInstr()) { + ++I; + continue; + } + if (!getAnalyzableBrOpc(I->getOpcode())) + break; + I->eraseFromParent(); + I = MBB.rbegin(); + ++removed; + } + return removed; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/reverseBranchCondition.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/reverseBranchCondition.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bf4c73519980083d2273651b2680171851c4d0a1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/reverseBranchCondition.cpp @@ -0,0 +1,5 @@ +bool MipsInstrInfo::reverseBranchCondition(SmallVectorImpl &Cond) const { + assert( (Cond.size() && Cond.size() <= 3) && "Invalid Mips branch condition!"); + Cond[0].setImm(getOppositeBranchOpc(Cond[0].getImm())); + return false; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/storeRegToStackSlot.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/storeRegToStackSlot.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b46bd40f8ae60038cbce551cc210dfdc0d86cc72 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/InstrInfo/storeRegToStackSlot.cpp @@ -0,0 +1,10 @@ +void Mips16InstrInfo::storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const { + DebugLoc DL; + if (I != MBB.end()) DL = I->getDebugLoc(); + MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore); + unsigned Opc = 0; + if (Mips::CPU16RegsRegClass.hasSubClassEq(RC)) + Opc = Mips::SwRxSpImmX16; + assert(Opc && "Register class not handled!"); + BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)).addFrameIndex(FI).addImm(Offset).addMemOperand(MMO); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/MachineFunctionInfo/Call.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/MachineFunctionInfo/Call.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/MachineFunctionInfo/Call.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/MachineFunctionInfo/ExternalSymbolCall.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/MachineFunctionInfo/ExternalSymbolCall.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/MachineFunctionInfo/ExternalSymbolCall.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/MachineFunctionInfo/FunctionCall.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/MachineFunctionInfo/FunctionCall.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/MachineFunctionInfo/FunctionCall.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/MachineFunctionInfo/FunctionInfo.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/MachineFunctionInfo/FunctionInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/MachineFunctionInfo/FunctionInfo.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/MachineFunctionInfo/FunctionInfo2.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/MachineFunctionInfo/FunctionInfo2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/MachineFunctionInfo/FunctionInfo2.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/MachineFunctionInfo/classof1.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/MachineFunctionInfo/classof1.cpp new file mode 100644 index 0000000000000000000000000000000000000000..18efd6eb03d8a873e79039e5a7191354ce092d82 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/MachineFunctionInfo/classof1.cpp @@ -0,0 +1,3 @@ +static bool classof(const MCExpr *E) { + return E->getKind() == MCExpr::Target; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/MachineFunctionInfo/classof2.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/MachineFunctionInfo/classof2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..18efd6eb03d8a873e79039e5a7191354ce092d82 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/MachineFunctionInfo/classof2.cpp @@ -0,0 +1,3 @@ +static bool classof(const MCExpr *E) { + return E->getKind() == MCExpr::Target; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/MachineFunctionInfo/classof3.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/MachineFunctionInfo/classof3.cpp new file mode 100644 index 0000000000000000000000000000000000000000..18efd6eb03d8a873e79039e5a7191354ce092d82 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/MachineFunctionInfo/classof3.cpp @@ -0,0 +1,3 @@ +static bool classof(const MCExpr *E) { + return E->getKind() == MCExpr::Target; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/MachineFunctionInfo/classof4.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/MachineFunctionInfo/classof4.cpp new file mode 100644 index 0000000000000000000000000000000000000000..18efd6eb03d8a873e79039e5a7191354ce092d82 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/MachineFunctionInfo/classof4.cpp @@ -0,0 +1,3 @@ +static bool classof(const MCExpr *E) { + return E->getKind() == MCExpr::Target; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/MachineFunctionInfo/classof5.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/MachineFunctionInfo/classof5.cpp new file mode 100644 index 0000000000000000000000000000000000000000..18efd6eb03d8a873e79039e5a7191354ce092d82 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/MachineFunctionInfo/classof5.cpp @@ -0,0 +1,3 @@ +static bool classof(const MCExpr *E) { + return E->getKind() == MCExpr::Target; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/MachineFunctionInfo/getCalls.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/MachineFunctionInfo/getCalls.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/MachineFunctionInfo/getCalls.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/MachineFunctionInfo/getFunction.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/MachineFunctionInfo/getFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/MachineFunctionInfo/getFunction.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/MachineFunctionInfo/getHasIndirectCalls.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/MachineFunctionInfo/getHasIndirectCalls.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/MachineFunctionInfo/getHasIndirectCalls.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/MachineFunctionInfo/getSymbol.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/MachineFunctionInfo/getSymbol.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/MachineFunctionInfo/getSymbol.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/MachineFunctionInfo/getType.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/MachineFunctionInfo/getType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/MachineFunctionInfo/getType.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/MachineFunctionInfo/getVarArgsFrameIndex.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/MachineFunctionInfo/getVarArgsFrameIndex.cpp new file mode 100644 index 0000000000000000000000000000000000000000..815700881400f3e2610e1d74e0907493d5ea7898 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/MachineFunctionInfo/getVarArgsFrameIndex.cpp @@ -0,0 +1,3 @@ +int getVarArgsFrameIndex() const { + return VarArgsFrameIndex; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/MachineFunctionInfo/setHasIndirectCalls.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/MachineFunctionInfo/setHasIndirectCalls.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/MachineFunctionInfo/setHasIndirectCalls.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/MachineFunctionInfo/setVarArgsFrameIndex.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/MachineFunctionInfo/setVarArgsFrameIndex.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f453600ffb2d2bf1e86883efc8373719fb63f8ae --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/MachineFunctionInfo/setVarArgsFrameIndex.cpp @@ -0,0 +1,3 @@ +void setVarArgsFrameIndex(int Index) { + VarArgsFrameIndex = Index; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/MachineFunctionInfo/~FunctionInfo.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/MachineFunctionInfo/~FunctionInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/MachineFunctionInfo/~FunctionInfo.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/Subtarget/Subtarget.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/Subtarget/Subtarget.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f8dbe9393d5f502927a51bf3bd6e31b2ef5a0ed3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/Subtarget/Subtarget.cpp @@ -0,0 +1,89 @@ +MipsSubtarget::MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS, bool little, const MipsTargetMachine &TM, MaybeAlign StackAlignOverride): MipsGenSubtargetInfo(TT, CPU, CPU, FS), MipsArchVersion(MipsDefault), IsLittle(little), IsSoftFloat(false), IsSingleFloat(false), IsFPXX(false), NoABICalls(false), Abs2008(false), IsFP64bit(false), UseOddSPReg(true), IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false), HasCnMips(false), HasCnMipsP(false), HasMips3_32(false), HasMips3_32r2(false), HasMips4_32(false), HasMips4_32r2(false), HasMips5_32r2(false), InMips16Mode(false), InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false), HasDSPR2(false), HasDSPR3(false), AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16), HasMSA(false), UseTCCInDIV(false), HasSym32(false), HasEVA(false), DisableMadd4(false), HasMT(false), HasCRC(false), HasVirt(false), HasGINV(false), UseIndirectJumpsHazard(false), StackAlignOverride(StackAlignOverride), TM(TM), TargetTriple(TT), TSInfo(), InstrInfo(MipsInstrInfo::create( initializeSubtargetDependencies(CPU, FS, TM))), FrameLowering(MipsFrameLowering::create(*this)), TLInfo(MipsTargetLowering::create(TM, *this)) { + if (MipsArchVersion == MipsDefault) + MipsArchVersion = Mips32; + if (MipsArchVersion == Mips1) + report_fatal_error("Code generation for MIPS-I is not implemented", false); + if (MipsArchVersion == Mips5) + report_fatal_error("Code generation for MIPS-V is not implemented", false); + assert(((!isGP64bit() && isABI_O32()) || (isGP64bit() && (isABI_N32() || isABI_N64()))) && "Invalid Arch & ABI pair."); + if (hasMSA() && !isFP64bit()) + report_fatal_error("MSA requires a 64-bit FPU register file (FR=1 mode). See -mattr=+fp64.", false); + if (isFP64bit() && !hasMips64() && hasMips32() && !hasMips32r2()) + report_fatal_error("FPU with 64-bit registers is not available on MIPS32 pre revision 2. Use -mcpu=mips32r2 or greater."); + if (!isABI_O32() && !useOddSPReg()) + report_fatal_error("-mattr=+nooddspreg requires the O32 ABI.", false); + if (IsFPXX && (isABI_N32() || isABI_N64())) + report_fatal_error("FPXX is not permitted for the N32/N64 ABI's.", false); + if (hasMips64r6() && InMicroMipsMode) + report_fatal_error("microMIPS64R6 is not supported", false); + if (!isABI_O32() && InMicroMipsMode) + report_fatal_error("microMIPS64 is not supported.", false); + if (UseIndirectJumpsHazard) { + if (InMicroMipsMode) + report_fatal_error("cannot combine indirect jumps with hazard barriers and microMIPS"); + if (!hasMips32r2()) + report_fatal_error("indirect jumps with hazard barriers requires MIPS32R2 or later"); + } + if (inAbs2008Mode() && hasMips32() && !hasMips32r2()) { + report_fatal_error("IEEE 754-2008 abs.fmt is not supported for the given architecture.", false); + } + if (hasMips32r6()) { + StringRef ISA = hasMips64r6() ? "MIPS64r6" : "MIPS32r6"; + assert(isFP64bit()); + assert(isNaN2008()); + assert(inAbs2008Mode()); + if (hasDSP()) + report_fatal_error(ISA + " is not compatible with the DSP ASE", false); + } + if (NoABICalls && TM.isPositionIndependent()) + report_fatal_error("position-independent code requires '-mabicalls'"); + if (isABI_N64() && !TM.isPositionIndependent() && !hasSym32()) + NoABICalls = true; + UseSmallSection = GPOpt; + if (!NoABICalls && GPOpt) { + errs() << "warning: cannot use small-data accesses for '-mabicalls'" << "\n"; + UseSmallSection = false; + } + if (hasDSPR2() && !DspWarningPrinted) { + if (hasMips64() && !hasMips64r2()) { + errs() << "warning: the 'dspr2' ASE requires MIPS64 revision 2 or " << "greater\n"; + DspWarningPrinted = true; + } + else if (hasMips32() && !hasMips32r2()) { + errs() << "warning: the 'dspr2' ASE requires MIPS32 revision 2 or " << "greater\n"; + DspWarningPrinted = true; + } + } + else if (hasDSP() && !DspWarningPrinted) { + if (hasMips64() && !hasMips64r2()) { + errs() << "warning: the 'dsp' ASE requires MIPS64 revision 2 or " << "greater\n"; + DspWarningPrinted = true; + } + else if (hasMips32() && !hasMips32r2()) { + errs() << "warning: the 'dsp' ASE requires MIPS32 revision 2 or " << "greater\n"; + DspWarningPrinted = true; + } + } + StringRef ArchName = hasMips64() ? "MIPS64" : "MIPS32"; + if (!hasMips32r5() && hasMSA() && !MSAWarningPrinted) { + errs() << "warning: the 'msa' ASE requires " << ArchName << " revision 5 or greater\n"; + MSAWarningPrinted = true; + } + if (!hasMips32r5() && hasVirt() && !VirtWarningPrinted) { + errs() << "warning: the 'virt' ASE requires " << ArchName << " revision 5 or greater\n"; + VirtWarningPrinted = true; + } + if (!hasMips32r6() && hasCRC() && !CRCWarningPrinted) { + errs() << "warning: the 'crc' ASE requires " << ArchName << " revision 6 or greater\n"; + CRCWarningPrinted = true; + } + if (!hasMips32r6() && hasGINV() && !GINVWarningPrinted) { + errs() << "warning: the 'ginv' ASE requires " << ArchName << " revision 6 or greater\n"; + GINVWarningPrinted = true; + } + CallLoweringInfo.reset(new MipsCallLowering(*getTargetLowering())); + Legalizer.reset(new MipsLegalizerInfo(*this)); + auto *RBI = new MipsRegisterBankInfo(*getRegisterInfo()); + RegBankInfo.reset(RBI); + InstSelector.reset(createMipsInstructionSelector(*static_cast(&TM), *this, *RBI)); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/TargetInfo/LLVMInitializeTargetInfo.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/TargetInfo/LLVMInitializeTargetInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..aa19b102fcb9d571a36a08f83de9e63d0dad45af --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/TargetInfo/LLVMInitializeTargetInfo.cpp @@ -0,0 +1,6 @@ +extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMipsTargetInfo() { + RegisterTarget X(getTheMipsTarget(), "mips", "MIPS (32-bit big endian)", "Mips"); + RegisterTarget Y(getTheMipselTarget(), "mipsel", "MIPS (32-bit little endian)", "Mips"); + RegisterTarget A(getTheMips64Target(), "mips64", "MIPS (64-bit big endian)", "Mips"); + RegisterTarget B(getTheMips64elTarget(), "mips64el", "MIPS (64-bit little endian)","Mips"); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/TargetMachine/LLVMInitializeTarget.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/TargetMachine/LLVMInitializeTarget.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cebec48b8e7e252d90044f50cbef0210c65c5fa2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/TargetMachine/LLVMInitializeTarget.cpp @@ -0,0 +1,13 @@ +extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMipsTarget() { + RegisterTargetMachine X(getTheMipsTarget()); + RegisterTargetMachine Y(getTheMipselTarget()); + RegisterTargetMachine A(getTheMips64Target()); + RegisterTargetMachine B(getTheMips64elTarget()); + PassRegistry *PR = PassRegistry::getPassRegistry(); + initializeGlobalISel(*PR); + initializeMipsDelaySlotFillerPass(*PR); + initializeMipsBranchExpansionPass(*PR); + initializeMicroMipsSizeReducePass(*PR); + initializeMipsPreLegalizerCombinerPass(*PR); +} + diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/TargetMachine/TargetMachine.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/TargetMachine/TargetMachine.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bb7a4b12d46b90e267a11d089bac3205f01c869d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/TargetMachine/TargetMachine.cpp @@ -0,0 +1,5 @@ +MipsTargetMachine::MipsTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional RM, Optional CM, CodeGenOpt::Level OL, bool JIT, bool isLittle) : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT, CPU, FS, Options, getEffectiveRelocModel(JIT, RM), getEffectiveCodeModel(CM, CodeModel::Small), OL), isLittle(isLittle), TLOF(std::make_unique()), ABI(MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions)), Subtarget(nullptr), DefaultSubtarget(TT, CPU, FS, isLittle, *this, MaybeAlign(Options.StackAlignmentOverride)), NoMips16Subtarget(TT, CPU, FS.empty() ? "-mips16" : FS.str() + ",-mips16", isLittle, *this, MaybeAlign(Options.StackAlignmentOverride)), Mips16Subtarget(TT, CPU, FS.empty() ? "+mips16" : FS.str() + ",+mips16", isLittle, *this, MaybeAlign(Options.StackAlignmentOverride)) { + Subtarget = &DefaultSubtarget; + initAsmInfo(); + setSupportsDebugEntryValues(true); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/TargetMachine/addInstSelector.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/TargetMachine/addInstSelector.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fed7400583c9fc2fb0ebb7485b3e4058b93f7c8b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/TargetMachine/addInstSelector.cpp @@ -0,0 +1,6 @@ +bool MipsPassConfig::addInstSelector() { + addPass(createMipsModuleISelDagPass()); + addPass(createMips16ISelDag(getMipsTargetMachine(), getOptLevel())); + addPass(createMipsSEISelDag(getMipsTargetMachine(), getOptLevel())); + return false; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/TargetMachine/addPreEmitPass.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/TargetMachine/addPreEmitPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..06d033e3b1fed3f9944e982215833add08185065 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/TargetMachine/addPreEmitPass.cpp @@ -0,0 +1,7 @@ +void MipsPassConfig::addPreEmitPass() { + addPass(createMipsExpandPseudoPass()); + addPass(createMicroMipsSizeReducePass()); + addPass(createMipsDelaySlotFillerPass()); + addPass(createMipsBranchExpansion()); + addPass(createMipsConstantIslandPass()); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/TargetMachine/addPreISel.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/TargetMachine/addPreISel.cpp new file mode 100644 index 0000000000000000000000000000000000000000..06d033e3b1fed3f9944e982215833add08185065 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/TargetMachine/addPreISel.cpp @@ -0,0 +1,7 @@ +void MipsPassConfig::addPreEmitPass() { + addPass(createMipsExpandPseudoPass()); + addPass(createMicroMipsSizeReducePass()); + addPass(createMipsDelaySlotFillerPass()); + addPass(createMipsBranchExpansion()); + addPass(createMipsConstantIslandPass()); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/TargetMachine/getFrameLowering.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/TargetMachine/getFrameLowering.cpp new file mode 100644 index 0000000000000000000000000000000000000000..46facc9d53d8ed20463a68f1486618473e216322 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/TargetMachine/getFrameLowering.cpp @@ -0,0 +1,3 @@ +const TargetFrameLowering *getFrameLowering() const override { + return FrameLowering.get(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/TargetMachine/getInstrInfo.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/TargetMachine/getInstrInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e800e2a8b4f1864f21678597f1942ae03a8a6ab2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/TargetMachine/getInstrInfo.cpp @@ -0,0 +1,3 @@ +const MipsInstrInfo *getInstrInfo() const override { + return InstrInfo.get(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/TargetMachine/getRegisterInfo.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/TargetMachine/getRegisterInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..70e4b467269f9a62a119d78ba8756d15153967e2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/TargetMachine/getRegisterInfo.cpp @@ -0,0 +1,3 @@ +const MipsRegisterInfo *getRegisterInfo() const override { + return &InstrInfo->getRegisterInfo(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/TargetMachine/getSelectionDAGInfo.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/TargetMachine/getSelectionDAGInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d9cec09b2f3127f3d36917798ff8d808237620f9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/TargetMachine/getSelectionDAGInfo.cpp @@ -0,0 +1,3 @@ +const SelectionDAGTargetInfo *getSelectionDAGInfo() const override { + return &TSInfo; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/TargetMachine/getSubtargetImpl.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/TargetMachine/getSubtargetImpl.cpp new file mode 100644 index 0000000000000000000000000000000000000000..72a6aa9b0b63f9e9fcc02d673c5a32c466330d21 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/TargetMachine/getSubtargetImpl.cpp @@ -0,0 +1,27 @@ +const MipsSubtarget *MipsTargetMachine::getSubtargetImpl(const Function &F) const { + Attribute CPUAttr = F.getFnAttribute("target-cpu"); + Attribute FSAttr = F.getFnAttribute("target-features"); + std::string CPU = CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU; + std::string FS = FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS; + bool hasMips16Attr = F.getFnAttribute("mips16").isValid(); + bool hasNoMips16Attr = F.getFnAttribute("nomips16").isValid(); + bool HasMicroMipsAttr = F.getFnAttribute("micromips").isValid(); + bool HasNoMicroMipsAttr = F.getFnAttribute("nomicromips").isValid(); + bool softFloat = F.hasFnAttribute("use-soft-float") && F.getFnAttribute("use-soft-float").getValueAsString() == "true"; + if (hasMips16Attr) + FS += FS.empty() ? "+mips16" : ",+mips16"; + else if (hasNoMips16Attr) + FS += FS.empty() ? "-mips16" : ",-mips16"; + if (HasMicroMipsAttr) + FS += FS.empty() ? "+micromips" : ",+micromips"; + else if (HasNoMicroMipsAttr) + FS += FS.empty() ? "-micromips" : ",-micromips"; + if (softFloat) + FS += FS.empty() ? "+soft-float" : ",+soft-float"; + auto &I = SubtargetMap[CPU + FS]; + if (!I) { + resetTargetOptions(F); + I = std::make_unique(TargetTriple, CPU, FS, isLittle, *this, MaybeAlign(Options.StackAlignmentOverride)); + } + return I.get(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/TargetMachine/getTargetData.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/TargetMachine/getTargetData.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/TargetMachine/getTargetData.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/TargetMachine/getTargetLowering.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/TargetMachine/getTargetLowering.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f6a80a497f8d2bee84fc660d8e8cdfcfe7048369 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/TargetMachine/getTargetLowering.cpp @@ -0,0 +1,3 @@ +const MipsTargetLowering *getTargetLowering() const override { + return TLInfo.get(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/TargetObjectFile/Initialize.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/TargetObjectFile/Initialize.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a0d8533856448921babe3c7b5cab65e7ceeebca3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/TargetObjectFile/Initialize.cpp @@ -0,0 +1,6 @@ +void MipsTargetObjectFile::Initialize(MCContext &Ctx, const TargetMachine &TM){ + TargetLoweringObjectFileELF::Initialize(Ctx, TM); + SmallDataSection = getContext().getELFSection(".sdata", ELF::SHT_PROGBITS, ELF::SHF_WRITE | ELF::SHF_ALLOC | ELF::SHF_MIPS_GPREL); + SmallBSSSection = getContext().getELFSection(".sbss", ELF::SHT_NOBITS, ELF::SHF_WRITE | ELF::SHF_ALLOC | ELF::SHF_MIPS_GPREL); + this->TM = &static_cast(TM); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/TargetObjectFile/SelectSectionForGlobal.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/TargetObjectFile/SelectSectionForGlobal.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bcb179748f251dd885c72ec65ea012aa51523e27 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/TargetObjectFile/SelectSectionForGlobal.cpp @@ -0,0 +1,12 @@ +MCSection *MipsTargetObjectFile::SelectSectionForGlobal(const GlobalObject *GO, SectionKind Kind, const TargetMachine &TM) const { + if (Kind.isBSS() && IsGlobalInSmallSection(GO, TM, Kind)) { + return SmallBSSSection; + } + if (Kind.isData() && IsGlobalInSmallSection(GO, TM, Kind)) { + return SmallDataSection; + } + if (Kind.isReadOnly() && IsGlobalInSmallSection(GO, TM, Kind)) { + return SmallDataSection; + } + return TargetLoweringObjectFileELF::SelectSectionForGlobal(GO, Kind, TM); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/TargetObjectFile/getExplicitSectionGlobal.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/TargetObjectFile/getExplicitSectionGlobal.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/TargetObjectFile/getExplicitSectionGlobal.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/TargetObjectFile/getSectionForConstant.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/TargetObjectFile/getSectionForConstant.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2aa9fc13963d18be314c20bb620b4fea6a394505 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Scheduling/TargetObjectFile/getSectionForConstant.cpp @@ -0,0 +1,5 @@ +MCSection *MipsTargetObjectFile::getSectionForConstant(const DataLayout &DL, SectionKind Kind, const Constant *C, Align &Alignment) const { + if (IsConstantInSmallSection(DL, C, *TM)) + return SmallDataSection; + return TargetLoweringObjectFileELF::getSectionForConstant(DL, Kind, C, Alignment); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/FrameLowering/FrameLowering.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/FrameLowering/FrameLowering.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b384d32685bad5866f04b66f1bea348030208c0d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/FrameLowering/FrameLowering.cpp @@ -0,0 +1,2 @@ +explicit MipsFrameLowering(const MipsSubtarget &sti, Align Alignment) : TargetFrameLowering(StackGrowsDown, Alignment, 0, Alignment), STI(sti) { +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/FrameLowering/emitEpilogue.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/FrameLowering/emitEpilogue.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fecd648fee2494cb011a5cd242be9efbd0d7efe2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/FrameLowering/emitEpilogue.cpp @@ -0,0 +1,35 @@ +void MipsSEFrameLowering::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { + MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator(); + MachineFrameInfo &MFI = MF.getFrameInfo(); + MipsFunctionInfo *MipsFI = MF.getInfo(); + const MipsSEInstrInfo &TII = *static_cast(STI.getInstrInfo()); + const MipsRegisterInfo &RegInfo = *static_cast(STI.getRegisterInfo()); + DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); + MipsABIInfo ABI = STI.getABI(); + unsigned SP = ABI.GetStackPtr(); + unsigned FP = ABI.GetFramePtr(); + unsigned ZERO = ABI.GetNullPtr(); + unsigned MOVE = ABI.GetGPRMoveOp(); + if (hasFP(MF)) { + MachineBasicBlock::iterator I = MBBI; + for (unsigned i = 0; i < MFI.getCalleeSavedInfo().size(); ++i) + --I; + BuildMI(MBB, I, DL, TII.get(MOVE), SP).addReg(FP).addReg(ZERO); + } + if (MipsFI->callsEhReturn()) { + const TargetRegisterClass *RC = ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; + MachineBasicBlock::iterator I = MBBI; + for (unsigned i = 0; i < MFI.getCalleeSavedInfo().size(); ++i) + --I; + for (int J = 0; J < 4; ++J) { + TII.loadRegFromStackSlot(MBB, I, ABI.GetEhDataReg(J), MipsFI->getEhDataRegFI(J), RC, &RegInfo); + } + } + if (MF.getFunction().hasFnAttribute("interrupt")) + emitInterruptEpilogueStub(MF, MBB); + uint64_t StackSize = MFI.getStackSize(); + if (!StackSize) + return; + TII.adjustStackPtr(SP, StackSize, MBB, MBBI); +} + diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/FrameLowering/emitPrologue.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/FrameLowering/emitPrologue.cpp new file mode 100644 index 0000000000000000000000000000000000000000..04cc5f5bac4d52157c1c5891a8c7a3810d0c6ef0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/FrameLowering/emitPrologue.cpp @@ -0,0 +1,88 @@ +void MipsSEFrameLowering::emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const { + MachineFrameInfo &MFI = MF.getFrameInfo(); + MipsFunctionInfo *MipsFI = MF.getInfo(); + const MipsSEInstrInfo &TII = *static_cast(STI.getInstrInfo()); + const MipsRegisterInfo &RegInfo = *static_cast(STI.getRegisterInfo()); + MachineBasicBlock::iterator MBBI = MBB.begin(); + DebugLoc dl; + MipsABIInfo ABI = STI.getABI(); + unsigned SP = ABI.GetStackPtr(); + unsigned FP = ABI.GetFramePtr(); + unsigned ZERO = ABI.GetNullPtr(); + unsigned MOVE = ABI.GetGPRMoveOp(); + unsigned ADDiu = ABI.GetPtrAddiuOp(); + unsigned AND = ABI.IsN64() ? Mips::AND64 : Mips::AND; + const TargetRegisterClass *RC = ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; + uint64_t StackSize = MFI.getStackSize(); + if (StackSize == 0 && !MFI.adjustsStack()) + return; + MachineModuleInfo &MMI = MF.getMMI(); + const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); + TII.adjustStackPtr(SP, -StackSize, MBB, MBBI); + unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, StackSize)); + BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)).addCFIIndex(CFIIndex); + if (MF.getFunction().hasFnAttribute("interrupt")) + emitInterruptPrologueStub(MF, MBB); + const std::vector &CSI = MFI.getCalleeSavedInfo(); + if (!CSI.empty()) { + for (unsigned i = 0; i < CSI.size(); ++i) + ++MBBI; + for (std::vector::const_iterator I = CSI.begin(), E = CSI.end(); I != E; ++I) { + int64_t Offset = MFI.getObjectOffset(I->getFrameIdx()); + unsigned Reg = I->getReg(); + if (Mips::AFGR64RegClass.contains(Reg)) { + unsigned Reg0 = MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_lo), true); + unsigned Reg1 = MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_hi), true); + if (!STI.isLittle()) + std::swap(Reg0, Reg1); + unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(nullptr, Reg0, Offset)); + BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)).addCFIIndex(CFIIndex); + CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4)); + BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)).addCFIIndex(CFIIndex); + } + else if (Mips::FGR64RegClass.contains(Reg)) { + unsigned Reg0 = MRI->getDwarfRegNum(Reg, true); + unsigned Reg1 = MRI->getDwarfRegNum(Reg, true) + 1; + if (!STI.isLittle()) + std::swap(Reg0, Reg1); + unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(nullptr, Reg0, Offset)); + BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)).addCFIIndex(CFIIndex); + CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4)); + BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)).addCFIIndex(CFIIndex); + } + else { + unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(nullptr, MRI->getDwarfRegNum(Reg, true), Offset)); + BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)).addCFIIndex(CFIIndex); + } + } + } + if (MipsFI->callsEhReturn()) { + for (int I = 0; I < 4; ++I) { + if (!MBB.isLiveIn(ABI.GetEhDataReg(I))) + MBB.addLiveIn(ABI.GetEhDataReg(I)); + TII.storeRegToStackSlot(MBB, MBBI, ABI.GetEhDataReg(I), false, MipsFI->getEhDataRegFI(I), RC, &RegInfo); + } + for (int I = 0; I < 4; ++I) { + int64_t Offset = MFI.getObjectOffset(MipsFI->getEhDataRegFI(I)); + unsigned Reg = MRI->getDwarfRegNum(ABI.GetEhDataReg(I), true); + unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(nullptr, Reg, Offset)); + BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)).addCFIIndex(CFIIndex); + } + } + if (hasFP(MF)) { + BuildMI(MBB, MBBI, dl, TII.get(MOVE), FP).addReg(SP).addReg(ZERO).setMIFlag(MachineInstr::FrameSetup); + unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfaRegister( nullptr, MRI->getDwarfRegNum(FP, true))); + BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)).addCFIIndex(CFIIndex); + if (RegInfo.needsStackRealignment(MF)) { + Register VR = MF.getRegInfo().createVirtualRegister(RC); + assert((Log2(MFI.getMaxAlign()) < 16) && "Function's alignment size requirement is not supported."); + int64_t MaxAlign = -(int64_t)MFI.getMaxAlign().value(); + BuildMI(MBB, MBBI, dl, TII.get(ADDiu), VR).addReg(ZERO).addImm(MaxAlign); + BuildMI(MBB, MBBI, dl, TII.get(AND), SP).addReg(SP).addReg(VR); + if (hasBP(MF)) { + unsigned BP = STI.isABI_N64() ? Mips::S7_64 : Mips::S7; + BuildMI(MBB, MBBI, dl, TII.get(MOVE), BP).addReg(SP).addReg(ZERO); + } + } + } +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/FrameLowering/hasFP.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/FrameLowering/hasFP.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2984a24fb87e41d561111fe745a031a4ae00d2f8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/FrameLowering/hasFP.cpp @@ -0,0 +1,5 @@ +bool MipsFrameLowering::hasFP(const MachineFunction &MF) const { + const MachineFrameInfo &MFI = MF.getFrameInfo(); + const TargetRegisterInfo *TRI = STI.getRegisterInfo(); + return MF.getTarget().Options.DisableFramePointerElim(MF) || MFI.hasVarSizedObjects() || MFI.isFrameAddressTaken() || TRI->needsStackRealignment(MF); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/FrameLowering/isShrinkWrappingProfitable.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/FrameLowering/isShrinkWrappingProfitable.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/FrameLowering/isShrinkWrappingProfitable.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/FrameLowering/processFunctionBeforeCalleeSavedScan.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/FrameLowering/processFunctionBeforeCalleeSavedScan.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/FrameLowering/processFunctionBeforeCalleeSavedScan.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/FrameLowering/processFunctionBeforeFrameFinalized.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/FrameLowering/processFunctionBeforeFrameFinalized.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/FrameLowering/processFunctionBeforeFrameFinalized.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/FrameLowering/restoreCalleeSavedRegisters.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/FrameLowering/restoreCalleeSavedRegisters.cpp new file mode 100644 index 0000000000000000000000000000000000000000..39a52f6a3ffb6bddaec5669406257eaaf8382c20 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/FrameLowering/restoreCalleeSavedRegisters.cpp @@ -0,0 +1,3 @@ +bool Mips16FrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, MutableArrayRef CSI, const TargetRegisterInfo *TRI) const { + return true; +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/FrameLowering/spillCalleeSavedRegisters.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/FrameLowering/spillCalleeSavedRegisters.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d7ccdfa1edf7514e9f46b468c4a170614877a6c7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/FrameLowering/spillCalleeSavedRegisters.cpp @@ -0,0 +1,29 @@ +bool MipsSEFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef CSI, const TargetRegisterInfo *TRI) const { + MachineFunction *MF = MBB.getParent(); + const TargetInstrInfo &TII = *STI.getInstrInfo(); + for (unsigned i = 0, e = CSI.size(); i != e; ++i) { + unsigned Reg = CSI[i].getReg(); + bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA || Reg == Mips::RA_64) && MF->getFrameInfo().isReturnAddressTaken(); + if (!IsRAAndRetAddrIsTaken) + MBB.addLiveIn(Reg); + bool IsLOHI = (Reg == Mips::LO0 || Reg == Mips::LO0_64 || Reg == Mips::HI0 || Reg == Mips::HI0_64); + const Function &Func = MBB.getParent()->getFunction(); + if (IsLOHI && Func.hasFnAttribute("interrupt")) { + DebugLoc DL = MI->getDebugLoc(); + unsigned Op = 0; + if (!STI.getABI().ArePtrs64bit()) { + Op = (Reg == Mips::HI0) ? Mips::MFHI : Mips::MFLO; + Reg = Mips::K0; + } + else { + Op = (Reg == Mips::HI0) ? Mips::MFHI64 : Mips::MFLO64; + Reg = Mips::K0_64; + } + BuildMI(MBB, MI, DL, TII.get(Op), Mips::K0).setMIFlag(MachineInstr::FrameSetup); + } + bool IsKill = !IsRAAndRetAddrIsTaken; + const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); + TII.storeRegToStackSlot(MBB, MI, Reg, IsKill, CSI[i].getFrameIdx(), RC, TRI); + } + return true; +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/FrameLowering/stackSlotSize.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/FrameLowering/stackSlotSize.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/FrameLowering/stackSlotSize.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelDAGToDAG/DAGToDAGISel.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelDAGToDAG/DAGToDAGISel.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5a7fcbbf66a18053cbb09eb170938804acb78987 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelDAGToDAG/DAGToDAGISel.cpp @@ -0,0 +1,2 @@ +explicit MipsSEDAGToDAGISel(MipsTargetMachine &TM, CodeGenOpt::Level OL) : MipsDAGToDAGISel(TM, OL) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelDAGToDAG/Select.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelDAGToDAG/Select.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelDAGToDAG/Select.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelDAGToDAG/SelectADDRcpii.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelDAGToDAG/SelectADDRcpii.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelDAGToDAG/SelectADDRcpii.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelDAGToDAG/SelectADDRdpii.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelDAGToDAG/SelectADDRdpii.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelDAGToDAG/SelectADDRdpii.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelDAGToDAG/SelectADDRspii.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelDAGToDAG/SelectADDRspii.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelDAGToDAG/SelectADDRspii.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelDAGToDAG/SelectInlineAsmMemoryOperand.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelDAGToDAG/SelectInlineAsmMemoryOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d342f74eef8e6835cb6a33677db55fb78cb5d785 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelDAGToDAG/SelectInlineAsmMemoryOperand.cpp @@ -0,0 +1,50 @@ +bool MipsSEDAGToDAGISel::SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, std::vector &OutOps) { + SDValue Base, Offset; + switch(ConstraintID) { + default: + llvm_unreachable("Unexpected asm memory constraint"); + case InlineAsm::Constraint_m: + case InlineAsm::Constraint_o: + if (selectAddrRegImm16(Op, Base, Offset)) { + OutOps.push_back(Base); + OutOps.push_back(Offset); + return false; + } + OutOps.push_back(Op); + OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32)); + return false; + case InlineAsm::Constraint_R: + if (selectAddrRegImm9(Op, Base, Offset)) { + OutOps.push_back(Base); + OutOps.push_back(Offset); + return false; + } + OutOps.push_back(Op); + OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32)); + return false; + case InlineAsm::Constraint_ZC: + if (Subtarget->inMicroMipsMode()) { + if (selectAddrRegImm12(Op, Base, Offset)) { + OutOps.push_back(Base); + OutOps.push_back(Offset); + return false; + } + } + else if (Subtarget->hasMips32r6()) { + if (selectAddrRegImm9(Op, Base, Offset)) { + OutOps.push_back(Base); + OutOps.push_back(Offset); + return false; + } + } + else if (selectAddrRegImm16(Op, Base, Offset)) { + OutOps.push_back(Base); + OutOps.push_back(Offset); + return false; + } + OutOps.push_back(Op); + OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32)); + return false; + } + return true; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelDAGToDAG/createISelDag.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelDAGToDAG/createISelDag.cpp new file mode 100644 index 0000000000000000000000000000000000000000..36e8855eb544200582451f8c21a565df6b7b9a48 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelDAGToDAG/createISelDag.cpp @@ -0,0 +1,3 @@ +FunctionPass *llvm::createMipsSEISelDag(MipsTargetMachine &TM, CodeGenOpt::Level OptLevel) { + return new MipsSEDAGToDAGISel(TM, OptLevel); +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelDAGToDAG/getI32Imm.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelDAGToDAG/getI32Imm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelDAGToDAG/getI32Imm.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelDAGToDAG/getPassName.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelDAGToDAG/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5049e898a5b33a064ed6484e2e7cf1667997bef8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelDAGToDAG/getPassName.cpp @@ -0,0 +1,3 @@ +StringRef getPassName() const override { + return "MIPS DAG->DAG Pattern Instruction Selection"; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelDAGToDAG/immBitp.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelDAGToDAG/immBitp.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelDAGToDAG/immBitp.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelDAGToDAG/immMskBitp.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelDAGToDAG/immMskBitp.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelDAGToDAG/immMskBitp.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/CanLowerReturn.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/CanLowerReturn.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e857257cc58f086519f5aa8fb47b84c794ac83d0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/CanLowerReturn.cpp @@ -0,0 +1,5 @@ +bool MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg, const SmallVectorImpl &Outs, LLVMContext &Context) const { + SmallVector RVLocs; + MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context); + return CCInfo.CheckReturn(Outs, RetCC_Mips); +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/EmitInstrWithCustomInserter.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/EmitInstrWithCustomInserter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c7a577133ff50ac6ce86af208c82aec90f270744 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/EmitInstrWithCustomInserter.cpp @@ -0,0 +1,154 @@ +MachineBasicBlock *MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const { + switch (MI.getOpcode()) { + default: + llvm_unreachable("Unexpected instr type to insert"); + case Mips::ATOMIC_LOAD_ADD_I8: + return emitAtomicBinaryPartword(MI, BB, 1); + case Mips::ATOMIC_LOAD_ADD_I16: + return emitAtomicBinaryPartword(MI, BB, 2); + case Mips::ATOMIC_LOAD_ADD_I32: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_LOAD_ADD_I64: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_LOAD_AND_I8: + return emitAtomicBinaryPartword(MI, BB, 1); + case Mips::ATOMIC_LOAD_AND_I16: + return emitAtomicBinaryPartword(MI, BB, 2); + case Mips::ATOMIC_LOAD_AND_I32: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_LOAD_AND_I64: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_LOAD_OR_I8: + return emitAtomicBinaryPartword(MI, BB, 1); + case Mips::ATOMIC_LOAD_OR_I16: + return emitAtomicBinaryPartword(MI, BB, 2); + case Mips::ATOMIC_LOAD_OR_I32: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_LOAD_OR_I64: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_LOAD_XOR_I8: + return emitAtomicBinaryPartword(MI, BB, 1); + case Mips::ATOMIC_LOAD_XOR_I16: + return emitAtomicBinaryPartword(MI, BB, 2); + case Mips::ATOMIC_LOAD_XOR_I32: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_LOAD_XOR_I64: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_LOAD_NAND_I8: + return emitAtomicBinaryPartword(MI, BB, 1); + case Mips::ATOMIC_LOAD_NAND_I16: + return emitAtomicBinaryPartword(MI, BB, 2); + case Mips::ATOMIC_LOAD_NAND_I32: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_LOAD_NAND_I64: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_LOAD_SUB_I8: + return emitAtomicBinaryPartword(MI, BB, 1); + case Mips::ATOMIC_LOAD_SUB_I16: + return emitAtomicBinaryPartword(MI, BB, 2); + case Mips::ATOMIC_LOAD_SUB_I32: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_LOAD_SUB_I64: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_SWAP_I8: + return emitAtomicBinaryPartword(MI, BB, 1); + case Mips::ATOMIC_SWAP_I16: + return emitAtomicBinaryPartword(MI, BB, 2); + case Mips::ATOMIC_SWAP_I32: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_SWAP_I64: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_CMP_SWAP_I8: + return emitAtomicCmpSwapPartword(MI, BB, 1); + case Mips::ATOMIC_CMP_SWAP_I16: + return emitAtomicCmpSwapPartword(MI, BB, 2); + case Mips::ATOMIC_CMP_SWAP_I32: + return emitAtomicCmpSwap(MI, BB); + case Mips::ATOMIC_CMP_SWAP_I64: + return emitAtomicCmpSwap(MI, BB); + case Mips::ATOMIC_LOAD_MIN_I8: + return emitAtomicBinaryPartword(MI, BB, 1); + case Mips::ATOMIC_LOAD_MIN_I16: + return emitAtomicBinaryPartword(MI, BB, 2); + case Mips::ATOMIC_LOAD_MIN_I32: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_LOAD_MIN_I64: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_LOAD_MAX_I8: + return emitAtomicBinaryPartword(MI, BB, 1); + case Mips::ATOMIC_LOAD_MAX_I16: + return emitAtomicBinaryPartword(MI, BB, 2); + case Mips::ATOMIC_LOAD_MAX_I32: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_LOAD_MAX_I64: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_LOAD_UMIN_I8: + return emitAtomicBinaryPartword(MI, BB, 1); + case Mips::ATOMIC_LOAD_UMIN_I16: + return emitAtomicBinaryPartword(MI, BB, 2); + case Mips::ATOMIC_LOAD_UMIN_I32: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_LOAD_UMIN_I64: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_LOAD_UMAX_I8: + return emitAtomicBinaryPartword(MI, BB, 1); + case Mips::ATOMIC_LOAD_UMAX_I16: + return emitAtomicBinaryPartword(MI, BB, 2); + case Mips::ATOMIC_LOAD_UMAX_I32: + return emitAtomicBinary(MI, BB); + case Mips::ATOMIC_LOAD_UMAX_I64: + return emitAtomicBinary(MI, BB); + case Mips::PseudoSDIV: + case Mips::PseudoUDIV: + case Mips::DIV: + case Mips::DIVU: + case Mips::MOD: + case Mips::MODU: + return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, false); + case Mips::SDIV_MM_Pseudo: + case Mips::UDIV_MM_Pseudo: + case Mips::SDIV_MM: + case Mips::UDIV_MM: + case Mips::DIV_MMR6: + case Mips::DIVU_MMR6: + case Mips::MOD_MMR6: + case Mips::MODU_MMR6: + return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, true); + case Mips::PseudoDSDIV: + case Mips::PseudoDUDIV: + case Mips::DDIV: + case Mips::DDIVU: + case Mips::DMOD: + case Mips::DMODU: + return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, false); + case Mips::PseudoSELECT_I: + case Mips::PseudoSELECT_I64: + case Mips::PseudoSELECT_S: + case Mips::PseudoSELECT_D32: + case Mips::PseudoSELECT_D64: + return emitPseudoSELECT(MI, BB, false, Mips::BNE); + case Mips::PseudoSELECTFP_F_I: + case Mips::PseudoSELECTFP_F_I64: + case Mips::PseudoSELECTFP_F_S: + case Mips::PseudoSELECTFP_F_D32: + case Mips::PseudoSELECTFP_F_D64: + return emitPseudoSELECT(MI, BB, true, Mips::BC1F); + case Mips::PseudoSELECTFP_T_I: + case Mips::PseudoSELECTFP_T_I64: + case Mips::PseudoSELECTFP_T_S: + case Mips::PseudoSELECTFP_T_D32: + case Mips::PseudoSELECTFP_T_D64: + return emitPseudoSELECT(MI, BB, true, Mips::BC1T); + case Mips::PseudoD_SELECT_I: + case Mips::PseudoD_SELECT_I64: + return emitPseudoD_SELECT(MI, BB); + case Mips::LDR_W: + return emitLDR_W(MI, BB); + case Mips::LDR_D: + return emitLDR_D(MI, BB); + case Mips::STR_W: + return emitSTR_W(MI, BB); + case Mips::STR_D: + return emitSTR_D(MI, BB); + } +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/ExpandADDSUB.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/ExpandADDSUB.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/ExpandADDSUB.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerADJUST_TRAMPOLINE.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerADJUST_TRAMPOLINE.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerADJUST_TRAMPOLINE.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerATOMIC_FENCE.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerATOMIC_FENCE.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e049555ac68c4ab9cbf7331380a481c26d01c38c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerATOMIC_FENCE.cpp @@ -0,0 +1,5 @@ +SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const { + unsigned SType = 0; + SDLoc DL(Op); + return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0), DAG.getConstant(SType, DL, MVT::i32)); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerBR_JT.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerBR_JT.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerBR_JT.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerBlockAddress.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerBlockAddress.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d79eabbd2efdb54089e2201050b3419e772ee8a8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerBlockAddress.cpp @@ -0,0 +1,7 @@ +SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const { + BlockAddressSDNode *N = cast(Op); + EVT Ty = Op.getValueType(); + if (!isPositionIndependent()) + return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); + return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerCall.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerCall.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e452e8db8b1f84d438f35752f0c4f697f1ca6bd3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerCall.cpp @@ -0,0 +1,194 @@ +SDValue MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl &InVals) const { + SelectionDAG &DAG = CLI.DAG; + SDLoc DL = CLI.DL; + SmallVectorImpl &Outs = CLI.Outs; + SmallVectorImpl &OutVals = CLI.OutVals; + SmallVectorImpl &Ins = CLI.Ins; + SDValue Chain = CLI.Chain; + SDValue Callee = CLI.Callee; + bool &IsTailCall = CLI.IsTailCall; + CallingConv::ID CallConv = CLI.CallConv; + bool IsVarArg = CLI.IsVarArg; + MachineFunction &MF = DAG.getMachineFunction(); + MachineFrameInfo &MFI = MF.getFrameInfo(); + const TargetFrameLowering *TFL = Subtarget.getFrameLowering(); + MipsFunctionInfo *FuncInfo = MF.getInfo(); + bool IsPIC = isPositionIndependent(); + SmallVector ArgLocs; + MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext(), MipsCCState::getSpecialCallingConvForCallee(Callee.getNode(), Subtarget)); + const ExternalSymbolSDNode *ES = dyn_cast_or_null(Callee.getNode()); + bool MemcpyInByVal = ES && StringRef(ES->getSymbol()) == StringRef("memcpy") && CallConv != CallingConv::Fast && Chain.getOpcode() == ISD::CALLSEQ_START; + unsigned ReservedArgArea = MemcpyInByVal ? 0 : ABI.GetCalleeAllocdArgSizeInBytes(CallConv); + CCInfo.AllocateStack(ReservedArgArea, Align(1)); + CCInfo.AnalyzeCallOperands(Outs, CC_Mips, CLI.getArgs(), ES ? ES->getSymbol() : nullptr); + unsigned NextStackOffset = CCInfo.getNextStackOffset(); + MachineFunction::CallSiteInfo CSInfo; + bool InternalLinkage = false; + if (IsTailCall) { + IsTailCall = isEligibleForTailCallOptimization(CCInfo, NextStackOffset, *MF.getInfo()); + if (GlobalAddressSDNode *G = dyn_cast(Callee)) { + InternalLinkage = G->getGlobal()->hasInternalLinkage(); + IsTailCall &= (InternalLinkage || G->getGlobal()->hasLocalLinkage() || G->getGlobal()->hasPrivateLinkage() || G->getGlobal()->hasHiddenVisibility() || G->getGlobal()->hasProtectedVisibility()); + } + } + if (!IsTailCall && CLI.CB && CLI.CB->isMustTailCall()) + report_fatal_error("failed to perform tail call elimination on a call site marked musttail"); + if (IsTailCall) + ++NumTailCalls; + unsigned StackAlignment = TFL->getStackAlignment(); + NextStackOffset = alignTo(NextStackOffset, StackAlignment); + SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, DL, true); + if (!(IsTailCall || MemcpyInByVal)) + Chain = DAG.getCALLSEQ_START(Chain, NextStackOffset, 0, DL); + SDValue StackPtr = DAG.getCopyFromReg(Chain, DL, ABI.IsN64() ? Mips::SP_64 : Mips::SP, getPointerTy(DAG.getDataLayout())); + std::deque> RegsToPass; + SmallVector MemOpChains; + CCInfo.rewindByValRegsInfo(); + for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { + SDValue Arg = OutVals[i]; + CCValAssign &VA = ArgLocs[i]; + MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT(); + ISD::ArgFlagsTy Flags = Outs[i].Flags; + bool UseUpperBits = false; + if (Flags.isByVal()) { + unsigned FirstByValReg, LastByValReg; + unsigned ByValIdx = CCInfo.getInRegsParamsProcessed(); + CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg); + assert(Flags.getByValSize() && "ByVal args of size 0 should have been ignored by front-end."); + assert(ByValIdx < CCInfo.getInRegsParamsCount()); + assert(!IsTailCall && "Do not tail-call optimize if there is a byval argument."); + passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg, FirstByValReg, LastByValReg, Flags, Subtarget.isLittle(), VA); + CCInfo.nextInRegsParam(); + continue; + } + switch (VA.getLocInfo()) { + default: + llvm_unreachable("Unknown loc info!"); + case CCValAssign::Full: + if (VA.isRegLoc()) { + if ((ValVT == MVT::f32 && LocVT == MVT::i32) || (ValVT == MVT::f64 && LocVT == MVT::i64) || (ValVT == MVT::i64 && LocVT == MVT::f64)) + Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg); + else if (ValVT == MVT::f64 && LocVT == MVT::i32) { + SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Arg, DAG.getConstant(0, DL, MVT::i32)); + SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Arg, DAG.getConstant(1, DL, MVT::i32)); + if (!Subtarget.isLittle()) + std::swap(Lo, Hi); + Register LocRegLo = VA.getLocReg(); + unsigned LocRegHigh = getNextIntArgReg(LocRegLo); + RegsToPass.push_back(std::make_pair(LocRegLo, Lo)); + RegsToPass.push_back(std::make_pair(LocRegHigh, Hi)); + continue; + } + } + break; + case CCValAssign::BCvt: + Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg); + break; + case CCValAssign::SExtUpper: + UseUpperBits = true; + LLVM_FALLTHROUGH; + case CCValAssign::SExt: + Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg); + break; + case CCValAssign::ZExtUpper: + UseUpperBits = true; + LLVM_FALLTHROUGH; + case CCValAssign::ZExt: + Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg); + break; + case CCValAssign::AExtUpper: + UseUpperBits = true; + LLVM_FALLTHROUGH; + case CCValAssign::AExt: + Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg); + break; + } + if (UseUpperBits) { + unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits(); + unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); + Arg = DAG.getNode(ISD::SHL, DL, VA.getLocVT(), Arg, DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); + } + if (VA.isRegLoc()) { + RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); + if (Mips::AFGR64RegClass.contains(VA.getLocReg())) + continue; + const TargetOptions &Options = DAG.getTarget().Options; + if (Options.SupportsDebugEntryValues) + CSInfo.emplace_back(VA.getLocReg(), i); + continue; + } + assert(VA.isMemLoc()); + MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(), Chain, Arg, DL, IsTailCall, DAG)); + } + if (!MemOpChains.empty()) + Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains); + EVT Ty = Callee.getValueType(); + bool GlobalOrExternal = false, IsCallReloc = false; + if (!Subtarget.isABICalls() && !IsPIC) { + if (auto *N = dyn_cast(Callee)) { + if (Subtarget.useLongCalls()) + Callee = Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); + } + else if (auto *N = dyn_cast(Callee)) { + bool UseLongCalls = Subtarget.useLongCalls(); + if (auto *F = dyn_cast(N->getGlobal())) { + if (F->hasFnAttribute("long-call")) + UseLongCalls = true; + else if (F->hasFnAttribute("short-call")) + UseLongCalls = false; + } + if (UseLongCalls) + Callee = Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); + } + } + if (GlobalAddressSDNode *G = dyn_cast(Callee)) { + if (IsPIC) { + const GlobalValue *Val = G->getGlobal(); + InternalLinkage = Val->hasInternalLinkage(); + if (InternalLinkage) + Callee = getAddrLocal(G, DL, Ty, DAG, ABI.IsN32() || ABI.IsN64()); + else if (Subtarget.useXGOT()) { + Callee = getAddrGlobalLargeGOT(G, DL, Ty, DAG, MipsII::MO_CALL_HI16, MipsII::MO_CALL_LO16, Chain, FuncInfo->callPtrInfo(MF, Val)); + IsCallReloc = true; + } + else { + Callee = getAddrGlobal(G, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain, FuncInfo->callPtrInfo(MF, Val)); + IsCallReloc = true; + } + } + else + Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, getPointerTy(DAG.getDataLayout()), 0, MipsII::MO_NO_FLAG); + GlobalOrExternal = true; + } + else if (ExternalSymbolSDNode *S = dyn_cast(Callee)) { + const char *Sym = S->getSymbol(); + if (!IsPIC) + Callee = DAG.getTargetExternalSymbol( Sym, getPointerTy(DAG.getDataLayout()), MipsII::MO_NO_FLAG); + else if (Subtarget.useXGOT()) { + Callee = getAddrGlobalLargeGOT(S, DL, Ty, DAG, MipsII::MO_CALL_HI16, MipsII::MO_CALL_LO16, Chain, FuncInfo->callPtrInfo(MF, Sym)); + IsCallReloc = true; + } + else { + Callee = getAddrGlobal(S, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain, FuncInfo->callPtrInfo(MF, Sym)); + IsCallReloc = true; + } + GlobalOrExternal = true; + } + SmallVector Ops(1, Chain); + SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); + getOpndList(Ops, RegsToPass, IsPIC, GlobalOrExternal, InternalLinkage, IsCallReloc, CLI, Callee, Chain); + if (IsTailCall) { + MF.getFrameInfo().setHasTailCall(); + SDValue Ret = DAG.getNode(MipsISD::TailCall, DL, MVT::Other, Ops); + DAG.addCallSiteInfo(Ret.getNode(), std::move(CSInfo)); + return Ret; + } + Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, Ops); + SDValue InFlag = Chain.getValue(1); + DAG.addCallSiteInfo(Chain.getNode(), std::move(CSInfo)); + if (!(MemcpyInByVal)) { + Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal, DAG.getIntPtrConstant(0, DL, true), InFlag, DL); + InFlag = Chain.getValue(1); + } + return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG, InVals, CLI); +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerConstantPool.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerConstantPool.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0a118c8fea23e323e770a810738ac56de09cca15 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerConstantPool.cpp @@ -0,0 +1,11 @@ +SDValue MipsTargetLowering::lowerConstantPool(SDValue Op, SelectionDAG &DAG) const { + ConstantPoolSDNode *N = cast(Op); + EVT Ty = Op.getValueType(); + if (!isPositionIndependent()) { + const MipsTargetObjectFile *TLOF = static_cast(getTargetMachine().getObjFileLowering()); + if (TLOF->IsConstantInSmallSection(DAG.getDataLayout(), N->getConstVal(), getTargetMachine())) + return getAddrGPRel(N, SDLoc(N), Ty, DAG, ABI.IsN64()); + return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); + } + return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerDYNAMIC_STACKALLOC.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerDYNAMIC_STACKALLOC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerDYNAMIC_STACKALLOC.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerEH_RETURN.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerEH_RETURN.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d6013ed5fc72a71593c03726f9f0b8b50dd8f74e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerEH_RETURN.cpp @@ -0,0 +1,15 @@ +SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const { + MachineFunction &MF = DAG.getMachineFunction(); + MipsFunctionInfo *MipsFI = MF.getInfo(); + MipsFI->setCallsEhReturn(); + SDValue Chain = Op.getOperand(0); + SDValue Offset = Op.getOperand(1); + SDValue Handler = Op.getOperand(2); + SDLoc DL(Op); + EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32; + unsigned OffsetReg = ABI.IsN64() ? Mips::V1_64 : Mips::V1; + unsigned AddrReg = ABI.IsN64() ? Mips::V0_64 : Mips::V0; + Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue()); + Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1)); + return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain, DAG.getRegister(OffsetReg, Ty), DAG.getRegister(AddrReg, getPointerTy(MF.getDataLayout())), Chain.getValue(1)); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerFRAMEADDR.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerFRAMEADDR.cpp new file mode 100644 index 0000000000000000000000000000000000000000..55304c0e002c25426cac915e340d397c57564694 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerFRAMEADDR.cpp @@ -0,0 +1,12 @@ +SDValue MipsTargetLowering::lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { + if (cast(Op.getOperand(0))->getZExtValue() != 0) { + DAG.getContext()->emitError("return address can be determined only for current frame"); + return SDValue(); + } + MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); + MFI.setFrameAddressIsTaken(true); + EVT VT = Op.getValueType(); + SDLoc DL(Op); + SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), DL, ABI.IsN64() ? Mips::FP_64 : Mips::FP, VT); + return FrameAddr; +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerFRAME_TO_ARGS_OFFSET.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerFRAME_TO_ARGS_OFFSET.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerFRAME_TO_ARGS_OFFSET.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerFormalArguments.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerFormalArguments.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bbb9efff7eb46b474008aab70f4ce03c006a5618 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerFormalArguments.cpp @@ -0,0 +1,90 @@ +SDValue MipsTargetLowering::LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl &InVals) const { + MachineFunction &MF = DAG.getMachineFunction(); + MachineFrameInfo &MFI = MF.getFrameInfo(); + MipsFunctionInfo *MipsFI = MF.getInfo(); + MipsFI->setVarArgsFrameIndex(0); + std::vector OutChains; + SmallVector ArgLocs; + MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext()); + CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), Align(1)); + const Function &Func = DAG.getMachineFunction().getFunction(); + Function::const_arg_iterator FuncArg = Func.arg_begin(); + if (Func.hasFnAttribute("interrupt") && !Func.arg_empty()) + report_fatal_error("Functions with the interrupt attribute cannot have arguments!"); + CCInfo.AnalyzeFormalArguments(Ins, CC_Mips_FixedArg); + MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(), CCInfo.getInRegsParamsCount() > 0); + unsigned CurArgIdx = 0; + CCInfo.rewindByValRegsInfo(); + for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { + CCValAssign &VA = ArgLocs[i]; + if (Ins[i].isOrigArg()) { + std::advance(FuncArg, Ins[i].getOrigArgIndex() - CurArgIdx); + CurArgIdx = Ins[i].getOrigArgIndex(); + } + EVT ValVT = VA.getValVT(); + ISD::ArgFlagsTy Flags = Ins[i].Flags; + bool IsRegLoc = VA.isRegLoc(); + if (Flags.isByVal()) { + assert(Ins[i].isOrigArg() && "Byval arguments cannot be implicit"); + unsigned FirstByValReg, LastByValReg; + unsigned ByValIdx = CCInfo.getInRegsParamsProcessed(); + CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg); + assert(Flags.getByValSize() && "ByVal args of size 0 should have been ignored by front-end."); + assert(ByValIdx < CCInfo.getInRegsParamsCount()); + copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg, FirstByValReg, LastByValReg, VA, CCInfo); + CCInfo.nextInRegsParam(); + continue; + } + if (IsRegLoc) { + MVT RegVT = VA.getLocVT(); + Register ArgReg = VA.getLocReg(); + const TargetRegisterClass *RC = getRegClassFor(RegVT); + unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC); + SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); + ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG); + if ((RegVT == MVT::i32 && ValVT == MVT::f32) || (RegVT == MVT::i64 && ValVT == MVT::f64) || (RegVT == MVT::f64 && ValVT == MVT::i64)) + ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue); + else if (ABI.IsO32() && RegVT == MVT::i32 && ValVT == MVT::f64) { + unsigned Reg2 = addLiveIn(DAG.getMachineFunction(), getNextIntArgReg(ArgReg), RC); + SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT); + if (!Subtarget.isLittle()) + std::swap(ArgValue, ArgValue2); + ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, ArgValue, ArgValue2); + } + InVals.push_back(ArgValue); + } + else { + MVT LocVT = VA.getLocVT(); + if (ABI.IsO32()) { + if (VA.getValVT().isFloatingPoint() && !Subtarget.useSoftFloat()) + LocVT = VA.getValVT(); + } + assert(VA.isMemLoc()); + int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8, VA.getLocMemOffset(), true); + SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); + SDValue ArgValue = DAG.getLoad(LocVT, DL, Chain, FIN, MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI)); + OutChains.push_back(ArgValue.getValue(1)); + ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG); + InVals.push_back(ArgValue); + } + } + for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { + if (Ins[i].Flags.isSRet()) { + unsigned Reg = MipsFI->getSRetReturnReg(); + if (!Reg) { + Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(ABI.IsN64() ? MVT::i64 : MVT::i32)); + MipsFI->setSRetReturnReg(Reg); + } + SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[i]); + Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain); + break; + } + } + if (IsVarArg) + writeVarArgRegs(OutChains, Chain, DL, DAG, CCInfo); + if (!OutChains.empty()) { + OutChains.push_back(Chain); + Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains); + } + return Chain; +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerGlobalAddress.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerGlobalAddress.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3bc241861141aeaf0155e6e05b289a3c4232fdc8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerGlobalAddress.cpp @@ -0,0 +1,17 @@ +SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const { + EVT Ty = Op.getValueType(); + GlobalAddressSDNode *N = cast(Op); + const GlobalValue *GV = N->getGlobal(); + if (!isPositionIndependent()) { + const MipsTargetObjectFile *TLOF = static_cast(getTargetMachine().getObjFileLowering()); + const GlobalObject *GO = GV->getBaseObject(); + if (GO && TLOF->IsGlobalInSmallSection(GO, getTargetMachine())) + return getAddrGPRel(N, SDLoc(N), Ty, DAG, ABI.IsN64()); + return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); + } + if (GV->hasLocalLinkage()) + return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); + if (Subtarget.useXGOT()) + return getAddrGlobalLargeGOT(N, SDLoc(N), Ty, DAG, MipsII::MO_GOT_HI16, MipsII::MO_GOT_LO16, DAG.getEntryNode(), MachinePointerInfo::getGOT(DAG.getMachineFunction())); + return getAddrGlobal(N, SDLoc(N), Ty, DAG, (ABI.IsN32() || ABI.IsN64()) ? MipsII::MO_GOT_DISP : MipsII::MO_GOT, DAG.getEntryNode(), MachinePointerInfo::getGOT(DAG.getMachineFunction())); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerGlobalTLSAddress.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerGlobalTLSAddress.cpp new file mode 100644 index 0000000000000000000000000000000000000000..40d4302abbe9ff053b9574dac4d63cd2fbc144cf --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerGlobalTLSAddress.cpp @@ -0,0 +1,50 @@ +SDValue MipsTargetLowering::lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { + GlobalAddressSDNode *GA = cast(Op); + if (DAG.getTarget().useEmulatedTLS()) + return LowerToTLSEmulatedModel(GA, DAG); + SDLoc DL(GA); + const GlobalValue *GV = GA->getGlobal(); + EVT PtrVT = getPointerTy(DAG.getDataLayout()); + TLSModel::Model model = getTargetMachine().getTLSModel(GV); + if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) { + unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM : MipsII::MO_TLSGD; + SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, Flag); + SDValue Argument = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT), TGA); + unsigned PtrSize = PtrVT.getSizeInBits(); + IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize); + SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT); + ArgListTy Args; + ArgListEntry Entry; + Entry.Node = Argument; + Entry.Ty = PtrTy; + Args.push_back(Entry); + TargetLowering::CallLoweringInfo CLI(DAG); + CLI.setDebugLoc(DL).setChain(DAG.getEntryNode()).setLibCallee(CallingConv::C, PtrTy, TlsGetAddr, std::move(Args)); + std::pair CallResult = LowerCallTo(CLI); + SDValue Ret = CallResult.first; + if (model != TLSModel::LocalDynamic) + return Ret; + SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, MipsII::MO_DTPREL_HI); + SDValue Hi = DAG.getNode(MipsISD::TlsHi, DL, PtrVT, TGAHi); + SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, MipsII::MO_DTPREL_LO); + SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); + SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret); + return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo); + } + SDValue Offset; + if (model == TLSModel::InitialExec) { + SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, MipsII::MO_GOTTPREL); + TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT),TGA); + Offset = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), TGA, MachinePointerInfo()); + } + else { + assert(model == TLSModel::LocalExec); + SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, MipsII::MO_TPREL_HI); + SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, MipsII::MO_TPREL_LO); + SDValue Hi = DAG.getNode(MipsISD::TlsHi, DL, PtrVT, TGAHi); + SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); + Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo); + } + SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT); + return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset); +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerINIT_TRAMPOLINE.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerINIT_TRAMPOLINE.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerINIT_TRAMPOLINE.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerINTRINSIC_WO_CHAIN.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerINTRINSIC_WO_CHAIN.cpp new file mode 100644 index 0000000000000000000000000000000000000000..150e8c0e72027acdaeeb3a046260a9210d8c6e7c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerINTRINSIC_WO_CHAIN.cpp @@ -0,0 +1,601 @@ +SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const { + SDLoc DL(Op); + unsigned Intrinsic = cast(Op->getOperand(0))->getZExtValue(); + switch (Intrinsic) { + default: + return SDValue(); + case Intrinsic::mips_shilo: + return lowerDSPIntr(Op, DAG, MipsISD::SHILO); + case Intrinsic::mips_dpau_h_qbl: + return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL); + case Intrinsic::mips_dpau_h_qbr: + return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR); + case Intrinsic::mips_dpsu_h_qbl: + return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL); + case Intrinsic::mips_dpsu_h_qbr: + return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR); + case Intrinsic::mips_dpa_w_ph: + return lowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH); + case Intrinsic::mips_dps_w_ph: + return lowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH); + case Intrinsic::mips_dpax_w_ph: + return lowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH); + case Intrinsic::mips_dpsx_w_ph: + return lowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH); + case Intrinsic::mips_mulsa_w_ph: + return lowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH); + case Intrinsic::mips_mult: + return lowerDSPIntr(Op, DAG, MipsISD::Mult); + case Intrinsic::mips_multu: + return lowerDSPIntr(Op, DAG, MipsISD::Multu); + case Intrinsic::mips_madd: + return lowerDSPIntr(Op, DAG, MipsISD::MAdd); + case Intrinsic::mips_maddu: + return lowerDSPIntr(Op, DAG, MipsISD::MAddu); + case Intrinsic::mips_msub: + return lowerDSPIntr(Op, DAG, MipsISD::MSub); + case Intrinsic::mips_msubu: + return lowerDSPIntr(Op, DAG, MipsISD::MSubu); + case Intrinsic::mips_addv_b: + case Intrinsic::mips_addv_h: + case Intrinsic::mips_addv_w: + case Intrinsic::mips_addv_d: + return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_addvi_b: + case Intrinsic::mips_addvi_h: + case Intrinsic::mips_addvi_w: + case Intrinsic::mips_addvi_d: + return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); + case Intrinsic::mips_and_v: + return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_andi_b: + return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); + case Intrinsic::mips_bclr_b: + case Intrinsic::mips_bclr_h: + case Intrinsic::mips_bclr_w: + case Intrinsic::mips_bclr_d: + return lowerMSABitClear(Op, DAG); + case Intrinsic::mips_bclri_b: + case Intrinsic::mips_bclri_h: + case Intrinsic::mips_bclri_w: + case Intrinsic::mips_bclri_d: + return lowerMSABitClearImm(Op, DAG); + case Intrinsic::mips_binsli_b: + case Intrinsic::mips_binsli_h: + case Intrinsic::mips_binsli_w: + case Intrinsic::mips_binsli_d: { + EVT VecTy = Op->getValueType(0); + EVT EltTy = VecTy.getVectorElementType(); + if (Op->getConstantOperandVal(3) >= EltTy.getSizeInBits()) + report_fatal_error("Immediate out of range"); + APInt Mask = APInt::getHighBitsSet(EltTy.getSizeInBits(), Op->getConstantOperandVal(3) + 1); + return DAG.getNode(ISD::VSELECT, DL, VecTy, DAG.getConstant(Mask, DL, VecTy, true), Op->getOperand(2), Op->getOperand(1)); + } + case Intrinsic::mips_binsri_b: + case Intrinsic::mips_binsri_h: + case Intrinsic::mips_binsri_w: + case Intrinsic::mips_binsri_d: { + EVT VecTy = Op->getValueType(0); + EVT EltTy = VecTy.getVectorElementType(); + if (Op->getConstantOperandVal(3) >= EltTy.getSizeInBits()) + report_fatal_error("Immediate out of range"); + APInt Mask = APInt::getLowBitsSet(EltTy.getSizeInBits(), Op->getConstantOperandVal(3) + 1); + return DAG.getNode(ISD::VSELECT, DL, VecTy, DAG.getConstant(Mask, DL, VecTy, true), Op->getOperand(2), Op->getOperand(1)); + } + case Intrinsic::mips_bmnz_v: + return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3), Op->getOperand(2), Op->getOperand(1)); + case Intrinsic::mips_bmnzi_b: + return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), lowerMSASplatImm(Op, 3, DAG), Op->getOperand(2), Op->getOperand(1)); + case Intrinsic::mips_bmz_v: + return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_bmzi_b: + return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), lowerMSASplatImm(Op, 3, DAG), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_bneg_b: + case Intrinsic::mips_bneg_h: + case Intrinsic::mips_bneg_w: + case Intrinsic::mips_bneg_d: { + EVT VecTy = Op->getValueType(0); + SDValue One = DAG.getConstant(1, DL, VecTy); + return DAG.getNode(ISD::XOR, DL, VecTy, Op->getOperand(1), DAG.getNode(ISD::SHL, DL, VecTy, One, truncateVecElts(Op, DAG))); + } + case Intrinsic::mips_bnegi_b: + case Intrinsic::mips_bnegi_h: + case Intrinsic::mips_bnegi_w: + case Intrinsic::mips_bnegi_d: + return lowerMSABinaryBitImmIntr(Op, DAG, ISD::XOR, Op->getOperand(2), !Subtarget.isLittle()); + case Intrinsic::mips_bnz_b: + case Intrinsic::mips_bnz_h: + case Intrinsic::mips_bnz_w: + case Intrinsic::mips_bnz_d: + return DAG.getNode(MipsISD::VALL_NONZERO, DL, Op->getValueType(0), Op->getOperand(1)); + case Intrinsic::mips_bnz_v: + return DAG.getNode(MipsISD::VANY_NONZERO, DL, Op->getValueType(0), Op->getOperand(1)); + case Intrinsic::mips_bsel_v: + return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(3), Op->getOperand(2)); + case Intrinsic::mips_bseli_b: + return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 3, DAG), Op->getOperand(2)); + case Intrinsic::mips_bset_b: + case Intrinsic::mips_bset_h: + case Intrinsic::mips_bset_w: + case Intrinsic::mips_bset_d: { + EVT VecTy = Op->getValueType(0); + SDValue One = DAG.getConstant(1, DL, VecTy); + return DAG.getNode(ISD::OR, DL, VecTy, Op->getOperand(1), DAG.getNode(ISD::SHL, DL, VecTy, One, truncateVecElts(Op, DAG))); + } + case Intrinsic::mips_bseti_b: + case Intrinsic::mips_bseti_h: + case Intrinsic::mips_bseti_w: + case Intrinsic::mips_bseti_d: + return lowerMSABinaryBitImmIntr(Op, DAG, ISD::OR, Op->getOperand(2), !Subtarget.isLittle()); + case Intrinsic::mips_bz_b: + case Intrinsic::mips_bz_h: + case Intrinsic::mips_bz_w: + case Intrinsic::mips_bz_d: + return DAG.getNode(MipsISD::VALL_ZERO, DL, Op->getValueType(0), Op->getOperand(1)); + case Intrinsic::mips_bz_v: + return DAG.getNode(MipsISD::VANY_ZERO, DL, Op->getValueType(0), Op->getOperand(1)); + case Intrinsic::mips_ceq_b: + case Intrinsic::mips_ceq_h: + case Intrinsic::mips_ceq_w: + case Intrinsic::mips_ceq_d: + return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2), ISD::SETEQ); + case Intrinsic::mips_ceqi_b: + case Intrinsic::mips_ceqi_h: + case Intrinsic::mips_ceqi_w: + case Intrinsic::mips_ceqi_d: + return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG, true), ISD::SETEQ); + case Intrinsic::mips_cle_s_b: + case Intrinsic::mips_cle_s_h: + case Intrinsic::mips_cle_s_w: + case Intrinsic::mips_cle_s_d: + return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2), ISD::SETLE); + case Intrinsic::mips_clei_s_b: + case Intrinsic::mips_clei_s_h: + case Intrinsic::mips_clei_s_w: + case Intrinsic::mips_clei_s_d: + return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG, true), ISD::SETLE); + case Intrinsic::mips_cle_u_b: + case Intrinsic::mips_cle_u_h: + case Intrinsic::mips_cle_u_w: + case Intrinsic::mips_cle_u_d: + return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2), ISD::SETULE); + case Intrinsic::mips_clei_u_b: + case Intrinsic::mips_clei_u_h: + case Intrinsic::mips_clei_u_w: + case Intrinsic::mips_clei_u_d: + return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG), ISD::SETULE); + case Intrinsic::mips_clt_s_b: + case Intrinsic::mips_clt_s_h: + case Intrinsic::mips_clt_s_w: + case Intrinsic::mips_clt_s_d: + return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2), ISD::SETLT); + case Intrinsic::mips_clti_s_b: + case Intrinsic::mips_clti_s_h: + case Intrinsic::mips_clti_s_w: + case Intrinsic::mips_clti_s_d: + return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG, true), ISD::SETLT); + case Intrinsic::mips_clt_u_b: + case Intrinsic::mips_clt_u_h: + case Intrinsic::mips_clt_u_w: + case Intrinsic::mips_clt_u_d: + return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2), ISD::SETULT); + case Intrinsic::mips_clti_u_b: + case Intrinsic::mips_clti_u_h: + case Intrinsic::mips_clti_u_w: + case Intrinsic::mips_clti_u_d: + return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG), ISD::SETULT); + case Intrinsic::mips_copy_s_b: + case Intrinsic::mips_copy_s_h: + case Intrinsic::mips_copy_s_w: + return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT); + case Intrinsic::mips_copy_s_d: + if (Subtarget.hasMips64()) + return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT); + else { + return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + } + case Intrinsic::mips_copy_u_b: + case Intrinsic::mips_copy_u_h: + case Intrinsic::mips_copy_u_w: + return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT); + case Intrinsic::mips_copy_u_d: + if (Subtarget.hasMips64()) + return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT); + else { + return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + } + case Intrinsic::mips_div_s_b: + case Intrinsic::mips_div_s_h: + case Intrinsic::mips_div_s_w: + case Intrinsic::mips_div_s_d: + return DAG.getNode(ISD::SDIV, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_div_u_b: + case Intrinsic::mips_div_u_h: + case Intrinsic::mips_div_u_w: + case Intrinsic::mips_div_u_d: + return DAG.getNode(ISD::UDIV, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_fadd_w: + case Intrinsic::mips_fadd_d: + return DAG.getNode(ISD::FADD, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_fceq_w: + case Intrinsic::mips_fceq_d: + return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2), ISD::SETOEQ); + case Intrinsic::mips_fcle_w: + case Intrinsic::mips_fcle_d: + return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2), ISD::SETOLE); + case Intrinsic::mips_fclt_w: + case Intrinsic::mips_fclt_d: + return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2), ISD::SETOLT); + case Intrinsic::mips_fcne_w: + case Intrinsic::mips_fcne_d: + return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2), ISD::SETONE); + case Intrinsic::mips_fcor_w: + case Intrinsic::mips_fcor_d: + return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2), ISD::SETO); + case Intrinsic::mips_fcueq_w: + case Intrinsic::mips_fcueq_d: + return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2), ISD::SETUEQ); + case Intrinsic::mips_fcule_w: + case Intrinsic::mips_fcule_d: + return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2), ISD::SETULE); + case Intrinsic::mips_fcult_w: + case Intrinsic::mips_fcult_d: + return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2), ISD::SETULT); + case Intrinsic::mips_fcun_w: + case Intrinsic::mips_fcun_d: + return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2), ISD::SETUO); + case Intrinsic::mips_fcune_w: + case Intrinsic::mips_fcune_d: + return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2), ISD::SETUNE); + case Intrinsic::mips_fdiv_w: + case Intrinsic::mips_fdiv_d: + return DAG.getNode(ISD::FDIV, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_ffint_u_w: + case Intrinsic::mips_ffint_u_d: + return DAG.getNode(ISD::UINT_TO_FP, DL, Op->getValueType(0), Op->getOperand(1)); + case Intrinsic::mips_ffint_s_w: + case Intrinsic::mips_ffint_s_d: + return DAG.getNode(ISD::SINT_TO_FP, DL, Op->getValueType(0), Op->getOperand(1)); + case Intrinsic::mips_fill_b: + case Intrinsic::mips_fill_h: + case Intrinsic::mips_fill_w: + case Intrinsic::mips_fill_d: { + EVT ResTy = Op->getValueType(0); + SmallVector Ops(ResTy.getVectorNumElements(), Op->getOperand(1)); + return DAG.getBuildVector(ResTy, DL, Ops); + } + case Intrinsic::mips_fexp2_w: + case Intrinsic::mips_fexp2_d: { + EVT ResTy = Op->getValueType(0); + return DAG.getNode(ISD::FMUL, SDLoc(Op), ResTy, Op->getOperand(1), DAG.getNode(ISD::FEXP2, SDLoc(Op), ResTy, Op->getOperand(2))); + } + case Intrinsic::mips_flog2_w: + case Intrinsic::mips_flog2_d: + return DAG.getNode(ISD::FLOG2, DL, Op->getValueType(0), Op->getOperand(1)); + case Intrinsic::mips_fmadd_w: + case Intrinsic::mips_fmadd_d: + return DAG.getNode(ISD::FMA, SDLoc(Op), Op->getValueType(0), Op->getOperand(1), Op->getOperand(2), Op->getOperand(3)); + case Intrinsic::mips_fmul_w: + case Intrinsic::mips_fmul_d: + return DAG.getNode(ISD::FMUL, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_fmsub_w: + case Intrinsic::mips_fmsub_d: { + return DAG.getNode(MipsISD::FMS, SDLoc(Op), Op->getValueType(0), Op->getOperand(1), Op->getOperand(2), Op->getOperand(3)); + } + case Intrinsic::mips_frint_w: + case Intrinsic::mips_frint_d: + return DAG.getNode(ISD::FRINT, DL, Op->getValueType(0), Op->getOperand(1)); + case Intrinsic::mips_fsqrt_w: + case Intrinsic::mips_fsqrt_d: + return DAG.getNode(ISD::FSQRT, DL, Op->getValueType(0), Op->getOperand(1)); + case Intrinsic::mips_fsub_w: + case Intrinsic::mips_fsub_d: + return DAG.getNode(ISD::FSUB, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_ftrunc_u_w: + case Intrinsic::mips_ftrunc_u_d: + return DAG.getNode(ISD::FP_TO_UINT, DL, Op->getValueType(0), Op->getOperand(1)); + case Intrinsic::mips_ftrunc_s_w: + case Intrinsic::mips_ftrunc_s_d: + return DAG.getNode(ISD::FP_TO_SINT, DL, Op->getValueType(0), Op->getOperand(1)); + case Intrinsic::mips_ilvev_b: + case Intrinsic::mips_ilvev_h: + case Intrinsic::mips_ilvev_w: + case Intrinsic::mips_ilvev_d: + return DAG.getNode(MipsISD::ILVEV, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_ilvl_b: + case Intrinsic::mips_ilvl_h: + case Intrinsic::mips_ilvl_w: + case Intrinsic::mips_ilvl_d: + return DAG.getNode(MipsISD::ILVL, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_ilvod_b: + case Intrinsic::mips_ilvod_h: + case Intrinsic::mips_ilvod_w: + case Intrinsic::mips_ilvod_d: + return DAG.getNode(MipsISD::ILVOD, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_ilvr_b: + case Intrinsic::mips_ilvr_h: + case Intrinsic::mips_ilvr_w: + case Intrinsic::mips_ilvr_d: + return DAG.getNode(MipsISD::ILVR, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_insert_b: + case Intrinsic::mips_insert_h: + case Intrinsic::mips_insert_w: + case Intrinsic::mips_insert_d: + return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0), Op->getOperand(1), Op->getOperand(3), Op->getOperand(2)); + case Intrinsic::mips_insve_b: + case Intrinsic::mips_insve_h: + case Intrinsic::mips_insve_w: + case Intrinsic::mips_insve_d: { + int64_t Max; + switch (Intrinsic) { + case Intrinsic::mips_insve_b: Max = 15; break; + case Intrinsic::mips_insve_h: Max = 7; break; + case Intrinsic::mips_insve_w: Max = 3; break; + case Intrinsic::mips_insve_d: Max = 1; break; + default: llvm_unreachable("Unmatched intrinsic"); + } + int64_t Value = cast(Op->getOperand(2))->getSExtValue(); + if (Value < 0 || Value > Max) + report_fatal_error("Immediate out of range"); + return DAG.getNode(MipsISD::INSVE, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2), Op->getOperand(3), DAG.getConstant(0, DL, MVT::i32)); + } + case Intrinsic::mips_ldi_b: + case Intrinsic::mips_ldi_h: + case Intrinsic::mips_ldi_w: + case Intrinsic::mips_ldi_d: + return lowerMSASplatImm(Op, 1, DAG, true); + case Intrinsic::mips_lsa: + case Intrinsic::mips_dlsa: { + EVT ResTy = Op->getValueType(0); + return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1), DAG.getNode(ISD::SHL, SDLoc(Op), ResTy, Op->getOperand(2), Op->getOperand(3))); + } + case Intrinsic::mips_maddv_b: + case Intrinsic::mips_maddv_h: + case Intrinsic::mips_maddv_w: + case Intrinsic::mips_maddv_d: { + EVT ResTy = Op->getValueType(0); + return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1), DAG.getNode(ISD::MUL, SDLoc(Op), ResTy, Op->getOperand(2), Op->getOperand(3))); + } + case Intrinsic::mips_max_s_b: + case Intrinsic::mips_max_s_h: + case Intrinsic::mips_max_s_w: + case Intrinsic::mips_max_s_d: + return DAG.getNode(ISD::SMAX, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_max_u_b: + case Intrinsic::mips_max_u_h: + case Intrinsic::mips_max_u_w: + case Intrinsic::mips_max_u_d: + return DAG.getNode(ISD::UMAX, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_maxi_s_b: + case Intrinsic::mips_maxi_s_h: + case Intrinsic::mips_maxi_s_w: + case Intrinsic::mips_maxi_s_d: + return DAG.getNode(ISD::SMAX, DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG, true)); + case Intrinsic::mips_maxi_u_b: + case Intrinsic::mips_maxi_u_h: + case Intrinsic::mips_maxi_u_w: + case Intrinsic::mips_maxi_u_d: + return DAG.getNode(ISD::UMAX, DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); + case Intrinsic::mips_min_s_b: + case Intrinsic::mips_min_s_h: + case Intrinsic::mips_min_s_w: + case Intrinsic::mips_min_s_d: + return DAG.getNode(ISD::SMIN, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_min_u_b: + case Intrinsic::mips_min_u_h: + case Intrinsic::mips_min_u_w: + case Intrinsic::mips_min_u_d: + return DAG.getNode(ISD::UMIN, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_mini_s_b: + case Intrinsic::mips_mini_s_h: + case Intrinsic::mips_mini_s_w: + case Intrinsic::mips_mini_s_d: + return DAG.getNode(ISD::SMIN, DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG, true)); + case Intrinsic::mips_mini_u_b: + case Intrinsic::mips_mini_u_h: + case Intrinsic::mips_mini_u_w: + case Intrinsic::mips_mini_u_d: + return DAG.getNode(ISD::UMIN, DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); + case Intrinsic::mips_mod_s_b: + case Intrinsic::mips_mod_s_h: + case Intrinsic::mips_mod_s_w: + case Intrinsic::mips_mod_s_d: + return DAG.getNode(ISD::SREM, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_mod_u_b: + case Intrinsic::mips_mod_u_h: + case Intrinsic::mips_mod_u_w: + case Intrinsic::mips_mod_u_d: + return DAG.getNode(ISD::UREM, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_mulv_b: + case Intrinsic::mips_mulv_h: + case Intrinsic::mips_mulv_w: + case Intrinsic::mips_mulv_d: + return DAG.getNode(ISD::MUL, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_msubv_b: + case Intrinsic::mips_msubv_h: + case Intrinsic::mips_msubv_w: + case Intrinsic::mips_msubv_d: { + EVT ResTy = Op->getValueType(0); + return DAG.getNode(ISD::SUB, SDLoc(Op), ResTy, Op->getOperand(1), DAG.getNode(ISD::MUL, SDLoc(Op), ResTy, Op->getOperand(2), Op->getOperand(3))); + } + case Intrinsic::mips_nlzc_b: + case Intrinsic::mips_nlzc_h: + case Intrinsic::mips_nlzc_w: + case Intrinsic::mips_nlzc_d: + return DAG.getNode(ISD::CTLZ, DL, Op->getValueType(0), Op->getOperand(1)); + case Intrinsic::mips_nor_v: { + SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + return DAG.getNOT(DL, Res, Res->getValueType(0)); + } + case Intrinsic::mips_nori_b: { + SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); + return DAG.getNOT(DL, Res, Res->getValueType(0)); + } + case Intrinsic::mips_or_v: + return DAG.getNode(ISD::OR, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_ori_b: + return DAG.getNode(ISD::OR, DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); + case Intrinsic::mips_pckev_b: + case Intrinsic::mips_pckev_h: + case Intrinsic::mips_pckev_w: + case Intrinsic::mips_pckev_d: + return DAG.getNode(MipsISD::PCKEV, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_pckod_b: + case Intrinsic::mips_pckod_h: + case Intrinsic::mips_pckod_w: + case Intrinsic::mips_pckod_d: + return DAG.getNode(MipsISD::PCKOD, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_pcnt_b: + case Intrinsic::mips_pcnt_h: + case Intrinsic::mips_pcnt_w: + case Intrinsic::mips_pcnt_d: + return DAG.getNode(ISD::CTPOP, DL, Op->getValueType(0), Op->getOperand(1)); + case Intrinsic::mips_sat_s_b: + case Intrinsic::mips_sat_s_h: + case Intrinsic::mips_sat_s_w: + case Intrinsic::mips_sat_s_d: + case Intrinsic::mips_sat_u_b: + case Intrinsic::mips_sat_u_h: + case Intrinsic::mips_sat_u_w: + case Intrinsic::mips_sat_u_d: { + int64_t Max; + switch (Intrinsic) { + case Intrinsic::mips_sat_s_b: + case Intrinsic::mips_sat_u_b: Max = 7; break; + case Intrinsic::mips_sat_s_h: + case Intrinsic::mips_sat_u_h: Max = 15; break; + case Intrinsic::mips_sat_s_w: + case Intrinsic::mips_sat_u_w: Max = 31; break; + case Intrinsic::mips_sat_s_d: + case Intrinsic::mips_sat_u_d: Max = 63; break; + default: llvm_unreachable("Unmatched intrinsic"); + } + int64_t Value = cast(Op->getOperand(2))->getSExtValue(); + if (Value < 0 || Value > Max) + report_fatal_error("Immediate out of range"); + return SDValue(); + } + case Intrinsic::mips_shf_b: + case Intrinsic::mips_shf_h: + case Intrinsic::mips_shf_w: { + int64_t Value = cast(Op->getOperand(2))->getSExtValue(); + if (Value < 0 || Value > 255) + report_fatal_error("Immediate out of range"); + return DAG.getNode(MipsISD::SHF, DL, Op->getValueType(0), Op->getOperand(2), Op->getOperand(1)); + } + case Intrinsic::mips_sldi_b: + case Intrinsic::mips_sldi_h: + case Intrinsic::mips_sldi_w: + case Intrinsic::mips_sldi_d: { + int64_t Max; + switch (Intrinsic) { + case Intrinsic::mips_sldi_b: Max = 15; break; + case Intrinsic::mips_sldi_h: Max = 7; break; + case Intrinsic::mips_sldi_w: Max = 3; break; + case Intrinsic::mips_sldi_d: Max = 1; break; + default: llvm_unreachable("Unmatched intrinsic"); + } + int64_t Value = cast(Op->getOperand(3))->getSExtValue(); + if (Value < 0 || Value > Max) + report_fatal_error("Immediate out of range"); + return SDValue(); + } + case Intrinsic::mips_sll_b: + case Intrinsic::mips_sll_h: + case Intrinsic::mips_sll_w: + case Intrinsic::mips_sll_d: + return DAG.getNode(ISD::SHL, DL, Op->getValueType(0), Op->getOperand(1), truncateVecElts(Op, DAG)); + case Intrinsic::mips_slli_b: + case Intrinsic::mips_slli_h: + case Intrinsic::mips_slli_w: + case Intrinsic::mips_slli_d: + return DAG.getNode(ISD::SHL, DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); + case Intrinsic::mips_splat_b: + case Intrinsic::mips_splat_h: + case Intrinsic::mips_splat_w: + case Intrinsic::mips_splat_d: + return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0), lowerMSASplatZExt(Op, 2, DAG), Op->getOperand(1), Op->getOperand(1)); + case Intrinsic::mips_splati_b: + case Intrinsic::mips_splati_h: + case Intrinsic::mips_splati_w: + case Intrinsic::mips_splati_d: + return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0), lowerMSASplatImm(Op, 2, DAG), Op->getOperand(1), Op->getOperand(1)); + case Intrinsic::mips_sra_b: + case Intrinsic::mips_sra_h: + case Intrinsic::mips_sra_w: + case Intrinsic::mips_sra_d: + return DAG.getNode(ISD::SRA, DL, Op->getValueType(0), Op->getOperand(1), truncateVecElts(Op, DAG)); + case Intrinsic::mips_srai_b: + case Intrinsic::mips_srai_h: + case Intrinsic::mips_srai_w: + case Intrinsic::mips_srai_d: + return DAG.getNode(ISD::SRA, DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); + case Intrinsic::mips_srari_b: + case Intrinsic::mips_srari_h: + case Intrinsic::mips_srari_w: + case Intrinsic::mips_srari_d: { + int64_t Max; + switch (Intrinsic) { + case Intrinsic::mips_srari_b: Max = 7; break; + case Intrinsic::mips_srari_h: Max = 15; break; + case Intrinsic::mips_srari_w: Max = 31; break; + case Intrinsic::mips_srari_d: Max = 63; break; + default: llvm_unreachable("Unmatched intrinsic"); + } + int64_t Value = cast(Op->getOperand(2))->getSExtValue(); + if (Value < 0 || Value > Max) + report_fatal_error("Immediate out of range"); + return SDValue(); + } + case Intrinsic::mips_srl_b: + case Intrinsic::mips_srl_h: + case Intrinsic::mips_srl_w: + case Intrinsic::mips_srl_d: + return DAG.getNode(ISD::SRL, DL, Op->getValueType(0), Op->getOperand(1), truncateVecElts(Op, DAG)); + case Intrinsic::mips_srli_b: + case Intrinsic::mips_srli_h: + case Intrinsic::mips_srli_w: + case Intrinsic::mips_srli_d: + return DAG.getNode(ISD::SRL, DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); + case Intrinsic::mips_srlri_b: + case Intrinsic::mips_srlri_h: + case Intrinsic::mips_srlri_w: + case Intrinsic::mips_srlri_d: { + int64_t Max; + switch (Intrinsic) { + case Intrinsic::mips_srlri_b: Max = 7; break; + case Intrinsic::mips_srlri_h: Max = 15; break; + case Intrinsic::mips_srlri_w: Max = 31; break; + case Intrinsic::mips_srlri_d: Max = 63; break; + default: llvm_unreachable("Unmatched intrinsic"); + } + int64_t Value = cast(Op->getOperand(2))->getSExtValue(); + if (Value < 0 || Value > Max) + report_fatal_error("Immediate out of range"); + return SDValue(); + } + case Intrinsic::mips_subv_b: + case Intrinsic::mips_subv_h: + case Intrinsic::mips_subv_w: + case Intrinsic::mips_subv_d: + return DAG.getNode(ISD::SUB, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_subvi_b: + case Intrinsic::mips_subvi_h: + case Intrinsic::mips_subvi_w: + case Intrinsic::mips_subvi_d: + return DAG.getNode(ISD::SUB, DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); + case Intrinsic::mips_vshf_b: + case Intrinsic::mips_vshf_h: + case Intrinsic::mips_vshf_w: + case Intrinsic::mips_vshf_d: + return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2), Op->getOperand(3)); + case Intrinsic::mips_xor_v: + return DAG.getNode(ISD::XOR, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2)); + case Intrinsic::mips_xori_b: + return DAG.getNode(ISD::XOR, DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); + case Intrinsic::thread_pointer: { + EVT PtrVT = getPointerTy(DAG.getDataLayout()); + return DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT); + } + } +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerLOAD.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerLOAD.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c386ba3e624a943893bdeee81a344bf221934428 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerLOAD.cpp @@ -0,0 +1,28 @@ +SDValue MipsTargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const { + LoadSDNode *LD = cast(Op); + EVT MemVT = LD->getMemoryVT(); + if (Subtarget.systemSupportsUnalignedAccess()) + return Op; + if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) || ((MemVT != MVT::i32) && (MemVT != MVT::i64))) + return SDValue(); + bool IsLittle = Subtarget.isLittle(); + EVT VT = Op.getValueType(); + ISD::LoadExtType ExtType = LD->getExtensionType(); + SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT); + assert((VT == MVT::i32) || (VT == MVT::i64)); + if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) { + SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef, IsLittle ? 7 : 0); + return createLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL, IsLittle ? 0 : 7); + } + SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef, IsLittle ? 3 : 0); + SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL, IsLittle ? 0 : 3); + if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) || (ExtType == ISD::EXTLOAD)) + return LWR; + assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD)); + SDLoc DL(LD); + SDValue Const32 = DAG.getConstant(32, DL, MVT::i32); + SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32); + SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32); + SDValue Ops[] = { SRL, LWR.getValue(1) }; + return DAG.getMergeValues(Ops, DL); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerOperation.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerOperation.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fbfe3d2f0ef29923975a86d495e1dd2120dba454 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerOperation.cpp @@ -0,0 +1,22 @@ +SDValue MipsSETargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { + switch(Op.getOpcode()) { + case ISD::LOAD: return lowerLOAD(Op, DAG); + case ISD::STORE: return lowerSTORE(Op, DAG); + case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG); + case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG); + case ISD::MULHS: return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG); + case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG); + case ISD::MUL: return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG); + case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG); + case ISD::UDIVREM: return lowerMulDiv(Op, MipsISD::DivRemU, true, true, DAG); + case ISD::INTRINSIC_WO_CHAIN: return lowerINTRINSIC_WO_CHAIN(Op, DAG); + case ISD::INTRINSIC_W_CHAIN: return lowerINTRINSIC_W_CHAIN(Op, DAG); + case ISD::INTRINSIC_VOID: return lowerINTRINSIC_VOID(Op, DAG); + case ISD::EXTRACT_VECTOR_ELT: return lowerEXTRACT_VECTOR_ELT(Op, DAG); + case ISD::BUILD_VECTOR: return lowerBUILD_VECTOR(Op, DAG); + case ISD::VECTOR_SHUFFLE: return lowerVECTOR_SHUFFLE(Op, DAG); + case ISD::SELECT: return lowerSELECT(Op, DAG); + case ISD::BITCAST: return lowerBITCAST(Op, DAG); + } + return MipsTargetLowering::LowerOperation(Op, DAG); +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerRETURNADDR.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerRETURNADDR.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ded637a4455513a16d891e39639e269a720641e3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerRETURNADDR.cpp @@ -0,0 +1,15 @@ +SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const { + if (verifyReturnAddressArgumentIsConstant(Op, DAG)) + return SDValue(); + if (cast(Op.getOperand(0))->getZExtValue() != 0) { + DAG.getContext()->emitError("return address can be determined only for current frame"); + return SDValue(); + } + MachineFunction &MF = DAG.getMachineFunction(); + MachineFrameInfo &MFI = MF.getFrameInfo(); + MVT VT = Op.getSimpleValueType(); + unsigned RA = ABI.IsN64() ? Mips::RA_64 : Mips::RA; + MFI.setReturnAddressIsTaken(true); + unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT)); + return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerReturn.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerReturn.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1ed075e6ccf9610456191789f39cad7dd5b16736 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerReturn.cpp @@ -0,0 +1,66 @@ +SDValue MipsTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl &Outs, const SmallVectorImpl &OutVals, const SDLoc &DL, SelectionDAG &DAG) const { + SmallVector RVLocs; + MachineFunction &MF = DAG.getMachineFunction(); + MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext()); + CCInfo.AnalyzeReturn(Outs, RetCC_Mips); + SDValue Flag; + SmallVector RetOps(1, Chain); + for (unsigned i = 0; i != RVLocs.size(); ++i) { + SDValue Val = OutVals[i]; + CCValAssign &VA = RVLocs[i]; + assert(VA.isRegLoc() && "Can only return in registers!"); + bool UseUpperBits = false; + switch (VA.getLocInfo()) { + default: + llvm_unreachable("Unknown loc info!"); + case CCValAssign::Full: + break; + case CCValAssign::BCvt: + Val = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Val); + break; + case CCValAssign::AExtUpper: + UseUpperBits = true; + LLVM_FALLTHROUGH; + case CCValAssign::AExt: + Val = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Val); + break; + case CCValAssign::ZExtUpper: + UseUpperBits = true; + LLVM_FALLTHROUGH; + case CCValAssign::ZExt: + Val = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Val); + break; + case CCValAssign::SExtUpper: + UseUpperBits = true; + LLVM_FALLTHROUGH; + case CCValAssign::SExt: + Val = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Val); + break; + } + if (UseUpperBits) { + unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits(); + unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); + Val = DAG.getNode(ISD::SHL, DL, VA.getLocVT(), Val, DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); + } + Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag); + Flag = Chain.getValue(1); + RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); + } + if (MF.getFunction().hasStructRetAttr()) { + MipsFunctionInfo *MipsFI = MF.getInfo(); + unsigned Reg = MipsFI->getSRetReturnReg(); + if (!Reg) + llvm_unreachable("sret virtual register not created in the entry block"); + SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout())); + unsigned V0 = ABI.IsN64() ? Mips::V0_64 : Mips::V0; + Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag); + Flag = Chain.getValue(1); + RetOps.push_back(DAG.getRegister(V0, getPointerTy(DAG.getDataLayout()))); + } + RetOps[0] = Chain;. + if (Flag.getNode()) + RetOps.push_back(Flag); + if (DAG.getMachineFunction().getFunction().hasFnAttribute("interrupt")) + return LowerInterruptReturn(RetOps, DL, DAG); + return DAG.getNode(MipsISD::Ret, DL, MVT::Other, RetOps); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerSELECT_CC.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerSELECT_CC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerSELECT_CC.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerSMUL_LOHI.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerSMUL_LOHI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerSMUL_LOHI.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerSTACKSAVE.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerSTACKSAVE.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0047fa49f09537200023a679a676db5c8173cfc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerSTACKSAVE.cpp @@ -0,0 +1 @@ +None diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerSTORE.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerSTORE.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8480d434b4f2a11f981760cd1a6b7fbd041cdc6c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerSTORE.cpp @@ -0,0 +1,7 @@ +SDValue MipsTargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const { + StoreSDNode *SD = cast(Op); + EVT MemVT = SD->getMemoryVT();. + if (!Subtarget.systemSupportsUnalignedAccess() && (SD->getAlignment() < MemVT.getSizeInBits() / 8) && ((MemVT == MVT::i32) || (MemVT == MVT::i64))) + return lowerUnalignedIntStore(SD, DAG, Subtarget.isLittle()); + return lowerFP_TO_SINT_STORE(SD, DAG, Subtarget.isSingleFloat()); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerUMUL_LOHI.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerUMUL_LOHI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerUMUL_LOHI.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerVAARG.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerVAARG.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c25f7a8bbc98b97c5f375c8bf8e107e5f6b52579 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerVAARG.cpp @@ -0,0 +1,25 @@ +SDValue MipsTargetLowering::lowerVAARG(SDValue Op, SelectionDAG &DAG) const { + SDNode *Node = Op.getNode(); + EVT VT = Node->getValueType(0); + SDValue Chain = Node->getOperand(0); + SDValue VAListPtr = Node->getOperand(1); + const Align Align = llvm::MaybeAlign(Node->getConstantOperandVal(3)).valueOrOne(); + const Value *SV = cast(Node->getOperand(2))->getValue(); + SDLoc DL(Node); + unsigned ArgSlotSizeInBytes = (ABI.IsN32() || ABI.IsN64()) ? 8 : 4; + SDValue VAListLoad = DAG.getLoad(getPointerTy(DAG.getDataLayout()), DL, Chain, VAListPtr, MachinePointerInfo(SV)); + SDValue VAList = VAListLoad; + if (Align > getMinStackArgumentAlignment()) { + VAList = DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList, DAG.getConstant(Align.value() - 1, DL, VAList.getValueType())); + VAList = DAG.getNode(ISD::AND, DL, VAList.getValueType(), VAList, DAG.getConstant(-(int64_t)Align.value(), DL, VAList.getValueType())); + } + auto &TD = DAG.getDataLayout(); + unsigned ArgSizeInBytes = TD.getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())); + SDValue Tmp3 = DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList, DAG.getConstant(alignTo(ArgSizeInBytes, ArgSlotSizeInBytes), DL, VAList.getValueType())); + Chain = DAG.getStore(VAListLoad.getValue(1), DL, Tmp3, VAListPtr, MachinePointerInfo(SV)); + if (!Subtarget.isLittle() && ArgSizeInBytes < ArgSlotSizeInBytes) { + unsigned Adjustment = ArgSlotSizeInBytes - ArgSizeInBytes; + VAList = DAG.getNode(ISD::ADD, DL, VAListPtr.getValueType(), VAList, DAG.getIntPtrConstant(Adjustment, DL)); + } + return DAG.getLoad(VT, DL, Chain, VAList, MachinePointerInfo()); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerVASTART.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerVASTART.cpp new file mode 100644 index 0000000000000000000000000000000000000000..82c750e52dc286a4e812e266e95aad7444d81f06 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/LowerVASTART.cpp @@ -0,0 +1,8 @@ +SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const { + MachineFunction &MF = DAG.getMachineFunction(); + MipsFunctionInfo *FuncInfo = MF.getInfo(); + SDLoc DL(Op); + SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), getPointerTy(MF.getDataLayout())); + const Value *SV = cast(Op.getOperand(2))->getValue(); + return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1), MachinePointerInfo(SV)); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/NodeType.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/NodeType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a38352825f56aab99f061204881b1757052b6041 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/NodeType.cpp @@ -0,0 +1,115 @@ +enum NodeType : unsigned { + FIRST_NUMBER = ISD::BUILTIN_OP_END, + JmpLink, + TailCall, + Highest, + Higher, + Hi, + Lo, + GotHi, + TlsHi, + GPRel, + ThreadPointer, + FMS, + FPBrcond, + FPCmp, + FSELECT, + MTC1_D64, + CMovFP_T, + CMovFP_F, + TruncIntFP, + Ret, + ERet, + EH_RETURN, + MFHI, + MFLO, + MTLOHI, + Mult, + Multu, + MAdd, + MAddu, + MSub, + MSubu, + DivRem, + DivRemU, + DivRem16, + DivRemU16, + BuildPairF64, + ExtractElementF64, + Wrapper, + DynAlloc, + Sync, + Ext, + Ins, + CIns, + EXTP, + EXTPDP, + EXTR_S_H, + EXTR_W, + EXTR_R_W, + EXTR_RS_W, + SHILO, + MTHLIP, + MULSAQ_S_W_PH, + MAQ_S_W_PHL, + MAQ_S_W_PHR, + MAQ_SA_W_PHL, + MAQ_SA_W_PHR, + DPAU_H_QBL, + DPAU_H_QBR, + DPSU_H_QBL, + DPSU_H_QBR, + DPAQ_S_W_PH, + DPSQ_S_W_PH, + DPAQ_SA_L_W, + DPSQ_SA_L_W, + DPA_W_PH, + DPS_W_PH, + DPAQX_S_W_PH, + DPAQX_SA_W_PH, + DPAX_W_PH, + DPSX_W_PH, + DPSQX_S_W_PH, + DPSQX_SA_W_PH, + MULSA_W_PH, + MULT, + MULTU, + MADD_DSP, + MADDU_DSP, + MSUB_DSP, + MSUBU_DSP, + SHLL_DSP, + SHRA_DSP, + SHRL_DSP, + SETCC_DSP, + SELECT_CC_DSP, + VALL_ZERO, + VANY_ZERO, + VALL_NONZERO, + VANY_NONZERO, + VCEQ, + VCLE_S, + VCLE_U, + VCLT_S, + VCLT_U, + VSHF, + SHF, + ILVEV, + ILVOD, + ILVL, + ILVR, + PCKEV, + PCKOD, + INSVE, + VNOR, + VEXTRACT_SEXT_ELT, + VEXTRACT_ZEXT_ELT, + LWL = ISD::FIRST_TARGET_MEMORY_OPCODE, + LWR, + SWL, + SWR, + LDL, + LDR, + SDL, + SDR +}; \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/PerformDAGCombine.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/PerformDAGCombine.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b4c27aab8d97ef85c9947073d81e7dab0609a8e5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/PerformDAGCombine.cpp @@ -0,0 +1,34 @@ +SDValue MipsSETargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { + SelectionDAG &DAG = DCI.DAG; + SDValue Val; + switch (N->getOpcode()) { + case ISD::AND: + Val = performANDCombine(N, DAG, DCI, Subtarget); + break; + case ISD::OR: + Val = performORCombine(N, DAG, DCI, Subtarget); + break; + case ISD::MUL: + return performMULCombine(N, DAG, DCI, this, Subtarget); + case ISD::SHL: + Val = performSHLCombine(N, DAG, DCI, Subtarget); + break; + case ISD::SRA: + return performSRACombine(N, DAG, DCI, Subtarget); + case ISD::SRL: + return performSRLCombine(N, DAG, DCI, Subtarget); + case ISD::VSELECT: + return performVSELECTCombine(N, DAG); + case ISD::XOR: + Val = performXORCombine(N, DAG, Subtarget); + break; + case ISD::SETCC: + Val = performSETCCCombine(N, DAG); + break; + } + if (Val.getNode()) { + LLVM_DEBUG(dbgs() << "\nMipsSE DAG Combine:\n"; N->printrWithDepth(dbgs(), &DAG); dbgs() << "\n=> \n"; Val.getNode()->printrWithDepth(dbgs(), &DAG); dbgs() << "\n"); + return Val; + } + return MipsTargetLowering::PerformDAGCombine(N, DCI); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/ReplaceNodeResults.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/ReplaceNodeResults.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8e0b70bb9b6952f3748f9c7143aec894bfccf9c8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/ReplaceNodeResults.cpp @@ -0,0 +1,3 @@ +void MipsTargetLowering::ReplaceNodeResults(SDNode *N, SmallVectorImpl &Results, SelectionDAG &DAG) const { + return LowerOperationWrapper(N, Results, DAG); +} diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/TargetLowering.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/TargetLowering.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b374c388335c1101e9b9313b761335931a0abe3a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/TargetLowering.cpp @@ -0,0 +1,173 @@ +MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI) : TargetLowering(TM), Subtarget(STI), ABI(TM.getABI()) { + setBooleanContents(ZeroOrOneBooleanContent); + setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); + if (Subtarget.hasMips32r6()) + setBooleanContents(ZeroOrOneBooleanContent, ZeroOrNegativeOneBooleanContent); + for (MVT VT : MVT::integer_valuetypes()) { + setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); + setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); + setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); + } + for (MVT VT : MVT::fp_valuetypes()) { + setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); + setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand); + } + for (MVT VT : MVT::fp_fixedlen_vector_valuetypes()) { + MVT F16VT = MVT::getVectorVT(MVT::f16, VT.getVectorNumElements()); + if (F16VT.isValid()) + setLoadExtAction(ISD::EXTLOAD, VT, F16VT, Expand); + } + setTruncStoreAction(MVT::f32, MVT::f16, Expand); + setTruncStoreAction(MVT::f64, MVT::f16, Expand); + setTruncStoreAction(MVT::f64, MVT::f32, Expand); + AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); + setOperationAction(ISD::BR_JT, MVT::Other, Expand); + setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); + setOperationAction(ISD::BlockAddress, MVT::i32, Custom); + setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); + setOperationAction(ISD::JumpTable, MVT::i32, Custom); + setOperationAction(ISD::ConstantPool, MVT::i32, Custom); + setOperationAction(ISD::SELECT, MVT::f32, Custom); + setOperationAction(ISD::SELECT, MVT::f64, Custom); + setOperationAction(ISD::SELECT, MVT::i32, Custom); + setOperationAction(ISD::SETCC, MVT::f32, Custom); + setOperationAction(ISD::SETCC, MVT::f64, Custom); + setOperationAction(ISD::BRCOND, MVT::Other, Custom); + setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); + setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); + setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); + if (!(TM.Options.NoNaNsFPMath || Subtarget.inAbs2008Mode())) { + setOperationAction(ISD::FABS, MVT::f32, Custom); + setOperationAction(ISD::FABS, MVT::f64, Custom); + } + if (Subtarget.isGP64bit()) { + setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); + setOperationAction(ISD::BlockAddress, MVT::i64, Custom); + setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); + setOperationAction(ISD::JumpTable, MVT::i64, Custom); + setOperationAction(ISD::ConstantPool, MVT::i64, Custom); + setOperationAction(ISD::SELECT, MVT::i64, Custom); + setOperationAction(ISD::LOAD, MVT::i64, Custom); + setOperationAction(ISD::STORE, MVT::i64, Custom); + setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); + setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom); + setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom); + setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom); + } + if (!Subtarget.isGP64bit()) { + setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); + setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); + setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); + } + setOperationAction(ISD::EH_DWARF_CFA, MVT::i32, Custom); + if (Subtarget.isGP64bit()) + setOperationAction(ISD::EH_DWARF_CFA, MVT::i64, Custom); + setOperationAction(ISD::SDIV, MVT::i32, Expand); + setOperationAction(ISD::SREM, MVT::i32, Expand); + setOperationAction(ISD::UDIV, MVT::i32, Expand); + setOperationAction(ISD::UREM, MVT::i32, Expand); + setOperationAction(ISD::SDIV, MVT::i64, Expand); + setOperationAction(ISD::SREM, MVT::i64, Expand); + setOperationAction(ISD::UDIV, MVT::i64, Expand); + setOperationAction(ISD::UREM, MVT::i64, Expand); + setOperationAction(ISD::BR_CC, MVT::f32, Expand); + setOperationAction(ISD::BR_CC, MVT::f64, Expand); + setOperationAction(ISD::BR_CC, MVT::i32, Expand); + setOperationAction(ISD::BR_CC, MVT::i64, Expand); + setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); + setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); + setOperationAction(ISD::SELECT_CC, MVT::f32, Expand); + setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); + setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); + setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); + setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); + setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); + setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); + if (Subtarget.hasCnMips()) { + setOperationAction(ISD::CTPOP, MVT::i32, Legal); + setOperationAction(ISD::CTPOP, MVT::i64, Legal); + } + else { + setOperationAction(ISD::CTPOP, MVT::i32, Expand); + setOperationAction(ISD::CTPOP, MVT::i64, Expand); + } + setOperationAction(ISD::CTTZ, MVT::i32, Expand); + setOperationAction(ISD::CTTZ, MVT::i64, Expand); + setOperationAction(ISD::ROTL, MVT::i32, Expand); + setOperationAction(ISD::ROTL, MVT::i64, Expand); + setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); + setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); + if (!Subtarget.hasMips32r2()) + setOperationAction(ISD::ROTR, MVT::i32, Expand); + if (!Subtarget.hasMips64r2()) + setOperationAction(ISD::ROTR, MVT::i64, Expand); + setOperationAction(ISD::FSIN, MVT::f32, Expand); + setOperationAction(ISD::FSIN, MVT::f64, Expand); + setOperationAction(ISD::FCOS, MVT::f32, Expand); + setOperationAction(ISD::FCOS, MVT::f64, Expand); + setOperationAction(ISD::FSINCOS, MVT::f32, Expand); + setOperationAction(ISD::FSINCOS, MVT::f64, Expand); + setOperationAction(ISD::FPOW, MVT::f32, Expand); + setOperationAction(ISD::FPOW, MVT::f64, Expand); + setOperationAction(ISD::FLOG, MVT::f32, Expand); + setOperationAction(ISD::FLOG2, MVT::f32, Expand); + setOperationAction(ISD::FLOG10, MVT::f32, Expand); + setOperationAction(ISD::FEXP, MVT::f32, Expand); + setOperationAction(ISD::FMA, MVT::f32, Expand); + setOperationAction(ISD::FMA, MVT::f64, Expand); + setOperationAction(ISD::FREM, MVT::f32, Expand); + setOperationAction(ISD::FREM, MVT::f64, Expand); + setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand); + setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand); + setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand); + setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand); + setOperationAction(ISD::EH_RETURN, MVT::Other, Custom); + setOperationAction(ISD::VASTART, MVT::Other, Custom); + setOperationAction(ISD::VAARG, MVT::Other, Custom); + setOperationAction(ISD::VACOPY, MVT::Other, Expand); + setOperationAction(ISD::VAEND, MVT::Other, Expand); + setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); + setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); + if (!Subtarget.isGP64bit()) { + setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand); + setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand); + } + if (!Subtarget.hasMips32r2()) { + setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); + setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); + } + if (!Subtarget.hasMips32() || Subtarget.inMips16Mode()) + setOperationAction(ISD::CTLZ, MVT::i32, Expand); + if (!Subtarget.hasMips64()) + setOperationAction(ISD::CTLZ, MVT::i64, Expand); + if (!Subtarget.hasMips32r2()) + setOperationAction(ISD::BSWAP, MVT::i32, Expand); + if (!Subtarget.hasMips64r2()) + setOperationAction(ISD::BSWAP, MVT::i64, Expand); + if (Subtarget.isGP64bit()) { + setLoadExtAction(ISD::SEXTLOAD, MVT::i64, MVT::i32, Custom); + setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, MVT::i32, Custom); + setLoadExtAction(ISD::EXTLOAD, MVT::i64, MVT::i32, Custom); + setTruncStoreAction(MVT::i64, MVT::i32, Custom); + } + setOperationAction(ISD::TRAP, MVT::Other, Legal); + setTargetDAGCombine(ISD::SDIVREM); + setTargetDAGCombine(ISD::UDIVREM); + setTargetDAGCombine(ISD::SELECT); + setTargetDAGCombine(ISD::AND); + setTargetDAGCombine(ISD::OR); + setTargetDAGCombine(ISD::ADD); + setTargetDAGCombine(ISD::SUB); + setTargetDAGCombine(ISD::AssertZext); + setTargetDAGCombine(ISD::SHL); + if (ABI.IsO32()) { + setLibcallName(RTLIB::SHL_I128, nullptr); + setLibcallName(RTLIB::SRL_I128, nullptr); + setLibcallName(RTLIB::SRA_I128, nullptr); + } + setMinFunctionAlignment(Subtarget.isGP64bit() ? Align(8) : Align(4)); + setMinStackArgumentAlignment((ABI.IsN32() || ABI.IsN64()) ? Align(8) : Align(4)); + setStackPointerRegisterToSaveRestore(ABI.IsN64() ? Mips::SP_64 : Mips::SP); + MaxStoresPerMemcpy = 16; + isMicroMips = Subtarget.inMicroMipsMode(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/computeMaskedBitsForTargetNode.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/computeMaskedBitsForTargetNode.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/computeMaskedBitsForTargetNode.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/enum NodeType.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/enum NodeType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7dbfada60499fd466d80b554df14092a07c7992f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/enum NodeType.cpp @@ -0,0 +1,26 @@ +enum NodeType { + ISD::ADD, + ISD::SUB, + ISD::MUL, + ISD::SDIV, + ISD::UDIV, + ISD::SREM, + ISD::UREM, + ISD::SMUL_LOHI, + ISD::UMUL_LOHI, + ISD::SDIVREM, + ISD::UDIVREM, + ISD::AND, + ISD::OR, + ISD::XOR, + ISD::SHL, + ISD::SRA, + ISD::SRL, + ISD::CTLZ, + ISD::CTLZ_ZERO_UNDEF, + ISD::CTTZ, + ISD::CTTZ_ZERO_UNDEF, + ISD::CTPOP, + ISD::SELECT, + ISD::SELECT_CC, +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/getJumpTableEncoding.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/getJumpTableEncoding.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0af5f9457e09348a5eb08c15ce717e092dc51262 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/getJumpTableEncoding.cpp @@ -0,0 +1,5 @@ +unsigned MipsTargetLowering::getJumpTableEncoding() const { + if (ABI.IsN64() && isPositionIndependent()) + return MachineJumpTableInfo::EK_GPRel64BlockAddress; + return TargetLowering::getJumpTableEncoding(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/getRegForInlineAsmConstraint.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/getRegForInlineAsmConstraint.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c4d6cb04cdaf5d170a432c7141d5bcd31383559f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/getRegForInlineAsmConstraint.cpp @@ -0,0 +1,56 @@ +std::pair MipsTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const { + if (Constraint.size() == 1) { + switch (Constraint[0]) { + case 'd': + case 'y': + case 'r': + if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) { + if (Subtarget.inMips16Mode()) + return std::make_pair(0U, &Mips::CPU16RegsRegClass); + return std::make_pair(0U, &Mips::GPR32RegClass); + } + if (VT == MVT::i64 && !Subtarget.isGP64bit()) + return std::make_pair(0U, &Mips::GPR32RegClass); + if (VT == MVT::i64 && Subtarget.isGP64bit()) + return std::make_pair(0U, &Mips::GPR64RegClass); + return std::make_pair(0U, nullptr); + case 'f': + if (VT == MVT::v16i8) + return std::make_pair(0U, &Mips::MSA128BRegClass); + else if (VT == MVT::v8i16 || VT == MVT::v8f16) + return std::make_pair(0U, &Mips::MSA128HRegClass); + else if (VT == MVT::v4i32 || VT == MVT::v4f32) + return std::make_pair(0U, &Mips::MSA128WRegClass); + else if (VT == MVT::v2i64 || VT == MVT::v2f64) + return std::make_pair(0U, &Mips::MSA128DRegClass); + else if (VT == MVT::f32) + return std::make_pair(0U, &Mips::FGR32RegClass); + else if ((VT == MVT::f64) && (!Subtarget.isSingleFloat())) { + if (Subtarget.isFP64bit()) + return std::make_pair(0U, &Mips::FGR64RegClass); + return std::make_pair(0U, &Mips::AFGR64RegClass); + } + break; + case 'c': + if (VT == MVT::i32) + return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass); + if (VT == MVT::i64) + return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass); + return std::make_pair(0U, nullptr); + case 'l': + if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) + return std::make_pair((unsigned)Mips::LO0, &Mips::LO32RegClass); + return std::make_pair((unsigned)Mips::LO0_64, &Mips::LO64RegClass); + case 'x': + return std::make_pair(0U, nullptr); + } + } + if (!Constraint.empty()) { + std::pair R; + R = parseRegForInlineAsmConstraint(Constraint, VT); + if (R.second) + return R; + } + return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT); +} + diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/getShiftAmountTy.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/getShiftAmountTy.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/getShiftAmountTy.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/getTargetNodeName.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/getTargetNodeName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ade0fdb0440c27670f94810d2d2933ed722c9eb9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/getTargetNodeName.cpp @@ -0,0 +1,231 @@ +const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const { + switch ((MipsISD::NodeType)Opcode) { + case MipsISD::FIRST_NUMBER: + break; + case MipsISD::JmpLink: + return "MipsISD::JmpLink"; + case MipsISD::TailCall: + return "MipsISD::TailCall"; + case MipsISD::Highest: + return "MipsISD::Highest"; + case MipsISD::Higher: + return "MipsISD::Higher"; + case MipsISD::Hi: + return "MipsISD::Hi"; + case MipsISD::Lo: + return "MipsISD::Lo"; + case MipsISD::GotHi: + return "MipsISD::GotHi"; + case MipsISD::TlsHi: + return "MipsISD::TlsHi"; + case MipsISD::GPRel: + return "MipsISD::GPRel"; + case MipsISD::ThreadPointer: + return "MipsISD::ThreadPointer"; + case MipsISD::Ret: + return "MipsISD::Ret"; + case MipsISD::ERet: + return "MipsISD::ERet"; + case MipsISD::EH_RETURN: + return "MipsISD::EH_RETURN"; + case MipsISD::FMS: + return "MipsISD::FMS"; + case MipsISD::FPBrcond: + return "MipsISD::FPBrcond"; + case MipsISD::FPCmp: + return "MipsISD::FPCmp"; + case MipsISD::FSELECT: + return "MipsISD::FSELECT"; + case MipsISD::MTC1_D64: + return "MipsISD::MTC1_D64"; + case MipsISD::CMovFP_T: + return "MipsISD::CMovFP_T"; + case MipsISD::CMovFP_F: + return "MipsISD::CMovFP_F"; + case MipsISD::TruncIntFP: + return "MipsISD::TruncIntFP"; + case MipsISD::MFHI: + return "MipsISD::MFHI"; + case MipsISD::MFLO: + return "MipsISD::MFLO"; + case MipsISD::MTLOHI: + return "MipsISD::MTLOHI"; + case MipsISD::Mult: + return "MipsISD::Mult"; + case MipsISD::Multu: + return "MipsISD::Multu"; + case MipsISD::MAdd: + return "MipsISD::MAdd"; + case MipsISD::MAddu: + return "MipsISD::MAddu"; + case MipsISD::MSub: + return "MipsISD::MSub"; + case MipsISD::MSubu: + return "MipsISD::MSubu"; + case MipsISD::DivRem: + return "MipsISD::DivRem"; + case MipsISD::DivRemU: + return "MipsISD::DivRemU"; + case MipsISD::DivRem16: + return "MipsISD::DivRem16"; + case MipsISD::DivRemU16: + return "MipsISD::DivRemU16"; + case MipsISD::BuildPairF64: + return "MipsISD::BuildPairF64"; + case MipsISD::ExtractElementF64: + return "MipsISD::ExtractElementF64"; + case MipsISD::Wrapper: + return "MipsISD::Wrapper"; + case MipsISD::DynAlloc: + return "MipsISD::DynAlloc"; + case MipsISD::Sync: + return "MipsISD::Sync"; + case MipsISD::Ext: + return "MipsISD::Ext"; + case MipsISD::Ins: + return "MipsISD::Ins"; + case MipsISD::CIns: + return "MipsISD::CIns"; + case MipsISD::LWL: + return "MipsISD::LWL"; + case MipsISD::LWR: + return "MipsISD::LWR"; + case MipsISD::SWL: + return "MipsISD::SWL"; + case MipsISD::SWR: + return "MipsISD::SWR"; + case MipsISD::LDL: + return "MipsISD::LDL"; + case MipsISD::LDR: + return "MipsISD::LDR"; + case MipsISD::SDL: + return "MipsISD::SDL"; + case MipsISD::SDR: + return "MipsISD::SDR"; + case MipsISD::EXTP: + return "MipsISD::EXTP"; + case MipsISD::EXTPDP: + return "MipsISD::EXTPDP"; + case MipsISD::EXTR_S_H: + return "MipsISD::EXTR_S_H"; + case MipsISD::EXTR_W: + return "MipsISD::EXTR_W"; + case MipsISD::EXTR_R_W: + return "MipsISD::EXTR_R_W"; + case MipsISD::EXTR_RS_W: + return "MipsISD::EXTR_RS_W"; + case MipsISD::SHILO: + return "MipsISD::SHILO"; + case MipsISD::MTHLIP: + return "MipsISD::MTHLIP"; + case MipsISD::MULSAQ_S_W_PH: + return "MipsISD::MULSAQ_S_W_PH"; + case MipsISD::MAQ_S_W_PHL: + return "MipsISD::MAQ_S_W_PHL"; + case MipsISD::MAQ_S_W_PHR: + return "MipsISD::MAQ_S_W_PHR"; + case MipsISD::MAQ_SA_W_PHL: + return "MipsISD::MAQ_SA_W_PHL"; + case MipsISD::MAQ_SA_W_PHR: + return "MipsISD::MAQ_SA_W_PHR"; + case MipsISD::DPAU_H_QBL: + return "MipsISD::DPAU_H_QBL"; + case MipsISD::DPAU_H_QBR: + return "MipsISD::DPAU_H_QBR"; + case MipsISD::DPSU_H_QBL: + return "MipsISD::DPSU_H_QBL"; + case MipsISD::DPSU_H_QBR: + return "MipsISD::DPSU_H_QBR"; + case MipsISD::DPAQ_S_W_PH: + return "MipsISD::DPAQ_S_W_PH"; + case MipsISD::DPSQ_S_W_PH: + return "MipsISD::DPSQ_S_W_PH"; + case MipsISD::DPAQ_SA_L_W: + return "MipsISD::DPAQ_SA_L_W"; + case MipsISD::DPSQ_SA_L_W: + return "MipsISD::DPSQ_SA_L_W"; + case MipsISD::DPA_W_PH: + return "MipsISD::DPA_W_PH"; + case MipsISD::DPS_W_PH: + return "MipsISD::DPS_W_PH"; + case MipsISD::DPAQX_S_W_PH: + return "MipsISD::DPAQX_S_W_PH"; + case MipsISD::DPAQX_SA_W_PH: + return "MipsISD::DPAQX_SA_W_PH"; + case MipsISD::DPAX_W_PH: + return "MipsISD::DPAX_W_PH"; + case MipsISD::DPSX_W_PH: + return "MipsISD::DPSX_W_PH"; + case MipsISD::DPSQX_S_W_PH: + return "MipsISD::DPSQX_S_W_PH"; + case MipsISD::DPSQX_SA_W_PH: + return "MipsISD::DPSQX_SA_W_PH"; + case MipsISD::MULSA_W_PH: + return "MipsISD::MULSA_W_PH"; + case MipsISD::MULT: + return "MipsISD::MULT"; + case MipsISD::MULTU: + return "MipsISD::MULTU"; + case MipsISD::MADD_DSP: + return "MipsISD::MADD_DSP"; + case MipsISD::MADDU_DSP: + return "MipsISD::MADDU_DSP"; + case MipsISD::MSUB_DSP: + return "MipsISD::MSUB_DSP"; + case MipsISD::MSUBU_DSP: + return "MipsISD::MSUBU_DSP"; + case MipsISD::SHLL_DSP: + return "MipsISD::SHLL_DSP"; + case MipsISD::SHRA_DSP: + return "MipsISD::SHRA_DSP"; + case MipsISD::SHRL_DSP: + return "MipsISD::SHRL_DSP"; + case MipsISD::SETCC_DSP: + return "MipsISD::SETCC_DSP"; + case MipsISD::SELECT_CC_DSP: + return "MipsISD::SELECT_CC_DSP"; + case MipsISD::VALL_ZERO: + return "MipsISD::VALL_ZERO"; + case MipsISD::VANY_ZERO: + return "MipsISD::VANY_ZERO"; + case MipsISD::VALL_NONZERO: + return "MipsISD::VALL_NONZERO"; + case MipsISD::VANY_NONZERO: + return "MipsISD::VANY_NONZERO"; + case MipsISD::VCEQ: + return "MipsISD::VCEQ"; + case MipsISD::VCLE_S: + return "MipsISD::VCLE_S"; + case MipsISD::VCLE_U: + return "MipsISD::VCLE_U"; + case MipsISD::VCLT_S: + return "MipsISD::VCLT_S"; + case MipsISD::VCLT_U: + return "MipsISD::VCLT_U"; + case MipsISD::VEXTRACT_SEXT_ELT: + return "MipsISD::VEXTRACT_SEXT_ELT"; + case MipsISD::VEXTRACT_ZEXT_ELT: + return "MipsISD::VEXTRACT_ZEXT_ELT"; + case MipsISD::VNOR: + return "MipsISD::VNOR"; + case MipsISD::VSHF: + return "MipsISD::VSHF"; + case MipsISD::SHF: + return "MipsISD::SHF"; + case MipsISD::ILVEV: + return "MipsISD::ILVEV"; + case MipsISD::ILVOD: + return "MipsISD::ILVOD"; + case MipsISD::ILVL: + return "MipsISD::ILVL"; + case MipsISD::ILVR: + return "MipsISD::ILVR"; + case MipsISD::PCKEV: + return "MipsISD::PCKEV"; + case MipsISD::PCKOD: + return "MipsISD::PCKOD"; + case MipsISD::INSVE: + return "MipsISD::INSVE"; + } + return nullptr; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/isLegalAddImmediate.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/isLegalAddImmediate.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/isLegalAddImmediate.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/isLegalAddressingMode.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/isLegalAddressingMode.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bce29b2aa473dfb01a1adc6b39d25eec12f141ab --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/isLegalAddressingMode.cpp @@ -0,0 +1,15 @@ +bool MipsTargetLowering::isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I) const { + if (AM.BaseGV) + return false; + switch (AM.Scale) { + case 0: + break; + case 1: + if (!AM.HasBaseReg) + break; + return false; + default: + return false; + } + return true; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/isLegalICmpImmediate.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/isLegalICmpImmediate.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/ISelLowering/isLegalICmpImmediate.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/SelectionDAGInfo/EmitTargetCodeForMemcpy.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/SelectionDAGInfo/EmitTargetCodeForMemcpy.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/SelectionDAGInfo/EmitTargetCodeForMemcpy.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/SelectionDAGInfo/SelectionDAGInfo.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/SelectionDAGInfo/SelectionDAGInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/SelectionDAGInfo/SelectionDAGInfo.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/SelectionDAGInfo/~SelectionDAGInfo.cpp b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/SelectionDAGInfo/~SelectionDAGInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af18322e32f3dd19579c80e26e4a306ad11e049 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Mips_Code/XCore/Selection/SelectionDAGInfo/~SelectionDAGInfo.cpp @@ -0,0 +1 @@ +None \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/My_Difflib.py b/Scripts/Exp/ForkFlow/My_Difflib.py new file mode 100644 index 0000000000000000000000000000000000000000..3ceacdffbe4737380686ccdaf77361f3de215cd8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/My_Difflib.py @@ -0,0 +1,2096 @@ +""" +Module difflib -- helpers for computing deltas between objects. + +Function get_close_matches(word, possibilities, n=3, cutoff=0.6): + Use SequenceMatcher to return list of the best "good enough" matches. + +Function context_diff(a, b): + For two lists of strings, return a delta in context diff format. + +Function ndiff(a, b): + Return a delta: the difference between `a` and `b` (lists of strings). + +Function restore(delta, which): + Return one of the two sequences that generated an ndiff delta. + +Function unified_diff(a, b): + For two lists of strings, return a delta in unified diff format. + +Class SequenceMatcher: + A flexible class for comparing pairs of sequences of any type. + +Class Differ: + For producing human-readable deltas from sequences of lines of text. + +Class HtmlDiff: + For producing HTML side by side comparison with change highlights. +""" + +__all__ = ['get_close_matches', 'ndiff', 'restore', 'SequenceMatcher', + 'Differ','IS_CHARACTER_JUNK', 'IS_LINE_JUNK', 'context_diff', + 'unified_diff', 'diff_bytes', 'HtmlDiff', 'Match'] + +from heapq import nlargest as _nlargest +from collections import namedtuple as _namedtuple +#from types import GenericAlias + +Match = _namedtuple('Match', 'a b size') + +def _calculate_ratio(matches, length): + if length: + return 2.0 * matches / length + return 1.0 + +class SequenceMatcher: + + """ + SequenceMatcher is a flexible class for comparing pairs of sequences of + any type, so long as the sequence elements are hashable. The basic + algorithm predates, and is a little fancier than, an algorithm + published in the late 1980's by Ratcliff and Obershelp under the + hyperbolic name "gestalt pattern matching". The basic idea is to find + the longest contiguous matching subsequence that contains no "junk" + elements (R-O doesn't address junk). The same idea is then applied + recursively to the pieces of the sequences to the left and to the right + of the matching subsequence. This does not yield minimal edit + sequences, but does tend to yield matches that "look right" to people. + + SequenceMatcher tries to compute a "human-friendly diff" between two + sequences. Unlike e.g. UNIX(tm) diff, the fundamental notion is the + longest *contiguous* & junk-free matching subsequence. That's what + catches peoples' eyes. The Windows(tm) windiff has another interesting + notion, pairing up elements that appear uniquely in each sequence. + That, and the method here, appear to yield more intuitive difference + reports than does diff. This method appears to be the least vulnerable + to synching up on blocks of "junk lines", though (like blank lines in + ordinary text files, or maybe "

" lines in HTML files). That may be + because this is the only method of the 3 that has a *concept* of + "junk" . + + Example, comparing two strings, and considering blanks to be "junk": + + >>> s = SequenceMatcher(lambda x: x == " ", + ... "private Thread currentThread;", + ... "private volatile Thread currentThread;") + >>> + + .ratio() returns a float in [0, 1], measuring the "similarity" of the + sequences. As a rule of thumb, a .ratio() value over 0.6 means the + sequences are close matches: + + >>> print(round(s.ratio(), 3)) + 0.866 + >>> + + If you're only interested in where the sequences match, + .get_matching_blocks() is handy: + + >>> for block in s.get_matching_blocks(): + ... print("a[%d] and b[%d] match for %d elements" % block) + a[0] and b[0] match for 8 elements + a[8] and b[17] match for 21 elements + a[29] and b[38] match for 0 elements + + Note that the last tuple returned by .get_matching_blocks() is always a + dummy, (len(a), len(b), 0), and this is the only case in which the last + tuple element (number of elements matched) is 0. + + If you want to know how to change the first sequence into the second, + use .get_opcodes(): + + >>> for opcode in s.get_opcodes(): + ... print("%6s a[%d:%d] b[%d:%d]" % opcode) + equal a[0:8] b[0:8] + insert a[8:8] b[8:17] + equal a[8:29] b[17:38] + + See the Differ class for a fancy human-friendly file differencer, which + uses SequenceMatcher both to compare sequences of lines, and to compare + sequences of characters within similar (near-matching) lines. + + See also function get_close_matches() in this module, which shows how + simple code building on SequenceMatcher can be used to do useful work. + + Timing: Basic R-O is cubic time worst case and quadratic time expected + case. SequenceMatcher is quadratic time for the worst case and has + expected-case behavior dependent in a complicated way on how many + elements the sequences have in common; best case time is linear. + + Methods: + + __init__(isjunk=None, a='', b='') + Construct a SequenceMatcher. + + set_seqs(a, b) + Set the two sequences to be compared. + + set_seq1(a) + Set the first sequence to be compared. + + set_seq2(b) + Set the second sequence to be compared. + + find_longest_match(alo=0, ahi=None, blo=0, bhi=None) + Find longest matching block in a[alo:ahi] and b[blo:bhi]. + + get_matching_blocks() + Return list of triples describing matching subsequences. + + get_opcodes() + Return list of 5-tuples describing how to turn a into b. + + ratio() + Return a measure of the sequences' similarity (float in [0,1]). + + quick_ratio() + Return an upper bound on .ratio() relatively quickly. + + real_quick_ratio() + Return an upper bound on ratio() very quickly. + """ + + def __init__(self, isjunk=None, a='', b='', autojunk=True): + """Construct a SequenceMatcher. + + Optional arg isjunk is None (the default), or a one-argument + function that takes a sequence element and returns true iff the + element is junk. None is equivalent to passing "lambda x: 0", i.e. + no elements are considered to be junk. For example, pass + lambda x: x in " \\t" + if you're comparing lines as sequences of characters, and don't + want to synch up on blanks or hard tabs. + + Optional arg a is the first of two sequences to be compared. By + default, an empty string. The elements of a must be hashable. See + also .set_seqs() and .set_seq1(). + + Optional arg b is the second of two sequences to be compared. By + default, an empty string. The elements of b must be hashable. See + also .set_seqs() and .set_seq2(). + + Optional arg autojunk should be set to False to disable the + "automatic junk heuristic" that treats popular elements as junk + (see module documentation for more information). + """ + + # Members: + # a + # first sequence + # b + # second sequence; differences are computed as "what do + # we need to do to 'a' to change it into 'b'?" + # b2j + # for x in b, b2j[x] is a list of the indices (into b) + # at which x appears; junk and popular elements do not appear + # fullbcount + # for x in b, fullbcount[x] == the number of times x + # appears in b; only materialized if really needed (used + # only for computing quick_ratio()) + # matching_blocks + # a list of (i, j, k) triples, where a[i:i+k] == b[j:j+k]; + # ascending & non-overlapping in i and in j; terminated by + # a dummy (len(a), len(b), 0) sentinel + # opcodes + # a list of (tag, i1, i2, j1, j2) tuples, where tag is + # one of + # 'replace' a[i1:i2] should be replaced by b[j1:j2] + # 'delete' a[i1:i2] should be deleted + # 'insert' b[j1:j2] should be inserted + # 'equal' a[i1:i2] == b[j1:j2] + # isjunk + # a user-supplied function taking a sequence element and + # returning true iff the element is "junk" -- this has + # subtle but helpful effects on the algorithm, which I'll + # get around to writing up someday <0.9 wink>. + # DON'T USE! Only __chain_b uses this. Use "in self.bjunk". + # bjunk + # the items in b for which isjunk is True. + # bpopular + # nonjunk items in b treated as junk by the heuristic (if used). + + self.isjunk = isjunk + self.a = self.b = None + self.autojunk = autojunk + self.set_seqs(a, b) + + def set_seqs(self, a, b): + """Set the two sequences to be compared. + + >>> s = SequenceMatcher() + >>> s.set_seqs("abcd", "bcde") + >>> s.ratio() + 0.75 + """ + + self.set_seq1(a) + self.set_seq2(b) + + def set_seq1(self, a): + """Set the first sequence to be compared. + + The second sequence to be compared is not changed. + + >>> s = SequenceMatcher(None, "abcd", "bcde") + >>> s.ratio() + 0.75 + >>> s.set_seq1("bcde") + >>> s.ratio() + 1.0 + >>> + + SequenceMatcher computes and caches detailed information about the + second sequence, so if you want to compare one sequence S against + many sequences, use .set_seq2(S) once and call .set_seq1(x) + repeatedly for each of the other sequences. + + See also set_seqs() and set_seq2(). + """ + + if a is self.a: + return + self.a = a + self.matching_blocks = self.opcodes = None + + def set_seq2(self, b): + """Set the second sequence to be compared. + + The first sequence to be compared is not changed. + + >>> s = SequenceMatcher(None, "abcd", "bcde") + >>> s.ratio() + 0.75 + >>> s.set_seq2("abcd") + >>> s.ratio() + 1.0 + >>> + + SequenceMatcher computes and caches detailed information about the + second sequence, so if you want to compare one sequence S against + many sequences, use .set_seq2(S) once and call .set_seq1(x) + repeatedly for each of the other sequences. + + See also set_seqs() and set_seq1(). + """ + + if b is self.b: + return + self.b = b + self.matching_blocks = self.opcodes = None + self.fullbcount = None + self.__chain_b() + + # For each element x in b, set b2j[x] to a list of the indices in + # b where x appears; the indices are in increasing order; note that + # the number of times x appears in b is len(b2j[x]) ... + # when self.isjunk is defined, junk elements don't show up in this + # map at all, which stops the central find_longest_match method + # from starting any matching block at a junk element ... + # b2j also does not contain entries for "popular" elements, meaning + # elements that account for more than 1 + 1% of the total elements, and + # when the sequence is reasonably large (>= 200 elements); this can + # be viewed as an adaptive notion of semi-junk, and yields an enormous + # speedup when, e.g., comparing program files with hundreds of + # instances of "return NULL;" ... + # note that this is only called when b changes; so for cross-product + # kinds of matches, it's best to call set_seq2 once, then set_seq1 + # repeatedly + + def __chain_b(self): + # Because isjunk is a user-defined (not C) function, and we test + # for junk a LOT, it's important to minimize the number of calls. + # Before the tricks described here, __chain_b was by far the most + # time-consuming routine in the whole module! If anyone sees + # Jim Roskind, thank him again for profile.py -- I never would + # have guessed that. + # The first trick is to build b2j ignoring the possibility + # of junk. I.e., we don't call isjunk at all yet. Throwing + # out the junk later is much cheaper than building b2j "right" + # from the start. + b = self.b + self.b2j = b2j = {} + + for i, elt in enumerate(b): + indices = b2j.setdefault(elt, []) + indices.append(i) + + # Purge junk elements + self.bjunk = junk = set() + isjunk = self.isjunk + if isjunk: + for elt in b2j.keys(): + if isjunk(elt): + junk.add(elt) + for elt in junk: # separate loop avoids separate list of keys + del b2j[elt] + + # Purge popular elements that are not junk + self.bpopular = popular = set() + n = len(b) + if self.autojunk and n >= 200: + ntest = n // 100 + 1 + for elt, idxs in b2j.items(): + if len(idxs) > ntest: + popular.add(elt) + for elt in popular: # ditto; as fast for 1% deletion + del b2j[elt] + + def find_longest_match(self, alo=0, ahi=None, blo=0, bhi=None): + """Find longest matching block in a[alo:ahi] and b[blo:bhi]. + + By default it will find the longest match in the entirety of a and b. + + If isjunk is not defined: + + Return (i,j,k) such that a[i:i+k] is equal to b[j:j+k], where + alo <= i <= i+k <= ahi + blo <= j <= j+k <= bhi + and for all (i',j',k') meeting those conditions, + k >= k' + i <= i' + and if i == i', j <= j' + + In other words, of all maximal matching blocks, return one that + starts earliest in a, and of all those maximal matching blocks that + start earliest in a, return the one that starts earliest in b. + + >>> s = SequenceMatcher(None, " abcd", "abcd abcd") + >>> s.find_longest_match(0, 5, 0, 9) + Match(a=0, b=4, size=5) + + If isjunk is defined, first the longest matching block is + determined as above, but with the additional restriction that no + junk element appears in the block. Then that block is extended as + far as possible by matching (only) junk elements on both sides. So + the resulting block never matches on junk except as identical junk + happens to be adjacent to an "interesting" match. + + Here's the same example as before, but considering blanks to be + junk. That prevents " abcd" from matching the " abcd" at the tail + end of the second sequence directly. Instead only the "abcd" can + match, and matches the leftmost "abcd" in the second sequence: + + >>> s = SequenceMatcher(lambda x: x==" ", " abcd", "abcd abcd") + >>> s.find_longest_match(0, 5, 0, 9) + Match(a=1, b=0, size=4) + + If no blocks match, return (alo, blo, 0). + + >>> s = SequenceMatcher(None, "ab", "c") + >>> s.find_longest_match(0, 2, 0, 1) + Match(a=0, b=0, size=0) + """ + + # CAUTION: stripping common prefix or suffix would be incorrect. + # E.g., + # ab + # acab + # Longest matching block is "ab", but if common prefix is + # stripped, it's "a" (tied with "b"). UNIX(tm) diff does so + # strip, so ends up claiming that ab is changed to acab by + # inserting "ca" in the middle. That's minimal but unintuitive: + # "it's obvious" that someone inserted "ac" at the front. + # Windiff ends up at the same place as diff, but by pairing up + # the unique 'b's and then matching the first two 'a's. + + a, b, b2j, isbjunk = self.a, self.b, self.b2j, self.bjunk.__contains__ + if ahi is None: + ahi = len(a) + if bhi is None: + bhi = len(b) + besti, bestj, bestsize = alo, blo, 0 + # find longest junk-free match + # during an iteration of the loop, j2len[j] = length of longest + # junk-free match ending with a[i-1] and b[j] + j2len = {} + nothing = [] + for i in range(alo, ahi): + # look at all instances of a[i] in b; note that because + # b2j has no junk keys, the loop is skipped if a[i] is junk + j2lenget = j2len.get + newj2len = {} + for j in b2j.get(a[i], nothing): + # a[i] matches b[j] + if j < blo: + continue + if j >= bhi: + break + k = newj2len[j] = j2lenget(j-1, 0) + 1 + if k > bestsize: + besti, bestj, bestsize = i-k+1, j-k+1, k + j2len = newj2len + + # Extend the best by non-junk elements on each end. In particular, + # "popular" non-junk elements aren't in b2j, which greatly speeds + # the inner loop above, but also means "the best" match so far + # doesn't contain any junk *or* popular non-junk elements. + while besti > alo and bestj > blo and \ + not isbjunk(b[bestj-1]) and \ + a[besti-1] == b[bestj-1]: + besti, bestj, bestsize = besti-1, bestj-1, bestsize+1 + while besti+bestsize < ahi and bestj+bestsize < bhi and \ + not isbjunk(b[bestj+bestsize]) and \ + a[besti+bestsize] == b[bestj+bestsize]: + bestsize += 1 + + # Now that we have a wholly interesting match (albeit possibly + # empty!), we may as well suck up the matching junk on each + # side of it too. Can't think of a good reason not to, and it + # saves post-processing the (possibly considerable) expense of + # figuring out what to do with it. In the case of an empty + # interesting match, this is clearly the right thing to do, + # because no other kind of match is possible in the regions. + while besti > alo and bestj > blo and \ + isbjunk(b[bestj-1]) and \ + a[besti-1] == b[bestj-1]: + besti, bestj, bestsize = besti-1, bestj-1, bestsize+1 + while besti+bestsize < ahi and bestj+bestsize < bhi and \ + isbjunk(b[bestj+bestsize]) and \ + a[besti+bestsize] == b[bestj+bestsize]: + bestsize = bestsize + 1 + + return Match(besti, bestj, bestsize) + + def get_matching_blocks(self): + """Return list of triples describing matching subsequences. + + Each triple is of the form (i, j, n), and means that + a[i:i+n] == b[j:j+n]. The triples are monotonically increasing in + i and in j. New in Python 2.5, it's also guaranteed that if + (i, j, n) and (i', j', n') are adjacent triples in the list, and + the second is not the last triple in the list, then i+n != i' or + j+n != j'. IOW, adjacent triples never describe adjacent equal + blocks. + + The last triple is a dummy, (len(a), len(b), 0), and is the only + triple with n==0. + + >>> s = SequenceMatcher(None, "abxcd", "abcd") + >>> list(s.get_matching_blocks()) + [Match(a=0, b=0, size=2), Match(a=3, b=2, size=2), Match(a=5, b=4, size=0)] + """ + + if self.matching_blocks is not None: + return self.matching_blocks + la, lb = len(self.a), len(self.b) + + # This is most naturally expressed as a recursive algorithm, but + # at least one user bumped into extreme use cases that exceeded + # the recursion limit on their box. So, now we maintain a list + # ('queue`) of blocks we still need to look at, and append partial + # results to `matching_blocks` in a loop; the matches are sorted + # at the end. + queue = [(0, la, 0, lb)] + matching_blocks = [] + while queue: + alo, ahi, blo, bhi = queue.pop() + i, j, k = x = self.find_longest_match(alo, ahi, blo, bhi) + # a[alo:i] vs b[blo:j] unknown + # a[i:i+k] same as b[j:j+k] + # a[i+k:ahi] vs b[j+k:bhi] unknown + if k: # if k is 0, there was no matching block + matching_blocks.append(x) + if alo < i and blo < j: + queue.append((alo, i, blo, j)) + if i+k < ahi and j+k < bhi: + queue.append((i+k, ahi, j+k, bhi)) + matching_blocks.sort() + + # It's possible that we have adjacent equal blocks in the + # matching_blocks list now. Starting with 2.5, this code was added + # to collapse them. + i1 = j1 = k1 = 0 + non_adjacent = [] + for i2, j2, k2 in matching_blocks: + # Is this block adjacent to i1, j1, k1? + if i1 + k1 == i2 and j1 + k1 == j2: + # Yes, so collapse them -- this just increases the length of + # the first block by the length of the second, and the first + # block so lengthened remains the block to compare against. + k1 += k2 + else: + # Not adjacent. Remember the first block (k1==0 means it's + # the dummy we started with), and make the second block the + # new block to compare against. + if k1: + non_adjacent.append((i1, j1, k1)) + i1, j1, k1 = i2, j2, k2 + if k1: + non_adjacent.append((i1, j1, k1)) + + non_adjacent.append( (la, lb, 0) ) + self.matching_blocks = list(map(Match._make, non_adjacent)) + return self.matching_blocks + + def get_opcodes(self): + """Return list of 5-tuples describing how to turn a into b. + + Each tuple is of the form (tag, i1, i2, j1, j2). The first tuple + has i1 == j1 == 0, and remaining tuples have i1 == the i2 from the + tuple preceding it, and likewise for j1 == the previous j2. + + The tags are strings, with these meanings: + + 'replace': a[i1:i2] should be replaced by b[j1:j2] + 'delete': a[i1:i2] should be deleted. + Note that j1==j2 in this case. + 'insert': b[j1:j2] should be inserted at a[i1:i1]. + Note that i1==i2 in this case. + 'equal': a[i1:i2] == b[j1:j2] + + >>> a = "qabxcd" + >>> b = "abycdf" + >>> s = SequenceMatcher(None, a, b) + >>> for tag, i1, i2, j1, j2 in s.get_opcodes(): + ... print(("%7s a[%d:%d] (%s) b[%d:%d] (%s)" % + ... (tag, i1, i2, a[i1:i2], j1, j2, b[j1:j2]))) + delete a[0:1] (q) b[0:0] () + equal a[1:3] (ab) b[0:2] (ab) + replace a[3:4] (x) b[2:3] (y) + equal a[4:6] (cd) b[3:5] (cd) + insert a[6:6] () b[5:6] (f) + """ + + if self.opcodes is not None: + return self.opcodes + i = j = 0 + self.opcodes = answer = [] + for ai, bj, size in self.get_matching_blocks(): + # invariant: we've pumped out correct diffs to change + # a[:i] into b[:j], and the next matching block is + # a[ai:ai+size] == b[bj:bj+size]. So we need to pump + # out a diff to change a[i:ai] into b[j:bj], pump out + # the matching block, and move (i,j) beyond the match + tag = '' + if i < ai and j < bj: + tag = 'replace' + elif i < ai: + tag = 'delete' + elif j < bj: + tag = 'insert' + if tag: + answer.append( (tag, i, ai, j, bj) ) + i, j = ai+size, bj+size + # the list of matching blocks is terminated by a + # sentinel with size 0 + if size: + answer.append( ('equal', ai, i, bj, j) ) + return answer + + def get_grouped_opcodes(self, n=3): + """ Isolate change clusters by eliminating ranges with no changes. + + Return a generator of groups with up to n lines of context. + Each group is in the same format as returned by get_opcodes(). + + >>> from pprint import pprint + >>> a = list(map(str, range(1,40))) + >>> b = a[:] + >>> b[8:8] = ['i'] # Make an insertion + >>> b[20] += 'x' # Make a replacement + >>> b[23:28] = [] # Make a deletion + >>> b[30] += 'y' # Make another replacement + >>> pprint(list(SequenceMatcher(None,a,b).get_grouped_opcodes())) + [[('equal', 5, 8, 5, 8), ('insert', 8, 8, 8, 9), ('equal', 8, 11, 9, 12)], + [('equal', 16, 19, 17, 20), + ('replace', 19, 20, 20, 21), + ('equal', 20, 22, 21, 23), + ('delete', 22, 27, 23, 23), + ('equal', 27, 30, 23, 26)], + [('equal', 31, 34, 27, 30), + ('replace', 34, 35, 30, 31), + ('equal', 35, 38, 31, 34)]] + """ + + codes = self.get_opcodes() + if not codes: + codes = [("equal", 0, 1, 0, 1)] + # Fixup leading and trailing groups if they show no changes. + if codes[0][0] == 'equal': + tag, i1, i2, j1, j2 = codes[0] + codes[0] = tag, max(i1, i2-n), i2, max(j1, j2-n), j2 + if codes[-1][0] == 'equal': + tag, i1, i2, j1, j2 = codes[-1] + codes[-1] = tag, i1, min(i2, i1+n), j1, min(j2, j1+n) + + nn = n + n + group = [] + for tag, i1, i2, j1, j2 in codes: + # End the current group and start a new one whenever + # there is a large range with no changes. + if tag == 'equal' and i2-i1 > nn: + group.append((tag, i1, min(i2, i1+n), j1, min(j2, j1+n))) + yield group + group = [] + i1, j1 = max(i1, i2-n), max(j1, j2-n) + group.append((tag, i1, i2, j1 ,j2)) + if group and not (len(group)==1 and group[0][0] == 'equal'): + yield group + + def ratio(self): + """Return a measure of the sequences' similarity (float in [0,1]). + + Where T is the total number of elements in both sequences, and + M is the number of matches, this is 2.0*M / T. + Note that this is 1 if the sequences are identical, and 0 if + they have nothing in common. + + .ratio() is expensive to compute if you haven't already computed + .get_matching_blocks() or .get_opcodes(), in which case you may + want to try .quick_ratio() or .real_quick_ratio() first to get an + upper bound. + + >>> s = SequenceMatcher(None, "abcd", "bcde") + >>> s.ratio() + 0.75 + >>> s.quick_ratio() + 0.75 + >>> s.real_quick_ratio() + 1.0 + """ + + matches = sum(triple[-1] for triple in self.get_matching_blocks()) + return _calculate_ratio(matches, len(self.a) + len(self.b)) + + def quick_ratio(self): + """Return an upper bound on ratio() relatively quickly. + + This isn't defined beyond that it is an upper bound on .ratio(), and + is faster to compute. + """ + + # viewing a and b as multisets, set matches to the cardinality + # of their intersection; this counts the number of matches + # without regard to order, so is clearly an upper bound + if self.fullbcount is None: + self.fullbcount = fullbcount = {} + for elt in self.b: + fullbcount[elt] = fullbcount.get(elt, 0) + 1 + fullbcount = self.fullbcount + # avail[x] is the number of times x appears in 'b' less the + # number of times we've seen it in 'a' so far ... kinda + avail = {} + availhas, matches = avail.__contains__, 0 + for elt in self.a: + if availhas(elt): + numb = avail[elt] + else: + numb = fullbcount.get(elt, 0) + avail[elt] = numb - 1 + if numb > 0: + matches = matches + 1 + return _calculate_ratio(matches, len(self.a) + len(self.b)) + + def real_quick_ratio(self): + """Return an upper bound on ratio() very quickly. + + This isn't defined beyond that it is an upper bound on .ratio(), and + is faster to compute than either .ratio() or .quick_ratio(). + """ + + la, lb = len(self.a), len(self.b) + # can't have more matches than the number of elements in the + # shorter sequence + return _calculate_ratio(min(la, lb), la + lb) + + #__class_getitem__ = classmethod(GenericAlias) + + +def get_close_matches(word, possibilities, n=3, cutoff=0.6): + """Use SequenceMatcher to return list of the best "good enough" matches. + + word is a sequence for which close matches are desired (typically a + string). + + possibilities is a list of sequences against which to match word + (typically a list of strings). + + Optional arg n (default 3) is the maximum number of close matches to + return. n must be > 0. + + Optional arg cutoff (default 0.6) is a float in [0, 1]. Possibilities + that don't score at least that similar to word are ignored. + + The best (no more than n) matches among the possibilities are returned + in a list, sorted by similarity score, most similar first. + + >>> get_close_matches("appel", ["ape", "apple", "peach", "puppy"]) + ['apple', 'ape'] + >>> import keyword as _keyword + >>> get_close_matches("wheel", _keyword.kwlist) + ['while'] + >>> get_close_matches("Apple", _keyword.kwlist) + [] + >>> get_close_matches("accept", _keyword.kwlist) + ['except'] + """ + + if not n > 0: + raise ValueError("n must be > 0: %r" % (n,)) + if not 0.0 <= cutoff <= 1.0: + raise ValueError("cutoff must be in [0.0, 1.0]: %r" % (cutoff,)) + result = [] + s = SequenceMatcher() + s.set_seq2(word) + for x in possibilities: + s.set_seq1(x) + if s.real_quick_ratio() >= cutoff and \ + s.quick_ratio() >= cutoff and \ + s.ratio() >= cutoff: + result.append((s.ratio(), x)) + + # Move the best scorers to head of list + result = _nlargest(n, result) + # Strip scores for the best n matches + return [x for score, x in result] + + +def _keep_original_ws(s, tag_s): + """Replace whitespace with the original whitespace characters in `s`""" + return ''.join( + c if tag_c == " " and c.isspace() else tag_c + for c, tag_c in zip(s, tag_s) + ) + + + +class Differ: + r""" + Differ is a class for comparing sequences of lines of text, and + producing human-readable differences or deltas. Differ uses + SequenceMatcher both to compare sequences of lines, and to compare + sequences of characters within similar (near-matching) lines. + + Each line of a Differ delta begins with a two-letter code: + + '- ' line unique to sequence 1 + '+ ' line unique to sequence 2 + ' ' line common to both sequences + '? ' line not present in either input sequence + + Lines beginning with '? ' attempt to guide the eye to intraline + differences, and were not present in either input sequence. These lines + can be confusing if the sequences contain tab characters. + + Note that Differ makes no claim to produce a *minimal* diff. To the + contrary, minimal diffs are often counter-intuitive, because they synch + up anywhere possible, sometimes accidental matches 100 pages apart. + Restricting synch points to contiguous matches preserves some notion of + locality, at the occasional cost of producing a longer diff. + + Example: Comparing two texts. + + First we set up the texts, sequences of individual single-line strings + ending with newlines (such sequences can also be obtained from the + `readlines()` method of file-like objects): + + >>> text1 = ''' 1. Beautiful is better than ugly. + ... 2. Explicit is better than implicit. + ... 3. Simple is better than complex. + ... 4. Complex is better than complicated. + ... '''.splitlines(keepends=True) + >>> len(text1) + 4 + >>> text1[0][-1] + '\n' + >>> text2 = ''' 1. Beautiful is better than ugly. + ... 3. Simple is better than complex. + ... 4. Complicated is better than complex. + ... 5. Flat is better than nested. + ... '''.splitlines(keepends=True) + + Next we instantiate a Differ object: + + >>> d = Differ() + + Note that when instantiating a Differ object we may pass functions to + filter out line and character 'junk'. See Differ.__init__ for details. + + Finally, we compare the two: + + >>> result = list(d.compare(text1, text2)) + + 'result' is a list of strings, so let's pretty-print it: + + >>> from pprint import pprint as _pprint + >>> _pprint(result) + [' 1. Beautiful is better than ugly.\n', + '- 2. Explicit is better than implicit.\n', + '- 3. Simple is better than complex.\n', + '+ 3. Simple is better than complex.\n', + '? ++\n', + '- 4. Complex is better than complicated.\n', + '? ^ ---- ^\n', + '+ 4. Complicated is better than complex.\n', + '? ++++ ^ ^\n', + '+ 5. Flat is better than nested.\n'] + + As a single multi-line string it looks like this: + + >>> print(''.join(result), end="") + 1. Beautiful is better than ugly. + - 2. Explicit is better than implicit. + - 3. Simple is better than complex. + + 3. Simple is better than complex. + ? ++ + - 4. Complex is better than complicated. + ? ^ ---- ^ + + 4. Complicated is better than complex. + ? ++++ ^ ^ + + 5. Flat is better than nested. + + Methods: + + __init__(linejunk=None, charjunk=None) + Construct a text differencer, with optional filters. + + compare(a, b) + Compare two sequences of lines; generate the resulting delta. + """ + + def __init__(self, linejunk=None, charjunk=None): + """ + Construct a text differencer, with optional filters. + + The two optional keyword parameters are for filter functions: + + - `linejunk`: A function that should accept a single string argument, + and return true iff the string is junk. The module-level function + `IS_LINE_JUNK` may be used to filter out lines without visible + characters, except for at most one splat ('#'). It is recommended + to leave linejunk None; the underlying SequenceMatcher class has + an adaptive notion of "noise" lines that's better than any static + definition the author has ever been able to craft. + + - `charjunk`: A function that should accept a string of length 1. The + module-level function `IS_CHARACTER_JUNK` may be used to filter out + whitespace characters (a blank or tab; **note**: bad idea to include + newline in this!). Use of IS_CHARACTER_JUNK is recommended. + """ + + self.linejunk = linejunk + self.charjunk = charjunk + + def compare(self, a, b): + r""" + Compare two sequences of lines; generate the resulting delta. + + Each sequence must contain individual single-line strings ending with + newlines. Such sequences can be obtained from the `readlines()` method + of file-like objects. The delta generated also consists of newline- + terminated strings, ready to be printed as-is via the writeline() + method of a file-like object. + + Example: + + >>> print(''.join(Differ().compare('one\ntwo\nthree\n'.splitlines(True), + ... 'ore\ntree\nemu\n'.splitlines(True))), + ... end="") + - one + ? ^ + + ore + ? ^ + - two + - three + ? - + + tree + + emu + """ + + cruncher = SequenceMatcher(self.linejunk, a, b) + for tag, alo, ahi, blo, bhi in cruncher.get_opcodes(): + if tag == 'replace': + g = self._fancy_replace(a, alo, ahi, b, blo, bhi) + elif tag == 'delete': + g = self._dump('-', a, alo, ahi) + elif tag == 'insert': + g = self._dump('+', b, blo, bhi) + elif tag == 'equal': + g = self._dump(' ', a, alo, ahi) + else: + raise ValueError('unknown tag %r' % (tag,)) + + yield from g + + def _dump(self, tag, x, lo, hi): + """Generate comparison results for a same-tagged range.""" + for i in range(lo, hi): + yield '%s %s' % (tag, x[i]) + + def _plain_replace(self, a, alo, ahi, b, blo, bhi): + assert alo < ahi and blo < bhi + # dump the shorter block first -- reduces the burden on short-term + # memory if the blocks are of very different sizes + if bhi - blo < ahi - alo: + first = self._dump('+', b, blo, bhi) + second = self._dump('-', a, alo, ahi) + else: + first = self._dump('-', a, alo, ahi) + second = self._dump('+', b, blo, bhi) + + for g in first, second: + yield from g + + def _fancy_replace(self, a, alo, ahi, b, blo, bhi): + r""" + When replacing one block of lines with another, search the blocks + for *similar* lines; the best-matching pair (if any) is used as a + synch point, and intraline difference marking is done on the + similar pair. Lots of work, but often worth it. + + Example: + + >>> d = Differ() + >>> results = d._fancy_replace(['abcDefghiJkl\n'], 0, 1, + ... ['abcdefGhijkl\n'], 0, 1) + >>> print(''.join(results), end="") + - abcDefghiJkl + ? ^ ^ ^ + + abcdefGhijkl + ? ^ ^ ^ + """ + + # don't synch up unless the lines have a similarity score of at + # least cutoff; best_ratio tracks the best score seen so far + best_ratio, cutoff = 0.1, 0.5 + cruncher = SequenceMatcher(self.charjunk) + eqi, eqj = None, None # 1st indices of equal lines (if any) + + # search for the pair that matches best without being identical + # (identical lines must be junk lines, & we don't want to synch up + # on junk -- unless we have to) + for j in range(blo, bhi): + bj = b[j] + cruncher.set_seq2(bj) + for i in range(alo, ahi): + ai = a[i] + if ai == bj: + if eqi is None: + eqi, eqj = i, j + continue + cruncher.set_seq1(ai) + # computing similarity is expensive, so use the quick + # upper bounds first -- have seen this speed up messy + # compares by a factor of 3. + # note that ratio() is only expensive to compute the first + # time it's called on a sequence pair; the expensive part + # of the computation is cached by cruncher + if cruncher.real_quick_ratio() > best_ratio and \ + cruncher.quick_ratio() > best_ratio and \ + cruncher.ratio() > best_ratio: + best_ratio, best_i, best_j = cruncher.ratio(), i, j + if best_ratio < cutoff: + # no non-identical "pretty close" pair + if eqi is None: + # no identical pair either -- treat it as a straight replace + yield from self._plain_replace(a, alo, ahi, b, blo, bhi) + return + # no close pair, but an identical pair -- synch up on that + best_i, best_j, best_ratio = eqi, eqj, 1.0 + else: + # there's a close pair, so forget the identical pair (if any) + eqi = None + + # a[best_i] very similar to b[best_j]; eqi is None iff they're not + # identical + + # pump out diffs from before the synch point + yield from self._fancy_helper(a, alo, best_i, b, blo, best_j) + + # do intraline marking on the synch pair + aelt, belt = a[best_i], b[best_j] + if eqi is None: + # pump out a '-', '?', '+', '?' quad for the synched lines + atags = btags = "" + cruncher.set_seqs(aelt, belt) + for tag, ai1, ai2, bj1, bj2 in cruncher.get_opcodes(): + la, lb = ai2 - ai1, bj2 - bj1 + if tag == 'replace': + atags += '^' * la + btags += '^' * lb + elif tag == 'delete': + atags += '-' * la + elif tag == 'insert': + btags += '+' * lb + elif tag == 'equal': + atags += ' ' * la + btags += ' ' * lb + else: + raise ValueError('unknown tag %r' % (tag,)) + yield from self._qformat(aelt, belt, atags, btags) + else: + # the synch pair is identical + yield ' ' + aelt + + # pump out diffs from after the synch point + yield from self._fancy_helper(a, best_i+1, ahi, b, best_j+1, bhi) + + def _fancy_helper(self, a, alo, ahi, b, blo, bhi): + g = [] + if alo < ahi: + if blo < bhi: + g = self._fancy_replace(a, alo, ahi, b, blo, bhi) + else: + g = self._dump('-', a, alo, ahi) + elif blo < bhi: + g = self._dump('+', b, blo, bhi) + + yield from g + + def _qformat(self, aline, bline, atags, btags): + r""" + Format "?" output and deal with tabs. + + Example: + + >>> d = Differ() + >>> results = d._qformat('\tabcDefghiJkl\n', '\tabcdefGhijkl\n', + ... ' ^ ^ ^ ', ' ^ ^ ^ ') + >>> for line in results: print(repr(line)) + ... + '- \tabcDefghiJkl\n' + '? \t ^ ^ ^\n' + '+ \tabcdefGhijkl\n' + '? \t ^ ^ ^\n' + """ + atags = _keep_original_ws(aline, atags).rstrip() + btags = _keep_original_ws(bline, btags).rstrip() + + yield "- " + aline + if atags: + yield f"? {atags}\n" + + yield "+ " + bline + if btags: + yield f"? {btags}\n" + +# With respect to junk, an earlier version of ndiff simply refused to +# *start* a match with a junk element. The result was cases like this: +# before: private Thread currentThread; +# after: private volatile Thread currentThread; +# If you consider whitespace to be junk, the longest contiguous match +# not starting with junk is "e Thread currentThread". So ndiff reported +# that "e volatil" was inserted between the 't' and the 'e' in "private". +# While an accurate view, to people that's absurd. The current version +# looks for matching blocks that are entirely junk-free, then extends the +# longest one of those as far as possible but only with matching junk. +# So now "currentThread" is matched, then extended to suck up the +# preceding blank; then "private" is matched, and extended to suck up the +# following blank; then "Thread" is matched; and finally ndiff reports +# that "volatile " was inserted before "Thread". The only quibble +# remaining is that perhaps it was really the case that " volatile" +# was inserted after "private". I can live with that . + +import re + +def IS_LINE_JUNK(line, pat=re.compile(r"\s*(?:#\s*)?$").match): + r""" + Return True for ignorable line: iff `line` is blank or contains a single '#'. + + Examples: + + >>> IS_LINE_JUNK('\n') + True + >>> IS_LINE_JUNK(' # \n') + True + >>> IS_LINE_JUNK('hello\n') + False + """ + + return pat(line) is not None + +def IS_CHARACTER_JUNK(ch, ws=" \t"): + r""" + Return True for ignorable character: iff `ch` is a space or tab. + + Examples: + + >>> IS_CHARACTER_JUNK(' ') + True + >>> IS_CHARACTER_JUNK('\t') + True + >>> IS_CHARACTER_JUNK('\n') + False + >>> IS_CHARACTER_JUNK('x') + False + """ + + return ch in ws + + +######################################################################## +### Unified Diff +######################################################################## + +def _format_range_unified(start, stop): + 'Convert range to the "ed" format' + # Per the diff spec at http://www.unix.org/single_unix_specification/ + beginning = start + 1 # lines start numbering with one + length = stop - start + if length == 1: + return '{}'.format(beginning) + if not length: + beginning -= 1 # empty ranges begin at line just before the range + return '{},{}'.format(beginning, length) + +def unified_diff(a, b, fromfile='', tofile='', fromfiledate='', + tofiledate='', n=3, lineterm='\n'): + r""" + Compare two sequences of lines; generate the delta as a unified diff. + + Unified diffs are a compact way of showing line changes and a few + lines of context. The number of context lines is set by 'n' which + defaults to three. + + By default, the diff control lines (those with ---, +++, or @@) are + created with a trailing newline. This is helpful so that inputs + created from file.readlines() result in diffs that are suitable for + file.writelines() since both the inputs and outputs have trailing + newlines. + + For inputs that do not have trailing newlines, set the lineterm + argument to "" so that the output will be uniformly newline free. + + The unidiff format normally has a header for filenames and modification + times. Any or all of these may be specified using strings for + 'fromfile', 'tofile', 'fromfiledate', and 'tofiledate'. + The modification times are normally expressed in the ISO 8601 format. + + Example: + + >>> for line in unified_diff('one two three four'.split(), + ... 'zero one tree four'.split(), 'Original', 'Current', + ... '2005-01-26 23:30:50', '2010-04-02 10:20:52', + ... lineterm=''): + ... print(line) # doctest: +NORMALIZE_WHITESPACE + --- Original 2005-01-26 23:30:50 + +++ Current 2010-04-02 10:20:52 + @@ -1,4 +1,4 @@ + +zero + one + -two + -three + +tree + four + """ + + _check_types(a, b, fromfile, tofile, fromfiledate, tofiledate, lineterm) + started = False + for group in SequenceMatcher(None,a,b).get_grouped_opcodes(n): + if not started: + started = True + fromdate = '\t{}'.format(fromfiledate) if fromfiledate else '' + todate = '\t{}'.format(tofiledate) if tofiledate else '' + yield '--- {}{}{}'.format(fromfile, fromdate, lineterm) + yield '+++ {}{}{}'.format(tofile, todate, lineterm) + + first, last = group[0], group[-1] + file1_range = _format_range_unified(first[1], last[2]) + file2_range = _format_range_unified(first[3], last[4]) + yield '@@ -{} +{} @@{}'.format(file1_range, file2_range, lineterm) + + for tag, i1, i2, j1, j2 in group: + if tag == 'equal': + for line in a[i1:i2]: + yield ' ' + line + continue + if tag in {'replace', 'delete'}: + for line in a[i1:i2]: + yield '-' + line + if tag in {'replace', 'insert'}: + for line in b[j1:j2]: + yield '+' + line + + +######################################################################## +### Context Diff +######################################################################## + +def _format_range_context(start, stop): + 'Convert range to the "ed" format' + # Per the diff spec at http://www.unix.org/single_unix_specification/ + beginning = start + 1 # lines start numbering with one + length = stop - start + if not length: + beginning -= 1 # empty ranges begin at line just before the range + if length <= 1: + return '{}'.format(beginning) + return '{},{}'.format(beginning, beginning + length - 1) + +# See http://www.unix.org/single_unix_specification/ +def context_diff(a, b, fromfile='', tofile='', + fromfiledate='', tofiledate='', n=3, lineterm='\n'): + r""" + Compare two sequences of lines; generate the delta as a context diff. + + Context diffs are a compact way of showing line changes and a few + lines of context. The number of context lines is set by 'n' which + defaults to three. + + By default, the diff control lines (those with *** or ---) are + created with a trailing newline. This is helpful so that inputs + created from file.readlines() result in diffs that are suitable for + file.writelines() since both the inputs and outputs have trailing + newlines. + + For inputs that do not have trailing newlines, set the lineterm + argument to "" so that the output will be uniformly newline free. + + The context diff format normally has a header for filenames and + modification times. Any or all of these may be specified using + strings for 'fromfile', 'tofile', 'fromfiledate', and 'tofiledate'. + The modification times are normally expressed in the ISO 8601 format. + If not specified, the strings default to blanks. + + Example: + + >>> print(''.join(context_diff('one\ntwo\nthree\nfour\n'.splitlines(True), + ... 'zero\none\ntree\nfour\n'.splitlines(True), 'Original', 'Current')), + ... end="") + *** Original + --- Current + *************** + *** 1,4 **** + one + ! two + ! three + four + --- 1,4 ---- + + zero + one + ! tree + four + """ + + _check_types(a, b, fromfile, tofile, fromfiledate, tofiledate, lineterm) + prefix = dict(insert='+ ', delete='- ', replace='! ', equal=' ') + started = False + for group in SequenceMatcher(None,a,b).get_grouped_opcodes(n): + if not started: + started = True + fromdate = '\t{}'.format(fromfiledate) if fromfiledate else '' + todate = '\t{}'.format(tofiledate) if tofiledate else '' + yield '*** {}{}{}'.format(fromfile, fromdate, lineterm) + yield '--- {}{}{}'.format(tofile, todate, lineterm) + + first, last = group[0], group[-1] + yield '***************' + lineterm + + file1_range = _format_range_context(first[1], last[2]) + yield '*** {} ****{}'.format(file1_range, lineterm) + + if any(tag in {'replace', 'delete'} for tag, _, _, _, _ in group): + for tag, i1, i2, _, _ in group: + if tag != 'insert': + for line in a[i1:i2]: + yield prefix[tag] + line + + file2_range = _format_range_context(first[3], last[4]) + yield '--- {} ----{}'.format(file2_range, lineterm) + + if any(tag in {'replace', 'insert'} for tag, _, _, _, _ in group): + for tag, _, _, j1, j2 in group: + if tag != 'delete': + for line in b[j1:j2]: + yield prefix[tag] + line + +def _check_types(a, b, *args): + # Checking types is weird, but the alternative is garbled output when + # someone passes mixed bytes and str to {unified,context}_diff(). E.g. + # without this check, passing filenames as bytes results in output like + # --- b'oldfile.txt' + # +++ b'newfile.txt' + # because of how str.format() incorporates bytes objects. + if a and not isinstance(a[0], str): + raise TypeError('lines to compare must be str, not %s (%r)' % + (type(a[0]).__name__, a[0])) + if b and not isinstance(b[0], str): + raise TypeError('lines to compare must be str, not %s (%r)' % + (type(b[0]).__name__, b[0])) + for arg in args: + if not isinstance(arg, str): + raise TypeError('all arguments must be str, not: %r' % (arg,)) + +def diff_bytes(dfunc, a, b, fromfile=b'', tofile=b'', + fromfiledate=b'', tofiledate=b'', n=3, lineterm=b'\n'): + r""" + Compare `a` and `b`, two sequences of lines represented as bytes rather + than str. This is a wrapper for `dfunc`, which is typically either + unified_diff() or context_diff(). Inputs are losslessly converted to + strings so that `dfunc` only has to worry about strings, and encoded + back to bytes on return. This is necessary to compare files with + unknown or inconsistent encoding. All other inputs (except `n`) must be + bytes rather than str. + """ + def decode(s): + try: + return s.decode('ascii', 'surrogateescape') + except AttributeError as err: + msg = ('all arguments must be bytes, not %s (%r)' % + (type(s).__name__, s)) + raise TypeError(msg) from err + a = list(map(decode, a)) + b = list(map(decode, b)) + fromfile = decode(fromfile) + tofile = decode(tofile) + fromfiledate = decode(fromfiledate) + tofiledate = decode(tofiledate) + lineterm = decode(lineterm) + + lines = dfunc(a, b, fromfile, tofile, fromfiledate, tofiledate, n, lineterm) + for line in lines: + yield line.encode('ascii', 'surrogateescape') + +def ndiff(a, b, linejunk=None, charjunk=IS_CHARACTER_JUNK): + r""" + Compare `a` and `b` (lists of strings); return a `Differ`-style delta. + + Optional keyword parameters `linejunk` and `charjunk` are for filter + functions, or can be None: + + - linejunk: A function that should accept a single string argument and + return true iff the string is junk. The default is None, and is + recommended; the underlying SequenceMatcher class has an adaptive + notion of "noise" lines. + + - charjunk: A function that accepts a character (string of length + 1), and returns true iff the character is junk. The default is + the module-level function IS_CHARACTER_JUNK, which filters out + whitespace characters (a blank or tab; note: it's a bad idea to + include newline in this!). + + Tools/scripts/ndiff.py is a command-line front-end to this function. + + Example: + + >>> diff = ndiff('one\ntwo\nthree\n'.splitlines(keepends=True), + ... 'ore\ntree\nemu\n'.splitlines(keepends=True)) + >>> print(''.join(diff), end="") + - one + ? ^ + + ore + ? ^ + - two + - three + ? - + + tree + + emu + """ + return Differ(linejunk, charjunk).compare(a, b) + +def _mdiff(fromlines, tolines, context=None, linejunk=None, + charjunk=IS_CHARACTER_JUNK): + r"""Returns generator yielding marked up from/to side by side differences. + + Arguments: + fromlines -- list of text lines to compared to tolines + tolines -- list of text lines to be compared to fromlines + context -- number of context lines to display on each side of difference, + if None, all from/to text lines will be generated. + linejunk -- passed on to ndiff (see ndiff documentation) + charjunk -- passed on to ndiff (see ndiff documentation) + + This function returns an iterator which returns a tuple: + (from line tuple, to line tuple, boolean flag) + + from/to line tuple -- (line num, line text) + line num -- integer or None (to indicate a context separation) + line text -- original line text with following markers inserted: + '\0+' -- marks start of added text + '\0-' -- marks start of deleted text + '\0^' -- marks start of changed text + '\1' -- marks end of added/deleted/changed text + + boolean flag -- None indicates context separation, True indicates + either "from" or "to" line contains a change, otherwise False. + + This function/iterator was originally developed to generate side by side + file difference for making HTML pages (see HtmlDiff class for example + usage). + + Note, this function utilizes the ndiff function to generate the side by + side difference markup. Optional ndiff arguments may be passed to this + function and they in turn will be passed to ndiff. + """ + import re + + # regular expression for finding intraline change indices + change_re = re.compile(r'(\++|\-+|\^+)') + + # create the difference iterator to generate the differences + diff_lines_iterator = ndiff(fromlines,tolines,linejunk,charjunk) + + def _make_line(lines, format_key, side, num_lines=[0,0]): + """Returns line of text with user's change markup and line formatting. + + lines -- list of lines from the ndiff generator to produce a line of + text from. When producing the line of text to return, the + lines used are removed from this list. + format_key -- '+' return first line in list with "add" markup around + the entire line. + '-' return first line in list with "delete" markup around + the entire line. + '?' return first line in list with add/delete/change + intraline markup (indices obtained from second line) + None return first line in list with no markup + side -- indice into the num_lines list (0=from,1=to) + num_lines -- from/to current line number. This is NOT intended to be a + passed parameter. It is present as a keyword argument to + maintain memory of the current line numbers between calls + of this function. + + Note, this function is purposefully not defined at the module scope so + that data it needs from its parent function (within whose context it + is defined) does not need to be of module scope. + """ + num_lines[side] += 1 + # Handle case where no user markup is to be added, just return line of + # text with user's line format to allow for usage of the line number. + if format_key is None: + return (num_lines[side],lines.pop(0)[2:]) + # Handle case of intraline changes + if format_key == '?': + text, markers = lines.pop(0), lines.pop(0) + # find intraline changes (store change type and indices in tuples) + sub_info = [] + def record_sub_info(match_object,sub_info=sub_info): + sub_info.append([match_object.group(1)[0],match_object.span()]) + return match_object.group(1) + change_re.sub(record_sub_info,markers) + # process each tuple inserting our special marks that won't be + # noticed by an xml/html escaper. + for key,(begin,end) in reversed(sub_info): + text = text[0:begin]+'\0'+key+text[begin:end]+'\1'+text[end:] + text = text[2:] + # Handle case of add/delete entire line + else: + text = lines.pop(0)[2:] + # if line of text is just a newline, insert a space so there is + # something for the user to highlight and see. + if not text: + text = ' ' + # insert marks that won't be noticed by an xml/html escaper. + text = '\0' + format_key + text + '\1' + # Return line of text, first allow user's line formatter to do its + # thing (such as adding the line number) then replace the special + # marks with what the user's change markup. + return (num_lines[side],text) + + def _line_iterator(): + """Yields from/to lines of text with a change indication. + + This function is an iterator. It itself pulls lines from a + differencing iterator, processes them and yields them. When it can + it yields both a "from" and a "to" line, otherwise it will yield one + or the other. In addition to yielding the lines of from/to text, a + boolean flag is yielded to indicate if the text line(s) have + differences in them. + + Note, this function is purposefully not defined at the module scope so + that data it needs from its parent function (within whose context it + is defined) does not need to be of module scope. + """ + lines = [] + num_blanks_pending, num_blanks_to_yield = 0, 0 + while True: + # Load up next 4 lines so we can look ahead, create strings which + # are a concatenation of the first character of each of the 4 lines + # so we can do some very readable comparisons. + while len(lines) < 4: + lines.append(next(diff_lines_iterator, 'X')) + s = ''.join([line[0] for line in lines]) + if s.startswith('X'): + # When no more lines, pump out any remaining blank lines so the + # corresponding add/delete lines get a matching blank line so + # all line pairs get yielded at the next level. + num_blanks_to_yield = num_blanks_pending + elif s.startswith('-?+?'): + # simple intraline change + yield _make_line(lines,'?',0), _make_line(lines,'?',1), True + continue + elif s.startswith('--++'): + # in delete block, add block coming: we do NOT want to get + # caught up on blank lines yet, just process the delete line + num_blanks_pending -= 1 + yield _make_line(lines,'-',0), None, True + continue + elif s.startswith(('--?+', '--+', '- ')): + # in delete block and see an intraline change or unchanged line + # coming: yield the delete line and then blanks + from_line,to_line = _make_line(lines,'-',0), None + num_blanks_to_yield,num_blanks_pending = num_blanks_pending-1,0 + elif s.startswith('-+?'): + # intraline change + yield _make_line(lines,None,0), _make_line(lines,'?',1), True + continue + elif s.startswith('-?+'): + # intraline change + yield _make_line(lines,'?',0), _make_line(lines,None,1), True + continue + elif s.startswith('-'): + # delete FROM line + num_blanks_pending -= 1 + yield _make_line(lines,'-',0), None, True + continue + elif s.startswith('+--'): + # in add block, delete block coming: we do NOT want to get + # caught up on blank lines yet, just process the add line + num_blanks_pending += 1 + yield None, _make_line(lines,'+',1), True + continue + elif s.startswith(('+ ', '+-')): + # will be leaving an add block: yield blanks then add line + from_line, to_line = None, _make_line(lines,'+',1) + num_blanks_to_yield,num_blanks_pending = num_blanks_pending+1,0 + elif s.startswith('+'): + # inside an add block, yield the add line + num_blanks_pending += 1 + yield None, _make_line(lines,'+',1), True + continue + elif s.startswith(' '): + # unchanged text, yield it to both sides + yield _make_line(lines[:],None,0),_make_line(lines,None,1),False + continue + # Catch up on the blank lines so when we yield the next from/to + # pair, they are lined up. + while(num_blanks_to_yield < 0): + num_blanks_to_yield += 1 + yield None,('','\n'),True + while(num_blanks_to_yield > 0): + num_blanks_to_yield -= 1 + yield ('','\n'),None,True + if s.startswith('X'): + return + else: + yield from_line,to_line,True + + def _line_pair_iterator(): + """Yields from/to lines of text with a change indication. + + This function is an iterator. It itself pulls lines from the line + iterator. Its difference from that iterator is that this function + always yields a pair of from/to text lines (with the change + indication). If necessary it will collect single from/to lines + until it has a matching pair from/to pair to yield. + + Note, this function is purposefully not defined at the module scope so + that data it needs from its parent function (within whose context it + is defined) does not need to be of module scope. + """ + line_iterator = _line_iterator() + fromlines,tolines=[],[] + while True: + # Collecting lines of text until we have a from/to pair + while (len(fromlines)==0 or len(tolines)==0): + try: + from_line, to_line, found_diff = next(line_iterator) + except StopIteration: + return + if from_line is not None: + fromlines.append((from_line,found_diff)) + if to_line is not None: + tolines.append((to_line,found_diff)) + # Once we have a pair, remove them from the collection and yield it + from_line, fromDiff = fromlines.pop(0) + to_line, to_diff = tolines.pop(0) + yield (from_line,to_line,fromDiff or to_diff) + + # Handle case where user does not want context differencing, just yield + # them up without doing anything else with them. + line_pair_iterator = _line_pair_iterator() + if context is None: + yield from line_pair_iterator + # Handle case where user wants context differencing. We must do some + # storage of lines until we know for sure that they are to be yielded. + else: + context += 1 + lines_to_write = 0 + while True: + # Store lines up until we find a difference, note use of a + # circular queue because we only need to keep around what + # we need for context. + index, contextLines = 0, [None]*(context) + found_diff = False + while(found_diff is False): + try: + from_line, to_line, found_diff = next(line_pair_iterator) + except StopIteration: + return + i = index % context + contextLines[i] = (from_line, to_line, found_diff) + index += 1 + # Yield lines that we have collected so far, but first yield + # the user's separator. + if index > context: + yield None, None, None + lines_to_write = context + else: + lines_to_write = index + index = 0 + while(lines_to_write): + i = index % context + index += 1 + yield contextLines[i] + lines_to_write -= 1 + # Now yield the context lines after the change + lines_to_write = context-1 + try: + while(lines_to_write): + from_line, to_line, found_diff = next(line_pair_iterator) + # If another change within the context, extend the context + if found_diff: + lines_to_write = context-1 + else: + lines_to_write -= 1 + yield from_line, to_line, found_diff + except StopIteration: + # Catch exception from next() and return normally + return + + +_file_template = """ + + + + + + + + + + + + %(table)s%(legend)s + + +""" + +_styles = """ + table.diff {font-family:Courier; border:medium;} + .diff_header {background-color:#e0e0e0} + td.diff_header {text-align:right} + .diff_next {background-color:#c0c0c0} + .diff_add {background-color:#aaffaa} + .diff_chg {background-color:#ffff77} + .diff_sub {background-color:#ffaaaa}""" + +_table_template = """ + + + + %(header_row)s + +%(data_rows)s +
""" + +_legend = """ + + + + +
Legends
+ + + + +
Colors
 Added 
Changed
Deleted
+ + + + +
Links
(f)irst change
(n)ext change
(t)op
""" + +class HtmlDiff(object): + """For producing HTML side by side comparison with change highlights. + + This class can be used to create an HTML table (or a complete HTML file + containing the table) showing a side by side, line by line comparison + of text with inter-line and intra-line change highlights. The table can + be generated in either full or contextual difference mode. + + The following methods are provided for HTML generation: + + make_table -- generates HTML for a single side by side table + make_file -- generates complete HTML file with a single side by side table + + See tools/scripts/diff.py for an example usage of this class. + """ + + _file_template = _file_template + _styles = _styles + _table_template = _table_template + _legend = _legend + _default_prefix = 0 + + def __init__(self,tabsize=8,wrapcolumn=None,linejunk=None, + charjunk=IS_CHARACTER_JUNK): + """HtmlDiff instance initializer + + Arguments: + tabsize -- tab stop spacing, defaults to 8. + wrapcolumn -- column number where lines are broken and wrapped, + defaults to None where lines are not wrapped. + linejunk,charjunk -- keyword arguments passed into ndiff() (used by + HtmlDiff() to generate the side by side HTML differences). See + ndiff() documentation for argument default values and descriptions. + """ + self._tabsize = tabsize + self._wrapcolumn = wrapcolumn + self._linejunk = linejunk + self._charjunk = charjunk + + def make_file(self, fromlines, tolines, fromdesc='', todesc='', + context=False, numlines=5, *, charset='utf-8'): + """Returns HTML file of side by side comparison with change highlights + + Arguments: + fromlines -- list of "from" lines + tolines -- list of "to" lines + fromdesc -- "from" file column header string + todesc -- "to" file column header string + context -- set to True for contextual differences (defaults to False + which shows full differences). + numlines -- number of context lines. When context is set True, + controls number of lines displayed before and after the change. + When context is False, controls the number of lines to place + the "next" link anchors before the next change (so click of + "next" link jumps to just before the change). + charset -- charset of the HTML document + """ + + return (self._file_template % dict( + styles=self._styles, + legend=self._legend, + table=self.make_table(fromlines, tolines, fromdesc, todesc, + context=context, numlines=numlines), + charset=charset + )).encode(charset, 'xmlcharrefreplace').decode(charset) + + def _tab_newline_replace(self,fromlines,tolines): + """Returns from/to line lists with tabs expanded and newlines removed. + + Instead of tab characters being replaced by the number of spaces + needed to fill in to the next tab stop, this function will fill + the space with tab characters. This is done so that the difference + algorithms can identify changes in a file when tabs are replaced by + spaces and vice versa. At the end of the HTML generation, the tab + characters will be replaced with a nonbreakable space. + """ + def expand_tabs(line): + # hide real spaces + line = line.replace(' ','\0') + # expand tabs into spaces + line = line.expandtabs(self._tabsize) + # replace spaces from expanded tabs back into tab characters + # (we'll replace them with markup after we do differencing) + line = line.replace(' ','\t') + return line.replace('\0',' ').rstrip('\n') + fromlines = [expand_tabs(line) for line in fromlines] + tolines = [expand_tabs(line) for line in tolines] + return fromlines,tolines + + def _split_line(self,data_list,line_num,text): + """Builds list of text lines by splitting text lines at wrap point + + This function will determine if the input text line needs to be + wrapped (split) into separate lines. If so, the first wrap point + will be determined and the first line appended to the output + text line list. This function is used recursively to handle + the second part of the split line to further split it. + """ + # if blank line or context separator, just add it to the output list + if not line_num: + data_list.append((line_num,text)) + return + + # if line text doesn't need wrapping, just add it to the output list + size = len(text) + max = self._wrapcolumn + if (size <= max) or ((size -(text.count('\0')*3)) <= max): + data_list.append((line_num,text)) + return + + # scan text looking for the wrap point, keeping track if the wrap + # point is inside markers + i = 0 + n = 0 + mark = '' + while n < max and i < size: + if text[i] == '\0': + i += 1 + mark = text[i] + i += 1 + elif text[i] == '\1': + i += 1 + mark = '' + else: + i += 1 + n += 1 + + # wrap point is inside text, break it up into separate lines + line1 = text[:i] + line2 = text[i:] + + # if wrap point is inside markers, place end marker at end of first + # line and start marker at beginning of second line because each + # line will have its own table tag markup around it. + if mark: + line1 = line1 + '\1' + line2 = '\0' + mark + line2 + + # tack on first line onto the output list + data_list.append((line_num,line1)) + + # use this routine again to wrap the remaining text + self._split_line(data_list,'>',line2) + + def _line_wrapper(self,diffs): + """Returns iterator that splits (wraps) mdiff text lines""" + + # pull from/to data and flags from mdiff iterator + for fromdata,todata,flag in diffs: + # check for context separators and pass them through + if flag is None: + yield fromdata,todata,flag + continue + (fromline,fromtext),(toline,totext) = fromdata,todata + # for each from/to line split it at the wrap column to form + # list of text lines. + fromlist,tolist = [],[] + self._split_line(fromlist,fromline,fromtext) + self._split_line(tolist,toline,totext) + # yield from/to line in pairs inserting blank lines as + # necessary when one side has more wrapped lines + while fromlist or tolist: + if fromlist: + fromdata = fromlist.pop(0) + else: + fromdata = ('',' ') + if tolist: + todata = tolist.pop(0) + else: + todata = ('',' ') + yield fromdata,todata,flag + + def _collect_lines(self,diffs): + """Collects mdiff output into separate lists + + Before storing the mdiff from/to data into a list, it is converted + into a single line of text with HTML markup. + """ + + fromlist,tolist,flaglist = [],[],[] + # pull from/to data and flags from mdiff style iterator + for fromdata,todata,flag in diffs: + try: + # store HTML markup of the lines into the lists + fromlist.append(self._format_line(0,flag,*fromdata)) + tolist.append(self._format_line(1,flag,*todata)) + except TypeError: + # exceptions occur for lines where context separators go + fromlist.append(None) + tolist.append(None) + flaglist.append(flag) + return fromlist,tolist,flaglist + + def _format_line(self,side,flag,linenum,text): + """Returns HTML markup of "from" / "to" text lines + + side -- 0 or 1 indicating "from" or "to" text + flag -- indicates if difference on line + linenum -- line number (used for line number column) + text -- line text to be marked up + """ + try: + linenum = '%d' % linenum + id = ' id="%s%s"' % (self._prefix[side],linenum) + except TypeError: + # handle blank lines where linenum is '>' or '' + id = '' + # replace those things that would get confused with HTML symbols + text=text.replace("&","&").replace(">",">").replace("<","<") + + # make space non-breakable so they don't get compressed or line wrapped + text = text.replace(' ',' ').rstrip() + + return '%s%s' \ + % (id,linenum,text) + + def _make_prefix(self): + """Create unique anchor prefixes""" + + # Generate a unique anchor prefix so multiple tables + # can exist on the same HTML page without conflicts. + fromprefix = "from%d_" % HtmlDiff._default_prefix + toprefix = "to%d_" % HtmlDiff._default_prefix + HtmlDiff._default_prefix += 1 + # store prefixes so line format method has access + self._prefix = [fromprefix,toprefix] + + def _convert_flags(self,fromlist,tolist,flaglist,context,numlines): + """Makes list of "next" links""" + + # all anchor names will be generated using the unique "to" prefix + toprefix = self._prefix[1] + + # process change flags, generating middle column of next anchors/links + next_id = ['']*len(flaglist) + next_href = ['']*len(flaglist) + num_chg, in_change = 0, False + last = 0 + for i,flag in enumerate(flaglist): + if flag: + if not in_change: + in_change = True + last = i + # at the beginning of a change, drop an anchor a few lines + # (the context lines) before the change for the previous + # link + i = max([0,i-numlines]) + next_id[i] = ' id="difflib_chg_%s_%d"' % (toprefix,num_chg) + # at the beginning of a change, drop a link to the next + # change + num_chg += 1 + next_href[last] = 'n' % ( + toprefix,num_chg) + else: + in_change = False + # check for cases where there is no content to avoid exceptions + if not flaglist: + flaglist = [False] + next_id = [''] + next_href = [''] + last = 0 + if context: + fromlist = [' No Differences Found '] + tolist = fromlist + else: + fromlist = tolist = [' Empty File '] + # if not a change on first line, drop a link + if not flaglist[0]: + next_href[0] = 'f' % toprefix + # redo the last link to link to the top + next_href[last] = 't' % (toprefix) + + return fromlist,tolist,flaglist,next_href,next_id + + def make_table(self,fromlines,tolines,fromdesc='',todesc='',context=False, + numlines=5): + """Returns HTML table of side by side comparison with change highlights + + Arguments: + fromlines -- list of "from" lines + tolines -- list of "to" lines + fromdesc -- "from" file column header string + todesc -- "to" file column header string + context -- set to True for contextual differences (defaults to False + which shows full differences). + numlines -- number of context lines. When context is set True, + controls number of lines displayed before and after the change. + When context is False, controls the number of lines to place + the "next" link anchors before the next change (so click of + "next" link jumps to just before the change). + """ + + # make unique anchor prefixes so that multiple tables may exist + # on the same page without conflict. + self._make_prefix() + + # change tabs to spaces before it gets more difficult after we insert + # markup + fromlines,tolines = self._tab_newline_replace(fromlines,tolines) + + # create diffs iterator which generates side by side from/to data + if context: + context_lines = numlines + else: + context_lines = None + diffs = _mdiff(fromlines,tolines,context_lines,linejunk=self._linejunk, + charjunk=self._charjunk) + + # set up iterator to wrap lines that exceed desired width + if self._wrapcolumn: + diffs = self._line_wrapper(diffs) + + # collect up from/to lines and flags into lists (also format the lines) + fromlist,tolist,flaglist = self._collect_lines(diffs) + + # process change flags, generating middle column of next anchors/links + fromlist,tolist,flaglist,next_href,next_id = self._convert_flags( + fromlist,tolist,flaglist,context,numlines) + + s = [] + fmt = ' %s%s' + \ + '%s%s\n' + for i in range(len(flaglist)): + if flaglist[i] is None: + # mdiff yields None on separator lines skip the bogus ones + # generated for the first line + if i > 0: + s.append(' \n \n') + else: + s.append( fmt % (next_id[i],next_href[i],fromlist[i], + next_href[i],tolist[i])) + if fromdesc or todesc: + header_row = '%s%s%s%s' % ( + '
', + '%s' % fromdesc, + '
', + '%s' % todesc) + else: + header_row = '' + + table = self._table_template % dict( + data_rows=''.join(s), + header_row=header_row, + prefix=self._prefix[1]) + + return table.replace('\0+',''). \ + replace('\0-',''). \ + replace('\0^',''). \ + replace('\1',''). \ + replace('\t',' ') + +del re + +def restore(delta, which): + r""" + Generate one of the two sequences that generated a delta. + + Given a `delta` produced by `Differ.compare()` or `ndiff()`, extract + lines originating from file 1 or 2 (parameter `which`), stripping off line + prefixes. + + Examples: + + >>> diff = ndiff('one\ntwo\nthree\n'.splitlines(keepends=True), + ... 'ore\ntree\nemu\n'.splitlines(keepends=True)) + >>> diff = list(diff) + >>> print(''.join(restore(diff, 1)), end="") + one + two + three + >>> print(''.join(restore(diff, 2)), end="") + ore + tree + emu + """ + try: + tag = {1: "- ", 2: "+ "}[int(which)] + except KeyError: + raise ValueError('unknown delta choice (must be 1 or 2): %r' + % which) from None + prefixes = (" ", tag) + for line in delta: + if line[:2] in prefixes: + yield line[2:] + +def _test(): + import doctest, difflib + return doctest.testmod(difflib) + +if __name__ == "__main__": + _test() diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Allocation/RegisterBankInfo/RegisterBankInfo.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Allocation/RegisterBankInfo/RegisterBankInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4dc7ae84acc6da01a6fc88136b4545507046b3da --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Allocation/RegisterBankInfo/RegisterBankInfo.cpp @@ -0,0 +1,2 @@ +RISCVRegisterBankInfo::RISCVRegisterBankInfo(const TargetRegisterInfo &TRI) : RISCVGenRegisterBankInfo() { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Allocation/RegisterInfo/RegisterInfo.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Allocation/RegisterInfo/RegisterInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1480303244e07d20dda536668a1d006b005c6abf --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Allocation/RegisterInfo/RegisterInfo.cpp @@ -0,0 +1,2 @@ +RISCVRegisterInfo::RISCVRegisterInfo(unsigned HwMode) : RISCVGenRegisterInfo(RISCV::X1, 0, 0, 0, HwMode) { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Allocation/RegisterInfo/eliminateFrameIndex.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Allocation/RegisterInfo/eliminateFrameIndex.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4627583a88c723ec5625aa71d430e6bc6fca6ed5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Allocation/RegisterInfo/eliminateFrameIndex.cpp @@ -0,0 +1,27 @@ +void RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const { + assert(SPAdj == 0 && "Unexpected non-zero SPAdj value"); + MachineInstr &MI = *II; + MachineFunction &MF = *MI.getParent()->getParent(); + MachineRegisterInfo &MRI = MF.getRegInfo(); + const RISCVInstrInfo *TII = MF.getSubtarget().getInstrInfo(); + DebugLoc DL = MI.getDebugLoc(); + int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); + Register FrameReg; + int Offset = getFrameLowering(MF)->getFrameIndexReference(MF, FrameIndex, FrameReg).getFixed() + MI.getOperand(FIOperandNum + 1).getImm(); + if (!isInt<32>(Offset)) { + report_fatal_error("Frame offsets outside of the signed 32-bit range not supported"); + } + MachineBasicBlock &MBB = *MI.getParent(); + bool FrameRegIsKill = false; + if (!isInt<12>(Offset)) { + assert(isInt<32>(Offset) && "Int32 expected"); + Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); + TII->movImm(MBB, II, DL, ScratchReg, Offset); + BuildMI(MBB, II, DL, TII->get(RISCV::ADD), ScratchReg).addReg(FrameReg).addReg(ScratchReg, RegState::Kill); + Offset = 0; + FrameReg = ScratchReg; + FrameRegIsKill = true; + } + MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, FrameRegIsKill); + MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Allocation/RegisterInfo/getCallPreservedMask.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Allocation/RegisterInfo/getCallPreservedMask.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a8e9de57806a18f51b53e3d7fa691a28052d7d64 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Allocation/RegisterInfo/getCallPreservedMask.cpp @@ -0,0 +1,19 @@ +const uint32_t *RISCVRegisterInfo::getCallPreservedMask(const MachineFunction & MF, CallingConv::ID CC) const { + auto &Subtarget = MF.getSubtarget(); + if (CC == CallingConv::GHC) { + return CSR_NoRegs_RegMask; + } + switch (Subtarget.getTargetABI()) { + case RISCVABI::ABI_ILP32: + case RISCVABI::ABI_LP64: + return CSR_ILP32_LP64_RegMask; + case RISCVABI::ABI_ILP32F: + case RISCVABI::ABI_LP64F: + return CSR_ILP32F_LP64F_RegMask; + case RISCVABI::ABI_ILP32D: + case RISCVABI::ABI_LP64D: + return CSR_ILP32D_LP64D_RegMask; + default: + llvm_unreachable("Unrecognized ABI"); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Allocation/RegisterInfo/getCalleeSavedRegs.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Allocation/RegisterInfo/getCalleeSavedRegs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3050b17a62d80679cf10f80be303f18b7def4c51 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Allocation/RegisterInfo/getCalleeSavedRegs.cpp @@ -0,0 +1,28 @@ +const MCPhysReg *RISCVRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { + auto &Subtarget = MF->getSubtarget(); + if (MF->getFunction().getCallingConv() == CallingConv::GHC) { + return CSR_NoRegs_SaveList; + } + if (MF->getFunction().hasFnAttribute("interrupt")) { + if (Subtarget.hasStdExtD()) { + return CSR_XLEN_F64_Interrupt_SaveList; + } + if (Subtarget.hasStdExtF()) { + return CSR_XLEN_F32_Interrupt_SaveList; + } + return CSR_Interrupt_SaveList; + } + switch (Subtarget.getTargetABI()) { + case RISCVABI::ABI_ILP32: + case RISCVABI::ABI_LP64: + return CSR_ILP32_LP64_SaveList; + case RISCVABI::ABI_ILP32F: + case RISCVABI::ABI_LP64F: + return CSR_ILP32F_LP64F_SaveList; + case RISCVABI::ABI_ILP32D: + case RISCVABI::ABI_LP64D: + return CSR_ILP32D_LP64D_SaveList; + default: + llvm_unreachable("Unrecognized ABI"); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Allocation/RegisterInfo/getFrameRegister.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Allocation/RegisterInfo/getFrameRegister.cpp new file mode 100644 index 0000000000000000000000000000000000000000..72c4c839e6e91d5177aac289f685491ab3ec84a2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Allocation/RegisterInfo/getFrameRegister.cpp @@ -0,0 +1,4 @@ +Register RISCVRegisterInfo::getFrameRegister(const MachineFunction &MF) const { + const TargetFrameLowering *TFI = getFrameLowering(MF); + return TFI->hasFP(MF) ? RISCV::X8 : RISCV::X2; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Allocation/RegisterInfo/getNoPreservedMask.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Allocation/RegisterInfo/getNoPreservedMask.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7fa56f2bf4b0fa58c156cb2b44e640600fd4e8df --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Allocation/RegisterInfo/getNoPreservedMask.cpp @@ -0,0 +1,3 @@ +const uint32_t *RISCVRegisterInfo::getNoPreservedMask() const { + return CSR_NoRegs_RegMask; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Allocation/RegisterInfo/getPointerRegClass.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Allocation/RegisterInfo/getPointerRegClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..88663c48f37912ceed74f49de1e37a38e9411d0a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Allocation/RegisterInfo/getPointerRegClass.cpp @@ -0,0 +1,3 @@ +const TargetRegisterClass *getPointerRegClass(const MachineFunction &MF, unsigned Kind = 0) const override { + return &RISCV::GPRRegClass; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Allocation/RegisterInfo/getReservedRegs.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Allocation/RegisterInfo/getReservedRegs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4de8d55da32eb35d5bbf5d18d0057f8121e39df1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Allocation/RegisterInfo/getReservedRegs.cpp @@ -0,0 +1,25 @@ +BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const { + const RISCVFrameLowering *TFI = getFrameLowering(MF); + BitVector Reserved(getNumRegs()); + for (size_t Reg = 0; Reg < getNumRegs(); Reg++) { + if (MF.getSubtarget().isRegisterReservedByUser(Reg)) { + markSuperRegs(Reserved, Reg); + } + } + if (TFI->hasBP(MF)) { + markSuperRegs(Reserved, RISCV::X9); + } + if (TFI->hasFP(MF)) { + markSuperRegs(Reserved, RISCV::X8); + } + markSuperRegs(Reserved, RISCV::X0); + markSuperRegs(Reserved, RISCV::X2); + markSuperRegs(Reserved, RISCV::X3); + markSuperRegs(Reserved, RISCV::X4); + markSuperRegs(Reserved, RISCV::VL); + markSuperRegs(Reserved, RISCV::VTYPE); + markSuperRegs(Reserved, RISCV::VXSAT); + markSuperRegs(Reserved, RISCV::VXRM); + assert(checkAllSuperRegsMarked(Reserved)); + return Reserved; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Allocation/RegisterInfo/hasReservedSpillSlot.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Allocation/RegisterInfo/hasReservedSpillSlot.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0128afe039488da081ce0db8ac0fa9d0c2001e05 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Allocation/RegisterInfo/hasReservedSpillSlot.cpp @@ -0,0 +1,12 @@ +bool RISCVRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF, Register Reg, int &FrameIdx) const { + const auto *RVFI = MF.getInfo(); + if (!RVFI->useSaveRestoreLibCalls(MF)) { + return false; + } + auto FII = FixedCSRFIMap.find(Reg); + if (FII == FixedCSRFIMap.end()) { + return false; + } + FrameIdx = FII->second; + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Allocation/RegisterInfo/isAsmClobberable.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Allocation/RegisterInfo/isAsmClobberable.cpp new file mode 100644 index 0000000000000000000000000000000000000000..25561255c0b0144c3f52ec50dd6542c764b476af --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Allocation/RegisterInfo/isAsmClobberable.cpp @@ -0,0 +1,3 @@ +bool RISCVRegisterInfo::isAsmClobberable(const MachineFunction &MF, MCRegister PhysReg) const { + return !MF.getSubtarget().isRegisterReservedByUser(PhysReg); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Allocation/RegisterInfo/isConstantPhysReg.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Allocation/RegisterInfo/isConstantPhysReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5f3ae8dcbdb06cd2b11c08d4304bc5fbbeb7a0bf --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Allocation/RegisterInfo/isConstantPhysReg.cpp @@ -0,0 +1,3 @@ +bool RISCVRegisterInfo::isConstantPhysReg(MCRegister PhysReg) const { + return PhysReg == RISCV::X0; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Allocation/RegisterInfo/requiresFrameIndexScavenging.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Allocation/RegisterInfo/requiresFrameIndexScavenging.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fcdefd787701998b4ca78c8a05ad2a8d3a8da92b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Allocation/RegisterInfo/requiresFrameIndexScavenging.cpp @@ -0,0 +1,3 @@ +bool requiresFrameIndexScavenging(const MachineFunction &MF) const override { + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Allocation/RegisterInfo/requiresRegisterScavenging.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Allocation/RegisterInfo/requiresRegisterScavenging.cpp new file mode 100644 index 0000000000000000000000000000000000000000..14b5f8108d512990df2060604418ece481a51ba3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Allocation/RegisterInfo/requiresRegisterScavenging.cpp @@ -0,0 +1,3 @@ +bool requiresRegisterScavenging(const MachineFunction &MF) const override { + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/AsmParser.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/AsmParser.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7797cdba62f86a46e4dea7c5120f3c6aefe6bfde --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/AsmParser.cpp @@ -0,0 +1,16 @@ +RISCVAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser, const MCInstrInfo &MII, const MCTargetOptions &Options) : MCTargetAsmParser(Options, STI, MII) { + Parser.addAliasForDirective(".half", ".2byte"); + Parser.addAliasForDirective(".hword", ".2byte"); + Parser.addAliasForDirective(".word", ".4byte"); + Parser.addAliasForDirective(".dword", ".8byte"); + setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); + auto ABIName = StringRef(Options.ABIName); + if (ABIName.endswith("f") && !getSTI().getFeatureBits()[RISCV::FeatureStdExtF]) { + errs() << "Hard-float 'f' ABI can't be used for a target that doesn't support the F instruction set extension (ignoring target-abi)\n"; + } + else if (ABIName.endswith("d") && !getSTI().getFeatureBits()[RISCV::FeatureStdExtD]) { + errs() << "Hard-float 'd' ABI can't be used for a target that doesn't support the D instruction set extension (ignoring target-abi)\n"; + } + const MCObjectFileInfo *MOFI = Parser.getContext().getObjectFileInfo(); + ParserOptions.IsPicEnabled = MOFI->isPositionIndependent(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/KindTy.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/KindTy.cpp new file mode 100644 index 0000000000000000000000000000000000000000..371575f0ea6716a531fb88cd3fb871d6a05d4417 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/KindTy.cpp @@ -0,0 +1,7 @@ +enum class KindTy { + Token, + Register, + Immediate, + SystemRegister, + VType, +} Kind; diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/LLVMInitializeAsmParser.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/LLVMInitializeAsmParser.cpp new file mode 100644 index 0000000000000000000000000000000000000000..71228f1bad2b593ede7681696f374a8ce3765475 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/LLVMInitializeAsmParser.cpp @@ -0,0 +1,4 @@ +extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVAsmParser() { + RegisterMCAsmParser X(getTheRISCV32Target()); + RegisterMCAsmParser Y(getTheRISCV64Target()); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/MatchAndEmitInstruction.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/MatchAndEmitInstruction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a0b5f960569745689b8abf24bb90aaf3d291803c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/MatchAndEmitInstruction.cpp @@ -0,0 +1,621 @@ +bool RISCVAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, OperandVector &Operands, MCStreamer &Out, uint64_t &ErrorInfo, bool MatchingInlineAsm) { + MCInst Inst; + FeatureBitset MissingFeatures; + auto Result = MatchInstructionImpl(Operands, Inst, ErrorInfo, MissingFeatures, MatchingInlineAsm); + switch (Result) { + default: + break; + case Match_Success: + const MCInstrDesc &MCID = MII.get(Inst.getOpcode()); + unsigned Constraints = (MCID.TSFlags & RISCVII::ConstraintMask) >> RISCVII::ConstraintShift; + unsigned DestReg = Inst.getOperand(0).getReg(); + SMLoc Loc = Operands[1]->getStartLoc(); + if (Constraints & RISCVII::VS2Constraint) { + unsigned CheckReg = Inst.getOperand(1).getReg(); + if (DestReg == CheckReg) { + return Error(Loc, "The destination vector register group cannot overlap the source vector register group."); + } + } + if ((Constraints & RISCVII::VS1Constraint) && (Inst.getOperand(2).isReg())) { + unsigned CheckReg = Inst.getOperand(2).getReg(); + if (DestReg == CheckReg) { + return Error(Loc, "The destination vector register group cannot overlap the source vector register group."); + } + } + if ((Constraints & RISCVII::VMConstraint) && (DestReg == RISCV::V0)) { + unsigned Opcode = Inst.getOpcode(); + if (Opcode == RISCV::VADC_VVM || Opcode == RISCV::VADC_VXM || Opcode == RISCV::VADC_VIM || Opcode == RISCV::VSBC_VVM || Opcode == RISCV::VSBC_VXM || Opcode == RISCV::VFMERGE_VFM || Opcode == RISCV::VMERGE_VIM || Opcode == RISCV::VMERGE_VVM || Opcode == RISCV::VMERGE_VXM) { + return Error(Loc, "The destination vector register group cannot be V0."); + } + unsigned CheckReg = Inst.getOperand(Inst.getNumOperands() - 1).getReg(); + assert((CheckReg == RISCV::V0 || CheckReg == RISCV::NoRegister) && "Unexpected register for mask operand"); + if (DestReg == CheckReg) { + return Error(Loc, "The destination vector register group cannot overlap the mask register."); + } + } + Inst.setLoc(IDLoc); + switch (Inst.getOpcode()) { + default: + break; + case RISCV::PseudoLI: { + MCRegister Reg = Inst.getOperand(0).getReg(); + const MCOperand &Op1 = Inst.getOperand(1); + if (Op1.isExpr()) { + emitToStreamer(Out, MCInstBuilder(RISCV::ADDI).addReg(Reg).addReg(RISCV::X0).addExpr(Op1.getExpr())); + return false; + } + int64_t Imm = Inst.getOperand(1).getImm(); + if (!isRV64()) { + Imm = SignExtend64<32>(Imm); + } + RISCVMatInt::InstSeq Seq; + RISCVMatInt::generateInstSeq(Value, isRV64(), Seq); + MCRegister SrcReg = RISCV::X0; + for (RISCVMatInt::Inst &Inst : Seq) { + if (Inst.Opc == RISCV::LUI) { + emitToStreamer(Out, MCInstBuilder(RISCV::LUI).addReg(DestReg).addImm(Inst.Imm)); + } else { + emitToStreamer(Out, MCInstBuilder(Inst.Opc).addReg(DestReg).addReg(SrcReg).addImm(Inst.Imm)); + } + SrcReg = DestReg; + } + return false; + } + case RISCV::PseudoLLA: + MCOperand DestReg = Inst.getOperand(0); + const MCExpr *Symbol = Inst.getOperand(1).getExpr(); + MCContext &Ctx = getContext(); + MCSymbol *TmpLabel = Ctx.createNamedTempSymbol("pcrel_hi"); + Out.emitLabel(TmpLabel); + const RISCVMCExpr *SymbolHi = RISCVMCExpr::create(Symbol, VKHi, Ctx); + emitToStreamer(Out, MCInstBuilder(RISCV::AUIPC).addOperand(TmpReg).addExpr(SymbolHi)); + const MCExpr *RefToLinkTmpLabel = RISCVMCExpr::create(MCSymbolRefExpr::create(TmpLabel, Ctx), RISCVMCExpr::VK_RISCV_PCREL_LO, Ctx); + emitToStreamer(Out, MCInstBuilder(SecondOpcode).addOperand(DestReg).addOperand(TmpReg).addExpr(RefToLinkTmpLabel)); + return false; + case RISCV::PseudoLA: + MCOperand DestReg = Inst.getOperand(0); + const MCExpr *Symbol = Inst.getOperand(1).getExpr(); + unsigned SecondOpcode; + RISCVMCExpr::VariantKind VKHi; + if (ParserOptions.IsPicEnabled) { + SecondOpcode = isRV64() ? RISCV::LD : RISCV::LW; + VKHi = RISCVMCExpr::VK_RISCV_GOT_HI; + } else { + SecondOpcode = RISCV::ADDI; + VKHi = RISCVMCExpr::VK_RISCV_PCREL_HI; + } + MCContext &Ctx = getContext(); + MCSymbol *TmpLabel = Ctx.createNamedTempSymbol("pcrel_hi"); + Out.emitLabel(TmpLabel); + const RISCVMCExpr *SymbolHi = RISCVMCExpr::create(Symbol, VKHi, Ctx); + emitToStreamer(Out, MCInstBuilder(RISCV::AUIPC).addOperand(TmpReg).addExpr(SymbolHi)); + const MCExpr *RefToLinkTmpLabel = RISCVMCExpr::create(MCSymbolRefExpr::create(TmpLabel, Ctx), RISCVMCExpr::VK_RISCV_PCREL_LO, Ctx); + emitToStreamer(Out, MCInstBuilder(SecondOpcode).addOperand(DestReg).addOperand(TmpReg).addExpr(RefToLinkTmpLabel)); + return false; + case RISCV::PseudoLA_TLS_IE: + MCOperand DestReg = Inst.getOperand(0); + const MCExpr *Symbol = Inst.getOperand(1).getExpr(); + unsigned SecondOpcode = isRV64() ? RISCV::LD : RISCV::LW; + MCContext &Ctx = getContext(); + MCSymbol *TmpLabel = Ctx.createNamedTempSymbol("pcrel_hi"); + Out.emitLabel(TmpLabel); + const RISCVMCExpr *SymbolHi = RISCVMCExpr::create(Symbol, VKHi, Ctx); + emitToStreamer(Out, MCInstBuilder(RISCV::AUIPC).addOperand(TmpReg).addExpr(SymbolHi)); + const MCExpr *RefToLinkTmpLabel = RISCVMCExpr::create(MCSymbolRefExpr::create(TmpLabel, Ctx), RISCVMCExpr::VK_RISCV_PCREL_LO, Ctx); + emitToStreamer(Out, MCInstBuilder(SecondOpcode).addOperand(DestReg).addOperand(TmpReg).addExpr(RefToLinkTmpLabel)); + return false; + case RISCV::PseudoLA_TLS_GD: + MCOperand DestReg = Inst.getOperand(0); + const MCExpr *Symbol = Inst.getOperand(1).getExpr(); + MCContext &Ctx = getContext(); + MCSymbol *TmpLabel = Ctx.createNamedTempSymbol("pcrel_hi"); + Out.emitLabel(TmpLabel); + const RISCVMCExpr *SymbolHi = RISCVMCExpr::create(Symbol, VKHi, Ctx); + emitToStreamer(Out, MCInstBuilder(RISCV::AUIPC).addOperand(TmpReg).addExpr(SymbolHi)); + const MCExpr *RefToLinkTmpLabel = RISCVMCExpr::create(MCSymbolRefExpr::create(TmpLabel, Ctx), RISCVMCExpr::VK_RISCV_PCREL_LO, Ctx); + emitToStreamer(Out, MCInstBuilder(SecondOpcode).addOperand(DestReg).addOperand(TmpReg).addExpr(RefToLinkTmpLabel)); + return false; + case RISCV::PseudoLB: + MCOperand DestReg = Inst.getOperand(0); + unsigned SymbolOpIdx = HasTmpReg ? 2 : 1; + unsigned TmpRegOpIdx = HasTmpReg ? 1 : 0; + MCOperand TmpReg = Inst.getOperand(TmpRegOpIdx); + const MCExpr *Symbol = Inst.getOperand(SymbolOpIdx).getExpr(); + MCContext &Ctx = getContext(); + MCSymbol *TmpLabel = Ctx.createNamedTempSymbol("pcrel_hi"); + Out.emitLabel(TmpLabel); + const RISCVMCExpr *SymbolHi = RISCVMCExpr::create(Symbol, VKHi, Ctx); + emitToStreamer(Out, MCInstBuilder(RISCV::AUIPC).addOperand(TmpReg).addExpr(SymbolHi)); + const MCExpr *RefToLinkTmpLabel = RISCVMCExpr::create(MCSymbolRefExpr::create(TmpLabel, Ctx), RISCVMCExpr::VK_RISCV_PCREL_LO, Ctx); + emitToStreamer(Out, MCInstBuilder(SecondOpcode).addOperand(DestReg).addOperand(TmpReg).addExpr(RefToLinkTmpLabel)); + return false; + case RISCV::PseudoLBU: + MCOperand DestReg = Inst.getOperand(0); + unsigned SymbolOpIdx = HasTmpReg ? 2 : 1; + unsigned TmpRegOpIdx = HasTmpReg ? 1 : 0; + MCOperand TmpReg = Inst.getOperand(TmpRegOpIdx); + const MCExpr *Symbol = Inst.getOperand(SymbolOpIdx).getExpr(); + MCContext &Ctx = getContext(); + MCSymbol *TmpLabel = Ctx.createNamedTempSymbol("pcrel_hi"); + Out.emitLabel(TmpLabel); + const RISCVMCExpr *SymbolHi = RISCVMCExpr::create(Symbol, VKHi, Ctx); + emitToStreamer(Out, MCInstBuilder(RISCV::AUIPC).addOperand(TmpReg).addExpr(SymbolHi)); + const MCExpr *RefToLinkTmpLabel = RISCVMCExpr::create(MCSymbolRefExpr::create(TmpLabel, Ctx), RISCVMCExpr::VK_RISCV_PCREL_LO, Ctx); + emitToStreamer(Out, MCInstBuilder(SecondOpcode).addOperand(DestReg).addOperand(TmpReg).addExpr(RefToLinkTmpLabel)); + return false; + case RISCV::PseudoLH: + MCOperand DestReg = Inst.getOperand(0); + unsigned SymbolOpIdx = HasTmpReg ? 2 : 1; + unsigned TmpRegOpIdx = HasTmpReg ? 1 : 0; + MCOperand TmpReg = Inst.getOperand(TmpRegOpIdx); + const MCExpr *Symbol = Inst.getOperand(SymbolOpIdx).getExpr(); + MCContext &Ctx = getContext(); + MCSymbol *TmpLabel = Ctx.createNamedTempSymbol("pcrel_hi"); + Out.emitLabel(TmpLabel); + const RISCVMCExpr *SymbolHi = RISCVMCExpr::create(Symbol, VKHi, Ctx); + emitToStreamer(Out, MCInstBuilder(RISCV::AUIPC).addOperand(TmpReg).addExpr(SymbolHi)); + const MCExpr *RefToLinkTmpLabel = RISCVMCExpr::create(MCSymbolRefExpr::create(TmpLabel, Ctx), RISCVMCExpr::VK_RISCV_PCREL_LO, Ctx); + emitToStreamer(Out, MCInstBuilder(SecondOpcode).addOperand(DestReg).addOperand(TmpReg).addExpr(RefToLinkTmpLabel)); + return false; + case RISCV::PseudoLHU: + MCOperand DestReg = Inst.getOperand(0); + unsigned SymbolOpIdx = HasTmpReg ? 2 : 1; + unsigned TmpRegOpIdx = HasTmpReg ? 1 : 0; + MCOperand TmpReg = Inst.getOperand(TmpRegOpIdx); + const MCExpr *Symbol = Inst.getOperand(SymbolOpIdx).getExpr(); + MCContext &Ctx = getContext(); + MCSymbol *TmpLabel = Ctx.createNamedTempSymbol("pcrel_hi"); + Out.emitLabel(TmpLabel); + const RISCVMCExpr *SymbolHi = RISCVMCExpr::create(Symbol, VKHi, Ctx); + emitToStreamer(Out, MCInstBuilder(RISCV::AUIPC).addOperand(TmpReg).addExpr(SymbolHi)); + const MCExpr *RefToLinkTmpLabel = RISCVMCExpr::create(MCSymbolRefExpr::create(TmpLabel, Ctx), RISCVMCExpr::VK_RISCV_PCREL_LO, Ctx); + emitToStreamer(Out, MCInstBuilder(SecondOpcode).addOperand(DestReg).addOperand(TmpReg).addExpr(RefToLinkTmpLabel)); + return false; + case RISCV::PseudoLW: + MCOperand DestReg = Inst.getOperand(0); + unsigned SymbolOpIdx = HasTmpReg ? 2 : 1; + unsigned TmpRegOpIdx = HasTmpReg ? 1 : 0; + MCOperand TmpReg = Inst.getOperand(TmpRegOpIdx); + const MCExpr *Symbol = Inst.getOperand(SymbolOpIdx).getExpr(); + MCContext &Ctx = getContext(); + MCSymbol *TmpLabel = Ctx.createNamedTempSymbol("pcrel_hi"); + Out.emitLabel(TmpLabel); + const RISCVMCExpr *SymbolHi = RISCVMCExpr::create(Symbol, VKHi, Ctx); + emitToStreamer(Out, MCInstBuilder(RISCV::AUIPC).addOperand(TmpReg).addExpr(SymbolHi)); + const MCExpr *RefToLinkTmpLabel = RISCVMCExpr::create(MCSymbolRefExpr::create(TmpLabel, Ctx), RISCVMCExpr::VK_RISCV_PCREL_LO, Ctx); + emitToStreamer(Out, MCInstBuilder(SecondOpcode).addOperand(DestReg).addOperand(TmpReg).addExpr(RefToLinkTmpLabel)); + return false; + case RISCV::PseudoLWU: + MCOperand DestReg = Inst.getOperand(0); + unsigned SymbolOpIdx = HasTmpReg ? 2 : 1; + unsigned TmpRegOpIdx = HasTmpReg ? 1 : 0; + MCOperand TmpReg = Inst.getOperand(TmpRegOpIdx); + const MCExpr *Symbol = Inst.getOperand(SymbolOpIdx).getExpr(); + MCContext &Ctx = getContext(); + MCSymbol *TmpLabel = Ctx.createNamedTempSymbol("pcrel_hi"); + Out.emitLabel(TmpLabel); + const RISCVMCExpr *SymbolHi = RISCVMCExpr::create(Symbol, VKHi, Ctx); + emitToStreamer(Out, MCInstBuilder(RISCV::AUIPC).addOperand(TmpReg).addExpr(SymbolHi)); + const MCExpr *RefToLinkTmpLabel = RISCVMCExpr::create(MCSymbolRefExpr::create(TmpLabel, Ctx), RISCVMCExpr::VK_RISCV_PCREL_LO, Ctx); + emitToStreamer(Out, MCInstBuilder(SecondOpcode).addOperand(DestReg).addOperand(TmpReg).addExpr(RefToLinkTmpLabel)); + return false; + case RISCV::PseudoLD: + MCOperand DestReg = Inst.getOperand(0); + unsigned SymbolOpIdx = HasTmpReg ? 2 : 1; + unsigned TmpRegOpIdx = HasTmpReg ? 1 : 0; + MCOperand TmpReg = Inst.getOperand(TmpRegOpIdx); + const MCExpr *Symbol = Inst.getOperand(SymbolOpIdx).getExpr(); + MCContext &Ctx = getContext(); + MCSymbol *TmpLabel = Ctx.createNamedTempSymbol("pcrel_hi"); + Out.emitLabel(TmpLabel); + const RISCVMCExpr *SymbolHi = RISCVMCExpr::create(Symbol, VKHi, Ctx); + emitToStreamer(Out, MCInstBuilder(RISCV::AUIPC).addOperand(TmpReg).addExpr(SymbolHi)); + const MCExpr *RefToLinkTmpLabel = RISCVMCExpr::create(MCSymbolRefExpr::create(TmpLabel, Ctx), RISCVMCExpr::VK_RISCV_PCREL_LO, Ctx); + emitToStreamer(Out, MCInstBuilder(SecondOpcode).addOperand(DestReg).addOperand(TmpReg).addExpr(RefToLinkTmpLabel)); + return false; + case RISCV::PseudoFLH: + MCOperand DestReg = Inst.getOperand(0); + unsigned SymbolOpIdx = HasTmpReg ? 2 : 1; + unsigned TmpRegOpIdx = HasTmpReg ? 1 : 0; + MCOperand TmpReg = Inst.getOperand(TmpRegOpIdx); + const MCExpr *Symbol = Inst.getOperand(SymbolOpIdx).getExpr(); + MCContext &Ctx = getContext(); + MCSymbol *TmpLabel = Ctx.createNamedTempSymbol("pcrel_hi"); + Out.emitLabel(TmpLabel); + const RISCVMCExpr *SymbolHi = RISCVMCExpr::create(Symbol, VKHi, Ctx); + emitToStreamer(Out, MCInstBuilder(RISCV::AUIPC).addOperand(TmpReg).addExpr(SymbolHi)); + const MCExpr *RefToLinkTmpLabel = RISCVMCExpr::create(MCSymbolRefExpr::create(TmpLabel, Ctx), RISCVMCExpr::VK_RISCV_PCREL_LO, Ctx); + emitToStreamer(Out, MCInstBuilder(SecondOpcode).addOperand(DestReg).addOperand(TmpReg).addExpr(RefToLinkTmpLabel)); + return false; + case RISCV::PseudoFLW: + MCOperand DestReg = Inst.getOperand(0); + unsigned SymbolOpIdx = HasTmpReg ? 2 : 1; + unsigned TmpRegOpIdx = HasTmpReg ? 1 : 0; + MCOperand TmpReg = Inst.getOperand(TmpRegOpIdx); + const MCExpr *Symbol = Inst.getOperand(SymbolOpIdx).getExpr(); + MCContext &Ctx = getContext(); + MCSymbol *TmpLabel = Ctx.createNamedTempSymbol("pcrel_hi"); + Out.emitLabel(TmpLabel); + const RISCVMCExpr *SymbolHi = RISCVMCExpr::create(Symbol, VKHi, Ctx); + emitToStreamer(Out, MCInstBuilder(RISCV::AUIPC).addOperand(TmpReg).addExpr(SymbolHi)); + const MCExpr *RefToLinkTmpLabel = RISCVMCExpr::create(MCSymbolRefExpr::create(TmpLabel, Ctx), RISCVMCExpr::VK_RISCV_PCREL_LO, Ctx); + emitToStreamer(Out, MCInstBuilder(SecondOpcode).addOperand(DestReg).addOperand(TmpReg).addExpr(RefToLinkTmpLabel)); + return false; + case RISCV::PseudoFLD: + MCOperand DestReg = Inst.getOperand(0); + unsigned SymbolOpIdx = HasTmpReg ? 2 : 1; + unsigned TmpRegOpIdx = HasTmpReg ? 1 : 0; + MCOperand TmpReg = Inst.getOperand(TmpRegOpIdx); + const MCExpr *Symbol = Inst.getOperand(SymbolOpIdx).getExpr(); + MCContext &Ctx = getContext(); + MCSymbol *TmpLabel = Ctx.createNamedTempSymbol("pcrel_hi"); + Out.emitLabel(TmpLabel); + const RISCVMCExpr *SymbolHi = RISCVMCExpr::create(Symbol, VKHi, Ctx); + emitToStreamer(Out, MCInstBuilder(RISCV::AUIPC).addOperand(TmpReg).addExpr(SymbolHi)); + const MCExpr *RefToLinkTmpLabel = RISCVMCExpr::create(MCSymbolRefExpr::create(TmpLabel, Ctx), RISCVMCExpr::VK_RISCV_PCREL_LO, Ctx); + emitToStreamer(Out, MCInstBuilder(SecondOpcode).addOperand(DestReg).addOperand(TmpReg).addExpr(RefToLinkTmpLabel)); + return false; + case RISCV::PseudoSB: + MCOperand DestReg = Inst.getOperand(0); + unsigned SymbolOpIdx = HasTmpReg ? 2 : 1; + unsigned TmpRegOpIdx = HasTmpReg ? 1 : 0; + MCOperand TmpReg = Inst.getOperand(TmpRegOpIdx); + const MCExpr *Symbol = Inst.getOperand(SymbolOpIdx).getExpr(); + MCContext &Ctx = getContext(); + MCSymbol *TmpLabel = Ctx.createNamedTempSymbol("pcrel_hi"); + Out.emitLabel(TmpLabel); + const RISCVMCExpr *SymbolHi = RISCVMCExpr::create(Symbol, VKHi, Ctx); + emitToStreamer(Out, MCInstBuilder(RISCV::AUIPC).addOperand(TmpReg).addExpr(SymbolHi)); + const MCExpr *RefToLinkTmpLabel = RISCVMCExpr::create(MCSymbolRefExpr::create(TmpLabel, Ctx), RISCVMCExpr::VK_RISCV_PCREL_LO, Ctx); + emitToStreamer(Out, MCInstBuilder(SecondOpcode).addOperand(DestReg).addOperand(TmpReg).addExpr(RefToLinkTmpLabel)); + return false; + case RISCV::PseudoSH: + MCOperand DestReg = Inst.getOperand(0); + unsigned SymbolOpIdx = HasTmpReg ? 2 : 1; + unsigned TmpRegOpIdx = HasTmpReg ? 1 : 0; + MCOperand TmpReg = Inst.getOperand(TmpRegOpIdx); + const MCExpr *Symbol = Inst.getOperand(SymbolOpIdx).getExpr(); + MCContext &Ctx = getContext(); + MCSymbol *TmpLabel = Ctx.createNamedTempSymbol("pcrel_hi"); + Out.emitLabel(TmpLabel); + const RISCVMCExpr *SymbolHi = RISCVMCExpr::create(Symbol, VKHi, Ctx); + emitToStreamer(Out, MCInstBuilder(RISCV::AUIPC).addOperand(TmpReg).addExpr(SymbolHi)); + const MCExpr *RefToLinkTmpLabel = RISCVMCExpr::create(MCSymbolRefExpr::create(TmpLabel, Ctx), RISCVMCExpr::VK_RISCV_PCREL_LO, Ctx); + emitToStreamer(Out, MCInstBuilder(SecondOpcode).addOperand(DestReg).addOperand(TmpReg).addExpr(RefToLinkTmpLabel)); + return false; + case RISCV::PseudoSW: + MCOperand DestReg = Inst.getOperand(0); + unsigned SymbolOpIdx = HasTmpReg ? 2 : 1; + unsigned TmpRegOpIdx = HasTmpReg ? 1 : 0; + MCOperand TmpReg = Inst.getOperand(TmpRegOpIdx); + const MCExpr *Symbol = Inst.getOperand(SymbolOpIdx).getExpr(); + MCContext &Ctx = getContext(); + MCSymbol *TmpLabel = Ctx.createNamedTempSymbol("pcrel_hi"); + Out.emitLabel(TmpLabel); + const RISCVMCExpr *SymbolHi = RISCVMCExpr::create(Symbol, VKHi, Ctx); + emitToStreamer(Out, MCInstBuilder(RISCV::AUIPC).addOperand(TmpReg).addExpr(SymbolHi)); + const MCExpr *RefToLinkTmpLabel = RISCVMCExpr::create(MCSymbolRefExpr::create(TmpLabel, Ctx), RISCVMCExpr::VK_RISCV_PCREL_LO, Ctx); + emitToStreamer(Out, MCInstBuilder(SecondOpcode).addOperand(DestReg).addOperand(TmpReg).addExpr(RefToLinkTmpLabel)); + return false; + case RISCV::PseudoSD: + MCOperand DestReg = Inst.getOperand(0); + unsigned SymbolOpIdx = HasTmpReg ? 2 : 1; + unsigned TmpRegOpIdx = HasTmpReg ? 1 : 0; + MCOperand TmpReg = Inst.getOperand(TmpRegOpIdx); + const MCExpr *Symbol = Inst.getOperand(SymbolOpIdx).getExpr(); + MCContext &Ctx = getContext(); + MCSymbol *TmpLabel = Ctx.createNamedTempSymbol("pcrel_hi"); + Out.emitLabel(TmpLabel); + const RISCVMCExpr *SymbolHi = RISCVMCExpr::create(Symbol, VKHi, Ctx); + emitToStreamer(Out, MCInstBuilder(RISCV::AUIPC).addOperand(TmpReg).addExpr(SymbolHi)); + const MCExpr *RefToLinkTmpLabel = RISCVMCExpr::create(MCSymbolRefExpr::create(TmpLabel, Ctx), RISCVMCExpr::VK_RISCV_PCREL_LO, Ctx); + emitToStreamer(Out, MCInstBuilder(SecondOpcode).addOperand(DestReg).addOperand(TmpReg).addExpr(RefToLinkTmpLabel)); + return false; + case RISCV::PseudoFSH: + MCOperand DestReg = Inst.getOperand(0); + unsigned SymbolOpIdx = HasTmpReg ? 2 : 1; + unsigned TmpRegOpIdx = HasTmpReg ? 1 : 0; + MCOperand TmpReg = Inst.getOperand(TmpRegOpIdx); + const MCExpr *Symbol = Inst.getOperand(SymbolOpIdx).getExpr(); + MCContext &Ctx = getContext(); + MCSymbol *TmpLabel = Ctx.createNamedTempSymbol("pcrel_hi"); + Out.emitLabel(TmpLabel); + const RISCVMCExpr *SymbolHi = RISCVMCExpr::create(Symbol, VKHi, Ctx); + emitToStreamer(Out, MCInstBuilder(RISCV::AUIPC).addOperand(TmpReg).addExpr(SymbolHi)); + const MCExpr *RefToLinkTmpLabel = RISCVMCExpr::create(MCSymbolRefExpr::create(TmpLabel, Ctx), RISCVMCExpr::VK_RISCV_PCREL_LO, Ctx); + emitToStreamer(Out, MCInstBuilder(SecondOpcode).addOperand(DestReg).addOperand(TmpReg).addExpr(RefToLinkTmpLabel)); + return false; + case RISCV::PseudoFSW: + MCOperand DestReg = Inst.getOperand(0); + unsigned SymbolOpIdx = HasTmpReg ? 2 : 1; + unsigned TmpRegOpIdx = HasTmpReg ? 1 : 0; + MCOperand TmpReg = Inst.getOperand(TmpRegOpIdx); + const MCExpr *Symbol = Inst.getOperand(SymbolOpIdx).getExpr(); + MCContext &Ctx = getContext(); + MCSymbol *TmpLabel = Ctx.createNamedTempSymbol("pcrel_hi"); + Out.emitLabel(TmpLabel); + const RISCVMCExpr *SymbolHi = RISCVMCExpr::create(Symbol, VKHi, Ctx); + emitToStreamer(Out, MCInstBuilder(RISCV::AUIPC).addOperand(TmpReg).addExpr(SymbolHi)); + const MCExpr *RefToLinkTmpLabel = RISCVMCExpr::create(MCSymbolRefExpr::create(TmpLabel, Ctx), RISCVMCExpr::VK_RISCV_PCREL_LO, Ctx); + emitToStreamer(Out, MCInstBuilder(SecondOpcode).addOperand(DestReg).addOperand(TmpReg).addExpr(RefToLinkTmpLabel)); + return false; + case RISCV::PseudoFSD: + MCOperand DestReg = Inst.getOperand(0); + unsigned SymbolOpIdx = HasTmpReg ? 2 : 1; + unsigned TmpRegOpIdx = HasTmpReg ? 1 : 0; + MCOperand TmpReg = Inst.getOperand(TmpRegOpIdx); + const MCExpr *Symbol = Inst.getOperand(SymbolOpIdx).getExpr(); + MCContext &Ctx = getContext(); + MCSymbol *TmpLabel = Ctx.createNamedTempSymbol("pcrel_hi"); + Out.emitLabel(TmpLabel); + const RISCVMCExpr *SymbolHi = RISCVMCExpr::create(Symbol, VKHi, Ctx); + emitToStreamer(Out, MCInstBuilder(RISCV::AUIPC).addOperand(TmpReg).addExpr(SymbolHi)); + const MCExpr *RefToLinkTmpLabel = RISCVMCExpr::create(MCSymbolRefExpr::create(TmpLabel, Ctx), RISCVMCExpr::VK_RISCV_PCREL_LO, Ctx); + emitToStreamer(Out, MCInstBuilder(SecondOpcode).addOperand(DestReg).addOperand(TmpReg).addExpr(RefToLinkTmpLabel)); + return false; + case RISCV::PseudoAddTPRel: + assert(Inst.getOpcode() == RISCV::PseudoAddTPRel && "Invalid instruction"); + assert(Inst.getOperand(2).isReg() && "Unexpected second operand kind"); + if (Inst.getOperand(2).getReg() != RISCV::X4) { + SMLoc ErrorLoc = ((RISCVOperand &)*Operands[3]).getStartLoc(); + return Error(ErrorLoc, "the second input operand must be tp/x4 when using %tprel_add modifier"); + } + break; + case RISCV::PseudoSEXT_B: + MCOperand DestReg = Inst.getOperand(0); + MCOperand SourceReg = Inst.getOperand(1); + unsigned SecondOpcode = SignExtend ? RISCV::SRAI : RISCV::SRLI; + int64_t ShAmt = (isRV64() ? 64 : 32) - Width; + assert(ShAmt > 0 && "Shift amount must be non-zero."); + emitToStreamer(Out, MCInstBuilder(RISCV::SLLI).addOperand(DestReg).addOperand(SourceReg).addImm(ShAmt)); + emitToStreamer(Out, MCInstBuilder(SecondOpcode).addOperand(DestReg).addOperand(DestReg).addImm(ShAmt)); + return false; + case RISCV::PseudoSEXT_H: + MCOperand DestReg = Inst.getOperand(0); + MCOperand SourceReg = Inst.getOperand(1); + unsigned SecondOpcode = SignExtend ? RISCV::SRAI : RISCV::SRLI; + int64_t ShAmt = (isRV64() ? 64 : 32) - Width; + assert(ShAmt > 0 && "Shift amount must be non-zero."); + emitToStreamer(Out, MCInstBuilder(RISCV::SLLI).addOperand(DestReg).addOperand(SourceReg).addImm(ShAmt)); + emitToStreamer(Out, MCInstBuilder(SecondOpcode).addOperand(DestReg).addOperand(DestReg).addImm(ShAmt)); + return false; + case RISCV::PseudoZEXT_H: + MCOperand DestReg = Inst.getOperand(0); + MCOperand SourceReg = Inst.getOperand(1); + unsigned SecondOpcode = SignExtend ? RISCV::SRAI : RISCV::SRLI; + int64_t ShAmt = (isRV64() ? 64 : 32) - Width; + assert(ShAmt > 0 && "Shift amount must be non-zero."); + emitToStreamer(Out, MCInstBuilder(RISCV::SLLI).addOperand(DestReg).addOperand(SourceReg).addImm(ShAmt)); + emitToStreamer(Out, MCInstBuilder(SecondOpcode).addOperand(DestReg).addOperand(DestReg).addImm(ShAmt)); + return false; + case RISCV::PseudoZEXT_W: + MCOperand DestReg = Inst.getOperand(0); + MCOperand SourceReg = Inst.getOperand(1); + unsigned SecondOpcode = SignExtend ? RISCV::SRAI : RISCV::SRLI; + int64_t ShAmt = (isRV64() ? 64 : 32) - Width; + assert(ShAmt > 0 && "Shift amount must be non-zero."); + emitToStreamer(Out, MCInstBuilder(RISCV::SLLI).addOperand(DestReg).addOperand(SourceReg).addImm(ShAmt)); + emitToStreamer(Out, MCInstBuilder(SecondOpcode).addOperand(DestReg).addOperand(DestReg).addImm(ShAmt)); + return false; + case RISCV::PseudoVMSGEU_VX: + case RISCV::PseudoVMSGEU_VX_M: + case RISCV::PseudoVMSGEU_VX_M_T: + if (Inst.getNumOperands() == 3) { + emitToStreamer(Out, MCInstBuilder(Opcode).addOperand(Inst.getOperand(0)).addOperand(Inst.getOperand(1)).addOperand(Inst.getOperand(2)).addReg(RISCV::NoRegister)); + emitToStreamer(Out, MCInstBuilder(RISCV::VMNAND_MM).addOperand(Inst.getOperand(0)).addOperand(Inst.getOperand(0)).addOperand(Inst.getOperand(0))); + } + else if (Inst.getNumOperands() == 4) { + assert(Inst.getOperand(0).getReg() != RISCV::V0 && "The destination register should not be V0."); + emitToStreamer(Out, MCInstBuilder(Opcode).addOperand(Inst.getOperand(0)).addOperand(Inst.getOperand(1)).addOperand(Inst.getOperand(2)).addOperand(Inst.getOperand(3))); + emitToStreamer(Out, MCInstBuilder(RISCV::VMXOR_MM).addOperand(Inst.getOperand(0)).addOperand(Inst.getOperand(0)).addReg(RISCV::V0)); + } + else if (Inst.getNumOperands() == 5) { + assert(Inst.getOperand(0).getReg() == RISCV::V0 && "The destination register should be V0."); + assert(Inst.getOperand(1).getReg() != RISCV::V0 && "The temporary vector register should not be V0."); + emitToStreamer(Out, MCInstBuilder(Opcode).addOperand(Inst.getOperand(1)).addOperand(Inst.getOperand(2)).addOperand(Inst.getOperand(3)).addOperand(Inst.getOperand(4))); + emitToStreamer(Out, MCInstBuilder(RISCV::VMANDNOT_MM).addOperand(Inst.getOperand(0)).addOperand(Inst.getOperand(0)).addOperand(Inst.getOperand(1))); + } + return false; + case RISCV::PseudoVMSGE_VX: + case RISCV::PseudoVMSGE_VX_M: + case RISCV::PseudoVMSGE_VX_M_T: + if (Inst.getNumOperands() == 3) { + emitToStreamer(Out, MCInstBuilder(Opcode).addOperand(Inst.getOperand(0)).addOperand(Inst.getOperand(1)).addOperand(Inst.getOperand(2)).addReg(RISCV::NoRegister)); + emitToStreamer(Out, MCInstBuilder(RISCV::VMNAND_MM).addOperand(Inst.getOperand(0)).addOperand(Inst.getOperand(0)).addOperand(Inst.getOperand(0))); + } + else if (Inst.getNumOperands() == 4) { + assert(Inst.getOperand(0).getReg() != RISCV::V0 && "The destination register should not be V0."); + emitToStreamer(Out, MCInstBuilder(Opcode).addOperand(Inst.getOperand(0)).addOperand(Inst.getOperand(1)).addOperand(Inst.getOperand(2)).addOperand(Inst.getOperand(3))); + emitToStreamer(Out, MCInstBuilder(RISCV::VMXOR_MM).addOperand(Inst.getOperand(0)).addOperand(Inst.getOperand(0)).addReg(RISCV::V0)); + } + else if (Inst.getNumOperands() == 5) { + assert(Inst.getOperand(0).getReg() == RISCV::V0 && "The destination register should be V0."); + assert(Inst.getOperand(1).getReg() != RISCV::V0 && "The temporary vector register should not be V0."); + emitToStreamer(Out, MCInstBuilder(Opcode).addOperand(Inst.getOperand(1)).addOperand(Inst.getOperand(2)).addOperand(Inst.getOperand(3)).addOperand(Inst.getOperand(4))); + emitToStreamer(Out, MCInstBuilder(RISCV::VMANDNOT_MM).addOperand(Inst.getOperand(0)).addOperand(Inst.getOperand(0)).addOperand(Inst.getOperand(1))); + } + return false; + case RISCV::PseudoVMSGE_VI: + case RISCV::PseudoVMSLT_VI: { + int64_t Imm = Inst.getOperand(2).getImm(); + unsigned Opc = Inst.getOpcode() == RISCV::PseudoVMSGE_VI ? RISCV::VMSGT_VI : RISCV::VMSLE_VI; + emitToStreamer(Out, MCInstBuilder(Opc).addOperand(Inst.getOperand(0)).addOperand(Inst.getOperand(1)).addImm(Imm - 1).addOperand(Inst.getOperand(3))); + return false; + } + case RISCV::PseudoVMSGEU_VI: + case RISCV::PseudoVMSLTU_VI: { + int64_t Imm = Inst.getOperand(2).getImm(); + if (Imm == 0) { + unsigned Opc = Inst.getOpcode() == RISCV::PseudoVMSGEU_VI ? RISCV::VMSEQ_VV : RISCV::VMSNE_VV; + emitToStreamer(Out, MCInstBuilder(Opc).addOperand(Inst.getOperand(0)).addOperand(Inst.getOperand(1)).addOperand(Inst.getOperand(1)).addOperand(Inst.getOperand(3))); + } + else { + unsigned Opc = Inst.getOpcode() == RISCV::PseudoVMSGEU_VI ? RISCV::VMSGTU_VI : RISCV::VMSLEU_VI; + emitToStreamer(Out, MCInstBuilder(Opc).addOperand(Inst.getOperand(0)).addOperand(Inst.getOperand(1)).addImm(Imm - 1).addOperand(Inst.getOperand(3))); + } + return false; + } + } + emitToStreamer(Out, Inst); + return false; + case Match_MissingFeature: { + assert(MissingFeatures.any() && "Unknown missing features!"); + bool FirstFeature = true; + std::string Msg = "instruction requires the following:"; + for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i) { + if (MissingFeatures[i]) { + Msg += FirstFeature ? " " : ", "; + Msg += getSubtargetFeatureName(i); + FirstFeature = false; + } + } + return Error(IDLoc, Msg); + } + case Match_MnemonicFail: { + FeatureBitset FBS = ComputeAvailableFeatures(getSTI().getFeatureBits()); + std::string Suggestion = RISCVMnemonicSpellCheck(((RISCVOperand &)*Operands[0]).getToken(), FBS); + return Error(IDLoc, "unrecognized instruction mnemonic" + Suggestion); + } + case Match_InvalidOperand: { + SMLoc ErrorLoc = IDLoc; + if (ErrorInfo != ~0U) { + if (ErrorInfo >= Operands.size()) { + return Error(ErrorLoc, "too few operands for instruction"); + } + ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc(); + if (ErrorLoc == SMLoc()) { + ErrorLoc = IDLoc; + } + } + return Error(ErrorLoc, "invalid operand for instruction"); + } + } + if (Result > FIRST_TARGET_MATCH_RESULT_TY) { + SMLoc ErrorLoc = IDLoc; + if (ErrorInfo != ~0U && ErrorInfo >= Operands.size()) { + return Error(ErrorLoc, "too few operands for instruction"); + } + } + if (Result == Match_InvalidImmXLenLI) { + if (isRV64()) { + SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc(); + return Error(ErrorLoc, "operand must be a constant 64-bit integer"); + } + return generateImmOutOfRangeError(Operands, ErrorInfo, std::numeric_limits::min(), std::numeric_limits::max()); + } + if (Result == Match_InvalidImmZero) { + SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc(); + return Error(ErrorLoc, "immediate must be zero"); + } + if (Result == Match_InvalidUImmLog2XLen) { + if (isRV64()) { + return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 6) - 1); + } + return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 5) - 1); + } + if (Result == Match_InvalidUImmLog2XLenNonZero) { + if (isRV64()) { + return generateImmOutOfRangeError(Operands, ErrorInfo, 1, (1 << 6) - 1); + } + return generateImmOutOfRangeError(Operands, ErrorInfo, 1, (1 << 5) - 1); + } + if (Result == Match_InvalidUImmLog2XLenHalf) { + if (isRV64()) { + return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 5) - 1); + } + return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 4) - 1); + } + if (Result == Match_InvalidUImm5) { + return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 5) - 1); + } + if (Result == Match_InvalidSImm5) { + return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 4), (1 << 4) - 1); + } + if (Result == Match_InvalidSImm6) { + return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 5), (1 << 5) - 1); + } + if (Result == Match_InvalidSImm6NonZero) { + return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 5), (1 << 5) - 1, "immediate must be non-zero in the range"); + } + if (Result == Match_InvalidCLUIImm) { + return generateImmOutOfRangeError(Operands, ErrorInfo, 1, (1 << 5) - 1, "immediate must be in [0xfffe0, 0xfffff] or"); + } + if (Result == Match_InvalidUImm7Lsb00) { + return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 7) - 4, "immediate must be a multiple of 4 bytes in the range"); + } + if (Result == Match_InvalidUImm8Lsb00) { + return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 8) - 4, "immediate must be a multiple of 4 bytes in the range"); + } + if (Result == Match_InvalidUImm8Lsb000) { + return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 8) - 8, "immediate must be a multiple of 8 bytes in the range"); + } + if (Result == Match_InvalidSImm9Lsb0) { + return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 8), (1 << 8) - 2, "immediate must be a multiple of 2 bytes in the range"); + } + if (Result == Match_InvalidUImm9Lsb000) { + return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 8), (1 << 8) - 2, "immediate must be a multiple of 2 bytes in the range"); + } + if (Result == Match_InvalidUImm10Lsb00NonZero) { + return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 8), (1 << 8) - 2, "immediate must be a multiple of 2 bytes in the range"); + } + if (Result == Match_InvalidSImm10Lsb0000NonZero) { + return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 8), (1 << 8) - 2, "immediate must be a multiple of 2 bytes in the range"); + } + if (Result == Match_InvalidSImm12) { + return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 8), (1 << 8) - 2, "immediate must be a multiple of 2 bytes in the range"); + } + if (Result == Match_InvalidSImm12Lsb0) { + return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 8), (1 << 8) - 2, "immediate must be a multiple of 2 bytes in the range"); + } + if (Result == Match_InvalidSImm13Lsb0) { + return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 8), (1 << 8) - 2, "immediate must be a multiple of 2 bytes in the range"); + } + if (Result == Match_InvalidUImm20LUI) { + return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 8), (1 << 8) - 2, "immediate must be a multiple of 2 bytes in the range"); + } + if (Result == Match_InvalidUImm20AUIPC) { + return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 8), (1 << 8) - 2, "immediate must be a multiple of 2 bytes in the range"); + } + if (Result == Match_InvalidSImm21Lsb0JAL) { + return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 8), (1 << 8) - 2, "immediate must be a multiple of 2 bytes in the range"); + } + if (Result == Match_InvalidCSRSystemRegister) { + return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 8), (1 << 8) - 2, "immediate must be a multiple of 2 bytes in the range"); + } + if (Result == Match_InvalidFenceArg) { + SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc(); + return Error(ErrorLoc, "operand must be formed of letters selected in-order from 'iorw'"); + } + if (Result == Match_InvalidFRMArg) { + SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc(); + return Error(ErrorLoc, "operand must be formed of letters selected in-order from 'iorw'"); + } + if (Result == Match_InvalidBareSymbol) { + SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc(); + return Error(ErrorLoc, "operand must be formed of letters selected in-order from 'iorw'"); + } + if (Result == Match_InvalidPseudoJumpSymbol) { + SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc(); + return Error(ErrorLoc, "operand must be formed of letters selected in-order from 'iorw'"); + } + if (Result == Match_InvalidCallSymbol) { + SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc(); + return Error(ErrorLoc, "operand must be formed of letters selected in-order from 'iorw'"); + } + if (Result == Match_InvalidTPRelAddSymbol) { + SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc(); + return Error(ErrorLoc, "operand must be formed of letters selected in-order from 'iorw'"); + } + if (Result == Match_InvalidVTypeI) { + SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc(); + return Error(ErrorLoc, "operand must be formed of letters selected in-order from 'iorw'"); + } + if (Result == Match_InvalidVMaskRegister) { + SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc(); + return Error(ErrorLoc, "operand must be formed of letters selected in-order from 'iorw'"); + } + if (Result == Match_InvalidSImm5Plus1) { + return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 4) + 1, (1 << 4), "immediate must be in the range"); + } + llvm_unreachable("Unknown match type detected!"); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/Operand.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/Operand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ad138dbf9306883ea3346180a9391df10b1586d0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/Operand.cpp @@ -0,0 +1,2 @@ +RISCVOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/Operand2.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/Operand2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..63faea7f475d64855bbadb5f070b7ef2b0026308 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/Operand2.cpp @@ -0,0 +1,21 @@ +RISCVOperand(const RISCVOperand &o) : MCParsedAsmOperand() { + Kind = o.Kind; + IsRV64 = o.IsRV64; + StartLoc = o.StartLoc; + EndLoc = o.EndLoc; + if (Kind == KindTy::Register) { + Reg = o.Reg; + } + if (Kind == KindTy::Immediate) { + Imm = o.Imm; + } + if (Kind == KindTy::Token) { + Tok = o.Tok; + } + if (Kind == KindTy::SystemRegister) { + SysReg = o.SysReg; + } + if (Kind == KindTy::VType) { + VType = o.VType; + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/ParseDirective.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/ParseDirective.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af12e125e12358102bf5a3e08bf0bd44dfaf4e1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/ParseDirective.cpp @@ -0,0 +1,437 @@ +bool RISCVAsmParser::ParseDirective(AsmToken DirectiveID) { + StringRef IDVal = DirectiveID.getString(); + if (IDVal == ".option") { + MCAsmParser &Parser = getParser(); + AsmToken Tok = Parser.getTok(); + if (Tok.isNot(AsmToken::Identifier)) { + return Error(Parser.getTok().getLoc(), "unexpected token, expected identifier"); + } + StringRef Option = Tok.getIdentifier(); + if (Option == "push") { + getTargetStreamer().emitDirectiveOptionPush(); + Parser.Lex(); + if (Parser.getTok().isNot(AsmToken::EndOfStatement)) { + return Error(Parser.getTok().getLoc(), "unexpected token, expected end of statement"); + } + assert(FeatureBitStack.size() == ParserOptionsStack.size() && "These two stacks must be kept synchronized"); + FeatureBitStack.push_back(getSTI().getFeatureBits()); + ParserOptionsStack.push_back(ParserOptions); + return false; + } + if (Option == "pop") { + SMLoc StartLoc = Parser.getTok().getLoc(); + getTargetStreamer().emitDirectiveOptionPop(); + Parser.Lex(); + if (Parser.getTok().isNot(AsmToken::EndOfStatement)) { + return Error(Parser.getTok().getLoc(), "unexpected token, expected end of statement"); + } + assert(FeatureBitStack.size() == ParserOptionsStack.size() && "These two stacks must be kept synchronized"); + if (FeatureBitStack.empty()) { + return Error(StartLoc, ".option pop with no .option push"); + } + FeatureBitset FeatureBits = FeatureBitStack.pop_back_val(); + copySTI().setFeatureBits(FeatureBits); + setAvailableFeatures(ComputeAvailableFeatures(FeatureBits)); + ParserOptions = ParserOptionsStack.pop_back_val(); + return false; + } + if (Option == "rvc") { + getTargetStreamer().emitDirectiveOptionRVC(); + Parser.Lex(); + if (Parser.getTok().isNot(AsmToken::EndOfStatement)) { + return Error(Parser.getTok().getLoc(), "unexpected token, expected end of statement"); + } + setFeatureBits(RISCV::FeatureStdExtC, "c"); + return false; + } + if (Option == "norvc") { + getTargetStreamer().emitDirectiveOptionNoRVC(); + Parser.Lex(); + if (Parser.getTok().isNot(AsmToken::EndOfStatement)) { + return Error(Parser.getTok().getLoc(), "unexpected token, expected end of statement"); + } + clearFeatureBits(RISCV::FeatureStdExtC, "c"); + return false; + } + if (Option == "pic") { + getTargetStreamer().emitDirectiveOptionPIC(); + Parser.Lex(); + if (Parser.getTok().isNot(AsmToken::EndOfStatement)) { + return Error(Parser.getTok().getLoc(), "unexpected token, expected end of statement"); + } + ParserOptions.IsPicEnabled = true; + return false; + } + if (Option == "nopic") { + getTargetStreamer().emitDirectiveOptionNoPIC(); + Parser.Lex(); + if (Parser.getTok().isNot(AsmToken::EndOfStatement)) { + return Error(Parser.getTok().getLoc(), "unexpected token, expected end of statement"); + } + ParserOptions.IsPicEnabled = false; + return false; + } + if (Option == "relax") { + getTargetStreamer().emitDirectiveOptionRelax(); + Parser.Lex(); + if (Parser.getTok().isNot(AsmToken::EndOfStatement)) { + return Error(Parser.getTok().getLoc(), "unexpected token, expected end of statement"); + } + setFeatureBits(RISCV::FeatureRelax, "relax"); + return false; + } + if (Option == "norelax") { + getTargetStreamer().emitDirectiveOptionNoRelax(); + Parser.Lex(); + if (Parser.getTok().isNot(AsmToken::EndOfStatement)) { + return Error(Parser.getTok().getLoc(), "unexpected token, expected end of statement"); + } + clearFeatureBits(RISCV::FeatureRelax, "relax"); + return false; + } + Warning(Parser.getTok().getLoc(), "unknown option, expected 'push', 'pop', 'rvc', 'norvc', 'relax' or 'norelax'"); + Parser.eatToEndOfStatement(); + return false; + } + else if (IDVal == ".attribute") { + MCAsmParser &Parser = getParser(); + int64_t Tag; + SMLoc TagLoc; + TagLoc = Parser.getTok().getLoc(); + if (Parser.getTok().is(AsmToken::Identifier)) { + StringRef Name = Parser.getTok().getIdentifier(); + Optional Ret = ELFAttrs::attrTypeFromString(Name, RISCVAttrs::RISCVAttributeTags); + if (!Ret.hasValue()) { + Error(TagLoc, "attribute name not recognised: " + Name); + return false; + } + Tag = Ret.getValue(); + Parser.Lex(); + } + else { + const MCExpr *AttrExpr; + TagLoc = Parser.getTok().getLoc(); + if (Parser.parseExpression(AttrExpr)) { + return true; + } + const MCConstantExpr *CE = dyn_cast(AttrExpr); + if (check(!CE, TagLoc, "expected numeric constant")) { + return true; + } + Tag = CE->getValue(); + } + if (Parser.parseToken(AsmToken::Comma, "comma expected")) { + return true; + } + StringRef StringValue; + int64_t IntegerValue = 0; + bool IsIntegerValue = true; + if (Tag % 2) { + IsIntegerValue = false; + } + SMLoc ValueExprLoc = Parser.getTok().getLoc(); + if (IsIntegerValue) { + const MCExpr *ValueExpr; + if (Parser.parseExpression(ValueExpr)) { + return true; + } + const MCConstantExpr *CE = dyn_cast(ValueExpr); + if (!CE) { + return true; + } + IntegerValue = CE->getValue(); + } + else { + if (Parser.getTok().isNot(AsmToken::String)) { + return Error(Parser.getTok().getLoc(), "expected string constant"); + } + StringValue = Parser.getTok().getStringContents(); + Parser.Lex(); + } + if (Parser.parseToken(AsmToken::EndOfStatement, "unexpected token in '.attribute' directive")) { + return true; + } + if (Tag == RISCVAttrs::ARCH) { + StringRef Arch = StringValue; + if (Arch.consume_front("rv32")) { + if (getSTI().getFeatureBits()[RISCV::Feature64Bit]) { + MCSubtargetInfo &STI = copySTI(); + setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature("64bit"))); + } + } + else if (Arch.consume_front("rv64")) { + setFeatureBits(RISCV::Feature64Bit, "64bit"); + } + else { + return Error(ValueExprLoc, "bad arch string " + Arch); + } + if (getSTI().getFeatureBits()[RISCV::FeatureRV32E]) { + MCSubtargetInfo &STI = copySTI(); + setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature("e"))); + } + if (getSTI().getFeatureBits()[RISCV::FeatureStdExtM]) { + MCSubtargetInfo &STI = copySTI(); + setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature("m"))); + } + if (getSTI().getFeatureBits()[RISCV::FeatureStdExtA]) { + MCSubtargetInfo &STI = copySTI(); + setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature("a"))); + } + if (getSTI().getFeatureBits()[RISCV::FeatureStdExtF]) { + MCSubtargetInfo &STI = copySTI(); + setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature("f"))); + } + if (getSTI().getFeatureBits()[RISCV::FeatureStdExtD]) { + MCSubtargetInfo &STI = copySTI(); + setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature("d"))); + } + if (getSTI().getFeatureBits()[RISCV::FeatureStdExtC]) { + MCSubtargetInfo &STI = copySTI(); + setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature("c"))); + } + if (getSTI().getFeatureBits()[RISCV::FeatureStdExtB]) { + MCSubtargetInfo &STI = copySTI(); + setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature("experimental-b"))); + } + if (getSTI().getFeatureBits()[RISCV::FeatureStdExtV]) { + MCSubtargetInfo &STI = copySTI(); + setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature("experimental-v"))); + } + if (getSTI().getFeatureBits()[RISCV::FeatureExtZfh]) { + MCSubtargetInfo &STI = copySTI(); + setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature("experimental-zfh"))); + } + if (getSTI().getFeatureBits()[RISCV::FeatureExtZba]) { + MCSubtargetInfo &STI = copySTI(); + setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature("experimental-zba"))); + } + if (getSTI().getFeatureBits()[RISCV::FeatureExtZbb]) { + MCSubtargetInfo &STI = copySTI(); + setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature("experimental-zbb"))); + } + if (getSTI().getFeatureBits()[RISCV::FeatureExtZbc]) { + MCSubtargetInfo &STI = copySTI(); + setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature("experimental-zbc"))); + } + if (getSTI().getFeatureBits()[RISCV::FeatureExtZbe]) { + MCSubtargetInfo &STI = copySTI(); + setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature("experimental-zbe"))); + } + if (getSTI().getFeatureBits()[RISCV::FeatureExtZbf]) { + MCSubtargetInfo &STI = copySTI(); + setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature("experimental-zbf"))); + } + if (getSTI().getFeatureBits()[RISCV::FeatureExtZbm]) { + MCSubtargetInfo &STI = copySTI(); + setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature("experimental-zbm"))); + } + if (getSTI().getFeatureBits()[RISCV::FeatureExtZbp]) { + MCSubtargetInfo &STI = copySTI(); + setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature("experimental-zbp"))); + } + if (getSTI().getFeatureBits()[RISCV::FeatureExtZbproposedc]) { + MCSubtargetInfo &STI = copySTI(); + setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature("experimental-zbproposedc"))); + } + if (getSTI().getFeatureBits()[RISCV::FeatureExtZbr]) { + MCSubtargetInfo &STI = copySTI(); + setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature("experimental-zbr"))); + } + if (getSTI().getFeatureBits()[RISCV::FeatureExtZbs]) { + MCSubtargetInfo &STI = copySTI(); + setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature("experimental-zbs"))); + } + if (getSTI().getFeatureBits()[RISCV::FeatureExtZbt]) { + MCSubtargetInfo &STI = copySTI(); + setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature("experimental-zbt"))); + } + if (getSTI().getFeatureBits()[RISCV::FeatureExtZvamo]) { + MCSubtargetInfo &STI = copySTI(); + setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature("experimental-zvamo"))); + } + if (getSTI().getFeatureBits()[RISCV::FeatureStdExtZvlsseg]) { + MCSubtargetInfo &STI = copySTI(); + setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature("experimental-zvlsseg"))); + } + while (!Arch.empty()) { + bool DropFirst = true; + if (Arch[0] == 'i') { + if (getSTI().getFeatureBits()[RISCV::FeatureRV32E]) { + MCSubtargetInfo &STI = copySTI(); + setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature("e"))); + } + } + else if (Arch[0] == 'e') { + setFeatureBits(RISCV::FeatureRV32E, "e"); + } + else if (Arch[0] == 'g') { + if (getSTI().getFeatureBits()[RISCV::FeatureRV32E]) { + MCSubtargetInfo &STI = copySTI(); + setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature("e"))); + } + setFeatureBits(RISCV::FeatureStdExtM, "m"); + setFeatureBits(RISCV::FeatureStdExtA, "a"); + setFeatureBits(RISCV::FeatureStdExtF, "f"); + setFeatureBits(RISCV::FeatureStdExtD, "d"); + } + else if (Arch[0] == 'm') { + setFeatureBits(RISCV::FeatureStdExtM, "m"); + } + else if (Arch[0] == 'a') { + setFeatureBits(RISCV::FeatureStdExtA, "a"); + } + else if (Arch[0] == 'f') { + setFeatureBits(RISCV::FeatureStdExtF, "f"); + } + else if (Arch[0] == 'd') { + setFeatureBits(RISCV::FeatureStdExtF, "f"); + setFeatureBits(RISCV::FeatureStdExtD, "d"); + } + else if (Arch[0] == 'c') { + setFeatureBits(RISCV::FeatureStdExtC, "c"); + } + else if (Arch[0] == 'b') { + setFeatureBits(RISCV::FeatureStdExtB, "experimental-b"); + } + else if (Arch[0] == 'v') { + setFeatureBits(RISCV::FeatureStdExtV, "experimental-v"); + } + else if (Arch[0] == 's' || Arch[0] == 'x' || Arch[0] == 'z') { + StringRef Ext = Arch.take_until([](char c) { return ::isdigit(c) || c == '_'; }); + if (Ext == "zba") { + setFeatureBits(RISCV::FeatureExtZba, "experimental-zba"); + } + else if (Ext == "zbb") { + setFeatureBits(RISCV::FeatureExtZbb, "experimental-zbb"); + } + else if (Ext == "zbc") { + setFeatureBits(RISCV::FeatureExtZbc, "experimental-zbc"); + } + else if (Ext == "zbe") { + setFeatureBits(RISCV::FeatureExtZbe, "experimental-zbe"); + } + else if (Ext == "zbf") { + setFeatureBits(RISCV::FeatureExtZbf, "experimental-zbf"); + } + else if (Ext == "zbm") { + setFeatureBits(RISCV::FeatureExtZbm, "experimental-zbm"); + } + else if (Ext == "zbp") { + setFeatureBits(RISCV::FeatureExtZbp, "experimental-zbp"); + } + else if (Ext == "zbproposedc") { + setFeatureBits(RISCV::FeatureExtZbproposedc, "experimental-zbproposedc"); + } + else if (Ext == "zbr") { + setFeatureBits(RISCV::FeatureExtZbr, "experimental-zbr"); + } + else if (Ext == "zbs") { + setFeatureBits(RISCV::FeatureExtZbs, "experimental-zbs"); + } + else if (Ext == "zbt") { + setFeatureBits(RISCV::FeatureExtZbt, "experimental-zbt"); + } + else if (Ext == "zfh") { + setFeatureBits(RISCV::FeatureExtZfh, "experimental-zfh"); + } + else if (Ext == "zvamo") { + setFeatureBits(RISCV::FeatureExtZvamo, "experimental-zvamo"); + } + else if (Ext == "zvlsseg") { + setFeatureBits(RISCV::FeatureStdExtZvlsseg, "experimental-zvlsseg"); + } + else { + return Error(ValueExprLoc, "bad arch string " + Ext); + } + Arch = Arch.drop_until([](char c) { return ::isdigit(c) || c == '_'; }); + DropFirst = false; + } + else { + return Error(ValueExprLoc, "bad arch string " + Arch); + } + if (DropFirst) { + Arch = Arch.drop_front(1); + } + int major = 0; + int minor = 0; + Arch.consumeInteger(10, major); + Arch.consume_front("p"); + Arch.consumeInteger(10, minor); + Arch = Arch.drop_while([](char c) { return c == '_'; }); + } + } + if (IsIntegerValue) { + getTargetStreamer().emitAttribute(Tag, IntegerValue); + } + else { + if (Tag != RISCVAttrs::ARCH) { + getTargetStreamer().emitTextAttribute(Tag, StringValue); + } + else { + std::string formalArchStr = "rv32"; + if (getFeatureBits(RISCV::Feature64Bit)) + formalArchStr = "rv64"; + if (getFeatureBits(RISCV::FeatureRV32E)) + formalArchStr = (Twine(formalArchStr) + "e1p9").str(); + else + formalArchStr = (Twine(formalArchStr) + "i2p0").str(); + if (getFeatureBits(RISCV::FeatureStdExtM)) + formalArchStr = (Twine(formalArchStr) + "_m2p0").str(); + if (getFeatureBits(RISCV::FeatureStdExtA)) + formalArchStr = (Twine(formalArchStr) + "_a2p0").str(); + if (getFeatureBits(RISCV::FeatureStdExtF)) + formalArchStr = (Twine(formalArchStr) + "_f2p0").str(); + if (getFeatureBits(RISCV::FeatureStdExtD)) + formalArchStr = (Twine(formalArchStr) + "_d2p0").str(); + if (getFeatureBits(RISCV::FeatureStdExtC)) + formalArchStr = (Twine(formalArchStr) + "_c2p0").str(); + if (getFeatureBits(RISCV::FeatureStdExtB)) + formalArchStr = (Twine(formalArchStr) + "_b0p93").str(); + if (getFeatureBits(RISCV::FeatureStdExtV)) + formalArchStr = (Twine(formalArchStr) + "_v0p10").str(); + if (getFeatureBits(RISCV::FeatureExtZfh)) + formalArchStr = (Twine(formalArchStr) + "_zfh0p1").str(); + if (getFeatureBits(RISCV::FeatureExtZba)) + formalArchStr = (Twine(formalArchStr) + "_zba0p93").str(); + if (getFeatureBits(RISCV::FeatureExtZbb)) + formalArchStr = (Twine(formalArchStr) + "_zbb0p93").str(); + if (getFeatureBits(RISCV::FeatureExtZbc)) { + formalArchStr = (Twine(formalArchStr) + "_zbc0p93").str(); + } + if (getFeatureBits(RISCV::FeatureExtZbe)) { + formalArchStr = (Twine(formalArchStr) + "_zbe0p93").str(); + } + if (getFeatureBits(RISCV::FeatureExtZbf)) { + formalArchStr = (Twine(formalArchStr) + "_zbf0p93").str(); + } + if (getFeatureBits(RISCV::FeatureExtZbm)) { + formalArchStr = (Twine(formalArchStr) + "_zbm0p93").str(); + } + if (getFeatureBits(RISCV::FeatureExtZbp)) { + formalArchStr = (Twine(formalArchStr) + "_zbp0p93").str(); + } + if (getFeatureBits(RISCV::FeatureExtZbproposedc)) { + formalArchStr = (Twine(formalArchStr) + "_zbproposedc0p93").str(); + } + if (getFeatureBits(RISCV::FeatureExtZbr)) { + formalArchStr = (Twine(formalArchStr) + "_zbr0p93").str(); + } + if (getFeatureBits(RISCV::FeatureExtZbs)) { + formalArchStr = (Twine(formalArchStr) + "_zbs0p93").str(); + } + if (getFeatureBits(RISCV::FeatureExtZbt)) { + formalArchStr = (Twine(formalArchStr) + "_zbt0p93").str(); + } + if (getFeatureBits(RISCV::FeatureExtZvamo)) { + formalArchStr = (Twine(formalArchStr) + "_zvamo0p10").str(); + } + if (getFeatureBits(RISCV::FeatureStdExtZvlsseg)) { + formalArchStr = (Twine(formalArchStr) + "_zvlsseg0p10").str(); + } + getTargetStreamer().emitTextAttribute(Tag, formalArchStr); + } + } + return false; + } + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/ParseInstruction.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/ParseInstruction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7e9cdadb0936ababf2f6c45f59c54e181e9d21a4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/ParseInstruction.cpp @@ -0,0 +1,31 @@ +bool RISCVAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, OperandVector &Operands) { + if (getSTI().getFeatureBits()[RISCV::FeatureRelax]) { + auto *Assembler = getTargetStreamer().getStreamer().getAssemblerPtr(); + if (Assembler != nullptr) { + RISCVAsmBackend &MAB = static_cast(Assembler->getBackend()); + MAB.setForceRelocs(); + } + } + Operands.push_back(RISCVOperand::createToken(Name, NameLoc, isRV64())); + if (getLexer().is(AsmToken::EndOfStatement)) { + return false; + } + if (parseOperand(Operands, Name)) { + return true; + } + unsigned OperandIdx = 1; + while (getLexer().is(AsmToken::Comma)) { + getLexer().Lex(); + if (parseOperand(Operands, Name)) { + return true; + } + ++OperandIdx; + } + if (getLexer().isNot(AsmToken::EndOfStatement)) { + SMLoc Loc = getLexer().getLoc(); + getParser().eatToEndOfStatement(); + return Error(Loc, "unexpected token"); + } + getParser().Lex(); + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/ParseRegister.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/ParseRegister.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a5d4359121cc681b1667e4b723d63f8a260df120 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/ParseRegister.cpp @@ -0,0 +1,6 @@ +bool RISCVAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) { + if (tryParseRegister(RegNo, StartLoc, EndLoc) != MatchOperand_Success) { + return Error(StartLoc, "invalid register name"); + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/addCSRSystemRegisterOperands.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/addCSRSystemRegisterOperands.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ccc9683fc9110594147015b16f0c9b51543c0d2d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/addCSRSystemRegisterOperands.cpp @@ -0,0 +1,4 @@ +void addCSRSystemRegisterOperands(MCInst &Inst, unsigned N) const { + assert(N == 1 && "Invalid number of operands!"); + Inst.addOperand(MCOperand::createImm(SysReg.Encoding)); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/addExpr.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/addExpr.cpp new file mode 100644 index 0000000000000000000000000000000000000000..214fe9f44a01731c40c1084f3ff205132df9e262 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/addExpr.cpp @@ -0,0 +1,12 @@ +void addExpr(MCInst &Inst, const MCExpr *Expr) const { + assert(Expr && "Expr shouldn't be null!"); + int64_t Imm = 0; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + bool IsConstant = evaluateConstantImm(Expr, Imm, VK); + if (IsConstant) { + Inst.addOperand(MCOperand::createImm(Imm)); + } + else { + Inst.addOperand(MCOperand::createExpr(Expr)); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/addFRMArgOperands.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/addFRMArgOperands.cpp new file mode 100644 index 0000000000000000000000000000000000000000..73d49a88563d2c4aca26d1c150579bc82e0babf2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/addFRMArgOperands.cpp @@ -0,0 +1,4 @@ +void addFRMArgOperands(MCInst &Inst, unsigned N) const { + assert(N == 1 && "Invalid number of operands!"); + Inst.addOperand(MCOperand::createImm(getRoundingMode())); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/addFenceArgOperands.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/addFenceArgOperands.cpp new file mode 100644 index 0000000000000000000000000000000000000000..792d4fa164c9d9d497708692cc4167f5c14775a5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/addFenceArgOperands.cpp @@ -0,0 +1,16 @@ +void addFenceArgOperands(MCInst &Inst, unsigned N) const { + assert(N == 1 && "Invalid number of operands!"); + auto SE = cast(getImm()); + unsigned Imm = 0; + for (char c : SE->getSymbol().getName()) { + switch (c) { + default: + llvm_unreachable("FenceArg must contain only [iorw]"); + case 'i': Imm |= RISCVFenceField::I; break; + case 'o': Imm |= RISCVFenceField::O; break; + case 'r': Imm |= RISCVFenceField::R; break; + case 'w': Imm |= RISCVFenceField::W; break; + } + } + Inst.addOperand(MCOperand::createImm(Imm)); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/addImmOperands.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/addImmOperands.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a69f8ac923d9234ea41ac4606011cacda986f3e5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/addImmOperands.cpp @@ -0,0 +1,4 @@ +void addImmOperands(MCInst &Inst, unsigned N) const { + assert(N == 1 && "Invalid number of operands!"); + addExpr(Inst, getImm()); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/addRegOperands.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/addRegOperands.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0238a375be523b4d683ea934130d2e5390c7dfa7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/addRegOperands.cpp @@ -0,0 +1,4 @@ +void addRegOperands(MCInst &Inst, unsigned N) const { + assert(N == 1 && "Invalid number of operands!"); + Inst.addOperand(MCOperand::createReg(getReg())); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/addVTypeIOperands.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/addVTypeIOperands.cpp new file mode 100644 index 0000000000000000000000000000000000000000..47fb952384ac089c38b1615985b2fdd2e107225f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/addVTypeIOperands.cpp @@ -0,0 +1,4 @@ +void addVTypeIOperands(MCInst &Inst, unsigned N) const { + assert(N == 1 && "Invalid number of operands!"); + Inst.addOperand(MCOperand::createImm(getVType())); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/classifySymbolRef.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/classifySymbolRef.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e84a90bbcd6b57ad4a18f3de6f079fab9ea6ef6a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/classifySymbolRef.cpp @@ -0,0 +1,13 @@ +bool RISCVAsmParser::classifySymbolRef(const MCExpr *Expr, MCExpr::VariantKind &Kind) { + Kind = RISCVMCExpr::VK_RISCV_None; + if (const RISCVMCExpr *RE = dyn_cast(Expr)) { + Kind = RE->getKind(); + Expr = RE->getSubExpr(); + } + MCValue Res; + MCFixup Fixup; + if (Expr->evaluateAsRelocatable(Res, nullptr, &Fixup)) { + return Res.getRefKind() == RISCVMCExpr::VK_RISCV_None; + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/convertFPR64ToFPR16.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/convertFPR64ToFPR16.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e026cba6a73b81985778dc9bb3c9d65b32fb1666 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/convertFPR64ToFPR16.cpp @@ -0,0 +1,4 @@ +static MCRegister convertFPR64ToFPR16(MCRegister Reg) { + assert(Reg >= RISCV::F0_D && Reg <= RISCV::F31_D && "Invalid register"); + return Reg - RISCV::F0_D + RISCV::F0_H; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/convertFPR64ToFPR32.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/convertFPR64ToFPR32.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6f4dc9ae940f1dd462ac08522f4c04f563e554d8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/convertFPR64ToFPR32.cpp @@ -0,0 +1,4 @@ +static MCRegister convertFPR64ToFPR32(MCRegister Reg) { + assert(Reg >= RISCV::F0_D && Reg <= RISCV::F31_D && "Invalid register"); + return Reg - RISCV::F0_D + RISCV::F0_F; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/createImm.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/createImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..399ee2614f3b539f1368f7c10cdc6e506119e381 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/createImm.cpp @@ -0,0 +1,8 @@ +static std::unique_ptr createImm(const MCExpr *Val, SMLoc S, SMLoc E, bool IsRV64) { + auto Op = std::make_unique(KindTy::Immediate); + Op->Imm.Val = Val; + Op->StartLoc = S; + Op->EndLoc = E; + Op->IsRV64 = IsRV64; + return Op; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/createReg.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/createReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6c2c43a6a8093aa2194f4fba74917b2fc21eb193 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/createReg.cpp @@ -0,0 +1,8 @@ +static std::unique_ptr createReg(unsigned RegNo, SMLoc S, SMLoc E, bool IsRV64) { + auto Op = std::make_unique(KindTy::Register); + Op->Reg.RegNum = RegNo; + Op->StartLoc = S; + Op->EndLoc = E; + Op->IsRV64 = IsRV64; + return Op; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/createSysReg.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/createSysReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1b7a2657c346e52c22ccd28703bc5baa75cff344 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/createSysReg.cpp @@ -0,0 +1,9 @@ +static std::unique_ptr createSysReg(StringRef Str, SMLoc S, unsigned Encoding, bool IsRV64) { + auto Op = std::make_unique(KindTy::SystemRegister); + Op->SysReg.Data = Str.data(); + Op->SysReg.Length = Str.size(); + Op->SysReg.Encoding = Encoding; + Op->StartLoc = S; + Op->IsRV64 = IsRV64; + return Op; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/createToken.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/createToken.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bdaa650df5adf6dc96daae935f42ae08ac7f4283 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/createToken.cpp @@ -0,0 +1,8 @@ +static std::unique_ptr createToken(StringRef Str, SMLoc S, bool IsRV64) { + auto Op = std::make_unique(KindTy::Token); + Op->Tok = Str; + Op->StartLoc = S; + Op->EndLoc = S; + Op->IsRV64 = IsRV64; + return Op; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/createVType.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/createVType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4deb57ffa06e779c7e3e92cae9f34bdba8a9d9b9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/createVType.cpp @@ -0,0 +1,7 @@ +static std::unique_ptr createVType(unsigned VTypeI, SMLoc S, bool IsRV64) { + auto Op = std::make_unique(KindTy::VType); + Op->VType.Val = VTypeI; + Op->StartLoc = S; + Op->IsRV64 = IsRV64; + return Op; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/defaultMaskRegOp.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/defaultMaskRegOp.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b022f4d2360a1bb7aae0c7121a89aae81ffb4c75 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/defaultMaskRegOp.cpp @@ -0,0 +1,3 @@ +std::unique_ptr RISCVAsmParser::defaultMaskRegOp() const { + return RISCVOperand::createReg(RISCV::NoRegister, llvm::SMLoc(), llvm::SMLoc(), isRV64()); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/emitToStreamer.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/emitToStreamer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..85deea136f491e311c7514cc7cc3319a332e069d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/emitToStreamer.cpp @@ -0,0 +1,9 @@ +void RISCVAsmParser::emitToStreamer(MCStreamer &S, const MCInst &Inst) { + MCInst CInst; + bool Res = false; + Res = compressInst(CInst, Inst, getSTI(), S.getContext()); + if (Res) { + RISCVNumInstrsCompressed = RISCVNumInstrsCompressed + 1; + } + S.emitInstruction((Res ? CInst : Inst), getSTI()); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/evaluateConstantImm.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/evaluateConstantImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..66157e504bc3b499d080b12e3a0c1b14ae434c52 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/evaluateConstantImm.cpp @@ -0,0 +1,12 @@ +static bool evaluateConstantImm(const MCExpr *Expr, int64_t &Imm, RISCVMCExpr::VariantKind &VK) { + if (auto *RE = dyn_cast(Expr)) { + VK = RE->getKind(); + return RE->evaluateAsConstant(Imm); + } + if (auto CE = dyn_cast(Expr)) { + VK = RISCVMCExpr::VK_RISCV_None; + Imm = CE->getValue(); + return true; + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/generateImmOutOfRangeError.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/generateImmOutOfRangeError.cpp new file mode 100644 index 0000000000000000000000000000000000000000..38a0c63d84cc29155e89b8f20de13c896c70af91 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/generateImmOutOfRangeError.cpp @@ -0,0 +1,4 @@ +bool RISCVAsmParser::generateImmOutOfRangeError(OperandVector &Operands, uint64_t ErrorInfo, int64_t Lower, int64_t Upper, Twine Msg = "immediate must be an integer in the range") { + SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc(); + return Error(ErrorLoc, Msg + " [" + Twine(Lower) + ", " + Twine(Upper) + "]"); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/getEndLoc.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/getEndLoc.cpp new file mode 100644 index 0000000000000000000000000000000000000000..62829900d768fc89d50171419f738e8ec8124b58 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/getEndLoc.cpp @@ -0,0 +1,3 @@ +SMLoc getEndLoc() const override { + return EndLoc; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/getFeatureBits.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/getFeatureBits.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f8b7d6acceee057eaf23f6023ac5aa0493a08037 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/getFeatureBits.cpp @@ -0,0 +1,3 @@ +bool getFeatureBits(uint64_t Feature) { + return getFeatureBits()[Feature]; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/getImm.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/getImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..680aa6e8b7c97665bca7b25e7ba715d083360048 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/getImm.cpp @@ -0,0 +1,4 @@ +const MCExpr *getImm() const { + assert(Kind == KindTy::Immediate && "Invalid type access!"); + return Imm.Val; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/getLoc.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/getLoc.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ee06922bf6091cbb8ed19c3dcc5b42aa0335fbc5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/getLoc.cpp @@ -0,0 +1,3 @@ +SMLoc getLoc() const { + return getParser().getTok().getLoc(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/getReg.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/getReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b727268741262d50d0b7be12f8f224ae221d70d5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/getReg.cpp @@ -0,0 +1,4 @@ +unsigned getReg() const override { + assert(Kind == KindTy::Register && "Invalid type access!"); + return Reg.RegNum.id(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/getRoundingMode.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/getRoundingMode.cpp new file mode 100644 index 0000000000000000000000000000000000000000..59bafeff69c9ddbdeac847d8c5295be2781a6739 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/getRoundingMode.cpp @@ -0,0 +1,6 @@ +RISCVFPRndMode::RoundingMode getRoundingMode() const { + auto SE = cast(getImm()); + RISCVFPRndMode::RoundingMode FRM = RISCVFPRndMode::stringToRoundingMode(SE->getSymbol().getName()); + assert(FRM != RISCVFPRndMode::Invalid && "Invalid rounding mode"); + return FRM; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/getStartLoc.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/getStartLoc.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1468c5ab73e31cdbf7622d7fb4cc05414acef937 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/getStartLoc.cpp @@ -0,0 +1,3 @@ +SMLoc getStartLoc() const override { + return StartLoc; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/getSysReg.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/getSysReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c409acf907d63507ebf66c33bb6055965fddc7a7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/getSysReg.cpp @@ -0,0 +1,4 @@ +StringRef getSysReg() const { + assert(Kind == KindTy::SystemRegister && "Invalid type access!"); + return StringRef(SysReg.Data, SysReg.Length); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/getTargetStreamer.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/getTargetStreamer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e3c9c2ce61d650ef0464f9b4aa2539d390a2e11e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/getTargetStreamer.cpp @@ -0,0 +1,4 @@ +RISCVTargetStreamer &getTargetStreamer() { + MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer(); + return static_cast(TS); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/getToken.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/getToken.cpp new file mode 100644 index 0000000000000000000000000000000000000000..445834686b5ec1bb686bda4abcc004a4ec9ee82a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/getToken.cpp @@ -0,0 +1,4 @@ +StringRef getToken() const { + assert(Kind == KindTy::Token && "Invalid type access!"); + return Tok; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/getVType.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/getVType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..af123b58f738de16129e3a5fbb1a323ecf40eb1f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/getVType.cpp @@ -0,0 +1,4 @@ +unsigned getVType() const { + assert(Kind == KindTy::VType && "Invalid type access!"); + return VType.Val; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isBareSimmNLsb0.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isBareSimmNLsb0.cpp new file mode 100644 index 0000000000000000000000000000000000000000..dfd9e592f1bb7c039a98e85fd4c7a525b677fe69 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isBareSimmNLsb0.cpp @@ -0,0 +1,16 @@ +template bool isBareSimmNLsb0() const { + if (!isImm()) { + return false; + } + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + int64_t Imm; + bool IsValid; + bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); + if (IsConstantImm) { + IsValid = isShiftedInt(Imm); + } + if (!IsConstantImm) { + IsValid = RISCVAsmParser::classifySymbolRef(getImm(), VK); + } + return IsValid && VK == RISCVMCExpr::VK_RISCV_None; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isBareSymbol.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isBareSymbol.cpp new file mode 100644 index 0000000000000000000000000000000000000000..48a01b62fd0d0730ca3fbc3730793c50e55ab55a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isBareSymbol.cpp @@ -0,0 +1,14 @@ +bool isBareSymbol() const { + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + if (!isImm()) { + return false; + } + if (evaluateConstantImm(getImm(), Imm, VK)) { + return false; + } + if (!evaluateConstantImm(getImm(), Imm, VK)) { + return RISCVAsmParser::classifySymbolRef(getImm(), VK) && VK == RISCVMCExpr::VK_RISCV_None; + } + return RISCVAsmParser::classifySymbolRef(getImm(), VK) && VK == RISCVMCExpr::VK_RISCV_None; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isCLUIImm.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isCLUIImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f89c302eb8bc0bcfca47f2f9845303081503982d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isCLUIImm.cpp @@ -0,0 +1,11 @@ +bool isCLUIImm() const { + if (!isImm()) { + return false; + } + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + if (evaluateConstantImm(getImm(), Imm, VK)) { + return (Imm != 0) && (isUInt<5>(Imm) || (Imm >= 0xfffe0 && Imm <= 0xfffff)) && VK == RISCVMCExpr::VK_RISCV_None; + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isCSRSystemRegister.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isCSRSystemRegister.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ffb7bbbe9a914a516b01cc030bf81758a80e3270 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isCSRSystemRegister.cpp @@ -0,0 +1,3 @@ +bool isCSRSystemRegister() const { + return Kind == KindTy::SystemRegister; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isCallSymbol.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isCallSymbol.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d6142f6614dfe57e8c93e793847ae07ddf837848 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isCallSymbol.cpp @@ -0,0 +1,11 @@ +bool isCallSymbol() const { + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + if (!isImm()) { + return false; + } + if (evaluateConstantImm(getImm(), Imm, VK)) { + return false; + } + return RISCVAsmParser::classifySymbolRef(getImm(), VK) && (VK == RISCVMCExpr::VK_RISCV_CALL || VK == RISCVMCExpr::VK_RISCV_CALL_PLT); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isFRMArg.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isFRMArg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..98df83b42fc3323559573c60f0e7a30405f28bdb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isFRMArg.cpp @@ -0,0 +1,12 @@ +bool isFRMArg() const { + if (!isImm()) { + return false; + } + const MCExpr *Val = getImm(); + auto *SVal = dyn_cast(Val); + if (!SVal || SVal->getKind() != MCSymbolRefExpr::VK_None) { + return false; + } + StringRef Str = SVal->getSymbol().getName(); + return RISCVFPRndMode::stringToRoundingMode(Str) != RISCVFPRndMode::Invalid; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isFenceArg.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isFenceArg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..41d6f3f46374b1b9a6e6634a0de10b1bba1ef5ac --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isFenceArg.cpp @@ -0,0 +1,22 @@ +bool isFenceArg() const { + if (!isImm()) { + return false; + } + const MCExpr *Val = getImm(); + auto *SVal = dyn_cast(Val); + if (!SVal || SVal->getKind() != MCSymbolRefExpr::VK_None) { + return false; + } + StringRef Str = SVal->getSymbol().getName(); + char Prev = '\0'; + for (char c : Str) { + if (c != 'i' && c != 'o' && c != 'r' && c != 'w') { + return false; + } + if (c <= Prev) { + return false; + } + Prev = c; + } + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isGPR.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isGPR.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e2990020b5ef61ab36d27572763e8f15efb9772d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isGPR.cpp @@ -0,0 +1,3 @@ +bool isGPR() const { + return Kind == KindTy::Register && RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg.RegNum); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isImm.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..400db8c5883144be4963e33031283ae54db7ddf7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isImm.cpp @@ -0,0 +1,3 @@ +bool isImm() const override { + return Kind == KindTy::Immediate; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isImmXLenLI.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isImmXLenLI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b460d989d40ad769b6179758abfe2864344e640e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isImmXLenLI.cpp @@ -0,0 +1,11 @@ +bool isImmXLenLI() const { + if (!isImm()) { + return false; + } + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + if (evaluateConstantImm(getImm(), Imm, VK)) { + return VK == RISCVMCExpr::VK_RISCV_LO || VK == RISCVMCExpr::VK_RISCV_PCREL_LO || (VK == RISCVMCExpr::VK_RISCV_None && (isRV64() || (isInt<32>(Imm) || isUInt<32>(Imm)))); + } + return IsValid && VK == zmtarzmMCExpr :: VK_RISCV_LO || VK == zmtarzmMCExpr :: VK_RISCV_PCREL_LO ; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isMem.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isMem.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c43c1fbf793d7bd6d2e893e67962bd3cccf94715 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isMem.cpp @@ -0,0 +1,3 @@ +bool isMem() const override { + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isPseudoJumpSymbol.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isPseudoJumpSymbol.cpp new file mode 100644 index 0000000000000000000000000000000000000000..eec91dbdac1b9ab829dccf99b39973eded1da5b0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isPseudoJumpSymbol.cpp @@ -0,0 +1,11 @@ +bool isPseudoJumpSymbol() const { + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + if (!isImm()) { + return false; + } + if (evaluateConstantImm(getImm(), Imm, VK)) { + return false; + } + return RISCVAsmParser::classifySymbolRef(getImm(), VK) && VK == RISCVMCExpr::VK_RISCV_CALL; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isRV32E.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isRV32E.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c21e42e5f798bcb0e6b8f92f3a3cc1dd96f87b44 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isRV32E.cpp @@ -0,0 +1,3 @@ +bool isRV32E() const { + return getSTI().hasFeature(RISCV::FeatureRV32E); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isRV64-2.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isRV64-2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..383cfa600df6dac196f2c01b85967a5b0fee19c4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isRV64-2.cpp @@ -0,0 +1,3 @@ +bool isRV64() const { + return IsRV64; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isRV64.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isRV64.cpp new file mode 100644 index 0000000000000000000000000000000000000000..eec7fe92227f97b819ea0ba36ff7b64f641acbce --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isRV64.cpp @@ -0,0 +1,3 @@ +bool isRV64() const { + return getSTI().hasFeature(RISCV::Feature64Bit); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isReg.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fcb79a981f0b63d5b3d34a12ff7dc35589d32480 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isReg.cpp @@ -0,0 +1,3 @@ +bool isReg() const override { + return Kind == KindTy::Register; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isSImm10Lsb0000NonZero.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isSImm10Lsb0000NonZero.cpp new file mode 100644 index 0000000000000000000000000000000000000000..24d6dc2d00014b75b1869a58e1b07898a4404222 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isSImm10Lsb0000NonZero.cpp @@ -0,0 +1,11 @@ +bool isSImm10Lsb0000NonZero() const { + if (!isImm()) { + return false; + } + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + if (evaluateConstantImm(getImm(), Imm, VK)) { + return (Imm != 0) && isShiftedInt<6, 4>(Imm) && VK == RISCVMCExpr::VK_RISCV_None; + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isSImm12.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isSImm12.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2dcd623be87da6b40f0c329d74836d9aca17d455 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isSImm12.cpp @@ -0,0 +1,16 @@ +bool isSImm12() const { + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + int64_t Imm; + bool IsValid; + if (!isImm()) { + return false; + } + bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); + if (!IsConstantImm) { + IsValid = RISCVAsmParser::classifySymbolRef(getImm(), VK); + } + else { + IsValid = isInt<12>(Imm); + } + return IsValid && ((IsConstantImm && VK == RISCVMCExpr::VK_RISCV_None) || VK == RISCVMCExpr::VK_RISCV_LO || VK == RISCVMCExpr::VK_RISCV_PCREL_LO || VK == RISCVMCExpr::VK_RISCV_TPREL_LO); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isSImm12Lsb0.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isSImm12Lsb0.cpp new file mode 100644 index 0000000000000000000000000000000000000000..63073bc64c003ca0e83e707b57b7a4ea9c9ce158 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isSImm12Lsb0.cpp @@ -0,0 +1,14 @@ +bool isSImm12Lsb0() const { + if (!isImm()) { + return false; + } + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + if (evaluateConstantImm(getImm(), Imm, VK)) { + return isShiftedInt<11, 1>(Imm) && VK == RISCVMCExpr::VK_RISCV_None; + } + if (!evaluateConstantImm(getImm(), Imm, VK)) { + return RISCVAsmParser::classifySymbolRef(getImm(), VK) && VK == RISCVMCExpr::VK_RISCV_None; + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isSImm13Lsb0.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isSImm13Lsb0.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7f6c636265bd63d8a777132c2a0eb78dbb54be86 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isSImm13Lsb0.cpp @@ -0,0 +1,14 @@ +bool isSImm13Lsb0() const { + if (!isImm()) { + return false; + } + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + if (evaluateConstantImm(getImm(), Imm, VK)) { + return isShiftedInt<12, 1>(Imm) && VK == RISCVMCExpr::VK_RISCV_None; + } + if (!evaluateConstantImm(getImm(), Imm, VK)) { + return RISCVAsmParser::classifySymbolRef(getImm(), VK) && VK == RISCVMCExpr::VK_RISCV_None; + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isSImm21Lsb0JAL.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isSImm21Lsb0JAL.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b33656f8aabf36763566f623cf1f73adabe6177f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isSImm21Lsb0JAL.cpp @@ -0,0 +1,14 @@ +bool isSImm21Lsb0JAL() const { + if (!isImm()) { + return false; + } + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + if (evaluateConstantImm(getImm(), Imm, VK)) { + return isShiftedInt<20, 1>(Imm) && VK == RISCVMCExpr::VK_RISCV_None; + } + if (!evaluateConstantImm(getImm(), Imm, VK)) { + return RISCVAsmParser::classifySymbolRef(getImm(), VK) && VK == RISCVMCExpr::VK_RISCV_None; + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isSImm5.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isSImm5.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1b64ab3a9e82f435809b69ee895c34d33b707169 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isSImm5.cpp @@ -0,0 +1,11 @@ +bool isSImm5() const { + if (!isImm()) { + return false; + } + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + if (evaluateConstantImm(getImm(), Imm, VK)) { + return isInt<5>(Imm) && VK == RISCVMCExpr::VK_RISCV_None; + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isSImm5Plus1.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isSImm5Plus1.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fe561ca354d6609427bfe55244528003bf886fd7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isSImm5Plus1.cpp @@ -0,0 +1,11 @@ +bool isSImm5Plus1() const { + if (!isImm()) { + return false; + } + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + if (evaluateConstantImm(getImm(), Imm, VK)) { + return isInt<5>(Imm - 1) && VK == RISCVMCExpr::VK_RISCV_None; + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isSImm6.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isSImm6.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5b111421d4683f6af55ac579d99981703d94ad9e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isSImm6.cpp @@ -0,0 +1,11 @@ +bool isSImm6() const { + if (!isImm()) { + return false; + } + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + if (evaluateConstantImm(getImm(), Imm, VK)) { + return isInt<6>(Imm) && VK == RISCVMCExpr::VK_RISCV_None; + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isSImm6NonZero.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isSImm6NonZero.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b717a48ce5bbedd11d8b6a832de0ef2f398f66d8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isSImm6NonZero.cpp @@ -0,0 +1,11 @@ +bool isSImm6NonZero() const { + if (!isImm()) { + return false; + } + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + if (evaluateConstantImm(getImm(), Imm, VK)) { + return isInt<6>(Imm) && (Imm != 0) && VK == RISCVMCExpr::VK_RISCV_None; + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isSImm9Lsb0.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isSImm9Lsb0.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0ad3cbc4906910b459fb690b753c04ad71f3c7c8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isSImm9Lsb0.cpp @@ -0,0 +1,14 @@ +bool isSImm9Lsb0() const { + if (!isImm()) { + return false; + } + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + if (evaluateConstantImm(getImm(), Imm, VK)) { + return isShiftedInt<8, 1>(Imm) && VK == RISCVMCExpr::VK_RISCV_None; + } + if (!evaluateConstantImm(getImm(), Imm, VK)) { + return RISCVAsmParser::classifySymbolRef(getImm(), VK) && VK == RISCVMCExpr::VK_RISCV_None; + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isSystemRegister.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isSystemRegister.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0f392bfff3b4e8e84b2ff2a1435e84f8d71aa647 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isSystemRegister.cpp @@ -0,0 +1,3 @@ +bool isSystemRegister() const { + return Kind == KindTy::SystemRegister; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isTPRelAddSymbol.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isTPRelAddSymbol.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bbd00f01251645ec33d1af74a00e138f137a715c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isTPRelAddSymbol.cpp @@ -0,0 +1,8 @@ +bool isTPRelAddSymbol() const { + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + if (!isImm() || evaluateConstantImm(getImm(), Imm, VK)) { + return false; + } + return RISCVAsmParser::classifySymbolRef(getImm(), VK) && VK == RISCVMCExpr::VK_RISCV_TPREL_ADD; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isToken.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isToken.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a1dfb1dd6786afb1f04ef6c6a933834f7bf532f1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isToken.cpp @@ -0,0 +1,3 @@ +bool isToken() const override { + return Kind == KindTy::Token; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isUImm1.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isUImm1.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a7a4b5b9b58ffe125f4a0cc5cddc62daf6255dc3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isUImm1.cpp @@ -0,0 +1,9 @@ +bool isUImm1() const { + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + if (!isImm()) { + return false; + } + bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); + return IsConstantImm && isUInt<1>(Imm) && VK == RISCVMCExpr::VK_RISCV_None; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isUImm10Lsb00NonZero.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isUImm10Lsb00NonZero.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8e919d0e2c50071258ae1f27c9354a25e023d0c5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isUImm10Lsb00NonZero.cpp @@ -0,0 +1,11 @@ +bool isUImm10Lsb00NonZero() const { + if (!isImm()) { + return false; + } + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + if (evaluateConstantImm(getImm(), Imm, VK)) { + return isShiftedUInt<8, 2>(Imm) && (Imm != 0) && VK == RISCVMCExpr::VK_RISCV_None; + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isUImm12.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isUImm12.cpp new file mode 100644 index 0000000000000000000000000000000000000000..217a4d76c95bfa35ee512214b63fa497d2a6478c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isUImm12.cpp @@ -0,0 +1,16 @@ +bool isUImm12() const { + RISCVMCExpr::VariantKind VK; + int64_t Imm; + bool IsValid; + if (!isImm()) { + return false; + } + bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); + if (!IsConstantImm) { + IsValid = RISCVAsmParser::classifySymbolRef(getImm(), VK); + } + else { + IsValid = isUInt<12>(Imm); + } + return IsValid && ((IsConstantImm && VK == RISCVMCExpr::VK_RISCV_None) || VK == RISCVMCExpr::VK_RISCV_LO || VK == RISCVMCExpr::VK_RISCV_PCREL_LO || VK == RISCVMCExpr::VK_RISCV_TPREL_LO); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isUImm12M1.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isUImm12M1.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ef62975a219e5dd8e2789a537c91854699273287 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isUImm12M1.cpp @@ -0,0 +1,9 @@ +bool isUImm12M1() const { + if (!isImm()) { + return false; + } + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + int64_t Imm; + bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); + return IsConstantImm && isUInt<12>(Imm) && (Imm != 0) && VK == RISCVMCExpr::VK_RISCV_None; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isUImm13Lsb0.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isUImm13Lsb0.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6bbf8b9df408abe759c8eeeaf32eea827d816dc9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isUImm13Lsb0.cpp @@ -0,0 +1,9 @@ +bool isUImm13Lsb0() const { + if (!isImm()) { + return false; + } + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); + return IsConstantImm && isShiftedUInt<12, 1>(Imm) && VK == RISCVMCExpr::VK_RISCV_None; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isUImm20AUIPC.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isUImm20AUIPC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..89b7a149611af05f335eaf59e3f8cd3648411d75 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isUImm20AUIPC.cpp @@ -0,0 +1,16 @@ +bool isUImm20AUIPC() const { + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + int64_t Imm; + bool IsValid; + if (!isImm()) { + return false; + } + bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); + if (!IsConstantImm) { + IsValid = RISCVAsmParser::classifySymbolRef(getImm(), VK); + return IsValid && (VK == RISCVMCExpr::VK_RISCV_PCREL_HI || VK == RISCVMCExpr::VK_RISCV_GOT_HI || VK == RISCVMCExpr::VK_RISCV_TLS_GOT_HI || VK == RISCVMCExpr::VK_RISCV_TLS_GD_HI); + } + else { + return isUInt<20>(Imm) && (VK == RISCVMCExpr::VK_RISCV_None || VK == RISCVMCExpr::VK_RISCV_PCREL_HI || VK == RISCVMCExpr::VK_RISCV_GOT_HI || VK == RISCVMCExpr::VK_RISCV_TLS_GOT_HI || VK == RISCVMCExpr::VK_RISCV_TLS_GD_HI); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isUImm20LUI.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isUImm20LUI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..923f243b5e92bda4596b995757b38cfc685d1ec9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isUImm20LUI.cpp @@ -0,0 +1,16 @@ +bool isUImm20LUI() const { + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + int64_t Imm; + bool IsValid; + if (!isImm()) { + return false; + } + bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); + if (!IsConstantImm) { + IsValid = RISCVAsmParser::classifySymbolRef(getImm(), VK); + return IsValid && (VK == RISCVMCExpr::VK_RISCV_HI || VK == RISCVMCExpr::VK_RISCV_TPREL_HI); + } + else { + return isUInt<20>(Imm) && (VK == RISCVMCExpr::VK_RISCV_None || VK == RISCVMCExpr::VK_RISCV_HI || VK == RISCVMCExpr::VK_RISCV_TPREL_HI); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isUImm3.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isUImm3.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2153b241ddd40511331dd4303dbc0530c58398c1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isUImm3.cpp @@ -0,0 +1,9 @@ +bool isUImm3() const { + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + if (!isImm()) { + return false; + } + bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); + return IsConstantImm && isUInt<3>(Imm) && VK == RISCVMCExpr::VK_RISCV_None; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isUImm4.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isUImm4.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1d2e08c7ba12d0a6bcba3bbaafe7b9a79c27a6d3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isUImm4.cpp @@ -0,0 +1,9 @@ +bool isUImm4() const { + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + if (!isImm()) { + return false; + } + bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); + return IsConstantImm && isUInt<4>(Imm) && VK == RISCVMCExpr::VK_RISCV_None; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isUImm5.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isUImm5.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b18cb034281c59c4c483e7321ee15b4dcafff652 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isUImm5.cpp @@ -0,0 +1,9 @@ +bool isUImm5() const { + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + if (!isImm()) { + return false; + } + bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); + return IsConstantImm && isUInt<5>(Imm) && VK == RISCVMCExpr::VK_RISCV_None; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isUImm6.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isUImm6.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b1b95853447047f6d14cdefe9b4f4e452a5d2f32 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isUImm6.cpp @@ -0,0 +1,9 @@ +bool isUImm6() const { + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + if (!isImm()) { + return false; + } + bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); + return IsConstantImm && isUInt<6>(Imm) && VK == RISCVMCExpr::VK_RISCV_None; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isUImm6Lsb0.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isUImm6Lsb0.cpp new file mode 100644 index 0000000000000000000000000000000000000000..234cb7b22253e6019bf4ce64a42c24ef26df1389 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isUImm6Lsb0.cpp @@ -0,0 +1,16 @@ +bool isUImm6Lsb0() const { + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + if (!isImm()) { + return false; + } + bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); + bool IsValid; + if (!IsConstantImm) { + IsValid = RISCVAsmParser::classifySymbolRef(getImm(), VK); + } + else { + IsValid = isShiftedUInt<5, 1>(Imm); + } + return IsValid && VK == RISCVMCExpr::VK_RISCV_None; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isUImm7Lsb00.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isUImm7Lsb00.cpp new file mode 100644 index 0000000000000000000000000000000000000000..24c29da9a8cbed9c78d112302095c0013b32a31b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isUImm7Lsb00.cpp @@ -0,0 +1,9 @@ +bool isUImm7Lsb00() const { + if (!isImm()) { + return false; + } + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); + return IsConstantImm && isShiftedUInt<5, 2>(Imm) && VK == RISCVMCExpr::VK_RISCV_None; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isUImm8Lsb00.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isUImm8Lsb00.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3ccc5fd5ffb3c7162ff7165e1f056db0ff5f0f83 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isUImm8Lsb00.cpp @@ -0,0 +1,9 @@ +bool isUImm8Lsb00() const { + if (!isImm()) { + return false; + } + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); + return IsConstantImm && isShiftedUInt<6, 2>(Imm) && VK == RISCVMCExpr::VK_RISCV_None; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isUImm8Lsb000.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isUImm8Lsb000.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7eff26abdf3912a7976c2c7a67e9a024b47ea6bb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isUImm8Lsb000.cpp @@ -0,0 +1,9 @@ +bool isUImm8Lsb000() const { + if (!isImm()) { + return false; + } + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); + return IsConstantImm && isShiftedUInt<5, 3>(Imm) && VK == RISCVMCExpr::VK_RISCV_None; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isUImm9Lsb000.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isUImm9Lsb000.cpp new file mode 100644 index 0000000000000000000000000000000000000000..06310c952d4c996d47144ed5e65f84d235458aaf --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isUImm9Lsb000.cpp @@ -0,0 +1,9 @@ +bool isUImm9Lsb000() const { + if (!isImm()) { + return false; + } + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); + return IsConstantImm && isShiftedUInt<6, 3>(Imm) && VK == RISCVMCExpr::VK_RISCV_None; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isUImmLog2XLen.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isUImmLog2XLen.cpp new file mode 100644 index 0000000000000000000000000000000000000000..76c5c7d94ae735807c0e08a8ba26d4a441ba3b1d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isUImmLog2XLen.cpp @@ -0,0 +1,11 @@ +bool isUImmLog2XLen() const { + if (!isImm()) { + return false; + } + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + if (evaluateConstantImm(getImm(), Imm, VK)) { + return VK == RISCVMCExpr::VK_RISCV_None && ((isRV64() && isUInt<6>(Imm)) || isUInt<5>(Imm)); + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isUImmLog2XLenHalf.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isUImmLog2XLenHalf.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e962acbdddc793ea296bb646aa7e1829f29c1078 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isUImmLog2XLenHalf.cpp @@ -0,0 +1,11 @@ +bool isUImmLog2XLenHalf() const { + if (!isImm()) { + return false; + } + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + if (evaluateConstantImm(getImm(), Imm, VK)) { + return VK == RISCVMCExpr::VK_RISCV_None; + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isUImmLog2XLenNonZero.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isUImmLog2XLenNonZero.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4a00a205afacb1a8befa223480ef0e27092c6336 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isUImmLog2XLenNonZero.cpp @@ -0,0 +1,11 @@ +bool isUImmLog2XLenNonZero() const { + if (!isImm()) { + return false; + } + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + if (evaluateConstantImm(getImm(), Imm, VK)) { + return VK == RISCVMCExpr::VK_RISCV_None; + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isV0Reg.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isV0Reg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3925060552980f02dcfb4ddf2b3390f7ee29ab33 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isV0Reg.cpp @@ -0,0 +1,3 @@ +bool isV0Reg() const { + return Kind == KindTy::Register && Reg.RegNum == RISCV::V0; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isVType.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isVType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..19e3cbf2a0f73d6ef2c860853164a4697d40546f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isVType.cpp @@ -0,0 +1,3 @@ +bool isVType() const { + return Kind == KindTy::VType; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isVTypeI.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isVTypeI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..19e3cbf2a0f73d6ef2c860853164a4697d40546f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/isVTypeI.cpp @@ -0,0 +1,3 @@ +bool isVType() const { + return Kind == KindTy::VType; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/matchRegisterNameHelper.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/matchRegisterNameHelper.cpp new file mode 100644 index 0000000000000000000000000000000000000000..27ae49e62bcf881645cbe1722de6c7742918c0d5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/matchRegisterNameHelper.cpp @@ -0,0 +1,14 @@ +static bool matchRegisterNameHelper(bool IsRV32E, MCRegister &RegNo, StringRef Name) { + RegNo = MatchRegisterName(Name); + assert(!(RegNo >= RISCV::F0_H && RegNo <= RISCV::F31_H)); + assert(!(RegNo >= RISCV::F0_F && RegNo <= RISCV::F31_F)); + static_assert(RISCV::F0_D < RISCV::F0_H, "FPR matching must be updated"); + static_assert(RISCV::F0_D < RISCV::F0_F, "FPR matching must be updated"); + if (RegNo == RISCV::NoRegister) { + RegNo = MatchRegisterAltName(Name); + } + if (IsRV32E && RegNo >= RISCV::X16 && RegNo <= RISCV::X31) { + RegNo = RISCV::NoRegister; + } + return RegNo == RISCV::NoRegister; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/parseAtomicMemOp.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/parseAtomicMemOp.cpp new file mode 100644 index 0000000000000000000000000000000000000000..73fa5f840b2095a3ff4d84b0a43741fcb127a04b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/parseAtomicMemOp.cpp @@ -0,0 +1,31 @@ +OperandMatchResultTy RISCVAsmParser::parseAtomicMemOp(OperandVector &Operands) { + std::unique_ptr OptionalImmOp; + if (getLexer().isNot(AsmToken::LParen)) { + int64_t ImmVal; + SMLoc ImmStart = getLoc(); + if (getParser().parseIntToken(ImmVal, "expected '(' or optional integer offset")) { + return MatchOperand_ParseFail; + } + SMLoc ImmEnd = getLoc(); + OptionalImmOp = RISCVOperand::createImm(MCConstantExpr::create(ImmVal, getContext()), ImmStart, ImmEnd, isRV64()); + } + if (getLexer().isNot(AsmToken::LParen)) { + Error(getLoc(), OptionalImmOp ? "expected '(' after optional integer offset" : "expected '(' or optional integer offset"); + return MatchOperand_ParseFail; + } + getParser().Lex(); + if (parseRegister(Operands) != MatchOperand_Success) { + Error(getLoc(), "expected register"); + return MatchOperand_ParseFail; + } + if (getLexer().isNot(AsmToken::RParen)) { + Error(getLoc(), "expected ')'"); + return MatchOperand_ParseFail; + } + getParser().Lex(); + if (OptionalImmOp && !OptionalImmOp->isImmZero()) { + Error(OptionalImmOp->getStartLoc(), "optional integer offset must be 0", SMRange(OptionalImmOp->getStartLoc(), OptionalImmOp->getEndLoc())); + return MatchOperand_ParseFail; + } + return MatchOperand_Success; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/parseBareSymbol.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/parseBareSymbol.cpp new file mode 100644 index 0000000000000000000000000000000000000000..57f7bc977450d3c2da02c005d74f59303d313ad1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/parseBareSymbol.cpp @@ -0,0 +1,54 @@ +OperandMatchResultTy RISCVAsmParser::parseBareSymbol(OperandVector &Operands) { + SMLoc S = getLoc(); + SMLoc E = SMLoc::getFromPointer(S.getPointer() - 1); + const MCExpr *Res; + if (getLexer().getKind() != AsmToken::Identifier) { + return MatchOperand_NoMatch; + } + StringRef Identifier; + AsmToken Tok = getLexer().getTok(); + if (getParser().parseIdentifier(Identifier)) { + return MatchOperand_ParseFail; + } + if (Identifier.consume_back("@plt")) { + Error(getLoc(), "'@plt' operand not valid for instruction"); + return MatchOperand_ParseFail; + } + MCSymbol *Sym = getContext().getOrCreateSymbol(Identifier); + if (Sym->isVariable()) { + const MCExpr *V = Sym->getVariableValue(false); + if (!isa(V)) { + getLexer().UnLex(Tok); + return MatchOperand_NoMatch; + } + Res = V; + } + if (!Sym->isVariable()) { + Res = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext()); + } + MCBinaryExpr::Opcode Opcode; + if (getLexer().getKind() == AsmToken::Plus) { + Opcode = MCBinaryExpr::Add; + getLexer().Lex(); + const MCExpr *Expr; + if (getParser().parseExpression(Expr)) { + return MatchOperand_ParseFail; + } + Res = MCBinaryExpr::create(Opcode, Res, Expr, getContext()); + Operands.push_back(RISCVOperand::createImm(Res, S, E, isRV64())); + return MatchOperand_Success; + } + if (getLexer().getKind() == AsmToken::Minus) { + Opcode = MCBinaryExpr::Sub; + getLexer().Lex(); + const MCExpr *Expr; + if (getParser().parseExpression(Expr)) { + return MatchOperand_ParseFail; + } + Res = MCBinaryExpr::create(Opcode, Res, Expr, getContext()); + Operands.push_back(RISCVOperand::createImm(Res, S, E, isRV64())); + return MatchOperand_Success; + } + Operands.push_back(RISCVOperand::createImm(Res, S, E, isRV64())); + return MatchOperand_Success; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/parseCSRSyestemRegister.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/parseCSRSyestemRegister.cpp new file mode 100644 index 0000000000000000000000000000000000000000..96d54657bc5e40fad131f08a4c6c265d5da2663c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/parseCSRSyestemRegister.cpp @@ -0,0 +1,58 @@ +OperandMatchResultTy RISCVAsmParser::parseCSRSystemRegister(OperandVector &Operands) { + SMLoc S = getLoc(); + const MCExpr *Res; + switch (getLexer().getKind()) { + default: + return MatchOperand_NoMatch; + case AsmToken::LParen: + case AsmToken::Minus: + case AsmToken::Plus: + case AsmToken::Exclaim: + case AsmToken::Tilde: + case AsmToken::Integer: + case AsmToken::String: { + if (getParser().parseExpression(Res)) { + return MatchOperand_ParseFail; + } + auto *CE = dyn_cast(Res); + if (CE) { + int64_t Imm = CE->getValue(); + if (isUInt<12>(Imm)) { + auto SysReg = RISCVSysReg::lookupSysRegByEncoding(Imm); + Operands.push_back(RISCVOperand::createSysReg(SysReg ? SysReg->Name : "", S, Imm, isRV64())); + return MatchOperand_Success; + } + } + Twine Msg = "immediate must be an integer in the range"; + Error(S, Msg + " [" + Twine(0) + ", " + Twine((1 << 12) - 1) + "]"); + return MatchOperand_ParseFail; + } + case AsmToken::Identifier: { + StringRef Identifier; + if (getParser().parseIdentifier(Identifier)) { + return MatchOperand_ParseFail; + } + auto SysReg = RISCVSysReg::lookupSysRegByName(Identifier); + if (!SysReg) { + SysReg = RISCVSysReg::lookupSysRegByAltName(Identifier); + } + if (SysReg) { + if (!SysReg->haveRequiredFeatures(getSTI().getFeatureBits())) { + Error(S, "system register use requires an option to be enabled"); + return MatchOperand_ParseFail; + } + Operands.push_back(RISCVOperand::createSysReg(Identifier, S, SysReg->Encoding, isRV64())); + return MatchOperand_Success; + } + Twine Msg = "operand must be a valid system register name or an integer in the range"; + Error(S, Msg + " [" + Twine(0) + ", " + Twine((1 << 12) - 1) + "]"); + return MatchOperand_ParseFail; + } + case AsmToken::Percent: { + Twine Msg = "immediate must be an integer in the range"; + Error(S, Msg + " [" + Twine(0) + ", " + Twine((1 << 12) - 1) + "]"); + return MatchOperand_ParseFail; + } + } + return MatchOperand_NoMatch; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/parseCallSymbol.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/parseCallSymbol.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fe6a4808b76d4d27e94f8d2fb928ea9efcec5566 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/parseCallSymbol.cpp @@ -0,0 +1,24 @@ +OperandMatchResultTy RISCVAsmParser::parseCallSymbol(OperandVector &Operands) { + SMLoc S = getLoc(); + SMLoc E = SMLoc::getFromPointer(S.getPointer() - 1); + const MCExpr *Res; + if (getLexer().getKind() != AsmToken::Identifier) { + return MatchOperand_NoMatch; + } + if (getLexer().peekTok().getKind() != AsmToken::EndOfStatement) { + return MatchOperand_NoMatch; + } + StringRef Identifier; + if (getParser().parseIdentifier(Identifier)) { + return MatchOperand_ParseFail; + } + RISCVMCExpr::VariantKind Kind = RISCVMCExpr::VK_RISCV_CALL; + if (Identifier.consume_back("@plt")) { + Kind = RISCVMCExpr::VK_RISCV_CALL_PLT; + } + MCSymbol *Sym = getContext().getOrCreateSymbol(Identifier); + Res = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext()); + Res = RISCVMCExpr::create(Res, Kind, getContext()); + Operands.push_back(RISCVOperand::createImm(Res, S, E, isRV64())); + return MatchOperand_Success; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/parseImmediate.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/parseImmediate.cpp new file mode 100644 index 0000000000000000000000000000000000000000..feac87761130aaf45a8121dea0eae6f59102e1d6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/parseImmediate.cpp @@ -0,0 +1,25 @@ +OperandMatchResultTy RISCVAsmParser::parseImmediate(OperandVector &Operands) { + SMLoc S = getLoc(); + SMLoc E = SMLoc::getFromPointer(S.getPointer() - 1); + const MCExpr *Res; + switch (getLexer().getKind()) { + default: + return MatchOperand_NoMatch; + case AsmToken::LParen: + case AsmToken::Dot: + case AsmToken::Minus: + case AsmToken::Plus: + case AsmToken::Exclaim: + case AsmToken::Tilde: + case AsmToken::Integer: + case AsmToken::String: + case AsmToken::Identifier: + if (getParser().parseExpression(Res)) + return MatchOperand_ParseFail; + break; + case AsmToken::Percent: + return parseOperandWithModifier(Operands); + } + Operands.push_back(RISCVOperand::createImm(Res, S, E, isRV64())); + return MatchOperand_Success; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/parseJALOffset.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/parseJALOffset.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4347a538d20ac2d19cd66ac66b94dea2d4ee61a8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/parseJALOffset.cpp @@ -0,0 +1,6 @@ +OperandMatchResultTy RISCVAsmParser::parseJALOffset(OperandVector &Operands) { + if (getLexer().is(AsmToken::Identifier) && getLexer().peekTok().is(AsmToken::Comma)) { + return MatchOperand_NoMatch; + } + return parseImmediate(Operands); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/parseMaskReg.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/parseMaskReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..901f42d5b8e97a73b21f91b7bc31ab4375d074a0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/parseMaskReg.cpp @@ -0,0 +1,23 @@ +OperandMatchResultTy RISCVAsmParser::parseMaskReg(OperandVector &Operands) { + if (getLexer().getKind() != AsmToken::Identifier) { + return MatchOperand_NoMatch; + } + StringRef Name = getLexer().getTok().getIdentifier(); + if (!Name.consume_back(".t")) { + Error(getLoc(), "expected '.t' suffix"); + return MatchOperand_ParseFail; + } + MCRegister RegNo; + matchRegisterNameHelper(isRV32E(), RegNo, Name); + if (RegNo == RISCV::NoRegister) { + return MatchOperand_NoMatch; + } + if (RegNo != RISCV::V0) { + return MatchOperand_NoMatch; + } + SMLoc S = getLoc(); + SMLoc E = SMLoc::getFromPointer(S.getPointer() - 1); + getLexer().Lex(); + Operands.push_back(RISCVOperand::createReg(RegNo, S, E, isRV64())); + return MatchOperand_Success; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/parseMemOpBaseReg.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/parseMemOpBaseReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..afb11381c7eb3dec6dd072e6e0a0cc194a3f41dd --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/parseMemOpBaseReg.cpp @@ -0,0 +1,25 @@ +OperandMatchResultTy RISCVAsmParser::parseMemOpBaseReg(OperandVector &Operands) { + if (getLexer().isNot(AsmToken::LParen)) { + Error(getLoc(), "expected '('"); + return MatchOperand_ParseFail; + } + getParser().Lex(); + Operands.push_back(RISCVOperand::createToken("(", getLoc(), isRV64())); + if (parseRegister(Operands) != MatchOperand_Success) { + Error(getLoc(), "expected register"); + return MatchOperand_ParseFail; + } + if (getSTI().getFeatureBits()[RISCV::FeaturePULPExtV2]) { + if (getLexer().is(AsmToken::Exclaim)){ + getParser().Lex(); + Operands.push_back(RISCVOperand::createToken("!", getLoc(), isRV64())); + } + } + if (getLexer().isNot(AsmToken::RParen)) { + Error(getLoc(), "expected ')'"); + return MatchOperand_ParseFail; + } + getParser().Lex(); + Operands.push_back(RISCVOperand::createToken(")", getLoc(), isRV64())); + return MatchOperand_Success; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/parseOperand.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/parseOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6769c11558589db17f62334e2140e71df26a61e0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/parseOperand.cpp @@ -0,0 +1,27 @@ +bool RISCVAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) { + OperandMatchResultTy Result = MatchOperandParserImpl(Operands, Mnemonic, true); + if (Result == MatchOperand_Success) { + return false; + } + if (Result == MatchOperand_ParseFail) { + return true; + } + if (parseRegister(Operands, true) == MatchOperand_Success) { + return false; + } + if (parseRegister(Operands, true) == MatchOperand_Success) { + if (getSTI().getFeatureBits()[RISCV::FeaturePULPExtV2]) { + if (getLexer().is(AsmToken::LParen)) + return parseMemOpBaseReg(Operands) != MatchOperand_Success; + } + return false; + } + if (parseImmediate(Operands) == MatchOperand_Success) { + if (getLexer().is(AsmToken::LParen)) { + return parseMemOpBaseReg(Operands) != MatchOperand_Success; + } + return false; + } + Error(getLoc(), "unknown operand"); + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/parseOperandWithModifier.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/parseOperandWithModifier.cpp new file mode 100644 index 0000000000000000000000000000000000000000..27f42bfe733a0007030006dfbc7d50f869067eda --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/parseOperandWithModifier.cpp @@ -0,0 +1,32 @@ +OperandMatchResultTy RISCVAsmParser::parseOperandWithModifier(OperandVector &Operands) { + SMLoc S = getLoc(); + SMLoc E = SMLoc::getFromPointer(S.getPointer() - 1); + if (getLexer().getKind() != AsmToken::Percent) { + Error(getLoc(), "expected '%' for operand modifier"); + return MatchOperand_ParseFail; + } + getParser().Lex(); + if (getLexer().getKind() != AsmToken::Identifier) { + Error(getLoc(), "expected valid identifier for operand modifier"); + return MatchOperand_ParseFail; + } + StringRef Identifier = getParser().getTok().getIdentifier(); + RISCVMCExpr::VariantKind VK = RISCVMCExpr::getVariantKindForName(Identifier); + if (VK == RISCVMCExpr::VK_RISCV_Invalid) { + Error(getLoc(), "unrecognized operand modifier"); + return MatchOperand_ParseFail; + } + getParser().Lex(); + if (getLexer().getKind() != AsmToken::LParen) { + Error(getLoc(), "expected '('"); + return MatchOperand_ParseFail; + } + getParser().Lex(); + const MCExpr *SubExpr; + if (getParser().parseParenExpression(SubExpr, E)) { + return MatchOperand_ParseFail; + } + const MCExpr *ModExpr = RISCVMCExpr::create(SubExpr, VK, getContext()); + Operands.push_back(RISCVOperand::createImm(ModExpr, S, E, isRV64())); + return MatchOperand_Success; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/parsePseudoJumpSymbol.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/parsePseudoJumpSymbol.cpp new file mode 100644 index 0000000000000000000000000000000000000000..69b270de1636f260bc365037fb79e6d55d7af2f7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/parsePseudoJumpSymbol.cpp @@ -0,0 +1,15 @@ +OperandMatchResultTy RISCVAsmParser::parsePseudoJumpSymbol(OperandVector &Operands) { + SMLoc S = getLoc(); + SMLoc E = SMLoc::getFromPointer(S.getPointer() - 1); + const MCExpr *Res; + if (getParser().parseExpression(Res)) { + return MatchOperand_ParseFail; + } + if (Res->getKind() != MCExpr::ExprKind::SymbolRef || cast(Res)->getKind() == MCSymbolRefExpr::VariantKind::VK_PLT) { + Error(S, "operand must be a valid jump target"); + return MatchOperand_ParseFail; + } + Res = RISCVMCExpr::create(Res, RISCVMCExpr::VK_RISCV_CALL, getContext()); + Operands.push_back(RISCVOperand::createImm(Res, S, E, isRV64())); + return MatchOperand_Success; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/parseRegister2.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/parseRegister2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7fe5924f959488bcb9783bee83611e7623f013e8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/parseRegister2.cpp @@ -0,0 +1,43 @@ +OperandMatchResultTy RISCVAsmParser::parseRegister(OperandVector &Operands, bool AllowParens) { + SMLoc FirstS = getLoc(); + bool HadParens = false; + AsmToken LParen; + if (AllowParens && getLexer().is(AsmToken::LParen)) { + AsmToken Buf[2]; + size_t ReadCount = getLexer().peekTokens(Buf); + if (ReadCount == 2 && Buf[1].getKind() == AsmToken::RParen) { + HadParens = true; + LParen = getParser().getTok(); + getParser().Lex(); + } + } + switch (getLexer().getKind()) { + default: + if (HadParens) { + getLexer().UnLex(LParen); + } + return MatchOperand_NoMatch; + case AsmToken::Identifier: + StringRef Name = getLexer().getTok().getIdentifier(); + MCRegister RegNo; + matchRegisterNameHelper(isRV32E(), RegNo, Name); + if (RegNo == RISCV::NoRegister) { + if (HadParens) { + getLexer().UnLex(LParen); + } + return MatchOperand_NoMatch; + } + if (HadParens) { + Operands.push_back(RISCVOperand::createToken("(", FirstS, isRV64())); + } + SMLoc S = getLoc(); + SMLoc E = SMLoc::getFromPointer(S.getPointer() - 1); + getLexer().Lex(); + Operands.push_back(RISCVOperand::createReg(RegNo, S, E, isRV64())); + } + if (HadParens) { + getParser().Lex(); + Operands.push_back(RISCVOperand::createToken(")", getLoc(), isRV64())); + } + return MatchOperand_Success; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/parseVTypeI.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/parseVTypeI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e220c8a45f48d51816290c8ee89f6dfe78b71cd5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/parseVTypeI.cpp @@ -0,0 +1,85 @@ +OperandMatchResultTy RISCVAsmParser::parseVTypeI(OperandVector &Operands) { + SMLoc S = getLoc(); + if (getLexer().getKind() != AsmToken::Identifier) { + return MatchOperand_NoMatch; + } + StringRef Name = getLexer().getTok().getIdentifier(); + if (!Name.consume_front("e")) { + return MatchOperand_NoMatch; + } + unsigned Sew; + if (Name.getAsInteger(10, Sew)) { + return MatchOperand_NoMatch; + } + if (!RISCVVType::isValidSEW(Sew)) { + return MatchOperand_NoMatch; + } + getLexer().Lex(); + if (!getLexer().is(AsmToken::Comma)) { + return MatchOperand_NoMatch; + } + getLexer().Lex(); + Name = getLexer().getTok().getIdentifier(); + if (!Name.consume_front("m")) { + return MatchOperand_NoMatch; + } + bool Fractional = Name.consume_front("f"); + unsigned Lmul; + if (Name.getAsInteger(10, Lmul)) { + return MatchOperand_NoMatch; + } + if (!RISCVVType::isValidLMUL(Lmul, Fractional)) { + return MatchOperand_NoMatch; + } + getLexer().Lex(); + if (!getLexer().is(AsmToken::Comma)) { + return MatchOperand_NoMatch; + } + getLexer().Lex(); + Name = getLexer().getTok().getIdentifier(); + bool TailAgnostic; + if (Name == "ta") { + TailAgnostic = true; + } + else if (Name == "tu") { + TailAgnostic = false; + } + else { + return MatchOperand_NoMatch; + } + getLexer().Lex(); + if (!getLexer().is(AsmToken::Comma)) { + return MatchOperand_NoMatch; + } + getLexer().Lex(); + Name = getLexer().getTok().getIdentifier(); + bool MaskAgnostic; + if (Name == "ma") { + MaskAgnostic = true; + } + else if (Name == "mu") { + MaskAgnostic = false; + } + else { + return MatchOperand_NoMatch; + } + getLexer().Lex(); + if (getLexer().getKind() != AsmToken::EndOfStatement) { + return MatchOperand_NoMatch; + } + unsigned SewLog2 = Log2_32(Sew / 8); + unsigned LmulLog2 = Log2_32(Lmul); + RISCVVSEW VSEW = static_cast(SewLog2); + RISCVVLMUL VLMUL = static_cast(Fractional ? 8 - LmulLog2 : LmulLog2); + unsigned VLMULBits = static_cast(VLMUL); + unsigned VSEWBits = static_cast(VSEW); + unsigned VTypeI = (VSEWBits << 3) | (VLMULBits & 0x7); + if (TailAgnostic) { + VTypeI |= 0x40; + } + if (MaskAgnostic) { + VTypeI |= 0x80; + } + Operands.push_back(RISCVOperand::createVType(VTypeI, S, isRV64())); + return MatchOperand_Success; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/print.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/print.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9a8b9ee45de91092637a6df1c5cc22485819a36f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/print.cpp @@ -0,0 +1,27 @@ +void print(raw_ostream &OS) const override { + auto RegName = [](unsigned Reg) { + if (Reg) { + return RISCVInstPrinter::getRegisterName(Reg); + } + else { + return "noreg"; + } + }; + if (Kind == KindTy::Token) { + OS << "'" << getToken() << "'"; + } + if (Kind == KindTy::Register) { + OS << ""; + } + if (Kind == KindTy::Immediate) { + OS << *getImm(); + } + if (Kind == KindTy::SystemRegister) { + OS << "'; + } + if (Kind == KindTy::VType) { + OS << "'; + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/setFeatureBits.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/setFeatureBits.cpp new file mode 100644 index 0000000000000000000000000000000000000000..211903c48c17873e04e301dd463681dff6bb9c72 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/setFeatureBits.cpp @@ -0,0 +1,6 @@ +void setFeatureBits(uint64_t Feature, StringRef FeatureString) { + if (!(getSTI().getFeatureBits()[Feature])) { + MCSubtargetInfo &STI = copySTI(); + setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature(FeatureString))); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/tryParseRegister.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/tryParseRegister.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5a1d6873add2be39e3f257393382aec5e4ed8d3a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/tryParseRegister.cpp @@ -0,0 +1,12 @@ +OperandMatchResultTy RISCVAsmParser::tryParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) { + const AsmToken &Tok = getParser().getTok(); + StartLoc = Tok.getLoc(); + EndLoc = Tok.getEndLoc(); + RegNo = 0; + StringRef Name = getLexer().getTok().getIdentifier(); + if (matchRegisterNameHelper(isRV32E(), (MCRegister &)RegNo, Name)) { + return MatchOperand_NoMatch; + } + getParser().Lex(); + return MatchOperand_Success; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/validateTargetOperandClass.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/validateTargetOperandClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c072b9c27d13a6ecb7d25a3e02a5bd74d804d7b6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmParser/validateTargetOperandClass.cpp @@ -0,0 +1,18 @@ +unsigned RISCVAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp, unsigned Kind) { + RISCVOperand &Op = static_cast(AsmOp); + if (!Op.isReg()) { + return Match_InvalidOperand; + } + MCRegister Reg = Op.getReg(); + bool IsRegFPR64 = RISCVMCRegisterClasses[RISCV::FPR64RegClassID].contains(Reg); + bool IsRegFPR64C = RISCVMCRegisterClasses[RISCV::FPR64CRegClassID].contains(Reg); + if ((IsRegFPR64 && Kind == MCK_FPR32) || (IsRegFPR64C && Kind == MCK_FPR32C)) { + Op.Reg.RegNum = convertFPR64ToFPR32(Reg); + return Match_Success; + } + if (IsRegFPR64 && Kind == MCK_FPR16) { + Op.Reg.RegNum = convertFPR64ToFPR16(Reg); + return Match_Success; + } + return Match_InvalidOperand; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmPrinter/AsmPrinter.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmPrinter/AsmPrinter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e166353dd214035178ed8fd3747bf6c0d1d6a724 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmPrinter/AsmPrinter.cpp @@ -0,0 +1,2 @@ +explicit RISCVAsmPrinter(TargetMachine &TM, std::unique_ptr Streamer) : AsmPrinter(TM, std::move(Streamer)), STI(TM.getMCSubtargetInfo()) { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmPrinter/EmitToStreamer.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmPrinter/EmitToStreamer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1b00b8f8b42d9c2fbe308b81fe001a750e400ae4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmPrinter/EmitToStreamer.cpp @@ -0,0 +1,8 @@ +void RISCVAsmPrinter::EmitToStreamer(MCStreamer &S, const MCInst &Inst) { + MCInst CInst; + bool Res = compressInst(CInst, Inst, *STI, OutStreamer->getContext()); + if (Res) { + ++RISCVNumInstrsCompressed; + } + AsmPrinter::EmitToStreamer(*OutStreamer, Res ? CInst : Inst); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmPrinter/LLVMInitializeAsmPrinter.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmPrinter/LLVMInitializeAsmPrinter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4b6f0328c0d570906d89e27f1b6c6bd2958c6ee6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmPrinter/LLVMInitializeAsmPrinter.cpp @@ -0,0 +1,4 @@ +extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVAsmPrinter() { + RegisterAsmPrinter X(getTheRISCV32Target()); + RegisterAsmPrinter Y(getTheRISCV64Target()); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmPrinter/PrintAsmMemoryOperand.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmPrinter/PrintAsmMemoryOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..31132f2f38be4753150937d0d9e817e46726ce1e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmPrinter/PrintAsmMemoryOperand.cpp @@ -0,0 +1,11 @@ +bool RISCVAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS) { + if (!ExtraCode) { + const MachineOperand &MO = MI->getOperand(OpNo); + if (!MO.isReg()) { + return true; + } + OS << "0(" << RISCVInstPrinter::getRegisterName(MO.getReg()) << ")"; + return false; + } + return AsmPrinter::PrintAsmMemoryOperand(MI, OpNo, ExtraCode, OS); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmPrinter/PrintAsmOperand.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmPrinter/PrintAsmOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c31fdfafce0d2ff8dea052096b61a742174ece7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmPrinter/PrintAsmOperand.cpp @@ -0,0 +1,45 @@ +bool RISCVAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS) { + if (!AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, OS)) { + return false; + } + const MachineOperand &MO = MI->getOperand(OpNo); + if (ExtraCode && ExtraCode[0]) { + if (ExtraCode[1] != 0) { + return true; + } + switch (ExtraCode[0]) { + default: + return true; + case 'z': + if (MO.isImm() && MO.getImm() == 0) { + OS << RISCVInstPrinter::getRegisterName(RISCV::X0); + return false; + } + break; + case 'i': + if (!MO.isReg()) { + OS << 'i'; + } + return false; + } + } + switch (MO.getType()) { + case MachineOperand::MO_Immediate: + OS << MO.getImm(); + return false; + case MachineOperand::MO_Register: + OS << RISCVInstPrinter::getRegisterName(MO.getReg()); + return false; + case MachineOperand::MO_GlobalAddress: + PrintSymbolOperand(MO, OS); + return false; + case MachineOperand::MO_BlockAddress: { + MCSymbol *Sym = GetBlockAddressSymbol(MO.getBlockAddress()); + Sym->print(OS, MAI); + return false; + } + default: + break; + } + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmPrinter/emitAttributes.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmPrinter/emitAttributes.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c13bd2b11bf02aab0983c3ffc0c3b5ad848e0be2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmPrinter/emitAttributes.cpp @@ -0,0 +1,9 @@ +void RISCVAsmPrinter::emitAttributes() { + RISCVTargetStreamer &RTS = static_cast(*OutStreamer->getTargetStreamer()); + const Triple &TT = TM.getTargetTriple(); + StringRef CPU = TM.getTargetCPU(); + StringRef FS = TM.getTargetFeatureString(); + const RISCVTargetMachine &RTM = static_cast(TM); + const RISCVSubtarget STI(TT, CPU, CPU, FS, "", RTM); + RTS.emitTargetAttributes(STI); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmPrinter/emitEndOfAsmFile.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmPrinter/emitEndOfAsmFile.cpp new file mode 100644 index 0000000000000000000000000000000000000000..871ffa5737cbbebb3646e8d4332bd04b329067da --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmPrinter/emitEndOfAsmFile.cpp @@ -0,0 +1,6 @@ +void RISCVAsmPrinter::emitEndOfAsmFile(Module &M) { + RISCVTargetStreamer &CTS = static_cast(*OutStreamer->getTargetStreamer()); + if (TM.getTargetTriple().isOSBinFormatELF()) { + CTS.finishAttributeSection(); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmPrinter/emitInstruction.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmPrinter/emitInstruction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bdd093f184563015cb1be5ba8975ef04762fd8b6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmPrinter/emitInstruction.cpp @@ -0,0 +1,8 @@ +void RISCVAsmPrinter::emitInstruction(const MachineInstr *MI) { + if (emitPseudoExpansionLowering(*OutStreamer, MI)) { + return ; + } + MCInst TmpInst; + LowerRISCVMachineInstrToMCInst(MI, TmpInst, *this); + EmitToStreamer(*OutStreamer, TmpInst); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmPrinter/emitStartOfAsmFile.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmPrinter/emitStartOfAsmFile.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6895c501148e6daaad0ad8d522f0cbdb0fb2a9e6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmPrinter/emitStartOfAsmFile.cpp @@ -0,0 +1,5 @@ +void RISCVAsmPrinter::emitStartOfAsmFile(Module &M) { + if (TM.getTargetTriple().isOSBinFormatELF()) { + emitAttributes(); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmPrinter/getPassName.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmPrinter/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..408ede981a828294678c062ffab8cb8538586a4a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmPrinter/getPassName.cpp @@ -0,0 +1,3 @@ +StringRef getPassName() const override { + return "RISCV Assembly Printer"; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmPrinter/lowerOperand.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmPrinter/lowerOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e46620f964aa5e16a8f2d0ea650ef87a4e687718 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmPrinter/lowerOperand.cpp @@ -0,0 +1,3 @@ +bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const { + return LowerRISCVMachineOperandToMCOperand(MO, MCOp, *this); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmPrinter/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmPrinter/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..789e25a498fe0fcd1c781cb7aa07b505321457e0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Assembler/AsmPrinter/runOnMachineFunction.cpp @@ -0,0 +1,8 @@ +bool RISCVAsmPrinter::runOnMachineFunction(MachineFunction &MF) { + MCSubtargetInfo &NewSTI = OutStreamer->getContext().getSubtargetCopy(*TM.getMCSubtargetInfo()); + NewSTI.setFeatureBits(MF.getSubtarget().getFeatureBits()); + STI = &NewSTI; + SetupMachineFunction(MF); + emitFunctionBody(); + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/DecodeFPR16RegisterClass.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/DecodeFPR16RegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..92d7310f19818315af77ce1c98d61f5c1d4fdf10 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/DecodeFPR16RegisterClass.cpp @@ -0,0 +1,8 @@ +static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { + if (RegNo >= 32) { + return MCDisassembler::Fail; + } + MCRegister Reg = RISCV::F0_H + RegNo; + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/DecodeFPR32CRegisterClass.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/DecodeFPR32CRegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d1bc847c2b24fafa879484f9d062041ad9950bae --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/DecodeFPR32CRegisterClass.cpp @@ -0,0 +1,8 @@ +static DecodeStatus DecodeFPR32CRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { + if (RegNo >= 8) { + return MCDisassembler::Fail; + } + MCRegister Reg = RISCV::F8_F + RegNo; + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/DecodeFPR32RegisterClass.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/DecodeFPR32RegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..36aae9478effe333858379c9a1b304100f38eaf1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/DecodeFPR32RegisterClass.cpp @@ -0,0 +1,8 @@ +static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { + if (RegNo >= 32) { + return MCDisassembler::Fail; + } + MCRegister Reg = RISCV::F0_F + RegNo; + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/DecodeFPR64CRegisterClass.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/DecodeFPR64CRegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6ad24e5137888045d3acc32ed95530c2d3e15529 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/DecodeFPR64CRegisterClass.cpp @@ -0,0 +1,8 @@ +static DecodeStatus DecodeFPR64CRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { + if (RegNo >= 8) { + return MCDisassembler::Fail; + } + MCRegister Reg = RISCV::F8_D + RegNo; + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/DecodeFPR64RegisterClass.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/DecodeFPR64RegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ae3dfca3caacd67020ee25fe6f85414520efaabe --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/DecodeFPR64RegisterClass.cpp @@ -0,0 +1,8 @@ +static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { + if (RegNo >= 32) { + return MCDisassembler::Fail; + } + MCRegister Reg = RISCV::F0_D + RegNo; + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/DecodeGPRCRegisterClass.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/DecodeGPRCRegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3edc390bf8de970a40451494a5aec58321519e7e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/DecodeGPRCRegisterClass.cpp @@ -0,0 +1,8 @@ +static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { + if (RegNo >= 8) { + return MCDisassembler::Fail; + } + MCRegister Reg = RISCV::X8 + RegNo; + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/DecodeGPRNoX0RegisterClass.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/DecodeGPRNoX0RegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..019654808af5f3e9c6795bc28ace71abdf367d21 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/DecodeGPRNoX0RegisterClass.cpp @@ -0,0 +1,6 @@ +static DecodeStatus DecodeGPRNoX0RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { + if (RegNo == 0) { + return MCDisassembler::Fail; + } + return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/DecodeGPRNoX0X2RegisterClass.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/DecodeGPRNoX0X2RegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d6f18fdce1b4c98576300921500dfc1bd3d0f4f8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/DecodeGPRNoX0X2RegisterClass.cpp @@ -0,0 +1,6 @@ +static DecodeStatus DecodeGPRNoX0X2RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { + if (RegNo == 2) { + return MCDisassembler::Fail; + } + return DecodeGPRNoX0RegisterClass(Inst, RegNo, Address, Decoder); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/DecodeGPRRegisterClass.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/DecodeGPRRegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..23847ddc8e1562eb28b6353bbee940cac56d8acd --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/DecodeGPRRegisterClass.cpp @@ -0,0 +1,10 @@ +static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { + const FeatureBitset &FeatureBits = static_cast(Decoder)->getSubtargetInfo().getFeatureBits(); + bool IsRV32E = FeatureBits[RISCV::FeatureRV32E]; + if (RegNo >= 32 || (IsRV32E && RegNo >= 16)) { + return MCDisassembler::Fail; + } + MCRegister Reg = RISCV::X0 + RegNo; + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/DecodePulpV2RegisterClass.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/DecodePulpV2RegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c099b92870018dc8e0147eb619c31ba6f27fd3ed --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/DecodePulpV2RegisterClass.cpp @@ -0,0 +1,3 @@ +static DecodeStatus DecodePulpV2RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { + return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/DecodePulpV4RegisterClass.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/DecodePulpV4RegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9592a25bf4dbd25b64ffe003a8da445000768cac --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/DecodePulpV4RegisterClass.cpp @@ -0,0 +1,3 @@ +static DecodeStatus DecodePulpV4RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { + return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/DecodeVRRegisterClass.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/DecodeVRRegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ea83a9dcc3429e5c226968b1d1d94ddeedc751bc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/DecodeVRRegisterClass.cpp @@ -0,0 +1,8 @@ +static DecodeStatus DecodeVRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { + if (RegNo >= 32) { + return MCDisassembler::Fail; + } + MCRegister Reg = RISCV::V0 + RegNo; + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/Disassembler.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/Disassembler.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b68c6a0167549bc8f749b0e470e9d23c43926635 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/Disassembler.cpp @@ -0,0 +1,2 @@ +RISCVDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, MCInstrInfo const *MCII) : MCDisassembler(STI, Ctx), MCII(MCII) { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/LLVMInitializeDisassembler.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/LLVMInitializeDisassembler.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1ed8ecad6545c74078d9b77942c9b5c2a24a16d8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/LLVMInitializeDisassembler.cpp @@ -0,0 +1,4 @@ +extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVDisassembler() { + TargetRegistry::RegisterMCDisassembler(getTheRISCV32Target(), createRISCVDisassembler); + TargetRegistry::RegisterMCDisassembler(getTheRISCV64Target(), createRISCVDisassembler); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/addImplySP.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/addImplySP.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8ccacd508efb4089c860bb106baa89d892902431 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/addImplySP.cpp @@ -0,0 +1,9 @@ +static void addImplySP(MCInst &Inst, int64_t Address, const void *Decoder) { + if (Inst.getOpcode() == RISCV::C_LWSP || Inst.getOpcode() == RISCV::C_SWSP || Inst.getOpcode() == RISCV::C_LDSP || Inst.getOpcode() == RISCV::C_SDSP || Inst.getOpcode() == RISCV::C_FLWSP || Inst.getOpcode() == RISCV::C_FSWSP || Inst.getOpcode() == RISCV::C_FLDSP || Inst.getOpcode() == RISCV::C_FSDSP || Inst.getOpcode() == RISCV::C_ADDI4SPN) { + DecodeGPRRegisterClass(Inst, 2, Address, Decoder); + } + if (Inst.getOpcode() == RISCV::C_ADDI16SP) { + DecodeGPRRegisterClass(Inst, 2, Address, Decoder); + DecodeGPRRegisterClass(Inst, 2, Address, Decoder); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/createDisassembler.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/createDisassembler.cpp new file mode 100644 index 0000000000000000000000000000000000000000..498d4e2da63069504b61fd82b710c75962d5a343 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/createDisassembler.cpp @@ -0,0 +1,3 @@ +static MCDisassembler *createRISCVDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx) { + return new RISCVDisassembler(STI, Ctx, T.createMCInstrInfo()); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/decodeCLUIImmOperand.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/decodeCLUIImmOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..56923d00f9f34f97fd7d6f2a92844eefb789431b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/decodeCLUIImmOperand.cpp @@ -0,0 +1,8 @@ +static DecodeStatus decodeCLUIImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) { + assert(isUInt<6>(Imm) && "Invalid immediate"); + if (Imm > 31) { + Imm = (SignExtend64<6>(Imm) & 0xfffff); + } + Inst.addOperand(MCOperand::createImm(Imm)); + return MCDisassembler::Success; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/decodeFRMArg.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/decodeFRMArg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..42bc2ab0b8e381b06b0a7b99bc2e16f91132e611 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/decodeFRMArg.cpp @@ -0,0 +1,8 @@ +static DecodeStatus decodeFRMArg(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) { + assert(isUInt<3>(Imm) && "Invalid immediate"); + if (!llvm::RISCVFPRndMode::isValidRoundingMode(Imm)) { + return MCDisassembler::Fail; + } + Inst.addOperand(MCOperand::createImm(Imm)); + return MCDisassembler::Success; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/decodeRVCInstrRdRs1Rs2.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/decodeRVCInstrRdRs1Rs2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ff736e6728f99593a0e367fe7ae7c308fddee2cb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/decodeRVCInstrRdRs1Rs2.cpp @@ -0,0 +1,9 @@ +static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { + unsigned d = fieldFromInstruction(Insn, 7, 5); + unsigned const9 = 0; + unsigned s1 = fieldFromInstruction(Insn, 2, 5); + DecodeStatus status = DecodeGPRRegisterClass(Inst, d, Address, Decoder); + Inst.addOperand(Inst.getOperand(const9)); + status = DecodeGPRRegisterClass(Inst, s1, Address, Decoder); + return MCDisassembler::Success; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/decodeRVCInstrRdRs1UImm.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/decodeRVCInstrRdRs1UImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4583b28d5e2cc6dc158fc5c94735ce0db8db858d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/decodeRVCInstrRdRs1UImm.cpp @@ -0,0 +1,9 @@ +static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { + DecodeGPRRegisterClass(Inst, 0, Address, Decoder); + Inst.addOperand(Inst.getOperand(0)); + uint64_t UImm6 = fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5); + DecodeStatus Result = decodeUImmOperand<6>(Inst, UImm6, Address, Decoder); + (void)Result; + assert(Result == MCDisassembler::Success && "Invalid immediate"); + return MCDisassembler::Success; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/decodeRVCInstrRdRs2.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/decodeRVCInstrRdRs2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8ce75106ef40771cb6415341680d69cf98151355 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/decodeRVCInstrRdRs2.cpp @@ -0,0 +1,7 @@ +static DecodeStatus decodeRVCInstrRdRs2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { + unsigned Rd = fieldFromInstruction(Insn, 7, 5); + unsigned Rs2 = fieldFromInstruction(Insn, 2, 5); + DecodeGPRRegisterClass(Inst, Rd, Address, Decoder); + DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder); + return MCDisassembler::Success; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/decodeRVCInstrRdSImm.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/decodeRVCInstrRdSImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..faf42482128dc81f79631797aaa131b57faa45bb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/decodeRVCInstrRdSImm.cpp @@ -0,0 +1,8 @@ +static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { + DecodeGPRRegisterClass(Inst, 0, Address, Decoder); + uint64_t SImm6 = fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5); + DecodeStatus Result = decodeSImmOperand<6>(Inst, SImm6, Address, Decoder); + (void)Result; + assert(Result == MCDisassembler::Success && "Invalid immediate"); + return MCDisassembler::Success; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/decodeRVCInstrSImm.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/decodeRVCInstrSImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4380b36238a4132769709bf280da1414dfa1ab7f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/decodeRVCInstrSImm.cpp @@ -0,0 +1,7 @@ +static DecodeStatus decodeRVCInstrSImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { + uint64_t SImm6 = fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5); + DecodeStatus Result = decodeSImmOperand<6>(Inst, SImm6, Address, Decoder); + (void)Result; + assert(Result == MCDisassembler::Success && "Invalid immediate"); + return MCDisassembler::Success; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/decodeSImmNonZeroOperand.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/decodeSImmNonZeroOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b6df53e27f2f7bb0bf6af2592e13fc3189f9de88 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/decodeSImmNonZeroOperand.cpp @@ -0,0 +1,9 @@ +template static DecodeStatus decodeSImmNonZeroOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) { + if (Imm == 0) { + return MCDisassembler::Fail; + } + assert(isUInt(Imm) && "Invalid immediate"); + addImplySP(Inst, Address, Decoder); + Inst.addOperand(MCOperand::createImm(SignExtend64(Imm))); + return MCDisassembler::Success; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/decodeSImmOperand.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/decodeSImmOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a56c1c3848efb98e2783ac2b3e50392822d1860b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/decodeSImmOperand.cpp @@ -0,0 +1,6 @@ +template static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) { + assert(isUInt(Imm) && "Invalid immediate"); + addImplySP(Inst, Address, Decoder); + Inst.addOperand(MCOperand::createImm(SignExtend64(Imm))); + return MCDisassembler::Success; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/decodeSImmOperandAndLsl1.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/decodeSImmOperandAndLsl1.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0e565169c666715ddbb61d5b3e884cc7b628f469 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/decodeSImmOperandAndLsl1.cpp @@ -0,0 +1,5 @@ +template static DecodeStatus decodeSImmOperandAndLsl1(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) { + assert(isUInt(Imm) && "Invalid immediate"); + Inst.addOperand(MCOperand::createImm(SignExtend64(Imm << 1))); + return MCDisassembler::Success; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/decodeUImmMinus1Operand.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/decodeUImmMinus1Operand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..863355cee6b9cee4ed5bae687f71abb1e96bf4f4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/decodeUImmMinus1Operand.cpp @@ -0,0 +1,3 @@ +template static DecodeStatus decodeUImmMinus1Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) { + return decodeUImmOperand(Inst, Imm + 1, Address, Decoder); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/decodeUImmNonZeroOperand.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/decodeUImmNonZeroOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4f08c154acb38533e848886a589b04bc524212a9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/decodeUImmNonZeroOperand.cpp @@ -0,0 +1,6 @@ +template static DecodeStatus decodeUImmNonZeroOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) { + if (Imm == 0) { + return MCDisassembler::Fail; + } + return decodeUImmOperand(Inst, Imm, Address, Decoder); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/decodeUImmOperand.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/decodeUImmOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e940d44b9e6b88e433ea55a8013356671e1ef239 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/decodeUImmOperand.cpp @@ -0,0 +1,6 @@ +template static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) { + assert(isUInt(Imm) && "Invalid immediate"); + addImplySP(Inst, Address, Decoder); + Inst.addOperand(MCOperand::createImm(Imm)); + return MCDisassembler::Success; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/decodeVMaskReg.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/decodeVMaskReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0ea5f1578a4fbbdd90b384382f28cc1bc2bce945 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/decodeVMaskReg.cpp @@ -0,0 +1,12 @@ +static DecodeStatus decodeVMaskReg(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { + MCRegister Reg = RISCV::NoRegister; + if (RegNo == 0) { + Inst.addOperand(MCOperand::createReg(RISCV::V0)); + return MCDisassembler::Success; + } + if (RegNo == 1) { + Inst.addOperand(MCOperand::createReg(RISCV::NoRegister)); + return MCDisassembler::Success; + } + return MCDisassembler::Fail; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/getInstruction.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/getInstruction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1b6b768e230411e68b01e432b0cea4141325942a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Disassembler/Disassembler/getInstruction.cpp @@ -0,0 +1,41 @@ +DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size, ArrayRef Bytes, uint64_t Address, raw_ostream &CS) const { + uint32_t Insn; + DecodeStatus Result; + if ((Bytes[0] & 0x3) == 0x3) { + if (Bytes.size() < 4) { + Size = 0; + return MCDisassembler::Fail; + } + Insn = support::endian::read32le(Bytes.data()); + LLVM_DEBUG(dbgs() << "Trying RISCV32 table :\n"); + Result = decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI); + Size = 4; + } + else { + if (Bytes.size() < 2) { + Size = 0; + return MCDisassembler::Fail; + } + Insn = support::endian::read16le(Bytes.data()); + if (!STI.getFeatureBits()[RISCV::Feature64Bit]) { + LLVM_DEBUG(dbgs() << "Trying RISCV32Only_16 table (16-bit Instruction):\n"); + Result = decodeInstruction(DecoderTableRISCV32Only_16, MI, Insn, Address, this, STI); + if (Result != MCDisassembler::Fail) { + Size = 2; + return Result; + } + } + if (STI.getFeatureBits()[RISCV::FeatureExtZbproposedc] && STI.getFeatureBits()[RISCV::FeatureStdExtC]) { + LLVM_DEBUG(dbgs() << "Trying RVBC32 table (BitManip 16-bit Instruction):\n"); + Result = decodeInstruction(DecoderTableRVBC16, MI, Insn, Address, this, STI); + if (Result != MCDisassembler::Fail) { + Size = 2; + return Result; + } + } + LLVM_DEBUG(dbgs() << "Trying RISCV_C table (16-bit Instruction):\n"); + Result = decodeInstruction(DecoderTable16, MI, Insn, Address, this, STI); + Size = 2; + } + return Result; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/AsmBackend.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/AsmBackend.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ef34215b142479c87b1510584ea79489a5710109 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/AsmBackend.cpp @@ -0,0 +1,4 @@ +RISCVAsmBackend(const MCSubtargetInfo &STI, uint8_t OSABI, bool Is64Bit, const MCTargetOptions &Options) : MCAsmBackend(support::little), STI(STI), OSABI(OSABI), Is64Bit(Is64Bit), TargetOptions(Options) { + TargetABI = RISCVABI::computeTargetABI(STI.getTargetTriple(), STI.getFeatureBits(), Options.getABIName()); + RISCVFeatures::validate(STI.getTargetTriple(), STI.getFeatureBits()); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/adjustFixupValue.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/adjustFixupValue.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d8daf62b9dc230af80c678865ba65f88e131ae74 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/adjustFixupValue.cpp @@ -0,0 +1,92 @@ +static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value, MCContext &Ctx) { + unsigned Kind; + Kind = Fixup.getTargetKind(); + if (Kind == FK_Data_1) { + return Value; + } + if (Kind == FK_Data_2) { + return Value; + } + if (Kind == FK_Data_4) { + return Value; + } + if (Kind == FK_Data_8) { + return Value; + } + if (Kind == FK_Data_6b) { + return Value; + } + if (Kind == RISCV::fixup_riscv_lo12_i) { + return Value & 0xfff; + } + if (Kind == RISCV::fixup_riscv_pcrel_lo12_i) { + return Value & 0xfff; + } + if (Kind == RISCV::fixup_riscv_tprel_lo12_i) { + return Value & 0xfff; + } + if (Kind == RISCV::fixup_pulpv2_loop_setup) { + return Value >> 1; + } + if (Kind == RISCV::fixup_pulpv2_loop_setupi) { + return Value >> 1; + } + if (Kind == RISCV::fixup_riscv_lo12_s) { + return (((Value >> 5) & 0x7f) << 25) | ((Value & 0x1f) << 7); + } + if (Kind == RISCV::fixup_riscv_pcrel_lo12_s) { + return (((Value >> 5) & 0x7f) << 25) | ((Value & 0x1f) << 7); + } + if (Kind == RISCV::fixup_riscv_tprel_lo12_s) { + return (((Value >> 5) & 0x7f) << 25) | ((Value & 0x1f) << 7); + } + if (Kind == RISCV::fixup_riscv_hi20) { + return ((Value + 0x800) >> 12) & 0xfffff; + } + if (Kind == RISCV::fixup_riscv_pcrel_hi20) { + return ((Value + 0x800) >> 12) & 0xfffff; + } + if (Kind == RISCV::fixup_riscv_tprel_hi20) { + return ((Value + 0x800) >> 12) & 0xfffff; + } + if (Kind == RISCV::fixup_riscv_call) { + return ((Value + 0x800ULL) & 0xfffff000ULL) | (((Value & 0xfffULL) << 20) << 32); + } + if (Kind == RISCV::fixup_riscv_call_plt) { + return ((Value + 0x800ULL) & 0xfffff000ULL) | (((Value & 0xfffULL) << 20) << 32); + } + if (Kind == RISCV::fixup_riscv_rvc_jump) { + return (((Value >> 11) & 0x1) << 10) | (((Value >> 4) & 0x1) << 9) | (((Value >> 8) & 0x3) << 7) | (((Value >> 10) & 0x1) << 6) | (((Value >> 6) & 0x1) << 5) | (((Value >> 7) & 0x1) << 4) | (((Value >> 1) & 0x7) << 1) | ((Value >> 5) & 0x1); + } + if (Kind == RISCV::fixup_riscv_rvc_branch) { + return (((Value >> 8) & 0x1) << 12) | (((Value >> 3) & 0x3) << 10) | (((Value >> 6) & 0x3) << 5) | (((Value >> 1) & 0x3) << 3) | (((Value >> 5) & 0x1) << 2); + } + if (Kind == RISCV::fixup_riscv_tls_got_hi20) { + llvm_unreachable("Relocation should be unconditionally forced\n"); + } + if (Kind == RISCV::fixup_riscv_tls_gd_hi20) { + llvm_unreachable("Relocation should be unconditionally forced\n"); + } + if (Kind == RISCV::fixup_riscv_got_hi20) { + llvm_unreachable("Relocation should be unconditionally forced\n"); + } + if (Kind == RISCV::fixup_riscv_branch) { + if (!isInt<13>(Value)) { + Ctx.reportError(Fixup.getLoc(), "fixup value out of range"); + } + if (Value & 0x1) { + Ctx.reportError(Fixup.getLoc(), "fixup value must be 2-byte aligned"); + } + return (((Value >> 11) & 0x1) << 7); + } + if (Kind == RISCV::fixup_riscv_jal) { + if (!isInt<21>(Value)) { + Ctx.reportError(Fixup.getLoc(), "fixup value out of range"); + } + if (Value & 0x1) { + Ctx.reportError(Fixup.getLoc(), "fixup value must be 2-byte aligned"); + } + return (((Value >> 20) & 0x1) << 19) | (((Value >> 1) & 0x3ff) << 9) | (((Value >> 11) & 0x1) << 8) | ((Value >> 12) & 0xff); + } + llvm_unreachable("Unknown fixup kind!"); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/applyFixup.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/applyFixup.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6f805ec0a5bc2cb96d16ba5a8e177d99f0bad2aa --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/applyFixup.cpp @@ -0,0 +1,19 @@ +void RISCVAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,const MCValue &Target,MutableArrayRef Data, uint64_t Value,bool IsResolved, const MCSubtargetInfo *STI) const { + MCFixupKind Kind = Fixup.getKind(); + if (Kind >= FirstLiteralRelocationKind) { + return ; + } + MCContext &Ctx = Asm.getContext(); + MCFixupKindInfo Info = getFixupKindInfo(Kind); + if (!Value) { + return ; + } + Value = adjustFixupValue(Fixup, Value, Ctx); + Value <<= Info.TargetOffset; + unsigned Offset = Fixup.getOffset(); + unsigned NumBytes = alignTo(Info.TargetSize + Info.TargetOffset, 8) / 8; + assert(Offset + NumBytes <= Data.size() && "Invalid fixup offset!"); + for (unsigned i = 0; i != NumBytes; ++i) { + Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/createAsmBackend.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/createAsmBackend.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cbb77fce7853eba057e346ceab62e761785a5616 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/createAsmBackend.cpp @@ -0,0 +1,5 @@ +MCAsmBackend *llvm::createRISCVAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options) { + const Triple &TT = STI.getTargetTriple(); + uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS()); + return new RISCVAsmBackend(STI, OSABI, TT.isArch64Bit(), Options); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/createObjectTargetWriter.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/createObjectTargetWriter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..899027cb9566b9956193576250199de336ddb193 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/createObjectTargetWriter.cpp @@ -0,0 +1,3 @@ +std::unique_ptr RISCVAsmBackend::createObjectTargetWriter() const { + return createRISCVELFObjectWriter(OSABI, Is64Bit); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/evaluateTargetFixup.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/evaluateTargetFixup.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a200b75ea98b3459dc89d83a2964ae971e563063 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/evaluateTargetFixup.cpp @@ -0,0 +1,50 @@ +bool RISCVAsmBackend::evaluateTargetFixup(const MCAssembler &Asm, const MCAsmLayout &Layout, const MCFixup &Fixup, const MCFragment *DF, const MCValue &Target, uint64_t &Value, bool &WasForced) { + const MCFixup *AUIPCFixup; + const MCFragment *AUIPCDF; + MCValue AUIPCTarget; + switch (Fixup.getTargetKind()) { + default: + llvm_unreachable("Unexpected fixup kind!"); + case RISCV::fixup_riscv_pcrel_hi20: + AUIPCFixup = &Fixup; + AUIPCDF = DF; + AUIPCTarget = Target; + break; + case RISCV::fixup_riscv_pcrel_lo12_i: + case RISCV::fixup_riscv_pcrel_lo12_s: { + AUIPCFixup = cast(Fixup.getValue())->getPCRelHiFixup(&AUIPCDF); + if (!AUIPCFixup) { + Asm.getContext().reportError(Fixup.getLoc(), "could not find corresponding %pcrel_hi"); + return true; + } + const MCExpr *AUIPCExpr = AUIPCFixup->getValue(); + if (!AUIPCExpr->evaluateAsRelocatable(AUIPCTarget, &Layout, AUIPCFixup)) { + return true; + } + break; + } + } + if (!AUIPCTarget.getSymA() || AUIPCTarget.getSymB()) { + return false; + } + const MCSymbolRefExpr *A = AUIPCTarget.getSymA(); + const MCSymbol &SA = A->getSymbol(); + if (A->getKind() != MCSymbolRefExpr::VK_None || SA.isUndefined()) { + return false; + } + auto *Writer = Asm.getWriterPtr(); + if (!Writer) { + return false; + } + bool IsResolved = Writer->isSymbolRefDifferenceFullyResolvedImpl(Asm, SA, *AUIPCDF, false, true); + if (!IsResolved) { + return false; + } + Value = Layout.getSymbolOffset(SA) + AUIPCTarget.getConstant(); + Value -= Layout.getFragmentOffset(AUIPCDF) + AUIPCFixup->getOffset(); + if (shouldForceRelocation(Asm, *AUIPCFixup, AUIPCTarget)) { + WasForced = true; + return false; + } + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/fixupNeedsRelaxation.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/fixupNeedsRelaxation.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c2d7f65b53a8d71a36becd18d92452b97ccf728f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/fixupNeedsRelaxation.cpp @@ -0,0 +1,3 @@ +bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, const MCRelaxableFragment *DF, const MCAsmLayout &Layout) const override { + llvm_unreachable("Handled by fixupNeedsRelaxationAdvanced"); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/fixupNeedsRelaxationAdvanced.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/fixupNeedsRelaxationAdvanced.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0ec2d779def6933b2b61eb6de6cd74a3e29a2bf8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/fixupNeedsRelaxationAdvanced.cpp @@ -0,0 +1,14 @@ +bool RISCVAsmBackend::fixupNeedsRelaxationAdvanced(const MCFixup &Fixup, bool Resolved, uint64_t Value, const MCRelaxableFragment *DF, const MCAsmLayout &Layout, const bool WasForced) const { + if (!Resolved && !WasForced) { + return true; + } + int64_t Offset = int64_t(Value); + switch (Fixup.getTargetKind()) { + case RISCV::fixup_riscv_rvc_branch: + return Offset > 254 || Offset < -256; + case RISCV::fixup_riscv_rvc_jump: + return Offset > 2046 || Offset < -2048; + default: + return false; + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/getFixupKind.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/getFixupKind.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9016a3840b84201f3ee27f9769f23843493270a5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/getFixupKind.cpp @@ -0,0 +1,14 @@ +Optional RISCVAsmBackend::getFixupKind(StringRef Name) const { + if (STI.getTargetTriple().isOSBinFormatELF()) { + unsigned Type; + Type = llvm::StringSwitch(Name) + #define ELF_RELOC(X, Y) .Case(#X, Y) + #include "llvm/BinaryFormat/ELFRelocs/RISCV.def" + #undef ELF_RELOC + .Default(-1u); + if (Type != -1u) { + return static_cast(FirstLiteralRelocationKind + Type); + } + } + return None; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/getFixupKindInfo.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/getFixupKindInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..373e558edae4f7a556650bc501c74aaa9968c1b6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/getFixupKindInfo.cpp @@ -0,0 +1,35 @@ +const MCFixupKindInfo & RISCVAsmBackend::getFixupKindInfo(MCFixupKind Kind) const { + const static MCFixupKindInfo Infos[RISCV::NumTargetFixupKinds] = { + {"fixup_riscv_hi20", 12, 20, 0}, + {"fixup_riscv_lo12_i", 20, 12, 0}, + {"fixup_riscv_lo12_s", 0, 32, 0}, + {"fixup_riscv_pcrel_hi20", 12, 20, MCFixupKindInfo::FKF_IsPCRel | MCFixupKindInfo::FKF_IsTarget}, + {"fixup_riscv_pcrel_lo12_i", 20, 12, MCFixupKindInfo::FKF_IsPCRel | MCFixupKindInfo::FKF_IsTarget}, + {"fixup_riscv_pcrel_lo12_s", 0, 32, MCFixupKindInfo::FKF_IsPCRel | MCFixupKindInfo::FKF_IsTarget}, + {"fixup_riscv_got_hi20", 12, 20, MCFixupKindInfo::FKF_IsPCRel}, + {"fixup_riscv_tprel_hi20", 12, 20, 0}, + {"fixup_riscv_tprel_lo12_i", 20, 12, 0}, + {"fixup_riscv_tprel_lo12_s", 0, 32, 0}, + {"fixup_riscv_tprel_add", 0, 0, 0}, + {"fixup_riscv_tls_got_hi20", 12, 20, MCFixupKindInfo::FKF_IsPCRel}, + {"fixup_riscv_tls_gd_hi20", 12, 20, MCFixupKindInfo::FKF_IsPCRel}, + {"fixup_riscv_jal", 12, 20, MCFixupKindInfo::FKF_IsPCRel}, + {"fixup_riscv_branch", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, + {"fixup_riscv_rvc_jump", 2, 11, MCFixupKindInfo::FKF_IsPCRel}, + {"fixup_riscv_rvc_branch", 0, 16, MCFixupKindInfo::FKF_IsPCRel}, + {"fixup_riscv_call", 0, 64, MCFixupKindInfo::FKF_IsPCRel}, + {"fixup_riscv_call_plt", 0, 64, MCFixupKindInfo::FKF_IsPCRel}, + {"fixup_riscv_relax", 0, 0, 0}, + {"fixup_riscv_align", 0, 0, 0}, + {"fixup_pulpv2_loop_setup", 20, 12, MCFixupKindInfo::FKF_IsPCRel }, + {"fixup_pulpv2_loop_setupi", 15, 5, MCFixupKindInfo::FKF_IsPCRel } + }; + if (Kind >= FirstLiteralRelocationKind) { + return MCAsmBackend::getFixupKindInfo(FK_NONE); + } + if (Kind < FirstTargetFixupKind) { + return MCAsmBackend::getFixupKindInfo(Kind); + } + assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && "Invalid kind!"); + return Infos[Kind - FirstTargetFixupKind]; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/getNumFixupKinds.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/getNumFixupKinds.cpp new file mode 100644 index 0000000000000000000000000000000000000000..746a8de2786e0986eb0d4ef57b90b600aa813eb4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/getNumFixupKinds.cpp @@ -0,0 +1,3 @@ +unsigned getNumFixupKinds() const override { + return RISCV::NumTargetFixupKinds; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/getRelaxedOpcode.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/getRelaxedOpcode.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7a8dce3b201b77083cd73b657c5dac73e342fdca --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/getRelaxedOpcode.cpp @@ -0,0 +1,15 @@ +unsigned RISCVAsmBackend::getRelaxedOpcode(unsigned Op) const { + if (Op == RISCV::C_BEQZ) { + return RISCV::BEQ; + } + if (Op == RISCV::C_BNEZ) { + return RISCV::BNE; + } + if (Op == RISCV::C_J) { + return RISCV::JAL; + } + if (Op == RISCV::C_JAL) { + return RISCV::JAL; + } + return Op; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/getTargetABI.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/getTargetABI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6ba240b805d561f415ec4ee11045c3d6eb8dea8e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/getTargetABI.cpp @@ -0,0 +1,3 @@ +RISCVABI::ABI getTargetABI() const { + return TargetABI; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/getTargetOptions.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/getTargetOptions.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0ba9da6c2169958b5222a337d15c7920c3b3a0a4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/getTargetOptions.cpp @@ -0,0 +1,3 @@ +const MCTargetOptions &getTargetOptions() const { + return TargetOptions; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/mayNeedRelaxation.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/mayNeedRelaxation.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a6ab22b5e3a82bac66595e73244230ced8e6c2cb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/mayNeedRelaxation.cpp @@ -0,0 +1,15 @@ +bool RISCVAsmBackend::mayNeedRelaxation(const MCInst &Inst, const MCSubtargetInfo &STI) const { + if (Inst.getOpcode() == RISCV::C_BEQZ) { + return true; + } + if (Inst.getOpcode() == RISCV::C_BNEZ) { + return true; + } + if (Inst.getOpcode() == RISCV::C_J) { + return true; + } + if (Inst.getOpcode() == RISCV::C_JAL) { + return true; + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/relaxInstruction.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/relaxInstruction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5d47f9e24849b2b1245e390ffc5e557ee66c2675 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/relaxInstruction.cpp @@ -0,0 +1,34 @@ +void RISCVAsmBackend::relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI, MCInst &Res) const { + MCInst Res; + if (Inst.getOpcode() == RISCV::C_BEQZ) { + Res.setOpcode(RISCV::BEQ); + Res.addOperand(Inst.getOperand(0)); + Res.addOperand(MCOperand::createReg(RISCV::X0)); + Res.addOperand(Inst.getOperand(1)); + Inst = std::move(Res); + return ; + } + if (Inst.getOpcode() == RISCV::C_BNEZ) { + Res.setOpcode(RISCV::BNE); + Res.addOperand(Inst.getOperand(0)); + Res.addOperand(MCOperand::createReg(RISCV::X0)); + Res.addOperand(Inst.getOperand(1)); + Inst = std::move(Res); + return ; + } + if (Inst.getOpcode() == RISCV::C_J) { + Res.setOpcode(RISCV::JAL); + Res.addOperand(MCOperand::createReg(RISCV::X0)); + Res.addOperand(Inst.getOperand(0)); + Inst = std::move(Res); + return ; + } + if (Inst.getOpcode() == RISCV::C_JAL) { + Res.setOpcode(RISCV::JAL); + Res.addOperand(MCOperand::createReg(RISCV::X1)); + Res.addOperand(Inst.getOperand(0)); + Inst = std::move(Res); + return ; + } + llvm_unreachable("Opcode not expected!"); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/requiresDiffExpressionRelocations.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/requiresDiffExpressionRelocations.cpp new file mode 100644 index 0000000000000000000000000000000000000000..20caba2eb4d9bfb4a0d6f036615d2b0b9b4de29d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/requiresDiffExpressionRelocations.cpp @@ -0,0 +1,3 @@ +bool requiresDiffExpressionRelocations() const override { + return willForceRelocations(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/setForceRelocs.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/setForceRelocs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c50c542fcb66c027d042a9f86d3a2b22389d8363 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/setForceRelocs.cpp @@ -0,0 +1,3 @@ +void setForceRelocs() { + ForceRelocs = true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/shouldForceRelocation.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/shouldForceRelocation.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c0852e12e8e13bf21bbe587a79b70ddb929dbc0e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/shouldForceRelocation.cpp @@ -0,0 +1,45 @@ +bool RISCVAsmBackend::shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target) { + if (Fixup.getTargetKind() >= FirstLiteralRelocationKind) { + return true; + } + if (Fixup.getTargetKind() == FK_Data_1) { + if (Target.isAbsolute()) { + return false; + } + return true; + } + if (Fixup.getTargetKind() == FK_Data_2) { + if (Target.isAbsolute()) { + return false; + } + return true; + } + if (Fixup.getTargetKind() == FK_Data_4) { + if (Target.isAbsolute()) { + return false; + } + return true; + } + if (Fixup.getTargetKind() == FK_Data_8) { + if (Target.isAbsolute()) { + return false; + } + return true; + } + if (Fixup.getTargetKind() == RISCV::fixup_riscv_got_hi20) { + return true; + } + if (Fixup.getTargetKind() == RISCV::fixup_riscv_tls_got_hi20) { + return true; + } + if (Fixup.getTargetKind() == RISCV::fixup_riscv_tls_gd_hi20) { + return true; + } + if (Fixup.getTargetKind() == RISCV::fixup_pulpv2_loop_setup) { + return false; + } + if (Fixup.getTargetKind() == RISCV::fixup_pulpv2_loop_setupi) { + return false; + } + return STI.getFeatureBits()[RISCV::FeatureRelax] || ForceRelocs; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/shouldInsertExtraNopBytesForCodeAlign.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/shouldInsertExtraNopBytesForCodeAlign.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cbc97e17845d545983c933ea23dc3e4c437503b0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/shouldInsertExtraNopBytesForCodeAlign.cpp @@ -0,0 +1,14 @@ +bool RISCVAsmBackend::shouldInsertExtraNopBytesForCodeAlign(const MCAlignFragment &AF, unsigned &Size) { + if (!STI.getFeatureBits()[RISCV::FeatureRelax]) { + return false; + } + bool HasStdExtC = STI.getFeatureBits()[RISCV::FeatureStdExtC]; + unsigned MinNopLen = HasStdExtC ? 2 : 4; + if (AF.getAlignment() <= MinNopLen) { + return false; + } + else { + Size = AF.getAlignment() - MinNopLen; + return true; + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/shouldInsertFixupForCodeAlign.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/shouldInsertFixupForCodeAlign.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0cba76a5121626885e6f5d385f92d143bb1bbf7e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/shouldInsertFixupForCodeAlign.cpp @@ -0,0 +1,16 @@ +bool RISCVAsmBackend::shouldInsertFixupForCodeAlign(MCAssembler &Asm, const MCAsmLayout &Layout, MCAlignFragment &AF) { + if (!STI.getFeatureBits()[RISCV::FeatureRelax]) { + return false; + } + unsigned Count; + if (!shouldInsertExtraNopBytesForCodeAlign(AF, Count) || (Count == 0)) { + return false; + } + MCContext &Ctx = Asm.getContext(); + const MCExpr *Dummy = MCConstantExpr::create(0, Ctx); + MCFixup Fixup = MCFixup::create(0, Dummy, MCFixupKind(RISCV::fixup_riscv_align), SMLoc()); + uint64_t FixedValue = 0; + MCValue NopBytes = MCValue::get(Count); + Asm.getWriter().recordRelocation(Asm, Layout, &AF, Fixup, NopBytes, FixedValue); + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/willForceRelocations.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/willForceRelocations.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8d4f67dbd32002e52666f53c763a70a4dba9e31b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/willForceRelocations.cpp @@ -0,0 +1,3 @@ +bool willForceRelocations() const { + return ForceRelocs || STI.getFeatureBits()[RISCV::FeatureRelax]; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/writeNopData.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/writeNopData.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9d80a5b62dec8be0da614743dbfd8cce5bc86ea5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/writeNopData.cpp @@ -0,0 +1,14 @@ +bool RISCVAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const { + if (Count % 2 != 0) { + return false; + } + uint64_t NopCount = Count / 4; + uint64_t i; + for (i = 0; i < NopCount; ++i) { + OS.write("\x13\0\0\0", 4); + } + if (Count % 4 == 2) { + OS.write("\x01\0", 2); + } + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/~AsmBackend.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/~AsmBackend.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ef098a67f9366ad081d706783370f6efc23e3a48 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmBackend/~AsmBackend.cpp @@ -0,0 +1,2 @@ +~RISCVAsmBackend() override { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmInfo/MCAsmInfo.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmInfo/MCAsmInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9421589a9b9c1fc5b796893153daedb95b1d0d46 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmInfo/MCAsmInfo.cpp @@ -0,0 +1,10 @@ +RISCVMCAsmInfo::RISCVMCAsmInfo(const Triple &TT) { + CodePointerSize = TT.isArch64Bit() ? 8 : 4; + CalleeSaveStackSlotSize = TT.isArch64Bit() ? 8 : 4; + CommentString = "#"; + AlignmentIsInBytes = false; + SupportsDebugInformation = true; + ExceptionsType = ExceptionHandling::DwarfCFI; + Data16bitsDirective = "\t.half\t"; + Data32bitsDirective = "\t.word\t"; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmInfo/anchor.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmInfo/anchor.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a347705836916e209cf07b3a754f158902edef80 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmInfo/anchor.cpp @@ -0,0 +1,2 @@ +void RISCVMCAsmInfo::anchor() { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmInfo/getExprForFDESymbol.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmInfo/getExprForFDESymbol.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8123d7641ff42e395a6fae61de4cd9e72363c53a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/AsmInfo/getExprForFDESymbol.cpp @@ -0,0 +1,7 @@ +const MCExpr *RISCVMCAsmInfo::getExprForFDESymbol(const MCSymbol *Sym, unsigned Encoding, MCStreamer &Streamer) const { + if (Encoding & dwarf::DW_EH_PE_pcrel) { + MCContext &Ctx = Streamer.getContext(); + return RISCVMCExpr::create(MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, Ctx), RISCVMCExpr::VK_RISCV_32_PCREL, Ctx); + } + return MCAsmInfo::getExprForFDESymbol(Sym, Encoding, Streamer); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/BaseInfo/ABI.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/BaseInfo/ABI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f3883bfb643c747efaf1bd19098e38d0e4607708 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/BaseInfo/ABI.cpp @@ -0,0 +1,10 @@ +enum ABI { + ABI_ILP32, + ABI_ILP32F, + ABI_ILP32D, + ABI_ILP32E, + ABI_LP64, + ABI_LP64F, + ABI_LP64D, + ABI_Unknown +}; diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/BaseInfo/FenceField.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/BaseInfo/FenceField.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7c7b1924b5725066d01f765ea8d324f0c5053f3b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/BaseInfo/FenceField.cpp @@ -0,0 +1,6 @@ +enum FenceField { + I = 8, + O = 4, + R = 2, + W = 1 +}; diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/BaseInfo/II.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/BaseInfo/II.cpp new file mode 100644 index 0000000000000000000000000000000000000000..50b9d9071889f3b5a387cf23e5363093dd124268 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/BaseInfo/II.cpp @@ -0,0 +1,53 @@ +namespace RISCVII { +enum { + InstFormatPseudo = 0, + InstFormatR = 1, + InstFormatR4 = 2, + InstFormatI = 3, + InstFormatS = 4, + InstFormatB = 5, + InstFormatU = 6, + InstFormatJ = 7, + InstFormatCR = 8, + InstFormatCI = 9, + InstFormatCSS = 10, + InstFormatCIW = 11, + InstFormatCL = 12, + InstFormatCS = 13, + InstFormatCA = 14, + InstFormatCB = 15, + InstFormatCJ = 16, + InstFormatOther = 17, + InstFormatMask = 31, + ConstraintShift = 5, + ConstraintMask = 0b111 << ConstraintShift, + VLMulShift = ConstraintShift + 3, + VLMulMask = 0b111 , + HasDummyMaskOpShift = 3 , + HasDummyMaskOpShift = 1 , + WritesElement0Shift = HasDummyMaskOpShift + 1, + WritesElement0Mask = 1 << WritesElement0Shift, + HasMergeOpShift = 1 , + HasMergeOpMask = 1 << HasMergeOpShift, + HasSEWOpShift = 1 , + HasVLOpShift = 1 , + HasVLOpShift = HasSEWOpShift + 1, + HasVLOpMask = 1 << HasVLOpShift, +}; +enum { + MO_None = 0, + MO_CALL = 1, + MO_PLT = 2, + MO_LO = 3, + MO_HI = 4, + MO_PCREL_LO = 5, + MO_PCREL_HI = 6, + MO_GOT_HI = 7, + MO_TPREL_LO = 8, + MO_TPREL_HI = 9, + MO_TPREL_ADD = 10, + MO_TLS_GOT_HI = 11, + MO_TLS_GD_HI = 12, + MO_DIRECT_FLAG_MASK = 15 +}; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/BaseInfo/OperandType.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/BaseInfo/OperandType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a35e89e4ca6e38f5ab53518181d3b3f75ef59918 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/BaseInfo/OperandType.cpp @@ -0,0 +1,12 @@ +enum OperandType : unsigned { + OPERAND_FIRST_RISCV_IMM = MCOI::OPERAND_FIRST_TARGET, + OPERAND_UIMM4 = OPERAND_FIRST_RISCV_IMM, + OPERAND_UIMM5, + OPERAND_UIMM12, + OPERAND_UIMM12M1, + OPERAND_UIMM3, + OPERAND_SIMM12, + OPERAND_UIMM20, + OPERAND_UIMMLOG2XLEN, + OPERAND_LAST_RISCV_IMM = OPERAND_UIMMLOG2XLEN +}; diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/BaseInfo/RISCVVSEW.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/BaseInfo/RISCVVSEW.cpp new file mode 100644 index 0000000000000000000000000000000000000000..48e9a099c10a3c910227f7c4c692f1923cd7b265 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/BaseInfo/RISCVVSEW.cpp @@ -0,0 +1,10 @@ +enum class RISCVVSEW { + SEW_8 = 0, + SEW_16, + SEW_32, + SEW_64, + SEW_128, + SEW_256, + SEW_512, + SEW_1024, +}; diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/BaseInfo/RVVConstraintType.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/BaseInfo/RVVConstraintType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7f6426c797a3087af47909f6164404258de6ea5e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/BaseInfo/RVVConstraintType.cpp @@ -0,0 +1,6 @@ +enum RVVConstraintType { + NoConstraint = 0, + VS2Constraint = 0b001, + VS1Constraint = 0b010, + VMConstraint = 0b100, +}; diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/BaseInfo/RoundingMode.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/BaseInfo/RoundingMode.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9322bf2c008867e4d73fcd793cfb9480b8f6f94f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/BaseInfo/RoundingMode.cpp @@ -0,0 +1,9 @@ +enum RoundingMode { + RNE = 0, + RTZ = 1, + RDN = 2, + RUP = 3, + RMM = 4, + DYN = 7, + Invalid +}; diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/BaseInfo/VLMUL.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/BaseInfo/VLMUL.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4623e7ccd5fedd630b880aaa84b07f4a81dcf701 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/BaseInfo/VLMUL.cpp @@ -0,0 +1,10 @@ +enum class RISCVVLMUL { + LMUL_1 = 0, + LMUL_2, + LMUL_4, + LMUL_8, + LMUL_RESERVED, + LMUL_F8, + LMUL_F4, + LMUL_F2 +}; diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/BaseInfo/VMTs.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/BaseInfo/VMTs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2add02bb943bcb64d7795721888ad1d4a89d0dfd --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/BaseInfo/VMTs.cpp @@ -0,0 +1,46 @@ +namespace RISCVVMVTs { +constexpr MVT vint8mf8_t = MVT::nxv1i8; +constexpr MVT vint8mf4_t = MVT::nxv2i8; +constexpr MVT vint8mf2_t = MVT::nxv4i8; +constexpr MVT vint8m1_t = MVT::nxv8i8; +constexpr MVT vint8m2_t = MVT::nxv16i8; +constexpr MVT vint8m4_t = MVT::nxv32i8; +constexpr MVT vint8m8_t = MVT::nxv64i8; +constexpr MVT vint16mf4_t = MVT::nxv1i16; +constexpr MVT vint16mf2_t = MVT::nxv2i16; +constexpr MVT vint16m1_t = MVT::nxv4i16; +constexpr MVT vint16m2_t = MVT::nxv8i16; +constexpr MVT vint16m4_t = MVT::nxv16i16; +constexpr MVT vint16m8_t = MVT::nxv32i16; +constexpr MVT vint32mf2_t = MVT::nxv1i32; +constexpr MVT vint32m1_t = MVT::nxv2i32; +constexpr MVT vint32m2_t = MVT::nxv4i32; +constexpr MVT vint32m4_t = MVT::nxv8i32; +constexpr MVT vint32m8_t = MVT::nxv16i32; +constexpr MVT vint64m1_t = MVT::nxv1i64; +constexpr MVT vint64m2_t = MVT::nxv2i64; +constexpr MVT vint64m4_t = MVT::nxv4i64; +constexpr MVT vint64m8_t = MVT::nxv8i64; +constexpr MVT vfloat16mf4_t = MVT::nxv1f16; +constexpr MVT vfloat16mf2_t = MVT::nxv2f16; +constexpr MVT vfloat16m1_t = MVT::nxv4f16; +constexpr MVT vfloat16m2_t = MVT::nxv8f16; +constexpr MVT vfloat16m4_t = MVT::nxv16f16; +constexpr MVT vfloat16m8_t = MVT::nxv32f16; +constexpr MVT vfloat32mf2_t = MVT::nxv1f32; +constexpr MVT vfloat32m1_t = MVT::nxv2f32; +constexpr MVT vfloat32m2_t = MVT::nxv4f32; +constexpr MVT vfloat32m4_t = MVT::nxv8f32; +constexpr MVT vfloat32m8_t = MVT::nxv16f32; +constexpr MVT vfloat64m1_t = MVT::nxv1f64; +constexpr MVT vfloat64m2_t = MVT::nxv2f64; +constexpr MVT vfloat64m4_t = MVT::nxv4f64; +constexpr MVT vfloat64m8_t = MVT::nxv8f64; +constexpr MVT vbool1_t = MVT::nxv64i1; +constexpr MVT vbool2_t = MVT::nxv32i1; +constexpr MVT vbool4_t = MVT::nxv16i1; +constexpr MVT vbool8_t = MVT::nxv8i1; +constexpr MVT vbool16_t = MVT::nxv4i1; +constexpr MVT vbool32_t = MVT::nxv2i1; +constexpr MVT vbool64_t = MVT::nxv1i1; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/BaseInfo/computeTargetABI.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/BaseInfo/computeTargetABI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..089445f3c62c65b40b2eec1e8b2b0026a81373bc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/BaseInfo/computeTargetABI.cpp @@ -0,0 +1,30 @@ +ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits, StringRef ABIName) { + auto TargetABI = getTargetABI(ABIName); + bool IsRV64 = TT.isArch64Bit(); + bool IsRV32E = FeatureBits[RISCV::FeatureRV32E]; + if (!ABIName.empty() && TargetABI == ABI_Unknown) { + errs() << "'" << ABIName << "' is not a recognized ABI for this target (ignoring target-abi)\n"; + } + else if (ABIName.startswith("ilp32") && IsRV64) { + errs() << "32-bit ABIs are not supported for 64-bit targets (ignoring target-abi)\n"; + TargetABI = ABI_Unknown; + } + else if (ABIName.startswith("lp64") && !IsRV64) { + errs() << "64-bit ABIs are not supported for 32-bit targets (ignoring target-abi)\n"; + TargetABI = ABI_Unknown; + } + else if (IsRV32E && TargetABI != ABI_ILP32E && TargetABI != ABI_Unknown) { + errs() << "Only the ilp32e ABI is supported for RV32E (ignoring target-abi)\n"; + TargetABI = ABI_Unknown; + } + if (TargetABI != ABI_Unknown) { + return TargetABI; + } + if (IsRV32E) { + return ABI_ILP32E; + } + if (IsRV64) { + return ABI_LP64; + } + return ABI_ILP32; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/BaseInfo/getTargetABI.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/BaseInfo/getTargetABI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fd4ae74cfd65a034a0b6664d2b6d0d58e37164c6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/BaseInfo/getTargetABI.cpp @@ -0,0 +1,24 @@ +ABI getTargetABI(StringRef Str) { + if (Str == "ilp32") { + return ABI_ILP32; + } + if (Str == "ilp32f") { + return ABI_ILP32F; + } + if (Str == "ilp32d") { + return ABI_ILP32D; + } + if (Str == "ilp32e") { + return ABI_ILP32E; + } + if (Str == "lp64") { + return ABI_LP64; + } + if (Str == "lp64f") { + return ABI_LP64F; + } + if (Str == "lp64d") { + return ABI_LP64D; + } + return ABI_Unknown; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/BaseInfo/roundingModeToString.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/BaseInfo/roundingModeToString.cpp new file mode 100644 index 0000000000000000000000000000000000000000..11291aabba65a0d4a8c320fdbf84a1e20058c498 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/BaseInfo/roundingModeToString.cpp @@ -0,0 +1,18 @@ +inline static StringRef roundingModeToString(RoundingMode RndMode) { + switch (RndMode) { + case RISCVFPRndMode::RNE: + return "rne"; + case RISCVFPRndMode::RTZ: + return "rtz"; + case RISCVFPRndMode::RDN: + return "rdn"; + case RISCVFPRndMode::RUP: + return "rup"; + case RISCVFPRndMode::RMM: + return "rmm"; + case RISCVFPRndMode::DYN: + return "dyn"; + default: + llvm_unreachable("Unknown floating point rounding mode"); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/BaseInfo/stringToRoundingMode.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/BaseInfo/stringToRoundingMode.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a002650de82613870fdc7f3717210aa582d6de4f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/BaseInfo/stringToRoundingMode.cpp @@ -0,0 +1,21 @@ +inline static RoundingMode stringToRoundingMode(StringRef Str) { + if (Str == "rne") { + return RISCVFPRndMode::RNE; + } + if (Str == "rtz") { + return RISCVFPRndMode::RTZ; + } + if (Str == "rdn") { + return RISCVFPRndMode::RDN; + } + if (Str == "rup") { + return RISCVFPRndMode::RUP; + } + if (Str == "rmm") { + return RISCVFPRndMode::RMM; + } + if (Str == "dyn") { + return RISCVFPRndMode::DYN; + } + return RISCVFPRndMode::Invalid; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/BaseInfo/validate.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/BaseInfo/validate.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ea0370ee02ed8822169582aef94e41cbbfdc3892 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/BaseInfo/validate.cpp @@ -0,0 +1,5 @@ +void validate(const Triple &TT, const FeatureBitset &FeatureBits) { + if (TT.isArch64Bit() && FeatureBits[RISCV::FeatureRV32E]) { + report_fatal_error("RV32E can't be enabled for an RV64 target"); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFObjectWriter/ELFObjectWriter.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFObjectWriter/ELFObjectWriter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4f33f3e20c0425160b017bce65157ee473529c2e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFObjectWriter/ELFObjectWriter.cpp @@ -0,0 +1,2 @@ +RISCVELFObjectWriter::RISCVELFObjectWriter(uint8_t OSABI, bool Is64Bit) : MCELFObjectTargetWriter(Is64Bit, OSABI, ELF::EM_RISCV, true) { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFObjectWriter/createELFObjectWriter.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFObjectWriter/createELFObjectWriter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cf93750ac33e2b6b5c2496f27834ac02c19f9105 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFObjectWriter/createELFObjectWriter.cpp @@ -0,0 +1,3 @@ +std::unique_ptr llvm::createRISCVELFObjectWriter(uint8_t OSABI, bool Is64Bit) { + return std::make_unique(OSABI, Is64Bit); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFObjectWriter/getRelocType.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFObjectWriter/getRelocType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8a44c3413af04ac4c9d6be604ed4b53764f19723 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFObjectWriter/getRelocType.cpp @@ -0,0 +1,138 @@ +unsigned RISCVELFObjectWriter::getRelocType(MCContext &Ctx, const MCValue &Target, const MCFixup &Fixup, bool IsPCRel) const { + const RISCVMCExpr *SExpr; + if (SExpr = dyn_cast(Fixup.getValue())) { + if (SExpr->getKind() == RISCVMCExpr::VK_RISCV_32_PCREL) { + return ELF::R_RISCV_32_PCREL; + } + } + const MCExpr *Expr = Fixup.getValue(); + unsigned Kind = Fixup.getTargetKind(); + if (Kind >= FirstLiteralRelocationKind){ + return Kind - FirstLiteralRelocationKind; + } + if (IsPCRel) { + if (Kind == FK_PCRel_4) { + return ELF::R_RISCV_32_PCREL; + } + if (Kind == RISCV::fixup_riscv_pcrel_hi20) { + return ELF::R_RISCV_PCREL_HI20; + } + if (Kind == RISCV::fixup_riscv_pcrel_lo12_i) { + return ELF::R_RISCV_PCREL_LO12_I; + } + if (Kind == RISCV::fixup_riscv_pcrel_lo12_s) { + return ELF::R_RISCV_PCREL_LO12_S; + } + if (Kind == FK_Data_4) { + return ELF::R_RISCV_32_PCREL; + } + if (Kind == RISCV::fixup_riscv_got_hi20) { + return ELF::R_RISCV_GOT_HI20; + } + if (Kind == RISCV::fixup_riscv_tls_got_hi20) { + return ELF::R_RISCV_TLS_GOT_HI20; + } + if (Kind == RISCV::fixup_riscv_tls_gd_hi20) { + return ELF::R_RISCV_TLS_GD_HI20; + } + if (Kind == RISCV::fixup_riscv_jal) { + return ELF::R_RISCV_JAL; + } + if (Kind == RISCV::fixup_riscv_branch) { + return ELF::R_RISCV_BRANCH; + } + if (Kind == RISCV::fixup_riscv_rvc_jump) { + return ELF::R_RISCV_RVC_JUMP; + } + if (Kind == RISCV::fixup_riscv_rvc_branch) { + return ELF::R_RISCV_RVC_BRANCH; + } + if (Kind == RISCV::fixup_riscv_call) { + return ELF::R_RISCV_CALL; + } + if (Kind == RISCV::fixup_riscv_call_plt) { + return ELF::R_RISCV_CALL_PLT; + } + if (Kind == RISCV::fixup_pulpv2_loop_setup) { + return ELF::R_PULPV2_LOOP_SETUP; + } + if (Kind == RISCV::fixup_pulpv2_loop_setupi) { + return ELF::R_PULPV2_LOOP_SETUPI; + } + Ctx.reportError(Fixup.getLoc(), "Unsupported relocation type"); + return ELF::R_RISCV_NONE; + } + if (Kind == FK_Data_4) { + return ELF::R_RISCV_32; + } + if (Kind == FK_Data_8) { + return ELF::R_RISCV_64; + } + if (Kind == FK_Data_Add_1) { + return ELF::R_RISCV_ADD8; + } + if (Kind == FK_Data_Add_2) { + return ELF::R_RISCV_ADD16; + } + if (Kind == FK_Data_Add_4) { + return ELF::R_RISCV_ADD32; + } + if (Kind == FK_Data_Add_8) { + return ELF::R_RISCV_ADD64; + } + if (Kind == FK_Data_1) { + Ctx.reportError(Fixup.getLoc(), "1-byte data relocations not supported"); + return ELF::R_RISCV_NONE; + } + if (Kind == FK_Data_2) { + Ctx.reportError(Fixup.getLoc(), "2-byte data relocations not supported"); + return ELF::R_RISCV_NONE; + } + if (Kind == FK_Data_Add_6b) { + return ELF::R_RISCV_SET6; + } + if (Kind == FK_Data_Sub_1) { + return ELF::R_RISCV_SUB8; + } + if (Kind == FK_Data_Sub_2) { + return ELF::R_RISCV_SUB16; + } + if (Kind == FK_Data_Sub_4) { + return ELF::R_RISCV_SUB32; + } + if (Kind == FK_Data_Sub_8) { + return ELF::R_RISCV_SUB64; + } + if (Kind == FK_Data_Sub_6b) { + return ELF::R_RISCV_SUB6; + } + if (Kind == RISCV::fixup_riscv_hi20) { + return ELF::R_RISCV_HI20; + } + if (Kind == RISCV::fixup_riscv_lo12_i) { + return ELF::R_RISCV_LO12_I; + } + if (Kind == RISCV::fixup_riscv_lo12_s) { + return ELF::R_RISCV_LO12_S; + } + if (Kind == RISCV::fixup_riscv_tprel_hi20) { + return ELF::R_RISCV_TPREL_HI20; + } + if (Kind == RISCV::fixup_riscv_tprel_lo12_i) { + return ELF::R_RISCV_TPREL_LO12_I; + } + if (Kind == RISCV::fixup_riscv_tprel_lo12_s) { + return ELF::R_RISCV_TPREL_LO12_S; + } + if (Kind == RISCV::fixup_riscv_tprel_add) { + return ELF::R_RISCV_TPREL_ADD; + } + if (Kind == RISCV::fixup_riscv_relax) { + return ELF::R_RISCV_RELAX; + } + if (Kind == RISCV::fixup_riscv_align) { + return ELF::R_RISCV_ALIGN; + } + Ctx.reportError(Fixup.getLoc(), "Unsupported relocation type"); + return ELF::R_RISCV_NONE; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFObjectWriter/needsRelocateWithSymbol.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFObjectWriter/needsRelocateWithSymbol.cpp new file mode 100644 index 0000000000000000000000000000000000000000..946e0c43f12add7422f67306d02b7ec156134cb1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFObjectWriter/needsRelocateWithSymbol.cpp @@ -0,0 +1,3 @@ +bool needsRelocateWithSymbol(const MCSymbol &Sym, unsigned Type) const override { + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFObjectWriter/~ELFObjectWriter.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFObjectWriter/~ELFObjectWriter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3c1de5f7645a8cf79fb3b5ae7778810e57bd7de1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFObjectWriter/~ELFObjectWriter.cpp @@ -0,0 +1,2 @@ +RISCVELFObjectWriter::~RISCVELFObjectWriter() { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/AttributeItem.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/AttributeItem.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9f273585d2fbc4baf7b49dd8b5f86b5b3c7ee666 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/AttributeItem.cpp @@ -0,0 +1,6 @@ +struct AttributeItem { + AttributeType Type; + unsigned Tag; + unsigned IntValue; + std::string StringValue; +}; diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/AttributeType.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/AttributeType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0bfefe54c5445d3443931e6df0f69603042c15ed --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/AttributeType.cpp @@ -0,0 +1,6 @@ +enum class AttributeType { + Hidden, + Numeric, + Text, + NumericAndText +}; diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/TargetELFStreamer.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/TargetELFStreamer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..259b611fd6b6b41d92f0d9791a83cf2ea7314cb4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/TargetELFStreamer.cpp @@ -0,0 +1,40 @@ +RISCVTargetELFStreamer::RISCVTargetELFStreamer(MCStreamer &S, const MCSubtargetInfo &STI) : RISCVTargetStreamer(S), CurrentVendor("riscv") { + MCAssembler &MCA = getStreamer().getAssembler(); + const FeatureBitset &Features = STI.getFeatureBits(); + auto &MAB = static_cast(MCA.getBackend()); + RISCVABI::ABI ABI = MAB.getTargetABI(); + assert(ABI != RISCVABI::ABI_Unknown && "Improperly initialised target ABI"); + unsigned EFlags = MCA.getELFHeaderEFlags(); + if (Features[RISCV::FeatureStdExtC]) { + EFlags = EFlags | ELF::EF_RISCV_RVC; + } + if (ABI == RISCVABI::ABI_ILP32) { + MCA.setELFHeaderEFlags(EFlags); + } + if (ABI == RISCVABI::ABI_LP64) { + MCA.setELFHeaderEFlags(EFlags); + } + if (ABI == RISCVABI::ABI_ILP32F) { + EFlags = EFlags | ELF::EF_RISCV_FLOAT_ABI_SINGLE; + MCA.setELFHeaderEFlags(EFlags); + } + if (ABI == RISCVABI::ABI_LP64F) { + EFlags = EFlags | ELF::EF_RISCV_FLOAT_ABI_SINGLE; + MCA.setELFHeaderEFlags(EFlags); + } + if (ABI == RISCVABI::ABI_ILP32D) { + EFlags = EFlags | ELF::EF_RISCV_FLOAT_ABI_DOUBLE; + MCA.setELFHeaderEFlags(EFlags); + } + if (ABI == RISCVABI::ABI_LP64D) { + EFlags = EFlags | ELF::EF_RISCV_FLOAT_ABI_DOUBLE; + MCA.setELFHeaderEFlags(EFlags); + } + if (ABI == RISCVABI::ABI_ILP32E) { + EFlags = EFlags | ELF::EF_RISCV_RVE; + MCA.setELFHeaderEFlags(EFlags); + } + if (ABI == RISCVABI::ABI_Unknown) { + llvm_unreachable("Improperly initialised target ABI"); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/calculateContentSize.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/calculateContentSize.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3594e1ecd0913c40fb32f167f15a5b118204b93a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/calculateContentSize.cpp @@ -0,0 +1,23 @@ +size_t RISCVTargetELFStreamer::calculateContentSize() const { + size_t Result = 0; + for (AttributeItem item : Contents) { + switch (item.Type) { + case AttributeType::Hidden: + break; + case AttributeType::Numeric: + Result += getULEB128Size(item.Tag); + Result += getULEB128Size(item.IntValue); + break; + case AttributeType::Text: + Result += getULEB128Size(item.Tag); + Result += item.StringValue.size() + 1; + break; + case AttributeType::NumericAndText: + Result += getULEB128Size(item.Tag); + Result += getULEB128Size(item.IntValue); + Result += item.StringValue.size() + 1; + break; + } + } + return Result; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/emitAttribute.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/emitAttribute.cpp new file mode 100644 index 0000000000000000000000000000000000000000..093204945bdf9266020a4f252f5ba14556742ce0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/emitAttribute.cpp @@ -0,0 +1,3 @@ +void RISCVTargetELFStreamer::emitAttribute(unsigned Attribute, unsigned Value) { + setAttributeItem(Attribute, Value, true); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionNoPIC.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionNoPIC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6c03e079bf63ae8073d2ede610293d88e4fa88eb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionNoPIC.cpp @@ -0,0 +1,2 @@ +void RISCVTargetELFStreamer::emitDirectiveOptionNoPIC() { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionNoRVC.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionNoRVC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ae512f51c9e685aef4b8e839b94d030c9e642b97 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionNoRVC.cpp @@ -0,0 +1,2 @@ +void RISCVTargetELFStreamer::emitDirectiveOptionNoRVC() { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionNoRelax.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionNoRelax.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6c03e079bf63ae8073d2ede610293d88e4fa88eb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionNoRelax.cpp @@ -0,0 +1,2 @@ +void RISCVTargetELFStreamer::emitDirectiveOptionNoPIC() { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionPIC.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionPIC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e0df4494aa95369ebd9176fc8eb53b6979b3169d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionPIC.cpp @@ -0,0 +1,2 @@ +void RISCVTargetELFStreamer::emitDirectiveOptionPIC() { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionPop.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionPop.cpp new file mode 100644 index 0000000000000000000000000000000000000000..32917ce043bfc2eecfcf523c3a37644e75df0194 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionPop.cpp @@ -0,0 +1,2 @@ +void RISCVTargetELFStreamer::emitDirectiveOptionPop() { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionPush.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionPush.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5aedb00352e0d7bde5d482842d91f9acc06cbb0f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionPush.cpp @@ -0,0 +1,2 @@ +void RISCVTargetELFStreamer::emitDirectiveOptionPush() { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionRVC.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionRVC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9751c5671eb6fc82c84ff719958b4cda4f7fcd60 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionRVC.cpp @@ -0,0 +1,2 @@ +void RISCVTargetELFStreamer::emitDirectiveOptionRVC() { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionRelax.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionRelax.cpp new file mode 100644 index 0000000000000000000000000000000000000000..daf4623617344c5666aca7cfbbab1513a4eb66ad --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionRelax.cpp @@ -0,0 +1,2 @@ +void RISCVTargetELFStreamer::emitDirectiveOptionRelax() { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/emitIntTextAttribute.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/emitIntTextAttribute.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4373afae59249976a7f7250e5c2abc76b45c1349 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/emitIntTextAttribute.cpp @@ -0,0 +1,3 @@ +void RISCVTargetELFStreamer::emitIntTextAttribute(unsigned Attribute, unsigned IntValue, StringRef StringValue) { + setAttributeItems(Attribute, IntValue, StringValue, true); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/emitTextAttribute.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/emitTextAttribute.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3ac8a25c6405b9d62d6aa227a9ed6556f32070fc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/emitTextAttribute.cpp @@ -0,0 +1,3 @@ +void RISCVTargetELFStreamer::emitTextAttribute(unsigned Attribute, StringRef String) { + setAttributeItem(Attribute, String, true); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/finishAttributeSection.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/finishAttributeSection.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2f2489616110f13244dbe49376832a95d9564a9e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/finishAttributeSection.cpp @@ -0,0 +1,42 @@ +void RISCVTargetELFStreamer::finishAttributeSection() { + if (Contents.empty()) { + return ; + } + if (AttributeSection) { + Streamer.SwitchSection(AttributeSection); + } + else { + MCAssembler &MCA = getStreamer().getAssembler(); + AttributeSection = MCA.getContext().getELFSection(".riscv.attributes", ELF::SHT_RISCV_ATTRIBUTES, 0); + Streamer.SwitchSection(AttributeSection); + Streamer.emitInt8(ELFAttrs::Format_Version); + } + const size_t VendorHeaderSize = 4 + CurrentVendor.size() + 1; + const size_t TagHeaderSize = 1 + 4; + const size_t ContentsSize = calculateContentSize(); + Streamer.emitInt32(VendorHeaderSize + TagHeaderSize + ContentsSize); + Streamer.emitBytes(CurrentVendor); + Streamer.emitInt8(0); + Streamer.emitInt8(ELFAttrs::File); + Streamer.emitInt32(TagHeaderSize + ContentsSize); + for (AttributeItem item : Contents) { + Streamer.emitULEB128IntValue(item.Tag); + switch (item.Type) { + default: + llvm_unreachable("Invalid attribute type"); + case AttributeType::Numeric: + Streamer.emitULEB128IntValue(item.IntValue); + break; + case AttributeType::Text: + Streamer.emitBytes(item.StringValue); + Streamer.emitInt8(0); + break; + case AttributeType::NumericAndText: + Streamer.emitULEB128IntValue(item.IntValue); + Streamer.emitBytes(item.StringValue); + Streamer.emitInt8(0); + break; + } + } + Contents.clear(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/getAttributeItem.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/getAttributeItem.cpp new file mode 100644 index 0000000000000000000000000000000000000000..39d66abbc227662e2da806f5d4602ed1f7914637 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/getAttributeItem.cpp @@ -0,0 +1,8 @@ +AttributeItem *getAttributeItem(unsigned Attribute) { + for (size_t i = 0; i < Contents.size(); ++i) { + if (Contents[i].Tag == Attribute) { + return &Contents[i]; + } + } + return nullptr; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/getStreamer.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/getStreamer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..299b2c39af48ecf340b541686259cbf54c049d4f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/getStreamer.cpp @@ -0,0 +1,3 @@ +MCELFStreamer &RISCVTargetELFStreamer::getStreamer() { + return static_cast(Streamer); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/setAttributeItem1.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/setAttributeItem1.cpp new file mode 100644 index 0000000000000000000000000000000000000000..deacd4eaf5d070a5bbea710bbd81b77e0bcd09fb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/setAttributeItem1.cpp @@ -0,0 +1,11 @@ +void setAttributeItem(unsigned Attribute, unsigned Value, bool OverwriteExisting) { + if (AttributeItem *Item = getAttributeItem(Attribute)) { + if (!OverwriteExisting) { + return ; + } + Item->Type = AttributeType::Numeric; + Item->IntValue = Value; + return; + } + Contents.push_back({AttributeType::Numeric, Attribute, Value, ""}); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/setAttributeItem2.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/setAttributeItem2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fd7620a2c8dd656c22df61966125549d23aba3d6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/setAttributeItem2.cpp @@ -0,0 +1,11 @@ +void setAttributeItem(unsigned Attribute, StringRef Value, bool OverwriteExisting) { + if (AttributeItem *Item = getAttributeItem(Attribute)) { + if (!OverwriteExisting) { + return ; + } + Item->Type = AttributeType::Text; + Item->StringValue = std::string(Value); + return; + } + Contents.push_back({AttributeType::Text, Attribute, 0, std::string(Value)}); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/setAttributeItems.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/setAttributeItems.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fa5d986ed08a7aa3efff0db7d1b2e17d2bfe429a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/ELFStreamer/setAttributeItems.cpp @@ -0,0 +1,12 @@ +void setAttributeItems(unsigned Attribute, unsigned IntValue, StringRef StringValue, bool OverwriteExisting) { + if (AttributeItem *Item = getAttributeItem(Attribute)) { + if (!OverwriteExisting) { + return ; + } + Item->Type = AttributeType::NumericAndText; + Item->IntValue = IntValue; + Item->StringValue = std::string(StringValue); + return ; + } + Contents.push_back({AttributeType::NumericAndText, Attribute, IntValue, std::string(StringValue)}); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/FixupKind/enumFixups.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/FixupKind/enumFixups.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2a8fd50ab479525729e3374df95a2a58f02f2b75 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/FixupKind/enumFixups.cpp @@ -0,0 +1,27 @@ +enum Fixups { + fixup_riscv_hi20 = FirstTargetFixupKind, + fixup_riscv_lo12_i, + fixup_riscv_lo12_s, + fixup_riscv_pcrel_hi20, + fixup_riscv_pcrel_lo12_i, + fixup_riscv_pcrel_lo12_s, + fixup_riscv_got_hi20, + fixup_riscv_tprel_hi20, + fixup_riscv_tprel_lo12_i, + fixup_riscv_tprel_lo12_s, + fixup_riscv_tprel_add, + fixup_riscv_tls_got_hi20, + fixup_riscv_tls_gd_hi20, + fixup_riscv_jal, + fixup_riscv_branch, + fixup_riscv_rvc_jump, + fixup_riscv_rvc_branch, + fixup_riscv_call, + fixup_riscv_call_plt, + fixup_riscv_relax, + fixup_riscv_align, + fixup_pulpv2_loop_setup, + fixup_pulpv2_loop_setupi, + fixup_riscv_invalid, + NumTargetFixupKinds = fixup_riscv_invalid - FirstTargetFixupKind +}; diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/InstPrinter/InstPrinter.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/InstPrinter/InstPrinter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..71d998a21bbc237891bd1af9439f840ba481ed61 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/InstPrinter/InstPrinter.cpp @@ -0,0 +1,2 @@ +RISCVInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI) : MCInstPrinter(MAI, MII, MRI) { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/InstPrinter/applyTargetSpecificCLOption.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/InstPrinter/applyTargetSpecificCLOption.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c74c266403f121f6785e5bab3d396cffccc06305 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/InstPrinter/applyTargetSpecificCLOption.cpp @@ -0,0 +1,11 @@ +bool RISCVInstPrinter::applyTargetSpecificCLOption(StringRef Opt) { + if (Opt == "no-aliases") { + NoAliases = true; + return true; + } + if (Opt == "numeric") { + ArchRegNames = true; + return true; + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/InstPrinter/getRegisterName.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/InstPrinter/getRegisterName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..16127a97a65a5a76c80d613eb8cce8d76e67d59d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/InstPrinter/getRegisterName.cpp @@ -0,0 +1,3 @@ +const char *RISCVInstPrinter::getRegisterName(unsigned RegNo) { + return getRegisterName(RegNo, ArchRegNames ? RISCV::NoRegAltName : RISCV::ABIRegAltName); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/InstPrinter/printAtomicMemOp.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/InstPrinter/printAtomicMemOp.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3d1b3ccb7d8db5f73fbefacc28a689c8057e9ad7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/InstPrinter/printAtomicMemOp.cpp @@ -0,0 +1,7 @@ +void RISCVInstPrinter::printAtomicMemOp(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) { + const MCOperand &MO = MI->getOperand(OpNo); + assert(MO.isReg() && "printAtomicMemOp can only print register operands"); + O << "("; + printRegName(O, MO.getReg()); + O << ")"; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/InstPrinter/printBranchOperand.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/InstPrinter/printBranchOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a01d9b2e56167e27ab420b3b5ab9fd027d317f6f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/InstPrinter/printBranchOperand.cpp @@ -0,0 +1,16 @@ +void RISCVInstPrinter::printBranchOperand(const MCInst *MI, uint64_t Address, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) { + const MCOperand &MO = MI->getOperand(OpNo); + if (!MO.isImm()) { + return printOperand(MI, OpNo, STI, O); + } + if (PrintBranchImmAsAddress) { + uint64_t Target = Address + MO.getImm(); + if (!STI.hasFeature(RISCV::Feature64Bit)) { + Target &= 0xffffffff; + } + O << formatHex(Target); + } + else { + O << MO.getImm(); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/InstPrinter/printCSRSystemRegister.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/InstPrinter/printCSRSystemRegister.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3809af50492b7bd4de8f984928f1c4261af64686 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/InstPrinter/printCSRSystemRegister.cpp @@ -0,0 +1,10 @@ +void RISCVInstPrinter::printCSRSystemRegister(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) { + unsigned Imm = MI->getOperand(OpNo).getImm(); + auto SysReg = RISCVSysReg::lookupSysRegByEncoding(Imm); + if (SysReg && SysReg->haveRequiredFeatures(STI.getFeatureBits())) { + O << SysReg->Name; + } + else { + O << Imm; + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/InstPrinter/printFRMArg.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/InstPrinter/printFRMArg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6c645b1207ba1597386ae8a6d312aeefb5fea718 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/InstPrinter/printFRMArg.cpp @@ -0,0 +1,4 @@ +void RISCVInstPrinter::printFRMArg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) { + auto FRMArg = static_cast(MI->getOperand(OpNo).getImm()); + O << RISCVFPRndMode::roundingModeToString(FRMArg); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/InstPrinter/printFenceArg.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/InstPrinter/printFenceArg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7bb49dab7c797c58c549e93f140553048913667e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/InstPrinter/printFenceArg.cpp @@ -0,0 +1,19 @@ +void RISCVInstPrinter::printFenceArg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) { + unsigned FenceArg = MI->getOperand(OpNo).getImm(); + assert (((FenceArg >> 4) == 0) && "Invalid immediate in printFenceArg"); + if ((FenceArg & RISCVFenceField::I) != 0) { + O << 'i'; + } + if ((FenceArg & RISCVFenceField::O) != 0) { + O << 'o'; + } + if ((FenceArg & RISCVFenceField::R) != 0) { + O << 'r'; + } + if ((FenceArg & RISCVFenceField::W) != 0) { + O << 'w'; + } + if (FenceArg == 0) { + O << "unknown"; + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/InstPrinter/printInst.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/InstPrinter/printInst.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7fd912416d3c956ccf0b4e72deb8cb1e607606ff --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/InstPrinter/printInst.cpp @@ -0,0 +1,22 @@ +void RISCVInstPrinter::printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) { + bool Res = false; + const MCInst *NewMI = MI; + MCInst UncompressedMI; + if (!NoAliases) { + Res = uncompressInst(UncompressedMI, *MI, MRI, STI); + } + if (Res) { + NewMI = const_cast(&UncompressedMI); + } + if (NoAliases) { + printInstruction(NewMI, Address, STI, O); + printAnnotation(O, Annot); + return ; + } + if (!printAliasInstr(NewMI, Address, STI, O)) { + printInstruction(NewMI, Address, STI, O); + printAnnotation(O, Annot); + return ; + } + printAnnotation(O, Annot); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/InstPrinter/printOperand.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/InstPrinter/printOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7d0f0643720af5ad457f257e02853f99c0f67122 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/InstPrinter/printOperand.cpp @@ -0,0 +1,14 @@ +void RISCVInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O, const char *Modifier) { + assert((Modifier == 0 || Modifier[0] == 0) && "No modifiers supported"); + const MCOperand &MO = MI->getOperand(OpNo); + if (MO.isReg()) { + printRegName(O, MO.getReg()); + return; + } + if (MO.isImm()) { + O << MO.getImm(); + return; + } + assert(MO.isExpr() && "Unknown operand kind in printOperand"); + MO.getExpr()->print(O, &MAI); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/InstPrinter/printRegName.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/InstPrinter/printRegName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..44d46a100e8d5b198bbeca69ad0ebf8d85a67127 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/InstPrinter/printRegName.cpp @@ -0,0 +1,3 @@ +void RISCVInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { + OS << getRegisterName(RegNo); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/InstPrinter/printVMaskReg.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/InstPrinter/printVMaskReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0c27e28f489f40b2071578114af59538980a143b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/InstPrinter/printVMaskReg.cpp @@ -0,0 +1,10 @@ +void RISCVInstPrinter::printVMaskReg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) { + const MCOperand &MO = MI->getOperand(OpNo); + assert(MO.isReg() && "printVMaskReg can only print register operands"); + if (MO.getReg() == RISCV::NoRegister) { + return ; + } + O << ", "; + printRegName(O, MO.getReg()); + O << ".t"; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/InstPrinter/printVTypeI.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/InstPrinter/printVTypeI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..182d91094687c23adfa4a02dfafb94b892bd942d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/InstPrinter/printVTypeI.cpp @@ -0,0 +1,34 @@ +void RISCVInstPrinter::printVTypeI(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) { + unsigned Imm = MI->getOperand(OpNo).getImm(); + RISCVVSEW VSEW = getVSEW(VType); + RISCVVLMUL VLMUL = getVLMUL(VType); + unsigned Sew = 1 << (static_cast(VSEW) + 3); + OS << "e" << Sew; + switch (VLMUL) { + case RISCVVLMUL::LMUL_RESERVED: + llvm_unreachable("Unexpected LMUL value!"); + case RISCVVLMUL::LMUL_1: + case RISCVVLMUL::LMUL_2: + case RISCVVLMUL::LMUL_4: + case RISCVVLMUL::LMUL_8: { + unsigned LMul = 1 << static_cast(VLMUL); + OS << ",m" << LMul; + break; + } + case RISCVVLMUL::LMUL_F2: + case RISCVVLMUL::LMUL_F4: + case RISCVVLMUL::LMUL_F8: { + unsigned LMul = 1 << (8 - static_cast(VLMUL)); + OS << ",mf" << LMul; + break; + } + } + if (isTailAgnostic(VType)) + OS << ",ta"; + else + OS << ",tu"; + if (isMaskAgnostic(VType)) + OS << ",ma"; + else + OS << ",mu"; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCCodeEmitter/MCCodeEmitter.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCCodeEmitter/MCCodeEmitter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..79d3f43f91b2f9cb6eacf14c4504d0058646f84e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCCodeEmitter/MCCodeEmitter.cpp @@ -0,0 +1,2 @@ +RISCVMCCodeEmitter(MCContext &ctx, MCInstrInfo const &MCII) : Ctx(ctx), MCII(MCII) { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCCodeEmitter/createMCCodeEmitter.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCCodeEmitter/createMCCodeEmitter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a1af400e24ee65974cc8afec327f0489742cc57d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCCodeEmitter/createMCCodeEmitter.cpp @@ -0,0 +1,3 @@ +MCCodeEmitter *llvm::createRISCVMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx) { + return new RISCVMCCodeEmitter(Ctx, MCII); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCCodeEmitter/encodeInstruction.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCCodeEmitter/encodeInstruction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6fd2c7d7f19b595b6dca627db0e856d5448229d2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCCodeEmitter/encodeInstruction.cpp @@ -0,0 +1,112 @@ +void RISCVMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const { + verifyInstructionPredicates(MI, computeAvailableFeatures(STI.getFeatureBits())); + const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); + unsigned Size = Desc.getSize(); + if (MI.getOpcode() == RISCV::PseudoCALLReg) { + MCInst TmpInst; + MCOperand Func; + MCRegister Ra; + uint32_t Binary; + Func = MI.getOperand(1); + Ra = MI.getOperand(0).getReg(); + assert(Func.isExpr() && "Expected expression"); + const MCExpr *CallExpr = Func.getExpr(); + TmpInst = MCInstBuilder(RISCV::AUIPC).addReg(Ra).addOperand(MCOperand::createExpr(CallExpr)); + Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); + support::endian::write(OS, Binary, support::little); + TmpInst = MCInstBuilder(RISCV::JALR).addReg(Ra).addReg(Ra).addImm(0); + Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); + support::endian::write(OS, Binary, support::little); + MCNumEmitted = MCNumEmitted + 2; + return ; + } + if(MI.getOpcode() == RISCV::PseudoCALL) { + MCInst TmpInst; + MCOperand Func; + MCRegister Ra; + uint32_t Binary; + Func = MI.getOperand(1); + Ra = MI.getOperand(0).getReg(); + assert(Func.isExpr() && "Expected expression"); + const MCExpr *CallExpr = Func.getExpr(); + TmpInst = MCInstBuilder(RISCV::AUIPC).addReg(Ra).addOperand(MCOperand::createExpr(CallExpr)); + Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); + support::endian::write(OS, Binary, support::little); + TmpInst = MCInstBuilder(RISCV::JALR).addReg(Ra).addReg(Ra).addImm(0); + Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); + support::endian::write(OS, Binary, support::little); + MCNumEmitted = MCNumEmitted + 2; + return ; + } + if(MI.getOpcode() == RISCV::PseudoTAIL) { + MCInst TmpInst; + MCOperand Func; + MCRegister Ra; + uint32_t Binary; + Func = MI.getOperand(1); + Ra = MI.getOperand(0).getReg(); + assert(Func.isExpr() && "Expected expression"); + const MCExpr *CallExpr = Func.getExpr(); + TmpInst = MCInstBuilder(RISCV::AUIPC).addReg(Ra).addOperand(MCOperand::createExpr(CallExpr)); + Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); + support::endian::write(OS, Binary, support::little); + TmpInst = MCInstBuilder(RISCV::JALR).addReg(Ra).addReg(Ra).addImm(0); + Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); + support::endian::write(OS, Binary, support::little); + MCNumEmitted = MCNumEmitted + 2; + return ; + } + if(MI.getOpcode() == RISCV::PseudoJump) { + MCInst TmpInst; + MCOperand Func; + MCRegister Ra; + uint32_t Binary; + Func = MI.getOperand(1); + Ra = MI.getOperand(0).getReg(); + assert(Func.isExpr() && "Expected expression"); + const MCExpr *CallExpr = Func.getExpr(); + TmpInst = MCInstBuilder(RISCV::AUIPC).addReg(Ra).addOperand(MCOperand::createExpr(CallExpr)); + Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); + support::endian::write(OS, Binary, support::little); + TmpInst = MCInstBuilder(RISCV::JALR).addReg(Ra).addReg(Ra).addImm(0); + Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); + support::endian::write(OS, Binary, support::little); + MCNumEmitted = MCNumEmitted + 2; + return ; + } + if (MI.getOpcode() == RISCV::PseudoAddTPRel) { + MCOperand DestReg = MI.getOperand(0); + MCOperand SrcReg = MI.getOperand(1); + MCOperand TPReg = MI.getOperand(2); + assert(TPReg.isReg() && TPReg.getReg() == RISCV::X4 && "Expected thread pointer as second input to TP-relative add"); + MCOperand SrcSymbol = MI.getOperand(3); + assert(SrcSymbol.isExpr() && "Expected expression as third input to TP-relative add"); + const RISCVMCExpr *Expr = dyn_cast(SrcSymbol.getExpr()); + assert(Expr && Expr->getKind() == RISCVMCExpr::VK_RISCV_TPREL_ADD && "Expected tprel_add relocation on TP-relative symbol"); + Fixups.push_back(MCFixup::create(0, Expr, MCFixupKind(RISCV::fixup_riscv_tprel_add), MI.getLoc())); + if (STI.getFeatureBits()[RISCV::FeatureRelax]) { + const MCConstantExpr *Dummy = MCConstantExpr::create(0, Ctx); + Fixups.push_back(MCFixup::create(0, Dummy, MCFixupKind(RISCV::fixup_riscv_relax), MI.getLoc())); + } + MCInst TmpInst = MCInstBuilder(RISCV::ADD).addOperand(DestReg).addOperand(SrcReg).addOperand(TPReg); + uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); + support::endian::write(OS, Binary, support::little); + MCNumEmitted += 1; + return; + } + if (Size == 2) { + uint16_t Bits; + Bits = getBinaryCodeForInstr(MI, Fixups, STI); + support::endian::write(OS, Bits,support::little); + MCNumEmitted = MCNumEmitted + 1; + return ; + } + if (Size == 4) { + uint32_t Bits; + Bits = getBinaryCodeForInstr(MI, Fixups, STI); + support::endian::write(OS, Bits,support::little); + MCNumEmitted = MCNumEmitted + 1; + return ; + } + ++MCNumEmitted; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCCodeEmitter/getImmOpValue.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCCodeEmitter/getImmOpValue.cpp new file mode 100644 index 0000000000000000000000000000000000000000..17b6c231cb7ae743d9900d60f15bb39649137428 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCCodeEmitter/getImmOpValue.cpp @@ -0,0 +1,104 @@ +unsigned RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const { + bool EnableRelax = STI.getFeatureBits()[RISCV::FeatureRelax]; + const MCOperand &MO = MI.getOperand(OpNo); + MCInstrDesc const &Desc = MCII.get(MI.getOpcode()); + unsigned MIFrm = Desc.TSFlags & RISCVII::InstFormatMask; + if (MO.isImm()) { + return MO.getImm(); + } + assert(MO.isExpr() && "getImmOpValue expects only expressions or immediates"); + const MCExpr *Expr = MO.getExpr(); + MCExpr::ExprKind Kind = Expr->getKind(); + RISCV::Fixups FixupKind = RISCV::fixup_riscv_invalid; + bool RelaxCandidate = false; + if (Kind == MCExpr::Target) { + const RISCVMCExpr *RVExpr = cast(Expr); + switch (RVExpr->getKind()) { + case RISCVMCExpr::VK_RISCV_None: + case RISCVMCExpr::VK_RISCV_Invalid: + case RISCVMCExpr::VK_RISCV_32_PCREL: + llvm_unreachable("Unhandled fixup kind!"); + case RISCVMCExpr::VK_RISCV_TPREL_ADD: + llvm_unreachable("VK_RISCV_TPREL_ADD should not represent an instruction operand"); + case RISCVMCExpr::VK_RISCV_LO: + if (MIFrm == RISCVII::InstFormatI) + FixupKind = RISCV::fixup_riscv_lo12_i; + else if (MIFrm == RISCVII::InstFormatS) + FixupKind = RISCV::fixup_riscv_lo12_s; + else + llvm_unreachable("VK_RISCV_LO used with unexpected instruction format"); + RelaxCandidate = true; + break; + case RISCVMCExpr::VK_RISCV_HI: + FixupKind = RISCV::fixup_riscv_hi20; + RelaxCandidate = true; + break; + case RISCVMCExpr::VK_RISCV_PCREL_LO: + if (MIFrm == RISCVII::InstFormatI) + FixupKind = RISCV::fixup_riscv_pcrel_lo12_i; + else if (MIFrm == RISCVII::InstFormatS) + FixupKind = RISCV::fixup_riscv_pcrel_lo12_s; + else + llvm_unreachable("VK_RISCV_PCREL_LO used with unexpected instruction format"); + RelaxCandidate = true; + break; + case RISCVMCExpr::VK_RISCV_PCREL_HI: + FixupKind = RISCV::fixup_riscv_pcrel_hi20; + RelaxCandidate = true; + break; + case RISCVMCExpr::VK_RISCV_GOT_HI: + FixupKind = RISCV::fixup_riscv_got_hi20; + break; + case RISCVMCExpr::VK_RISCV_TPREL_LO: + if (MIFrm == RISCVII::InstFormatI) + FixupKind = RISCV::fixup_riscv_tprel_lo12_i; + else if (MIFrm == RISCVII::InstFormatS) + FixupKind = RISCV::fixup_riscv_tprel_lo12_s; + else + llvm_unreachable("VK_RISCV_TPREL_LO used with unexpected instruction format"); + RelaxCandidate = true; + break; + case RISCVMCExpr::VK_RISCV_TPREL_HI: + FixupKind = RISCV::fixup_riscv_tprel_hi20; + RelaxCandidate = true; + break; + case RISCVMCExpr::VK_RISCV_TLS_GOT_HI: + FixupKind = RISCV::fixup_riscv_tls_got_hi20; + break; + case RISCVMCExpr::VK_RISCV_TLS_GD_HI: + FixupKind = RISCV::fixup_riscv_tls_gd_hi20; + break; + case RISCVMCExpr::VK_RISCV_CALL: + FixupKind = RISCV::fixup_riscv_call; + RelaxCandidate = true; + break; + case RISCVMCExpr::VK_RISCV_CALL_PLT: + FixupKind = RISCV::fixup_riscv_call_plt; + RelaxCandidate = true; + break; + } + } + else if (Kind == MCExpr::SymbolRef && cast(Expr)->getKind() == MCSymbolRefExpr::VK_None) { + if (Desc.getOpcode() == RISCV::JAL) { + FixupKind = RISCV::fixup_riscv_jal; + } + else if (MIFrm == RISCVII::InstFormatB) { + FixupKind = RISCV::fixup_riscv_branch; + } + else if (MIFrm == RISCVII::InstFormatCJ) { + FixupKind = RISCV::fixup_riscv_rvc_jump; + } + else if (MIFrm == RISCVII::InstFormatCB) { + FixupKind = RISCV::fixup_riscv_rvc_branch; + } + } + assert(FixupKind != RISCV::fixup_riscv_invalid && "Unhandled expression!"); + Fixups.push_back(MCFixup::create(0, Expr, MCFixupKind(FixupKind), MI.getLoc())); + ++MCNumFixups; + if (EnableRelax && RelaxCandidate) { + const MCConstantExpr *Dummy = MCConstantExpr::create(0, Ctx); + Fixups.push_back(MCFixup::create(0, Dummy, MCFixupKind(RISCV::fixup_riscv_relax), MI.getLoc())); + ++MCNumFixups; + } + return 0; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCCodeEmitter/getImmOpValueAsr1.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCCodeEmitter/getImmOpValueAsr1.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0608bfeacb78631d4bd74acd7635d1eddcd1e943 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCCodeEmitter/getImmOpValueAsr1.cpp @@ -0,0 +1,9 @@ +unsigned RISCVMCCodeEmitter::getImmOpValueAsr1(const MCInst &MI, unsigned OpNo, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const { + const MCOperand &MO = MI.getOperand(OpNo); + if (MO.isImm()) { + unsigned Res = MO.getImm(); + assert((Res & 1) == 0 && "LSB is non-zero"); + return Res >> 1; + } + return getImmOpValue(MI, OpNo, Fixups, STI); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCCodeEmitter/getImmOpValueMinus1.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCCodeEmitter/getImmOpValueMinus1.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e2d6e76be7a6d84b4d4ed0441e831ac55aeef8b4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCCodeEmitter/getImmOpValueMinus1.cpp @@ -0,0 +1,9 @@ +unsigned RISCVMCCodeEmitter::getImmOpValueMinus1(const MCInst &MI, unsigned OpNo, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const { + const MCOperand &MO = MI.getOperand(OpNo); + if (MO.isImm()) { + unsigned Res = MO.getImm(); + assert((Res & 1) == 0 && "LSB is non-zero"); + return Res >> 1; + } + return getImmOpValue(MI, OpNo, Fixups, STI); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCCodeEmitter/getMachineOpValue.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCCodeEmitter/getMachineOpValue.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a40f05071c26ff021d38728e7ba22287d395082f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCCodeEmitter/getMachineOpValue.cpp @@ -0,0 +1,44 @@ +unsigned RISCVMCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const { + if (MO.isReg()) { + return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()); + } + if (MO.isImm()) { + return static_cast(MO.getImm()); + } + if (MO.isExpr()) { + if (MI.getOpcode() == RISCV::LOOP0setup) { + Fixups.push_back(MCFixup::create(0, MO.getExpr(), MCFixupKind(RISCV::fixup_pulpv2_loop_setup), MI.getLoc())); + } + if (MI.getOpcode() == RISCV::LOOP1setup) { + Fixups.push_back(MCFixup::create(0, MO.getExpr(), MCFixupKind(RISCV::fixup_pulpv2_loop_setup), MI.getLoc())); + } + if (MI.getOpcode() == RISCV::LOOP0setupi) { + Fixups.push_back(MCFixup::create(0, MO.getExpr(), MCFixupKind(RISCV::fixup_pulpv2_loop_setupi), MI.getLoc())); + } + if (MI.getOpcode() == RISCV::LOOP1setupi) { + Fixups.push_back(MCFixup::create(0, MO.getExpr(), MCFixupKind(RISCV::fixup_pulpv2_loop_setupi), MI.getLoc())); + } + if (MI.getOpcode() == RISCV::LOOP0starti) { + Fixups.push_back(MCFixup::create(0, MO.getExpr(), MCFixupKind(RISCV::fixup_pulpv2_loop_setup), MI.getLoc())); + } + if (MI.getOpcode() == RISCV::LOOP1starti) { + Fixups.push_back(MCFixup::create(0, MO.getExpr(), MCFixupKind(RISCV::fixup_pulpv2_loop_setup), MI.getLoc())); + } + if (MI.getOpcode() == RISCV::LOOP0endi) { + Fixups.push_back(MCFixup::create(0, MO.getExpr(), MCFixupKind(RISCV::fixup_pulpv2_loop_setup), MI.getLoc())); + } + if (MI.getOpcode() == RISCV::LOOP1endi) { + Fixups.push_back(MCFixup::create(0, MO.getExpr(), MCFixupKind(RISCV::fixup_pulpv2_loop_setup), MI.getLoc())); + } + if (MI.getOpcode() == RISCV::LOOP0counti) { + Fixups.push_back(MCFixup::create(0, MO.getExpr(), MCFixupKind(RISCV::fixup_pulpv2_loop_setup), MI.getLoc())); + } + if (MI.getOpcode() == RISCV::LOOP1counti) { + Fixups.push_back(MCFixup::create(0, MO.getExpr(), MCFixupKind(RISCV::fixup_pulpv2_loop_setup), MI.getLoc())); + } + MCNumFixups = MCNumFixups + 1; + return 0; + } + llvm_unreachable("Unhandled expression!"); + return 0; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCCodeEmitter/getVMaskReg.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCCodeEmitter/getVMaskReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cb6c71839d4ba3ae26572009f586539be7e0d390 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCCodeEmitter/getVMaskReg.cpp @@ -0,0 +1,12 @@ +unsigned RISCVMCCodeEmitter::getVMaskReg(const MCInst &MI, unsigned OpNo, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const { + MCOperand MO = MI.getOperand(OpNo); + assert(MO.isReg() && "Expected a register."); + switch (MO.getReg()) { + case RISCV::V0: + return 0; + case RISCV::NoRegister: + return 1; + default: + llvm_unreachable("Invalid mask register."); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCCodeEmitter/~MCCodeEmitter.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCCodeEmitter/~MCCodeEmitter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..59ae51d078977c3022b0a7003a3a5b6cc6cfccd0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCCodeEmitter/~MCCodeEmitter.cpp @@ -0,0 +1,2 @@ +~RISCVMCCodeEmitter() override { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCExpr/MCExpr.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCExpr/MCExpr.cpp new file mode 100644 index 0000000000000000000000000000000000000000..da4f6b8260348d1f5ae72c777c76f77b19b1c56b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCExpr/MCExpr.cpp @@ -0,0 +1,2 @@ +explicit RISCVMCExpr(const MCExpr *Expr, VariantKind Kind) : Expr(Expr), Kind(Kind) { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCExpr/classof1.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCExpr/classof1.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c18a16e9b79dfbe76cb62202c2b20dac602f027b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCExpr/classof1.cpp @@ -0,0 +1,3 @@ +static bool classof(const MCExpr *E) { + return E->getKind() == MCExpr::Target; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCExpr/classof2.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCExpr/classof2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e3b49b8ebace06424f104635e86ad479c4c2d122 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCExpr/classof2.cpp @@ -0,0 +1,3 @@ +static bool classof(const RISCVMCExpr *) { + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCExpr/create.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCExpr/create.cpp new file mode 100644 index 0000000000000000000000000000000000000000..39113cf36ed270b0c6d69b5360588428237b2475 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCExpr/create.cpp @@ -0,0 +1,3 @@ +const RISCVMCExpr *RISCVMCExpr::create(const MCExpr *Expr, VariantKind Kind, MCContext &Ctx) { + return new (Ctx) RISCVMCExpr(Expr, Kind); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCExpr/enumVariantKind.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCExpr/enumVariantKind.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9d3ea350c3d62324aeaad87cabbbfd85c3ea4588 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCExpr/enumVariantKind.cpp @@ -0,0 +1,17 @@ +enum VariantKind { + VK_RISCV_None, + VK_RISCV_LO, + VK_RISCV_HI, + VK_RISCV_PCREL_LO, + VK_RISCV_PCREL_HI, + VK_RISCV_GOT_HI, + VK_RISCV_TPREL_LO, + VK_RISCV_TPREL_HI, + VK_RISCV_TPREL_ADD, + VK_RISCV_TLS_GOT_HI, + VK_RISCV_TLS_GD_HI, + VK_RISCV_CALL, + VK_RISCV_CALL_PLT, + VK_RISCV_32_PCREL, + VK_RISCV_Invalid, + }; diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCExpr/evaluateAsConstant.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCExpr/evaluateAsConstant.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8a00985bb9a0e45063ef40c9356a6d51ba318393 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCExpr/evaluateAsConstant.cpp @@ -0,0 +1,14 @@ +bool RISCVMCExpr::evaluateAsConstant(int64_t &Res) const { + MCValue Value; + if (Kind == VK_RISCV_PCREL_HI || Kind == VK_RISCV_PCREL_LO || Kind == VK_RISCV_GOT_HI || Kind == VK_RISCV_TPREL_HI || Kind == VK_RISCV_TPREL_LO || Kind == VK_RISCV_TPREL_ADD || Kind == VK_RISCV_TLS_GOT_HI || Kind == VK_RISCV_TLS_GD_HI || Kind == VK_RISCV_CALL || Kind == VK_RISCV_CALL_PLT) { + return false; + } + if (!getSubExpr()->evaluateAsRelocatable(Value, nullptr, nullptr)) { + return false; + } + if (!Value.isAbsolute()) { + return false; + } + Res = evaluateAsInt64(Value.getConstant()); + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCExpr/evaluateAsInt64.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCExpr/evaluateAsInt64.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2d2ca349a0e1f92adb5fcbf38353c231ec73066f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCExpr/evaluateAsInt64.cpp @@ -0,0 +1,10 @@ +int64_t RISCVMCExpr::evaluateAsInt64(int64_t Value) const { + switch (Kind) { + case VK_RISCV_LO: + return SignExtend64<12>(Value); + case VK_RISCV_HI: + return ((Value + 0x800) >> 12) & 0xfffff; + default: + llvm_unreachable("Invalid kind"); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCExpr/evaluateAsRelocatableImpl.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCExpr/evaluateAsRelocatableImpl.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6e71bde5f7592f5ef4591791bcb86f58dc40765f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCExpr/evaluateAsRelocatableImpl.cpp @@ -0,0 +1,23 @@ +bool RISCVMCExpr::evaluateAsRelocatableImpl(MCValue &Res, const MCAsmLayout *Layout, const MCFixup *Fixup) const { + if (!getSubExpr()->evaluateAsRelocatable(Res, Layout, Fixup)){ + return false; + } + if (Res.getSymA() && Res.getSymB()) { + switch (getKind()) { + default: + return true; + case VK_RISCV_LO: + case VK_RISCV_HI: + case VK_RISCV_PCREL_LO: + case VK_RISCV_PCREL_HI: + case VK_RISCV_GOT_HI: + case VK_RISCV_TPREL_LO: + case VK_RISCV_TPREL_HI: + case VK_RISCV_TPREL_ADD: + case VK_RISCV_TLS_GOT_HI: + case VK_RISCV_TLS_GD_HI: + return false; + } + } + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCExpr/findAssociatedFragment.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCExpr/findAssociatedFragment.cpp new file mode 100644 index 0000000000000000000000000000000000000000..60f17e85d923bec938d38573f38737261c999694 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCExpr/findAssociatedFragment.cpp @@ -0,0 +1,3 @@ +MCFragment *findAssociatedFragment() const override { + return getSubExpr()->findAssociatedFragment(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCExpr/fixELFSymbolsInTLSFixups.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCExpr/fixELFSymbolsInTLSFixups.cpp new file mode 100644 index 0000000000000000000000000000000000000000..89e8ce3b031ea65a056d84127e579bd2815264c2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCExpr/fixELFSymbolsInTLSFixups.cpp @@ -0,0 +1,11 @@ +void RISCVMCExpr::fixELFSymbolsInTLSFixups(MCAssembler &Asm) const { + switch (getKind()) { + default: + return; + case VK_RISCV_TPREL_HI: + case VK_RISCV_TLS_GOT_HI: + case VK_RISCV_TLS_GD_HI: + break; + } + fixELFSymbolsInTLSFixupsImpl(getSubExpr(), Asm); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCExpr/fixELFSymbolsInTLSFixupsImpl.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCExpr/fixELFSymbolsInTLSFixupsImpl.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9380184f705c3b8053f961d7f265d676d373e6c4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCExpr/fixELFSymbolsInTLSFixupsImpl.cpp @@ -0,0 +1,23 @@ +static void fixELFSymbolsInTLSFixupsImpl(const MCExpr *Expr, MCAssembler &Asm) { + switch (Expr->getKind()) { + case MCExpr::Target: + llvm_unreachable("Can't handle nested target expression"); + break; + case MCExpr::Constant: + break; + case MCExpr::Binary: { + const MCBinaryExpr *BE = cast(Expr); + fixELFSymbolsInTLSFixupsImpl(BE->getLHS(), Asm); + fixELFSymbolsInTLSFixupsImpl(BE->getRHS(), Asm); + break; + } + case MCExpr::SymbolRef: { + const MCSymbolRefExpr &SymRef = *cast(Expr); + cast(SymRef.getSymbol()).setType(ELF::STT_TLS); + break; + } + case MCExpr::Unary: + fixELFSymbolsInTLSFixupsImpl(cast(Expr)->getSubExpr(), Asm); + break; + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCExpr/getKind.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCExpr/getKind.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d8873d03d56532262e2e464651e7ed13ac5736a6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCExpr/getKind.cpp @@ -0,0 +1,3 @@ +VariantKind getKind() const { + return Kind; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCExpr/getPCRelHiFixup.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCExpr/getPCRelHiFixup.cpp new file mode 100644 index 0000000000000000000000000000000000000000..89987b297a722bf3d6b3be128c1836a8216b5cb9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCExpr/getPCRelHiFixup.cpp @@ -0,0 +1,41 @@ +const MCFixup *RISCVMCExpr::getPCRelHiFixup(const MCFragment **DFOut) const { + MCValue AUIPCLoc; + if (!getSubExpr()->evaluateAsRelocatable(AUIPCLoc, nullptr, nullptr)) { + return nullptr; + } + const MCSymbolRefExpr *AUIPCSRE = AUIPCLoc.getSymA(); + if (!AUIPCSRE) { + return nullptr; + } + const MCSymbol *AUIPCSymbol = &AUIPCSRE->getSymbol(); + const auto *DF = dyn_cast_or_null(AUIPCSymbol->getFragment()); + if (!DF) { + return nullptr; + } + uint64_t Offset = AUIPCSymbol->getOffset(); + if (DF->getContents().size() == Offset) { + DF = dyn_cast_or_null(DF->getNextNode()); + if (!DF) { + return nullptr; + } + Offset = 0; + } + for (const MCFixup &F : DF->getFixups()) { + if (F.getOffset() != Offset) { + continue; + } + switch ((unsigned)F.getKind()) { + default: + continue; + case RISCV::fixup_riscv_got_hi20: + case RISCV::fixup_riscv_tls_got_hi20: + case RISCV::fixup_riscv_tls_gd_hi20: + case RISCV::fixup_riscv_pcrel_hi20: + if (DFOut) { + *DFOut = DF; + } + return &F; + } + } + return nullptr; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCExpr/getSubExpr.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCExpr/getSubExpr.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0938efd3638913ba4ab06b155113748fbcf3ba7b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCExpr/getSubExpr.cpp @@ -0,0 +1,3 @@ +const MCExpr *getSubExpr() const { + return Expr; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCExpr/getVariantKindForName.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCExpr/getVariantKindForName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3ceea7690a66c81e8392c3762eeb6bdc159adfb2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCExpr/getVariantKindForName.cpp @@ -0,0 +1,33 @@ +RISCVMCExpr::VariantKind RISCVMCExpr::getVariantKindForName(StringRef name) { + if (name == "lo") { + return RISCVMCExpr::VK_RISCV_LO; + } + if (name == "hi") { + return RISCVMCExpr::VK_RISCV_HI; + } + if (name == "pcrel_lo") { + return RISCVMCExpr::VK_RISCV_PCREL_LO; + } + if (name == "pcrel_hi") { + return RISCVMCExpr::VK_RISCV_PCREL_HI; + } + if (name == "got_pcrel_hi") { + return RISCVMCExpr::VK_RISCV_GOT_HI; + } + if (name == "tprel_lo") { + return RISCVMCExpr::VK_RISCV_TPREL_LO; + } + if (name == "tprel_hi") { + return RISCVMCExpr::VK_RISCV_TPREL_HI; + } + if (name == "tprel_add") { + return RISCVMCExpr::VK_RISCV_TPREL_ADD; + } + if (name == "tls_ie_pcrel_hi") { + return RISCVMCExpr::VK_RISCV_TLS_GOT_HI; + } + if (name == "tls_gd_pcrel_hi") { + return RISCVMCExpr::VK_RISCV_TLS_GD_HI; + } + return RISCVMCExpr::VK_RISCV_Invalid; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCExpr/getVariantKindName.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCExpr/getVariantKindName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9a08480b3ccbf2b76c97f73a0b86881ba90264eb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCExpr/getVariantKindName.cpp @@ -0,0 +1,26 @@ +StringRef RISCVMCExpr::getVariantKindName(VariantKind Kind) { + switch (Kind) { + case VK_RISCV_LO: + return "lo"; + case VK_RISCV_HI: + return "hi"; + case VK_RISCV_PCREL_LO: + return "pcrel_lo"; + case VK_RISCV_PCREL_HI: + return "pcrel_hi"; + case VK_RISCV_GOT_HI: + return "got_pcrel_hi"; + case VK_RISCV_TPREL_LO: + return "tprel_lo"; + case VK_RISCV_TPREL_HI: + return "tprel_hi"; + case VK_RISCV_TPREL_ADD: + return "tprel_add"; + case VK_RISCV_TLS_GOT_HI: + return "tls_ie_pcrel_hi"; + case VK_RISCV_TLS_GD_HI: + return "tls_gd_pcrel_hi"; + default: + llvm_unreachable("Invalid ELF symbol kind"); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCExpr/printImpl.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCExpr/printImpl.cpp new file mode 100644 index 0000000000000000000000000000000000000000..55d93d4d19a85acb53eace95c71cbd1dc389bcca --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCExpr/printImpl.cpp @@ -0,0 +1,82 @@ +void RISCVMCExpr::printImpl(raw_ostream &OS, const MCAsmInfo *MAI) const { + VariantKind Kind = getKind(); + if (Kind == RISCVMCExpr::VK_RISCV_PCREL_LO) { + OS << "%pcrel_lo("; + Expr->print(OS, MAI); + OS << ")"; + return ; + } + if (Kind == RISCVMCExpr::VK_RISCV_PCREL_HI) { + OS << "%pcrel_hi("; + Expr->print(OS, MAI); + OS << ")"; + return ; + } + if (Kind == RISCVMCExpr::VK_RISCV_TPREL_LO) { + OS << "%tprel_lo("; + Expr->print(OS, MAI); + OS << ")"; + return ; + } + if (Kind == RISCVMCExpr::VK_RISCV_TPREL_HI) { + OS << "%tprel_hi("; + Expr->print(OS, MAI); + OS << ")"; + return ; + } + if (Kind == RISCVMCExpr::VK_RISCV_TPREL_ADD) { + OS << "%tprel_add("; + Expr->print(OS, MAI); + OS << ")"; + return ; + } + if (Kind == RISCVMCExpr::VK_RISCV_LO) { + OS << "%lo("; + Expr->print(OS, MAI); + OS << ")"; + return ; + } + if (Kind == RISCVMCExpr::VK_RISCV_HI) { + OS << "%hi("; + Expr->print(OS, MAI); + OS << ")"; + return ; + } + if (Kind == RISCVMCExpr::VK_RISCV_GOT_HI) { + OS << "%got_pcrel_hi("; + Expr->print(OS, MAI); + OS << ")"; + return ; + } + if (Kind == RISCVMCExpr::VK_RISCV_TLS_GOT_HI) { + OS << "%tls_ie_pcrel_hi("; + Expr->print(OS, MAI); + OS << ")"; + return ; + } + if (Kind == RISCVMCExpr::VK_RISCV_TLS_GD_HI) { + OS << "%tls_gd_pcrel_hi("; + Expr->print(OS, MAI); + OS << ")"; + return ; + } + if (Kind == RISCVMCExpr::VK_RISCV_CALL_PLT) { + OS << ""; + Expr->print(OS, MAI); + OS << "@plt"; + return ; + } + if (Kind == RISCVMCExpr::VK_RISCV_CALL) { + OS << ""; + Expr->print(OS, MAI); + OS << ""; + return ; + } + if (Kind == RISCVMCExpr::VK_RISCV_None) { + OS << ""; + Expr->print(OS, MAI); + OS << ""; + return ; + } + llvm_unreachable("Invalid ELF symbol kind"); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCExpr/visitUsedExpr.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCExpr/visitUsedExpr.cpp new file mode 100644 index 0000000000000000000000000000000000000000..35e420112aded4140f320dbc4ad4ac870d3ee31a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCExpr/visitUsedExpr.cpp @@ -0,0 +1,3 @@ +void RISCVMCExpr::visitUsedExpr(MCStreamer &Streamer) const { + Streamer.visitUsedExpr(*getSubExpr()); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCTargetDesc/InstrAnalysis.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCTargetDesc/InstrAnalysis.cpp new file mode 100644 index 0000000000000000000000000000000000000000..451277e94556a0608d71ebc2c76e620e59e0ec99 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCTargetDesc/InstrAnalysis.cpp @@ -0,0 +1,2 @@ +explicit RISCVMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCTargetDesc/LLVMInitializeTargetMC.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCTargetDesc/LLVMInitializeTargetMC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..32d2fe18d6bb48ee672756467a7ed995da2ae810 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCTargetDesc/LLVMInitializeTargetMC.cpp @@ -0,0 +1,15 @@ +extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTargetMC() { + for (Target *T : {&getTheRISCV32Target(), &getTheRISCV64Target()}) { + TargetRegistry::RegisterMCAsmInfo(*T, createRISCVMCAsmInfo); + TargetRegistry::RegisterMCInstrInfo(*T, createRISCVMCInstrInfo); + TargetRegistry::RegisterMCRegInfo(*T, createRISCVMCRegisterInfo); + TargetRegistry::RegisterMCAsmBackend(*T, createRISCVAsmBackend); + TargetRegistry::RegisterMCCodeEmitter(*T, createRISCVMCCodeEmitter); + TargetRegistry::RegisterMCInstPrinter(*T, createRISCVMCInstPrinter); + TargetRegistry::RegisterMCSubtargetInfo(*T, createRISCVMCSubtargetInfo); + TargetRegistry::RegisterObjectTargetStreamer(*T, createRISCVObjectTargetStreamer); + TargetRegistry::RegisterMCInstrAnalysis(*T, createRISCVInstrAnalysis); + TargetRegistry::RegisterAsmTargetStreamer(*T, createRISCVAsmTargetStreamer); + TargetRegistry::RegisterNullTargetStreamer(*T, createRISCVNullTargetStreamer); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCTargetDesc/createAsmTargetStreamer.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCTargetDesc/createAsmTargetStreamer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..383b52ff72a10ac127ceb76173b77049aa5f0fd9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCTargetDesc/createAsmTargetStreamer.cpp @@ -0,0 +1,3 @@ +static MCTargetStreamer *createRISCVAsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint, bool isVerboseAsm) { + return new RISCVTargetAsmStreamer(S, OS); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCTargetDesc/createInstrAnalysis.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCTargetDesc/createInstrAnalysis.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5b45661b6fa3382d3f641c2fe3bb34f05970d975 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCTargetDesc/createInstrAnalysis.cpp @@ -0,0 +1,3 @@ +static MCInstrAnalysis *createRISCVInstrAnalysis(const MCInstrInfo *Info) { + return new RISCVMCInstrAnalysis(Info); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCTargetDesc/createMCAsmInfo.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCTargetDesc/createMCAsmInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c4cffda02c27994572bf42f788d40d04d2e73e7d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCTargetDesc/createMCAsmInfo.cpp @@ -0,0 +1,7 @@ +static MCAsmInfo *createRISCVMCAsmInfo(const MCRegisterInfo &MRI, const Triple &TT, const MCTargetOptions &Options) { + MCAsmInfo *MAI = new RISCVMCAsmInfo(TT); + MCRegister SP = MRI.getDwarfRegNum(RISCV::X2, true); + MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, SP, 0); + MAI->addInitialFrameState(Inst); + return MAI; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCTargetDesc/createMCInstPrinter.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCTargetDesc/createMCInstPrinter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7a6f660619bed0d38c739e2e0da3274e6d81b2a0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCTargetDesc/createMCInstPrinter.cpp @@ -0,0 +1,3 @@ +static MCInstPrinter *createRISCVMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI) { + return new RISCVInstPrinter(MAI, MII, MRI); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCTargetDesc/createMCInstrInfo.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCTargetDesc/createMCInstrInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..758df40aa015a0c161f506e8e7ea1cad2d8bcc8a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCTargetDesc/createMCInstrInfo.cpp @@ -0,0 +1,5 @@ +static MCInstrInfo *createRISCVMCInstrInfo() { + MCInstrInfo *X = new MCInstrInfo(); + InitRISCVMCInstrInfo(X); + return X; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCTargetDesc/createMCRegisterInfo.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCTargetDesc/createMCRegisterInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bb7c34dd1c8354b6b0fa67e4f7244d55c1ddc0f7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCTargetDesc/createMCRegisterInfo.cpp @@ -0,0 +1,5 @@ +static MCRegisterInfo *createRISCVMCRegisterInfo(const Triple &TT) { + MCRegisterInfo *X = new MCRegisterInfo(); + InitRISCVMCRegisterInfo(X, RISCV::X1); + return X; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCTargetDesc/createMCSubtargetInfo.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCTargetDesc/createMCSubtargetInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..78ee741005540e6c3e698640daefd523ceecfb94 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCTargetDesc/createMCSubtargetInfo.cpp @@ -0,0 +1,7 @@ +static MCSubtargetInfo *createRISCVMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { + std::string CPUName = std::string(CPU); + if (CPUName.empty()) { + CPUName = TT.isArch64Bit() ? "generic-rv64" : "generic-rv32"; + } + return createRISCVMCSubtargetInfoImpl(TT, CPUName, CPUName, FS); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCTargetDesc/createNullTargetStreamer.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCTargetDesc/createNullTargetStreamer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1a625f2d3b010f64ddbcf02b017f0f07c7f52e3a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCTargetDesc/createNullTargetStreamer.cpp @@ -0,0 +1,3 @@ +static MCTargetStreamer *createRISCVNullTargetStreamer(MCStreamer &S) { + return new RISCVTargetStreamer(S); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCTargetDesc/createObjectTargetStreamer.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCTargetDesc/createObjectTargetStreamer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1e4eba726c087cde28f6692f50ef5398beba9c98 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCTargetDesc/createObjectTargetStreamer.cpp @@ -0,0 +1,7 @@ +static MCTargetStreamer *createRISCVObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) { + const Triple &TT = STI.getTargetTriple(); + if (TT.isOSBinFormatELF()) { + return new RISCVTargetELFStreamer(S, STI); + } + return new RISCVTargetELFStreamer(S, STI); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCTargetDesc/evaluateBranch.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCTargetDesc/evaluateBranch.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1d30e225f0f4ef2635c256d52524ad347fc5927d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MCTargetDesc/evaluateBranch.cpp @@ -0,0 +1,55 @@ +bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size, uint64_t &Target) const { + if (Inst.getOpcode() == RISCV::BEQ) { + Target = Addr + Inst.getOperand(2).getImm(); + return true; + } + if (Inst.getOpcode() == RISCV::BNE) { + Target = Addr + Inst.getOperand(2).getImm(); + return true; + } + if (Inst.getOpcode() == RISCV::BLT) { + Target = Addr + Inst.getOperand(2).getImm(); + return true; + } + if (Inst.getOpcode() == RISCV::BGE) { + Target = Addr + Inst.getOperand(2).getImm(); + return true; + } + if (Inst.getOpcode() == RISCV::BLTU) { + Target = Addr + Inst.getOperand(2).getImm(); + return true; + } + if (Inst.getOpcode() == RISCV::BGEU) { + Target = Addr + Inst.getOperand(2).getImm(); + return true; + } + if (Inst.getOpcode() == RISCV::C_BEQZ) { + Target = Addr + Inst.getOperand(1).getImm(); + return true; + } + if (Inst.getOpcode() == RISCV::C_BNEZ) { + Target = Addr + Inst.getOperand(1).getImm(); + return true; + } + if (Inst.getOpcode() == RISCV::JAL) { + Target = Addr + Inst.getOperand(1).getImm(); + return true; + } + if (Inst.getOpcode() == RISCV::C_JAL) { + Target = Addr + Inst.getOperand(0).getImm(); + return true; + } + if (Inst.getOpcode() == RISCV::C_J) { + Target = Addr + Inst.getOperand(0).getImm(); + return true; + } + if (Inst.getOpcode() == RISCV::P_BEQIMM) { + Target = Addr + Inst.getOperand(1).getImm(); + return true; + } + if (Inst.getOpcode() == RISCV::P_BNEIMM) { + Target = Addr + Inst.getOperand(1).getImm(); + return true; + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MatInt/generateInstSeq.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MatInt/generateInstSeq.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0060cac9c917e49fbeb4ce1922e603e42795b1b7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MatInt/generateInstSeq.cpp @@ -0,0 +1,24 @@ +void generateInstSeq(int64_t Val, bool IsRV64, InstSeq &Res) { + if (isInt<32>(Val)) { + int64_t Hi20 = ((Val + 0x800) >> 12) & 0xFFFFF; + int64_t Lo12 = SignExtend64<12>(Val); + if (Hi20) { + Res.push_back(Inst(RISCV::LUI, Hi20)); + } + if (Lo12 || Hi20 == 0) { + unsigned AddiOpc = (IsRV64 && Hi20) ? RISCV::ADDIW : RISCV::ADDI; + Res.push_back(Inst(AddiOpc, Lo12)); + } + return; + } + assert(IsRV64 && "Can't emit >32-bit imm for non-RV64 target"); + int64_t Lo12 = SignExtend64<12>(Val); + int64_t Hi52 = ((uint64_t)Val + 0x800ull) >> 12; + int ShiftAmount = 12 + findFirstSet((uint64_t)Hi52); + Hi52 = SignExtend64(Hi52 >> (ShiftAmount - 12), 64 - ShiftAmount); + generateInstSeq(Hi52, IsRV64, Res); + Res.push_back(Inst(RISCV::SLLI, ShiftAmount)); + if (Lo12) { + Res.push_back(Inst(RISCV::ADDI, Lo12)); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MatInt/getIntMatCost.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MatInt/getIntMatCost.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6665d21f4034540dc8eec61a6bbfe54ef663c6b8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MatInt/getIntMatCost.cpp @@ -0,0 +1,11 @@ +int getIntMatCost(const APInt &Val, unsigned Size, bool IsRV64) { + int PlatRegSize = IsRV64 ? 64 : 32; + int Cost = 0; + for (unsigned ShiftVal = 0; ShiftVal < Size; ShiftVal += PlatRegSize) { + APInt Chunk = Val.ashr(ShiftVal).sextOrTrunc(PlatRegSize); + InstSeq MatSeq; + generateInstSeq(Chunk.getSExtValue(), IsRV64, MatSeq); + Cost += MatSeq.size(); + } + return std::max(1, Cost); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MatInt/structInst.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MatInt/structInst.cpp new file mode 100644 index 0000000000000000000000000000000000000000..72c131a03e62d00e247b4679e470e545130c5500 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/MatInt/structInst.cpp @@ -0,0 +1,6 @@ +struct Inst { + unsigned Opc; + int64_t Imm; + Inst(unsigned Opc, int64_t Imm) : Opc(Opc), Imm(Imm) { + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/TargetAsmStreamer.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/TargetAsmStreamer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6d3492c3c4b4b024f7373e13055b92638d05fb48 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/TargetAsmStreamer.cpp @@ -0,0 +1,2 @@ +RISCVTargetAsmStreamer::RISCVTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS) : RISCVTargetStreamer(S), OS(OS) { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/TargetStreamer.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/TargetStreamer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b94e431facda3c3c5b1dd95a39117c17ef23685e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/TargetStreamer.cpp @@ -0,0 +1,2 @@ +RISCVTargetStreamer::RISCVTargetStreamer(MCStreamer &S) : MCTargetStreamer(S) { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitAttribute.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitAttribute.cpp new file mode 100644 index 0000000000000000000000000000000000000000..82213bfb7296465510fc0319bf1ff39b9674d8af --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitAttribute.cpp @@ -0,0 +1,3 @@ +void RISCVTargetAsmStreamer::emitAttribute(unsigned Attribute, unsigned Value) { + OS << "\t.attribute\t" << Attribute << ", " << Twine(Value) << "\n"; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitAttribute2.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitAttribute2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..870438b26a6d2717a882ceaf9d551131fdbc7e9e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitAttribute2.cpp @@ -0,0 +1,2 @@ +void RISCVTargetStreamer::emitAttribute(unsigned Attribute, unsigned Value) { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionNoPIC.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionNoPIC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..20d877300fc7bca5ba6b1617a5338511c2bc87df --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionNoPIC.cpp @@ -0,0 +1,3 @@ +void RISCVTargetAsmStreamer::emitDirectiveOptionNoPIC() { + OS << "\t.option\tnopic\n"; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionNoPIC2.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionNoPIC2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..24d360b9a626b3ca30613e07a043e8c36ad04166 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionNoPIC2.cpp @@ -0,0 +1,2 @@ +void RISCVTargetStreamer::emitDirectiveOptionNoPIC() { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionNoRVC.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionNoRVC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..75229057eafcbd9f9adcbb535c46944ef23b39a3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionNoRVC.cpp @@ -0,0 +1,3 @@ +void RISCVTargetAsmStreamer::emitDirectiveOptionNoRVC() { + OS << "\t.option\tnorvc\n"; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionNoRVC2.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionNoRVC2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..64100dd55ed23fbe89ab192674b0e7caa64a0fe3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionNoRVC2.cpp @@ -0,0 +1,2 @@ +void RISCVTargetStreamer::emitDirectiveOptionNoRVC() { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionNoRelax.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionNoRelax.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0a3b8cb02d7a56b7872fcf7a739c9dbe383df43d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionNoRelax.cpp @@ -0,0 +1,3 @@ +void RISCVTargetAsmStreamer::emitDirectiveOptionNoRelax() { + OS << "\t.option\tnorelax\n"; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionNoRelax2.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionNoRelax2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..014cd7022e9839f21fa8aa4768a30cdaeffd861d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionNoRelax2.cpp @@ -0,0 +1,2 @@ +void RISCVTargetStreamer::emitDirectiveOptionNoRelax() { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionPIC.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionPIC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..47ea756b2e1b80b5b651c38d05504fe653b40088 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionPIC.cpp @@ -0,0 +1,3 @@ +void RISCVTargetAsmStreamer::emitDirectiveOptionPIC() { + OS << "\t.option\tpic\n"; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionPIC2.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionPIC2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..06c067ee99a154f8e224930842bc774d5dcb47e4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionPIC2.cpp @@ -0,0 +1,2 @@ +void RISCVTargetStreamer::emitDirectiveOptionPIC() { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionPop.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionPop.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f43b702a23d57cdb8d0a629f253d1d0c953333c9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionPop.cpp @@ -0,0 +1,3 @@ +void RISCVTargetAsmStreamer::emitDirectiveOptionPop() { + OS << "\t.option\tpop\n"; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionPop2.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionPop2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8ca636170f51e633b77f4f3398472f0a640b19ae --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionPop2.cpp @@ -0,0 +1,2 @@ +void RISCVTargetStreamer::emitDirectiveOptionPop() { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionPush.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionPush.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e01d6991e3599028e0801aa2283d93fb6aecf608 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionPush.cpp @@ -0,0 +1,3 @@ +void RISCVTargetAsmStreamer::emitDirectiveOptionPush() { + OS << "\t.option\tpush\n"; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionPush2.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionPush2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5badbcf4aee44982315a64b9d9d7b63501f1ca52 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionPush2.cpp @@ -0,0 +1,2 @@ +void RISCVTargetStreamer::emitDirectiveOptionPush() { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionRVC.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionRVC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3daa81c9defb1fe5908214512a9b997da9df84e9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionRVC.cpp @@ -0,0 +1,3 @@ +void RISCVTargetAsmStreamer::emitDirectiveOptionRVC() { + OS << "\t.option\trvc\n"; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionRVC2.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionRVC2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1e057b99bef751f948ce1248d8808e6b4a42f5cc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionRVC2.cpp @@ -0,0 +1,2 @@ +void RISCVTargetStreamer::emitDirectiveOptionRVC() { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionRelax.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionRelax.cpp new file mode 100644 index 0000000000000000000000000000000000000000..883a2f11627883b745590856102761fa69ea9917 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionRelax.cpp @@ -0,0 +1,3 @@ +void RISCVTargetAsmStreamer::emitDirectiveOptionRelax() { + OS << "\t.option\trelax\n"; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionRelax2.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionRelax2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a501aa992af95ee95eb223b9d508d37abfcd2344 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionRelax2.cpp @@ -0,0 +1,2 @@ +void RISCVTargetStreamer::emitDirectiveOptionRelax() { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitIntTextAttribute.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitIntTextAttribute.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9445cc18a399c4819969cfc8313374b8500f69c8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitIntTextAttribute.cpp @@ -0,0 +1,2 @@ +void RISCVTargetAsmStreamer::emitIntTextAttribute(unsigned Attribute, unsigned IntValue, StringRef StringValue) { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitIntTextAttribute2.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitIntTextAttribute2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..22139c129524dd04c8743fd1456fa9302f4052b7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitIntTextAttribute2.cpp @@ -0,0 +1,2 @@ +void RISCVTargetStreamer::emitIntTextAttribute(unsigned Attribute, unsigned IntValue, StringRef StringValue) { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitTargetAttributes.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitTargetAttributes.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7a944ac5265c68f9afd88fd4ea951f900ad33720 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitTargetAttributes.cpp @@ -0,0 +1,82 @@ +void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI) { + if (STI.hasFeature(RISCV::FeatureRV32E)) { + emitAttribute(RISCVAttrs::STACK_ALIGN, RISCVAttrs::ALIGN_4); + } + else { + emitAttribute(RISCVAttrs::STACK_ALIGN, RISCVAttrs::ALIGN_16); + } + std::string Arch = "rv32"; + if (STI.hasFeature(RISCV::Feature64Bit)) { + Arch = "rv64"; + } + if (STI.hasFeature(RISCV::FeatureRV32E)) { + Arch += "e1p9"; + } + else { + Arch += "i2p0"; + } + if (STI.hasFeature(RISCV::FeatureStdExtM)) { + Arch += "_m2p0"; + } + if (STI.hasFeature(RISCV::FeatureStdExtA)) { + Arch += "_a2p0"; + } + if (STI.hasFeature(RISCV::FeatureStdExtF)) { + Arch += "_f2p0"; + } + if (STI.hasFeature(RISCV::FeatureStdExtD)) { + Arch += "_d2p0"; + } + if (STI.hasFeature(RISCV::FeatureStdExtC)) { + Arch += "_c2p0"; + } + if (STI.hasFeature(RISCV::FeatureStdExtB)) { + Arch += "_b0p93"; + } + if (STI.hasFeature(RISCV::FeatureStdExtV)) { + Arch += "_v0p10"; + } + if (STI.hasFeature(RISCV::FeatureExtZfh)) { + Arch += "_zfh0p1"; + } + if (STI.hasFeature(RISCV::FeatureExtZba)) { + Arch += "_zba0p93"; + } + if (STI.hasFeature(RISCV::FeatureExtZbb)) { + Arch += "_zbb0p93"; + } + if (STI.hasFeature(RISCV::FeatureExtZbc)) { + Arch += "_zbc0p93"; + } + if (STI.hasFeature(RISCV::FeatureExtZbe)) { + Arch += "_zbe0p93"; + } + if (STI.hasFeature(RISCV::FeatureExtZbf)) { + Arch += "_zbf0p93"; + } + if (STI.hasFeature(RISCV::FeatureExtZbm)) { + Arch += "_zbm0p93"; + } + if (STI.hasFeature(RISCV::FeatureExtZbp)) { + Arch += "_zbp0p93"; + } + if (STI.hasFeature(RISCV::FeatureExtZbproposedc)) { + Arch += "_zbproposedc0p93"; + } + if (STI.hasFeature(RISCV::FeatureExtZbr)) { + Arch += "_zbr0p93"; + } + if (STI.hasFeature(RISCV::FeatureExtZbs)) { + Arch += "_zbs0p93"; + } + if (STI.hasFeature(RISCV::FeatureExtZbt)) { + Arch += "_zbt0p93"; + } + if (STI.hasFeature(RISCV::FeatureExtZvamo)) { + Arch += "_zvamo0p10"; + } + if (STI.hasFeature(RISCV::FeatureStdExtZvlsseg)) { + Arch += "_zvlsseg0p10"; + } + emitTextAttribute(RISCVAttrs::ARCH, Arch); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitTextAttribute.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitTextAttribute.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8adf9578c7a98e95d9518eca4e5e5ae261c9a3d3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitTextAttribute.cpp @@ -0,0 +1,2 @@ +void RISCVTargetStreamer::emitTextAttribute(unsigned Attribute, StringRef String) { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitTextAttribute2.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitTextAttribute2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a8d81c0b722b115d155adfa07cf4f9f53e883f06 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/emitTextAttribute2.cpp @@ -0,0 +1,3 @@ +void RISCVTargetAsmStreamer::emitTextAttribute(unsigned Attribute, StringRef String) { + OS << "\t.attribute\t" << Attribute << ", \"" << String << "\"\n"; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/finish.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/finish.cpp new file mode 100644 index 0000000000000000000000000000000000000000..de1f155329e0d6b104ab1c4139016e3276f42f33 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/finish.cpp @@ -0,0 +1,3 @@ +void RISCVTargetStreamer::finish() { + finishAttributeSection(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/finishAttributeSection.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/finishAttributeSection.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7097a145d4931a634134109460465f57fb62532d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/finishAttributeSection.cpp @@ -0,0 +1,2 @@ +void RISCVTargetAsmStreamer::finishAttributeSection() { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/finishAttributeSection2.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/finishAttributeSection2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..dbe790a4f46ac0e73ef02fbaa1295159764b0427 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Emission/TargetStreamer/finishAttributeSection2.cpp @@ -0,0 +1,2 @@ +void RISCVTargetStreamer::finishAttributeSection() { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/CleanupVSETVLI/CleanupVSETVLI.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/CleanupVSETVLI/CleanupVSETVLI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e448a59e103a5b278a32626fa22971c33e4e81a2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/CleanupVSETVLI/CleanupVSETVLI.cpp @@ -0,0 +1,3 @@ +RISCVCleanupVSETVLI() : MachineFunctionPass(ID) { + initializeRISCVCleanupVSETVLIPass(*PassRegistry::getPassRegistry()); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/CleanupVSETVLI/createPass.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/CleanupVSETVLI/createPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..58e6684cb0995575e8263291d2d1b4be23fb8be5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/CleanupVSETVLI/createPass.cpp @@ -0,0 +1,3 @@ +FunctionPass *llvm::createRISCVCleanupVSETVLIPass() { + return new RISCVCleanupVSETVLI(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/CleanupVSETVLI/getAnalysisUsage.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/CleanupVSETVLI/getAnalysisUsage.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f6d109b669c5aa09fb65618028e6a8e7de39a5c0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/CleanupVSETVLI/getAnalysisUsage.cpp @@ -0,0 +1,4 @@ +void getAnalysisUsage(AnalysisUsage &AU) const override { + AU.setPreservesCFG(); + MachineFunctionPass::getAnalysisUsage(AU); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/CleanupVSETVLI/getPassName.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/CleanupVSETVLI/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..927cff9993216c33d5539c62ac637b71f7f1d1ff --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/CleanupVSETVLI/getPassName.cpp @@ -0,0 +1,3 @@ +StringRef getPassName() const override { + return RISCV_CLEANUP_VSETVLI_NAME; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/CleanupVSETVLI/getRequiredProperties.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/CleanupVSETVLI/getRequiredProperties.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b5b9c0930d3d58a2f4601a4830a241ebb30ca4fd --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/CleanupVSETVLI/getRequiredProperties.cpp @@ -0,0 +1,3 @@ +MachineFunctionProperties getRequiredProperties() const override { + return MachineFunctionProperties().set(MachineFunctionProperties::Property::IsSSA); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/CleanupVSETVLI/runOnMachineBasicBlock.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/CleanupVSETVLI/runOnMachineBasicBlock.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c97a1eaf95f42cd86d239dbfe99d01c3ca33235b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/CleanupVSETVLI/runOnMachineBasicBlock.cpp @@ -0,0 +1,48 @@ +bool RISCVCleanupVSETVLI::runOnMachineBasicBlock(MachineBasicBlock &MBB) { + bool Changed = false; + MachineInstr *PrevVSETVLI = nullptr; + for (auto MII = MBB.begin(), MIE = MBB.end(); MII != MIE;) { + MachineInstr &MI = *MII++; + if (MI.getOpcode() != RISCV::PseudoVSETVLI && MI.getOpcode() != RISCV::PseudoVSETIVLI) { + if (PrevVSETVLI && (MI.isCall() || MI.modifiesRegister(RISCV::VL) || MI.modifiesRegister(RISCV::VTYPE))) { + PrevVSETVLI = nullptr; + } + continue; + } + if (!PrevVSETVLI || !MI.getOperand(0).isDead()) { + PrevVSETVLI = &MI; + continue; + } + if (PrevVSETVLI->getOpcode() != MI.getOpcode()) { + PrevVSETVLI = &MI; + continue; + } + Register AVLReg; + bool SameAVL = false; + if (MI.getOpcode() == RISCV::PseudoVSETVLI) { + AVLReg = MI.getOperand(1).getReg(); + SameAVL = PrevVSETVLI->getOperand(1).getReg() == AVLReg; + } + else { + SameAVL = PrevVSETVLI->getOperand(1).getImm() == MI.getOperand(1).getImm(); + } + int64_t PrevVTYPEImm = PrevVSETVLI->getOperand(2).getImm(); + int64_t VTYPEImm = MI.getOperand(2).getImm(); + if (!SameAVL || PrevVTYPEImm != VTYPEImm) { + PrevVSETVLI = &MI; + continue; + } + if ((MI.getOpcode() == RISCV::PseudoVSETVLI) && (AVLReg == RISCV::X0)) { + assert((PrevVSETVLI->getOpcode() == RISCV::PseudoVSETVLI) && "Unexpected vsetvli opcode."); + Register PrevOutVL = PrevVSETVLI->getOperand(0).getReg(); + Register OutVL = MI.getOperand(0).getReg(); + if (PrevOutVL == RISCV::X0 && OutVL != RISCV::X0) { + PrevVSETVLI = &MI; + continue; + } + } + MI.eraseFromParent(); + Changed = true; + } + return Changed; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/CleanupVSETVLI/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/CleanupVSETVLI/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6ece27d6d7d034f89e389b6590f98d8078dfce2d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/CleanupVSETVLI/runOnMachineFunction.cpp @@ -0,0 +1,14 @@ +bool RISCVCleanupVSETVLI::runOnMachineFunction(MachineFunction &MF) { + if (skipFunction(MF.getFunction())) { + return false; + } + const RISCVSubtarget &ST = MF.getSubtarget(); + if (!ST.hasStdExtV()) { + return false; + } + bool Changed = false; + for (MachineBasicBlock &MBB : MF) { + Changed |= runOnMachineBasicBlock(MBB); + } + return Changed; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandAtomicPseudoInsts/ExpandAtomicPseudo.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandAtomicPseudoInsts/ExpandAtomicPseudo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..71ee3fafd667bcf32e20bebcd315637773781ed5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandAtomicPseudoInsts/ExpandAtomicPseudo.cpp @@ -0,0 +1,3 @@ +RISCVExpandAtomicPseudo() : MachineFunctionPass(ID) { + initializeRISCVExpandAtomicPseudoPass(*PassRegistry::getPassRegistry()); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandAtomicPseudoInsts/createPass.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandAtomicPseudoInsts/createPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..83f0448b4561787d31d166f084a5a48eafb4258b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandAtomicPseudoInsts/createPass.cpp @@ -0,0 +1,3 @@ +FunctionPass *createRISCVExpandAtomicPseudoPass() { + return new RISCVExpandAtomicPseudo(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandAtomicPseudoInsts/expandMBB.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandAtomicPseudoInsts/expandMBB.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5dd006e57bfbbd88b5a4764fde7a58c18230b358 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandAtomicPseudoInsts/expandMBB.cpp @@ -0,0 +1,10 @@ +bool RISCVExpandAtomicPseudo::expandMBB(MachineBasicBlock &MBB) { + bool Modified = false; + MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end(); + while (MBBI != E) { + MachineBasicBlock::iterator NMBBI = std::next(MBBI); + Modified |= expandMI(MBB, MBBI, NMBBI); + MBBI = NMBBI; + } + return Modified; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandAtomicPseudoInsts/expandMI.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandAtomicPseudoInsts/expandMI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..64fa3c6df2e50d7812ffe10519289edb89f87299 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandAtomicPseudoInsts/expandMI.cpp @@ -0,0 +1,878 @@ +bool RISCVExpandAtomicPseudo::expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, MachineBasicBlock::iterator &NextMBBI) { + if (MBBI->getOpcode() == RISCV::PseudoAtomicLoadNand32) { + MachineInstr &MI = *MBBI; + DebugLoc DL = MI.getDebugLoc(); + MachineFunction *MF = MBB.getParent(); + auto LoopMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + auto DoneMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + MF->insert(++MBB.getIterator(), LoopMBB); + MF->insert(++LoopMBB->getIterator(), DoneMBB); + LoopMBB->addSuccessor(LoopMBB); + LoopMBB->addSuccessor(DoneMBB); + DoneMBB->splice(DoneMBB->end(), &MBB, MI, MBB.end()); + DoneMBB->transferSuccessors(&MBB); + MBB.addSuccessor(LoopMBB); + if (!IsMasked) { + Register DestReg = MI.getOperand(0).getReg(); + Register ScratchReg = MI.getOperand(1).getReg(); + Register AddrReg = MI.getOperand(2).getReg(); + Register IncrReg = MI.getOperand(3).getReg(); + AtomicOrdering Ordering = static_cast(MI.getOperand(4).getImm()); + BuildMI(LoopMBB, DL, TII->get(getLRForRMW(Ordering, Width)), DestReg).addReg(AddrReg); + switch (BinOp) { + default: + llvm_unreachable("Unexpected AtomicRMW BinOp"); + case AtomicRMWInst::Nand: + BuildMI(LoopMBB, DL, TII->get(RISCV::AND), ScratchReg).addReg(DestReg).addReg(IncrReg); + BuildMI(LoopMBB, DL, TII->get(RISCV::XORI), ScratchReg).addReg(ScratchReg).addImm(-1); + break; + } + BuildMI(LoopMBB, DL, TII->get(getSCForRMW(Ordering, Width)), ScratchReg).addReg(AddrReg).addReg(ScratchReg); + BuildMI(LoopMBB, DL, TII->get(RISCV::BNE)).addReg(ScratchReg).addReg(RISCV::X0).addMBB(LoopMBB); + } + else { + assert(Width == 32 && "Should never need to expand masked 64-bit operations"); + Register DestReg = MI.getOperand(0).getReg(); + Register ScratchReg = MI.getOperand(1).getReg(); + Register AddrReg = MI.getOperand(2).getReg(); + Register IncrReg = MI.getOperand(3).getReg(); + Register MaskReg = MI.getOperand(4).getReg(); + AtomicOrdering Ordering = static_cast(MI.getOperand(5).getImm()); + BuildMI(LoopMBB, DL, TII->get(getLRForRMW32(Ordering)), DestReg).addReg(AddrReg); + switch (BinOp) { + default: + llvm_unreachable("Unexpected AtomicRMW BinOp"); + case AtomicRMWInst::Xchg: + BuildMI(LoopMBB, DL, TII->get(RISCV::ADDI), ScratchReg).addReg(IncrReg).addImm(0); + break; + case AtomicRMWInst::Add: + BuildMI(LoopMBB, DL, TII->get(RISCV::ADD), ScratchReg).addReg(DestReg).addReg(IncrReg); + break; + case AtomicRMWInst::Sub: + BuildMI(LoopMBB, DL, TII->get(RISCV::SUB), ScratchReg).addReg(DestReg).addReg(IncrReg); + break; + case AtomicRMWInst::Nand: + BuildMI(LoopMBB, DL, TII->get(RISCV::AND), ScratchReg).addReg(DestReg).addReg(IncrReg); + BuildMI(LoopMBB, DL, TII->get(RISCV::XORI), ScratchReg).addReg(ScratchReg).addImm(-1); + break; + } + assert(OldValReg != ScratchReg && "OldValReg and ScratchReg must be unique"); + assert(OldValReg != MaskReg && "OldValReg and MaskReg must be unique"); + assert(ScratchReg != MaskReg && "ScratchReg and MaskReg must be unique"); + BuildMI(MBB, DL, TII->get(RISCV::XOR), ScratchReg).addReg(OldValReg).addReg(NewValReg); + BuildMI(MBB, DL, TII->get(RISCV::AND), ScratchReg).addReg(ScratchReg).addReg(MaskReg); + BuildMI(MBB, DL, TII->get(RISCV::XOR), DestReg).addReg(OldValReg).addReg(ScratchReg); + BuildMI(LoopMBB, DL, TII->get(getSCForRMW32(Ordering)), ScratchReg).addReg(AddrReg).addReg(ScratchReg); + BuildMI(LoopMBB, DL, TII->get(RISCV::BNE)).addReg(ScratchReg).addReg(RISCV::X0).addMBB(LoopMBB); + } + NextMBBI = MBB.end(); + MI.eraseFromParent(); + LivePhysRegs LiveRegs; + computeAndAddLiveIns(LiveRegs, *LoopMBB); + computeAndAddLiveIns(LiveRegs, *DoneMBB); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoAtomicLoadNand64) { + MachineInstr &MI = *MBBI; + DebugLoc DL = MI.getDebugLoc(); + MachineFunction *MF = MBB.getParent(); + auto LoopMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + auto DoneMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + MF->insert(++MBB.getIterator(), LoopMBB); + MF->insert(++LoopMBB->getIterator(), DoneMBB); + LoopMBB->addSuccessor(LoopMBB); + LoopMBB->addSuccessor(DoneMBB); + DoneMBB->splice(DoneMBB->end(), &MBB, MI, MBB.end()); + DoneMBB->transferSuccessors(&MBB); + MBB.addSuccessor(LoopMBB); + if (!IsMasked) { + Register DestReg = MI.getOperand(0).getReg(); + Register ScratchReg = MI.getOperand(1).getReg(); + Register AddrReg = MI.getOperand(2).getReg(); + Register IncrReg = MI.getOperand(3).getReg(); + AtomicOrdering Ordering = static_cast(MI.getOperand(4).getImm()); + BuildMI(LoopMBB, DL, TII->get(getLRForRMW(Ordering, Width)), DestReg).addReg(AddrReg); + switch (BinOp) { + default: + llvm_unreachable("Unexpected AtomicRMW BinOp"); + case AtomicRMWInst::Nand: + BuildMI(LoopMBB, DL, TII->get(RISCV::AND), ScratchReg).addReg(DestReg).addReg(IncrReg); + BuildMI(LoopMBB, DL, TII->get(RISCV::XORI), ScratchReg).addReg(ScratchReg).addImm(-1); + break; + } + BuildMI(LoopMBB, DL, TII->get(getSCForRMW(Ordering, Width)), ScratchReg).addReg(AddrReg).addReg(ScratchReg); + BuildMI(LoopMBB, DL, TII->get(RISCV::BNE)).addReg(ScratchReg).addReg(RISCV::X0).addMBB(LoopMBB); + } + else { + assert(Width == 32 && "Should never need to expand masked 64-bit operations"); + Register DestReg = MI.getOperand(0).getReg(); + Register ScratchReg = MI.getOperand(1).getReg(); + Register AddrReg = MI.getOperand(2).getReg(); + Register IncrReg = MI.getOperand(3).getReg(); + Register MaskReg = MI.getOperand(4).getReg(); + AtomicOrdering Ordering = static_cast(MI.getOperand(5).getImm()); + BuildMI(LoopMBB, DL, TII->get(getLRForRMW32(Ordering)), DestReg).addReg(AddrReg); + switch (BinOp) { + default: + llvm_unreachable("Unexpected AtomicRMW BinOp"); + case AtomicRMWInst::Xchg: + BuildMI(LoopMBB, DL, TII->get(RISCV::ADDI), ScratchReg).addReg(IncrReg).addImm(0); + break; + case AtomicRMWInst::Add: + BuildMI(LoopMBB, DL, TII->get(RISCV::ADD), ScratchReg).addReg(DestReg).addReg(IncrReg); + break; + case AtomicRMWInst::Sub: + BuildMI(LoopMBB, DL, TII->get(RISCV::SUB), ScratchReg).addReg(DestReg).addReg(IncrReg); + break; + case AtomicRMWInst::Nand: + BuildMI(LoopMBB, DL, TII->get(RISCV::AND), ScratchReg).addReg(DestReg).addReg(IncrReg); + BuildMI(LoopMBB, DL, TII->get(RISCV::XORI), ScratchReg).addReg(ScratchReg).addImm(-1); + break; + } + assert(OldValReg != ScratchReg && "OldValReg and ScratchReg must be unique"); + assert(OldValReg != MaskReg && "OldValReg and MaskReg must be unique"); + assert(ScratchReg != MaskReg && "ScratchReg and MaskReg must be unique"); + BuildMI(MBB, DL, TII->get(RISCV::XOR), ScratchReg).addReg(OldValReg).addReg(NewValReg); + BuildMI(MBB, DL, TII->get(RISCV::AND), ScratchReg).addReg(ScratchReg).addReg(MaskReg); + BuildMI(MBB, DL, TII->get(RISCV::XOR), DestReg).addReg(OldValReg).addReg(ScratchReg); + BuildMI(LoopMBB, DL, TII->get(getSCForRMW32(Ordering)), ScratchReg).addReg(AddrReg).addReg(ScratchReg); + BuildMI(LoopMBB, DL, TII->get(RISCV::BNE)).addReg(ScratchReg).addReg(RISCV::X0).addMBB(LoopMBB); + } + NextMBBI = MBB.end(); + MI.eraseFromParent(); + LivePhysRegs LiveRegs; + computeAndAddLiveIns(LiveRegs, *LoopMBB); + computeAndAddLiveIns(LiveRegs, *DoneMBB); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoMaskedAtomicSwap32) { + MachineInstr &MI = *MBBI; + DebugLoc DL = MI.getDebugLoc(); + MachineFunction *MF = MBB.getParent(); + auto LoopMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + auto DoneMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + MF->insert(++MBB.getIterator(), LoopMBB); + MF->insert(++LoopMBB->getIterator(), DoneMBB); + LoopMBB->addSuccessor(LoopMBB); + LoopMBB->addSuccessor(DoneMBB); + DoneMBB->splice(DoneMBB->end(), &MBB, MI, MBB.end()); + DoneMBB->transferSuccessors(&MBB); + MBB.addSuccessor(LoopMBB); + if (!IsMasked) { + Register DestReg = MI.getOperand(0).getReg(); + Register ScratchReg = MI.getOperand(1).getReg(); + Register AddrReg = MI.getOperand(2).getReg(); + Register IncrReg = MI.getOperand(3).getReg(); + AtomicOrdering Ordering = static_cast(MI.getOperand(4).getImm()); + BuildMI(LoopMBB, DL, TII->get(getLRForRMW(Ordering, Width)), DestReg).addReg(AddrReg); + switch (BinOp) { + default: + llvm_unreachable("Unexpected AtomicRMW BinOp"); + case AtomicRMWInst::Nand: + BuildMI(LoopMBB, DL, TII->get(RISCV::AND), ScratchReg).addReg(DestReg).addReg(IncrReg); + BuildMI(LoopMBB, DL, TII->get(RISCV::XORI), ScratchReg).addReg(ScratchReg).addImm(-1); + break; + } + BuildMI(LoopMBB, DL, TII->get(getSCForRMW(Ordering, Width)), ScratchReg).addReg(AddrReg).addReg(ScratchReg); + BuildMI(LoopMBB, DL, TII->get(RISCV::BNE)).addReg(ScratchReg).addReg(RISCV::X0).addMBB(LoopMBB); + } + else { + assert(Width == 32 && "Should never need to expand masked 64-bit operations"); + Register DestReg = MI.getOperand(0).getReg(); + Register ScratchReg = MI.getOperand(1).getReg(); + Register AddrReg = MI.getOperand(2).getReg(); + Register IncrReg = MI.getOperand(3).getReg(); + Register MaskReg = MI.getOperand(4).getReg(); + AtomicOrdering Ordering = static_cast(MI.getOperand(5).getImm()); + BuildMI(LoopMBB, DL, TII->get(getLRForRMW32(Ordering)), DestReg).addReg(AddrReg); + switch (BinOp) { + default: + llvm_unreachable("Unexpected AtomicRMW BinOp"); + case AtomicRMWInst::Xchg: + BuildMI(LoopMBB, DL, TII->get(RISCV::ADDI), ScratchReg).addReg(IncrReg).addImm(0); + break; + case AtomicRMWInst::Add: + BuildMI(LoopMBB, DL, TII->get(RISCV::ADD), ScratchReg).addReg(DestReg).addReg(IncrReg); + break; + case AtomicRMWInst::Sub: + BuildMI(LoopMBB, DL, TII->get(RISCV::SUB), ScratchReg).addReg(DestReg).addReg(IncrReg); + break; + case AtomicRMWInst::Nand: + BuildMI(LoopMBB, DL, TII->get(RISCV::AND), ScratchReg).addReg(DestReg).addReg(IncrReg); + BuildMI(LoopMBB, DL, TII->get(RISCV::XORI), ScratchReg).addReg(ScratchReg).addImm(-1); + break; + } + assert(OldValReg != ScratchReg && "OldValReg and ScratchReg must be unique"); + assert(OldValReg != MaskReg && "OldValReg and MaskReg must be unique"); + assert(ScratchReg != MaskReg && "ScratchReg and MaskReg must be unique"); + BuildMI(MBB, DL, TII->get(RISCV::XOR), ScratchReg).addReg(OldValReg).addReg(NewValReg); + BuildMI(MBB, DL, TII->get(RISCV::AND), ScratchReg).addReg(ScratchReg).addReg(MaskReg); + BuildMI(MBB, DL, TII->get(RISCV::XOR), DestReg).addReg(OldValReg).addReg(ScratchReg); + BuildMI(LoopMBB, DL, TII->get(getSCForRMW32(Ordering)), ScratchReg).addReg(AddrReg).addReg(ScratchReg); + BuildMI(LoopMBB, DL, TII->get(RISCV::BNE)).addReg(ScratchReg).addReg(RISCV::X0).addMBB(LoopMBB); + } + NextMBBI = MBB.end(); + MI.eraseFromParent(); + LivePhysRegs LiveRegs; + computeAndAddLiveIns(LiveRegs, *LoopMBB); + computeAndAddLiveIns(LiveRegs, *DoneMBB); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoMaskedAtomicLoadAdd32) { + MachineInstr &MI = *MBBI; + DebugLoc DL = MI.getDebugLoc(); + MachineFunction *MF = MBB.getParent(); + auto LoopMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + auto DoneMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + MF->insert(++MBB.getIterator(), LoopMBB); + MF->insert(++LoopMBB->getIterator(), DoneMBB); + LoopMBB->addSuccessor(LoopMBB); + LoopMBB->addSuccessor(DoneMBB); + DoneMBB->splice(DoneMBB->end(), &MBB, MI, MBB.end()); + DoneMBB->transferSuccessors(&MBB); + MBB.addSuccessor(LoopMBB); + if (!IsMasked) { + Register DestReg = MI.getOperand(0).getReg(); + Register ScratchReg = MI.getOperand(1).getReg(); + Register AddrReg = MI.getOperand(2).getReg(); + Register IncrReg = MI.getOperand(3).getReg(); + AtomicOrdering Ordering = static_cast(MI.getOperand(4).getImm()); + BuildMI(LoopMBB, DL, TII->get(getLRForRMW(Ordering, Width)), DestReg).addReg(AddrReg); + switch (BinOp) { + default: + llvm_unreachable("Unexpected AtomicRMW BinOp"); + case AtomicRMWInst::Nand: + BuildMI(LoopMBB, DL, TII->get(RISCV::AND), ScratchReg).addReg(DestReg).addReg(IncrReg); + BuildMI(LoopMBB, DL, TII->get(RISCV::XORI), ScratchReg).addReg(ScratchReg).addImm(-1); + break; + } + BuildMI(LoopMBB, DL, TII->get(getSCForRMW(Ordering, Width)), ScratchReg).addReg(AddrReg).addReg(ScratchReg); + BuildMI(LoopMBB, DL, TII->get(RISCV::BNE)).addReg(ScratchReg).addReg(RISCV::X0).addMBB(LoopMBB); + } + else { + assert(Width == 32 && "Should never need to expand masked 64-bit operations"); + Register DestReg = MI.getOperand(0).getReg(); + Register ScratchReg = MI.getOperand(1).getReg(); + Register AddrReg = MI.getOperand(2).getReg(); + Register IncrReg = MI.getOperand(3).getReg(); + Register MaskReg = MI.getOperand(4).getReg(); + AtomicOrdering Ordering = static_cast(MI.getOperand(5).getImm()); + BuildMI(LoopMBB, DL, TII->get(getLRForRMW32(Ordering)), DestReg).addReg(AddrReg); + switch (BinOp) { + default: + llvm_unreachable("Unexpected AtomicRMW BinOp"); + case AtomicRMWInst::Xchg: + BuildMI(LoopMBB, DL, TII->get(RISCV::ADDI), ScratchReg).addReg(IncrReg).addImm(0); + break; + case AtomicRMWInst::Add: + BuildMI(LoopMBB, DL, TII->get(RISCV::ADD), ScratchReg).addReg(DestReg).addReg(IncrReg); + break; + case AtomicRMWInst::Sub: + BuildMI(LoopMBB, DL, TII->get(RISCV::SUB), ScratchReg).addReg(DestReg).addReg(IncrReg); + break; + case AtomicRMWInst::Nand: + BuildMI(LoopMBB, DL, TII->get(RISCV::AND), ScratchReg).addReg(DestReg).addReg(IncrReg); + BuildMI(LoopMBB, DL, TII->get(RISCV::XORI), ScratchReg).addReg(ScratchReg).addImm(-1); + break; + } + assert(OldValReg != ScratchReg && "OldValReg and ScratchReg must be unique"); + assert(OldValReg != MaskReg && "OldValReg and MaskReg must be unique"); + assert(ScratchReg != MaskReg && "ScratchReg and MaskReg must be unique"); + BuildMI(MBB, DL, TII->get(RISCV::XOR), ScratchReg).addReg(OldValReg).addReg(NewValReg); + BuildMI(MBB, DL, TII->get(RISCV::AND), ScratchReg).addReg(ScratchReg).addReg(MaskReg); + BuildMI(MBB, DL, TII->get(RISCV::XOR), DestReg).addReg(OldValReg).addReg(ScratchReg); + BuildMI(LoopMBB, DL, TII->get(getSCForRMW32(Ordering)), ScratchReg).addReg(AddrReg).addReg(ScratchReg); + BuildMI(LoopMBB, DL, TII->get(RISCV::BNE)).addReg(ScratchReg).addReg(RISCV::X0).addMBB(LoopMBB); + } + NextMBBI = MBB.end(); + MI.eraseFromParent(); + LivePhysRegs LiveRegs; + computeAndAddLiveIns(LiveRegs, *LoopMBB); + computeAndAddLiveIns(LiveRegs, *DoneMBB); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoMaskedAtomicLoadSub32) { + MachineInstr &MI = *MBBI; + DebugLoc DL = MI.getDebugLoc(); + MachineFunction *MF = MBB.getParent(); + auto LoopMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + auto DoneMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + MF->insert(++MBB.getIterator(), LoopMBB); + MF->insert(++LoopMBB->getIterator(), DoneMBB); + LoopMBB->addSuccessor(LoopMBB); + LoopMBB->addSuccessor(DoneMBB); + DoneMBB->splice(DoneMBB->end(), &MBB, MI, MBB.end()); + DoneMBB->transferSuccessors(&MBB); + MBB.addSuccessor(LoopMBB); + if (!IsMasked) { + Register DestReg = MI.getOperand(0).getReg(); + Register ScratchReg = MI.getOperand(1).getReg(); + Register AddrReg = MI.getOperand(2).getReg(); + Register IncrReg = MI.getOperand(3).getReg(); + AtomicOrdering Ordering = static_cast(MI.getOperand(4).getImm()); + BuildMI(LoopMBB, DL, TII->get(getLRForRMW(Ordering, Width)), DestReg).addReg(AddrReg); + switch (BinOp) { + default: + llvm_unreachable("Unexpected AtomicRMW BinOp"); + case AtomicRMWInst::Nand: + BuildMI(LoopMBB, DL, TII->get(RISCV::AND), ScratchReg).addReg(DestReg).addReg(IncrReg); + BuildMI(LoopMBB, DL, TII->get(RISCV::XORI), ScratchReg).addReg(ScratchReg).addImm(-1); + break; + } + BuildMI(LoopMBB, DL, TII->get(getSCForRMW(Ordering, Width)), ScratchReg).addReg(AddrReg).addReg(ScratchReg); + BuildMI(LoopMBB, DL, TII->get(RISCV::BNE)).addReg(ScratchReg).addReg(RISCV::X0).addMBB(LoopMBB); + } + else { + assert(Width == 32 && "Should never need to expand masked 64-bit operations"); + Register DestReg = MI.getOperand(0).getReg(); + Register ScratchReg = MI.getOperand(1).getReg(); + Register AddrReg = MI.getOperand(2).getReg(); + Register IncrReg = MI.getOperand(3).getReg(); + Register MaskReg = MI.getOperand(4).getReg(); + AtomicOrdering Ordering = static_cast(MI.getOperand(5).getImm()); + BuildMI(LoopMBB, DL, TII->get(getLRForRMW32(Ordering)), DestReg).addReg(AddrReg); + switch (BinOp) { + default: + llvm_unreachable("Unexpected AtomicRMW BinOp"); + case AtomicRMWInst::Xchg: + BuildMI(LoopMBB, DL, TII->get(RISCV::ADDI), ScratchReg).addReg(IncrReg).addImm(0); + break; + case AtomicRMWInst::Add: + BuildMI(LoopMBB, DL, TII->get(RISCV::ADD), ScratchReg).addReg(DestReg).addReg(IncrReg); + break; + case AtomicRMWInst::Sub: + BuildMI(LoopMBB, DL, TII->get(RISCV::SUB), ScratchReg).addReg(DestReg).addReg(IncrReg); + break; + case AtomicRMWInst::Nand: + BuildMI(LoopMBB, DL, TII->get(RISCV::AND), ScratchReg).addReg(DestReg).addReg(IncrReg); + BuildMI(LoopMBB, DL, TII->get(RISCV::XORI), ScratchReg).addReg(ScratchReg).addImm(-1); + break; + } + assert(OldValReg != ScratchReg && "OldValReg and ScratchReg must be unique"); + assert(OldValReg != MaskReg && "OldValReg and MaskReg must be unique"); + assert(ScratchReg != MaskReg && "ScratchReg and MaskReg must be unique"); + BuildMI(MBB, DL, TII->get(RISCV::XOR), ScratchReg).addReg(OldValReg).addReg(NewValReg); + BuildMI(MBB, DL, TII->get(RISCV::AND), ScratchReg).addReg(ScratchReg).addReg(MaskReg); + BuildMI(MBB, DL, TII->get(RISCV::XOR), DestReg).addReg(OldValReg).addReg(ScratchReg); + BuildMI(LoopMBB, DL, TII->get(getSCForRMW32(Ordering)), ScratchReg).addReg(AddrReg).addReg(ScratchReg); + BuildMI(LoopMBB, DL, TII->get(RISCV::BNE)).addReg(ScratchReg).addReg(RISCV::X0).addMBB(LoopMBB); + } + NextMBBI = MBB.end(); + MI.eraseFromParent(); + LivePhysRegs LiveRegs; + computeAndAddLiveIns(LiveRegs, *LoopMBB); + computeAndAddLiveIns(LiveRegs, *DoneMBB); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoMaskedAtomicLoadNand32) { + MachineInstr &MI = *MBBI; + DebugLoc DL = MI.getDebugLoc(); + MachineFunction *MF = MBB.getParent(); + auto LoopMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + auto DoneMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + MF->insert(++MBB.getIterator(), LoopMBB); + MF->insert(++LoopMBB->getIterator(), DoneMBB); + LoopMBB->addSuccessor(LoopMBB); + LoopMBB->addSuccessor(DoneMBB); + DoneMBB->splice(DoneMBB->end(), &MBB, MI, MBB.end()); + DoneMBB->transferSuccessors(&MBB); + MBB.addSuccessor(LoopMBB); + if (!IsMasked) { + Register DestReg = MI.getOperand(0).getReg(); + Register ScratchReg = MI.getOperand(1).getReg(); + Register AddrReg = MI.getOperand(2).getReg(); + Register IncrReg = MI.getOperand(3).getReg(); + AtomicOrdering Ordering = static_cast(MI.getOperand(4).getImm()); + BuildMI(LoopMBB, DL, TII->get(getLRForRMW(Ordering, Width)), DestReg).addReg(AddrReg); + switch (BinOp) { + default: + llvm_unreachable("Unexpected AtomicRMW BinOp"); + case AtomicRMWInst::Nand: + BuildMI(LoopMBB, DL, TII->get(RISCV::AND), ScratchReg).addReg(DestReg).addReg(IncrReg); + BuildMI(LoopMBB, DL, TII->get(RISCV::XORI), ScratchReg).addReg(ScratchReg).addImm(-1); + break; + } + BuildMI(LoopMBB, DL, TII->get(getSCForRMW(Ordering, Width)), ScratchReg).addReg(AddrReg).addReg(ScratchReg); + BuildMI(LoopMBB, DL, TII->get(RISCV::BNE)).addReg(ScratchReg).addReg(RISCV::X0).addMBB(LoopMBB); + } + else { + assert(Width == 32 && "Should never need to expand masked 64-bit operations"); + Register DestReg = MI.getOperand(0).getReg(); + Register ScratchReg = MI.getOperand(1).getReg(); + Register AddrReg = MI.getOperand(2).getReg(); + Register IncrReg = MI.getOperand(3).getReg(); + Register MaskReg = MI.getOperand(4).getReg(); + AtomicOrdering Ordering = static_cast(MI.getOperand(5).getImm()); + BuildMI(LoopMBB, DL, TII->get(getLRForRMW32(Ordering)), DestReg).addReg(AddrReg); + switch (BinOp) { + default: + llvm_unreachable("Unexpected AtomicRMW BinOp"); + case AtomicRMWInst::Xchg: + BuildMI(LoopMBB, DL, TII->get(RISCV::ADDI), ScratchReg).addReg(IncrReg).addImm(0); + break; + case AtomicRMWInst::Add: + BuildMI(LoopMBB, DL, TII->get(RISCV::ADD), ScratchReg).addReg(DestReg).addReg(IncrReg); + break; + case AtomicRMWInst::Sub: + BuildMI(LoopMBB, DL, TII->get(RISCV::SUB), ScratchReg).addReg(DestReg).addReg(IncrReg); + break; + case AtomicRMWInst::Nand: + BuildMI(LoopMBB, DL, TII->get(RISCV::AND), ScratchReg).addReg(DestReg).addReg(IncrReg); + BuildMI(LoopMBB, DL, TII->get(RISCV::XORI), ScratchReg).addReg(ScratchReg).addImm(-1); + break; + } + assert(OldValReg != ScratchReg && "OldValReg and ScratchReg must be unique"); + assert(OldValReg != MaskReg && "OldValReg and MaskReg must be unique"); + assert(ScratchReg != MaskReg && "ScratchReg and MaskReg must be unique"); + BuildMI(MBB, DL, TII->get(RISCV::XOR), ScratchReg).addReg(OldValReg).addReg(NewValReg); + BuildMI(MBB, DL, TII->get(RISCV::AND), ScratchReg).addReg(ScratchReg).addReg(MaskReg); + BuildMI(MBB, DL, TII->get(RISCV::XOR), DestReg).addReg(OldValReg).addReg(ScratchReg); + BuildMI(LoopMBB, DL, TII->get(getSCForRMW32(Ordering)), ScratchReg).addReg(AddrReg).addReg(ScratchReg); + BuildMI(LoopMBB, DL, TII->get(RISCV::BNE)).addReg(ScratchReg).addReg(RISCV::X0).addMBB(LoopMBB); + } + NextMBBI = MBB.end(); + MI.eraseFromParent(); + LivePhysRegs LiveRegs; + computeAndAddLiveIns(LiveRegs, *LoopMBB); + computeAndAddLiveIns(LiveRegs, *DoneMBB); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoMaskedAtomicLoadMax32) { + assert(IsMasked == true && "Should only need to expand masked atomic max/min"); + assert(Width == 32 && "Should never need to expand masked 64-bit operations"); + MachineInstr &MI = *MBBI; + DebugLoc DL = MI.getDebugLoc(); + MachineFunction *MF = MBB.getParent(); + auto LoopHeadMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + auto LoopIfBodyMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + auto LoopTailMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + auto DoneMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + MF->insert(++MBB.getIterator(), LoopHeadMBB); + MF->insert(++LoopHeadMBB->getIterator(), LoopIfBodyMBB); + MF->insert(++LoopIfBodyMBB->getIterator(), LoopTailMBB); + MF->insert(++LoopTailMBB->getIterator(), DoneMBB); + LoopHeadMBB->addSuccessor(LoopIfBodyMBB); + LoopHeadMBB->addSuccessor(LoopTailMBB); + LoopIfBodyMBB->addSuccessor(LoopTailMBB); + LoopTailMBB->addSuccessor(LoopHeadMBB); + LoopTailMBB->addSuccessor(DoneMBB); + DoneMBB->splice(DoneMBB->end(), &MBB, MI, MBB.end()); + DoneMBB->transferSuccessors(&MBB); + MBB.addSuccessor(LoopHeadMBB); + Register DestReg = MI.getOperand(0).getReg(); + Register Scratch1Reg = MI.getOperand(1).getReg(); + Register Scratch2Reg = MI.getOperand(2).getReg(); + Register AddrReg = MI.getOperand(3).getReg(); + Register IncrReg = MI.getOperand(4).getReg(); + Register MaskReg = MI.getOperand(5).getReg(); + bool IsSigned = BinOp == AtomicRMWInst::Min || BinOp == AtomicRMWInst::Max; + AtomicOrdering Ordering = static_cast(MI.getOperand(IsSigned ? 7 : 6).getImm()); + BuildMI(LoopHeadMBB, DL, TII->get(getLRForRMW32(Ordering)), DestReg).addReg(AddrReg); + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::AND), Scratch2Reg).addReg(DestReg).addReg(MaskReg); + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::ADDI), Scratch1Reg).addReg(DestReg).addImm(0); + switch (BinOp) { + default: + llvm_unreachable("Unexpected AtomicRMW BinOp"); + case AtomicRMWInst::Max: { + BuildMI(MBB, DL, TII->get(RISCV::SLL), ValReg).addReg(ValReg).addReg(ShamtReg); + BuildMI(MBB, DL, TII->get(RISCV::SRA), ValReg).addReg(ValReg).addReg(ShamtReg); + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGE)).addReg(Scratch2Reg).addReg(IncrReg).addMBB(LoopTailMBB); + break; + } + case AtomicRMWInst::Min: { + BuildMI(MBB, DL, TII->get(RISCV::SLL), ValReg).addReg(ValReg).addReg(ShamtReg); + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGE)).addReg(IncrReg).addReg(Scratch2Reg).addMBB(LoopTailMBB); + break; + } + case AtomicRMWInst::UMax: + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGEU)).addReg(Scratch2Reg).addReg(IncrReg).addMBB(LoopTailMBB); + break; + case AtomicRMWInst::UMin: + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGEU)).addReg(IncrReg).addReg(Scratch2Reg).addMBB(LoopTailMBB); + break; + } + assert(OldValReg != ScratchReg && "OldValReg and ScratchReg must be unique"); + assert(OldValReg != MaskReg && "OldValReg and MaskReg must be unique"); + assert(ScratchReg != MaskReg && "ScratchReg and MaskReg must be unique"); + BuildMI(MBB, DL, TII->get(RISCV::XOR), ScratchReg).addReg(OldValReg).addReg(NewValReg); + BuildMI(MBB, DL, TII->get(RISCV::AND), ScratchReg).addReg(ScratchReg).addReg(MaskReg); + BuildMI(MBB, DL, TII->get(RISCV::XOR), DestReg).addReg(OldValReg).addReg(ScratchReg); + BuildMI(LoopTailMBB, DL, TII->get(getSCForRMW32(Ordering)), Scratch1Reg).addReg(AddrReg).addReg(Scratch1Reg); + BuildMI(LoopTailMBB, DL, TII->get(RISCV::BNE)).addReg(Scratch1Reg).addReg(RISCV::X0).addMBB(LoopHeadMBB); + NextMBBI = MBB.end(); + MI.eraseFromParent(); + LivePhysRegs LiveRegs; + computeAndAddLiveIns(LiveRegs, *LoopHeadMBB); + computeAndAddLiveIns(LiveRegs, *LoopIfBodyMBB); + computeAndAddLiveIns(LiveRegs, *LoopTailMBB); + computeAndAddLiveIns(LiveRegs, *DoneMBB); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoMaskedAtomicLoadMin32) { + assert(IsMasked == true && "Should only need to expand masked atomic max/min"); + assert(Width == 32 && "Should never need to expand masked 64-bit operations"); + MachineInstr &MI = *MBBI; + DebugLoc DL = MI.getDebugLoc(); + MachineFunction *MF = MBB.getParent(); + auto LoopHeadMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + auto LoopIfBodyMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + auto LoopTailMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + auto DoneMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + MF->insert(++MBB.getIterator(), LoopHeadMBB); + MF->insert(++LoopHeadMBB->getIterator(), LoopIfBodyMBB); + MF->insert(++LoopIfBodyMBB->getIterator(), LoopTailMBB); + MF->insert(++LoopTailMBB->getIterator(), DoneMBB); + LoopHeadMBB->addSuccessor(LoopIfBodyMBB); + LoopHeadMBB->addSuccessor(LoopTailMBB); + LoopIfBodyMBB->addSuccessor(LoopTailMBB); + LoopTailMBB->addSuccessor(LoopHeadMBB); + LoopTailMBB->addSuccessor(DoneMBB); + DoneMBB->splice(DoneMBB->end(), &MBB, MI, MBB.end()); + DoneMBB->transferSuccessors(&MBB); + MBB.addSuccessor(LoopHeadMBB); + Register DestReg = MI.getOperand(0).getReg(); + Register Scratch1Reg = MI.getOperand(1).getReg(); + Register Scratch2Reg = MI.getOperand(2).getReg(); + Register AddrReg = MI.getOperand(3).getReg(); + Register IncrReg = MI.getOperand(4).getReg(); + Register MaskReg = MI.getOperand(5).getReg(); + bool IsSigned = BinOp == AtomicRMWInst::Min || BinOp == AtomicRMWInst::Max; + AtomicOrdering Ordering = static_cast(MI.getOperand(IsSigned ? 7 : 6).getImm()); + BuildMI(LoopHeadMBB, DL, TII->get(getLRForRMW32(Ordering)), DestReg).addReg(AddrReg); + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::AND), Scratch2Reg).addReg(DestReg).addReg(MaskReg); + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::ADDI), Scratch1Reg).addReg(DestReg).addImm(0); + switch (BinOp) { + default: + llvm_unreachable("Unexpected AtomicRMW BinOp"); + case AtomicRMWInst::Max: { + BuildMI(MBB, DL, TII->get(RISCV::SLL), ValReg).addReg(ValReg).addReg(ShamtReg); + BuildMI(MBB, DL, TII->get(RISCV::SRA), ValReg).addReg(ValReg).addReg(ShamtReg); + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGE)).addReg(Scratch2Reg).addReg(IncrReg).addMBB(LoopTailMBB); + break; + } + case AtomicRMWInst::Min: { + BuildMI(MBB, DL, TII->get(RISCV::SLL), ValReg).addReg(ValReg).addReg(ShamtReg); + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGE)).addReg(IncrReg).addReg(Scratch2Reg).addMBB(LoopTailMBB); + break; + } + case AtomicRMWInst::UMax: + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGEU)).addReg(Scratch2Reg).addReg(IncrReg).addMBB(LoopTailMBB); + break; + case AtomicRMWInst::UMin: + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGEU)).addReg(IncrReg).addReg(Scratch2Reg).addMBB(LoopTailMBB); + break; + } + assert(OldValReg != ScratchReg && "OldValReg and ScratchReg must be unique"); + assert(OldValReg != MaskReg && "OldValReg and MaskReg must be unique"); + assert(ScratchReg != MaskReg && "ScratchReg and MaskReg must be unique"); + BuildMI(MBB, DL, TII->get(RISCV::XOR), ScratchReg).addReg(OldValReg).addReg(NewValReg); + BuildMI(MBB, DL, TII->get(RISCV::AND), ScratchReg).addReg(ScratchReg).addReg(MaskReg); + BuildMI(MBB, DL, TII->get(RISCV::XOR), DestReg).addReg(OldValReg).addReg(ScratchReg); + BuildMI(LoopTailMBB, DL, TII->get(getSCForRMW32(Ordering)), Scratch1Reg).addReg(AddrReg).addReg(Scratch1Reg); + BuildMI(LoopTailMBB, DL, TII->get(RISCV::BNE)).addReg(Scratch1Reg).addReg(RISCV::X0).addMBB(LoopHeadMBB); + NextMBBI = MBB.end(); + MI.eraseFromParent(); + LivePhysRegs LiveRegs; + computeAndAddLiveIns(LiveRegs, *LoopHeadMBB); + computeAndAddLiveIns(LiveRegs, *LoopIfBodyMBB); + computeAndAddLiveIns(LiveRegs, *LoopTailMBB); + computeAndAddLiveIns(LiveRegs, *DoneMBB); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoMaskedAtomicLoadUMax32) { + assert(IsMasked == true && "Should only need to expand masked atomic max/min"); + assert(Width == 32 && "Should never need to expand masked 64-bit operations"); + MachineInstr &MI = *MBBI; + DebugLoc DL = MI.getDebugLoc(); + MachineFunction *MF = MBB.getParent(); + auto LoopHeadMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + auto LoopIfBodyMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + auto LoopTailMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + auto DoneMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + MF->insert(++MBB.getIterator(), LoopHeadMBB); + MF->insert(++LoopHeadMBB->getIterator(), LoopIfBodyMBB); + MF->insert(++LoopIfBodyMBB->getIterator(), LoopTailMBB); + MF->insert(++LoopTailMBB->getIterator(), DoneMBB); + LoopHeadMBB->addSuccessor(LoopIfBodyMBB); + LoopHeadMBB->addSuccessor(LoopTailMBB); + LoopIfBodyMBB->addSuccessor(LoopTailMBB); + LoopTailMBB->addSuccessor(LoopHeadMBB); + LoopTailMBB->addSuccessor(DoneMBB); + DoneMBB->splice(DoneMBB->end(), &MBB, MI, MBB.end()); + DoneMBB->transferSuccessors(&MBB); + MBB.addSuccessor(LoopHeadMBB); + Register DestReg = MI.getOperand(0).getReg(); + Register Scratch1Reg = MI.getOperand(1).getReg(); + Register Scratch2Reg = MI.getOperand(2).getReg(); + Register AddrReg = MI.getOperand(3).getReg(); + Register IncrReg = MI.getOperand(4).getReg(); + Register MaskReg = MI.getOperand(5).getReg(); + bool IsSigned = BinOp == AtomicRMWInst::Min || BinOp == AtomicRMWInst::Max; + AtomicOrdering Ordering = static_cast(MI.getOperand(IsSigned ? 7 : 6).getImm()); + BuildMI(LoopHeadMBB, DL, TII->get(getLRForRMW32(Ordering)), DestReg).addReg(AddrReg); + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::AND), Scratch2Reg).addReg(DestReg).addReg(MaskReg); + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::ADDI), Scratch1Reg).addReg(DestReg).addImm(0); + switch (BinOp) { + default: + llvm_unreachable("Unexpected AtomicRMW BinOp"); + case AtomicRMWInst::Max: { + BuildMI(MBB, DL, TII->get(RISCV::SLL), ValReg).addReg(ValReg).addReg(ShamtReg); + BuildMI(MBB, DL, TII->get(RISCV::SRA), ValReg).addReg(ValReg).addReg(ShamtReg); + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGE)).addReg(Scratch2Reg).addReg(IncrReg).addMBB(LoopTailMBB); + break; + } + case AtomicRMWInst::Min: { + BuildMI(MBB, DL, TII->get(RISCV::SLL), ValReg).addReg(ValReg).addReg(ShamtReg); + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGE)).addReg(IncrReg).addReg(Scratch2Reg).addMBB(LoopTailMBB); + break; + } + case AtomicRMWInst::UMax: + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGEU)).addReg(Scratch2Reg).addReg(IncrReg).addMBB(LoopTailMBB); + break; + case AtomicRMWInst::UMin: + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGEU)).addReg(IncrReg).addReg(Scratch2Reg).addMBB(LoopTailMBB); + break; + } + assert(OldValReg != ScratchReg && "OldValReg and ScratchReg must be unique"); + assert(OldValReg != MaskReg && "OldValReg and MaskReg must be unique"); + assert(ScratchReg != MaskReg && "ScratchReg and MaskReg must be unique"); + BuildMI(MBB, DL, TII->get(RISCV::XOR), ScratchReg).addReg(OldValReg).addReg(NewValReg); + BuildMI(MBB, DL, TII->get(RISCV::AND), ScratchReg).addReg(ScratchReg).addReg(MaskReg); + BuildMI(MBB, DL, TII->get(RISCV::XOR), DestReg).addReg(OldValReg).addReg(ScratchReg); + BuildMI(LoopTailMBB, DL, TII->get(getSCForRMW32(Ordering)), Scratch1Reg).addReg(AddrReg).addReg(Scratch1Reg); + BuildMI(LoopTailMBB, DL, TII->get(RISCV::BNE)).addReg(Scratch1Reg).addReg(RISCV::X0).addMBB(LoopHeadMBB); + NextMBBI = MBB.end(); + MI.eraseFromParent(); + LivePhysRegs LiveRegs; + computeAndAddLiveIns(LiveRegs, *LoopHeadMBB); + computeAndAddLiveIns(LiveRegs, *LoopIfBodyMBB); + computeAndAddLiveIns(LiveRegs, *LoopTailMBB); + computeAndAddLiveIns(LiveRegs, *DoneMBB); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoMaskedAtomicLoadUMin32) { + assert(IsMasked == true && "Should only need to expand masked atomic max/min"); + assert(Width == 32 && "Should never need to expand masked 64-bit operations"); + MachineInstr &MI = *MBBI; + DebugLoc DL = MI.getDebugLoc(); + MachineFunction *MF = MBB.getParent(); + auto LoopHeadMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + auto LoopIfBodyMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + auto LoopTailMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + auto DoneMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + MF->insert(++MBB.getIterator(), LoopHeadMBB); + MF->insert(++LoopHeadMBB->getIterator(), LoopIfBodyMBB); + MF->insert(++LoopIfBodyMBB->getIterator(), LoopTailMBB); + MF->insert(++LoopTailMBB->getIterator(), DoneMBB); + LoopHeadMBB->addSuccessor(LoopIfBodyMBB); + LoopHeadMBB->addSuccessor(LoopTailMBB); + LoopIfBodyMBB->addSuccessor(LoopTailMBB); + LoopTailMBB->addSuccessor(LoopHeadMBB); + LoopTailMBB->addSuccessor(DoneMBB); + DoneMBB->splice(DoneMBB->end(), &MBB, MI, MBB.end()); + DoneMBB->transferSuccessors(&MBB); + MBB.addSuccessor(LoopHeadMBB); + Register DestReg = MI.getOperand(0).getReg(); + Register Scratch1Reg = MI.getOperand(1).getReg(); + Register Scratch2Reg = MI.getOperand(2).getReg(); + Register AddrReg = MI.getOperand(3).getReg(); + Register IncrReg = MI.getOperand(4).getReg(); + Register MaskReg = MI.getOperand(5).getReg(); + bool IsSigned = BinOp == AtomicRMWInst::Min || BinOp == AtomicRMWInst::Max; + AtomicOrdering Ordering = static_cast(MI.getOperand(IsSigned ? 7 : 6).getImm()); + BuildMI(LoopHeadMBB, DL, TII->get(getLRForRMW32(Ordering)), DestReg).addReg(AddrReg); + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::AND), Scratch2Reg).addReg(DestReg).addReg(MaskReg); + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::ADDI), Scratch1Reg).addReg(DestReg).addImm(0); + switch (BinOp) { + default: + llvm_unreachable("Unexpected AtomicRMW BinOp"); + case AtomicRMWInst::Max: { + BuildMI(MBB, DL, TII->get(RISCV::SLL), ValReg).addReg(ValReg).addReg(ShamtReg); + BuildMI(MBB, DL, TII->get(RISCV::SRA), ValReg).addReg(ValReg).addReg(ShamtReg); + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGE)).addReg(Scratch2Reg).addReg(IncrReg).addMBB(LoopTailMBB); + break; + } + case AtomicRMWInst::Min: { + BuildMI(MBB, DL, TII->get(RISCV::SLL), ValReg).addReg(ValReg).addReg(ShamtReg); + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGE)).addReg(IncrReg).addReg(Scratch2Reg).addMBB(LoopTailMBB); + break; + } + case AtomicRMWInst::UMax: + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGEU)).addReg(Scratch2Reg).addReg(IncrReg).addMBB(LoopTailMBB); + break; + case AtomicRMWInst::UMin: + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGEU)).addReg(IncrReg).addReg(Scratch2Reg).addMBB(LoopTailMBB); + break; + } + assert(OldValReg != ScratchReg && "OldValReg and ScratchReg must be unique"); + assert(OldValReg != MaskReg && "OldValReg and MaskReg must be unique"); + assert(ScratchReg != MaskReg && "ScratchReg and MaskReg must be unique"); + BuildMI(MBB, DL, TII->get(RISCV::XOR), ScratchReg).addReg(OldValReg).addReg(NewValReg); + BuildMI(MBB, DL, TII->get(RISCV::AND), ScratchReg).addReg(ScratchReg).addReg(MaskReg); + BuildMI(MBB, DL, TII->get(RISCV::XOR), DestReg).addReg(OldValReg).addReg(ScratchReg); + BuildMI(LoopTailMBB, DL, TII->get(getSCForRMW32(Ordering)), Scratch1Reg).addReg(AddrReg).addReg(Scratch1Reg); + BuildMI(LoopTailMBB, DL, TII->get(RISCV::BNE)).addReg(Scratch1Reg).addReg(RISCV::X0).addMBB(LoopHeadMBB); + NextMBBI = MBB.end(); + MI.eraseFromParent(); + LivePhysRegs LiveRegs; + computeAndAddLiveIns(LiveRegs, *LoopHeadMBB); + computeAndAddLiveIns(LiveRegs, *LoopIfBodyMBB); + computeAndAddLiveIns(LiveRegs, *LoopTailMBB); + computeAndAddLiveIns(LiveRegs, *DoneMBB); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoCmpXchg32) { + MachineInstr &MI = *MBBI; + DebugLoc DL = MI.getDebugLoc(); + MachineFunction *MF = MBB.getParent(); + auto LoopHeadMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + auto LoopTailMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + auto DoneMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + MF->insert(++MBB.getIterator(), LoopHeadMBB); + MF->insert(++LoopHeadMBB->getIterator(), LoopTailMBB); + MF->insert(++LoopTailMBB->getIterator(), DoneMBB); + LoopHeadMBB->addSuccessor(LoopTailMBB); + LoopHeadMBB->addSuccessor(DoneMBB); + LoopTailMBB->addSuccessor(DoneMBB); + LoopTailMBB->addSuccessor(LoopHeadMBB); + DoneMBB->splice(DoneMBB->end(), &MBB, MI, MBB.end()); + DoneMBB->transferSuccessors(&MBB); + MBB.addSuccessor(LoopHeadMBB); + Register DestReg = MI.getOperand(0).getReg(); + Register ScratchReg = MI.getOperand(1).getReg(); + Register AddrReg = MI.getOperand(2).getReg(); + Register CmpValReg = MI.getOperand(3).getReg(); + Register NewValReg = MI.getOperand(4).getReg(); + AtomicOrdering Ordering = static_cast(MI.getOperand(IsMasked ? 6 : 5).getImm()); + if (!IsMasked) { + BuildMI(LoopHeadMBB, DL, TII->get(getLRForRMW(Ordering, Width)), DestReg).addReg(AddrReg); + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BNE)).addReg(DestReg).addReg(CmpValReg).addMBB(DoneMBB); + BuildMI(LoopTailMBB, DL, TII->get(getSCForRMW(Ordering, Width)), ScratchReg).addReg(AddrReg).addReg(NewValReg); + BuildMI(LoopTailMBB, DL, TII->get(RISCV::BNE)).addReg(ScratchReg).addReg(RISCV::X0).addMBB(LoopHeadMBB); + } + else { + Register MaskReg = MI.getOperand(5).getReg(); + BuildMI(LoopHeadMBB, DL, TII->get(getLRForRMW(Ordering, Width)), DestReg).addReg(AddrReg); + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::AND), ScratchReg).addReg(DestReg).addReg(MaskReg); + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BNE)).addReg(ScratchReg).addReg(CmpValReg).addMBB(DoneMBB); + assert(OldValReg != ScratchReg && "OldValReg and ScratchReg must be unique"); + assert(OldValReg != MaskReg && "OldValReg and MaskReg must be unique"); + assert(ScratchReg != MaskReg && "ScratchReg and MaskReg must be unique"); + BuildMI(MBB, DL, TII->get(RISCV::XOR), ScratchReg).addReg(OldValReg).addReg(NewValReg); + BuildMI(MBB, DL, TII->get(RISCV::AND), ScratchReg).addReg(ScratchReg).addReg(MaskReg); + BuildMI(MBB, DL, TII->get(RISCV::XOR), DestReg).addReg(OldValReg).addReg(ScratchReg); + BuildMI(LoopTailMBB, DL, TII->get(getSCForRMW(Ordering, Width)), ScratchReg).addReg(AddrReg).addReg(ScratchReg); + BuildMI(LoopTailMBB, DL, TII->get(RISCV::BNE)).addReg(ScratchReg).addReg(RISCV::X0).addMBB(LoopHeadMBB); + } + NextMBBI = MBB.end(); + MI.eraseFromParent(); + LivePhysRegs LiveRegs; + computeAndAddLiveIns(LiveRegs, *LoopHeadMBB); + computeAndAddLiveIns(LiveRegs, *LoopTailMBB); + computeAndAddLiveIns(LiveRegs, *DoneMBB); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoCmpXchg64) { + MachineInstr &MI = *MBBI; + DebugLoc DL = MI.getDebugLoc(); + MachineFunction *MF = MBB.getParent(); + auto LoopHeadMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + auto LoopTailMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + auto DoneMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + MF->insert(++MBB.getIterator(), LoopHeadMBB); + MF->insert(++LoopHeadMBB->getIterator(), LoopTailMBB); + MF->insert(++LoopTailMBB->getIterator(), DoneMBB); + LoopHeadMBB->addSuccessor(LoopTailMBB); + LoopHeadMBB->addSuccessor(DoneMBB); + LoopTailMBB->addSuccessor(DoneMBB); + LoopTailMBB->addSuccessor(LoopHeadMBB); + DoneMBB->splice(DoneMBB->end(), &MBB, MI, MBB.end()); + DoneMBB->transferSuccessors(&MBB); + MBB.addSuccessor(LoopHeadMBB); + Register DestReg = MI.getOperand(0).getReg(); + Register ScratchReg = MI.getOperand(1).getReg(); + Register AddrReg = MI.getOperand(2).getReg(); + Register CmpValReg = MI.getOperand(3).getReg(); + Register NewValReg = MI.getOperand(4).getReg(); + AtomicOrdering Ordering = static_cast(MI.getOperand(IsMasked ? 6 : 5).getImm()); + if (!IsMasked) { + BuildMI(LoopHeadMBB, DL, TII->get(getLRForRMW(Ordering, Width)), DestReg).addReg(AddrReg); + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BNE)).addReg(DestReg).addReg(CmpValReg).addMBB(DoneMBB); + BuildMI(LoopTailMBB, DL, TII->get(getSCForRMW(Ordering, Width)), ScratchReg).addReg(AddrReg).addReg(NewValReg); + BuildMI(LoopTailMBB, DL, TII->get(RISCV::BNE)).addReg(ScratchReg).addReg(RISCV::X0).addMBB(LoopHeadMBB); + } + else { + Register MaskReg = MI.getOperand(5).getReg(); + BuildMI(LoopHeadMBB, DL, TII->get(getLRForRMW(Ordering, Width)), DestReg).addReg(AddrReg); + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::AND), ScratchReg).addReg(DestReg).addReg(MaskReg); + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BNE)).addReg(ScratchReg).addReg(CmpValReg).addMBB(DoneMBB); + assert(OldValReg != ScratchReg && "OldValReg and ScratchReg must be unique"); + assert(OldValReg != MaskReg && "OldValReg and MaskReg must be unique"); + assert(ScratchReg != MaskReg && "ScratchReg and MaskReg must be unique"); + BuildMI(MBB, DL, TII->get(RISCV::XOR), ScratchReg).addReg(OldValReg).addReg(NewValReg); + BuildMI(MBB, DL, TII->get(RISCV::AND), ScratchReg).addReg(ScratchReg).addReg(MaskReg); + BuildMI(MBB, DL, TII->get(RISCV::XOR), DestReg).addReg(OldValReg).addReg(ScratchReg); + BuildMI(LoopTailMBB, DL, TII->get(getSCForRMW(Ordering, Width)), ScratchReg).addReg(AddrReg).addReg(ScratchReg); + BuildMI(LoopTailMBB, DL, TII->get(RISCV::BNE)).addReg(ScratchReg).addReg(RISCV::X0).addMBB(LoopHeadMBB); + } + NextMBBI = MBB.end(); + MI.eraseFromParent(); + LivePhysRegs LiveRegs; + computeAndAddLiveIns(LiveRegs, *LoopHeadMBB); + computeAndAddLiveIns(LiveRegs, *LoopTailMBB); + computeAndAddLiveIns(LiveRegs, *DoneMBB); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoMaskedCmpXchg32) { + MachineInstr &MI = *MBBI; + DebugLoc DL = MI.getDebugLoc(); + MachineFunction *MF = MBB.getParent(); + auto LoopHeadMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + auto LoopTailMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + auto DoneMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + MF->insert(++MBB.getIterator(), LoopHeadMBB); + MF->insert(++LoopHeadMBB->getIterator(), LoopTailMBB); + MF->insert(++LoopTailMBB->getIterator(), DoneMBB); + LoopHeadMBB->addSuccessor(LoopTailMBB); + LoopHeadMBB->addSuccessor(DoneMBB); + LoopTailMBB->addSuccessor(DoneMBB); + LoopTailMBB->addSuccessor(LoopHeadMBB); + DoneMBB->splice(DoneMBB->end(), &MBB, MI, MBB.end()); + DoneMBB->transferSuccessors(&MBB); + MBB.addSuccessor(LoopHeadMBB); + Register DestReg = MI.getOperand(0).getReg(); + Register ScratchReg = MI.getOperand(1).getReg(); + Register AddrReg = MI.getOperand(2).getReg(); + Register CmpValReg = MI.getOperand(3).getReg(); + Register NewValReg = MI.getOperand(4).getReg(); + AtomicOrdering Ordering = static_cast(MI.getOperand(IsMasked ? 6 : 5).getImm()); + if (!IsMasked) { + BuildMI(LoopHeadMBB, DL, TII->get(getLRForRMW(Ordering, Width)), DestReg).addReg(AddrReg); + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BNE)).addReg(DestReg).addReg(CmpValReg).addMBB(DoneMBB); + BuildMI(LoopTailMBB, DL, TII->get(getSCForRMW(Ordering, Width)), ScratchReg).addReg(AddrReg).addReg(NewValReg); + BuildMI(LoopTailMBB, DL, TII->get(RISCV::BNE)).addReg(ScratchReg).addReg(RISCV::X0).addMBB(LoopHeadMBB); + } + else { + Register MaskReg = MI.getOperand(5).getReg(); + BuildMI(LoopHeadMBB, DL, TII->get(getLRForRMW(Ordering, Width)), DestReg).addReg(AddrReg); + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::AND), ScratchReg).addReg(DestReg).addReg(MaskReg); + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BNE)).addReg(ScratchReg).addReg(CmpValReg).addMBB(DoneMBB); + assert(OldValReg != ScratchReg && "OldValReg and ScratchReg must be unique"); + assert(OldValReg != MaskReg && "OldValReg and MaskReg must be unique"); + assert(ScratchReg != MaskReg && "ScratchReg and MaskReg must be unique"); + BuildMI(MBB, DL, TII->get(RISCV::XOR), ScratchReg).addReg(OldValReg).addReg(NewValReg); + BuildMI(MBB, DL, TII->get(RISCV::AND), ScratchReg).addReg(ScratchReg).addReg(MaskReg); + BuildMI(MBB, DL, TII->get(RISCV::XOR), DestReg).addReg(OldValReg).addReg(ScratchReg); + BuildMI(LoopTailMBB, DL, TII->get(getSCForRMW(Ordering, Width)), ScratchReg).addReg(AddrReg).addReg(ScratchReg); + BuildMI(LoopTailMBB, DL, TII->get(RISCV::BNE)).addReg(ScratchReg).addReg(RISCV::X0).addMBB(LoopHeadMBB); + } + NextMBBI = MBB.end(); + MI.eraseFromParent(); + LivePhysRegs LiveRegs; + computeAndAddLiveIns(LiveRegs, *LoopHeadMBB); + computeAndAddLiveIns(LiveRegs, *LoopTailMBB); + computeAndAddLiveIns(LiveRegs, *DoneMBB); + return true; + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandAtomicPseudoInsts/getPassName.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandAtomicPseudoInsts/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..be55c65dfca4dd0ed4321f773d46c7d6e86200c4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandAtomicPseudoInsts/getPassName.cpp @@ -0,0 +1,3 @@ +StringRef getPassName() const override { + return RISCV_EXPAND_ATOMIC_PSEUDO_NAME; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandAtomicPseudoInsts/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandAtomicPseudoInsts/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fd6bfc81864cf513dbe24e299d2cc82c81f36b27 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandAtomicPseudoInsts/runOnMachineFunction.cpp @@ -0,0 +1,8 @@ +bool RISCVExpandAtomicPseudo::runOnMachineFunction(MachineFunction &MF) { + TII = static_cast(MF.getSubtarget().getInstrInfo()); + bool Modified = false; + for (auto &MBB : MF) { + Modified |= expandMBB(MBB); + } + return Modified; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandPseudoInsts/ExpandPseudo.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandPseudoInsts/ExpandPseudo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..619ea5f1fb6cf92b77a790a42642051fc3450f92 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandPseudoInsts/ExpandPseudo.cpp @@ -0,0 +1,3 @@ +RISCVExpandPseudo() : MachineFunctionPass(ID) { + initializeRISCVExpandPseudoPass(*PassRegistry::getPassRegistry()); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandPseudoInsts/createPass.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandPseudoInsts/createPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..207e3c11c810551063e0c2b55a3d9af32a794d7b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandPseudoInsts/createPass.cpp @@ -0,0 +1,3 @@ +FunctionPass *createRISCVExpandPseudoPass() { + return new RISCVExpandPseudo(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandPseudoInsts/expandMBB.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandPseudoInsts/expandMBB.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bf9fe048bfd2dbdd4940122bf6e54f65401af7df --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandPseudoInsts/expandMBB.cpp @@ -0,0 +1,10 @@ +bool RISCVExpandPseudo::expandMBB(MachineBasicBlock &MBB) { + bool Modified = false; + MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end(); + while (MBBI != E) { + MachineBasicBlock::iterator NMBBI = std::next(MBBI); + Modified |= expandMI(MBB, MBBI, NMBBI); + MBBI = NMBBI; + } + return Modified; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandPseudoInsts/expandMI.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandPseudoInsts/expandMI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4df12ee0ca8495e367ac08772bf8cade7d1a7463 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandPseudoInsts/expandMI.cpp @@ -0,0 +1,243 @@ +bool RISCVExpandPseudo::expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, MachineBasicBlock::iterator &NextMBBI) { + if (MBBI->getOpcode() == RISCV::PseudoLLA) { + MachineFunction *MF = MBB.getParent(); + MachineInstr &MI = *MBBI; + DebugLoc DL = MI.getDebugLoc(); + Register DestReg = MI.getOperand(0).getReg(); + const MachineOperand &Symbol = MI.getOperand(1); + MachineBasicBlock *NewMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + NewMBB->setLabelMustBeEmitted(); + MF->insert(++MBB.getIterator(), NewMBB); + BuildMI(NewMBB, DL, TII->get(RISCV::AUIPC), DestReg).addDisp(Symbol, 0, FlagsHi); + BuildMI(NewMBB, DL, TII->get(SecondOpcode), DestReg).addReg(DestReg).addMBB(NewMBB, RISCVII::MO_PCREL_LO); + NewMBB->splice(NewMBB->end(), &MBB, std::next(MBBI), MBB.end()); + NewMBB->transferSuccessorsAndUpdatePHIs(&MBB); + MBB.addSuccessor(NewMBB); + LivePhysRegs LiveRegs; + computeAndAddLiveIns(LiveRegs, *NewMBB); + NextMBBI = MBB.end(); + MI.eraseFromParent(); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoLA) { + MachineFunction *MF = MBB.getParent(); + unsigned SecondOpcode; + unsigned FlagsHi; + if (MF->getTarget().isPositionIndependent()) { + const auto &STI = MF->getSubtarget(); + SecondOpcode = STI.is64Bit() ? RISCV::LD : RISCV::LW; + FlagsHi = RISCVII::MO_GOT_HI; + } + else { + SecondOpcode = RISCV::ADDI; + FlagsHi = RISCVII::MO_PCREL_HI; + } + MachineFunction *MF = MBB.getParent(); + MachineInstr &MI = *MBBI; + DebugLoc DL = MI.getDebugLoc(); + Register DestReg = MI.getOperand(0).getReg(); + const MachineOperand &Symbol = MI.getOperand(1); + MachineBasicBlock *NewMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + NewMBB->setLabelMustBeEmitted(); + MF->insert(++MBB.getIterator(), NewMBB); + BuildMI(NewMBB, DL, TII->get(RISCV::AUIPC), DestReg).addDisp(Symbol, 0, FlagsHi); + BuildMI(NewMBB, DL, TII->get(SecondOpcode), DestReg).addReg(DestReg).addMBB(NewMBB, RISCVII::MO_PCREL_LO); + NewMBB->splice(NewMBB->end(), &MBB, std::next(MBBI), MBB.end()); + NewMBB->transferSuccessorsAndUpdatePHIs(&MBB); + MBB.addSuccessor(NewMBB); + LivePhysRegs LiveRegs; + computeAndAddLiveIns(LiveRegs, *NewMBB); + NextMBBI = MBB.end(); + MI.eraseFromParent(); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoLA_TLS_IE) { + const auto &STI = MF->getSubtarget(); + unsigned SecondOpcode = STI.is64Bit() ? RISCV::LD : RISCV::LW; + MachineFunction *MF = MBB.getParent(); + MachineInstr &MI = *MBBI; + DebugLoc DL = MI.getDebugLoc(); + Register DestReg = MI.getOperand(0).getReg(); + const MachineOperand &Symbol = MI.getOperand(1); + MachineBasicBlock *NewMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + NewMBB->setLabelMustBeEmitted(); + MF->insert(++MBB.getIterator(), NewMBB); + BuildMI(NewMBB, DL, TII->get(RISCV::AUIPC), DestReg).addDisp(Symbol, 0, FlagsHi); + BuildMI(NewMBB, DL, TII->get(SecondOpcode), DestReg).addReg(DestReg).addMBB(NewMBB, RISCVII::MO_PCREL_LO); + NewMBB->splice(NewMBB->end(), &MBB, std::next(MBBI), MBB.end()); + NewMBB->transferSuccessorsAndUpdatePHIs(&MBB); + MBB.addSuccessor(NewMBB); + LivePhysRegs LiveRegs; + computeAndAddLiveIns(LiveRegs, *NewMBB); + NextMBBI = MBB.end(); + MI.eraseFromParent(); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoLA_TLS_GD) { + MachineFunction *MF = MBB.getParent(); + MachineInstr &MI = *MBBI; + DebugLoc DL = MI.getDebugLoc(); + Register DestReg = MI.getOperand(0).getReg(); + const MachineOperand &Symbol = MI.getOperand(1); + MachineBasicBlock *NewMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + NewMBB->setLabelMustBeEmitted(); + MF->insert(++MBB.getIterator(), NewMBB); + BuildMI(NewMBB, DL, TII->get(RISCV::AUIPC), DestReg).addDisp(Symbol, 0, FlagsHi); + BuildMI(NewMBB, DL, TII->get(SecondOpcode), DestReg).addReg(DestReg).addMBB(NewMBB, RISCVII::MO_PCREL_LO); + NewMBB->splice(NewMBB->end(), &MBB, std::next(MBBI), MBB.end()); + NewMBB->transferSuccessorsAndUpdatePHIs(&MBB); + MBB.addSuccessor(NewMBB); + LivePhysRegs LiveRegs; + computeAndAddLiveIns(LiveRegs, *NewMBB); + NextMBBI = MBB.end(); + MI.eraseFromParent(); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoVSETVLI) { + assert(MBBI->getNumOperands() == 5 && "Unexpected instruction format"); + DebugLoc DL = MBBI->getDebugLoc(); + assert((MBBI->getOpcode() == RISCV::PseudoVSETVLI || MBBI->getOpcode() == RISCV::PseudoVSETIVLI) && "Unexpected pseudo instruction"); + unsigned Opcode; + if (MBBI->getOpcode() == RISCV::PseudoVSETVLI) + Opcode = RISCV::VSETVLI; + else + Opcode = RISCV::VSETIVLI; + const MCInstrDesc &Desc = TII->get(Opcode); + assert(Desc.getNumOperands() == 3 && "Unexpected instruction format"); + Register DstReg = MBBI->getOperand(0).getReg(); + bool DstIsDead = MBBI->getOperand(0).isDead(); + BuildMI(MBB, MBBI, DL, Desc).addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)).add(MBBI->getOperand(1)).add(MBBI->getOperand(2)); + MBBI->eraseFromParent(); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoVSETIVLI) { + assert(MBBI->getNumOperands() == 5 && "Unexpected instruction format"); + DebugLoc DL = MBBI->getDebugLoc(); + assert((MBBI->getOpcode() == RISCV::PseudoVSETVLI || MBBI->getOpcode() == RISCV::PseudoVSETIVLI) && "Unexpected pseudo instruction"); + unsigned Opcode; + if (MBBI->getOpcode() == RISCV::PseudoVSETVLI) + Opcode = RISCV::VSETVLI; + else + Opcode = RISCV::VSETIVLI; + const MCInstrDesc &Desc = TII->get(Opcode); + assert(Desc.getNumOperands() == 3 && "Unexpected instruction format"); + Register DstReg = MBBI->getOperand(0).getReg(); + bool DstIsDead = MBBI->getOperand(0).isDead(); + BuildMI(MBB, MBBI, DL, Desc).addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)).add(MBBI->getOperand(1)).add(MBBI->getOperand(2)); + MBBI->eraseFromParent(); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoVMCLR_M_B1) { + DebugLoc DL = MBBI->getDebugLoc(); + Register DstReg = MBBI->getOperand(0).getReg(); + const MCInstrDesc &Desc = TII->get(Opcode); + BuildMI(MBB, MBBI, DL, Desc, DstReg).addReg(DstReg, RegState::Undef).addReg(DstReg, RegState::Undef); + MBBI->eraseFromParent(); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoVMCLR_M_B2) { + DebugLoc DL = MBBI->getDebugLoc(); + Register DstReg = MBBI->getOperand(0).getReg(); + const MCInstrDesc &Desc = TII->get(Opcode); + BuildMI(MBB, MBBI, DL, Desc, DstReg).addReg(DstReg, RegState::Undef).addReg(DstReg, RegState::Undef); + MBBI->eraseFromParent(); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoVMCLR_M_B4) { + DebugLoc DL = MBBI->getDebugLoc(); + Register DstReg = MBBI->getOperand(0).getReg(); + const MCInstrDesc &Desc = TII->get(Opcode); + BuildMI(MBB, MBBI, DL, Desc, DstReg).addReg(DstReg, RegState::Undef).addReg(DstReg, RegState::Undef); + MBBI->eraseFromParent(); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoVMCLR_M_B8) { + DebugLoc DL = MBBI->getDebugLoc(); + Register DstReg = MBBI->getOperand(0).getReg(); + const MCInstrDesc &Desc = TII->get(Opcode); + BuildMI(MBB, MBBI, DL, Desc, DstReg).addReg(DstReg, RegState::Undef).addReg(DstReg, RegState::Undef); + MBBI->eraseFromParent(); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoVMCLR_M_B16) { + DebugLoc DL = MBBI->getDebugLoc(); + Register DstReg = MBBI->getOperand(0).getReg(); + const MCInstrDesc &Desc = TII->get(Opcode); + BuildMI(MBB, MBBI, DL, Desc, DstReg).addReg(DstReg, RegState::Undef).addReg(DstReg, RegState::Undef); + MBBI->eraseFromParent(); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoVMCLR_M_B32) { + DebugLoc DL = MBBI->getDebugLoc(); + Register DstReg = MBBI->getOperand(0).getReg(); + const MCInstrDesc &Desc = TII->get(Opcode); + BuildMI(MBB, MBBI, DL, Desc, DstReg).addReg(DstReg, RegState::Undef).addReg(DstReg, RegState::Undef); + MBBI->eraseFromParent(); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoVMCLR_M_B64) { + DebugLoc DL = MBBI->getDebugLoc(); + Register DstReg = MBBI->getOperand(0).getReg(); + const MCInstrDesc &Desc = TII->get(Opcode); + BuildMI(MBB, MBBI, DL, Desc, DstReg).addReg(DstReg, RegState::Undef).addReg(DstReg, RegState::Undef); + MBBI->eraseFromParent(); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoVMSET_M_B1) { + DebugLoc DL = MBBI->getDebugLoc(); + Register DstReg = MBBI->getOperand(0).getReg(); + const MCInstrDesc &Desc = TII->get(Opcode); + BuildMI(MBB, MBBI, DL, Desc, DstReg).addReg(DstReg, RegState::Undef).addReg(DstReg, RegState::Undef); + MBBI->eraseFromParent(); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoVMSET_M_B2) { + DebugLoc DL = MBBI->getDebugLoc(); + Register DstReg = MBBI->getOperand(0).getReg(); + const MCInstrDesc &Desc = TII->get(Opcode); + BuildMI(MBB, MBBI, DL, Desc, DstReg).addReg(DstReg, RegState::Undef).addReg(DstReg, RegState::Undef); + MBBI->eraseFromParent(); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoVMSET_M_B4) { + DebugLoc DL = MBBI->getDebugLoc(); + Register DstReg = MBBI->getOperand(0).getReg(); + const MCInstrDesc &Desc = TII->get(Opcode); + BuildMI(MBB, MBBI, DL, Desc, DstReg).addReg(DstReg, RegState::Undef).addReg(DstReg, RegState::Undef); + MBBI->eraseFromParent(); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoVMSET_M_B8) { + DebugLoc DL = MBBI->getDebugLoc(); + Register DstReg = MBBI->getOperand(0).getReg(); + const MCInstrDesc &Desc = TII->get(Opcode); + BuildMI(MBB, MBBI, DL, Desc, DstReg).addReg(DstReg, RegState::Undef).addReg(DstReg, RegState::Undef); + MBBI->eraseFromParent(); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoVMSET_M_B16) { + DebugLoc DL = MBBI->getDebugLoc(); + Register DstReg = MBBI->getOperand(0).getReg(); + const MCInstrDesc &Desc = TII->get(Opcode); + BuildMI(MBB, MBBI, DL, Desc, DstReg).addReg(DstReg, RegState::Undef).addReg(DstReg, RegState::Undef); + MBBI->eraseFromParent(); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoVMSET_M_B32) { + DebugLoc DL = MBBI->getDebugLoc(); + Register DstReg = MBBI->getOperand(0).getReg(); + const MCInstrDesc &Desc = TII->get(Opcode); + BuildMI(MBB, MBBI, DL, Desc, DstReg).addReg(DstReg, RegState::Undef).addReg(DstReg, RegState::Undef); + MBBI->eraseFromParent(); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoVMSET_M_B64) { + DebugLoc DL = MBBI->getDebugLoc(); + Register DstReg = MBBI->getOperand(0).getReg(); + const MCInstrDesc &Desc = TII->get(Opcode); + BuildMI(MBB, MBBI, DL, Desc, DstReg).addReg(DstReg, RegState::Undef).addReg(DstReg, RegState::Undef); + MBBI->eraseFromParent(); + return true; + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandPseudoInsts/getPassName.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandPseudoInsts/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f746343de8bcbf0ec410bfee6eabf7dde8e37c4b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandPseudoInsts/getPassName.cpp @@ -0,0 +1,3 @@ +StringRef getPassName() const override { + return RISCV_EXPAND_PSEUDO_NAME; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandPseudoInsts/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandPseudoInsts/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3c3b6dc2dce658992de0bfbde1b5323b33b24ebb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandPseudoInsts/runOnMachineFunction.cpp @@ -0,0 +1,8 @@ +bool RISCVExpandPseudo::runOnMachineFunction(MachineFunction &MF) { + TII = static_cast(MF.getSubtarget().getInstrInfo()); + bool Modified = false; + for (auto &MBB : MF) { + Modified |= expandMBB(MBB); + } + return Modified; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandSDMAInsts/ExpandSDMA.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandSDMAInsts/ExpandSDMA.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bfd690f83227cf797a5122869053bdf61b88b080 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandSDMAInsts/ExpandSDMA.cpp @@ -0,0 +1,4 @@ +//zmCorrectzm +RISCVExpandSDMA() : MachineFunctionPass(ID) { + initializeRISCVExpandSDMAPass(*PassRegistry::getPassRegistry()); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandSDMAInsts/ExpandSDMAInsts.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandSDMAInsts/ExpandSDMAInsts.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b09cb138b81e142b9f132beb0e5141b14486f039 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandSDMAInsts/ExpandSDMAInsts.cpp @@ -0,0 +1,3 @@ +RISCVExpandSDMA() : MachineFunctionPass(ID) { + initializeRISCVExpandSDMAPass(*PassRegistry::getPassRegistry()); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandSDMAInsts/createPass.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandSDMAInsts/createPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6b3fbc434678cf0c2088d1839d15f8c3b1218bd7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandSDMAInsts/createPass.cpp @@ -0,0 +1,3 @@ +FunctionPass *createRISCVExpandSDMAPass() { + return new RISCVExpandSDMA(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandSDMAInsts/expandMBB.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandSDMAInsts/expandMBB.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d67ac95a5dbed0f8eebc6dc6f008cdcb5d661edb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandSDMAInsts/expandMBB.cpp @@ -0,0 +1,10 @@ +bool RISCVExpandSDMA::expandMBB(MachineBasicBlock &MBB) { + bool Modified = false; + MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end(); + for (; MBBI != E;) { + MachineBasicBlock::iterator NMBBI = std::next(MBBI); + Modified = Modified | expandMI(MBB, MBBI, NMBBI); + MBBI = NMBBI; + } + return Modified; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandSDMAInsts/expandMI.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandSDMAInsts/expandMI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..681242c4773a3b226e28b9d9f636c3ff775e02d0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandSDMAInsts/expandMI.cpp @@ -0,0 +1,61 @@ +bool RISCVExpandSDMA::expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, MachineBasicBlock::iterator &NextMBBI) { + if (MBBI->getOpcode() == RISCV::PseudoSDMAOned) { + DebugLoc DL = MBBI->getDebugLoc(); + MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); + LLVM_DEBUG(dbgs() << "-- Expanding SDMA Oned\n"); + Register R = MRI.createVirtualRegister(&RISCV::GPRRegClass); + BuildMI(MBB, MBBI, DL, TII->get(RISCV::ANDI), R).addReg(MBBI->getOperand(6).getReg(), 0).addImm(~(0x1<<1)); + BuildMI(MBB, MBBI, DL, TII->get(RISCV::DMSRC)).addReg(MBBI->getOperand(2).getReg(), 0).addReg(MBBI->getOperand(1).getReg(), 0); + BuildMI(MBB, MBBI, DL, TII->get(RISCV::DMDST)).addReg(MBBI->getOperand(4).getReg(), 0).addReg(MBBI->getOperand(3).getReg(), 0); + BuildMI(MBB, MBBI, DL, TII->get(RISCV::DMCPY), MBBI->getOperand(0).getReg()).addReg(MBBI->getOperand(5).getReg(), 0).addReg(R, RegState::Kill); + MBBI->eraseFromParent(); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoSDMATwod) { + DebugLoc DL = MBBI->getDebugLoc(); + MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); + LLVM_DEBUG(dbgs() << "-- Expanding SDMA Twod\n"); + Register R = MRI.createVirtualRegister(&RISCV::GPRRegClass); + BuildMI(MBB, MBBI, DL, TII->get(RISCV::ORI), R).addReg(MBBI->getOperand(9).getReg(), 0).addImm(0x1<<1); + BuildMI(MBB, MBBI, DL, TII->get(RISCV::DMSRC)).addReg(MBBI->getOperand(2).getReg(), 0)ptrlo.addReg(MBBI->getOperand(1).getReg(), 0); + BuildMI(MBB, MBBI, DL, TII->get(RISCV::DMDST)).addReg(MBBI->getOperand(4).getReg(), 0).addReg(MBBI->getOperand(3).getReg(), 0); + BuildMI(MBB, MBBI, DL, TII->get(RISCV::DMSTR)).addReg(MBBI->getOperand(6).getReg(), 0).addReg(MBBI->getOperand(7).getReg(), 0); + BuildMI(MBB, MBBI, DL, TII->get(RISCV::DMREP)).addReg(MBBI->getOperand(8).getReg(), 0); + BuildMI(MBB, MBBI, DL, TII->get(RISCV::DMCPY), MBBI->getOperand(0).getReg()).addReg(MBBI->getOperand(5).getReg(), 0).addReg(R, RegState::Kill); + MBBI->eraseFromParent(); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoSDMAStat) { + DebugLoc DL = MBBI->getDebugLoc(); + LLVM_DEBUG(dbgs() << "-- Expanding SDMA Stat\n"); + BuildMI(MBB, MBBI, DL, TII->get(RISCV::DMSTAT), MBBI->getOperand(0).getReg()).addReg(MBBI->getOperand(1).getReg(), 0); + MBBI->eraseFromParent(); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoSDMAWaitForIdle) { + MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); + MachineInstr &MI = *MBBI; + MachineFunction *MF = MBB.getParent(); + DebugLoc DL = MI.getDebugLoc(); + LLVM_DEBUG(dbgs() << "-- Expanding SDMA WaitForIdle\n"); + auto LoopMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + auto DoneMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + MF->insert(++MBB.getIterator(), LoopMBB); + MF->insert(++LoopMBB->getIterator(), DoneMBB); + LoopMBB->addSuccessor(LoopMBB); + LoopMBB->addSuccessor(DoneMBB); + DoneMBB->splice(DoneMBB->end(), &MBB, MI, MBB.end()); + DoneMBB->transferSuccessorsAndUpdatePHIs(&MBB); + MBB.addSuccessor(LoopMBB); + Register R = MRI.createVirtualRegister(&RISCV::GPRRegClass); + BuildMI(LoopMBB, DL, TII->get(RISCV::DMSTATI), R).addImm(2); + BuildMI(LoopMBB, DL, TII->get(RISCV::BNE)).addReg(R, RegState::Kill).addReg(RISCV::X0).addMBB(LoopMBB); + NextMBBI = MBB.end(); + MI.eraseFromParent(); + LivePhysRegs LiveRegs; + computeAndAddLiveIns(LiveRegs, *LoopMBB); + computeAndAddLiveIns(LiveRegs, *DoneMBB); + return true; + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandSDMAInsts/getPassName.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandSDMAInsts/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c094c34ef5d1fd305dc401a3e1413acf34759e4e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandSDMAInsts/getPassName.cpp @@ -0,0 +1,3 @@ +StringRef getPassName() const override { + return RISCV_EXPAND_SDMA_NAME; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandSDMAInsts/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandSDMAInsts/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9f71fa5b49af1d0ab2f9c296ed43b40ffd886ffe --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandSDMAInsts/runOnMachineFunction.cpp @@ -0,0 +1,8 @@ +bool RISCVExpandSDMA::runOnMachineFunction(MachineFunction &MF) { + TII = static_cast(MF.getSubtarget().getInstrInfo()); + bool Modified = false; + for (auto &MBB : MF) { + Modified = Modified | expandMBB(MBB); + } + return Modified; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandSSRInsts/ExpandSSR.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandSSRInsts/ExpandSSR.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fa757aa1fd9eaedaca391e3d7e85b7cbdce96b27 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandSSRInsts/ExpandSSR.cpp @@ -0,0 +1,4 @@ +//zmCorrectzm +RISCVExpandSSR() : MachineFunctionPass(ID) { + initializeRISCVExpandSSRPass(*PassRegistry::getPassRegistry()); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandSSRInsts/ExpandSSRInsts.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandSSRInsts/ExpandSSRInsts.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e0cd667c35d872f8b0ed94ea4bf39d5056ccccc0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandSSRInsts/ExpandSSRInsts.cpp @@ -0,0 +1,3 @@ +RISCVExpandSSR() : MachineFunctionPass(ID) { + initializeRISCVExpandSSRPass(*PassRegistry::getPassRegistry()); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandSSRInsts/createPass.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandSSRInsts/createPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6280ff6c1be633c97c314bc1dc10a30b219e0241 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandSSRInsts/createPass.cpp @@ -0,0 +1,3 @@ +FunctionPass *createRISCVExpandSSRPass() { + return new RISCVExpandSSR(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandSSRInsts/expandMBB.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandSSRInsts/expandMBB.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a997a16d030ddf0b257b91a307ab7bdbd487b8ce --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandSSRInsts/expandMBB.cpp @@ -0,0 +1,10 @@ +bool RISCVExpandSSR::expandMBB(MachineBasicBlock &MBB) { + bool Modified = false; + MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end(); + while (MBBI != E) { + MachineBasicBlock::iterator NMBBI = std::next(MBBI); + Modified |= expandMI(MBB, MBBI, NMBBI); + MBBI = NMBBI; + } + return Modified; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandSSRInsts/expandMI.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandSSRInsts/expandMI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4b06fd082fe52899681cfb7f8ec5c12450df50c9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandSSRInsts/expandMI.cpp @@ -0,0 +1,302 @@ +bool RISCVExpandSSR::expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, MachineBasicBlock::iterator &NextMBBI) { + if (MBBI->getOpcode() == RISCV::PseudoSSRSetup_1D_R) { + DebugLoc DL = MBBI->getDebugLoc(); + LLVM_DEBUG(dbgs() << "-- Expanding SSR Setup 1D\n"); + int dm_off = (int)MBBI->getOperand(0).getImm(); + Register RepReg = MBBI->getOperand(1).getReg(); + BuildMI(MBB, MBBI, DL, TII->get(RISCV::SCFGWI)).addReg(RepReg).addImm(dm_off+(0x1<<5)); + Register BoundReg = MBBI->getOperand(2).getReg(); + BuildMI(MBB, MBBI, DL, TII->get(RISCV::SCFGWI)).addReg(BoundReg).addImm(dm_off+(0x2<<5)); + Register StrideReg = MBBI->getOperand(3).getReg(); + BuildMI(MBB, MBBI, DL, TII->get(RISCV::SCFGWI)).addReg(StrideReg).addImm(dm_off+(0x6<<5)); + Register PtrReg = MBBI->getOperand(4).getReg(); + if(MBBI->getOpcode() == RISCV::PseudoSSRSetup_1D_R) { + BuildMI(MBB, MBBI, DL, TII->get(RISCV::SCFGWI)).addReg(PtrReg).addImm(dm_off+(0x18<<5)); + } + if(MBBI->getOpcode() == RISCV::PseudoSSRSetup_1D_W) { + BuildMI(MBB, MBBI, DL, TII->get(RISCV::SCFGWI)).addReg(PtrReg).addImm(dm_off+(0x1c<<5)); + } + MBBI->eraseFromParent(); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoSSRSetup_1D_W) { + DebugLoc DL = MBBI->getDebugLoc(); + LLVM_DEBUG(dbgs() << "-- Expanding SSR Setup 1D\n"); + int dm_off = (int)MBBI->getOperand(0).getImm(); + Register RepReg = MBBI->getOperand(1).getReg(); + BuildMI(MBB, MBBI, DL, TII->get(RISCV::SCFGWI)).addReg(RepReg).addImm(dm_off+(0x1<<5)); + Register BoundReg = MBBI->getOperand(2).getReg(); + BuildMI(MBB, MBBI, DL, TII->get(RISCV::SCFGWI)).addReg(BoundReg).addImm(dm_off+(0x2<<5)); + Register StrideReg = MBBI->getOperand(3).getReg(); + BuildMI(MBB, MBBI, DL, TII->get(RISCV::SCFGWI)).addReg(StrideReg).addImm(dm_off+(0x6<<5)); + Register PtrReg = MBBI->getOperand(4).getReg(); + if(MBBI->getOpcode() == RISCV::PseudoSSRSetup_1D_R) { + BuildMI(MBB, MBBI, DL, TII->get(RISCV::SCFGWI)).addReg(PtrReg).addImm(dm_off+(0x18<<5)); + } + if(MBBI->getOpcode() == RISCV::PseudoSSRSetup_1D_W) { + BuildMI(MBB, MBBI, DL, TII->get(RISCV::SCFGWI)).addReg(PtrReg).addImm(dm_off+(0x1c<<5)); + } + MBBI->eraseFromParent(); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoSSRPush) { + DebugLoc DL = MBBI->getDebugLoc(); + bool isPop = MBBI->getOpcode() == RISCV::PseudoSSRPop; + unsigned ssrArgIdx = MBBI->getOpcode() == RISCV::PseudoSSRPush ? 0 : 1; + unsigned ssrValIdx = ssrArgIdx^1; + unsigned streamer = (unsigned)MBBI->getOperand(ssrArgIdx).getImm(); + Register R = getSSRFtReg(streamer); + LLVM_DEBUG(dbgs() << "-- Expanding SSR " << (isPop?"Pop":"Push") << "\n"); + LLVM_DEBUG(dbgs() << " Using register " << R << " for SSR streamer "<get(RISCV::FSGNJ_D), MBBI->getOperand(ssrValIdx).getReg()).addReg(R, 0).addReg(R, 0); + } + else { + BuildMI(MBB, MBBI, DL, TII->get(RISCV::FSGNJ_D), R).addReg(MBBI->getOperand(ssrValIdx).getReg()).addReg(MBBI->getOperand(ssrValIdx).getReg()); + } + MBB.addLiveIn(R); + MBBI->eraseFromParent(); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoSSRPop) { + DebugLoc DL = MBBI->getDebugLoc(); + bool isPop = MBBI->getOpcode() == RISCV::PseudoSSRPop; + unsigned ssrArgIdx = MBBI->getOpcode() == RISCV::PseudoSSRPush ? 0 : 1; + unsigned ssrValIdx = ssrArgIdx^1; + unsigned streamer = (unsigned)MBBI->getOperand(ssrArgIdx).getImm(); + Register R = getSSRFtReg(streamer); + LLVM_DEBUG(dbgs() << "-- Expanding SSR " << (isPop?"Pop":"Push") << "\n"); + LLVM_DEBUG(dbgs() << " Using register " << R << " for SSR streamer "<get(RISCV::FSGNJ_D), MBBI->getOperand(ssrValIdx).getReg()).addReg(R, 0).addReg(R, 0); + } + else { + BuildMI(MBB, MBBI, DL, TII->get(RISCV::FSGNJ_D), R).addReg(MBBI->getOperand(ssrValIdx).getReg()).addReg(MBBI->getOperand(ssrValIdx).getReg()); + } + MBB.addLiveIn(R); + MBBI->eraseFromParent(); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoSSRRead) { + DebugLoc DL = MBBI->getDebugLoc(); + bool isRead = MBBI->getOpcode() == RISCV::PseudoSSRRead; + MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); + Register dm_off_reg = (int)MBBI->getOperand(0).getReg(); + Register dim_off_reg = (int)MBBI->getOperand(1).getReg(); + int rw_off = isRead ? 0x18 : 0x1c; + Register dim_off0 = MRI.createVirtualRegister(&RISCV::GPRRegClass); + BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), dim_off0).addReg(dim_off_reg).addImm(rw_off); + Register dim_off1 = MRI.createVirtualRegister(&RISCV::GPRRegClass); + BuildMI(MBB, MBBI, DL, TII->get(RISCV::SLLI), dim_off1).addReg(dim_off0).addImm(5); + Register dim_off2 = MRI.createVirtualRegister(&RISCV::GPRRegClass); + BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADD), dim_off2).addReg(dim_off1).addReg(dm_off_reg); + Register PtrReg = MBBI->getOperand(2).getReg(); + BuildMI(MBB, MBBI, DL, TII->get(RISCV::SCFGW)).addReg(PtrReg).addReg(dim_off2); + MBBI->eraseFromParent(); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoSSRWrite) { + DebugLoc DL = MBBI->getDebugLoc(); + bool isRead = MBBI->getOpcode() == RISCV::PseudoSSRRead; + MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); + Register dm_off_reg = (int)MBBI->getOperand(0).getReg(); + Register dim_off_reg = (int)MBBI->getOperand(1).getReg(); + int rw_off = isRead ? 0x18 : 0x1c; + Register dim_off0 = MRI.createVirtualRegister(&RISCV::GPRRegClass); + BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), dim_off0).addReg(dim_off_reg).addImm(rw_off); + Register dim_off1 = MRI.createVirtualRegister(&RISCV::GPRRegClass); + BuildMI(MBB, MBBI, DL, TII->get(RISCV::SLLI), dim_off1).addReg(dim_off0).addImm(5); + Register dim_off2 = MRI.createVirtualRegister(&RISCV::GPRRegClass); + BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADD), dim_off2).addReg(dim_off1).addReg(dm_off_reg); + Register PtrReg = MBBI->getOperand(2).getReg(); + BuildMI(MBB, MBBI, DL, TII->get(RISCV::SCFGW)).addReg(PtrReg).addReg(dim_off2); + MBBI->eraseFromParent(); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoSSRReadImm) { + DebugLoc DL = MBBI->getDebugLoc(); + bool read = MBBI->getOpcode() == RISCV::PseudoSSRReadImm; + int dm_off = (int)MBBI->getOperand(0).getImm(); + int dim = (int)MBBI->getOperand(1).getImm(); + int ssr_reg = (((read ? 0x18 : 0x1c) + dim) << 5) + dm_off; + Register PtrReg = MBBI->getOperand(2).getReg(); + BuildMI(MBB, MBBI, DL, TII->get(RISCV::SCFGWI)).addReg(PtrReg).addImm(ssr_reg); + MBBI->eraseFromParent(); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoSSRWriteImm) { + DebugLoc DL = MBBI->getDebugLoc(); + bool read = MBBI->getOpcode() == RISCV::PseudoSSRReadImm; + int dm_off = (int)MBBI->getOperand(0).getImm(); + int dim = (int)MBBI->getOperand(1).getImm(); + int ssr_reg = (((read ? 0x18 : 0x1c) + dim) << 5) + dm_off; + Register PtrReg = MBBI->getOperand(2).getReg(); + BuildMI(MBB, MBBI, DL, TII->get(RISCV::SCFGWI)).addReg(PtrReg).addImm(ssr_reg); + MBBI->eraseFromParent(); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoSSRSetupBoundStride_1D) { + unsigned dim; + DebugLoc DL = MBBI->getDebugLoc(); + MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); + if(MBBI->getOpcode() == RISCV::PseudoSSRSetupBoundStride_1D) dim = 1; + if(MBBI->getOpcode() == RISCV::PseudoSSRSetupBoundStride_2D) dim = 2; + if(MBBI->getOpcode() == RISCV::PseudoSSRSetupBoundStride_3D) dim = 3; + if(MBBI->getOpcode() == RISCV::PseudoSSRSetupBoundStride_4D) dim = 4; + LLVM_DEBUG(dbgs() << "-- Expanding SSR Bound Stride " << dim << "D\n"); + Register dm_off_reg = MBBI->getOperand(0).getReg(); + Register addr_bound = MRI.createVirtualRegister(&RISCV::GPRRegClass); + Register addr_stride = MRI.createVirtualRegister(&RISCV::GPRRegClass); + BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), addr_bound).addReg(dm_off_reg).addImm( ((2+(dim-1))<<5)); + BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), addr_stride).addReg(dm_off_reg).addImm( ((6+(dim-1))<<5)); + Register BoundReg = MBBI->getOperand(1).getReg(); + BuildMI(MBB, MBBI, DL, TII->get(RISCV::SCFGW)).addReg(BoundReg).addReg(addr_bound, RegState::Kill); + Register StrideReg = MBBI->getOperand(2).getReg(); + BuildMI(MBB, MBBI, DL, TII->get(RISCV::SCFGW)).addReg(StrideReg).addReg(addr_stride, RegState::Kill); + MBBI->eraseFromParent(); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoSSRSetupBoundStride_2D) { + unsigned dim; + DebugLoc DL = MBBI->getDebugLoc(); + MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); + if(MBBI->getOpcode() == RISCV::PseudoSSRSetupBoundStride_1D) dim = 1; + if(MBBI->getOpcode() == RISCV::PseudoSSRSetupBoundStride_2D) dim = 2; + if(MBBI->getOpcode() == RISCV::PseudoSSRSetupBoundStride_3D) dim = 3; + if(MBBI->getOpcode() == RISCV::PseudoSSRSetupBoundStride_4D) dim = 4; + LLVM_DEBUG(dbgs() << "-- Expanding SSR Bound Stride " << dim << "D\n"); + Register dm_off_reg = MBBI->getOperand(0).getReg(); + Register addr_bound = MRI.createVirtualRegister(&RISCV::GPRRegClass); + Register addr_stride = MRI.createVirtualRegister(&RISCV::GPRRegClass); + BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), addr_bound).addReg(dm_off_reg).addImm( ((2+(dim-1))<<5)); + BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), addr_stride).addReg(dm_off_reg).addImm( ((6+(dim-1))<<5)); + Register BoundReg = MBBI->getOperand(1).getReg(); + BuildMI(MBB, MBBI, DL, TII->get(RISCV::SCFGW)).addReg(BoundReg).addReg(addr_bound, RegState::Kill); + Register StrideReg = MBBI->getOperand(2).getReg(); + BuildMI(MBB, MBBI, DL, TII->get(RISCV::SCFGW)).addReg(StrideReg).addReg(addr_stride, RegState::Kill); + MBBI->eraseFromParent(); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoSSRSetupBoundStride_3D) { + unsigned dim; + DebugLoc DL = MBBI->getDebugLoc(); + MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); + if(MBBI->getOpcode() == RISCV::PseudoSSRSetupBoundStride_1D) dim = 1; + if(MBBI->getOpcode() == RISCV::PseudoSSRSetupBoundStride_2D) dim = 2; + if(MBBI->getOpcode() == RISCV::PseudoSSRSetupBoundStride_3D) dim = 3; + if(MBBI->getOpcode() == RISCV::PseudoSSRSetupBoundStride_4D) dim = 4; + LLVM_DEBUG(dbgs() << "-- Expanding SSR Bound Stride " << dim << "D\n"); + Register dm_off_reg = MBBI->getOperand(0).getReg(); + Register addr_bound = MRI.createVirtualRegister(&RISCV::GPRRegClass); + Register addr_stride = MRI.createVirtualRegister(&RISCV::GPRRegClass); + BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), addr_bound).addReg(dm_off_reg).addImm( ((2+(dim-1))<<5)); + BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), addr_stride).addReg(dm_off_reg).addImm( ((6+(dim-1))<<5)); + Register BoundReg = MBBI->getOperand(1).getReg(); + BuildMI(MBB, MBBI, DL, TII->get(RISCV::SCFGW)).addReg(BoundReg).addReg(addr_bound, RegState::Kill); + Register StrideReg = MBBI->getOperand(2).getReg(); + BuildMI(MBB, MBBI, DL, TII->get(RISCV::SCFGW)).addReg(StrideReg).addReg(addr_stride, RegState::Kill); + MBBI->eraseFromParent(); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoSSRSetupBoundStride_4D) { + unsigned dim; + DebugLoc DL = MBBI->getDebugLoc(); + MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); + if(MBBI->getOpcode() == RISCV::PseudoSSRSetupBoundStride_1D) dim = 1; + if(MBBI->getOpcode() == RISCV::PseudoSSRSetupBoundStride_2D) dim = 2; + if(MBBI->getOpcode() == RISCV::PseudoSSRSetupBoundStride_3D) dim = 3; + if(MBBI->getOpcode() == RISCV::PseudoSSRSetupBoundStride_4D) dim = 4; + LLVM_DEBUG(dbgs() << "-- Expanding SSR Bound Stride " << dim << "D\n"); + Register dm_off_reg = MBBI->getOperand(0).getReg(); + Register addr_bound = MRI.createVirtualRegister(&RISCV::GPRRegClass); + Register addr_stride = MRI.createVirtualRegister(&RISCV::GPRRegClass); + BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), addr_bound).addReg(dm_off_reg).addImm( ((2+(dim-1))<<5)); + BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), addr_stride).addReg(dm_off_reg).addImm( ((6+(dim-1))<<5)); + Register BoundReg = MBBI->getOperand(1).getReg(); + BuildMI(MBB, MBBI, DL, TII->get(RISCV::SCFGW)).addReg(BoundReg).addReg(addr_bound, RegState::Kill); + Register StrideReg = MBBI->getOperand(2).getReg(); + BuildMI(MBB, MBBI, DL, TII->get(RISCV::SCFGW)).addReg(StrideReg).addReg(addr_stride, RegState::Kill); + MBBI->eraseFromParent(); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoSSREnable) { + DebugLoc DL = MBBI->getDebugLoc(); + bool isEnable = MBBI->getOpcode() == RISCV::PseudoSSREnable; + MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); + LLVM_DEBUG(dbgs() << "-- Expanding SSR " << (isEnable ? "Enable" : "Disable") << "\n"); + Enabled = isEnable; + if(isEnable) { + BuildMI(MBB, MBBI, DL, TII->get(RISCV::CSRRSI)).addDef(MRI.createVirtualRegister(&RISCV::GPRRegClass), RegState::Dead).addImm(0x7C0).addImm(1); + unsigned ssrEnabledMask = 0; + for (unsigned n = 0; n != 3; ++n) { + ssrEnabledMask |= 1 << n; + } + RVFI->setUsedSSR(ssrEnabledMask); + } + else { + BuildMI(MBB, MBBI, DL, TII->get(RISCV::CSRRCI)).addDef(MRI.createVirtualRegister(&RISCV::GPRRegClass), RegState::Dead).addImm(0x7C0).addImm(1); + } + MBBI->eraseFromParent(); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoSSRDisable) { + DebugLoc DL = MBBI->getDebugLoc(); + bool isEnable = MBBI->getOpcode() == RISCV::PseudoSSREnable; + MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); + LLVM_DEBUG(dbgs() << "-- Expanding SSR " << (isEnable ? "Enable" : "Disable") << "\n"); + Enabled = isEnable; + if(isEnable) { + BuildMI(MBB, MBBI, DL, TII->get(RISCV::CSRRSI)).addDef(MRI.createVirtualRegister(&RISCV::GPRRegClass), RegState::Dead).addImm(0x7C0).addImm(1); + unsigned ssrEnabledMask = 0; + for (unsigned n = 0; n != 3; ++n) { + ssrEnabledMask |= 1 << n; + } + RVFI->setUsedSSR(ssrEnabledMask); + } + else { + BuildMI(MBB, MBBI, DL, TII->get(RISCV::CSRRCI)).addDef(MRI.createVirtualRegister(&RISCV::GPRRegClass), RegState::Dead).addImm(0x7C0).addImm(1); + } + MBBI->eraseFromParent(); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoSSRSetupRepetition) { + DebugLoc DL = MBBI->getDebugLoc(); + MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); + Register dm_off_reg = MBBI->getOperand(0).getReg(); + Register dm_off = MRI.createVirtualRegister(&RISCV::GPRRegClass); + BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), dm_off).addReg(dm_off_reg).addImm(1<<5); + Register PtrReg = MBBI->getOperand(1).getReg(); + BuildMI(MBB, MBBI, DL, TII->get(RISCV::SCFGW)).addReg(PtrReg).addReg(dm_off, RegState::Kill); + MBBI->eraseFromParent(); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoSSRBarrier) { + DebugLoc DL = MBBI->getDebugLoc(); + MachineInstr &MI = *MBBI; + MachineFunction *MF = MBB.getParent(); + MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); + unsigned streamer = (unsigned)MBBI->getOperand(0).getImm(); + LLVM_DEBUG(dbgs() << "-- Expanding SSR barrier on DM" << streamer << "\n"); + auto LoopMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + auto DoneMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + MF->insert(++MBB.getIterator(), LoopMBB); + MF->insert(++LoopMBB->getIterator(), DoneMBB); + LoopMBB->addSuccessor(LoopMBB); + LoopMBB->addSuccessor(DoneMBB); + DoneMBB->splice(DoneMBB->end(), &MBB, MI, MBB.end()); + DoneMBB->transferSuccessorsAndUpdatePHIs(&MBB); + MBB.addSuccessor(LoopMBB); + Register R = MRI.createVirtualRegister(&RISCV::GPRRegClass); + BuildMI(LoopMBB, DL, TII->get(RISCV::SCFGRI), R).addImm(streamer); + Register Rs = MRI.createVirtualRegister(&RISCV::GPRRegClass); + BuildMI(LoopMBB, DL, TII->get(RISCV::SRLI), Rs).addReg(R, RegState::Kill).addImm(31); + BuildMI(LoopMBB, DL, TII->get(RISCV::BEQ)).addReg(Rs, RegState::Kill).addReg(RISCV::X0).addMBB(LoopMBB); + NextMBBI = MBB.end(); + MI.eraseFromParent(); + LivePhysRegs LiveRegs; + computeAndAddLiveIns(LiveRegs, *LoopMBB); + computeAndAddLiveIns(LiveRegs, *DoneMBB); + return true; + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandSSRInsts/getPassName.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandSSRInsts/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..672b213111956debf86d2957f386a2b270e8ec5c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandSSRInsts/getPassName.cpp @@ -0,0 +1,3 @@ +StringRef getPassName() const override { + return RISCV_EXPAND_SSR_NAME; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandSSRInsts/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandSSRInsts/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..136ded60ddd72eb7afb3b38d4783db5202002f71 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/ExpandSSRInsts/runOnMachineFunction.cpp @@ -0,0 +1,70 @@ +bool RISCVExpandSSR::runOnMachineFunction(MachineFunction &MF) { + TII = static_cast(MF.getSubtarget().getInstrInfo()); + bool Modified = false; + this->MF = &MF; + this->RVFI = MF.getInfo(); + Enabled = false; + for (auto &MBB : MF) { + Modified |= expandMBB(MBB); + } + RISCVExpandSSR::RegisterMergingPreferences RMP; + RMP.Enable = true; + if (SSRRegisterMerge.getNumOccurrences() > 0) + RMP.Enable = !SSRRegisterMerge; + LLVM_DEBUG(dbgs() << "RMP Enable "<getUsedSSR()) + for (auto &MBB : MF) + SmallSet virtRegs[NUM_SSR]; + const TargetRegisterInfo *TRI = MBB.getParent()->getRegInfo().getTargetRegisterInfo(); + bool inSSRRegion = false; + Register ssr_regs[NUM_SSR]; + for(unsigned ssr_no = 0; ssr_no < NUM_SSR; ++ssr_no) ssr_regs[ssr_no] = getSSRFtReg(ssr_no); + for (auto MI = MBB.begin() ; MI != MBB.end() ; ) { + MachineBasicBlock::iterator NMI = std::next(MI); + LLVM_DEBUG(dbgs()<<"Analyzing: "<<*MI<<"\n"); + if(MI->getOpcode() == RISCV::FSGNJ_D) { + LLVM_DEBUG(dbgs()<<"Found FSGNJ_D, Op 0: " << MI->getOperand(1).getReg() << " Op1: " << MI->getOperand(2).getReg() << "\n"); + for(unsigned ssr_no = 0; ssr_no < NUM_SSR; ++ssr_no) { + if(MI->getOperand(1).getReg() == ssr_regs[ssr_no] && MI->getOperand(2).getReg() == ssr_regs[ssr_no]) { + LLVM_DEBUG(dbgs()<<" pop: both operands from SSR"<< ssr_no <<"\n"); + LLVM_DEBUG(dbgs()<<" append: "<< MI->getOperand(0).getReg() <<"\n"); + virtRegs[ssr_no].insert(MI->getOperand(0).getReg()); + MI->eraseFromParent(); + break; + } + else if(MI->getOperand(0).getReg() == ssr_regs[ssr_no]) { + break; + } + } + } + MI = NMI; + } + for(unsigned ssr_no = 0; ssr_no < NUM_SSR; ++ssr_no) { + for (auto iter = virtRegs[ssr_no].begin() ; iter != virtRegs[ssr_no].end() ; ++iter) + LLVM_DEBUG(dbgs() << "virtregs["<operands_begin() ; operand != MI->operands_end() ; ++operand) { + if(!operand->isReg()) continue; + for(unsigned ssr_no = 0; ssr_no < NUM_SSR; ++ssr_no) { + if(virtRegs[ssr_no].contains(operand->getReg())) { + LLVM_DEBUG(dbgs() << "Found use of operand " << operand->getReg() << " ssr: " << ssr_no << " in inst " << MI->getOpcode() << "\n"); + MI->substituteRegister(operand->getReg(), ssr_regs[ssr_no], 0, *TRI); + MBB.addLiveIn(ssr_regs[ssr_no]); + } + } + } + MI = NMI; + } + MBB.sortUniqueLiveIns(); + if(Modified) { + for (auto &MBB : MF) { + for(unsigned ssr_no = 0; ssr_no < NUM_SSR; ++ssr_no) + MBB.addLiveIn(getSSRFtReg(ssr_no)); + MBB.sortUniqueLiveIns(); + } + } + return Modified; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/MergeBaseOffset/MergeBaseOffsetOpt.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/MergeBaseOffset/MergeBaseOffsetOpt.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0335a4ef79ccad687d71bd1e7dfc446f4a07fe4b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/MergeBaseOffset/MergeBaseOffsetOpt.cpp @@ -0,0 +1,2 @@ +RISCVMergeBaseOffsetOpt() : MachineFunctionPass(ID) { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/MergeBaseOffset/createPass.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/MergeBaseOffset/createPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4f8195dd1360a5a7264e251088fea5e7dbc2d24d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/MergeBaseOffset/createPass.cpp @@ -0,0 +1,3 @@ +FunctionPass *llvm::createRISCVMergeBaseOffsetOptPass() { + return new RISCVMergeBaseOffsetOpt(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/MergeBaseOffset/getPassName.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/MergeBaseOffset/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..658f61cc76c6f58d97dbc4a3fa9d383799c42b6e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/MergeBaseOffset/getPassName.cpp @@ -0,0 +1,3 @@ +StringRef getPassName() const override { + return RISCV_MERGE_BASE_OFFSET_NAME; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/MergeBaseOffset/getRequiredProperties.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/MergeBaseOffset/getRequiredProperties.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b5b9c0930d3d58a2f4601a4830a241ebb30ca4fd --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/MergeBaseOffset/getRequiredProperties.cpp @@ -0,0 +1,3 @@ +MachineFunctionProperties getRequiredProperties() const override { + return MachineFunctionProperties().set(MachineFunctionProperties::Property::IsSSA); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/MergeBaseOffset/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/MergeBaseOffset/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..644005710c1b1a6bbf091cf43572a6d616d21b78 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/MergeBaseOffset/runOnMachineFunction.cpp @@ -0,0 +1,121 @@ +bool RISCVMergeBaseOffsetOpt::runOnMachineFunction(MachineFunction &Fn) { + if (skipFunction(*F.getFunction())) { + return false; + } + DeadInstrs.clear(); + MRI = &Fn.getRegInfo(); + for (MachineBasicBlock &MBB : Fn) { + LLVM_DEBUG(dbgs() << "MBB: " << MBB.getName() << "\n"); + for (MachineInstr &HiLUI : MBB) { + MachineInstr *LoADDI = nullptr; + if (HiLUI.getOpcode() != RISCV::LUI || HiLUI.getOperand(1).getTargetFlags() != RISCVII::MO_HI || HiLUI.getOperand(1).getType() != MachineOperand::MO_GlobalAddress || HiLUI.getOperand(1).getOffset() != 0 || !MRI->hasOneUse(HiLUI.getOperand(0).getReg())) + return false; + Register HiLuiDestReg = HiLUI.getOperand(0).getReg(); + LoADDI = MRI->use_begin(HiLuiDestReg)->getParent(); + if (LoADDI->getOpcode() != RISCV::ADDI || LoADDI->getOperand(2).getTargetFlags() != RISCVII::MO_LO || LoADDI->getOperand(2).getType() != MachineOperand::MO_GlobalAddress || LoADDI->getOperand(2).getOffset() != 0 || !MRI->hasOneUse(LoADDI->getOperand(0).getReg())) + return false; + continue + LLVM_DEBUG(dbgs() << " Found lowered global address with one use: " << *LoADDI->getOperand(2).getGlobal() << "\n"); + Register DestReg = LoADDI.getOperand(0).getReg(); + assert(MRI->hasOneUse(DestReg) && "expected one use for LoADDI"); + MachineInstr &Tail = *MRI->use_begin(DestReg)->getParent(); + switch (Tail.getOpcode()) { + default: + LLVM_DEBUG(dbgs() << "Don't know how to get offset from this instr:" << Tail); + return false; + case RISCV::ADDI: { + int64_t Offset = Tail.getOperand(2).getImm(); + LLVM_DEBUG(dbgs() << " Offset Instr: " << Tail); + HiLUI.getOperand(1).setOffset(Offset); + LoADDI.getOperand(2).setOffset(Offset); + DeadInstrs.insert(&Tail); + MRI->replaceRegWith(Tail.getOperand(0).getReg(), LoADDI.getOperand(0).getReg()); + LLVM_DEBUG(dbgs() << " Merged offset " << Offset << " into base.\n" << " " << HiLUI << " " << LoADDI;); + return true; + } break; + case RISCV::ADD: { + int64_t Offset; + assert((TailAdd.getOpcode() == RISCV::ADD) && "Expected ADD instruction!"); + Register Rs = TailAdd.getOperand(1).getReg(); + Register Rt = TailAdd.getOperand(2).getReg(); + Register Reg = Rs == GAReg ? Rt : Rs; + if (!MRI->hasOneUse(Reg)) + return false; + MachineInstr &OffsetTail = *MRI->getVRegDef(Reg); + if (OffsetTail.getOpcode() == RISCV::ADDI) { + MachineOperand &AddiImmOp = OffsetTail.getOperand(2); + if (AddiImmOp.getTargetFlags() != RISCVII::MO_None) + return false; + int64_t OffLo = AddiImmOp.getImm(); + MachineInstr &OffsetLui = *MRI->getVRegDef(OffsetTail.getOperand(1).getReg()); + MachineOperand &LuiImmOp = OffsetLui.getOperand(1); + if (OffsetLui.getOpcode() != RISCV::LUI || LuiImmOp.getTargetFlags() != RISCVII::MO_None || !MRI->hasOneUse(OffsetLui.getOperand(0).getReg())) + return false; + int64_t OffHi = OffsetLui.getOperand(1).getImm(); + Offset = (OffHi << 12) + OffLo; + LLVM_DEBUG(dbgs() << " Offset Instrs: " << OffsetTail << " " << OffsetLui); + DeadInstrs.insert(&OffsetTail); + DeadInstrs.insert(&OffsetLui); + return true; + } + else if (OffsetTail.getOpcode() == RISCV::LUI) { + LLVM_DEBUG(dbgs() << " Offset Instr: " << OffsetTail); + Offset = OffsetTail.getOperand(1).getImm() << 12; + DeadInstrs.insert(&OffsetTail); + return true; + } + return false; + if (!matchLargeOffset(Tail, DestReg, Offset)) { + return false; + } + HiLUI.getOperand(1).setOffset(Offset); + LoADDI.getOperand(2).setOffset(Offset); + DeadInstrs.insert(&Tail); + MRI->replaceRegWith(Tail.getOperand(0).getReg(), LoADDI.getOperand(0).getReg()); + LLVM_DEBUG(dbgs() << " Merged offset " << Offset << " into base.\n" << " " << HiLUI << " " << LoADDI;); + return true; + } + break; + case RISCV::LB: + case RISCV::LH: + case RISCV::LW: + case RISCV::LBU: + case RISCV::LHU: + case RISCV::LWU: + case RISCV::LD: + case RISCV::FLH: + case RISCV::FLW: + case RISCV::FLD: + case RISCV::SB: + case RISCV::SH: + case RISCV::SW: + case RISCV::SD: + case RISCV::FSH: + case RISCV::FSW: + case RISCV::FSD: { + if (Tail.getOperand(1).isFI()) { + return false; + } + Register BaseAddrReg = Tail.getOperand(1).getReg(); + if (DestReg != BaseAddrReg) + return false; + MachineOperand &TailImmOp = Tail.getOperand(2); + int64_t Offset = TailImmOp.getImm(); + HiLUI.getOperand(1).setOffset(Offset); + Tail.RemoveOperand(2); + MachineOperand &ImmOp = LoADDI.getOperand(2); + ImmOp.setOffset(Offset); + Tail.addOperand(ImmOp); + Tail.getOperand(1).setReg(HiLUI.getOperand(0).getReg()); + DeadInstrs.insert(&LoADDI); + return true; + } break; + } + return false; + } + } + for (auto *MI : DeadInstrs) { + MI->eraseFromParent(); + } + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPFixupHwLoops/FixupHwLoops.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPFixupHwLoops/FixupHwLoops.cpp new file mode 100644 index 0000000000000000000000000000000000000000..316b34c4cf0c8e5d9e4236ab94f33861df884864 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPFixupHwLoops/FixupHwLoops.cpp @@ -0,0 +1,3 @@ +PULPFixupHwLoops() : MachineFunctionPass(ID) { + initializePULPFixupHwLoopsPass(*PassRegistry::getPassRegistry()); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPFixupHwLoops/PULPFixupHwLoops.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPFixupHwLoops/PULPFixupHwLoops.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7c17fd5a279439a187f60893c6e3615c047d045e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPFixupHwLoops/PULPFixupHwLoops.cpp @@ -0,0 +1,4 @@ +//zmCorrectzm +PULPFixupHwLoops() : MachineFunctionPass(ID) { + initializePULPFixupHwLoopsPass(*PassRegistry::getPassRegistry()); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPFixupHwLoops/createPULPFixupHwLoops.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPFixupHwLoops/createPULPFixupHwLoops.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9228c6d2483d6a53cbfa3ed48c0366f7bb8826bb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPFixupHwLoops/createPULPFixupHwLoops.cpp @@ -0,0 +1,3 @@ +FunctionPass *llvm::createPULPFixupHwLoops() { + return new PULPFixupHwLoops(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPFixupHwLoops/createPass.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPFixupHwLoops/createPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b12c744298f9d869e8fc2ee963c1702dfb79d52e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPFixupHwLoops/createPass.cpp @@ -0,0 +1,4 @@ +//zmcorrectzm +FunctionPass *llvm::createPULPFixupHwLoops() { + return new PULPFixupHwLoops(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPFixupHwLoops/getAnalysisUsage.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPFixupHwLoops/getAnalysisUsage.cpp new file mode 100644 index 0000000000000000000000000000000000000000..52e0b136129998a3fd35a4b00d6233cf21f31d9e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPFixupHwLoops/getAnalysisUsage.cpp @@ -0,0 +1,5 @@ +void getAnalysisUsage(AnalysisUsage &AU) const override { + AU.setPreservesCFG(); + AU.addRequired(); + MachineFunctionPass::getAnalysisUsage(AU); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPFixupHwLoops/getPassName.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPFixupHwLoops/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..28206ae7e93f32080cb3f8c1934ca95818e47956 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPFixupHwLoops/getPassName.cpp @@ -0,0 +1,3 @@ +StringRef getPassName() const override { + return "PULP Hardware Loop Fixup"; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPFixupHwLoops/getRequiredProperties.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPFixupHwLoops/getRequiredProperties.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cd50d43365fe514848b8ee87b962013f4b925d4c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPFixupHwLoops/getRequiredProperties.cpp @@ -0,0 +1,3 @@ +MachineFunctionProperties getRequiredProperties() const override { + return MachineFunctionProperties().set(MachineFunctionProperties::Property::NoVRegs); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPFixupHwLoops/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPFixupHwLoops/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..52d9b95aa521daec482d8f52ef0cb71a19c18611 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPFixupHwLoops/runOnMachineFunction.cpp @@ -0,0 +1,289 @@ +bool PULPFixupHwLoops::runOnMachineFunction(MachineFunction &MF) { + if (skipFunction(MF.getFunction())) { + return false; + } + bool changed = false; + for (MachineBasicBlock &MBB : MF) { + for (MachineInstr &MI : MBB) { + if (isHardwareLoop(MI)) { + MachineInstr &Term = *(--MBB.end()); + if (Term.getDesc().isUnconditionalBranch()) { + assert(MBB.succ_size() == 1 && "Too many successors!"); + MachineBasicBlock *LoopStartMBB = *MBB.succ_begin(); + if (MBB.isLayoutSuccessor(LoopStartMBB)) { + Term.eraseFromParent(); + changed = true; + break; + } + } + } + } + } + bool changedNow = false; + bool changedOverall = false; + std::set toRemove; + do { + changedNow = false; + for (MachineBasicBlock &MBB : MF) { + for (MachineInstr &MI : MBB) { + if (isHardwareLoop(MI)) { + MachineLoopInfo *MLI = &getAnalysis(); + MachineBasicBlock *LastMBB = MI.getOperand(0).getMBB(); + MachineLoop *L = MLI->getLoopFor(LastMBB); + assert(L->contains(LastMBB) && "Loop does not contain LastMBB"); + if (L->getBottomBlock() != LastMBB) { + MachineBasicBlock *current = LastMBB; + bool reachedEnd = false; + while (current != L->getBottomBlock() && !reachedEnd) { + bool found = false; + for (MachineBasicBlock &succ : MF) { + if (current->isLayoutSuccessor(&succ) && L->getBlocksSet().find(&succ) != L->getBlocksSet().end()) { + current = ≻ + found = true; + break; + } + } + if (!found) { + reachedEnd = true; + } + } + if (current == L->getBottomBlock()) { + LastMBB = L->getBottomBlock(); + MachineOperand countMO = MI.getOperand(1); + MI.RemoveOperand(1); + MI.RemoveOperand(0); + MI.addOperand(MachineOperand::CreateMBB(LastMBB)); + MI.addOperand(countMO); + } + } + assert(L->getBottomBlock() == LastMBB && "Last is not Bottom"); + MachineBasicBlock *ExitBlock = L->getExitBlock(); + MachineBasicBlock::iterator LastI = LastMBB->getFirstTerminator(); + DebugLoc LastIDL = LastI->getDebugLoc(); + if (LastI != LastMBB->end()) { + if (LastI->getOpcode() == RISCV::BEQ || LastI->getOpcode() == RISCV::BNE || LastI->getOpcode() == RISCV::BLT || LastI->getOpcode() == RISCV::BGE || LastI->getOpcode() == RISCV::BLTU || LastI->getOpcode() == RISCV::BGEU || LastI->getOpcode() == RISCV::P_BNEIMM || LastI->getOpcode() == RISCV::P_BEQIMM) { + for (unsigned i = 0; i < LastI->getNumOperands(); i++) { + MachineOperand &MO = LastI->getOperand(i); + if (MO.isReg()) { + std::set regUsers; + if (fixupBump(LastMBB, &MI, MO.getReg(), regUsers)) { + if (regUsers.count(&(*LastI)) > 0) { + regUsers.erase(&(*LastI)); + } + if (regUsers.size() == 1) { + MachineInstr *Cand = (*regUsers.begin()); + if (Cand->getOpcode() == RISCV::ADD || Cand->getOpcode() == RISCV::ADDI || Cand->getOpcode() == RISCV::SUB) { + if (Cand->getOperand(0).isReg() && Cand->getOperand(1).isReg() && Cand->getOperand(0).getReg() == Cand->getOperand(1).getReg()) { + if (Cand->getParent()->size() <= 2) { + } + else { + toRemove.insert(Cand); + } + } + } + } + } + } + } + MachineBasicBlock *BranchTarget = LastI->getOperand(2).getMBB(); + LastI = LastMBB->erase(LastI); + if (BranchTarget == ExitBlock) { + if (LastI != LastMBB->end()) { + LastI = LastMBB->erase(LastI); + } + SmallVector Cond; + const RISCVSubtarget &HST = MF.getSubtarget(); + const RISCVInstrInfo *TII = HST.getInstrInfo(); + TII->insertBranch(*LastMBB, BranchTarget, nullptr, Cond, LastIDL); + changedNow = true; + changedOverall = true; + } + } + else if (LastI->getOpcode() == RISCV::PseudoBR) { + MachineBasicBlock *BranchTarget = LastI->getOperand(0).getMBB(); + if (BranchTarget == L->getHeader()) { + LastMBB->erase(LastI); + changedNow = true; + changedOverall = true; + } + } else { + llvm_unreachable("Unknown branch type!"); + } + } + } + if (changedNow) { + break; + } + } + if (changedNow) { + break; + } + } + } while (changedNow == true); + for (MachineInstr *MI : toRemove) { + MI->eraseFromParent(); + } + unsigned InstOffset = 0; + DenseMap BlockToInstOffset; + const RISCVInstrInfo *RII = static_cast(MF.getSubtarget().getInstrInfo()); + bool Changed = false; + for (MachineBasicBlock &MBB : MF) { + MachineBasicBlock::iterator MII = MBB.begin(); + MachineBasicBlock::iterator MIE = MBB.end(); + while (MII != MIE) { + if (MII->isMetaInstruction()) { + ++MII; + continue; + } + if (isHardwareLoop(*MII)) { + assert(MII->getOperand(0).isMBB() && "Expect a basic block as loop operand"); + MachineBasicBlock *LastMBB = MII->getOperand(0).getMBB(); + MachineBasicBlock::iterator instrToMove = --LastMBB->getFirstTerminator(); + if (instrToMove->isInlineAsm()) { + DebugLoc DL = instrToMove->getDebugLoc(); + BuildMI(*LastMBB, LastMBB->getFirstTerminator(), DL, RII->get(RISCV::ADDI)).addReg(RISCV::X0).addReg(RISCV::X0).addImm(0); + instrToMove = --LastMBB->getFirstTerminator(); + } + MachineBasicBlock::iterator firstPossibleMove = LastMBB->getFirstNonPHI(); + MachineFunction *MF = LastMBB->getParent(); + auto LoopEnd = MF->CreateMachineBasicBlock(); + MF->insert(++LastMBB->getIterator(), LoopEnd); + LoopEnd->transferSuccessors(LastMBB); + LastMBB->addSuccessor(LoopEnd); + while ((instrToMove->isTransient() || instrToMove->isBranch()) && instrToMove != firstPossibleMove) { + instrToMove--; + } + LoopEnd->splice(LoopEnd->begin(), LastMBB, instrToMove, LastMBB->end()); + LoopEnd->setLabelMustBeEmitted(); + DebugLoc DL = MII->getDebugLoc(); + MachineInstrBuilder MIB = BuildMI(*MII->getParent(), MII, DL, RII->get(MII->getOpcode())); + MIB.addMBB(LoopEnd); + MIB.add(MII->getOperand(1)); + MII = MII->getParent()->erase(MII); + } else { + ++MII; + } + } + } + for (const MachineBasicBlock &MBB : MF) { + BlockToInstOffset[&MBB] = InstOffset; + for (const MachineInstr &MI : MBB) { + InstOffset += getMISize(MI); + } + } + for (MachineBasicBlock &MBB : MF) { + InstOffset = BlockToInstOffset[&MBB]; + MachineBasicBlock::iterator MII = MBB.begin(); + MachineBasicBlock::iterator MIE = MBB.end(); + while (MII != MIE) { + unsigned InstSize = getMISize(*MII); + if (MII->isMetaInstruction()) { + ++MII; + continue; + } + if (isHardwareLoop(*MII)) { + bool offsetIncrease = 0; + assert(MII->getOperand(0).isMBB() && "Expect a basic block as loop operand"); + MachineBasicBlock *TargetBB = MII->getOperand(0).getMBB(); + unsigned Diff = AbsoluteDifference(InstOffset, BlockToInstOffset[TargetBB]); + signed LoopLen = Diff - getMISize(*MII); + MachineBasicBlock::iterator inspt = MII; + DebugLoc DL = inspt->getDebugLoc(); + inspt++; + if (isHardwareLoopImm(*MII) && LoopLen > MaxLoopRangeImm) { + assert(MBB.succ_size() == 1 && "Too many successors!"); + assert(isHardwareLoopZero(*MII) || isHardwareLoopOne(*MII)); + MachineBasicBlock *LoopStartMBB = *MBB.succ_begin(); + MachineInstrBuilder Start; + MachineInstrBuilder End; + MachineInstrBuilder Count; + if (isHardwareLoopZero(*MII)) { + Start = BuildMI(MBB, inspt, DL, RII->get(RISCV::LOOP0starti)).addMBB(LoopStartMBB); + End = BuildMI(MBB, inspt, DL, RII->get(RISCV::LOOP0endi)).addMBB(TargetBB); + Count = BuildMI(MBB, inspt, DL, RII->get(RISCV::LOOP0counti)).addImm(MII->getOperand(1).getImm()); + } + else if (isHardwareLoopOne(*MII)) { + Start = BuildMI(MBB, inspt, DL, RII->get(RISCV::LOOP1starti)).addMBB(LoopStartMBB); + End = BuildMI(MBB, inspt, DL, RII->get(RISCV::LOOP1endi)).addMBB(TargetBB); + Count = BuildMI(MBB, inspt, DL, RII->get(RISCV::LOOP1counti)).addImm(MII->getOperand(1).getImm()); + } + LoopLen += getMISize(*Start.getInstr()); + offsetIncrease += getMISize(*Start.getInstr()); + LoopLen += getMISize(*End.getInstr()); + offsetIncrease += getMISize(*Start.getInstr()); + LoopLen += getMISize(*Count.getInstr()); + offsetIncrease += getMISize(*Start.getInstr()); + LoopLen -= getMISize(*MII); + offsetIncrease -= getMISize(*MII); + LoopStartMBB->setHasAddressTaken(); + LoopStartMBB->setLabelMustBeEmitted(); + BlockAddress::get(const_cast(LoopStartMBB->getBasicBlock())); + MII->eraseFromParent(); + } + if (isHardwareLoopReg(*MII) && LoopLen > MaxLoopRangeReg) { + errs().changeColor(raw_fd_ostream::Colors::RED, true); + errs() << "UNHANDLED: Hardware Loop length " << LoopLen << " is " << "higher than limit for lp.setup: " << MaxLoopRangeReg << "\n"; + errs().resetColor(); + abort(); + } + if (LoopLen < 4) { + while (LoopLen < 4) { + MachineInstrBuilder NOP = BuildMI(MBB, inspt, DL, RII->get(RISCV::ADDI)); + NOP.addReg(RISCV::X0); + NOP.addReg(RISCV::X0); + NOP.addImm(0); + LoopLen += getMISize(*NOP.getInstr()); + offsetIncrease += getMISize(*NOP.getInstr()); + } + } + MII = inspt; + if (offsetIncrease > 0) { + bool hasSeenOurselves = false; + for (const MachineBasicBlock &otherBlock : MF) { + if (&MBB == &otherBlock) { + hasSeenOurselves = true; + continue; + } + else if (!hasSeenOurselves) { + continue; + } + BlockToInstOffset[&otherBlock] += offsetIncrease; + } + } + } + else { + ++MII; + } + InstOffset += InstSize; + } + } + for (MachineBasicBlock &MBB : MF) { + unsigned instrs = 0; + for (MachineInstr &MI : MBB) { + instrs++; + if (isHardwareLoop(MI) && instrs > 1) { + MachineBasicBlock::iterator SplitPoint(&MI); + MachineFunction *MF = OldMBB->getParent(); + LivePhysRegs LiveRegs; + MachineBasicBlock::iterator Prev(&MI); + LiveRegs.init(*MF->getSubtarget().getRegisterInfo()); + LiveRegs.addLiveOuts(*OldMBB); + for (auto I = OldMBB->rbegin(), E = Prev.getReverse(); I != E; ++I) { + LiveRegs.stepBackward(*I); + } + MachineBasicBlock *SplitBB = MF->CreateMachineBasicBlock(OldMBB->getBasicBlock()); + MF->insert(++MachineFunction::iterator(OldMBB), SplitBB); + SplitBB->splice(SplitBB->begin(), OldMBB, SplitPoint, OldMBB->end()); + SplitBB->transferSuccessorsAndUpdatePHIs(OldMBB); + OldMBB->addSuccessor(SplitBB); + addLiveIns(*SplitBB, LiveRegs); + if (New == &MBB) { + continue; + } + New->setAlignment(Align(4)); + break; + } + } + } + return fixedPreHd || fixedLatch || fixedInstr; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/CountValue.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/CountValue.cpp new file mode 100644 index 0000000000000000000000000000000000000000..26c51517892476bc1f825e05105cbb930db045d3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/CountValue.cpp @@ -0,0 +1,10 @@ +explicit CountValue(CountValueType t, unsigned v, unsigned u = 0) { + Kind = t; + if (Kind == CV_Register) { + Contents.R.Reg = v; + Contents.R.Sub = u; + } + else { + Contents.ImmVal = v; + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/HardWareLoops.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/HardWareLoops.cpp new file mode 100644 index 0000000000000000000000000000000000000000..58d2e084d50b83358610cdea163f6b7531686fa5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/HardWareLoops.cpp @@ -0,0 +1,3 @@ +PULPHardwareLoops() : MachineFunctionPass(ID) { + initializePULPHardwareLoopsPass(*PassRegistry::getPassRegistry()); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/PULPHardwareLoops.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/PULPHardwareLoops.cpp new file mode 100644 index 0000000000000000000000000000000000000000..059b70f62c067de93e000828574ee0e617720529 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/PULPHardwareLoops.cpp @@ -0,0 +1,2 @@ +PULPHardwareLoops() : MachineFunctionPass(ID) { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/checkForImmediate.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/checkForImmediate.cpp new file mode 100644 index 0000000000000000000000000000000000000000..005a0a55c3b6d3c871199808ac7be545996ae9b6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/checkForImmediate.cpp @@ -0,0 +1,50 @@ +bool PULPHardwareLoops::checkForImmediate(const MachineOperand &MO, int64_t &Val) const { + if (MO.isImm()) { + Val = MO.getImm(); + return true; + } + if (!MO.isReg()) { + return false; + } + int64_t TV; + unsigned R = MO.getReg(); + if (!Register::isVirtualRegister(R)) { + if (R == RISCV::X0) { + Val = 0; + return true; + } + return false; + } + MachineInstr *DI = MRI->getVRegDef(R); + unsigned DOpc = DI->getOpcode(); + if (DOpc == TargetOpcode::COPY) { + if (!checkForImmediate(DI->getOperand(1), TV)) { + return false; + } + Val = TV; + return true; + } + if (DOpc == RISCV::ADDI) { + if (DI->getOperand(1).isReg() && DI->getOperand(1).getReg() == RISCV::X0) { + if (!checkForImmediate(DI->getOperand(2), TV)) { + return false; + } + else { + Val = TV; + } + } + else if (DI->getOperand(2).isImm() && DI->getOperand(2).getImm() == 0) { + if (!checkForImmediate(DI->getOperand(1), TV)) { + return false; + } + else { + Val = TV; + } + } + else { + return false; + } + return true; + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/containsInvalidInstruction.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/containsInvalidInstruction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5d234723bae57bf328dfe66d52a8676c24d532f2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/containsInvalidInstruction.cpp @@ -0,0 +1,11 @@ +bool PULPHardwareLoops::containsInvalidInstruction(MachineLoop *L) const { + for (MachineBasicBlock *MBB : L->getBlocks()) { + for (MachineInstr &MI : *MBB) { + if (isInvalidLoopOperation(&MI)) { + LLVM_DEBUG(dbgs() << "\nCannot convert to hwloop due to:"; MI.dump();); + return true; + } + } + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/convertToHardwareLoop.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/convertToHardwareLoop.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f233be7cdb5524312c033a4b256a9d7a7f5ee87a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/convertToHardwareLoop.cpp @@ -0,0 +1,156 @@ +bool PULPHardwareLoops:: (MachineLoop *L, bool &RecL0used, bool &RecL1used) { +assert(L->getHeader() && "Loop without a header?"); +bool Changed = false; +bool L0Used = false; +bool L1Used = false; +for (MachineLoop::iterator I = L->begin(), E = L->end(); I != E; ++I) { +Changed = Changed | convertToHardwareLoop(*I, RecL0used, RecL1used); +L0Used = L0Used | RecL0used; +L1Used = L1Used | RecL1used; +} +if (Changed) { +if (L0Used) { +if (L1Used) { +return Changed; +} +} +} +unsigned LOOP_i; +unsigned LOOP_r; +unsigned ENDLOOP; +unsigned IsInnerHWLoop = 1; +if (L0Used) { +LOOP_i = RISCV::J2_loop1i; +LOOP_r = RISCV::J2_loop1r; +ENDLOOP = RISCV::ENDLOOP1; +IsInnerHWLoop = 0; +} +if (!L0Used) { +LOOP_i = RISCV::J2_loop0i; +LOOP_r = RISCV::J2_loop0r; +ENDLOOP = RISCV::ENDLOOP0; +} +if (containsInvalidInstruction(L, IsInnerHWLoop)) { +return false; +} +MachineBasicBlock *LastMBB = getExitingBlock(L); +if (!LastMBB) { +return false; +} +MachineBasicBlock::iterator LastI = LastMBB->getFirstTerminator(); +if (LastI == LastMBB->end()) { +return false; +} +if (!fixupInductionVariable(L)) { +return false; +} +MachineBasicBlock *Preheader = L->getLoopPreheader(); +if (!Preheader) { +Preheader = createPreheaderForLoop(L); +if (!Preheader) { +return false; +} +} +MachineBasicBlock::iterator InsertPos = Preheader->getFirstTerminator(); +SmallVector OldInsts; +CountValue *TripCount = getLoopTripCount(L, OldInsts); +if (!TripCount) { +return false; +} +if (TripCount->isReg()) { +MachineInstr *TCDef = MRI->getVRegDef(TripCount->getReg()); +MachineBasicBlock *BBDef = TCDef->getParent(); +if (!MDT->dominates(BBDef, Preheader)) { +return false; +} +} +MachineBasicBlock *TopBlock = L->getTopBlock(); +MachineBasicBlock *ExitingBlock = getExitingBlock(L); +MachineBasicBlock *LoopStart = 0; +if (ExitingBlock != L->getLoopLatch()) { +MachineBasicBlock *TB = 0, *FB = 0; +SmallVector Cond; +if (TII->analyzeBranch(*ExitingBlock, TB, FB, Cond, false)) { +return false; +} +if (L->contains(TB)) { +LoopStart = TB; +} +if (L->contains(FB)) { +LoopStart = FB; +} +if (!L->contains(TB)) { +if (!L->contains(FB)) { +return false; +} +} +} +if (ExitingBlock == L->getLoopLatch()) { +LoopStart = TopBlock; +} +DEBUG(dbgs() << "Change to hardware loop at "; L->dump()); +DebugLoc DL; +if (InsertPos != Preheader->end()) { +DL = InsertPos->getDebugLoc(); +} +if (TripCount->isReg()) { +unsigned CountReg = MRI->createVirtualRegister(&RISCV::IntRegsRegClass); +BuildMI(*Preheader, InsertPos, DL, TII->get(TargetOpcode::COPY), CountReg).addReg(TripCount->getReg(), 0, TripCount->getSubReg()); +BuildMI(*Preheader, InsertPos, DL, TII->get(LOOP_r)).addMBB(LoopStart).addReg(CountReg); +} +if (!TripCount->isReg()) { +assert(TripCount->isImm() && "Expecting immediate value for trip count"); +int64_t CountImm = TripCount->getImm(); +if (!TII->isValidOffset(LOOP_i, CountImm)) { +unsigned CountReg = MRI->createVirtualRegister(&RISCV::IntRegsRegClass); +BuildMI(*Preheader, InsertPos, DL, TII->get(RISCV::A2_tfrsi), CountReg).addImm(CountImm); +BuildMI(*Preheader, InsertPos, DL, TII->get(LOOP_r)).addMBB(LoopStart).addReg(CountReg); +} +if (TII->isValidOffset(LOOP_i, CountImm)) { +BuildMI(*Preheader, InsertPos, DL, TII->get(LOOP_i)).addMBB(LoopStart).addImm(CountImm); +} +} +LoopStart->setHasAddressTaken(); +BlockAddress::get(const_cast(LoopStart->getBasicBlock())); +DebugLoc LastIDL = LastI->getDebugLoc(); +BuildMI(*LastMBB, LastI, LastIDL, TII->get(ENDLOOP)).addMBB(LoopStart); +if (LastI->getOpcode() == RISCV::J2_jumpt) { +MachineBasicBlock *BranchTarget = LastI->getOperand(1).getMBB(); +LastI = LastMBB->erase(LastI); +if (!L->contains(BranchTarget)) { +if (LastI != LastMBB->end()) { +LastI = LastMBB->erase(LastI); +} +SmallVector Cond; +TII->InsertBranch(*LastMBB, BranchTarget, nullptr, Cond, LastIDL); +} +} +if (LastI->getOpcode() == RISCV::J2_jumpf) { +MachineBasicBlock *BranchTarget = LastI->getOperand(1).getMBB(); +LastI = LastMBB->erase(LastI); +if (!L->contains(BranchTarget)) { +if (LastI != LastMBB->end()) { +LastI = LastMBB->erase(LastI); +} +SmallVector Cond; +TII->InsertBranch(*LastMBB, BranchTarget, nullptr, Cond, LastIDL); +} +} +if (LastI->getOpcode() != RISCV::J2_jumpt) { +if (LastI->getOpcode() != RISCV::J2_jumpf) { +LastMBB->erase(LastI); +} +} +delete TripCount; +for (unsigned i = 0; i < OldInsts.size(); ++i) { +removeIfDead(OldInsts[i]); +} +NumHWLoops = NumHWLoops + 1; +if (L0Used) { +RecL1used = true; +} +if (!L0Used) { +RecL0used = true; +} +return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/createPULPHardwareLoops.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/createPULPHardwareLoops.cpp new file mode 100644 index 0000000000000000000000000000000000000000..22e78cc2e7b7238ff9e98a897b042dbb37b79065 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/createPULPHardwareLoops.cpp @@ -0,0 +1,3 @@ +FunctionPass *llvm::createPULPHardwareLoops() { + return new PULPHardwareLoops(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/createPass.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/createPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..863945051646c9f1c5aa4d13b92798567cf74358 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/createPass.cpp @@ -0,0 +1,4 @@ +//zmcorrectzm +FunctionPass *llvm::createPULPHardwareLoops() { + return new PULPHardwareLoops(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/enumCountValueType.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/enumCountValueType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..84c79208998defdbb6d20f1bc3d4469dd0bcf0a5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/enumCountValueType.cpp @@ -0,0 +1,4 @@ +enum CountValueType { + CV_Register, + CV_Immediate +}; diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/enumKind.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/enumKind.cpp new file mode 100644 index 0000000000000000000000000000000000000000..06934a6723a77c148733266a6459f940fb54480b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/enumKind.cpp @@ -0,0 +1,15 @@ +enum Kind { + EQ = 0x01, + NE = 0x02, + L = 0x04, + G = 0x08, + U = 0x40, + LTs = L, + LEs = L | EQ, + GTs = G, + GEs = G | EQ, + LTu = L | U, + LEu = L | EQ | U, + GTu = G | U, + GEu = G | EQ | U +}; diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/findInductionRegister.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/findInductionRegister.cpp new file mode 100644 index 0000000000000000000000000000000000000000..94e147da406f745130c3064c3f92fbfd6add4b8d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/findInductionRegister.cpp @@ -0,0 +1,80 @@ +bool PULPHardwareLoops::findInductionRegister(MachineLoop *L, unsigned &Reg, int64_t &IVBump, MachineInstr *&IVOp) const { + MachineBasicBlock *Preheader = MLI->findLoopPreheader(L, SpecPreheader); + MachineBasicBlock *Header = L->getHeader(); + MachineBasicBlock *Latch = L->getLoopLatch(); + MachineBasicBlock *ExitingBlock = L->findLoopControlBlock(); + if (!Header) { + return false; + } + if (!Preheader) { + return false; + } + if (!Latch) { + return false; + } + if (!ExitingBlock) { + return false; + } + using RegisterBump = std::pair; + using InductionMap = std::map; + InductionMap IndMap; + using instr_iterator = MachineBasicBlock::instr_iterator; + for (instr_iterator I = Header->instr_begin(), E = Header->instr_end(); I != E && I->isPHI(); ++I) { + MachineInstr *Phi = &*I; + for (unsigned i = 1, n = Phi->getNumOperands(); i < n; i += 2) { + if (Phi->getOperand(i+1).getMBB() != Latch) { + continue; + } + unsigned PhiOpReg = Phi->getOperand(i).getReg(); + MachineInstr *DI = MRI->getVRegDef(PhiOpReg); + if (DI->getDesc().getOpcode() == RISCV::ADDI) { + unsigned IndReg = DI->getOperand(1).getReg(); + MachineOperand &Opnd2 = DI->getOperand(2); + int64_t V; + if (MRI->getVRegDef(IndReg) == Phi && checkForImmediate(Opnd2, V)) { + unsigned UpdReg = DI->getOperand(0).getReg(); + IndMap.insert(std::make_pair(UpdReg, std::make_pair(IndReg, V))); + } + } + } + } + if (IndMap.empty()) { + return false; + } + MachineBasicBlock *TB = nullptr, *FB = nullptr; + SmallVector Cond; + bool NotAnalyzed = TII->analyzeBranch(*ExitingBlock, TB, FB, Cond, false); + if (NotAnalyzed || Cond.empty()) { + return false; + } + MachineInstr *condTerm = &(*Latch->getFirstTerminator()); + MachineInstr *uncondTerm = &(*std::next(Latch->getFirstTerminator())); + if (!(condTerm->getDesc().isConditionalBranch() && uncondTerm->getDesc().isUnconditionalBranch())) { + return false; + } + unsigned CmpReg1 = Cond[1].isReg() ? (unsigned) Cond[1].getReg() : 0; + unsigned CmpReg2 = Cond[2].isReg() ? (unsigned) Cond[2].getReg() : 0; + InductionMap::iterator IndMapEnd = IndMap.end(); + InductionMap::iterator F = IndMapEnd; + if (CmpReg1 != 0) { + InductionMap::iterator F1 = IndMap.find(CmpReg1); + if (F1 != IndMapEnd) + F = F1; + } + if (CmpReg2 != 0) { + InductionMap::iterator F2 = IndMap.find(CmpReg2); + if (F2 != IndMapEnd) { + if (F != IndMapEnd) { + return false; + } + F = F2; + } + } + if (F == IndMapEnd) { + return false; + } + Reg = F->second.first; + IVBump = F->second.second; + IVOp = MRI->getVRegDef(F->first); + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/getAnalysisUsage.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/getAnalysisUsage.cpp new file mode 100644 index 0000000000000000000000000000000000000000..008370676124d4400b6c7f7aaba93b088e710f44 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/getAnalysisUsage.cpp @@ -0,0 +1,5 @@ +void getAnalysisUsage(AnalysisUsage &AU) const override { + AU.addRequired(); + AU.addRequired(); + MachineFunctionPass::getAnalysisUsage(AU); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/getComparisonKind.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/getComparisonKind.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c37759ea88d5e1c9d3e64734898c8cfd783c37ab --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/getComparisonKind.cpp @@ -0,0 +1,32 @@ +PULPHardwareLoops::Comparison::Kind PULPHardwareLoops::getComparisonKind(unsigned CondOpc, MachineOperand *InitialValue, const MachineOperand *EndValue, int64_t IVBump) const { + Comparison::Kind Cmp = (Comparison::Kind)0; + switch (CondOpc) { + case RISCV::BEQ: + Cmp = Comparison::EQ; + break; + case RISCV::BNE: + Cmp = Comparison::NE; + break; + case RISCV::BLT: + Cmp = Comparison::LTs; + break; + case RISCV::BLTU: + Cmp = Comparison::LTu; + break; + case RISCV::BGE: + Cmp = Comparison::GEs; + break; + case RISCV::BGEU: + Cmp = Comparison::GEs; + break; + case RISCV::P_BNEIMM: + Cmp = Comparison::NE; + break; + case RISCV::P_BEQIMM: + Cmp = Comparison::EQ; + break; + default: + return (Comparison::Kind)0; + } + return Cmp; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/getImm.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/getImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..926b8c43cd5728c5187b2fb95773e11602a6ae6b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/getImm.cpp @@ -0,0 +1,4 @@ +unsigned getImm() const { + assert(isImm() && "Wrong CountValue accessor"); + return Contents.ImmVal; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/getLoopTripCount.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/getLoopTripCount.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0665e124d42ad6102cf3b1737469e9b3e1870a0c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/getLoopTripCount.cpp @@ -0,0 +1,277 @@ +CountValue *PULPHardwareLoops::getLoopTripCount(MachineLoop *L, SmallVectorImpl &OldInsts) { + MachineBasicBlock *TopMBB = L->getTopBlock(); + MachineBasicBlock::pred_iterator PI = TopMBB->pred_begin(); + assert(PI != TopMBB->pred_end() && + "Loop must have more than one incoming edge!"); + MachineBasicBlock *Backedge = *PI++; + if (PI == TopMBB->pred_end()) { + return nullptr; + } + MachineBasicBlock *Incoming = *PI++; + if (PI != TopMBB->pred_end()) { + return nullptr; + } + if (L->contains(Incoming)) { + if (L->contains(Backedge)) { + return nullptr; + } + std::swap(Incoming, Backedge); + } else if (!L->contains(Backedge)) { + return nullptr; + } + MachineBasicBlock *ExitingBlock = L->findLoopControlBlock(); + if (!ExitingBlock) { + return nullptr; + } + unsigned IVReg = 0; + int64_t IVBump = 0; + MachineInstr *IVOp; + bool FoundIV = findInductionRegister(L, IVReg, IVBump, IVOp); + if (!FoundIV) { + return nullptr; + } + MachineBasicBlock *Preheader = MLI->findLoopPreheader(L, SpecPreheader); + MachineOperand *InitialValue = nullptr; + MachineInstr *IV_Phi = MRI->getVRegDef(IVReg); + MachineBasicBlock *Latch = L->getLoopLatch(); + for (unsigned i = 1, n = IV_Phi->getNumOperands(); i < n; i += 2) { + MachineBasicBlock *MBB = IV_Phi->getOperand(i+1).getMBB(); + if (MBB == Preheader) + InitialValue = &IV_Phi->getOperand(i); + else if (MBB == Latch) + IVReg = IV_Phi->getOperand(i).getReg(); + } + if (!InitialValue) { + return nullptr; + } + SmallVector Cond; + MachineBasicBlock *TB = nullptr, *FB = nullptr; + bool NotAnalyzed = TII->analyzeBranch(*ExitingBlock, TB, FB, Cond, false); + if (NotAnalyzed) { + return nullptr; + } + MachineBasicBlock *Header = L->getHeader(); + assert (TB && "Exit block without a branch?"); + if (ExitingBlock != Latch && (TB == Latch || FB == Latch)) { + MachineBasicBlock *LTB = nullptr, *LFB = nullptr; + SmallVector LCond; + bool NotAnalyzed = TII->analyzeBranch(*Latch, LTB, LFB, LCond, false); + if (NotAnalyzed) { + return nullptr; + } + if (TB == Latch) + TB = (LTB == Header) ? LTB : LFB; + else + FB = (LTB == Header) ? LTB: LFB; + } + assert ((!FB || TB == Header || FB == Header) && "Branches not to header?"); + if (!TB || (FB && TB != Header && FB != Header)) { + return nullptr; + } + MachineBasicBlock::iterator firstTerm = Latch->getFirstTerminator(); + MachineBasicBlock::iterator secondTerm = std::next(firstTerm); + if (!(firstTerm->getDesc().isConditionalBranch() && secondTerm->getDesc().isUnconditionalBranch())) { + return nullptr; + } + unsigned CondOpc = Cond[0].getImm(); + OldInsts.push_back(IVOp); + Comparison::Kind Cmp; + bool isSwapped = false; + const MachineOperand &Op1 = Cond[1]; + const MachineOperand &Op2 = Cond[2]; + const MachineOperand *EndValue = nullptr; + if (Op1.isReg()) { + if (Op2.isImm() || Op1.getReg() == IVReg) + EndValue = &Op2; + else { + EndValue = &Op1; + isSwapped = true; + } + } + if (!EndValue) { + return nullptr; + } + Cmp = getComparisonKind(CondOpc, InitialValue, EndValue, IVBump); + if (!Cmp) { + return nullptr; + } + if (isSwapped) { + Cmp = Comparison::getSwappedComparison(Cmp); + } + if (InitialValue->isReg()) { + unsigned R = InitialValue->getReg(); + MachineBasicBlock *DefBB = MRI->getVRegDef(R)->getParent(); + if (!MDT->properlyDominates(DefBB, Header)) { + int64_t V; + if (!checkForImmediate(*InitialValue, V)) { + return nullptr; + } + } + OldInsts.push_back(MRI->getVRegDef(R)); + } + if (EndValue->isReg()) { + unsigned R = EndValue->getReg(); + MachineBasicBlock *DefBB = MRI->getVRegDef(R)->getParent(); + if (!MDT->properlyDominates(DefBB, Header)) { + int64_t V; + if (!checkForImmediate(*EndValue, V)) { + return nullptr; + } + } + OldInsts.push_back(MRI->getVRegDef(R)); + } + FL->isFirstOperandEndvalue = isFirstOperandEndvalue; + FL->isCondExit = isCondExit; + InductionReg = new Register(IndReg); + IncrementReg = new Register(IncReg); + MachineBasicBlock *PH = MLI->findLoopPreheader(Loop, SpecPreheader); + assert (PH && "Should have a preheader by now"); + MachineBasicBlock::iterator InsertPos = PH->getFirstTerminator(); + DebugLoc DL; + if (InsertPos != PH->end()) + DL = InsertPos->getDebugLoc(); + const TargetRegisterClass *IntRC = &RISCV::GPRRegClass; + bool startIsImm = false, endIsImm = false; + int64_t immStart, immEnd; + startIsImm = checkForImmediate(*Start, immStart); + endIsImm = checkForImmediate(*End, immEnd); + if (endIsImm && !End->isImm()) { + if(immEnd == 0) { + unsigned VGPR = MRI->createVirtualRegister(IntRC); + MachineInstrBuilder ZeroInit = BuildMI(*PH, InsertPos, DL, TII->get(TargetOpcode::COPY), VGPR); + ZeroInit.addReg(RISCV::X0); + End = &ZeroInit->getOperand(0); + } + } + bool CmpLess = Cmp & Comparison::L; + bool CmpGreater = Cmp & Comparison::G; + bool CmpHasEqual = Cmp & Comparison::EQ; + if (!Start->isReg() && !startIsImm) { + return nullptr; + } + if (!End->isReg() && !endIsImm) { + return nullptr; + } + if (CmpLess && IVBump < 0) { + return nullptr; + } + if (CmpGreater && IVBump > 0) { + return nullptr; + } + if (IVBump == 0) { + return nullptr; + } + if (startIsImm && endIsImm) { + if(!CmpHasEqual) { + return nullptr; + } + int64_t Dist = std::max(immStart, immEnd) - std::min(immStart, immEnd); + if (Dist == 0) { + return nullptr; + } + if (Cmp != Comparison::EQ) { + return nullptr; + } + bool Exact = (Dist % IVBump) == 0; + if (!Exact) { + return nullptr; + } + uint64_t Count = Dist / std::abs(IVBump); + if (Count > 0xFFFFFFFFULL) { + return nullptr; + } + return new CountValue(CountValue::CV_Immediate, Count); + } + LoopFeederMap LoopFeederPhi; + if (loopCountMayWrapOrUnderFlow(Start, End, Loop->getLoopPreheader(), Loop, LoopFeederPhi)) { + return nullptr; + } + if (!isPowerOf2_64(std::abs(IVBump))) { + return nullptr; + } + if (IVBump < 0) { + std::swap(Start, End); + IVBump = -IVBump; + } + bool RegToImm = Start->isReg() && End->isImm(); + bool RegToReg = Start->isReg() && End->isReg(); + int64_t StartV = 0, EndV = 0; + if (Start->isImm()) { + StartV = Start->getImm(); + } + if (End->isImm()) { + EndV = End->getImm(); + } + int64_t AdjV = 0; + unsigned DistR, DistSR; + bool startIsImmZeroOrZeroReg = (Start->isImm() && StartV == 0); + if (!startIsImmZeroOrZeroReg && Start->isReg()) { + int64_t startImm; + if (checkForImmediate(*Start, startImm)) { + startIsImmZeroOrZeroReg = (startImm == 0); + } + } + if (startIsImmZeroOrZeroReg) { + DistR = End->getReg(); + DistSR = End->getSubReg(); + } + else { + const MCInstrDesc &SubD = RegToReg ? TII->get(RISCV::SUB) : (RegToImm ? TII->get(RISCV::SUB) /* TODO */ : TII->get(RISCV::ADDI)); + if (RegToReg || RegToImm) { + unsigned SubR = MRI->createVirtualRegister(IntRC); + MachineInstrBuilder SubIB = BuildMI(*PH, InsertPos, DL, SubD, SubR); + if (RegToReg) { + SubIB.addReg(End->getReg(), 0, End->getSubReg()).addReg(Start->getReg(), 0, Start->getSubReg()); + } + else { + MachineBasicBlock::iterator ThisInsertPos = InsertPos; + ThisInsertPos--; + unsigned ImmToRegReg = MRI->createVirtualRegister(IntRC); + MachineInstrBuilder ImmToReg = BuildMI(*PH, ThisInsertPos, DL, TII->get(RISCV::ADDI), ImmToRegReg); + ImmToReg.addReg(RISCV::X0).addImm(EndV); + SubIB.addReg(ImmToReg->getOperand(0).getReg()).addReg(Start->getReg(), 0, Start->getSubReg()); + } + DistR = SubR; + } + else { + const MachineInstr *EndValInstr = MRI->getVRegDef(End->getReg()); + if (EndValInstr->getOpcode() == RISCV::ADDI && EndValInstr->getOperand(1).getSubReg() == 0 && EndValInstr->getOperand(2).getImm() == StartV) { + DistR = EndValInstr->getOperand(1).getReg(); + } + else { + unsigned SubR = MRI->createVirtualRegister(IntRC); + MachineInstrBuilder SubIB = BuildMI(*PH, InsertPos, DL, SubD, SubR); + SubIB.addReg(End->getReg(), 0, End->getSubReg()).addImm(-StartV); + DistR = SubR; + } + } + DistSR = 0; + } + unsigned AdjR, AdjSR; + if (AdjV == 0) { + AdjR = DistR; + AdjSR = DistSR; + } + else { + unsigned AddR = MRI->createVirtualRegister(IntRC); + MCInstrDesc const &AddD = TII->get(RISCV::ADDI); + BuildMI(*PH, InsertPos, DL, AddD, AddR).addReg(DistR, 0, DistSR).addImm(AdjV); + AdjR = AddR; + AdjSR = 0; + } + unsigned CountR, CountSR; + if (IVBump == 1) { + CountR = AdjR; + CountSR = AdjSR; + } + else { + unsigned Shift = Log2_32(IVBump); + unsigned LsrR = MRI->createVirtualRegister(IntRC); + const MCInstrDesc &LsrD = TII->get(RISCV::SRLI); + BuildMI(*PH, InsertPos, DL, LsrD, LsrR).addReg(AdjR, 0, AdjSR).addImm(Shift); + CountR = LsrR; + CountSR = 0; + } + return new CountValue(CountValue::CV_Register, CountR, CountSR); +} +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/getNegatedComparison.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/getNegatedComparison.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8a13423387ee5fbe6555d5082ab4a403413de6f4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/getNegatedComparison.cpp @@ -0,0 +1,9 @@ +static Kind getNegatedComparison(Kind Cmp) { + if ((Cmp & L) || (Cmp & G)) { + return (Kind)((Cmp ^ (L | G)) ^ EQ); + } + if ((Cmp & NE) || (Cmp & EQ)) { + return (Kind)(Cmp ^ (EQ | NE)); + } + return (Kind)0; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/getPassName.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..88db3099350e40fa0d4cfabc732be3b1d06f0ba9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/getPassName.cpp @@ -0,0 +1,3 @@ +StringRef getPassName() const override { + return "PULP Hardware Loops"; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/getReg.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/getReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2f6681dcc1a7d87c841a32fcfc8275dd4af179c7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/getReg.cpp @@ -0,0 +1,4 @@ +unsigned getReg() const { + assert(isReg() && "Wrong CountValue accessor"); + return Contents.R.Reg; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/getSubReg.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/getSubReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cff1bb27c34b61906a86c7f741e8de982019bb79 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/getSubReg.cpp @@ -0,0 +1,4 @@ +unsigned getSubReg() const { + assert(isReg() && "Wrong CountValue accessor"); + return Contents.R.Sub; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/getSwappedComparison.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/getSwappedComparison.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ec0cca39b910463d25f200de5c7324bd5d9368d2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/getSwappedComparison.cpp @@ -0,0 +1,7 @@ +static Kind getSwappedComparison(Kind Cmp) { + assert ((!((Cmp & L) && (Cmp & G))) && "Malformed comparison operator"); + if ((Cmp & L) || (Cmp & G)) { + return (Kind)(Cmp ^ (L|G)); + } + return Cmp; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/isDead.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/isDead.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8d0fd1c6e1e565b831bf30a631c3386d5ebe5157 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/isDead.cpp @@ -0,0 +1,32 @@ +bool PULPHardwareLoops::isDead(const MachineInstr *MI, SmallVectorImpl &DeadPhis) const { + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { + const MachineOperand &MO = MI->getOperand(i); + if (!MO.isReg() || !MO.isDef()) + continue; + unsigned Reg = MO.getReg(); + if (MRI->use_nodbg_empty(Reg)) + continue; + using use_nodbg_iterator = MachineRegisterInfo::use_nodbg_iterator; + use_nodbg_iterator I = MRI->use_nodbg_begin(Reg); + use_nodbg_iterator End = MRI->use_nodbg_end(); + if (std::next(I) != End || !I->getParent()->isPHI()) + return false; + MachineInstr *OnePhi = I->getParent(); + for (unsigned j = 0, f = OnePhi->getNumOperands(); j != f; ++j) { + const MachineOperand &OPO = OnePhi->getOperand(j); + if (!OPO.isReg() || !OPO.isDef()) + continue; + unsigned OPReg = OPO.getReg(); + use_nodbg_iterator nextJ; + for (use_nodbg_iterator J = MRI->use_nodbg_begin(OPReg); J != End; J = nextJ) { + nextJ = std::next(J); + MachineOperand &Use = *J; + MachineInstr *UseMI = Use.getParent(); + if (MI != UseMI) + return false; + } + } + DeadPhis.push_back(OnePhi); + } + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/isImm.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/isImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..dc64ab4323d8f6b869d0a1cef8d7218e4ab79081 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/isImm.cpp @@ -0,0 +1,3 @@ +bool isImm() const { + return Kind == CV_Immediate; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/isInvalidLoopOperation.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/isInvalidLoopOperation.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5f4f22f91f44ed4217c037ae6be289172515f95c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/isInvalidLoopOperation.cpp @@ -0,0 +1,18 @@ +bool PULPHardwareLoops::isInvalidLoopOperation(const MachineInstr *MI) const { + if (MI->getDesc().isCall()) { + return true; + } + if (MO.getReg() == RISCV::LOOP0setup) { + return KnownHardwareLoops.count(MI) == 0; + } + if (MO.getReg() == RISCV::LOOP1setup) { + return KnownHardwareLoops.count(MI) == 0; + } + if (MO.getReg() == RISCV::LOOP0setupi) { + return KnownHardwareLoops.count(MI) == 0; + } + if (MO.getReg() == RISCV::LOOP1setupi) { + return KnownHardwareLoops.count(MI) == 0; + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/isLoopFeeder.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/isLoopFeeder.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3c9511384a7e59e90f95a99440837a5baefc2273 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/isLoopFeeder.cpp @@ -0,0 +1,15 @@ +bool PULPHardwareLoops::isLoopFeeder(MachineLoop *L, MachineBasicBlock *A, MachineInstr *MI, const MachineOperand *MO, LoopFeederMap &LoopFeederPhi) const { + if (LoopFeederPhi.find(MO->getReg()) == LoopFeederPhi.end()) { + LLVM_DEBUG(dbgs() << "\nhw_loop head, " << printMBBReference(**L->block_begin())); + for (MachineBasicBlock *MBB : L->getBlocks()) { + if (A == MBB) + return false; + } + MachineInstr *Def = MRI->getVRegDef(MO->getReg()); + LoopFeederPhi.insert(std::make_pair(MO->getReg(), Def)); + return true; + } + else { + return false; + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/isReg.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/isReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..39a3b1a4a320cf5fa42671064beafec9eaf2aced --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/isReg.cpp @@ -0,0 +1,3 @@ +bool isReg() const { + return Kind == CV_Register; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/isSigned.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/isSigned.cpp new file mode 100644 index 0000000000000000000000000000000000000000..dc85ce445f35cd0e967ac51228897ff83c7ccf54 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/isSigned.cpp @@ -0,0 +1,3 @@ +static bool isSigned(Kind Cmp) { + return (Cmp & (L | G) && !(Cmp & U)); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/isUnsigned.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/isUnsigned.cpp new file mode 100644 index 0000000000000000000000000000000000000000..832beba9cac1339893e9305ccd1698e085711c36 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/isUnsigned.cpp @@ -0,0 +1,3 @@ +static bool isUnsigned(Kind Cmp) { + return (Cmp & U); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/loopCountMayWrapOrUnderFlow.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/loopCountMayWrapOrUnderFlow.cpp new file mode 100644 index 0000000000000000000000000000000000000000..efeeeddfc7ec63b3244065b73509df85d52bdcb4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/loopCountMayWrapOrUnderFlow.cpp @@ -0,0 +1,56 @@ +bool PULPHardwareLoops::loopCountMayWrapOrUnderFlow(const MachineOperand *InitVal, const MachineOperand *EndVal, MachineBasicBlock *MBB, MachineLoop *L, LoopFeederMap &LoopFeederPhi) const { + if (!InitVal -> isReg()) { + return false; + } + if (!EndVal -> isImm()) { + return false; + } + int64_t Imm; + if (checkForImmediate(*InitVal, Imm)) { + return EndVal->getImm() == Imm; + } + Register Reg = InitVal->getReg(); + if (!Reg.isVirtual()) { + return true; + } + MachineInstr *Def = MRI->getVRegDef(Reg); + if (!Def) { + return true; + } + if (Def->isPHI() && !phiMayWrapOrUnderflow(Def, EndVal, Def->getParent(), L, LoopFeederPhi)) { + return false; + } + if (Def->isCopy() && !loopCountMayWrapOrUnderFlow(&(Def->getOperand(1)), EndVal, Def->getParent(), L, LoopFeederPhi)) { + return false; + } + for (MachineRegisterInfo::use_instr_nodbg_iterator I = MRI->use_instr_nodbg_begin(Reg), E = MRI->use_instr_nodbg_end(); I != E; ++I) { + MachineInstr *MI = &*I; + Register CmpReg1 = 0, CmpReg2 = 0; + int CmpMask = 0, CmpValue = 0; + if (!TII->analyzeCompare(*MI, CmpReg1, CmpReg2, CmpMask, CmpValue)) { + continue; + } + MachineBasicBlock *TBB = nullptr, *FBB = nullptr; + SmallVector Cond; + if (TII->analyzeBranch(*MI->getParent(), TBB, FBB, Cond, false)) { + continue; + } + Comparison::Kind Cmp = getComparisonKind(MI->getOpcode(), nullptr, nullptr, 0); + if (Cmp == 0) { + continue; + } + if (CmpReg2 != 0 && CmpReg2 == Reg) { + Cmp = Comparison::getSwappedComparison(Cmp); + } + if (Comparison::isSigned(Cmp)) { + return false; + } + if ((Cmp & Comparison::G) || Cmp == Comparison::NE) { + return false; + } + } + if (!Def->isCopy() && !Def->isPHI()) { + return false; + } + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/phiMayWrapOrUnderflow.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/phiMayWrapOrUnderflow.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b720d8f1b25ab6fdfa47794bc2acfe2eb1642790 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/phiMayWrapOrUnderflow.cpp @@ -0,0 +1,11 @@ +bool PULPHardwareLoops::phiMayWrapOrUnderflow(MachineInstr *Phi, const MachineOperand *EndVal, MachineBasicBlock *MBB, MachineLoop *L, LoopFeederMap &LoopFeederPhi) const { + assert(Phi->isPHI() && "Expecting a Phi."); + for (int i = 1, n = Phi->getNumOperands(); i < n; i += 2) { + if (isLoopFeeder(L, MBB, Phi, &(Phi->getOperand(i)), LoopFeederPhi)) { + if (loopCountMayWrapOrUnderFlow(&(Phi->getOperand(i)), EndVal, Phi->getParent(), L, LoopFeederPhi)) { + return true; + } + } + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/print.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/print.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bb34211b7a963966e9198729846f7a46520d019f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/print.cpp @@ -0,0 +1,8 @@ +void print(raw_ostream &OS, const TargetRegisterInfo *TRI = nullptr) const { + if (isReg()) { + OS << printReg(Contents.R.Reg, TRI, Contents.R.Sub); + } + if (isImm()) { + OS << Contents.ImmVal; + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/removeIfDead.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/removeIfDead.cpp new file mode 100644 index 0000000000000000000000000000000000000000..573102109eff8a14835d4f0cf2a687ebc7d75093 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/removeIfDead.cpp @@ -0,0 +1,26 @@ +void PULPHardwareLoops::removeIfDead(MachineInstr *MI) { + SmallVector DeadPhis; + if (isDead(MI, DeadPhis)) { + LLVM_DEBUG(dbgs() << "HW looping will remove: " << *MI); + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { + const MachineOperand &MO = MI->getOperand(i); + if (!MO.isReg() || !MO.isDef()) + continue; + unsigned Reg = MO.getReg(); + MachineRegisterInfo::use_iterator nextI; + for (MachineRegisterInfo::use_iterator I = MRI->use_begin(Reg), E = MRI->use_end(); I != E; I = nextI) { + nextI = std::next(I); + MachineOperand &Use = *I; + MachineInstr *UseMI = I->getParent(); + if (UseMI == MI) + continue; + if (Use.isDebug()) + UseMI->getOperand(0).setReg(0U); + } + } + MI->eraseFromParent(); + for (unsigned i = 0; i < DeadPhis.size(); ++i) { + DeadPhis[i]->eraseFromParent(); + } + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..32396ee89035052f4e8307e42b85270e9d0da451 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/runOnMachineFunction.cpp @@ -0,0 +1,30 @@ +bool PULPHardwareLoops::runOnMachineFunction(MachineFunction &MF) { + LLVM_DEBUG(dbgs() << "********* PULP Hardware Loops *********\n"); + if (!MF.getSubtarget().hasPULPExtV2()) { + return false; + } + if (skipFunction(MF.getFunction())) { + return false; + } + bool Changed = false; + NumHWLoopsInternal = 0; + MLI = &getAnalysis(); + MRI = &MF.getRegInfo(); + MDT = &getAnalysis(); + const RISCVSubtarget &HST = MF.getSubtarget(); + TII = HST.getInstrInfo(); + TRI = HST.getRegisterInfo(); + for (auto &L : *MLI) + if (!L->getParentLoop()) { + bool L0Used = false; + bool L1Used = false; + KnownHardwareLoops.clear(); + Changed |= convertToHardwareLoop(L, L0Used, L1Used); + } + if (Changed) { + errs().changeColor(raw_fd_ostream::Colors::BLUE, true); + errs() << "Created " << NumHWLoopsInternal << " hardware loops in " << MF.getName() << "!\n"; + errs().resetColor(); + } + return Changed; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/unionValues.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/unionValues.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5ba190c6eef41533e7debd2511464194bd8c9427 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/PULPHardWareLoops/unionValues.cpp @@ -0,0 +1,7 @@ +union Values { + struct { + unsigned Reg; + unsigned Sub; + } R; + unsigned ImmVal; +} Contents; diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/CountValue.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/CountValue.cpp new file mode 100644 index 0000000000000000000000000000000000000000..26c51517892476bc1f825e05105cbb930db045d3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/CountValue.cpp @@ -0,0 +1,10 @@ +explicit CountValue(CountValueType t, unsigned v, unsigned u = 0) { + Kind = t; + if (Kind == CV_Register) { + Contents.R.Reg = v; + Contents.R.Sub = u; + } + else { + Contents.ImmVal = v; + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/FrepLoop.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/FrepLoop.cpp new file mode 100644 index 0000000000000000000000000000000000000000..98c5c29889f2176f721e3f9604806c1932aa76dc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/FrepLoop.cpp @@ -0,0 +1,3 @@ +explicit FrepLoop(MachineLoop *ML) { + L = ML; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/FrepLoopsPass.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/FrepLoopsPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a57ba5865dbb3f7dd0933b0843eda5372b9d3171 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/FrepLoopsPass.cpp @@ -0,0 +1,4 @@ +//zmCorrectzm +SNITCHFrepLoops() : MachineFunctionPass(ID) { + initializeSNITCHFrepLoopsPass(*PassRegistry::getPassRegistry()); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/SNITCHFrepLoops.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/SNITCHFrepLoops.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9b4e37e0af58cc8245b4eba37735a07b26093555 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/SNITCHFrepLoops.cpp @@ -0,0 +1,3 @@ +SNITCHFrepLoops() : MachineFunctionPass(ID) { + initializeSNITCHFrepLoopsPass(*PassRegistry::getPassRegistry()); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/checkForImmediate.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/checkForImmediate.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e2b6e9fc7dc9a0cecf43f9c9894c6dcfd42e733b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/checkForImmediate.cpp @@ -0,0 +1,50 @@ +bool SNITCHFrepLoops::checkForImmediate(const MachineOperand &MO, int64_t &Val) const { + if (MO.isImm()) { + Val = MO.getImm(); + return true; + } + if (!MO.isReg()) { + return false; + } + int64_t TV; + unsigned R = MO.getReg(); + if (!Register::isVirtualRegister(R)) { + if (R == RISCV::X0) { + Val = 0; + return true; + } + return false; + } + MachineInstr *DI = MRI->getVRegDef(R); + unsigned DOpc = DI->getOpcode(); + if (DOpc == TargetOpcode::COPY) { + if (!checkForImmediate(DI->getOperand(1), TV)) { + return false; + } + Val = TV; + return true; + } + if (DOpc == RISCV::ADDI) { + if (DI->getOperand(1).isReg() && DI->getOperand(1).getReg() == RISCV::X0) { + if (!checkForImmediate(DI->getOperand(2), TV)) { + return false; + } + else { + Val = TV; + } + } + else if (DI->getOperand(2).isImm() && DI->getOperand(2).getImm() == 0) { + if (!checkForImmediate(DI->getOperand(1), TV)) { + return false; + } + else { + Val = TV; + } + } + else { + return false; + } + return true; + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/containsInvalidInstruction.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/containsInvalidInstruction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..29dc41292f0058fe1e1821df6745bb636fb0fabe --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/containsInvalidInstruction.cpp @@ -0,0 +1,74 @@ +unsigned SNITCHFrepLoops::containsInvalidInstruction(MachineLoop *L, Register *IV, Register *ICV, SmallVectorImpl &FPPhis) const { + MachineBasicBlock *Header = L->getHeader(); + MachineBasicBlock *Latch = L->getLoopLatch(); + MachineBasicBlock *ExitingBlock = L->findLoopControlBlock(); + bool skip = false; + unsigned Flops = 0; + for (MachineBasicBlock *MBB : L->getBlocks()) { + for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end(); MII != E; ++MII) { + MachineInstr *MI = &*MII; + LLVM_DEBUG(dbgs()<<"Checking"; MI->dump()); + if(MI->getOpcode() == TargetOpcode::PHI) { + LLVM_DEBUG(dbgs() << " ignoring PHI node\n"); + if(MRI->getRegClass(MI->getOperand(0).getReg()) == &RISCV::FPR64RegClass || MRI->getRegClass(MI->getOperand(0).getReg()) == &RISCV::FPR32RegClass) { + FPPhis.push_back(MI); + } + continue; + } + if(MI->getOpcode() == TargetOpcode::COPY) { + LLVM_DEBUG(dbgs() << " ignoring COPY\n"); + continue; + } + if(MI->isUnconditionalBranch()) { + if(MI->getOperand(0).getMBB() == Latch) { + LLVM_DEBUG(dbgs() << " ignoring unconditional branch to latch\n"); + continue; + } + if(MI->getOperand(0).getMBB() == Header) { + LLVM_DEBUG(dbgs() << " ignoring unconditional branch to header\n"); + continue; + } + if(MI->getOperand(0).getMBB() == ExitingBlock) { + LLVM_DEBUG(dbgs() << " ignoring unconditional branch to Exit\n"); + continue; + } + if(MI->getOperand(0).getMBB() == L->getExitBlock()) { + LLVM_DEBUG(dbgs() << " ignoring unconditional branch to Exit Block\n"); + continue; + } + } + if(MI->isDebugValue()) { + LLVM_DEBUG(dbgs() << " ignoring debug value\n"); + continue; + } + skip = false; + if(MI->isConditionalBranch()) { + for(auto MO : MI->operands()) + if(MO.isReg() && (MO.getReg() == *IV || MO.getReg() == *ICV) ) { + LLVM_DEBUG(dbgs()<<" ignoring conditional branch with inudction register usage\n"); + skip = true; + break; + } + } + if(skip) { + continue; + } + skip = false; + for(auto MO : MI->operands()) + if(MO.isReg() && (MO.getReg() == *IV) ) { + LLVM_DEBUG(dbgs()<<" skipped due to inudction register usage\n"); + skip = true; + break; + } + if(skip) { + continue; + } + if (isInvalidLoopOperation(MI)) { + LLVM_DEBUG(dbgs() << "Cannot convert to hw_loop due to:"; MI->dump()); + return 0; + } + Flops++; + } + } + return Flops; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/convertToHardwareLoop.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/convertToHardwareLoop.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9338fb17f831fde1a6df364975a20fd0aa9e6c97 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/convertToHardwareLoop.cpp @@ -0,0 +1,187 @@ +bool SNITCHFrepLoops::convertToHardwareLoop(MachineLoop *L) { + assert(L->getHeader() && "Loop without a header?"); + bool changed = false; + LLVM_DEBUG(L->dump();); + for (MachineLoop::iterator I = L->begin(), E = L->end(); I != E; ++I) { + changed |= convertToHardwareLoop(*I); + } + if(!L->isInnermost()) return false; + LLVM_DEBUG(dbgs()<<"-------------------\n"); + LLVM_DEBUG(dbgs()<<"Running on\n"); + LLVM_DEBUG(L->dump();); + LLVM_DEBUG(dbgs()<<"-------------------\n"); + if(!isMarkedForInference(L) && !EnableFrepInference) + return changed; + SmallVector OldInsts, NewInsts; + Register *IndReg, *IncReg; + LLVM_DEBUG(dbgs() << ">>>>> in getLoopTripCount()\n"); + CountValue *TripCount = getLoopTripCount(L, OldInsts, IndReg, IncReg); + if(TripCount == nullptr) { + LLVM_DEBUG(dbgs() << "trip count not found\n"); + return changed; + } + LLVM_DEBUG(dbgs() << "getLoopTripCount found count "; TripCount->print(dbgs(), TRI)); + LLVM_DEBUG(dbgs() << ">>>>> in containsInvalidInstruction()\n"); + SmallVector FPPhis; + unsigned nFlops = containsInvalidInstruction(L, IndReg, IncReg, FPPhis); + if (nFlops == 0) { + return changed; + } + LLVM_DEBUG(dbgs() << "No invalid instructions found\n"); + MachineBasicBlock *ControlBlock = L->findLoopControlBlock(); + if (!ControlBlock) { + return changed; + } + LLVM_DEBUG(dbgs()<<"ControlBlock: " << ControlBlock->getName() << "\n"); + MachineBasicBlock::iterator LastI = ControlBlock->getFirstTerminator(); + if (LastI == ControlBlock->end()) { + return changed; + } + MachineBasicBlock *Preheader = MLI->findLoopPreheader(L, SpecPreheader); + if (!Preheader) { + dbgs() << "No preheader found\n"; + return changed; + } + if (TripCount->isReg()) { + dbgs() << "Don't know yet how to handle register trip counts\n"; + return changed; + } + LLVM_DEBUG(dbgs() << ">>>>> find loop start\n"); + MachineBasicBlock * TopBlock = L->getTopBlock(); + MachineBasicBlock * ExitBlock = L->getExitBlock(); + MachineBasicBlock * LoopStart = nullptr; + MachineBasicBlock * LoopSucc = nullptr; + MachineBasicBlock * LatchBlock = L->getLoopLatch(); + MachineBasicBlock * Header = L->getHeader(); + MachineBasicBlock * TB = nullptr, * FB = nullptr; + SmallVector Cond; + LLVM_DEBUG(dbgs()<<"TopBlock: " << TopBlock->getName() << "\n"); + bool branchNotFound = TII->analyzeBranch(*ControlBlock, TB, FB, Cond, false); + if (ControlBlock != LatchBlock) { + if (branchNotFound) { + return changed; + } + if (L->contains(TB)) { + LoopStart = TB; + LoopSucc = FB; + } + else if (L->contains(FB)) { + LoopStart = FB; + LoopSucc = TB; + } + else { + return changed; + } + } + else { + LoopStart = TopBlock; + LoopSucc = L->contains(TB) ? FB : TB; + } + assert(LoopStart != nullptr && "Didn't find loop start!"); + LLVM_DEBUG(dbgs()<<"LoopStart: " << LoopStart->getName()<<" LoopSucc: " << LoopSucc->getName() << "\n"); + if (!ExitBlock) { + dbgs() << "no exit block found\n"; + return changed; + } + LLVM_DEBUG(dbgs() << ">>>>> find loop size\n"); + unsigned loopSize = 0; + const unsigned instructionSize = 4; + for (const MachineBasicBlock *LB : L->getBlocks()) { + loopSize += instructionSize * LB->size(); + if (loopSize > 0xFFF) { + dbgs() << "loopsize exceeds limit: "<>>>> insert frep\n"); + MachineBasicBlock::iterator InsertPos = TopBlock->getFirstNonPHI(); + LLVM_DEBUG(dbgs() << "Change to hardware loop at "; L->dump()); + DebugLoc DL; + if (InsertPos != Header->end()) + DL = InsertPos->getDebugLoc(); + if (TripCount->isReg()) { + unsigned CountReg = MRI->createVirtualRegister(&RISCV::GPRRegClass); + BuildMI(*TopBlock, InsertPos, DL, TII->get(TargetOpcode::COPY), CountReg).addReg(TripCount->getReg(), 0, TripCount->getSubReg()); + BuildMI(*TopBlock, InsertPos, DL, TII->get(RISCV::ADDI)).addReg(CountReg).addReg(CountReg).addImm(-1); + auto hwloop = BuildMI(*TopBlock, InsertPos, DL, TII->get(RISCV::FREP_O)).addReg(CountReg).addImm(nFlops).addImm(0).addImm(0); + KnownHardwareLoops.insert(hwloop.getInstr()); + } + else { + assert(TripCount->isImm() && "Expecting immediate value for trip count if not register"); + int64_t CountImm = TripCount->getImm(); + unsigned CountReg = MRI->createVirtualRegister(&RISCV::GPRRegClass); + BuildMI(*TopBlock, InsertPos, DL, TII->get(RISCV::ADDI), CountReg).addReg(RISCV::X0).addImm(CountImm-1); + auto hwloop = BuildMI(*TopBlock, InsertPos, DL, TII->get(RISCV::FREP_O)).addReg(CountReg).addImm(nFlops).addImm(0).addImm(0); + KnownHardwareLoops.insert(hwloop.getInstr()); + } + delete TripCount; + ControlBlock->setHasAddressTaken(); + ControlBlock->setLabelMustBeEmitted(); + BlockAddress::get(const_cast(ControlBlock->getBasicBlock())); + LLVM_DEBUG(dbgs() << ">>>>> cleanup\n"); + if(FL->isCondExit && LatchBlock==ControlBlock) { + assert(FL->condTerm != nullptr && "Expected a reference to the conditional term"); + assert(LoopSucc != nullptr && "Expected a loop successor for unconditional branch"); + LLVM_DEBUG(dbgs()<<"Change conditional exit branch to uncondition with target " << LoopSucc->getName() << "\n"); + LLVM_DEBUG(dbgs()<<" insert at"; FL->condTerm->dump()); + NewInsts.push_back(BuildMI(*FL->condTerm->getParent(), FL->condTerm, FL->condTerm->getDebugLoc(), TII->get(RISCV::PseudoBR)).addMBB(LoopSucc).getInstr()); + FL->condTerm->removeFromParent(); + } + else { + OldInsts.push_back(FL->condTerm); + } + for(unsigned j = 0; j < 2; ++j) + for (unsigned i = 0; i < OldInsts.size(); ++i) { + if(OldInsts[i] && OldInsts[i]->getParent()) { + LLVM_DEBUG(dbgs()<<"Check if can be removed:"; OldInsts[i]->dump()); + removeIfDead(OldInsts[i]); + } + } + for (MachineBasicBlock *MBB : L->getBlocks()) { + MachineBasicBlock::iterator term = MBB->getFirstTerminator(); + if(term == MBB->end()) + continue; + MachineBasicBlock::iterator nextTerm; + for(;term != MBB->end(); term = nextTerm) { + nextTerm = std::next(term); + unsigned skip = 0; + for(unsigned p = 0; p < NewInsts.size(); ++p) { + if(NewInsts[p] == term) { + skip = 1; + LLVM_DEBUG(dbgs()<<"skip removal of terminator"; term->dump()); + } + } + if(skip) continue; + if(term->isUnconditionalBranch() && + term->getOperand(0).getMBB() == Header) { + LLVM_DEBUG(dbgs()<<"removing unconditional backedge to header "; term->dump()); + if(!term->getParent()->isSuccessor(LoopSucc)) term->getParent()->addSuccessor(LoopSucc); + term->getParent()->removeSuccessor(Header); + term->removeFromParent(); + } + else if(term->isUnconditionalBranch() && + term->getOperand(0).getMBB() == LatchBlock) { + LLVM_DEBUG(dbgs()<<"removing unconditional backedge to latch "; term->dump()); + term->getParent()->removeSuccessor(LoopSucc); + term->removeFromParent(); + } + else if(term->isUnconditionalBranch() && + term->getOperand(0).getMBB() == LoopSucc) { + LLVM_DEBUG(dbgs()<<"removing unconditional branch to loop successor "; term->dump()); + term->removeFromParent(); + } + } + } + insertFPUBarrier(L, ExitBlock); + ++NumFrepLoops; + FL->TopBlock = TopBlock; + FL->ExitBlock = ExitBlock; + FL->LoopStart = LoopStart; + FL->LoopSucc = LoopSucc; + FL->LatchBlock = LatchBlock; + FL->Header = Header; + FL->TB = TB; + FL->TB = FB; + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/createPass.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/createPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..13afedbcaa1d50da9013e6346335c6c9abec58a3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/createPass.cpp @@ -0,0 +1,4 @@ +//zmcorrectzm +FunctionPass *createSNITCHFrepLoopsPass() { + return new SNITCHFrepLoops(); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/createSNITCHFrepLoopsPass.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/createSNITCHFrepLoopsPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..08c67b5d3aca9dafc9d664780176f3a1114b9854 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/createSNITCHFrepLoopsPass.cpp @@ -0,0 +1,3 @@ +FunctionPass *createSNITCHFrepLoopsPass() { + return new SNITCHFrepLoops(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/enumCountValueType.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/enumCountValueType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..84c79208998defdbb6d20f1bc3d4469dd0bcf0a5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/enumCountValueType.cpp @@ -0,0 +1,4 @@ +enum CountValueType { + CV_Register, + CV_Immediate +}; diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/enumKind.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/enumKind.cpp new file mode 100644 index 0000000000000000000000000000000000000000..06934a6723a77c148733266a6459f940fb54480b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/enumKind.cpp @@ -0,0 +1,15 @@ +enum Kind { + EQ = 0x01, + NE = 0x02, + L = 0x04, + G = 0x08, + U = 0x40, + LTs = L, + LEs = L | EQ, + GTs = G, + GEs = G | EQ, + LTu = L | U, + LEu = L | EQ | U, + GTu = G | U, + GEu = G | EQ | U +}; diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/findBranchInstruction.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/findBranchInstruction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4a57dc94a2983dd5351ab9f3f3d071bc49a33e25 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/findBranchInstruction.cpp @@ -0,0 +1,21 @@ +const MachineInstr *SNITCHFrepLoops::findBranchInstruction(MachineLoop *L) { + using namespace RISCV; + static const unsigned Bops[] = {BNE}; + unsigned insInBops = 0; + const MachineInstr *BI = nullptr; + for (MachineBasicBlock *MBB : L->getBlocks()) { + for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end(); MII != E; ++MII) { + const MachineInstr *MI = &*MII; + for(unsigned i = 0; i < sizeof(Bops)/sizeof(Bops[0]); ++i) + if(MI->getOpcode() == Bops[i]) { + BI = MI; + ++insInBops; + } + } + } + if(insInBops != 1) { + LLVM_DEBUG(dbgs() << "Multiple or none ("<findLoopPreheader(L, SpecPreheader); + MachineBasicBlock *Header = L->getHeader(); + MachineBasicBlock *Latch = L->getLoopLatch(); + MachineBasicBlock *ExitingBlock = L->findLoopControlBlock(); + if (!Header) { + return false; + } + if (!Preheader) { + return false; + } + if (!Latch) { + return false; + } + if (!ExitingBlock) { + return false; + } + LLVM_DEBUG(dbgs()<<"Found Header ["<getName()<<"], Preheader ["<getName()<<"], Latch ["<getName()<<"], ExitingBlock ["<getName()<<"]\n"); + bool latchExitOneBlock = (Latch == ExitingBlock); + LLVM_DEBUG(dbgs() << "latchExitOneBlock = "<; + using InductionMap = std::map; + InductionMap IndMap; + using instr_iterator = MachineBasicBlock::instr_iterator; + for (instr_iterator I = Header->instr_begin(), E = Header->instr_end(); I != E && I->isPHI(); ++I) { + MachineInstr *Phi = &*I; + LLVM_DEBUG(dbgs()<<"found PHI: "; Phi->dump()); + for (unsigned i = 1, n = Phi->getNumOperands(); i < n; i += 2) { + if (Phi->getOperand(i+1).getMBB() != Latch) { + continue; + } + unsigned PhiOpReg = Phi->getOperand(i).getReg(); + MachineInstr *DI = MRI->getVRegDef(PhiOpReg); + if (DI->getDesc().getOpcode() == RISCV::ADDI) { + unsigned InducReg = DI->getOperand(1).getReg(); + MachineOperand &Opnd2 = DI->getOperand(2); + int64_t V; + if (MRI->getVRegDef(InducReg) == Phi && checkForImmediate(Opnd2, V)) { + unsigned UpdReg = DI->getOperand(0).getReg(); + if(latchExitOneBlock) { + IndMap.insert(std::make_pair(UpdReg, std::make_pair(InducReg, V))); + } + else { + IndMap.insert(std::make_pair(InducReg, std::make_pair(UpdReg, V))); + } + } + } + } + } + if (IndMap.empty()) { + LLVM_DEBUG(dbgs()<<"Couldn't find any PHI nodes\n"); + return false; + } + MachineBasicBlock *TB = nullptr, *FB = nullptr; + SmallVector Cond; + bool NotAnalyzed = TII->analyzeBranch(*ExitingBlock, TB, FB, Cond, false); + if (NotAnalyzed || Cond.empty()) { + LLVM_DEBUG(dbgs()<<"Couldn't analyze block ("<getName()<<"] False dst: ["<getName()<<"]\n"); + MachineInstr *condTerm = &(*ExitingBlock->getFirstTerminator()); + MachineInstr *uncondTerm = &(*std::next(ExitingBlock->getFirstTerminator())); + if (!(condTerm->getDesc().isConditionalBranch() && uncondTerm->getDesc().isUnconditionalBranch())) { + return false; + } + LLVM_DEBUG(dbgs()<<"condTerm :"; condTerm->dump()); + LLVM_DEBUG(dbgs()<<"uncondTerm :"; uncondTerm->dump()); + LLVM_DEBUG(dbgs()<<"Cond[1] : "; Cond[1].dump()); + LLVM_DEBUG(dbgs()<<"Cond[2] : "; Cond[2].dump()); + FL->condTerm = condTerm; + FL->uncondTerm = uncondTerm; + unsigned CmpReg1 = Cond[1].isReg() ? (unsigned) Cond[1].getReg() : 0; + unsigned CmpReg2 = Cond[2].isReg() ? (unsigned) Cond[2].getReg() : 0; + InductionMap::iterator IndMapEnd = IndMap.end(); + InductionMap::iterator F = IndMapEnd; + if (CmpReg1 != 0) { + InductionMap::iterator F1 = IndMap.find(CmpReg1); + if (F1 != IndMapEnd) + F = F1; + } + if (CmpReg2 != 0) { + InductionMap::iterator F2 = IndMap.find(CmpReg2); + if (F2 != IndMapEnd) { + if (F != IndMapEnd) { + LLVM_DEBUG(dbgs() << "both PHI registers found in conditional, abort\n"); + return false; + } + F = F2; + } + } + if (F == IndMapEnd) { + LLVM_DEBUG(dbgs() << "no PHI registers found in conditional, abort\n"); + return false; + } + if(!latchExitOneBlock) { + IndReg = F->first; + IncReg = F->second.first; + IVBump = F->second.second; + BumpOp = MRI->getVRegDef(F->second.first); + } + else { + IndReg = F->second.first; + IncReg = F->first; + IVBump = F->second.second; + BumpOp = MRI->getVRegDef(F->first); + } + LLVM_DEBUG(dbgs()<< "Found induction! IndReg ["<(); + AU.addRequired(); + MachineFunctionPass::getAnalysisUsage(AU); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/getComparisonKind.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/getComparisonKind.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0739fb3f1ef31e46d55bb9e3394989737947bf54 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/getComparisonKind.cpp @@ -0,0 +1,26 @@ +SNITCHFrepLoops::Comparison::Kind SNITCHFrepLoops::getComparisonKind(unsigned CondOpc, MachineOperand *InitialValue, const MachineOperand *EndValue, int64_t IVBump) const { + Comparison::Kind Cmp = (Comparison::Kind)0; + switch (CondOpc) { + case RISCV::BEQ: + Cmp = Comparison::EQ; + break; + case RISCV::BNE: + Cmp = Comparison::NE; + break; + case RISCV::BLT: + Cmp = Comparison::LTs; + break; + case RISCV::BLTU: + Cmp = Comparison::LTu; + break; + case RISCV::BGE: + Cmp = Comparison::GEs; + break; + case RISCV::BGEU: + Cmp = Comparison::GEs; + break; + default: + return (Comparison::Kind)0; + } + return Cmp; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/getImm.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/getImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..926b8c43cd5728c5187b2fb95773e11602a6ae6b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/getImm.cpp @@ -0,0 +1,4 @@ +unsigned getImm() const { + assert(isImm() && "Wrong CountValue accessor"); + return Contents.ImmVal; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/getLoopTripCount.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/getLoopTripCount.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0f269f9f28645efa2261975ef486121e5ed4deef --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/getLoopTripCount.cpp @@ -0,0 +1,255 @@ +CountValue *SNITCHFrepLoops::getLoopTripCount(MachineLoop *L, SmallVectorImpl &OldInsts, Register *&InductionReg, Register *&IncrementReg) { + MachineBasicBlock *TopMBB = L->getTopBlock(); + MachineBasicBlock::pred_iterator PI = TopMBB->pred_begin(); + assert(PI != TopMBB->pred_end() && "Loop must have more than one incoming edge!"); + MachineBasicBlock *Backedge = *PI++; + if (PI == TopMBB->pred_end()) { + return nullptr; + } + MachineBasicBlock *Incoming = *PI++; + if (PI != TopMBB->pred_end()) { + return nullptr; + } + if (L->contains(Incoming)) { + if (L->contains(Backedge)) { + return nullptr; + } + std::swap(Incoming, Backedge); + } + else if (!L->contains(Backedge)) { + return nullptr; + } + LLVM_DEBUG(dbgs()<<"Contains Incoming: " << L->contains(Incoming)<<" Concains Backedge: " << L->contains(Backedge)<<"\n"); + MachineBasicBlock *ExitingBlock = L->findLoopControlBlock(); + if (!ExitingBlock) { + return nullptr; + } + LLVM_DEBUG(dbgs()<<"ExitingBlock (contains: "<contains(ExitingBlock)<<")\n"); + unsigned IndReg = 0, IncReg = 0; + int64_t IVBump = 0; + MachineInstr *BumpOp; + bool FoundIV = findInductionRegister(L, IndReg, IncReg, IVBump, BumpOp); + if (!FoundIV) { + return nullptr; + } + OldInsts.push_back(BumpOp); + MachineBasicBlock *Preheader = MLI->findLoopPreheader(L, SpecPreheader); + MachineOperand *InitialValue = nullptr; + MachineInstr *IV_Phi = MRI->getVRegDef(IndReg); + MachineBasicBlock *Latch = L->getLoopLatch(); + LLVM_DEBUG(dbgs()<<"IV_Phi: ";IV_Phi->dump()); + for (unsigned i = 1, n = IV_Phi->getNumOperands(); i < n; i += 2) { + MachineBasicBlock *MBB = IV_Phi->getOperand(i+1).getMBB(); + if (MBB == Preheader) + InitialValue = &IV_Phi->getOperand(i); + } + if (!InitialValue) { + return nullptr; + } + SmallVector Cond; + MachineBasicBlock *TB = nullptr, *FB = nullptr; + bool NotAnalyzed = TII->analyzeBranch(*ExitingBlock, TB, FB, Cond, false); + if (NotAnalyzed) { + return nullptr; + } + bool isCondExit = true; + MachineBasicBlock *Header = L->getHeader(); + if((TB == Latch) || (TB == Header)) isCondExit = false; + bool isFirstOperandEndvalue = false; + const MachineOperand &Op1 = Cond[1]; + const MachineOperand &Op2 = Cond[2]; + const MachineOperand *EndValue = nullptr; + isFirstOperandEndvalue = Op1.getReg() != IndReg && Op1.getReg() != IncReg; + EndValue = (isFirstOperandEndvalue ? &Op1 : &Op2); + LLVM_DEBUG(dbgs() << "isFirstOperandEndvalue: " << isFirstOperandEndvalue << " isCondExit: " << isCondExit << "\n"); + OldInsts.push_back(MRI->getVRegDef(isFirstOperandEndvalue ? Op1.getReg() : Op2.getReg())); + Comparison::Kind Cmp; + unsigned CondOpc = Cond[0].getImm(); + Cmp = getComparisonKind(CondOpc, InitialValue, EndValue, IVBump); + if (!Cmp) { + return nullptr; + } + if (isFirstOperandEndvalue) { + Cmp = Comparison::getSwappedComparison(Cmp); + } + if (isCondExit) { + Cmp = Comparison::getNegatedComparison(Cmp); + } + if (InitialValue->isReg()) { + unsigned R = InitialValue->getReg(); + MachineBasicBlock *DefBB = MRI->getVRegDef(R)->getParent(); + if (!MDT->properlyDominates(DefBB, Header)) { + int64_t V; + if (!checkForImmediate(*InitialValue, V)) { + LLVM_DEBUG(dbgs()<<"can't determine initial value\n"); + return nullptr; + } + } + OldInsts.push_back(MRI->getVRegDef(R)); + } + if (EndValue->isReg()) { + unsigned R = EndValue->getReg(); + MachineBasicBlock *DefBB = MRI->getVRegDef(R)->getParent(); + if (!MDT->properlyDominates(DefBB, Header)) { + int64_t V; + if (!checkForImmediate(*EndValue, V)) { + LLVM_DEBUG(dbgs()<<"can't determine end value\n"); + return nullptr; + } + } + OldInsts.push_back(MRI->getVRegDef(R)); + } + FL->isFirstOperandEndvalue = isFirstOperandEndvalue; + FL->isCondExit = isCondExit; + InductionReg = new Register(IndReg); + IncrementReg = new Register(IncReg); + MachineBasicBlock *PH = MLI->findLoopPreheader(Loop, SpecPreheader); + assert (PH && "Should have a preheader by now"); + MachineBasicBlock::iterator InsertPos = PH->getFirstTerminator(); + DebugLoc DL; + if (InsertPos != PH->end()) + DL = InsertPos->getDebugLoc(); + const TargetRegisterClass *IntRC = &RISCV::GPRRegClass; + bool startIsImm = false, endIsImm = false; + int64_t immStart, immEnd; + startIsImm = checkForImmediate(*Start, immStart); + endIsImm = checkForImmediate(*End, immEnd); + if (endIsImm && !End->isImm()) { + if(immEnd == 0) { + unsigned VGPR = MRI->createVirtualRegister(IntRC); + MachineInstrBuilder ZeroInit = BuildMI(*PH, InsertPos, DL, TII->get(TargetOpcode::COPY), VGPR); + ZeroInit.addReg(RISCV::X0); + End = &ZeroInit->getOperand(0); + } + } + bool CmpLess = Cmp & Comparison::L; + bool CmpGreater = Cmp & Comparison::G; + bool CmpHasEqual = Cmp & Comparison::EQ; + if (!Start->isReg() && !startIsImm) { + return nullptr; + } + if (!End->isReg() && !endIsImm) { + return nullptr; + } + if (CmpLess && IVBump < 0) { + return nullptr; + } + if (CmpGreater && IVBump > 0) { + return nullptr; + } + if (IVBump == 0) { + return nullptr; + } + if (startIsImm && endIsImm) { + if(!CmpHasEqual) { + return nullptr; + } + int64_t Dist = std::max(immStart, immEnd) - std::min(immStart, immEnd); + if (Dist == 0) { + return nullptr; + } + if (Cmp != Comparison::EQ) { + return nullptr; + } + bool Exact = (Dist % IVBump) == 0; + if (!Exact) { + return nullptr; + } + uint64_t Count = Dist / std::abs(IVBump); + if (Count > 0xFFFFFFFFULL) { + return nullptr; + } + return new CountValue(CountValue::CV_Immediate, Count); + } + LoopFeederMap LoopFeederPhi; + if (loopCountMayWrapOrUnderFlow(Start, End, Loop->getLoopPreheader(), Loop, LoopFeederPhi)) { + return nullptr; + } + if (!isPowerOf2_64(std::abs(IVBump))) { + return nullptr; + } + if (IVBump < 0) { + std::swap(Start, End); + IVBump = -IVBump; + } + bool RegToImm = Start->isReg() && End->isImm(); + bool RegToReg = Start->isReg() && End->isReg(); + int64_t StartV = 0, EndV = 0; + if (Start->isImm()) { + StartV = Start->getImm(); + } + if (End->isImm()) { + EndV = End->getImm(); + } + int64_t AdjV = 0; + unsigned DistR, DistSR; + bool startIsImmZeroOrZeroReg = (Start->isImm() && StartV == 0); + if (!startIsImmZeroOrZeroReg && Start->isReg()) { + int64_t startImm; + if (checkForImmediate(*Start, startImm)) { + startIsImmZeroOrZeroReg = (startImm == 0); + } + } + if (startIsImmZeroOrZeroReg) { + DistR = End->getReg(); + DistSR = End->getSubReg(); + } + else { + const MCInstrDesc &SubD = RegToReg ? TII->get(RISCV::SUB) : (RegToImm ? TII->get(RISCV::SUB) /* TODO */ : TII->get(RISCV::ADDI)); + if (RegToReg || RegToImm) { + unsigned SubR = MRI->createVirtualRegister(IntRC); + MachineInstrBuilder SubIB = BuildMI(*PH, InsertPos, DL, SubD, SubR); + if (RegToReg) { + SubIB.addReg(End->getReg(), 0, End->getSubReg()).addReg(Start->getReg(), 0, Start->getSubReg()); + } + else { + MachineBasicBlock::iterator ThisInsertPos = InsertPos; + ThisInsertPos--; + unsigned ImmToRegReg = MRI->createVirtualRegister(IntRC); + MachineInstrBuilder ImmToReg = BuildMI(*PH, ThisInsertPos, DL, TII->get(RISCV::ADDI), ImmToRegReg); + ImmToReg.addReg(RISCV::X0).addImm(EndV); + SubIB.addReg(ImmToReg->getOperand(0).getReg()).addReg(Start->getReg(), 0, Start->getSubReg()); + } + DistR = SubR; + } + else { + const MachineInstr *EndValInstr = MRI->getVRegDef(End->getReg()); + if (EndValInstr->getOpcode() == RISCV::ADDI && EndValInstr->getOperand(1).getSubReg() == 0 && EndValInstr->getOperand(2).getImm() == StartV) { + DistR = EndValInstr->getOperand(1).getReg(); + } + else { + unsigned SubR = MRI->createVirtualRegister(IntRC); + MachineInstrBuilder SubIB = BuildMI(*PH, InsertPos, DL, SubD, SubR); + SubIB.addReg(End->getReg(), 0, End->getSubReg()).addImm(-StartV); + DistR = SubR; + } + } + DistSR = 0; + } + unsigned AdjR, AdjSR; + if (AdjV == 0) { + AdjR = DistR; + AdjSR = DistSR; + } + else { + unsigned AddR = MRI->createVirtualRegister(IntRC); + MCInstrDesc const &AddD = TII->get(RISCV::ADDI); + BuildMI(*PH, InsertPos, DL, AddD, AddR).addReg(DistR, 0, DistSR).addImm(AdjV); + AdjR = AddR; + AdjSR = 0; + } + unsigned CountR, CountSR; + if (IVBump == 1) { + CountR = AdjR; + CountSR = AdjSR; + } + else { + unsigned Shift = Log2_32(IVBump); + unsigned LsrR = MRI->createVirtualRegister(IntRC); + const MCInstrDesc &LsrD = TII->get(RISCV::SRLI); + BuildMI(*PH, InsertPos, DL, LsrD, LsrR).addReg(AdjR, 0, AdjSR).addImm(Shift); + CountR = LsrR; + CountSR = 0; + } + return new CountValue(CountValue::CV_Register, CountR, CountSR); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/getNegatedComparison.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/getNegatedComparison.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8a13423387ee5fbe6555d5082ab4a403413de6f4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/getNegatedComparison.cpp @@ -0,0 +1,9 @@ +static Kind getNegatedComparison(Kind Cmp) { + if ((Cmp & L) || (Cmp & G)) { + return (Kind)((Cmp ^ (L | G)) ^ EQ); + } + if ((Cmp & NE) || (Cmp & EQ)) { + return (Kind)(Cmp ^ (EQ | NE)); + } + return (Kind)0; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/getPassName.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d51a27eb64338334a8a8b4c50e8f7bc5359d9db3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/getPassName.cpp @@ -0,0 +1,3 @@ +StringRef getPassName() const override { + return SNITCH_FREP_LOOPS_NAME; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/getReg.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/getReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2f6681dcc1a7d87c841a32fcfc8275dd4af179c7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/getReg.cpp @@ -0,0 +1,4 @@ +unsigned getReg() const { + assert(isReg() && "Wrong CountValue accessor"); + return Contents.R.Reg; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/getSubReg.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/getSubReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cff1bb27c34b61906a86c7f741e8de982019bb79 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/getSubReg.cpp @@ -0,0 +1,4 @@ +unsigned getSubReg() const { + assert(isReg() && "Wrong CountValue accessor"); + return Contents.R.Sub; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/getSwappedComparison.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/getSwappedComparison.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ec0cca39b910463d25f200de5c7324bd5d9368d2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/getSwappedComparison.cpp @@ -0,0 +1,7 @@ +static Kind getSwappedComparison(Kind Cmp) { + assert ((!((Cmp & L) && (Cmp & G))) && "Malformed comparison operator"); + if ((Cmp & L) || (Cmp & G)) { + return (Kind)(Cmp ^ (L|G)); + } + return Cmp; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/isDead.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/isDead.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ff9794a1cdfadf4848547056bb9b040d121307f1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/isDead.cpp @@ -0,0 +1,41 @@ +bool SNITCHFrepLoops::isDead(const MachineInstr *MI, SmallVectorImpl &DeadPhis) const { + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { + const MachineOperand &MO = MI->getOperand(i); + if (!MO.isReg() || !MO.isDef()) + continue; + unsigned Reg = MO.getReg(); + if (MRI->use_nodbg_empty(Reg)) + continue; + using use_nodbg_iterator = MachineRegisterInfo::use_nodbg_iterator; + use_nodbg_iterator I = MRI->use_nodbg_begin(Reg); + use_nodbg_iterator End = MRI->use_nodbg_end(); + if (std::next(I) != End) { + LLVM_DEBUG(dbgs() << " not dead because >2 uses\n"); + return false; + } + if(!I->getParent()->isPHI()) { + LLVM_DEBUG(dbgs() << " not dead because use is not PHI\n"); + return false; + } + MachineInstr *UsePhi = I->getParent(); + for (unsigned j = 0, f = UsePhi->getNumOperands(); j != f; ++j) { + const MachineOperand &OPO = UsePhi->getOperand(j); + if (!OPO.isReg() || !OPO.isDef()) + continue; + unsigned OPReg = OPO.getReg(); + use_nodbg_iterator nextJ; + for (use_nodbg_iterator J = MRI->use_nodbg_begin(OPReg); J != End; J = nextJ) { + nextJ = std::next(J); + MachineOperand &Use = *J; + MachineInstr *UseMI = Use.getParent(); + LLVM_DEBUG(dbgs()<<" checking use:\n"; UseMI->dump()); + if (MI != UseMI) { + LLVM_DEBUG(dbgs() << " not dead because the phi node has a user that is not MI\n"); + return false; + } + } + } + DeadPhis.push_back(UsePhi); + } + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/isImm.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/isImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..dc64ab4323d8f6b869d0a1cef8d7218e4ab79081 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/isImm.cpp @@ -0,0 +1,3 @@ +bool isImm() const { + return Kind == CV_Immediate; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/isInvalidLoopOperation.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/isInvalidLoopOperation.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2fd90d29334564ea9e328e2ddba1da8b21207bcf --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/isInvalidLoopOperation.cpp @@ -0,0 +1,10 @@ +bool SNITCHFrepLoops::isInvalidLoopOperation(const MachineInstr *MI) const { + for(auto MO : MI->operands()) { + if(MO.isReg() && MO.getReg().isVirtual()) { + if(MRI->getRegClass(MO.getReg()) != &RISCV::FPR64RegClass || MRI->getRegClass(MO.getReg()) != &RISCV::FPR32RegClass) { + return false; + } + } + } + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/isReg.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/isReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..39a3b1a4a320cf5fa42671064beafec9eaf2aced --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/isReg.cpp @@ -0,0 +1,3 @@ +bool isReg() const { + return Kind == CV_Register; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/isSigned.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/isSigned.cpp new file mode 100644 index 0000000000000000000000000000000000000000..dc85ce445f35cd0e967ac51228897ff83c7ccf54 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/isSigned.cpp @@ -0,0 +1,3 @@ +static bool isSigned(Kind Cmp) { + return (Cmp & (L | G) && !(Cmp & U)); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/isUnsigned.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/isUnsigned.cpp new file mode 100644 index 0000000000000000000000000000000000000000..832beba9cac1339893e9305ccd1698e085711c36 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/isUnsigned.cpp @@ -0,0 +1,3 @@ +static bool isUnsigned(Kind Cmp) { + return (Cmp & U); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/print.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/print.cpp new file mode 100644 index 0000000000000000000000000000000000000000..feadf81810e5e69db66550e0bcf6a42819a2de87 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/print.cpp @@ -0,0 +1,8 @@ +void print(raw_ostream &OS, const TargetRegisterInfo *TRI = nullptr) const { + if (isReg()) { + OS << "register: " << printReg(Contents.R.Reg, TRI, Contents.R.Sub) << '\n'; + } + if (isImm()) { + OS << "immediate: " << Contents.ImmVal << '\n'; + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/removeIfDead.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/removeIfDead.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8b94424170126b61438b016629a75041ba5f7119 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/removeIfDead.cpp @@ -0,0 +1,26 @@ +void SNITCHFrepLoops::removeIfDead(MachineInstr *MI) { + SmallVector DeadPhis; + if (isDead(MI, DeadPhis)) { + LLVM_DEBUG(dbgs() << "HW looping will remove: " << *MI); + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { + const MachineOperand &MO = MI->getOperand(i); + if (!MO.isReg() || !MO.isDef()) + continue; + unsigned Reg = MO.getReg(); + MachineRegisterInfo::use_iterator nextI; + for (MachineRegisterInfo::use_iterator I = MRI->use_begin(Reg), E = MRI->use_end(); I != E; I = nextI) { + nextI = std::next(I); + MachineOperand &Use = *I; + MachineInstr *UseMI = I->getParent(); + if (UseMI == MI) + continue; + if (Use.isDebug()) + UseMI->getOperand(0).setReg(0U); + } + } + MI->eraseFromParent(); + for (unsigned i = 0; i < DeadPhis.size(); ++i) { + DeadPhis[i]->eraseFromParent(); + } + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..58b60bb37ed73781da6ca6dc74d21f33360aa737 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/runOnMachineFunction.cpp @@ -0,0 +1,26 @@ +bool SNITCHFrepLoops::runOnMachineFunction(MachineFunction &MF) { + LLVM_DEBUG(dbgs()<<"------------ Snitch Frep Loops ------------\n"); + bool Changed = false; + MLI = &getAnalysis(); + MRI = &MF.getRegInfo(); + MDT = &getAnalysis(); + const RISCVSubtarget &HST = MF.getSubtarget(); + TII = HST.getInstrInfo(); + TRI = HST.getRegisterInfo(); + for (auto &L : *MLI) + if (L->isOutermost()) { + FL = new FrepLoop(L); + Changed |= convertToHardwareLoop(L); + delete FL; + } + for (auto &MBB : MF) { + MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end(); + while (MBBI != E) { + MachineBasicBlock::iterator NMBBI = std::next(MBBI); + if(MBBI->getOpcode() == RISCV::PseudoFrepInfer) + MBBI->removeFromParent(); + MBBI = NMBBI; + } + } + return Changed; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/unionValues.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/unionValues.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5ba190c6eef41533e7debd2511464194bd8c9427 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Optimization/SNITCHFrepLoops/unionValues.cpp @@ -0,0 +1,7 @@ +union Values { + struct { + unsigned Reg; + unsigned Sub; + } R; + unsigned ImmVal; +} Contents; diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/InstrInfo.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/InstrInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..748278cc79300d8a5ec326134622a47f923f34f6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/InstrInfo.cpp @@ -0,0 +1,2 @@ +RISCVInstrInfo::RISCVInstrInfo(RISCVSubtarget &STI) : RISCVGenInstrInfo( RISCV::ADJCALLSTACKDOWN, RISCV::ADJCALLSTACKUP), STI(STI) { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/analyzeBranch.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/analyzeBranch.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d86ee8cd4f838d592e68b58e88bd472f670cf458 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/analyzeBranch.cpp @@ -0,0 +1,43 @@ +bool RISCVInstrInfo::analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl &Cond, bool AllowModify) const { + TBB = FBB = nullptr; + Cond.clear(); + MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr(); + if (I == MBB.end() || !isUnpredicatedTerminator(*I)) { + return false; + } + MachineBasicBlock::iterator FirstUncondOrIndirectBr = MBB.end(); + int NumTerminators = 0; + for (auto J = I.getReverse(); J != MBB.rend() && isUnpredicatedTerminator(*J); J++) { + NumTerminators++; + if (J->getDesc().isUnconditionalBranch() || J->getDesc().isIndirectBranch()) { + FirstUncondOrIndirectBr = J.getReverse(); + } + } + if (AllowModify && FirstUncondOrIndirectBr != MBB.end()) { + while (std::next(FirstUncondOrIndirectBr) != MBB.end()) { + std::next(FirstUncondOrIndirectBr)->eraseFromParent(); + NumTerminators--; + } + I = FirstUncondOrIndirectBr; + } + if (I->getDesc().isIndirectBranch()) { + return true; + } + if (NumTerminators > 2) { + return true; + } + if (NumTerminators == 1 && I->getDesc().isUnconditionalBranch()) { + TBB = getBranchDestBlock(*I); + return false; + } + if (NumTerminators == 1 && I->getDesc().isConditionalBranch()) { + parseCondBranch(*I, TBB, Cond); + return false; + } + if (NumTerminators == 2 && std::prev(I)->getDesc().isConditionalBranch() && I->getDesc().isUnconditionalBranch()) { + parseCondBranch(*std::prev(I), TBB, Cond); + FBB = getBranchDestBlock(*I); + return false; + } + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/areMemAccessesTriviallyDisjoint.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/areMemAccessesTriviallyDisjoint.cpp new file mode 100644 index 0000000000000000000000000000000000000000..84c10e93be57ac9e456e12ff8b4453d873ba50fa --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/areMemAccessesTriviallyDisjoint.cpp @@ -0,0 +1,22 @@ +bool RISCVInstrInfo::areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const { + assert(MIa.mayLoadOrStore() && "MIa must be a load or store."); + assert(MIb.mayLoadOrStore() && "MIb must be a load or store."); + if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() || MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) { + return false; + } + const TargetRegisterInfo *TRI = STI.getRegisterInfo(); + const MachineOperand *BaseOpA = nullptr, *BaseOpB = nullptr; + int64_t OffsetA = 0, OffsetB = 0; + unsigned int WidthA = 0, WidthB = 0; + if (getMemOperandWithOffsetWidth(MIa, BaseOpA, OffsetA, WidthA, TRI) && getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, WidthB, TRI)) { + if (BaseOpA->isIdenticalTo(*BaseOpB)) { + int LowOffset = std::min(OffsetA, OffsetB); + int HighOffset = std::max(OffsetA, OffsetB); + int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB; + if (LowOffset + LowWidth <= HighOffset) { + return true; + } + } + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/buildOutlinedFrame.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/buildOutlinedFrame.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bcb2321cf28d3ecdc90f327ad2cbeb346542dafc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/buildOutlinedFrame.cpp @@ -0,0 +1,17 @@ +void RISCVInstrInfo::buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const { + bool Changed = true; + while (Changed) { + Changed = false; + auto I = MBB.begin(); + auto E = MBB.end(); + for (; I != E; ++I) { + if (I->isCFIInstruction()) { + I->removeFromParent(); + Changed = true; + break; + } + } + } + MBB.addLiveIn(RISCV::X5); + MBB.insert(MBB.end(), BuildMI(MF, DebugLoc(), get(RISCV::JALR)).addReg(RISCV::X0, RegState::Define).addReg(RISCV::X5).addImm(0)); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/copyPhysReg.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/copyPhysReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3d86b0f026bac722f6a15accf9e7a9fe2a33d932 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/copyPhysReg.cpp @@ -0,0 +1,36 @@ + +void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg, bool KillSrc) const { + if (RISCV::GPRRegClass.contains(DstReg, SrcReg)) { + BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg).addReg(SrcReg, getKillRegState(KillSrc)).addImm(0); + return; + } + if (RISCV::FPR16RegClass.contains(DstReg, SrcReg)) { + BuildMI(MBB, MBBI, DL, get(RISCV::FSGNJ_H), DstReg).addReg(SrcReg, getKillRegState(KillSrc)).addReg(SrcReg, getKillRegState(KillSrc)); + return ; + } + if (RISCV::FPR32RegClass.contains(DstReg, SrcReg)) { + BuildMI(MBB, MBBI, DL, get(RISCV::FSGNJ_S), DstReg).addReg(SrcReg, getKillRegState(KillSrc)).addReg(SrcReg, getKillRegState(KillSrc)); + return ; + } + if (RISCV::FPR64RegClass.contains(DstReg, SrcReg)) { + BuildMI(MBB, MBBI, DL, get(RISCV::FSGNJ_D;), DstReg).addReg(SrcReg, getKillRegState(KillSrc)).addReg(SrcReg, getKillRegState(KillSrc)); + return ; + } + if (RISCV::VRRegClass.contains(DstReg, SrcReg)) { + BuildMI(MBB, MBBI, DL, get(RISCV::PseudoVMV1R_V), DstReg).addReg(SrcReg, getKillRegState(KillSrc)); + return ; + } + if (RISCV::VRM2RegClass.contains(DstReg, SrcReg)) { + BuildMI(MBB, MBBI, DL, get(RISCV::PseudoVMV2R_V), DstReg).addReg(SrcReg, getKillRegState(KillSrc)); + return ; + } + if (RISCV::VRM4RegClass.contains(DstReg, SrcReg)) { + BuildMI(MBB, MBBI, DL, get(RISCV::PseudoVMV4R_V), DstReg).addReg(SrcReg, getKillRegState(KillSrc)); + return ; + } + if (RISCV::VRM8RegClass.contains(DstReg, SrcReg)) { + BuildMI(MBB, MBBI, DL, get(RISCV::PseudoVMV8R_V), DstReg).addReg(SrcReg, getKillRegState(KillSrc)); + return ; + } + llvm_unreachable("Impossible reg-to-reg copy"); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/decomposeMachineOperandsTargetFlags.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/decomposeMachineOperandsTargetFlags.cpp new file mode 100644 index 0000000000000000000000000000000000000000..371fad319519ebb28816b75c9b94dbc64622e257 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/decomposeMachineOperandsTargetFlags.cpp @@ -0,0 +1,4 @@ +std::pair RISCVInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const { + const unsigned Mask = RISCVII::MO_DIRECT_FLAG_MASK; + return std::make_pair(TF & Mask, TF & ~Mask); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/getBranchDestBlock.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/getBranchDestBlock.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cae1b652d38074daf74f2f39cb157d40817089f3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/getBranchDestBlock.cpp @@ -0,0 +1,4 @@ +MachineBasicBlock *RISCVInstrInfo::getBranchDestBlock(const MachineInstr &MI) const { + assert(MI.getDesc().isBranch() && "Unexpected opcode!"); + return MI.getOperand(MI.getNumExplicitOperands() - 1).getMBB(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/getInstSizeInBytes.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/getInstSizeInBytes.cpp new file mode 100644 index 0000000000000000000000000000000000000000..36cddb1f977605d0d6516645512555561b85e5a8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/getInstSizeInBytes.cpp @@ -0,0 +1,58 @@ +unsigned RISCVInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const { + unsigned Opcode = MI.getOpcode(); + switch (Opcode) { + default: { + if (MI.getParent() && MI.getParent()->getParent()) { + const auto MF = MI.getMF(); + const auto &TM = static_cast(MF->getTarget()); + const MCRegisterInfo &MRI = *TM.getMCRegisterInfo(); + const MCSubtargetInfo &STI = *TM.getMCSubtargetInfo(); + const RISCVSubtarget &ST = MF->getSubtarget(); + if (isCompressibleInst(MI, &ST, MRI, STI)) { + return 2; + } + } + return get(Opcode).getSize(); + } + case TargetOpcode::EH_LABEL: + case TargetOpcode::IMPLICIT_DEF: + case TargetOpcode::KILL: + case TargetOpcode::DBG_VALUE: + return 0; + case RISCV::PseudoCALLReg: + case RISCV::PseudoCALL: + case RISCV::PseudoJump: + case RISCV::PseudoTAIL: + case RISCV::PseudoLLA: + case RISCV::PseudoLA: + case RISCV::PseudoLA_TLS_IE: + case RISCV::PseudoLA_TLS_GD: + return 8; + case RISCV::PseudoAtomicLoadNand32: + case RISCV::PseudoAtomicLoadNand64: + return 20; + case RISCV::PseudoMaskedAtomicSwap32: + case RISCV::PseudoMaskedAtomicLoadAdd32: + case RISCV::PseudoMaskedAtomicLoadSub32: + return 28; + case RISCV::PseudoMaskedAtomicLoadNand32: + return 32; + case RISCV::PseudoMaskedAtomicLoadMax32: + case RISCV::PseudoMaskedAtomicLoadMin32: + return 44; + case RISCV::PseudoMaskedAtomicLoadUMax32: + case RISCV::PseudoMaskedAtomicLoadUMin32: + return 36; + case RISCV::PseudoCmpXchg32: + case RISCV::PseudoCmpXchg64: + return 16; + case RISCV::PseudoMaskedCmpXchg32: + return 32; + case TargetOpcode::INLINEASM: + case TargetOpcode::INLINEASM_BR: { + const MachineFunction &MF = *MI.getParent()->getParent(); + const auto &TM = static_cast(MF.getTarget()); + return getInlineAsmLength(MI.getOperand(0).getSymbolName(), *TM.getMCAsmInfo()); + } + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/getMemOperandWithOffsetWidth.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/getMemOperandWithOffsetWidth.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c047851933d8e04b86ede618330b87e4ca0b4859 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/getMemOperandWithOffsetWidth.cpp @@ -0,0 +1,18 @@ +bool RISCVInstrInfo::getMemOperandWithOffsetWidth(const MachineInstr &LdSt, const MachineOperand *&BaseReg, int64_t &Offset, unsigned &Width, const TargetRegisterInfo *TRI) const { + if (!LdSt.mayLoadOrStore()) { + return false; + } + if (LdSt.getNumExplicitOperands() != 3) { + return false; + } + if (!LdSt.getOperand(1).isReg() || !LdSt.getOperand(2).isImm()) { + return false; + } + if (!LdSt.hasOneMemOperand()) { + return false; + } + Width = (*LdSt.memoperands_begin())->getSize(); + BaseReg = &LdSt.getOperand(1); + Offset = LdSt.getOperand(2).getImm(); + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/getOutliningCandidateInfo.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/getOutliningCandidateInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c46ce820392baeb07d11944ca084ec5cba2091c7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/getOutliningCandidateInfo.cpp @@ -0,0 +1,27 @@ +outliner::OutlinedFunction RISCVInstrInfo::getOutliningCandidateInfo(std::vector &RepeatedSequenceLocs) const { + auto CannotInsertCall = [](outliner::Candidate &C) { + const TargetRegisterInfo *TRI = C.getMF()->getSubtarget().getRegisterInfo(); + C.initLRU(*TRI); + LiveRegUnits LRU = C.LRU; + return !LRU.available(RISCV::X5); + }; + llvm::erase_if(RepeatedSequenceLocs, CannotInsertCall); + if (RepeatedSequenceLocs.size() < 2) { + return outliner::OutlinedFunction(); + } + unsigned SequenceSize = 0; + auto I = RepeatedSequenceLocs[0].front(); + auto E = std::next(RepeatedSequenceLocs[0].back()); + for (; I != E; ++I) { + SequenceSize += getInstSizeInBytes(*I); + } + unsigned CallOverhead = 8; + for (auto &C : RepeatedSequenceLocs) { + C.setCallInfo(MachineOutlinerDefault, CallOverhead); + } + unsigned FrameOverhead = 4; + if (RepeatedSequenceLocs[0].getMF()->getSubtarget().getFeatureBits()[RISCV::FeatureStdExtC]) { + FrameOverhead = 2; + } + return outliner::OutlinedFunction(RepeatedSequenceLocs, SequenceSize, FrameOverhead, MachineOutlinerDefault); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/getOutliningType.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/getOutliningType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9a3dd323cf6a01428a868ff2e81d3613bad1aad4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/getOutliningType.cpp @@ -0,0 +1,32 @@ +outliner::InstrType RISCVInstrInfo::getOutliningType(MachineBasicBlock::iterator &MBBI, unsigned Flags) const { + MachineInstr &MI = *MBBI; + MachineBasicBlock *MBB = MI.getParent(); + const TargetRegisterInfo *TRI = MBB->getParent()->getSubtarget().getRegisterInfo(); + if (MI.isPosition()) { + if (MI.isCFIInstruction()) { + return outliner::InstrType::Invisible; + } + return outliner::InstrType::Illegal; + } + if (MI.isInlineAsm()) { + return outliner::InstrType::Illegal; + } + if (MI.isTerminator() && !MBB->succ_empty()) { + return outliner::InstrType::Illegal; + } + if (MI.isReturn()) { + return outliner::InstrType::Illegal; + } + if (MI.modifiesRegister(RISCV::X5, TRI) || MI.getDesc().hasImplicitDefOfPhysReg(RISCV::X5)) { + return outliner::InstrType::Illegal; + } + for (const auto &MO : MI.operands()) { + if (MO.isMBB() || MO.isBlockAddress() || MO.isCPI()) { + return outliner::InstrType::Illegal; + } + } + if (MI.isMetaInstruction()) { + return outliner::InstrType::Invisible; + } + return outliner::InstrType::Legal; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/getSerializableDirectMachineOperandTargetFlags.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/getSerializableDirectMachineOperandTargetFlags.cpp new file mode 100644 index 0000000000000000000000000000000000000000..263cfb665f67d84e93145d137c3d2ab6ab3b7d06 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/getSerializableDirectMachineOperandTargetFlags.cpp @@ -0,0 +1,5 @@ +ArrayRef> RISCVInstrInfo::getSerializableDirectMachineOperandTargetFlags() const { + using namespace RISCVII; + static const std::pair TargetFlags[] = {{MO_CALL, "riscv-call"},{MO_PLT, "riscv-plt"},{MO_LO, "riscv-lo"},{MO_HI, "riscv-hi"},{MO_PCREL_LO, "riscv-pcrel-lo"},{MO_PCREL_HI, "riscv-pcrel-hi"},{MO_GOT_HI, "riscv-got-hi"},{MO_TPREL_LO, "riscv-tprel-lo"},{MO_TPREL_HI, "riscv-tprel-hi"},{MO_TPREL_ADD, "riscv-tprel-add"},{MO_TLS_GOT_HI, "riscv-tls-got-hi"},{MO_TLS_GD_HI, "riscv-tls-gd-hi"}}; + return makeArrayRef(TargetFlags); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/insertBranch.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/insertBranch.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cf05adfad8dde46f66f5392c7b824e5c8eb9fd87 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/insertBranch.cpp @@ -0,0 +1,27 @@ +unsigned RISCVInstrInfo::insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, const DebugLoc &DL, int *BytesAdded) const { + if (BytesAdded) { + *BytesAdded = 0; + } + assert(TBB && "insertBranch must not be told to insert a fallthrough"); + assert((Cond.size() == 3 || Cond.size() == 0) && "RISCV branch conditions have two components!"); + if (Cond.empty()) { + MachineInstr &MI = *BuildMI(&MBB, DL, get(RISCV::PseudoBR)).addMBB(TBB); + if (BytesAdded) { + *BytesAdded = *BytesAdded + getInstSizeInBytes(MI); + } + return 1; + } + unsigned Opc = Cond[0].getImm(); + MachineInstr &CondMI = *BuildMI(&MBB, DL, get(Opc)).add(Cond[1]).add(Cond[2]).addMBB(TBB); + if (BytesAdded) { + *BytesAdded = *BytesAdded + getInstSizeInBytes(CondMI); + } + if (!FBB) { + return 1; + } + MachineInstr &MI = *BuildMI(&MBB, DL, get(RISCV::PseudoBR)).addMBB(FBB); + if (BytesAdded) { + *BytesAdded = *BytesAdded + getInstSizeInBytes(MI); + } + return 2; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/insertIndirectBranch.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/insertIndirectBranch.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b1492bf3ef915bf02e849b172335d6538b40164d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/insertIndirectBranch.cpp @@ -0,0 +1,19 @@ +unsigned RISCVInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &DestBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS) const { + assert(RS && "RegScavenger required for long branching"); + assert(MBB.empty() && "new block should be inserted for expanding unconditional branch"); + assert(MBB.pred_size() == 1); + MachineFunction *MF = MBB.getParent(); + MachineRegisterInfo &MRI = MF->getRegInfo(); + if (!isInt<32>(BrOffset)) { + report_fatal_error("Branch offsets outside of the signed 32-bit range not supported"); + } + Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); + auto II = MBB.end(); + MachineInstr &MI = *BuildMI(MBB, II, DL, get(RISCV::PseudoJump)).addReg(ScratchReg, RegState::Define | RegState::Dead).addMBB(&DestBB, RISCVII::MO_CALL); + RS->enterBasicBlockEnd(MBB); + unsigned Scav = RS->scavengeRegisterBackwards(RISCV::GPRRegClass, MI.getIterator(), false, 0); + MRI.replaceRegWith(ScratchReg, Scav); + MRI.clearVirtRegs(); + RS->setRegUsed(Scav); + return 8; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/insertOutlinedCall.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/insertOutlinedCall.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bc4fc501f51d854d8e3da7721b447adee3a5d2f1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/insertOutlinedCall.cpp @@ -0,0 +1,4 @@ +MachineBasicBlock::iterator RISCVInstrInfo::insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, const outliner::Candidate &C) const { + It = MBB.insert(It, BuildMI(MF, DebugLoc(), get(RISCV::PseudoCALLReg), RISCV::X5).addGlobalAddress(M.getNamedValue(MF.getName()), 0, RISCVII::MO_CALL)); + return It; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/isAsCheapAsAMove.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/isAsCheapAsAMove.cpp new file mode 100644 index 0000000000000000000000000000000000000000..39ad00c050eb6a3d2f6bc0acda49ffd7a8a5b252 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/isAsCheapAsAMove.cpp @@ -0,0 +1,19 @@ +bool RISCVInstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const { + const unsigned Opcode = MI.getOpcode(); + if(Opcode ==RISCV::FSGNJ_D) { + return MI.getOperand(1).isReg() && MI.getOperand(2).isReg() && MI.getOperand(1).getReg() == MI.getOperand(2).getReg(); + } + if(Opcode ==RISCV::FSGNJ_S) { + return MI.getOperand(1).isReg() && MI.getOperand(2).isReg() && MI.getOperand(1).getReg() == MI.getOperand(2).getReg(); + } + if(Opcode ==RISCV::ADDI) { + return (MI.getOperand(1).isReg() && MI.getOperand(1).getReg() == RISCV::X0) || (MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0); + } + if(Opcode ==RISCV::ORI) { + return (MI.getOperand(1).isReg() && MI.getOperand(1).getReg() == RISCV::X0) || (MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0); + } + if(Opcode ==RISCV::XORI) { + return (MI.getOperand(1).isReg() && MI.getOperand(1).getReg() == RISCV::X0) || (MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0); + } + return MI.isAsCheapAsAMove(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/isBranchOffsetInRange.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/isBranchOffsetInRange.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f7230e1936b7ec5585c50d3dfc69cf9dffe19c26 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/isBranchOffsetInRange.cpp @@ -0,0 +1,21 @@ +bool RISCVInstrInfo::isBranchOffsetInRange(unsigned BranchOp, int64_t BrOffset) const { + unsigned XLen = STI.getXLen(); + switch (BranchOp) { + case RISCV::BEQ: + case RISCV::BNE: + case RISCV::BLT: + case RISCV::BGE: + case RISCV::BLTU: + case RISCV::BGEU: + case RISCV::P_BEQIMM: + case RISCV::P_BNEIMM: + return isIntN(13, BrOffset); + case RISCV::JAL: + case RISCV::PseudoBR: + return isIntN(21, BrOffset); + case RISCV::PseudoJump: + return isIntN(32, SignExtend64(BrOffset + 0x800, XLen)); + default: + llvm_unreachable("Unexpected opcode!"); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/isCopyInstrImpl.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/isCopyInstrImpl.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c815f394615b68f75ab7532e5b30d428b93b1d9a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/isCopyInstrImpl.cpp @@ -0,0 +1,21 @@ +Optional RISCVInstrInfo::isCopyInstrImpl(const MachineInstr &MI) const { + if (MI.isMoveReg()) { + return DestSourcePair{MI.getOperand(0), MI.getOperand(1)}; + } + if (MI.getOpcode() == RISCV::ADDI) { + if (MI.getOperand(1).isReg() && MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) { + return DestSourcePair{MI.getOperand(0), MI.getOperand(1)}; + } + } + if (MI.getOpcode() == RISCV::FSGNJ_D) { + if (MI.getOperand(1).isReg() && MI.getOperand(2).isReg() && MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) { + return DestSourcePair{MI.getOperand(0), MI.getOperand(1)}; + } + } + if (MI.getOpcode() == RISCV::FSGNJ_S) { + if (MI.getOperand(1).isReg() && MI.getOperand(2).isReg() && MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) { + return DestSourcePair{MI.getOperand(0), MI.getOperand(1)}; + } + } + return None; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/isFunctionSafeToOutlineFrom.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/isFunctionSafeToOutlineFrom.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9caad0ee4e4d0f3759c8d9c9fe481cee5f378ec5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/isFunctionSafeToOutlineFrom.cpp @@ -0,0 +1,10 @@ +bool RISCVInstrInfo::isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const { + const Function &F = MF.getFunction(); + if (!OutlineFromLinkOnceODRs && F.hasLinkOnceODRLinkage()) { + return false; + } + if (F.hasSection()) { + return false; + } + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/isLoadFromStackSlot.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/isLoadFromStackSlot.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2dd099d2cc9c5b17a2b05c2f8cadf6939da7b835 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/isLoadFromStackSlot.cpp @@ -0,0 +1,103 @@ +unsigned RISCVInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const { + if (MI.getOpcode() == RISCV::LB) { + if (MI.getOperand(1).isFI()) { + if (MI.getOperand(2).isImm()) { + if (MI.getOperand(2).getImm() == 0) { + FrameIndex = MI.getOperand(1).getIndex(); + return MI.getOperand(0).getReg(); + } + } + } + } + if (MI.getOpcode() == RISCV::LBU) { + if (MI.getOperand(1).isFI()) { + if (MI.getOperand(2).isImm()) { + if (MI.getOperand(2).getImm() == 0) { + FrameIndex = MI.getOperand(1).getIndex(); + return MI.getOperand(0).getReg(); + } + } + } + } + if (MI.getOpcode() == RISCV::LH) { + if (MI.getOperand(1).isFI()) { + if (MI.getOperand(2).isImm()) { + if (MI.getOperand(2).getImm() == 0) { + FrameIndex = MI.getOperand(1).getIndex(); + return MI.getOperand(0).getReg(); + } + } + } + } + if (MI.getOpcode() == RISCV::LHU) { + if (MI.getOperand(1).isFI()) { + if (MI.getOperand(2).isImm()) { + if (MI.getOperand(2).getImm() == 0) { + FrameIndex = MI.getOperand(1).getIndex(); + return MI.getOperand(0).getReg(); + } + } + } + } + if (MI.getOpcode() == RISCV::FLH) { + if (MI.getOperand(1).isFI()) { + if (MI.getOperand(2).isImm()) { + if (MI.getOperand(2).getImm() == 0) { + FrameIndex = MI.getOperand(1).getIndex(); + return MI.getOperand(0).getReg(); + } + } + } + } + if (MI.getOpcode() == RISCV::LW) { + if (MI.getOperand(1).isFI()) { + if (MI.getOperand(2).isImm()) { + if (MI.getOperand(2).getImm() == 0) { + FrameIndex = MI.getOperand(1).getIndex(); + return MI.getOperand(0).getReg(); + } + } + } + } + if (MI.getOpcode() == RISCV::FWL) { + if (MI.getOperand(1).isFI()) { + if (MI.getOperand(2).isImm()) { + if (MI.getOperand(2).getImm() == 0) { + FrameIndex = MI.getOperand(1).getIndex(); + return MI.getOperand(0).getReg(); + } + } + } + } + if (MI.getOpcode() == RISCV::LWU) { + if (MI.getOperand(1).isFI()) { + if (MI.getOperand(2).isImm()) { + if (MI.getOperand(2).getImm() == 0) { + FrameIndex = MI.getOperand(1).getIndex(); + return MI.getOperand(0).getReg(); + } + } + } + } + if (MI.getOpcode() == RISCV::LD) { + if (MI.getOperand(1).isFI()) { + if (MI.getOperand(2).isImm()) { + if (MI.getOperand(2).getImm() == 0) { + FrameIndex = MI.getOperand(1).getIndex(); + return MI.getOperand(0).getReg(); + } + } + } + } + if (MI.getOpcode() == RISCV::FLD) { + if (MI.getOperand(1).isFI()) { + if (MI.getOperand(2).isImm()) { + if (MI.getOperand(2).getImm() == 0) { + FrameIndex = MI.getOperand(1).getIndex(); + return MI.getOperand(0).getReg(); + } + } + } + } + return 0; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/isMBBSafeToOutlineFrom.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/isMBBSafeToOutlineFrom.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d9e89b48698e2fb498dd5f8e8facf15525e862aa --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/isMBBSafeToOutlineFrom.cpp @@ -0,0 +1,3 @@ +bool RISCVInstrInfo::isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, unsigned &Flags) const { + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/isSchedulingBoundary.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/isSchedulingBoundary.cpp new file mode 100644 index 0000000000000000000000000000000000000000..08854954eb2087e555e0d7c24cf0f493552b768a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/isSchedulingBoundary.cpp @@ -0,0 +1,14 @@ +bool RISCVInstrInfo::isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const { + if (TargetInstrInfo::isSchedulingBoundary(MI, MBB, MF)) { + return true; + } + switch (MI.getOpcode()) { + case RISCV::LOOP0setup: + case RISCV::LOOP1setup: + case RISCV::LOOP0setupi: + case RISCV::LOOP1setupi: + return true; + default:; + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/isStoreToStackSlot.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/isStoreToStackSlot.cpp new file mode 100644 index 0000000000000000000000000000000000000000..25f4bf9ad1bb3535889e398c48412ab3ff94334a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/isStoreToStackSlot.cpp @@ -0,0 +1,19 @@ +unsigned RISCVInstrInfo::isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const { + switch (MI.getOpcode()) { + default: + return 0; + case RISCV::SB: + case RISCV::SH: + case RISCV::SW: + case RISCV::FSH: + case RISCV::FSW: + case RISCV::SD: + case RISCV::FSD: + break; + } + if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) { + FrameIndex = MI.getOperand(1).getIndex(); + return MI.getOperand(0).getReg(); + } + return 0; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/loadRegFromStackSlot.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/loadRegFromStackSlot.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e71f82302950ea15b9fad418bc5c9ab1b10bd6be --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/loadRegFromStackSlot.cpp @@ -0,0 +1,31 @@ +void RISCVInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register DstReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const { + DebugLoc DL; + if (I != MBB.end()) { + DL = I->getDebugLoc(); + } + MachineFunction *MF = MBB.getParent(); + const MachineFrameInfo &MFI = MF->getFrameInfo(); + MachineMemOperand *MMO = MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOLoad, MFI.getObjectSize(FI), MFI.getObjectAlign(FI)); + unsigned Opcode; + if (RISCV::GPRRegClass.hasSubClassEq(RC)) { + Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ? RISCV::LW : RISCV::LD; + BuildMI(MBB, I, DL, get(Opcode), DstReg).addFrameIndex(FI).addImm(0).addMemOperand(MMO); + return ; + } + if (RISCV::FPR16RegClass.hasSubClassEq(RC)) { + Opcode = RISCV::FLH; + BuildMI(MBB, I, DL, get(Opcode), DstReg).addFrameIndex(FI).addImm(0).addMemOperand(MMO); + return ; + } + if (RISCV::FPR32RegClass.hasSubClassEq(RC)) { + Opcode = RISCV::FWL; + BuildMI(MBB, I, DL, get(Opcode), DstReg).addFrameIndex(FI).addImm(0).addMemOperand(MMO); + return ; + } + if (RISCV::FPR64RegClass.hasSubClassEq(RC)) { + Opcode = RISCV::FLD; + BuildMI(MBB, I, DL, get(Opcode), DstReg).addFrameIndex(FI).addImm(0).addMemOperand(MMO); + return ; + } + llvm_unreachable("Can't load this register from stack slot"); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/movImm.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/movImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c72f7f9e84e4ace08a3e3a7dad1d6a68cf683f24 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/movImm.cpp @@ -0,0 +1,26 @@ +void RISCVInstrInfo::movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register DstReg, uint64_t Val, MachineInstr::MIFlag Flag) const { + MachineRegisterInfo &MRI = MF->getRegInfo(); + MachineFunction *MF = MBB.getParent(); + bool IsRV64 = MF->getSubtarget().is64Bit(); + Register SrcReg = RISCV::X0; + Register Result = MRI.createVirtualRegister(&RISCV::GPRRegClass); + unsigned Num = 0; + if (!IsRV64 && !isInt<32>(Val)) { + report_fatal_error("Should only materialize 32-bit constants for RV32"); + } + RISCVMatInt::InstSeq Seq; + RISCVMatInt::generateInstSeq(Val, IsRV64, Seq); + assert(Seq.size() > 0); + for (RISCVMatInt::Inst &Inst : Seq) { + if (++Num == Seq.size()) { + Result = DstReg; + } + if (Inst.Opc == RISCV::LUI) { + BuildMI(MBB, MBBI, DL, get(RISCV::LUI), Result).addImm(Inst.Imm).setMIFlag(Flag); + } + else { + BuildMI(MBB, MBBI, DL, get(Inst.Opc), Result).addReg(SrcReg, RegState::Kill).addImm(Inst.Imm).setMIFlag(Flag); + } + SrcReg = Result; + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/parseCondBranch.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/parseCondBranch.cpp new file mode 100644 index 0000000000000000000000000000000000000000..aef3d0ecdf646f8417201ea3baa82992390cf15b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/parseCondBranch.cpp @@ -0,0 +1,7 @@ +static void parseCondBranch(MachineInstr &LastInst, MachineBasicBlock *&Target, SmallVectorImpl &Cond) { + assert(LastInst.getDesc().isConditionalBranch() && "Unknown conditional branch"); + Target = LastInst.getOperand(2).getMBB(); + Cond.push_back(MachineOperand::CreateImm(LastInst.getOpcode())); + Cond.push_back(LastInst.getOperand(0)); + Cond.push_back(LastInst.getOperand(1)); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/removeBranch.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/removeBranch.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fd30e85a8f2e12786e68b6e78bdf15a32405af38 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/removeBranch.cpp @@ -0,0 +1,29 @@ +unsigned RISCVInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved) const { + if (BytesRemoved) { + *BytesRemoved = 0; + } + MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr(); + if (I == MBB.end()) { + return 0; + } + if (!I->getDesc().isUnconditionalBranch() && !I->getDesc().isConditionalBranch()) { + return 0; + } + if (BytesRemoved) { + *BytesRemoved += getInstSizeInBytes(*I); + } + I->eraseFromParent(); + I = MBB.end(); + if (I == MBB.begin()) { + return 1; + } + --I; + if (!I->getDesc().isConditionalBranch()) { + return 1; + } + if (BytesRemoved) { + *BytesRemoved += getInstSizeInBytes(*I); + } + I->eraseFromParent(); + return 2; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/reverseBranchCondition.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/reverseBranchCondition.cpp new file mode 100644 index 0000000000000000000000000000000000000000..518236fcb35df0b50482ad41a57f1da3bb8b7bfe --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/reverseBranchCondition.cpp @@ -0,0 +1,5 @@ +bool RISCVInstrInfo::reverseBranchCondition(SmallVectorImpl &Cond) const { + assert((Cond.size() == 3) && "Invalid branch condition!"); + Cond[0].setImm(getOppositeBranchOpcode(Cond[0].getImm())); + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/storeRegToStackSlot.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/storeRegToStackSlot.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e0ae4eae7913dca4a4503f04564cf151eb5e25b7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/storeRegToStackSlot.cpp @@ -0,0 +1,26 @@ +void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register SrcReg, bool IsKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const { + DebugLoc DL; + if (I != MBB.end()) { + DL = I->getDebugLoc(); + } + MachineFunction *MF = MBB.getParent(); + const MachineFrameInfo &MFI = MF->getFrameInfo(); + MachineMemOperand *MMO = MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOStore, MFI.getObjectSize(FI), MFI.getObjectAlign(FI)); + unsigned Opcode; + if (RISCV::GPRRegClass.hasSubClassEq(RC)) { + Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ? RISCV::SW : RISCV::SD; + } + else if (RISCV::FPR16RegClass.hasSubClassEq(RC)) { + Opcode = RISCV::FSH; + } + else if (RISCV::FPR32RegClass.hasSubClassEq(RC)) { + Opcode = RISCV::FSW; + } + else if (RISCV::FPR64RegClass.hasSubClassEq(RC)) { + Opcode = RISCV::FSD; + } + else { + llvm_unreachable("Can't store this register to stack slot"); + } + BuildMI(MBB, I, DL, get(Opcode)).addReg(SrcReg, getKillRegState(IsKill)).addFrameIndex(FI).addImm(0).addMemOperand(MMO); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/verifyInstruction.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/verifyInstruction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fc6132c159d95d82c73a20c8cfadc860f781c4dd --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/InstrInfo/verifyInstruction.cpp @@ -0,0 +1,50 @@ +bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const { + const MCInstrInfo *MCII = STI.getInstrInfo(); + MCInstrDesc const &Desc = MCII->get(MI.getOpcode()); + for (auto &OI : enumerate(Desc.operands())) { + unsigned OpType = OI.value().OperandType; + if (OpType >= RISCVOp::OPERAND_FIRST_RISCV_IMM && OpType <= RISCVOp::OPERAND_LAST_RISCV_IMM) { + const MachineOperand &MO = MI.getOperand(OI.index()); + if (MO.isImm()) { + int64_t Imm = MO.getImm(); + bool Ok; + switch (OpType) { + default: + llvm_unreachable("Unexpected operand type"); + case RISCVOp::OPERAND_UIMM4: + Ok = isUInt<4>(Imm); + break; + case RISCVOp::OPERAND_UIMM5: + Ok = isUInt<5>(Imm); + break; + case RISCVOp::OPERAND_UIMM12: + Ok = isUInt<12>(Imm); + break; + case RISCVOp::OPERAND_UIMM12M1: + Ok = isUInt<12>(Imm) && (Imm != 0); + break; + case RISCVOp::OPERAND_UIMM3: + Ok = isUInt<3>(Imm); + break; + case RISCVOp::OPERAND_SIMM12: + Ok = isInt<12>(Imm); + break; + case RISCVOp::OPERAND_UIMM20: + Ok = isUInt<20>(Imm); + break; + case RISCVOp::OPERAND_UIMMLOG2XLEN: + if (STI.getTargetTriple().isArch64Bit()) + Ok = isUInt<6>(Imm); + else + Ok = isUInt<5>(Imm); + break; + } + if (!Ok) { + ErrInfo = "Invalid immediate"; + return false; + } + } + } + } + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/MachineFunctionInfo/MachineFunctionInfo.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/MachineFunctionInfo/MachineFunctionInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a73ce4b15067ea6dd345e8f804506eb820ce687b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/MachineFunctionInfo/MachineFunctionInfo.cpp @@ -0,0 +1,2 @@ +RISCVMachineFunctionInfo(const MachineFunction &MF) { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/MachineFunctionInfo/getLibCallStackSize.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/MachineFunctionInfo/getLibCallStackSize.cpp new file mode 100644 index 0000000000000000000000000000000000000000..79005827d02719d27077d7e3bbe5d9c839a908e2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/MachineFunctionInfo/getLibCallStackSize.cpp @@ -0,0 +1,3 @@ +unsigned getLibCallStackSize() const { + return LibCallStackSize; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/MachineFunctionInfo/getMoveF64FrameIndex.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/MachineFunctionInfo/getMoveF64FrameIndex.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7c988c0796a82546234e3f8e39a1182b7d1ea2b8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/MachineFunctionInfo/getMoveF64FrameIndex.cpp @@ -0,0 +1,6 @@ +int getMoveF64FrameIndex(MachineFunction &MF) { + if (MoveF64FrameIndex == -1) { + MoveF64FrameIndex = MF.getFrameInfo().CreateStackObject(8, Align(8), false); + } + return MoveF64FrameIndex; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/MachineFunctionInfo/getUsedSSR.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/MachineFunctionInfo/getUsedSSR.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7d4a2413ae12ddd5eefda1c613fff7ac463f7e05 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/MachineFunctionInfo/getUsedSSR.cpp @@ -0,0 +1,3 @@ +unsigned getUsedSSR() const { + return UsedSSR; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/MachineFunctionInfo/getVarArgsFrameIndex.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/MachineFunctionInfo/getVarArgsFrameIndex.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2ad7e3a6df3da4abe5143ddf276a5a8dd208c0d1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/MachineFunctionInfo/getVarArgsFrameIndex.cpp @@ -0,0 +1,3 @@ +int getVarArgsFrameIndex() const { + return VarArgsFrameIndex; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/MachineFunctionInfo/getVarArgsSaveSize.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/MachineFunctionInfo/getVarArgsSaveSize.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ff3900efa130d85bd23cdf0bf46f4492a11b3207 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/MachineFunctionInfo/getVarArgsSaveSize.cpp @@ -0,0 +1,3 @@ +unsigned getVarArgsSaveSize() const { + return VarArgsSaveSize; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/MachineFunctionInfo/setLibCallStackSize.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/MachineFunctionInfo/setLibCallStackSize.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e2c605685906e3f74e9d19eb3a425bb677ecf6e8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/MachineFunctionInfo/setLibCallStackSize.cpp @@ -0,0 +1,3 @@ +void setLibCallStackSize(unsigned Size) { + LibCallStackSize = Size; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/MachineFunctionInfo/setUsedSSR.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/MachineFunctionInfo/setUsedSSR.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ec08754db512c25241208b4d04f526ba159ef7a2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/MachineFunctionInfo/setUsedSSR.cpp @@ -0,0 +1,3 @@ +void setUsedSSR(unsigned SSR) { + UsedSSR = SSR; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/MachineFunctionInfo/setVarArgsFrameIndex.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/MachineFunctionInfo/setVarArgsFrameIndex.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f57e9f48831fa353d584c49669f0413fc095c594 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/MachineFunctionInfo/setVarArgsFrameIndex.cpp @@ -0,0 +1,3 @@ +void setVarArgsFrameIndex(int Index) { + VarArgsFrameIndex = Index; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/MachineFunctionInfo/setVarArgsSaveSize.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/MachineFunctionInfo/setVarArgsSaveSize.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3a72ac1c44b6abb48837cf13d74446638ee97792 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/MachineFunctionInfo/setVarArgsSaveSize.cpp @@ -0,0 +1,3 @@ +void setVarArgsSaveSize(int Size) { + VarArgsSaveSize = Size; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/MachineFunctionInfo/useSaveRestoreLibCalls.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/MachineFunctionInfo/useSaveRestoreLibCalls.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bcd8f637f04add2d1722e6da9011c498bb8571c8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/MachineFunctionInfo/useSaveRestoreLibCalls.cpp @@ -0,0 +1,3 @@ +bool useSaveRestoreLibCalls(const MachineFunction &MF) const { + return MF.getSubtarget().enableSaveRestore() && VarArgsSaveSize == 0 && !MF.getFrameInfo().hasTailCall(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/Subtarget.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/Subtarget.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b485bfc3f8c679a1968fbd947cfb7a1a630ceb15 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/Subtarget.cpp @@ -0,0 +1,7 @@ +RISCVSubtarget::RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, StringRef ABIName, const TargetMachine &TM) : RISCVGenSubtargetInfo(TT, CPU, TuneCPU, FS), UserReservedRegister(RISCV::NUM_TARGET_REGS), FrameLowering(initializeSubtargetDependencies(TT, CPU, TuneCPU, FS, ABIName)), InstrInfo(*this), RegInfo(getHwMode()), TLInfo(TM, *this) { + CallLoweringInfo.reset(new RISCVCallLowering(*getTargetLowering())); + Legalizer.reset(new RISCVLegalizerInfo(*this)); + auto *RBI = new RISCVRegisterBankInfo(*getRegisterInfo()); + RegBankInfo.reset(RBI); + InstSelector.reset(createRISCVInstructionSelector(*static_cast(&TM), *this, *RBI)); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/anchor.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/anchor.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3c6f04a53d1e860d1cb5cb48fc428103a470ef0f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/anchor.cpp @@ -0,0 +1,2 @@ +void RISCVSubtarget::anchor() { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/enableLinkerRelax.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/enableLinkerRelax.cpp new file mode 100644 index 0000000000000000000000000000000000000000..21de073065f1c45c637d96155064fa1e17a1de02 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/enableLinkerRelax.cpp @@ -0,0 +1,3 @@ +bool enableLinkerRelax() const { + return EnableLinkerRelax; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/enableMachineScheduler.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/enableMachineScheduler.cpp new file mode 100644 index 0000000000000000000000000000000000000000..358b44992259774bd76684c0ec9175e49433d00f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/enableMachineScheduler.cpp @@ -0,0 +1,3 @@ +bool enableMachineScheduler() const override { + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/enableRVCHintInstrs.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/enableRVCHintInstrs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a15b00dc080602258900bbbe99e7e945b36ba6cb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/enableRVCHintInstrs.cpp @@ -0,0 +1,3 @@ +bool enableRVCHintInstrs() const { + return EnableRVCHintInstrs; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/enableSaveRestore.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/enableSaveRestore.cpp new file mode 100644 index 0000000000000000000000000000000000000000..343f8da6be2a7efb133ed8ceb361f0e04baf970c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/enableSaveRestore.cpp @@ -0,0 +1,3 @@ +bool enableSaveRestore() const { + return EnableSaveRestore; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/getCallLowering.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/getCallLowering.cpp new file mode 100644 index 0000000000000000000000000000000000000000..38840e3abf5721f2f2bb806ec7b4c36e9c80c33b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/getCallLowering.cpp @@ -0,0 +1,3 @@ +const CallLowering *RISCVSubtarget::getCallLowering() const { + return CallLoweringInfo.get(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/getFrameLowering.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/getFrameLowering.cpp new file mode 100644 index 0000000000000000000000000000000000000000..dbbed9b4540b34f6fcda3e88827d89fc8b271b92 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/getFrameLowering.cpp @@ -0,0 +1,3 @@ +const RISCVFrameLowering *getFrameLowering() const override { + return &FrameLowering; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/getInstrInfo.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/getInstrInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..241a6f789b9336fb755e0f8bd27f6411d2016581 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/getInstrInfo.cpp @@ -0,0 +1,3 @@ +const RISCVInstrInfo *getInstrInfo() const override { + return &InstrInfo; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/getInstructionSelector.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/getInstructionSelector.cpp new file mode 100644 index 0000000000000000000000000000000000000000..48c25e17f0bcb2c488a43f59965f14252652be1b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/getInstructionSelector.cpp @@ -0,0 +1,3 @@ +InstructionSelector *RISCVSubtarget::getInstructionSelector() const { + return InstSelector.get(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/getLegalizerInfo.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/getLegalizerInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..34b918d70ad4c109ca034168fc2dc5f7762cba5c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/getLegalizerInfo.cpp @@ -0,0 +1,3 @@ +const LegalizerInfo *RISCVSubtarget::getLegalizerInfo() const { + return Legalizer.get(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/getRegBankInfo.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/getRegBankInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e51ba7750e72c82e020ae09634218d29c8b6e080 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/getRegBankInfo.cpp @@ -0,0 +1,3 @@ +const RegisterBankInfo *RISCVSubtarget::getRegBankInfo() const { + return RegBankInfo.get(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/getRegisterInfo.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/getRegisterInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0323310ac0e1eb0128dc614c5b8e5810c97fd662 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/getRegisterInfo.cpp @@ -0,0 +1,3 @@ +const RISCVRegisterInfo *getRegisterInfo() const override { + return &RegInfo; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/getSelectionDAGInfo.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/getSelectionDAGInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a587bb87c2bf9c4c35e25ccfee788761dc1d8a6a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/getSelectionDAGInfo.cpp @@ -0,0 +1,3 @@ +const SelectionDAGTargetInfo *getSelectionDAGInfo() const override { + return &TSInfo; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/getTargetABI.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/getTargetABI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6ba240b805d561f415ec4ee11045c3d6eb8dea8e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/getTargetABI.cpp @@ -0,0 +1,3 @@ +RISCVABI::ABI getTargetABI() const { + return TargetABI; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/getTargetLowering.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/getTargetLowering.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ae252b5d67893ec68615f1dfafc89e95b3676d6d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/getTargetLowering.cpp @@ -0,0 +1,3 @@ +const RISCVTargetLowering *getTargetLowering() const override { + return &TLInfo; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/getXLen.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/getXLen.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1b93e9c9f4885d72046bc33a4c96130e4796e755 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/getXLen.cpp @@ -0,0 +1,3 @@ +unsigned getXLen() const { + return XLen; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/getXLenVT.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/getXLenVT.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f65801b1cfce99bb6f22e7828e3f2be8e8095ddb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/getXLenVT.cpp @@ -0,0 +1,3 @@ +MVT getXLenVT() const { + return XLenVT; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXdma.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXdma.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b50f94b35a91179fab9b2749cb3c2e48d81fe9cd --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXdma.cpp @@ -0,0 +1,3 @@ +bool hasExtXdma() const { + return HasExtXdma; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfalthalf.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfalthalf.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ee1eddd67878923b6fb263318bf24c7cf99ecbd2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfalthalf.cpp @@ -0,0 +1,3 @@ +bool hasExtXfalthalf() const { + return HasExtXfalthalf; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfaltquarter.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfaltquarter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8dc56654edc8975e44f482c559393c168e83e253 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfaltquarter.cpp @@ -0,0 +1,3 @@ +bool hasExtXfaltquarter() const { + return HasExtXfaltquarter; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfauxalthalf.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfauxalthalf.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4d4eb0ed77ad86d07fbb4dde3494b44d457f59bb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfauxalthalf.cpp @@ -0,0 +1,3 @@ +bool hasExtXfauxalthalf() const { + return HasExtXfauxalthalf; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfauxaltquarter.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfauxaltquarter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..84cb32004fc45ee254d87b70a5c0c96d6889a383 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfauxaltquarter.cpp @@ -0,0 +1,3 @@ +bool hasExtXfauxaltquarter() const { + return HasExtXfauxaltquarter; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfauxhalf.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfauxhalf.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7de782eb97c32ba76294775e9c8dfb965f335b05 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfauxhalf.cpp @@ -0,0 +1,3 @@ +bool hasExtXfauxhalf() const { + return HasExtXfauxhalf; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfauxquarter.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfauxquarter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cbf79cd504372208eaa7893ea73b840e5aeaef00 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfauxquarter.cpp @@ -0,0 +1,3 @@ +bool hasExtXfauxquarter() const { + return HasExtXfauxquarter; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfauxvecalthalf.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfauxvecalthalf.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4a8c9f9b8429c53e2c6192380fe15a45f7d7f0ea --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfauxvecalthalf.cpp @@ -0,0 +1,3 @@ +bool hasExtXfauxvecalthalf() const { + return HasExtXfauxvecalthalf; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfauxvecaltquarter.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfauxvecaltquarter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4bd816d9550c011decc2f605cd09552cbbf184d8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfauxvecaltquarter.cpp @@ -0,0 +1,3 @@ +bool hasExtXfauxvecaltquarter() const { + return HasExtXfauxvecaltquarter; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfauxvechalf.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfauxvechalf.cpp new file mode 100644 index 0000000000000000000000000000000000000000..767cc573a601174be1ef656d304e268fd3a540db --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfauxvechalf.cpp @@ -0,0 +1,3 @@ +bool hasExtXfauxvechalf() const { + return HasExtXfauxvechalf; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfauxvecquarter.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfauxvecquarter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..682f5318c843b5ad741a8f55c29823253334ce87 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfauxvecquarter.cpp @@ -0,0 +1,3 @@ +bool hasExtXfauxvecquarter() const { + return HasExtXfauxvecquarter; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfauxvecsingle.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfauxvecsingle.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e5cb7e31401326abe2ddc65cf0d8217f17a32f73 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfauxvecsingle.cpp @@ -0,0 +1,3 @@ +bool hasExtXfauxvecsingle() const { + return HasExtXfauxvecsingle; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfexpauxvecalthalf.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfexpauxvecalthalf.cpp new file mode 100644 index 0000000000000000000000000000000000000000..106e373991d2c699b961aeef1577920dbaf67f34 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfexpauxvecalthalf.cpp @@ -0,0 +1,3 @@ +bool hasExtXfexpauxvecalthalf() const { + return HasExtXfexpauxvecalthalf; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfexpauxvecaltquarter.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfexpauxvecaltquarter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e924eb943825132563e1cdca12cda38b5535b2cf --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfexpauxvecaltquarter.cpp @@ -0,0 +1,3 @@ +bool hasExtXfexpauxvecaltquarter() const { + return HasExtXfexpauxvecaltquarter; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfexpauxvechalf.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfexpauxvechalf.cpp new file mode 100644 index 0000000000000000000000000000000000000000..756da6a60ab06a2cd71312262f8e97570ba99f34 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfexpauxvechalf.cpp @@ -0,0 +1,3 @@ +bool hasExtXfexpauxvechalf() const { + return HasExtXfexpauxvechalf; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfexpauxvecquarter.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfexpauxvecquarter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b89eedceac7860150c3b5b40e32c99e2658e71c8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfexpauxvecquarter.cpp @@ -0,0 +1,3 @@ +bool hasExtXfexpauxvecquarter() const { + return HasExtXfexpauxvecquarter; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfquarter.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfquarter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e31dc636c535c73eb1503dcb231be32480e3dd2f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfquarter.cpp @@ -0,0 +1,3 @@ +bool hasExtXfquarter() const { + return HasExtXfquarter; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfrep.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfrep.cpp new file mode 100644 index 0000000000000000000000000000000000000000..35b7a06baa3a4ecfed8efa050620607a395b53b4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfrep.cpp @@ -0,0 +1,3 @@ +bool hasExtXfrep() const { + return HasExtXfrep; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfvecalthalf.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfvecalthalf.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4b76712a5fe5cb9a8609ee5ee0303f9d21f466f7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfvecalthalf.cpp @@ -0,0 +1,3 @@ +bool hasExtXfvecalthalf() const { + return HasExtXfvecalthalf; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfvecaltquarter.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfvecaltquarter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5f10d6dc6589cb2b3c64bcb6f0f744cb9dc2b517 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfvecaltquarter.cpp @@ -0,0 +1,3 @@ +bool hasExtXfvecaltquarter() const { + return HasExtXfvecaltquarter; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfvechalf.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfvechalf.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9d8e3439f302acf088ad90e43549b0543078a0dd --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfvechalf.cpp @@ -0,0 +1,3 @@ +bool hasExtXfvechalf() const { + return HasExtXfvechalf; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfvecquarter.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfvecquarter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..092a6ec38142f84b44c054baa818a8dde6efd74c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfvecquarter.cpp @@ -0,0 +1,3 @@ +bool hasExtXfvecquarter() const { + return HasExtXfvecquarter; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfvecsingle.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfvecsingle.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e49dd14107613df91d4f29c9decc9e521f4c3a31 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXfvecsingle.cpp @@ -0,0 +1,3 @@ +bool hasExtXfvecsingle() const { + return HasExtXfvecsingle; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXmempool.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXmempool.cpp new file mode 100644 index 0000000000000000000000000000000000000000..525e28fb0669138eeb093bc6b2ef2f975b5082c0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXmempool.cpp @@ -0,0 +1,3 @@ +bool hasExtXmempool() const { + return HasExtXmempool; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXsmallfloat.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXsmallfloat.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d72952920107186a40f23563d24f54d2449871e5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXsmallfloat.cpp @@ -0,0 +1,3 @@ +bool hasExtXsmallfloat() const { + return HasExtXfalthalf || HasExtXfquarter || HasExtXfaltquarter || HasExtXfvecsingle || HasExtXfvechalf || HasExtXfvecalthalf || HasExtXfvecquarter || HasExtXfvecaltquarter || HasExtXfauxhalf || HasExtXfauxalthalf || HasExtXfauxquarter || HasExtXfauxaltquarter || HasExtXfauxvecsingle || HasExtXfauxvechalf || HasExtXfauxvecalthalf || HasExtXfauxvecquarter || HasExtXfauxvecaltquarter || HasExtXfexpauxvechalf || HasExtXfexpauxvecalthalf || HasExtXfexpauxvecquarter || HasExtXfexpauxvecaltquarter; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXssr.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXssr.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7497bc2f4ceabd51075636f406d1cdd3480039fc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasExtXssr.cpp @@ -0,0 +1,3 @@ +bool hasExtXssr() const { + return HasExtXssr; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasPULPExtV2.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasPULPExtV2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3441b5174bd4cb1da169b79f355d3be99fc67ba8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasPULPExtV2.cpp @@ -0,0 +1,3 @@ +bool hasPULPExtV2() const { + return HasPULPExtV2; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtA.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtA.cpp new file mode 100644 index 0000000000000000000000000000000000000000..045084578632528b294c467beabb11bcec85b93e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtA.cpp @@ -0,0 +1,3 @@ +bool hasStdExtA() const { + return HasStdExtA; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtB.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtB.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c102f9d01106d3f90c03b80ad507bf41a61fbdbe --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtB.cpp @@ -0,0 +1,3 @@ +bool hasStdExtB() const { + return HasStdExtB; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtC.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..785c95523c80c75eaae143f94294a1b159b11b27 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtC.cpp @@ -0,0 +1,3 @@ +bool hasStdExtC() const { + return HasStdExtC; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtD.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtD.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c0d41f4cdb4f7a92d8a9ce0c402a53b8cc7697a7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtD.cpp @@ -0,0 +1,3 @@ +bool hasStdExtD() const { + return HasStdExtD; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtF.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtF.cpp new file mode 100644 index 0000000000000000000000000000000000000000..dfe330377a0077baad1cc0ee8b900335fc99c7a5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtF.cpp @@ -0,0 +1,3 @@ +bool hasStdExtF() const { + return HasStdExtF; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtM.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtM.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f5e79be711a1b0176abd5623e66e222d8106828b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtM.cpp @@ -0,0 +1,3 @@ +bool hasStdExtM() const { + return HasStdExtM; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtV.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtV.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5223acaac264f68a6fc3f33c7b15e6d79e1dffd7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtV.cpp @@ -0,0 +1,3 @@ +bool hasStdExtV() const { + return HasStdExtV; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtZba.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtZba.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fa2fdb498d75c1d5e09f33e14da97cb8b6c439cf --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtZba.cpp @@ -0,0 +1,3 @@ +bool hasStdExtZba() const { + return HasStdExtZba; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtZbb.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtZbb.cpp new file mode 100644 index 0000000000000000000000000000000000000000..580a2ecde2d98f6211573d9c0182a66888e30a4f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtZbb.cpp @@ -0,0 +1,3 @@ +bool hasStdExtZbb() const { + return HasStdExtZbb; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtZbc.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtZbc.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3665774de6ea27b4f43cc2ce9725e3ef8ee03f24 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtZbc.cpp @@ -0,0 +1,3 @@ +bool hasStdExtZbc() const { + return HasStdExtZbc; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtZbe.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtZbe.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b885070bf501e4aa033b5c64c27d6cde94fd574f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtZbe.cpp @@ -0,0 +1,3 @@ +bool hasStdExtZbe() const { + return HasStdExtZbe; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtZbf.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtZbf.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9d30a77301e6f77bcf71149553258fdf6ba72802 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtZbf.cpp @@ -0,0 +1,3 @@ +bool hasStdExtZbf() const { + return HasStdExtZbf; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtZbm.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtZbm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..64e8f6da0a82c37c1c84768cfbd9c41e4f9d4c27 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtZbm.cpp @@ -0,0 +1,3 @@ +bool hasStdExtZbm() const { + return HasStdExtZbm; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtZbp.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtZbp.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e70ce03f491bf72fc64954ff90e195393b67e99c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtZbp.cpp @@ -0,0 +1,3 @@ +bool hasStdExtZbp() const { + return HasStdExtZbp; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtZbproposedc.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtZbproposedc.cpp new file mode 100644 index 0000000000000000000000000000000000000000..05ca4bea84b6696d19aafd851732afc5363c7ee5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtZbproposedc.cpp @@ -0,0 +1,3 @@ +bool hasStdExtZbproposedc() const { + return HasStdExtZbproposedc; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtZbr.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtZbr.cpp new file mode 100644 index 0000000000000000000000000000000000000000..88f9e522cd20fd732d826a9b8eaeb7f76be8551f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtZbr.cpp @@ -0,0 +1,3 @@ +bool hasStdExtZbr() const { + return HasStdExtZbr; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtZbs.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtZbs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..77d6819e118c6e1f82cdedf26c55783737418fb3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtZbs.cpp @@ -0,0 +1,3 @@ +bool hasStdExtZbs() const { + return HasStdExtZbs; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtZbt.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtZbt.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8432f49748cc5b1627de7d8aa7e42ab26c5463bd --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtZbt.cpp @@ -0,0 +1,3 @@ +bool hasStdExtZbt() const { + return HasStdExtZbt; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtZfh.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtZfh.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6b8f1a64d51d18301744d11c4f5879d8ae084a21 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtZfh.cpp @@ -0,0 +1,3 @@ +bool hasStdExtZfh() const { + return HasStdExtZfh; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtZvamo.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtZvamo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4f140c6331d83ac7a5f8d0308537923cdac4b480 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtZvamo.cpp @@ -0,0 +1,3 @@ +bool hasStdExtZvamo() const { + return HasStdExtZvamo; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtZvlsseg.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtZvlsseg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d9c8265a1f76104be737068c99616f36543fa720 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/hasStdExtZvlsseg.cpp @@ -0,0 +1,3 @@ +bool hasStdExtZvlsseg() const { + return HasStdExtZvlsseg; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/initializeSubtargetDependencies.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/initializeSubtargetDependencies.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e252c6d74395b08bc3f85a8df3c085538e2240d9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/initializeSubtargetDependencies.cpp @@ -0,0 +1,22 @@ +RISCVSubtarget &RISCVSubtarget::initializeSubtargetDependencies(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, StringRef ABIName) { + bool Is64Bit = TT.isArch64Bit(); + std::string CPUName = std::string(CPU); + std::string TuneCPUName = std::string(TuneCPU); + if (CPUName.empty()) { + CPUName = Is64Bit ? "generic-rv64" : "generic-rv32"; + } + if (TuneCPUName.empty()) { + TuneCPUName = CPUName; + } + ParseSubtargetFeatures(CPUName, TuneCPUName, FS); + if (Is64Bit) { + XLenVT = MVT::i64; + XLen = 64; + } + TargetABI = RISCVABI::computeTargetABI(TT, getFeatureBits(), ABIName); + RISCVFeatures::validate(TT, getFeatureBits()); + if(TT.getVendor() == Triple::HERO) { + IsPULP = true; + } + return *this; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/is64Bit.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/is64Bit.cpp new file mode 100644 index 0000000000000000000000000000000000000000..026df9778ca9ddace0d34a9f3e0d8eb157bd293e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/is64Bit.cpp @@ -0,0 +1,3 @@ +bool is64Bit() const { + return HasRV64; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/isPULP.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/isPULP.cpp new file mode 100644 index 0000000000000000000000000000000000000000..061b8cdfcc03ad94ac5a2e30d0daca7b06335f8f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/isPULP.cpp @@ -0,0 +1,3 @@ +bool isPULP() const { + return IsPULP; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/isRV32E.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/isRV32E.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e9fc1cb3169afb18c1184d05bcd22cb858a5676e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/isRV32E.cpp @@ -0,0 +1,3 @@ +bool isRV32E() const { + return IsRV32E; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/isRegisterReservedByUser.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/isRegisterReservedByUser.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8ac2e733fe0b3623076323b1347a74e43a721deb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/Subtarget/isRegisterReservedByUser.cpp @@ -0,0 +1,4 @@ +bool isRegisterReservedByUser(Register R) const { + assert(R < RISCV::NUM_TARGET_REGS && "Register out of range"); + return UserReservedRegister[R]; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetInfo/LLVMInitializeTargetInfo.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetInfo/LLVMInitializeTargetInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..37b315659994b32de45ce8870d6a29db4acfbd3a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetInfo/LLVMInitializeTargetInfo.cpp @@ -0,0 +1,4 @@ +extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTargetInfo() { + RegisterTarget X(getTheRISCV32Target(), "riscv32", "32-bit RISC-V", "RISCV"); + RegisterTarget Y(getTheRISCV64Target(), "riscv64", "64-bit RISC-V", "RISCV"); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetInfo/getThe32Target.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetInfo/getThe32Target.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6d0317f9493f86d48647af0d9d65986f46cbf77b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetInfo/getThe32Target.cpp @@ -0,0 +1,4 @@ +Target &llvm::getTheRISCV32Target() { + static Target TheRISCV32Target; + return TheRISCV32Target; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetInfo/getThe64Target.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetInfo/getThe64Target.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f7a649e2d1dcc685575c2f9ec1dca9aaf6fa8aba --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetInfo/getThe64Target.cpp @@ -0,0 +1,4 @@ +Target &llvm::getTheRISCV64Target() { + static Target TheRISCV64Target; + return TheRISCV64Target; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/LLVMInitializeTarget.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/LLVMInitializeTarget.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3ec72f6f7f4ebd30c69080a6510c2df6c33274bc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/LLVMInitializeTarget.cpp @@ -0,0 +1,11 @@ +extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() { + RegisterTargetMachine X(getTheRISCV32Target()); + RegisterTargetMachine Y(getTheRISCV64Target()); + auto *PR = PassRegistry::getPassRegistry(); + initializeGlobalISel(*PR); + initializeRISCVMergeBaseOffsetOptPass(*PR); + initializeRISCVExpandSSRPass(*PR); + initializeSNITCHFrepLoopsPass(*PR); + initializeRISCVExpandPseudoPass(*PR); + initializezmtarzmCleanupVSETVLIFPass(*PR); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/PassConfig.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/PassConfig.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b20b53464b621e4e92357ebd6307c69ffb9a40e4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/PassConfig.cpp @@ -0,0 +1,2 @@ +RISCVPassConfig(RISCVTargetMachine &TM, PassManagerBase &PM) : TargetPassConfig(TM, PM) { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/TargetMachine.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/TargetMachine.cpp new file mode 100644 index 0000000000000000000000000000000000000000..73ec6bedf09619270970355907e32b855791f128 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/TargetMachine.cpp @@ -0,0 +1,4 @@ +RISCVTargetMachine::RISCVTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional RM, CodeModel::Model CM, CodeGenOpt::Level OL) : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, getEffectiveRelocModel(RM), CM, OL), TLOF(make_unique()), Subtarget(TT, CPU, FS, *this) { + initAsmInfo(); + setMachineOutliner(true); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/addGlobalInstructionSelect.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/addGlobalInstructionSelect.cpp new file mode 100644 index 0000000000000000000000000000000000000000..53a717c5a28993e11ab524b64f8f9b5dde960abc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/addGlobalInstructionSelect.cpp @@ -0,0 +1,4 @@ +bool RISCVPassConfig::addGlobalInstructionSelect() { + addPass(new InstructionSelect()); + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/addIRPasses.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/addIRPasses.cpp new file mode 100644 index 0000000000000000000000000000000000000000..249cfd6b8fbbd2f318e66c2e9edcc522e72786ce --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/addIRPasses.cpp @@ -0,0 +1,4 @@ +void RISCVPassConfig::addIRPasses() { + addPass(createAtomicExpandPass()); + TargetPassConfig::addIRPasses(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/addIRTranslator.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/addIRTranslator.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e40ddbd47024c1bb26c2d10c54d2d2fb0c3c73f0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/addIRTranslator.cpp @@ -0,0 +1,4 @@ +bool RISCVPassConfig::addIRTranslator() { + addPass(new IRTranslator(getOptLevel())); + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/addInstSelector.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/addInstSelector.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bceda22a3721c766e191bd621bc2068efb9440e4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/addInstSelector.cpp @@ -0,0 +1,4 @@ +bool RISCVPassConfig::addInstSelector() { + addPass(createRISCVISelDag(getRISCVTargetMachine())); + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/addLegalizeMachineIR.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/addLegalizeMachineIR.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1932ec43e2cbb1e9ec97351c4421aa1d7c006317 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/addLegalizeMachineIR.cpp @@ -0,0 +1,4 @@ +bool RISCVPassConfig::addLegalizeMachineIR() { + addPass(new Legalizer()); + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/addPreEmitPass.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/addPreEmitPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c2ff69c52170cecce0743c34b95be10f32f76ce5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/addPreEmitPass.cpp @@ -0,0 +1,3 @@ +void RISCVPassConfig::addPreEmitPass() { + addPass(&BranchRelaxationPassID); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/addPreEmitPass2.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/addPreEmitPass2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e4d05114718df13693636112b72074e03fc4e83f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/addPreEmitPass2.cpp @@ -0,0 +1,5 @@ +void RISCVPassConfig::addPreEmitPass() { + addPass(createRISCVExpandPseudoPass()); + addPass(createRISCVExpandAtomicPseudoPass()); + addPass(createPULPFixupHwLoops()); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/addPreRegAlloc.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/addPreRegAlloc.cpp new file mode 100644 index 0000000000000000000000000000000000000000..31da21546bc22765cf99974c3efd80d633243390 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/addPreRegAlloc.cpp @@ -0,0 +1,10 @@ +void RISCVPassConfig::addPreRegAlloc() { + addPass(createRISCVExpandSDMAPass()); + addPass(createRISCVExpandSSRPass()); + addPass(createSNITCHFrepLoopsPass()); + if (TM->getOptLevel() != CodeGenOpt::None) { + addPass(createRISCVMergeBaseOffsetOptPass()); + addPass(createRISCVCleanupVSETVLIPass()); + addPass(createPULPHardwareLoops()); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/addPreSched2.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/addPreSched2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4ca661dadbfb7d390a899a4418bf15b9e1daeb40 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/addPreSched2.cpp @@ -0,0 +1,2 @@ +void RISCVPassConfig::addPreSched2() { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/addRegBankSelect.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/addRegBankSelect.cpp new file mode 100644 index 0000000000000000000000000000000000000000..784ce6e69101604753ad0faae4ce064c8ac54a6b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/addRegBankSelect.cpp @@ -0,0 +1,4 @@ +bool RISCVPassConfig::addRegBankSelect() { + addPass(new RegBankSelect()); + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/computeDataLayout.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/computeDataLayout.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cc998cd546aec1eb49f68f89e54417de94f8f74c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/computeDataLayout.cpp @@ -0,0 +1,10 @@ +static StringRef computeDataLayout(const Triple &TT) { + if (TT.isArch64Bit()) { + return "e-m:e-p:64:64-i64:64-i128:128-n64-S128"; + } + if (TT.getVendor() == Triple::HERO) { + return "e-m:e-p:32:32-p1:64:32-i64:64-n32-S128-P0-A0"; + } + assert(TT.isArch32Bit() && "only RV32 and RV64 are currently supported"); + return "e-m:e-p:32:32-i64:64-n32-S128"; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/createPassConfig.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/createPassConfig.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e26ed90631bc09a534221d3b0d89d3d0fb4a2f08 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/createPassConfig.cpp @@ -0,0 +1,3 @@ +TargetPassConfig *RISCVTargetMachine::createPassConfig(PassManagerBase &PM) { + return new RISCVPassConfig(*this, PM); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/getEffectiveRelocModel.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/getEffectiveRelocModel.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f8e47bfda9700302b8897ba128ce6aaa4acfbb8d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/getEffectiveRelocModel.cpp @@ -0,0 +1,6 @@ +static Reloc::Model getEffectiveRelocModel(const Triple &TT, Optional RM) { + if (!RM.hasValue()) { + return Reloc::Static; + } + return *RM; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/getObjFileLowering.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/getObjFileLowering.cpp new file mode 100644 index 0000000000000000000000000000000000000000..191f39130017a606dd77f12beee5e067e30a1edd --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/getObjFileLowering.cpp @@ -0,0 +1,3 @@ +TargetLoweringObjectFile *getObjFileLowering() const override { + return TLOF.get(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/getSubtargetImpl.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/getSubtargetImpl.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3910b1ff75ce36bb25563a278318b819a66dd309 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/getSubtargetImpl.cpp @@ -0,0 +1,25 @@ +const RISCVSubtarget *RISCVTargetMachine::getSubtargetImpl(const Function &F) const { + Attribute TuneAttr = F.getFnAttribute("tune-cpu"); + Attribute CPUAttr = F.getFnAttribute("target-cpu"); + Attribute FSAttr = F.getFnAttribute("target-features"); + std::string CPU = CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU; + std::string TuneCPU = TuneAttr.isValid() ? TuneAttr.getValueAsString().str() : CPU; + std::string FS = FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS; + std::string Key = CPU + TuneCPU + FS; + auto &I = SubtargetMap[Key]; + if (!I) { + resetTargetOptions(F); + auto ABIName = Options.MCOptions.getABIName(); + if (const MDString *ModuleTargetABI = dyn_cast_or_null(F.getParent()->getModuleFlag("target-abi"))) { + auto TargetABI = RISCVABI::getTargetABI(ABIName); + if (TargetABI != RISCVABI::ABI_Unknown) { + if (ModuleTargetABI->getString() != ABIName) { + report_fatal_error("-target-abi option != target-abi module flag"); + } + } + ABIName = ModuleTargetABI->getString(); + } + I = std::make_unique(TargetTriple, CPU, TuneCPU, FS, ABIName, *this); + } + return I.get(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/getTargetMachine.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/getTargetMachine.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5a41a250abddaaf2f72411583edeb8514ecc15fb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/getTargetMachine.cpp @@ -0,0 +1,3 @@ +RISCVTargetMachine &getRISCVTargetMachine() const { + return getTM(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/getTargetTransformInfo.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/getTargetTransformInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..de21c28d38b6b1f01d074c67513e6cefd58f284b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/getTargetTransformInfo.cpp @@ -0,0 +1,3 @@ +TargetTransformInfo RISCVTargetMachine::getTargetTransformInfo(const Function &F) { + return TargetTransformInfo(RISCVTTIImpl(this, F)); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/isNoopAddrSpaceCast.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/isNoopAddrSpaceCast.cpp new file mode 100644 index 0000000000000000000000000000000000000000..40909ed282d63a3b6673b49e76d705f5bac453f3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/isNoopAddrSpaceCast.cpp @@ -0,0 +1,3 @@ +bool RISCVTargetMachine::isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const { + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/setTargetOptionsWithModuleMetadata.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/setTargetOptionsWithModuleMetadata.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4ab8970cc0701e22e362bbdf6bcd1703a95b66d2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetMachine/setTargetOptionsWithModuleMetadata.cpp @@ -0,0 +1,12 @@ +void RISCVTargetMachine::setTargetOptionsWithModuleMetadata(const Module &M LLVM_ATTRIBUTE_UNUSED) { + StringRef ABIName = Options.MCOptions.getABIName(); + if (const MDString *ModuleTargetABI = dyn_cast_or_null(M.getModuleFlag("target-abi"))) { + StringRef ModuleABIName = ModuleTargetABI->getString(); + if (!ABIName.empty() && ModuleABIName != ABIName) { + report_fatal_error("-target-abi option != target-abi module flag"); + } + if (ABIName.empty()) { + Options.MCOptions.ABIName = ModuleABIName.str(); + } + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetObjectFile/Initialize.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetObjectFile/Initialize.cpp new file mode 100644 index 0000000000000000000000000000000000000000..98b08bcc1f079b2714504cf436a5a7c3530e1885 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetObjectFile/Initialize.cpp @@ -0,0 +1,5 @@ +void RISCVELFTargetObjectFile::Initialize(MCContext &Ctx, const TargetMachine &TM) { + TargetLoweringObjectFileELF::Initialize(Ctx, TM); + SmallDataSection = getContext().getELFSection(".sdata", ELF::SHT_PROGBITS, ELF::SHF_WRITE | ELF::SHF_ALLOC); + SmallBSSSection = getContext().getELFSection(".sbss", ELF::SHT_NOBITS, ELF::SHF_WRITE | ELF::SHF_ALLOC); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetObjectFile/SelectSectionForGlobal.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetObjectFile/SelectSectionForGlobal.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b6e5fb66e33a68d6f5d4aa6fbd6fa67a49ee342a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetObjectFile/SelectSectionForGlobal.cpp @@ -0,0 +1,9 @@ +MCSection *RISCVELFTargetObjectFile::SelectSectionForGlobal(const GlobalObject *GO, SectionKind Kind, const TargetMachine &TM) const { + if (Kind.isBSS() && isGlobalInSmallSection(GO, TM)) { + return SmallBSSSection; + } + if (Kind.isData() && isGlobalInSmallSection(GO, TM)) { + return SmallDataSection; + } + return TargetLoweringObjectFileELF::SelectSectionForGlobal(GO, Kind, TM); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetObjectFile/getModuleMetadata.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetObjectFile/getModuleMetadata.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fbe0c45c090047e1d764d2795db62ec1e15fe255 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetObjectFile/getModuleMetadata.cpp @@ -0,0 +1,11 @@ +void RISCVELFTargetObjectFile::getModuleMetadata(Module &M) { + SmallVector ModuleFlags; + M.getModuleFlagsMetadata(ModuleFlags); + for (const auto &MFE : ModuleFlags) { + StringRef Key = MFE.Key->getString(); + if (Key == "SmallDataLimit") { + SSThreshold = mdconst::extract(MFE.Val)->getZExtValue(); + break; + } + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetObjectFile/getSectionForConstant.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetObjectFile/getSectionForConstant.cpp new file mode 100644 index 0000000000000000000000000000000000000000..88aa5000ec9d5a0ffc49ae8b1b6bb97bb7707153 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetObjectFile/getSectionForConstant.cpp @@ -0,0 +1,6 @@ +MCSection *RISCVELFTargetObjectFile::getSectionForConstant( const DataLayout &DL, SectionKind Kind, const Constant *C, Align &Alignment) const { + if (isConstantInSmallSection(DL, C)) { + return SmallDataSection; + } + return TargetLoweringObjectFileELF::getSectionForConstant(DL, Kind, C, Alignment); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetObjectFile/isConstantInSmallSection.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetObjectFile/isConstantInSmallSection.cpp new file mode 100644 index 0000000000000000000000000000000000000000..03070c7967520e2db15231715cdf5404fe77cef0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetObjectFile/isConstantInSmallSection.cpp @@ -0,0 +1,3 @@ +bool RISCVELFTargetObjectFile::isConstantInSmallSection(const DataLayout &DL, const Constant *CN) const { + return isInSmallSection(DL.getTypeAllocSize(CN->getType())); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetObjectFile/isGlobalInSmallSection.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetObjectFile/isGlobalInSmallSection.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d15ea59c38f894725279f9fb82f0731c79548e5a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetObjectFile/isGlobalInSmallSection.cpp @@ -0,0 +1,21 @@ +bool RISCVELFTargetObjectFile::isGlobalInSmallSection(const GlobalObject *GO, const TargetMachine &TM) const { + const GlobalVariable *GVA = dyn_cast(GO); + if (!GVA) { + return false; + } + if (GVA->hasSection()) { + StringRef Section = GVA->getSection(); + if (Section == ".sdata" || Section == ".sbss") { + return true; + } + return false; + } + if (((GVA->hasExternalLinkage() && GVA->isDeclaration()) || GVA->hasCommonLinkage())) { + return false; + } + Type *Ty = GVA->getValueType(); + if (!Ty->isSized()) { + return false; + } + return isInSmallSection(GVA->getParent()->getDataLayout().getTypeAllocSize(Ty)); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetObjectFile/isInSmallSection.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetObjectFile/isInSmallSection.cpp new file mode 100644 index 0000000000000000000000000000000000000000..77772fb82ad184a8a4d2455cbc1cf202550c1af0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetObjectFile/isInSmallSection.cpp @@ -0,0 +1,3 @@ +bool RISCVELFTargetObjectFile::isInSmallSection(uint64_t Size) const { + return Size > 0 && Size <= SSThreshold; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetTransformInfo/TTIImpl.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetTransformInfo/TTIImpl.cpp new file mode 100644 index 0000000000000000000000000000000000000000..22191cb2dea9757287f93e29e9e0f5d88a5abc6c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetTransformInfo/TTIImpl.cpp @@ -0,0 +1,2 @@ +explicit RISCVTTIImpl(const RISCVTargetMachine *TM, const Function &F) : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)), TLI(ST->getTargetLowering()) { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetTransformInfo/getIntImmCost.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetTransformInfo/getIntImmCost.cpp new file mode 100644 index 0000000000000000000000000000000000000000..01d7fd4a5292e1d82961e69efa3f3bd08f29ff0a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetTransformInfo/getIntImmCost.cpp @@ -0,0 +1,8 @@ +int RISCVTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) { + assert(Ty->isIntegerTy() && "getIntImmCost can only estimate cost of materialising integers"); + if (Imm == 0) { + return TTI::TCC_Free; + } + const DataLayout &DL = getDataLayout(); + return RISCVMatInt::getIntMatCost(Imm, DL.getTypeSizeInBits(Ty), getST()->is64Bit()); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetTransformInfo/getIntImmCostInst.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetTransformInfo/getIntImmCostInst.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0c01363a8faf86a4c31e05ebe57cad34936b229 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetTransformInfo/getIntImmCostInst.cpp @@ -0,0 +1,37 @@ +int RISCVTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, Instruction *Inst) { + assert(Ty->isIntegerTy() && "getIntImmCost can only estimate cost of materialising integers"); + if (Imm == 0) { + return TTI::TCC_Free; + } + bool Takes12BitImm = false; + unsigned ImmArgIdx = ~0U; + switch (Opcode) { + case Instruction::GetElementPtr: + return TTI::TCC_Free; + case Instruction::Add: + case Instruction::And: + case Instruction::Or: + case Instruction::Xor: + case Instruction::Mul: + Takes12BitImm = true; + break; + case Instruction::Sub: + case Instruction::Shl: + case Instruction::LShr: + case Instruction::AShr: + Takes12BitImm = true; + ImmArgIdx = 1; + break; + default: + break; + } + if (Takes12BitImm) { + if (Instruction::isCommutative(Opcode) || Idx == ImmArgIdx) { + if (Imm.getMinSignedBits() <= 64 && getTLI()->isLegalAddImmediate(Imm.getSExtValue())) { + return TTI::TCC_Free; + } + } + return getIntImmCost(Imm, Ty, CostKind); + } + return TTI::TCC_Free; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetTransformInfo/getIntImmCostIntrin.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetTransformInfo/getIntImmCostIntrin.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ff244e23aa7c352fb557907d1c8528e63c9cf942 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetTransformInfo/getIntImmCostIntrin.cpp @@ -0,0 +1,3 @@ +int RISCVTTIImpl::getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) { + return TTI::TCC_Free; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetTransformInfo/getST.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetTransformInfo/getST.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3085911b846be9fe97364305924fd1e72c52af7f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetTransformInfo/getST.cpp @@ -0,0 +1,3 @@ +const RISCVSubtarget *getST() const { + return ST; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetTransformInfo/getTLI.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetTransformInfo/getTLI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4e8723265e898db24c643b890ede218d98cd5b62 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetTransformInfo/getTLI.cpp @@ -0,0 +1,3 @@ +const RISCVTargetLowering *getTLI() const { + return TLI; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetTransformInfo/isLoweredToCall.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetTransformInfo/isLoweredToCall.cpp new file mode 100644 index 0000000000000000000000000000000000000000..de686375cfeedff494d4847b2ff891158b91cf41 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetTransformInfo/isLoweredToCall.cpp @@ -0,0 +1,6 @@ +bool RISCVTTIImpl::isLoweredToCall(const Function *F) { + if (F->getName().startswith("llvm.riscv.pulp")) { + return false; + } + return BaseT::isLoweredToCall(F); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetTransformInfo/shouldFavorPostInc.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetTransformInfo/shouldFavorPostInc.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8c1571aa6e5baf2f38a158c32eacae1bd863b74c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Scheduling/TargetTransformInfo/shouldFavorPostInc.cpp @@ -0,0 +1,6 @@ +bool RISCVTTIImpl::shouldFavorPostInc() const { + if (ST->hasPULPExtV2()) { + return true; + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/CallLowering/CallLowering.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/CallLowering/CallLowering.cpp new file mode 100644 index 0000000000000000000000000000000000000000..44322d52c70e92f7e669a7c814a0825858d8a83d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/CallLowering/CallLowering.cpp @@ -0,0 +1,2 @@ +RISCVCallLowering::RISCVCallLowering(const RISCVTargetLowering &TLI) : CallLowering(&TLI) { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/CallLowering/lowerCall.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/CallLowering/lowerCall.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fc8637b1f0ea4b69b232a8c00e5c54df10bb470a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/CallLowering/lowerCall.cpp @@ -0,0 +1,3 @@ +bool RISCVCallLowering::lowerCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info) const { + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/CallLowering/lowerFormalArguments.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/CallLowering/lowerFormalArguments.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f8344a5c36b8b7f909b3f5bfff96e829687e6d80 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/CallLowering/lowerFormalArguments.cpp @@ -0,0 +1,6 @@ +bool RISCVCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef> VRegs, FunctionLoweringInfo &FLI) const { + if (F.arg_empty()) { + return true; + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/CallLowering/lowerReturn.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/CallLowering/lowerReturn.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9a0a34ed59d315e93fb2eb0040afebfc1ef94e7c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/CallLowering/lowerReturn.cpp @@ -0,0 +1,8 @@ +bool RISCVCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val, ArrayRef VRegs, FunctionLoweringInfo &FLI) const { + MachineInstrBuilder Ret = MIRBuilder.buildInstrNoInsert(RISCV::PseudoRET); + if (Val != nullptr) { + return false; + } + MIRBuilder.insertInstr(Ret); + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/FrameLowering/FrameLowering.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/FrameLowering/FrameLowering.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cc75bbabc713bf9ef22e7fb35f9ba8e802457383 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/FrameLowering/FrameLowering.cpp @@ -0,0 +1,2 @@ +explicit RISCVFrameLowering(const RISCVSubtarget &STI) : TargetFrameLowering(StackGrowsDown, Align(16), 0), STI(STI) { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/FrameLowering/adjustReg.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/FrameLowering/adjustReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c7dae994073558b0f037aa2e910c54258b035e8d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/FrameLowering/adjustReg.cpp @@ -0,0 +1,21 @@ +void RISCVFrameLowering::adjustReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register DestReg, Register SrcReg, int64_t Val, MachineInstr::MIFlag Flag) const { + MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); + const RISCVInstrInfo *TII = STI.getInstrInfo(); + if (DestReg == SrcReg && Val == 0) { + return ; + } + if (isInt<12>(Val)) { + BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), DestReg).addReg(SrcReg).addImm(Val).setMIFlag(Flag); + } + else { + unsigned Opc = RISCV::ADD; + bool isSub = Val < 0; + if (isSub) { + Val = -Val; + Opc = RISCV::SUB; + } + Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); + TII->movImm(MBB, MBBI, DL, ScratchReg, Val, Flag); + BuildMI(MBB, MBBI, DL, TII->get(Opc), DestReg).addReg(SrcReg).addReg(ScratchReg, RegState::Kill).setMIFlag(Flag); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/FrameLowering/canUseAsEpilogue.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/FrameLowering/canUseAsEpilogue.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bc50f8ce2fe6c77b83a82dd1c51e99b053cfcf64 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/FrameLowering/canUseAsEpilogue.cpp @@ -0,0 +1,16 @@ +bool RISCVFrameLowering::canUseAsEpilogue(const MachineBasicBlock &MBB) const { + const MachineFunction *MF = MBB.getParent(); + MachineBasicBlock *TmpMBB = const_cast(&MBB); + const auto *RVFI = MF->getInfo(); + if (!RVFI->useSaveRestoreLibCalls(*MF)) { + return true; + } + if (MBB.succ_size() > 1) { + return false; + } + MachineBasicBlock *SuccMBB = MBB.succ_empty() ? TmpMBB->getFallThrough() : *MBB.succ_begin(); + if (!SuccMBB) { + return true; + } + return SuccMBB->isReturnBlock() && SuccMBB->size() == 1; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/FrameLowering/canUseAsPrologue.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/FrameLowering/canUseAsPrologue.cpp new file mode 100644 index 0000000000000000000000000000000000000000..14ca7440ae53421c255bd958604dfcb5a32e346e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/FrameLowering/canUseAsPrologue.cpp @@ -0,0 +1,11 @@ +bool RISCVFrameLowering::canUseAsPrologue(const MachineBasicBlock &MBB) const { + MachineBasicBlock *TmpMBB = const_cast(&MBB); + const MachineFunction *MF = MBB.getParent(); + const auto *RVFI = MF->getInfo(); + if (!RVFI->useSaveRestoreLibCalls(*MF)) { + return true; + } + RegScavenger RS; + RS.enterBasicBlock(*TmpMBB); + return !RS.isRegUsed(RISCV::X5); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/FrameLowering/determineCalleeSaves.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/FrameLowering/determineCalleeSaves.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cc90cf82ab0d07d668daf8218552e032d84faba6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/FrameLowering/determineCalleeSaves.cpp @@ -0,0 +1,25 @@ +void RISCVFrameLowering::determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS) const { + TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS); + if (hasFP(MF)) { + SavedRegs.set(RISCV::X1); + SavedRegs.set(RISCV::X8); + } + if (hasBP(MF)) { + SavedRegs.set(RISCVABI::getBPReg()); + } + MachineFrameInfo &MFI = MF.getFrameInfo(); + if (MF.getFunction().hasFnAttribute("interrupt") && MFI.hasCalls()) { + static const MCPhysReg CSRegs[] = { RISCV::X1, RISCV::X5, RISCV::X6, RISCV::X7, RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31, 0}; + for (unsigned i = 0; CSRegs[i]; ++i) { + SavedRegs.set(CSRegs[i]); + } + if (MF.getSubtarget().hasStdExtF()) { + const MCPhysReg * Regs = MF.getRegInfo().getCalleeSavedRegs(); + for (unsigned i = 0; Regs[i]; ++i) { + if (RISCV::FPR16RegClass.contains(Regs[i]) || RISCV::FPR32RegClass.contains(Regs[i]) || RISCV::FPR64RegClass.contains(Regs[i])) { + SavedRegs.set(Regs[i]); + } + } + } + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/FrameLowering/eliminateCallFramePseudoInstr.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/FrameLowering/eliminateCallFramePseudoInstr.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1fa9f9d14dc9c6fc09c3c01a88db76d2312e69df --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/FrameLowering/eliminateCallFramePseudoInstr.cpp @@ -0,0 +1,15 @@ +MachineBasicBlock::iterator RISCVFrameLowering::eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const { + Register SPReg = RISCV::X2; + DebugLoc DL = MI->getDebugLoc(); + if (!hasReservedCallFrame(MF)) { + int64_t Amount = MI->getOperand(0).getImm(); + if (Amount != 0) { + Amount = alignSPAdjust(Amount); + if (MI->getOpcode() == RISCV::ADJCALLSTACKDOWN) { + Amount = -Amount; + } + adjustReg(MBB, MI, DL, SPReg, SPReg, Amount, MachineInstr::NoFlags); + } + } + return MBB.erase(MI); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/FrameLowering/emitEpilogue.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/FrameLowering/emitEpilogue.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4e2061f54290ae445a02f9c65b6d8720cb59e141 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/FrameLowering/emitEpilogue.cpp @@ -0,0 +1,88 @@ +void RISCVFrameLowering::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { + const RISCVRegisterInfo *RI = STI.getRegisterInfo(); + MachineFrameInfo &MFI = MF.getFrameInfo(); + auto *RVFI = MF.getInfo(); + Register FPReg = RISCV::X8; + Register SPReg = RISCV::X2; + if (MF.getFunction().getCallingConv() == CallingConv::GHC) { + return; + } + MachineBasicBlock::iterator MBBI = MBB.end(); + DebugLoc DL; + if (!MBB.empty()) { + MBBI = MBB.getFirstTerminator(); + if (MBBI == MBB.end()) { + MBBI = MBB.getLastNonDebugInstr(); + } + DL = MBBI->getDebugLoc(); + if (!MBBI->isTerminator()) { + MBBI = std::next(MBBI); + } + while (MBBI != MBB.begin() && std::prev(MBBI)->getFlag(MachineInstr::FrameDestroy)) { + --MBBI; + } + } + SmallVector NonLibcallCSI; + for (auto &CS : MFI.getCalleeSavedInfo()) { + if (CS.getFrameIdx() >= 0) { + NonLibcallCSI.push_back(CS); + } + } + const auto &CSI = NonLibcallCSI; + auto LastFrameDestroy = MBBI; + if (!CSI.empty()) { + LastFrameDestroy = std::prev(MBBI, CSI.size()); + } + uint64_t StackSize = MFI.getStackSize(); + uint64_t RealStackSize = StackSize + RVFI->getLibCallStackSize(); + uint64_t FPOffset = RealStackSize - RVFI->getVarArgsSaveSize(); + if (RI->needsStackRealignment(MF) || MFI.hasVarSizedObjects()) { + assert(hasFP(MF) && "frame pointer should not have been eliminated"); + adjustReg(MBB, LastFrameDestroy, DL, SPReg, FPReg, -FPOffset, MachineInstr::FrameDestroy); + } + uint64_t FirstSPAdjustAmount = 0; + const auto *RVFI = MF.getInfo(); + const MachineFrameInfo &MFI = MF.getFrameInfo(); + const std::vector &CSI = MFI.getCalleeSavedInfo(); + uint64_t StackSize = MFI.getStackSize(); + if (RVFI->getLibCallStackSize()) { + FirstSPAdjustAmount = 0; + } + if (!isInt<12>(StackSize) && (CSI.size() > 0)) { + FirstSPAdjustAmount = 2048 - getStackAlign().value(); + } + if (FirstSPAdjustAmount) { + uint64_t SecondSPAdjustAmount = MFI.getStackSize() - FirstSPAdjustAmount; + assert(SecondSPAdjustAmount > 0 && "SecondSPAdjustAmount should be greater than zero"); + adjustReg(MBB, LastFrameDestroy, DL, SPReg, SPReg, SecondSPAdjustAmount, MachineInstr::FrameDestroy); + } + if (FirstSPAdjustAmount) { + StackSize = FirstSPAdjustAmount; + } + adjustReg(MBB, MBBI, DL, SPReg, SPReg, StackSize, MachineInstr::FrameDestroy); + if (!MF.getFunction().hasFnAttribute(Attribute::ShadowCallStack)) { + return; + } + const auto &STI = MF.getSubtarget(); + Register RAReg = STI.getRegisterInfo()->getRARegister();. + std::vector &CSI = MF.getFrameInfo().getCalleeSavedInfo(); + if (std::none_of(CSI.begin(), CSI.end(), [&](CalleeSavedInfo &CSR) { return CSR.getReg() == RAReg; })) { + return; + } + Register SCSPReg = RISCVABI::getSCSPReg(); + auto &Ctx = MF.getFunction().getContext(); + if (!STI.isRegisterReservedByUser(SCSPReg)) { + Ctx.diagnose(DiagnosticInfoUnsupported{MF.getFunction(), "x18 not reserved by user for Shadow Call Stack."}); + return; + } + const auto *RVFI = MF.getInfo(); + if (RVFI->useSaveRestoreLibCalls(MF)) { + Ctx.diagnose(DiagnosticInfoUnsupported{MF.getFunction(), "Shadow Call Stack cannot be combined with Save/Restore LibCalls."}); + return; + } + const RISCVInstrInfo *TII = STI.getInstrInfo(); + bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit); + int64_t SlotSize = STI.getXLen() / 8; + BuildMI(MBB, MI, DL, TII->get(IsRV64 ? RISCV::LD : RISCV::LW)).addReg(RAReg, RegState::Define).addReg(SCSPReg).addImm(-SlotSize); + BuildMI(MBB, MI, DL, TII->get(RISCV::ADDI)).addReg(SCSPReg, RegState::Define).addReg(SCSPReg).addImm(-SlotSize); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/FrameLowering/emitPrologue.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/FrameLowering/emitPrologue.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8048950b0f019688715749d1f0850f32087a97ea --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/FrameLowering/emitPrologue.cpp @@ -0,0 +1,130 @@ +void RISCVFrameLowering::emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const { + MachineFrameInfo &MFI = MF.getFrameInfo(); + auto *RVFI = MF.getInfo(); + const RISCVRegisterInfo *RI = STI.getRegisterInfo(); + const RISCVInstrInfo *TII = STI.getInstrInfo(); + MachineBasicBlock::iterator MBBI = MBB.begin(); + Register FPReg = RISCV::X8; + Register SPReg = RISCV::X2; + Register BPReg = RISCVABI::getBPReg(); + DebugLoc DL; + if (MF.getFunction().getCallingConv() == CallingConv::GHC) { + return ; + } + if (!MF.getFunction().hasFnAttribute(Attribute::ShadowCallStack)) { + return; + } + const auto &STI = MF.getSubtarget(); + Register RAReg = STI.getRegisterInfo()->getRARegister();. + std::vector &CSI = MF.getFrameInfo().getCalleeSavedInfo(); + if (std::none_of(CSI.begin(), CSI.end(), [&](CalleeSavedInfo &CSR) { return CSR.getReg() == RAReg; })) { + return; + } + Register SCSPReg = RISCVABI::getSCSPReg(); + auto &Ctx = MF.getFunction().getContext(); + if (!STI.isRegisterReservedByUser(SCSPReg)) { + Ctx.diagnose(DiagnosticInfoUnsupported{MF.getFunction(), "x18 not reserved by user for Shadow Call Stack."}); + return; + } + const auto *RVFI = MF.getInfo(); + if (RVFI->useSaveRestoreLibCalls(MF)) { + Ctx.diagnose(DiagnosticInfoUnsupported{MF.getFunction(), "Shadow Call Stack cannot be combined with Save/Restore LibCalls."}); + return; + } + const RISCVInstrInfo *TII = STI.getInstrInfo(); + bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit); + int64_t SlotSize = STI.getXLen() / 8; + BuildMI(MBB, MI, DL, TII->get(IsRV64 ? RISCV::LD : RISCV::LW)).addReg(RAReg, RegState::Define).addReg(SCSPReg).addImm(-SlotSize); + BuildMI(MBB, MI, DL, TII->get(RISCV::ADDI)).addReg(SCSPReg, RegState::Define).addReg(SCSPReg).addImm(-SlotSize); + while (MBBI != MBB.end() && MBBI->getFlag(MachineInstr::FrameSetup)) { + ++MBBI; + } + MachineFrameInfo &MFI = MF.getFrameInfo(); + uint64_t FrameSize = MFI.getStackSize(); + Align StackAlign = getStackAlign(); + uint64_t MaxCallSize = alignTo(MFI.getMaxCallFrameSize(), StackAlign); + MFI.setMaxCallFrameSize(MaxCallSize); + FrameSize = alignTo(FrameSize, StackAlign); + MFI.setStackSize(FrameSize); + if (int LibCallRegs = getLibCallID(MF, MFI.getCalleeSavedInfo()) + 1) { + unsigned LibCallFrameSize = alignTo((STI.getXLen() / 8) * LibCallRegs, 16); + RVFI->setLibCallStackSize(LibCallFrameSize); + } + uint64_t StackSize = MFI.getStackSize(); + uint64_t RealStackSize = StackSize + RVFI->getLibCallStackSize(); + if (RealStackSize == 0 && !MFI.adjustsStack()) { + return ; + } + if (STI.isRegisterReservedByUser(SPReg)) { + MF.getFunction().getContext().diagnose(DiagnosticInfoUnsupported{MF.getFunction(), "Stack pointer required, but has been reserved."}); + } + uint64_t FirstSPAdjustAmount = 0; + const auto *RVFI = MF.getInfo(); + const MachineFrameInfo &MFI = MF.getFrameInfo(); + const std::vector &CSI = MFI.getCalleeSavedInfo(); + uint64_t StackSize = MFI.getStackSize(); + if (RVFI->getLibCallStackSize()) { + FirstSPAdjustAmount = 0; + } + if (!isInt<12>(StackSize) && (CSI.size() > 0)) { + FirstSPAdjustAmount = 2048 - getStackAlign().value(); + } + if (FirstSPAdjustAmount) { + StackSize = FirstSPAdjustAmount; + RealStackSize = FirstSPAdjustAmount; + } + adjustReg(MBB, MBBI, DL, SPReg, SPReg, -StackSize, MachineInstr::FrameSetup); + unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, RealStackSize)); + BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)).addCFIIndex(CFIIndex); + const auto &CSI = MFI.getCalleeSavedInfo(); + std::advance(MBBI, getNonLibcallCSI(CSI).size()); + for (const auto &Entry : CSI) { + int FrameIdx = Entry.getFrameIdx(); + int64_t Offset; + if (FrameIdx < 0) { + Offset = FrameIdx * (int64_t) STI.getXLen() / 8; + } + else { + Offset = MFI.getObjectOffset(Entry.getFrameIdx()) - RVFI->getLibCallStackSize(); + } + Register Reg = Entry.getReg(); + unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(nullptr, RI->getDwarfRegNum(Reg, true), Offset)); + BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)).addCFIIndex(CFIIndex); + } + if (hasFP(MF)) { + if (STI.isRegisterReservedByUser(FPReg)) { + MF.getFunction().getContext().diagnose(DiagnosticInfoUnsupported{MF.getFunction(), "Frame pointer required, but has been reserved."}); + } + adjustReg(MBB, MBBI, DL, FPReg, SPReg, RealStackSize - RVFI->getVarArgsSaveSize(), MachineInstr::FrameSetup); + unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfa(nullptr, RI->getDwarfRegNum(FPReg, true), RVFI->getVarArgsSaveSize())); + BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)).addCFIIndex(CFIIndex); + } + if (FirstSPAdjustAmount) { + uint64_t SecondSPAdjustAmount = MFI.getStackSize() - FirstSPAdjustAmount; + assert(SecondSPAdjustAmount > 0 && "SecondSPAdjustAmount should be greater than zero"); + adjustReg(MBB, MBBI, DL, SPReg, SPReg, -SecondSPAdjustAmount, MachineInstr::FrameSetup); + if (!hasFP(MF)) { + unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, MFI.getStackSize())); + BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)).addCFIIndex(CFIIndex); + } + } + if (hasFP(MF)) { + const RISCVRegisterInfo *RI = STI.getRegisterInfo(); + if (RI->needsStackRealignment(MF)) { + Align MaxAlignment = MFI.getMaxAlign(); + const RISCVInstrInfo *TII = STI.getInstrInfo(); + if (isInt<12>(-(int)MaxAlignment.value())) { + BuildMI(MBB, MBBI, DL, TII->get(RISCV::ANDI), SPReg).addReg(SPReg).addImm(-(int)MaxAlignment.value()); + } + else { + unsigned ShiftAmount = Log2(MaxAlignment); + Register VR = MF.getRegInfo().createVirtualRegister(&RISCV::GPRRegClass); + BuildMI(MBB, MBBI, DL, TII->get(RISCV::SRLI), VR).addReg(SPReg).addImm(ShiftAmount); + BuildMI(MBB, MBBI, DL, TII->get(RISCV::SLLI), SPReg).addReg(VR).addImm(ShiftAmount); + } + if (hasBP(MF)) { + BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), BPReg).addReg(SPReg).addImm(0); + } + } + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/FrameLowering/getFrameIndexReference.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/FrameLowering/getFrameIndexReference.cpp new file mode 100644 index 0000000000000000000000000000000000000000..08c62666cb52c52383f1b96f43d706c6bca38eb7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/FrameLowering/getFrameIndexReference.cpp @@ -0,0 +1,67 @@ +StackOffset RISCVFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg) const { + const MachineFrameInfo &MFI = MF.getFrameInfo(); + const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo(); + const auto *RVFI = MF.getInfo(); + SmallVector NonLibcallCSI; + for (auto &CS : MFI.getCalleeSavedInfo()) { + if (CS.getFrameIdx() >= 0) { + NonLibcallCSI.push_back(CS); + } + } + const auto &CSI = NonLibcallCSI; + int MinCSFI = 0; + int MaxCSFI = -1; + int Offset = MFI.getObjectOffset(FI) - getOffsetOfLocalArea() + MFI.getOffsetAdjustment(); + uint64_t FirstSPAdjustAmount = 0; + const auto *RVFI = MF.getInfo(); + const MachineFrameInfo &MFI = MF.getFrameInfo(); + const std::vector &CSI = MFI.getCalleeSavedInfo(); + uint64_t StackSize = MFI.getStackSize(); + if (RVFI->getLibCallStackSize()) { + FirstSPAdjustAmount = 0; + } + if (!isInt<12>(StackSize) && (CSI.size() > 0)) { + FirstSPAdjustAmount = 2048 - getStackAlign().value(); + } + if (CSI.size()) { + MinCSFI = CSI[0].getFrameIdx(); + MaxCSFI = CSI[CSI.size() - 1].getFrameIdx(); + } + if (FI >= MinCSFI && FI <= MaxCSFI) { + FrameReg = RISCV::X2; + if (FirstSPAdjustAmount) { + Offset += FirstSPAdjustAmount; + } + else { + Offset += MFI.getStackSize(); + } + } + else if (RI->needsStackRealignment(MF) && !MFI.isFixedObjectIndex(FI)) { + if (hasBP(MF)) { + FrameReg = RISCVABI::getBPReg(); + } + else { + FrameReg = RISCV::X2; + } + Offset += MFI.getStackSize(); + if (FI < 0) { + Offset += RVFI->getLibCallStackSize(); + } + } + else { + FrameReg = RI->getFrameRegister(MF); + if (hasFP(MF)) { + Offset += RVFI->getVarArgsSaveSize(); + if (FI >= 0) { + Offset -= RVFI->getLibCallStackSize(); + } + } + else { + Offset += MFI.getStackSize(); + if (FI < 0) { + Offset += RVFI->getLibCallStackSize(); + } + } + } + return StackOffset::getFixed(Offset); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/FrameLowering/hasBP.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/FrameLowering/hasBP.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5574f49a88f76684df7f258066e46968b3ca683e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/FrameLowering/hasBP.cpp @@ -0,0 +1,5 @@ +bool RISCVFrameLowering::hasBP(const MachineFunction &MF) const { + const MachineFrameInfo &MFI = MF.getFrameInfo(); + const TargetRegisterInfo *TRI = STI.getRegisterInfo(); + return MFI.hasVarSizedObjects() && TRI->needsStackRealignment(MF); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/FrameLowering/hasFP.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/FrameLowering/hasFP.cpp new file mode 100644 index 0000000000000000000000000000000000000000..52beb3a078d6d11924752420b10316994936a37a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/FrameLowering/hasFP.cpp @@ -0,0 +1,5 @@ +bool RISCVFrameLowering::hasFP(const MachineFunction &MF) const { + const MachineFrameInfo &MFI = MF.getFrameInfo(); + const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); + return MF.getTarget().Options.DisableFramePointerElim(MF) || RegInfo->needsStackRealignment(MF) || MFI.hasVarSizedObjects() || MFI.isFrameAddressTaken(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/FrameLowering/hasReservedCallFrame.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/FrameLowering/hasReservedCallFrame.cpp new file mode 100644 index 0000000000000000000000000000000000000000..33c01431709078493a443b5c20651203bcfb781a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/FrameLowering/hasReservedCallFrame.cpp @@ -0,0 +1,3 @@ +bool RISCVFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const { + return !MF.getFrameInfo().hasVarSizedObjects(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/FrameLowering/processFunctionBeforeFrameFinalized.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/FrameLowering/processFunctionBeforeFrameFinalized.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4fd3e4fc864c8feda05e9898c4e705651542721e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/FrameLowering/processFunctionBeforeFrameFinalized.cpp @@ -0,0 +1,9 @@ +void RISCVFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS) const { + const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); + MachineFrameInfo &MFI = MF.getFrameInfo(); + const TargetRegisterClass *RC = &RISCV::GPRRegClass; + if (!isInt<11>(MFI.estimateStackSize(MF))) { + int RegScavFI = MFI.CreateStackObject(RegInfo->getSpillSize(*RC), RegInfo->getSpillAlign(*RC), false); + RS->addScavengingFrameIndex(RegScavFI); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/FrameLowering/restoreCalleeSavedRegisters.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/FrameLowering/restoreCalleeSavedRegisters.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5aad41ddb0dbd296fef38f4f37bb326d9717d4fd --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/FrameLowering/restoreCalleeSavedRegisters.cpp @@ -0,0 +1,70 @@ +bool RISCVFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, MutableArrayRef CSI, const TargetRegisterInfo *TRI) const { + if (CSI.empty()) { + return true; + } + MachineFunction *MF = MBB.getParent(); + const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo(); + DebugLoc DL; + if (MI != MBB.end() && !MI->isDebugInstr()) { + DL = MI->getDebugLoc(); + } + SmallVector NonLibcallCSI2; + for (auto &CS : CSI) { + if (CS.getFrameIdx() >= 0) { + NonLibcallCSI2.push_back(CS); + } + } + const auto &NonLibcallCSI = NonLibcallCSI2; + for (auto &CS : reverse(NonLibcallCSI)) { + Register Reg = CS.getReg(); + const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); + TII.loadRegFromStackSlot(MBB, MI, Reg, CS.getFrameIdx(), RC, TRI); + assert(MI != MBB.begin() && "loadRegFromStackSlot didn't insert any code!"); + } + const char *RestoreLibCall; + static const char *const RestoreLibCalls[] = {"__riscv_restore_0", "__riscv_restore_1", "__riscv_restore_2", "__riscv_restore_3", "__riscv_restore_4", "__riscv_restore_5", "__riscv_restore_6", "__riscv_restore_7", "__riscv_restore_8", "__riscv_restore_9", "__riscv_restore_10", "__riscv_restore_11", "__riscv_restore_12"}; + int LibCallID; + const auto *RVFI = MF.getInfo(); + if (CSI.empty() || !RVFI->useSaveRestoreLibCalls(MF)) { + LibCallID = -1; + } + Register MaxReg = RISCV::NoRegister; + for (auto &CS : CSI) { + if (CS.getFrameIdx() < 0) { + MaxReg = std::max(MaxReg.id(), CS.getReg().id()); + } + } + if (MaxReg == RISCV::NoRegister) { + LibCallID = -1; + } + switch (MaxReg) { + default: + llvm_unreachable("Something has gone wrong!"); + case RISCV::X27: LibCallID = 12; + case RISCV::X26: LibCallID = 11; + case RISCV::X25: LibCallID = 10; + case RISCV::X24: LibCallID = 9; + case RISCV::X23: LibCallID = 8; + case RISCV::X22: LibCallID = 7; + case RISCV::X21: LibCallID = 6; + case RISCV::X20: LibCallID = 5; + case RISCV::X19: LibCallID = 4; + case RISCV::X18: LibCallID = 3; + case RISCV::X9: LibCallID = 2; + case RISCV::X8: LibCallID = 1; + case RISCV::X1: LibCallID = 0; + } + if (LibCallID == -1) { + RestoreLibCall = nullptr; + } + RestoreLibCall = RestoreLibCalls[LibCallID]; + const char *RestoreLibCall = getRestoreLibCallName(*MF, CSI); + if (RestoreLibCall) { + MachineBasicBlock::iterator NewMI = BuildMI(MBB, MI, DL, TII.get(RISCV::PseudoTAIL)).addExternalSymbol(RestoreLibCall, RISCVII::MO_CALL).setMIFlag(MachineInstr::FrameDestroy); + if (MI != MBB.end() && MI->getOpcode() == RISCV::PseudoRET) { + NewMI->copyImplicitOps(*MF, *MI); + MI->eraseFromParent(); + } + } + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/FrameLowering/spillCalleeSavedRegisters.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/FrameLowering/spillCalleeSavedRegisters.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7344391a22670e42b028c4323e619b6fe220c4cb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/FrameLowering/spillCalleeSavedRegisters.cpp @@ -0,0 +1,67 @@ +bool RISCVFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef CSI, const TargetRegisterInfo *TRI) const { + if (CSI.empty()) { + return true; + } + MachineFunction *MF = MBB.getParent(); + const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo(); + DebugLoc DL; + if (MI != MBB.end() && !MI->isDebugInstr()) { + DL = MI->getDebugLoc(); + } + const char *SpillLibCall; + static const char *const SpillLibCalls[] = {"__riscv_save_0", "__riscv_save_1", "__riscv_save_2", "__riscv_save_3", "__riscv_save_4", "__riscv_save_5", "__riscv_save_6", "__riscv_save_7", "__riscv_save_8", "__riscv_save_9", "__riscv_save_10", "__riscv_save_11", "__riscv_save_12"}; + int LibCallID; + const auto *RVFI = MF.getInfo(); + if (CSI.empty() || !RVFI->useSaveRestoreLibCalls(MF)) { + LibCallID = -1; + } + Register MaxReg = RISCV::NoRegister; + for (auto &CS : CSI) { + if (CS.getFrameIdx() < 0) { + MaxReg = std::max(MaxReg.id(), CS.getReg().id()); + } + } + if (MaxReg == RISCV::NoRegister) { + LibCallID = -1; + } + switch (MaxReg) { + default: + llvm_unreachable("Something has gone wrong!"); + case RISCV::X27: LibCallID = 12; + case RISCV::X26: LibCallID = 11; + case RISCV::X25: LibCallID = 10; + case RISCV::X24: LibCallID = 9; + case RISCV::X23: LibCallID = 8; + case RISCV::X22: LibCallID = 7; + case RISCV::X21: LibCallID = 6; + case RISCV::X20: LibCallID = 5; + case RISCV::X19: LibCallID = 4; + case RISCV::X18: LibCallID = 3; + case RISCV::X9: LibCallID = 2; + case RISCV::X8: LibCallID = 1; + case RISCV::X1: LibCallID = 0; + } + if (LibCallID == -1) { + SpillLibCall = nullptr; + } + SpillLibCall = SpillLibCalls[LibCallID]; + if (SpillLibCall) { + BuildMI(MBB, MI, DL, TII.get(RISCV::PseudoCALLReg), RISCV::X5).addExternalSymbol(SpillLibCall, RISCVII::MO_CALL).setMIFlag(MachineInstr::FrameSetup); + for (auto &CS : CSI) { + MBB.addLiveIn(CS.getReg()); + } + } + SmallVector NonLibcallCSI2; + for (auto &CS : CSI) { + if (CS.getFrameIdx() >= 0) { + NonLibcallCSI2.push_back(CS); + } + } + const auto &NonLibcallCSI = NonLibcallCSI2; + for (auto &CS : NonLibcallCSI) { + Register Reg = CS.getReg(); + const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); + TII.storeRegToStackSlot(MBB, MI, Reg, true, CS.getFrameIdx(), RC, TRI); + } + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelDAGToDAG/DAGToDAGISel.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelDAGToDAG/DAGToDAGISel.cpp new file mode 100644 index 0000000000000000000000000000000000000000..71b402e1f73281139075f655ca142ba3f6cd7f6c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelDAGToDAG/DAGToDAGISel.cpp @@ -0,0 +1,2 @@ +explicit RISCVDAGToDAGISel(RISCVTargetMachine &TargetMachine) : SelectionDAGISel(TargetMachine) { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelDAGToDAG/MatchSLLIUW.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelDAGToDAG/MatchSLLIUW.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9823b1da0db069cc49a64e482ac6c5d70e2b57fe --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelDAGToDAG/MatchSLLIUW.cpp @@ -0,0 +1,14 @@ +bool RISCVDAGToDAGISel::MatchSLLIUW(SDNode *N) const { + assert(N->getOpcode() == ISD::AND); + assert(N->getOperand(0).getOpcode() == ISD::SHL); + assert(isa(N->getOperand(1))); + assert(isa(N->getOperand(0).getOperand(1))); + if (!Subtarget->is64Bit()) { + return false; + } + SDValue Shl = N->getOperand(0); + uint64_t VC1 = N->getConstantOperandVal(1); + uint64_t VC2 = Shl.getConstantOperandVal(1); + assert(VC2 < 32 && "Unexpected immediate"); + return (VC1 >> VC2) == UINT64_C(0xFFFFFFFF); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelDAGToDAG/MatchSRLIUW.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelDAGToDAG/MatchSRLIUW.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ed6d54e7e5c4fd7431794ade702363890c9fb9b9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelDAGToDAG/MatchSRLIUW.cpp @@ -0,0 +1,13 @@ +bool RISCVDAGToDAGISel::MatchSRLIW(SDNode *N) const { + assert(N->getOpcode() == ISD::SRL); + assert(N->getOperand(0).getOpcode() == ISD::AND); + assert(isa(N->getOperand(1))); + assert(isa(N->getOperand(0).getOperand(1))); + if (!Subtarget->is64Bit()) { + return false; + } + SDValue And = N->getOperand(0); + uint64_t ShAmt = N->getConstantOperandVal(1); + uint64_t Mask = And.getConstantOperandVal(1); + return (Mask | maskTrailingOnes(ShAmt)) == 0xffffffff; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelDAGToDAG/PostprocessISelDAG.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelDAGToDAG/PostprocessISelDAG.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f6328e8bc19e4b307aa8cec3d75d5573277b5e72 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelDAGToDAG/PostprocessISelDAG.cpp @@ -0,0 +1,83 @@ +void RISCVDAGToDAGISel::PostprocessISelDAG() { + SelectionDAG::allnodes_iterator Position(CurDAG->getRoot().getNode()); + ++Position; + while (Position != CurDAG->allnodes_begin()) { + SDNode *N = &*--Position; + if (N->use_empty() || !N->isMachineOpcode()) + continue; + int OffsetOpIdx; + int BaseOpIdx; + switch (N->getMachineOpcode()) { + default: + continue; + case RISCV::LB: + case RISCV::LH: + case RISCV::LW: + case RISCV::LBU: + case RISCV::LHU: + case RISCV::LWU: + case RISCV::LD: + case RISCV::FLH: + case RISCV::FLW: + case RISCV::FLD: + BaseOpIdx = 0; + OffsetOpIdx = 1; + break; + case RISCV::SB: + case RISCV::SH: + case RISCV::SW: + case RISCV::SD: + case RISCV::FSH: + case RISCV::FSW: + case RISCV::FSD: + BaseOpIdx = 1; + OffsetOpIdx = 2; + break; + } + if (!isa(N->getOperand(OffsetOpIdx))) + continue; + SDValue Base = N->getOperand(BaseOpIdx); + if (!Base.isMachineOpcode() || Base.getMachineOpcode() != RISCV::ADDI) + continue; + SDValue ImmOperand = Base.getOperand(1); + uint64_t Offset2 = N->getConstantOperandVal(OffsetOpIdx); + if (auto Const = dyn_cast(ImmOperand)) { + int64_t Offset1 = Const->getSExtValue(); + int64_t CombinedOffset = Offset1 + Offset2; + if (!isInt<12>(CombinedOffset)) + continue; + ImmOperand = CurDAG->getTargetConstant(CombinedOffset, SDLoc(ImmOperand), ImmOperand.getValueType()); + } + else if (auto GA = dyn_cast(ImmOperand)) { + const DataLayout &DL = CurDAG->getDataLayout(); + Align Alignment = GA->getGlobal()->getPointerAlignment(DL); + if (Offset2 != 0 && Alignment <= Offset2) + continue; + int64_t Offset1 = GA->getOffset(); + int64_t CombinedOffset = Offset1 + Offset2; + ImmOperand = CurDAG->getTargetGlobalAddress(GA->getGlobal(), SDLoc(ImmOperand), ImmOperand.getValueType(), CombinedOffset, GA->getTargetFlags()); + } + else if (auto CP = dyn_cast(ImmOperand)) { + Align Alignment = CP->getAlign(); + if (Offset2 != 0 && Alignment <= Offset2) + continue; + int64_t Offset1 = CP->getOffset(); + int64_t CombinedOffset = Offset1 + Offset2; + ImmOperand = CurDAG->getTargetConstantPool(CP->getConstVal(), ImmOperand.getValueType(), CP->getAlign(), CombinedOffset, CP->getTargetFlags()); + } + else { + continue; + } + LLVM_DEBUG(dbgs() << "Folding add-immediate into mem-op:\nBase: "); + LLVM_DEBUG(Base->dump(CurDAG)); + LLVM_DEBUG(dbgs() << "\nN: "); + LLVM_DEBUG(N->dump(CurDAG)); + LLVM_DEBUG(dbgs() << "\n"); + if (BaseOpIdx == 0) + CurDAG->UpdateNodeOperands(N, Base.getOperand(0), ImmOperand, N->getOperand(2)); + else + CurDAG->UpdateNodeOperands(N, N->getOperand(0), Base.getOperand(0), ImmOperand, N->getOperand(3)); + if (Base.getNode()->use_empty()) + CurDAG->RemoveDeadNode(Base.getNode()); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelDAGToDAG/Select.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelDAGToDAG/Select.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7a7775f229ef2daf901972a36677bc646ce468e3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelDAGToDAG/Select.cpp @@ -0,0 +1,689 @@ +void RISCVDAGToDAGISel::Select(SDNode *Node) { + if (Node->isMachineOpcode()) { + LLVM_DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << "\n"); + Node->setNodeId(-1); + return; + } + unsigned Opcode = Node->getOpcode(); + MVT XLenVT = Subtarget->getXLenVT(); + SDLoc DL(Node); + EVT VT = Node->getValueType(0); + switch (Opcode) { + case ISD::ADD: { + if (auto *ConstOp = dyn_cast(Node->getOperand(1))) { + if (!(ConstOp->hasOneUse())) { + break; + } + int64_t Imm = ConstOp->getSExtValue(); + if (!(-4096 <= Imm && Imm <= -2049) && !(2048 <= Imm && Imm <= 4094)) { + break; + } + EVT VT = Node->getValueType(0); + const SDValue ImmOp0 = CurDAG->getTargetConstant(Imm - Imm / 2, DL, VT); + const SDValue ImmOp1 = CurDAG->getTargetConstant(Imm / 2, DL, VT); + auto *NodeAddi0 = CurDAG->getMachineNode(RISCV::ADDI, DL, VT, + Node->getOperand(0), ImmOp0); + auto *NodeAddi1 = CurDAG->getMachineNode(RISCV::ADDI, DL, VT, + SDValue(NodeAddi0, 0), ImmOp1); + ReplaceNode(Node, NodeAddi1); + return; + } + break; + } + case ISD::Constant: { + auto ConstNode = cast(Node); + if (VT == XLenVT && ConstNode->isNullValue()) { + SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL, RISCV::X0, XLenVT); + ReplaceNode(Node, New.getNode()); + return; + } + int64_t Imm = ConstNode->getSExtValue(); + if (XLenVT == MVT::i64) { + ReplaceNode(Node, selectImm(CurDAG, DL, Imm, XLenVT)); + return; + } + break; + } + case ISD::FrameIndex: { + SDValue Imm = CurDAG->getTargetConstant(0, DL, XLenVT); + int FI = cast(Node)->getIndex(); + SDValue TFI = CurDAG->getTargetFrameIndex(FI, VT); + ReplaceNode(Node, CurDAG->getMachineNode(RISCV::ADDI, DL, VT, TFI, Imm)); + return; + } + case ISD::INTRINSIC_W_CHAIN: { + unsigned IntNo = cast(Node->getOperand(1))->getZExtValue(); + switch (IntNo) { + default: + break; + case Intrinsic::riscv_vsetvli: { + if (!Subtarget->hasStdExtV()) { + break; + } + assert(Node->getNumOperands() == 5); + RISCVVSEW VSEW = static_cast(Node->getConstantOperandVal(3) & 0x7); + RISCVVLMUL VLMul = static_cast(Node->getConstantOperandVal(4) & 0x7); + unsigned VTypeI = RISCVVType::encodeVTYPE(VLMul, VSEW, true, false); + SDValue VTypeIOp = CurDAG->getTargetConstant(VTypeI, DL, XLenVT); + SDValue VLOperand = Node->getOperand(2); + if (auto *C = dyn_cast(VLOperand)) { + uint64_t AVL = C->getZExtValue(); + if (isUInt<5>(AVL)) { + SDValue VLImm = CurDAG->getTargetConstant(AVL, DL, XLenVT); + ReplaceNode(Node, CurDAG->getMachineNode(RISCV::PseudoVSETIVLI, DL, XLenVT, MVT::Other, VLImm, VTypeIOp, Node->getOperand(0))); + return; + } + } + ReplaceNode(Node, CurDAG->getMachineNode(RISCV::PseudoVSETVLI, DL, XLenVT, MVT::Other, VLOperand, VTypeIOp, Node->getOperand(0))); + return; + } + case Intrinsic::riscv_vsetvlimax: { + if (!Subtarget->hasStdExtV()) { + break; + } + assert(Node->getNumOperands() == 4); + RISCVVSEW VSEW = static_cast(Node->getConstantOperandVal(2) & 0x7); + RISCVVLMUL VLMul = static_cast(Node->getConstantOperandVal(3) & 0x7); + unsigned VTypeI = RISCVVType::encodeVTYPE(VLMul, VSEW, true, false); + SDValue VTypeIOp = CurDAG->getTargetConstant(VTypeI, DL, XLenVT); + SDValue VLOperand = CurDAG->getRegister(RISCV::X0, XLenVT); + ReplaceNode(Node, CurDAG->getMachineNode(RISCV::PseudoVSETVLI, DL, XLenVT, MVT::Other, VLOperand, VTypeIOp, Node->getOperand(0))); + return; + } + case Intrinsic::riscv_vlseg2: + case Intrinsic::riscv_vlseg3: + case Intrinsic::riscv_vlseg4: + case Intrinsic::riscv_vlseg5: + case Intrinsic::riscv_vlseg6: + case Intrinsic::riscv_vlseg7: + case Intrinsic::riscv_vlseg8: { + SDLoc DL(Node); + unsigned NF = Node->getNumValues() - 1; + EVT VT = Node->getValueType(0); + unsigned ScalarSize = VT.getScalarSizeInBits(); + MVT XLenVT = Subtarget->getXLenVT(); + RISCVVLMUL LMUL = getLMUL(VT); + SDValue SEW = CurDAG->getTargetConstant(ScalarSize, DL, XLenVT); + SmallVector Operands; + Operands.push_back(Node->getOperand(2)); + if (IsStrided) { + Operands.push_back(Node->getOperand(3)); + Operands.push_back(Node->getOperand(4)); + } + else { + Operands.push_back(Node->getOperand(3)); + } + Operands.push_back(SEW); + Operands.push_back(Node->getOperand(0)); + const RISCVZvlssegTable::RISCVZvlsseg *P = RISCVZvlssegTable::getPseudo(IntNo, ScalarSize, static_cast(LMUL), static_cast(RISCVVLMUL::LMUL_1)); + SDNode *Load = CurDAG->getMachineNode(P->Pseudo, DL, MVT::Untyped, MVT::Other, Operands); + SDValue SuperReg = SDValue(Load, 0); + for (unsigned I = 0; I < NF; ++I) + ReplaceUses(SDValue(Node, I), CurDAG->getTargetExtractSubreg(getSubregIndexByEVT(VT, I), DL, VT, SuperReg)); + ReplaceUses(SDValue(Node, NF), SDValue(Load, 1)); + CurDAG->RemoveDeadNode(Node); + return; + } + case Intrinsic::riscv_vlseg2_mask: + case Intrinsic::riscv_vlseg3_mask: + case Intrinsic::riscv_vlseg4_mask: + case Intrinsic::riscv_vlseg5_mask: + case Intrinsic::riscv_vlseg6_mask: + case Intrinsic::riscv_vlseg7_mask: + case Intrinsic::riscv_vlseg8_mask: { + SDLoc DL(Node); + unsigned NF = Node->getNumValues() - 1; + EVT VT = Node->getValueType(0); + unsigned ScalarSize = VT.getScalarSizeInBits(); + MVT XLenVT = Subtarget->getXLenVT(); + RISCVVLMUL LMUL = getLMUL(VT); + SDValue SEW = CurDAG->getTargetConstant(ScalarSize, DL, XLenVT); + SmallVector Regs(Node->op_begin() + 2, Node->op_begin() + 2 + NF); + SDValue MaskedOff = createTuple(*CurDAG, Regs, NF, LMUL); + SmallVector Operands; + Operands.push_back(MaskedOff); + Operands.push_back(Node->getOperand(NF + 2)); + if (IsStrided) { + Operands.push_back(Node->getOperand(NF + 3)); + Operands.push_back(Node->getOperand(NF + 4)); + Operands.push_back(Node->getOperand(NF + 5)); + } else { + Operands.push_back(Node->getOperand(NF + 3)); + Operands.push_back(Node->getOperand(NF + 4)); + } + Operands.push_back(SEW); + Operands.push_back(Node->getOperand(0)); + const RISCVZvlssegTable::RISCVZvlsseg *P = RISCVZvlssegTable::getPseudo(IntNo, ScalarSize, static_cast(LMUL), static_cast(RISCVVLMUL::LMUL_1)); + SDNode *Load = CurDAG->getMachineNode(P->Pseudo, DL, MVT::Untyped, MVT::Other, Operands); + SDValue SuperReg = SDValue(Load, 0); + for (unsigned I = 0; I < NF; ++I) + ReplaceUses(SDValue(Node, I), CurDAG->getTargetExtractSubreg(getSubregIndexByEVT(VT, I), DL, VT, SuperReg)); + ReplaceUses(SDValue(Node, NF), SDValue(Load, 1)); + CurDAG->RemoveDeadNode(Node); + return; + } + case Intrinsic::riscv_vlsseg2: + case Intrinsic::riscv_vlsseg3: + case Intrinsic::riscv_vlsseg4: + case Intrinsic::riscv_vlsseg5: + case Intrinsic::riscv_vlsseg6: + case Intrinsic::riscv_vlsseg7: + case Intrinsic::riscv_vlsseg8: { + SDLoc DL(Node); + unsigned NF = Node->getNumValues() - 1; + EVT VT = Node->getValueType(0); + unsigned ScalarSize = VT.getScalarSizeInBits(); + MVT XLenVT = Subtarget->getXLenVT(); + RISCVVLMUL LMUL = getLMUL(VT); + SDValue SEW = CurDAG->getTargetConstant(ScalarSize, DL, XLenVT); + SmallVector Operands; + Operands.push_back(Node->getOperand(2)); + if (IsStrided) { + Operands.push_back(Node->getOperand(3)); + Operands.push_back(Node->getOperand(4)); + } + else { + Operands.push_back(Node->getOperand(3)); + } + Operands.push_back(SEW); + Operands.push_back(Node->getOperand(0)); + const RISCVZvlssegTable::RISCVZvlsseg *P = RISCVZvlssegTable::getPseudo(IntNo, ScalarSize, static_cast(LMUL), static_cast(RISCVVLMUL::LMUL_1)); + SDNode *Load = CurDAG->getMachineNode(P->Pseudo, DL, MVT::Untyped, MVT::Other, Operands); + SDValue SuperReg = SDValue(Load, 0); + for (unsigned I = 0; I < NF; ++I) + ReplaceUses(SDValue(Node, I), CurDAG->getTargetExtractSubreg(getSubregIndexByEVT(VT, I), DL, VT, SuperReg)); + ReplaceUses(SDValue(Node, NF), SDValue(Load, 1)); + CurDAG->RemoveDeadNode(Node); + return; + } + case Intrinsic::riscv_vlsseg2_mask: + case Intrinsic::riscv_vlsseg3_mask: + case Intrinsic::riscv_vlsseg4_mask: + case Intrinsic::riscv_vlsseg5_mask: + case Intrinsic::riscv_vlsseg6_mask: + case Intrinsic::riscv_vlsseg7_mask: + case Intrinsic::riscv_vlsseg8_mask: { + SDLoc DL(Node); + unsigned NF = Node->getNumValues() - 1; + EVT VT = Node->getValueType(0); + unsigned ScalarSize = VT.getScalarSizeInBits(); + MVT XLenVT = Subtarget->getXLenVT(); + RISCVVLMUL LMUL = getLMUL(VT); + SDValue SEW = CurDAG->getTargetConstant(ScalarSize, DL, XLenVT); + SmallVector Regs(Node->op_begin() + 2, Node->op_begin() + 2 + NF); + SDValue MaskedOff = createTuple(*CurDAG, Regs, NF, LMUL); + SmallVector Operands; + Operands.push_back(MaskedOff); + Operands.push_back(Node->getOperand(NF + 2)); + if (IsStrided) { + Operands.push_back(Node->getOperand(NF + 3)); + Operands.push_back(Node->getOperand(NF + 4)); + Operands.push_back(Node->getOperand(NF + 5)); + } + else { + Operands.push_back(Node->getOperand(NF + 3)); + Operands.push_back(Node->getOperand(NF + 4)); + } + Operands.push_back(SEW); + Operands.push_back(Node->getOperand(0)); + const RISCVZvlssegTable::RISCVZvlsseg *P = RISCVZvlssegTable::getPseudo(IntNo, ScalarSize, static_cast(LMUL), static_cast(RISCVVLMUL::LMUL_1)); + SDNode *Load = CurDAG->getMachineNode(P->Pseudo, DL, MVT::Untyped, MVT::Other, Operands); + SDValue SuperReg = SDValue(Load, 0); + for (unsigned I = 0; I < NF; ++I) + ReplaceUses(SDValue(Node, I), CurDAG->getTargetExtractSubreg(getSubregIndexByEVT(VT, I), DL, VT, SuperReg)); + ReplaceUses(SDValue(Node, NF), SDValue(Load, 1)); + CurDAG->RemoveDeadNode(Node); + return; + } + case Intrinsic::riscv_vloxseg2: + case Intrinsic::riscv_vloxseg3: + case Intrinsic::riscv_vloxseg4: + case Intrinsic::riscv_vloxseg5: + case Intrinsic::riscv_vloxseg6: + case Intrinsic::riscv_vloxseg7: + case Intrinsic::riscv_vloxseg8: + case Intrinsic::riscv_vluxseg2: + case Intrinsic::riscv_vluxseg3: + case Intrinsic::riscv_vluxseg4: + case Intrinsic::riscv_vluxseg5: + case Intrinsic::riscv_vluxseg6: + case Intrinsic::riscv_vluxseg7: + case Intrinsic::riscv_vluxseg8: { + SDLoc DL(Node); + unsigned NF = Node->getNumValues() - 1; + EVT VT = Node->getValueType(0); + unsigned ScalarSize = VT.getScalarSizeInBits(); + MVT XLenVT = Subtarget->getXLenVT(); + RISCVVLMUL LMUL = getLMUL(VT); + SDValue SEW = CurDAG->getTargetConstant(ScalarSize, DL, XLenVT); + SDValue Operands[] = { + Node->getOperand(2), + Node->getOperand(3), + Node->getOperand(4), + SEW, Node->getOperand(0) + }; + EVT IndexVT = Node->getOperand(3)->getValueType(0); + RISCVVLMUL IndexLMUL = getLMUL(IndexVT); + unsigned IndexScalarSize = IndexVT.getScalarSizeInBits(); + const RISCVZvlssegTable::RISCVZvlsseg *P = RISCVZvlssegTable::getPseudo(IntNo, IndexScalarSize, static_cast(LMUL), static_cast(IndexLMUL)); + SDNode *Load = CurDAG->getMachineNode(P->Pseudo, DL, MVT::Untyped, MVT::Other, Operands); + SDValue SuperReg = SDValue(Load, 0); + for (unsigned I = 0; I < NF; ++I) + ReplaceUses(SDValue(Node, I), CurDAG->getTargetExtractSubreg(getSubregIndexByEVT(VT, I), DL,VT, SuperReg)); + ReplaceUses(SDValue(Node, NF), SDValue(Load, 1)); + CurDAG->RemoveDeadNode(Node); + return; + } + case Intrinsic::riscv_vloxseg2_mask: + case Intrinsic::riscv_vloxseg3_mask: + case Intrinsic::riscv_vloxseg4_mask: + case Intrinsic::riscv_vloxseg5_mask: + case Intrinsic::riscv_vloxseg6_mask: + case Intrinsic::riscv_vloxseg7_mask: + case Intrinsic::riscv_vloxseg8_mask: + case Intrinsic::riscv_vluxseg2_mask: + case Intrinsic::riscv_vluxseg3_mask: + case Intrinsic::riscv_vluxseg4_mask: + case Intrinsic::riscv_vluxseg5_mask: + case Intrinsic::riscv_vluxseg6_mask: + case Intrinsic::riscv_vluxseg7_mask: + case Intrinsic::riscv_vluxseg8_mask: { + SDLoc DL(Node); + unsigned NF = Node->getNumValues() - 1; + EVT VT = Node->getValueType(0); + unsigned ScalarSize = VT.getScalarSizeInBits(); + MVT XLenVT = Subtarget->getXLenVT(); + RISCVVLMUL LMUL = getLMUL(VT); + SDValue SEW = CurDAG->getTargetConstant(ScalarSize, DL, XLenVT); + SmallVector Regs(Node->op_begin() + 2, Node->op_begin() + 2 + NF); + SDValue MaskedOff = createTuple(*CurDAG, Regs, NF, LMUL); + SDValue Operands[] = { + MaskedOff, + Node->getOperand(NF + 2), + Node->getOperand(NF + 3), + Node->getOperand(NF + 4), + Node->getOperand(NF + 5), + SEW, + Node->getOperand(0) + }; + EVT IndexVT = Node->getOperand(NF + 3)->getValueType(0); + RISCVVLMUL IndexLMUL = getLMUL(IndexVT); + unsigned IndexScalarSize = IndexVT.getScalarSizeInBits(); + const RISCVZvlssegTable::RISCVZvlsseg *P = RISCVZvlssegTable::getPseudo(IntNo, IndexScalarSize, static_cast(LMUL), static_cast(IndexLMUL)); + SDNode *Load = CurDAG->getMachineNode(P->Pseudo, DL, MVT::Untyped, MVT::Other, Operands); + SDValue SuperReg = SDValue(Load, 0); + for (unsigned I = 0; I < NF; ++I) + ReplaceUses(SDValue(Node, I), CurDAG->getTargetExtractSubreg(getSubregIndexByEVT(VT, I), DL, VT, SuperReg)); + ReplaceUses(SDValue(Node, NF), SDValue(Load, 1)); + CurDAG->RemoveDeadNode(Node); + return; + } + } + break; + } + case ISD::INTRINSIC_VOID: { + unsigned IntNo = cast(Node->getOperand(1))->getZExtValue(); + switch (IntNo) { + case Intrinsic::riscv_vsseg2: + case Intrinsic::riscv_vsseg3: + case Intrinsic::riscv_vsseg4: + case Intrinsic::riscv_vsseg5: + case Intrinsic::riscv_vsseg6: + case Intrinsic::riscv_vsseg7: + case Intrinsic::riscv_vsseg8: { + SDLoc DL(Node); + unsigned NF = Node->getNumOperands() - 4; + if (IsStrided) + NF--; + EVT VT = Node->getOperand(2)->getValueType(0); + unsigned ScalarSize = VT.getScalarSizeInBits(); + MVT XLenVT = Subtarget->getXLenVT(); + RISCVVLMUL LMUL = getLMUL(VT); + SDValue SEW = CurDAG->getTargetConstant(ScalarSize, DL, XLenVT); + SmallVector Regs(Node->op_begin() + 2, Node->op_begin() + 2 + NF); + SDValue StoreVal = createTuple(*CurDAG, Regs, NF, LMUL); + SmallVector Operands; + Operands.push_back(StoreVal); + Operands.push_back(Node->getOperand(2 + NF)); + if (IsStrided) { + Operands.push_back(Node->getOperand(3 + NF)); + Operands.push_back(Node->getOperand(4 + NF)); + } + else { + Operands.push_back(Node->getOperand(3 + NF)); + } + Operands.push_back(SEW); + Operands.push_back(Node->getOperand(0)); + const RISCVZvlssegTable::RISCVZvlsseg *P = RISCVZvlssegTable::getPseudo(IntNo, ScalarSize, static_cast(LMUL), static_cast(RISCVVLMUL::LMUL_1)); + SDNode *Store = CurDAG->getMachineNode(P->Pseudo, DL, Node->getValueType(0), Operands); + ReplaceNode(Node, Store); + return; + } + case Intrinsic::riscv_vsseg2_mask: + case Intrinsic::riscv_vsseg3_mask: + case Intrinsic::riscv_vsseg4_mask: + case Intrinsic::riscv_vsseg5_mask: + case Intrinsic::riscv_vsseg6_mask: + case Intrinsic::riscv_vsseg7_mask: + case Intrinsic::riscv_vsseg8_mask: { + SDLoc DL(Node); + unsigned NF = Node->getNumOperands() - 5; + if (IsStrided) + NF--; + EVT VT = Node->getOperand(2)->getValueType(0); + unsigned ScalarSize = VT.getScalarSizeInBits(); + MVT XLenVT = Subtarget->getXLenVT(); + RISCVVLMUL LMUL = getLMUL(VT); + SDValue SEW = CurDAG->getTargetConstant(ScalarSize, DL, XLenVT); + SmallVector Regs(Node->op_begin() + 2, Node->op_begin() + 2 + NF); + SDValue StoreVal = createTuple(*CurDAG, Regs, NF, LMUL); + SmallVector Operands; + Operands.push_back(StoreVal); + Operands.push_back(Node->getOperand(2 + NF)); + if (IsStrided) { + Operands.push_back(Node->getOperand(3 + NF)); + Operands.push_back(Node->getOperand(4 + NF)); + Operands.push_back(Node->getOperand(5 + NF)); + } + else { + Operands.push_back(Node->getOperand(3 + NF)); + Operands.push_back(Node->getOperand(4 + NF)); + } + Operands.push_back(SEW); + Operands.push_back(Node->getOperand(0)); + const RISCVZvlssegTable::RISCVZvlsseg *P = RISCVZvlssegTable::getPseudo(IntNo, ScalarSize, static_cast(LMUL), static_cast(RISCVVLMUL::LMUL_1)); + SDNode *Store = CurDAG->getMachineNode(P->Pseudo, DL, Node->getValueType(0), Operands); + ReplaceNode(Node, Store); + return; + } + case Intrinsic::riscv_vssseg2: + case Intrinsic::riscv_vssseg3: + case Intrinsic::riscv_vssseg4: + case Intrinsic::riscv_vssseg5: + case Intrinsic::riscv_vssseg6: + case Intrinsic::riscv_vssseg7: + case Intrinsic::riscv_vssseg8: { + SDLoc DL(Node); + unsigned NF = Node->getNumOperands() - 4; + if (IsStrided) + NF--; + EVT VT = Node->getOperand(2)->getValueType(0); + unsigned ScalarSize = VT.getScalarSizeInBits(); + MVT XLenVT = Subtarget->getXLenVT(); + RISCVVLMUL LMUL = getLMUL(VT); + SDValue SEW = CurDAG->getTargetConstant(ScalarSize, DL, XLenVT); + SmallVector Regs(Node->op_begin() + 2, Node->op_begin() + 2 + NF); + SDValue StoreVal = createTuple(*CurDAG, Regs, NF, LMUL); + SmallVector Operands; + Operands.push_back(StoreVal); + Operands.push_back(Node->getOperand(2 + NF)); + if (IsStrided) { + Operands.push_back(Node->getOperand(3 + NF)); + Operands.push_back(Node->getOperand(4 + NF)); + } + else { + Operands.push_back(Node->getOperand(3 + NF)); + } + Operands.push_back(SEW); + Operands.push_back(Node->getOperand(0)); + const RISCVZvlssegTable::RISCVZvlsseg *P = RISCVZvlssegTable::getPseudo(IntNo, ScalarSize, static_cast(LMUL), static_cast(RISCVVLMUL::LMUL_1)); + SDNode *Store = CurDAG->getMachineNode(P->Pseudo, DL, Node->getValueType(0), Operands); + ReplaceNode(Node, Store); + return; + } + case Intrinsic::riscv_vssseg2_mask: + case Intrinsic::riscv_vssseg3_mask: + case Intrinsic::riscv_vssseg4_mask: + case Intrinsic::riscv_vssseg5_mask: + case Intrinsic::riscv_vssseg6_mask: + case Intrinsic::riscv_vssseg7_mask: + case Intrinsic::riscv_vssseg8_mask: { + SDLoc DL(Node); + unsigned NF = Node->getNumOperands() - 5; + if (IsStrided) + NF--; + EVT VT = Node->getOperand(2)->getValueType(0); + unsigned ScalarSize = VT.getScalarSizeInBits(); + MVT XLenVT = Subtarget->getXLenVT(); + RISCVVLMUL LMUL = getLMUL(VT); + SDValue SEW = CurDAG->getTargetConstant(ScalarSize, DL, XLenVT); + SmallVector Regs(Node->op_begin() + 2, Node->op_begin() + 2 + NF); + SDValue StoreVal = createTuple(*CurDAG, Regs, NF, LMUL); + SmallVector Operands; + Operands.push_back(StoreVal); + Operands.push_back(Node->getOperand(2 + NF)); + if (IsStrided) { + Operands.push_back(Node->getOperand(3 + NF)); + Operands.push_back(Node->getOperand(4 + NF)); + Operands.push_back(Node->getOperand(5 + NF)); + } + else { + Operands.push_back(Node->getOperand(3 + NF)); + Operands.push_back(Node->getOperand(4 + NF)); + } + Operands.push_back(SEW); + Operands.push_back(Node->getOperand(0)); + const RISCVZvlssegTable::RISCVZvlsseg *P = RISCVZvlssegTable::getPseudo(IntNo, ScalarSize, static_cast(LMUL), static_cast(RISCVVLMUL::LMUL_1)); + SDNode *Store = CurDAG->getMachineNode(P->Pseudo, DL, Node->getValueType(0), Operands); + ReplaceNode(Node, Store); + return; + } + case Intrinsic::riscv_vsoxseg2: + case Intrinsic::riscv_vsoxseg3: + case Intrinsic::riscv_vsoxseg4: + case Intrinsic::riscv_vsoxseg5: + case Intrinsic::riscv_vsoxseg6: + case Intrinsic::riscv_vsoxseg7: + case Intrinsic::riscv_vsoxseg8: + case Intrinsic::riscv_vsuxseg2: + case Intrinsic::riscv_vsuxseg3: + case Intrinsic::riscv_vsuxseg4: + case Intrinsic::riscv_vsuxseg5: + case Intrinsic::riscv_vsuxseg6: + case Intrinsic::riscv_vsuxseg7: + case Intrinsic::riscv_vsuxseg8: { + SDLoc DL(Node); + unsigned NF = Node->getNumOperands() - 5; + EVT VT = Node->getOperand(2)->getValueType(0); + unsigned ScalarSize = VT.getScalarSizeInBits(); + MVT XLenVT = Subtarget->getXLenVT(); + RISCVVLMUL LMUL = getLMUL(VT); + SDValue SEW = CurDAG->getTargetConstant(ScalarSize, DL, XLenVT); + SmallVector Regs(Node->op_begin() + 2, Node->op_begin() + 2 + NF); + SDValue StoreVal = createTuple(*CurDAG, Regs, NF, LMUL); + SDValue Operands[] = { + StoreVal, + Node->getOperand(2 + NF), + Node->getOperand(3 + NF), + Node->getOperand(4 + NF), + SEW, + Node->getOperand(0) + }; + EVT IndexVT = Node->getOperand(3 + NF)->getValueType(0); + RISCVVLMUL IndexLMUL = getLMUL(IndexVT); + unsigned IndexScalarSize = IndexVT.getScalarSizeInBits(); + const RISCVZvlssegTable::RISCVZvlsseg *P = RISCVZvlssegTable::getPseudo(IntNo, IndexScalarSize, static_cast(LMUL), static_cast(IndexLMUL)); + SDNode *Store = CurDAG->getMachineNode(P->Pseudo, DL, Node->getValueType(0), Operands); + ReplaceNode(Node, Store); + return; + } + case Intrinsic::riscv_vsoxseg2_mask: + case Intrinsic::riscv_vsoxseg3_mask: + case Intrinsic::riscv_vsoxseg4_mask: + case Intrinsic::riscv_vsoxseg5_mask: + case Intrinsic::riscv_vsoxseg6_mask: + case Intrinsic::riscv_vsoxseg7_mask: + case Intrinsic::riscv_vsoxseg8_mask: + case Intrinsic::riscv_vsuxseg2_mask: + case Intrinsic::riscv_vsuxseg3_mask: + case Intrinsic::riscv_vsuxseg4_mask: + case Intrinsic::riscv_vsuxseg5_mask: + case Intrinsic::riscv_vsuxseg6_mask: + case Intrinsic::riscv_vsuxseg7_mask: + case Intrinsic::riscv_vsuxseg8_mask: { + SDLoc DL(Node); + unsigned NF = Node->getNumOperands() - 6; + EVT VT = Node->getOperand(2)->getValueType(0); + unsigned ScalarSize = VT.getScalarSizeInBits(); + MVT XLenVT = Subtarget->getXLenVT(); + RISCVVLMUL LMUL = getLMUL(VT); + SDValue SEW = CurDAG->getTargetConstant(ScalarSize, DL, XLenVT); + SmallVector Regs(Node->op_begin() + 2, Node->op_begin() + 2 + NF); + SDValue StoreVal = createTuple(*CurDAG, Regs, NF, LMUL); + SDValue Operands[] = { + StoreVal, + Node->getOperand(2 + NF), + Node->getOperand(3 + NF), + Node->getOperand(4 + NF), + Node->getOperand(5 + NF), + SEW, + Node->getOperand(0) + }; + EVT IndexVT = Node->getOperand(3 + NF)->getValueType(0); + RISCVVLMUL IndexLMUL = getLMUL(IndexVT); + unsigned IndexScalarSize = IndexVT.getScalarSizeInBits(); + const RISCVZvlssegTable::RISCVZvlsseg *P = RISCVZvlssegTable::getPseudo(IntNo, IndexScalarSize, static_cast(LMUL), static_cast(IndexLMUL)); + SDNode *Store = CurDAG->getMachineNode(P->Pseudo, DL, Node->getValueType(0), Operands); + ReplaceNode(Node, Store); + return; + } + } + break; + } + case RISCVISD::VLSEGFF: { + SDLoc DL(Node); + unsigned IntNo = cast(Node->getOperand(1))->getZExtValue(); + unsigned NF = Node->getNumValues() - 2; + EVT VT = Node->getValueType(0); + unsigned ScalarSize = VT.getScalarSizeInBits(); + MVT XLenVT = Subtarget->getXLenVT(); + RISCVVLMUL LMUL = getLMUL(VT); + SDValue SEW = CurDAG->getTargetConstant(ScalarSize, DL, XLenVT); + SmallVector Operands; + Operands.push_back(Node->getOperand(2)); + Operands.push_back(Node->getOperand(3)); + Operands.push_back(SEW); + Operands.push_back(Node->getOperand(0)); + const RISCVZvlssegTable::RISCVZvlsseg *P = RISCVZvlssegTable::getPseudo(IntNo, ScalarSize, static_cast(LMUL), static_cast(RISCVVLMUL::LMUL_1)); + SDNode *Load = CurDAG->getMachineNode(P->Pseudo, DL, MVT::Untyped, MVT::Other, MVT::Glue, Operands); + SDValue SuperReg = SDValue(Load, 0); + for (unsigned I = 0; I < NF; ++I) + ReplaceUses(SDValue(Node, I), CurDAG->getTargetExtractSubreg(getSubregIndexByEVT(VT, I), DL, VT, SuperReg)); + ReplaceUses(SDValue(Node, NF), SDValue(Load, 1)); + ReplaceUses(SDValue(Node, NF + 1), SDValue(Load, 2)); + CurDAG->RemoveDeadNode(Node); + return; + } + case RISCVISD::VLSEGFF_MASK: { + SDLoc DL(Node); + unsigned IntNo = cast(Node->getOperand(1))->getZExtValue(); + unsigned NF = Node->getNumValues() - 2; + EVT VT = Node->getValueType(0); + unsigned ScalarSize = VT.getScalarSizeInBits(); + MVT XLenVT = Subtarget->getXLenVT(); + RISCVVLMUL LMUL = getLMUL(VT); + SDValue SEW = CurDAG->getTargetConstant(ScalarSize, DL, XLenVT); + SmallVector Regs(Node->op_begin() + 2, Node->op_begin() + 2 + NF); + SDValue MaskedOff = createTuple(*CurDAG, Regs, NF, LMUL); + SmallVector Operands; + Operands.push_back(MaskedOff); + Operands.push_back(Node->getOperand(NF + 2)); + Operands.push_back(Node->getOperand(NF + 3)); + Operands.push_back(Node->getOperand(NF + 4)); + Operands.push_back(SEW); + Operands.push_back(Node->getOperand(0)); + const RISCVZvlssegTable::RISCVZvlsseg *P = RISCVZvlssegTable::getPseudo(IntNo, ScalarSize, static_cast(LMUL), static_cast(RISCVVLMUL::LMUL_1)); + SDNode *Load = CurDAG->getMachineNode(P->Pseudo, DL, MVT::Untyped, MVT::Other, MVT::Glue, Operands); + SDValue SuperReg = SDValue(Load, 0); + for (unsigned I = 0; I < NF; ++I) + ReplaceUses(SDValue(Node, I), CurDAG->getTargetExtractSubreg(getSubregIndexByEVT(VT, I), DL, VT, SuperReg)); + ReplaceUses(SDValue(Node, NF), SDValue(Load, 1)); // Chain. + ReplaceUses(SDValue(Node, NF + 1), SDValue(Load, 2)); // Glue. + CurDAG->RemoveDeadNode(Node); + return; + } + case ISD::LOAD: { + LoadSDNode *Load = cast(Node); + if (Load->getAddressingMode() == ISD::UNINDEXED) + break; + SDValue Chain = Node->getOperand(0); + SDValue Base = Node->getOperand(1); + SDValue Offset = Node->getOperand(2); + bool simm12 = false; + bool signExtend = Load->getExtensionType() == ISD::SEXTLOAD; + if(auto ConstantOffset = dyn_cast(Offset)) { + int ConstantVal = ConstantOffset->getSExtValue(); + simm12 = isInt<12>(ConstantVal); + if (simm12) + Offset = CurDAG->getTargetConstant(ConstantVal, DL, Offset.getValueType()); + } + unsigned Opcode = 0; + switch (Load->getMemoryVT().getSimpleVT().SimpleTy) { + case MVT::i8: + if ( simm12 && signExtend) Opcode = RISCV::P_LB_ri_PostIncrement; + else if ( simm12 && !signExtend) Opcode = RISCV::P_LBU_ri_PostIncrement; + else if (!simm12 && signExtend) Opcode = RISCV::P_LB_rr_PostIncrement; + else Opcode = RISCV::P_LBU_rr_PostIncrement; + break; + case MVT::i16: + if ( simm12 && signExtend) Opcode = RISCV::P_LH_ri_PostIncrement; + else if ( simm12 && !signExtend) Opcode = RISCV::P_LHU_ri_PostIncrement; + else if (!simm12 && signExtend) Opcode = RISCV::P_LH_rr_PostIncrement; + else Opcode = RISCV::P_LHU_rr_PostIncrement; + break; + case MVT::i32: + if (simm12) Opcode = RISCV::P_LW_ri_PostIncrement; + else Opcode = RISCV::P_LW_rr_PostIncrement; + default: break; + } + if (!Opcode) break; + ReplaceNode(Node, CurDAG->getMachineNode(Opcode, DL, MVT::i32, MVT::i32, Chain.getSimpleValueType(), Base, Offset, Chain)); + return; + } + case ISD::VECTOR_SHUFFLE: { + ShuffleVectorSDNode *Shuffle = cast(Node); + SDValue Vec0 = Shuffle->getOperand(0); + SDValue Vec1 = Shuffle->getOperand(1); + unsigned Opcode; + int imm; + if (Vec1->getOpcode() == ISD::UNDEF) { + if (VT == MVT::v2i16) { + Opcode = RISCV::PV_SHUFFLE_SCI_H; + imm = (Shuffle->getMaskElt(1) & 1) << 1; + imm |= Shuffle->getMaskElt(0) & 1; + } + else { + switch (Shuffle->getMaskElt(3)) { + default: + case 0: Opcode = RISCV::PV_SHUFFLEI0_SCI_B; break; + case 1: Opcode = RISCV::PV_SHUFFLEI1_SCI_B; break; + case 2: Opcode = RISCV::PV_SHUFFLEI2_SCI_B; break; + case 3: Opcode = RISCV::PV_SHUFFLEI3_SCI_B; break; + } + imm = (Shuffle->getMaskElt(2) & 3) << 4; + imm |= (Shuffle->getMaskElt(1) & 3) << 2; + imm |= Shuffle->getMaskElt(0) & 3; + } + SDValue Imm = CurDAG->getTargetConstant(imm, SDLoc(Node), MVT::i32); + ReplaceNode(Node, CurDAG->getMachineNode(Opcode, DL, VT, Vec0, Imm)); + return; + } + if (VT == MVT::v2i16) { + Opcode = RISCV::PV_SHUFFLE2_H; + imm = (Shuffle->getMaskElt(1) & 1) << 16; + imm |= Shuffle->getMaskElt(0) & 1; + } + else { + Opcode = RISCV::PV_SHUFFLE2_B; + imm = (Shuffle->getMaskElt(3) & 3) << 24; + imm |= (Shuffle->getMaskElt(2) & 3) << 16; + imm |= (Shuffle->getMaskElt(1) & 3) << 8; + imm |= Shuffle->getMaskElt(0) & 3; + } + SDValue Imm = SDValue(selectImm(CurDAG, DL, imm, MVT::i32), 0); + ReplaceNode(Node, CurDAG->getMachineNode(Opcode, DL, VT, Vec0, Vec1, Imm)); + return; + } + } + SelectCode(Node); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelDAGToDAG/SelectAddrFI.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelDAGToDAG/SelectAddrFI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9379dd240442854fd152c1a8fed8a2b885473a0e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelDAGToDAG/SelectAddrFI.cpp @@ -0,0 +1,7 @@ +bool RISCVDAGToDAGISel::SelectAddrFI(SDValue Addr, SDValue &Base) { + if (auto FIN = dyn_cast(Addr)) { + Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), Subtarget->getXLenVT()); + return true; + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelDAGToDAG/SelectInlineAsmMemoryOperand.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelDAGToDAG/SelectInlineAsmMemoryOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..165beb5cae4ca44de1b3b5882179fb69421c957b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelDAGToDAG/SelectInlineAsmMemoryOperand.cpp @@ -0,0 +1,13 @@ +bool RISCVDAGToDAGISel::SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, std::vector &OutOps) { + switch (ConstraintID) { + case InlineAsm::Constraint_m: + OutOps.push_back(Op); + return false; + case InlineAsm::Constraint_A: + OutOps.push_back(Op); + return false; + default: + break; + } + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelDAGToDAG/createISelDag.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelDAGToDAG/createISelDag.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c6275786f621741ef641c1c9653dfc8c1c5fb094 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelDAGToDAG/createISelDag.cpp @@ -0,0 +1,3 @@ +FunctionPass *llvm::createRISCVISelDag(RISCVTargetMachine &TM) { + return new RISCVDAGToDAGISel(TM); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelDAGToDAG/getPassName.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelDAGToDAG/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b96cb682522bb4d42ce3557a54892030e1538f48 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelDAGToDAG/getPassName.cpp @@ -0,0 +1,3 @@ +StringRef getPassName() const override { + return "RISCV DAG->DAG Pattern Instruction Selection"; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelDAGToDAG/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelDAGToDAG/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5777ae33b7d6e056d8705bec6b95c6237351d2ce --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelDAGToDAG/runOnMachineFunction.cpp @@ -0,0 +1,4 @@ +bool runOnMachineFunction(MachineFunction &MF) override { + Subtarget = &MF.getSubtarget(); + return SelectionDAGISel::runOnMachineFunction(MF); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelDAGToDAG/selectVLOp.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelDAGToDAG/selectVLOp.cpp new file mode 100644 index 0000000000000000000000000000000000000000..02f2a0b029e45085011587a91e97581811fcfce9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelDAGToDAG/selectVLOp.cpp @@ -0,0 +1,22 @@ +bool RISCVDAGToDAGISel::selectVLOp(SDValue N, SDValue &VL) { + auto *C = dyn_cast(N); + if (C && C->isNullValue()) { + RISCVMatInt::InstSeq Seq; + RISCVMatInt::generateInstSeq(Imm, XLenVT == MVT::i64, Seq); + SDNode *Result = nullptr; + SDValue SrcReg = CurDAG->getRegister(RISCV::X0, XLenVT); + for (RISCVMatInt::Inst &Inst : Seq) { + SDValue SDImm = CurDAG->getTargetConstant(Inst.Imm, DL, XLenVT); + if (Inst.Opc == RISCV::LUI) + Result = CurDAG->getMachineNode(RISCV::LUI, DL, XLenVT, SDImm); + else + Result = CurDAG->getMachineNode(Inst.Opc, DL, XLenVT, SrcReg, SDImm); + SrcReg = SDValue(Result, 0); + } + VL = SDValue(selectImm(CurDAG, SDLoc(N), 0, Subtarget->getXLenVT()), 0); + } + else { + VL = N; + } + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelDAGToDAG/selectVSplat.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelDAGToDAG/selectVSplat.cpp new file mode 100644 index 0000000000000000000000000000000000000000..500365156eb27b9ec53e3c54d7bd31402e02bb80 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelDAGToDAG/selectVSplat.cpp @@ -0,0 +1,7 @@ +bool RISCVDAGToDAGISel::selectVSplat(SDValue N, SDValue &SplatVal) { + if (N.getOpcode() != ISD::SPLAT_VECTOR && N.getOpcode() != RISCVISD::SPLAT_VECTOR_I64) { + return false; + } + SplatVal = N.getOperand(0); + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelDAGToDAG/selectVSplatSimm5.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelDAGToDAG/selectVSplatSimm5.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3f19416c4249c3fa0ba66fedcff7a3e7eb734fdb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelDAGToDAG/selectVSplatSimm5.cpp @@ -0,0 +1,17 @@ +bool RISCVDAGToDAGISel::selectVSplatSimm5(SDValue N, SDValue &SplatVal) { + if ((N.getOpcode() != ISD::SPLAT_VECTOR && N.getOpcode() != RISCVISD::SPLAT_VECTOR_I64) || !isa(N.getOperand(0))) { + return false; + } + int64_t SplatImm = cast(N.getOperand(0))->getSExtValue(); + auto XLenVT = Subtarget->getXLenVT(); + assert(XLenVT == N.getOperand(0).getSimpleValueType() && "Unexpected splat operand type"); + auto EltVT = N.getValueType().getVectorElementType(); + if (EltVT.bitsLT(XLenVT)) { + SplatImm = SignExtend64(SplatImm, EltVT.getSizeInBits()); + } + if (!isInt<5>(SplatImm)) { + return false; + } + SplatVal = CurDAG->getTargetConstant(SplatImm, SDLoc(N), XLenVT); + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelDAGToDAG/selectVSplatUimm5.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelDAGToDAG/selectVSplatUimm5.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bdff0c6f5dc1586897ad9c7787e6a82ee582e996 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelDAGToDAG/selectVSplatUimm5.cpp @@ -0,0 +1,11 @@ +bool RISCVDAGToDAGISel::selectVSplatUimm5(SDValue N, SDValue &SplatVal) { + if ((N.getOpcode() != ISD::SPLAT_VECTOR && N.getOpcode() != RISCVISD::SPLAT_VECTOR_I64) || !isa(N.getOperand(0))) { + return false; + } + int64_t SplatImm = cast(N.getOperand(0))->getSExtValue(); + if (!isUInt<5>(SplatImm)) { + return false; + } + SplatVal = CurDAG->getTargetConstant(SplatImm, SDLoc(N), Subtarget->getXLenVT()); + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/CanLowerReturn.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/CanLowerReturn.cpp new file mode 100644 index 0000000000000000000000000000000000000000..313f69ae69dddca02aef0b43936b47304afc7ae2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/CanLowerReturn.cpp @@ -0,0 +1,171 @@ +bool RISCVTargetLowering::CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg, const SmallVectorImpl &Outs, LLVMContext &Context) const { + SmallVector RVLocs; + CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context); + Optional FirstMaskArgument; + if (Subtarget.hasStdExtV()) { + for (const auto &ArgIdx : enumerate(Args)) { + MVT ArgVT = ArgIdx.value().VT; + if (ArgVT.isScalableVector() && ArgVT.getVectorElementType().SimpleTy == MVT::i1) + return ArgIdx.index(); + } + return None; + } + for (unsigned i = 0, e = Outs.size(); i != e; ++i) { + MVT VT = Outs[i].VT; + ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; + RISCVABI::ABI ABI = MF.getSubtarget().getTargetABI(); + unsigned XLen = DL.getLargestLegalIntTypeSizeInBits(); + assert(XLen == 32 || XLen == 64); + MVT XLenVT = XLen == 32 ? MVT::i32 : MVT::i64; + if (IsRet && ValNo > 1) + return true; + bool UseGPRForF16_F32 = true; + bool UseGPRForF64 = true; + switch (ABI) { + default: + llvm_unreachable("Unexpected ABI"); + case RISCVABI::ABI_ILP32: + case RISCVABI::ABI_LP64: + break; + case RISCVABI::ABI_ILP32F: + case RISCVABI::ABI_LP64F: + UseGPRForF16_F32 = !IsFixed; + break; + case RISCVABI::ABI_ILP32D: + case RISCVABI::ABI_LP64D: + UseGPRForF16_F32 = !IsFixed; + UseGPRForF64 = !IsFixed; + break; + } + if (State.getFirstUnallocated(ArgFPR32s) == array_lengthof(ArgFPR32s)) { + UseGPRForF16_F32 = true; + UseGPRForF64 = true; + } + if (UseGPRForF16_F32 && (ValVT == MVT::f16 || ValVT == MVT::f32)) { + LocVT = XLenVT; + LocInfo = CCValAssign::BCvt; + } + else if (UseGPRForF64 && XLen == 64 && ValVT == MVT::f64) { + LocVT = MVT::i64; + LocInfo = CCValAssign::BCvt; + } + unsigned TwoXLenInBytes = (2 * XLen) / 8; + if (!IsFixed && ArgFlags.getNonZeroOrigAlign() == TwoXLenInBytes && DL.getTypeAllocSize(OrigTy) == TwoXLenInBytes) { + unsigned RegIdx = State.getFirstUnallocated(ArgGPRs); + if (RegIdx != array_lengthof(ArgGPRs) && RegIdx % 2 == 1) + State.AllocateReg(ArgGPRs); + } + SmallVectorImpl &PendingLocs = State.getPendingLocs(); + SmallVectorImpl &PendingArgFlags = State.getPendingArgFlags(); + assert(PendingLocs.size() == PendingArgFlags.size() && "PendingLocs and PendingArgFlags out of sync"); + if (UseGPRForF64 && XLen == 32 && ValVT == MVT::f64) { + assert(!ArgFlags.isSplit() && PendingLocs.empty() && "Can't lower f64 if it is split"); + Register Reg = State.AllocateReg(ArgGPRs); + LocVT = MVT::i32; + if (!Reg) { + unsigned StackOffset = State.AllocateStack(8, Align(8)); + State.addLoc(CCValAssign::getMem(ValNo, ValVT, StackOffset, LocVT, LocInfo)); + return false; + } + if (!State.AllocateReg(ArgGPRs)) + State.AllocateStack(4, Align(4)); + State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); + return false; + } + if (ArgFlags.isSplit() || !PendingLocs.empty()) { + LocVT = XLenVT; + LocInfo = CCValAssign::Indirect; + PendingLocs.push_back(CCValAssign::getPending(ValNo, ValVT, LocVT, LocInfo)); + PendingArgFlags.push_back(ArgFlags); + if (!ArgFlags.isSplitEnd()) { + return false; + } + } + if (ArgFlags.isSplitEnd() && PendingLocs.size() <= 2) { + assert(PendingLocs.size() == 2 && "Unexpected PendingLocs.size()"); + CCValAssign VA = PendingLocs[0]; + ISD::ArgFlagsTy AF = PendingArgFlags[0]; + PendingLocs.clear(); + PendingArgFlags.clear(); + unsigned XLenInBytes = XLen / 8; + if (Register Reg = State.AllocateReg(ArgGPRs)) { + State.addLoc(CCValAssign::getReg(VA1.getValNo(), VA1.getValVT(), Reg, VA1.getLocVT(), CCValAssign::Full)); + } else { + Align StackAlign = std::max(Align(XLenInBytes), ArgFlags1.getNonZeroOrigAlign()); + State.addLoc(CCValAssign::getMem(VA1.getValNo(), VA1.getValVT(), State.AllocateStack(XLenInBytes, StackAlign), VA1.getLocVT(), CCValAssign::Full)); + State.addLoc(CCValAssign::getMem(ValNo2, ValVT2, State.AllocateStack(XLenInBytes, Align(XLenInBytes)), LocVT2, CCValAssign::Full)); + return false; + } + if (Register Reg = State.AllocateReg(ArgGPRs)) { + State.addLoc(CCValAssign::getReg(ValNo2, ValVT2, Reg, LocVT2, CCValAssign::Full)); + } + else { + State.addLoc(CCValAssign::getMem(ValNo2, ValVT2, State.AllocateStack(XLenInBytes, Align(XLenInBytes)), LocVT2, CCValAssign::Full)); + } + return false; + } + Register Reg; + if (ValVT == MVT::f16 && !UseGPRForF16_F32) + Reg = State.AllocateReg(ArgFPR16s); + else if (ValVT == MVT::f32 && !UseGPRForF16_F32) + Reg = State.AllocateReg(ArgFPR32s); + else if (ValVT == MVT::f64 && !UseGPRForF64) + Reg = State.AllocateReg(ArgFPR64s); + else if (ValVT.isScalableVector()) { + const TargetRegisterClass *RC = TLI.getRegClassFor(ValVT); + if (RC == &RISCV::VRRegClass) { + if (FirstMaskArgument.hasValue() && ValNo == FirstMaskArgument.getValue()) { + Reg = State.AllocateReg(RISCV::V0); + } + else { + Reg = State.AllocateReg(ArgVRs); + } + } + else if (RC == &RISCV::VRM2RegClass) { + Reg = State.AllocateReg(ArgVRM2s); + } + else if (RC == &RISCV::VRM4RegClass) { + Reg = State.AllocateReg(ArgVRM4s); + } + else if (RC == &RISCV::VRM8RegClass) { + Reg = State.AllocateReg(ArgVRM8s); + } + else { + llvm_unreachable("Unhandled class register for ValueType"); + } + if (!Reg) { + LocInfo = CCValAssign::Indirect; + Reg = State.AllocateReg(ArgGPRs); + LocVT = XLenVT; + } + } else + Reg = State.AllocateReg(ArgGPRs); + unsigned StackOffset = Reg ? 0 : State.AllocateStack(XLen / 8, Align(XLen / 8)); + if (!PendingLocs.empty()) { + assert(ArgFlags.isSplitEnd() && "Expected ArgFlags.isSplitEnd()"); + assert(PendingLocs.size() > 2 && "Unexpected PendingLocs.size()"); + for (auto &It : PendingLocs) { + if (Reg) + It.convertToReg(Reg); + else + It.convertToMem(StackOffset); + State.addLoc(It); + } + PendingLocs.clear(); + PendingArgFlags.clear(); + return false; + } + assert((!UseGPRForF16_F32 || !UseGPRForF64 || LocVT == XLenVT || (TLI.getSubtarget().hasStdExtV() && ValVT.isScalableVector())) && "Expected an XLenVT or scalable vector types at this stage"); + if (Reg) { + State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); + return false; + } + if (ValVT.isFloatingPoint()) { + LocVT = ValVT; + LocInfo = CCValAssign::Full; + } + State.addLoc(CCValAssign::getMem(ValNo, ValVT, StackOffset, LocVT, LocInfo)); + return false; + } + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/ComputeNumSignBitsForTargetNode.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/ComputeNumSignBitsForTargetNode.cpp new file mode 100644 index 0000000000000000000000000000000000000000..63f9dcd4bfa99711bec59e8db8683e30194ac2a1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/ComputeNumSignBitsForTargetNode.cpp @@ -0,0 +1,45 @@ +unsigned RISCVTargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const { + if (Op.getOpcode() == RISCVISD::SLLW) { + return Op.getScalarValueSizeInBits(); + } + if (Op.getOpcode() == RISCVISD::SRAW) { + return Op.getScalarValueSizeInBits(); + } + if (Op.getOpcode() == RISCVISD::SRLW) { + return 33; + } + if (Op.getOpcode() == RISCVISD::DIVW) { + return 33; + } + if (Op.getOpcode() == RISCVISD::DIVUW) { + return 33; + } + if (Op.getOpcode() == RISCVISD::REMUW) { + return 33; + } + if (Op.getOpcode() == RISCVISD::ROLW) { + return 33; + } + if (Op.getOpcode() == RISCVISD::RORW) { + return 33; + } + if (Op.getOpcode() == RISCVISD::GREVIW) { + return 33; + } + if (Op.getOpcode() == RISCVISD::GORCIW) { + return 33; + } + if (Op.getOpcode() == RISCVISD::FSLW) { + return 33; + } + if (Op.getOpcode() == RISCVISD::FSRW) { + return 33; + } + if (Op.getOpcode() == RISCVISD::VMV_X_S) { + if (Op.getOperand(0).getScalarValueSizeInBits() > Subtarget.getXLen()) { + return 1; + } + return Subtarget.getXLen() - Op.getOperand(0).getScalarValueSizeInBits() + 1; + } + return 1; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/EmitInstrWithCustomInserter.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/EmitInstrWithCustomInserter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..78f8c6ed2abbddd3aa2e311bcd887beaf74bc0ea --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/EmitInstrWithCustomInserter.cpp @@ -0,0 +1,165 @@ +MachineBasicBlock *RISCVTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const { + uint64_t TSFlags = MI.getDesc().TSFlags; + if (TSFlags & RISCVII::HasSEWOpMask) { + unsigned NumOperands = MI.getNumExplicitOperands(); + int VLIndex = (TSFlags & RISCVII::HasVLOpMask) ? NumOperands - 2 : -1; + unsigned SEWIndex = NumOperands - 1; + bool WritesElement0 = TSFlags & RISCVII::WritesElement0Mask; + RISCVVLMUL VLMul = static_cast((TSFlags & RISCVII::VLMulMask) >> RISCVII::VLMulShift); + MachineFunction &MF = *BB->getParent(); + DebugLoc DL = MI.getDebugLoc(); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); + unsigned SEW = MI.getOperand(SEWIndex).getImm(); + assert(RISCVVType::isValidSEW(SEW) && "Unexpected SEW"); + RISCVVSEW ElementWidth = static_cast(Log2_32(SEW / 8)); + MachineRegisterInfo &MRI = MF.getRegInfo(); + MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, TII.get(RISCV::PseudoVSETVLI)); + if (VLIndex >= 0) { + Register DestReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); + MIB.addReg(DestReg, RegState::Define | RegState::Dead).addReg(MI.getOperand(VLIndex).getReg()); + } + else + MIB.addReg(RISCV::X0, RegState::Define | RegState::Dead).addReg(RISCV::X0, RegState::Kill); + bool TailAgnostic = true; + unsigned UseOpIdx; + if (MI.isRegTiedToUseOperand(0, &UseOpIdx) && !WritesElement0) { + TailAgnostic = false; + const MachineOperand &UseMO = MI.getOperand(UseOpIdx); + MachineInstr *UseMI = MRI.getVRegDef(UseMO.getReg()); + if (UseMI && UseMI->isImplicitDef()) + TailAgnostic = true; + } + unsigned VLMULBits = static_cast(VLMUL); + unsigned VSEWBits = static_cast(VSEW); + unsigned VTypeI = (VSEWBits << 3) | (VLMULBits & 0x7); + if (TailAgnostic) + VTypeI |= 0x40; + if (MaskAgnostic) + VTypeI |= 0x80; + MIB.addImm(RISCVVType::encodeVTYPE(VLMul, ElementWidth, TailAgnostic, false)); + MI.getOperand(SEWIndex).setImm(-1); + if (VLIndex >= 0) { + MI.getOperand(VLIndex).setReg(RISCV::NoRegister); + MI.getOperand(VLIndex).setIsKill(false); + } + } + switch (MI.getOpcode()) { + default: + llvm_unreachable("Unexpected instr type to insert"); + case RISCV::ReadCycleWide: + assert(!Subtarget.is64Bit() && "ReadCycleWrite is only to be used on riscv32"); + assert(MI.getOpcode() == RISCV::ReadCycleWide && "Unexpected instruction"); + MachineFunction &MF = *BB->getParent(); + const BasicBlock *LLVM_BB = BB->getBasicBlock(); + MachineFunction::iterator It = ++BB->getIterator(); + MachineBasicBlock *LoopMBB = MF.CreateMachineBasicBlock(LLVM_BB); + MF.insert(It, LoopMBB); + MachineBasicBlock *DoneMBB = MF.CreateMachineBasicBlock(LLVM_BB); + MF.insert(It, DoneMBB); + DoneMBB->splice(DoneMBB->begin(), BB, std::next(MachineBasicBlock::iterator(MI)), BB->end()); + DoneMBB->transferSuccessorsAndUpdatePHIs(BB); + BB->addSuccessor(LoopMBB); + MachineRegisterInfo &RegInfo = MF.getRegInfo(); + Register ReadAgainReg = RegInfo.createVirtualRegister(&RISCV::GPRRegClass); + Register LoReg = MI.getOperand(0).getReg(); + Register HiReg = MI.getOperand(1).getReg(); + DebugLoc DL = MI.getDebugLoc(); + const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo(); + BuildMI(LoopMBB, DL, TII->get(RISCV::CSRRS), HiReg).addImm(RISCVSysReg::lookupSysRegByName("CYCLEH")->Encoding).addReg(RISCV::X0); + BuildMI(LoopMBB, DL, TII->get(RISCV::CSRRS), LoReg).addImm(RISCVSysReg::lookupSysRegByName("CYCLE")->Encoding).addReg(RISCV::X0); + BuildMI(LoopMBB, DL, TII->get(RISCV::CSRRS), ReadAgainReg).addImm(RISCVSysReg::lookupSysRegByName("CYCLEH")->Encoding).addReg(RISCV::X0); + BuildMI(LoopMBB, DL, TII->get(RISCV::BNE)).addReg(HiReg).addReg(ReadAgainReg).addMBB(LoopMBB); + LoopMBB->addSuccessor(LoopMBB); + LoopMBB->addSuccessor(DoneMBB); + MI.eraseFromParent(); + return DoneMBB; + case RISCV::Select_GPR_Using_CC_GPR: + case RISCV::Select_FPR16_Using_CC_GPR: + case RISCV::Select_FPR32_Using_CC_GPR: + case RISCV::Select_FPR64_Using_CC_GPR: + and(2).getReg() != RHS || SequenceMBBI->getOperand(3).getImm() != CC || SelectDests.count(SequenceMBBI->getOperand(4).getReg()) || SelectDests.count(SequenceMBBI->getOperand(5).getReg())) + break; + LastSelectPseudo = &*SequenceMBBI; + SequenceMBBI->collectDebugValues(SelectDebugValues); + SelectDests.insert(SequenceMBBI->getOperand(0).getReg()); + else { + if (SequenceMBBI->hasUnmodeledSideEffects() || SequenceMBBI->mayLoadOrStore()) + break; + if (llvm::any_of(SequenceMBBI->operands(), [&](MachineOperand &MO) { + return MO.isReg() && MO.isUse() && SelectDests.count(MO.getReg()); + })) + break; + } + const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo(); + const BasicBlock *LLVM_BB = BB->getBasicBlock(); + DebugLoc DL = MI.getDebugLoc(); + MachineFunction::iterator I = ++BB->getIterator(); + MachineBasicBlock *HeadMBB = BB; + MachineFunction *F = BB->getParent(); + MachineBasicBlock *TailMBB = F->CreateMachineBasicBlock(LLVM_BB); + MachineBasicBlock *IfFalseMBB = F->CreateMachineBasicBlock(LLVM_BB); + F->insert(I, IfFalseMBB); + F->insert(I, TailMBB); + for (MachineInstr *DebugInstr : SelectDebugValues) { + TailMBB->push_back(DebugInstr->removeFromParent()); + } + TailMBB->splice(TailMBB->end(), HeadMBB, std::next(LastSelectPseudo->getIterator()), HeadMBB->end()); + TailMBB->transferSuccessorsAndUpdatePHIs(HeadMBB); + HeadMBB->addSuccessor(IfFalseMBB); + HeadMBB->addSuccessor(TailMBB); + unsigned Opcode = getBranchOpcodeForIntCondCode(CC); + BuildMI(HeadMBB, DL, TII.get(Opcode)).addReg(LHS).addReg(RHS).addMBB(TailMBB); + IfFalseMBB->addSuccessor(TailMBB); + auto SelectMBBI = MI.getIterator(); + auto SelectEnd = std::next(LastSelectPseudo->getIterator()); + auto InsertionPoint = TailMBB->begin(); + while (SelectMBBI != SelectEnd) { + auto Next = std::next(SelectMBBI); + if (isSelectPseudo(*SelectMBBI)) { + BuildMI(*TailMBB, InsertionPoint, SelectMBBI->getDebugLoc(), TII.get(RISCV::PHI), SelectMBBI->getOperand(0).getReg()).addReg(SelectMBBI->getOperand(4).getReg()).addMBB(HeadMBB).addReg(SelectMBBI->getOperand(5).getReg()).addMBB(IfFalseMBB); + SelectMBBI->eraseFromParent(); + } + SelectMBBI = Next; + } + F->getProperties().reset(MachineFunctionProperties::Property::NoPHIs); + return TailMBB; + case RISCV::BuildPairF64Pseudo: + assert(MI.getOpcode() == RISCV::BuildPairF64Pseudo && "Unexpected instruction"); + MachineFunction &MF = *BB->getParent(); + DebugLoc DL = MI.getDebugLoc(); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); + const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo(); + Register DstReg = MI.getOperand(0).getReg(); + Register LoReg = MI.getOperand(1).getReg(); + Register HiReg = MI.getOperand(2).getReg(); + const TargetRegisterClass *DstRC = &RISCV::FPR64RegClass; + int FI = MF.getInfo()->getMoveF64FrameIndex(MF); + MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(MF, FI); + MachineMemOperand *MMOLo = MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, Align(8)); + MachineMemOperand *MMOHi = MF.getMachineMemOperand(MPI.getWithOffset(4), MachineMemOperand::MOStore, 4, Align(8)); + BuildMI(*BB, MI, DL, TII.get(RISCV::SW)).addReg(LoReg, getKillRegState(MI.getOperand(1).isKill())).addFrameIndex(FI).addImm(0).addMemOperand(MMOLo); + BuildMI(*BB, MI, DL, TII.get(RISCV::SW)).addReg(HiReg, getKillRegState(MI.getOperand(2).isKill())).addFrameIndex(FI).addImm(4).addMemOperand(MMOHi); + TII.loadRegFromStackSlot(*BB, MI, DstReg, FI, DstRC, RI); + MI.eraseFromParent(); + return BB; + case RISCV::SplitF64Pseudo: + assert(MI.getOpcode() == RISCV::SplitF64Pseudo && "Unexpected instruction");= + MachineFunction &MF = *BB->getParent(); + DebugLoc DL = MI.getDebugLoc(); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); + const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo(); + Register LoReg = MI.getOperand(0).getReg(); + Register HiReg = MI.getOperand(1).getReg(); + Register SrcReg = MI.getOperand(2).getReg(); + const TargetRegisterClass *SrcRC = &RISCV::FPR64RegClass; + int FI = MF.getInfo()->getMoveF64FrameIndex(MF); + TII.storeRegToStackSlot(*BB, MI, SrcReg, MI.getOperand(2).isKill(), FI, SrcRC, RI); + MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(MF, FI); + MachineMemOperand *MMOLo = MF.getMachineMemOperand(MPI, MachineMemOperand::MOLoad, 4, Align(8)); + MachineMemOperand *MMOHi = MF.getMachineMemOperand( PI.getWithOffset(4), MachineMemOperand::MOLoad, 4, Align(8)); + BuildMI(*BB, MI, DL, TII.get(RISCV::LW), LoReg).addFrameIndex(FI).addImm(0).addMemOperand(MMOLo); + BuildMI(*BB, MI, DL, TII.get(RISCV::LW), HiReg).addFrameIndex(FI).addImm(4).addMemOperand(MMOHi); + MI.eraseFromParent(); + return BB; + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/LowerAsmOperandForConstraint.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/LowerAsmOperandForConstraint.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3120cdc9e0247fc2f5bbeaa81b831c974641b9fe --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/LowerAsmOperandForConstraint.cpp @@ -0,0 +1,34 @@ +void RISCVTargetLowering::LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector &Ops, SelectionDAG &DAG) const { + SDLoc DL(Op); + MVT XLenVT = Subtarget.getXLenVT(); + if (Constraint.length() == 1) { + if (Constraint[0] == 'I') { + if (auto *C = dyn_cast(Op)) { + uint64_t Val = C->getSExtValue(); + if (isInt<12>(Val)) { + Ops.push_back(DAG.getTargetConstant(Val, DL, XLenVT)); + } + } + return ; + } + if (Constraint[0] == 'J') { + if (auto *C = dyn_cast(Op)) { + uint64_t Val = C->getSExtValue(); + if (Val == 0) { + Ops.push_back(DAG.getTargetConstant(0, DL, XLenVT)); + } + } + return ; + } + if (Constraint[0] == 'K') { + if (auto *C = dyn_cast(Op)) { + uint64_t Val = C->getSExtValue(); + if (isUInt<5>(Val)) { + Ops.push_back(DAG.getTargetConstant(Val, DL, XLenVT)); + } + } + return ; + } + } + TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/LowerBlockAddress.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/LowerBlockAddress.cpp new file mode 100644 index 0000000000000000000000000000000000000000..97d4a427e101d5f49d5240064ece9c020a72ab75 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/LowerBlockAddress.cpp @@ -0,0 +1,4 @@ +SDValue RISCVTargetLowering::lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const { + BlockAddressSDNode *N = cast(Op); + return getAddr(N, DAG); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/LowerCall.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/LowerCall.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7af74735e1d7dc1c5b685944c4694f244897d869 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/LowerCall.cpp @@ -0,0 +1,197 @@ +SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI, SmallVectorImpl &InVals) const { + SelectionDAG &DAG = CLI.DAG; + SDLoc &DL = CLI.DL; + SmallVectorImpl &Outs = CLI.Outs; + SmallVectorImpl &OutVals = CLI.OutVals; + SmallVectorImpl &Ins = CLI.Ins; + SDValue Chain = CLI.Chain; + SDValue Callee = CLI.Callee; + bool &IsTailCall = CLI.IsTailCall; + CallingConv::ID CallConv = CLI.CallConv; + bool IsVarArg = CLI.IsVarArg; + EVT PtrVT = getPointerTy(DAG.getDataLayout()); + MVT XLenVT = Subtarget.getXLenVT(); + MachineFunction &MF = DAG.getMachineFunction(); + SmallVector ArgLocs; + CCState ArgCCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext()); + if (CallConv == CallingConv::Fast) + ArgCCInfo.AnalyzeCallOperands(Outs, CC_RISCV_FastCC); + else if (CallConv == CallingConv::GHC) + ArgCCInfo.AnalyzeCallOperands(Outs, CC_RISCV_GHC); + else + analyzeOutputArgs(MF, ArgCCInfo, Outs, false, &CLI); + if (IsTailCall) + IsTailCall = isEligibleForTailCallOptimization(ArgCCInfo, CLI, MF, ArgLocs); + if (IsTailCall) + ++NumTailCalls; + else if (CLI.CB && CLI.CB->isMustTailCall()) + report_fatal_error("failed to perform tail call elimination on a call site marked musttail"); + unsigned NumBytes = ArgCCInfo.getNextStackOffset(); + SmallVector ByValArgs; + for (unsigned i = 0, e = Outs.size(); i != e; ++i) { + ISD::ArgFlagsTy Flags = Outs[i].Flags; + if (!Flags.isByVal()) + continue; + SDValue Arg = OutVals[i]; + unsigned Size = Flags.getByValSize(); + Align Alignment = Flags.getNonZeroByValAlign(); + int FI = MF.getFrameInfo().CreateStackObject(Size, Alignment, false); + SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); + SDValue SizeNode = DAG.getConstant(Size, DL, XLenVT); + Chain = DAG.getMemcpy(Chain, DL, FIPtr, Arg, SizeNode, Alignment, false, false, IsTailCall, MachinePointerInfo(), MachinePointerInfo()); + ByValArgs.push_back(FIPtr); + } + if (!IsTailCall) + Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, CLI.DL); + SmallVector, 8> RegsToPass; + SmallVector MemOpChains; + SDValue StackPtr; + for (unsigned i = 0, j = 0, e = ArgLocs.size(); i != e; ++i) { + CCValAssign &VA = ArgLocs[i]; + SDValue ArgValue = OutVals[i]; + ISD::ArgFlagsTy Flags = Outs[i].Flags; + bool IsF64OnRV32DSoftABI = VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64; + if (IsF64OnRV32DSoftABI && VA.isRegLoc()) { + SDValue SplitF64 = DAG.getNode(RISCVISD::SplitF64, DL, DAG.getVTList(MVT::i32, MVT::i32), ArgValue); + SDValue Lo = SplitF64.getValue(0); + SDValue Hi = SplitF64.getValue(1); + Register RegLo = VA.getLocReg(); + RegsToPass.push_back(std::make_pair(RegLo, Lo)); + if (RegLo == RISCV::X17) { + if (!StackPtr.getNode()) + StackPtr = DAG.getCopyFromReg(Chain, DL, RISCV::X2, PtrVT); + MemOpChains.push_back(DAG.getStore(Chain, DL, Hi, StackPtr, MachinePointerInfo())); + } + else { + assert(RegLo < RISCV::X31 && "Invalid register pair"); + Register RegHigh = RegLo + 1; + RegsToPass.push_back(std::make_pair(RegHigh, Hi)); + } + continue; + } + if (VA.getLocInfo() == CCValAssign::Indirect) { + SDValue SpillSlot = DAG.CreateStackTemporary(Outs[i].ArgVT); + int FI = cast(SpillSlot)->getIndex(); + MemOpChains.push_back(DAG.getStore(Chain, DL, ArgValue, SpillSlot, MachinePointerInfo::getFixedStack(MF, FI))); + unsigned ArgIndex = Outs[i].OrigArgIndex; + assert(Outs[i].PartOffset == 0); + while (i + 1 != e && Outs[i + 1].OrigArgIndex == ArgIndex) { + SDValue PartValue = OutVals[i + 1]; + unsigned PartOffset = Outs[i + 1].PartOffset; + SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, SpillSlot, DAG.getIntPtrConstant(PartOffset, DL)); + MemOpChains.push_back(DAG.getStore(Chain, DL, PartValue, Address, MachinePointerInfo::getFixedStack(MF, FI))); + ++i; + } + ArgValue = SpillSlot; + } + else { + EVT LocVT = VA.getLocVT(); + switch (VA.getLocInfo()) { + default: + llvm_unreachable("Unexpected CCValAssign::LocInfo"); + case CCValAssign::Full: + break; + case CCValAssign::BCvt: + if (VA.getLocVT().isInteger() && VA.getValVT() == MVT::f16) + Val = DAG.getNode(RISCVISD::FMV_X_ANYEXTH, DL, VA.getLocVT(), Val); + else if (VA.getLocVT() == MVT::i64 && VA.getValVT() == MVT::f32) + Val = DAG.getNode(RISCVISD::FMV_X_ANYEXTW_RV64, DL, MVT::i64, Val); + else + Val = DAG.getNode(ISD::BITCAST, DL, LocVT, Val); + break; + } + ArgValue = Val; + } + if (Flags.isByVal()) + ArgValue = ByValArgs[j++]; + if (VA.isRegLoc()) { + RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue)); + } + else { + assert(VA.isMemLoc() && "Argument not register or memory"); + assert(!IsTailCall && "Tail call not allowed if stack is used for passing parameters"); + if (!StackPtr.getNode()) + StackPtr = DAG.getCopyFromReg(Chain, DL, RISCV::X2, PtrVT); + SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, DAG.getIntPtrConstant(VA.getLocMemOffset(), DL)); + MemOpChains.push_back(DAG.getStore(Chain, DL, ArgValue, Address, MachinePointerInfo())); + } + } + if (!MemOpChains.empty()) + Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains); + SDValue Glue; + for (auto &Reg : RegsToPass) { + Chain = DAG.getCopyToReg(Chain, DL, Reg.first, Reg.second, Glue); + Glue = Chain.getValue(1); + } + validateCCReservedRegs(RegsToPass, MF); + if (!IsTailCall && MF.getSubtarget().isRegisterReservedByUser(RISCV::X1)) + MF.getFunction().getContext().diagnose(DiagnosticInfoUnsupported{MF.getFunction(), "Return address register required, but has been reserved."}); + if (GlobalAddressSDNode *S = dyn_cast(Callee)) { + const GlobalValue *GV = S->getGlobal(); + unsigned OpFlags = RISCVII::MO_CALL; + if (!getTargetMachine().shouldAssumeDSOLocal(*GV->getParent(), GV)) + OpFlags = RISCVII::MO_PLT; + Callee = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, OpFlags); + } + else if (ExternalSymbolSDNode *S = dyn_cast(Callee)) { + unsigned OpFlags = RISCVII::MO_CALL; + if (!getTargetMachine().shouldAssumeDSOLocal(*MF.getFunction().getParent(), nullptr)) + OpFlags = RISCVII::MO_PLT; + Callee = DAG.getTargetExternalSymbol(S->getSymbol(), PtrVT, OpFlags); + } + SmallVector Ops; + Ops.push_back(Chain); + Ops.push_back(Callee); + for (auto &Reg : RegsToPass) + Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType())); + if (!IsTailCall) { + const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); + const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv); + assert(Mask && "Missing call preserved mask for calling convention"); + Ops.push_back(DAG.getRegisterMask(Mask)); + } + if (Glue.getNode()) + Ops.push_back(Glue); + SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); + if (IsTailCall) { + MF.getFrameInfo().setHasTailCall(); + return DAG.getNode(RISCVISD::TAIL, DL, NodeTys, Ops); + } + Chain = DAG.getNode(RISCVISD::CALL, DL, NodeTys, Ops); + DAG.addNoMergeSiteInfo(Chain.getNode(), CLI.NoMerge); + Glue = Chain.getValue(1); + Chain = DAG.getCALLSEQ_END(Chain, DAG.getConstant(NumBytes, DL, PtrVT, true), DAG.getConstant(0, DL, PtrVT, true), Glue, DL); + Glue = Chain.getValue(1); + SmallVector RVLocs; + CCState RetCCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext()); + analyzeInputArgs(MF, RetCCInfo, Ins, true); + for (auto &VA : RVLocs) { + SDValue RetValue = DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), Glue); + Chain = RetValue.getValue(1); + Glue = RetValue.getValue(2); + if (VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64) { + assert(VA.getLocReg() == ArgGPRs[0] && "Unexpected reg assignment"); + SDValue RetValue2 = DAG.getCopyFromReg(Chain, DL, ArgGPRs[1], MVT::i32, Glue); + Chain = RetValue2.getValue(1); + Glue = RetValue2.getValue(2); + RetValue = DAG.getNode(RISCVISD::BuildPairF64, DL, MVT::f64, RetValue, RetValue2); + } + switch (VA.getLocInfo()) { + default: + llvm_unreachable("Unexpected CCValAssign::LocInfo"); + case CCValAssign::Full: + break; + case CCValAssign::BCvt: + if (VA.getLocVT().isInteger() && VA.getValVT() == MVT::f16) + Val = DAG.getNode(RISCVISD::FMV_H_X, DL, MVT::f16, Val); + else if (VA.getLocVT() == MVT::i64 && VA.getValVT() == MVT::f32) + Val = DAG.getNode(RISCVISD::FMV_W_X_RV64, DL, MVT::f32, Val); + else + Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val); + break; + } + RetValue = Val; + InVals.push_back(RetValue); + } + return Chain; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/LowerConstantPool.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/LowerConstantPool.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8c2111e520eec0abbd9dce63ea31d3df135efd14 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/LowerConstantPool.cpp @@ -0,0 +1,4 @@ +SDValue RISCVTargetLowering::lowerConstantPool(SDValue Op, SelectionDAG &DAG) const { + ConstantPoolSDNode *N = cast(Op); + return getAddr(N, DAG); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/LowerFRAMEADDR.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/LowerFRAMEADDR.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7e10d42b15911726b9b98aaadba7f5bbd1bc60fd --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/LowerFRAMEADDR.cpp @@ -0,0 +1,18 @@ +SDValue RISCVTargetLowering::lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { + const RISCVRegisterInfo &RI = *Subtarget.getRegisterInfo(); + MachineFunction &MF = DAG.getMachineFunction(); + MachineFrameInfo &MFI = MF.getFrameInfo(); + MFI.setFrameAddressIsTaken(true); + Register FrameReg = RI.getFrameRegister(MF); + int XLenInBytes = Subtarget.getXLen() / 8; + EVT VT = Op.getValueType(); + SDLoc DL(Op); + SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), DL, FrameReg, VT); + unsigned Depth = cast(Op.getOperand(0))->getZExtValue(); + while (Depth--) { + int Offset = -(XLenInBytes * 2); + SDValue Ptr = DAG.getNode(ISD::ADD, DL, VT, FrameAddr, DAG.getIntPtrConstant(Offset, DL)); + FrameAddr = DAG.getLoad(VT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo()); + } + return FrameAddr; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/LowerFormalArguments.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/LowerFormalArguments.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7469ac29c8818f7827888c7dc5619a3b1397882e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/LowerFormalArguments.cpp @@ -0,0 +1,173 @@ +SDValue RISCVTargetLowering::LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl &InVals) const { + MachineFunction &MF = DAG.getMachineFunction(); + switch (CallConv) { + default: + report_fatal_error("Unsupported calling convention"); + case CallingConv::C: + case CallingConv::Fast: + break; + case CallingConv::GHC: + if (!MF.getSubtarget().getFeatureBits()[RISCV::FeatureStdExtF] || !MF.getSubtarget().getFeatureBits()[RISCV::FeatureStdExtD]) + report_fatal_error("GHC calling convention requires the F and D instruction set extensions"); + } + const Function &Func = MF.getFunction(); + if (Func.hasFnAttribute("interrupt")) { + if (!Func.arg_empty()) + report_fatal_error("Functions with the interrupt attribute cannot have arguments!"); + StringRef Kind = MF.getFunction().getFnAttribute("interrupt").getValueAsString(); + if (!(Kind == "user" || Kind == "supervisor" || Kind == "machine")) + report_fatal_error("Function interrupt attribute argument not supported!"); + } + EVT PtrVT = getPointerTy(DAG.getDataLayout()); + MVT XLenVT = Subtarget.getXLenVT(); + unsigned XLenInBytes = Subtarget.getXLen() / 8; + std::vector OutChains; + SmallVector ArgLocs; + CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext()); + if (CallConv == CallingConv::Fast) + CCInfo.AnalyzeFormalArguments(Ins, CC_RISCV_FastCC); + else if (CallConv == CallingConv::GHC) + CCInfo.AnalyzeFormalArguments(Ins, CC_RISCV_GHC); + else + analyzeInputArgs(MF, CCInfo, Ins, false); + for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { + CCValAssign &VA = ArgLocs[i]; + SDValue ArgValue; + if (VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64) { + assert(VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64 && "Unexpected VA"); + MachineFunction &MF = DAG.getMachineFunction(); + MachineFrameInfo &MFI = MF.getFrameInfo(); + MachineRegisterInfo &RegInfo = MF.getRegInfo(); + if (VA.isMemLoc()) { + int FI = MFI.CreateFixedObject(8, VA.getLocMemOffset(), true); + SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); + ArgValue = DAG.getLoad(MVT::f64, DL, Chain, FIN, MachinePointerInfo::getFixedStack(MF, FI)); + } + assert(VA.isRegLoc() && "Expected register VA assignment"); + Register LoVReg = RegInfo.createVirtualRegister(&RISCV::GPRRegClass); + RegInfo.addLiveIn(VA.getLocReg(), LoVReg); + SDValue Lo = DAG.getCopyFromReg(Chain, DL, LoVReg, MVT::i32); + SDValue Hi; + if (VA.getLocReg() == RISCV::X17) { + int FI = MFI.CreateFixedObject(4, 0, true); + SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); + Hi = DAG.getLoad(MVT::i32, DL, Chain, FIN, MachinePointerInfo::getFixedStack(MF, FI)); + } + else { + Register HiVReg = RegInfo.createVirtualRegister(&RISCV::GPRRegClass); + RegInfo.addLiveIn(VA.getLocReg() + 1, HiVReg); + Hi = DAG.getCopyFromReg(Chain, DL, HiVReg, MVT::i32); + } + ArgValue = DAG.getNode(RISCVISD::BuildPairF64, DL, MVT::f64, Lo, Hi); + } + else if (VA.isRegLoc()) { + MachineFunction &MF = DAG.getMachineFunction(); + MachineRegisterInfo &RegInfo = MF.getRegInfo(); + EVT LocVT = VA.getLocVT(); + SDValue Val; + const TargetRegisterClass *RC = TLI.getRegClassFor(LocVT.getSimpleVT()); + Register VReg = RegInfo.createVirtualRegister(RC); + RegInfo.addLiveIn(VA.getLocReg(), VReg); + Val = DAG.getCopyFromReg(Chain, DL, VReg, LocVT); + if (VA.getLocInfo() == CCValAssign::Indirect) { + return Val; + } + switch (VA.getLocInfo()) { + default: + llvm_unreachable("Unexpected CCValAssign::LocInfo"); + case CCValAssign::Full: + break; + case CCValAssign::BCvt: + if (VA.getLocVT().isInteger() && VA.getValVT() == MVT::f16) + Val = DAG.getNode(RISCVISD::FMV_H_X, DL, MVT::f16, Val); + else if (VA.getLocVT() == MVT::i64 && VA.getValVT() == MVT::f32) + Val = DAG.getNode(RISCVISD::FMV_W_X_RV64, DL, MVT::f32, Val); + else + Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val); + break; + } + ArgValue = Val; + } + else { + MachineFunction &MF = DAG.getMachineFunction(); + MachineRegisterInfo &RegInfo = MF.getRegInfo(); + EVT LocVT = VA.getLocVT(); + SDValue Val; + const TargetRegisterClass *RC = TLI.getRegClassFor(LocVT.getSimpleVT()); + Register VReg = RegInfo.createVirtualRegister(RC); + RegInfo.addLiveIn(VA.getLocReg(), VReg); + Val = DAG.getCopyFromReg(Chain, DL, VReg, LocVT); + if (VA.getLocInfo() == CCValAssign::Indirect) { + return Val; + } + switch (VA.getLocInfo()) { + default: + llvm_unreachable("Unexpected CCValAssign::LocInfo"); + case CCValAssign::Full: + break; + case CCValAssign::BCvt: + if (VA.getLocVT().isInteger() && VA.getValVT() == MVT::f16) + Val = DAG.getNode(RISCVISD::FMV_H_X, DL, MVT::f16, Val); + else if (VA.getLocVT() == MVT::i64 && VA.getValVT() == MVT::f32) + Val = DAG.getNode(RISCVISD::FMV_W_X_RV64, DL, MVT::f32, Val); + else + Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val); + break; + } + ArgValue = Val; + } + if (VA.getLocInfo() == CCValAssign::Indirect) { + InVals.push_back(DAG.getLoad(VA.getValVT(), DL, Chain, ArgValue, MachinePointerInfo())); + unsigned ArgIndex = Ins[i].OrigArgIndex; + assert(Ins[i].PartOffset == 0); + while (i + 1 != e && Ins[i + 1].OrigArgIndex == ArgIndex) { + CCValAssign &PartVA = ArgLocs[i + 1]; + unsigned PartOffset = Ins[i + 1].PartOffset; + SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, ArgValue, DAG.getIntPtrConstant(PartOffset, DL)); + InVals.push_back(DAG.getLoad(PartVA.getValVT(), DL, Chain, Address, MachinePointerInfo())); + ++i; + } + continue; + } + InVals.push_back(ArgValue); + } + if (IsVarArg) { + ArrayRef ArgRegs = makeArrayRef(ArgGPRs); + unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs); + const TargetRegisterClass *RC = &RISCV::GPRRegClass; + MachineFrameInfo &MFI = MF.getFrameInfo(); + MachineRegisterInfo &RegInfo = MF.getRegInfo(); + RISCVMachineFunctionInfo *RVFI = MF.getInfo(); + int VaArgOffset, VarArgsSaveSize; + if (ArgRegs.size() == Idx) { + VaArgOffset = CCInfo.getNextStackOffset(); + VarArgsSaveSize = 0; + } + else { + VarArgsSaveSize = XLenInBytes * (ArgRegs.size() - Idx); + VaArgOffset = -VarArgsSaveSize; + } + int FI = MFI.CreateFixedObject(XLenInBytes, VaArgOffset, true); + RVFI->setVarArgsFrameIndex(FI); + if (Idx % 2) { + MFI.CreateFixedObject(XLenInBytes, VaArgOffset - (int)XLenInBytes, true); + VarArgsSaveSize += XLenInBytes; + } + for (unsigned I = Idx; I < ArgRegs.size(); ++I, VaArgOffset += XLenInBytes) { + const Register Reg = RegInfo.createVirtualRegister(RC); + RegInfo.addLiveIn(ArgRegs[I], Reg); + SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, XLenVT); + FI = MFI.CreateFixedObject(XLenInBytes, VaArgOffset, true); + SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); + SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff, MachinePointerInfo::getFixedStack(MF, FI)); + cast(Store.getNode())->getMemOperand()->setValue((Value *)nullptr); + OutChains.push_back(Store); + } + RVFI->setVarArgsSaveSize(VarArgsSaveSize); + } + if (!OutChains.empty()) { + OutChains.push_back(Chain); + Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains); + } + return Chain; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/LowerGlobalAddress.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/LowerGlobalAddress.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c25fe7ba981ac3b403417bdc8e02f9bd6b4c8c15 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/LowerGlobalAddress.cpp @@ -0,0 +1,14 @@ +SDValue RISCVTargetLowering::lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const { + SDLoc DL(Op); + EVT Ty = Op.getValueType(); + GlobalAddressSDNode *N = cast(Op); + int64_t Offset = N->getOffset(); + MVT XLenVT = Subtarget.getXLenVT(); + const GlobalValue *GV = N->getGlobal(); + bool IsLocal = getTargetMachine().shouldAssumeDSOLocal(*GV->getParent(), GV); + SDValue Addr = getAddr(N, DAG, IsLocal); + if (Offset != 0) { + return DAG.getNode(ISD::ADD, DL, Ty, Addr, DAG.getConstant(Offset, DL, XLenVT)); + } + return Addr; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/LowerGlobalTLSAddress.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/LowerGlobalTLSAddress.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5d4b3eab18404fd36209d8bc0fe8ec8025c6bad1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/LowerGlobalTLSAddress.cpp @@ -0,0 +1,28 @@ +SDValue RISCVTargetLowering::lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { + SDLoc DL(Op); + EVT Ty = Op.getValueType(); + GlobalAddressSDNode *N = cast(Op); + int64_t Offset = N->getOffset(); + MVT XLenVT = Subtarget.getXLenVT(); + TLSModel::Model Model = getTargetMachine().getTLSModel(N->getGlobal()); + if (DAG.getMachineFunction().getFunction().getCallingConv() == CallingConv::GHC) { + report_fatal_error("In GHC calling convention TLS is not supported"); + } + SDValue Addr; + switch (Model) { + case TLSModel::LocalExec: + Addr = getStaticTLSAddr(N, DAG, false); + break; + case TLSModel::InitialExec: + Addr = getStaticTLSAddr(N, DAG, true); + break; + case TLSModel::LocalDynamic: + case TLSModel::GeneralDynamic: + Addr = getDynamicTLSAddr(N, DAG); + break; + } + if (Offset != 0) { + return DAG.getNode(ISD::ADD, DL, Ty, Addr, DAG.getConstant(Offset, DL, XLenVT)); + } + return Addr; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/LowerINTRINSIC_WO_CHAIN.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/LowerINTRINSIC_WO_CHAIN.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d271e260065b73f42c25f03d51b9b440bdc038bb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/LowerINTRINSIC_WO_CHAIN.cpp @@ -0,0 +1,30 @@ +SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const { + unsigned IntNo = cast(Op.getOperand(0))->getZExtValue(); + SDLoc DL(Op); + if (Subtarget.hasStdExtV()) { + if (const RISCVVIntrinsicsTable::RISCVVIntrinsicInfo *II = RISCVVIntrinsicsTable::getRISCVVIntrinsicInfo(IntNo)) { + if (II->ExtendedOperand) { + assert(II->ExtendedOperand < Op.getNumOperands()); + SmallVector Operands(Op->op_begin(), Op->op_end()); + SDValue &ScalarOp = Operands[II->ExtendedOperand]; + EVT OpVT = ScalarOp.getValueType(); + if (OpVT == MVT::i8 || OpVT == MVT::i16 || (OpVT == MVT::i32 && Subtarget.is64Bit())) { + unsigned ExtOpc = isa(ScalarOp) ? ISD::SIGN_EXTEND : ISD::ANY_EXTEND; + ScalarOp = DAG.getNode(ExtOpc, DL, Subtarget.getXLenVT(), ScalarOp); + return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, Op.getValueType(), Operands); + } + } + } + } + switch (IntNo) { + default: + return SDValue(); + case Intrinsic::thread_pointer: { + EVT PtrVT = getPointerTy(DAG.getDataLayout()); + return DAG.getRegister(RISCV::X4, PtrVT); + } + case Intrinsic::riscv_vmv_x_s: + assert(Op.getValueType() == Subtarget.getXLenVT() && "Unexpected VT!"); + return DAG.getNode(RISCVISD::VMV_X_S, DL, Op.getValueType(), Op.getOperand(1)); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/LowerINTRINSIC_W_CHAIN.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/LowerINTRINSIC_W_CHAIN.cpp new file mode 100644 index 0000000000000000000000000000000000000000..75222c60f17cae9305bbe5868ddff56b5bd22751 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/LowerINTRINSIC_W_CHAIN.cpp @@ -0,0 +1,122 @@ +SDValue RISCVTargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const { + unsigned IntNo = cast(Op.getOperand(1))->getZExtValue(); + SDLoc DL(Op); + if (Subtarget.hasStdExtV()) { + if (const RISCVVIntrinsicsTable::RISCVVIntrinsicInfo *II = RISCVVIntrinsicsTable::getRISCVVIntrinsicInfo(IntNo)) { + if (II->ExtendedOperand) { + unsigned ExtendOp = II->ExtendedOperand + 1; + assert(ExtendOp < Op.getNumOperands()); + SmallVector Operands(Op->op_begin(), Op->op_end()); + SDValue &ScalarOp = Operands[ExtendOp]; + EVT OpVT = ScalarOp.getValueType(); + if (OpVT == MVT::i8 || OpVT == MVT::i16 || (OpVT == MVT::i32 && Subtarget.is64Bit())) { + unsigned ExtOpc = isa(ScalarOp) ? ISD::SIGN_EXTEND : ISD::ANY_EXTEND; + ScalarOp = DAG.getNode(ExtOpc, DL, Subtarget.getXLenVT(), ScalarOp); + return DAG.getNode(ISD::INTRINSIC_W_CHAIN, DL, Op->getVTList(), Operands); + } + } + } + } + unsigned NF = 1; + switch (IntNo) { + default: + return SDValue(); + case Intrinsic::riscv_vleff: { + SDLoc DL(Op); + SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Other, MVT::Glue); + SDValue Load = DAG.getNode(RISCVISD::VLEFF, DL, VTs, Op.getOperand(0), Op.getOperand(2), Op.getOperand(3)); + VTs = DAG.getVTList(Op->getValueType(1), MVT::Other); + SDValue ReadVL = DAG.getNode(RISCVISD::READ_VL, DL, VTs, Load.getValue(2)); + return DAG.getMergeValues({Load, ReadVL, Load.getValue(1)}, DL); + } + case Intrinsic::riscv_vleff_mask: { + SDLoc DL(Op); + SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Other, MVT::Glue); + SDValue Load = DAG.getNode(RISCVISD::VLEFF_MASK, DL, VTs, Op.getOperand(0), Op.getOperand(2), Op.getOperand(3), Op.getOperand(4), Op.getOperand(5)); + VTs = DAG.getVTList(Op->getValueType(1), MVT::Other); + SDValue ReadVL = DAG.getNode(RISCVISD::READ_VL, DL, VTs, Load.getValue(2)); + return DAG.getMergeValues({Load, ReadVL, Load.getValue(1)}, DL); + } + case Intrinsic::riscv_vlseg8ff: + NF++; + LLVM_FALLTHROUGH; + case Intrinsic::riscv_vlseg7ff: + NF++; + LLVM_FALLTHROUGH; + case Intrinsic::riscv_vlseg6ff: + NF++; + LLVM_FALLTHROUGH; + case Intrinsic::riscv_vlseg5ff: + NF++; + LLVM_FALLTHROUGH; + case Intrinsic::riscv_vlseg4ff: + NF++; + LLVM_FALLTHROUGH; + case Intrinsic::riscv_vlseg3ff: + NF++; + LLVM_FALLTHROUGH; + case Intrinsic::riscv_vlseg2ff: { + NF++; + SDLoc DL(Op); + SmallVector EVTs(NF, Op.getValueType()); + EVTs.push_back(MVT::Other); + EVTs.push_back(MVT::Glue); + SDVTList VTs = DAG.getVTList(EVTs); + SDValue Load = DAG.getNode(RISCVISD::VLSEGFF, DL, VTs, Op.getOperand(0), Op.getOperand(1), Op.getOperand(2), Op.getOperand(3)); + VTs = DAG.getVTList(Op->getValueType(NF), MVT::Other); + SDValue ReadVL = DAG.getNode(RISCVISD::READ_VL, DL, VTs, Load.getValue(NF + 1)); + SmallVector Results; + for (unsigned i = 0; i < NF; ++i) { + Results.push_back(Load.getValue(i)); + } + Results.push_back(ReadVL); + Results.push_back(Load.getValue(NF)); + return DAG.getMergeValues(Results, DL); + } + case Intrinsic::riscv_vlseg8ff_mask: + NF++; + LLVM_FALLTHROUGH; + case Intrinsic::riscv_vlseg7ff_mask: + NF++; + LLVM_FALLTHROUGH; + case Intrinsic::riscv_vlseg6ff_mask: + NF++; + LLVM_FALLTHROUGH; + case Intrinsic::riscv_vlseg5ff_mask: + NF++; + LLVM_FALLTHROUGH; + case Intrinsic::riscv_vlseg4ff_mask: + NF++; + LLVM_FALLTHROUGH; + case Intrinsic::riscv_vlseg3ff_mask: + NF++; + LLVM_FALLTHROUGH; + case Intrinsic::riscv_vlseg2ff_mask: { + NF++; + SDLoc DL(Op); + SmallVector EVTs(NF, Op.getValueType()); + EVTs.push_back(MVT::Other); + EVTs.push_back(MVT::Glue); + SDVTList VTs = DAG.getVTList(EVTs); + SmallVector LoadOps; + LoadOps.push_back(Op.getOperand(0)); + LoadOps.push_back(Op.getOperand(1)); + for (unsigned i = 0; i < NF; ++i) { + LoadOps.push_back(Op.getOperand(2 + i)); + } + LoadOps.push_back(Op.getOperand(2 + NF)); + LoadOps.push_back(Op.getOperand(3 + NF)); + LoadOps.push_back(Op.getOperand(4 + NF)); + SDValue Load = DAG.getNode(RISCVISD::VLSEGFF_MASK, DL, VTs, LoadOps); + VTs = DAG.getVTList(Op->getValueType(NF), MVT::Other); + SDValue ReadVL = DAG.getNode(RISCVISD::READ_VL, DL, VTs, Load.getValue(NF + 1)); + SmallVector Results; + for (unsigned i = 0; i < NF; ++i) { + Results.push_back(Load.getValue(i)); + } + Results.push_back(ReadVL); + Results.push_back(Load.getValue(NF)); + return DAG.getMergeValues(Results, DL); + } + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/LowerJumpTable.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/LowerJumpTable.cpp new file mode 100644 index 0000000000000000000000000000000000000000..68048321fc1a4520cf96294b8748c120bfbe8b55 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/LowerJumpTable.cpp @@ -0,0 +1,4 @@ +SDValue RISCVTargetLowering::lowerJumpTable(SDValue Op, SelectionDAG &DAG) const { + JumpTableSDNode *N = cast(Op); + return getAddr(N, DAG); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/LowerOperation.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/LowerOperation.cpp new file mode 100644 index 0000000000000000000000000000000000000000..65190eb29c998ae548a8d652898fe5771b4c5e37 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/LowerOperation.cpp @@ -0,0 +1,133 @@ +SDValue RISCVTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { + if (Op.getOpcode() == ISD::GlobalAddress) { + return lowerGlobalAddress(Op, DAG); + } + if (Op.getOpcode() == ISD::BlockAddress) { + return lowerBlockAddress(Op, DAG); + } + if (Op.getOpcode() == ISD::ConstantPool) { + return lowerConstantPool(Op, DAG); + } + if (Op.getOpcode() == ISD::BlockAddress) { + return lowerBlockAddress(Op, DAG); + } + if (Op.getOpcode() == ISD::JumpTable) { + return lowerJumpTable(Op, DAG); + } + if (Op.getOpcode() == ISD::GlobalTLSAddress) { + return lowerGlobalTLSAddress(Op, DAG); + } + if (Op.getOpcode() == ISD::SELECT) { + return lowerSELECT(Op, DAG); + } + if (Op.getOpcode() == ISD::VASTART) { + return lowerVASTART(Op, DAG); + } + if (Op.getOpcode() == ISD::RETURNADDR) { + return lowerRETURNADDR(Op, DAG); + } + if (Op.getOpcode() == ISD::FRAMEADDR) { + return lowerFRAMEADDR(Op, DAG); + } + if (Op.getOpcode() == ISD::SHL_PARTS) { + return lowerShiftLeftParts(Op, DAG); + } + if (Op.getOpcode() == ISD::SRA_PARTS) { + return lowerShiftRightParts(Op, DAG, true); + } + if (Op.getOpcode() == ISD::SRL_PARTS) { + return lowerShiftRightParts(Op, DAG, false); + } + if (Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN) { + return LowerINTRINSIC_WO_CHAIN(Op, DAG); + } + if (Op.getOpcode() == ISD::INTRINSIC_W_CHAIN) { + return LowerINTRINSIC_W_CHAIN(Op, DAG); + } + if (Op.getOpcode() == ISD::ANY_EXTEND) { + return lowerVectorMaskExt(Op, DAG, 1); + } + if (Op.getOpcode() == ISD::ZERO_EXTEND) { + return lowerVectorMaskExt(Op, DAG, 1); + } + if (Op.getOpcode() == ISD::SIGN_EXTEND) { + return lowerVectorMaskExt(Op, DAG, -1); + } + if (Op.getOpcode() == ISD::SPLAT_VECTOR) { + return lowerSPLATVECTOR(Op, DAG); + } + if (Op.getOpcode() == ISD::INSERT_VECTOR_ELT) { + return lowerINSERT_VECTOR_ELT(Op, DAG); + } + if (Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT) { + return lowerEXTRACT_VECTOR_ELT(Op, DAG); + } + if (Op.getOpcode() == ISD::BITCAST) { + assert(((Subtarget.is64Bit() && Subtarget.hasStdExtF()) || Subtarget.hasStdExtZfh()) && "Unexpected custom legalisation"); + SDLoc DL(Op); + SDValue Op0 = Op.getOperand(0); + if (Op.getValueType() == MVT::f16 && Subtarget.hasStdExtZfh()) { + if (Op0.getValueType() != MVT::i16) + return SDValue(); + SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, Subtarget.getXLenVT(), Op0); + SDValue FPConv = DAG.getNode(RISCVISD::FMV_H_X, DL, MVT::f16, NewOp0); + return FPConv; + } + else if (Op.getValueType() == MVT::f32 && Subtarget.is64Bit() && Subtarget.hasStdExtF()) { + if (Op0.getValueType() != MVT::i32) + return SDValue(); + SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op0); + SDValue FPConv = DAG.getNode(RISCVISD::FMV_W_X_RV64, DL, MVT::f32, NewOp0); + return FPConv; + } + return SDValue(); + } + if (Op.getOpcode() == ISD::BSWAP) { + assert(Subtarget.hasStdExtZbp() && "Unexpected custom legalisation"); + MVT VT = Op.getSimpleValueType(); + SDLoc DL(Op); + unsigned Imm = VT.getSizeInBits() - 1; + if (Op.getOpcode() == ISD::BSWAP) + Imm &= ~0x7U; + return DAG.getNode(RISCVISD::GREVI, DL, VT, Op.getOperand(0), DAG.getTargetConstant(Imm, DL, Subtarget.getXLenVT())); + } + if (Op.getOpcode() == ISD::BITREVERSE) { + assert(Subtarget.hasStdExtZbp() && "Unexpected custom legalisation"); + MVT VT = Op.getSimpleValueType(); + SDLoc DL(Op); + unsigned Imm = VT.getSizeInBits() - 1; + if (Op.getOpcode() == ISD::BSWAP) + Imm &= ~0x7U; + return DAG.getNode(RISCVISD::GREVI, DL, VT, Op.getOperand(0), DAG.getTargetConstant(Imm, DL, Subtarget.getXLenVT())); + } + if (Op.getOpcode() == ISD::TRUNCATE) { + SDLoc DL(Op); + EVT VT = Op.getValueType(); + if (!VT.isVector()) + return Op; + if (VT.getVectorElementType() == MVT::i1) + return lowerVectorMaskTrunc(Op, DAG); + EVT DstEltVT = VT.getVectorElementType(); + SDValue Src = Op.getOperand(0); + EVT SrcVT = Src.getValueType(); + EVT SrcEltVT = SrcVT.getVectorElementType(); + assert(DstEltVT.bitsLT(SrcEltVT) && isPowerOf2_64(DstEltVT.getSizeInBits()) && isPowerOf2_64(SrcEltVT.getSizeInBits()) && "Unexpected vector truncate lowering"); + SDValue Result = Src; + LLVMContext &Context = *DAG.getContext(); + const ElementCount Count = SrcVT.getVectorElementCount(); + do { + SrcEltVT = EVT::getIntegerVT(Context, SrcEltVT.getSizeInBits() / 2); + EVT ResultVT = EVT::getVectorVT(Context, SrcEltVT, Count); + Result = DAG.getNode(RISCVISD::TRUNCATE_VECTOR, DL, ResultVT, Result); + } while (SrcEltVT != DstEltVT); + return Result; + } + if (Op.getOpcode() == ISD::VSCALE) { + MVT VT = Op.getSimpleValueType(); + SDLoc DL(Op); + SDValue VLENB = DAG.getNode(RISCVISD::READ_VLENB, DL, VT); + SDValue VScale = DAG.getNode(ISD::SRL, DL, VT, VLENB, DAG.getConstant(3, DL, VT)); + return DAG.getNode(ISD::MUL, DL, VT, VScale, Op.getOperand(0)); + } + report_fatal_error("unimplemented operand"); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/LowerRETURNADDR.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/LowerRETURNADDR.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cedd67999ef313543cc50253a91f0d00bc57396a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/LowerRETURNADDR.cpp @@ -0,0 +1,22 @@ +SDValue RISCVTargetLowering::lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const { + const RISCVRegisterInfo &RI = *Subtarget.getRegisterInfo(); + MachineFunction &MF = DAG.getMachineFunction(); + MachineFrameInfo &MFI = MF.getFrameInfo(); + MFI.setReturnAddressIsTaken(true); + MVT XLenVT = Subtarget.getXLenVT(); + int XLenInBytes = Subtarget.getXLen() / 8; + if (verifyReturnAddressArgumentIsConstant(Op, DAG)) { + return SDValue(); + } + EVT VT = Op.getValueType(); + SDLoc DL(Op); + unsigned Depth = cast(Op.getOperand(0))->getZExtValue(); + if (Depth) { + int Off = -XLenInBytes; + SDValue FrameAddr = lowerFRAMEADDR(Op, DAG); + SDValue Offset = DAG.getConstant(Off, DL, VT); + return DAG.getLoad(VT, DL, DAG.getEntryNode(), DAG.getNode(ISD::ADD, DL, VT, FrameAddr, Offset), MachinePointerInfo()); + } + Register Reg = MF.addLiveIn(RI.getRARegister(), getRegClassFor(XLenVT)); + return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, XLenVT); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/LowerReturn.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/LowerReturn.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1fe9a45c04e3607a7410233c686e1945b9b64220 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/LowerReturn.cpp @@ -0,0 +1,82 @@ +SDValue RISCVTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl &Outs, const SmallVectorImpl &OutVals, const SDLoc &DL, SelectionDAG &DAG) const { + const MachineFunction &MF = DAG.getMachineFunction(); + const RISCVSubtarget &STI = MF.getSubtarget(); + SmallVector RVLocs; + CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, *DAG.getContext()); + analyzeOutputArgs(DAG.getMachineFunction(), CCInfo, Outs, true, nullptr); + if (CallConv == CallingConv::GHC && !RVLocs.empty()) { + report_fatal_error("GHC functions return void only"); + } + SDValue Glue; + SmallVector RetOps(1, Chain); + for (unsigned i = 0, e = RVLocs.size(); i < e; ++i) { + SDValue Val = OutVals[i]; + CCValAssign &VA = RVLocs[i]; + assert(VA.isRegLoc() && "Can only return in registers!"); + if (VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64) { + assert(VA.isRegLoc() && "Expected return via registers"); + SDValue SplitF64 = DAG.getNode(RISCVISD::SplitF64, DL, DAG.getVTList(MVT::i32, MVT::i32), Val); + SDValue Lo = SplitF64.getValue(0); + SDValue Hi = SplitF64.getValue(1); + Register RegLo = VA.getLocReg(); + assert(RegLo < RISCV::X31 && "Invalid register pair"); + Register RegHi = RegLo + 1; + if (STI.isRegisterReservedByUser(RegLo) || STI.isRegisterReservedByUser(RegHi)) { + MF.getFunction().getContext().diagnose(DiagnosticInfoUnsupported{MF.getFunction(), "Return value register required, but has been reserved."}); + } + Chain = DAG.getCopyToReg(Chain, DL, RegLo, Lo, Glue); + Glue = Chain.getValue(1); + RetOps.push_back(DAG.getRegister(RegLo, MVT::i32)); + Chain = DAG.getCopyToReg(Chain, DL, RegHi, Hi, Glue); + Glue = Chain.getValue(1); + RetOps.push_back(DAG.getRegister(RegHi, MVT::i32)); + } + else { + EVT LocVT = VA.getLocVT(); + switch (VA.getLocInfo()) { + default: + llvm_unreachable("Unexpected CCValAssign::LocInfo"); + case CCValAssign::Full: + break; + case CCValAssign::BCvt: + if (VA.getLocVT().isInteger() && VA.getValVT() == MVT::f16) + Val = DAG.getNode(RISCVISD::FMV_X_ANYEXTH, DL, VA.getLocVT(), Val); + else if (VA.getLocVT() == MVT::i64 && VA.getValVT() == MVT::f32) + Val = DAG.getNode(RISCVISD::FMV_X_ANYEXTW_RV64, DL, MVT::i64, Val); + else + Val = DAG.getNode(ISD::BITCAST, DL, LocVT, Val); + break; + } + Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Glue); + if (STI.isRegisterReservedByUser(VA.getLocReg())) { + MF.getFunction().getContext().diagnose(DiagnosticInfoUnsupported{MF.getFunction(), "Return value register required, but has been reserved."}); + } + Glue = Chain.getValue(1); + RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); + } + } + RetOps[0] = Chain; + if (Glue.getNode()) { + RetOps.push_back(Glue); + } + const Function &Func = DAG.getMachineFunction().getFunction(); + if (Func.hasFnAttribute("interrupt")) { + if (!Func.getReturnType()->isVoidTy()) { + report_fatal_error("Functions with the interrupt attribute must have void return type!"); + } + MachineFunction &MF = DAG.getMachineFunction(); + StringRef Kind = MF.getFunction().getFnAttribute("interrupt").getValueAsString(); + unsigned RetOpc; + if (Kind == "user") { + RetOpc = RISCVISD::URET_FLAG; + } + else if (Kind == "supervisor") { + RetOpc = RISCVISD::SRET_FLAG; + } + else { + RetOpc = RISCVISD::MRET_FLAG; + } + return DAG.getNode(RetOpc, DL, MVT::Other, RetOps); + } + return DAG.getNode(RISCVISD::RET_FLAG, DL, MVT::Other, RetOps); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/LowerVASTART.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/LowerVASTART.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c2a8b1538a1e45039697e8f264bcdc901c75ab5e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/LowerVASTART.cpp @@ -0,0 +1,8 @@ +SDValue RISCVTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const { + MachineFunction &MF = DAG.getMachineFunction(); + RISCVMachineFunctionInfo *FuncInfo = MF.getInfo(); + SDLoc DL(Op); + SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), getPointerTy(MF.getDataLayout())); + const Value *SV = cast(Op.getOperand(2))->getValue(); + return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1), MachinePointerInfo(SV)); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/NodeType.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/NodeType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5b667b731b88f74eb2e0a2d08828d7fb845c2a26 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/NodeType.cpp @@ -0,0 +1,43 @@ +enum NodeType : unsigned { +FIRST_NUMBER = ISD::BUILTIN_OP_END, +RET_FLAG, +URET_FLAG, +SRET_FLAG, +MRET_FLAG, +CALL, +SELECT_CC, +BuildPairF64, +SplitF64, +TAIL, +SLLW, +SRAW, +SRLW, +DIVW, +DIVUW, +REMUW, +ROLW, +RORW, +FSRW, +FSLW, +FMV_H_X, +FMV_X_ANYEXTH, +FMV_W_X_RV64, +FMV_X_ANYEXTW_RV64, +READ_CYCLE_WIDE, +GREVI, +GREVIW, +GORCI, +GORCIW, +VMV_X_S, +SPLAT_VECTOR_I64, +READ_VLENB, +TRUNCATE_VECTOR, +VLEFF, +VLEFF_MASK, +VLSEGFF, +VLSEGFF_MASK, +READ_VL, +VSLIDEUP, +VSLIDEDOWN, +VID, +}; diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/PerformDAGCombine.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/PerformDAGCombine.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b5d7b0da4ad63e0b6d0d5a2618796ca7bacb4ee0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/PerformDAGCombine.cpp @@ -0,0 +1,348 @@ +SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { + SelectionDAG &DAG = DCI.DAG; + switch (N->getOpcode()) { + default: + break; + case RISCVISD::SplitF64: { + SDValue Op0 = N->getOperand(0); + if (Op0->getOpcode() == RISCVISD::BuildPairF64) + return DCI.CombineTo(N, Op0.getOperand(0), Op0.getOperand(1)); + SDLoc DL(N); + if (ConstantFPSDNode *C = dyn_cast(Op0)) { + APInt V = C->getValueAPF().bitcastToAPInt(); + SDValue Lo = DAG.getConstant(V.trunc(32), DL, MVT::i32); + SDValue Hi = DAG.getConstant(V.lshr(32).trunc(32), DL, MVT::i32); + return DCI.CombineTo(N, Lo, Hi); + } + if (!(Op0.getOpcode() == ISD::FNEG || Op0.getOpcode() == ISD::FABS) || !Op0.getNode()->hasOneUse()) + break; + SDValue NewSplitF64 = DAG.getNode(RISCVISD::SplitF64, DL, DAG.getVTList(MVT::i32, MVT::i32), Op0.getOperand(0)); + SDValue Lo = NewSplitF64.getValue(0); + SDValue Hi = NewSplitF64.getValue(1); + APInt SignBit = APInt::getSignMask(32); + if (Op0.getOpcode() == ISD::FNEG) { + SDValue NewHi = DAG.getNode(ISD::XOR, DL, MVT::i32, Hi, DAG.getConstant(SignBit, DL, MVT::i32)); + return DCI.CombineTo(N, Lo, NewHi); + } + assert(Op0.getOpcode() == ISD::FABS); + SDValue NewHi = DAG.getNode(ISD::AND, DL, MVT::i32, Hi, DAG.getConstant(~SignBit, DL, MVT::i32)); + return DCI.CombineTo(N, Lo, NewHi); + } + case RISCVISD::SLLW: + case RISCVISD::SRAW: + case RISCVISD::SRLW: + case RISCVISD::ROLW: + case RISCVISD::RORW: { + SDValue LHS = N->getOperand(0); + SDValue RHS = N->getOperand(1); + APInt LHSMask = APInt::getLowBitsSet(LHS.getValueSizeInBits(), 32); + APInt RHSMask = APInt::getLowBitsSet(RHS.getValueSizeInBits(), 5); + if (SimplifyDemandedBits(N->getOperand(0), LHSMask, DCI) || SimplifyDemandedBits(N->getOperand(1), RHSMask, DCI)) { + if (N->getOpcode() != ISD::DELETED_NODE) + DCI.AddToWorklist(N); + return SDValue(N, 0); + } + break; + } + case RISCVISD::FSLW: + case RISCVISD::FSRW: { + SDValue Op0 = N->getOperand(0); + SDValue Op1 = N->getOperand(1); + SDValue ShAmt = N->getOperand(2); + APInt OpMask = APInt::getLowBitsSet(Op0.getValueSizeInBits(), 32); + APInt ShAmtMask = APInt::getLowBitsSet(ShAmt.getValueSizeInBits(), 6); + if (SimplifyDemandedBits(Op0, OpMask, DCI) || SimplifyDemandedBits(Op1, OpMask, DCI) || SimplifyDemandedBits(ShAmt, ShAmtMask, DCI)) { + if (N->getOpcode() != ISD::DELETED_NODE) + DCI.AddToWorklist(N); + return SDValue(N, 0); + } + break; + } + case RISCVISD::GREVIW: + case RISCVISD::GORCIW: { + SDValue Op0 = N->getOperand(0); + APInt Mask = APInt::getLowBitsSet(Op0.getValueSizeInBits(), 32); + if (SimplifyDemandedBits(Op0, Mask, DCI)) { + if (N->getOpcode() != ISD::DELETED_NODE) DCI.AddToWorklist(N); + return SDValue(N, 0); + } + unsigned ShAmt1 = N->getConstantOperandVal(1); + SDValue Src = N->getOperand(0); + if (Src.getOpcode() != N->getOpcode()) + return SDValue(); + unsigned ShAmt2 = Src.getConstantOperandVal(1); + Src = Src.getOperand(0); + unsigned CombinedShAmt; + if (N->getOpcode() == RISCVISD::GORCI || N->getOpcode() == RISCVISD::GORCIW) + CombinedShAmt = ShAmt1 | ShAmt2; + else + CombinedShAmt = ShAmt1 ^ ShAmt2; + if (CombinedShAmt == 0) + return Src; + SDLoc DL(N); + return DAG.getNode(N->getOpcode(), DL, N->getValueType(0), Src, DAG.getTargetConstant(CombinedShAmt, DL, N->getOperand(1).getValueType())); + } + case RISCVISD::FMV_X_ANYEXTW_RV64: { + SDLoc DL(N); + SDValue Op0 = N->getOperand(0); + if (Op0->getOpcode() == RISCVISD::FMV_W_X_RV64) { + assert(Op0.getOperand(0).getValueType() == MVT::i64 && "Unexpected value type!"); + return Op0.getOperand(0); + } + if (!(Op0.getOpcode() == ISD::FNEG || Op0.getOpcode() == ISD::FABS) || !Op0.getNode()->hasOneUse()) + break; + SDValue NewFMV = DAG.getNode(RISCVISD::FMV_X_ANYEXTW_RV64, DL, MVT::i64, Op0.getOperand(0)); + APInt SignBit = APInt::getSignMask(32).sext(64); + if (Op0.getOpcode() == ISD::FNEG) + return DAG.getNode(ISD::XOR, DL, MVT::i64, NewFMV, DAG.getConstant(SignBit, DL, MVT::i64)); + assert(Op0.getOpcode() == ISD::FABS); + return DAG.getNode(ISD::AND, DL, MVT::i64, NewFMV, DAG.getConstant(~SignBit, DL, MVT::i64)); + } + case RISCVISD::GREVI: + case RISCVISD::GORCI: + unsigned ShAmt1 = N->getConstantOperandVal(1); + SDValue Src = N->getOperand(0); + if (Src.getOpcode() != N->getOpcode()) + return SDValue(); + unsigned ShAmt2 = Src.getConstantOperandVal(1); + Src = Src.getOperand(0); + unsigned CombinedShAmt; + if (N->getOpcode() == RISCVISD::GORCI || N->getOpcode() == RISCVISD::GORCIW) + CombinedShAmt = ShAmt1 | ShAmt2; + else + CombinedShAmt = ShAmt1 ^ ShAmt2; + if (CombinedShAmt == 0) + return Src; + SDLoc DL(N); + return DAG.getNode(N->getOpcode(), DL, N->getValueType(0), Src, DAG.getTargetConstant(CombinedShAmt, DL, N->getOperand(1).getValueType())); + case ISD::OR: + EVT VT = Op.getValueType(); + if (VT == Subtarget.getXLenVT() || (Subtarget.is64Bit() && VT == MVT::i32)) { + Optional Mask; + if (Op.getOpcode() == ISD::AND && isa(Op.getOperand(1))) { + Mask = Op.getConstantOperandVal(1); + Op = Op.getOperand(0); + } + if (Op.getOpcode() != ISD::SHL && Op.getOpcode() != ISD::SRL) + return None; + bool IsSHL = Op.getOpcode() == ISD::SHL; + if (!isa(Op.getOperand(1))) + return None; + auto ShAmt = Op.getConstantOperandVal(1); + if (!isPowerOf2_64(ShAmt)) + return None; + static const uint64_t BitmanipMasks[] = { + 0x5555555555555555ULL, 0x3333333333333333ULL, 0x0F0F0F0F0F0F0F0FULL, + 0x00FF00FF00FF00FFULL, 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL, + }; + unsigned MaskIdx = Log2_64(ShAmt); + if (MaskIdx >= array_lengthof(BitmanipMasks)) + return None; + auto Src = Op.getOperand(0); + unsigned Width = Op.getValueType() == MVT::i64 ? 64 : 32; + auto ExpMask = BitmanipMasks[MaskIdx] & maskTrailingOnes(Width); + bool SHLExpMask = IsSHL; + if (!Mask) { + if (Src.getOpcode() == ISD::AND && isa(Src.getOperand(1))) { + Mask = Src.getConstantOperandVal(1); + Src = Src.getOperand(0); + SHLExpMask = !SHLExpMask; + } + else { + Mask = maskTrailingOnes(Width); + *Mask &= (IsSHL ? *Mask << ShAmt : *Mask >> ShAmt); + } + } + if (SHLExpMask) + ExpMask <<= ShAmt; + if (Mask != ExpMask) + return None; + LHS = RISCVBitmanipPat{Src, (unsigned)ShAmt, IsSHL}; + Optional Mask; + if (Op.getOpcode() == ISD::AND && isa(Op.getOperand(1))) { + Mask = Op.getConstantOperandVal(1); + Op = Op.getOperand(0); + } + if (Op.getOpcode() != ISD::SHL && Op.getOpcode() != ISD::SRL) + return None; + bool IsSHL = Op.getOpcode() == ISD::SHL; + if (!isa(Op.getOperand(1))) + return None; + auto ShAmt = Op.getConstantOperandVal(1); + if (!isPowerOf2_64(ShAmt)) + return None; + static const uint64_t BitmanipMasks[] = { + 0x5555555555555555ULL, 0x3333333333333333ULL, 0x0F0F0F0F0F0F0F0FULL, + 0x00FF00FF00FF00FFULL, 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL, + }; + unsigned MaskIdx = Log2_64(ShAmt); + if (MaskIdx >= array_lengthof(BitmanipMasks)) + return None; + auto Src = Op.getOperand(0); + unsigned Width = Op.getValueType() == MVT::i64 ? 64 : 32; + auto ExpMask = BitmanipMasks[MaskIdx] & maskTrailingOnes(Width); + bool SHLExpMask = IsSHL; + if (!Mask) { + if (Src.getOpcode() == ISD::AND && isa(Src.getOperand(1))) { + Mask = Src.getConstantOperandVal(1); + Src = Src.getOperand(0); + SHLExpMask = !SHLExpMask; + } + else { + Mask = maskTrailingOnes(Width); + *Mask &= (IsSHL ? *Mask << ShAmt : *Mask >> ShAmt); + } + } + if (SHLExpMask) + ExpMask <<= ShAmt; + if (Mask != ExpMask) + return None; + RHS = RISCVBitmanipPat{Src, (unsigned)ShAmt, IsSHL}; + if (LHS && RHS && LHS->formsPairWith(*RHS)) { + SDLoc DL(Op); + return DAG.getNode(RISCVISD::GREVI, DL, VT, LHS->Op, DAG.getTargetConstant(LHS->ShAmt, DL, Subtarget.getXLenVT())); + } + } + auto GORC = SDValue(); + EVT VT = Op.getValueType(); + if (VT == Subtarget.getXLenVT() || (Subtarget.is64Bit() && VT == MVT::i32)) { + Optional Mask; + if (Op.getOpcode() == ISD::AND && isa(Op.getOperand(1))) { + Mask = Op.getConstantOperandVal(1); + Op = Op.getOperand(0); + } + if (Op.getOpcode() != ISD::SHL && Op.getOpcode() != ISD::SRL) + return None; + bool IsSHL = Op.getOpcode() == ISD::SHL; + if (!isa(Op.getOperand(1))) + return None; + auto ShAmt = Op.getConstantOperandVal(1); + if (!isPowerOf2_64(ShAmt)) + return None; + static const uint64_t BitmanipMasks[] = { + 0x5555555555555555ULL, 0x3333333333333333ULL, 0x0F0F0F0F0F0F0F0FULL, + 0x00FF00FF00FF00FFULL, 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL, + }; + unsigned MaskIdx = Log2_64(ShAmt); + if (MaskIdx >= array_lengthof(BitmanipMasks)) + return None; + auto Src = Op.getOperand(0); + unsigned Width = Op.getValueType() == MVT::i64 ? 64 : 32; + auto ExpMask = BitmanipMasks[MaskIdx] & maskTrailingOnes(Width); + bool SHLExpMask = IsSHL; + if (!Mask) { + if (Src.getOpcode() == ISD::AND && isa(Src.getOperand(1))) { + Mask = Src.getConstantOperandVal(1); + Src = Src.getOperand(0); + SHLExpMask = !SHLExpMask; + } + else { + Mask = maskTrailingOnes(Width); + *Mask &= (IsSHL ? *Mask << ShAmt : *Mask >> ShAmt); + } + } + if (SHLExpMask) + ExpMask <<= ShAmt; + if (Mask != ExpMask) + return None; + LHS = RISCVBitmanipPat{Src, (unsigned)ShAmt, IsSHL}; + Optional Mask; + if (Op.getOpcode() == ISD::AND && isa(Op.getOperand(1))) { + Mask = Op.getConstantOperandVal(1); + Op = Op.getOperand(0); + } + if (Op.getOpcode() != ISD::SHL && Op.getOpcode() != ISD::SRL) + return None; + bool IsSHL = Op.getOpcode() == ISD::SHL; + if (!isa(Op.getOperand(1))) + return None; + auto ShAmt = Op.getConstantOperandVal(1); + if (!isPowerOf2_64(ShAmt)) + return None; + static const uint64_t BitmanipMasks[] = { + 0x5555555555555555ULL, 0x3333333333333333ULL, 0x0F0F0F0F0F0F0F0FULL, + 0x00FF00FF00FF00FFULL, 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL, + }; + unsigned MaskIdx = Log2_64(ShAmt); + if (MaskIdx >= array_lengthof(BitmanipMasks)) + return None; + auto Src = Op.getOperand(0); + unsigned Width = Op.getValueType() == MVT::i64 ? 64 : 32; + auto ExpMask = BitmanipMasks[MaskIdx] & maskTrailingOnes(Width); + bool SHLExpMask = IsSHL; + if (!Mask) { + if (Src.getOpcode() == ISD::AND && isa(Src.getOperand(1))) { + Mask = Src.getConstantOperandVal(1); + Src = Src.getOperand(0); + SHLExpMask = !SHLExpMask; + } + else { + Mask = maskTrailingOnes(Width); + *Mask &= (IsSHL ? *Mask << ShAmt : *Mask >> ShAmt); + } + } + if (SHLExpMask) + ExpMask <<= ShAmt; + if (Mask != ExpMask) + return None; + RHS = RISCVBitmanipPat{Src, (unsigned)ShAmt, IsSHL}; + if (LHS && RHS && LHS->formsPairWith(*RHS)) { + SDLoc DL(Op); + return DAG.getNode(RISCVISD::GREVI, DL, VT, LHS->Op, DAG.getTargetConstant(LHS->ShAmt, DL, Subtarget.getXLenVT())); + } + } + auto GORC = SDValue(); + if (GORC) + return GORC; + break; + case RISCVISD::SELECT_CC: { + SDValue LHS = N->getOperand(0); + SDValue RHS = N->getOperand(1); + auto CCVal = static_cast(N->getConstantOperandVal(2)); + APInt Mask = APInt::getBitsSetFrom(LHS.getValueSizeInBits(), 1); + if (ISD::isIntEqualitySetCC(CCVal) && isNullConstant(RHS) && LHS.getOpcode() == ISD::XOR && isOneConstant(LHS.getOperand(1)) && DAG.MaskedValueIsZero(LHS.getOperand(0), Mask)) { + SDLoc DL(N); + CCVal = ISD::getSetCCInverse(CCVal, LHS.getValueType()); + SDValue TargetCC = DAG.getConstant(CCVal, DL, Subtarget.getXLenVT()); + return DAG.getNode(RISCVISD::SELECT_CC, DL, N->getValueType(0), {LHS.getOperand(0), RHS, TargetCC, N->getOperand(3), N->getOperand(4)}); + } + break; + } + case ISD::SETCC: { + SDValue LHS = N->getOperand(0); + SDValue RHS = N->getOperand(1); + if (LHS.getValueType().isScalableVector()) + break; + auto CC = cast(N->getOperand(2))->get(); + APInt Mask = APInt::getBitsSetFrom(LHS.getValueSizeInBits(), 1); + if (isOneConstant(RHS) && ISD::isIntEqualitySetCC(CC) && DAG.MaskedValueIsZero(LHS, Mask)) { + SDLoc DL(N); + SDValue Zero = DAG.getConstant(0, DL, LHS.getValueType()); + CC = ISD::getSetCCInverse(CC, LHS.getValueType()); + return DAG.getSetCC(DL, N->getValueType(0), LHS, Zero, CC); + } + break; + } + case ISD::BR: { + SDValue BrCond = N->getOperand(0); + if (BrCond->getOpcode() != ISD::BRCOND) + break; + SDValue Xor = BrCond->getOperand(1); + if (Xor->getOpcode() != ISD::XOR) + break; + if (auto True = dyn_cast(Xor->getOperand(1))){ + if (True->getSExtValue() != -1) break; + } + else break; + SDValue LoopDecrement = Xor->getOperand(0); + if (LoopDecrement->getOpcode() != ISD::INTRINSIC_W_CHAIN || LoopDecrement->getConstantOperandVal(1) != Intrinsic::loop_decrement) + break; + SDValue BB1 = N->getOperand(1); + SDValue LoopBranch = DAG.getNode(ISD::BRCOND, SDLoc(BrCond), MVT::Other, BrCond->getOperand(0), LoopDecrement, BB1); + SDValue BB2 = BrCond->getOperand(2); + SDValue ElseBranch = DAG.getNode(ISD::BR, SDLoc(N), MVT::Other, LoopBranch, BB2); + return DCI.CombineTo(N, ElseBranch); + } + } + return SDValue(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/ReplaceNodeResults.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/ReplaceNodeResults.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fcb7e257a67ab4aabcfa12a0a4d5afa2da879f4c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/ReplaceNodeResults.cpp @@ -0,0 +1,178 @@ +void RISCVTargetLowering::ReplaceNodeResults(SDNode *N, SmallVectorImpl &Results, SelectionDAG &DAG) const { + SDLoc DL(N); + switch (N->getOpcode()) { + default: + llvm_unreachable("Don't know how to custom type legalize this operation!"); + case ISD::STRICT_FP_TO_SINT: + case ISD::STRICT_FP_TO_UINT: + case ISD::FP_TO_SINT: + case ISD::FP_TO_UINT: { + bool IsStrict = N->isStrictFPOpcode(); + assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() && "Unexpected custom legalisation"); + SDValue Op0 = IsStrict ? N->getOperand(1) : N->getOperand(0); + if (getTypeAction(*DAG.getContext(), Op0.getValueType()) != TargetLowering::TypeSoftenFloat) + return; + RTLIB::Libcall LC; + if (N->getOpcode() == ISD::FP_TO_SINT || N->getOpcode() == ISD::STRICT_FP_TO_SINT) + LC = RTLIB::getFPTOSINT(Op0.getValueType(), N->getValueType(0)); + else + LC = RTLIB::getFPTOUINT(Op0.getValueType(), N->getValueType(0)); + MakeLibCallOptions CallOptions; + EVT OpVT = Op0.getValueType(); + CallOptions.setTypeListBeforeSoften(OpVT, N->getValueType(0), true); + SDValue Chain = IsStrict ? N->getOperand(0) : SDValue(); + SDValue Result; + std::tie(Result, Chain) = makeLibCall(DAG, LC, N->getValueType(0), Op0, CallOptions, DL, Chain); + Results.push_back(Result); + if (IsStrict) + Results.push_back(Chain); + break; + } + case ISD::READCYCLECOUNTER: { + assert(!Subtarget.is64Bit() && "READCYCLECOUNTER only has custom type legalization on riscv32"); + SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); + SDValue RCW = DAG.getNode(RISCVISD::READ_CYCLE_WIDE, DL, VTs, N->getOperand(0)); + Results.push_back( DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, RCW, RCW.getValue(1))); + Results.push_back(RCW.getValue(2)); + break; + } + case ISD::ADD: + case ISD::SUB: + case ISD::MUL: + assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() && "Unexpected custom legalisation"); + if (N->getOperand(1).getOpcode() == ISD::Constant) + return; + Results.push_back(customLegalizeToWOpWithSExt(N, DAG)); + SDLoc DL(N); + SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(0)); + SDValue NewOp1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(1)); + SDValue NewWOp = DAG.getNode(N->getOpcode(), DL, MVT::i64, NewOp0, NewOp1); + SDValue NewRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i64, NewWOp, DAG.getValueType(MVT::i32)); + return DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, NewRes); + break; + case ISD::SHL: + case ISD::SRA: + case ISD::SRL: + assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() && "Unexpected custom legalisation"); + if (N->getOperand(1).getOpcode() == ISD::Constant) + return; + Results.push_back(customLegalizeToWOp(N, DAG)); + SDLoc DL(N); + RISCVISD::NodeType WOpcode = getRISCVWOpcode(N->getOpcode()); + SDValue NewOp0 = DAG.getNode(ExtOpc, DL, MVT::i64, N->getOperand(0)); + SDValue NewOp1 = DAG.getNode(ExtOpc, DL, MVT::i64, N->getOperand(1)); + SDValue NewRes = DAG.getNode(WOpcode, DL, MVT::i64, NewOp0, NewOp1); + return DAG.getNode(ISD::TRUNCATE, DL, N->getValueType(0), NewRes); + break; + case ISD::ROTL: + case ISD::ROTR: + assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() && "Unexpected custom legalisation"); + Results.push_back(customLegalizeToWOp(N, DAG)); + SDLoc DL(N); + RISCVISD::NodeType WOpcode = getRISCVWOpcode(N->getOpcode()); + SDValue NewOp0 = DAG.getNode(ExtOpc, DL, MVT::i64, N->getOperand(0)); + SDValue NewOp1 = DAG.getNode(ExtOpc, DL, MVT::i64, N->getOperand(1)); + SDValue NewRes = DAG.getNode(WOpcode, DL, MVT::i64, NewOp0, NewOp1); + return DAG.getNode(ISD::TRUNCATE, DL, N->getValueType(0), NewRes); + break; + case ISD::SDIV: + case ISD::UDIV: + case ISD::UREM: { + MVT VT = N->getSimpleValueType(0); + assert((VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) && Subtarget.is64Bit() && Subtarget.hasStdExtM() && "Unexpected custom legalisation"); + if (N->getOperand(0).getOpcode() == ISD::Constant || N->getOperand(1).getOpcode() == ISD::Constant) + return; + unsigned ExtOpc = ISD::ANY_EXTEND; + if (VT != MVT::i32) + ExtOpc = N->getOpcode() == ISD::SDIV ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; + Results.push_back(customLegalizeToWOp(N, DAG, ExtOpc)); + SDLoc DL(N); + RISCVISD::NodeType WOpcode = getRISCVWOpcode(N->getOpcode()); + SDValue NewOp0 = DAG.getNode(ExtOpc, DL, MVT::i64, N->getOperand(0)); + SDValue NewOp1 = DAG.getNode(ExtOpc, DL, MVT::i64, N->getOperand(1)); + SDValue NewRes = DAG.getNode(WOpcode, DL, MVT::i64, NewOp0, NewOp1); + return DAG.getNode(ISD::TRUNCATE, DL, N->getValueType(0), NewRes); + break; + } + case ISD::BITCAST: { + assert(((N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() && Subtarget.hasStdExtF()) || (N->getValueType(0) == MVT::i16 && Subtarget.hasStdExtZfh())) && "Unexpected custom legalisation"); + SDValue Op0 = N->getOperand(0); + if (N->getValueType(0) == MVT::i16 && Subtarget.hasStdExtZfh()) { + if (Op0.getValueType() != MVT::f16) + return; + SDValue FPConv = DAG.getNode(RISCVISD::FMV_X_ANYEXTH, DL, Subtarget.getXLenVT(), Op0); + Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, FPConv)); + } + else if (N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() && Subtarget.hasStdExtF()) { + if (Op0.getValueType() != MVT::f32) + return; + SDValue FPConv = DAG.getNode(RISCVISD::FMV_X_ANYEXTW_RV64, DL, MVT::i64, Op0); + Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, FPConv)); + } + break; + } + case RISCVISD::GREVI: + case RISCVISD::GORCI: { + assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() && "Unexpected custom legalisation"); + SDLoc DL(N); + RISCVISD::NodeType WOpcode = getRISCVWOpcode(N->getOpcode()); + SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(0)); + SDValue NewRes = DAG.getNode(WOpcode, DL, MVT::i64, NewOp0, N->getOperand(1)); + Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, NewRes)); + break; + } + case ISD::BSWAP: + case ISD::BITREVERSE: { + assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() && Subtarget.hasStdExtZbp() && "Unexpected custom legalisation"); + SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(0)); + unsigned Imm = N->getOpcode() == ISD::BITREVERSE ? 31 : 24; + SDValue GREVIW = DAG.getNode(RISCVISD::GREVIW, DL, MVT::i64, NewOp0, DAG.getTargetConstant(Imm, DL, Subtarget.getXLenVT())); + Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, GREVIW)); + break; + } + case ISD::FSHL: + case ISD::FSHR: { + assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() && Subtarget.hasStdExtZbt() && "Unexpected custom legalisation"); + SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(0)); + SDValue NewOp1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(1)); + SDValue NewOp2 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(2)); + NewOp2 = DAG.getNode(ISD::AND, DL, MVT::i64, NewOp2, DAG.getConstant(0x1f, DL, MVT::i64)); + unsigned Opc = N->getOpcode() == ISD::FSHL ? RISCVISD::FSLW : RISCVISD::FSRW; + SDValue NewOp = DAG.getNode(Opc, DL, MVT::i64, NewOp0, NewOp1, NewOp2); + Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, NewOp)); + break; + } + case ISD::EXTRACT_VECTOR_ELT: { + SDLoc DL(N); + SDValue Vec = N->getOperand(0); + SDValue Idx = N->getOperand(1); + EVT VecVT = Vec.getValueType(); + assert(!Subtarget.is64Bit() && N->getValueType(0) == MVT::i64 && VecVT.getVectorElementType() == MVT::i64 && "Unexpected EXTRACT_VECTOR_ELT legalization"); + SDValue Slidedown = Vec; + if (!isNullConstant(Idx)) + Slidedown = DAG.getNode(RISCVISD::VSLIDEDOWN, DL, VecVT, DAG.getUNDEF(VecVT), Vec, Idx); + MVT XLenVT = Subtarget.getXLenVT(); + SDValue EltLo = DAG.getNode(RISCVISD::VMV_X_S, DL, XLenVT, Slidedown, Idx); + SDValue ThirtyTwoV = DAG.getNode(RISCVISD::SPLAT_VECTOR_I64, DL, VecVT, DAG.getConstant(32, DL, Subtarget.getXLenVT())); + SDValue LShr32 = DAG.getNode(ISD::SRL, DL, VecVT, Slidedown, ThirtyTwoV); + SDValue EltHi = DAG.getNode(RISCVISD::VMV_X_S, DL, XLenVT, LShr32, Idx); + Results.push_back(DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, EltLo, EltHi)); + break; + } + case ISD::INTRINSIC_WO_CHAIN: { + unsigned IntNo = cast(N->getOperand(0))->getZExtValue(); + switch (IntNo) { + default: + llvm_unreachable("Don't know how to custom type legalize this intrinsic!"); + case Intrinsic::riscv_vmv_x_s: { + EVT VT = N->getValueType(0); + assert((VT == MVT::i8 || VT == MVT::i16 || (Subtarget.is64Bit() && VT == MVT::i32)) && "Unexpected custom legalisation!"); + SDValue Extract = DAG.getNode(RISCVISD::VMV_X_S, DL, Subtarget.getXLenVT(), N->getOperand(1)); + Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, VT, Extract)); + break; + } + } + break; + } + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/TargetLowering.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/TargetLowering.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f36b91ccdbca211f36db98d0815a3bc0c3067159 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/TargetLowering.cpp @@ -0,0 +1,375 @@ +RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, const RISCVSubtarget &STI) : TargetLowering(TM), Subtarget(STI) { + if (Subtarget.isRV32E()) + report_fatal_error("Codegen not yet implemented for RV32E"); + RISCVABI::ABI ABI = Subtarget.getTargetABI(); + assert(ABI != RISCVABI::ABI_Unknown && "Improperly initialised target ABI"); + if ((ABI == RISCVABI::ABI_ILP32F || ABI == RISCVABI::ABI_LP64F) && !Subtarget.hasStdExtF()) { + errs() << "Hard-float 'f' ABI can't be used for a target that doesn't support the F instruction set extension (ignoring target-abi)\n"; + ABI = Subtarget.is64Bit() ? RISCVABI::ABI_LP64 : RISCVABI::ABI_ILP32; + } + else if ((ABI == RISCVABI::ABI_ILP32D || ABI == RISCVABI::ABI_LP64D) && !Subtarget.hasStdExtD()) { + errs() << "Hard-float 'd' ABI can't be used for a target that doesn't support the D instruction set extension (ignoring target-abi)\n"; + ABI = Subtarget.is64Bit() ? RISCVABI::ABI_LP64 : RISCVABI::ABI_ILP32; + } + switch (ABI) { + default: + report_fatal_error("Don't know how to lower this ABI"); + case RISCVABI::ABI_ILP32: + case RISCVABI::ABI_ILP32F: + case RISCVABI::ABI_ILP32D: + case RISCVABI::ABI_LP64: + case RISCVABI::ABI_LP64F: + case RISCVABI::ABI_LP64D: + break; + } + MVT XLenVT = Subtarget.getXLenVT(); + addRegisterClass(XLenVT, &RISCV::GPRRegClass); + if (Subtarget.hasStdExtZfh()) + addRegisterClass(MVT::f16, &RISCV::FPR16RegClass); + if (Subtarget.hasStdExtF()) + addRegisterClass(MVT::f32, &RISCV::FPR32RegClass); + if (Subtarget.hasStdExtD()) + addRegisterClass(MVT::f64, &RISCV::FPR64RegClass); + if (Subtarget.hasStdExtV()) { + addRegisterClass(RISCVVMVTs::vbool64_t, &RISCV::VRRegClass); + addRegisterClass(RISCVVMVTs::vbool32_t, &RISCV::VRRegClass); + addRegisterClass(RISCVVMVTs::vbool16_t, &RISCV::VRRegClass); + addRegisterClass(RISCVVMVTs::vbool8_t, &RISCV::VRRegClass); + addRegisterClass(RISCVVMVTs::vbool4_t, &RISCV::VRRegClass); + addRegisterClass(RISCVVMVTs::vbool2_t, &RISCV::VRRegClass); + addRegisterClass(RISCVVMVTs::vbool1_t, &RISCV::VRRegClass); + addRegisterClass(RISCVVMVTs::vint8mf8_t, &RISCV::VRRegClass); + addRegisterClass(RISCVVMVTs::vint8mf4_t, &RISCV::VRRegClass); + addRegisterClass(RISCVVMVTs::vint8mf2_t, &RISCV::VRRegClass); + addRegisterClass(RISCVVMVTs::vint8m1_t, &RISCV::VRRegClass); + addRegisterClass(RISCVVMVTs::vint8m2_t, &RISCV::VRM2RegClass); + addRegisterClass(RISCVVMVTs::vint8m4_t, &RISCV::VRM4RegClass); + addRegisterClass(RISCVVMVTs::vint8m8_t, &RISCV::VRM8RegClass); + addRegisterClass(RISCVVMVTs::vint16mf4_t, &RISCV::VRRegClass); + addRegisterClass(RISCVVMVTs::vint16mf2_t, &RISCV::VRRegClass); + addRegisterClass(RISCVVMVTs::vint16m1_t, &RISCV::VRRegClass); + addRegisterClass(RISCVVMVTs::vint16m2_t, &RISCV::VRM2RegClass); + addRegisterClass(RISCVVMVTs::vint16m4_t, &RISCV::VRM4RegClass); + addRegisterClass(RISCVVMVTs::vint16m8_t, &RISCV::VRM8RegClass); + addRegisterClass(RISCVVMVTs::vint32mf2_t, &RISCV::VRRegClass); + addRegisterClass(RISCVVMVTs::vint32m1_t, &RISCV::VRRegClass); + addRegisterClass(RISCVVMVTs::vint32m2_t, &RISCV::VRM2RegClass); + addRegisterClass(RISCVVMVTs::vint32m4_t, &RISCV::VRM4RegClass); + addRegisterClass(RISCVVMVTs::vint32m8_t, &RISCV::VRM8RegClass); + addRegisterClass(RISCVVMVTs::vint64m1_t, &RISCV::VRRegClass); + addRegisterClass(RISCVVMVTs::vint64m2_t, &RISCV::VRM2RegClass); + addRegisterClass(RISCVVMVTs::vint64m4_t, &RISCV::VRM4RegClass); + addRegisterClass(RISCVVMVTs::vint64m8_t, &RISCV::VRM8RegClass); + if (Subtarget.hasStdExtZfh()) { + addRegisterClass(RISCVVMVTs::vfloat16mf4_t, &RISCV::VRRegClass); + addRegisterClass(RISCVVMVTs::vfloat16mf2_t, &RISCV::VRRegClass); + addRegisterClass(RISCVVMVTs::vfloat16m1_t, &RISCV::VRRegClass); + addRegisterClass(RISCVVMVTs::vfloat16m2_t, &RISCV::VRM2RegClass); + addRegisterClass(RISCVVMVTs::vfloat16m4_t, &RISCV::VRM4RegClass); + addRegisterClass(RISCVVMVTs::vfloat16m8_t, &RISCV::VRM8RegClass); + } + if (Subtarget.hasStdExtF()) { + addRegisterClass(RISCVVMVTs::vfloat32mf2_t, &RISCV::VRRegClass); + addRegisterClass(RISCVVMVTs::vfloat32m1_t, &RISCV::VRRegClass); + addRegisterClass(RISCVVMVTs::vfloat32m2_t, &RISCV::VRM2RegClass); + addRegisterClass(RISCVVMVTs::vfloat32m4_t, &RISCV::VRM4RegClass); + addRegisterClass(RISCVVMVTs::vfloat32m8_t, &RISCV::VRM8RegClass); + } + if (Subtarget.hasStdExtD()) { + addRegisterClass(RISCVVMVTs::vfloat64m1_t, &RISCV::VRRegClass); + addRegisterClass(RISCVVMVTs::vfloat64m2_t, &RISCV::VRM2RegClass); + addRegisterClass(RISCVVMVTs::vfloat64m4_t, &RISCV::VRM4RegClass); + addRegisterClass(RISCVVMVTs::vfloat64m8_t, &RISCV::VRM8RegClass); + } + } + computeRegisterProperties(STI.getRegisterInfo()); + setStackPointerRegisterToSaveRestore(RISCV::X2); + for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) + setLoadExtAction(N, XLenVT, MVT::i1, Promote); + setOperationAction(ISD::DYNAMIC_STACKALLOC, XLenVT, Expand); + setOperationAction(ISD::BR_JT, MVT::Other, Expand); + setOperationAction(ISD::BR_CC, XLenVT, Expand); + setOperationAction(ISD::SELECT_CC, XLenVT, Expand); + setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); + setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); + setOperationAction(ISD::VASTART, MVT::Other, Custom); + setOperationAction(ISD::VAARG, MVT::Other, Expand); + setOperationAction(ISD::VACOPY, MVT::Other, Expand); + setOperationAction(ISD::VAEND, MVT::Other, Expand); + setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); + if (!Subtarget.hasStdExtZbb()) { + setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); + setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); + } + if (Subtarget.is64Bit()) { + setOperationAction(ISD::ADD, MVT::i32, Custom); + setOperationAction(ISD::SUB, MVT::i32, Custom); + setOperationAction(ISD::SHL, MVT::i32, Custom); + setOperationAction(ISD::SRA, MVT::i32, Custom); + setOperationAction(ISD::SRL, MVT::i32, Custom); + } + if (!Subtarget.hasStdExtM()) { + setOperationAction(ISD::MUL, XLenVT, Expand); + setOperationAction(ISD::MULHS, XLenVT, Expand); + setOperationAction(ISD::MULHU, XLenVT, Expand); + setOperationAction(ISD::SDIV, XLenVT, Expand); + setOperationAction(ISD::UDIV, XLenVT, Expand); + setOperationAction(ISD::SREM, XLenVT, Expand); + setOperationAction(ISD::UREM, XLenVT, Expand); + } + if (Subtarget.is64Bit() && Subtarget.hasStdExtM()) { + setOperationAction(ISD::MUL, MVT::i32, Custom); + setOperationAction(ISD::SDIV, MVT::i8, Custom); + setOperationAction(ISD::UDIV, MVT::i8, Custom); + setOperationAction(ISD::UREM, MVT::i8, Custom); + setOperationAction(ISD::SDIV, MVT::i16, Custom); + setOperationAction(ISD::UDIV, MVT::i16, Custom); + setOperationAction(ISD::UREM, MVT::i16, Custom); + setOperationAction(ISD::SDIV, MVT::i32, Custom); + setOperationAction(ISD::UDIV, MVT::i32, Custom); + setOperationAction(ISD::UREM, MVT::i32, Custom); + } + setOperationAction(ISD::SDIVREM, XLenVT, Expand); + setOperationAction(ISD::UDIVREM, XLenVT, Expand); + setOperationAction(ISD::SMUL_LOHI, XLenVT, Expand); + setOperationAction(ISD::UMUL_LOHI, XLenVT, Expand); + setOperationAction(ISD::SHL_PARTS, XLenVT, Custom); + setOperationAction(ISD::SRL_PARTS, XLenVT, Custom); + setOperationAction(ISD::SRA_PARTS, XLenVT, Custom); + if (Subtarget.hasStdExtZbb() || Subtarget.hasStdExtZbp()) { + if (Subtarget.is64Bit()) { + setOperationAction(ISD::ROTL, MVT::i32, Custom); + setOperationAction(ISD::ROTR, MVT::i32, Custom); + } + } + else { + setOperationAction(ISD::ROTL, XLenVT, Expand); + setOperationAction(ISD::ROTR, XLenVT, Expand); + } + if (Subtarget.hasStdExtZbp()) { + setOperationAction(ISD::BITREVERSE, XLenVT, Custom); + setOperationAction(ISD::BSWAP, XLenVT, Custom); + if (Subtarget.is64Bit()) { + setOperationAction(ISD::BITREVERSE, MVT::i32, Custom); + setOperationAction(ISD::BSWAP, MVT::i32, Custom); + } + } + else { + setOperationAction(ISD::BSWAP, XLenVT, Subtarget.hasStdExtZbb() ? Legal : Expand); + } + if (Subtarget.hasStdExtZbb()) { + setOperationAction(ISD::SMIN, XLenVT, Legal); + setOperationAction(ISD::SMAX, XLenVT, Legal); + setOperationAction(ISD::UMIN, XLenVT, Legal); + setOperationAction(ISD::UMAX, XLenVT, Legal); + } + else { + setOperationAction(ISD::CTTZ, XLenVT, Expand); + setOperationAction(ISD::CTLZ, XLenVT, Expand); + setOperationAction(ISD::CTPOP, XLenVT, Expand); + } + if (Subtarget.hasStdExtZbt()) { + setOperationAction(ISD::FSHL, XLenVT, Legal); + setOperationAction(ISD::FSHR, XLenVT, Legal); + setOperationAction(ISD::SELECT, XLenVT, Legal); + if (Subtarget.is64Bit()) { + setOperationAction(ISD::FSHL, MVT::i32, Custom); + setOperationAction(ISD::FSHR, MVT::i32, Custom); + } + } + else { + setOperationAction(ISD::SELECT, XLenVT, Custom); + } + ISD::CondCode FPCCToExpand[] = {ISD::SETOGT, ISD::SETOGE, ISD::SETONE, ISD::SETUEQ, ISD::SETUGT, ISD::SETUGE, ISD::SETULT, ISD::SETULE, ISD::SETUNE, ISD::SETGT, ISD::SETGE, ISD::SETNE, ISD::SETO, ISD::SETUO}; + ISD::NodeType FPOpToExpand[] = {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM, ISD::FP16_TO_FP, ISD::FP_TO_FP16}; + if (Subtarget.hasStdExtZfh()) + setOperationAction(ISD::BITCAST, MVT::i16, Custom); + if (Subtarget.hasStdExtZfh()) { + setOperationAction(ISD::FMINNUM, MVT::f16, Legal); + setOperationAction(ISD::FMAXNUM, MVT::f16, Legal); + for (auto CC : FPCCToExpand) + setCondCodeAction(CC, MVT::f16, Expand); + setOperationAction(ISD::SELECT_CC, MVT::f16, Expand); + setOperationAction(ISD::SELECT, MVT::f16, Custom); + setOperationAction(ISD::BR_CC, MVT::f16, Expand); + for (auto Op : FPOpToExpand) + setOperationAction(Op, MVT::f16, Expand); + } + if (Subtarget.hasStdExtF()) { + setOperationAction(ISD::FMINNUM, MVT::f32, Legal); + setOperationAction(ISD::FMAXNUM, MVT::f32, Legal); + for (auto CC : FPCCToExpand) + setCondCodeAction(CC, MVT::f32, Expand); + setOperationAction(ISD::SELECT_CC, MVT::f32, Expand); + setOperationAction(ISD::SELECT, MVT::f32, Custom); + setOperationAction(ISD::BR_CC, MVT::f32, Expand); + for (auto Op : FPOpToExpand) + setOperationAction(Op, MVT::f32, Expand); + setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand); + setTruncStoreAction(MVT::f32, MVT::f16, Expand); + } + if (Subtarget.hasStdExtF() && Subtarget.is64Bit()) + setOperationAction(ISD::BITCAST, MVT::i32, Custom); + if (Subtarget.hasStdExtD()) { + setOperationAction(ISD::FMINNUM, MVT::f64, Legal); + setOperationAction(ISD::FMAXNUM, MVT::f64, Legal); + for (auto CC : FPCCToExpand) + setCondCodeAction(CC, MVT::f64, Expand); + setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); + setOperationAction(ISD::SELECT, MVT::f64, Custom); + setOperationAction(ISD::BR_CC, MVT::f64, Expand); + setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand); + setTruncStoreAction(MVT::f64, MVT::f32, Expand); + for (auto Op : FPOpToExpand) + setOperationAction(Op, MVT::f64, Expand); + setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand); + setTruncStoreAction(MVT::f64, MVT::f16, Expand); + } + if (Subtarget.is64Bit()) { + setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); + setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); + setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Custom); + setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Custom); + } + setOperationAction(ISD::GlobalAddress, XLenVT, Custom); + setOperationAction(ISD::BlockAddress, XLenVT, Custom); + setOperationAction(ISD::ConstantPool, XLenVT, Custom); + setOperationAction(ISD::JumpTable, XLenVT, Custom); + setOperationAction(ISD::GlobalTLSAddress, XLenVT, Custom); + setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Subtarget.is64Bit() ? Legal : Custom); + setOperationAction(ISD::TRAP, MVT::Other, Legal); + setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal); + setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); + if (Subtarget.hasPULPExtV2()) { + for (auto VT : {XLenVT.SimpleTy, MVT::v2i16, MVT::v4i8}){ + setOperationAction(ISD::ABS, VT, Legal); + setOperationAction(ISD::SMIN, VT, Legal); + setOperationAction(ISD::UMIN, VT, Legal); + setOperationAction(ISD::SMAX, VT, Legal); + setOperationAction(ISD::UMAX, VT, Legal); + } + setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Legal); + setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal); + setOperationAction(ISD::CTLZ_ZERO_UNDEF, XLenVT, Legal); + setOperationAction(ISD::CTTZ, XLenVT, Legal); + setOperationAction(ISD::CTPOP, XLenVT, Legal); + setOperationAction(ISD::ROTR, XLenVT, Legal); + setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom); + for (auto VT : {MVT::v2i16, MVT::v4i8}){ + setOperationAction(ISD::SPLAT_VECTOR, VT, Legal); + setOperationAction(ISD::VECREDUCE_ADD, VT, Legal); + setOperationPromotedToType(ISD::LOAD, VT, MVT::i32); + setOperationPromotedToType(ISD::STORE, VT, MVT::i32); + setOperationAction(ISD::VSELECT, VT, Expand); + setOperationAction(ISD::MUL, VT, Expand); + setOperationAction(ISD::SDIV, VT, Expand); + setOperationAction(ISD::UDIV, VT, Expand); + setOperationAction(ISD::SREM, VT, Expand); + setOperationAction(ISD::UREM, VT, Expand); + setOperationAction(ISD::ROTR, VT, Expand); + setOperationAction(ISD::ROTL, VT, Expand); + setOperationAction(ISD::BSWAP, VT, Expand); + setOperationAction(ISD::CTTZ, VT, Expand); + setOperationAction(ISD::CTLZ, VT, Expand); + setOperationAction(ISD::CTPOP, VT, Expand); + setOperationAction(ISD::SDIVREM, VT, Expand); + setOperationAction(ISD::UDIVREM, VT, Expand); + setOperationAction(ISD::SMUL_LOHI, VT, Expand); + setOperationAction(ISD::UMUL_LOHI, VT, Expand); + } + setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, MVT::v2i8, Expand); + setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, MVT::v2i8, Expand); + setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i16, MVT::v2i8, Expand); + setTruncStoreAction(MVT::v2i16, MVT::v2i8, Expand); + setTargetDAGCombine(ISD::BR); + setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); + } + if (Subtarget.hasStdExtA()) { + setMaxAtomicSizeInBitsSupported(Subtarget.getXLen()); + setMinCmpXchgSizeInBits(32); + } + else { + setMaxAtomicSizeInBitsSupported(0); + } + if (Subtarget.hasPULPExtV2()) { + setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal); + setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal); + setIndexedLoadAction(ISD::POST_INC, MVT::i32, Legal); + setIndexedLoadAction(ISD::POST_INC, MVT::v2i16, Legal); + setIndexedLoadAction(ISD::POST_INC, MVT::v4i8, Legal); + setIndexedStoreAction(ISD::POST_INC, MVT::i8, Legal); + setIndexedStoreAction(ISD::POST_INC, MVT::i16, Legal); + setIndexedStoreAction(ISD::POST_INC, MVT::i32, Legal); + setIndexedStoreAction(ISD::POST_INC, MVT::v2i16, Legal); + setIndexedStoreAction(ISD::POST_INC, MVT::v4i8, Legal); + } + setBooleanContents(ZeroOrOneBooleanContent); + if (Subtarget.hasStdExtV()) { + setBooleanVectorContents(ZeroOrOneBooleanContent); + setOperationAction(ISD::VSCALE, XLenVT, Custom); + setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i8, Custom); + setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i16, Custom); + setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i8, Custom); + setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i16, Custom); + setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i32, Custom); + setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i32, Custom); + setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom); + if (Subtarget.is64Bit()) { + setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom); + setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom); + } + for (auto VT : MVT::integer_scalable_vector_valuetypes()) { + setOperationAction(ISD::SPLAT_VECTOR, VT, Legal); + setOperationAction(ISD::SMIN, VT, Legal); + setOperationAction(ISD::SMAX, VT, Legal); + setOperationAction(ISD::UMIN, VT, Legal); + setOperationAction(ISD::UMAX, VT, Legal); + setOperationAction(ISD::ROTL, VT, Expand); + setOperationAction(ISD::ROTR, VT, Expand); + if (isTypeLegal(VT)) { + setOperationAction(ISD::ANY_EXTEND, VT, Custom); + setOperationAction(ISD::SIGN_EXTEND, VT, Custom); + setOperationAction(ISD::ZERO_EXTEND, VT, Custom); + setOperationAction(ISD::TRUNCATE, VT, Custom); + setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); + setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); + } + } + if (!Subtarget.is64Bit()) { + setOperationAction(ISD::SPLAT_VECTOR, MVT::i64, Custom); + setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::i64, Custom); + setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::i64, Custom); + } + ISD::CondCode VFPCCToExpand[] = {ISD::SETO, ISD::SETONE, ISD::SETUEQ, ISD::SETUGT, ISD::SETUGE, ISD::SETULT, ISD::SETULE, ISD::SETUO, ISD::SETGT, ISD::SETOGT, ISD::SETGE, ISD::SETOGE, + }; + const auto SetCommonVFPActions = [&](MVT VT) { + setOperationAction(ISD::SPLAT_VECTOR, VT, Legal); + setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); + setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); + for (auto CC : VFPCCToExpand) + setCondCodeAction(CC, VT, Expand); + }; + if (Subtarget.hasStdExtZfh()) { + for (auto VT : {RISCVVMVTs::vfloat16mf4_t, RISCVVMVTs::vfloat16mf2_t, RISCVVMVTs::vfloat16m1_t, RISCVVMVTs::vfloat16m2_t, RISCVVMVTs::vfloat16m4_t, RISCVVMVTs::vfloat16m8_t}) + SetCommonVFPActions(VT); + } + if (Subtarget.hasStdExtF()) { + for (auto VT : {RISCVVMVTs::vfloat32mf2_t, RISCVVMVTs::vfloat32m1_t, RISCVVMVTs::vfloat32m2_t, RISCVVMVTs::vfloat32m4_t, RISCVVMVTs::vfloat32m8_t}) + SetCommonVFPActions(VT); + } + if (Subtarget.hasStdExtD()) { + for (auto VT : {RISCVVMVTs::vfloat64m1_t, RISCVVMVTs::vfloat64m2_t, RISCVVMVTs::vfloat64m4_t, RISCVVMVTs::vfloat64m8_t}) + SetCommonVFPActions(VT); + } + } + const Align FunctionAlignment(Subtarget.hasStdExtC() ? 2 : 4); + setMinFunctionAlignment(FunctionAlignment); + setPrefFunctionAlignment(FunctionAlignment); + setMinimumJumpTableEntries(5); + setJumpIsExpensive(); + setHasMultipleConditionRegisters(); + setTargetDAGCombine(ISD::SETCC); + if (Subtarget.hasStdExtZbp()) { + setTargetDAGCombine(ISD::OR); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/allowsMisalignedMemoryAccesses.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/allowsMisalignedMemoryAccesses.cpp new file mode 100644 index 0000000000000000000000000000000000000000..50fdd89b5836f6e98c8105fea915e478bd1d6d5f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/allowsMisalignedMemoryAccesses.cpp @@ -0,0 +1,9 @@ +bool RISCVTargetLowering::allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace = 0, unsigned Align = 1, MachineMemOperand::Flags Flags = MachineMemOperand::MONone, bool *Fast = nullptr) const { + if (Subtarget.hasPULPExtV2()) { + if (Fast) { + *Fast = false; + } + return true; + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/analyzeInputArgs.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/analyzeInputArgs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..48aa3497564c29edb79bfa481025bf26abae26e9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/analyzeInputArgs.cpp @@ -0,0 +1,191 @@ +void RISCVTargetLowering::analyzeInputArgs(MachineFunction &MF, CCState &CCInfo, const SmallVectorImpl &Ins, bool IsRet) const { + unsigned NumArgs = Ins.size(); + FunctionType *FType = MF.getFunction().getFunctionType(); + Optional FirstMaskArgument; + if (Subtarget.hasStdExtV()) { + FirstMaskArgument = None; + for (const auto &ArgIdx : enumerate(Args)) { + MVT ArgVT = ArgIdx.value().VT; + if (ArgVT.isScalableVector() && ArgVT.getVectorElementType().SimpleTy == MVT::i1) { + FirstMaskArgument = ArgIdx.index(); + } + } + } + for (unsigned i = 0; i != NumArgs; ++i) { + MVT ArgVT = Ins[i].VT; + ISD::ArgFlagsTy ArgFlags = Ins[i].Flags; + Type *ArgTy = nullptr; + if (IsRet) { + ArgTy = FType->getReturnType(); + } + else if (Ins[i].isOrigArg()) { + ArgTy = FType->getParamType(Ins[i].getOrigArgIndex()); + } + RISCVABI::ABI ABI = MF.getSubtarget().getTargetABI(); + unsigned XLen = DL.getLargestLegalIntTypeSizeInBits(); + assert(XLen == 32 || XLen == 64); + MVT XLenVT = XLen == 32 ? MVT::i32 : MVT::i64; + if (IsRet && ValNo > 1) { + return true; + } + bool UseGPRForF16_F32 = true; + bool UseGPRForF64 = true; + switch (ABI) { + default: + llvm_unreachable("Unexpected ABI"); + case RISCVABI::ABI_ILP32: + case RISCVABI::ABI_LP64: + break; + case RISCVABI::ABI_ILP32F: + case RISCVABI::ABI_LP64F: + UseGPRForF16_F32 = !IsFixed; + break; + case RISCVABI::ABI_ILP32D: + case RISCVABI::ABI_LP64D: + UseGPRForF16_F32 = !IsFixed; + UseGPRForF64 = !IsFixed; + break; + } + if (State.getFirstUnallocated(ArgFPR32s) == array_lengthof(ArgFPR32s)) { + UseGPRForF16_F32 = true; + UseGPRForF64 = true; + } + if (UseGPRForF16_F32 && (ValVT == MVT::f16 || ValVT == MVT::f32)) { + LocVT = XLenVT; + LocInfo = CCValAssign::BCvt; + } + else if (UseGPRForF64 && XLen == 64 && ValVT == MVT::f64) { + LocVT = MVT::i64; + LocInfo = CCValAssign::BCvt; + } + unsigned TwoXLenInBytes = (2 * XLen) / 8; + if (!IsFixed && ArgFlags.getNonZeroOrigAlign() == TwoXLenInBytes && DL.getTypeAllocSize(OrigTy) == TwoXLenInBytes) { + unsigned RegIdx = State.getFirstUnallocated(ArgGPRs); + if (RegIdx != array_lengthof(ArgGPRs) && RegIdx % 2 == 1) { + State.AllocateReg(ArgGPRs); + } + } + SmallVectorImpl &PendingLocs = State.getPendingLocs(); + SmallVectorImpl &PendingArgFlags = State.getPendingArgFlags(); + assert(PendingLocs.size() == PendingArgFlags.size() && "PendingLocs and PendingArgFlags out of sync"); + if (UseGPRForF64 && XLen == 32 && ValVT == MVT::f64) { + assert(!ArgFlags.isSplit() && PendingLocs.empty() && "Can't lower f64 if it is split"); + Register Reg = State.AllocateReg(ArgGPRs); + LocVT = MVT::i32; + if (!Reg) { + unsigned StackOffset = State.AllocateStack(8, Align(8)); + State.addLoc(CCValAssign::getMem(ValNo, ValVT, StackOffset, LocVT, LocInfo)); + return false; + } + if (!State.AllocateReg(ArgGPRs)) { + State.AllocateStack(4, Align(4)); + } + State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); + return false; + } + if (ArgFlags.isSplit() || !PendingLocs.empty()) { + LocVT = XLenVT; + LocInfo = CCValAssign::Indirect; + PendingLocs.push_back(CCValAssign::getPending(ValNo, ValVT, LocVT, LocInfo)); + PendingArgFlags.push_back(ArgFlags); + if (!ArgFlags.isSplitEnd()) { + return false; + } + } + if (ArgFlags.isSplitEnd() && PendingLocs.size() <= 2) { + assert(PendingLocs.size() == 2 && "Unexpected PendingLocs.size()"); + CCValAssign VA = PendingLocs[0]; + ISD::ArgFlagsTy AF = PendingArgFlags[0]; + PendingLocs.clear(); + PendingArgFlags.clear(); + unsigned XLenInBytes = XLen / 8; + if (Register Reg = State.AllocateReg(ArgGPRs)) { + State.addLoc(CCValAssign::getReg(VA1.getValNo(), VA1.getValVT(), Reg, VA1.getLocVT(), CCValAssign::Full)); + } + else { + Align StackAlign = std::max(Align(XLenInBytes), ArgFlags1.getNonZeroOrigAlign()); + State.addLoc(CCValAssign::getMem(VA1.getValNo(), VA1.getValVT(), State.AllocateStack(XLenInBytes, StackAlign), VA1.getLocVT(), CCValAssign::Full)); + State.addLoc(CCValAssign::getMem(ValNo2, ValVT2, State.AllocateStack(XLenInBytes, Align(XLenInBytes)), LocVT2, CCValAssign::Full)); + return false; + } + if (Register Reg = State.AllocateReg(ArgGPRs)) { + State.addLoc(CCValAssign::getReg(ValNo2, ValVT2, Reg, LocVT2, CCValAssign::Full)); + } + else { + State.addLoc(CCValAssign::getMem(ValNo2, ValVT2, State.AllocateStack(XLenInBytes, Align(XLenInBytes)), LocVT2, CCValAssign::Full)); + } + return false; + } + Register Reg; + if (ValVT == MVT::f16 && !UseGPRForF16_F32) { + Reg = State.AllocateReg(ArgFPR16s); + } + else if (ValVT == MVT::f32 && !UseGPRForF16_F32) { + Reg = State.AllocateReg(ArgFPR32s); + } + else if (ValVT == MVT::f64 && !UseGPRForF64) { + Reg = State.AllocateReg(ArgFPR64s); + } + else if (ValVT.isScalableVector()) { + const TargetRegisterClass *RC = TLI.getRegClassFor(ValVT); + if (RC == &RISCV::VRRegClass) { + if (FirstMaskArgument.hasValue() && ValNo == FirstMaskArgument.getValue()) { + Reg = State.AllocateReg(RISCV::V0); + } + else { + Reg = State.AllocateReg(ArgVRs); + } + } + else if (RC == &RISCV::VRM2RegClass) { + Reg = State.AllocateReg(ArgVRM2s); + } + else if (RC == &RISCV::VRM4RegClass) { + Reg = State.AllocateReg(ArgVRM4s); + } + else if (RC == &RISCV::VRM8RegClass) { + Reg = State.AllocateReg(ArgVRM8s); + } + else { + llvm_unreachable("Unhandled class register for ValueType"); + } + if (!Reg) { + LocInfo = CCValAssign::Indirect; + Reg = State.AllocateReg(ArgGPRs); + LocVT = XLenVT; + } + } + else { + Reg = State.AllocateReg(ArgGPRs); + } + unsigned StackOffset = Reg ? 0 : State.AllocateStack(XLen / 8, Align(XLen / 8)); + if (!PendingLocs.empty()) { + assert(ArgFlags.isSplitEnd() && "Expected ArgFlags.isSplitEnd()"); + assert(PendingLocs.size() > 2 && "Unexpected PendingLocs.size()"); + for (auto &It : PendingLocs) { + if (Reg) + It.convertToReg(Reg); + else + It.convertToMem(StackOffset); + State.addLoc(It); + } + PendingLocs.clear(); + PendingArgFlags.clear(); + return false; + } + assert((!UseGPRForF16_F32 || !UseGPRForF64 || LocVT == XLenVT || (TLI.getSubtarget().hasStdExtV() && ValVT.isScalableVector())) && "Expected an XLenVT or scalable vector types at this stage"); + if (Reg) { + State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); + return false; + } + if (ValVT.isFloatingPoint()) { + LocVT = ValVT; + LocInfo = CCValAssign::Full; + } + State.addLoc(CCValAssign::getMem(ValNo, ValVT, StackOffset, LocVT, LocInfo)); + return false; + if (CC_RISCV(MF.getDataLayout(), ABI, i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo, true, IsRet, ArgTy, *this, FirstMaskArgument)) { + LLVM_DEBUG(dbgs() << "InputArg #" << i << " has unhandled type " << EVT(ArgVT).getEVTString() << '\n'); + llvm_unreachable(nullptr); + } + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/analyzeOutputArgs.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/analyzeOutputArgs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c2c9f60ce6caff0ffd02b84657be3bcebbdb39e5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/analyzeOutputArgs.cpp @@ -0,0 +1,184 @@ +void RISCVTargetLowering::analyzeOutputArgs(MachineFunction &MF, CCState &CCInfo, const SmallVectorImpl &Outs, bool IsRet, CallLoweringInfo *CLI) const { + unsigned NumArgs = Outs.size(); + Optional FirstMaskArgument; + if (Subtarget.hasStdExtV()) { + FirstMaskArgument = None; + for (const auto &ArgIdx : enumerate(Args)) { + MVT ArgVT = ArgIdx.value().VT; + if (ArgVT.isScalableVector() && ArgVT.getVectorElementType().SimpleTy == MVT::i1) { + FirstMaskArgument = ArgIdx.index(); + } + } + } + for (unsigned i = 0; i != NumArgs; i++) { + MVT ArgVT = Outs[i].VT; + ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; + Type *OrigTy = CLI ? CLI->getArgs()[Outs[i].OrigArgIndex].Ty : nullptr; + RISCVABI::ABI ABI = MF.getSubtarget().getTargetABI(); + unsigned XLen = DL.getLargestLegalIntTypeSizeInBits(); + assert(XLen == 32 || XLen == 64); + MVT XLenVT = XLen == 32 ? MVT::i32 : MVT::i64; + if (IsRet && ValNo > 1) { + return true; + } + bool UseGPRForF16_F32 = true; + bool UseGPRForF64 = true; + switch (ABI) { + default: + llvm_unreachable("Unexpected ABI"); + case RISCVABI::ABI_ILP32: + case RISCVABI::ABI_LP64: + break; + case RISCVABI::ABI_ILP32F: + case RISCVABI::ABI_LP64F: + UseGPRForF16_F32 = !IsFixed; + break; + case RISCVABI::ABI_ILP32D: + case RISCVABI::ABI_LP64D: + UseGPRForF16_F32 = !IsFixed; + UseGPRForF64 = !IsFixed; + break; + } + if (State.getFirstUnallocated(ArgFPR32s) == array_lengthof(ArgFPR32s)) { + UseGPRForF16_F32 = true; + UseGPRForF64 = true; + } + if (UseGPRForF16_F32 && (ValVT == MVT::f16 || ValVT == MVT::f32)) { + LocVT = XLenVT; + LocInfo = CCValAssign::BCvt; + } + else if (UseGPRForF64 && XLen == 64 && ValVT == MVT::f64) { + LocVT = MVT::i64; + LocInfo = CCValAssign::BCvt; + } + unsigned TwoXLenInBytes = (2 * XLen) / 8; + if (!IsFixed && ArgFlags.getNonZeroOrigAlign() == TwoXLenInBytes && DL.getTypeAllocSize(OrigTy) == TwoXLenInBytes) { + unsigned RegIdx = State.getFirstUnallocated(ArgGPRs); + if (RegIdx != array_lengthof(ArgGPRs) && RegIdx % 2 == 1) { + State.AllocateReg(ArgGPRs); + } + } + SmallVectorImpl &PendingLocs = State.getPendingLocs(); + SmallVectorImpl &PendingArgFlags = State.getPendingArgFlags(); + assert(PendingLocs.size() == PendingArgFlags.size() && "PendingLocs and PendingArgFlags out of sync"); + if (UseGPRForF64 && XLen == 32 && ValVT == MVT::f64) { + assert(!ArgFlags.isSplit() && PendingLocs.empty() && "Can't lower f64 if it is split"); + Register Reg = State.AllocateReg(ArgGPRs); + LocVT = MVT::i32; + if (!Reg) { + unsigned StackOffset = State.AllocateStack(8, Align(8)); + State.addLoc(CCValAssign::getMem(ValNo, ValVT, StackOffset, LocVT, LocInfo)); + return false; + } + if (!State.AllocateReg(ArgGPRs)) { + State.AllocateStack(4, Align(4)); + } + State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); + return false; + } + if (ArgFlags.isSplit() || !PendingLocs.empty()) { + LocVT = XLenVT; + LocInfo = CCValAssign::Indirect; + PendingLocs.push_back(CCValAssign::getPending(ValNo, ValVT, LocVT, LocInfo)); + PendingArgFlags.push_back(ArgFlags); + if (!ArgFlags.isSplitEnd()) { + return false; + } + } + if (ArgFlags.isSplitEnd() && PendingLocs.size() <= 2) { + assert(PendingLocs.size() == 2 && "Unexpected PendingLocs.size()"); + CCValAssign VA = PendingLocs[0]; + ISD::ArgFlagsTy AF = PendingArgFlags[0]; + PendingLocs.clear(); + PendingArgFlags.clear(); + unsigned XLenInBytes = XLen / 8; + if (Register Reg = State.AllocateReg(ArgGPRs)) { + State.addLoc(CCValAssign::getReg(VA1.getValNo(), VA1.getValVT(), Reg, VA1.getLocVT(), CCValAssign::Full)); + } + else { + Align StackAlign = std::max(Align(XLenInBytes), ArgFlags1.getNonZeroOrigAlign()); + State.addLoc(CCValAssign::getMem(VA1.getValNo(), VA1.getValVT(), State.AllocateStack(XLenInBytes, StackAlign), VA1.getLocVT(), CCValAssign::Full)); + State.addLoc(CCValAssign::getMem(ValNo2, ValVT2, State.AllocateStack(XLenInBytes, Align(XLenInBytes)), LocVT2, CCValAssign::Full)); + return false; + } + if (Register Reg = State.AllocateReg(ArgGPRs)) { + State.addLoc(CCValAssign::getReg(ValNo2, ValVT2, Reg, LocVT2, CCValAssign::Full)); + } + else { + State.addLoc(CCValAssign::getMem(ValNo2, ValVT2, State.AllocateStack(XLenInBytes, Align(XLenInBytes)), LocVT2, CCValAssign::Full)); + } + return false; + } + Register Reg; + if (ValVT == MVT::f16 && !UseGPRForF16_F32) { + Reg = State.AllocateReg(ArgFPR16s); + } + else if (ValVT == MVT::f32 && !UseGPRForF16_F32) { + Reg = State.AllocateReg(ArgFPR32s); + } + else if (ValVT == MVT::f64 && !UseGPRForF64) { + Reg = State.AllocateReg(ArgFPR64s); + } + else if (ValVT.isScalableVector()) { + const TargetRegisterClass *RC = TLI.getRegClassFor(ValVT); + if (RC == &RISCV::VRRegClass) { + if (FirstMaskArgument.hasValue() && ValNo == FirstMaskArgument.getValue()) { + Reg = State.AllocateReg(RISCV::V0); + } + else { + Reg = State.AllocateReg(ArgVRs); + } + } + else if (RC == &RISCV::VRM2RegClass) { + Reg = State.AllocateReg(ArgVRM2s); + } + else if (RC == &RISCV::VRM4RegClass) { + Reg = State.AllocateReg(ArgVRM4s); + } + else if (RC == &RISCV::VRM8RegClass) { + Reg = State.AllocateReg(ArgVRM8s); + } + else { + llvm_unreachable("Unhandled class register for ValueType"); + } + if (!Reg) { + LocInfo = CCValAssign::Indirect; + Reg = State.AllocateReg(ArgGPRs); + LocVT = XLenVT; + } + } + else { + Reg = State.AllocateReg(ArgGPRs); + } + unsigned StackOffset = Reg ? 0 : State.AllocateStack(XLen / 8, Align(XLen / 8)); + if (!PendingLocs.empty()) { + assert(ArgFlags.isSplitEnd() && "Expected ArgFlags.isSplitEnd()"); + assert(PendingLocs.size() > 2 && "Unexpected PendingLocs.size()"); + for (auto &It : PendingLocs) { + if (Reg) + It.convertToReg(Reg); + else + It.convertToMem(StackOffset); + State.addLoc(It); + } + PendingLocs.clear(); + PendingArgFlags.clear(); + return false; + } + assert((!UseGPRForF16_F32 || !UseGPRForF64 || LocVT == XLenVT || (TLI.getSubtarget().hasStdExtV() && ValVT.isScalableVector())) && "Expected an XLenVT or scalable vector types at this stage"); + if (Reg) { + State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); + return false; + } + if (ValVT.isFloatingPoint()) { + LocVT = ValVT; + LocInfo = CCValAssign::Full; + } + State.addLoc(CCValAssign::getMem(ValNo, ValVT, StackOffset, LocVT, LocInfo)); + return false; + if (CC_RISCV(MF.getDataLayout(), ABI, i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo, Outs[i].IsFixed, IsRet, OrigTy, *this, FirstMaskArgument)) { + LLVM_DEBUG(dbgs() << "OutputArg #" << i << " has unhandled type " << EVT(ArgVT).getEVTString() << "\n"); + llvm_unreachable(nullptr); + } + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/computeKnownBitsForTargetNode.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/computeKnownBitsForTargetNode.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cb60f440f2c3d49c6bd08e043910840c8c738be3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/computeKnownBitsForTargetNode.cpp @@ -0,0 +1,27 @@ +void RISCVTargetLowering::computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const { + KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0); + APInt KnownZero2; + APInt KnownOne2; + unsigned BitWidth = Known.getBitWidth(); + unsigned Opc = Op.getOpcode(); + EVT VT = Op.getValueType(); + assert((Opc >= ISD::BUILTIN_OP_END || Opc == ISD::INTRINSIC_WO_CHAIN || Opc == ISD::INTRINSIC_W_CHAIN || Opc == ISD::INTRINSIC_VOID) && "Should use MaskedValueIsZero if you don't know whether Op is a target node!"); + Known.resetAll(); + if (Op.getOpcode() == RISCVISD::REMUW) { + KnownBits Known2; + Known = DAG.computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1); + Known2 = DAG.computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1); + Known = KnownBits::urem(Known.trunc(32), Known2.trunc(32)); + Known = Known.sext(BitWidth); + } + if (Op.getOpcode() == RISCVISD::DIVUW) { + KnownBits Known2; + Known = DAG.computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1); + Known2 = DAG.computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1); + Known = KnownBits::udiv(Known.trunc(32), Known2.trunc(32)); + Known = Known.sext(BitWidth); + } + if (Op.getOpcode() == RISCVISD::READ_VLENB) { + Known.Zero.setLowBits(3); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/convertSelectOfConstantsToMath.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/convertSelectOfConstantsToMath.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c1bfd4ff9c0142d140fa2d0204586a61289d84a5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/convertSelectOfConstantsToMath.cpp @@ -0,0 +1,3 @@ +bool convertSelectOfConstantsToMath(EVT VT) const override { + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/convertSetCCLogicToBitwiseLogic.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/convertSetCCLogicToBitwiseLogic.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e3721be5b16c34bcd975aeae2f4dce484d080226 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/convertSetCCLogicToBitwiseLogic.cpp @@ -0,0 +1,3 @@ +bool convertSetCCLogicToBitwiseLogic(EVT VT) const override { + return VT.isScalarInteger(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/decomposeMulByConstant.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/decomposeMulByConstant.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8a5c7fcf9043b0cab2a9beb5f9f97e9405099052 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/decomposeMulByConstant.cpp @@ -0,0 +1,24 @@ +bool RISCVTargetLowering::decomposeMulByConstant(LLVMContext &Context, EVT VT, SDValue C) const { + if (!VT.isScalarInteger()) { + return false; + } + if (Subtarget.hasStdExtM() && VT.getSizeInBits() > Subtarget.getXLen()) { + return false; + } + if (auto *ConstNode = dyn_cast(C.getNode())) { + const APInt &Imm = ConstNode->getAPIntValue(); + if ((Imm + 1).isPowerOf2() || (Imm - 1).isPowerOf2() || (1 - Imm).isPowerOf2() || (-1 - Imm).isPowerOf2()) { + return true; + } + if (Subtarget.hasStdExtM() && VT.getSizeInBits() >= Subtarget.getXLen()) { + return false; + } + if (!Imm.isSignedIntN(12) && Imm.countTrailingZeros() < 12) { + APInt ImmS = Imm.ashr(Imm.countTrailingZeros()); + if ((ImmS + 1).isPowerOf2() || (ImmS - 1).isPowerOf2() || (1 - ImmS).isPowerOf2()) { + return true; + } + } + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/emitLeadingFence.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/emitLeadingFence.cpp new file mode 100644 index 0000000000000000000000000000000000000000..509c7a0e3f0b5b7d1c9ddc616ed049a5f0648f15 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/emitLeadingFence.cpp @@ -0,0 +1,9 @@ +Instruction *RISCVTargetLowering::emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst, AtomicOrdering Ord) const { + if (isa(Inst) && Ord == AtomicOrdering::SequentiallyConsistent) { + return Builder.CreateFence(Ord); + } + if (isa(Inst) && isReleaseOrStronger(Ord)) { + return Builder.CreateFence(AtomicOrdering::Release); + } + return nullptr; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/emitMaskedAtomicCmpXchgIntrinsic.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/emitMaskedAtomicCmpXchgIntrinsic.cpp new file mode 100644 index 0000000000000000000000000000000000000000..abfa250a03dc885e387fa3aca22d89acdc995376 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/emitMaskedAtomicCmpXchgIntrinsic.cpp @@ -0,0 +1,18 @@ +Value *RISCVTargetLowering::emitMaskedAtomicCmpXchgIntrinsic(IRBuilder<> &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const { + unsigned XLen = Subtarget.getXLen(); + Value *Ordering = Builder.getIntN(XLen, static_cast(Ord)); + Intrinsic::ID CmpXchgIntrID = Intrinsic::riscv_masked_cmpxchg_i32; + if (XLen == 64) { + CmpVal = Builder.CreateSExt(CmpVal, Builder.getInt64Ty()); + NewVal = Builder.CreateSExt(NewVal, Builder.getInt64Ty()); + Mask = Builder.CreateSExt(Mask, Builder.getInt64Ty()); + CmpXchgIntrID = Intrinsic::riscv_masked_cmpxchg_i64; + } + Type *Tys[] = {AlignedAddr->getType()}; + Function *MaskedCmpXchg = Intrinsic::getDeclaration(CI->getModule(), CmpXchgIntrID, Tys); + Value *Result = Builder.CreateCall(MaskedCmpXchg, {AlignedAddr, CmpVal, NewVal, Mask, Ordering}); + if (XLen == 64) { + Result = Builder.CreateTrunc(Result, Builder.getInt32Ty()); + } + return Result; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/emitMaskedAtomicRMWIntrinsic.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/emitMaskedAtomicRMWIntrinsic.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c3ee2d975b835746f82a0da490b18a4385d0a50f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/emitMaskedAtomicRMWIntrinsic.cpp @@ -0,0 +1,70 @@ +Value *RISCVTargetLowering::emitMaskedAtomicRMWIntrinsic(IRBuilder<> &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const { + unsigned XLen = Subtarget.getXLen(); + Value *Ordering = Builder.getIntN(XLen, static_cast(AI->getOrdering())); + Type *Tys[] = {AlignedAddr->getType()}; + Function *LrwOpScwLoop = Intrinsic::getDeclaration(AI->getModule(), getIntrinsicForMaskedAtomicRMWBinOp(XLen, AI->getOperation()), Tys); + if (XLen == 32) { + switch (BinOp) { + default: + llvm_unreachable("Unexpected AtomicRMW BinOp"); + case AtomicRMWInst::Xchg: + return Intrinsic::riscv_masked_atomicrmw_xchg_i32; + case AtomicRMWInst::Add: + return Intrinsic::riscv_masked_atomicrmw_add_i32; + case AtomicRMWInst::Sub: + return Intrinsic::riscv_masked_atomicrmw_sub_i32; + case AtomicRMWInst::Nand: + return Intrinsic::riscv_masked_atomicrmw_nand_i32; + case AtomicRMWInst::Max: + return Intrinsic::riscv_masked_atomicrmw_max_i32; + case AtomicRMWInst::Min: + return Intrinsic::riscv_masked_atomicrmw_min_i32; + case AtomicRMWInst::UMax: + return Intrinsic::riscv_masked_atomicrmw_umax_i32; + case AtomicRMWInst::UMin: + return Intrinsic::riscv_masked_atomicrmw_umin_i32; + } + } + if (XLen == 64) { + switch (BinOp) { + default: + llvm_unreachable("Unexpected AtomicRMW BinOp"); + case AtomicRMWInst::Xchg: + return Intrinsic::riscv_masked_atomicrmw_xchg_i64; + case AtomicRMWInst::Add: + return Intrinsic::riscv_masked_atomicrmw_add_i64; + case AtomicRMWInst::Sub: + return Intrinsic::riscv_masked_atomicrmw_sub_i64; + case AtomicRMWInst::Nand: + return Intrinsic::riscv_masked_atomicrmw_nand_i64; + case AtomicRMWInst::Max: + return Intrinsic::riscv_masked_atomicrmw_max_i64; + case AtomicRMWInst::Min: + return Intrinsic::riscv_masked_atomicrmw_min_i64; + case AtomicRMWInst::UMax: + return Intrinsic::riscv_masked_atomicrmw_umax_i64; + case AtomicRMWInst::UMin: + return Intrinsic::riscv_masked_atomicrmw_umin_i64; + } + } + llvm_unreachable("Unexpected XLen\n"); + if (XLen == 64) { + Incr = Builder.CreateSExt(Incr, Builder.getInt64Ty()); + Mask = Builder.CreateSExt(Mask, Builder.getInt64Ty()); + ShiftAmt = Builder.CreateSExt(ShiftAmt, Builder.getInt64Ty()); + } + Value *Result; + if (AI->getOperation() == AtomicRMWInst::Min || AI->getOperation() == AtomicRMWInst::Max) { + const DataLayout &DL = AI->getModule()->getDataLayout(); + unsigned ValWidth = DL.getTypeStoreSizeInBits(AI->getValOperand()->getType()); + Value *SextShamt = Builder.CreateSub(Builder.getIntN(XLen, XLen - ValWidth), ShiftAmt); + Result = Builder.CreateCall(LrwOpScwLoop, {AlignedAddr, Incr, Mask, SextShamt, Ordering}); + } + else { + Result = Builder.CreateCall(LrwOpScwLoop, {AlignedAddr, Incr, Mask, Ordering}); + } + if (XLen == 64) { + Result = Builder.CreateTrunc(Result, Builder.getInt32Ty()); + } + return Result; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/emitTrailingFence.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/emitTrailingFence.cpp new file mode 100644 index 0000000000000000000000000000000000000000..787eeb8fc972fa00907f61c8d38b99dc41fd1fb5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/emitTrailingFence.cpp @@ -0,0 +1,8 @@ +Instruction *RISCVTargetLowering::emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst, AtomicOrdering Ord) const { + if (isAcquireOrStronger(Ord)) { + if (isa(Inst)) { + return Builder.CreateFence(AtomicOrdering::Acquire); + } + } + return nullptr; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/getAddr.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/getAddr.cpp new file mode 100644 index 0000000000000000000000000000000000000000..45b896e36009000a6701f992a091e5a60a139227 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/getAddr.cpp @@ -0,0 +1,25 @@ +template SDValue RISCVTargetLowering::getAddr(NodeTy *N, SelectionDAG &DAG, bool IsLocal) const { + SDLoc DL(N); + EVT Ty = getPointerTy(DAG.getDataLayout()); + if (isPositionIndependent()) { + SDValue Addr = getTargetNode(N, DL, Ty, DAG, 0); + if (IsLocal) { + return SDValue(DAG.getMachineNode(RISCV::PseudoLLA, DL, Ty, Addr), 0); + } + return SDValue(DAG.getMachineNode(RISCV::PseudoLA, DL, Ty, Addr), 0); + } + switch (getTargetMachine().getCodeModel()) { + default: + report_fatal_error("Unsupported code model for lowering"); + case CodeModel::Small: { + SDValue AddrHi = getTargetNode(N, DL, Ty, DAG, RISCVII::MO_HI); + SDValue AddrLo = getTargetNode(N, DL, Ty, DAG, RISCVII::MO_LO); + SDValue MNHi = SDValue(DAG.getMachineNode(RISCV::LUI, DL, Ty, AddrHi), 0); + return SDValue(DAG.getMachineNode(RISCV::ADDI, DL, Ty, MNHi, AddrLo), 0); + } + case CodeModel::Medium: { + SDValue Addr = getTargetNode(N, DL, Ty, DAG, 0); + return SDValue(DAG.getMachineNode(RISCV::PseudoLLA, DL, Ty, Addr), 0); + } + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/getConstraintType.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/getConstraintType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..915131641ca5dd4cc6c2356db00e6fd67b5b82b8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/getConstraintType.cpp @@ -0,0 +1,17 @@ +RISCVTargetLowering::ConstraintType RISCVTargetLowering::getConstraintType(StringRef Constraint) const { + if (Constraint.size() == 1) { + switch (Constraint[0]) { + default: + break; + case 'f': + return C_RegisterClass; + case 'I': + case 'J': + case 'K': + return C_Immediate; + case 'A': + return C_Memory; + } + } + return TargetLowering::getConstraintType(Constraint); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/getDynamicTLSAddr.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/getDynamicTLSAddr.cpp new file mode 100644 index 0000000000000000000000000000000000000000..46ed5ac12e9f62e6e019a25294f0fc96f25d8f4d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/getDynamicTLSAddr.cpp @@ -0,0 +1,16 @@ +SDValue RISCVTargetLowering::getDynamicTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG) const { + SDLoc DL(N); + EVT Ty = getPointerTy(DAG.getDataLayout()); + IntegerType *CallTy = Type::getIntNTy(*DAG.getContext(), Ty.getSizeInBits()); + const GlobalValue *GV = N->getGlobal(); + SDValue Addr = DAG.getTargetGlobalAddress(GV, DL, Ty, 0, 0); + SDValue Load = SDValue(DAG.getMachineNode(RISCV::PseudoLA_TLS_GD, DL, Ty, Addr), 0); + ArgListTy Args; + ArgListEntry Entry; + Entry.Node = Load; + Entry.Ty = CallTy; + Args.push_back(Entry); + TargetLowering::CallLoweringInfo CLI(DAG); + CLI.setDebugLoc(DL).setChain(DAG.getEntryNode()).setLibCallee(CallingConv::C, CallTy, DAG.getExternalSymbol("__tls_get_addr", Ty), std::move(Args)); + return LowerCallTo(CLI).first; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/getExceptionPointerRegister.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/getExceptionPointerRegister.cpp new file mode 100644 index 0000000000000000000000000000000000000000..eb02e54d876a19eac0a9f798a894bdb8ad094aa6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/getExceptionPointerRegister.cpp @@ -0,0 +1,3 @@ +Register RISCVTargetLowering::getExceptionPointerRegister(const Constant *PersonalityFn) const { + return RISCV::X10; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/getExceptionSelectorRegister.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/getExceptionSelectorRegister.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d21248ae6b5a38fab11aef82cb88fdc8ad6f6150 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/getExceptionSelectorRegister.cpp @@ -0,0 +1,3 @@ +Register RISCVTargetLowering::getExceptionSelectorRegister(const Constant *PersonalityFn) const { + return RISCV::X11; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/getExtendForAtomicCmpSwapArg.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/getExtendForAtomicCmpSwapArg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4fbe6c054b9796da3f9e9476976964f562a3e55a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/getExtendForAtomicCmpSwapArg.cpp @@ -0,0 +1,3 @@ +ISD::NodeType getExtendForAtomicCmpSwapArg() const override { + return ISD::SIGN_EXTEND; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/getExtendForAtomicOps.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/getExtendForAtomicOps.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8115491be720522f593d5b6c220ecf0659c42759 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/getExtendForAtomicOps.cpp @@ -0,0 +1,3 @@ +ISD::NodeType getExtendForAtomicOps() const override { + return ISD::SIGN_EXTEND; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/getInlineAsmMemConstraint.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/getInlineAsmMemConstraint.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b639b42ebb4b943ce1428b84bd6d6574cc675104 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/getInlineAsmMemConstraint.cpp @@ -0,0 +1,11 @@ +unsigned RISCVTargetLowering::getInlineAsmMemConstraint(StringRef ConstraintCode) const { + if (ConstraintCode.size() == 1) { + switch (ConstraintCode[0]) { + case 'A': + return InlineAsm::Constraint_A; + default: + break; + } + } + return TargetLowering::getInlineAsmMemConstraint(ConstraintCode); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/getPointerMemTy.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/getPointerMemTy.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4ac4daeba93b2ffd55e6fd6f2b28fe3ddeae1fc4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/getPointerMemTy.cpp @@ -0,0 +1,6 @@ +MVT RISCVTargetLowering::getPointerMemTy(const DataLayout &DL, uint32_t AS) const { + if(AS == UINT32_MAX) { + AS = 0; + } + return MVT::getIntegerVT(DL.getPointerSizeInBits(AS)); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/getPointerTy.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/getPointerTy.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a08da433397b663a71351d0e0cf4256e93e59c50 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/getPointerTy.cpp @@ -0,0 +1,6 @@ +MVT RISCVTargetLowering::getPointerTy(const DataLayout &DL, uint32_t AS) const { + if(AS == UINT32_MAX) { + AS = 0; + } + return MVT::getIntegerVT(DL.getPointerSizeInBits(AS)); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/getPostIndexedAddressParts.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/getPostIndexedAddressParts.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f62882d4b32f0dbd1cfa5c8669256a54ab3259d0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/getPostIndexedAddressParts.cpp @@ -0,0 +1,35 @@ + +bool RISCVTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const { + EVT VT; + SDValue BaseFromLDST; + if (LoadSDNode *LD = dyn_cast(N)) { + VT = LD->getMemoryVT(); + BaseFromLDST = LD->getBasePtr(); + } + else if (StoreSDNode *ST = dyn_cast(N)) { + BaseFromLDST = ST->getBasePtr(); + VT = ST->getMemoryVT(); + } + else { + return false; + } + if (Op->getOpcode() == ISD::ADD) { + AM = ISD::POST_INC; + Base = Op->getOperand(0); + Offset = Op->getOperand(1); + if (BaseFromLDST != Base && BaseFromLDST == Offset) { + std::swap(Base, Offset); + } + if (!(VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32)) { + return false; + } + if (ConstantSDNode *ConstOffset = dyn_cast(Offset)) { + uint64_t imm = ConstOffset->getZExtValue(); + if (!isInt<12>(imm)) { + return false; + } + } + return BaseFromLDST == Base; + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/getRegForInlineAsmConstraint.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/getRegForInlineAsmConstraint.cpp new file mode 100644 index 0000000000000000000000000000000000000000..700e248e4992dd8745c5e6bbf6198c37e1d39e67 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/getRegForInlineAsmConstraint.cpp @@ -0,0 +1,349 @@ +std::pair RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const { + if (Constraint.size() == 1) { + if (Constraint[0] == 'r') { + return std::make_pair(0U, &RISCV::GPRRegClass); + } + if (Constraint[0] == 'f') { + if (Subtarget.hasStdExtF()) { + if (VT == MVT::f32) { + return std::make_pair(0U, &RISCV::FPR32RegClass); + } + } + if (Subtarget.hasStdExtD()) { + if (VT == MVT::f64) { + return std::make_pair(0U, &RISCV::FPR64RegClass); + } + } + if (Subtarget.hasStdExtZfh()) { + if (VT == MVT::f16) { + return std::make_pair(0U, &RISCV::FPR16RegClass); + } + } + if (Subtarget.hasStdExtXSmallfloat()) { + if (VT == MVT::v2f32) { + return std::make_pair(0U, &RISCV::FPR64RegClass); + } + if (VT == MVT::v4f16) { + return std::make_pair(0U, &RISCV::FPR64RegClass); + } + if (VT == MVT::v4bf16) { + return std::make_pair(0U, &RISCV::FPR64RegClass); + } + if (VT == MVT::v4i16) { + return std::make_pair(0U, &RISCV::FPR64RegClass); + } + if (VT == MVT::v8i8) { + return std::make_pair(0U, &RISCV::FPR64RegClass); + } + } + } + } + unsigned XRegFromAlias = RISCV::NoRegister; + if (Constraint.lower() == "{zero}") { + XRegFromAlias = RISCV::X0; + } + if (Constraint.lower() == "{ra}") { + XRegFromAlias = RISCV::X1; + } + if (Constraint.lower() == "{sp}") { + XRegFromAlias = RISCV::X2; + } + if (Constraint.lower() == "{gp}") { + XRegFromAlias = RISCV::X3; + } + if (Constraint.lower() == "{tp}") { + XRegFromAlias = RISCV::X4; + } + if (Constraint.lower() == "{t0}") { + XRegFromAlias = RISCV::X5; + } + if (Constraint.lower() == "{t1}") { + XRegFromAlias = RISCV::X6; + } + if (Constraint.lower() == "{t2}") { + XRegFromAlias = RISCV::X7; + } + if (Constraint.lower() == "{s0}") { + XRegFromAlias = RISCV::X8; + } + if (Constraint.lower() == "{fp}") { + XRegFromAlias = RISCV::X8; + } + if (Constraint.lower() == "{s1}") { + XRegFromAlias = RISCV::X9; + } + if (Constraint.lower() == "{a0}") { + XRegFromAlias = RISCV::X10; + } + if (Constraint.lower() == "{a1}") { + XRegFromAlias = RISCV::X11; + } + if (Constraint.lower() == "{a2}") { + XRegFromAlias = RISCV::X12; + } + if (Constraint.lower() == "{a3}") { + XRegFromAlias = RISCV::X13; + } + if (Constraint.lower() == "{a4}") { + XRegFromAlias = RISCV::X14; + } + if (Constraint.lower() == "{a5}") { + XRegFromAlias = RISCV::X15; + } + if (Constraint.lower() == "{a6}") { + XRegFromAlias = RISCV::X16; + } + if (Constraint.lower() == "{a7}") { + XRegFromAlias = RISCV::X17; + } + if (Constraint.lower() == "{s2}") { + XRegFromAlias = RISCV::X18; + } + if (Constraint.lower() == "{s3}") { + XRegFromAlias = RISCV::X19; + } + if (Constraint.lower() == "{s4}") { + XRegFromAlias = RISCV::X20; + } + if (Constraint.lower() == "{s5}") { + XRegFromAlias = RISCV::X21; + } + if (Constraint.lower() == "{s6}") { + XRegFromAlias = RISCV::X22; + } + if (Constraint.lower() == "{s7}") { + XRegFromAlias = RISCV::X23; + } + if (Constraint.lower() == "{s8}") { + XRegFromAlias = RISCV::X24; + } + if (Constraint.lower() == "{s9}") { + XRegFromAlias = RISCV::X25; + } + if (Constraint.lower() == "{s10}") { + XRegFromAlias = RISCV::X26; + } + if (Constraint.lower() == "{s11}") { + XRegFromAlias = RISCV::X27; + } + if (Constraint.lower() == "{t3}") { + XRegFromAlias = RISCV::X28; + } + if (Constraint.lower() == "{t4}") { + XRegFromAlias = RISCV::X29; + } + if (Constraint.lower() == "{t5}") { + XRegFromAlias = RISCV::X30; + } + if (Constraint.lower() == "{t6}") { + XRegFromAlias = RISCV::X31; + } + if (XRegFromAlias != RISCV::NoRegister) { + return std::make_pair(XRegFromAlias, &RISCV::GPRRegClass); + } + if (Subtarget.hasStdExtF()) { + unsigned FReg = RISCV::NoRegister; + if (Constraint.lower() == "{f0}") { + FReg = RISCV::F0_F; + } + if (Constraint.lower() == "{ft0}") { + FReg = RISCV::F0_F; + } + if (Constraint.lower() == "{f1}") { + FReg = RISCV::F1_F; + } + if (Constraint.lower() == "{ft1}") { + FReg = RISCV::F1_F; + } + if (Constraint.lower() == "{f2}") { + FReg = RISCV::F2_F; + } + if (Constraint.lower() == "{ft2}") { + FReg = RISCV::F2_F; + } + if (Constraint.lower() == "{f3}") { + FReg = RISCV::F3_F; + } + if (Constraint.lower() == "{ft3}") { + FReg = RISCV::F3_F; + } + if (Constraint.lower() == "{f4}") { + FReg = RISCV::F4_F; + } + if (Constraint.lower() == "{ft4}") { + FReg = RISCV::F4_F; + } + if (Constraint.lower() == "{f5}") { + FReg = RISCV::F5_F; + } + if (Constraint.lower() == "{ft5}") { + FReg = RISCV::F5_F; + } + if (Constraint.lower() == "{f6}") { + FReg = RISCV::F6_F; + } + if (Constraint.lower() == "{ft6}") { + FReg = RISCV::F6_F; + } + if (Constraint.lower() == "{f7}") { + FReg = RISCV::F7_F; + } + if (Constraint.lower() == "{ft7}") { + FReg = RISCV::F7_F; + } + if (Constraint.lower() == "{f8}") { + FReg = RISCV::F8_F; + } + if (Constraint.lower() == "{ft8}") { + FReg = RISCV::F8_F; + } + if (Constraint.lower() == "{f9}") { + FReg = RISCV::F9_F; + } + if (Constraint.lower() == "{ft9}") { + FReg = RISCV::F9_F; + } + if (Constraint.lower() == "{f10}") { + FReg = RISCV::F10_F; + } + if (Constraint.lower() == "{ft10}") { + FReg = RISCV::F10_F; + } + if (Constraint.lower() == "{f11}") { + FReg = RISCV::F11_F; + } + if (Constraint.lower() == "{ft11}") { + FReg = RISCV::F11_F; + } + if (Constraint.lower() == "{f12}") { + FReg = RISCV::F12_F; + } + if (Constraint.lower() == "{ft12}") { + FReg = RISCV::F12_F; + } + if (Constraint.lower() == "{f13}") { + FReg = RISCV::F13_F; + } + if (Constraint.lower() == "{ft13}") { + FReg = RISCV::F13_F; + } + if (Constraint.lower() == "{f14}") { + FReg = RISCV::F14_F; + } + if (Constraint.lower() == "{ft14}") { + FReg = RISCV::F14_F; + } + if (Constraint.lower() == "{f15}") { + FReg = RISCV::F15_F; + } + if (Constraint.lower() == "{ft15}") { + FReg = RISCV::F15_F; + } + if (Constraint.lower() == "{f16}") { + FReg = RISCV::F16_F; + } + if (Constraint.lower() == "{ft16}") { + FReg = RISCV::F16_F; + } + if (Constraint.lower() == "{f17}") { + FReg = RISCV::F17_F; + } + if (Constraint.lower() == "{ft17}") { + FReg = RISCV::F17_F; + } + if (Constraint.lower() == "{f18}") { + FReg = RISCV::F18_F; + } + if (Constraint.lower() == "{ft18}") { + FReg = RISCV::F18_F; + } + if (Constraint.lower() == "{f19}") { + FReg = RISCV::F19_F; + } + if (Constraint.lower() == "{ft19}") { + FReg = RISCV::F19_F; + } + if (Constraint.lower() == "{f20}") { + FReg = RISCV::F20_F; + } + if (Constraint.lower() == "{ft20}") { + FReg = RISCV::F20_F; + } + if (Constraint.lower() == "{f21}") { + FReg = RISCV::F21_F; + } + if (Constraint.lower() == "{ft21}") { + FReg = RISCV::F21_F; + } + if (Constraint.lower() == "{f22}") { + FReg = RISCV::F22_F; + } + if (Constraint.lower() == "{ft22}") { + FReg = RISCV::F22_F; + } + if (Constraint.lower() == "{f23}") { + FReg = RISCV::F23_F; + } + if (Constraint.lower() == "{ft23}") { + FReg = RISCV::F23_F; + } + if (Constraint.lower() == "{f24}") { + FReg = RISCV::F24_F; + } + if (Constraint.lower() == "{ft24}") { + FReg = RISCV::F24_F; + } + if (Constraint.lower() == "{f25}") { + FReg = RISCV::F25_F; + } + if (Constraint.lower() == "{ft25}") { + FReg = RISCV::F25_F; + } + if (Constraint.lower() == "{f26}") { + FReg = RISCV::F26_F; + } + if (Constraint.lower() == "{ft26}") { + FReg = RISCV::F26_F; + } + if (Constraint.lower() == "{f27}") { + FReg = RISCV::F27_F; + } + if (Constraint.lower() == "{ft27}") { + FReg = RISCV::F27_F; + } + if (Constraint.lower() == "{f28}") { + FReg = RISCV::F28_F; + } + if (Constraint.lower() == "{ft28}") { + FReg = RISCV::F28_F; + } + if (Constraint.lower() == "{f29}") { + FReg = RISCV::F29_F; + } + if (Constraint.lower() == "{ft29}") { + FReg = RISCV::F29_F; + } + if (Constraint.lower() == "{f30}") { + FReg = RISCV::F30_F; + } + if (Constraint.lower() == "{ft30}") { + FReg = RISCV::F30_F; + } + if (Constraint.lower() == "{f31}") { + FReg = RISCV::F31_F; + } + if (Constraint.lower() == "{ft31}") { + FReg = RISCV::F31_F; + } + if (FReg != RISCV::NoRegister) { + assert(RISCV::F0_32 <= FReg && FReg <= RISCV::F31_32 && "Unknown fp-reg"); + if (Subtarget.hasStdExtD()) { + unsigned RegNo = FReg - RISCV::F0_F; + unsigned DReg = RISCV::F0_D + RegNo; + return std::make_pair(DReg, &RISCV::FPR64RegClass); + } + return std::make_pair(FReg, &RISCV::FPR32RegClass); + } + } + return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/getRegisterByName.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/getRegisterByName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..26ad342c7f779b295cd18cd28b9b3f8724c1896c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/getRegisterByName.cpp @@ -0,0 +1,14 @@ +Register RISCVTargetLowering::getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const { + Register Reg = MatchRegisterAltName(RegName); + if (Reg == RISCV::NoRegister) { + Reg = MatchRegisterName(RegName); + } + if (Reg == RISCV::NoRegister) { + report_fatal_error(Twine("Invalid register name \"" + StringRef(RegName) + "\".")); + } + BitVector ReservedRegs = Subtarget.getRegisterInfo()->getReservedRegs(MF); + if (!ReservedRegs.test(Reg) && !Subtarget.isRegisterReservedByUser(Reg)) { + report_fatal_error(Twine("Trying to obtain non-reserved register \"" + StringRef(RegName) + "\".")); + } + return Reg; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/getScalarShiftAmountTy.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/getScalarShiftAmountTy.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b4d550679f775347d981c7222c64f2be8cc69841 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/getScalarShiftAmountTy.cpp @@ -0,0 +1,3 @@ +MVT RISCVTargetLowering::getScalarShiftAmountTy(const DataLayout &DL, EVT) const { + return Subtarget.getXLenVT(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/getSetCCResultType.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/getSetCCResultType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ca330ad9133ea7d3b3682e5e651961f59d6709eb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/getSetCCResultType.cpp @@ -0,0 +1,9 @@ +EVT RISCVTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &, EVT VT) const { + if (!VT.isVector()) { + return getPointerTy(DL); + } + if (Subtarget.hasStdExtV()) { + return MVT::getVectorVT(MVT::i1, VT.getVectorElementCount()); + } + return VT.changeVectorElementTypeToInteger(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/getStaticTLSAddr.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/getStaticTLSAddr.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8f231109058dae006fecd5590954e0a119396b49 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/getStaticTLSAddr.cpp @@ -0,0 +1,19 @@ +SDValue RISCVTargetLowering::getStaticTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG, bool UseGOT) const { + SDLoc DL(N); + EVT Ty = getPointerTy(DAG.getDataLayout()); + const GlobalValue *GV = N->getGlobal(); + MVT XLenVT = Subtarget.getXLenVT(); + if (UseGOT) { + SDValue Addr = DAG.getTargetGlobalAddress(GV, DL, Ty, 0, 0); + SDValue Load = SDValue(DAG.getMachineNode(RISCV::PseudoLA_TLS_IE, DL, Ty, Addr), 0); + SDValue TPReg = DAG.getRegister(RISCV::X4, XLenVT); + return DAG.getNode(ISD::ADD, DL, Ty, Load, TPReg); + } + SDValue AddrHi = DAG.getTargetGlobalAddress(GV, DL, Ty, 0, RISCVII::MO_TPREL_HI); + SDValue AddrAdd = DAG.getTargetGlobalAddress(GV, DL, Ty, 0, RISCVII::MO_TPREL_ADD); + SDValue AddrLo = DAG.getTargetGlobalAddress(GV, DL, Ty, 0, RISCVII::MO_TPREL_LO); + SDValue MNHi = SDValue(DAG.getMachineNode(RISCV::LUI, DL, Ty, AddrHi), 0); + SDValue TPReg = DAG.getRegister(RISCV::X4, XLenVT); + SDValue MNAdd = SDValue(DAG.getMachineNode(RISCV::PseudoAddTPRel, DL, Ty, MNHi, TPReg, AddrAdd), 0); + return SDValue(DAG.getMachineNode(RISCV::ADDI, DL, Ty, MNAdd, AddrLo), 0); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/getSubtarget.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/getSubtarget.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4d7571dffca9b46bd58d715c218cba477a279eed --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/getSubtarget.cpp @@ -0,0 +1,3 @@ +const RISCVSubtarget &getSubtarget() const { + return Subtarget; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/getTargetNodeName.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/getTargetNodeName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d2af7ef3833346212519e245d5021adcd5b7b5c8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/getTargetNodeName.cpp @@ -0,0 +1,123 @@ +const char *RISCVTargetLowering::getTargetNodeName(unsigned Opcode) const { + if ((RISCVISD::NodeType)Opcode == RISCVISD::RET_FLAG) { + return "RISCVISD::RET_FLAG"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::URET_FLAG) { + return "RISCVISD::URET_FLAG"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::SRET_FLAG) { + return "RISCVISD::SRET_FLAG"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::MRET_FLAG) { + return "RISCVISD::MRET_FLAG"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::CALL) { + return "RISCVISD::CALL"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::SELECT_CC) { + return "RISCVISD::SELECT_CC"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::BuildPairF64) { + return "RISCVISD::BuildPairF64"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::SplitF64) { + return "RISCVISD::SplitF64"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::TAIL) { + return "RISCVISD::TAIL"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::FMV_X_ANYEXTH) { + return "RISCVISD::FMV_X_ANYEXTH"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::FMV_W_X_RV64) { + return "RISCVISD::FMV_W_X_RV64"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::FMV_X_ANYEXTW_RV64) { + return "RISCVISD::FMV_X_ANYEXTW_RV64"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::READ_CYCLE_WIDE) { + return "RISCVISD::READ_CYCLE_WIDE"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::GREVI) { + return "RISCVISD::GREVI"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::GREVIW) { + return "RISCVISD::GREVIW"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::GORCI) { + return "RISCVISD::GORCI"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::GORCIW) { + return "RISCVISD::GORCIW"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::VMV_X_S) { + return "RISCVISD::VMV_X_S"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::SPLAT_VECTOR_I64) { + return "RISCVISD::SPLAT_VECTOR_I64"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::READ_VLENB) { + return "RISCVISD::READ_VLENB"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::TRUNCATE_VECTOR) { + return "RISCVISD::TRUNCATE_VECTOR"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::VLEFF) { + return "RISCVISD::VLEFF"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::VLEFF_MASK) { + return "RISCVISD::VLEFF_MASK"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::VLSEGFF) { + return "RISCVISD::VLSEGFF"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::VLSEGFF_MASK) { + return "RISCVISD::VLSEGFF_MASK"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::READ_VL) { + return "RISCVISD::READ_VL"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::VSLIDEUP) { + return "RISCVISD::VSLIDEUP"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::VSLIDEDOWN) { + return "RISCVISD::VSLIDEDOWN"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::VID) { + return "RISCVISD::VID"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::FMV_H_X) { + return "RISCVISD::FMV_H_X"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::FSRW) { + return "RISCVISD::FSRW"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::FSLW) { + return "RISCVISD::FSLW"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::RORW) { + return "RISCVISD::RORW"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::ROLW) { + return "RISCVISD::ROLW"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::REMUW) { + return "RISCVISD::REMUW"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::DIVUW) { + return "RISCVISD::DIVUW"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::DIVW) { + return "RISCVISD::DIVW"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::SRLW) { + return "RISCVISD::SRLW"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::SRAW) { + return "RISCVISD::SRAW"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::SLLW) { + return "RISCVISD::SLLW"; + } + return nullptr; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/getTgtMemIntrinsic.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/getTgtMemIntrinsic.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4d8deda7d83d9f59a857e66fddd44324aa0de609 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/getTgtMemIntrinsic.cpp @@ -0,0 +1,93 @@ +bool RISCVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const { + if (Intrinsic == Intrinsic::riscv_masked_atomicrmw_xchg_i32) { + PointerType *PtrTy = cast(I.getArgOperand(0)->getType()); + Info.opc = ISD::INTRINSIC_W_CHAIN; + Info.memVT = MVT::getVT(PtrTy->getElementType()); + Info.ptrVal = I.getArgOperand(0); + Info.offset = 0; + Info.align = Align(4); + Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore | MachineMemOperand::MOVolatile; + return true; + } + if (Intrinsic == Intrinsic::riscv_masked_atomicrmw_add_i32) { + PointerType *PtrTy = cast(I.getArgOperand(0)->getType()); + Info.opc = ISD::INTRINSIC_W_CHAIN; + Info.memVT = MVT::getVT(PtrTy->getElementType()); + Info.ptrVal = I.getArgOperand(0); + Info.offset = 0; + Info.align = Align(4); + Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore | MachineMemOperand::MOVolatile; + return true; + } + if (Intrinsic == Intrinsic::riscv_masked_atomicrmw_sub_i32) { + PointerType *PtrTy = cast(I.getArgOperand(0)->getType()); + Info.opc = ISD::INTRINSIC_W_CHAIN; + Info.memVT = MVT::getVT(PtrTy->getElementType()); + Info.ptrVal = I.getArgOperand(0); + Info.offset = 0; + Info.align = Align(4); + Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore | MachineMemOperand::MOVolatile; + return true; + } + if (Intrinsic == Intrinsic::riscv_masked_atomicrmw_nand_i32) { + PointerType *PtrTy = cast(I.getArgOperand(0)->getType()); + Info.opc = ISD::INTRINSIC_W_CHAIN; + Info.memVT = MVT::getVT(PtrTy->getElementType()); + Info.ptrVal = I.getArgOperand(0); + Info.offset = 0; + Info.align = Align(4); + Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore | MachineMemOperand::MOVolatile; + return true; + } + if (Intrinsic == Intrinsic::riscv_masked_atomicrmw_max_i32) { + PointerType *PtrTy = cast(I.getArgOperand(0)->getType()); + Info.opc = ISD::INTRINSIC_W_CHAIN; + Info.memVT = MVT::getVT(PtrTy->getElementType()); + Info.ptrVal = I.getArgOperand(0); + Info.offset = 0; + Info.align = Align(4); + Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore | MachineMemOperand::MOVolatile; + return true; + } + if (Intrinsic == Intrinsic::riscv_masked_atomicrmw_min_i32) { + PointerType *PtrTy = cast(I.getArgOperand(0)->getType()); + Info.opc = ISD::INTRINSIC_W_CHAIN; + Info.memVT = MVT::getVT(PtrTy->getElementType()); + Info.ptrVal = I.getArgOperand(0); + Info.offset = 0; + Info.align = Align(4); + Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore | MachineMemOperand::MOVolatile; + return true; + } + if (Intrinsic == Intrinsic::riscv_masked_atomicrmw_umax_i32) { + PointerType *PtrTy = cast(I.getArgOperand(0)->getType()); + Info.opc = ISD::INTRINSIC_W_CHAIN; + Info.memVT = MVT::getVT(PtrTy->getElementType()); + Info.ptrVal = I.getArgOperand(0); + Info.offset = 0; + Info.align = Align(4); + Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore | MachineMemOperand::MOVolatile; + return true; + } + if (Intrinsic == Intrinsic::riscv_masked_atomicrmw_umin_i32) { + PointerType *PtrTy = cast(I.getArgOperand(0)->getType()); + Info.opc = ISD::INTRINSIC_W_CHAIN; + Info.memVT = MVT::getVT(PtrTy->getElementType()); + Info.ptrVal = I.getArgOperand(0); + Info.offset = 0; + Info.align = Align(4); + Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore | MachineMemOperand::MOVolatile; + return true; + } + if (Intrinsic == Intrinsic::riscv_masked_cmpxchg_i32) { + PointerType *PtrTy = cast(I.getArgOperand(0)->getType()); + Info.opc = ISD::INTRINSIC_W_CHAIN; + Info.memVT = MVT::getVT(PtrTy->getElementType()); + Info.ptrVal = I.getArgOperand(0); + Info.offset = 0; + Info.align = Align(4); + Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore | MachineMemOperand::MOVolatile; + return true; + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/hasBitPreservingFPLogic.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/hasBitPreservingFPLogic.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d1c41f213e055244de1922cb5a036fe323993663 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/hasBitPreservingFPLogic.cpp @@ -0,0 +1,3 @@ +bool RISCVTargetLowering::hasBitPreservingFPLogic(EVT VT) const { + return (VT == MVT::f16 && Subtarget.hasStdExtZfh()) || (VT == MVT::f32 && Subtarget.hasStdExtF()) || (VT == MVT::f64 && Subtarget.hasStdExtD()); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/isCheapToSpeculateCtlz.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/isCheapToSpeculateCtlz.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7d9f871f13e0b61779ec7b7ac0e64443ee06b43f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/isCheapToSpeculateCtlz.cpp @@ -0,0 +1,3 @@ +bool RISCVTargetLowering::isCheapToSpeculateCtlz() const { + return Subtarget.hasStdExtZbb(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/isCheapToSpeculateCttz.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/isCheapToSpeculateCttz.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d9a2e056622fab5c51755ed36e67138289278601 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/isCheapToSpeculateCttz.cpp @@ -0,0 +1,3 @@ +bool RISCVTargetLowering::isCheapToSpeculateCttz() const { + return Subtarget.hasStdExtZbb(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/isDesirableToCommuteWithShift.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/isDesirableToCommuteWithShift.cpp new file mode 100644 index 0000000000000000000000000000000000000000..972b11ab3501171966e3bfd4b96ec82355cbbcaa --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/isDesirableToCommuteWithShift.cpp @@ -0,0 +1,24 @@ +bool RISCVTargetLowering::isDesirableToCommuteWithShift(const SDNode *N, CombineLevel Level) const { + SDValue N0 = N->getOperand(0); + EVT Ty = N0.getValueType(); + if (Ty.isScalarInteger() && (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::OR)) { + auto *C1 = dyn_cast(N0->getOperand(1)); + auto *C2 = dyn_cast(N->getOperand(1)); + if (C1 && C2) { + const APInt &C1Int = C1->getAPIntValue(); + APInt ShiftedC1Int = C1Int << C2->getAPIntValue(); + if (ShiftedC1Int.getMinSignedBits() <= 64 && isLegalAddImmediate(ShiftedC1Int.getSExtValue())) { + return true; + } + if (C1Int.getMinSignedBits() <= 64 && isLegalAddImmediate(C1Int.getSExtValue())) { + return false; + } + int C1Cost = RISCVMatInt::getIntMatCost(C1Int, Ty.getSizeInBits(), Subtarget.is64Bit()); + int ShiftedC1Cost = RISCVMatInt::getIntMatCost(ShiftedC1Int, Ty.getSizeInBits(), Subtarget.is64Bit()); + if (C1Cost < ShiftedC1Cost) { + return false; + } + } + } + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/isEligibleForTailCallOptimization.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/isEligibleForTailCallOptimization.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4ade96d77d668102258fdfb941e8165d21a19205 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/isEligibleForTailCallOptimization.cpp @@ -0,0 +1,44 @@ + +bool RISCVTargetLowering::isEligibleForTailCallOptimization(CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF, const SmallVector &ArgLocs) const { + auto &Callee = CLI.Callee; + auto CalleeCC = CLI.CallConv; + auto &Outs = CLI.Outs; + auto &Caller = MF.getFunction(); + auto CallerCC = Caller.getCallingConv(); + if (Caller.hasFnAttribute("interrupt")) { + return false; + } + if (CCInfo.getNextStackOffset() != 0) { + return false; + } + for (auto &VA : ArgLocs) { + if (VA.getLocInfo() == CCValAssign::Indirect) { + return false; + } + } + auto IsCallerStructRet = Caller.hasStructRetAttr(); + auto IsCalleeStructRet = Outs.empty() ? false : Outs[0].Flags.isSRet(); + if (IsCallerStructRet || IsCalleeStructRet) { + return false; + } + if (GlobalAddressSDNode *G = dyn_cast(Callee)) { + const GlobalValue *GV = G->getGlobal(); + if (GV->hasExternalWeakLinkage()) { + return false; + } + } + const RISCVRegisterInfo *TRI = Subtarget.getRegisterInfo(); + const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC); + if (CalleeCC != CallerCC) { + const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC); + if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved)) { + return false; + } + } + for (auto &Arg : Outs) { + if (Arg.Flags.isByVal()) { + return false; + } + } + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/isFMAFasterThanFMulAndFAdd.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/isFMAFasterThanFMulAndFAdd.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2056d0ac4e9581359873184d0cedfb79ae3e2723 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/isFMAFasterThanFMulAndFAdd.cpp @@ -0,0 +1,17 @@ +bool RISCVTargetLowering::isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const { + VT = VT.getScalarType(); + if (!VT.isSimple()) { + return false; + } + switch (VT.getSimpleVT().SimpleTy) { + case MVT::f16: + return Subtarget.hasStdExtZfh(); + case MVT::f32: + return Subtarget.hasStdExtF(); + case MVT::f64: + return Subtarget.hasStdExtD(); + default: + break; + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/isFPImmLegal.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/isFPImmLegal.cpp new file mode 100644 index 0000000000000000000000000000000000000000..36936d70cb866640bf90c1d991e6af92243eec59 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/isFPImmLegal.cpp @@ -0,0 +1,21 @@ +bool RISCVTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const { + if (VT == MVT::f16) { + if (!Subtarget.hasStdExtZfh()) { + return false; + } + } + if (VT == MVT::f32) { + if (!Subtarget.hasStdExtF()) { + return false; + } + } + if (VT == MVT::f64) { + if (!Subtarget.hasStdExtD()) { + return false; + } + } + if (Imm.isNegZero()) { + return false; + } + return Imm.isZero(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/isLegalAddImmediate.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/isLegalAddImmediate.cpp new file mode 100644 index 0000000000000000000000000000000000000000..27342f01a75e9602e8823826937d056a8c10605f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/isLegalAddImmediate.cpp @@ -0,0 +1,3 @@ +bool RISCVTargetLowering::isLegalAddImmediate(int64_t Imm) const { + return isInt<12>(Imm); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/isLegalAddressingMode.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/isLegalAddressingMode.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c3fc00237148c4d20cfe2aea80e3a44e2f1aaad8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/isLegalAddressingMode.cpp @@ -0,0 +1,20 @@ +bool RISCVTargetLowering::isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I) const { + if (AM.BaseGV) { + return false; + } + if (!isInt<12>(AM.BaseOffs)) { + return false; + } + switch (AM.Scale) { + case 0: + break; + case 1: + if (!AM.HasBaseReg) { + break; + } + return false; + default: + return false; + } + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/isLegalICmpImmediate.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/isLegalICmpImmediate.cpp new file mode 100644 index 0000000000000000000000000000000000000000..50a187b1c95b0177261e158b1676e2eef2e5b294 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/isLegalICmpImmediate.cpp @@ -0,0 +1,3 @@ +bool RISCVTargetLowering::isLegalICmpImmediate(int64_t Imm) const { + return isInt<12>(Imm); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/isSExtCheaperThanZExt.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/isSExtCheaperThanZExt.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e8f8585225e31860fa294413e0d386f6e3ca4b51 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/isSExtCheaperThanZExt.cpp @@ -0,0 +1,3 @@ +bool RISCVTargetLowering::isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const { + return Subtarget.is64Bit() && SrcVT == MVT::i32 && DstVT == MVT::i64; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/isTruncateFree.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/isTruncateFree.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6d27755e3ae3c64b204a428d561db12e21d89e8d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/isTruncateFree.cpp @@ -0,0 +1,8 @@ +bool RISCVTargetLowering::isTruncateFree(Type *SrcTy, Type *DstTy) const { + if (Subtarget.is64Bit() || !SrcTy->isIntegerTy() || !DstTy->isIntegerTy()) { + return false; + } + unsigned SrcBits = SrcTy->getPrimitiveSizeInBits(); + unsigned DestBits = DstTy->getPrimitiveSizeInBits(); + return (SrcBits == 64 && DestBits == 32); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/isTruncateFree2.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/isTruncateFree2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0d212b5aaadd33f2042e323c9e69be7f2022ece5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/isTruncateFree2.cpp @@ -0,0 +1,8 @@ +bool RISCVTargetLowering::isTruncateFree(EVT SrcVT, EVT DstVT) const { + if (Subtarget.is64Bit() || SrcVT.isVector() || DstVT.isVector() || !SrcVT.isInteger() || !DstVT.isInteger()) { + return false; + } + unsigned SrcBits = SrcVT.getSizeInBits(); + unsigned DestBits = DstVT.getSizeInBits(); + return (SrcBits == 64 && DestBits == 32); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/isZExtFree.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/isZExtFree.cpp new file mode 100644 index 0000000000000000000000000000000000000000..75d97387f9027fe3ec4fac559ed7892b3b769ecd --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/isZExtFree.cpp @@ -0,0 +1,9 @@ +bool RISCVTargetLowering::isZExtFree(SDValue Val, EVT VT2) const { + if (auto *LD = dyn_cast(Val)) { + EVT MemVT = LD->getMemoryVT(); + if ((MemVT == MVT::i8 || MemVT == MVT::i16 || (Subtarget.is64Bit() && MemVT == MVT::i32)) && (LD->getExtensionType() == ISD::NON_EXTLOAD || LD->getExtensionType() == ISD::ZEXTLOAD)) { + return true; + } + } + return TargetLowering::isZExtFree(Val, VT2); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/lowerEXTRACT_VECTOR_ELT.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/lowerEXTRACT_VECTOR_ELT.cpp new file mode 100644 index 0000000000000000000000000000000000000000..050e83980f6a8e966d61e932a1c240c89fefcc43 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/lowerEXTRACT_VECTOR_ELT.cpp @@ -0,0 +1,12 @@ +SDValue RISCVTargetLowering::lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const { + SDLoc DL(Op); + SDValue Idx = Op.getOperand(1); + if (isNullConstant(Idx)) { + return Op; + } + SDValue Vec = Op.getOperand(0); + EVT EltVT = Op.getValueType(); + EVT VecVT = Vec.getValueType(); + SDValue Slidedown = DAG.getNode(RISCVISD::VSLIDEDOWN, DL, VecVT, DAG.getUNDEF(VecVT), Vec, Idx); + return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Slidedown, DAG.getConstant(0, DL, Subtarget.getXLenVT())); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/lowerINSERT_VECTOR_ELT.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/lowerINSERT_VECTOR_ELT.cpp new file mode 100644 index 0000000000000000000000000000000000000000..41468edf3120b3af736ffa9f92aa9d239535b7a0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/lowerINSERT_VECTOR_ELT.cpp @@ -0,0 +1,21 @@ + +SDValue RISCVTargetLowering::lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const { + SDLoc DL(Op); + EVT VecVT = Op.getValueType(); + SDValue Vec = Op.getOperand(0); + SDValue Val = Op.getOperand(1); + SDValue Idx = Op.getOperand(2); + if (Subtarget.is64Bit() || VecVT.getVectorElementType() != MVT::i64) { + if (isNullConstant(Idx)) + return Op; + SDValue Slidedown = DAG.getNode(RISCVISD::VSLIDEDOWN, DL, VecVT, DAG.getUNDEF(VecVT), Vec, Idx); + SDValue InsertElt0 = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VecVT, Slidedown, Val, DAG.getConstant(0, DL, Subtarget.getXLenVT())); + return DAG.getNode(RISCVISD::VSLIDEUP, DL, VecVT, Vec, InsertElt0, Idx); + } + SDValue SplattedVal = DAG.getSplatVector(VecVT, DL, Val); + SDValue SplattedIdx = DAG.getNode(RISCVISD::SPLAT_VECTOR_I64, DL, VecVT, Idx); + SDValue VID = DAG.getNode(RISCVISD::VID, DL, VecVT); + auto SetCCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VecVT); + SDValue Mask = DAG.getSetCC(DL, SetCCVT, VID, SplattedIdx, ISD::SETEQ); + return DAG.getNode(ISD::VSELECT, DL, VecVT, Mask, SplattedVal, Vec); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/lowerSELECT.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/lowerSELECT.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d178b704135564eb306892895a477348039fefb8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/lowerSELECT.cpp @@ -0,0 +1,21 @@ +SDValue RISCVTargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const { + SDValue CondV = Op.getOperand(0); + SDValue TrueV = Op.getOperand(1); + SDValue FalseV = Op.getOperand(2); + SDLoc DL(Op); + MVT XLenVT = Subtarget.getXLenVT(); + if (Op.getSimpleValueType() == XLenVT && CondV.getOpcode() == ISD::SETCC && CondV.getOperand(0).getSimpleValueType() == XLenVT) { + SDValue LHS = CondV.getOperand(0); + SDValue RHS = CondV.getOperand(1); + auto CC = cast(CondV.getOperand(2)); + ISD::CondCode CCVal = CC->get(); + normaliseSetCC(LHS, RHS, CCVal); + SDValue TargetCC = DAG.getConstant(CCVal, DL, XLenVT); + SDValue Ops[] = {LHS, RHS, TargetCC, TrueV, FalseV}; + return DAG.getNode(RISCVISD::SELECT_CC, DL, Op.getValueType(), Ops); + } + SDValue Zero = DAG.getConstant(0, DL, XLenVT); + SDValue SetNE = DAG.getConstant(ISD::SETNE, DL, XLenVT); + SDValue Ops[] = {CondV, Zero, SetNE, TrueV, FalseV}; + return DAG.getNode(RISCVISD::SELECT_CC, DL, Op.getValueType(), Ops); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/lowerSPLATVECTOR.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/lowerSPLATVECTOR.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a9078247c7a9a4149ed654f10dd7d4f9d2f34abd --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/lowerSPLATVECTOR.cpp @@ -0,0 +1,26 @@ +SDValue RISCVTargetLowering::lowerSPLATVECTOR(SDValue Op, SelectionDAG &DAG) const { + SDLoc DL(Op); + EVT VecVT = Op.getValueType(); + assert(!Subtarget.is64Bit() && VecVT.getVectorElementType() == MVT::i64 && "Unexpected SPLAT_VECTOR lowering"); + SDValue SplatVal = Op.getOperand(0); + if (auto *CVal = dyn_cast(SplatVal)) { + if (isInt<32>(CVal->getSExtValue())) + return DAG.getNode(RISCVISD::SPLAT_VECTOR_I64, DL, VecVT, DAG.getConstant(CVal->getSExtValue(), DL, MVT::i32)); + } + if (SplatVal.getOpcode() == ISD::SIGN_EXTEND && SplatVal.getOperand(0).getValueType() == MVT::i32) { + return DAG.getNode(RISCVISD::SPLAT_VECTOR_I64, DL, VecVT, SplatVal.getOperand(0)); + } + SDValue One = DAG.getConstant(1, DL, MVT::i32); + SDValue Zero = DAG.getConstant(0, DL, MVT::i32); + SDValue ThirtyTwoV = DAG.getConstant(32, DL, VecVT); + SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, SplatVal, Zero); + SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, SplatVal, One); + Lo = DAG.getNode(RISCVISD::SPLAT_VECTOR_I64, DL, VecVT, Lo); + Lo = DAG.getNode(ISD::SHL, DL, VecVT, Lo, ThirtyTwoV); + Lo = DAG.getNode(ISD::SRL, DL, VecVT, Lo, ThirtyTwoV); + if (isNullConstant(Hi)) + return Lo; + Hi = DAG.getNode(RISCVISD::SPLAT_VECTOR_I64, DL, VecVT, Hi); + Hi = DAG.getNode(ISD::SHL, DL, VecVT, Hi, ThirtyTwoV); + return DAG.getNode(ISD::OR, DL, VecVT, Lo, Hi); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/lowerShiftLeftParts.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/lowerShiftLeftParts.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8a781b0834469a4688ad73e9a4725749eac3b6f3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/lowerShiftLeftParts.cpp @@ -0,0 +1,24 @@ +SDValue RISCVTargetLowering::lowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const { + SDLoc DL(Op); + SDValue Lo = Op.getOperand(0); + SDValue Hi = Op.getOperand(1); + SDValue Shamt = Op.getOperand(2); + SDValue Zero = DAG.getConstant(0, DL, VT); + SDValue One = DAG.getConstant(1, DL, VT); + EVT VT = Lo.getValueType(); + SDValue MinusXLen = DAG.getConstant(-(int)Subtarget.getXLen(), DL, VT); + SDValue XLenMinus1 = DAG.getConstant(Subtarget.getXLen() - 1, DL, VT); + SDValue ShamtMinusXLen = DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusXLen); + SDValue XLenMinus1Shamt = DAG.getNode(ISD::SUB, DL, VT, XLenMinus1, Shamt); + SDValue LoTrue = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt); + SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo, One); + SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, XLenMinus1Shamt); + SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt); + SDValue HiTrue = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo); + SDValue HiFalse = DAG.getNode(ISD::SHL, DL, VT, Lo, ShamtMinusXLen); + SDValue CC = DAG.getSetCC(DL, VT, ShamtMinusXLen, Zero, ISD::SETLT); + Lo = DAG.getNode(ISD::SELECT, DL, VT, CC, LoTrue, Zero); + Hi = DAG.getNode(ISD::SELECT, DL, VT, CC, HiTrue, HiFalse); + SDValue Parts[2] = {Lo, Hi}; + return DAG.getMergeValues(Parts, DL); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/lowerShiftRightParts.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/lowerShiftRightParts.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a763204f45299f1efa455b96f65930c2e3e267ef --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/lowerShiftRightParts.cpp @@ -0,0 +1,26 @@ +SDValue RISCVTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const { + SDLoc DL(Op); + SDValue Lo = Op.getOperand(0); + SDValue Hi = Op.getOperand(1); + SDValue Shamt = Op.getOperand(2); + EVT VT = Lo.getValueType(); + unsigned ShiftRightOp = IsSRA ? ISD::SRA : ISD::SRL; + SDValue Zero = DAG.getConstant(0, DL, VT); + SDValue One = DAG.getConstant(1, DL, VT); + SDValue MinusXLen = DAG.getConstant(-(int)Subtarget.getXLen(), DL, VT); + SDValue XLenMinus1 = DAG.getConstant(Subtarget.getXLen() - 1, DL, VT); + SDValue ShamtMinusXLen = DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusXLen); + SDValue XLenMinus1Shamt = DAG.getNode(ISD::SUB, DL, VT, XLenMinus1, Shamt); + SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt); + SDValue ShiftLeftHi1 = DAG.getNode(ISD::SHL, DL, VT, Hi, One); + SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeftHi1, XLenMinus1Shamt); + SDValue LoTrue = DAG.getNode(ISD::OR, DL, VT, ShiftRightLo, ShiftLeftHi); + SDValue HiTrue = DAG.getNode(ShiftRightOp, DL, VT, Hi, Shamt); + SDValue LoFalse = DAG.getNode(ShiftRightOp, DL, VT, Hi, ShamtMinusXLen); + SDValue HiFalse = IsSRA ? DAG.getNode(ISD::SRA, DL, VT, Hi, XLenMinus1) : Zero; + SDValue CC = DAG.getSetCC(DL, VT, ShamtMinusXLen, Zero, ISD::SETLT); + Lo = DAG.getNode(ISD::SELECT, DL, VT, CC, LoTrue, LoFalse); + Hi = DAG.getNode(ISD::SELECT, DL, VT, CC, HiTrue, HiFalse); + SDValue Parts[2] = {Lo, Hi}; + return DAG.getMergeValues(Parts, DL); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/lowerVectorMaskExt.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/lowerVectorMaskExt.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9c860632f70220e7401fd9e8e3d7240d21e74964 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/lowerVectorMaskExt.cpp @@ -0,0 +1,20 @@ +SDValue RISCVTargetLowering::lowerVectorMaskExt(SDValue Op, SelectionDAG &DAG, int64_t ExtTrueVal) const { + SDLoc DL(Op); + EVT VecVT = Op.getValueType(); + SDValue Src = Op.getOperand(0); + if (!Src.getValueType().isVector() || Src.getValueType().getVectorElementType() != MVT::i1) { + return Op; + } + bool IsRV32E64 = !Subtarget.is64Bit() && VecVT.getVectorElementType() == MVT::i64; + SDValue SplatZero = DAG.getConstant(0, DL, Subtarget.getXLenVT()); + SDValue SplatTrueVal = DAG.getConstant(ExtTrueVal, DL, Subtarget.getXLenVT()); + if (!IsRV32E64) { + SplatZero = DAG.getSplatVector(VecVT, DL, SplatZero); + SplatTrueVal = DAG.getSplatVector(VecVT, DL, SplatTrueVal); + } + else { + SplatZero = DAG.getNode(RISCVISD::SPLAT_VECTOR_I64, DL, VecVT, SplatZero); + SplatTrueVal = DAG.getNode(RISCVISD::SPLAT_VECTOR_I64, DL, VecVT, SplatTrueVal); + } + return DAG.getNode(ISD::VSELECT, DL, VecVT, Src, SplatTrueVal, SplatZero); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/lowerVectorMaskTrunc.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/lowerVectorMaskTrunc.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c98f553f2d44e030d17fe05f422ae1fb199ece6f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/lowerVectorMaskTrunc.cpp @@ -0,0 +1,20 @@ +SDValue RISCVTargetLowering::lowerVectorMaskTrunc(SDValue Op, SelectionDAG &DAG) const { + SDLoc DL(Op); + EVT MaskVT = Op.getValueType(); + assert(MaskVT.isVector() && MaskVT.getVectorElementType() == MVT::i1 && "Unexpected type for vector mask lowering"); + SDValue Src = Op.getOperand(0); + EVT VecVT = Src.getValueType(); + bool IsRV32E64 = !Subtarget.is64Bit() && VecVT.getVectorElementType() == MVT::i64; + SDValue SplatOne = DAG.getConstant(1, DL, Subtarget.getXLenVT()); + SDValue SplatZero = DAG.getConstant(0, DL, Subtarget.getXLenVT()); + if (!IsRV32E64) { + SplatOne = DAG.getSplatVector(VecVT, DL, SplatOne); + SplatZero = DAG.getSplatVector(VecVT, DL, SplatZero); + } + else { + SplatOne = DAG.getNode(RISCVISD::SPLAT_VECTOR_I64, DL, VecVT, SplatOne); + SplatZero = DAG.getNode(RISCVISD::SPLAT_VECTOR_I64, DL, VecVT, SplatZero); + } + SDValue Trunc = DAG.getNode(ISD::AND, DL, VecVT, Src, SplatOne); + return DAG.getSetCC(DL, MaskVT, Trunc, SplatZero, ISD::SETNE); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/mayBeEmittedAsTailCall.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/mayBeEmittedAsTailCall.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ede8c5227cba93dac852a1d065fa68b425858673 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/mayBeEmittedAsTailCall.cpp @@ -0,0 +1,3 @@ +bool RISCVTargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const { + return CI->isTailCall(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/normaliseSetCC.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/normaliseSetCC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..81761d63f787d7ededa1a742cd4605cddb2a4530 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/normaliseSetCC.cpp @@ -0,0 +1,13 @@ +static void normaliseSetCC(SDValue &LHS, SDValue &RHS, ISD::CondCode &CC) { + switch (CC) { + default: + break; + case ISD::SETGT: + case ISD::SETLE: + case ISD::SETUGT: + case ISD::SETULE: + CC = ISD::getSetCCSwappedOperands(CC); + std::swap(LHS, RHS); + break; + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/normalizeSetCC.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/normalizeSetCC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f68f25a787d6d9d179404a12f57ee6bc55abf05a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/normalizeSetCC.cpp @@ -0,0 +1,2 @@ +static void normaliseSetCC(SDValue &LHS, SDValue &RHS, ISD::CondCode &CC) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/shouldConsiderGEPOffsetSplit.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/shouldConsiderGEPOffsetSplit.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d6227315c51762f79d2968256df1156d834e76e3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/shouldConsiderGEPOffsetSplit.cpp @@ -0,0 +1,3 @@ +bool shouldConsiderGEPOffsetSplit() const override { + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/shouldConvertConstantLoadToIntImm.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/shouldConvertConstantLoadToIntImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bf5f534d508b97390d1ee1ae00b5cc79a7861324 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/shouldConvertConstantLoadToIntImm.cpp @@ -0,0 +1,3 @@ +bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override { + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/shouldExpandAtomicCmpXchgInIR.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/shouldExpandAtomicCmpXchgInIR.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ac3aae03b6673555878d5192537d50cc530ff736 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/shouldExpandAtomicCmpXchgInIR.cpp @@ -0,0 +1,7 @@ +TargetLowering::AtomicExpansionKind RISCVTargetLowering::shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *CI) const { + unsigned Size = CI->getCompareOperand()->getType()->getPrimitiveSizeInBits(); + if (Size == 8 || Size == 16) { + return AtomicExpansionKind::MaskedIntrinsic; + } + return AtomicExpansionKind::None; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/shouldExpandAtomicRMWInIR.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/shouldExpandAtomicRMWInIR.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4625774d344f7f29a1166ef8ecbca7823323f687 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/shouldExpandAtomicRMWInIR.cpp @@ -0,0 +1,10 @@ +TargetLowering::AtomicExpansionKind RISCVTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const { + if (AI->isFloatingPointOperation()) { + return AtomicExpansionKind::CmpXChg; + } + unsigned Size = AI->getType()->getPrimitiveSizeInBits(); + if (Size == 8 || Size == 16) { + return AtomicExpansionKind::MaskedIntrinsic; + } + return AtomicExpansionKind::None; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/shouldExpandShift.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/shouldExpandShift.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b6604d98ac52fd4c5047c923e074351eea490f8f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/shouldExpandShift.cpp @@ -0,0 +1,6 @@ +bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override { + if (DAG.getMachineFunction().getFunction().hasMinSize()) { + return false; + } + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/shouldExtendTypeInLibCall.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/shouldExtendTypeInLibCall.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d32e64209e6b08e4763994b4f801e4c206f38c74 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/shouldExtendTypeInLibCall.cpp @@ -0,0 +1,7 @@ +bool RISCVTargetLowering::shouldExtendTypeInLibCall(EVT Type) const { + RISCVABI::ABI ABI = Subtarget.getTargetABI(); + if (ABI == RISCVABI::ABI_LP64 && (Type == MVT::f32)) { + return false; + } + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/shouldInsertFencesForAtomic.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/shouldInsertFencesForAtomic.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e56fe49efb7aebf69d2c959f42c622a45c409323 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/shouldInsertFencesForAtomic.cpp @@ -0,0 +1,3 @@ +bool shouldInsertFencesForAtomic(const Instruction *I) const override { + return isa(I) || isa(I); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/shouldSignExtendTypeInLibCall.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/shouldSignExtendTypeInLibCall.cpp new file mode 100644 index 0000000000000000000000000000000000000000..260ccec9da37823ed051c89f36e5a92ee1f5e02c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/shouldSignExtendTypeInLibCall.cpp @@ -0,0 +1,6 @@ +bool RISCVTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const { + if (Subtarget.is64Bit() && Type == MVT::i32) { + return true; + } + return IsSigned; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/targetShrinkDemandedConstant.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/targetShrinkDemandedConstant.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a4d16ec95b820e45afaa94d482643662493978f4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/targetShrinkDemandedConstant.cpp @@ -0,0 +1,44 @@ +bool RISCVTargetLowering::targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, TargetLoweringOpt &TLO) const { + if (!TLO.LegalOps) { + return false; + } + EVT VT = Op.getValueType(); + if (VT.isVector()) { + return false; + } + if (Op.getOpcode() != ISD::AND) { + return false; + } + ConstantSDNode *C = dyn_cast(Op.getOperand(1)); + if (!C) { + return false; + } + const APInt &Mask = C->getAPIntValue(); + APInt ShrunkMask = Mask & DemandedBits; + if (ShrunkMask.isSignedIntN(12)) { + return false; + } + APInt ExpandedMask = Mask | ~DemandedBits; + if (!ExpandedMask.isNegative()) { + return false; + } + unsigned MinSignedBits = ExpandedMask.getMinSignedBits(); + APInt NewMask = ShrunkMask; + if (MinSignedBits <= 12) { + NewMask.setBitsFrom(11); + } + else if (MinSignedBits <= 32 && !ShrunkMask.isSignedIntN(32)) { + NewMask.setBitsFrom(31); + } + else { + return false; + } + assert(NewMask.isSubsetOf(ExpandedMask)); + if (NewMask == Mask) { + return true; + } + SDLoc DL(Op); + SDValue NewC = TLO.DAG.getConstant(NewMask, DL, VT); + SDValue NewOp = TLO.DAG.getNode(ISD::AND, DL, VT, Op.getOperand(0), NewC); + return TLO.CombineTo(Op, NewOp); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/validateCCReservedRegs.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/validateCCReservedRegs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..18092d2a41f8aacf563ddf86d379df202fe8c4e1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/ISelLowering/validateCCReservedRegs.cpp @@ -0,0 +1,8 @@ +void RISCVTargetLowering::validateCCReservedRegs(const SmallVectorImpl> &Regs, MachineFunction &MF) const { + const Function &F = MF.getFunction(); + const RISCVSubtarget &STI = MF.getSubtarget(); + if (llvm::any_of(Regs, [&STI](auto Reg) { + return STI.isRegisterReservedByUser(Reg.first); + })) + F.getContext().diagnose(DiagnosticInfoUnsupported{F, "Argument register required, but has been reserved."}); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/InstructionSelector/InstructionSelector.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/InstructionSelector/InstructionSelector.cpp new file mode 100644 index 0000000000000000000000000000000000000000..53cc2835a41ac58f713da3322777b6baeda2bb12 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/InstructionSelector/InstructionSelector.cpp @@ -0,0 +1,9 @@ +RISCVInstructionSelector::RISCVInstructionSelector(const RISCVTargetMachine &TM, const RISCVSubtarget &STI,const RISCVRegisterBankInfo &RBI) : InstructionSelector(), STI(STI), TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()), RBI(RBI), +#define GET_GLOBALISEL_PREDICATES_INIT +#include "RISCVGenGlobalISel.inc" +#undef GET_GLOBALISEL_PREDICATES_INIT +#define GET_GLOBALISEL_TEMPORARIES_INIT +#include "RISCVGenGlobalISel.inc" +#undef GET_GLOBALISEL_TEMPORARIES_INIT +{ +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/InstructionSelector/createInstructionSelector.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/InstructionSelector/createInstructionSelector.cpp new file mode 100644 index 0000000000000000000000000000000000000000..db262f141398799e83acb55cc3b48da452774550 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/InstructionSelector/createInstructionSelector.cpp @@ -0,0 +1,3 @@ +InstructionSelector *createRISCVInstructionSelector(const RISCVTargetMachine &TM, RISCVSubtarget &Subtarget, RISCVRegisterBankInfo &RBI) { + return new RISCVInstructionSelector(TM, Subtarget, RBI); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/InstructionSelector/getName.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/InstructionSelector/getName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3070f67f8b2d72c6473a6bf2cc4639c82757caaa --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/InstructionSelector/getName.cpp @@ -0,0 +1,3 @@ +static const char *getName() { + return DEBUG_TYPE; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/InstructionSelector/select.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/InstructionSelector/select.cpp new file mode 100644 index 0000000000000000000000000000000000000000..333a38c3ab713a75f6667c26f37dfadbd1ac8adf --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/InstructionSelector/select.cpp @@ -0,0 +1,8 @@ +bool RISCVInstructionSelector::select(MachineInstr &I) { + if (!isPreISelGenericOpcode(I.getOpcode())) { + } + if (selectImpl(I, *CoverageInfo)) { + return true; + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/LegalizeInfo/LegalizerInfo.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/LegalizeInfo/LegalizerInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..58f919e738fbe34244db0d85687060525c38698e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/LegalizeInfo/LegalizerInfo.cpp @@ -0,0 +1,3 @@ +RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) { + computeTables(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/MCInstLower/lowerMachineInstrToMCInst.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/MCInstLower/lowerMachineInstrToMCInst.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2b5ff6b81c894f20f1d1f66973d1c9c51cf5dec5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/MCInstLower/lowerMachineInstrToMCInst.cpp @@ -0,0 +1,78 @@ +void llvm::LowerRISCVMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, const AsmPrinter &AP) { + const RISCVVPseudosTable::PseudoInfo *RVV = RISCVVPseudosTable::getPseudoInfo(MI->getOpcode()); + if (!RVV) { + return false; + } + OutMI.setOpcode(RVV->BaseInstr); + const MachineBasicBlock *MBB = MI->getParent(); + assert(MBB && "MI expected to be in a basic block"); + const MachineFunction *MF = MBB->getParent(); + assert(MF && "MBB expected to be in a machine function"); + const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo(); + assert(TRI && "TargetRegisterInfo expected"); + uint64_t TSFlags = MI->getDesc().TSFlags; + int NumOps = MI->getNumExplicitOperands(); + for (const MachineOperand &MO : MI->explicit_operands()) { + int OpNo = (int)MI->getOperandNo(&MO); + assert(OpNo >= 0 && "Operand number doesn't fit in an 'int' type"); + if ((TSFlags & RISCVII::HasVLOpMask) && OpNo == (NumOps - 2)) { + continue; + } + if ((TSFlags & RISCVII::HasSEWOpMask) && OpNo == (NumOps - 1)) { + continue; + } + if ((TSFlags & RISCVII::HasMergeOpMask) && OpNo == 1) { + assert(MI->getNumExplicitDefs() == 1); + continue; + } + MCOperand MCOp; + switch (MO.getType()) { + default: + llvm_unreachable("Unknown operand type"); + case MachineOperand::MO_Register: { + unsigned Reg = MO.getReg(); + if (RISCV::VRM2RegClass.contains(Reg) || RISCV::VRM4RegClass.contains(Reg) || RISCV::VRM8RegClass.contains(Reg)) { + Reg = TRI->getSubReg(Reg, RISCV::sub_vrm1_0); + assert(Reg && "Subregister does not exist"); + } + else if (RISCV::FPR16RegClass.contains(Reg)) { + Reg = TRI->getMatchingSuperReg(Reg, RISCV::sub_16, &RISCV::FPR32RegClass); + assert(Reg && "Subregister does not exist"); + } + else if (RISCV::FPR64RegClass.contains(Reg)) { + Reg = TRI->getSubReg(Reg, RISCV::sub_32); + assert(Reg && "Superregister does not exist"); + } + MCOp = MCOperand::createReg(Reg); + break; + } + case MachineOperand::MO_Immediate: + MCOp = MCOperand::createImm(MO.getImm()); + break; + } + OutMI.addOperand(MCOp); + } + if (TSFlags & RISCVII::HasDummyMaskOpMask) { + OutMI.addOperand(MCOperand::createReg(RISCV::NoRegister)); + } + return true; + OutMI.setOpcode(MI->getOpcode()); + for (const MachineOperand &MO : MI->operands()) { + MCOperand MCOp; + if (LowerRISCVMachineOperandToMCOperand(MO, MCOp, AP)) { + OutMI.addOperand(MCOp); + } + } + if (OutMI.getOpcode() == RISCV::PseudoReadVLENB) { + OutMI.setOpcode(RISCV::CSRRS); + OutMI.addOperand(MCOperand::createImm(RISCVSysReg::lookupSysRegByName("VLENB")->Encoding)); + OutMI.addOperand(MCOperand::createReg(RISCV::X0)); + return; + } + if (OutMI.getOpcode() == RISCV::PseudoReadVL) { + OutMI.setOpcode(RISCV::CSRRS); + OutMI.addOperand(MCOperand::createImm(RISCVSysReg::lookupSysRegByName("VL")->Encoding)); + OutMI.addOperand(MCOperand::createReg(RISCV::X0)); + return; + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/MCInstLower/lowerMachineOperandToMCOperand.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/MCInstLower/lowerMachineOperandToMCOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e3449796f21b6124dd5bde5e2cc45d1b32c568cb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/MCInstLower/lowerMachineOperandToMCOperand.cpp @@ -0,0 +1,37 @@ +bool llvm::LowerRISCVMachineOperandToMCOperand(const MachineOperand &MO, MCOperand &MCOp, const AsmPrinter &AP) { + switch (MO.getType()) { + case MachineOperand::MO_Register: + if (MO.isImplicit()) + return false; + MCOp = MCOperand::createReg(MO.getReg()); + break; + case MachineOperand::MO_RegisterMask: + return false; + case MachineOperand::MO_Immediate: + MCOp = MCOperand::createImm(MO.getImm()); + break; + case MachineOperand::MO_MachineBasicBlock: + MCOp = lowerSymbolOperand(MO, MO.getMBB()->getSymbol(), AP); + break; + case MachineOperand::MO_GlobalAddress: + MCOp = lowerSymbolOperand(MO, AP.getSymbol(MO.getGlobal()), AP); + break; + case MachineOperand::MO_BlockAddress: + MCOp = lowerSymbolOperand( + MO, AP.GetBlockAddressSymbol(MO.getBlockAddress()), AP); + break; + case MachineOperand::MO_ExternalSymbol: + MCOp = lowerSymbolOperand( + MO, AP.GetExternalSymbolSymbol(MO.getSymbolName()), AP); + break; + case MachineOperand::MO_ConstantPoolIndex: + MCOp = lowerSymbolOperand(MO, AP.GetCPISymbol(MO.getIndex()), AP); + break; + case MachineOperand::MO_JumpTableIndex: + MCOp = lowerSymbolOperand(MO, AP.GetJTISymbol(MO.getIndex()), AP); + break; + default: + report_fatal_error("LowerRISCVMachineInstrToMCInst: unknown operand type"); + } + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/MCInstLower/lowerSymbolOperand.cpp b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/MCInstLower/lowerSymbolOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8107e367a395520aca9a0bde41ed05df30ad152a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/PULP/Selection/MCInstLower/lowerSymbolOperand.cpp @@ -0,0 +1,55 @@ +static MCOperand lowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym, const AsmPrinter &AP) { + MCContext &Ctx = AP.OutContext; + RISCVMCExpr::VariantKind Kind; + switch (MO.getTargetFlags()) { + default: + llvm_unreachable("Unknown target flag on GV operand"); + case RISCVII::MO_None: + Kind = RISCVMCExpr::VK_RISCV_None; + break; + case RISCVII::MO_CALL: + Kind = RISCVMCExpr::VK_RISCV_CALL; + break; + case RISCVII::MO_PLT: + Kind = RISCVMCExpr::VK_RISCV_CALL_PLT; + break; + case RISCVII::MO_LO: + Kind = RISCVMCExpr::VK_RISCV_LO; + break; + case RISCVII::MO_HI: + Kind = RISCVMCExpr::VK_RISCV_HI; + break; + case RISCVII::MO_PCREL_LO: + Kind = RISCVMCExpr::VK_RISCV_PCREL_LO; + break; + case RISCVII::MO_PCREL_HI: + Kind = RISCVMCExpr::VK_RISCV_PCREL_HI; + break; + case RISCVII::MO_GOT_HI: + Kind = RISCVMCExpr::VK_RISCV_GOT_HI; + break; + case RISCVII::MO_TPREL_LO: + Kind = RISCVMCExpr::VK_RISCV_TPREL_LO; + break; + case RISCVII::MO_TPREL_HI: + Kind = RISCVMCExpr::VK_RISCV_TPREL_HI; + break; + case RISCVII::MO_TPREL_ADD: + Kind = RISCVMCExpr::VK_RISCV_TPREL_ADD; + break; + case RISCVII::MO_TLS_GOT_HI: + Kind = RISCVMCExpr::VK_RISCV_TLS_GOT_HI; + break; + case RISCVII::MO_TLS_GD_HI: + Kind = RISCVMCExpr::VK_RISCV_TLS_GD_HI; + break; + } + const MCExpr *ME = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, Ctx); + if (!MO.isJTI() && !MO.isMBB() && MO.getOffset()) { + ME = MCBinaryExpr::createAdd(ME, MCConstantExpr::create(MO.getOffset(), Ctx), Ctx); + } + if (Kind != RISCVMCExpr::VK_RISCV_None) { + ME = RISCVMCExpr::create(ME, Kind, Ctx); + } + return MCOperand::createExpr(ME); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Allocation/RegisterBankInfo/RegisterBankInfo.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Allocation/RegisterBankInfo/RegisterBankInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4dc7ae84acc6da01a6fc88136b4545507046b3da --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Allocation/RegisterBankInfo/RegisterBankInfo.cpp @@ -0,0 +1,2 @@ +RISCVRegisterBankInfo::RISCVRegisterBankInfo(const TargetRegisterInfo &TRI) : RISCVGenRegisterBankInfo() { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Allocation/RegisterInfo/RegisterInfo.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Allocation/RegisterInfo/RegisterInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1480303244e07d20dda536668a1d006b005c6abf --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Allocation/RegisterInfo/RegisterInfo.cpp @@ -0,0 +1,2 @@ +RISCVRegisterInfo::RISCVRegisterInfo(unsigned HwMode) : RISCVGenRegisterInfo(RISCV::X1, 0, 0, 0, HwMode) { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Allocation/RegisterInfo/eliminateFrameIndex.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Allocation/RegisterInfo/eliminateFrameIndex.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4627583a88c723ec5625aa71d430e6bc6fca6ed5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Allocation/RegisterInfo/eliminateFrameIndex.cpp @@ -0,0 +1,27 @@ +void RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const { + assert(SPAdj == 0 && "Unexpected non-zero SPAdj value"); + MachineInstr &MI = *II; + MachineFunction &MF = *MI.getParent()->getParent(); + MachineRegisterInfo &MRI = MF.getRegInfo(); + const RISCVInstrInfo *TII = MF.getSubtarget().getInstrInfo(); + DebugLoc DL = MI.getDebugLoc(); + int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); + Register FrameReg; + int Offset = getFrameLowering(MF)->getFrameIndexReference(MF, FrameIndex, FrameReg).getFixed() + MI.getOperand(FIOperandNum + 1).getImm(); + if (!isInt<32>(Offset)) { + report_fatal_error("Frame offsets outside of the signed 32-bit range not supported"); + } + MachineBasicBlock &MBB = *MI.getParent(); + bool FrameRegIsKill = false; + if (!isInt<12>(Offset)) { + assert(isInt<32>(Offset) && "Int32 expected"); + Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); + TII->movImm(MBB, II, DL, ScratchReg, Offset); + BuildMI(MBB, II, DL, TII->get(RISCV::ADD), ScratchReg).addReg(FrameReg).addReg(ScratchReg, RegState::Kill); + Offset = 0; + FrameReg = ScratchReg; + FrameRegIsKill = true; + } + MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, FrameRegIsKill); + MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Allocation/RegisterInfo/getCallPreservedMask.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Allocation/RegisterInfo/getCallPreservedMask.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a8e9de57806a18f51b53e3d7fa691a28052d7d64 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Allocation/RegisterInfo/getCallPreservedMask.cpp @@ -0,0 +1,19 @@ +const uint32_t *RISCVRegisterInfo::getCallPreservedMask(const MachineFunction & MF, CallingConv::ID CC) const { + auto &Subtarget = MF.getSubtarget(); + if (CC == CallingConv::GHC) { + return CSR_NoRegs_RegMask; + } + switch (Subtarget.getTargetABI()) { + case RISCVABI::ABI_ILP32: + case RISCVABI::ABI_LP64: + return CSR_ILP32_LP64_RegMask; + case RISCVABI::ABI_ILP32F: + case RISCVABI::ABI_LP64F: + return CSR_ILP32F_LP64F_RegMask; + case RISCVABI::ABI_ILP32D: + case RISCVABI::ABI_LP64D: + return CSR_ILP32D_LP64D_RegMask; + default: + llvm_unreachable("Unrecognized ABI"); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Allocation/RegisterInfo/getCalleeSavedRegs.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Allocation/RegisterInfo/getCalleeSavedRegs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3050b17a62d80679cf10f80be303f18b7def4c51 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Allocation/RegisterInfo/getCalleeSavedRegs.cpp @@ -0,0 +1,28 @@ +const MCPhysReg *RISCVRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { + auto &Subtarget = MF->getSubtarget(); + if (MF->getFunction().getCallingConv() == CallingConv::GHC) { + return CSR_NoRegs_SaveList; + } + if (MF->getFunction().hasFnAttribute("interrupt")) { + if (Subtarget.hasStdExtD()) { + return CSR_XLEN_F64_Interrupt_SaveList; + } + if (Subtarget.hasStdExtF()) { + return CSR_XLEN_F32_Interrupt_SaveList; + } + return CSR_Interrupt_SaveList; + } + switch (Subtarget.getTargetABI()) { + case RISCVABI::ABI_ILP32: + case RISCVABI::ABI_LP64: + return CSR_ILP32_LP64_SaveList; + case RISCVABI::ABI_ILP32F: + case RISCVABI::ABI_LP64F: + return CSR_ILP32F_LP64F_SaveList; + case RISCVABI::ABI_ILP32D: + case RISCVABI::ABI_LP64D: + return CSR_ILP32D_LP64D_SaveList; + default: + llvm_unreachable("Unrecognized ABI"); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Allocation/RegisterInfo/getFrameRegister.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Allocation/RegisterInfo/getFrameRegister.cpp new file mode 100644 index 0000000000000000000000000000000000000000..72c4c839e6e91d5177aac289f685491ab3ec84a2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Allocation/RegisterInfo/getFrameRegister.cpp @@ -0,0 +1,4 @@ +Register RISCVRegisterInfo::getFrameRegister(const MachineFunction &MF) const { + const TargetFrameLowering *TFI = getFrameLowering(MF); + return TFI->hasFP(MF) ? RISCV::X8 : RISCV::X2; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Allocation/RegisterInfo/getNoPreservedMask.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Allocation/RegisterInfo/getNoPreservedMask.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7fa56f2bf4b0fa58c156cb2b44e640600fd4e8df --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Allocation/RegisterInfo/getNoPreservedMask.cpp @@ -0,0 +1,3 @@ +const uint32_t *RISCVRegisterInfo::getNoPreservedMask() const { + return CSR_NoRegs_RegMask; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Allocation/RegisterInfo/getPointerRegClass.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Allocation/RegisterInfo/getPointerRegClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..88663c48f37912ceed74f49de1e37a38e9411d0a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Allocation/RegisterInfo/getPointerRegClass.cpp @@ -0,0 +1,3 @@ +const TargetRegisterClass *getPointerRegClass(const MachineFunction &MF, unsigned Kind = 0) const override { + return &RISCV::GPRRegClass; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Allocation/RegisterInfo/getReservedRegs.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Allocation/RegisterInfo/getReservedRegs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f31c4f5d6450a0cdcfec3c9c7e0c23f25273b3b2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Allocation/RegisterInfo/getReservedRegs.cpp @@ -0,0 +1,25 @@ +BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const { + const RISCVFrameLowering *TFI = getFrameLowering(MF); + BitVector Reserved(getNumRegs()); + for (size_t Reg = 0; Reg < getNumRegs(); Reg++) { + if (MF.getSubtarget().isRegisterReservedByUser(Reg)) { + markSuperRegs(Reserved, Reg); + } + } + markSuperRegs(Reserved, RISCV::X0); + markSuperRegs(Reserved, RISCV::X2); + markSuperRegs(Reserved, RISCV::X3); + markSuperRegs(Reserved, RISCV::X4); + if (TFI->hasFP(MF)) { + markSuperRegs(Reserved, RISCV::X8); + } + if (TFI->hasBP(MF)) { + markSuperRegs(Reserved, RISCVABI::getBPReg()); + } + markSuperRegs(Reserved, RISCV::VL); + markSuperRegs(Reserved, RISCV::VTYPE); + markSuperRegs(Reserved, RISCV::VXSAT); + markSuperRegs(Reserved, RISCV::VXRM); + assert(checkAllSuperRegsMarked(Reserved)); + return Reserved; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Allocation/RegisterInfo/hasReservedSpillSlot.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Allocation/RegisterInfo/hasReservedSpillSlot.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0128afe039488da081ce0db8ac0fa9d0c2001e05 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Allocation/RegisterInfo/hasReservedSpillSlot.cpp @@ -0,0 +1,12 @@ +bool RISCVRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF, Register Reg, int &FrameIdx) const { + const auto *RVFI = MF.getInfo(); + if (!RVFI->useSaveRestoreLibCalls(MF)) { + return false; + } + auto FII = FixedCSRFIMap.find(Reg); + if (FII == FixedCSRFIMap.end()) { + return false; + } + FrameIdx = FII->second; + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Allocation/RegisterInfo/isAsmClobberable.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Allocation/RegisterInfo/isAsmClobberable.cpp new file mode 100644 index 0000000000000000000000000000000000000000..25561255c0b0144c3f52ec50dd6542c764b476af --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Allocation/RegisterInfo/isAsmClobberable.cpp @@ -0,0 +1,3 @@ +bool RISCVRegisterInfo::isAsmClobberable(const MachineFunction &MF, MCRegister PhysReg) const { + return !MF.getSubtarget().isRegisterReservedByUser(PhysReg); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Allocation/RegisterInfo/isConstantPhysReg.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Allocation/RegisterInfo/isConstantPhysReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5f3ae8dcbdb06cd2b11c08d4304bc5fbbeb7a0bf --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Allocation/RegisterInfo/isConstantPhysReg.cpp @@ -0,0 +1,3 @@ +bool RISCVRegisterInfo::isConstantPhysReg(MCRegister PhysReg) const { + return PhysReg == RISCV::X0; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Allocation/RegisterInfo/requiresFrameIndexScavenging.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Allocation/RegisterInfo/requiresFrameIndexScavenging.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fcdefd787701998b4ca78c8a05ad2a8d3a8da92b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Allocation/RegisterInfo/requiresFrameIndexScavenging.cpp @@ -0,0 +1,3 @@ +bool requiresFrameIndexScavenging(const MachineFunction &MF) const override { + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Allocation/RegisterInfo/requiresRegisterScavenging.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Allocation/RegisterInfo/requiresRegisterScavenging.cpp new file mode 100644 index 0000000000000000000000000000000000000000..14b5f8108d512990df2060604418ece481a51ba3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Allocation/RegisterInfo/requiresRegisterScavenging.cpp @@ -0,0 +1,3 @@ +bool requiresRegisterScavenging(const MachineFunction &MF) const override { + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/AsmParser.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/AsmParser.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7797cdba62f86a46e4dea7c5120f3c6aefe6bfde --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/AsmParser.cpp @@ -0,0 +1,16 @@ +RISCVAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser, const MCInstrInfo &MII, const MCTargetOptions &Options) : MCTargetAsmParser(Options, STI, MII) { + Parser.addAliasForDirective(".half", ".2byte"); + Parser.addAliasForDirective(".hword", ".2byte"); + Parser.addAliasForDirective(".word", ".4byte"); + Parser.addAliasForDirective(".dword", ".8byte"); + setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); + auto ABIName = StringRef(Options.ABIName); + if (ABIName.endswith("f") && !getSTI().getFeatureBits()[RISCV::FeatureStdExtF]) { + errs() << "Hard-float 'f' ABI can't be used for a target that doesn't support the F instruction set extension (ignoring target-abi)\n"; + } + else if (ABIName.endswith("d") && !getSTI().getFeatureBits()[RISCV::FeatureStdExtD]) { + errs() << "Hard-float 'd' ABI can't be used for a target that doesn't support the D instruction set extension (ignoring target-abi)\n"; + } + const MCObjectFileInfo *MOFI = Parser.getContext().getObjectFileInfo(); + ParserOptions.IsPicEnabled = MOFI->isPositionIndependent(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/KindTy.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/KindTy.cpp new file mode 100644 index 0000000000000000000000000000000000000000..371575f0ea6716a531fb88cd3fb871d6a05d4417 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/KindTy.cpp @@ -0,0 +1,7 @@ +enum class KindTy { + Token, + Register, + Immediate, + SystemRegister, + VType, +} Kind; diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/LLVMInitializeAsmParser.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/LLVMInitializeAsmParser.cpp new file mode 100644 index 0000000000000000000000000000000000000000..71228f1bad2b593ede7681696f374a8ce3765475 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/LLVMInitializeAsmParser.cpp @@ -0,0 +1,4 @@ +extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVAsmParser() { + RegisterMCAsmParser X(getTheRISCV32Target()); + RegisterMCAsmParser Y(getTheRISCV64Target()); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/MatchAndEmitInstruction.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/MatchAndEmitInstruction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a0b5f960569745689b8abf24bb90aaf3d291803c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/MatchAndEmitInstruction.cpp @@ -0,0 +1,621 @@ +bool RISCVAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, OperandVector &Operands, MCStreamer &Out, uint64_t &ErrorInfo, bool MatchingInlineAsm) { + MCInst Inst; + FeatureBitset MissingFeatures; + auto Result = MatchInstructionImpl(Operands, Inst, ErrorInfo, MissingFeatures, MatchingInlineAsm); + switch (Result) { + default: + break; + case Match_Success: + const MCInstrDesc &MCID = MII.get(Inst.getOpcode()); + unsigned Constraints = (MCID.TSFlags & RISCVII::ConstraintMask) >> RISCVII::ConstraintShift; + unsigned DestReg = Inst.getOperand(0).getReg(); + SMLoc Loc = Operands[1]->getStartLoc(); + if (Constraints & RISCVII::VS2Constraint) { + unsigned CheckReg = Inst.getOperand(1).getReg(); + if (DestReg == CheckReg) { + return Error(Loc, "The destination vector register group cannot overlap the source vector register group."); + } + } + if ((Constraints & RISCVII::VS1Constraint) && (Inst.getOperand(2).isReg())) { + unsigned CheckReg = Inst.getOperand(2).getReg(); + if (DestReg == CheckReg) { + return Error(Loc, "The destination vector register group cannot overlap the source vector register group."); + } + } + if ((Constraints & RISCVII::VMConstraint) && (DestReg == RISCV::V0)) { + unsigned Opcode = Inst.getOpcode(); + if (Opcode == RISCV::VADC_VVM || Opcode == RISCV::VADC_VXM || Opcode == RISCV::VADC_VIM || Opcode == RISCV::VSBC_VVM || Opcode == RISCV::VSBC_VXM || Opcode == RISCV::VFMERGE_VFM || Opcode == RISCV::VMERGE_VIM || Opcode == RISCV::VMERGE_VVM || Opcode == RISCV::VMERGE_VXM) { + return Error(Loc, "The destination vector register group cannot be V0."); + } + unsigned CheckReg = Inst.getOperand(Inst.getNumOperands() - 1).getReg(); + assert((CheckReg == RISCV::V0 || CheckReg == RISCV::NoRegister) && "Unexpected register for mask operand"); + if (DestReg == CheckReg) { + return Error(Loc, "The destination vector register group cannot overlap the mask register."); + } + } + Inst.setLoc(IDLoc); + switch (Inst.getOpcode()) { + default: + break; + case RISCV::PseudoLI: { + MCRegister Reg = Inst.getOperand(0).getReg(); + const MCOperand &Op1 = Inst.getOperand(1); + if (Op1.isExpr()) { + emitToStreamer(Out, MCInstBuilder(RISCV::ADDI).addReg(Reg).addReg(RISCV::X0).addExpr(Op1.getExpr())); + return false; + } + int64_t Imm = Inst.getOperand(1).getImm(); + if (!isRV64()) { + Imm = SignExtend64<32>(Imm); + } + RISCVMatInt::InstSeq Seq; + RISCVMatInt::generateInstSeq(Value, isRV64(), Seq); + MCRegister SrcReg = RISCV::X0; + for (RISCVMatInt::Inst &Inst : Seq) { + if (Inst.Opc == RISCV::LUI) { + emitToStreamer(Out, MCInstBuilder(RISCV::LUI).addReg(DestReg).addImm(Inst.Imm)); + } else { + emitToStreamer(Out, MCInstBuilder(Inst.Opc).addReg(DestReg).addReg(SrcReg).addImm(Inst.Imm)); + } + SrcReg = DestReg; + } + return false; + } + case RISCV::PseudoLLA: + MCOperand DestReg = Inst.getOperand(0); + const MCExpr *Symbol = Inst.getOperand(1).getExpr(); + MCContext &Ctx = getContext(); + MCSymbol *TmpLabel = Ctx.createNamedTempSymbol("pcrel_hi"); + Out.emitLabel(TmpLabel); + const RISCVMCExpr *SymbolHi = RISCVMCExpr::create(Symbol, VKHi, Ctx); + emitToStreamer(Out, MCInstBuilder(RISCV::AUIPC).addOperand(TmpReg).addExpr(SymbolHi)); + const MCExpr *RefToLinkTmpLabel = RISCVMCExpr::create(MCSymbolRefExpr::create(TmpLabel, Ctx), RISCVMCExpr::VK_RISCV_PCREL_LO, Ctx); + emitToStreamer(Out, MCInstBuilder(SecondOpcode).addOperand(DestReg).addOperand(TmpReg).addExpr(RefToLinkTmpLabel)); + return false; + case RISCV::PseudoLA: + MCOperand DestReg = Inst.getOperand(0); + const MCExpr *Symbol = Inst.getOperand(1).getExpr(); + unsigned SecondOpcode; + RISCVMCExpr::VariantKind VKHi; + if (ParserOptions.IsPicEnabled) { + SecondOpcode = isRV64() ? RISCV::LD : RISCV::LW; + VKHi = RISCVMCExpr::VK_RISCV_GOT_HI; + } else { + SecondOpcode = RISCV::ADDI; + VKHi = RISCVMCExpr::VK_RISCV_PCREL_HI; + } + MCContext &Ctx = getContext(); + MCSymbol *TmpLabel = Ctx.createNamedTempSymbol("pcrel_hi"); + Out.emitLabel(TmpLabel); + const RISCVMCExpr *SymbolHi = RISCVMCExpr::create(Symbol, VKHi, Ctx); + emitToStreamer(Out, MCInstBuilder(RISCV::AUIPC).addOperand(TmpReg).addExpr(SymbolHi)); + const MCExpr *RefToLinkTmpLabel = RISCVMCExpr::create(MCSymbolRefExpr::create(TmpLabel, Ctx), RISCVMCExpr::VK_RISCV_PCREL_LO, Ctx); + emitToStreamer(Out, MCInstBuilder(SecondOpcode).addOperand(DestReg).addOperand(TmpReg).addExpr(RefToLinkTmpLabel)); + return false; + case RISCV::PseudoLA_TLS_IE: + MCOperand DestReg = Inst.getOperand(0); + const MCExpr *Symbol = Inst.getOperand(1).getExpr(); + unsigned SecondOpcode = isRV64() ? RISCV::LD : RISCV::LW; + MCContext &Ctx = getContext(); + MCSymbol *TmpLabel = Ctx.createNamedTempSymbol("pcrel_hi"); + Out.emitLabel(TmpLabel); + const RISCVMCExpr *SymbolHi = RISCVMCExpr::create(Symbol, VKHi, Ctx); + emitToStreamer(Out, MCInstBuilder(RISCV::AUIPC).addOperand(TmpReg).addExpr(SymbolHi)); + const MCExpr *RefToLinkTmpLabel = RISCVMCExpr::create(MCSymbolRefExpr::create(TmpLabel, Ctx), RISCVMCExpr::VK_RISCV_PCREL_LO, Ctx); + emitToStreamer(Out, MCInstBuilder(SecondOpcode).addOperand(DestReg).addOperand(TmpReg).addExpr(RefToLinkTmpLabel)); + return false; + case RISCV::PseudoLA_TLS_GD: + MCOperand DestReg = Inst.getOperand(0); + const MCExpr *Symbol = Inst.getOperand(1).getExpr(); + MCContext &Ctx = getContext(); + MCSymbol *TmpLabel = Ctx.createNamedTempSymbol("pcrel_hi"); + Out.emitLabel(TmpLabel); + const RISCVMCExpr *SymbolHi = RISCVMCExpr::create(Symbol, VKHi, Ctx); + emitToStreamer(Out, MCInstBuilder(RISCV::AUIPC).addOperand(TmpReg).addExpr(SymbolHi)); + const MCExpr *RefToLinkTmpLabel = RISCVMCExpr::create(MCSymbolRefExpr::create(TmpLabel, Ctx), RISCVMCExpr::VK_RISCV_PCREL_LO, Ctx); + emitToStreamer(Out, MCInstBuilder(SecondOpcode).addOperand(DestReg).addOperand(TmpReg).addExpr(RefToLinkTmpLabel)); + return false; + case RISCV::PseudoLB: + MCOperand DestReg = Inst.getOperand(0); + unsigned SymbolOpIdx = HasTmpReg ? 2 : 1; + unsigned TmpRegOpIdx = HasTmpReg ? 1 : 0; + MCOperand TmpReg = Inst.getOperand(TmpRegOpIdx); + const MCExpr *Symbol = Inst.getOperand(SymbolOpIdx).getExpr(); + MCContext &Ctx = getContext(); + MCSymbol *TmpLabel = Ctx.createNamedTempSymbol("pcrel_hi"); + Out.emitLabel(TmpLabel); + const RISCVMCExpr *SymbolHi = RISCVMCExpr::create(Symbol, VKHi, Ctx); + emitToStreamer(Out, MCInstBuilder(RISCV::AUIPC).addOperand(TmpReg).addExpr(SymbolHi)); + const MCExpr *RefToLinkTmpLabel = RISCVMCExpr::create(MCSymbolRefExpr::create(TmpLabel, Ctx), RISCVMCExpr::VK_RISCV_PCREL_LO, Ctx); + emitToStreamer(Out, MCInstBuilder(SecondOpcode).addOperand(DestReg).addOperand(TmpReg).addExpr(RefToLinkTmpLabel)); + return false; + case RISCV::PseudoLBU: + MCOperand DestReg = Inst.getOperand(0); + unsigned SymbolOpIdx = HasTmpReg ? 2 : 1; + unsigned TmpRegOpIdx = HasTmpReg ? 1 : 0; + MCOperand TmpReg = Inst.getOperand(TmpRegOpIdx); + const MCExpr *Symbol = Inst.getOperand(SymbolOpIdx).getExpr(); + MCContext &Ctx = getContext(); + MCSymbol *TmpLabel = Ctx.createNamedTempSymbol("pcrel_hi"); + Out.emitLabel(TmpLabel); + const RISCVMCExpr *SymbolHi = RISCVMCExpr::create(Symbol, VKHi, Ctx); + emitToStreamer(Out, MCInstBuilder(RISCV::AUIPC).addOperand(TmpReg).addExpr(SymbolHi)); + const MCExpr *RefToLinkTmpLabel = RISCVMCExpr::create(MCSymbolRefExpr::create(TmpLabel, Ctx), RISCVMCExpr::VK_RISCV_PCREL_LO, Ctx); + emitToStreamer(Out, MCInstBuilder(SecondOpcode).addOperand(DestReg).addOperand(TmpReg).addExpr(RefToLinkTmpLabel)); + return false; + case RISCV::PseudoLH: + MCOperand DestReg = Inst.getOperand(0); + unsigned SymbolOpIdx = HasTmpReg ? 2 : 1; + unsigned TmpRegOpIdx = HasTmpReg ? 1 : 0; + MCOperand TmpReg = Inst.getOperand(TmpRegOpIdx); + const MCExpr *Symbol = Inst.getOperand(SymbolOpIdx).getExpr(); + MCContext &Ctx = getContext(); + MCSymbol *TmpLabel = Ctx.createNamedTempSymbol("pcrel_hi"); + Out.emitLabel(TmpLabel); + const RISCVMCExpr *SymbolHi = RISCVMCExpr::create(Symbol, VKHi, Ctx); + emitToStreamer(Out, MCInstBuilder(RISCV::AUIPC).addOperand(TmpReg).addExpr(SymbolHi)); + const MCExpr *RefToLinkTmpLabel = RISCVMCExpr::create(MCSymbolRefExpr::create(TmpLabel, Ctx), RISCVMCExpr::VK_RISCV_PCREL_LO, Ctx); + emitToStreamer(Out, MCInstBuilder(SecondOpcode).addOperand(DestReg).addOperand(TmpReg).addExpr(RefToLinkTmpLabel)); + return false; + case RISCV::PseudoLHU: + MCOperand DestReg = Inst.getOperand(0); + unsigned SymbolOpIdx = HasTmpReg ? 2 : 1; + unsigned TmpRegOpIdx = HasTmpReg ? 1 : 0; + MCOperand TmpReg = Inst.getOperand(TmpRegOpIdx); + const MCExpr *Symbol = Inst.getOperand(SymbolOpIdx).getExpr(); + MCContext &Ctx = getContext(); + MCSymbol *TmpLabel = Ctx.createNamedTempSymbol("pcrel_hi"); + Out.emitLabel(TmpLabel); + const RISCVMCExpr *SymbolHi = RISCVMCExpr::create(Symbol, VKHi, Ctx); + emitToStreamer(Out, MCInstBuilder(RISCV::AUIPC).addOperand(TmpReg).addExpr(SymbolHi)); + const MCExpr *RefToLinkTmpLabel = RISCVMCExpr::create(MCSymbolRefExpr::create(TmpLabel, Ctx), RISCVMCExpr::VK_RISCV_PCREL_LO, Ctx); + emitToStreamer(Out, MCInstBuilder(SecondOpcode).addOperand(DestReg).addOperand(TmpReg).addExpr(RefToLinkTmpLabel)); + return false; + case RISCV::PseudoLW: + MCOperand DestReg = Inst.getOperand(0); + unsigned SymbolOpIdx = HasTmpReg ? 2 : 1; + unsigned TmpRegOpIdx = HasTmpReg ? 1 : 0; + MCOperand TmpReg = Inst.getOperand(TmpRegOpIdx); + const MCExpr *Symbol = Inst.getOperand(SymbolOpIdx).getExpr(); + MCContext &Ctx = getContext(); + MCSymbol *TmpLabel = Ctx.createNamedTempSymbol("pcrel_hi"); + Out.emitLabel(TmpLabel); + const RISCVMCExpr *SymbolHi = RISCVMCExpr::create(Symbol, VKHi, Ctx); + emitToStreamer(Out, MCInstBuilder(RISCV::AUIPC).addOperand(TmpReg).addExpr(SymbolHi)); + const MCExpr *RefToLinkTmpLabel = RISCVMCExpr::create(MCSymbolRefExpr::create(TmpLabel, Ctx), RISCVMCExpr::VK_RISCV_PCREL_LO, Ctx); + emitToStreamer(Out, MCInstBuilder(SecondOpcode).addOperand(DestReg).addOperand(TmpReg).addExpr(RefToLinkTmpLabel)); + return false; + case RISCV::PseudoLWU: + MCOperand DestReg = Inst.getOperand(0); + unsigned SymbolOpIdx = HasTmpReg ? 2 : 1; + unsigned TmpRegOpIdx = HasTmpReg ? 1 : 0; + MCOperand TmpReg = Inst.getOperand(TmpRegOpIdx); + const MCExpr *Symbol = Inst.getOperand(SymbolOpIdx).getExpr(); + MCContext &Ctx = getContext(); + MCSymbol *TmpLabel = Ctx.createNamedTempSymbol("pcrel_hi"); + Out.emitLabel(TmpLabel); + const RISCVMCExpr *SymbolHi = RISCVMCExpr::create(Symbol, VKHi, Ctx); + emitToStreamer(Out, MCInstBuilder(RISCV::AUIPC).addOperand(TmpReg).addExpr(SymbolHi)); + const MCExpr *RefToLinkTmpLabel = RISCVMCExpr::create(MCSymbolRefExpr::create(TmpLabel, Ctx), RISCVMCExpr::VK_RISCV_PCREL_LO, Ctx); + emitToStreamer(Out, MCInstBuilder(SecondOpcode).addOperand(DestReg).addOperand(TmpReg).addExpr(RefToLinkTmpLabel)); + return false; + case RISCV::PseudoLD: + MCOperand DestReg = Inst.getOperand(0); + unsigned SymbolOpIdx = HasTmpReg ? 2 : 1; + unsigned TmpRegOpIdx = HasTmpReg ? 1 : 0; + MCOperand TmpReg = Inst.getOperand(TmpRegOpIdx); + const MCExpr *Symbol = Inst.getOperand(SymbolOpIdx).getExpr(); + MCContext &Ctx = getContext(); + MCSymbol *TmpLabel = Ctx.createNamedTempSymbol("pcrel_hi"); + Out.emitLabel(TmpLabel); + const RISCVMCExpr *SymbolHi = RISCVMCExpr::create(Symbol, VKHi, Ctx); + emitToStreamer(Out, MCInstBuilder(RISCV::AUIPC).addOperand(TmpReg).addExpr(SymbolHi)); + const MCExpr *RefToLinkTmpLabel = RISCVMCExpr::create(MCSymbolRefExpr::create(TmpLabel, Ctx), RISCVMCExpr::VK_RISCV_PCREL_LO, Ctx); + emitToStreamer(Out, MCInstBuilder(SecondOpcode).addOperand(DestReg).addOperand(TmpReg).addExpr(RefToLinkTmpLabel)); + return false; + case RISCV::PseudoFLH: + MCOperand DestReg = Inst.getOperand(0); + unsigned SymbolOpIdx = HasTmpReg ? 2 : 1; + unsigned TmpRegOpIdx = HasTmpReg ? 1 : 0; + MCOperand TmpReg = Inst.getOperand(TmpRegOpIdx); + const MCExpr *Symbol = Inst.getOperand(SymbolOpIdx).getExpr(); + MCContext &Ctx = getContext(); + MCSymbol *TmpLabel = Ctx.createNamedTempSymbol("pcrel_hi"); + Out.emitLabel(TmpLabel); + const RISCVMCExpr *SymbolHi = RISCVMCExpr::create(Symbol, VKHi, Ctx); + emitToStreamer(Out, MCInstBuilder(RISCV::AUIPC).addOperand(TmpReg).addExpr(SymbolHi)); + const MCExpr *RefToLinkTmpLabel = RISCVMCExpr::create(MCSymbolRefExpr::create(TmpLabel, Ctx), RISCVMCExpr::VK_RISCV_PCREL_LO, Ctx); + emitToStreamer(Out, MCInstBuilder(SecondOpcode).addOperand(DestReg).addOperand(TmpReg).addExpr(RefToLinkTmpLabel)); + return false; + case RISCV::PseudoFLW: + MCOperand DestReg = Inst.getOperand(0); + unsigned SymbolOpIdx = HasTmpReg ? 2 : 1; + unsigned TmpRegOpIdx = HasTmpReg ? 1 : 0; + MCOperand TmpReg = Inst.getOperand(TmpRegOpIdx); + const MCExpr *Symbol = Inst.getOperand(SymbolOpIdx).getExpr(); + MCContext &Ctx = getContext(); + MCSymbol *TmpLabel = Ctx.createNamedTempSymbol("pcrel_hi"); + Out.emitLabel(TmpLabel); + const RISCVMCExpr *SymbolHi = RISCVMCExpr::create(Symbol, VKHi, Ctx); + emitToStreamer(Out, MCInstBuilder(RISCV::AUIPC).addOperand(TmpReg).addExpr(SymbolHi)); + const MCExpr *RefToLinkTmpLabel = RISCVMCExpr::create(MCSymbolRefExpr::create(TmpLabel, Ctx), RISCVMCExpr::VK_RISCV_PCREL_LO, Ctx); + emitToStreamer(Out, MCInstBuilder(SecondOpcode).addOperand(DestReg).addOperand(TmpReg).addExpr(RefToLinkTmpLabel)); + return false; + case RISCV::PseudoFLD: + MCOperand DestReg = Inst.getOperand(0); + unsigned SymbolOpIdx = HasTmpReg ? 2 : 1; + unsigned TmpRegOpIdx = HasTmpReg ? 1 : 0; + MCOperand TmpReg = Inst.getOperand(TmpRegOpIdx); + const MCExpr *Symbol = Inst.getOperand(SymbolOpIdx).getExpr(); + MCContext &Ctx = getContext(); + MCSymbol *TmpLabel = Ctx.createNamedTempSymbol("pcrel_hi"); + Out.emitLabel(TmpLabel); + const RISCVMCExpr *SymbolHi = RISCVMCExpr::create(Symbol, VKHi, Ctx); + emitToStreamer(Out, MCInstBuilder(RISCV::AUIPC).addOperand(TmpReg).addExpr(SymbolHi)); + const MCExpr *RefToLinkTmpLabel = RISCVMCExpr::create(MCSymbolRefExpr::create(TmpLabel, Ctx), RISCVMCExpr::VK_RISCV_PCREL_LO, Ctx); + emitToStreamer(Out, MCInstBuilder(SecondOpcode).addOperand(DestReg).addOperand(TmpReg).addExpr(RefToLinkTmpLabel)); + return false; + case RISCV::PseudoSB: + MCOperand DestReg = Inst.getOperand(0); + unsigned SymbolOpIdx = HasTmpReg ? 2 : 1; + unsigned TmpRegOpIdx = HasTmpReg ? 1 : 0; + MCOperand TmpReg = Inst.getOperand(TmpRegOpIdx); + const MCExpr *Symbol = Inst.getOperand(SymbolOpIdx).getExpr(); + MCContext &Ctx = getContext(); + MCSymbol *TmpLabel = Ctx.createNamedTempSymbol("pcrel_hi"); + Out.emitLabel(TmpLabel); + const RISCVMCExpr *SymbolHi = RISCVMCExpr::create(Symbol, VKHi, Ctx); + emitToStreamer(Out, MCInstBuilder(RISCV::AUIPC).addOperand(TmpReg).addExpr(SymbolHi)); + const MCExpr *RefToLinkTmpLabel = RISCVMCExpr::create(MCSymbolRefExpr::create(TmpLabel, Ctx), RISCVMCExpr::VK_RISCV_PCREL_LO, Ctx); + emitToStreamer(Out, MCInstBuilder(SecondOpcode).addOperand(DestReg).addOperand(TmpReg).addExpr(RefToLinkTmpLabel)); + return false; + case RISCV::PseudoSH: + MCOperand DestReg = Inst.getOperand(0); + unsigned SymbolOpIdx = HasTmpReg ? 2 : 1; + unsigned TmpRegOpIdx = HasTmpReg ? 1 : 0; + MCOperand TmpReg = Inst.getOperand(TmpRegOpIdx); + const MCExpr *Symbol = Inst.getOperand(SymbolOpIdx).getExpr(); + MCContext &Ctx = getContext(); + MCSymbol *TmpLabel = Ctx.createNamedTempSymbol("pcrel_hi"); + Out.emitLabel(TmpLabel); + const RISCVMCExpr *SymbolHi = RISCVMCExpr::create(Symbol, VKHi, Ctx); + emitToStreamer(Out, MCInstBuilder(RISCV::AUIPC).addOperand(TmpReg).addExpr(SymbolHi)); + const MCExpr *RefToLinkTmpLabel = RISCVMCExpr::create(MCSymbolRefExpr::create(TmpLabel, Ctx), RISCVMCExpr::VK_RISCV_PCREL_LO, Ctx); + emitToStreamer(Out, MCInstBuilder(SecondOpcode).addOperand(DestReg).addOperand(TmpReg).addExpr(RefToLinkTmpLabel)); + return false; + case RISCV::PseudoSW: + MCOperand DestReg = Inst.getOperand(0); + unsigned SymbolOpIdx = HasTmpReg ? 2 : 1; + unsigned TmpRegOpIdx = HasTmpReg ? 1 : 0; + MCOperand TmpReg = Inst.getOperand(TmpRegOpIdx); + const MCExpr *Symbol = Inst.getOperand(SymbolOpIdx).getExpr(); + MCContext &Ctx = getContext(); + MCSymbol *TmpLabel = Ctx.createNamedTempSymbol("pcrel_hi"); + Out.emitLabel(TmpLabel); + const RISCVMCExpr *SymbolHi = RISCVMCExpr::create(Symbol, VKHi, Ctx); + emitToStreamer(Out, MCInstBuilder(RISCV::AUIPC).addOperand(TmpReg).addExpr(SymbolHi)); + const MCExpr *RefToLinkTmpLabel = RISCVMCExpr::create(MCSymbolRefExpr::create(TmpLabel, Ctx), RISCVMCExpr::VK_RISCV_PCREL_LO, Ctx); + emitToStreamer(Out, MCInstBuilder(SecondOpcode).addOperand(DestReg).addOperand(TmpReg).addExpr(RefToLinkTmpLabel)); + return false; + case RISCV::PseudoSD: + MCOperand DestReg = Inst.getOperand(0); + unsigned SymbolOpIdx = HasTmpReg ? 2 : 1; + unsigned TmpRegOpIdx = HasTmpReg ? 1 : 0; + MCOperand TmpReg = Inst.getOperand(TmpRegOpIdx); + const MCExpr *Symbol = Inst.getOperand(SymbolOpIdx).getExpr(); + MCContext &Ctx = getContext(); + MCSymbol *TmpLabel = Ctx.createNamedTempSymbol("pcrel_hi"); + Out.emitLabel(TmpLabel); + const RISCVMCExpr *SymbolHi = RISCVMCExpr::create(Symbol, VKHi, Ctx); + emitToStreamer(Out, MCInstBuilder(RISCV::AUIPC).addOperand(TmpReg).addExpr(SymbolHi)); + const MCExpr *RefToLinkTmpLabel = RISCVMCExpr::create(MCSymbolRefExpr::create(TmpLabel, Ctx), RISCVMCExpr::VK_RISCV_PCREL_LO, Ctx); + emitToStreamer(Out, MCInstBuilder(SecondOpcode).addOperand(DestReg).addOperand(TmpReg).addExpr(RefToLinkTmpLabel)); + return false; + case RISCV::PseudoFSH: + MCOperand DestReg = Inst.getOperand(0); + unsigned SymbolOpIdx = HasTmpReg ? 2 : 1; + unsigned TmpRegOpIdx = HasTmpReg ? 1 : 0; + MCOperand TmpReg = Inst.getOperand(TmpRegOpIdx); + const MCExpr *Symbol = Inst.getOperand(SymbolOpIdx).getExpr(); + MCContext &Ctx = getContext(); + MCSymbol *TmpLabel = Ctx.createNamedTempSymbol("pcrel_hi"); + Out.emitLabel(TmpLabel); + const RISCVMCExpr *SymbolHi = RISCVMCExpr::create(Symbol, VKHi, Ctx); + emitToStreamer(Out, MCInstBuilder(RISCV::AUIPC).addOperand(TmpReg).addExpr(SymbolHi)); + const MCExpr *RefToLinkTmpLabel = RISCVMCExpr::create(MCSymbolRefExpr::create(TmpLabel, Ctx), RISCVMCExpr::VK_RISCV_PCREL_LO, Ctx); + emitToStreamer(Out, MCInstBuilder(SecondOpcode).addOperand(DestReg).addOperand(TmpReg).addExpr(RefToLinkTmpLabel)); + return false; + case RISCV::PseudoFSW: + MCOperand DestReg = Inst.getOperand(0); + unsigned SymbolOpIdx = HasTmpReg ? 2 : 1; + unsigned TmpRegOpIdx = HasTmpReg ? 1 : 0; + MCOperand TmpReg = Inst.getOperand(TmpRegOpIdx); + const MCExpr *Symbol = Inst.getOperand(SymbolOpIdx).getExpr(); + MCContext &Ctx = getContext(); + MCSymbol *TmpLabel = Ctx.createNamedTempSymbol("pcrel_hi"); + Out.emitLabel(TmpLabel); + const RISCVMCExpr *SymbolHi = RISCVMCExpr::create(Symbol, VKHi, Ctx); + emitToStreamer(Out, MCInstBuilder(RISCV::AUIPC).addOperand(TmpReg).addExpr(SymbolHi)); + const MCExpr *RefToLinkTmpLabel = RISCVMCExpr::create(MCSymbolRefExpr::create(TmpLabel, Ctx), RISCVMCExpr::VK_RISCV_PCREL_LO, Ctx); + emitToStreamer(Out, MCInstBuilder(SecondOpcode).addOperand(DestReg).addOperand(TmpReg).addExpr(RefToLinkTmpLabel)); + return false; + case RISCV::PseudoFSD: + MCOperand DestReg = Inst.getOperand(0); + unsigned SymbolOpIdx = HasTmpReg ? 2 : 1; + unsigned TmpRegOpIdx = HasTmpReg ? 1 : 0; + MCOperand TmpReg = Inst.getOperand(TmpRegOpIdx); + const MCExpr *Symbol = Inst.getOperand(SymbolOpIdx).getExpr(); + MCContext &Ctx = getContext(); + MCSymbol *TmpLabel = Ctx.createNamedTempSymbol("pcrel_hi"); + Out.emitLabel(TmpLabel); + const RISCVMCExpr *SymbolHi = RISCVMCExpr::create(Symbol, VKHi, Ctx); + emitToStreamer(Out, MCInstBuilder(RISCV::AUIPC).addOperand(TmpReg).addExpr(SymbolHi)); + const MCExpr *RefToLinkTmpLabel = RISCVMCExpr::create(MCSymbolRefExpr::create(TmpLabel, Ctx), RISCVMCExpr::VK_RISCV_PCREL_LO, Ctx); + emitToStreamer(Out, MCInstBuilder(SecondOpcode).addOperand(DestReg).addOperand(TmpReg).addExpr(RefToLinkTmpLabel)); + return false; + case RISCV::PseudoAddTPRel: + assert(Inst.getOpcode() == RISCV::PseudoAddTPRel && "Invalid instruction"); + assert(Inst.getOperand(2).isReg() && "Unexpected second operand kind"); + if (Inst.getOperand(2).getReg() != RISCV::X4) { + SMLoc ErrorLoc = ((RISCVOperand &)*Operands[3]).getStartLoc(); + return Error(ErrorLoc, "the second input operand must be tp/x4 when using %tprel_add modifier"); + } + break; + case RISCV::PseudoSEXT_B: + MCOperand DestReg = Inst.getOperand(0); + MCOperand SourceReg = Inst.getOperand(1); + unsigned SecondOpcode = SignExtend ? RISCV::SRAI : RISCV::SRLI; + int64_t ShAmt = (isRV64() ? 64 : 32) - Width; + assert(ShAmt > 0 && "Shift amount must be non-zero."); + emitToStreamer(Out, MCInstBuilder(RISCV::SLLI).addOperand(DestReg).addOperand(SourceReg).addImm(ShAmt)); + emitToStreamer(Out, MCInstBuilder(SecondOpcode).addOperand(DestReg).addOperand(DestReg).addImm(ShAmt)); + return false; + case RISCV::PseudoSEXT_H: + MCOperand DestReg = Inst.getOperand(0); + MCOperand SourceReg = Inst.getOperand(1); + unsigned SecondOpcode = SignExtend ? RISCV::SRAI : RISCV::SRLI; + int64_t ShAmt = (isRV64() ? 64 : 32) - Width; + assert(ShAmt > 0 && "Shift amount must be non-zero."); + emitToStreamer(Out, MCInstBuilder(RISCV::SLLI).addOperand(DestReg).addOperand(SourceReg).addImm(ShAmt)); + emitToStreamer(Out, MCInstBuilder(SecondOpcode).addOperand(DestReg).addOperand(DestReg).addImm(ShAmt)); + return false; + case RISCV::PseudoZEXT_H: + MCOperand DestReg = Inst.getOperand(0); + MCOperand SourceReg = Inst.getOperand(1); + unsigned SecondOpcode = SignExtend ? RISCV::SRAI : RISCV::SRLI; + int64_t ShAmt = (isRV64() ? 64 : 32) - Width; + assert(ShAmt > 0 && "Shift amount must be non-zero."); + emitToStreamer(Out, MCInstBuilder(RISCV::SLLI).addOperand(DestReg).addOperand(SourceReg).addImm(ShAmt)); + emitToStreamer(Out, MCInstBuilder(SecondOpcode).addOperand(DestReg).addOperand(DestReg).addImm(ShAmt)); + return false; + case RISCV::PseudoZEXT_W: + MCOperand DestReg = Inst.getOperand(0); + MCOperand SourceReg = Inst.getOperand(1); + unsigned SecondOpcode = SignExtend ? RISCV::SRAI : RISCV::SRLI; + int64_t ShAmt = (isRV64() ? 64 : 32) - Width; + assert(ShAmt > 0 && "Shift amount must be non-zero."); + emitToStreamer(Out, MCInstBuilder(RISCV::SLLI).addOperand(DestReg).addOperand(SourceReg).addImm(ShAmt)); + emitToStreamer(Out, MCInstBuilder(SecondOpcode).addOperand(DestReg).addOperand(DestReg).addImm(ShAmt)); + return false; + case RISCV::PseudoVMSGEU_VX: + case RISCV::PseudoVMSGEU_VX_M: + case RISCV::PseudoVMSGEU_VX_M_T: + if (Inst.getNumOperands() == 3) { + emitToStreamer(Out, MCInstBuilder(Opcode).addOperand(Inst.getOperand(0)).addOperand(Inst.getOperand(1)).addOperand(Inst.getOperand(2)).addReg(RISCV::NoRegister)); + emitToStreamer(Out, MCInstBuilder(RISCV::VMNAND_MM).addOperand(Inst.getOperand(0)).addOperand(Inst.getOperand(0)).addOperand(Inst.getOperand(0))); + } + else if (Inst.getNumOperands() == 4) { + assert(Inst.getOperand(0).getReg() != RISCV::V0 && "The destination register should not be V0."); + emitToStreamer(Out, MCInstBuilder(Opcode).addOperand(Inst.getOperand(0)).addOperand(Inst.getOperand(1)).addOperand(Inst.getOperand(2)).addOperand(Inst.getOperand(3))); + emitToStreamer(Out, MCInstBuilder(RISCV::VMXOR_MM).addOperand(Inst.getOperand(0)).addOperand(Inst.getOperand(0)).addReg(RISCV::V0)); + } + else if (Inst.getNumOperands() == 5) { + assert(Inst.getOperand(0).getReg() == RISCV::V0 && "The destination register should be V0."); + assert(Inst.getOperand(1).getReg() != RISCV::V0 && "The temporary vector register should not be V0."); + emitToStreamer(Out, MCInstBuilder(Opcode).addOperand(Inst.getOperand(1)).addOperand(Inst.getOperand(2)).addOperand(Inst.getOperand(3)).addOperand(Inst.getOperand(4))); + emitToStreamer(Out, MCInstBuilder(RISCV::VMANDNOT_MM).addOperand(Inst.getOperand(0)).addOperand(Inst.getOperand(0)).addOperand(Inst.getOperand(1))); + } + return false; + case RISCV::PseudoVMSGE_VX: + case RISCV::PseudoVMSGE_VX_M: + case RISCV::PseudoVMSGE_VX_M_T: + if (Inst.getNumOperands() == 3) { + emitToStreamer(Out, MCInstBuilder(Opcode).addOperand(Inst.getOperand(0)).addOperand(Inst.getOperand(1)).addOperand(Inst.getOperand(2)).addReg(RISCV::NoRegister)); + emitToStreamer(Out, MCInstBuilder(RISCV::VMNAND_MM).addOperand(Inst.getOperand(0)).addOperand(Inst.getOperand(0)).addOperand(Inst.getOperand(0))); + } + else if (Inst.getNumOperands() == 4) { + assert(Inst.getOperand(0).getReg() != RISCV::V0 && "The destination register should not be V0."); + emitToStreamer(Out, MCInstBuilder(Opcode).addOperand(Inst.getOperand(0)).addOperand(Inst.getOperand(1)).addOperand(Inst.getOperand(2)).addOperand(Inst.getOperand(3))); + emitToStreamer(Out, MCInstBuilder(RISCV::VMXOR_MM).addOperand(Inst.getOperand(0)).addOperand(Inst.getOperand(0)).addReg(RISCV::V0)); + } + else if (Inst.getNumOperands() == 5) { + assert(Inst.getOperand(0).getReg() == RISCV::V0 && "The destination register should be V0."); + assert(Inst.getOperand(1).getReg() != RISCV::V0 && "The temporary vector register should not be V0."); + emitToStreamer(Out, MCInstBuilder(Opcode).addOperand(Inst.getOperand(1)).addOperand(Inst.getOperand(2)).addOperand(Inst.getOperand(3)).addOperand(Inst.getOperand(4))); + emitToStreamer(Out, MCInstBuilder(RISCV::VMANDNOT_MM).addOperand(Inst.getOperand(0)).addOperand(Inst.getOperand(0)).addOperand(Inst.getOperand(1))); + } + return false; + case RISCV::PseudoVMSGE_VI: + case RISCV::PseudoVMSLT_VI: { + int64_t Imm = Inst.getOperand(2).getImm(); + unsigned Opc = Inst.getOpcode() == RISCV::PseudoVMSGE_VI ? RISCV::VMSGT_VI : RISCV::VMSLE_VI; + emitToStreamer(Out, MCInstBuilder(Opc).addOperand(Inst.getOperand(0)).addOperand(Inst.getOperand(1)).addImm(Imm - 1).addOperand(Inst.getOperand(3))); + return false; + } + case RISCV::PseudoVMSGEU_VI: + case RISCV::PseudoVMSLTU_VI: { + int64_t Imm = Inst.getOperand(2).getImm(); + if (Imm == 0) { + unsigned Opc = Inst.getOpcode() == RISCV::PseudoVMSGEU_VI ? RISCV::VMSEQ_VV : RISCV::VMSNE_VV; + emitToStreamer(Out, MCInstBuilder(Opc).addOperand(Inst.getOperand(0)).addOperand(Inst.getOperand(1)).addOperand(Inst.getOperand(1)).addOperand(Inst.getOperand(3))); + } + else { + unsigned Opc = Inst.getOpcode() == RISCV::PseudoVMSGEU_VI ? RISCV::VMSGTU_VI : RISCV::VMSLEU_VI; + emitToStreamer(Out, MCInstBuilder(Opc).addOperand(Inst.getOperand(0)).addOperand(Inst.getOperand(1)).addImm(Imm - 1).addOperand(Inst.getOperand(3))); + } + return false; + } + } + emitToStreamer(Out, Inst); + return false; + case Match_MissingFeature: { + assert(MissingFeatures.any() && "Unknown missing features!"); + bool FirstFeature = true; + std::string Msg = "instruction requires the following:"; + for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i) { + if (MissingFeatures[i]) { + Msg += FirstFeature ? " " : ", "; + Msg += getSubtargetFeatureName(i); + FirstFeature = false; + } + } + return Error(IDLoc, Msg); + } + case Match_MnemonicFail: { + FeatureBitset FBS = ComputeAvailableFeatures(getSTI().getFeatureBits()); + std::string Suggestion = RISCVMnemonicSpellCheck(((RISCVOperand &)*Operands[0]).getToken(), FBS); + return Error(IDLoc, "unrecognized instruction mnemonic" + Suggestion); + } + case Match_InvalidOperand: { + SMLoc ErrorLoc = IDLoc; + if (ErrorInfo != ~0U) { + if (ErrorInfo >= Operands.size()) { + return Error(ErrorLoc, "too few operands for instruction"); + } + ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc(); + if (ErrorLoc == SMLoc()) { + ErrorLoc = IDLoc; + } + } + return Error(ErrorLoc, "invalid operand for instruction"); + } + } + if (Result > FIRST_TARGET_MATCH_RESULT_TY) { + SMLoc ErrorLoc = IDLoc; + if (ErrorInfo != ~0U && ErrorInfo >= Operands.size()) { + return Error(ErrorLoc, "too few operands for instruction"); + } + } + if (Result == Match_InvalidImmXLenLI) { + if (isRV64()) { + SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc(); + return Error(ErrorLoc, "operand must be a constant 64-bit integer"); + } + return generateImmOutOfRangeError(Operands, ErrorInfo, std::numeric_limits::min(), std::numeric_limits::max()); + } + if (Result == Match_InvalidImmZero) { + SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc(); + return Error(ErrorLoc, "immediate must be zero"); + } + if (Result == Match_InvalidUImmLog2XLen) { + if (isRV64()) { + return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 6) - 1); + } + return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 5) - 1); + } + if (Result == Match_InvalidUImmLog2XLenNonZero) { + if (isRV64()) { + return generateImmOutOfRangeError(Operands, ErrorInfo, 1, (1 << 6) - 1); + } + return generateImmOutOfRangeError(Operands, ErrorInfo, 1, (1 << 5) - 1); + } + if (Result == Match_InvalidUImmLog2XLenHalf) { + if (isRV64()) { + return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 5) - 1); + } + return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 4) - 1); + } + if (Result == Match_InvalidUImm5) { + return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 5) - 1); + } + if (Result == Match_InvalidSImm5) { + return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 4), (1 << 4) - 1); + } + if (Result == Match_InvalidSImm6) { + return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 5), (1 << 5) - 1); + } + if (Result == Match_InvalidSImm6NonZero) { + return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 5), (1 << 5) - 1, "immediate must be non-zero in the range"); + } + if (Result == Match_InvalidCLUIImm) { + return generateImmOutOfRangeError(Operands, ErrorInfo, 1, (1 << 5) - 1, "immediate must be in [0xfffe0, 0xfffff] or"); + } + if (Result == Match_InvalidUImm7Lsb00) { + return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 7) - 4, "immediate must be a multiple of 4 bytes in the range"); + } + if (Result == Match_InvalidUImm8Lsb00) { + return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 8) - 4, "immediate must be a multiple of 4 bytes in the range"); + } + if (Result == Match_InvalidUImm8Lsb000) { + return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 8) - 8, "immediate must be a multiple of 8 bytes in the range"); + } + if (Result == Match_InvalidSImm9Lsb0) { + return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 8), (1 << 8) - 2, "immediate must be a multiple of 2 bytes in the range"); + } + if (Result == Match_InvalidUImm9Lsb000) { + return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 8), (1 << 8) - 2, "immediate must be a multiple of 2 bytes in the range"); + } + if (Result == Match_InvalidUImm10Lsb00NonZero) { + return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 8), (1 << 8) - 2, "immediate must be a multiple of 2 bytes in the range"); + } + if (Result == Match_InvalidSImm10Lsb0000NonZero) { + return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 8), (1 << 8) - 2, "immediate must be a multiple of 2 bytes in the range"); + } + if (Result == Match_InvalidSImm12) { + return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 8), (1 << 8) - 2, "immediate must be a multiple of 2 bytes in the range"); + } + if (Result == Match_InvalidSImm12Lsb0) { + return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 8), (1 << 8) - 2, "immediate must be a multiple of 2 bytes in the range"); + } + if (Result == Match_InvalidSImm13Lsb0) { + return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 8), (1 << 8) - 2, "immediate must be a multiple of 2 bytes in the range"); + } + if (Result == Match_InvalidUImm20LUI) { + return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 8), (1 << 8) - 2, "immediate must be a multiple of 2 bytes in the range"); + } + if (Result == Match_InvalidUImm20AUIPC) { + return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 8), (1 << 8) - 2, "immediate must be a multiple of 2 bytes in the range"); + } + if (Result == Match_InvalidSImm21Lsb0JAL) { + return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 8), (1 << 8) - 2, "immediate must be a multiple of 2 bytes in the range"); + } + if (Result == Match_InvalidCSRSystemRegister) { + return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 8), (1 << 8) - 2, "immediate must be a multiple of 2 bytes in the range"); + } + if (Result == Match_InvalidFenceArg) { + SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc(); + return Error(ErrorLoc, "operand must be formed of letters selected in-order from 'iorw'"); + } + if (Result == Match_InvalidFRMArg) { + SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc(); + return Error(ErrorLoc, "operand must be formed of letters selected in-order from 'iorw'"); + } + if (Result == Match_InvalidBareSymbol) { + SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc(); + return Error(ErrorLoc, "operand must be formed of letters selected in-order from 'iorw'"); + } + if (Result == Match_InvalidPseudoJumpSymbol) { + SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc(); + return Error(ErrorLoc, "operand must be formed of letters selected in-order from 'iorw'"); + } + if (Result == Match_InvalidCallSymbol) { + SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc(); + return Error(ErrorLoc, "operand must be formed of letters selected in-order from 'iorw'"); + } + if (Result == Match_InvalidTPRelAddSymbol) { + SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc(); + return Error(ErrorLoc, "operand must be formed of letters selected in-order from 'iorw'"); + } + if (Result == Match_InvalidVTypeI) { + SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc(); + return Error(ErrorLoc, "operand must be formed of letters selected in-order from 'iorw'"); + } + if (Result == Match_InvalidVMaskRegister) { + SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc(); + return Error(ErrorLoc, "operand must be formed of letters selected in-order from 'iorw'"); + } + if (Result == Match_InvalidSImm5Plus1) { + return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 4) + 1, (1 << 4), "immediate must be in the range"); + } + llvm_unreachable("Unknown match type detected!"); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/Operand.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/Operand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ad138dbf9306883ea3346180a9391df10b1586d0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/Operand.cpp @@ -0,0 +1,2 @@ +RISCVOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/Operand2.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/Operand2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..63faea7f475d64855bbadb5f070b7ef2b0026308 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/Operand2.cpp @@ -0,0 +1,21 @@ +RISCVOperand(const RISCVOperand &o) : MCParsedAsmOperand() { + Kind = o.Kind; + IsRV64 = o.IsRV64; + StartLoc = o.StartLoc; + EndLoc = o.EndLoc; + if (Kind == KindTy::Register) { + Reg = o.Reg; + } + if (Kind == KindTy::Immediate) { + Imm = o.Imm; + } + if (Kind == KindTy::Token) { + Tok = o.Tok; + } + if (Kind == KindTy::SystemRegister) { + SysReg = o.SysReg; + } + if (Kind == KindTy::VType) { + VType = o.VType; + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/ParseDirective.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/ParseDirective.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4af12e125e12358102bf5a3e08bf0bd44dfaf4e1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/ParseDirective.cpp @@ -0,0 +1,437 @@ +bool RISCVAsmParser::ParseDirective(AsmToken DirectiveID) { + StringRef IDVal = DirectiveID.getString(); + if (IDVal == ".option") { + MCAsmParser &Parser = getParser(); + AsmToken Tok = Parser.getTok(); + if (Tok.isNot(AsmToken::Identifier)) { + return Error(Parser.getTok().getLoc(), "unexpected token, expected identifier"); + } + StringRef Option = Tok.getIdentifier(); + if (Option == "push") { + getTargetStreamer().emitDirectiveOptionPush(); + Parser.Lex(); + if (Parser.getTok().isNot(AsmToken::EndOfStatement)) { + return Error(Parser.getTok().getLoc(), "unexpected token, expected end of statement"); + } + assert(FeatureBitStack.size() == ParserOptionsStack.size() && "These two stacks must be kept synchronized"); + FeatureBitStack.push_back(getSTI().getFeatureBits()); + ParserOptionsStack.push_back(ParserOptions); + return false; + } + if (Option == "pop") { + SMLoc StartLoc = Parser.getTok().getLoc(); + getTargetStreamer().emitDirectiveOptionPop(); + Parser.Lex(); + if (Parser.getTok().isNot(AsmToken::EndOfStatement)) { + return Error(Parser.getTok().getLoc(), "unexpected token, expected end of statement"); + } + assert(FeatureBitStack.size() == ParserOptionsStack.size() && "These two stacks must be kept synchronized"); + if (FeatureBitStack.empty()) { + return Error(StartLoc, ".option pop with no .option push"); + } + FeatureBitset FeatureBits = FeatureBitStack.pop_back_val(); + copySTI().setFeatureBits(FeatureBits); + setAvailableFeatures(ComputeAvailableFeatures(FeatureBits)); + ParserOptions = ParserOptionsStack.pop_back_val(); + return false; + } + if (Option == "rvc") { + getTargetStreamer().emitDirectiveOptionRVC(); + Parser.Lex(); + if (Parser.getTok().isNot(AsmToken::EndOfStatement)) { + return Error(Parser.getTok().getLoc(), "unexpected token, expected end of statement"); + } + setFeatureBits(RISCV::FeatureStdExtC, "c"); + return false; + } + if (Option == "norvc") { + getTargetStreamer().emitDirectiveOptionNoRVC(); + Parser.Lex(); + if (Parser.getTok().isNot(AsmToken::EndOfStatement)) { + return Error(Parser.getTok().getLoc(), "unexpected token, expected end of statement"); + } + clearFeatureBits(RISCV::FeatureStdExtC, "c"); + return false; + } + if (Option == "pic") { + getTargetStreamer().emitDirectiveOptionPIC(); + Parser.Lex(); + if (Parser.getTok().isNot(AsmToken::EndOfStatement)) { + return Error(Parser.getTok().getLoc(), "unexpected token, expected end of statement"); + } + ParserOptions.IsPicEnabled = true; + return false; + } + if (Option == "nopic") { + getTargetStreamer().emitDirectiveOptionNoPIC(); + Parser.Lex(); + if (Parser.getTok().isNot(AsmToken::EndOfStatement)) { + return Error(Parser.getTok().getLoc(), "unexpected token, expected end of statement"); + } + ParserOptions.IsPicEnabled = false; + return false; + } + if (Option == "relax") { + getTargetStreamer().emitDirectiveOptionRelax(); + Parser.Lex(); + if (Parser.getTok().isNot(AsmToken::EndOfStatement)) { + return Error(Parser.getTok().getLoc(), "unexpected token, expected end of statement"); + } + setFeatureBits(RISCV::FeatureRelax, "relax"); + return false; + } + if (Option == "norelax") { + getTargetStreamer().emitDirectiveOptionNoRelax(); + Parser.Lex(); + if (Parser.getTok().isNot(AsmToken::EndOfStatement)) { + return Error(Parser.getTok().getLoc(), "unexpected token, expected end of statement"); + } + clearFeatureBits(RISCV::FeatureRelax, "relax"); + return false; + } + Warning(Parser.getTok().getLoc(), "unknown option, expected 'push', 'pop', 'rvc', 'norvc', 'relax' or 'norelax'"); + Parser.eatToEndOfStatement(); + return false; + } + else if (IDVal == ".attribute") { + MCAsmParser &Parser = getParser(); + int64_t Tag; + SMLoc TagLoc; + TagLoc = Parser.getTok().getLoc(); + if (Parser.getTok().is(AsmToken::Identifier)) { + StringRef Name = Parser.getTok().getIdentifier(); + Optional Ret = ELFAttrs::attrTypeFromString(Name, RISCVAttrs::RISCVAttributeTags); + if (!Ret.hasValue()) { + Error(TagLoc, "attribute name not recognised: " + Name); + return false; + } + Tag = Ret.getValue(); + Parser.Lex(); + } + else { + const MCExpr *AttrExpr; + TagLoc = Parser.getTok().getLoc(); + if (Parser.parseExpression(AttrExpr)) { + return true; + } + const MCConstantExpr *CE = dyn_cast(AttrExpr); + if (check(!CE, TagLoc, "expected numeric constant")) { + return true; + } + Tag = CE->getValue(); + } + if (Parser.parseToken(AsmToken::Comma, "comma expected")) { + return true; + } + StringRef StringValue; + int64_t IntegerValue = 0; + bool IsIntegerValue = true; + if (Tag % 2) { + IsIntegerValue = false; + } + SMLoc ValueExprLoc = Parser.getTok().getLoc(); + if (IsIntegerValue) { + const MCExpr *ValueExpr; + if (Parser.parseExpression(ValueExpr)) { + return true; + } + const MCConstantExpr *CE = dyn_cast(ValueExpr); + if (!CE) { + return true; + } + IntegerValue = CE->getValue(); + } + else { + if (Parser.getTok().isNot(AsmToken::String)) { + return Error(Parser.getTok().getLoc(), "expected string constant"); + } + StringValue = Parser.getTok().getStringContents(); + Parser.Lex(); + } + if (Parser.parseToken(AsmToken::EndOfStatement, "unexpected token in '.attribute' directive")) { + return true; + } + if (Tag == RISCVAttrs::ARCH) { + StringRef Arch = StringValue; + if (Arch.consume_front("rv32")) { + if (getSTI().getFeatureBits()[RISCV::Feature64Bit]) { + MCSubtargetInfo &STI = copySTI(); + setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature("64bit"))); + } + } + else if (Arch.consume_front("rv64")) { + setFeatureBits(RISCV::Feature64Bit, "64bit"); + } + else { + return Error(ValueExprLoc, "bad arch string " + Arch); + } + if (getSTI().getFeatureBits()[RISCV::FeatureRV32E]) { + MCSubtargetInfo &STI = copySTI(); + setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature("e"))); + } + if (getSTI().getFeatureBits()[RISCV::FeatureStdExtM]) { + MCSubtargetInfo &STI = copySTI(); + setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature("m"))); + } + if (getSTI().getFeatureBits()[RISCV::FeatureStdExtA]) { + MCSubtargetInfo &STI = copySTI(); + setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature("a"))); + } + if (getSTI().getFeatureBits()[RISCV::FeatureStdExtF]) { + MCSubtargetInfo &STI = copySTI(); + setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature("f"))); + } + if (getSTI().getFeatureBits()[RISCV::FeatureStdExtD]) { + MCSubtargetInfo &STI = copySTI(); + setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature("d"))); + } + if (getSTI().getFeatureBits()[RISCV::FeatureStdExtC]) { + MCSubtargetInfo &STI = copySTI(); + setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature("c"))); + } + if (getSTI().getFeatureBits()[RISCV::FeatureStdExtB]) { + MCSubtargetInfo &STI = copySTI(); + setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature("experimental-b"))); + } + if (getSTI().getFeatureBits()[RISCV::FeatureStdExtV]) { + MCSubtargetInfo &STI = copySTI(); + setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature("experimental-v"))); + } + if (getSTI().getFeatureBits()[RISCV::FeatureExtZfh]) { + MCSubtargetInfo &STI = copySTI(); + setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature("experimental-zfh"))); + } + if (getSTI().getFeatureBits()[RISCV::FeatureExtZba]) { + MCSubtargetInfo &STI = copySTI(); + setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature("experimental-zba"))); + } + if (getSTI().getFeatureBits()[RISCV::FeatureExtZbb]) { + MCSubtargetInfo &STI = copySTI(); + setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature("experimental-zbb"))); + } + if (getSTI().getFeatureBits()[RISCV::FeatureExtZbc]) { + MCSubtargetInfo &STI = copySTI(); + setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature("experimental-zbc"))); + } + if (getSTI().getFeatureBits()[RISCV::FeatureExtZbe]) { + MCSubtargetInfo &STI = copySTI(); + setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature("experimental-zbe"))); + } + if (getSTI().getFeatureBits()[RISCV::FeatureExtZbf]) { + MCSubtargetInfo &STI = copySTI(); + setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature("experimental-zbf"))); + } + if (getSTI().getFeatureBits()[RISCV::FeatureExtZbm]) { + MCSubtargetInfo &STI = copySTI(); + setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature("experimental-zbm"))); + } + if (getSTI().getFeatureBits()[RISCV::FeatureExtZbp]) { + MCSubtargetInfo &STI = copySTI(); + setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature("experimental-zbp"))); + } + if (getSTI().getFeatureBits()[RISCV::FeatureExtZbproposedc]) { + MCSubtargetInfo &STI = copySTI(); + setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature("experimental-zbproposedc"))); + } + if (getSTI().getFeatureBits()[RISCV::FeatureExtZbr]) { + MCSubtargetInfo &STI = copySTI(); + setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature("experimental-zbr"))); + } + if (getSTI().getFeatureBits()[RISCV::FeatureExtZbs]) { + MCSubtargetInfo &STI = copySTI(); + setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature("experimental-zbs"))); + } + if (getSTI().getFeatureBits()[RISCV::FeatureExtZbt]) { + MCSubtargetInfo &STI = copySTI(); + setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature("experimental-zbt"))); + } + if (getSTI().getFeatureBits()[RISCV::FeatureExtZvamo]) { + MCSubtargetInfo &STI = copySTI(); + setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature("experimental-zvamo"))); + } + if (getSTI().getFeatureBits()[RISCV::FeatureStdExtZvlsseg]) { + MCSubtargetInfo &STI = copySTI(); + setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature("experimental-zvlsseg"))); + } + while (!Arch.empty()) { + bool DropFirst = true; + if (Arch[0] == 'i') { + if (getSTI().getFeatureBits()[RISCV::FeatureRV32E]) { + MCSubtargetInfo &STI = copySTI(); + setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature("e"))); + } + } + else if (Arch[0] == 'e') { + setFeatureBits(RISCV::FeatureRV32E, "e"); + } + else if (Arch[0] == 'g') { + if (getSTI().getFeatureBits()[RISCV::FeatureRV32E]) { + MCSubtargetInfo &STI = copySTI(); + setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature("e"))); + } + setFeatureBits(RISCV::FeatureStdExtM, "m"); + setFeatureBits(RISCV::FeatureStdExtA, "a"); + setFeatureBits(RISCV::FeatureStdExtF, "f"); + setFeatureBits(RISCV::FeatureStdExtD, "d"); + } + else if (Arch[0] == 'm') { + setFeatureBits(RISCV::FeatureStdExtM, "m"); + } + else if (Arch[0] == 'a') { + setFeatureBits(RISCV::FeatureStdExtA, "a"); + } + else if (Arch[0] == 'f') { + setFeatureBits(RISCV::FeatureStdExtF, "f"); + } + else if (Arch[0] == 'd') { + setFeatureBits(RISCV::FeatureStdExtF, "f"); + setFeatureBits(RISCV::FeatureStdExtD, "d"); + } + else if (Arch[0] == 'c') { + setFeatureBits(RISCV::FeatureStdExtC, "c"); + } + else if (Arch[0] == 'b') { + setFeatureBits(RISCV::FeatureStdExtB, "experimental-b"); + } + else if (Arch[0] == 'v') { + setFeatureBits(RISCV::FeatureStdExtV, "experimental-v"); + } + else if (Arch[0] == 's' || Arch[0] == 'x' || Arch[0] == 'z') { + StringRef Ext = Arch.take_until([](char c) { return ::isdigit(c) || c == '_'; }); + if (Ext == "zba") { + setFeatureBits(RISCV::FeatureExtZba, "experimental-zba"); + } + else if (Ext == "zbb") { + setFeatureBits(RISCV::FeatureExtZbb, "experimental-zbb"); + } + else if (Ext == "zbc") { + setFeatureBits(RISCV::FeatureExtZbc, "experimental-zbc"); + } + else if (Ext == "zbe") { + setFeatureBits(RISCV::FeatureExtZbe, "experimental-zbe"); + } + else if (Ext == "zbf") { + setFeatureBits(RISCV::FeatureExtZbf, "experimental-zbf"); + } + else if (Ext == "zbm") { + setFeatureBits(RISCV::FeatureExtZbm, "experimental-zbm"); + } + else if (Ext == "zbp") { + setFeatureBits(RISCV::FeatureExtZbp, "experimental-zbp"); + } + else if (Ext == "zbproposedc") { + setFeatureBits(RISCV::FeatureExtZbproposedc, "experimental-zbproposedc"); + } + else if (Ext == "zbr") { + setFeatureBits(RISCV::FeatureExtZbr, "experimental-zbr"); + } + else if (Ext == "zbs") { + setFeatureBits(RISCV::FeatureExtZbs, "experimental-zbs"); + } + else if (Ext == "zbt") { + setFeatureBits(RISCV::FeatureExtZbt, "experimental-zbt"); + } + else if (Ext == "zfh") { + setFeatureBits(RISCV::FeatureExtZfh, "experimental-zfh"); + } + else if (Ext == "zvamo") { + setFeatureBits(RISCV::FeatureExtZvamo, "experimental-zvamo"); + } + else if (Ext == "zvlsseg") { + setFeatureBits(RISCV::FeatureStdExtZvlsseg, "experimental-zvlsseg"); + } + else { + return Error(ValueExprLoc, "bad arch string " + Ext); + } + Arch = Arch.drop_until([](char c) { return ::isdigit(c) || c == '_'; }); + DropFirst = false; + } + else { + return Error(ValueExprLoc, "bad arch string " + Arch); + } + if (DropFirst) { + Arch = Arch.drop_front(1); + } + int major = 0; + int minor = 0; + Arch.consumeInteger(10, major); + Arch.consume_front("p"); + Arch.consumeInteger(10, minor); + Arch = Arch.drop_while([](char c) { return c == '_'; }); + } + } + if (IsIntegerValue) { + getTargetStreamer().emitAttribute(Tag, IntegerValue); + } + else { + if (Tag != RISCVAttrs::ARCH) { + getTargetStreamer().emitTextAttribute(Tag, StringValue); + } + else { + std::string formalArchStr = "rv32"; + if (getFeatureBits(RISCV::Feature64Bit)) + formalArchStr = "rv64"; + if (getFeatureBits(RISCV::FeatureRV32E)) + formalArchStr = (Twine(formalArchStr) + "e1p9").str(); + else + formalArchStr = (Twine(formalArchStr) + "i2p0").str(); + if (getFeatureBits(RISCV::FeatureStdExtM)) + formalArchStr = (Twine(formalArchStr) + "_m2p0").str(); + if (getFeatureBits(RISCV::FeatureStdExtA)) + formalArchStr = (Twine(formalArchStr) + "_a2p0").str(); + if (getFeatureBits(RISCV::FeatureStdExtF)) + formalArchStr = (Twine(formalArchStr) + "_f2p0").str(); + if (getFeatureBits(RISCV::FeatureStdExtD)) + formalArchStr = (Twine(formalArchStr) + "_d2p0").str(); + if (getFeatureBits(RISCV::FeatureStdExtC)) + formalArchStr = (Twine(formalArchStr) + "_c2p0").str(); + if (getFeatureBits(RISCV::FeatureStdExtB)) + formalArchStr = (Twine(formalArchStr) + "_b0p93").str(); + if (getFeatureBits(RISCV::FeatureStdExtV)) + formalArchStr = (Twine(formalArchStr) + "_v0p10").str(); + if (getFeatureBits(RISCV::FeatureExtZfh)) + formalArchStr = (Twine(formalArchStr) + "_zfh0p1").str(); + if (getFeatureBits(RISCV::FeatureExtZba)) + formalArchStr = (Twine(formalArchStr) + "_zba0p93").str(); + if (getFeatureBits(RISCV::FeatureExtZbb)) + formalArchStr = (Twine(formalArchStr) + "_zbb0p93").str(); + if (getFeatureBits(RISCV::FeatureExtZbc)) { + formalArchStr = (Twine(formalArchStr) + "_zbc0p93").str(); + } + if (getFeatureBits(RISCV::FeatureExtZbe)) { + formalArchStr = (Twine(formalArchStr) + "_zbe0p93").str(); + } + if (getFeatureBits(RISCV::FeatureExtZbf)) { + formalArchStr = (Twine(formalArchStr) + "_zbf0p93").str(); + } + if (getFeatureBits(RISCV::FeatureExtZbm)) { + formalArchStr = (Twine(formalArchStr) + "_zbm0p93").str(); + } + if (getFeatureBits(RISCV::FeatureExtZbp)) { + formalArchStr = (Twine(formalArchStr) + "_zbp0p93").str(); + } + if (getFeatureBits(RISCV::FeatureExtZbproposedc)) { + formalArchStr = (Twine(formalArchStr) + "_zbproposedc0p93").str(); + } + if (getFeatureBits(RISCV::FeatureExtZbr)) { + formalArchStr = (Twine(formalArchStr) + "_zbr0p93").str(); + } + if (getFeatureBits(RISCV::FeatureExtZbs)) { + formalArchStr = (Twine(formalArchStr) + "_zbs0p93").str(); + } + if (getFeatureBits(RISCV::FeatureExtZbt)) { + formalArchStr = (Twine(formalArchStr) + "_zbt0p93").str(); + } + if (getFeatureBits(RISCV::FeatureExtZvamo)) { + formalArchStr = (Twine(formalArchStr) + "_zvamo0p10").str(); + } + if (getFeatureBits(RISCV::FeatureStdExtZvlsseg)) { + formalArchStr = (Twine(formalArchStr) + "_zvlsseg0p10").str(); + } + getTargetStreamer().emitTextAttribute(Tag, formalArchStr); + } + } + return false; + } + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/ParseInstruction.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/ParseInstruction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7e9cdadb0936ababf2f6c45f59c54e181e9d21a4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/ParseInstruction.cpp @@ -0,0 +1,31 @@ +bool RISCVAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, OperandVector &Operands) { + if (getSTI().getFeatureBits()[RISCV::FeatureRelax]) { + auto *Assembler = getTargetStreamer().getStreamer().getAssemblerPtr(); + if (Assembler != nullptr) { + RISCVAsmBackend &MAB = static_cast(Assembler->getBackend()); + MAB.setForceRelocs(); + } + } + Operands.push_back(RISCVOperand::createToken(Name, NameLoc, isRV64())); + if (getLexer().is(AsmToken::EndOfStatement)) { + return false; + } + if (parseOperand(Operands, Name)) { + return true; + } + unsigned OperandIdx = 1; + while (getLexer().is(AsmToken::Comma)) { + getLexer().Lex(); + if (parseOperand(Operands, Name)) { + return true; + } + ++OperandIdx; + } + if (getLexer().isNot(AsmToken::EndOfStatement)) { + SMLoc Loc = getLexer().getLoc(); + getParser().eatToEndOfStatement(); + return Error(Loc, "unexpected token"); + } + getParser().Lex(); + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/ParseRegister.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/ParseRegister.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a5d4359121cc681b1667e4b723d63f8a260df120 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/ParseRegister.cpp @@ -0,0 +1,6 @@ +bool RISCVAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) { + if (tryParseRegister(RegNo, StartLoc, EndLoc) != MatchOperand_Success) { + return Error(StartLoc, "invalid register name"); + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/addCSRSystemRegisterOperands.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/addCSRSystemRegisterOperands.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ccc9683fc9110594147015b16f0c9b51543c0d2d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/addCSRSystemRegisterOperands.cpp @@ -0,0 +1,4 @@ +void addCSRSystemRegisterOperands(MCInst &Inst, unsigned N) const { + assert(N == 1 && "Invalid number of operands!"); + Inst.addOperand(MCOperand::createImm(SysReg.Encoding)); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/addExpr.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/addExpr.cpp new file mode 100644 index 0000000000000000000000000000000000000000..214fe9f44a01731c40c1084f3ff205132df9e262 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/addExpr.cpp @@ -0,0 +1,12 @@ +void addExpr(MCInst &Inst, const MCExpr *Expr) const { + assert(Expr && "Expr shouldn't be null!"); + int64_t Imm = 0; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + bool IsConstant = evaluateConstantImm(Expr, Imm, VK); + if (IsConstant) { + Inst.addOperand(MCOperand::createImm(Imm)); + } + else { + Inst.addOperand(MCOperand::createExpr(Expr)); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/addFRMArgOperands.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/addFRMArgOperands.cpp new file mode 100644 index 0000000000000000000000000000000000000000..73d49a88563d2c4aca26d1c150579bc82e0babf2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/addFRMArgOperands.cpp @@ -0,0 +1,4 @@ +void addFRMArgOperands(MCInst &Inst, unsigned N) const { + assert(N == 1 && "Invalid number of operands!"); + Inst.addOperand(MCOperand::createImm(getRoundingMode())); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/addFenceArgOperands.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/addFenceArgOperands.cpp new file mode 100644 index 0000000000000000000000000000000000000000..792d4fa164c9d9d497708692cc4167f5c14775a5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/addFenceArgOperands.cpp @@ -0,0 +1,16 @@ +void addFenceArgOperands(MCInst &Inst, unsigned N) const { + assert(N == 1 && "Invalid number of operands!"); + auto SE = cast(getImm()); + unsigned Imm = 0; + for (char c : SE->getSymbol().getName()) { + switch (c) { + default: + llvm_unreachable("FenceArg must contain only [iorw]"); + case 'i': Imm |= RISCVFenceField::I; break; + case 'o': Imm |= RISCVFenceField::O; break; + case 'r': Imm |= RISCVFenceField::R; break; + case 'w': Imm |= RISCVFenceField::W; break; + } + } + Inst.addOperand(MCOperand::createImm(Imm)); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/addImmOperands.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/addImmOperands.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a69f8ac923d9234ea41ac4606011cacda986f3e5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/addImmOperands.cpp @@ -0,0 +1,4 @@ +void addImmOperands(MCInst &Inst, unsigned N) const { + assert(N == 1 && "Invalid number of operands!"); + addExpr(Inst, getImm()); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/addRegOperands.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/addRegOperands.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0238a375be523b4d683ea934130d2e5390c7dfa7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/addRegOperands.cpp @@ -0,0 +1,4 @@ +void addRegOperands(MCInst &Inst, unsigned N) const { + assert(N == 1 && "Invalid number of operands!"); + Inst.addOperand(MCOperand::createReg(getReg())); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/addVTypeIOperands.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/addVTypeIOperands.cpp new file mode 100644 index 0000000000000000000000000000000000000000..47fb952384ac089c38b1615985b2fdd2e107225f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/addVTypeIOperands.cpp @@ -0,0 +1,4 @@ +void addVTypeIOperands(MCInst &Inst, unsigned N) const { + assert(N == 1 && "Invalid number of operands!"); + Inst.addOperand(MCOperand::createImm(getVType())); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/classifySymbolRef.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/classifySymbolRef.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e84a90bbcd6b57ad4a18f3de6f079fab9ea6ef6a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/classifySymbolRef.cpp @@ -0,0 +1,13 @@ +bool RISCVAsmParser::classifySymbolRef(const MCExpr *Expr, MCExpr::VariantKind &Kind) { + Kind = RISCVMCExpr::VK_RISCV_None; + if (const RISCVMCExpr *RE = dyn_cast(Expr)) { + Kind = RE->getKind(); + Expr = RE->getSubExpr(); + } + MCValue Res; + MCFixup Fixup; + if (Expr->evaluateAsRelocatable(Res, nullptr, &Fixup)) { + return Res.getRefKind() == RISCVMCExpr::VK_RISCV_None; + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/convertFPR64ToFPR16.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/convertFPR64ToFPR16.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e026cba6a73b81985778dc9bb3c9d65b32fb1666 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/convertFPR64ToFPR16.cpp @@ -0,0 +1,4 @@ +static MCRegister convertFPR64ToFPR16(MCRegister Reg) { + assert(Reg >= RISCV::F0_D && Reg <= RISCV::F31_D && "Invalid register"); + return Reg - RISCV::F0_D + RISCV::F0_H; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/convertFPR64ToFPR32.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/convertFPR64ToFPR32.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6f4dc9ae940f1dd462ac08522f4c04f563e554d8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/convertFPR64ToFPR32.cpp @@ -0,0 +1,4 @@ +static MCRegister convertFPR64ToFPR32(MCRegister Reg) { + assert(Reg >= RISCV::F0_D && Reg <= RISCV::F31_D && "Invalid register"); + return Reg - RISCV::F0_D + RISCV::F0_F; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/createImm.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/createImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..399ee2614f3b539f1368f7c10cdc6e506119e381 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/createImm.cpp @@ -0,0 +1,8 @@ +static std::unique_ptr createImm(const MCExpr *Val, SMLoc S, SMLoc E, bool IsRV64) { + auto Op = std::make_unique(KindTy::Immediate); + Op->Imm.Val = Val; + Op->StartLoc = S; + Op->EndLoc = E; + Op->IsRV64 = IsRV64; + return Op; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/createReg.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/createReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6c2c43a6a8093aa2194f4fba74917b2fc21eb193 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/createReg.cpp @@ -0,0 +1,8 @@ +static std::unique_ptr createReg(unsigned RegNo, SMLoc S, SMLoc E, bool IsRV64) { + auto Op = std::make_unique(KindTy::Register); + Op->Reg.RegNum = RegNo; + Op->StartLoc = S; + Op->EndLoc = E; + Op->IsRV64 = IsRV64; + return Op; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/createSysReg.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/createSysReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1b7a2657c346e52c22ccd28703bc5baa75cff344 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/createSysReg.cpp @@ -0,0 +1,9 @@ +static std::unique_ptr createSysReg(StringRef Str, SMLoc S, unsigned Encoding, bool IsRV64) { + auto Op = std::make_unique(KindTy::SystemRegister); + Op->SysReg.Data = Str.data(); + Op->SysReg.Length = Str.size(); + Op->SysReg.Encoding = Encoding; + Op->StartLoc = S; + Op->IsRV64 = IsRV64; + return Op; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/createToken.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/createToken.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bdaa650df5adf6dc96daae935f42ae08ac7f4283 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/createToken.cpp @@ -0,0 +1,8 @@ +static std::unique_ptr createToken(StringRef Str, SMLoc S, bool IsRV64) { + auto Op = std::make_unique(KindTy::Token); + Op->Tok = Str; + Op->StartLoc = S; + Op->EndLoc = S; + Op->IsRV64 = IsRV64; + return Op; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/createVType.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/createVType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4deb57ffa06e779c7e3e92cae9f34bdba8a9d9b9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/createVType.cpp @@ -0,0 +1,7 @@ +static std::unique_ptr createVType(unsigned VTypeI, SMLoc S, bool IsRV64) { + auto Op = std::make_unique(KindTy::VType); + Op->VType.Val = VTypeI; + Op->StartLoc = S; + Op->IsRV64 = IsRV64; + return Op; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/defaultMaskRegOp.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/defaultMaskRegOp.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b022f4d2360a1bb7aae0c7121a89aae81ffb4c75 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/defaultMaskRegOp.cpp @@ -0,0 +1,3 @@ +std::unique_ptr RISCVAsmParser::defaultMaskRegOp() const { + return RISCVOperand::createReg(RISCV::NoRegister, llvm::SMLoc(), llvm::SMLoc(), isRV64()); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/emitToStreamer.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/emitToStreamer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..85deea136f491e311c7514cc7cc3319a332e069d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/emitToStreamer.cpp @@ -0,0 +1,9 @@ +void RISCVAsmParser::emitToStreamer(MCStreamer &S, const MCInst &Inst) { + MCInst CInst; + bool Res = false; + Res = compressInst(CInst, Inst, getSTI(), S.getContext()); + if (Res) { + RISCVNumInstrsCompressed = RISCVNumInstrsCompressed + 1; + } + S.emitInstruction((Res ? CInst : Inst), getSTI()); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/evaluateConstantImm.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/evaluateConstantImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..66157e504bc3b499d080b12e3a0c1b14ae434c52 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/evaluateConstantImm.cpp @@ -0,0 +1,12 @@ +static bool evaluateConstantImm(const MCExpr *Expr, int64_t &Imm, RISCVMCExpr::VariantKind &VK) { + if (auto *RE = dyn_cast(Expr)) { + VK = RE->getKind(); + return RE->evaluateAsConstant(Imm); + } + if (auto CE = dyn_cast(Expr)) { + VK = RISCVMCExpr::VK_RISCV_None; + Imm = CE->getValue(); + return true; + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/generateImmOutOfRangeError.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/generateImmOutOfRangeError.cpp new file mode 100644 index 0000000000000000000000000000000000000000..38a0c63d84cc29155e89b8f20de13c896c70af91 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/generateImmOutOfRangeError.cpp @@ -0,0 +1,4 @@ +bool RISCVAsmParser::generateImmOutOfRangeError(OperandVector &Operands, uint64_t ErrorInfo, int64_t Lower, int64_t Upper, Twine Msg = "immediate must be an integer in the range") { + SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc(); + return Error(ErrorLoc, Msg + " [" + Twine(Lower) + ", " + Twine(Upper) + "]"); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/getEndLoc.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/getEndLoc.cpp new file mode 100644 index 0000000000000000000000000000000000000000..62829900d768fc89d50171419f738e8ec8124b58 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/getEndLoc.cpp @@ -0,0 +1,3 @@ +SMLoc getEndLoc() const override { + return EndLoc; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/getFeatureBits.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/getFeatureBits.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f8b7d6acceee057eaf23f6023ac5aa0493a08037 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/getFeatureBits.cpp @@ -0,0 +1,3 @@ +bool getFeatureBits(uint64_t Feature) { + return getFeatureBits()[Feature]; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/getImm.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/getImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..680aa6e8b7c97665bca7b25e7ba715d083360048 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/getImm.cpp @@ -0,0 +1,4 @@ +const MCExpr *getImm() const { + assert(Kind == KindTy::Immediate && "Invalid type access!"); + return Imm.Val; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/getLoc.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/getLoc.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ee06922bf6091cbb8ed19c3dcc5b42aa0335fbc5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/getLoc.cpp @@ -0,0 +1,3 @@ +SMLoc getLoc() const { + return getParser().getTok().getLoc(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/getReg.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/getReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b727268741262d50d0b7be12f8f224ae221d70d5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/getReg.cpp @@ -0,0 +1,4 @@ +unsigned getReg() const override { + assert(Kind == KindTy::Register && "Invalid type access!"); + return Reg.RegNum.id(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/getRoundingMode.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/getRoundingMode.cpp new file mode 100644 index 0000000000000000000000000000000000000000..59bafeff69c9ddbdeac847d8c5295be2781a6739 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/getRoundingMode.cpp @@ -0,0 +1,6 @@ +RISCVFPRndMode::RoundingMode getRoundingMode() const { + auto SE = cast(getImm()); + RISCVFPRndMode::RoundingMode FRM = RISCVFPRndMode::stringToRoundingMode(SE->getSymbol().getName()); + assert(FRM != RISCVFPRndMode::Invalid && "Invalid rounding mode"); + return FRM; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/getStartLoc.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/getStartLoc.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1468c5ab73e31cdbf7622d7fb4cc05414acef937 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/getStartLoc.cpp @@ -0,0 +1,3 @@ +SMLoc getStartLoc() const override { + return StartLoc; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/getSysReg.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/getSysReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c409acf907d63507ebf66c33bb6055965fddc7a7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/getSysReg.cpp @@ -0,0 +1,4 @@ +StringRef getSysReg() const { + assert(Kind == KindTy::SystemRegister && "Invalid type access!"); + return StringRef(SysReg.Data, SysReg.Length); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/getTargetStreamer.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/getTargetStreamer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e3c9c2ce61d650ef0464f9b4aa2539d390a2e11e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/getTargetStreamer.cpp @@ -0,0 +1,4 @@ +RISCVTargetStreamer &getTargetStreamer() { + MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer(); + return static_cast(TS); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/getToken.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/getToken.cpp new file mode 100644 index 0000000000000000000000000000000000000000..445834686b5ec1bb686bda4abcc004a4ec9ee82a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/getToken.cpp @@ -0,0 +1,4 @@ +StringRef getToken() const { + assert(Kind == KindTy::Token && "Invalid type access!"); + return Tok; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/getVType.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/getVType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..af123b58f738de16129e3a5fbb1a323ecf40eb1f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/getVType.cpp @@ -0,0 +1,4 @@ +unsigned getVType() const { + assert(Kind == KindTy::VType && "Invalid type access!"); + return VType.Val; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isBareSimmNLsb0.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isBareSimmNLsb0.cpp new file mode 100644 index 0000000000000000000000000000000000000000..dfd9e592f1bb7c039a98e85fd4c7a525b677fe69 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isBareSimmNLsb0.cpp @@ -0,0 +1,16 @@ +template bool isBareSimmNLsb0() const { + if (!isImm()) { + return false; + } + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + int64_t Imm; + bool IsValid; + bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); + if (IsConstantImm) { + IsValid = isShiftedInt(Imm); + } + if (!IsConstantImm) { + IsValid = RISCVAsmParser::classifySymbolRef(getImm(), VK); + } + return IsValid && VK == RISCVMCExpr::VK_RISCV_None; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isBareSymbol.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isBareSymbol.cpp new file mode 100644 index 0000000000000000000000000000000000000000..48a01b62fd0d0730ca3fbc3730793c50e55ab55a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isBareSymbol.cpp @@ -0,0 +1,14 @@ +bool isBareSymbol() const { + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + if (!isImm()) { + return false; + } + if (evaluateConstantImm(getImm(), Imm, VK)) { + return false; + } + if (!evaluateConstantImm(getImm(), Imm, VK)) { + return RISCVAsmParser::classifySymbolRef(getImm(), VK) && VK == RISCVMCExpr::VK_RISCV_None; + } + return RISCVAsmParser::classifySymbolRef(getImm(), VK) && VK == RISCVMCExpr::VK_RISCV_None; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isCLUIImm.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isCLUIImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f89c302eb8bc0bcfca47f2f9845303081503982d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isCLUIImm.cpp @@ -0,0 +1,11 @@ +bool isCLUIImm() const { + if (!isImm()) { + return false; + } + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + if (evaluateConstantImm(getImm(), Imm, VK)) { + return (Imm != 0) && (isUInt<5>(Imm) || (Imm >= 0xfffe0 && Imm <= 0xfffff)) && VK == RISCVMCExpr::VK_RISCV_None; + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isCSRSystemRegister.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isCSRSystemRegister.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ffb7bbbe9a914a516b01cc030bf81758a80e3270 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isCSRSystemRegister.cpp @@ -0,0 +1,3 @@ +bool isCSRSystemRegister() const { + return Kind == KindTy::SystemRegister; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isCallSymbol.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isCallSymbol.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d6142f6614dfe57e8c93e793847ae07ddf837848 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isCallSymbol.cpp @@ -0,0 +1,11 @@ +bool isCallSymbol() const { + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + if (!isImm()) { + return false; + } + if (evaluateConstantImm(getImm(), Imm, VK)) { + return false; + } + return RISCVAsmParser::classifySymbolRef(getImm(), VK) && (VK == RISCVMCExpr::VK_RISCV_CALL || VK == RISCVMCExpr::VK_RISCV_CALL_PLT); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isFRMArg.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isFRMArg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..98df83b42fc3323559573c60f0e7a30405f28bdb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isFRMArg.cpp @@ -0,0 +1,12 @@ +bool isFRMArg() const { + if (!isImm()) { + return false; + } + const MCExpr *Val = getImm(); + auto *SVal = dyn_cast(Val); + if (!SVal || SVal->getKind() != MCSymbolRefExpr::VK_None) { + return false; + } + StringRef Str = SVal->getSymbol().getName(); + return RISCVFPRndMode::stringToRoundingMode(Str) != RISCVFPRndMode::Invalid; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isFenceArg.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isFenceArg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..41d6f3f46374b1b9a6e6634a0de10b1bba1ef5ac --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isFenceArg.cpp @@ -0,0 +1,22 @@ +bool isFenceArg() const { + if (!isImm()) { + return false; + } + const MCExpr *Val = getImm(); + auto *SVal = dyn_cast(Val); + if (!SVal || SVal->getKind() != MCSymbolRefExpr::VK_None) { + return false; + } + StringRef Str = SVal->getSymbol().getName(); + char Prev = '\0'; + for (char c : Str) { + if (c != 'i' && c != 'o' && c != 'r' && c != 'w') { + return false; + } + if (c <= Prev) { + return false; + } + Prev = c; + } + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isGPR.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isGPR.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e2990020b5ef61ab36d27572763e8f15efb9772d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isGPR.cpp @@ -0,0 +1,3 @@ +bool isGPR() const { + return Kind == KindTy::Register && RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg.RegNum); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isImm.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..400db8c5883144be4963e33031283ae54db7ddf7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isImm.cpp @@ -0,0 +1,3 @@ +bool isImm() const override { + return Kind == KindTy::Immediate; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isImmXLenLI.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isImmXLenLI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b460d989d40ad769b6179758abfe2864344e640e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isImmXLenLI.cpp @@ -0,0 +1,11 @@ +bool isImmXLenLI() const { + if (!isImm()) { + return false; + } + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + if (evaluateConstantImm(getImm(), Imm, VK)) { + return VK == RISCVMCExpr::VK_RISCV_LO || VK == RISCVMCExpr::VK_RISCV_PCREL_LO || (VK == RISCVMCExpr::VK_RISCV_None && (isRV64() || (isInt<32>(Imm) || isUInt<32>(Imm)))); + } + return IsValid && VK == zmtarzmMCExpr :: VK_RISCV_LO || VK == zmtarzmMCExpr :: VK_RISCV_PCREL_LO ; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isMem.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isMem.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c43c1fbf793d7bd6d2e893e67962bd3cccf94715 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isMem.cpp @@ -0,0 +1,3 @@ +bool isMem() const override { + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isPseudoJumpSymbol.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isPseudoJumpSymbol.cpp new file mode 100644 index 0000000000000000000000000000000000000000..eec91dbdac1b9ab829dccf99b39973eded1da5b0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isPseudoJumpSymbol.cpp @@ -0,0 +1,11 @@ +bool isPseudoJumpSymbol() const { + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + if (!isImm()) { + return false; + } + if (evaluateConstantImm(getImm(), Imm, VK)) { + return false; + } + return RISCVAsmParser::classifySymbolRef(getImm(), VK) && VK == RISCVMCExpr::VK_RISCV_CALL; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isRV32E.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isRV32E.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c21e42e5f798bcb0e6b8f92f3a3cc1dd96f87b44 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isRV32E.cpp @@ -0,0 +1,3 @@ +bool isRV32E() const { + return getSTI().hasFeature(RISCV::FeatureRV32E); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isRV64-2.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isRV64-2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..383cfa600df6dac196f2c01b85967a5b0fee19c4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isRV64-2.cpp @@ -0,0 +1,3 @@ +bool isRV64() const { + return IsRV64; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isRV64.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isRV64.cpp new file mode 100644 index 0000000000000000000000000000000000000000..eec7fe92227f97b819ea0ba36ff7b64f641acbce --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isRV64.cpp @@ -0,0 +1,3 @@ +bool isRV64() const { + return getSTI().hasFeature(RISCV::Feature64Bit); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isReg.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fcb79a981f0b63d5b3d34a12ff7dc35589d32480 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isReg.cpp @@ -0,0 +1,3 @@ +bool isReg() const override { + return Kind == KindTy::Register; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isSImm10Lsb0000NonZero.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isSImm10Lsb0000NonZero.cpp new file mode 100644 index 0000000000000000000000000000000000000000..24d6dc2d00014b75b1869a58e1b07898a4404222 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isSImm10Lsb0000NonZero.cpp @@ -0,0 +1,11 @@ +bool isSImm10Lsb0000NonZero() const { + if (!isImm()) { + return false; + } + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + if (evaluateConstantImm(getImm(), Imm, VK)) { + return (Imm != 0) && isShiftedInt<6, 4>(Imm) && VK == RISCVMCExpr::VK_RISCV_None; + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isSImm12.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isSImm12.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2dcd623be87da6b40f0c329d74836d9aca17d455 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isSImm12.cpp @@ -0,0 +1,16 @@ +bool isSImm12() const { + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + int64_t Imm; + bool IsValid; + if (!isImm()) { + return false; + } + bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); + if (!IsConstantImm) { + IsValid = RISCVAsmParser::classifySymbolRef(getImm(), VK); + } + else { + IsValid = isInt<12>(Imm); + } + return IsValid && ((IsConstantImm && VK == RISCVMCExpr::VK_RISCV_None) || VK == RISCVMCExpr::VK_RISCV_LO || VK == RISCVMCExpr::VK_RISCV_PCREL_LO || VK == RISCVMCExpr::VK_RISCV_TPREL_LO); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isSImm12Lsb0.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isSImm12Lsb0.cpp new file mode 100644 index 0000000000000000000000000000000000000000..63073bc64c003ca0e83e707b57b7a4ea9c9ce158 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isSImm12Lsb0.cpp @@ -0,0 +1,14 @@ +bool isSImm12Lsb0() const { + if (!isImm()) { + return false; + } + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + if (evaluateConstantImm(getImm(), Imm, VK)) { + return isShiftedInt<11, 1>(Imm) && VK == RISCVMCExpr::VK_RISCV_None; + } + if (!evaluateConstantImm(getImm(), Imm, VK)) { + return RISCVAsmParser::classifySymbolRef(getImm(), VK) && VK == RISCVMCExpr::VK_RISCV_None; + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isSImm13Lsb0.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isSImm13Lsb0.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7f6c636265bd63d8a777132c2a0eb78dbb54be86 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isSImm13Lsb0.cpp @@ -0,0 +1,14 @@ +bool isSImm13Lsb0() const { + if (!isImm()) { + return false; + } + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + if (evaluateConstantImm(getImm(), Imm, VK)) { + return isShiftedInt<12, 1>(Imm) && VK == RISCVMCExpr::VK_RISCV_None; + } + if (!evaluateConstantImm(getImm(), Imm, VK)) { + return RISCVAsmParser::classifySymbolRef(getImm(), VK) && VK == RISCVMCExpr::VK_RISCV_None; + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isSImm21Lsb0JAL.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isSImm21Lsb0JAL.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b33656f8aabf36763566f623cf1f73adabe6177f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isSImm21Lsb0JAL.cpp @@ -0,0 +1,14 @@ +bool isSImm21Lsb0JAL() const { + if (!isImm()) { + return false; + } + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + if (evaluateConstantImm(getImm(), Imm, VK)) { + return isShiftedInt<20, 1>(Imm) && VK == RISCVMCExpr::VK_RISCV_None; + } + if (!evaluateConstantImm(getImm(), Imm, VK)) { + return RISCVAsmParser::classifySymbolRef(getImm(), VK) && VK == RISCVMCExpr::VK_RISCV_None; + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isSImm5.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isSImm5.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1b64ab3a9e82f435809b69ee895c34d33b707169 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isSImm5.cpp @@ -0,0 +1,11 @@ +bool isSImm5() const { + if (!isImm()) { + return false; + } + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + if (evaluateConstantImm(getImm(), Imm, VK)) { + return isInt<5>(Imm) && VK == RISCVMCExpr::VK_RISCV_None; + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isSImm5Plus1.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isSImm5Plus1.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fe561ca354d6609427bfe55244528003bf886fd7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isSImm5Plus1.cpp @@ -0,0 +1,11 @@ +bool isSImm5Plus1() const { + if (!isImm()) { + return false; + } + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + if (evaluateConstantImm(getImm(), Imm, VK)) { + return isInt<5>(Imm - 1) && VK == RISCVMCExpr::VK_RISCV_None; + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isSImm6.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isSImm6.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5b111421d4683f6af55ac579d99981703d94ad9e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isSImm6.cpp @@ -0,0 +1,11 @@ +bool isSImm6() const { + if (!isImm()) { + return false; + } + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + if (evaluateConstantImm(getImm(), Imm, VK)) { + return isInt<6>(Imm) && VK == RISCVMCExpr::VK_RISCV_None; + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isSImm6NonZero.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isSImm6NonZero.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b717a48ce5bbedd11d8b6a832de0ef2f398f66d8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isSImm6NonZero.cpp @@ -0,0 +1,11 @@ +bool isSImm6NonZero() const { + if (!isImm()) { + return false; + } + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + if (evaluateConstantImm(getImm(), Imm, VK)) { + return isInt<6>(Imm) && (Imm != 0) && VK == RISCVMCExpr::VK_RISCV_None; + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isSImm9Lsb0.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isSImm9Lsb0.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0ad3cbc4906910b459fb690b753c04ad71f3c7c8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isSImm9Lsb0.cpp @@ -0,0 +1,14 @@ +bool isSImm9Lsb0() const { + if (!isImm()) { + return false; + } + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + if (evaluateConstantImm(getImm(), Imm, VK)) { + return isShiftedInt<8, 1>(Imm) && VK == RISCVMCExpr::VK_RISCV_None; + } + if (!evaluateConstantImm(getImm(), Imm, VK)) { + return RISCVAsmParser::classifySymbolRef(getImm(), VK) && VK == RISCVMCExpr::VK_RISCV_None; + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isSystemRegister.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isSystemRegister.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0f392bfff3b4e8e84b2ff2a1435e84f8d71aa647 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isSystemRegister.cpp @@ -0,0 +1,3 @@ +bool isSystemRegister() const { + return Kind == KindTy::SystemRegister; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isTPRelAddSymbol.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isTPRelAddSymbol.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bbd00f01251645ec33d1af74a00e138f137a715c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isTPRelAddSymbol.cpp @@ -0,0 +1,8 @@ +bool isTPRelAddSymbol() const { + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + if (!isImm() || evaluateConstantImm(getImm(), Imm, VK)) { + return false; + } + return RISCVAsmParser::classifySymbolRef(getImm(), VK) && VK == RISCVMCExpr::VK_RISCV_TPREL_ADD; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isToken.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isToken.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a1dfb1dd6786afb1f04ef6c6a933834f7bf532f1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isToken.cpp @@ -0,0 +1,3 @@ +bool isToken() const override { + return Kind == KindTy::Token; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isUImm10Lsb00NonZero.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isUImm10Lsb00NonZero.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8e919d0e2c50071258ae1f27c9354a25e023d0c5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isUImm10Lsb00NonZero.cpp @@ -0,0 +1,11 @@ +bool isUImm10Lsb00NonZero() const { + if (!isImm()) { + return false; + } + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + if (evaluateConstantImm(getImm(), Imm, VK)) { + return isShiftedUInt<8, 2>(Imm) && (Imm != 0) && VK == RISCVMCExpr::VK_RISCV_None; + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isUImm20AUIPC.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isUImm20AUIPC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..89b7a149611af05f335eaf59e3f8cd3648411d75 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isUImm20AUIPC.cpp @@ -0,0 +1,16 @@ +bool isUImm20AUIPC() const { + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + int64_t Imm; + bool IsValid; + if (!isImm()) { + return false; + } + bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); + if (!IsConstantImm) { + IsValid = RISCVAsmParser::classifySymbolRef(getImm(), VK); + return IsValid && (VK == RISCVMCExpr::VK_RISCV_PCREL_HI || VK == RISCVMCExpr::VK_RISCV_GOT_HI || VK == RISCVMCExpr::VK_RISCV_TLS_GOT_HI || VK == RISCVMCExpr::VK_RISCV_TLS_GD_HI); + } + else { + return isUInt<20>(Imm) && (VK == RISCVMCExpr::VK_RISCV_None || VK == RISCVMCExpr::VK_RISCV_PCREL_HI || VK == RISCVMCExpr::VK_RISCV_GOT_HI || VK == RISCVMCExpr::VK_RISCV_TLS_GOT_HI || VK == RISCVMCExpr::VK_RISCV_TLS_GD_HI); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isUImm20LUI.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isUImm20LUI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..923f243b5e92bda4596b995757b38cfc685d1ec9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isUImm20LUI.cpp @@ -0,0 +1,16 @@ +bool isUImm20LUI() const { + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + int64_t Imm; + bool IsValid; + if (!isImm()) { + return false; + } + bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); + if (!IsConstantImm) { + IsValid = RISCVAsmParser::classifySymbolRef(getImm(), VK); + return IsValid && (VK == RISCVMCExpr::VK_RISCV_HI || VK == RISCVMCExpr::VK_RISCV_TPREL_HI); + } + else { + return isUInt<20>(Imm) && (VK == RISCVMCExpr::VK_RISCV_None || VK == RISCVMCExpr::VK_RISCV_HI || VK == RISCVMCExpr::VK_RISCV_TPREL_HI); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isUImm5.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isUImm5.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b18cb034281c59c4c483e7321ee15b4dcafff652 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isUImm5.cpp @@ -0,0 +1,9 @@ +bool isUImm5() const { + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + if (!isImm()) { + return false; + } + bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); + return IsConstantImm && isUInt<5>(Imm) && VK == RISCVMCExpr::VK_RISCV_None; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isUImm7Lsb00.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isUImm7Lsb00.cpp new file mode 100644 index 0000000000000000000000000000000000000000..24c29da9a8cbed9c78d112302095c0013b32a31b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isUImm7Lsb00.cpp @@ -0,0 +1,9 @@ +bool isUImm7Lsb00() const { + if (!isImm()) { + return false; + } + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); + return IsConstantImm && isShiftedUInt<5, 2>(Imm) && VK == RISCVMCExpr::VK_RISCV_None; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isUImm8Lsb00.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isUImm8Lsb00.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3ccc5fd5ffb3c7162ff7165e1f056db0ff5f0f83 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isUImm8Lsb00.cpp @@ -0,0 +1,9 @@ +bool isUImm8Lsb00() const { + if (!isImm()) { + return false; + } + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); + return IsConstantImm && isShiftedUInt<6, 2>(Imm) && VK == RISCVMCExpr::VK_RISCV_None; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isUImm8Lsb000.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isUImm8Lsb000.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7eff26abdf3912a7976c2c7a67e9a024b47ea6bb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isUImm8Lsb000.cpp @@ -0,0 +1,9 @@ +bool isUImm8Lsb000() const { + if (!isImm()) { + return false; + } + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); + return IsConstantImm && isShiftedUInt<5, 3>(Imm) && VK == RISCVMCExpr::VK_RISCV_None; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isUImm9Lsb000.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isUImm9Lsb000.cpp new file mode 100644 index 0000000000000000000000000000000000000000..06310c952d4c996d47144ed5e65f84d235458aaf --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isUImm9Lsb000.cpp @@ -0,0 +1,9 @@ +bool isUImm9Lsb000() const { + if (!isImm()) { + return false; + } + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); + return IsConstantImm && isShiftedUInt<6, 3>(Imm) && VK == RISCVMCExpr::VK_RISCV_None; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isUImmLog2XLen.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isUImmLog2XLen.cpp new file mode 100644 index 0000000000000000000000000000000000000000..76c5c7d94ae735807c0e08a8ba26d4a441ba3b1d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isUImmLog2XLen.cpp @@ -0,0 +1,11 @@ +bool isUImmLog2XLen() const { + if (!isImm()) { + return false; + } + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + if (evaluateConstantImm(getImm(), Imm, VK)) { + return VK == RISCVMCExpr::VK_RISCV_None && ((isRV64() && isUInt<6>(Imm)) || isUInt<5>(Imm)); + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isUImmLog2XLenHalf.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isUImmLog2XLenHalf.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e962acbdddc793ea296bb646aa7e1829f29c1078 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isUImmLog2XLenHalf.cpp @@ -0,0 +1,11 @@ +bool isUImmLog2XLenHalf() const { + if (!isImm()) { + return false; + } + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + if (evaluateConstantImm(getImm(), Imm, VK)) { + return VK == RISCVMCExpr::VK_RISCV_None; + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isUImmLog2XLenNonZero.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isUImmLog2XLenNonZero.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4a00a205afacb1a8befa223480ef0e27092c6336 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isUImmLog2XLenNonZero.cpp @@ -0,0 +1,11 @@ +bool isUImmLog2XLenNonZero() const { + if (!isImm()) { + return false; + } + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + if (evaluateConstantImm(getImm(), Imm, VK)) { + return VK == RISCVMCExpr::VK_RISCV_None; + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isV0Reg.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isV0Reg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3925060552980f02dcfb4ddf2b3390f7ee29ab33 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isV0Reg.cpp @@ -0,0 +1,3 @@ +bool isV0Reg() const { + return Kind == KindTy::Register && Reg.RegNum == RISCV::V0; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isVType.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isVType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..19e3cbf2a0f73d6ef2c860853164a4697d40546f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isVType.cpp @@ -0,0 +1,3 @@ +bool isVType() const { + return Kind == KindTy::VType; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isVTypeI.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isVTypeI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..19e3cbf2a0f73d6ef2c860853164a4697d40546f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/isVTypeI.cpp @@ -0,0 +1,3 @@ +bool isVType() const { + return Kind == KindTy::VType; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/matchRegisterNameHelper.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/matchRegisterNameHelper.cpp new file mode 100644 index 0000000000000000000000000000000000000000..27ae49e62bcf881645cbe1722de6c7742918c0d5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/matchRegisterNameHelper.cpp @@ -0,0 +1,14 @@ +static bool matchRegisterNameHelper(bool IsRV32E, MCRegister &RegNo, StringRef Name) { + RegNo = MatchRegisterName(Name); + assert(!(RegNo >= RISCV::F0_H && RegNo <= RISCV::F31_H)); + assert(!(RegNo >= RISCV::F0_F && RegNo <= RISCV::F31_F)); + static_assert(RISCV::F0_D < RISCV::F0_H, "FPR matching must be updated"); + static_assert(RISCV::F0_D < RISCV::F0_F, "FPR matching must be updated"); + if (RegNo == RISCV::NoRegister) { + RegNo = MatchRegisterAltName(Name); + } + if (IsRV32E && RegNo >= RISCV::X16 && RegNo <= RISCV::X31) { + RegNo = RISCV::NoRegister; + } + return RegNo == RISCV::NoRegister; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/parseAtomicMemOp.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/parseAtomicMemOp.cpp new file mode 100644 index 0000000000000000000000000000000000000000..73fa5f840b2095a3ff4d84b0a43741fcb127a04b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/parseAtomicMemOp.cpp @@ -0,0 +1,31 @@ +OperandMatchResultTy RISCVAsmParser::parseAtomicMemOp(OperandVector &Operands) { + std::unique_ptr OptionalImmOp; + if (getLexer().isNot(AsmToken::LParen)) { + int64_t ImmVal; + SMLoc ImmStart = getLoc(); + if (getParser().parseIntToken(ImmVal, "expected '(' or optional integer offset")) { + return MatchOperand_ParseFail; + } + SMLoc ImmEnd = getLoc(); + OptionalImmOp = RISCVOperand::createImm(MCConstantExpr::create(ImmVal, getContext()), ImmStart, ImmEnd, isRV64()); + } + if (getLexer().isNot(AsmToken::LParen)) { + Error(getLoc(), OptionalImmOp ? "expected '(' after optional integer offset" : "expected '(' or optional integer offset"); + return MatchOperand_ParseFail; + } + getParser().Lex(); + if (parseRegister(Operands) != MatchOperand_Success) { + Error(getLoc(), "expected register"); + return MatchOperand_ParseFail; + } + if (getLexer().isNot(AsmToken::RParen)) { + Error(getLoc(), "expected ')'"); + return MatchOperand_ParseFail; + } + getParser().Lex(); + if (OptionalImmOp && !OptionalImmOp->isImmZero()) { + Error(OptionalImmOp->getStartLoc(), "optional integer offset must be 0", SMRange(OptionalImmOp->getStartLoc(), OptionalImmOp->getEndLoc())); + return MatchOperand_ParseFail; + } + return MatchOperand_Success; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/parseBareSymbol.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/parseBareSymbol.cpp new file mode 100644 index 0000000000000000000000000000000000000000..57f7bc977450d3c2da02c005d74f59303d313ad1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/parseBareSymbol.cpp @@ -0,0 +1,54 @@ +OperandMatchResultTy RISCVAsmParser::parseBareSymbol(OperandVector &Operands) { + SMLoc S = getLoc(); + SMLoc E = SMLoc::getFromPointer(S.getPointer() - 1); + const MCExpr *Res; + if (getLexer().getKind() != AsmToken::Identifier) { + return MatchOperand_NoMatch; + } + StringRef Identifier; + AsmToken Tok = getLexer().getTok(); + if (getParser().parseIdentifier(Identifier)) { + return MatchOperand_ParseFail; + } + if (Identifier.consume_back("@plt")) { + Error(getLoc(), "'@plt' operand not valid for instruction"); + return MatchOperand_ParseFail; + } + MCSymbol *Sym = getContext().getOrCreateSymbol(Identifier); + if (Sym->isVariable()) { + const MCExpr *V = Sym->getVariableValue(false); + if (!isa(V)) { + getLexer().UnLex(Tok); + return MatchOperand_NoMatch; + } + Res = V; + } + if (!Sym->isVariable()) { + Res = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext()); + } + MCBinaryExpr::Opcode Opcode; + if (getLexer().getKind() == AsmToken::Plus) { + Opcode = MCBinaryExpr::Add; + getLexer().Lex(); + const MCExpr *Expr; + if (getParser().parseExpression(Expr)) { + return MatchOperand_ParseFail; + } + Res = MCBinaryExpr::create(Opcode, Res, Expr, getContext()); + Operands.push_back(RISCVOperand::createImm(Res, S, E, isRV64())); + return MatchOperand_Success; + } + if (getLexer().getKind() == AsmToken::Minus) { + Opcode = MCBinaryExpr::Sub; + getLexer().Lex(); + const MCExpr *Expr; + if (getParser().parseExpression(Expr)) { + return MatchOperand_ParseFail; + } + Res = MCBinaryExpr::create(Opcode, Res, Expr, getContext()); + Operands.push_back(RISCVOperand::createImm(Res, S, E, isRV64())); + return MatchOperand_Success; + } + Operands.push_back(RISCVOperand::createImm(Res, S, E, isRV64())); + return MatchOperand_Success; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/parseCSRSyestemRegister.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/parseCSRSyestemRegister.cpp new file mode 100644 index 0000000000000000000000000000000000000000..96d54657bc5e40fad131f08a4c6c265d5da2663c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/parseCSRSyestemRegister.cpp @@ -0,0 +1,58 @@ +OperandMatchResultTy RISCVAsmParser::parseCSRSystemRegister(OperandVector &Operands) { + SMLoc S = getLoc(); + const MCExpr *Res; + switch (getLexer().getKind()) { + default: + return MatchOperand_NoMatch; + case AsmToken::LParen: + case AsmToken::Minus: + case AsmToken::Plus: + case AsmToken::Exclaim: + case AsmToken::Tilde: + case AsmToken::Integer: + case AsmToken::String: { + if (getParser().parseExpression(Res)) { + return MatchOperand_ParseFail; + } + auto *CE = dyn_cast(Res); + if (CE) { + int64_t Imm = CE->getValue(); + if (isUInt<12>(Imm)) { + auto SysReg = RISCVSysReg::lookupSysRegByEncoding(Imm); + Operands.push_back(RISCVOperand::createSysReg(SysReg ? SysReg->Name : "", S, Imm, isRV64())); + return MatchOperand_Success; + } + } + Twine Msg = "immediate must be an integer in the range"; + Error(S, Msg + " [" + Twine(0) + ", " + Twine((1 << 12) - 1) + "]"); + return MatchOperand_ParseFail; + } + case AsmToken::Identifier: { + StringRef Identifier; + if (getParser().parseIdentifier(Identifier)) { + return MatchOperand_ParseFail; + } + auto SysReg = RISCVSysReg::lookupSysRegByName(Identifier); + if (!SysReg) { + SysReg = RISCVSysReg::lookupSysRegByAltName(Identifier); + } + if (SysReg) { + if (!SysReg->haveRequiredFeatures(getSTI().getFeatureBits())) { + Error(S, "system register use requires an option to be enabled"); + return MatchOperand_ParseFail; + } + Operands.push_back(RISCVOperand::createSysReg(Identifier, S, SysReg->Encoding, isRV64())); + return MatchOperand_Success; + } + Twine Msg = "operand must be a valid system register name or an integer in the range"; + Error(S, Msg + " [" + Twine(0) + ", " + Twine((1 << 12) - 1) + "]"); + return MatchOperand_ParseFail; + } + case AsmToken::Percent: { + Twine Msg = "immediate must be an integer in the range"; + Error(S, Msg + " [" + Twine(0) + ", " + Twine((1 << 12) - 1) + "]"); + return MatchOperand_ParseFail; + } + } + return MatchOperand_NoMatch; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/parseCallSymbol.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/parseCallSymbol.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fe6a4808b76d4d27e94f8d2fb928ea9efcec5566 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/parseCallSymbol.cpp @@ -0,0 +1,24 @@ +OperandMatchResultTy RISCVAsmParser::parseCallSymbol(OperandVector &Operands) { + SMLoc S = getLoc(); + SMLoc E = SMLoc::getFromPointer(S.getPointer() - 1); + const MCExpr *Res; + if (getLexer().getKind() != AsmToken::Identifier) { + return MatchOperand_NoMatch; + } + if (getLexer().peekTok().getKind() != AsmToken::EndOfStatement) { + return MatchOperand_NoMatch; + } + StringRef Identifier; + if (getParser().parseIdentifier(Identifier)) { + return MatchOperand_ParseFail; + } + RISCVMCExpr::VariantKind Kind = RISCVMCExpr::VK_RISCV_CALL; + if (Identifier.consume_back("@plt")) { + Kind = RISCVMCExpr::VK_RISCV_CALL_PLT; + } + MCSymbol *Sym = getContext().getOrCreateSymbol(Identifier); + Res = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext()); + Res = RISCVMCExpr::create(Res, Kind, getContext()); + Operands.push_back(RISCVOperand::createImm(Res, S, E, isRV64())); + return MatchOperand_Success; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/parseImmediate.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/parseImmediate.cpp new file mode 100644 index 0000000000000000000000000000000000000000..feac87761130aaf45a8121dea0eae6f59102e1d6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/parseImmediate.cpp @@ -0,0 +1,25 @@ +OperandMatchResultTy RISCVAsmParser::parseImmediate(OperandVector &Operands) { + SMLoc S = getLoc(); + SMLoc E = SMLoc::getFromPointer(S.getPointer() - 1); + const MCExpr *Res; + switch (getLexer().getKind()) { + default: + return MatchOperand_NoMatch; + case AsmToken::LParen: + case AsmToken::Dot: + case AsmToken::Minus: + case AsmToken::Plus: + case AsmToken::Exclaim: + case AsmToken::Tilde: + case AsmToken::Integer: + case AsmToken::String: + case AsmToken::Identifier: + if (getParser().parseExpression(Res)) + return MatchOperand_ParseFail; + break; + case AsmToken::Percent: + return parseOperandWithModifier(Operands); + } + Operands.push_back(RISCVOperand::createImm(Res, S, E, isRV64())); + return MatchOperand_Success; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/parseJALOffset.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/parseJALOffset.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4347a538d20ac2d19cd66ac66b94dea2d4ee61a8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/parseJALOffset.cpp @@ -0,0 +1,6 @@ +OperandMatchResultTy RISCVAsmParser::parseJALOffset(OperandVector &Operands) { + if (getLexer().is(AsmToken::Identifier) && getLexer().peekTok().is(AsmToken::Comma)) { + return MatchOperand_NoMatch; + } + return parseImmediate(Operands); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/parseMaskReg.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/parseMaskReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..901f42d5b8e97a73b21f91b7bc31ab4375d074a0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/parseMaskReg.cpp @@ -0,0 +1,23 @@ +OperandMatchResultTy RISCVAsmParser::parseMaskReg(OperandVector &Operands) { + if (getLexer().getKind() != AsmToken::Identifier) { + return MatchOperand_NoMatch; + } + StringRef Name = getLexer().getTok().getIdentifier(); + if (!Name.consume_back(".t")) { + Error(getLoc(), "expected '.t' suffix"); + return MatchOperand_ParseFail; + } + MCRegister RegNo; + matchRegisterNameHelper(isRV32E(), RegNo, Name); + if (RegNo == RISCV::NoRegister) { + return MatchOperand_NoMatch; + } + if (RegNo != RISCV::V0) { + return MatchOperand_NoMatch; + } + SMLoc S = getLoc(); + SMLoc E = SMLoc::getFromPointer(S.getPointer() - 1); + getLexer().Lex(); + Operands.push_back(RISCVOperand::createReg(RegNo, S, E, isRV64())); + return MatchOperand_Success; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/parseMemOpBaseReg.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/parseMemOpBaseReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a1511d06f4bed7e5bdbe162d055ebd9cb72aadfd --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/parseMemOpBaseReg.cpp @@ -0,0 +1,19 @@ +OperandMatchResultTy RISCVAsmParser::parseMemOpBaseReg(OperandVector &Operands) { + if (getLexer().isNot(AsmToken::LParen)) { + Error(getLoc(), "expected '('"); + return MatchOperand_ParseFail; + } + getParser().Lex(); + Operands.push_back(RISCVOperand::createToken("(", getLoc(), isRV64())); + if (parseRegister(Operands) != MatchOperand_Success) { + Error(getLoc(), "expected register"); + return MatchOperand_ParseFail; + } + if (getLexer().isNot(AsmToken::RParen)) { + Error(getLoc(), "expected ')'"); + return MatchOperand_ParseFail; + } + getParser().Lex(); + Operands.push_back(RISCVOperand::createToken(")", getLoc(), isRV64())); + return MatchOperand_Success; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/parseOperand.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/parseOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6b95d698771a42bf80e9f83db2769c52a2de381c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/parseOperand.cpp @@ -0,0 +1,20 @@ +bool RISCVAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) { + OperandMatchResultTy Result = MatchOperandParserImpl(Operands, Mnemonic, true); + if (Result == MatchOperand_Success) { + return false; + } + if (Result == MatchOperand_ParseFail) { + return true; + } + if (parseRegister(Operands, true) == MatchOperand_Success) { + return false; + } + if (parseImmediate(Operands) == MatchOperand_Success) { + if (getLexer().is(AsmToken::LParen)) { + return parseMemOpBaseReg(Operands) != MatchOperand_Success; + } + return false; + } + Error(getLoc(), "unknown operand"); + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/parseOperandWithModifier.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/parseOperandWithModifier.cpp new file mode 100644 index 0000000000000000000000000000000000000000..27f42bfe733a0007030006dfbc7d50f869067eda --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/parseOperandWithModifier.cpp @@ -0,0 +1,32 @@ +OperandMatchResultTy RISCVAsmParser::parseOperandWithModifier(OperandVector &Operands) { + SMLoc S = getLoc(); + SMLoc E = SMLoc::getFromPointer(S.getPointer() - 1); + if (getLexer().getKind() != AsmToken::Percent) { + Error(getLoc(), "expected '%' for operand modifier"); + return MatchOperand_ParseFail; + } + getParser().Lex(); + if (getLexer().getKind() != AsmToken::Identifier) { + Error(getLoc(), "expected valid identifier for operand modifier"); + return MatchOperand_ParseFail; + } + StringRef Identifier = getParser().getTok().getIdentifier(); + RISCVMCExpr::VariantKind VK = RISCVMCExpr::getVariantKindForName(Identifier); + if (VK == RISCVMCExpr::VK_RISCV_Invalid) { + Error(getLoc(), "unrecognized operand modifier"); + return MatchOperand_ParseFail; + } + getParser().Lex(); + if (getLexer().getKind() != AsmToken::LParen) { + Error(getLoc(), "expected '('"); + return MatchOperand_ParseFail; + } + getParser().Lex(); + const MCExpr *SubExpr; + if (getParser().parseParenExpression(SubExpr, E)) { + return MatchOperand_ParseFail; + } + const MCExpr *ModExpr = RISCVMCExpr::create(SubExpr, VK, getContext()); + Operands.push_back(RISCVOperand::createImm(ModExpr, S, E, isRV64())); + return MatchOperand_Success; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/parsePseudoJumpSymbol.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/parsePseudoJumpSymbol.cpp new file mode 100644 index 0000000000000000000000000000000000000000..69b270de1636f260bc365037fb79e6d55d7af2f7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/parsePseudoJumpSymbol.cpp @@ -0,0 +1,15 @@ +OperandMatchResultTy RISCVAsmParser::parsePseudoJumpSymbol(OperandVector &Operands) { + SMLoc S = getLoc(); + SMLoc E = SMLoc::getFromPointer(S.getPointer() - 1); + const MCExpr *Res; + if (getParser().parseExpression(Res)) { + return MatchOperand_ParseFail; + } + if (Res->getKind() != MCExpr::ExprKind::SymbolRef || cast(Res)->getKind() == MCSymbolRefExpr::VariantKind::VK_PLT) { + Error(S, "operand must be a valid jump target"); + return MatchOperand_ParseFail; + } + Res = RISCVMCExpr::create(Res, RISCVMCExpr::VK_RISCV_CALL, getContext()); + Operands.push_back(RISCVOperand::createImm(Res, S, E, isRV64())); + return MatchOperand_Success; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/parseRegister2.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/parseRegister2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7fe5924f959488bcb9783bee83611e7623f013e8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/parseRegister2.cpp @@ -0,0 +1,43 @@ +OperandMatchResultTy RISCVAsmParser::parseRegister(OperandVector &Operands, bool AllowParens) { + SMLoc FirstS = getLoc(); + bool HadParens = false; + AsmToken LParen; + if (AllowParens && getLexer().is(AsmToken::LParen)) { + AsmToken Buf[2]; + size_t ReadCount = getLexer().peekTokens(Buf); + if (ReadCount == 2 && Buf[1].getKind() == AsmToken::RParen) { + HadParens = true; + LParen = getParser().getTok(); + getParser().Lex(); + } + } + switch (getLexer().getKind()) { + default: + if (HadParens) { + getLexer().UnLex(LParen); + } + return MatchOperand_NoMatch; + case AsmToken::Identifier: + StringRef Name = getLexer().getTok().getIdentifier(); + MCRegister RegNo; + matchRegisterNameHelper(isRV32E(), RegNo, Name); + if (RegNo == RISCV::NoRegister) { + if (HadParens) { + getLexer().UnLex(LParen); + } + return MatchOperand_NoMatch; + } + if (HadParens) { + Operands.push_back(RISCVOperand::createToken("(", FirstS, isRV64())); + } + SMLoc S = getLoc(); + SMLoc E = SMLoc::getFromPointer(S.getPointer() - 1); + getLexer().Lex(); + Operands.push_back(RISCVOperand::createReg(RegNo, S, E, isRV64())); + } + if (HadParens) { + getParser().Lex(); + Operands.push_back(RISCVOperand::createToken(")", getLoc(), isRV64())); + } + return MatchOperand_Success; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/parseVTypeI.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/parseVTypeI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e220c8a45f48d51816290c8ee89f6dfe78b71cd5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/parseVTypeI.cpp @@ -0,0 +1,85 @@ +OperandMatchResultTy RISCVAsmParser::parseVTypeI(OperandVector &Operands) { + SMLoc S = getLoc(); + if (getLexer().getKind() != AsmToken::Identifier) { + return MatchOperand_NoMatch; + } + StringRef Name = getLexer().getTok().getIdentifier(); + if (!Name.consume_front("e")) { + return MatchOperand_NoMatch; + } + unsigned Sew; + if (Name.getAsInteger(10, Sew)) { + return MatchOperand_NoMatch; + } + if (!RISCVVType::isValidSEW(Sew)) { + return MatchOperand_NoMatch; + } + getLexer().Lex(); + if (!getLexer().is(AsmToken::Comma)) { + return MatchOperand_NoMatch; + } + getLexer().Lex(); + Name = getLexer().getTok().getIdentifier(); + if (!Name.consume_front("m")) { + return MatchOperand_NoMatch; + } + bool Fractional = Name.consume_front("f"); + unsigned Lmul; + if (Name.getAsInteger(10, Lmul)) { + return MatchOperand_NoMatch; + } + if (!RISCVVType::isValidLMUL(Lmul, Fractional)) { + return MatchOperand_NoMatch; + } + getLexer().Lex(); + if (!getLexer().is(AsmToken::Comma)) { + return MatchOperand_NoMatch; + } + getLexer().Lex(); + Name = getLexer().getTok().getIdentifier(); + bool TailAgnostic; + if (Name == "ta") { + TailAgnostic = true; + } + else if (Name == "tu") { + TailAgnostic = false; + } + else { + return MatchOperand_NoMatch; + } + getLexer().Lex(); + if (!getLexer().is(AsmToken::Comma)) { + return MatchOperand_NoMatch; + } + getLexer().Lex(); + Name = getLexer().getTok().getIdentifier(); + bool MaskAgnostic; + if (Name == "ma") { + MaskAgnostic = true; + } + else if (Name == "mu") { + MaskAgnostic = false; + } + else { + return MatchOperand_NoMatch; + } + getLexer().Lex(); + if (getLexer().getKind() != AsmToken::EndOfStatement) { + return MatchOperand_NoMatch; + } + unsigned SewLog2 = Log2_32(Sew / 8); + unsigned LmulLog2 = Log2_32(Lmul); + RISCVVSEW VSEW = static_cast(SewLog2); + RISCVVLMUL VLMUL = static_cast(Fractional ? 8 - LmulLog2 : LmulLog2); + unsigned VLMULBits = static_cast(VLMUL); + unsigned VSEWBits = static_cast(VSEW); + unsigned VTypeI = (VSEWBits << 3) | (VLMULBits & 0x7); + if (TailAgnostic) { + VTypeI |= 0x40; + } + if (MaskAgnostic) { + VTypeI |= 0x80; + } + Operands.push_back(RISCVOperand::createVType(VTypeI, S, isRV64())); + return MatchOperand_Success; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/print.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/print.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9a8b9ee45de91092637a6df1c5cc22485819a36f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/print.cpp @@ -0,0 +1,27 @@ +void print(raw_ostream &OS) const override { + auto RegName = [](unsigned Reg) { + if (Reg) { + return RISCVInstPrinter::getRegisterName(Reg); + } + else { + return "noreg"; + } + }; + if (Kind == KindTy::Token) { + OS << "'" << getToken() << "'"; + } + if (Kind == KindTy::Register) { + OS << ""; + } + if (Kind == KindTy::Immediate) { + OS << *getImm(); + } + if (Kind == KindTy::SystemRegister) { + OS << "'; + } + if (Kind == KindTy::VType) { + OS << "'; + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/setFeatureBits.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/setFeatureBits.cpp new file mode 100644 index 0000000000000000000000000000000000000000..211903c48c17873e04e301dd463681dff6bb9c72 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/setFeatureBits.cpp @@ -0,0 +1,6 @@ +void setFeatureBits(uint64_t Feature, StringRef FeatureString) { + if (!(getSTI().getFeatureBits()[Feature])) { + MCSubtargetInfo &STI = copySTI(); + setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature(FeatureString))); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/tryParseRegister.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/tryParseRegister.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5a1d6873add2be39e3f257393382aec5e4ed8d3a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/tryParseRegister.cpp @@ -0,0 +1,12 @@ +OperandMatchResultTy RISCVAsmParser::tryParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) { + const AsmToken &Tok = getParser().getTok(); + StartLoc = Tok.getLoc(); + EndLoc = Tok.getEndLoc(); + RegNo = 0; + StringRef Name = getLexer().getTok().getIdentifier(); + if (matchRegisterNameHelper(isRV32E(), (MCRegister &)RegNo, Name)) { + return MatchOperand_NoMatch; + } + getParser().Lex(); + return MatchOperand_Success; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/validateTargetOperandClass.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/validateTargetOperandClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c072b9c27d13a6ecb7d25a3e02a5bd74d804d7b6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmParser/validateTargetOperandClass.cpp @@ -0,0 +1,18 @@ +unsigned RISCVAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp, unsigned Kind) { + RISCVOperand &Op = static_cast(AsmOp); + if (!Op.isReg()) { + return Match_InvalidOperand; + } + MCRegister Reg = Op.getReg(); + bool IsRegFPR64 = RISCVMCRegisterClasses[RISCV::FPR64RegClassID].contains(Reg); + bool IsRegFPR64C = RISCVMCRegisterClasses[RISCV::FPR64CRegClassID].contains(Reg); + if ((IsRegFPR64 && Kind == MCK_FPR32) || (IsRegFPR64C && Kind == MCK_FPR32C)) { + Op.Reg.RegNum = convertFPR64ToFPR32(Reg); + return Match_Success; + } + if (IsRegFPR64 && Kind == MCK_FPR16) { + Op.Reg.RegNum = convertFPR64ToFPR16(Reg); + return Match_Success; + } + return Match_InvalidOperand; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmPrinter/AsmPrinter.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmPrinter/AsmPrinter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e166353dd214035178ed8fd3747bf6c0d1d6a724 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmPrinter/AsmPrinter.cpp @@ -0,0 +1,2 @@ +explicit RISCVAsmPrinter(TargetMachine &TM, std::unique_ptr Streamer) : AsmPrinter(TM, std::move(Streamer)), STI(TM.getMCSubtargetInfo()) { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmPrinter/EmitToStreamer.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmPrinter/EmitToStreamer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1b00b8f8b42d9c2fbe308b81fe001a750e400ae4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmPrinter/EmitToStreamer.cpp @@ -0,0 +1,8 @@ +void RISCVAsmPrinter::EmitToStreamer(MCStreamer &S, const MCInst &Inst) { + MCInst CInst; + bool Res = compressInst(CInst, Inst, *STI, OutStreamer->getContext()); + if (Res) { + ++RISCVNumInstrsCompressed; + } + AsmPrinter::EmitToStreamer(*OutStreamer, Res ? CInst : Inst); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmPrinter/LLVMInitializeAsmPrinter.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmPrinter/LLVMInitializeAsmPrinter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4b6f0328c0d570906d89e27f1b6c6bd2958c6ee6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmPrinter/LLVMInitializeAsmPrinter.cpp @@ -0,0 +1,4 @@ +extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVAsmPrinter() { + RegisterAsmPrinter X(getTheRISCV32Target()); + RegisterAsmPrinter Y(getTheRISCV64Target()); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmPrinter/PrintAsmMemoryOperand.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmPrinter/PrintAsmMemoryOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..31132f2f38be4753150937d0d9e817e46726ce1e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmPrinter/PrintAsmMemoryOperand.cpp @@ -0,0 +1,11 @@ +bool RISCVAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS) { + if (!ExtraCode) { + const MachineOperand &MO = MI->getOperand(OpNo); + if (!MO.isReg()) { + return true; + } + OS << "0(" << RISCVInstPrinter::getRegisterName(MO.getReg()) << ")"; + return false; + } + return AsmPrinter::PrintAsmMemoryOperand(MI, OpNo, ExtraCode, OS); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmPrinter/PrintAsmOperand.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmPrinter/PrintAsmOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c31fdfafce0d2ff8dea052096b61a742174ece7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmPrinter/PrintAsmOperand.cpp @@ -0,0 +1,45 @@ +bool RISCVAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS) { + if (!AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, OS)) { + return false; + } + const MachineOperand &MO = MI->getOperand(OpNo); + if (ExtraCode && ExtraCode[0]) { + if (ExtraCode[1] != 0) { + return true; + } + switch (ExtraCode[0]) { + default: + return true; + case 'z': + if (MO.isImm() && MO.getImm() == 0) { + OS << RISCVInstPrinter::getRegisterName(RISCV::X0); + return false; + } + break; + case 'i': + if (!MO.isReg()) { + OS << 'i'; + } + return false; + } + } + switch (MO.getType()) { + case MachineOperand::MO_Immediate: + OS << MO.getImm(); + return false; + case MachineOperand::MO_Register: + OS << RISCVInstPrinter::getRegisterName(MO.getReg()); + return false; + case MachineOperand::MO_GlobalAddress: + PrintSymbolOperand(MO, OS); + return false; + case MachineOperand::MO_BlockAddress: { + MCSymbol *Sym = GetBlockAddressSymbol(MO.getBlockAddress()); + Sym->print(OS, MAI); + return false; + } + default: + break; + } + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmPrinter/emitAttributes.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmPrinter/emitAttributes.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c13bd2b11bf02aab0983c3ffc0c3b5ad848e0be2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmPrinter/emitAttributes.cpp @@ -0,0 +1,9 @@ +void RISCVAsmPrinter::emitAttributes() { + RISCVTargetStreamer &RTS = static_cast(*OutStreamer->getTargetStreamer()); + const Triple &TT = TM.getTargetTriple(); + StringRef CPU = TM.getTargetCPU(); + StringRef FS = TM.getTargetFeatureString(); + const RISCVTargetMachine &RTM = static_cast(TM); + const RISCVSubtarget STI(TT, CPU, CPU, FS, "", RTM); + RTS.emitTargetAttributes(STI); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmPrinter/emitEndOfAsmFile.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmPrinter/emitEndOfAsmFile.cpp new file mode 100644 index 0000000000000000000000000000000000000000..871ffa5737cbbebb3646e8d4332bd04b329067da --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmPrinter/emitEndOfAsmFile.cpp @@ -0,0 +1,6 @@ +void RISCVAsmPrinter::emitEndOfAsmFile(Module &M) { + RISCVTargetStreamer &CTS = static_cast(*OutStreamer->getTargetStreamer()); + if (TM.getTargetTriple().isOSBinFormatELF()) { + CTS.finishAttributeSection(); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmPrinter/emitInstruction.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmPrinter/emitInstruction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bdd093f184563015cb1be5ba8975ef04762fd8b6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmPrinter/emitInstruction.cpp @@ -0,0 +1,8 @@ +void RISCVAsmPrinter::emitInstruction(const MachineInstr *MI) { + if (emitPseudoExpansionLowering(*OutStreamer, MI)) { + return ; + } + MCInst TmpInst; + LowerRISCVMachineInstrToMCInst(MI, TmpInst, *this); + EmitToStreamer(*OutStreamer, TmpInst); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmPrinter/emitStartOfAsmFile.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmPrinter/emitStartOfAsmFile.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6895c501148e6daaad0ad8d522f0cbdb0fb2a9e6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmPrinter/emitStartOfAsmFile.cpp @@ -0,0 +1,5 @@ +void RISCVAsmPrinter::emitStartOfAsmFile(Module &M) { + if (TM.getTargetTriple().isOSBinFormatELF()) { + emitAttributes(); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmPrinter/getPassName.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmPrinter/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..408ede981a828294678c062ffab8cb8538586a4a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmPrinter/getPassName.cpp @@ -0,0 +1,3 @@ +StringRef getPassName() const override { + return "RISCV Assembly Printer"; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmPrinter/lowerOperand.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmPrinter/lowerOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e46620f964aa5e16a8f2d0ea650ef87a4e687718 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmPrinter/lowerOperand.cpp @@ -0,0 +1,3 @@ +bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const { + return LowerRISCVMachineOperandToMCOperand(MO, MCOp, *this); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmPrinter/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmPrinter/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..789e25a498fe0fcd1c781cb7aa07b505321457e0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Assembler/AsmPrinter/runOnMachineFunction.cpp @@ -0,0 +1,8 @@ +bool RISCVAsmPrinter::runOnMachineFunction(MachineFunction &MF) { + MCSubtargetInfo &NewSTI = OutStreamer->getContext().getSubtargetCopy(*TM.getMCSubtargetInfo()); + NewSTI.setFeatureBits(MF.getSubtarget().getFeatureBits()); + STI = &NewSTI; + SetupMachineFunction(MF); + emitFunctionBody(); + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/DecodeFPR16RegisterClass.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/DecodeFPR16RegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..92d7310f19818315af77ce1c98d61f5c1d4fdf10 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/DecodeFPR16RegisterClass.cpp @@ -0,0 +1,8 @@ +static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { + if (RegNo >= 32) { + return MCDisassembler::Fail; + } + MCRegister Reg = RISCV::F0_H + RegNo; + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/DecodeFPR32CRegisterClass.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/DecodeFPR32CRegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d1bc847c2b24fafa879484f9d062041ad9950bae --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/DecodeFPR32CRegisterClass.cpp @@ -0,0 +1,8 @@ +static DecodeStatus DecodeFPR32CRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { + if (RegNo >= 8) { + return MCDisassembler::Fail; + } + MCRegister Reg = RISCV::F8_F + RegNo; + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/DecodeFPR32RegisterClass.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/DecodeFPR32RegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..36aae9478effe333858379c9a1b304100f38eaf1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/DecodeFPR32RegisterClass.cpp @@ -0,0 +1,8 @@ +static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { + if (RegNo >= 32) { + return MCDisassembler::Fail; + } + MCRegister Reg = RISCV::F0_F + RegNo; + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/DecodeFPR64CRegisterClass.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/DecodeFPR64CRegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6ad24e5137888045d3acc32ed95530c2d3e15529 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/DecodeFPR64CRegisterClass.cpp @@ -0,0 +1,8 @@ +static DecodeStatus DecodeFPR64CRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { + if (RegNo >= 8) { + return MCDisassembler::Fail; + } + MCRegister Reg = RISCV::F8_D + RegNo; + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/DecodeFPR64RegisterClass.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/DecodeFPR64RegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ae3dfca3caacd67020ee25fe6f85414520efaabe --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/DecodeFPR64RegisterClass.cpp @@ -0,0 +1,8 @@ +static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { + if (RegNo >= 32) { + return MCDisassembler::Fail; + } + MCRegister Reg = RISCV::F0_D + RegNo; + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/DecodeGPRCRegisterClass.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/DecodeGPRCRegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3edc390bf8de970a40451494a5aec58321519e7e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/DecodeGPRCRegisterClass.cpp @@ -0,0 +1,8 @@ +static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { + if (RegNo >= 8) { + return MCDisassembler::Fail; + } + MCRegister Reg = RISCV::X8 + RegNo; + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/DecodeGPRNoX0RegisterClass.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/DecodeGPRNoX0RegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..019654808af5f3e9c6795bc28ace71abdf367d21 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/DecodeGPRNoX0RegisterClass.cpp @@ -0,0 +1,6 @@ +static DecodeStatus DecodeGPRNoX0RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { + if (RegNo == 0) { + return MCDisassembler::Fail; + } + return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/DecodeGPRNoX0X2RegisterClass.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/DecodeGPRNoX0X2RegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d6f18fdce1b4c98576300921500dfc1bd3d0f4f8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/DecodeGPRNoX0X2RegisterClass.cpp @@ -0,0 +1,6 @@ +static DecodeStatus DecodeGPRNoX0X2RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { + if (RegNo == 2) { + return MCDisassembler::Fail; + } + return DecodeGPRNoX0RegisterClass(Inst, RegNo, Address, Decoder); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/DecodeGPRRegisterClass.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/DecodeGPRRegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..23847ddc8e1562eb28b6353bbee940cac56d8acd --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/DecodeGPRRegisterClass.cpp @@ -0,0 +1,10 @@ +static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { + const FeatureBitset &FeatureBits = static_cast(Decoder)->getSubtargetInfo().getFeatureBits(); + bool IsRV32E = FeatureBits[RISCV::FeatureRV32E]; + if (RegNo >= 32 || (IsRV32E && RegNo >= 16)) { + return MCDisassembler::Fail; + } + MCRegister Reg = RISCV::X0 + RegNo; + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/DecodeVRRegisterClass.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/DecodeVRRegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ea83a9dcc3429e5c226968b1d1d94ddeedc751bc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/DecodeVRRegisterClass.cpp @@ -0,0 +1,8 @@ +static DecodeStatus DecodeVRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { + if (RegNo >= 32) { + return MCDisassembler::Fail; + } + MCRegister Reg = RISCV::V0 + RegNo; + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/Disassembler.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/Disassembler.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b68c6a0167549bc8f749b0e470e9d23c43926635 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/Disassembler.cpp @@ -0,0 +1,2 @@ +RISCVDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, MCInstrInfo const *MCII) : MCDisassembler(STI, Ctx), MCII(MCII) { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/LLVMInitializeDisassembler.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/LLVMInitializeDisassembler.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1ed8ecad6545c74078d9b77942c9b5c2a24a16d8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/LLVMInitializeDisassembler.cpp @@ -0,0 +1,4 @@ +extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVDisassembler() { + TargetRegistry::RegisterMCDisassembler(getTheRISCV32Target(), createRISCVDisassembler); + TargetRegistry::RegisterMCDisassembler(getTheRISCV64Target(), createRISCVDisassembler); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/addImplySP.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/addImplySP.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8ccacd508efb4089c860bb106baa89d892902431 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/addImplySP.cpp @@ -0,0 +1,9 @@ +static void addImplySP(MCInst &Inst, int64_t Address, const void *Decoder) { + if (Inst.getOpcode() == RISCV::C_LWSP || Inst.getOpcode() == RISCV::C_SWSP || Inst.getOpcode() == RISCV::C_LDSP || Inst.getOpcode() == RISCV::C_SDSP || Inst.getOpcode() == RISCV::C_FLWSP || Inst.getOpcode() == RISCV::C_FSWSP || Inst.getOpcode() == RISCV::C_FLDSP || Inst.getOpcode() == RISCV::C_FSDSP || Inst.getOpcode() == RISCV::C_ADDI4SPN) { + DecodeGPRRegisterClass(Inst, 2, Address, Decoder); + } + if (Inst.getOpcode() == RISCV::C_ADDI16SP) { + DecodeGPRRegisterClass(Inst, 2, Address, Decoder); + DecodeGPRRegisterClass(Inst, 2, Address, Decoder); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/createDisassembler.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/createDisassembler.cpp new file mode 100644 index 0000000000000000000000000000000000000000..498d4e2da63069504b61fd82b710c75962d5a343 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/createDisassembler.cpp @@ -0,0 +1,3 @@ +static MCDisassembler *createRISCVDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx) { + return new RISCVDisassembler(STI, Ctx, T.createMCInstrInfo()); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/decodeCLUIImmOperand.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/decodeCLUIImmOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..56923d00f9f34f97fd7d6f2a92844eefb789431b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/decodeCLUIImmOperand.cpp @@ -0,0 +1,8 @@ +static DecodeStatus decodeCLUIImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) { + assert(isUInt<6>(Imm) && "Invalid immediate"); + if (Imm > 31) { + Imm = (SignExtend64<6>(Imm) & 0xfffff); + } + Inst.addOperand(MCOperand::createImm(Imm)); + return MCDisassembler::Success; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/decodeFRMArg.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/decodeFRMArg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..42bc2ab0b8e381b06b0a7b99bc2e16f91132e611 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/decodeFRMArg.cpp @@ -0,0 +1,8 @@ +static DecodeStatus decodeFRMArg(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) { + assert(isUInt<3>(Imm) && "Invalid immediate"); + if (!llvm::RISCVFPRndMode::isValidRoundingMode(Imm)) { + return MCDisassembler::Fail; + } + Inst.addOperand(MCOperand::createImm(Imm)); + return MCDisassembler::Success; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/decodeRVCInstrRdRs1Rs2.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/decodeRVCInstrRdRs1Rs2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ff736e6728f99593a0e367fe7ae7c308fddee2cb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/decodeRVCInstrRdRs1Rs2.cpp @@ -0,0 +1,9 @@ +static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { + unsigned d = fieldFromInstruction(Insn, 7, 5); + unsigned const9 = 0; + unsigned s1 = fieldFromInstruction(Insn, 2, 5); + DecodeStatus status = DecodeGPRRegisterClass(Inst, d, Address, Decoder); + Inst.addOperand(Inst.getOperand(const9)); + status = DecodeGPRRegisterClass(Inst, s1, Address, Decoder); + return MCDisassembler::Success; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/decodeRVCInstrRdRs1UImm.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/decodeRVCInstrRdRs1UImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4583b28d5e2cc6dc158fc5c94735ce0db8db858d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/decodeRVCInstrRdRs1UImm.cpp @@ -0,0 +1,9 @@ +static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { + DecodeGPRRegisterClass(Inst, 0, Address, Decoder); + Inst.addOperand(Inst.getOperand(0)); + uint64_t UImm6 = fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5); + DecodeStatus Result = decodeUImmOperand<6>(Inst, UImm6, Address, Decoder); + (void)Result; + assert(Result == MCDisassembler::Success && "Invalid immediate"); + return MCDisassembler::Success; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/decodeRVCInstrRdRs2.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/decodeRVCInstrRdRs2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8ce75106ef40771cb6415341680d69cf98151355 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/decodeRVCInstrRdRs2.cpp @@ -0,0 +1,7 @@ +static DecodeStatus decodeRVCInstrRdRs2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { + unsigned Rd = fieldFromInstruction(Insn, 7, 5); + unsigned Rs2 = fieldFromInstruction(Insn, 2, 5); + DecodeGPRRegisterClass(Inst, Rd, Address, Decoder); + DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder); + return MCDisassembler::Success; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/decodeRVCInstrRdSImm.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/decodeRVCInstrRdSImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..faf42482128dc81f79631797aaa131b57faa45bb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/decodeRVCInstrRdSImm.cpp @@ -0,0 +1,8 @@ +static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { + DecodeGPRRegisterClass(Inst, 0, Address, Decoder); + uint64_t SImm6 = fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5); + DecodeStatus Result = decodeSImmOperand<6>(Inst, SImm6, Address, Decoder); + (void)Result; + assert(Result == MCDisassembler::Success && "Invalid immediate"); + return MCDisassembler::Success; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/decodeRVCInstrSImm.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/decodeRVCInstrSImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4380b36238a4132769709bf280da1414dfa1ab7f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/decodeRVCInstrSImm.cpp @@ -0,0 +1,7 @@ +static DecodeStatus decodeRVCInstrSImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { + uint64_t SImm6 = fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5); + DecodeStatus Result = decodeSImmOperand<6>(Inst, SImm6, Address, Decoder); + (void)Result; + assert(Result == MCDisassembler::Success && "Invalid immediate"); + return MCDisassembler::Success; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/decodeSImmNonZeroOperand.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/decodeSImmNonZeroOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b6df53e27f2f7bb0bf6af2592e13fc3189f9de88 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/decodeSImmNonZeroOperand.cpp @@ -0,0 +1,9 @@ +template static DecodeStatus decodeSImmNonZeroOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) { + if (Imm == 0) { + return MCDisassembler::Fail; + } + assert(isUInt(Imm) && "Invalid immediate"); + addImplySP(Inst, Address, Decoder); + Inst.addOperand(MCOperand::createImm(SignExtend64(Imm))); + return MCDisassembler::Success; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/decodeSImmOperand.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/decodeSImmOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a56c1c3848efb98e2783ac2b3e50392822d1860b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/decodeSImmOperand.cpp @@ -0,0 +1,6 @@ +template static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) { + assert(isUInt(Imm) && "Invalid immediate"); + addImplySP(Inst, Address, Decoder); + Inst.addOperand(MCOperand::createImm(SignExtend64(Imm))); + return MCDisassembler::Success; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/decodeSImmOperandAndLsl1.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/decodeSImmOperandAndLsl1.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0e565169c666715ddbb61d5b3e884cc7b628f469 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/decodeSImmOperandAndLsl1.cpp @@ -0,0 +1,5 @@ +template static DecodeStatus decodeSImmOperandAndLsl1(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) { + assert(isUInt(Imm) && "Invalid immediate"); + Inst.addOperand(MCOperand::createImm(SignExtend64(Imm << 1))); + return MCDisassembler::Success; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/decodeUImmNonZeroOperand.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/decodeUImmNonZeroOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4f08c154acb38533e848886a589b04bc524212a9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/decodeUImmNonZeroOperand.cpp @@ -0,0 +1,6 @@ +template static DecodeStatus decodeUImmNonZeroOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) { + if (Imm == 0) { + return MCDisassembler::Fail; + } + return decodeUImmOperand(Inst, Imm, Address, Decoder); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/decodeUImmOperand.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/decodeUImmOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e940d44b9e6b88e433ea55a8013356671e1ef239 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/decodeUImmOperand.cpp @@ -0,0 +1,6 @@ +template static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) { + assert(isUInt(Imm) && "Invalid immediate"); + addImplySP(Inst, Address, Decoder); + Inst.addOperand(MCOperand::createImm(Imm)); + return MCDisassembler::Success; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/decodeVMaskReg.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/decodeVMaskReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0ea5f1578a4fbbdd90b384382f28cc1bc2bce945 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/decodeVMaskReg.cpp @@ -0,0 +1,12 @@ +static DecodeStatus decodeVMaskReg(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { + MCRegister Reg = RISCV::NoRegister; + if (RegNo == 0) { + Inst.addOperand(MCOperand::createReg(RISCV::V0)); + return MCDisassembler::Success; + } + if (RegNo == 1) { + Inst.addOperand(MCOperand::createReg(RISCV::NoRegister)); + return MCDisassembler::Success; + } + return MCDisassembler::Fail; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/getInstruction.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/getInstruction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1b6b768e230411e68b01e432b0cea4141325942a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Disassembler/Disassembler/getInstruction.cpp @@ -0,0 +1,41 @@ +DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size, ArrayRef Bytes, uint64_t Address, raw_ostream &CS) const { + uint32_t Insn; + DecodeStatus Result; + if ((Bytes[0] & 0x3) == 0x3) { + if (Bytes.size() < 4) { + Size = 0; + return MCDisassembler::Fail; + } + Insn = support::endian::read32le(Bytes.data()); + LLVM_DEBUG(dbgs() << "Trying RISCV32 table :\n"); + Result = decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI); + Size = 4; + } + else { + if (Bytes.size() < 2) { + Size = 0; + return MCDisassembler::Fail; + } + Insn = support::endian::read16le(Bytes.data()); + if (!STI.getFeatureBits()[RISCV::Feature64Bit]) { + LLVM_DEBUG(dbgs() << "Trying RISCV32Only_16 table (16-bit Instruction):\n"); + Result = decodeInstruction(DecoderTableRISCV32Only_16, MI, Insn, Address, this, STI); + if (Result != MCDisassembler::Fail) { + Size = 2; + return Result; + } + } + if (STI.getFeatureBits()[RISCV::FeatureExtZbproposedc] && STI.getFeatureBits()[RISCV::FeatureStdExtC]) { + LLVM_DEBUG(dbgs() << "Trying RVBC32 table (BitManip 16-bit Instruction):\n"); + Result = decodeInstruction(DecoderTableRVBC16, MI, Insn, Address, this, STI); + if (Result != MCDisassembler::Fail) { + Size = 2; + return Result; + } + } + LLVM_DEBUG(dbgs() << "Trying RISCV_C table (16-bit Instruction):\n"); + Result = decodeInstruction(DecoderTable16, MI, Insn, Address, this, STI); + Size = 2; + } + return Result; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/AsmBackend.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/AsmBackend.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ef34215b142479c87b1510584ea79489a5710109 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/AsmBackend.cpp @@ -0,0 +1,4 @@ +RISCVAsmBackend(const MCSubtargetInfo &STI, uint8_t OSABI, bool Is64Bit, const MCTargetOptions &Options) : MCAsmBackend(support::little), STI(STI), OSABI(OSABI), Is64Bit(Is64Bit), TargetOptions(Options) { + TargetABI = RISCVABI::computeTargetABI(STI.getTargetTriple(), STI.getFeatureBits(), Options.getABIName()); + RISCVFeatures::validate(STI.getTargetTriple(), STI.getFeatureBits()); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/adjustFixupValue.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/adjustFixupValue.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1d00ba8cb22e6e315ffa265d1c176117c48a3639 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/adjustFixupValue.cpp @@ -0,0 +1,86 @@ +static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value, MCContext &Ctx) { + unsigned Kind; + Kind = Fixup.getTargetKind(); + if (Kind == FK_Data_1) { + return Value; + } + if (Kind == FK_Data_2) { + return Value; + } + if (Kind == FK_Data_4) { + return Value; + } + if (Kind == FK_Data_8) { + return Value; + } + if (Kind == FK_Data_6b) { + return Value; + } + if (Kind == RISCV::fixup_riscv_lo12_i) { + return Value & 0xfff; + } + if (Kind == RISCV::fixup_riscv_pcrel_lo12_i) { + return Value & 0xfff; + } + if (Kind == RISCV::fixup_riscv_tprel_lo12_i) { + return Value & 0xfff; + } + if (Kind == RISCV::fixup_riscv_lo12_s) { + return (((Value >> 5) & 0x7f) << 25) | ((Value & 0x1f) << 7); + } + if (Kind == RISCV::fixup_riscv_pcrel_lo12_s) { + return (((Value >> 5) & 0x7f) << 25) | ((Value & 0x1f) << 7); + } + if (Kind == RISCV::fixup_riscv_tprel_lo12_s) { + return (((Value >> 5) & 0x7f) << 25) | ((Value & 0x1f) << 7); + } + if (Kind == RISCV::fixup_riscv_hi20) { + return ((Value + 0x800) >> 12) & 0xfffff; + } + if (Kind == RISCV::fixup_riscv_pcrel_hi20) { + return ((Value + 0x800) >> 12) & 0xfffff; + } + if (Kind == RISCV::fixup_riscv_tprel_hi20) { + return ((Value + 0x800) >> 12) & 0xfffff; + } + if (Kind == RISCV::fixup_riscv_call) { + return ((Value + 0x800ULL) & 0xfffff000ULL) | (((Value & 0xfffULL) << 20) << 32); + } + if (Kind == RISCV::fixup_riscv_call_plt) { + return ((Value + 0x800ULL) & 0xfffff000ULL) | (((Value & 0xfffULL) << 20) << 32); + } + if (Kind == RISCV::fixup_riscv_rvc_jump) { + return (((Value >> 11) & 0x1) << 10) | (((Value >> 4) & 0x1) << 9) | (((Value >> 8) & 0x3) << 7) | (((Value >> 10) & 0x1) << 6) | (((Value >> 6) & 0x1) << 5) | (((Value >> 7) & 0x1) << 4) | (((Value >> 1) & 0x7) << 1) | ((Value >> 5) & 0x1); + } + if (Kind == RISCV::fixup_riscv_rvc_branch) { + return (((Value >> 8) & 0x1) << 12) | (((Value >> 3) & 0x3) << 10) | (((Value >> 6) & 0x3) << 5) | (((Value >> 1) & 0x3) << 3) | (((Value >> 5) & 0x1) << 2); + } + if (Kind == RISCV::fixup_riscv_tls_got_hi20) { + llvm_unreachable("Relocation should be unconditionally forced\n"); + } + if (Kind == RISCV::fixup_riscv_tls_gd_hi20) { + llvm_unreachable("Relocation should be unconditionally forced\n"); + } + if (Kind == RISCV::fixup_riscv_got_hi20) { + llvm_unreachable("Relocation should be unconditionally forced\n"); + } + if (Kind == RISCV::fixup_riscv_branch) { + if (!isInt<13>(Value)) { + Ctx.reportError(Fixup.getLoc(), "fixup value out of range"); + } + if (Value & 0x1) { + Ctx.reportError(Fixup.getLoc(), "fixup value must be 2-byte aligned"); + } + return (((Value >> 11) & 0x1) << 7); + } + if (Kind == RISCV::fixup_riscv_jal) { + if (!isInt<21>(Value)) { + Ctx.reportError(Fixup.getLoc(), "fixup value out of range"); + } + if (Value & 0x1) { + Ctx.reportError(Fixup.getLoc(), "fixup value must be 2-byte aligned"); + } + return (((Value >> 20) & 0x1) << 19) | (((Value >> 1) & 0x3ff) << 9) | (((Value >> 11) & 0x1) << 8) | ((Value >> 12) & 0xff); + } + llvm_unreachable("Unknown fixup kind!"); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/applyFixup.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/applyFixup.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6f805ec0a5bc2cb96d16ba5a8e177d99f0bad2aa --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/applyFixup.cpp @@ -0,0 +1,19 @@ +void RISCVAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,const MCValue &Target,MutableArrayRef Data, uint64_t Value,bool IsResolved, const MCSubtargetInfo *STI) const { + MCFixupKind Kind = Fixup.getKind(); + if (Kind >= FirstLiteralRelocationKind) { + return ; + } + MCContext &Ctx = Asm.getContext(); + MCFixupKindInfo Info = getFixupKindInfo(Kind); + if (!Value) { + return ; + } + Value = adjustFixupValue(Fixup, Value, Ctx); + Value <<= Info.TargetOffset; + unsigned Offset = Fixup.getOffset(); + unsigned NumBytes = alignTo(Info.TargetSize + Info.TargetOffset, 8) / 8; + assert(Offset + NumBytes <= Data.size() && "Invalid fixup offset!"); + for (unsigned i = 0; i != NumBytes; ++i) { + Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/createAsmBackend.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/createAsmBackend.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cbb77fce7853eba057e346ceab62e761785a5616 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/createAsmBackend.cpp @@ -0,0 +1,5 @@ +MCAsmBackend *llvm::createRISCVAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options) { + const Triple &TT = STI.getTargetTriple(); + uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS()); + return new RISCVAsmBackend(STI, OSABI, TT.isArch64Bit(), Options); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/createObjectTargetWriter.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/createObjectTargetWriter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..899027cb9566b9956193576250199de336ddb193 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/createObjectTargetWriter.cpp @@ -0,0 +1,3 @@ +std::unique_ptr RISCVAsmBackend::createObjectTargetWriter() const { + return createRISCVELFObjectWriter(OSABI, Is64Bit); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/evaluateTargetFixup.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/evaluateTargetFixup.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a200b75ea98b3459dc89d83a2964ae971e563063 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/evaluateTargetFixup.cpp @@ -0,0 +1,50 @@ +bool RISCVAsmBackend::evaluateTargetFixup(const MCAssembler &Asm, const MCAsmLayout &Layout, const MCFixup &Fixup, const MCFragment *DF, const MCValue &Target, uint64_t &Value, bool &WasForced) { + const MCFixup *AUIPCFixup; + const MCFragment *AUIPCDF; + MCValue AUIPCTarget; + switch (Fixup.getTargetKind()) { + default: + llvm_unreachable("Unexpected fixup kind!"); + case RISCV::fixup_riscv_pcrel_hi20: + AUIPCFixup = &Fixup; + AUIPCDF = DF; + AUIPCTarget = Target; + break; + case RISCV::fixup_riscv_pcrel_lo12_i: + case RISCV::fixup_riscv_pcrel_lo12_s: { + AUIPCFixup = cast(Fixup.getValue())->getPCRelHiFixup(&AUIPCDF); + if (!AUIPCFixup) { + Asm.getContext().reportError(Fixup.getLoc(), "could not find corresponding %pcrel_hi"); + return true; + } + const MCExpr *AUIPCExpr = AUIPCFixup->getValue(); + if (!AUIPCExpr->evaluateAsRelocatable(AUIPCTarget, &Layout, AUIPCFixup)) { + return true; + } + break; + } + } + if (!AUIPCTarget.getSymA() || AUIPCTarget.getSymB()) { + return false; + } + const MCSymbolRefExpr *A = AUIPCTarget.getSymA(); + const MCSymbol &SA = A->getSymbol(); + if (A->getKind() != MCSymbolRefExpr::VK_None || SA.isUndefined()) { + return false; + } + auto *Writer = Asm.getWriterPtr(); + if (!Writer) { + return false; + } + bool IsResolved = Writer->isSymbolRefDifferenceFullyResolvedImpl(Asm, SA, *AUIPCDF, false, true); + if (!IsResolved) { + return false; + } + Value = Layout.getSymbolOffset(SA) + AUIPCTarget.getConstant(); + Value -= Layout.getFragmentOffset(AUIPCDF) + AUIPCFixup->getOffset(); + if (shouldForceRelocation(Asm, *AUIPCFixup, AUIPCTarget)) { + WasForced = true; + return false; + } + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/fixupNeedsRelaxation.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/fixupNeedsRelaxation.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c2d7f65b53a8d71a36becd18d92452b97ccf728f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/fixupNeedsRelaxation.cpp @@ -0,0 +1,3 @@ +bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, const MCRelaxableFragment *DF, const MCAsmLayout &Layout) const override { + llvm_unreachable("Handled by fixupNeedsRelaxationAdvanced"); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/fixupNeedsRelaxationAdvanced.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/fixupNeedsRelaxationAdvanced.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0ec2d779def6933b2b61eb6de6cd74a3e29a2bf8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/fixupNeedsRelaxationAdvanced.cpp @@ -0,0 +1,14 @@ +bool RISCVAsmBackend::fixupNeedsRelaxationAdvanced(const MCFixup &Fixup, bool Resolved, uint64_t Value, const MCRelaxableFragment *DF, const MCAsmLayout &Layout, const bool WasForced) const { + if (!Resolved && !WasForced) { + return true; + } + int64_t Offset = int64_t(Value); + switch (Fixup.getTargetKind()) { + case RISCV::fixup_riscv_rvc_branch: + return Offset > 254 || Offset < -256; + case RISCV::fixup_riscv_rvc_jump: + return Offset > 2046 || Offset < -2048; + default: + return false; + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/getFixupKind.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/getFixupKind.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9016a3840b84201f3ee27f9769f23843493270a5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/getFixupKind.cpp @@ -0,0 +1,14 @@ +Optional RISCVAsmBackend::getFixupKind(StringRef Name) const { + if (STI.getTargetTriple().isOSBinFormatELF()) { + unsigned Type; + Type = llvm::StringSwitch(Name) + #define ELF_RELOC(X, Y) .Case(#X, Y) + #include "llvm/BinaryFormat/ELFRelocs/RISCV.def" + #undef ELF_RELOC + .Default(-1u); + if (Type != -1u) { + return static_cast(FirstLiteralRelocationKind + Type); + } + } + return None; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/getFixupKindInfo.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/getFixupKindInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..344e37ea708d0c1573e1d5e08920d42d54d66739 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/getFixupKindInfo.cpp @@ -0,0 +1,33 @@ +const MCFixupKindInfo & RISCVAsmBackend::getFixupKindInfo(MCFixupKind Kind) const { + const static MCFixupKindInfo Infos[RISCV::NumTargetFixupKinds] = { + {"fixup_riscv_hi20", 12, 20, 0}, + {"fixup_riscv_lo12_i", 20, 12, 0}, + {"fixup_riscv_lo12_s", 0, 32, 0}, + {"fixup_riscv_pcrel_hi20", 12, 20, MCFixupKindInfo::FKF_IsPCRel | MCFixupKindInfo::FKF_IsTarget}, + {"fixup_riscv_pcrel_lo12_i", 20, 12, MCFixupKindInfo::FKF_IsPCRel | MCFixupKindInfo::FKF_IsTarget}, + {"fixup_riscv_pcrel_lo12_s", 0, 32, MCFixupKindInfo::FKF_IsPCRel | MCFixupKindInfo::FKF_IsTarget}, + {"fixup_riscv_got_hi20", 12, 20, MCFixupKindInfo::FKF_IsPCRel}, + {"fixup_riscv_tprel_hi20", 12, 20, 0}, + {"fixup_riscv_tprel_lo12_i", 20, 12, 0}, + {"fixup_riscv_tprel_lo12_s", 0, 32, 0}, + {"fixup_riscv_tprel_add", 0, 0, 0}, + {"fixup_riscv_tls_got_hi20", 12, 20, MCFixupKindInfo::FKF_IsPCRel}, + {"fixup_riscv_tls_gd_hi20", 12, 20, MCFixupKindInfo::FKF_IsPCRel}, + {"fixup_riscv_jal", 12, 20, MCFixupKindInfo::FKF_IsPCRel}, + {"fixup_riscv_branch", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, + {"fixup_riscv_rvc_jump", 2, 11, MCFixupKindInfo::FKF_IsPCRel}, + {"fixup_riscv_rvc_branch", 0, 16, MCFixupKindInfo::FKF_IsPCRel}, + {"fixup_riscv_call", 0, 64, MCFixupKindInfo::FKF_IsPCRel}, + {"fixup_riscv_call_plt", 0, 64, MCFixupKindInfo::FKF_IsPCRel}, + {"fixup_riscv_relax", 0, 0, 0}, + {"fixup_riscv_align", 0, 0, 0} + }; + if (Kind >= FirstLiteralRelocationKind) { + return MCAsmBackend::getFixupKindInfo(FK_NONE); + } + if (Kind < FirstTargetFixupKind) { + return MCAsmBackend::getFixupKindInfo(Kind); + } + assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && "Invalid kind!"); + return Infos[Kind - FirstTargetFixupKind]; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/getNumFixupKinds.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/getNumFixupKinds.cpp new file mode 100644 index 0000000000000000000000000000000000000000..746a8de2786e0986eb0d4ef57b90b600aa813eb4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/getNumFixupKinds.cpp @@ -0,0 +1,3 @@ +unsigned getNumFixupKinds() const override { + return RISCV::NumTargetFixupKinds; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/getRelaxedOpcode.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/getRelaxedOpcode.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7a8dce3b201b77083cd73b657c5dac73e342fdca --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/getRelaxedOpcode.cpp @@ -0,0 +1,15 @@ +unsigned RISCVAsmBackend::getRelaxedOpcode(unsigned Op) const { + if (Op == RISCV::C_BEQZ) { + return RISCV::BEQ; + } + if (Op == RISCV::C_BNEZ) { + return RISCV::BNE; + } + if (Op == RISCV::C_J) { + return RISCV::JAL; + } + if (Op == RISCV::C_JAL) { + return RISCV::JAL; + } + return Op; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/getTargetABI.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/getTargetABI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6ba240b805d561f415ec4ee11045c3d6eb8dea8e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/getTargetABI.cpp @@ -0,0 +1,3 @@ +RISCVABI::ABI getTargetABI() const { + return TargetABI; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/getTargetOptions.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/getTargetOptions.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0ba9da6c2169958b5222a337d15c7920c3b3a0a4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/getTargetOptions.cpp @@ -0,0 +1,3 @@ +const MCTargetOptions &getTargetOptions() const { + return TargetOptions; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/mayNeedRelaxation.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/mayNeedRelaxation.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a6ab22b5e3a82bac66595e73244230ced8e6c2cb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/mayNeedRelaxation.cpp @@ -0,0 +1,15 @@ +bool RISCVAsmBackend::mayNeedRelaxation(const MCInst &Inst, const MCSubtargetInfo &STI) const { + if (Inst.getOpcode() == RISCV::C_BEQZ) { + return true; + } + if (Inst.getOpcode() == RISCV::C_BNEZ) { + return true; + } + if (Inst.getOpcode() == RISCV::C_J) { + return true; + } + if (Inst.getOpcode() == RISCV::C_JAL) { + return true; + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/relaxInstruction.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/relaxInstruction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5d47f9e24849b2b1245e390ffc5e557ee66c2675 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/relaxInstruction.cpp @@ -0,0 +1,34 @@ +void RISCVAsmBackend::relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI, MCInst &Res) const { + MCInst Res; + if (Inst.getOpcode() == RISCV::C_BEQZ) { + Res.setOpcode(RISCV::BEQ); + Res.addOperand(Inst.getOperand(0)); + Res.addOperand(MCOperand::createReg(RISCV::X0)); + Res.addOperand(Inst.getOperand(1)); + Inst = std::move(Res); + return ; + } + if (Inst.getOpcode() == RISCV::C_BNEZ) { + Res.setOpcode(RISCV::BNE); + Res.addOperand(Inst.getOperand(0)); + Res.addOperand(MCOperand::createReg(RISCV::X0)); + Res.addOperand(Inst.getOperand(1)); + Inst = std::move(Res); + return ; + } + if (Inst.getOpcode() == RISCV::C_J) { + Res.setOpcode(RISCV::JAL); + Res.addOperand(MCOperand::createReg(RISCV::X0)); + Res.addOperand(Inst.getOperand(0)); + Inst = std::move(Res); + return ; + } + if (Inst.getOpcode() == RISCV::C_JAL) { + Res.setOpcode(RISCV::JAL); + Res.addOperand(MCOperand::createReg(RISCV::X1)); + Res.addOperand(Inst.getOperand(0)); + Inst = std::move(Res); + return ; + } + llvm_unreachable("Opcode not expected!"); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/requiresDiffExpressionRelocations.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/requiresDiffExpressionRelocations.cpp new file mode 100644 index 0000000000000000000000000000000000000000..20caba2eb4d9bfb4a0d6f036615d2b0b9b4de29d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/requiresDiffExpressionRelocations.cpp @@ -0,0 +1,3 @@ +bool requiresDiffExpressionRelocations() const override { + return willForceRelocations(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/setForceRelocs.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/setForceRelocs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c50c542fcb66c027d042a9f86d3a2b22389d8363 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/setForceRelocs.cpp @@ -0,0 +1,3 @@ +void setForceRelocs() { + ForceRelocs = true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/shouldForceRelocation.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/shouldForceRelocation.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5ba38725c60c617aaa46c733ff8a0ed4b0c77bcb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/shouldForceRelocation.cpp @@ -0,0 +1,39 @@ +bool RISCVAsmBackend::shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target) { + if (Fixup.getTargetKind() >= FirstLiteralRelocationKind) { + return true; + } + if (Fixup.getTargetKind() == FK_Data_1) { + if (Target.isAbsolute()) { + return false; + } + return true; + } + if (Fixup.getTargetKind() == FK_Data_2) { + if (Target.isAbsolute()) { + return false; + } + return true; + } + if (Fixup.getTargetKind() == FK_Data_4) { + if (Target.isAbsolute()) { + return false; + } + return true; + } + if (Fixup.getTargetKind() == FK_Data_8) { + if (Target.isAbsolute()) { + return false; + } + return true; + } + if (Fixup.getTargetKind() == RISCV::fixup_riscv_got_hi20) { + return true; + } + if (Fixup.getTargetKind() == RISCV::fixup_riscv_tls_got_hi20) { + return true; + } + if (Fixup.getTargetKind() == RISCV::fixup_riscv_tls_gd_hi20) { + return true; + } + return STI.getFeatureBits()[RISCV::FeatureRelax] || ForceRelocs; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/shouldInsertExtraNopBytesForCodeAlign.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/shouldInsertExtraNopBytesForCodeAlign.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cbc97e17845d545983c933ea23dc3e4c437503b0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/shouldInsertExtraNopBytesForCodeAlign.cpp @@ -0,0 +1,14 @@ +bool RISCVAsmBackend::shouldInsertExtraNopBytesForCodeAlign(const MCAlignFragment &AF, unsigned &Size) { + if (!STI.getFeatureBits()[RISCV::FeatureRelax]) { + return false; + } + bool HasStdExtC = STI.getFeatureBits()[RISCV::FeatureStdExtC]; + unsigned MinNopLen = HasStdExtC ? 2 : 4; + if (AF.getAlignment() <= MinNopLen) { + return false; + } + else { + Size = AF.getAlignment() - MinNopLen; + return true; + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/shouldInsertFixupForCodeAlign.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/shouldInsertFixupForCodeAlign.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0cba76a5121626885e6f5d385f92d143bb1bbf7e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/shouldInsertFixupForCodeAlign.cpp @@ -0,0 +1,16 @@ +bool RISCVAsmBackend::shouldInsertFixupForCodeAlign(MCAssembler &Asm, const MCAsmLayout &Layout, MCAlignFragment &AF) { + if (!STI.getFeatureBits()[RISCV::FeatureRelax]) { + return false; + } + unsigned Count; + if (!shouldInsertExtraNopBytesForCodeAlign(AF, Count) || (Count == 0)) { + return false; + } + MCContext &Ctx = Asm.getContext(); + const MCExpr *Dummy = MCConstantExpr::create(0, Ctx); + MCFixup Fixup = MCFixup::create(0, Dummy, MCFixupKind(RISCV::fixup_riscv_align), SMLoc()); + uint64_t FixedValue = 0; + MCValue NopBytes = MCValue::get(Count); + Asm.getWriter().recordRelocation(Asm, Layout, &AF, Fixup, NopBytes, FixedValue); + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/willForceRelocations.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/willForceRelocations.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8d4f67dbd32002e52666f53c763a70a4dba9e31b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/willForceRelocations.cpp @@ -0,0 +1,3 @@ +bool willForceRelocations() const { + return ForceRelocs || STI.getFeatureBits()[RISCV::FeatureRelax]; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/writeNopData.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/writeNopData.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9d80a5b62dec8be0da614743dbfd8cce5bc86ea5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/writeNopData.cpp @@ -0,0 +1,14 @@ +bool RISCVAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const { + if (Count % 2 != 0) { + return false; + } + uint64_t NopCount = Count / 4; + uint64_t i; + for (i = 0; i < NopCount; ++i) { + OS.write("\x13\0\0\0", 4); + } + if (Count % 4 == 2) { + OS.write("\x01\0", 2); + } + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/~AsmBackend.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/~AsmBackend.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ef098a67f9366ad081d706783370f6efc23e3a48 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmBackend/~AsmBackend.cpp @@ -0,0 +1,2 @@ +~RISCVAsmBackend() override { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmInfo/MCAsmInfo.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmInfo/MCAsmInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9421589a9b9c1fc5b796893153daedb95b1d0d46 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmInfo/MCAsmInfo.cpp @@ -0,0 +1,10 @@ +RISCVMCAsmInfo::RISCVMCAsmInfo(const Triple &TT) { + CodePointerSize = TT.isArch64Bit() ? 8 : 4; + CalleeSaveStackSlotSize = TT.isArch64Bit() ? 8 : 4; + CommentString = "#"; + AlignmentIsInBytes = false; + SupportsDebugInformation = true; + ExceptionsType = ExceptionHandling::DwarfCFI; + Data16bitsDirective = "\t.half\t"; + Data32bitsDirective = "\t.word\t"; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmInfo/anchor.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmInfo/anchor.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a347705836916e209cf07b3a754f158902edef80 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmInfo/anchor.cpp @@ -0,0 +1,2 @@ +void RISCVMCAsmInfo::anchor() { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmInfo/getExprForFDESymbol.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmInfo/getExprForFDESymbol.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8123d7641ff42e395a6fae61de4cd9e72363c53a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/AsmInfo/getExprForFDESymbol.cpp @@ -0,0 +1,7 @@ +const MCExpr *RISCVMCAsmInfo::getExprForFDESymbol(const MCSymbol *Sym, unsigned Encoding, MCStreamer &Streamer) const { + if (Encoding & dwarf::DW_EH_PE_pcrel) { + MCContext &Ctx = Streamer.getContext(); + return RISCVMCExpr::create(MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, Ctx), RISCVMCExpr::VK_RISCV_32_PCREL, Ctx); + } + return MCAsmInfo::getExprForFDESymbol(Sym, Encoding, Streamer); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/BaseInfo/ABI.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/BaseInfo/ABI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f3883bfb643c747efaf1bd19098e38d0e4607708 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/BaseInfo/ABI.cpp @@ -0,0 +1,10 @@ +enum ABI { + ABI_ILP32, + ABI_ILP32F, + ABI_ILP32D, + ABI_ILP32E, + ABI_LP64, + ABI_LP64F, + ABI_LP64D, + ABI_Unknown +}; diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/BaseInfo/FenceField.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/BaseInfo/FenceField.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7c7b1924b5725066d01f765ea8d324f0c5053f3b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/BaseInfo/FenceField.cpp @@ -0,0 +1,6 @@ +enum FenceField { + I = 8, + O = 4, + R = 2, + W = 1 +}; diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/BaseInfo/II.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/BaseInfo/II.cpp new file mode 100644 index 0000000000000000000000000000000000000000..50b9d9071889f3b5a387cf23e5363093dd124268 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/BaseInfo/II.cpp @@ -0,0 +1,53 @@ +namespace RISCVII { +enum { + InstFormatPseudo = 0, + InstFormatR = 1, + InstFormatR4 = 2, + InstFormatI = 3, + InstFormatS = 4, + InstFormatB = 5, + InstFormatU = 6, + InstFormatJ = 7, + InstFormatCR = 8, + InstFormatCI = 9, + InstFormatCSS = 10, + InstFormatCIW = 11, + InstFormatCL = 12, + InstFormatCS = 13, + InstFormatCA = 14, + InstFormatCB = 15, + InstFormatCJ = 16, + InstFormatOther = 17, + InstFormatMask = 31, + ConstraintShift = 5, + ConstraintMask = 0b111 << ConstraintShift, + VLMulShift = ConstraintShift + 3, + VLMulMask = 0b111 , + HasDummyMaskOpShift = 3 , + HasDummyMaskOpShift = 1 , + WritesElement0Shift = HasDummyMaskOpShift + 1, + WritesElement0Mask = 1 << WritesElement0Shift, + HasMergeOpShift = 1 , + HasMergeOpMask = 1 << HasMergeOpShift, + HasSEWOpShift = 1 , + HasVLOpShift = 1 , + HasVLOpShift = HasSEWOpShift + 1, + HasVLOpMask = 1 << HasVLOpShift, +}; +enum { + MO_None = 0, + MO_CALL = 1, + MO_PLT = 2, + MO_LO = 3, + MO_HI = 4, + MO_PCREL_LO = 5, + MO_PCREL_HI = 6, + MO_GOT_HI = 7, + MO_TPREL_LO = 8, + MO_TPREL_HI = 9, + MO_TPREL_ADD = 10, + MO_TLS_GOT_HI = 11, + MO_TLS_GD_HI = 12, + MO_DIRECT_FLAG_MASK = 15 +}; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/BaseInfo/OperandType.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/BaseInfo/OperandType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3ee082abd033ba7a52a0e579c7094d92d68a2d2a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/BaseInfo/OperandType.cpp @@ -0,0 +1,10 @@ +enum OperandType : unsigned { + OPERAND_FIRST_RISCV_IMM = MCOI::OPERAND_FIRST_TARGET, + OPERAND_UIMM4 = OPERAND_FIRST_RISCV_IMM, + OPERAND_UIMM5, + OPERAND_UIMM12, + OPERAND_SIMM12, + OPERAND_UIMM20, + OPERAND_UIMMLOG2XLEN, + OPERAND_LAST_RISCV_IMM = OPERAND_UIMMLOG2XLEN +}; diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/BaseInfo/RISCVVSEW.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/BaseInfo/RISCVVSEW.cpp new file mode 100644 index 0000000000000000000000000000000000000000..48e9a099c10a3c910227f7c4c692f1923cd7b265 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/BaseInfo/RISCVVSEW.cpp @@ -0,0 +1,10 @@ +enum class RISCVVSEW { + SEW_8 = 0, + SEW_16, + SEW_32, + SEW_64, + SEW_128, + SEW_256, + SEW_512, + SEW_1024, +}; diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/BaseInfo/RVVConstraintType.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/BaseInfo/RVVConstraintType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7f6426c797a3087af47909f6164404258de6ea5e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/BaseInfo/RVVConstraintType.cpp @@ -0,0 +1,6 @@ +enum RVVConstraintType { + NoConstraint = 0, + VS2Constraint = 0b001, + VS1Constraint = 0b010, + VMConstraint = 0b100, +}; diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/BaseInfo/RoundingMode.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/BaseInfo/RoundingMode.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9322bf2c008867e4d73fcd793cfb9480b8f6f94f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/BaseInfo/RoundingMode.cpp @@ -0,0 +1,9 @@ +enum RoundingMode { + RNE = 0, + RTZ = 1, + RDN = 2, + RUP = 3, + RMM = 4, + DYN = 7, + Invalid +}; diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/BaseInfo/VLMUL.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/BaseInfo/VLMUL.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4623e7ccd5fedd630b880aaa84b07f4a81dcf701 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/BaseInfo/VLMUL.cpp @@ -0,0 +1,10 @@ +enum class RISCVVLMUL { + LMUL_1 = 0, + LMUL_2, + LMUL_4, + LMUL_8, + LMUL_RESERVED, + LMUL_F8, + LMUL_F4, + LMUL_F2 +}; diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/BaseInfo/VMTs.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/BaseInfo/VMTs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2add02bb943bcb64d7795721888ad1d4a89d0dfd --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/BaseInfo/VMTs.cpp @@ -0,0 +1,46 @@ +namespace RISCVVMVTs { +constexpr MVT vint8mf8_t = MVT::nxv1i8; +constexpr MVT vint8mf4_t = MVT::nxv2i8; +constexpr MVT vint8mf2_t = MVT::nxv4i8; +constexpr MVT vint8m1_t = MVT::nxv8i8; +constexpr MVT vint8m2_t = MVT::nxv16i8; +constexpr MVT vint8m4_t = MVT::nxv32i8; +constexpr MVT vint8m8_t = MVT::nxv64i8; +constexpr MVT vint16mf4_t = MVT::nxv1i16; +constexpr MVT vint16mf2_t = MVT::nxv2i16; +constexpr MVT vint16m1_t = MVT::nxv4i16; +constexpr MVT vint16m2_t = MVT::nxv8i16; +constexpr MVT vint16m4_t = MVT::nxv16i16; +constexpr MVT vint16m8_t = MVT::nxv32i16; +constexpr MVT vint32mf2_t = MVT::nxv1i32; +constexpr MVT vint32m1_t = MVT::nxv2i32; +constexpr MVT vint32m2_t = MVT::nxv4i32; +constexpr MVT vint32m4_t = MVT::nxv8i32; +constexpr MVT vint32m8_t = MVT::nxv16i32; +constexpr MVT vint64m1_t = MVT::nxv1i64; +constexpr MVT vint64m2_t = MVT::nxv2i64; +constexpr MVT vint64m4_t = MVT::nxv4i64; +constexpr MVT vint64m8_t = MVT::nxv8i64; +constexpr MVT vfloat16mf4_t = MVT::nxv1f16; +constexpr MVT vfloat16mf2_t = MVT::nxv2f16; +constexpr MVT vfloat16m1_t = MVT::nxv4f16; +constexpr MVT vfloat16m2_t = MVT::nxv8f16; +constexpr MVT vfloat16m4_t = MVT::nxv16f16; +constexpr MVT vfloat16m8_t = MVT::nxv32f16; +constexpr MVT vfloat32mf2_t = MVT::nxv1f32; +constexpr MVT vfloat32m1_t = MVT::nxv2f32; +constexpr MVT vfloat32m2_t = MVT::nxv4f32; +constexpr MVT vfloat32m4_t = MVT::nxv8f32; +constexpr MVT vfloat32m8_t = MVT::nxv16f32; +constexpr MVT vfloat64m1_t = MVT::nxv1f64; +constexpr MVT vfloat64m2_t = MVT::nxv2f64; +constexpr MVT vfloat64m4_t = MVT::nxv4f64; +constexpr MVT vfloat64m8_t = MVT::nxv8f64; +constexpr MVT vbool1_t = MVT::nxv64i1; +constexpr MVT vbool2_t = MVT::nxv32i1; +constexpr MVT vbool4_t = MVT::nxv16i1; +constexpr MVT vbool8_t = MVT::nxv8i1; +constexpr MVT vbool16_t = MVT::nxv4i1; +constexpr MVT vbool32_t = MVT::nxv2i1; +constexpr MVT vbool64_t = MVT::nxv1i1; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/BaseInfo/computeTargetABI.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/BaseInfo/computeTargetABI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..089445f3c62c65b40b2eec1e8b2b0026a81373bc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/BaseInfo/computeTargetABI.cpp @@ -0,0 +1,30 @@ +ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits, StringRef ABIName) { + auto TargetABI = getTargetABI(ABIName); + bool IsRV64 = TT.isArch64Bit(); + bool IsRV32E = FeatureBits[RISCV::FeatureRV32E]; + if (!ABIName.empty() && TargetABI == ABI_Unknown) { + errs() << "'" << ABIName << "' is not a recognized ABI for this target (ignoring target-abi)\n"; + } + else if (ABIName.startswith("ilp32") && IsRV64) { + errs() << "32-bit ABIs are not supported for 64-bit targets (ignoring target-abi)\n"; + TargetABI = ABI_Unknown; + } + else if (ABIName.startswith("lp64") && !IsRV64) { + errs() << "64-bit ABIs are not supported for 32-bit targets (ignoring target-abi)\n"; + TargetABI = ABI_Unknown; + } + else if (IsRV32E && TargetABI != ABI_ILP32E && TargetABI != ABI_Unknown) { + errs() << "Only the ilp32e ABI is supported for RV32E (ignoring target-abi)\n"; + TargetABI = ABI_Unknown; + } + if (TargetABI != ABI_Unknown) { + return TargetABI; + } + if (IsRV32E) { + return ABI_ILP32E; + } + if (IsRV64) { + return ABI_LP64; + } + return ABI_ILP32; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/BaseInfo/getTargetABI.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/BaseInfo/getTargetABI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fd4ae74cfd65a034a0b6664d2b6d0d58e37164c6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/BaseInfo/getTargetABI.cpp @@ -0,0 +1,24 @@ +ABI getTargetABI(StringRef Str) { + if (Str == "ilp32") { + return ABI_ILP32; + } + if (Str == "ilp32f") { + return ABI_ILP32F; + } + if (Str == "ilp32d") { + return ABI_ILP32D; + } + if (Str == "ilp32e") { + return ABI_ILP32E; + } + if (Str == "lp64") { + return ABI_LP64; + } + if (Str == "lp64f") { + return ABI_LP64F; + } + if (Str == "lp64d") { + return ABI_LP64D; + } + return ABI_Unknown; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/BaseInfo/roundingModeToString.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/BaseInfo/roundingModeToString.cpp new file mode 100644 index 0000000000000000000000000000000000000000..11291aabba65a0d4a8c320fdbf84a1e20058c498 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/BaseInfo/roundingModeToString.cpp @@ -0,0 +1,18 @@ +inline static StringRef roundingModeToString(RoundingMode RndMode) { + switch (RndMode) { + case RISCVFPRndMode::RNE: + return "rne"; + case RISCVFPRndMode::RTZ: + return "rtz"; + case RISCVFPRndMode::RDN: + return "rdn"; + case RISCVFPRndMode::RUP: + return "rup"; + case RISCVFPRndMode::RMM: + return "rmm"; + case RISCVFPRndMode::DYN: + return "dyn"; + default: + llvm_unreachable("Unknown floating point rounding mode"); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/BaseInfo/stringToRoundingMode.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/BaseInfo/stringToRoundingMode.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a002650de82613870fdc7f3717210aa582d6de4f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/BaseInfo/stringToRoundingMode.cpp @@ -0,0 +1,21 @@ +inline static RoundingMode stringToRoundingMode(StringRef Str) { + if (Str == "rne") { + return RISCVFPRndMode::RNE; + } + if (Str == "rtz") { + return RISCVFPRndMode::RTZ; + } + if (Str == "rdn") { + return RISCVFPRndMode::RDN; + } + if (Str == "rup") { + return RISCVFPRndMode::RUP; + } + if (Str == "rmm") { + return RISCVFPRndMode::RMM; + } + if (Str == "dyn") { + return RISCVFPRndMode::DYN; + } + return RISCVFPRndMode::Invalid; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/BaseInfo/validate.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/BaseInfo/validate.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ea0370ee02ed8822169582aef94e41cbbfdc3892 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/BaseInfo/validate.cpp @@ -0,0 +1,5 @@ +void validate(const Triple &TT, const FeatureBitset &FeatureBits) { + if (TT.isArch64Bit() && FeatureBits[RISCV::FeatureRV32E]) { + report_fatal_error("RV32E can't be enabled for an RV64 target"); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFObjectWriter/ELFObjectWriter.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFObjectWriter/ELFObjectWriter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4f33f3e20c0425160b017bce65157ee473529c2e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFObjectWriter/ELFObjectWriter.cpp @@ -0,0 +1,2 @@ +RISCVELFObjectWriter::RISCVELFObjectWriter(uint8_t OSABI, bool Is64Bit) : MCELFObjectTargetWriter(Is64Bit, OSABI, ELF::EM_RISCV, true) { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFObjectWriter/createELFObjectWriter.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFObjectWriter/createELFObjectWriter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cf93750ac33e2b6b5c2496f27834ac02c19f9105 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFObjectWriter/createELFObjectWriter.cpp @@ -0,0 +1,3 @@ +std::unique_ptr llvm::createRISCVELFObjectWriter(uint8_t OSABI, bool Is64Bit) { + return std::make_unique(OSABI, Is64Bit); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFObjectWriter/getRelocType.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFObjectWriter/getRelocType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a849817c9fb30e56734817ee119b857cdc083330 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFObjectWriter/getRelocType.cpp @@ -0,0 +1,132 @@ +unsigned RISCVELFObjectWriter::getRelocType(MCContext &Ctx, const MCValue &Target, const MCFixup &Fixup, bool IsPCRel) const { + const RISCVMCExpr *SExpr; + if (SExpr = dyn_cast(Fixup.getValue())) { + if (SExpr->getKind() == RISCVMCExpr::VK_RISCV_32_PCREL) { + return ELF::R_RISCV_32_PCREL; + } + } + const MCExpr *Expr = Fixup.getValue(); + unsigned Kind = Fixup.getTargetKind(); + if (Kind >= FirstLiteralRelocationKind){ + return Kind - FirstLiteralRelocationKind; + } + if (IsPCRel) { + if (Kind == FK_PCRel_4) { + return ELF::R_RISCV_32_PCREL; + } + if (Kind == RISCV::fixup_riscv_pcrel_hi20) { + return ELF::R_RISCV_PCREL_HI20; + } + if (Kind == RISCV::fixup_riscv_pcrel_lo12_i) { + return ELF::R_RISCV_PCREL_LO12_I; + } + if (Kind == RISCV::fixup_riscv_pcrel_lo12_s) { + return ELF::R_RISCV_PCREL_LO12_S; + } + if (Kind == FK_Data_4) { + return ELF::R_RISCV_32_PCREL; + } + if (Kind == RISCV::fixup_riscv_got_hi20) { + return ELF::R_RISCV_GOT_HI20; + } + if (Kind == RISCV::fixup_riscv_tls_got_hi20) { + return ELF::R_RISCV_TLS_GOT_HI20; + } + if (Kind == RISCV::fixup_riscv_tls_gd_hi20) { + return ELF::R_RISCV_TLS_GD_HI20; + } + if (Kind == RISCV::fixup_riscv_jal) { + return ELF::R_RISCV_JAL; + } + if (Kind == RISCV::fixup_riscv_branch) { + return ELF::R_RISCV_BRANCH; + } + if (Kind == RISCV::fixup_riscv_rvc_jump) { + return ELF::R_RISCV_RVC_JUMP; + } + if (Kind == RISCV::fixup_riscv_rvc_branch) { + return ELF::R_RISCV_RVC_BRANCH; + } + if (Kind == RISCV::fixup_riscv_call) { + return ELF::R_RISCV_CALL; + } + if (Kind == RISCV::fixup_riscv_call_plt) { + return ELF::R_RISCV_CALL_PLT; + } + Ctx.reportError(Fixup.getLoc(), "Unsupported relocation type"); + return ELF::R_RISCV_NONE; + } + if (Kind == FK_Data_4) { + return ELF::R_RISCV_32; + } + if (Kind == FK_Data_8) { + return ELF::R_RISCV_64; + } + if (Kind == FK_Data_Add_1) { + return ELF::R_RISCV_ADD8; + } + if (Kind == FK_Data_Add_2) { + return ELF::R_RISCV_ADD16; + } + if (Kind == FK_Data_Add_4) { + return ELF::R_RISCV_ADD32; + } + if (Kind == FK_Data_Add_8) { + return ELF::R_RISCV_ADD64; + } + if (Kind == FK_Data_1) { + Ctx.reportError(Fixup.getLoc(), "1-byte data relocations not supported"); + return ELF::R_RISCV_NONE; + } + if (Kind == FK_Data_2) { + Ctx.reportError(Fixup.getLoc(), "2-byte data relocations not supported"); + return ELF::R_RISCV_NONE; + } + if (Kind == FK_Data_Add_6b) { + return ELF::R_RISCV_SET6; + } + if (Kind == FK_Data_Sub_1) { + return ELF::R_RISCV_SUB8; + } + if (Kind == FK_Data_Sub_2) { + return ELF::R_RISCV_SUB16; + } + if (Kind == FK_Data_Sub_4) { + return ELF::R_RISCV_SUB32; + } + if (Kind == FK_Data_Sub_8) { + return ELF::R_RISCV_SUB64; + } + if (Kind == FK_Data_Sub_6b) { + return ELF::R_RISCV_SUB6; + } + if (Kind == RISCV::fixup_riscv_hi20) { + return ELF::R_RISCV_HI20; + } + if (Kind == RISCV::fixup_riscv_lo12_i) { + return ELF::R_RISCV_LO12_I; + } + if (Kind == RISCV::fixup_riscv_lo12_s) { + return ELF::R_RISCV_LO12_S; + } + if (Kind == RISCV::fixup_riscv_tprel_hi20) { + return ELF::R_RISCV_TPREL_HI20; + } + if (Kind == RISCV::fixup_riscv_tprel_lo12_i) { + return ELF::R_RISCV_TPREL_LO12_I; + } + if (Kind == RISCV::fixup_riscv_tprel_lo12_s) { + return ELF::R_RISCV_TPREL_LO12_S; + } + if (Kind == RISCV::fixup_riscv_tprel_add) { + return ELF::R_RISCV_TPREL_ADD; + } + if (Kind == RISCV::fixup_riscv_relax) { + return ELF::R_RISCV_RELAX; + } + if (Kind == RISCV::fixup_riscv_align) { + return ELF::R_RISCV_ALIGN; + } + Ctx.reportError(Fixup.getLoc(), "Unsupported relocation type"); + return ELF::R_RISCV_NONE; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFObjectWriter/needsRelocateWithSymbol.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFObjectWriter/needsRelocateWithSymbol.cpp new file mode 100644 index 0000000000000000000000000000000000000000..946e0c43f12add7422f67306d02b7ec156134cb1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFObjectWriter/needsRelocateWithSymbol.cpp @@ -0,0 +1,3 @@ +bool needsRelocateWithSymbol(const MCSymbol &Sym, unsigned Type) const override { + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFObjectWriter/~ELFObjectWriter.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFObjectWriter/~ELFObjectWriter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3c1de5f7645a8cf79fb3b5ae7778810e57bd7de1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFObjectWriter/~ELFObjectWriter.cpp @@ -0,0 +1,2 @@ +RISCVELFObjectWriter::~RISCVELFObjectWriter() { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/AttributeItem.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/AttributeItem.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9f273585d2fbc4baf7b49dd8b5f86b5b3c7ee666 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/AttributeItem.cpp @@ -0,0 +1,6 @@ +struct AttributeItem { + AttributeType Type; + unsigned Tag; + unsigned IntValue; + std::string StringValue; +}; diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/AttributeType.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/AttributeType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0bfefe54c5445d3443931e6df0f69603042c15ed --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/AttributeType.cpp @@ -0,0 +1,6 @@ +enum class AttributeType { + Hidden, + Numeric, + Text, + NumericAndText +}; diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/TargetELFStreamer.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/TargetELFStreamer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..259b611fd6b6b41d92f0d9791a83cf2ea7314cb4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/TargetELFStreamer.cpp @@ -0,0 +1,40 @@ +RISCVTargetELFStreamer::RISCVTargetELFStreamer(MCStreamer &S, const MCSubtargetInfo &STI) : RISCVTargetStreamer(S), CurrentVendor("riscv") { + MCAssembler &MCA = getStreamer().getAssembler(); + const FeatureBitset &Features = STI.getFeatureBits(); + auto &MAB = static_cast(MCA.getBackend()); + RISCVABI::ABI ABI = MAB.getTargetABI(); + assert(ABI != RISCVABI::ABI_Unknown && "Improperly initialised target ABI"); + unsigned EFlags = MCA.getELFHeaderEFlags(); + if (Features[RISCV::FeatureStdExtC]) { + EFlags = EFlags | ELF::EF_RISCV_RVC; + } + if (ABI == RISCVABI::ABI_ILP32) { + MCA.setELFHeaderEFlags(EFlags); + } + if (ABI == RISCVABI::ABI_LP64) { + MCA.setELFHeaderEFlags(EFlags); + } + if (ABI == RISCVABI::ABI_ILP32F) { + EFlags = EFlags | ELF::EF_RISCV_FLOAT_ABI_SINGLE; + MCA.setELFHeaderEFlags(EFlags); + } + if (ABI == RISCVABI::ABI_LP64F) { + EFlags = EFlags | ELF::EF_RISCV_FLOAT_ABI_SINGLE; + MCA.setELFHeaderEFlags(EFlags); + } + if (ABI == RISCVABI::ABI_ILP32D) { + EFlags = EFlags | ELF::EF_RISCV_FLOAT_ABI_DOUBLE; + MCA.setELFHeaderEFlags(EFlags); + } + if (ABI == RISCVABI::ABI_LP64D) { + EFlags = EFlags | ELF::EF_RISCV_FLOAT_ABI_DOUBLE; + MCA.setELFHeaderEFlags(EFlags); + } + if (ABI == RISCVABI::ABI_ILP32E) { + EFlags = EFlags | ELF::EF_RISCV_RVE; + MCA.setELFHeaderEFlags(EFlags); + } + if (ABI == RISCVABI::ABI_Unknown) { + llvm_unreachable("Improperly initialised target ABI"); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/calculateContentSize.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/calculateContentSize.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3594e1ecd0913c40fb32f167f15a5b118204b93a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/calculateContentSize.cpp @@ -0,0 +1,23 @@ +size_t RISCVTargetELFStreamer::calculateContentSize() const { + size_t Result = 0; + for (AttributeItem item : Contents) { + switch (item.Type) { + case AttributeType::Hidden: + break; + case AttributeType::Numeric: + Result += getULEB128Size(item.Tag); + Result += getULEB128Size(item.IntValue); + break; + case AttributeType::Text: + Result += getULEB128Size(item.Tag); + Result += item.StringValue.size() + 1; + break; + case AttributeType::NumericAndText: + Result += getULEB128Size(item.Tag); + Result += getULEB128Size(item.IntValue); + Result += item.StringValue.size() + 1; + break; + } + } + return Result; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/emitAttribute.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/emitAttribute.cpp new file mode 100644 index 0000000000000000000000000000000000000000..093204945bdf9266020a4f252f5ba14556742ce0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/emitAttribute.cpp @@ -0,0 +1,3 @@ +void RISCVTargetELFStreamer::emitAttribute(unsigned Attribute, unsigned Value) { + setAttributeItem(Attribute, Value, true); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionNoPIC.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionNoPIC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6c03e079bf63ae8073d2ede610293d88e4fa88eb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionNoPIC.cpp @@ -0,0 +1,2 @@ +void RISCVTargetELFStreamer::emitDirectiveOptionNoPIC() { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionNoRVC.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionNoRVC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ae512f51c9e685aef4b8e839b94d030c9e642b97 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionNoRVC.cpp @@ -0,0 +1,2 @@ +void RISCVTargetELFStreamer::emitDirectiveOptionNoRVC() { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionNoRelax.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionNoRelax.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6c03e079bf63ae8073d2ede610293d88e4fa88eb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionNoRelax.cpp @@ -0,0 +1,2 @@ +void RISCVTargetELFStreamer::emitDirectiveOptionNoPIC() { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionPIC.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionPIC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e0df4494aa95369ebd9176fc8eb53b6979b3169d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionPIC.cpp @@ -0,0 +1,2 @@ +void RISCVTargetELFStreamer::emitDirectiveOptionPIC() { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionPop.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionPop.cpp new file mode 100644 index 0000000000000000000000000000000000000000..32917ce043bfc2eecfcf523c3a37644e75df0194 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionPop.cpp @@ -0,0 +1,2 @@ +void RISCVTargetELFStreamer::emitDirectiveOptionPop() { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionPush.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionPush.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5aedb00352e0d7bde5d482842d91f9acc06cbb0f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionPush.cpp @@ -0,0 +1,2 @@ +void RISCVTargetELFStreamer::emitDirectiveOptionPush() { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionRVC.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionRVC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9751c5671eb6fc82c84ff719958b4cda4f7fcd60 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionRVC.cpp @@ -0,0 +1,2 @@ +void RISCVTargetELFStreamer::emitDirectiveOptionRVC() { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionRelax.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionRelax.cpp new file mode 100644 index 0000000000000000000000000000000000000000..daf4623617344c5666aca7cfbbab1513a4eb66ad --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionRelax.cpp @@ -0,0 +1,2 @@ +void RISCVTargetELFStreamer::emitDirectiveOptionRelax() { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/emitIntTextAttribute.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/emitIntTextAttribute.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4373afae59249976a7f7250e5c2abc76b45c1349 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/emitIntTextAttribute.cpp @@ -0,0 +1,3 @@ +void RISCVTargetELFStreamer::emitIntTextAttribute(unsigned Attribute, unsigned IntValue, StringRef StringValue) { + setAttributeItems(Attribute, IntValue, StringValue, true); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/emitTextAttribute.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/emitTextAttribute.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3ac8a25c6405b9d62d6aa227a9ed6556f32070fc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/emitTextAttribute.cpp @@ -0,0 +1,3 @@ +void RISCVTargetELFStreamer::emitTextAttribute(unsigned Attribute, StringRef String) { + setAttributeItem(Attribute, String, true); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/finishAttributeSection.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/finishAttributeSection.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2f2489616110f13244dbe49376832a95d9564a9e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/finishAttributeSection.cpp @@ -0,0 +1,42 @@ +void RISCVTargetELFStreamer::finishAttributeSection() { + if (Contents.empty()) { + return ; + } + if (AttributeSection) { + Streamer.SwitchSection(AttributeSection); + } + else { + MCAssembler &MCA = getStreamer().getAssembler(); + AttributeSection = MCA.getContext().getELFSection(".riscv.attributes", ELF::SHT_RISCV_ATTRIBUTES, 0); + Streamer.SwitchSection(AttributeSection); + Streamer.emitInt8(ELFAttrs::Format_Version); + } + const size_t VendorHeaderSize = 4 + CurrentVendor.size() + 1; + const size_t TagHeaderSize = 1 + 4; + const size_t ContentsSize = calculateContentSize(); + Streamer.emitInt32(VendorHeaderSize + TagHeaderSize + ContentsSize); + Streamer.emitBytes(CurrentVendor); + Streamer.emitInt8(0); + Streamer.emitInt8(ELFAttrs::File); + Streamer.emitInt32(TagHeaderSize + ContentsSize); + for (AttributeItem item : Contents) { + Streamer.emitULEB128IntValue(item.Tag); + switch (item.Type) { + default: + llvm_unreachable("Invalid attribute type"); + case AttributeType::Numeric: + Streamer.emitULEB128IntValue(item.IntValue); + break; + case AttributeType::Text: + Streamer.emitBytes(item.StringValue); + Streamer.emitInt8(0); + break; + case AttributeType::NumericAndText: + Streamer.emitULEB128IntValue(item.IntValue); + Streamer.emitBytes(item.StringValue); + Streamer.emitInt8(0); + break; + } + } + Contents.clear(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/getAttributeItem.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/getAttributeItem.cpp new file mode 100644 index 0000000000000000000000000000000000000000..39d66abbc227662e2da806f5d4602ed1f7914637 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/getAttributeItem.cpp @@ -0,0 +1,8 @@ +AttributeItem *getAttributeItem(unsigned Attribute) { + for (size_t i = 0; i < Contents.size(); ++i) { + if (Contents[i].Tag == Attribute) { + return &Contents[i]; + } + } + return nullptr; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/getStreamer.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/getStreamer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..299b2c39af48ecf340b541686259cbf54c049d4f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/getStreamer.cpp @@ -0,0 +1,3 @@ +MCELFStreamer &RISCVTargetELFStreamer::getStreamer() { + return static_cast(Streamer); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/setAttributeItem1.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/setAttributeItem1.cpp new file mode 100644 index 0000000000000000000000000000000000000000..deacd4eaf5d070a5bbea710bbd81b77e0bcd09fb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/setAttributeItem1.cpp @@ -0,0 +1,11 @@ +void setAttributeItem(unsigned Attribute, unsigned Value, bool OverwriteExisting) { + if (AttributeItem *Item = getAttributeItem(Attribute)) { + if (!OverwriteExisting) { + return ; + } + Item->Type = AttributeType::Numeric; + Item->IntValue = Value; + return; + } + Contents.push_back({AttributeType::Numeric, Attribute, Value, ""}); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/setAttributeItem2.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/setAttributeItem2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fd7620a2c8dd656c22df61966125549d23aba3d6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/setAttributeItem2.cpp @@ -0,0 +1,11 @@ +void setAttributeItem(unsigned Attribute, StringRef Value, bool OverwriteExisting) { + if (AttributeItem *Item = getAttributeItem(Attribute)) { + if (!OverwriteExisting) { + return ; + } + Item->Type = AttributeType::Text; + Item->StringValue = std::string(Value); + return; + } + Contents.push_back({AttributeType::Text, Attribute, 0, std::string(Value)}); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/setAttributeItems.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/setAttributeItems.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fa5d986ed08a7aa3efff0db7d1b2e17d2bfe429a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/ELFStreamer/setAttributeItems.cpp @@ -0,0 +1,12 @@ +void setAttributeItems(unsigned Attribute, unsigned IntValue, StringRef StringValue, bool OverwriteExisting) { + if (AttributeItem *Item = getAttributeItem(Attribute)) { + if (!OverwriteExisting) { + return ; + } + Item->Type = AttributeType::NumericAndText; + Item->IntValue = IntValue; + Item->StringValue = std::string(StringValue); + return ; + } + Contents.push_back({AttributeType::NumericAndText, Attribute, IntValue, std::string(StringValue)}); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/FixupKind/enumFixups.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/FixupKind/enumFixups.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4754cd830f701834880839959a387397abc8d37a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/FixupKind/enumFixups.cpp @@ -0,0 +1,25 @@ +enum Fixups { + fixup_riscv_hi20 = FirstTargetFixupKind, + fixup_riscv_lo12_i, + fixup_riscv_lo12_s, + fixup_riscv_pcrel_hi20, + fixup_riscv_pcrel_lo12_i, + fixup_riscv_pcrel_lo12_s, + fixup_riscv_got_hi20, + fixup_riscv_tprel_hi20, + fixup_riscv_tprel_lo12_i, + fixup_riscv_tprel_lo12_s, + fixup_riscv_tprel_add, + fixup_riscv_tls_got_hi20, + fixup_riscv_tls_gd_hi20, + fixup_riscv_jal, + fixup_riscv_branch, + fixup_riscv_rvc_jump, + fixup_riscv_rvc_branch, + fixup_riscv_call, + fixup_riscv_call_plt, + fixup_riscv_relax, + fixup_riscv_align, + fixup_riscv_invalid, + NumTargetFixupKinds = fixup_riscv_invalid - FirstTargetFixupKind +}; diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/InstPrinter/InstPrinter.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/InstPrinter/InstPrinter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..71d998a21bbc237891bd1af9439f840ba481ed61 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/InstPrinter/InstPrinter.cpp @@ -0,0 +1,2 @@ +RISCVInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI) : MCInstPrinter(MAI, MII, MRI) { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/InstPrinter/applyTargetSpecificCLOption.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/InstPrinter/applyTargetSpecificCLOption.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c74c266403f121f6785e5bab3d396cffccc06305 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/InstPrinter/applyTargetSpecificCLOption.cpp @@ -0,0 +1,11 @@ +bool RISCVInstPrinter::applyTargetSpecificCLOption(StringRef Opt) { + if (Opt == "no-aliases") { + NoAliases = true; + return true; + } + if (Opt == "numeric") { + ArchRegNames = true; + return true; + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/InstPrinter/getRegisterName.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/InstPrinter/getRegisterName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..16127a97a65a5a76c80d613eb8cce8d76e67d59d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/InstPrinter/getRegisterName.cpp @@ -0,0 +1,3 @@ +const char *RISCVInstPrinter::getRegisterName(unsigned RegNo) { + return getRegisterName(RegNo, ArchRegNames ? RISCV::NoRegAltName : RISCV::ABIRegAltName); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/InstPrinter/printAtomicMemOp.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/InstPrinter/printAtomicMemOp.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3d1b3ccb7d8db5f73fbefacc28a689c8057e9ad7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/InstPrinter/printAtomicMemOp.cpp @@ -0,0 +1,7 @@ +void RISCVInstPrinter::printAtomicMemOp(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) { + const MCOperand &MO = MI->getOperand(OpNo); + assert(MO.isReg() && "printAtomicMemOp can only print register operands"); + O << "("; + printRegName(O, MO.getReg()); + O << ")"; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/InstPrinter/printBranchOperand.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/InstPrinter/printBranchOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a01d9b2e56167e27ab420b3b5ab9fd027d317f6f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/InstPrinter/printBranchOperand.cpp @@ -0,0 +1,16 @@ +void RISCVInstPrinter::printBranchOperand(const MCInst *MI, uint64_t Address, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) { + const MCOperand &MO = MI->getOperand(OpNo); + if (!MO.isImm()) { + return printOperand(MI, OpNo, STI, O); + } + if (PrintBranchImmAsAddress) { + uint64_t Target = Address + MO.getImm(); + if (!STI.hasFeature(RISCV::Feature64Bit)) { + Target &= 0xffffffff; + } + O << formatHex(Target); + } + else { + O << MO.getImm(); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/InstPrinter/printCSRSystemRegister.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/InstPrinter/printCSRSystemRegister.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3809af50492b7bd4de8f984928f1c4261af64686 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/InstPrinter/printCSRSystemRegister.cpp @@ -0,0 +1,10 @@ +void RISCVInstPrinter::printCSRSystemRegister(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) { + unsigned Imm = MI->getOperand(OpNo).getImm(); + auto SysReg = RISCVSysReg::lookupSysRegByEncoding(Imm); + if (SysReg && SysReg->haveRequiredFeatures(STI.getFeatureBits())) { + O << SysReg->Name; + } + else { + O << Imm; + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/InstPrinter/printFRMArg.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/InstPrinter/printFRMArg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6c645b1207ba1597386ae8a6d312aeefb5fea718 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/InstPrinter/printFRMArg.cpp @@ -0,0 +1,4 @@ +void RISCVInstPrinter::printFRMArg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) { + auto FRMArg = static_cast(MI->getOperand(OpNo).getImm()); + O << RISCVFPRndMode::roundingModeToString(FRMArg); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/InstPrinter/printFenceArg.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/InstPrinter/printFenceArg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7bb49dab7c797c58c549e93f140553048913667e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/InstPrinter/printFenceArg.cpp @@ -0,0 +1,19 @@ +void RISCVInstPrinter::printFenceArg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) { + unsigned FenceArg = MI->getOperand(OpNo).getImm(); + assert (((FenceArg >> 4) == 0) && "Invalid immediate in printFenceArg"); + if ((FenceArg & RISCVFenceField::I) != 0) { + O << 'i'; + } + if ((FenceArg & RISCVFenceField::O) != 0) { + O << 'o'; + } + if ((FenceArg & RISCVFenceField::R) != 0) { + O << 'r'; + } + if ((FenceArg & RISCVFenceField::W) != 0) { + O << 'w'; + } + if (FenceArg == 0) { + O << "unknown"; + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/InstPrinter/printInst.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/InstPrinter/printInst.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7fd912416d3c956ccf0b4e72deb8cb1e607606ff --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/InstPrinter/printInst.cpp @@ -0,0 +1,22 @@ +void RISCVInstPrinter::printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) { + bool Res = false; + const MCInst *NewMI = MI; + MCInst UncompressedMI; + if (!NoAliases) { + Res = uncompressInst(UncompressedMI, *MI, MRI, STI); + } + if (Res) { + NewMI = const_cast(&UncompressedMI); + } + if (NoAliases) { + printInstruction(NewMI, Address, STI, O); + printAnnotation(O, Annot); + return ; + } + if (!printAliasInstr(NewMI, Address, STI, O)) { + printInstruction(NewMI, Address, STI, O); + printAnnotation(O, Annot); + return ; + } + printAnnotation(O, Annot); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/InstPrinter/printOperand.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/InstPrinter/printOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7d0f0643720af5ad457f257e02853f99c0f67122 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/InstPrinter/printOperand.cpp @@ -0,0 +1,14 @@ +void RISCVInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O, const char *Modifier) { + assert((Modifier == 0 || Modifier[0] == 0) && "No modifiers supported"); + const MCOperand &MO = MI->getOperand(OpNo); + if (MO.isReg()) { + printRegName(O, MO.getReg()); + return; + } + if (MO.isImm()) { + O << MO.getImm(); + return; + } + assert(MO.isExpr() && "Unknown operand kind in printOperand"); + MO.getExpr()->print(O, &MAI); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/InstPrinter/printRegName.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/InstPrinter/printRegName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..44d46a100e8d5b198bbeca69ad0ebf8d85a67127 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/InstPrinter/printRegName.cpp @@ -0,0 +1,3 @@ +void RISCVInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { + OS << getRegisterName(RegNo); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/InstPrinter/printVMaskReg.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/InstPrinter/printVMaskReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0c27e28f489f40b2071578114af59538980a143b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/InstPrinter/printVMaskReg.cpp @@ -0,0 +1,10 @@ +void RISCVInstPrinter::printVMaskReg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) { + const MCOperand &MO = MI->getOperand(OpNo); + assert(MO.isReg() && "printVMaskReg can only print register operands"); + if (MO.getReg() == RISCV::NoRegister) { + return ; + } + O << ", "; + printRegName(O, MO.getReg()); + O << ".t"; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/InstPrinter/printVTypeI.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/InstPrinter/printVTypeI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..182d91094687c23adfa4a02dfafb94b892bd942d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/InstPrinter/printVTypeI.cpp @@ -0,0 +1,34 @@ +void RISCVInstPrinter::printVTypeI(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) { + unsigned Imm = MI->getOperand(OpNo).getImm(); + RISCVVSEW VSEW = getVSEW(VType); + RISCVVLMUL VLMUL = getVLMUL(VType); + unsigned Sew = 1 << (static_cast(VSEW) + 3); + OS << "e" << Sew; + switch (VLMUL) { + case RISCVVLMUL::LMUL_RESERVED: + llvm_unreachable("Unexpected LMUL value!"); + case RISCVVLMUL::LMUL_1: + case RISCVVLMUL::LMUL_2: + case RISCVVLMUL::LMUL_4: + case RISCVVLMUL::LMUL_8: { + unsigned LMul = 1 << static_cast(VLMUL); + OS << ",m" << LMul; + break; + } + case RISCVVLMUL::LMUL_F2: + case RISCVVLMUL::LMUL_F4: + case RISCVVLMUL::LMUL_F8: { + unsigned LMul = 1 << (8 - static_cast(VLMUL)); + OS << ",mf" << LMul; + break; + } + } + if (isTailAgnostic(VType)) + OS << ",ta"; + else + OS << ",tu"; + if (isMaskAgnostic(VType)) + OS << ",ma"; + else + OS << ",mu"; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCCodeEmitter/MCCodeEmitter.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCCodeEmitter/MCCodeEmitter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..79d3f43f91b2f9cb6eacf14c4504d0058646f84e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCCodeEmitter/MCCodeEmitter.cpp @@ -0,0 +1,2 @@ +RISCVMCCodeEmitter(MCContext &ctx, MCInstrInfo const &MCII) : Ctx(ctx), MCII(MCII) { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCCodeEmitter/createMCCodeEmitter.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCCodeEmitter/createMCCodeEmitter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a1af400e24ee65974cc8afec327f0489742cc57d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCCodeEmitter/createMCCodeEmitter.cpp @@ -0,0 +1,3 @@ +MCCodeEmitter *llvm::createRISCVMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx) { + return new RISCVMCCodeEmitter(Ctx, MCII); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCCodeEmitter/encodeInstruction.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCCodeEmitter/encodeInstruction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6fd2c7d7f19b595b6dca627db0e856d5448229d2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCCodeEmitter/encodeInstruction.cpp @@ -0,0 +1,112 @@ +void RISCVMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const { + verifyInstructionPredicates(MI, computeAvailableFeatures(STI.getFeatureBits())); + const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); + unsigned Size = Desc.getSize(); + if (MI.getOpcode() == RISCV::PseudoCALLReg) { + MCInst TmpInst; + MCOperand Func; + MCRegister Ra; + uint32_t Binary; + Func = MI.getOperand(1); + Ra = MI.getOperand(0).getReg(); + assert(Func.isExpr() && "Expected expression"); + const MCExpr *CallExpr = Func.getExpr(); + TmpInst = MCInstBuilder(RISCV::AUIPC).addReg(Ra).addOperand(MCOperand::createExpr(CallExpr)); + Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); + support::endian::write(OS, Binary, support::little); + TmpInst = MCInstBuilder(RISCV::JALR).addReg(Ra).addReg(Ra).addImm(0); + Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); + support::endian::write(OS, Binary, support::little); + MCNumEmitted = MCNumEmitted + 2; + return ; + } + if(MI.getOpcode() == RISCV::PseudoCALL) { + MCInst TmpInst; + MCOperand Func; + MCRegister Ra; + uint32_t Binary; + Func = MI.getOperand(1); + Ra = MI.getOperand(0).getReg(); + assert(Func.isExpr() && "Expected expression"); + const MCExpr *CallExpr = Func.getExpr(); + TmpInst = MCInstBuilder(RISCV::AUIPC).addReg(Ra).addOperand(MCOperand::createExpr(CallExpr)); + Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); + support::endian::write(OS, Binary, support::little); + TmpInst = MCInstBuilder(RISCV::JALR).addReg(Ra).addReg(Ra).addImm(0); + Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); + support::endian::write(OS, Binary, support::little); + MCNumEmitted = MCNumEmitted + 2; + return ; + } + if(MI.getOpcode() == RISCV::PseudoTAIL) { + MCInst TmpInst; + MCOperand Func; + MCRegister Ra; + uint32_t Binary; + Func = MI.getOperand(1); + Ra = MI.getOperand(0).getReg(); + assert(Func.isExpr() && "Expected expression"); + const MCExpr *CallExpr = Func.getExpr(); + TmpInst = MCInstBuilder(RISCV::AUIPC).addReg(Ra).addOperand(MCOperand::createExpr(CallExpr)); + Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); + support::endian::write(OS, Binary, support::little); + TmpInst = MCInstBuilder(RISCV::JALR).addReg(Ra).addReg(Ra).addImm(0); + Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); + support::endian::write(OS, Binary, support::little); + MCNumEmitted = MCNumEmitted + 2; + return ; + } + if(MI.getOpcode() == RISCV::PseudoJump) { + MCInst TmpInst; + MCOperand Func; + MCRegister Ra; + uint32_t Binary; + Func = MI.getOperand(1); + Ra = MI.getOperand(0).getReg(); + assert(Func.isExpr() && "Expected expression"); + const MCExpr *CallExpr = Func.getExpr(); + TmpInst = MCInstBuilder(RISCV::AUIPC).addReg(Ra).addOperand(MCOperand::createExpr(CallExpr)); + Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); + support::endian::write(OS, Binary, support::little); + TmpInst = MCInstBuilder(RISCV::JALR).addReg(Ra).addReg(Ra).addImm(0); + Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); + support::endian::write(OS, Binary, support::little); + MCNumEmitted = MCNumEmitted + 2; + return ; + } + if (MI.getOpcode() == RISCV::PseudoAddTPRel) { + MCOperand DestReg = MI.getOperand(0); + MCOperand SrcReg = MI.getOperand(1); + MCOperand TPReg = MI.getOperand(2); + assert(TPReg.isReg() && TPReg.getReg() == RISCV::X4 && "Expected thread pointer as second input to TP-relative add"); + MCOperand SrcSymbol = MI.getOperand(3); + assert(SrcSymbol.isExpr() && "Expected expression as third input to TP-relative add"); + const RISCVMCExpr *Expr = dyn_cast(SrcSymbol.getExpr()); + assert(Expr && Expr->getKind() == RISCVMCExpr::VK_RISCV_TPREL_ADD && "Expected tprel_add relocation on TP-relative symbol"); + Fixups.push_back(MCFixup::create(0, Expr, MCFixupKind(RISCV::fixup_riscv_tprel_add), MI.getLoc())); + if (STI.getFeatureBits()[RISCV::FeatureRelax]) { + const MCConstantExpr *Dummy = MCConstantExpr::create(0, Ctx); + Fixups.push_back(MCFixup::create(0, Dummy, MCFixupKind(RISCV::fixup_riscv_relax), MI.getLoc())); + } + MCInst TmpInst = MCInstBuilder(RISCV::ADD).addOperand(DestReg).addOperand(SrcReg).addOperand(TPReg); + uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); + support::endian::write(OS, Binary, support::little); + MCNumEmitted += 1; + return; + } + if (Size == 2) { + uint16_t Bits; + Bits = getBinaryCodeForInstr(MI, Fixups, STI); + support::endian::write(OS, Bits,support::little); + MCNumEmitted = MCNumEmitted + 1; + return ; + } + if (Size == 4) { + uint32_t Bits; + Bits = getBinaryCodeForInstr(MI, Fixups, STI); + support::endian::write(OS, Bits,support::little); + MCNumEmitted = MCNumEmitted + 1; + return ; + } + ++MCNumEmitted; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCCodeEmitter/getImmOpValue.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCCodeEmitter/getImmOpValue.cpp new file mode 100644 index 0000000000000000000000000000000000000000..17b6c231cb7ae743d9900d60f15bb39649137428 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCCodeEmitter/getImmOpValue.cpp @@ -0,0 +1,104 @@ +unsigned RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const { + bool EnableRelax = STI.getFeatureBits()[RISCV::FeatureRelax]; + const MCOperand &MO = MI.getOperand(OpNo); + MCInstrDesc const &Desc = MCII.get(MI.getOpcode()); + unsigned MIFrm = Desc.TSFlags & RISCVII::InstFormatMask; + if (MO.isImm()) { + return MO.getImm(); + } + assert(MO.isExpr() && "getImmOpValue expects only expressions or immediates"); + const MCExpr *Expr = MO.getExpr(); + MCExpr::ExprKind Kind = Expr->getKind(); + RISCV::Fixups FixupKind = RISCV::fixup_riscv_invalid; + bool RelaxCandidate = false; + if (Kind == MCExpr::Target) { + const RISCVMCExpr *RVExpr = cast(Expr); + switch (RVExpr->getKind()) { + case RISCVMCExpr::VK_RISCV_None: + case RISCVMCExpr::VK_RISCV_Invalid: + case RISCVMCExpr::VK_RISCV_32_PCREL: + llvm_unreachable("Unhandled fixup kind!"); + case RISCVMCExpr::VK_RISCV_TPREL_ADD: + llvm_unreachable("VK_RISCV_TPREL_ADD should not represent an instruction operand"); + case RISCVMCExpr::VK_RISCV_LO: + if (MIFrm == RISCVII::InstFormatI) + FixupKind = RISCV::fixup_riscv_lo12_i; + else if (MIFrm == RISCVII::InstFormatS) + FixupKind = RISCV::fixup_riscv_lo12_s; + else + llvm_unreachable("VK_RISCV_LO used with unexpected instruction format"); + RelaxCandidate = true; + break; + case RISCVMCExpr::VK_RISCV_HI: + FixupKind = RISCV::fixup_riscv_hi20; + RelaxCandidate = true; + break; + case RISCVMCExpr::VK_RISCV_PCREL_LO: + if (MIFrm == RISCVII::InstFormatI) + FixupKind = RISCV::fixup_riscv_pcrel_lo12_i; + else if (MIFrm == RISCVII::InstFormatS) + FixupKind = RISCV::fixup_riscv_pcrel_lo12_s; + else + llvm_unreachable("VK_RISCV_PCREL_LO used with unexpected instruction format"); + RelaxCandidate = true; + break; + case RISCVMCExpr::VK_RISCV_PCREL_HI: + FixupKind = RISCV::fixup_riscv_pcrel_hi20; + RelaxCandidate = true; + break; + case RISCVMCExpr::VK_RISCV_GOT_HI: + FixupKind = RISCV::fixup_riscv_got_hi20; + break; + case RISCVMCExpr::VK_RISCV_TPREL_LO: + if (MIFrm == RISCVII::InstFormatI) + FixupKind = RISCV::fixup_riscv_tprel_lo12_i; + else if (MIFrm == RISCVII::InstFormatS) + FixupKind = RISCV::fixup_riscv_tprel_lo12_s; + else + llvm_unreachable("VK_RISCV_TPREL_LO used with unexpected instruction format"); + RelaxCandidate = true; + break; + case RISCVMCExpr::VK_RISCV_TPREL_HI: + FixupKind = RISCV::fixup_riscv_tprel_hi20; + RelaxCandidate = true; + break; + case RISCVMCExpr::VK_RISCV_TLS_GOT_HI: + FixupKind = RISCV::fixup_riscv_tls_got_hi20; + break; + case RISCVMCExpr::VK_RISCV_TLS_GD_HI: + FixupKind = RISCV::fixup_riscv_tls_gd_hi20; + break; + case RISCVMCExpr::VK_RISCV_CALL: + FixupKind = RISCV::fixup_riscv_call; + RelaxCandidate = true; + break; + case RISCVMCExpr::VK_RISCV_CALL_PLT: + FixupKind = RISCV::fixup_riscv_call_plt; + RelaxCandidate = true; + break; + } + } + else if (Kind == MCExpr::SymbolRef && cast(Expr)->getKind() == MCSymbolRefExpr::VK_None) { + if (Desc.getOpcode() == RISCV::JAL) { + FixupKind = RISCV::fixup_riscv_jal; + } + else if (MIFrm == RISCVII::InstFormatB) { + FixupKind = RISCV::fixup_riscv_branch; + } + else if (MIFrm == RISCVII::InstFormatCJ) { + FixupKind = RISCV::fixup_riscv_rvc_jump; + } + else if (MIFrm == RISCVII::InstFormatCB) { + FixupKind = RISCV::fixup_riscv_rvc_branch; + } + } + assert(FixupKind != RISCV::fixup_riscv_invalid && "Unhandled expression!"); + Fixups.push_back(MCFixup::create(0, Expr, MCFixupKind(FixupKind), MI.getLoc())); + ++MCNumFixups; + if (EnableRelax && RelaxCandidate) { + const MCConstantExpr *Dummy = MCConstantExpr::create(0, Ctx); + Fixups.push_back(MCFixup::create(0, Dummy, MCFixupKind(RISCV::fixup_riscv_relax), MI.getLoc())); + ++MCNumFixups; + } + return 0; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCCodeEmitter/getImmOpValueAsr1.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCCodeEmitter/getImmOpValueAsr1.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0608bfeacb78631d4bd74acd7635d1eddcd1e943 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCCodeEmitter/getImmOpValueAsr1.cpp @@ -0,0 +1,9 @@ +unsigned RISCVMCCodeEmitter::getImmOpValueAsr1(const MCInst &MI, unsigned OpNo, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const { + const MCOperand &MO = MI.getOperand(OpNo); + if (MO.isImm()) { + unsigned Res = MO.getImm(); + assert((Res & 1) == 0 && "LSB is non-zero"); + return Res >> 1; + } + return getImmOpValue(MI, OpNo, Fixups, STI); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCCodeEmitter/getMachineOpValue.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCCodeEmitter/getMachineOpValue.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4c2edf1c37a06d5c3ca2919dc5cbb12fa344db6f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCCodeEmitter/getMachineOpValue.cpp @@ -0,0 +1,10 @@ +unsigned RISCVMCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const { + if (MO.isReg()) { + return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()); + } + if (MO.isImm()) { + return static_cast(MO.getImm()); + } + llvm_unreachable("Unhandled expression!"); + return 0; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCCodeEmitter/getVMaskReg.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCCodeEmitter/getVMaskReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cb6c71839d4ba3ae26572009f586539be7e0d390 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCCodeEmitter/getVMaskReg.cpp @@ -0,0 +1,12 @@ +unsigned RISCVMCCodeEmitter::getVMaskReg(const MCInst &MI, unsigned OpNo, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const { + MCOperand MO = MI.getOperand(OpNo); + assert(MO.isReg() && "Expected a register."); + switch (MO.getReg()) { + case RISCV::V0: + return 0; + case RISCV::NoRegister: + return 1; + default: + llvm_unreachable("Invalid mask register."); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCCodeEmitter/~MCCodeEmitter.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCCodeEmitter/~MCCodeEmitter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..59ae51d078977c3022b0a7003a3a5b6cc6cfccd0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCCodeEmitter/~MCCodeEmitter.cpp @@ -0,0 +1,2 @@ +~RISCVMCCodeEmitter() override { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCExpr/MCExpr.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCExpr/MCExpr.cpp new file mode 100644 index 0000000000000000000000000000000000000000..da4f6b8260348d1f5ae72c777c76f77b19b1c56b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCExpr/MCExpr.cpp @@ -0,0 +1,2 @@ +explicit RISCVMCExpr(const MCExpr *Expr, VariantKind Kind) : Expr(Expr), Kind(Kind) { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCExpr/classof1.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCExpr/classof1.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c18a16e9b79dfbe76cb62202c2b20dac602f027b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCExpr/classof1.cpp @@ -0,0 +1,3 @@ +static bool classof(const MCExpr *E) { + return E->getKind() == MCExpr::Target; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCExpr/classof2.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCExpr/classof2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e3b49b8ebace06424f104635e86ad479c4c2d122 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCExpr/classof2.cpp @@ -0,0 +1,3 @@ +static bool classof(const RISCVMCExpr *) { + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCExpr/create.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCExpr/create.cpp new file mode 100644 index 0000000000000000000000000000000000000000..39113cf36ed270b0c6d69b5360588428237b2475 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCExpr/create.cpp @@ -0,0 +1,3 @@ +const RISCVMCExpr *RISCVMCExpr::create(const MCExpr *Expr, VariantKind Kind, MCContext &Ctx) { + return new (Ctx) RISCVMCExpr(Expr, Kind); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCExpr/enumVariantKind.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCExpr/enumVariantKind.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9d3ea350c3d62324aeaad87cabbbfd85c3ea4588 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCExpr/enumVariantKind.cpp @@ -0,0 +1,17 @@ +enum VariantKind { + VK_RISCV_None, + VK_RISCV_LO, + VK_RISCV_HI, + VK_RISCV_PCREL_LO, + VK_RISCV_PCREL_HI, + VK_RISCV_GOT_HI, + VK_RISCV_TPREL_LO, + VK_RISCV_TPREL_HI, + VK_RISCV_TPREL_ADD, + VK_RISCV_TLS_GOT_HI, + VK_RISCV_TLS_GD_HI, + VK_RISCV_CALL, + VK_RISCV_CALL_PLT, + VK_RISCV_32_PCREL, + VK_RISCV_Invalid, + }; diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCExpr/evaluateAsConstant.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCExpr/evaluateAsConstant.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8a00985bb9a0e45063ef40c9356a6d51ba318393 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCExpr/evaluateAsConstant.cpp @@ -0,0 +1,14 @@ +bool RISCVMCExpr::evaluateAsConstant(int64_t &Res) const { + MCValue Value; + if (Kind == VK_RISCV_PCREL_HI || Kind == VK_RISCV_PCREL_LO || Kind == VK_RISCV_GOT_HI || Kind == VK_RISCV_TPREL_HI || Kind == VK_RISCV_TPREL_LO || Kind == VK_RISCV_TPREL_ADD || Kind == VK_RISCV_TLS_GOT_HI || Kind == VK_RISCV_TLS_GD_HI || Kind == VK_RISCV_CALL || Kind == VK_RISCV_CALL_PLT) { + return false; + } + if (!getSubExpr()->evaluateAsRelocatable(Value, nullptr, nullptr)) { + return false; + } + if (!Value.isAbsolute()) { + return false; + } + Res = evaluateAsInt64(Value.getConstant()); + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCExpr/evaluateAsInt64.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCExpr/evaluateAsInt64.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2d2ca349a0e1f92adb5fcbf38353c231ec73066f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCExpr/evaluateAsInt64.cpp @@ -0,0 +1,10 @@ +int64_t RISCVMCExpr::evaluateAsInt64(int64_t Value) const { + switch (Kind) { + case VK_RISCV_LO: + return SignExtend64<12>(Value); + case VK_RISCV_HI: + return ((Value + 0x800) >> 12) & 0xfffff; + default: + llvm_unreachable("Invalid kind"); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCExpr/evaluateAsRelocatableImpl.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCExpr/evaluateAsRelocatableImpl.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6e71bde5f7592f5ef4591791bcb86f58dc40765f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCExpr/evaluateAsRelocatableImpl.cpp @@ -0,0 +1,23 @@ +bool RISCVMCExpr::evaluateAsRelocatableImpl(MCValue &Res, const MCAsmLayout *Layout, const MCFixup *Fixup) const { + if (!getSubExpr()->evaluateAsRelocatable(Res, Layout, Fixup)){ + return false; + } + if (Res.getSymA() && Res.getSymB()) { + switch (getKind()) { + default: + return true; + case VK_RISCV_LO: + case VK_RISCV_HI: + case VK_RISCV_PCREL_LO: + case VK_RISCV_PCREL_HI: + case VK_RISCV_GOT_HI: + case VK_RISCV_TPREL_LO: + case VK_RISCV_TPREL_HI: + case VK_RISCV_TPREL_ADD: + case VK_RISCV_TLS_GOT_HI: + case VK_RISCV_TLS_GD_HI: + return false; + } + } + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCExpr/findAssociatedFragment.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCExpr/findAssociatedFragment.cpp new file mode 100644 index 0000000000000000000000000000000000000000..60f17e85d923bec938d38573f38737261c999694 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCExpr/findAssociatedFragment.cpp @@ -0,0 +1,3 @@ +MCFragment *findAssociatedFragment() const override { + return getSubExpr()->findAssociatedFragment(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCExpr/fixELFSymbolsInTLSFixups.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCExpr/fixELFSymbolsInTLSFixups.cpp new file mode 100644 index 0000000000000000000000000000000000000000..89e8ce3b031ea65a056d84127e579bd2815264c2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCExpr/fixELFSymbolsInTLSFixups.cpp @@ -0,0 +1,11 @@ +void RISCVMCExpr::fixELFSymbolsInTLSFixups(MCAssembler &Asm) const { + switch (getKind()) { + default: + return; + case VK_RISCV_TPREL_HI: + case VK_RISCV_TLS_GOT_HI: + case VK_RISCV_TLS_GD_HI: + break; + } + fixELFSymbolsInTLSFixupsImpl(getSubExpr(), Asm); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCExpr/fixELFSymbolsInTLSFixupsImpl.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCExpr/fixELFSymbolsInTLSFixupsImpl.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9380184f705c3b8053f961d7f265d676d373e6c4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCExpr/fixELFSymbolsInTLSFixupsImpl.cpp @@ -0,0 +1,23 @@ +static void fixELFSymbolsInTLSFixupsImpl(const MCExpr *Expr, MCAssembler &Asm) { + switch (Expr->getKind()) { + case MCExpr::Target: + llvm_unreachable("Can't handle nested target expression"); + break; + case MCExpr::Constant: + break; + case MCExpr::Binary: { + const MCBinaryExpr *BE = cast(Expr); + fixELFSymbolsInTLSFixupsImpl(BE->getLHS(), Asm); + fixELFSymbolsInTLSFixupsImpl(BE->getRHS(), Asm); + break; + } + case MCExpr::SymbolRef: { + const MCSymbolRefExpr &SymRef = *cast(Expr); + cast(SymRef.getSymbol()).setType(ELF::STT_TLS); + break; + } + case MCExpr::Unary: + fixELFSymbolsInTLSFixupsImpl(cast(Expr)->getSubExpr(), Asm); + break; + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCExpr/getKind.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCExpr/getKind.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d8873d03d56532262e2e464651e7ed13ac5736a6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCExpr/getKind.cpp @@ -0,0 +1,3 @@ +VariantKind getKind() const { + return Kind; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCExpr/getPCRelHiFixup.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCExpr/getPCRelHiFixup.cpp new file mode 100644 index 0000000000000000000000000000000000000000..89987b297a722bf3d6b3be128c1836a8216b5cb9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCExpr/getPCRelHiFixup.cpp @@ -0,0 +1,41 @@ +const MCFixup *RISCVMCExpr::getPCRelHiFixup(const MCFragment **DFOut) const { + MCValue AUIPCLoc; + if (!getSubExpr()->evaluateAsRelocatable(AUIPCLoc, nullptr, nullptr)) { + return nullptr; + } + const MCSymbolRefExpr *AUIPCSRE = AUIPCLoc.getSymA(); + if (!AUIPCSRE) { + return nullptr; + } + const MCSymbol *AUIPCSymbol = &AUIPCSRE->getSymbol(); + const auto *DF = dyn_cast_or_null(AUIPCSymbol->getFragment()); + if (!DF) { + return nullptr; + } + uint64_t Offset = AUIPCSymbol->getOffset(); + if (DF->getContents().size() == Offset) { + DF = dyn_cast_or_null(DF->getNextNode()); + if (!DF) { + return nullptr; + } + Offset = 0; + } + for (const MCFixup &F : DF->getFixups()) { + if (F.getOffset() != Offset) { + continue; + } + switch ((unsigned)F.getKind()) { + default: + continue; + case RISCV::fixup_riscv_got_hi20: + case RISCV::fixup_riscv_tls_got_hi20: + case RISCV::fixup_riscv_tls_gd_hi20: + case RISCV::fixup_riscv_pcrel_hi20: + if (DFOut) { + *DFOut = DF; + } + return &F; + } + } + return nullptr; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCExpr/getSubExpr.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCExpr/getSubExpr.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0938efd3638913ba4ab06b155113748fbcf3ba7b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCExpr/getSubExpr.cpp @@ -0,0 +1,3 @@ +const MCExpr *getSubExpr() const { + return Expr; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCExpr/getVariantKindForName.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCExpr/getVariantKindForName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3ceea7690a66c81e8392c3762eeb6bdc159adfb2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCExpr/getVariantKindForName.cpp @@ -0,0 +1,33 @@ +RISCVMCExpr::VariantKind RISCVMCExpr::getVariantKindForName(StringRef name) { + if (name == "lo") { + return RISCVMCExpr::VK_RISCV_LO; + } + if (name == "hi") { + return RISCVMCExpr::VK_RISCV_HI; + } + if (name == "pcrel_lo") { + return RISCVMCExpr::VK_RISCV_PCREL_LO; + } + if (name == "pcrel_hi") { + return RISCVMCExpr::VK_RISCV_PCREL_HI; + } + if (name == "got_pcrel_hi") { + return RISCVMCExpr::VK_RISCV_GOT_HI; + } + if (name == "tprel_lo") { + return RISCVMCExpr::VK_RISCV_TPREL_LO; + } + if (name == "tprel_hi") { + return RISCVMCExpr::VK_RISCV_TPREL_HI; + } + if (name == "tprel_add") { + return RISCVMCExpr::VK_RISCV_TPREL_ADD; + } + if (name == "tls_ie_pcrel_hi") { + return RISCVMCExpr::VK_RISCV_TLS_GOT_HI; + } + if (name == "tls_gd_pcrel_hi") { + return RISCVMCExpr::VK_RISCV_TLS_GD_HI; + } + return RISCVMCExpr::VK_RISCV_Invalid; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCExpr/getVariantKindName.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCExpr/getVariantKindName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9a08480b3ccbf2b76c97f73a0b86881ba90264eb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCExpr/getVariantKindName.cpp @@ -0,0 +1,26 @@ +StringRef RISCVMCExpr::getVariantKindName(VariantKind Kind) { + switch (Kind) { + case VK_RISCV_LO: + return "lo"; + case VK_RISCV_HI: + return "hi"; + case VK_RISCV_PCREL_LO: + return "pcrel_lo"; + case VK_RISCV_PCREL_HI: + return "pcrel_hi"; + case VK_RISCV_GOT_HI: + return "got_pcrel_hi"; + case VK_RISCV_TPREL_LO: + return "tprel_lo"; + case VK_RISCV_TPREL_HI: + return "tprel_hi"; + case VK_RISCV_TPREL_ADD: + return "tprel_add"; + case VK_RISCV_TLS_GOT_HI: + return "tls_ie_pcrel_hi"; + case VK_RISCV_TLS_GD_HI: + return "tls_gd_pcrel_hi"; + default: + llvm_unreachable("Invalid ELF symbol kind"); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCExpr/printImpl.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCExpr/printImpl.cpp new file mode 100644 index 0000000000000000000000000000000000000000..55d93d4d19a85acb53eace95c71cbd1dc389bcca --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCExpr/printImpl.cpp @@ -0,0 +1,82 @@ +void RISCVMCExpr::printImpl(raw_ostream &OS, const MCAsmInfo *MAI) const { + VariantKind Kind = getKind(); + if (Kind == RISCVMCExpr::VK_RISCV_PCREL_LO) { + OS << "%pcrel_lo("; + Expr->print(OS, MAI); + OS << ")"; + return ; + } + if (Kind == RISCVMCExpr::VK_RISCV_PCREL_HI) { + OS << "%pcrel_hi("; + Expr->print(OS, MAI); + OS << ")"; + return ; + } + if (Kind == RISCVMCExpr::VK_RISCV_TPREL_LO) { + OS << "%tprel_lo("; + Expr->print(OS, MAI); + OS << ")"; + return ; + } + if (Kind == RISCVMCExpr::VK_RISCV_TPREL_HI) { + OS << "%tprel_hi("; + Expr->print(OS, MAI); + OS << ")"; + return ; + } + if (Kind == RISCVMCExpr::VK_RISCV_TPREL_ADD) { + OS << "%tprel_add("; + Expr->print(OS, MAI); + OS << ")"; + return ; + } + if (Kind == RISCVMCExpr::VK_RISCV_LO) { + OS << "%lo("; + Expr->print(OS, MAI); + OS << ")"; + return ; + } + if (Kind == RISCVMCExpr::VK_RISCV_HI) { + OS << "%hi("; + Expr->print(OS, MAI); + OS << ")"; + return ; + } + if (Kind == RISCVMCExpr::VK_RISCV_GOT_HI) { + OS << "%got_pcrel_hi("; + Expr->print(OS, MAI); + OS << ")"; + return ; + } + if (Kind == RISCVMCExpr::VK_RISCV_TLS_GOT_HI) { + OS << "%tls_ie_pcrel_hi("; + Expr->print(OS, MAI); + OS << ")"; + return ; + } + if (Kind == RISCVMCExpr::VK_RISCV_TLS_GD_HI) { + OS << "%tls_gd_pcrel_hi("; + Expr->print(OS, MAI); + OS << ")"; + return ; + } + if (Kind == RISCVMCExpr::VK_RISCV_CALL_PLT) { + OS << ""; + Expr->print(OS, MAI); + OS << "@plt"; + return ; + } + if (Kind == RISCVMCExpr::VK_RISCV_CALL) { + OS << ""; + Expr->print(OS, MAI); + OS << ""; + return ; + } + if (Kind == RISCVMCExpr::VK_RISCV_None) { + OS << ""; + Expr->print(OS, MAI); + OS << ""; + return ; + } + llvm_unreachable("Invalid ELF symbol kind"); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCExpr/visitUsedExpr.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCExpr/visitUsedExpr.cpp new file mode 100644 index 0000000000000000000000000000000000000000..35e420112aded4140f320dbc4ad4ac870d3ee31a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCExpr/visitUsedExpr.cpp @@ -0,0 +1,3 @@ +void RISCVMCExpr::visitUsedExpr(MCStreamer &Streamer) const { + Streamer.visitUsedExpr(*getSubExpr()); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCTargetDesc/InstrAnalysis.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCTargetDesc/InstrAnalysis.cpp new file mode 100644 index 0000000000000000000000000000000000000000..451277e94556a0608d71ebc2c76e620e59e0ec99 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCTargetDesc/InstrAnalysis.cpp @@ -0,0 +1,2 @@ +explicit RISCVMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCTargetDesc/LLVMInitializeTargetMC.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCTargetDesc/LLVMInitializeTargetMC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..32d2fe18d6bb48ee672756467a7ed995da2ae810 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCTargetDesc/LLVMInitializeTargetMC.cpp @@ -0,0 +1,15 @@ +extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTargetMC() { + for (Target *T : {&getTheRISCV32Target(), &getTheRISCV64Target()}) { + TargetRegistry::RegisterMCAsmInfo(*T, createRISCVMCAsmInfo); + TargetRegistry::RegisterMCInstrInfo(*T, createRISCVMCInstrInfo); + TargetRegistry::RegisterMCRegInfo(*T, createRISCVMCRegisterInfo); + TargetRegistry::RegisterMCAsmBackend(*T, createRISCVAsmBackend); + TargetRegistry::RegisterMCCodeEmitter(*T, createRISCVMCCodeEmitter); + TargetRegistry::RegisterMCInstPrinter(*T, createRISCVMCInstPrinter); + TargetRegistry::RegisterMCSubtargetInfo(*T, createRISCVMCSubtargetInfo); + TargetRegistry::RegisterObjectTargetStreamer(*T, createRISCVObjectTargetStreamer); + TargetRegistry::RegisterMCInstrAnalysis(*T, createRISCVInstrAnalysis); + TargetRegistry::RegisterAsmTargetStreamer(*T, createRISCVAsmTargetStreamer); + TargetRegistry::RegisterNullTargetStreamer(*T, createRISCVNullTargetStreamer); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCTargetDesc/createAsmTargetStreamer.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCTargetDesc/createAsmTargetStreamer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..383b52ff72a10ac127ceb76173b77049aa5f0fd9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCTargetDesc/createAsmTargetStreamer.cpp @@ -0,0 +1,3 @@ +static MCTargetStreamer *createRISCVAsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint, bool isVerboseAsm) { + return new RISCVTargetAsmStreamer(S, OS); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCTargetDesc/createInstrAnalysis.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCTargetDesc/createInstrAnalysis.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5b45661b6fa3382d3f641c2fe3bb34f05970d975 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCTargetDesc/createInstrAnalysis.cpp @@ -0,0 +1,3 @@ +static MCInstrAnalysis *createRISCVInstrAnalysis(const MCInstrInfo *Info) { + return new RISCVMCInstrAnalysis(Info); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCTargetDesc/createMCAsmInfo.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCTargetDesc/createMCAsmInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c4cffda02c27994572bf42f788d40d04d2e73e7d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCTargetDesc/createMCAsmInfo.cpp @@ -0,0 +1,7 @@ +static MCAsmInfo *createRISCVMCAsmInfo(const MCRegisterInfo &MRI, const Triple &TT, const MCTargetOptions &Options) { + MCAsmInfo *MAI = new RISCVMCAsmInfo(TT); + MCRegister SP = MRI.getDwarfRegNum(RISCV::X2, true); + MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, SP, 0); + MAI->addInitialFrameState(Inst); + return MAI; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCTargetDesc/createMCInstPrinter.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCTargetDesc/createMCInstPrinter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7a6f660619bed0d38c739e2e0da3274e6d81b2a0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCTargetDesc/createMCInstPrinter.cpp @@ -0,0 +1,3 @@ +static MCInstPrinter *createRISCVMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI) { + return new RISCVInstPrinter(MAI, MII, MRI); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCTargetDesc/createMCInstrInfo.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCTargetDesc/createMCInstrInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..758df40aa015a0c161f506e8e7ea1cad2d8bcc8a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCTargetDesc/createMCInstrInfo.cpp @@ -0,0 +1,5 @@ +static MCInstrInfo *createRISCVMCInstrInfo() { + MCInstrInfo *X = new MCInstrInfo(); + InitRISCVMCInstrInfo(X); + return X; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCTargetDesc/createMCRegisterInfo.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCTargetDesc/createMCRegisterInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bb7c34dd1c8354b6b0fa67e4f7244d55c1ddc0f7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCTargetDesc/createMCRegisterInfo.cpp @@ -0,0 +1,5 @@ +static MCRegisterInfo *createRISCVMCRegisterInfo(const Triple &TT) { + MCRegisterInfo *X = new MCRegisterInfo(); + InitRISCVMCRegisterInfo(X, RISCV::X1); + return X; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCTargetDesc/createMCSubtargetInfo.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCTargetDesc/createMCSubtargetInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..78ee741005540e6c3e698640daefd523ceecfb94 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCTargetDesc/createMCSubtargetInfo.cpp @@ -0,0 +1,7 @@ +static MCSubtargetInfo *createRISCVMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { + std::string CPUName = std::string(CPU); + if (CPUName.empty()) { + CPUName = TT.isArch64Bit() ? "generic-rv64" : "generic-rv32"; + } + return createRISCVMCSubtargetInfoImpl(TT, CPUName, CPUName, FS); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCTargetDesc/createNullTargetStreamer.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCTargetDesc/createNullTargetStreamer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1a625f2d3b010f64ddbcf02b017f0f07c7f52e3a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCTargetDesc/createNullTargetStreamer.cpp @@ -0,0 +1,3 @@ +static MCTargetStreamer *createRISCVNullTargetStreamer(MCStreamer &S) { + return new RISCVTargetStreamer(S); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCTargetDesc/createObjectTargetStreamer.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCTargetDesc/createObjectTargetStreamer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1e4eba726c087cde28f6692f50ef5398beba9c98 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCTargetDesc/createObjectTargetStreamer.cpp @@ -0,0 +1,7 @@ +static MCTargetStreamer *createRISCVObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) { + const Triple &TT = STI.getTargetTriple(); + if (TT.isOSBinFormatELF()) { + return new RISCVTargetELFStreamer(S, STI); + } + return new RISCVTargetELFStreamer(S, STI); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCTargetDesc/evaluateBranch.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCTargetDesc/evaluateBranch.cpp new file mode 100644 index 0000000000000000000000000000000000000000..eeba9579fc9ad3442ad8d10ee702dfcd667da54b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MCTargetDesc/evaluateBranch.cpp @@ -0,0 +1,47 @@ +bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size, uint64_t &Target) const { + if (Inst.getOpcode() == RISCV::BEQ) { + Target = Addr + Inst.getOperand(2).getImm(); + return true; + } + if (Inst.getOpcode() == RISCV::BNE) { + Target = Addr + Inst.getOperand(2).getImm(); + return true; + } + if (Inst.getOpcode() == RISCV::BLT) { + Target = Addr + Inst.getOperand(2).getImm(); + return true; + } + if (Inst.getOpcode() == RISCV::BGE) { + Target = Addr + Inst.getOperand(2).getImm(); + return true; + } + if (Inst.getOpcode() == RISCV::BLTU) { + Target = Addr + Inst.getOperand(2).getImm(); + return true; + } + if (Inst.getOpcode() == RISCV::BGEU) { + Target = Addr + Inst.getOperand(2).getImm(); + return true; + } + if (Inst.getOpcode() == RISCV::C_BEQZ) { + Target = Addr + Inst.getOperand(1).getImm(); + return true; + } + if (Inst.getOpcode() == RISCV::C_BNEZ) { + Target = Addr + Inst.getOperand(1).getImm(); + return true; + } + if (Inst.getOpcode() == RISCV::JAL) { + Target = Addr + Inst.getOperand(1).getImm(); + return true; + } + if (Inst.getOpcode() == RISCV::C_JAL) { + Target = Addr + Inst.getOperand(0).getImm(); + return true; + } + if (Inst.getOpcode() == RISCV::C_J) { + Target = Addr + Inst.getOperand(0).getImm(); + return true; + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MatInt/generateInstSeq.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MatInt/generateInstSeq.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0060cac9c917e49fbeb4ce1922e603e42795b1b7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MatInt/generateInstSeq.cpp @@ -0,0 +1,24 @@ +void generateInstSeq(int64_t Val, bool IsRV64, InstSeq &Res) { + if (isInt<32>(Val)) { + int64_t Hi20 = ((Val + 0x800) >> 12) & 0xFFFFF; + int64_t Lo12 = SignExtend64<12>(Val); + if (Hi20) { + Res.push_back(Inst(RISCV::LUI, Hi20)); + } + if (Lo12 || Hi20 == 0) { + unsigned AddiOpc = (IsRV64 && Hi20) ? RISCV::ADDIW : RISCV::ADDI; + Res.push_back(Inst(AddiOpc, Lo12)); + } + return; + } + assert(IsRV64 && "Can't emit >32-bit imm for non-RV64 target"); + int64_t Lo12 = SignExtend64<12>(Val); + int64_t Hi52 = ((uint64_t)Val + 0x800ull) >> 12; + int ShiftAmount = 12 + findFirstSet((uint64_t)Hi52); + Hi52 = SignExtend64(Hi52 >> (ShiftAmount - 12), 64 - ShiftAmount); + generateInstSeq(Hi52, IsRV64, Res); + Res.push_back(Inst(RISCV::SLLI, ShiftAmount)); + if (Lo12) { + Res.push_back(Inst(RISCV::ADDI, Lo12)); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MatInt/getIntMatCost.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MatInt/getIntMatCost.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6665d21f4034540dc8eec61a6bbfe54ef663c6b8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MatInt/getIntMatCost.cpp @@ -0,0 +1,11 @@ +int getIntMatCost(const APInt &Val, unsigned Size, bool IsRV64) { + int PlatRegSize = IsRV64 ? 64 : 32; + int Cost = 0; + for (unsigned ShiftVal = 0; ShiftVal < Size; ShiftVal += PlatRegSize) { + APInt Chunk = Val.ashr(ShiftVal).sextOrTrunc(PlatRegSize); + InstSeq MatSeq; + generateInstSeq(Chunk.getSExtValue(), IsRV64, MatSeq); + Cost += MatSeq.size(); + } + return std::max(1, Cost); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MatInt/structInst.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MatInt/structInst.cpp new file mode 100644 index 0000000000000000000000000000000000000000..72c131a03e62d00e247b4679e470e545130c5500 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/MatInt/structInst.cpp @@ -0,0 +1,6 @@ +struct Inst { + unsigned Opc; + int64_t Imm; + Inst(unsigned Opc, int64_t Imm) : Opc(Opc), Imm(Imm) { + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/TargetAsmStreamer.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/TargetAsmStreamer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6d3492c3c4b4b024f7373e13055b92638d05fb48 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/TargetAsmStreamer.cpp @@ -0,0 +1,2 @@ +RISCVTargetAsmStreamer::RISCVTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS) : RISCVTargetStreamer(S), OS(OS) { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/TargetStreamer.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/TargetStreamer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b94e431facda3c3c5b1dd95a39117c17ef23685e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/TargetStreamer.cpp @@ -0,0 +1,2 @@ +RISCVTargetStreamer::RISCVTargetStreamer(MCStreamer &S) : MCTargetStreamer(S) { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitAttribute.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitAttribute.cpp new file mode 100644 index 0000000000000000000000000000000000000000..82213bfb7296465510fc0319bf1ff39b9674d8af --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitAttribute.cpp @@ -0,0 +1,3 @@ +void RISCVTargetAsmStreamer::emitAttribute(unsigned Attribute, unsigned Value) { + OS << "\t.attribute\t" << Attribute << ", " << Twine(Value) << "\n"; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitAttribute2.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitAttribute2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..870438b26a6d2717a882ceaf9d551131fdbc7e9e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitAttribute2.cpp @@ -0,0 +1,2 @@ +void RISCVTargetStreamer::emitAttribute(unsigned Attribute, unsigned Value) { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionNoPIC.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionNoPIC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..20d877300fc7bca5ba6b1617a5338511c2bc87df --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionNoPIC.cpp @@ -0,0 +1,3 @@ +void RISCVTargetAsmStreamer::emitDirectiveOptionNoPIC() { + OS << "\t.option\tnopic\n"; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionNoPIC2.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionNoPIC2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..24d360b9a626b3ca30613e07a043e8c36ad04166 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionNoPIC2.cpp @@ -0,0 +1,2 @@ +void RISCVTargetStreamer::emitDirectiveOptionNoPIC() { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionNoRVC.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionNoRVC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..75229057eafcbd9f9adcbb535c46944ef23b39a3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionNoRVC.cpp @@ -0,0 +1,3 @@ +void RISCVTargetAsmStreamer::emitDirectiveOptionNoRVC() { + OS << "\t.option\tnorvc\n"; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionNoRVC2.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionNoRVC2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..64100dd55ed23fbe89ab192674b0e7caa64a0fe3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionNoRVC2.cpp @@ -0,0 +1,2 @@ +void RISCVTargetStreamer::emitDirectiveOptionNoRVC() { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionNoRelax.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionNoRelax.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0a3b8cb02d7a56b7872fcf7a739c9dbe383df43d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionNoRelax.cpp @@ -0,0 +1,3 @@ +void RISCVTargetAsmStreamer::emitDirectiveOptionNoRelax() { + OS << "\t.option\tnorelax\n"; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionNoRelax2.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionNoRelax2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..014cd7022e9839f21fa8aa4768a30cdaeffd861d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionNoRelax2.cpp @@ -0,0 +1,2 @@ +void RISCVTargetStreamer::emitDirectiveOptionNoRelax() { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionPIC.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionPIC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..47ea756b2e1b80b5b651c38d05504fe653b40088 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionPIC.cpp @@ -0,0 +1,3 @@ +void RISCVTargetAsmStreamer::emitDirectiveOptionPIC() { + OS << "\t.option\tpic\n"; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionPIC2.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionPIC2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..06c067ee99a154f8e224930842bc774d5dcb47e4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionPIC2.cpp @@ -0,0 +1,2 @@ +void RISCVTargetStreamer::emitDirectiveOptionPIC() { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionPop.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionPop.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f43b702a23d57cdb8d0a629f253d1d0c953333c9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionPop.cpp @@ -0,0 +1,3 @@ +void RISCVTargetAsmStreamer::emitDirectiveOptionPop() { + OS << "\t.option\tpop\n"; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionPop2.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionPop2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8ca636170f51e633b77f4f3398472f0a640b19ae --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionPop2.cpp @@ -0,0 +1,2 @@ +void RISCVTargetStreamer::emitDirectiveOptionPop() { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionPush.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionPush.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e01d6991e3599028e0801aa2283d93fb6aecf608 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionPush.cpp @@ -0,0 +1,3 @@ +void RISCVTargetAsmStreamer::emitDirectiveOptionPush() { + OS << "\t.option\tpush\n"; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionPush2.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionPush2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5badbcf4aee44982315a64b9d9d7b63501f1ca52 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionPush2.cpp @@ -0,0 +1,2 @@ +void RISCVTargetStreamer::emitDirectiveOptionPush() { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionRVC.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionRVC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3daa81c9defb1fe5908214512a9b997da9df84e9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionRVC.cpp @@ -0,0 +1,3 @@ +void RISCVTargetAsmStreamer::emitDirectiveOptionRVC() { + OS << "\t.option\trvc\n"; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionRVC2.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionRVC2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1e057b99bef751f948ce1248d8808e6b4a42f5cc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionRVC2.cpp @@ -0,0 +1,2 @@ +void RISCVTargetStreamer::emitDirectiveOptionRVC() { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionRelax.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionRelax.cpp new file mode 100644 index 0000000000000000000000000000000000000000..883a2f11627883b745590856102761fa69ea9917 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionRelax.cpp @@ -0,0 +1,3 @@ +void RISCVTargetAsmStreamer::emitDirectiveOptionRelax() { + OS << "\t.option\trelax\n"; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionRelax2.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionRelax2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a501aa992af95ee95eb223b9d508d37abfcd2344 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionRelax2.cpp @@ -0,0 +1,2 @@ +void RISCVTargetStreamer::emitDirectiveOptionRelax() { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitIntTextAttribute.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitIntTextAttribute.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9445cc18a399c4819969cfc8313374b8500f69c8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitIntTextAttribute.cpp @@ -0,0 +1,2 @@ +void RISCVTargetAsmStreamer::emitIntTextAttribute(unsigned Attribute, unsigned IntValue, StringRef StringValue) { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitIntTextAttribute2.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitIntTextAttribute2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..22139c129524dd04c8743fd1456fa9302f4052b7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitIntTextAttribute2.cpp @@ -0,0 +1,2 @@ +void RISCVTargetStreamer::emitIntTextAttribute(unsigned Attribute, unsigned IntValue, StringRef StringValue) { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitTargetAttributes.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitTargetAttributes.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7a944ac5265c68f9afd88fd4ea951f900ad33720 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitTargetAttributes.cpp @@ -0,0 +1,82 @@ +void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI) { + if (STI.hasFeature(RISCV::FeatureRV32E)) { + emitAttribute(RISCVAttrs::STACK_ALIGN, RISCVAttrs::ALIGN_4); + } + else { + emitAttribute(RISCVAttrs::STACK_ALIGN, RISCVAttrs::ALIGN_16); + } + std::string Arch = "rv32"; + if (STI.hasFeature(RISCV::Feature64Bit)) { + Arch = "rv64"; + } + if (STI.hasFeature(RISCV::FeatureRV32E)) { + Arch += "e1p9"; + } + else { + Arch += "i2p0"; + } + if (STI.hasFeature(RISCV::FeatureStdExtM)) { + Arch += "_m2p0"; + } + if (STI.hasFeature(RISCV::FeatureStdExtA)) { + Arch += "_a2p0"; + } + if (STI.hasFeature(RISCV::FeatureStdExtF)) { + Arch += "_f2p0"; + } + if (STI.hasFeature(RISCV::FeatureStdExtD)) { + Arch += "_d2p0"; + } + if (STI.hasFeature(RISCV::FeatureStdExtC)) { + Arch += "_c2p0"; + } + if (STI.hasFeature(RISCV::FeatureStdExtB)) { + Arch += "_b0p93"; + } + if (STI.hasFeature(RISCV::FeatureStdExtV)) { + Arch += "_v0p10"; + } + if (STI.hasFeature(RISCV::FeatureExtZfh)) { + Arch += "_zfh0p1"; + } + if (STI.hasFeature(RISCV::FeatureExtZba)) { + Arch += "_zba0p93"; + } + if (STI.hasFeature(RISCV::FeatureExtZbb)) { + Arch += "_zbb0p93"; + } + if (STI.hasFeature(RISCV::FeatureExtZbc)) { + Arch += "_zbc0p93"; + } + if (STI.hasFeature(RISCV::FeatureExtZbe)) { + Arch += "_zbe0p93"; + } + if (STI.hasFeature(RISCV::FeatureExtZbf)) { + Arch += "_zbf0p93"; + } + if (STI.hasFeature(RISCV::FeatureExtZbm)) { + Arch += "_zbm0p93"; + } + if (STI.hasFeature(RISCV::FeatureExtZbp)) { + Arch += "_zbp0p93"; + } + if (STI.hasFeature(RISCV::FeatureExtZbproposedc)) { + Arch += "_zbproposedc0p93"; + } + if (STI.hasFeature(RISCV::FeatureExtZbr)) { + Arch += "_zbr0p93"; + } + if (STI.hasFeature(RISCV::FeatureExtZbs)) { + Arch += "_zbs0p93"; + } + if (STI.hasFeature(RISCV::FeatureExtZbt)) { + Arch += "_zbt0p93"; + } + if (STI.hasFeature(RISCV::FeatureExtZvamo)) { + Arch += "_zvamo0p10"; + } + if (STI.hasFeature(RISCV::FeatureStdExtZvlsseg)) { + Arch += "_zvlsseg0p10"; + } + emitTextAttribute(RISCVAttrs::ARCH, Arch); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitTextAttribute.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitTextAttribute.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8adf9578c7a98e95d9518eca4e5e5ae261c9a3d3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitTextAttribute.cpp @@ -0,0 +1,2 @@ +void RISCVTargetStreamer::emitTextAttribute(unsigned Attribute, StringRef String) { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitTextAttribute2.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitTextAttribute2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a8d81c0b722b115d155adfa07cf4f9f53e883f06 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/emitTextAttribute2.cpp @@ -0,0 +1,3 @@ +void RISCVTargetAsmStreamer::emitTextAttribute(unsigned Attribute, StringRef String) { + OS << "\t.attribute\t" << Attribute << ", \"" << String << "\"\n"; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/finish.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/finish.cpp new file mode 100644 index 0000000000000000000000000000000000000000..de1f155329e0d6b104ab1c4139016e3276f42f33 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/finish.cpp @@ -0,0 +1,3 @@ +void RISCVTargetStreamer::finish() { + finishAttributeSection(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/finishAttributeSection.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/finishAttributeSection.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7097a145d4931a634134109460465f57fb62532d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/finishAttributeSection.cpp @@ -0,0 +1,2 @@ +void RISCVTargetAsmStreamer::finishAttributeSection() { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/finishAttributeSection2.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/finishAttributeSection2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..dbe790a4f46ac0e73ef02fbaa1295159764b0427 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Emission/TargetStreamer/finishAttributeSection2.cpp @@ -0,0 +1,2 @@ +void RISCVTargetStreamer::finishAttributeSection() { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/CleanupVSETVLI/CleanupVSETVLI.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/CleanupVSETVLI/CleanupVSETVLI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e448a59e103a5b278a32626fa22971c33e4e81a2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/CleanupVSETVLI/CleanupVSETVLI.cpp @@ -0,0 +1,3 @@ +RISCVCleanupVSETVLI() : MachineFunctionPass(ID) { + initializeRISCVCleanupVSETVLIPass(*PassRegistry::getPassRegistry()); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/CleanupVSETVLI/createPass.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/CleanupVSETVLI/createPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..58e6684cb0995575e8263291d2d1b4be23fb8be5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/CleanupVSETVLI/createPass.cpp @@ -0,0 +1,3 @@ +FunctionPass *llvm::createRISCVCleanupVSETVLIPass() { + return new RISCVCleanupVSETVLI(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/CleanupVSETVLI/getAnalysisUsage.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/CleanupVSETVLI/getAnalysisUsage.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f6d109b669c5aa09fb65618028e6a8e7de39a5c0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/CleanupVSETVLI/getAnalysisUsage.cpp @@ -0,0 +1,4 @@ +void getAnalysisUsage(AnalysisUsage &AU) const override { + AU.setPreservesCFG(); + MachineFunctionPass::getAnalysisUsage(AU); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/CleanupVSETVLI/getPassName.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/CleanupVSETVLI/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..927cff9993216c33d5539c62ac637b71f7f1d1ff --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/CleanupVSETVLI/getPassName.cpp @@ -0,0 +1,3 @@ +StringRef getPassName() const override { + return RISCV_CLEANUP_VSETVLI_NAME; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/CleanupVSETVLI/getRequiredProperties.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/CleanupVSETVLI/getRequiredProperties.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b5b9c0930d3d58a2f4601a4830a241ebb30ca4fd --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/CleanupVSETVLI/getRequiredProperties.cpp @@ -0,0 +1,3 @@ +MachineFunctionProperties getRequiredProperties() const override { + return MachineFunctionProperties().set(MachineFunctionProperties::Property::IsSSA); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/CleanupVSETVLI/runOnMachineBasicBlock.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/CleanupVSETVLI/runOnMachineBasicBlock.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c97a1eaf95f42cd86d239dbfe99d01c3ca33235b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/CleanupVSETVLI/runOnMachineBasicBlock.cpp @@ -0,0 +1,48 @@ +bool RISCVCleanupVSETVLI::runOnMachineBasicBlock(MachineBasicBlock &MBB) { + bool Changed = false; + MachineInstr *PrevVSETVLI = nullptr; + for (auto MII = MBB.begin(), MIE = MBB.end(); MII != MIE;) { + MachineInstr &MI = *MII++; + if (MI.getOpcode() != RISCV::PseudoVSETVLI && MI.getOpcode() != RISCV::PseudoVSETIVLI) { + if (PrevVSETVLI && (MI.isCall() || MI.modifiesRegister(RISCV::VL) || MI.modifiesRegister(RISCV::VTYPE))) { + PrevVSETVLI = nullptr; + } + continue; + } + if (!PrevVSETVLI || !MI.getOperand(0).isDead()) { + PrevVSETVLI = &MI; + continue; + } + if (PrevVSETVLI->getOpcode() != MI.getOpcode()) { + PrevVSETVLI = &MI; + continue; + } + Register AVLReg; + bool SameAVL = false; + if (MI.getOpcode() == RISCV::PseudoVSETVLI) { + AVLReg = MI.getOperand(1).getReg(); + SameAVL = PrevVSETVLI->getOperand(1).getReg() == AVLReg; + } + else { + SameAVL = PrevVSETVLI->getOperand(1).getImm() == MI.getOperand(1).getImm(); + } + int64_t PrevVTYPEImm = PrevVSETVLI->getOperand(2).getImm(); + int64_t VTYPEImm = MI.getOperand(2).getImm(); + if (!SameAVL || PrevVTYPEImm != VTYPEImm) { + PrevVSETVLI = &MI; + continue; + } + if ((MI.getOpcode() == RISCV::PseudoVSETVLI) && (AVLReg == RISCV::X0)) { + assert((PrevVSETVLI->getOpcode() == RISCV::PseudoVSETVLI) && "Unexpected vsetvli opcode."); + Register PrevOutVL = PrevVSETVLI->getOperand(0).getReg(); + Register OutVL = MI.getOperand(0).getReg(); + if (PrevOutVL == RISCV::X0 && OutVL != RISCV::X0) { + PrevVSETVLI = &MI; + continue; + } + } + MI.eraseFromParent(); + Changed = true; + } + return Changed; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/CleanupVSETVLI/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/CleanupVSETVLI/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6ece27d6d7d034f89e389b6590f98d8078dfce2d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/CleanupVSETVLI/runOnMachineFunction.cpp @@ -0,0 +1,14 @@ +bool RISCVCleanupVSETVLI::runOnMachineFunction(MachineFunction &MF) { + if (skipFunction(MF.getFunction())) { + return false; + } + const RISCVSubtarget &ST = MF.getSubtarget(); + if (!ST.hasStdExtV()) { + return false; + } + bool Changed = false; + for (MachineBasicBlock &MBB : MF) { + Changed |= runOnMachineBasicBlock(MBB); + } + return Changed; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/ExpandAtomicPseudoInsts/ExpandAtomicPseudo.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/ExpandAtomicPseudoInsts/ExpandAtomicPseudo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..71ee3fafd667bcf32e20bebcd315637773781ed5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/ExpandAtomicPseudoInsts/ExpandAtomicPseudo.cpp @@ -0,0 +1,3 @@ +RISCVExpandAtomicPseudo() : MachineFunctionPass(ID) { + initializeRISCVExpandAtomicPseudoPass(*PassRegistry::getPassRegistry()); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/ExpandAtomicPseudoInsts/createPass.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/ExpandAtomicPseudoInsts/createPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..83f0448b4561787d31d166f084a5a48eafb4258b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/ExpandAtomicPseudoInsts/createPass.cpp @@ -0,0 +1,3 @@ +FunctionPass *createRISCVExpandAtomicPseudoPass() { + return new RISCVExpandAtomicPseudo(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/ExpandAtomicPseudoInsts/expandMBB.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/ExpandAtomicPseudoInsts/expandMBB.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5dd006e57bfbbd88b5a4764fde7a58c18230b358 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/ExpandAtomicPseudoInsts/expandMBB.cpp @@ -0,0 +1,10 @@ +bool RISCVExpandAtomicPseudo::expandMBB(MachineBasicBlock &MBB) { + bool Modified = false; + MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end(); + while (MBBI != E) { + MachineBasicBlock::iterator NMBBI = std::next(MBBI); + Modified |= expandMI(MBB, MBBI, NMBBI); + MBBI = NMBBI; + } + return Modified; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/ExpandAtomicPseudoInsts/expandMI.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/ExpandAtomicPseudoInsts/expandMI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..64fa3c6df2e50d7812ffe10519289edb89f87299 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/ExpandAtomicPseudoInsts/expandMI.cpp @@ -0,0 +1,878 @@ +bool RISCVExpandAtomicPseudo::expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, MachineBasicBlock::iterator &NextMBBI) { + if (MBBI->getOpcode() == RISCV::PseudoAtomicLoadNand32) { + MachineInstr &MI = *MBBI; + DebugLoc DL = MI.getDebugLoc(); + MachineFunction *MF = MBB.getParent(); + auto LoopMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + auto DoneMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + MF->insert(++MBB.getIterator(), LoopMBB); + MF->insert(++LoopMBB->getIterator(), DoneMBB); + LoopMBB->addSuccessor(LoopMBB); + LoopMBB->addSuccessor(DoneMBB); + DoneMBB->splice(DoneMBB->end(), &MBB, MI, MBB.end()); + DoneMBB->transferSuccessors(&MBB); + MBB.addSuccessor(LoopMBB); + if (!IsMasked) { + Register DestReg = MI.getOperand(0).getReg(); + Register ScratchReg = MI.getOperand(1).getReg(); + Register AddrReg = MI.getOperand(2).getReg(); + Register IncrReg = MI.getOperand(3).getReg(); + AtomicOrdering Ordering = static_cast(MI.getOperand(4).getImm()); + BuildMI(LoopMBB, DL, TII->get(getLRForRMW(Ordering, Width)), DestReg).addReg(AddrReg); + switch (BinOp) { + default: + llvm_unreachable("Unexpected AtomicRMW BinOp"); + case AtomicRMWInst::Nand: + BuildMI(LoopMBB, DL, TII->get(RISCV::AND), ScratchReg).addReg(DestReg).addReg(IncrReg); + BuildMI(LoopMBB, DL, TII->get(RISCV::XORI), ScratchReg).addReg(ScratchReg).addImm(-1); + break; + } + BuildMI(LoopMBB, DL, TII->get(getSCForRMW(Ordering, Width)), ScratchReg).addReg(AddrReg).addReg(ScratchReg); + BuildMI(LoopMBB, DL, TII->get(RISCV::BNE)).addReg(ScratchReg).addReg(RISCV::X0).addMBB(LoopMBB); + } + else { + assert(Width == 32 && "Should never need to expand masked 64-bit operations"); + Register DestReg = MI.getOperand(0).getReg(); + Register ScratchReg = MI.getOperand(1).getReg(); + Register AddrReg = MI.getOperand(2).getReg(); + Register IncrReg = MI.getOperand(3).getReg(); + Register MaskReg = MI.getOperand(4).getReg(); + AtomicOrdering Ordering = static_cast(MI.getOperand(5).getImm()); + BuildMI(LoopMBB, DL, TII->get(getLRForRMW32(Ordering)), DestReg).addReg(AddrReg); + switch (BinOp) { + default: + llvm_unreachable("Unexpected AtomicRMW BinOp"); + case AtomicRMWInst::Xchg: + BuildMI(LoopMBB, DL, TII->get(RISCV::ADDI), ScratchReg).addReg(IncrReg).addImm(0); + break; + case AtomicRMWInst::Add: + BuildMI(LoopMBB, DL, TII->get(RISCV::ADD), ScratchReg).addReg(DestReg).addReg(IncrReg); + break; + case AtomicRMWInst::Sub: + BuildMI(LoopMBB, DL, TII->get(RISCV::SUB), ScratchReg).addReg(DestReg).addReg(IncrReg); + break; + case AtomicRMWInst::Nand: + BuildMI(LoopMBB, DL, TII->get(RISCV::AND), ScratchReg).addReg(DestReg).addReg(IncrReg); + BuildMI(LoopMBB, DL, TII->get(RISCV::XORI), ScratchReg).addReg(ScratchReg).addImm(-1); + break; + } + assert(OldValReg != ScratchReg && "OldValReg and ScratchReg must be unique"); + assert(OldValReg != MaskReg && "OldValReg and MaskReg must be unique"); + assert(ScratchReg != MaskReg && "ScratchReg and MaskReg must be unique"); + BuildMI(MBB, DL, TII->get(RISCV::XOR), ScratchReg).addReg(OldValReg).addReg(NewValReg); + BuildMI(MBB, DL, TII->get(RISCV::AND), ScratchReg).addReg(ScratchReg).addReg(MaskReg); + BuildMI(MBB, DL, TII->get(RISCV::XOR), DestReg).addReg(OldValReg).addReg(ScratchReg); + BuildMI(LoopMBB, DL, TII->get(getSCForRMW32(Ordering)), ScratchReg).addReg(AddrReg).addReg(ScratchReg); + BuildMI(LoopMBB, DL, TII->get(RISCV::BNE)).addReg(ScratchReg).addReg(RISCV::X0).addMBB(LoopMBB); + } + NextMBBI = MBB.end(); + MI.eraseFromParent(); + LivePhysRegs LiveRegs; + computeAndAddLiveIns(LiveRegs, *LoopMBB); + computeAndAddLiveIns(LiveRegs, *DoneMBB); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoAtomicLoadNand64) { + MachineInstr &MI = *MBBI; + DebugLoc DL = MI.getDebugLoc(); + MachineFunction *MF = MBB.getParent(); + auto LoopMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + auto DoneMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + MF->insert(++MBB.getIterator(), LoopMBB); + MF->insert(++LoopMBB->getIterator(), DoneMBB); + LoopMBB->addSuccessor(LoopMBB); + LoopMBB->addSuccessor(DoneMBB); + DoneMBB->splice(DoneMBB->end(), &MBB, MI, MBB.end()); + DoneMBB->transferSuccessors(&MBB); + MBB.addSuccessor(LoopMBB); + if (!IsMasked) { + Register DestReg = MI.getOperand(0).getReg(); + Register ScratchReg = MI.getOperand(1).getReg(); + Register AddrReg = MI.getOperand(2).getReg(); + Register IncrReg = MI.getOperand(3).getReg(); + AtomicOrdering Ordering = static_cast(MI.getOperand(4).getImm()); + BuildMI(LoopMBB, DL, TII->get(getLRForRMW(Ordering, Width)), DestReg).addReg(AddrReg); + switch (BinOp) { + default: + llvm_unreachable("Unexpected AtomicRMW BinOp"); + case AtomicRMWInst::Nand: + BuildMI(LoopMBB, DL, TII->get(RISCV::AND), ScratchReg).addReg(DestReg).addReg(IncrReg); + BuildMI(LoopMBB, DL, TII->get(RISCV::XORI), ScratchReg).addReg(ScratchReg).addImm(-1); + break; + } + BuildMI(LoopMBB, DL, TII->get(getSCForRMW(Ordering, Width)), ScratchReg).addReg(AddrReg).addReg(ScratchReg); + BuildMI(LoopMBB, DL, TII->get(RISCV::BNE)).addReg(ScratchReg).addReg(RISCV::X0).addMBB(LoopMBB); + } + else { + assert(Width == 32 && "Should never need to expand masked 64-bit operations"); + Register DestReg = MI.getOperand(0).getReg(); + Register ScratchReg = MI.getOperand(1).getReg(); + Register AddrReg = MI.getOperand(2).getReg(); + Register IncrReg = MI.getOperand(3).getReg(); + Register MaskReg = MI.getOperand(4).getReg(); + AtomicOrdering Ordering = static_cast(MI.getOperand(5).getImm()); + BuildMI(LoopMBB, DL, TII->get(getLRForRMW32(Ordering)), DestReg).addReg(AddrReg); + switch (BinOp) { + default: + llvm_unreachable("Unexpected AtomicRMW BinOp"); + case AtomicRMWInst::Xchg: + BuildMI(LoopMBB, DL, TII->get(RISCV::ADDI), ScratchReg).addReg(IncrReg).addImm(0); + break; + case AtomicRMWInst::Add: + BuildMI(LoopMBB, DL, TII->get(RISCV::ADD), ScratchReg).addReg(DestReg).addReg(IncrReg); + break; + case AtomicRMWInst::Sub: + BuildMI(LoopMBB, DL, TII->get(RISCV::SUB), ScratchReg).addReg(DestReg).addReg(IncrReg); + break; + case AtomicRMWInst::Nand: + BuildMI(LoopMBB, DL, TII->get(RISCV::AND), ScratchReg).addReg(DestReg).addReg(IncrReg); + BuildMI(LoopMBB, DL, TII->get(RISCV::XORI), ScratchReg).addReg(ScratchReg).addImm(-1); + break; + } + assert(OldValReg != ScratchReg && "OldValReg and ScratchReg must be unique"); + assert(OldValReg != MaskReg && "OldValReg and MaskReg must be unique"); + assert(ScratchReg != MaskReg && "ScratchReg and MaskReg must be unique"); + BuildMI(MBB, DL, TII->get(RISCV::XOR), ScratchReg).addReg(OldValReg).addReg(NewValReg); + BuildMI(MBB, DL, TII->get(RISCV::AND), ScratchReg).addReg(ScratchReg).addReg(MaskReg); + BuildMI(MBB, DL, TII->get(RISCV::XOR), DestReg).addReg(OldValReg).addReg(ScratchReg); + BuildMI(LoopMBB, DL, TII->get(getSCForRMW32(Ordering)), ScratchReg).addReg(AddrReg).addReg(ScratchReg); + BuildMI(LoopMBB, DL, TII->get(RISCV::BNE)).addReg(ScratchReg).addReg(RISCV::X0).addMBB(LoopMBB); + } + NextMBBI = MBB.end(); + MI.eraseFromParent(); + LivePhysRegs LiveRegs; + computeAndAddLiveIns(LiveRegs, *LoopMBB); + computeAndAddLiveIns(LiveRegs, *DoneMBB); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoMaskedAtomicSwap32) { + MachineInstr &MI = *MBBI; + DebugLoc DL = MI.getDebugLoc(); + MachineFunction *MF = MBB.getParent(); + auto LoopMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + auto DoneMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + MF->insert(++MBB.getIterator(), LoopMBB); + MF->insert(++LoopMBB->getIterator(), DoneMBB); + LoopMBB->addSuccessor(LoopMBB); + LoopMBB->addSuccessor(DoneMBB); + DoneMBB->splice(DoneMBB->end(), &MBB, MI, MBB.end()); + DoneMBB->transferSuccessors(&MBB); + MBB.addSuccessor(LoopMBB); + if (!IsMasked) { + Register DestReg = MI.getOperand(0).getReg(); + Register ScratchReg = MI.getOperand(1).getReg(); + Register AddrReg = MI.getOperand(2).getReg(); + Register IncrReg = MI.getOperand(3).getReg(); + AtomicOrdering Ordering = static_cast(MI.getOperand(4).getImm()); + BuildMI(LoopMBB, DL, TII->get(getLRForRMW(Ordering, Width)), DestReg).addReg(AddrReg); + switch (BinOp) { + default: + llvm_unreachable("Unexpected AtomicRMW BinOp"); + case AtomicRMWInst::Nand: + BuildMI(LoopMBB, DL, TII->get(RISCV::AND), ScratchReg).addReg(DestReg).addReg(IncrReg); + BuildMI(LoopMBB, DL, TII->get(RISCV::XORI), ScratchReg).addReg(ScratchReg).addImm(-1); + break; + } + BuildMI(LoopMBB, DL, TII->get(getSCForRMW(Ordering, Width)), ScratchReg).addReg(AddrReg).addReg(ScratchReg); + BuildMI(LoopMBB, DL, TII->get(RISCV::BNE)).addReg(ScratchReg).addReg(RISCV::X0).addMBB(LoopMBB); + } + else { + assert(Width == 32 && "Should never need to expand masked 64-bit operations"); + Register DestReg = MI.getOperand(0).getReg(); + Register ScratchReg = MI.getOperand(1).getReg(); + Register AddrReg = MI.getOperand(2).getReg(); + Register IncrReg = MI.getOperand(3).getReg(); + Register MaskReg = MI.getOperand(4).getReg(); + AtomicOrdering Ordering = static_cast(MI.getOperand(5).getImm()); + BuildMI(LoopMBB, DL, TII->get(getLRForRMW32(Ordering)), DestReg).addReg(AddrReg); + switch (BinOp) { + default: + llvm_unreachable("Unexpected AtomicRMW BinOp"); + case AtomicRMWInst::Xchg: + BuildMI(LoopMBB, DL, TII->get(RISCV::ADDI), ScratchReg).addReg(IncrReg).addImm(0); + break; + case AtomicRMWInst::Add: + BuildMI(LoopMBB, DL, TII->get(RISCV::ADD), ScratchReg).addReg(DestReg).addReg(IncrReg); + break; + case AtomicRMWInst::Sub: + BuildMI(LoopMBB, DL, TII->get(RISCV::SUB), ScratchReg).addReg(DestReg).addReg(IncrReg); + break; + case AtomicRMWInst::Nand: + BuildMI(LoopMBB, DL, TII->get(RISCV::AND), ScratchReg).addReg(DestReg).addReg(IncrReg); + BuildMI(LoopMBB, DL, TII->get(RISCV::XORI), ScratchReg).addReg(ScratchReg).addImm(-1); + break; + } + assert(OldValReg != ScratchReg && "OldValReg and ScratchReg must be unique"); + assert(OldValReg != MaskReg && "OldValReg and MaskReg must be unique"); + assert(ScratchReg != MaskReg && "ScratchReg and MaskReg must be unique"); + BuildMI(MBB, DL, TII->get(RISCV::XOR), ScratchReg).addReg(OldValReg).addReg(NewValReg); + BuildMI(MBB, DL, TII->get(RISCV::AND), ScratchReg).addReg(ScratchReg).addReg(MaskReg); + BuildMI(MBB, DL, TII->get(RISCV::XOR), DestReg).addReg(OldValReg).addReg(ScratchReg); + BuildMI(LoopMBB, DL, TII->get(getSCForRMW32(Ordering)), ScratchReg).addReg(AddrReg).addReg(ScratchReg); + BuildMI(LoopMBB, DL, TII->get(RISCV::BNE)).addReg(ScratchReg).addReg(RISCV::X0).addMBB(LoopMBB); + } + NextMBBI = MBB.end(); + MI.eraseFromParent(); + LivePhysRegs LiveRegs; + computeAndAddLiveIns(LiveRegs, *LoopMBB); + computeAndAddLiveIns(LiveRegs, *DoneMBB); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoMaskedAtomicLoadAdd32) { + MachineInstr &MI = *MBBI; + DebugLoc DL = MI.getDebugLoc(); + MachineFunction *MF = MBB.getParent(); + auto LoopMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + auto DoneMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + MF->insert(++MBB.getIterator(), LoopMBB); + MF->insert(++LoopMBB->getIterator(), DoneMBB); + LoopMBB->addSuccessor(LoopMBB); + LoopMBB->addSuccessor(DoneMBB); + DoneMBB->splice(DoneMBB->end(), &MBB, MI, MBB.end()); + DoneMBB->transferSuccessors(&MBB); + MBB.addSuccessor(LoopMBB); + if (!IsMasked) { + Register DestReg = MI.getOperand(0).getReg(); + Register ScratchReg = MI.getOperand(1).getReg(); + Register AddrReg = MI.getOperand(2).getReg(); + Register IncrReg = MI.getOperand(3).getReg(); + AtomicOrdering Ordering = static_cast(MI.getOperand(4).getImm()); + BuildMI(LoopMBB, DL, TII->get(getLRForRMW(Ordering, Width)), DestReg).addReg(AddrReg); + switch (BinOp) { + default: + llvm_unreachable("Unexpected AtomicRMW BinOp"); + case AtomicRMWInst::Nand: + BuildMI(LoopMBB, DL, TII->get(RISCV::AND), ScratchReg).addReg(DestReg).addReg(IncrReg); + BuildMI(LoopMBB, DL, TII->get(RISCV::XORI), ScratchReg).addReg(ScratchReg).addImm(-1); + break; + } + BuildMI(LoopMBB, DL, TII->get(getSCForRMW(Ordering, Width)), ScratchReg).addReg(AddrReg).addReg(ScratchReg); + BuildMI(LoopMBB, DL, TII->get(RISCV::BNE)).addReg(ScratchReg).addReg(RISCV::X0).addMBB(LoopMBB); + } + else { + assert(Width == 32 && "Should never need to expand masked 64-bit operations"); + Register DestReg = MI.getOperand(0).getReg(); + Register ScratchReg = MI.getOperand(1).getReg(); + Register AddrReg = MI.getOperand(2).getReg(); + Register IncrReg = MI.getOperand(3).getReg(); + Register MaskReg = MI.getOperand(4).getReg(); + AtomicOrdering Ordering = static_cast(MI.getOperand(5).getImm()); + BuildMI(LoopMBB, DL, TII->get(getLRForRMW32(Ordering)), DestReg).addReg(AddrReg); + switch (BinOp) { + default: + llvm_unreachable("Unexpected AtomicRMW BinOp"); + case AtomicRMWInst::Xchg: + BuildMI(LoopMBB, DL, TII->get(RISCV::ADDI), ScratchReg).addReg(IncrReg).addImm(0); + break; + case AtomicRMWInst::Add: + BuildMI(LoopMBB, DL, TII->get(RISCV::ADD), ScratchReg).addReg(DestReg).addReg(IncrReg); + break; + case AtomicRMWInst::Sub: + BuildMI(LoopMBB, DL, TII->get(RISCV::SUB), ScratchReg).addReg(DestReg).addReg(IncrReg); + break; + case AtomicRMWInst::Nand: + BuildMI(LoopMBB, DL, TII->get(RISCV::AND), ScratchReg).addReg(DestReg).addReg(IncrReg); + BuildMI(LoopMBB, DL, TII->get(RISCV::XORI), ScratchReg).addReg(ScratchReg).addImm(-1); + break; + } + assert(OldValReg != ScratchReg && "OldValReg and ScratchReg must be unique"); + assert(OldValReg != MaskReg && "OldValReg and MaskReg must be unique"); + assert(ScratchReg != MaskReg && "ScratchReg and MaskReg must be unique"); + BuildMI(MBB, DL, TII->get(RISCV::XOR), ScratchReg).addReg(OldValReg).addReg(NewValReg); + BuildMI(MBB, DL, TII->get(RISCV::AND), ScratchReg).addReg(ScratchReg).addReg(MaskReg); + BuildMI(MBB, DL, TII->get(RISCV::XOR), DestReg).addReg(OldValReg).addReg(ScratchReg); + BuildMI(LoopMBB, DL, TII->get(getSCForRMW32(Ordering)), ScratchReg).addReg(AddrReg).addReg(ScratchReg); + BuildMI(LoopMBB, DL, TII->get(RISCV::BNE)).addReg(ScratchReg).addReg(RISCV::X0).addMBB(LoopMBB); + } + NextMBBI = MBB.end(); + MI.eraseFromParent(); + LivePhysRegs LiveRegs; + computeAndAddLiveIns(LiveRegs, *LoopMBB); + computeAndAddLiveIns(LiveRegs, *DoneMBB); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoMaskedAtomicLoadSub32) { + MachineInstr &MI = *MBBI; + DebugLoc DL = MI.getDebugLoc(); + MachineFunction *MF = MBB.getParent(); + auto LoopMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + auto DoneMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + MF->insert(++MBB.getIterator(), LoopMBB); + MF->insert(++LoopMBB->getIterator(), DoneMBB); + LoopMBB->addSuccessor(LoopMBB); + LoopMBB->addSuccessor(DoneMBB); + DoneMBB->splice(DoneMBB->end(), &MBB, MI, MBB.end()); + DoneMBB->transferSuccessors(&MBB); + MBB.addSuccessor(LoopMBB); + if (!IsMasked) { + Register DestReg = MI.getOperand(0).getReg(); + Register ScratchReg = MI.getOperand(1).getReg(); + Register AddrReg = MI.getOperand(2).getReg(); + Register IncrReg = MI.getOperand(3).getReg(); + AtomicOrdering Ordering = static_cast(MI.getOperand(4).getImm()); + BuildMI(LoopMBB, DL, TII->get(getLRForRMW(Ordering, Width)), DestReg).addReg(AddrReg); + switch (BinOp) { + default: + llvm_unreachable("Unexpected AtomicRMW BinOp"); + case AtomicRMWInst::Nand: + BuildMI(LoopMBB, DL, TII->get(RISCV::AND), ScratchReg).addReg(DestReg).addReg(IncrReg); + BuildMI(LoopMBB, DL, TII->get(RISCV::XORI), ScratchReg).addReg(ScratchReg).addImm(-1); + break; + } + BuildMI(LoopMBB, DL, TII->get(getSCForRMW(Ordering, Width)), ScratchReg).addReg(AddrReg).addReg(ScratchReg); + BuildMI(LoopMBB, DL, TII->get(RISCV::BNE)).addReg(ScratchReg).addReg(RISCV::X0).addMBB(LoopMBB); + } + else { + assert(Width == 32 && "Should never need to expand masked 64-bit operations"); + Register DestReg = MI.getOperand(0).getReg(); + Register ScratchReg = MI.getOperand(1).getReg(); + Register AddrReg = MI.getOperand(2).getReg(); + Register IncrReg = MI.getOperand(3).getReg(); + Register MaskReg = MI.getOperand(4).getReg(); + AtomicOrdering Ordering = static_cast(MI.getOperand(5).getImm()); + BuildMI(LoopMBB, DL, TII->get(getLRForRMW32(Ordering)), DestReg).addReg(AddrReg); + switch (BinOp) { + default: + llvm_unreachable("Unexpected AtomicRMW BinOp"); + case AtomicRMWInst::Xchg: + BuildMI(LoopMBB, DL, TII->get(RISCV::ADDI), ScratchReg).addReg(IncrReg).addImm(0); + break; + case AtomicRMWInst::Add: + BuildMI(LoopMBB, DL, TII->get(RISCV::ADD), ScratchReg).addReg(DestReg).addReg(IncrReg); + break; + case AtomicRMWInst::Sub: + BuildMI(LoopMBB, DL, TII->get(RISCV::SUB), ScratchReg).addReg(DestReg).addReg(IncrReg); + break; + case AtomicRMWInst::Nand: + BuildMI(LoopMBB, DL, TII->get(RISCV::AND), ScratchReg).addReg(DestReg).addReg(IncrReg); + BuildMI(LoopMBB, DL, TII->get(RISCV::XORI), ScratchReg).addReg(ScratchReg).addImm(-1); + break; + } + assert(OldValReg != ScratchReg && "OldValReg and ScratchReg must be unique"); + assert(OldValReg != MaskReg && "OldValReg and MaskReg must be unique"); + assert(ScratchReg != MaskReg && "ScratchReg and MaskReg must be unique"); + BuildMI(MBB, DL, TII->get(RISCV::XOR), ScratchReg).addReg(OldValReg).addReg(NewValReg); + BuildMI(MBB, DL, TII->get(RISCV::AND), ScratchReg).addReg(ScratchReg).addReg(MaskReg); + BuildMI(MBB, DL, TII->get(RISCV::XOR), DestReg).addReg(OldValReg).addReg(ScratchReg); + BuildMI(LoopMBB, DL, TII->get(getSCForRMW32(Ordering)), ScratchReg).addReg(AddrReg).addReg(ScratchReg); + BuildMI(LoopMBB, DL, TII->get(RISCV::BNE)).addReg(ScratchReg).addReg(RISCV::X0).addMBB(LoopMBB); + } + NextMBBI = MBB.end(); + MI.eraseFromParent(); + LivePhysRegs LiveRegs; + computeAndAddLiveIns(LiveRegs, *LoopMBB); + computeAndAddLiveIns(LiveRegs, *DoneMBB); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoMaskedAtomicLoadNand32) { + MachineInstr &MI = *MBBI; + DebugLoc DL = MI.getDebugLoc(); + MachineFunction *MF = MBB.getParent(); + auto LoopMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + auto DoneMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + MF->insert(++MBB.getIterator(), LoopMBB); + MF->insert(++LoopMBB->getIterator(), DoneMBB); + LoopMBB->addSuccessor(LoopMBB); + LoopMBB->addSuccessor(DoneMBB); + DoneMBB->splice(DoneMBB->end(), &MBB, MI, MBB.end()); + DoneMBB->transferSuccessors(&MBB); + MBB.addSuccessor(LoopMBB); + if (!IsMasked) { + Register DestReg = MI.getOperand(0).getReg(); + Register ScratchReg = MI.getOperand(1).getReg(); + Register AddrReg = MI.getOperand(2).getReg(); + Register IncrReg = MI.getOperand(3).getReg(); + AtomicOrdering Ordering = static_cast(MI.getOperand(4).getImm()); + BuildMI(LoopMBB, DL, TII->get(getLRForRMW(Ordering, Width)), DestReg).addReg(AddrReg); + switch (BinOp) { + default: + llvm_unreachable("Unexpected AtomicRMW BinOp"); + case AtomicRMWInst::Nand: + BuildMI(LoopMBB, DL, TII->get(RISCV::AND), ScratchReg).addReg(DestReg).addReg(IncrReg); + BuildMI(LoopMBB, DL, TII->get(RISCV::XORI), ScratchReg).addReg(ScratchReg).addImm(-1); + break; + } + BuildMI(LoopMBB, DL, TII->get(getSCForRMW(Ordering, Width)), ScratchReg).addReg(AddrReg).addReg(ScratchReg); + BuildMI(LoopMBB, DL, TII->get(RISCV::BNE)).addReg(ScratchReg).addReg(RISCV::X0).addMBB(LoopMBB); + } + else { + assert(Width == 32 && "Should never need to expand masked 64-bit operations"); + Register DestReg = MI.getOperand(0).getReg(); + Register ScratchReg = MI.getOperand(1).getReg(); + Register AddrReg = MI.getOperand(2).getReg(); + Register IncrReg = MI.getOperand(3).getReg(); + Register MaskReg = MI.getOperand(4).getReg(); + AtomicOrdering Ordering = static_cast(MI.getOperand(5).getImm()); + BuildMI(LoopMBB, DL, TII->get(getLRForRMW32(Ordering)), DestReg).addReg(AddrReg); + switch (BinOp) { + default: + llvm_unreachable("Unexpected AtomicRMW BinOp"); + case AtomicRMWInst::Xchg: + BuildMI(LoopMBB, DL, TII->get(RISCV::ADDI), ScratchReg).addReg(IncrReg).addImm(0); + break; + case AtomicRMWInst::Add: + BuildMI(LoopMBB, DL, TII->get(RISCV::ADD), ScratchReg).addReg(DestReg).addReg(IncrReg); + break; + case AtomicRMWInst::Sub: + BuildMI(LoopMBB, DL, TII->get(RISCV::SUB), ScratchReg).addReg(DestReg).addReg(IncrReg); + break; + case AtomicRMWInst::Nand: + BuildMI(LoopMBB, DL, TII->get(RISCV::AND), ScratchReg).addReg(DestReg).addReg(IncrReg); + BuildMI(LoopMBB, DL, TII->get(RISCV::XORI), ScratchReg).addReg(ScratchReg).addImm(-1); + break; + } + assert(OldValReg != ScratchReg && "OldValReg and ScratchReg must be unique"); + assert(OldValReg != MaskReg && "OldValReg and MaskReg must be unique"); + assert(ScratchReg != MaskReg && "ScratchReg and MaskReg must be unique"); + BuildMI(MBB, DL, TII->get(RISCV::XOR), ScratchReg).addReg(OldValReg).addReg(NewValReg); + BuildMI(MBB, DL, TII->get(RISCV::AND), ScratchReg).addReg(ScratchReg).addReg(MaskReg); + BuildMI(MBB, DL, TII->get(RISCV::XOR), DestReg).addReg(OldValReg).addReg(ScratchReg); + BuildMI(LoopMBB, DL, TII->get(getSCForRMW32(Ordering)), ScratchReg).addReg(AddrReg).addReg(ScratchReg); + BuildMI(LoopMBB, DL, TII->get(RISCV::BNE)).addReg(ScratchReg).addReg(RISCV::X0).addMBB(LoopMBB); + } + NextMBBI = MBB.end(); + MI.eraseFromParent(); + LivePhysRegs LiveRegs; + computeAndAddLiveIns(LiveRegs, *LoopMBB); + computeAndAddLiveIns(LiveRegs, *DoneMBB); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoMaskedAtomicLoadMax32) { + assert(IsMasked == true && "Should only need to expand masked atomic max/min"); + assert(Width == 32 && "Should never need to expand masked 64-bit operations"); + MachineInstr &MI = *MBBI; + DebugLoc DL = MI.getDebugLoc(); + MachineFunction *MF = MBB.getParent(); + auto LoopHeadMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + auto LoopIfBodyMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + auto LoopTailMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + auto DoneMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + MF->insert(++MBB.getIterator(), LoopHeadMBB); + MF->insert(++LoopHeadMBB->getIterator(), LoopIfBodyMBB); + MF->insert(++LoopIfBodyMBB->getIterator(), LoopTailMBB); + MF->insert(++LoopTailMBB->getIterator(), DoneMBB); + LoopHeadMBB->addSuccessor(LoopIfBodyMBB); + LoopHeadMBB->addSuccessor(LoopTailMBB); + LoopIfBodyMBB->addSuccessor(LoopTailMBB); + LoopTailMBB->addSuccessor(LoopHeadMBB); + LoopTailMBB->addSuccessor(DoneMBB); + DoneMBB->splice(DoneMBB->end(), &MBB, MI, MBB.end()); + DoneMBB->transferSuccessors(&MBB); + MBB.addSuccessor(LoopHeadMBB); + Register DestReg = MI.getOperand(0).getReg(); + Register Scratch1Reg = MI.getOperand(1).getReg(); + Register Scratch2Reg = MI.getOperand(2).getReg(); + Register AddrReg = MI.getOperand(3).getReg(); + Register IncrReg = MI.getOperand(4).getReg(); + Register MaskReg = MI.getOperand(5).getReg(); + bool IsSigned = BinOp == AtomicRMWInst::Min || BinOp == AtomicRMWInst::Max; + AtomicOrdering Ordering = static_cast(MI.getOperand(IsSigned ? 7 : 6).getImm()); + BuildMI(LoopHeadMBB, DL, TII->get(getLRForRMW32(Ordering)), DestReg).addReg(AddrReg); + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::AND), Scratch2Reg).addReg(DestReg).addReg(MaskReg); + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::ADDI), Scratch1Reg).addReg(DestReg).addImm(0); + switch (BinOp) { + default: + llvm_unreachable("Unexpected AtomicRMW BinOp"); + case AtomicRMWInst::Max: { + BuildMI(MBB, DL, TII->get(RISCV::SLL), ValReg).addReg(ValReg).addReg(ShamtReg); + BuildMI(MBB, DL, TII->get(RISCV::SRA), ValReg).addReg(ValReg).addReg(ShamtReg); + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGE)).addReg(Scratch2Reg).addReg(IncrReg).addMBB(LoopTailMBB); + break; + } + case AtomicRMWInst::Min: { + BuildMI(MBB, DL, TII->get(RISCV::SLL), ValReg).addReg(ValReg).addReg(ShamtReg); + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGE)).addReg(IncrReg).addReg(Scratch2Reg).addMBB(LoopTailMBB); + break; + } + case AtomicRMWInst::UMax: + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGEU)).addReg(Scratch2Reg).addReg(IncrReg).addMBB(LoopTailMBB); + break; + case AtomicRMWInst::UMin: + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGEU)).addReg(IncrReg).addReg(Scratch2Reg).addMBB(LoopTailMBB); + break; + } + assert(OldValReg != ScratchReg && "OldValReg and ScratchReg must be unique"); + assert(OldValReg != MaskReg && "OldValReg and MaskReg must be unique"); + assert(ScratchReg != MaskReg && "ScratchReg and MaskReg must be unique"); + BuildMI(MBB, DL, TII->get(RISCV::XOR), ScratchReg).addReg(OldValReg).addReg(NewValReg); + BuildMI(MBB, DL, TII->get(RISCV::AND), ScratchReg).addReg(ScratchReg).addReg(MaskReg); + BuildMI(MBB, DL, TII->get(RISCV::XOR), DestReg).addReg(OldValReg).addReg(ScratchReg); + BuildMI(LoopTailMBB, DL, TII->get(getSCForRMW32(Ordering)), Scratch1Reg).addReg(AddrReg).addReg(Scratch1Reg); + BuildMI(LoopTailMBB, DL, TII->get(RISCV::BNE)).addReg(Scratch1Reg).addReg(RISCV::X0).addMBB(LoopHeadMBB); + NextMBBI = MBB.end(); + MI.eraseFromParent(); + LivePhysRegs LiveRegs; + computeAndAddLiveIns(LiveRegs, *LoopHeadMBB); + computeAndAddLiveIns(LiveRegs, *LoopIfBodyMBB); + computeAndAddLiveIns(LiveRegs, *LoopTailMBB); + computeAndAddLiveIns(LiveRegs, *DoneMBB); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoMaskedAtomicLoadMin32) { + assert(IsMasked == true && "Should only need to expand masked atomic max/min"); + assert(Width == 32 && "Should never need to expand masked 64-bit operations"); + MachineInstr &MI = *MBBI; + DebugLoc DL = MI.getDebugLoc(); + MachineFunction *MF = MBB.getParent(); + auto LoopHeadMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + auto LoopIfBodyMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + auto LoopTailMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + auto DoneMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + MF->insert(++MBB.getIterator(), LoopHeadMBB); + MF->insert(++LoopHeadMBB->getIterator(), LoopIfBodyMBB); + MF->insert(++LoopIfBodyMBB->getIterator(), LoopTailMBB); + MF->insert(++LoopTailMBB->getIterator(), DoneMBB); + LoopHeadMBB->addSuccessor(LoopIfBodyMBB); + LoopHeadMBB->addSuccessor(LoopTailMBB); + LoopIfBodyMBB->addSuccessor(LoopTailMBB); + LoopTailMBB->addSuccessor(LoopHeadMBB); + LoopTailMBB->addSuccessor(DoneMBB); + DoneMBB->splice(DoneMBB->end(), &MBB, MI, MBB.end()); + DoneMBB->transferSuccessors(&MBB); + MBB.addSuccessor(LoopHeadMBB); + Register DestReg = MI.getOperand(0).getReg(); + Register Scratch1Reg = MI.getOperand(1).getReg(); + Register Scratch2Reg = MI.getOperand(2).getReg(); + Register AddrReg = MI.getOperand(3).getReg(); + Register IncrReg = MI.getOperand(4).getReg(); + Register MaskReg = MI.getOperand(5).getReg(); + bool IsSigned = BinOp == AtomicRMWInst::Min || BinOp == AtomicRMWInst::Max; + AtomicOrdering Ordering = static_cast(MI.getOperand(IsSigned ? 7 : 6).getImm()); + BuildMI(LoopHeadMBB, DL, TII->get(getLRForRMW32(Ordering)), DestReg).addReg(AddrReg); + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::AND), Scratch2Reg).addReg(DestReg).addReg(MaskReg); + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::ADDI), Scratch1Reg).addReg(DestReg).addImm(0); + switch (BinOp) { + default: + llvm_unreachable("Unexpected AtomicRMW BinOp"); + case AtomicRMWInst::Max: { + BuildMI(MBB, DL, TII->get(RISCV::SLL), ValReg).addReg(ValReg).addReg(ShamtReg); + BuildMI(MBB, DL, TII->get(RISCV::SRA), ValReg).addReg(ValReg).addReg(ShamtReg); + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGE)).addReg(Scratch2Reg).addReg(IncrReg).addMBB(LoopTailMBB); + break; + } + case AtomicRMWInst::Min: { + BuildMI(MBB, DL, TII->get(RISCV::SLL), ValReg).addReg(ValReg).addReg(ShamtReg); + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGE)).addReg(IncrReg).addReg(Scratch2Reg).addMBB(LoopTailMBB); + break; + } + case AtomicRMWInst::UMax: + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGEU)).addReg(Scratch2Reg).addReg(IncrReg).addMBB(LoopTailMBB); + break; + case AtomicRMWInst::UMin: + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGEU)).addReg(IncrReg).addReg(Scratch2Reg).addMBB(LoopTailMBB); + break; + } + assert(OldValReg != ScratchReg && "OldValReg and ScratchReg must be unique"); + assert(OldValReg != MaskReg && "OldValReg and MaskReg must be unique"); + assert(ScratchReg != MaskReg && "ScratchReg and MaskReg must be unique"); + BuildMI(MBB, DL, TII->get(RISCV::XOR), ScratchReg).addReg(OldValReg).addReg(NewValReg); + BuildMI(MBB, DL, TII->get(RISCV::AND), ScratchReg).addReg(ScratchReg).addReg(MaskReg); + BuildMI(MBB, DL, TII->get(RISCV::XOR), DestReg).addReg(OldValReg).addReg(ScratchReg); + BuildMI(LoopTailMBB, DL, TII->get(getSCForRMW32(Ordering)), Scratch1Reg).addReg(AddrReg).addReg(Scratch1Reg); + BuildMI(LoopTailMBB, DL, TII->get(RISCV::BNE)).addReg(Scratch1Reg).addReg(RISCV::X0).addMBB(LoopHeadMBB); + NextMBBI = MBB.end(); + MI.eraseFromParent(); + LivePhysRegs LiveRegs; + computeAndAddLiveIns(LiveRegs, *LoopHeadMBB); + computeAndAddLiveIns(LiveRegs, *LoopIfBodyMBB); + computeAndAddLiveIns(LiveRegs, *LoopTailMBB); + computeAndAddLiveIns(LiveRegs, *DoneMBB); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoMaskedAtomicLoadUMax32) { + assert(IsMasked == true && "Should only need to expand masked atomic max/min"); + assert(Width == 32 && "Should never need to expand masked 64-bit operations"); + MachineInstr &MI = *MBBI; + DebugLoc DL = MI.getDebugLoc(); + MachineFunction *MF = MBB.getParent(); + auto LoopHeadMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + auto LoopIfBodyMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + auto LoopTailMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + auto DoneMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + MF->insert(++MBB.getIterator(), LoopHeadMBB); + MF->insert(++LoopHeadMBB->getIterator(), LoopIfBodyMBB); + MF->insert(++LoopIfBodyMBB->getIterator(), LoopTailMBB); + MF->insert(++LoopTailMBB->getIterator(), DoneMBB); + LoopHeadMBB->addSuccessor(LoopIfBodyMBB); + LoopHeadMBB->addSuccessor(LoopTailMBB); + LoopIfBodyMBB->addSuccessor(LoopTailMBB); + LoopTailMBB->addSuccessor(LoopHeadMBB); + LoopTailMBB->addSuccessor(DoneMBB); + DoneMBB->splice(DoneMBB->end(), &MBB, MI, MBB.end()); + DoneMBB->transferSuccessors(&MBB); + MBB.addSuccessor(LoopHeadMBB); + Register DestReg = MI.getOperand(0).getReg(); + Register Scratch1Reg = MI.getOperand(1).getReg(); + Register Scratch2Reg = MI.getOperand(2).getReg(); + Register AddrReg = MI.getOperand(3).getReg(); + Register IncrReg = MI.getOperand(4).getReg(); + Register MaskReg = MI.getOperand(5).getReg(); + bool IsSigned = BinOp == AtomicRMWInst::Min || BinOp == AtomicRMWInst::Max; + AtomicOrdering Ordering = static_cast(MI.getOperand(IsSigned ? 7 : 6).getImm()); + BuildMI(LoopHeadMBB, DL, TII->get(getLRForRMW32(Ordering)), DestReg).addReg(AddrReg); + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::AND), Scratch2Reg).addReg(DestReg).addReg(MaskReg); + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::ADDI), Scratch1Reg).addReg(DestReg).addImm(0); + switch (BinOp) { + default: + llvm_unreachable("Unexpected AtomicRMW BinOp"); + case AtomicRMWInst::Max: { + BuildMI(MBB, DL, TII->get(RISCV::SLL), ValReg).addReg(ValReg).addReg(ShamtReg); + BuildMI(MBB, DL, TII->get(RISCV::SRA), ValReg).addReg(ValReg).addReg(ShamtReg); + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGE)).addReg(Scratch2Reg).addReg(IncrReg).addMBB(LoopTailMBB); + break; + } + case AtomicRMWInst::Min: { + BuildMI(MBB, DL, TII->get(RISCV::SLL), ValReg).addReg(ValReg).addReg(ShamtReg); + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGE)).addReg(IncrReg).addReg(Scratch2Reg).addMBB(LoopTailMBB); + break; + } + case AtomicRMWInst::UMax: + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGEU)).addReg(Scratch2Reg).addReg(IncrReg).addMBB(LoopTailMBB); + break; + case AtomicRMWInst::UMin: + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGEU)).addReg(IncrReg).addReg(Scratch2Reg).addMBB(LoopTailMBB); + break; + } + assert(OldValReg != ScratchReg && "OldValReg and ScratchReg must be unique"); + assert(OldValReg != MaskReg && "OldValReg and MaskReg must be unique"); + assert(ScratchReg != MaskReg && "ScratchReg and MaskReg must be unique"); + BuildMI(MBB, DL, TII->get(RISCV::XOR), ScratchReg).addReg(OldValReg).addReg(NewValReg); + BuildMI(MBB, DL, TII->get(RISCV::AND), ScratchReg).addReg(ScratchReg).addReg(MaskReg); + BuildMI(MBB, DL, TII->get(RISCV::XOR), DestReg).addReg(OldValReg).addReg(ScratchReg); + BuildMI(LoopTailMBB, DL, TII->get(getSCForRMW32(Ordering)), Scratch1Reg).addReg(AddrReg).addReg(Scratch1Reg); + BuildMI(LoopTailMBB, DL, TII->get(RISCV::BNE)).addReg(Scratch1Reg).addReg(RISCV::X0).addMBB(LoopHeadMBB); + NextMBBI = MBB.end(); + MI.eraseFromParent(); + LivePhysRegs LiveRegs; + computeAndAddLiveIns(LiveRegs, *LoopHeadMBB); + computeAndAddLiveIns(LiveRegs, *LoopIfBodyMBB); + computeAndAddLiveIns(LiveRegs, *LoopTailMBB); + computeAndAddLiveIns(LiveRegs, *DoneMBB); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoMaskedAtomicLoadUMin32) { + assert(IsMasked == true && "Should only need to expand masked atomic max/min"); + assert(Width == 32 && "Should never need to expand masked 64-bit operations"); + MachineInstr &MI = *MBBI; + DebugLoc DL = MI.getDebugLoc(); + MachineFunction *MF = MBB.getParent(); + auto LoopHeadMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + auto LoopIfBodyMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + auto LoopTailMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + auto DoneMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + MF->insert(++MBB.getIterator(), LoopHeadMBB); + MF->insert(++LoopHeadMBB->getIterator(), LoopIfBodyMBB); + MF->insert(++LoopIfBodyMBB->getIterator(), LoopTailMBB); + MF->insert(++LoopTailMBB->getIterator(), DoneMBB); + LoopHeadMBB->addSuccessor(LoopIfBodyMBB); + LoopHeadMBB->addSuccessor(LoopTailMBB); + LoopIfBodyMBB->addSuccessor(LoopTailMBB); + LoopTailMBB->addSuccessor(LoopHeadMBB); + LoopTailMBB->addSuccessor(DoneMBB); + DoneMBB->splice(DoneMBB->end(), &MBB, MI, MBB.end()); + DoneMBB->transferSuccessors(&MBB); + MBB.addSuccessor(LoopHeadMBB); + Register DestReg = MI.getOperand(0).getReg(); + Register Scratch1Reg = MI.getOperand(1).getReg(); + Register Scratch2Reg = MI.getOperand(2).getReg(); + Register AddrReg = MI.getOperand(3).getReg(); + Register IncrReg = MI.getOperand(4).getReg(); + Register MaskReg = MI.getOperand(5).getReg(); + bool IsSigned = BinOp == AtomicRMWInst::Min || BinOp == AtomicRMWInst::Max; + AtomicOrdering Ordering = static_cast(MI.getOperand(IsSigned ? 7 : 6).getImm()); + BuildMI(LoopHeadMBB, DL, TII->get(getLRForRMW32(Ordering)), DestReg).addReg(AddrReg); + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::AND), Scratch2Reg).addReg(DestReg).addReg(MaskReg); + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::ADDI), Scratch1Reg).addReg(DestReg).addImm(0); + switch (BinOp) { + default: + llvm_unreachable("Unexpected AtomicRMW BinOp"); + case AtomicRMWInst::Max: { + BuildMI(MBB, DL, TII->get(RISCV::SLL), ValReg).addReg(ValReg).addReg(ShamtReg); + BuildMI(MBB, DL, TII->get(RISCV::SRA), ValReg).addReg(ValReg).addReg(ShamtReg); + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGE)).addReg(Scratch2Reg).addReg(IncrReg).addMBB(LoopTailMBB); + break; + } + case AtomicRMWInst::Min: { + BuildMI(MBB, DL, TII->get(RISCV::SLL), ValReg).addReg(ValReg).addReg(ShamtReg); + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGE)).addReg(IncrReg).addReg(Scratch2Reg).addMBB(LoopTailMBB); + break; + } + case AtomicRMWInst::UMax: + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGEU)).addReg(Scratch2Reg).addReg(IncrReg).addMBB(LoopTailMBB); + break; + case AtomicRMWInst::UMin: + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGEU)).addReg(IncrReg).addReg(Scratch2Reg).addMBB(LoopTailMBB); + break; + } + assert(OldValReg != ScratchReg && "OldValReg and ScratchReg must be unique"); + assert(OldValReg != MaskReg && "OldValReg and MaskReg must be unique"); + assert(ScratchReg != MaskReg && "ScratchReg and MaskReg must be unique"); + BuildMI(MBB, DL, TII->get(RISCV::XOR), ScratchReg).addReg(OldValReg).addReg(NewValReg); + BuildMI(MBB, DL, TII->get(RISCV::AND), ScratchReg).addReg(ScratchReg).addReg(MaskReg); + BuildMI(MBB, DL, TII->get(RISCV::XOR), DestReg).addReg(OldValReg).addReg(ScratchReg); + BuildMI(LoopTailMBB, DL, TII->get(getSCForRMW32(Ordering)), Scratch1Reg).addReg(AddrReg).addReg(Scratch1Reg); + BuildMI(LoopTailMBB, DL, TII->get(RISCV::BNE)).addReg(Scratch1Reg).addReg(RISCV::X0).addMBB(LoopHeadMBB); + NextMBBI = MBB.end(); + MI.eraseFromParent(); + LivePhysRegs LiveRegs; + computeAndAddLiveIns(LiveRegs, *LoopHeadMBB); + computeAndAddLiveIns(LiveRegs, *LoopIfBodyMBB); + computeAndAddLiveIns(LiveRegs, *LoopTailMBB); + computeAndAddLiveIns(LiveRegs, *DoneMBB); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoCmpXchg32) { + MachineInstr &MI = *MBBI; + DebugLoc DL = MI.getDebugLoc(); + MachineFunction *MF = MBB.getParent(); + auto LoopHeadMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + auto LoopTailMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + auto DoneMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + MF->insert(++MBB.getIterator(), LoopHeadMBB); + MF->insert(++LoopHeadMBB->getIterator(), LoopTailMBB); + MF->insert(++LoopTailMBB->getIterator(), DoneMBB); + LoopHeadMBB->addSuccessor(LoopTailMBB); + LoopHeadMBB->addSuccessor(DoneMBB); + LoopTailMBB->addSuccessor(DoneMBB); + LoopTailMBB->addSuccessor(LoopHeadMBB); + DoneMBB->splice(DoneMBB->end(), &MBB, MI, MBB.end()); + DoneMBB->transferSuccessors(&MBB); + MBB.addSuccessor(LoopHeadMBB); + Register DestReg = MI.getOperand(0).getReg(); + Register ScratchReg = MI.getOperand(1).getReg(); + Register AddrReg = MI.getOperand(2).getReg(); + Register CmpValReg = MI.getOperand(3).getReg(); + Register NewValReg = MI.getOperand(4).getReg(); + AtomicOrdering Ordering = static_cast(MI.getOperand(IsMasked ? 6 : 5).getImm()); + if (!IsMasked) { + BuildMI(LoopHeadMBB, DL, TII->get(getLRForRMW(Ordering, Width)), DestReg).addReg(AddrReg); + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BNE)).addReg(DestReg).addReg(CmpValReg).addMBB(DoneMBB); + BuildMI(LoopTailMBB, DL, TII->get(getSCForRMW(Ordering, Width)), ScratchReg).addReg(AddrReg).addReg(NewValReg); + BuildMI(LoopTailMBB, DL, TII->get(RISCV::BNE)).addReg(ScratchReg).addReg(RISCV::X0).addMBB(LoopHeadMBB); + } + else { + Register MaskReg = MI.getOperand(5).getReg(); + BuildMI(LoopHeadMBB, DL, TII->get(getLRForRMW(Ordering, Width)), DestReg).addReg(AddrReg); + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::AND), ScratchReg).addReg(DestReg).addReg(MaskReg); + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BNE)).addReg(ScratchReg).addReg(CmpValReg).addMBB(DoneMBB); + assert(OldValReg != ScratchReg && "OldValReg and ScratchReg must be unique"); + assert(OldValReg != MaskReg && "OldValReg and MaskReg must be unique"); + assert(ScratchReg != MaskReg && "ScratchReg and MaskReg must be unique"); + BuildMI(MBB, DL, TII->get(RISCV::XOR), ScratchReg).addReg(OldValReg).addReg(NewValReg); + BuildMI(MBB, DL, TII->get(RISCV::AND), ScratchReg).addReg(ScratchReg).addReg(MaskReg); + BuildMI(MBB, DL, TII->get(RISCV::XOR), DestReg).addReg(OldValReg).addReg(ScratchReg); + BuildMI(LoopTailMBB, DL, TII->get(getSCForRMW(Ordering, Width)), ScratchReg).addReg(AddrReg).addReg(ScratchReg); + BuildMI(LoopTailMBB, DL, TII->get(RISCV::BNE)).addReg(ScratchReg).addReg(RISCV::X0).addMBB(LoopHeadMBB); + } + NextMBBI = MBB.end(); + MI.eraseFromParent(); + LivePhysRegs LiveRegs; + computeAndAddLiveIns(LiveRegs, *LoopHeadMBB); + computeAndAddLiveIns(LiveRegs, *LoopTailMBB); + computeAndAddLiveIns(LiveRegs, *DoneMBB); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoCmpXchg64) { + MachineInstr &MI = *MBBI; + DebugLoc DL = MI.getDebugLoc(); + MachineFunction *MF = MBB.getParent(); + auto LoopHeadMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + auto LoopTailMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + auto DoneMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + MF->insert(++MBB.getIterator(), LoopHeadMBB); + MF->insert(++LoopHeadMBB->getIterator(), LoopTailMBB); + MF->insert(++LoopTailMBB->getIterator(), DoneMBB); + LoopHeadMBB->addSuccessor(LoopTailMBB); + LoopHeadMBB->addSuccessor(DoneMBB); + LoopTailMBB->addSuccessor(DoneMBB); + LoopTailMBB->addSuccessor(LoopHeadMBB); + DoneMBB->splice(DoneMBB->end(), &MBB, MI, MBB.end()); + DoneMBB->transferSuccessors(&MBB); + MBB.addSuccessor(LoopHeadMBB); + Register DestReg = MI.getOperand(0).getReg(); + Register ScratchReg = MI.getOperand(1).getReg(); + Register AddrReg = MI.getOperand(2).getReg(); + Register CmpValReg = MI.getOperand(3).getReg(); + Register NewValReg = MI.getOperand(4).getReg(); + AtomicOrdering Ordering = static_cast(MI.getOperand(IsMasked ? 6 : 5).getImm()); + if (!IsMasked) { + BuildMI(LoopHeadMBB, DL, TII->get(getLRForRMW(Ordering, Width)), DestReg).addReg(AddrReg); + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BNE)).addReg(DestReg).addReg(CmpValReg).addMBB(DoneMBB); + BuildMI(LoopTailMBB, DL, TII->get(getSCForRMW(Ordering, Width)), ScratchReg).addReg(AddrReg).addReg(NewValReg); + BuildMI(LoopTailMBB, DL, TII->get(RISCV::BNE)).addReg(ScratchReg).addReg(RISCV::X0).addMBB(LoopHeadMBB); + } + else { + Register MaskReg = MI.getOperand(5).getReg(); + BuildMI(LoopHeadMBB, DL, TII->get(getLRForRMW(Ordering, Width)), DestReg).addReg(AddrReg); + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::AND), ScratchReg).addReg(DestReg).addReg(MaskReg); + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BNE)).addReg(ScratchReg).addReg(CmpValReg).addMBB(DoneMBB); + assert(OldValReg != ScratchReg && "OldValReg and ScratchReg must be unique"); + assert(OldValReg != MaskReg && "OldValReg and MaskReg must be unique"); + assert(ScratchReg != MaskReg && "ScratchReg and MaskReg must be unique"); + BuildMI(MBB, DL, TII->get(RISCV::XOR), ScratchReg).addReg(OldValReg).addReg(NewValReg); + BuildMI(MBB, DL, TII->get(RISCV::AND), ScratchReg).addReg(ScratchReg).addReg(MaskReg); + BuildMI(MBB, DL, TII->get(RISCV::XOR), DestReg).addReg(OldValReg).addReg(ScratchReg); + BuildMI(LoopTailMBB, DL, TII->get(getSCForRMW(Ordering, Width)), ScratchReg).addReg(AddrReg).addReg(ScratchReg); + BuildMI(LoopTailMBB, DL, TII->get(RISCV::BNE)).addReg(ScratchReg).addReg(RISCV::X0).addMBB(LoopHeadMBB); + } + NextMBBI = MBB.end(); + MI.eraseFromParent(); + LivePhysRegs LiveRegs; + computeAndAddLiveIns(LiveRegs, *LoopHeadMBB); + computeAndAddLiveIns(LiveRegs, *LoopTailMBB); + computeAndAddLiveIns(LiveRegs, *DoneMBB); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoMaskedCmpXchg32) { + MachineInstr &MI = *MBBI; + DebugLoc DL = MI.getDebugLoc(); + MachineFunction *MF = MBB.getParent(); + auto LoopHeadMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + auto LoopTailMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + auto DoneMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + MF->insert(++MBB.getIterator(), LoopHeadMBB); + MF->insert(++LoopHeadMBB->getIterator(), LoopTailMBB); + MF->insert(++LoopTailMBB->getIterator(), DoneMBB); + LoopHeadMBB->addSuccessor(LoopTailMBB); + LoopHeadMBB->addSuccessor(DoneMBB); + LoopTailMBB->addSuccessor(DoneMBB); + LoopTailMBB->addSuccessor(LoopHeadMBB); + DoneMBB->splice(DoneMBB->end(), &MBB, MI, MBB.end()); + DoneMBB->transferSuccessors(&MBB); + MBB.addSuccessor(LoopHeadMBB); + Register DestReg = MI.getOperand(0).getReg(); + Register ScratchReg = MI.getOperand(1).getReg(); + Register AddrReg = MI.getOperand(2).getReg(); + Register CmpValReg = MI.getOperand(3).getReg(); + Register NewValReg = MI.getOperand(4).getReg(); + AtomicOrdering Ordering = static_cast(MI.getOperand(IsMasked ? 6 : 5).getImm()); + if (!IsMasked) { + BuildMI(LoopHeadMBB, DL, TII->get(getLRForRMW(Ordering, Width)), DestReg).addReg(AddrReg); + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BNE)).addReg(DestReg).addReg(CmpValReg).addMBB(DoneMBB); + BuildMI(LoopTailMBB, DL, TII->get(getSCForRMW(Ordering, Width)), ScratchReg).addReg(AddrReg).addReg(NewValReg); + BuildMI(LoopTailMBB, DL, TII->get(RISCV::BNE)).addReg(ScratchReg).addReg(RISCV::X0).addMBB(LoopHeadMBB); + } + else { + Register MaskReg = MI.getOperand(5).getReg(); + BuildMI(LoopHeadMBB, DL, TII->get(getLRForRMW(Ordering, Width)), DestReg).addReg(AddrReg); + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::AND), ScratchReg).addReg(DestReg).addReg(MaskReg); + BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BNE)).addReg(ScratchReg).addReg(CmpValReg).addMBB(DoneMBB); + assert(OldValReg != ScratchReg && "OldValReg and ScratchReg must be unique"); + assert(OldValReg != MaskReg && "OldValReg and MaskReg must be unique"); + assert(ScratchReg != MaskReg && "ScratchReg and MaskReg must be unique"); + BuildMI(MBB, DL, TII->get(RISCV::XOR), ScratchReg).addReg(OldValReg).addReg(NewValReg); + BuildMI(MBB, DL, TII->get(RISCV::AND), ScratchReg).addReg(ScratchReg).addReg(MaskReg); + BuildMI(MBB, DL, TII->get(RISCV::XOR), DestReg).addReg(OldValReg).addReg(ScratchReg); + BuildMI(LoopTailMBB, DL, TII->get(getSCForRMW(Ordering, Width)), ScratchReg).addReg(AddrReg).addReg(ScratchReg); + BuildMI(LoopTailMBB, DL, TII->get(RISCV::BNE)).addReg(ScratchReg).addReg(RISCV::X0).addMBB(LoopHeadMBB); + } + NextMBBI = MBB.end(); + MI.eraseFromParent(); + LivePhysRegs LiveRegs; + computeAndAddLiveIns(LiveRegs, *LoopHeadMBB); + computeAndAddLiveIns(LiveRegs, *LoopTailMBB); + computeAndAddLiveIns(LiveRegs, *DoneMBB); + return true; + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/ExpandAtomicPseudoInsts/getPassName.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/ExpandAtomicPseudoInsts/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..be55c65dfca4dd0ed4321f773d46c7d6e86200c4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/ExpandAtomicPseudoInsts/getPassName.cpp @@ -0,0 +1,3 @@ +StringRef getPassName() const override { + return RISCV_EXPAND_ATOMIC_PSEUDO_NAME; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/ExpandAtomicPseudoInsts/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/ExpandAtomicPseudoInsts/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fd6bfc81864cf513dbe24e299d2cc82c81f36b27 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/ExpandAtomicPseudoInsts/runOnMachineFunction.cpp @@ -0,0 +1,8 @@ +bool RISCVExpandAtomicPseudo::runOnMachineFunction(MachineFunction &MF) { + TII = static_cast(MF.getSubtarget().getInstrInfo()); + bool Modified = false; + for (auto &MBB : MF) { + Modified |= expandMBB(MBB); + } + return Modified; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/ExpandPseudoInsts/ExpandPseudo.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/ExpandPseudoInsts/ExpandPseudo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..619ea5f1fb6cf92b77a790a42642051fc3450f92 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/ExpandPseudoInsts/ExpandPseudo.cpp @@ -0,0 +1,3 @@ +RISCVExpandPseudo() : MachineFunctionPass(ID) { + initializeRISCVExpandPseudoPass(*PassRegistry::getPassRegistry()); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/ExpandPseudoInsts/createPass.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/ExpandPseudoInsts/createPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..207e3c11c810551063e0c2b55a3d9af32a794d7b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/ExpandPseudoInsts/createPass.cpp @@ -0,0 +1,3 @@ +FunctionPass *createRISCVExpandPseudoPass() { + return new RISCVExpandPseudo(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/ExpandPseudoInsts/expandMBB.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/ExpandPseudoInsts/expandMBB.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bf9fe048bfd2dbdd4940122bf6e54f65401af7df --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/ExpandPseudoInsts/expandMBB.cpp @@ -0,0 +1,10 @@ +bool RISCVExpandPseudo::expandMBB(MachineBasicBlock &MBB) { + bool Modified = false; + MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end(); + while (MBBI != E) { + MachineBasicBlock::iterator NMBBI = std::next(MBBI); + Modified |= expandMI(MBB, MBBI, NMBBI); + MBBI = NMBBI; + } + return Modified; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/ExpandPseudoInsts/expandMI.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/ExpandPseudoInsts/expandMI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4df12ee0ca8495e367ac08772bf8cade7d1a7463 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/ExpandPseudoInsts/expandMI.cpp @@ -0,0 +1,243 @@ +bool RISCVExpandPseudo::expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, MachineBasicBlock::iterator &NextMBBI) { + if (MBBI->getOpcode() == RISCV::PseudoLLA) { + MachineFunction *MF = MBB.getParent(); + MachineInstr &MI = *MBBI; + DebugLoc DL = MI.getDebugLoc(); + Register DestReg = MI.getOperand(0).getReg(); + const MachineOperand &Symbol = MI.getOperand(1); + MachineBasicBlock *NewMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + NewMBB->setLabelMustBeEmitted(); + MF->insert(++MBB.getIterator(), NewMBB); + BuildMI(NewMBB, DL, TII->get(RISCV::AUIPC), DestReg).addDisp(Symbol, 0, FlagsHi); + BuildMI(NewMBB, DL, TII->get(SecondOpcode), DestReg).addReg(DestReg).addMBB(NewMBB, RISCVII::MO_PCREL_LO); + NewMBB->splice(NewMBB->end(), &MBB, std::next(MBBI), MBB.end()); + NewMBB->transferSuccessorsAndUpdatePHIs(&MBB); + MBB.addSuccessor(NewMBB); + LivePhysRegs LiveRegs; + computeAndAddLiveIns(LiveRegs, *NewMBB); + NextMBBI = MBB.end(); + MI.eraseFromParent(); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoLA) { + MachineFunction *MF = MBB.getParent(); + unsigned SecondOpcode; + unsigned FlagsHi; + if (MF->getTarget().isPositionIndependent()) { + const auto &STI = MF->getSubtarget(); + SecondOpcode = STI.is64Bit() ? RISCV::LD : RISCV::LW; + FlagsHi = RISCVII::MO_GOT_HI; + } + else { + SecondOpcode = RISCV::ADDI; + FlagsHi = RISCVII::MO_PCREL_HI; + } + MachineFunction *MF = MBB.getParent(); + MachineInstr &MI = *MBBI; + DebugLoc DL = MI.getDebugLoc(); + Register DestReg = MI.getOperand(0).getReg(); + const MachineOperand &Symbol = MI.getOperand(1); + MachineBasicBlock *NewMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + NewMBB->setLabelMustBeEmitted(); + MF->insert(++MBB.getIterator(), NewMBB); + BuildMI(NewMBB, DL, TII->get(RISCV::AUIPC), DestReg).addDisp(Symbol, 0, FlagsHi); + BuildMI(NewMBB, DL, TII->get(SecondOpcode), DestReg).addReg(DestReg).addMBB(NewMBB, RISCVII::MO_PCREL_LO); + NewMBB->splice(NewMBB->end(), &MBB, std::next(MBBI), MBB.end()); + NewMBB->transferSuccessorsAndUpdatePHIs(&MBB); + MBB.addSuccessor(NewMBB); + LivePhysRegs LiveRegs; + computeAndAddLiveIns(LiveRegs, *NewMBB); + NextMBBI = MBB.end(); + MI.eraseFromParent(); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoLA_TLS_IE) { + const auto &STI = MF->getSubtarget(); + unsigned SecondOpcode = STI.is64Bit() ? RISCV::LD : RISCV::LW; + MachineFunction *MF = MBB.getParent(); + MachineInstr &MI = *MBBI; + DebugLoc DL = MI.getDebugLoc(); + Register DestReg = MI.getOperand(0).getReg(); + const MachineOperand &Symbol = MI.getOperand(1); + MachineBasicBlock *NewMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + NewMBB->setLabelMustBeEmitted(); + MF->insert(++MBB.getIterator(), NewMBB); + BuildMI(NewMBB, DL, TII->get(RISCV::AUIPC), DestReg).addDisp(Symbol, 0, FlagsHi); + BuildMI(NewMBB, DL, TII->get(SecondOpcode), DestReg).addReg(DestReg).addMBB(NewMBB, RISCVII::MO_PCREL_LO); + NewMBB->splice(NewMBB->end(), &MBB, std::next(MBBI), MBB.end()); + NewMBB->transferSuccessorsAndUpdatePHIs(&MBB); + MBB.addSuccessor(NewMBB); + LivePhysRegs LiveRegs; + computeAndAddLiveIns(LiveRegs, *NewMBB); + NextMBBI = MBB.end(); + MI.eraseFromParent(); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoLA_TLS_GD) { + MachineFunction *MF = MBB.getParent(); + MachineInstr &MI = *MBBI; + DebugLoc DL = MI.getDebugLoc(); + Register DestReg = MI.getOperand(0).getReg(); + const MachineOperand &Symbol = MI.getOperand(1); + MachineBasicBlock *NewMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock()); + NewMBB->setLabelMustBeEmitted(); + MF->insert(++MBB.getIterator(), NewMBB); + BuildMI(NewMBB, DL, TII->get(RISCV::AUIPC), DestReg).addDisp(Symbol, 0, FlagsHi); + BuildMI(NewMBB, DL, TII->get(SecondOpcode), DestReg).addReg(DestReg).addMBB(NewMBB, RISCVII::MO_PCREL_LO); + NewMBB->splice(NewMBB->end(), &MBB, std::next(MBBI), MBB.end()); + NewMBB->transferSuccessorsAndUpdatePHIs(&MBB); + MBB.addSuccessor(NewMBB); + LivePhysRegs LiveRegs; + computeAndAddLiveIns(LiveRegs, *NewMBB); + NextMBBI = MBB.end(); + MI.eraseFromParent(); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoVSETVLI) { + assert(MBBI->getNumOperands() == 5 && "Unexpected instruction format"); + DebugLoc DL = MBBI->getDebugLoc(); + assert((MBBI->getOpcode() == RISCV::PseudoVSETVLI || MBBI->getOpcode() == RISCV::PseudoVSETIVLI) && "Unexpected pseudo instruction"); + unsigned Opcode; + if (MBBI->getOpcode() == RISCV::PseudoVSETVLI) + Opcode = RISCV::VSETVLI; + else + Opcode = RISCV::VSETIVLI; + const MCInstrDesc &Desc = TII->get(Opcode); + assert(Desc.getNumOperands() == 3 && "Unexpected instruction format"); + Register DstReg = MBBI->getOperand(0).getReg(); + bool DstIsDead = MBBI->getOperand(0).isDead(); + BuildMI(MBB, MBBI, DL, Desc).addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)).add(MBBI->getOperand(1)).add(MBBI->getOperand(2)); + MBBI->eraseFromParent(); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoVSETIVLI) { + assert(MBBI->getNumOperands() == 5 && "Unexpected instruction format"); + DebugLoc DL = MBBI->getDebugLoc(); + assert((MBBI->getOpcode() == RISCV::PseudoVSETVLI || MBBI->getOpcode() == RISCV::PseudoVSETIVLI) && "Unexpected pseudo instruction"); + unsigned Opcode; + if (MBBI->getOpcode() == RISCV::PseudoVSETVLI) + Opcode = RISCV::VSETVLI; + else + Opcode = RISCV::VSETIVLI; + const MCInstrDesc &Desc = TII->get(Opcode); + assert(Desc.getNumOperands() == 3 && "Unexpected instruction format"); + Register DstReg = MBBI->getOperand(0).getReg(); + bool DstIsDead = MBBI->getOperand(0).isDead(); + BuildMI(MBB, MBBI, DL, Desc).addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)).add(MBBI->getOperand(1)).add(MBBI->getOperand(2)); + MBBI->eraseFromParent(); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoVMCLR_M_B1) { + DebugLoc DL = MBBI->getDebugLoc(); + Register DstReg = MBBI->getOperand(0).getReg(); + const MCInstrDesc &Desc = TII->get(Opcode); + BuildMI(MBB, MBBI, DL, Desc, DstReg).addReg(DstReg, RegState::Undef).addReg(DstReg, RegState::Undef); + MBBI->eraseFromParent(); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoVMCLR_M_B2) { + DebugLoc DL = MBBI->getDebugLoc(); + Register DstReg = MBBI->getOperand(0).getReg(); + const MCInstrDesc &Desc = TII->get(Opcode); + BuildMI(MBB, MBBI, DL, Desc, DstReg).addReg(DstReg, RegState::Undef).addReg(DstReg, RegState::Undef); + MBBI->eraseFromParent(); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoVMCLR_M_B4) { + DebugLoc DL = MBBI->getDebugLoc(); + Register DstReg = MBBI->getOperand(0).getReg(); + const MCInstrDesc &Desc = TII->get(Opcode); + BuildMI(MBB, MBBI, DL, Desc, DstReg).addReg(DstReg, RegState::Undef).addReg(DstReg, RegState::Undef); + MBBI->eraseFromParent(); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoVMCLR_M_B8) { + DebugLoc DL = MBBI->getDebugLoc(); + Register DstReg = MBBI->getOperand(0).getReg(); + const MCInstrDesc &Desc = TII->get(Opcode); + BuildMI(MBB, MBBI, DL, Desc, DstReg).addReg(DstReg, RegState::Undef).addReg(DstReg, RegState::Undef); + MBBI->eraseFromParent(); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoVMCLR_M_B16) { + DebugLoc DL = MBBI->getDebugLoc(); + Register DstReg = MBBI->getOperand(0).getReg(); + const MCInstrDesc &Desc = TII->get(Opcode); + BuildMI(MBB, MBBI, DL, Desc, DstReg).addReg(DstReg, RegState::Undef).addReg(DstReg, RegState::Undef); + MBBI->eraseFromParent(); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoVMCLR_M_B32) { + DebugLoc DL = MBBI->getDebugLoc(); + Register DstReg = MBBI->getOperand(0).getReg(); + const MCInstrDesc &Desc = TII->get(Opcode); + BuildMI(MBB, MBBI, DL, Desc, DstReg).addReg(DstReg, RegState::Undef).addReg(DstReg, RegState::Undef); + MBBI->eraseFromParent(); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoVMCLR_M_B64) { + DebugLoc DL = MBBI->getDebugLoc(); + Register DstReg = MBBI->getOperand(0).getReg(); + const MCInstrDesc &Desc = TII->get(Opcode); + BuildMI(MBB, MBBI, DL, Desc, DstReg).addReg(DstReg, RegState::Undef).addReg(DstReg, RegState::Undef); + MBBI->eraseFromParent(); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoVMSET_M_B1) { + DebugLoc DL = MBBI->getDebugLoc(); + Register DstReg = MBBI->getOperand(0).getReg(); + const MCInstrDesc &Desc = TII->get(Opcode); + BuildMI(MBB, MBBI, DL, Desc, DstReg).addReg(DstReg, RegState::Undef).addReg(DstReg, RegState::Undef); + MBBI->eraseFromParent(); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoVMSET_M_B2) { + DebugLoc DL = MBBI->getDebugLoc(); + Register DstReg = MBBI->getOperand(0).getReg(); + const MCInstrDesc &Desc = TII->get(Opcode); + BuildMI(MBB, MBBI, DL, Desc, DstReg).addReg(DstReg, RegState::Undef).addReg(DstReg, RegState::Undef); + MBBI->eraseFromParent(); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoVMSET_M_B4) { + DebugLoc DL = MBBI->getDebugLoc(); + Register DstReg = MBBI->getOperand(0).getReg(); + const MCInstrDesc &Desc = TII->get(Opcode); + BuildMI(MBB, MBBI, DL, Desc, DstReg).addReg(DstReg, RegState::Undef).addReg(DstReg, RegState::Undef); + MBBI->eraseFromParent(); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoVMSET_M_B8) { + DebugLoc DL = MBBI->getDebugLoc(); + Register DstReg = MBBI->getOperand(0).getReg(); + const MCInstrDesc &Desc = TII->get(Opcode); + BuildMI(MBB, MBBI, DL, Desc, DstReg).addReg(DstReg, RegState::Undef).addReg(DstReg, RegState::Undef); + MBBI->eraseFromParent(); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoVMSET_M_B16) { + DebugLoc DL = MBBI->getDebugLoc(); + Register DstReg = MBBI->getOperand(0).getReg(); + const MCInstrDesc &Desc = TII->get(Opcode); + BuildMI(MBB, MBBI, DL, Desc, DstReg).addReg(DstReg, RegState::Undef).addReg(DstReg, RegState::Undef); + MBBI->eraseFromParent(); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoVMSET_M_B32) { + DebugLoc DL = MBBI->getDebugLoc(); + Register DstReg = MBBI->getOperand(0).getReg(); + const MCInstrDesc &Desc = TII->get(Opcode); + BuildMI(MBB, MBBI, DL, Desc, DstReg).addReg(DstReg, RegState::Undef).addReg(DstReg, RegState::Undef); + MBBI->eraseFromParent(); + return true; + } + if (MBBI->getOpcode() == RISCV::PseudoVMSET_M_B64) { + DebugLoc DL = MBBI->getDebugLoc(); + Register DstReg = MBBI->getOperand(0).getReg(); + const MCInstrDesc &Desc = TII->get(Opcode); + BuildMI(MBB, MBBI, DL, Desc, DstReg).addReg(DstReg, RegState::Undef).addReg(DstReg, RegState::Undef); + MBBI->eraseFromParent(); + return true; + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/ExpandPseudoInsts/getPassName.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/ExpandPseudoInsts/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f746343de8bcbf0ec410bfee6eabf7dde8e37c4b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/ExpandPseudoInsts/getPassName.cpp @@ -0,0 +1,3 @@ +StringRef getPassName() const override { + return RISCV_EXPAND_PSEUDO_NAME; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/ExpandPseudoInsts/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/ExpandPseudoInsts/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3c3b6dc2dce658992de0bfbde1b5323b33b24ebb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/ExpandPseudoInsts/runOnMachineFunction.cpp @@ -0,0 +1,8 @@ +bool RISCVExpandPseudo::runOnMachineFunction(MachineFunction &MF) { + TII = static_cast(MF.getSubtarget().getInstrInfo()); + bool Modified = false; + for (auto &MBB : MF) { + Modified |= expandMBB(MBB); + } + return Modified; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/MergeBaseOffset/MergeBaseOffsetOpt.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/MergeBaseOffset/MergeBaseOffsetOpt.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0335a4ef79ccad687d71bd1e7dfc446f4a07fe4b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/MergeBaseOffset/MergeBaseOffsetOpt.cpp @@ -0,0 +1,2 @@ +RISCVMergeBaseOffsetOpt() : MachineFunctionPass(ID) { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/MergeBaseOffset/createPass.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/MergeBaseOffset/createPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4f8195dd1360a5a7264e251088fea5e7dbc2d24d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/MergeBaseOffset/createPass.cpp @@ -0,0 +1,3 @@ +FunctionPass *llvm::createRISCVMergeBaseOffsetOptPass() { + return new RISCVMergeBaseOffsetOpt(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/MergeBaseOffset/getPassName.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/MergeBaseOffset/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..658f61cc76c6f58d97dbc4a3fa9d383799c42b6e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/MergeBaseOffset/getPassName.cpp @@ -0,0 +1,3 @@ +StringRef getPassName() const override { + return RISCV_MERGE_BASE_OFFSET_NAME; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/MergeBaseOffset/getRequiredProperties.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/MergeBaseOffset/getRequiredProperties.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b5b9c0930d3d58a2f4601a4830a241ebb30ca4fd --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/MergeBaseOffset/getRequiredProperties.cpp @@ -0,0 +1,3 @@ +MachineFunctionProperties getRequiredProperties() const override { + return MachineFunctionProperties().set(MachineFunctionProperties::Property::IsSSA); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/MergeBaseOffset/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/MergeBaseOffset/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..644005710c1b1a6bbf091cf43572a6d616d21b78 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Optimization/MergeBaseOffset/runOnMachineFunction.cpp @@ -0,0 +1,121 @@ +bool RISCVMergeBaseOffsetOpt::runOnMachineFunction(MachineFunction &Fn) { + if (skipFunction(*F.getFunction())) { + return false; + } + DeadInstrs.clear(); + MRI = &Fn.getRegInfo(); + for (MachineBasicBlock &MBB : Fn) { + LLVM_DEBUG(dbgs() << "MBB: " << MBB.getName() << "\n"); + for (MachineInstr &HiLUI : MBB) { + MachineInstr *LoADDI = nullptr; + if (HiLUI.getOpcode() != RISCV::LUI || HiLUI.getOperand(1).getTargetFlags() != RISCVII::MO_HI || HiLUI.getOperand(1).getType() != MachineOperand::MO_GlobalAddress || HiLUI.getOperand(1).getOffset() != 0 || !MRI->hasOneUse(HiLUI.getOperand(0).getReg())) + return false; + Register HiLuiDestReg = HiLUI.getOperand(0).getReg(); + LoADDI = MRI->use_begin(HiLuiDestReg)->getParent(); + if (LoADDI->getOpcode() != RISCV::ADDI || LoADDI->getOperand(2).getTargetFlags() != RISCVII::MO_LO || LoADDI->getOperand(2).getType() != MachineOperand::MO_GlobalAddress || LoADDI->getOperand(2).getOffset() != 0 || !MRI->hasOneUse(LoADDI->getOperand(0).getReg())) + return false; + continue + LLVM_DEBUG(dbgs() << " Found lowered global address with one use: " << *LoADDI->getOperand(2).getGlobal() << "\n"); + Register DestReg = LoADDI.getOperand(0).getReg(); + assert(MRI->hasOneUse(DestReg) && "expected one use for LoADDI"); + MachineInstr &Tail = *MRI->use_begin(DestReg)->getParent(); + switch (Tail.getOpcode()) { + default: + LLVM_DEBUG(dbgs() << "Don't know how to get offset from this instr:" << Tail); + return false; + case RISCV::ADDI: { + int64_t Offset = Tail.getOperand(2).getImm(); + LLVM_DEBUG(dbgs() << " Offset Instr: " << Tail); + HiLUI.getOperand(1).setOffset(Offset); + LoADDI.getOperand(2).setOffset(Offset); + DeadInstrs.insert(&Tail); + MRI->replaceRegWith(Tail.getOperand(0).getReg(), LoADDI.getOperand(0).getReg()); + LLVM_DEBUG(dbgs() << " Merged offset " << Offset << " into base.\n" << " " << HiLUI << " " << LoADDI;); + return true; + } break; + case RISCV::ADD: { + int64_t Offset; + assert((TailAdd.getOpcode() == RISCV::ADD) && "Expected ADD instruction!"); + Register Rs = TailAdd.getOperand(1).getReg(); + Register Rt = TailAdd.getOperand(2).getReg(); + Register Reg = Rs == GAReg ? Rt : Rs; + if (!MRI->hasOneUse(Reg)) + return false; + MachineInstr &OffsetTail = *MRI->getVRegDef(Reg); + if (OffsetTail.getOpcode() == RISCV::ADDI) { + MachineOperand &AddiImmOp = OffsetTail.getOperand(2); + if (AddiImmOp.getTargetFlags() != RISCVII::MO_None) + return false; + int64_t OffLo = AddiImmOp.getImm(); + MachineInstr &OffsetLui = *MRI->getVRegDef(OffsetTail.getOperand(1).getReg()); + MachineOperand &LuiImmOp = OffsetLui.getOperand(1); + if (OffsetLui.getOpcode() != RISCV::LUI || LuiImmOp.getTargetFlags() != RISCVII::MO_None || !MRI->hasOneUse(OffsetLui.getOperand(0).getReg())) + return false; + int64_t OffHi = OffsetLui.getOperand(1).getImm(); + Offset = (OffHi << 12) + OffLo; + LLVM_DEBUG(dbgs() << " Offset Instrs: " << OffsetTail << " " << OffsetLui); + DeadInstrs.insert(&OffsetTail); + DeadInstrs.insert(&OffsetLui); + return true; + } + else if (OffsetTail.getOpcode() == RISCV::LUI) { + LLVM_DEBUG(dbgs() << " Offset Instr: " << OffsetTail); + Offset = OffsetTail.getOperand(1).getImm() << 12; + DeadInstrs.insert(&OffsetTail); + return true; + } + return false; + if (!matchLargeOffset(Tail, DestReg, Offset)) { + return false; + } + HiLUI.getOperand(1).setOffset(Offset); + LoADDI.getOperand(2).setOffset(Offset); + DeadInstrs.insert(&Tail); + MRI->replaceRegWith(Tail.getOperand(0).getReg(), LoADDI.getOperand(0).getReg()); + LLVM_DEBUG(dbgs() << " Merged offset " << Offset << " into base.\n" << " " << HiLUI << " " << LoADDI;); + return true; + } + break; + case RISCV::LB: + case RISCV::LH: + case RISCV::LW: + case RISCV::LBU: + case RISCV::LHU: + case RISCV::LWU: + case RISCV::LD: + case RISCV::FLH: + case RISCV::FLW: + case RISCV::FLD: + case RISCV::SB: + case RISCV::SH: + case RISCV::SW: + case RISCV::SD: + case RISCV::FSH: + case RISCV::FSW: + case RISCV::FSD: { + if (Tail.getOperand(1).isFI()) { + return false; + } + Register BaseAddrReg = Tail.getOperand(1).getReg(); + if (DestReg != BaseAddrReg) + return false; + MachineOperand &TailImmOp = Tail.getOperand(2); + int64_t Offset = TailImmOp.getImm(); + HiLUI.getOperand(1).setOffset(Offset); + Tail.RemoveOperand(2); + MachineOperand &ImmOp = LoADDI.getOperand(2); + ImmOp.setOffset(Offset); + Tail.addOperand(ImmOp); + Tail.getOperand(1).setReg(HiLUI.getOperand(0).getReg()); + DeadInstrs.insert(&LoADDI); + return true; + } break; + } + return false; + } + } + for (auto *MI : DeadInstrs) { + MI->eraseFromParent(); + } + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/InstrInfo.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/InstrInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..748278cc79300d8a5ec326134622a47f923f34f6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/InstrInfo.cpp @@ -0,0 +1,2 @@ +RISCVInstrInfo::RISCVInstrInfo(RISCVSubtarget &STI) : RISCVGenInstrInfo( RISCV::ADJCALLSTACKDOWN, RISCV::ADJCALLSTACKUP), STI(STI) { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/analyzeBranch.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/analyzeBranch.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d86ee8cd4f838d592e68b58e88bd472f670cf458 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/analyzeBranch.cpp @@ -0,0 +1,43 @@ +bool RISCVInstrInfo::analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl &Cond, bool AllowModify) const { + TBB = FBB = nullptr; + Cond.clear(); + MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr(); + if (I == MBB.end() || !isUnpredicatedTerminator(*I)) { + return false; + } + MachineBasicBlock::iterator FirstUncondOrIndirectBr = MBB.end(); + int NumTerminators = 0; + for (auto J = I.getReverse(); J != MBB.rend() && isUnpredicatedTerminator(*J); J++) { + NumTerminators++; + if (J->getDesc().isUnconditionalBranch() || J->getDesc().isIndirectBranch()) { + FirstUncondOrIndirectBr = J.getReverse(); + } + } + if (AllowModify && FirstUncondOrIndirectBr != MBB.end()) { + while (std::next(FirstUncondOrIndirectBr) != MBB.end()) { + std::next(FirstUncondOrIndirectBr)->eraseFromParent(); + NumTerminators--; + } + I = FirstUncondOrIndirectBr; + } + if (I->getDesc().isIndirectBranch()) { + return true; + } + if (NumTerminators > 2) { + return true; + } + if (NumTerminators == 1 && I->getDesc().isUnconditionalBranch()) { + TBB = getBranchDestBlock(*I); + return false; + } + if (NumTerminators == 1 && I->getDesc().isConditionalBranch()) { + parseCondBranch(*I, TBB, Cond); + return false; + } + if (NumTerminators == 2 && std::prev(I)->getDesc().isConditionalBranch() && I->getDesc().isUnconditionalBranch()) { + parseCondBranch(*std::prev(I), TBB, Cond); + FBB = getBranchDestBlock(*I); + return false; + } + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/areMemAccessesTriviallyDisjoint.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/areMemAccessesTriviallyDisjoint.cpp new file mode 100644 index 0000000000000000000000000000000000000000..84c10e93be57ac9e456e12ff8b4453d873ba50fa --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/areMemAccessesTriviallyDisjoint.cpp @@ -0,0 +1,22 @@ +bool RISCVInstrInfo::areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const { + assert(MIa.mayLoadOrStore() && "MIa must be a load or store."); + assert(MIb.mayLoadOrStore() && "MIb must be a load or store."); + if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() || MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) { + return false; + } + const TargetRegisterInfo *TRI = STI.getRegisterInfo(); + const MachineOperand *BaseOpA = nullptr, *BaseOpB = nullptr; + int64_t OffsetA = 0, OffsetB = 0; + unsigned int WidthA = 0, WidthB = 0; + if (getMemOperandWithOffsetWidth(MIa, BaseOpA, OffsetA, WidthA, TRI) && getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, WidthB, TRI)) { + if (BaseOpA->isIdenticalTo(*BaseOpB)) { + int LowOffset = std::min(OffsetA, OffsetB); + int HighOffset = std::max(OffsetA, OffsetB); + int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB; + if (LowOffset + LowWidth <= HighOffset) { + return true; + } + } + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/buildOutlinedFrame.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/buildOutlinedFrame.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bcb2321cf28d3ecdc90f327ad2cbeb346542dafc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/buildOutlinedFrame.cpp @@ -0,0 +1,17 @@ +void RISCVInstrInfo::buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const { + bool Changed = true; + while (Changed) { + Changed = false; + auto I = MBB.begin(); + auto E = MBB.end(); + for (; I != E; ++I) { + if (I->isCFIInstruction()) { + I->removeFromParent(); + Changed = true; + break; + } + } + } + MBB.addLiveIn(RISCV::X5); + MBB.insert(MBB.end(), BuildMI(MF, DebugLoc(), get(RISCV::JALR)).addReg(RISCV::X0, RegState::Define).addReg(RISCV::X5).addImm(0)); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/copyPhysReg.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/copyPhysReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3d86b0f026bac722f6a15accf9e7a9fe2a33d932 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/copyPhysReg.cpp @@ -0,0 +1,36 @@ + +void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg, bool KillSrc) const { + if (RISCV::GPRRegClass.contains(DstReg, SrcReg)) { + BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg).addReg(SrcReg, getKillRegState(KillSrc)).addImm(0); + return; + } + if (RISCV::FPR16RegClass.contains(DstReg, SrcReg)) { + BuildMI(MBB, MBBI, DL, get(RISCV::FSGNJ_H), DstReg).addReg(SrcReg, getKillRegState(KillSrc)).addReg(SrcReg, getKillRegState(KillSrc)); + return ; + } + if (RISCV::FPR32RegClass.contains(DstReg, SrcReg)) { + BuildMI(MBB, MBBI, DL, get(RISCV::FSGNJ_S), DstReg).addReg(SrcReg, getKillRegState(KillSrc)).addReg(SrcReg, getKillRegState(KillSrc)); + return ; + } + if (RISCV::FPR64RegClass.contains(DstReg, SrcReg)) { + BuildMI(MBB, MBBI, DL, get(RISCV::FSGNJ_D;), DstReg).addReg(SrcReg, getKillRegState(KillSrc)).addReg(SrcReg, getKillRegState(KillSrc)); + return ; + } + if (RISCV::VRRegClass.contains(DstReg, SrcReg)) { + BuildMI(MBB, MBBI, DL, get(RISCV::PseudoVMV1R_V), DstReg).addReg(SrcReg, getKillRegState(KillSrc)); + return ; + } + if (RISCV::VRM2RegClass.contains(DstReg, SrcReg)) { + BuildMI(MBB, MBBI, DL, get(RISCV::PseudoVMV2R_V), DstReg).addReg(SrcReg, getKillRegState(KillSrc)); + return ; + } + if (RISCV::VRM4RegClass.contains(DstReg, SrcReg)) { + BuildMI(MBB, MBBI, DL, get(RISCV::PseudoVMV4R_V), DstReg).addReg(SrcReg, getKillRegState(KillSrc)); + return ; + } + if (RISCV::VRM8RegClass.contains(DstReg, SrcReg)) { + BuildMI(MBB, MBBI, DL, get(RISCV::PseudoVMV8R_V), DstReg).addReg(SrcReg, getKillRegState(KillSrc)); + return ; + } + llvm_unreachable("Impossible reg-to-reg copy"); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/decomposeMachineOperandsTargetFlags.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/decomposeMachineOperandsTargetFlags.cpp new file mode 100644 index 0000000000000000000000000000000000000000..371fad319519ebb28816b75c9b94dbc64622e257 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/decomposeMachineOperandsTargetFlags.cpp @@ -0,0 +1,4 @@ +std::pair RISCVInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const { + const unsigned Mask = RISCVII::MO_DIRECT_FLAG_MASK; + return std::make_pair(TF & Mask, TF & ~Mask); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/getBranchDestBlock.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/getBranchDestBlock.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cae1b652d38074daf74f2f39cb157d40817089f3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/getBranchDestBlock.cpp @@ -0,0 +1,4 @@ +MachineBasicBlock *RISCVInstrInfo::getBranchDestBlock(const MachineInstr &MI) const { + assert(MI.getDesc().isBranch() && "Unexpected opcode!"); + return MI.getOperand(MI.getNumExplicitOperands() - 1).getMBB(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/getInstSizeInBytes.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/getInstSizeInBytes.cpp new file mode 100644 index 0000000000000000000000000000000000000000..995d4bdb01ff49a8ff82e1f037826549065dcb8d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/getInstSizeInBytes.cpp @@ -0,0 +1,58 @@ +unsigned RISCVInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const { + unsigned Opcode = MI.getOpcode(); + switch (Opcode) { + default: { + if (MI.getParent() && MI.getParent()->getParent()) { + const auto MF = MI.getMF(); + const auto &TM = static_cast(MF->getTarget()); + const MCRegisterInfo &MRI = *TM.getMCRegisterInfo(); + const MCSubtargetInfo &STI = *TM.getMCSubtargetInfo(); + const RISCVSubtarget &ST = MF->getSubtarget(); + if (isCompressibleInst(MI, &ST, MRI, STI)) { + return 2; + } + } + return get(Opcode).getSize(); + } + case TargetOpcode::EH_LABEL: + case TargetOpcode::IMPLICIT_DEF: + case TargetOpcode::KILL: + case TargetOpcode::DBG_VALUE: + return 0; + case RISCV::PseudoCALLReg: + case RISCV::PseudoCALL: + case RISCV::PseudoJump: + case RISCV::PseudoTAIL: + case RISCV::PseudoLLA: + case RISCV::PseudoLA: + case RISCV::PseudoLA_TLS_IE: + case RISCV::PseudoLA_TLS_GD: + return 8; + case RISCV::PseudoAtomicLoadNand32: + case RISCV::PseudoAtomicLoadNand64: + return 20; + case RISCV::PseudoMaskedAtomicSwap32: + case RISCV::PseudoMaskedAtomicLoadAdd32: + case RISCV::PseudoMaskedAtomicLoadSub32: + return 28; + case RISCV::PseudoMaskedAtomicLoadNand32: + return 32; + case RISCV::PseudoMaskedAtomicLoadMax32: + case RISCV::PseudoMaskedAtomicLoadMin32: + return 44; + case RISCV::PseudoMaskedAtomicLoadUMax32: + case RISCV::PseudoMaskedAtomicLoadUMin32: + return 36; + case RISCV::PseudoCmpXchg32: + case RISCV::PseudoCmpXchg64: + return 16; + case RISCV::PseudoMaskedCmpXchg32: + return 32; + case TargetOpcode::INLINEASM: + case TargetOpcode::INLINEASM_BR: { + const MachineFunction &MF = *MI.getParent()->getParent(); + const auto &TM = static_cast(MF.getTarget()); + return getInlineAsmLength(MI.getOperand(0).getSymbolName(), *TM.getMCAsmInfo()); + } + } +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/getMemOperandWithOffsetWidth.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/getMemOperandWithOffsetWidth.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c047851933d8e04b86ede618330b87e4ca0b4859 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/getMemOperandWithOffsetWidth.cpp @@ -0,0 +1,18 @@ +bool RISCVInstrInfo::getMemOperandWithOffsetWidth(const MachineInstr &LdSt, const MachineOperand *&BaseReg, int64_t &Offset, unsigned &Width, const TargetRegisterInfo *TRI) const { + if (!LdSt.mayLoadOrStore()) { + return false; + } + if (LdSt.getNumExplicitOperands() != 3) { + return false; + } + if (!LdSt.getOperand(1).isReg() || !LdSt.getOperand(2).isImm()) { + return false; + } + if (!LdSt.hasOneMemOperand()) { + return false; + } + Width = (*LdSt.memoperands_begin())->getSize(); + BaseReg = &LdSt.getOperand(1); + Offset = LdSt.getOperand(2).getImm(); + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/getOutliningCandidateInfo.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/getOutliningCandidateInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c46ce820392baeb07d11944ca084ec5cba2091c7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/getOutliningCandidateInfo.cpp @@ -0,0 +1,27 @@ +outliner::OutlinedFunction RISCVInstrInfo::getOutliningCandidateInfo(std::vector &RepeatedSequenceLocs) const { + auto CannotInsertCall = [](outliner::Candidate &C) { + const TargetRegisterInfo *TRI = C.getMF()->getSubtarget().getRegisterInfo(); + C.initLRU(*TRI); + LiveRegUnits LRU = C.LRU; + return !LRU.available(RISCV::X5); + }; + llvm::erase_if(RepeatedSequenceLocs, CannotInsertCall); + if (RepeatedSequenceLocs.size() < 2) { + return outliner::OutlinedFunction(); + } + unsigned SequenceSize = 0; + auto I = RepeatedSequenceLocs[0].front(); + auto E = std::next(RepeatedSequenceLocs[0].back()); + for (; I != E; ++I) { + SequenceSize += getInstSizeInBytes(*I); + } + unsigned CallOverhead = 8; + for (auto &C : RepeatedSequenceLocs) { + C.setCallInfo(MachineOutlinerDefault, CallOverhead); + } + unsigned FrameOverhead = 4; + if (RepeatedSequenceLocs[0].getMF()->getSubtarget().getFeatureBits()[RISCV::FeatureStdExtC]) { + FrameOverhead = 2; + } + return outliner::OutlinedFunction(RepeatedSequenceLocs, SequenceSize, FrameOverhead, MachineOutlinerDefault); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/getOutliningType.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/getOutliningType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9a3dd323cf6a01428a868ff2e81d3613bad1aad4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/getOutliningType.cpp @@ -0,0 +1,32 @@ +outliner::InstrType RISCVInstrInfo::getOutliningType(MachineBasicBlock::iterator &MBBI, unsigned Flags) const { + MachineInstr &MI = *MBBI; + MachineBasicBlock *MBB = MI.getParent(); + const TargetRegisterInfo *TRI = MBB->getParent()->getSubtarget().getRegisterInfo(); + if (MI.isPosition()) { + if (MI.isCFIInstruction()) { + return outliner::InstrType::Invisible; + } + return outliner::InstrType::Illegal; + } + if (MI.isInlineAsm()) { + return outliner::InstrType::Illegal; + } + if (MI.isTerminator() && !MBB->succ_empty()) { + return outliner::InstrType::Illegal; + } + if (MI.isReturn()) { + return outliner::InstrType::Illegal; + } + if (MI.modifiesRegister(RISCV::X5, TRI) || MI.getDesc().hasImplicitDefOfPhysReg(RISCV::X5)) { + return outliner::InstrType::Illegal; + } + for (const auto &MO : MI.operands()) { + if (MO.isMBB() || MO.isBlockAddress() || MO.isCPI()) { + return outliner::InstrType::Illegal; + } + } + if (MI.isMetaInstruction()) { + return outliner::InstrType::Invisible; + } + return outliner::InstrType::Legal; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/getSerializableDirectMachineOperandTargetFlags.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/getSerializableDirectMachineOperandTargetFlags.cpp new file mode 100644 index 0000000000000000000000000000000000000000..263cfb665f67d84e93145d137c3d2ab6ab3b7d06 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/getSerializableDirectMachineOperandTargetFlags.cpp @@ -0,0 +1,5 @@ +ArrayRef> RISCVInstrInfo::getSerializableDirectMachineOperandTargetFlags() const { + using namespace RISCVII; + static const std::pair TargetFlags[] = {{MO_CALL, "riscv-call"},{MO_PLT, "riscv-plt"},{MO_LO, "riscv-lo"},{MO_HI, "riscv-hi"},{MO_PCREL_LO, "riscv-pcrel-lo"},{MO_PCREL_HI, "riscv-pcrel-hi"},{MO_GOT_HI, "riscv-got-hi"},{MO_TPREL_LO, "riscv-tprel-lo"},{MO_TPREL_HI, "riscv-tprel-hi"},{MO_TPREL_ADD, "riscv-tprel-add"},{MO_TLS_GOT_HI, "riscv-tls-got-hi"},{MO_TLS_GD_HI, "riscv-tls-gd-hi"}}; + return makeArrayRef(TargetFlags); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/insertBranch.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/insertBranch.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cf05adfad8dde46f66f5392c7b824e5c8eb9fd87 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/insertBranch.cpp @@ -0,0 +1,27 @@ +unsigned RISCVInstrInfo::insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, const DebugLoc &DL, int *BytesAdded) const { + if (BytesAdded) { + *BytesAdded = 0; + } + assert(TBB && "insertBranch must not be told to insert a fallthrough"); + assert((Cond.size() == 3 || Cond.size() == 0) && "RISCV branch conditions have two components!"); + if (Cond.empty()) { + MachineInstr &MI = *BuildMI(&MBB, DL, get(RISCV::PseudoBR)).addMBB(TBB); + if (BytesAdded) { + *BytesAdded = *BytesAdded + getInstSizeInBytes(MI); + } + return 1; + } + unsigned Opc = Cond[0].getImm(); + MachineInstr &CondMI = *BuildMI(&MBB, DL, get(Opc)).add(Cond[1]).add(Cond[2]).addMBB(TBB); + if (BytesAdded) { + *BytesAdded = *BytesAdded + getInstSizeInBytes(CondMI); + } + if (!FBB) { + return 1; + } + MachineInstr &MI = *BuildMI(&MBB, DL, get(RISCV::PseudoBR)).addMBB(FBB); + if (BytesAdded) { + *BytesAdded = *BytesAdded + getInstSizeInBytes(MI); + } + return 2; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/insertIndirectBranch.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/insertIndirectBranch.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b1492bf3ef915bf02e849b172335d6538b40164d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/insertIndirectBranch.cpp @@ -0,0 +1,19 @@ +unsigned RISCVInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &DestBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS) const { + assert(RS && "RegScavenger required for long branching"); + assert(MBB.empty() && "new block should be inserted for expanding unconditional branch"); + assert(MBB.pred_size() == 1); + MachineFunction *MF = MBB.getParent(); + MachineRegisterInfo &MRI = MF->getRegInfo(); + if (!isInt<32>(BrOffset)) { + report_fatal_error("Branch offsets outside of the signed 32-bit range not supported"); + } + Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); + auto II = MBB.end(); + MachineInstr &MI = *BuildMI(MBB, II, DL, get(RISCV::PseudoJump)).addReg(ScratchReg, RegState::Define | RegState::Dead).addMBB(&DestBB, RISCVII::MO_CALL); + RS->enterBasicBlockEnd(MBB); + unsigned Scav = RS->scavengeRegisterBackwards(RISCV::GPRRegClass, MI.getIterator(), false, 0); + MRI.replaceRegWith(ScratchReg, Scav); + MRI.clearVirtRegs(); + RS->setRegUsed(Scav); + return 8; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/insertOutlinedCall.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/insertOutlinedCall.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bc4fc501f51d854d8e3da7721b447adee3a5d2f1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/insertOutlinedCall.cpp @@ -0,0 +1,4 @@ +MachineBasicBlock::iterator RISCVInstrInfo::insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, const outliner::Candidate &C) const { + It = MBB.insert(It, BuildMI(MF, DebugLoc(), get(RISCV::PseudoCALLReg), RISCV::X5).addGlobalAddress(M.getNamedValue(MF.getName()), 0, RISCVII::MO_CALL)); + return It; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/isAsCheapAsAMove.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/isAsCheapAsAMove.cpp new file mode 100644 index 0000000000000000000000000000000000000000..39ad00c050eb6a3d2f6bc0acda49ffd7a8a5b252 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/isAsCheapAsAMove.cpp @@ -0,0 +1,19 @@ +bool RISCVInstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const { + const unsigned Opcode = MI.getOpcode(); + if(Opcode ==RISCV::FSGNJ_D) { + return MI.getOperand(1).isReg() && MI.getOperand(2).isReg() && MI.getOperand(1).getReg() == MI.getOperand(2).getReg(); + } + if(Opcode ==RISCV::FSGNJ_S) { + return MI.getOperand(1).isReg() && MI.getOperand(2).isReg() && MI.getOperand(1).getReg() == MI.getOperand(2).getReg(); + } + if(Opcode ==RISCV::ADDI) { + return (MI.getOperand(1).isReg() && MI.getOperand(1).getReg() == RISCV::X0) || (MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0); + } + if(Opcode ==RISCV::ORI) { + return (MI.getOperand(1).isReg() && MI.getOperand(1).getReg() == RISCV::X0) || (MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0); + } + if(Opcode ==RISCV::XORI) { + return (MI.getOperand(1).isReg() && MI.getOperand(1).getReg() == RISCV::X0) || (MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0); + } + return MI.isAsCheapAsAMove(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/isBranchOffsetInRange.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/isBranchOffsetInRange.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e6eef2ac0fe4155e7932c5290a105dcf1c8fe7f8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/isBranchOffsetInRange.cpp @@ -0,0 +1,19 @@ +bool RISCVInstrInfo::isBranchOffsetInRange(unsigned BranchOp, int64_t BrOffset) const { + unsigned XLen = STI.getXLen(); + switch (BranchOp) { + case RISCV::BEQ: + case RISCV::BNE: + case RISCV::BLT: + case RISCV::BGE: + case RISCV::BLTU: + case RISCV::BGEU: + return isIntN(13, BrOffset); + case RISCV::JAL: + case RISCV::PseudoBR: + return isIntN(21, BrOffset); + case RISCV::PseudoJump: + return isIntN(32, SignExtend64(BrOffset + 0x800, XLen)); + default: + llvm_unreachable("Unexpected opcode!"); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/isCopyInstrImpl.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/isCopyInstrImpl.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c815f394615b68f75ab7532e5b30d428b93b1d9a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/isCopyInstrImpl.cpp @@ -0,0 +1,21 @@ +Optional RISCVInstrInfo::isCopyInstrImpl(const MachineInstr &MI) const { + if (MI.isMoveReg()) { + return DestSourcePair{MI.getOperand(0), MI.getOperand(1)}; + } + if (MI.getOpcode() == RISCV::ADDI) { + if (MI.getOperand(1).isReg() && MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) { + return DestSourcePair{MI.getOperand(0), MI.getOperand(1)}; + } + } + if (MI.getOpcode() == RISCV::FSGNJ_D) { + if (MI.getOperand(1).isReg() && MI.getOperand(2).isReg() && MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) { + return DestSourcePair{MI.getOperand(0), MI.getOperand(1)}; + } + } + if (MI.getOpcode() == RISCV::FSGNJ_S) { + if (MI.getOperand(1).isReg() && MI.getOperand(2).isReg() && MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) { + return DestSourcePair{MI.getOperand(0), MI.getOperand(1)}; + } + } + return None; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/isFunctionSafeToOutlineFrom.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/isFunctionSafeToOutlineFrom.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9caad0ee4e4d0f3759c8d9c9fe481cee5f378ec5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/isFunctionSafeToOutlineFrom.cpp @@ -0,0 +1,10 @@ +bool RISCVInstrInfo::isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const { + const Function &F = MF.getFunction(); + if (!OutlineFromLinkOnceODRs && F.hasLinkOnceODRLinkage()) { + return false; + } + if (F.hasSection()) { + return false; + } + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/isLoadFromStackSlot.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/isLoadFromStackSlot.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2dd099d2cc9c5b17a2b05c2f8cadf6939da7b835 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/isLoadFromStackSlot.cpp @@ -0,0 +1,103 @@ +unsigned RISCVInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const { + if (MI.getOpcode() == RISCV::LB) { + if (MI.getOperand(1).isFI()) { + if (MI.getOperand(2).isImm()) { + if (MI.getOperand(2).getImm() == 0) { + FrameIndex = MI.getOperand(1).getIndex(); + return MI.getOperand(0).getReg(); + } + } + } + } + if (MI.getOpcode() == RISCV::LBU) { + if (MI.getOperand(1).isFI()) { + if (MI.getOperand(2).isImm()) { + if (MI.getOperand(2).getImm() == 0) { + FrameIndex = MI.getOperand(1).getIndex(); + return MI.getOperand(0).getReg(); + } + } + } + } + if (MI.getOpcode() == RISCV::LH) { + if (MI.getOperand(1).isFI()) { + if (MI.getOperand(2).isImm()) { + if (MI.getOperand(2).getImm() == 0) { + FrameIndex = MI.getOperand(1).getIndex(); + return MI.getOperand(0).getReg(); + } + } + } + } + if (MI.getOpcode() == RISCV::LHU) { + if (MI.getOperand(1).isFI()) { + if (MI.getOperand(2).isImm()) { + if (MI.getOperand(2).getImm() == 0) { + FrameIndex = MI.getOperand(1).getIndex(); + return MI.getOperand(0).getReg(); + } + } + } + } + if (MI.getOpcode() == RISCV::FLH) { + if (MI.getOperand(1).isFI()) { + if (MI.getOperand(2).isImm()) { + if (MI.getOperand(2).getImm() == 0) { + FrameIndex = MI.getOperand(1).getIndex(); + return MI.getOperand(0).getReg(); + } + } + } + } + if (MI.getOpcode() == RISCV::LW) { + if (MI.getOperand(1).isFI()) { + if (MI.getOperand(2).isImm()) { + if (MI.getOperand(2).getImm() == 0) { + FrameIndex = MI.getOperand(1).getIndex(); + return MI.getOperand(0).getReg(); + } + } + } + } + if (MI.getOpcode() == RISCV::FWL) { + if (MI.getOperand(1).isFI()) { + if (MI.getOperand(2).isImm()) { + if (MI.getOperand(2).getImm() == 0) { + FrameIndex = MI.getOperand(1).getIndex(); + return MI.getOperand(0).getReg(); + } + } + } + } + if (MI.getOpcode() == RISCV::LWU) { + if (MI.getOperand(1).isFI()) { + if (MI.getOperand(2).isImm()) { + if (MI.getOperand(2).getImm() == 0) { + FrameIndex = MI.getOperand(1).getIndex(); + return MI.getOperand(0).getReg(); + } + } + } + } + if (MI.getOpcode() == RISCV::LD) { + if (MI.getOperand(1).isFI()) { + if (MI.getOperand(2).isImm()) { + if (MI.getOperand(2).getImm() == 0) { + FrameIndex = MI.getOperand(1).getIndex(); + return MI.getOperand(0).getReg(); + } + } + } + } + if (MI.getOpcode() == RISCV::FLD) { + if (MI.getOperand(1).isFI()) { + if (MI.getOperand(2).isImm()) { + if (MI.getOperand(2).getImm() == 0) { + FrameIndex = MI.getOperand(1).getIndex(); + return MI.getOperand(0).getReg(); + } + } + } + } + return 0; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/isMBBSafeToOutlineFrom.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/isMBBSafeToOutlineFrom.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d9e89b48698e2fb498dd5f8e8facf15525e862aa --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/isMBBSafeToOutlineFrom.cpp @@ -0,0 +1,3 @@ +bool RISCVInstrInfo::isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, unsigned &Flags) const { + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/isStoreToStackSlot.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/isStoreToStackSlot.cpp new file mode 100644 index 0000000000000000000000000000000000000000..25f4bf9ad1bb3535889e398c48412ab3ff94334a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/isStoreToStackSlot.cpp @@ -0,0 +1,19 @@ +unsigned RISCVInstrInfo::isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const { + switch (MI.getOpcode()) { + default: + return 0; + case RISCV::SB: + case RISCV::SH: + case RISCV::SW: + case RISCV::FSH: + case RISCV::FSW: + case RISCV::SD: + case RISCV::FSD: + break; + } + if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) { + FrameIndex = MI.getOperand(1).getIndex(); + return MI.getOperand(0).getReg(); + } + return 0; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/loadRegFromStackSlot.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/loadRegFromStackSlot.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e71f82302950ea15b9fad418bc5c9ab1b10bd6be --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/loadRegFromStackSlot.cpp @@ -0,0 +1,31 @@ +void RISCVInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register DstReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const { + DebugLoc DL; + if (I != MBB.end()) { + DL = I->getDebugLoc(); + } + MachineFunction *MF = MBB.getParent(); + const MachineFrameInfo &MFI = MF->getFrameInfo(); + MachineMemOperand *MMO = MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOLoad, MFI.getObjectSize(FI), MFI.getObjectAlign(FI)); + unsigned Opcode; + if (RISCV::GPRRegClass.hasSubClassEq(RC)) { + Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ? RISCV::LW : RISCV::LD; + BuildMI(MBB, I, DL, get(Opcode), DstReg).addFrameIndex(FI).addImm(0).addMemOperand(MMO); + return ; + } + if (RISCV::FPR16RegClass.hasSubClassEq(RC)) { + Opcode = RISCV::FLH; + BuildMI(MBB, I, DL, get(Opcode), DstReg).addFrameIndex(FI).addImm(0).addMemOperand(MMO); + return ; + } + if (RISCV::FPR32RegClass.hasSubClassEq(RC)) { + Opcode = RISCV::FWL; + BuildMI(MBB, I, DL, get(Opcode), DstReg).addFrameIndex(FI).addImm(0).addMemOperand(MMO); + return ; + } + if (RISCV::FPR64RegClass.hasSubClassEq(RC)) { + Opcode = RISCV::FLD; + BuildMI(MBB, I, DL, get(Opcode), DstReg).addFrameIndex(FI).addImm(0).addMemOperand(MMO); + return ; + } + llvm_unreachable("Can't load this register from stack slot"); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/movImm.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/movImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c72f7f9e84e4ace08a3e3a7dad1d6a68cf683f24 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/movImm.cpp @@ -0,0 +1,26 @@ +void RISCVInstrInfo::movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register DstReg, uint64_t Val, MachineInstr::MIFlag Flag) const { + MachineRegisterInfo &MRI = MF->getRegInfo(); + MachineFunction *MF = MBB.getParent(); + bool IsRV64 = MF->getSubtarget().is64Bit(); + Register SrcReg = RISCV::X0; + Register Result = MRI.createVirtualRegister(&RISCV::GPRRegClass); + unsigned Num = 0; + if (!IsRV64 && !isInt<32>(Val)) { + report_fatal_error("Should only materialize 32-bit constants for RV32"); + } + RISCVMatInt::InstSeq Seq; + RISCVMatInt::generateInstSeq(Val, IsRV64, Seq); + assert(Seq.size() > 0); + for (RISCVMatInt::Inst &Inst : Seq) { + if (++Num == Seq.size()) { + Result = DstReg; + } + if (Inst.Opc == RISCV::LUI) { + BuildMI(MBB, MBBI, DL, get(RISCV::LUI), Result).addImm(Inst.Imm).setMIFlag(Flag); + } + else { + BuildMI(MBB, MBBI, DL, get(Inst.Opc), Result).addReg(SrcReg, RegState::Kill).addImm(Inst.Imm).setMIFlag(Flag); + } + SrcReg = Result; + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/parseCondBranch.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/parseCondBranch.cpp new file mode 100644 index 0000000000000000000000000000000000000000..aef3d0ecdf646f8417201ea3baa82992390cf15b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/parseCondBranch.cpp @@ -0,0 +1,7 @@ +static void parseCondBranch(MachineInstr &LastInst, MachineBasicBlock *&Target, SmallVectorImpl &Cond) { + assert(LastInst.getDesc().isConditionalBranch() && "Unknown conditional branch"); + Target = LastInst.getOperand(2).getMBB(); + Cond.push_back(MachineOperand::CreateImm(LastInst.getOpcode())); + Cond.push_back(LastInst.getOperand(0)); + Cond.push_back(LastInst.getOperand(1)); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/removeBranch.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/removeBranch.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fd30e85a8f2e12786e68b6e78bdf15a32405af38 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/removeBranch.cpp @@ -0,0 +1,29 @@ +unsigned RISCVInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved) const { + if (BytesRemoved) { + *BytesRemoved = 0; + } + MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr(); + if (I == MBB.end()) { + return 0; + } + if (!I->getDesc().isUnconditionalBranch() && !I->getDesc().isConditionalBranch()) { + return 0; + } + if (BytesRemoved) { + *BytesRemoved += getInstSizeInBytes(*I); + } + I->eraseFromParent(); + I = MBB.end(); + if (I == MBB.begin()) { + return 1; + } + --I; + if (!I->getDesc().isConditionalBranch()) { + return 1; + } + if (BytesRemoved) { + *BytesRemoved += getInstSizeInBytes(*I); + } + I->eraseFromParent(); + return 2; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/reverseBranchCondition.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/reverseBranchCondition.cpp new file mode 100644 index 0000000000000000000000000000000000000000..518236fcb35df0b50482ad41a57f1da3bb8b7bfe --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/reverseBranchCondition.cpp @@ -0,0 +1,5 @@ +bool RISCVInstrInfo::reverseBranchCondition(SmallVectorImpl &Cond) const { + assert((Cond.size() == 3) && "Invalid branch condition!"); + Cond[0].setImm(getOppositeBranchOpcode(Cond[0].getImm())); + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/storeRegToStackSlot.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/storeRegToStackSlot.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e0ae4eae7913dca4a4503f04564cf151eb5e25b7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/storeRegToStackSlot.cpp @@ -0,0 +1,26 @@ +void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register SrcReg, bool IsKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const { + DebugLoc DL; + if (I != MBB.end()) { + DL = I->getDebugLoc(); + } + MachineFunction *MF = MBB.getParent(); + const MachineFrameInfo &MFI = MF->getFrameInfo(); + MachineMemOperand *MMO = MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOStore, MFI.getObjectSize(FI), MFI.getObjectAlign(FI)); + unsigned Opcode; + if (RISCV::GPRRegClass.hasSubClassEq(RC)) { + Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ? RISCV::SW : RISCV::SD; + } + else if (RISCV::FPR16RegClass.hasSubClassEq(RC)) { + Opcode = RISCV::FSH; + } + else if (RISCV::FPR32RegClass.hasSubClassEq(RC)) { + Opcode = RISCV::FSW; + } + else if (RISCV::FPR64RegClass.hasSubClassEq(RC)) { + Opcode = RISCV::FSD; + } + else { + llvm_unreachable("Can't store this register to stack slot"); + } + BuildMI(MBB, I, DL, get(Opcode)).addReg(SrcReg, getKillRegState(IsKill)).addFrameIndex(FI).addImm(0).addMemOperand(MMO); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/verifyInstruction.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/verifyInstruction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8e343d48c820364dc7982050272a51d190407121 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/InstrInfo/verifyInstruction.cpp @@ -0,0 +1,35 @@ +bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const { + const MCInstrInfo *MCII = STI.getInstrInfo(); + MCInstrDesc const &Desc = MCII->get(MI.getOpcode()); + for (auto &OI : enumerate(Desc.operands())) { + unsigned OpType = OI.value().OperandType; + if (OpType >= RISCVOp::OPERAND_FIRST_RISCV_IMM && OpType <= RISCVOp::OPERAND_LAST_RISCV_IMM) { + const MachineOperand &MO = MI.getOperand(OI.index()); + if (MO.isImm()) { + int64_t Imm = MO.getImm(); + bool Ok; + switch (OpType) { + default: + llvm_unreachable("Unexpected operand type"); + case RISCVOp::OPERAND_SIMM12: + Ok = isInt<12>(Imm); + break; + case RISCVOp::OPERAND_UIMM20: + Ok = isUInt<20>(Imm); + break; + case RISCVOp::OPERAND_UIMMLOG2XLEN: + if (STI.getTargetTriple().isArch64Bit()) + Ok = isUInt<6>(Imm); + else + Ok = isUInt<5>(Imm); + break; + } + if (!Ok) { + ErrInfo = "Invalid immediate"; + return false; + } + } + } + } + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/MachineFunctionInfo/MachineFunctionInfo.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/MachineFunctionInfo/MachineFunctionInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a73ce4b15067ea6dd345e8f804506eb820ce687b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/MachineFunctionInfo/MachineFunctionInfo.cpp @@ -0,0 +1,2 @@ +RISCVMachineFunctionInfo(const MachineFunction &MF) { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/MachineFunctionInfo/getLibCallStackSize.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/MachineFunctionInfo/getLibCallStackSize.cpp new file mode 100644 index 0000000000000000000000000000000000000000..79005827d02719d27077d7e3bbe5d9c839a908e2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/MachineFunctionInfo/getLibCallStackSize.cpp @@ -0,0 +1,3 @@ +unsigned getLibCallStackSize() const { + return LibCallStackSize; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/MachineFunctionInfo/getMoveF64FrameIndex.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/MachineFunctionInfo/getMoveF64FrameIndex.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7c988c0796a82546234e3f8e39a1182b7d1ea2b8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/MachineFunctionInfo/getMoveF64FrameIndex.cpp @@ -0,0 +1,6 @@ +int getMoveF64FrameIndex(MachineFunction &MF) { + if (MoveF64FrameIndex == -1) { + MoveF64FrameIndex = MF.getFrameInfo().CreateStackObject(8, Align(8), false); + } + return MoveF64FrameIndex; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/MachineFunctionInfo/getVarArgsFrameIndex.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/MachineFunctionInfo/getVarArgsFrameIndex.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2ad7e3a6df3da4abe5143ddf276a5a8dd208c0d1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/MachineFunctionInfo/getVarArgsFrameIndex.cpp @@ -0,0 +1,3 @@ +int getVarArgsFrameIndex() const { + return VarArgsFrameIndex; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/MachineFunctionInfo/getVarArgsSaveSize.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/MachineFunctionInfo/getVarArgsSaveSize.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ff3900efa130d85bd23cdf0bf46f4492a11b3207 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/MachineFunctionInfo/getVarArgsSaveSize.cpp @@ -0,0 +1,3 @@ +unsigned getVarArgsSaveSize() const { + return VarArgsSaveSize; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/MachineFunctionInfo/setLibCallStackSize.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/MachineFunctionInfo/setLibCallStackSize.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e2c605685906e3f74e9d19eb3a425bb677ecf6e8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/MachineFunctionInfo/setLibCallStackSize.cpp @@ -0,0 +1,3 @@ +void setLibCallStackSize(unsigned Size) { + LibCallStackSize = Size; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/MachineFunctionInfo/setVarArgsFrameIndex.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/MachineFunctionInfo/setVarArgsFrameIndex.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f57e9f48831fa353d584c49669f0413fc095c594 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/MachineFunctionInfo/setVarArgsFrameIndex.cpp @@ -0,0 +1,3 @@ +void setVarArgsFrameIndex(int Index) { + VarArgsFrameIndex = Index; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/MachineFunctionInfo/setVarArgsSaveSize.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/MachineFunctionInfo/setVarArgsSaveSize.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3a72ac1c44b6abb48837cf13d74446638ee97792 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/MachineFunctionInfo/setVarArgsSaveSize.cpp @@ -0,0 +1,3 @@ +void setVarArgsSaveSize(int Size) { + VarArgsSaveSize = Size; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/MachineFunctionInfo/useSaveRestoreLibCalls.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/MachineFunctionInfo/useSaveRestoreLibCalls.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bcd8f637f04add2d1722e6da9011c498bb8571c8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/MachineFunctionInfo/useSaveRestoreLibCalls.cpp @@ -0,0 +1,3 @@ +bool useSaveRestoreLibCalls(const MachineFunction &MF) const { + return MF.getSubtarget().enableSaveRestore() && VarArgsSaveSize == 0 && !MF.getFrameInfo().hasTailCall(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/Subtarget.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/Subtarget.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b485bfc3f8c679a1968fbd947cfb7a1a630ceb15 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/Subtarget.cpp @@ -0,0 +1,7 @@ +RISCVSubtarget::RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, StringRef ABIName, const TargetMachine &TM) : RISCVGenSubtargetInfo(TT, CPU, TuneCPU, FS), UserReservedRegister(RISCV::NUM_TARGET_REGS), FrameLowering(initializeSubtargetDependencies(TT, CPU, TuneCPU, FS, ABIName)), InstrInfo(*this), RegInfo(getHwMode()), TLInfo(TM, *this) { + CallLoweringInfo.reset(new RISCVCallLowering(*getTargetLowering())); + Legalizer.reset(new RISCVLegalizerInfo(*this)); + auto *RBI = new RISCVRegisterBankInfo(*getRegisterInfo()); + RegBankInfo.reset(RBI); + InstSelector.reset(createRISCVInstructionSelector(*static_cast(&TM), *this, *RBI)); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/anchor.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/anchor.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3c6f04a53d1e860d1cb5cb48fc428103a470ef0f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/anchor.cpp @@ -0,0 +1,2 @@ +void RISCVSubtarget::anchor() { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/enableLinkerRelax.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/enableLinkerRelax.cpp new file mode 100644 index 0000000000000000000000000000000000000000..21de073065f1c45c637d96155064fa1e17a1de02 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/enableLinkerRelax.cpp @@ -0,0 +1,3 @@ +bool enableLinkerRelax() const { + return EnableLinkerRelax; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/enableMachineScheduler.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/enableMachineScheduler.cpp new file mode 100644 index 0000000000000000000000000000000000000000..358b44992259774bd76684c0ec9175e49433d00f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/enableMachineScheduler.cpp @@ -0,0 +1,3 @@ +bool enableMachineScheduler() const override { + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/enableRVCHintInstrs.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/enableRVCHintInstrs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a15b00dc080602258900bbbe99e7e945b36ba6cb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/enableRVCHintInstrs.cpp @@ -0,0 +1,3 @@ +bool enableRVCHintInstrs() const { + return EnableRVCHintInstrs; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/enableSaveRestore.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/enableSaveRestore.cpp new file mode 100644 index 0000000000000000000000000000000000000000..343f8da6be2a7efb133ed8ceb361f0e04baf970c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/enableSaveRestore.cpp @@ -0,0 +1,3 @@ +bool enableSaveRestore() const { + return EnableSaveRestore; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/getCallLowering.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/getCallLowering.cpp new file mode 100644 index 0000000000000000000000000000000000000000..38840e3abf5721f2f2bb806ec7b4c36e9c80c33b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/getCallLowering.cpp @@ -0,0 +1,3 @@ +const CallLowering *RISCVSubtarget::getCallLowering() const { + return CallLoweringInfo.get(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/getFrameLowering.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/getFrameLowering.cpp new file mode 100644 index 0000000000000000000000000000000000000000..dbbed9b4540b34f6fcda3e88827d89fc8b271b92 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/getFrameLowering.cpp @@ -0,0 +1,3 @@ +const RISCVFrameLowering *getFrameLowering() const override { + return &FrameLowering; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/getInstrInfo.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/getInstrInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..241a6f789b9336fb755e0f8bd27f6411d2016581 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/getInstrInfo.cpp @@ -0,0 +1,3 @@ +const RISCVInstrInfo *getInstrInfo() const override { + return &InstrInfo; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/getInstructionSelector.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/getInstructionSelector.cpp new file mode 100644 index 0000000000000000000000000000000000000000..48c25e17f0bcb2c488a43f59965f14252652be1b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/getInstructionSelector.cpp @@ -0,0 +1,3 @@ +InstructionSelector *RISCVSubtarget::getInstructionSelector() const { + return InstSelector.get(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/getLegalizerInfo.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/getLegalizerInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..34b918d70ad4c109ca034168fc2dc5f7762cba5c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/getLegalizerInfo.cpp @@ -0,0 +1,3 @@ +const LegalizerInfo *RISCVSubtarget::getLegalizerInfo() const { + return Legalizer.get(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/getRegBankInfo.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/getRegBankInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e51ba7750e72c82e020ae09634218d29c8b6e080 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/getRegBankInfo.cpp @@ -0,0 +1,3 @@ +const RegisterBankInfo *RISCVSubtarget::getRegBankInfo() const { + return RegBankInfo.get(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/getRegisterInfo.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/getRegisterInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0323310ac0e1eb0128dc614c5b8e5810c97fd662 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/getRegisterInfo.cpp @@ -0,0 +1,3 @@ +const RISCVRegisterInfo *getRegisterInfo() const override { + return &RegInfo; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/getSelectionDAGInfo.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/getSelectionDAGInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a587bb87c2bf9c4c35e25ccfee788761dc1d8a6a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/getSelectionDAGInfo.cpp @@ -0,0 +1,3 @@ +const SelectionDAGTargetInfo *getSelectionDAGInfo() const override { + return &TSInfo; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/getTargetABI.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/getTargetABI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6ba240b805d561f415ec4ee11045c3d6eb8dea8e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/getTargetABI.cpp @@ -0,0 +1,3 @@ +RISCVABI::ABI getTargetABI() const { + return TargetABI; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/getTargetLowering.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/getTargetLowering.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ae252b5d67893ec68615f1dfafc89e95b3676d6d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/getTargetLowering.cpp @@ -0,0 +1,3 @@ +const RISCVTargetLowering *getTargetLowering() const override { + return &TLInfo; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/getXLen.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/getXLen.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1b93e9c9f4885d72046bc33a4c96130e4796e755 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/getXLen.cpp @@ -0,0 +1,3 @@ +unsigned getXLen() const { + return XLen; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/getXLenVT.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/getXLenVT.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f65801b1cfce99bb6f22e7828e3f2be8e8095ddb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/getXLenVT.cpp @@ -0,0 +1,3 @@ +MVT getXLenVT() const { + return XLenVT; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtA.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtA.cpp new file mode 100644 index 0000000000000000000000000000000000000000..045084578632528b294c467beabb11bcec85b93e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtA.cpp @@ -0,0 +1,3 @@ +bool hasStdExtA() const { + return HasStdExtA; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtB.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtB.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c102f9d01106d3f90c03b80ad507bf41a61fbdbe --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtB.cpp @@ -0,0 +1,3 @@ +bool hasStdExtB() const { + return HasStdExtB; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtC.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..785c95523c80c75eaae143f94294a1b159b11b27 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtC.cpp @@ -0,0 +1,3 @@ +bool hasStdExtC() const { + return HasStdExtC; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtD.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtD.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c0d41f4cdb4f7a92d8a9ce0c402a53b8cc7697a7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtD.cpp @@ -0,0 +1,3 @@ +bool hasStdExtD() const { + return HasStdExtD; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtF.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtF.cpp new file mode 100644 index 0000000000000000000000000000000000000000..dfe330377a0077baad1cc0ee8b900335fc99c7a5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtF.cpp @@ -0,0 +1,3 @@ +bool hasStdExtF() const { + return HasStdExtF; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtM.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtM.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f5e79be711a1b0176abd5623e66e222d8106828b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtM.cpp @@ -0,0 +1,3 @@ +bool hasStdExtM() const { + return HasStdExtM; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtV.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtV.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5223acaac264f68a6fc3f33c7b15e6d79e1dffd7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtV.cpp @@ -0,0 +1,3 @@ +bool hasStdExtV() const { + return HasStdExtV; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtZba.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtZba.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fa2fdb498d75c1d5e09f33e14da97cb8b6c439cf --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtZba.cpp @@ -0,0 +1,3 @@ +bool hasStdExtZba() const { + return HasStdExtZba; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtZbb.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtZbb.cpp new file mode 100644 index 0000000000000000000000000000000000000000..580a2ecde2d98f6211573d9c0182a66888e30a4f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtZbb.cpp @@ -0,0 +1,3 @@ +bool hasStdExtZbb() const { + return HasStdExtZbb; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtZbc.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtZbc.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3665774de6ea27b4f43cc2ce9725e3ef8ee03f24 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtZbc.cpp @@ -0,0 +1,3 @@ +bool hasStdExtZbc() const { + return HasStdExtZbc; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtZbe.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtZbe.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b885070bf501e4aa033b5c64c27d6cde94fd574f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtZbe.cpp @@ -0,0 +1,3 @@ +bool hasStdExtZbe() const { + return HasStdExtZbe; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtZbf.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtZbf.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9d30a77301e6f77bcf71149553258fdf6ba72802 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtZbf.cpp @@ -0,0 +1,3 @@ +bool hasStdExtZbf() const { + return HasStdExtZbf; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtZbm.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtZbm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..64e8f6da0a82c37c1c84768cfbd9c41e4f9d4c27 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtZbm.cpp @@ -0,0 +1,3 @@ +bool hasStdExtZbm() const { + return HasStdExtZbm; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtZbp.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtZbp.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e70ce03f491bf72fc64954ff90e195393b67e99c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtZbp.cpp @@ -0,0 +1,3 @@ +bool hasStdExtZbp() const { + return HasStdExtZbp; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtZbproposedc.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtZbproposedc.cpp new file mode 100644 index 0000000000000000000000000000000000000000..05ca4bea84b6696d19aafd851732afc5363c7ee5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtZbproposedc.cpp @@ -0,0 +1,3 @@ +bool hasStdExtZbproposedc() const { + return HasStdExtZbproposedc; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtZbr.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtZbr.cpp new file mode 100644 index 0000000000000000000000000000000000000000..88f9e522cd20fd732d826a9b8eaeb7f76be8551f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtZbr.cpp @@ -0,0 +1,3 @@ +bool hasStdExtZbr() const { + return HasStdExtZbr; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtZbs.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtZbs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..77d6819e118c6e1f82cdedf26c55783737418fb3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtZbs.cpp @@ -0,0 +1,3 @@ +bool hasStdExtZbs() const { + return HasStdExtZbs; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtZbt.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtZbt.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8432f49748cc5b1627de7d8aa7e42ab26c5463bd --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtZbt.cpp @@ -0,0 +1,3 @@ +bool hasStdExtZbt() const { + return HasStdExtZbt; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtZfh.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtZfh.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6b8f1a64d51d18301744d11c4f5879d8ae084a21 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtZfh.cpp @@ -0,0 +1,3 @@ +bool hasStdExtZfh() const { + return HasStdExtZfh; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtZvamo.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtZvamo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4f140c6331d83ac7a5f8d0308537923cdac4b480 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtZvamo.cpp @@ -0,0 +1,3 @@ +bool hasStdExtZvamo() const { + return HasStdExtZvamo; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtZvlsseg.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtZvlsseg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d9c8265a1f76104be737068c99616f36543fa720 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/hasStdExtZvlsseg.cpp @@ -0,0 +1,3 @@ +bool hasStdExtZvlsseg() const { + return HasStdExtZvlsseg; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/initializeSubtargetDependencies.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/initializeSubtargetDependencies.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1562b15f36a42ad7a0b97b1c0cc718835185508c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/initializeSubtargetDependencies.cpp @@ -0,0 +1,19 @@ +RISCVSubtarget &RISCVSubtarget::initializeSubtargetDependencies(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, StringRef ABIName) { + bool Is64Bit = TT.isArch64Bit(); + std::string CPUName = std::string(CPU); + std::string TuneCPUName = std::string(TuneCPU); + if (CPUName.empty()) { + CPUName = Is64Bit ? "generic-rv64" : "generic-rv32"; + } + if (TuneCPUName.empty()) { + TuneCPUName = CPUName; + } + ParseSubtargetFeatures(CPUName, TuneCPUName, FS); + if (Is64Bit) { + XLenVT = MVT::i64; + XLen = 64; + } + TargetABI = RISCVABI::computeTargetABI(TT, getFeatureBits(), ABIName); + RISCVFeatures::validate(TT, getFeatureBits()); + return *this; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/is64Bit.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/is64Bit.cpp new file mode 100644 index 0000000000000000000000000000000000000000..026df9778ca9ddace0d34a9f3e0d8eb157bd293e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/is64Bit.cpp @@ -0,0 +1,3 @@ +bool is64Bit() const { + return HasRV64; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/isRV32E.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/isRV32E.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e9fc1cb3169afb18c1184d05bcd22cb858a5676e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/isRV32E.cpp @@ -0,0 +1,3 @@ +bool isRV32E() const { + return IsRV32E; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/isRegisterReservedByUser.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/isRegisterReservedByUser.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8ac2e733fe0b3623076323b1347a74e43a721deb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/Subtarget/isRegisterReservedByUser.cpp @@ -0,0 +1,4 @@ +bool isRegisterReservedByUser(Register R) const { + assert(R < RISCV::NUM_TARGET_REGS && "Register out of range"); + return UserReservedRegister[R]; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetInfo/LLVMInitializeTargetInfo.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetInfo/LLVMInitializeTargetInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..37b315659994b32de45ce8870d6a29db4acfbd3a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetInfo/LLVMInitializeTargetInfo.cpp @@ -0,0 +1,4 @@ +extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTargetInfo() { + RegisterTarget X(getTheRISCV32Target(), "riscv32", "32-bit RISC-V", "RISCV"); + RegisterTarget Y(getTheRISCV64Target(), "riscv64", "64-bit RISC-V", "RISCV"); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetInfo/getThe32Target.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetInfo/getThe32Target.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6d0317f9493f86d48647af0d9d65986f46cbf77b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetInfo/getThe32Target.cpp @@ -0,0 +1,4 @@ +Target &llvm::getTheRISCV32Target() { + static Target TheRISCV32Target; + return TheRISCV32Target; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetInfo/getThe64Target.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetInfo/getThe64Target.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f7a649e2d1dcc685575c2f9ec1dca9aaf6fa8aba --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetInfo/getThe64Target.cpp @@ -0,0 +1,4 @@ +Target &llvm::getTheRISCV64Target() { + static Target TheRISCV64Target; + return TheRISCV64Target; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/LLVMInitializeTarget.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/LLVMInitializeTarget.cpp new file mode 100644 index 0000000000000000000000000000000000000000..31b9278f970215379e2dc8061f277dad1d569d9a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/LLVMInitializeTarget.cpp @@ -0,0 +1,9 @@ +extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() { + RegisterTargetMachine X(getTheRISCV32Target()); + RegisterTargetMachine Y(getTheRISCV64Target()); + auto *PR = PassRegistry::getPassRegistry(); + initializeGlobalISel(*PR); + initializeRISCVMergeBaseOffsetOptPass(*PR); + initializeRISCVExpandPseudoPass(*PR); + initializezmtarzmCleanupVSETVLIFPass(*PR); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/PassConfig.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/PassConfig.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b20b53464b621e4e92357ebd6307c69ffb9a40e4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/PassConfig.cpp @@ -0,0 +1,2 @@ +RISCVPassConfig(RISCVTargetMachine &TM, PassManagerBase &PM) : TargetPassConfig(TM, PM) { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/TargetMachine.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/TargetMachine.cpp new file mode 100644 index 0000000000000000000000000000000000000000..73ec6bedf09619270970355907e32b855791f128 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/TargetMachine.cpp @@ -0,0 +1,4 @@ +RISCVTargetMachine::RISCVTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional RM, CodeModel::Model CM, CodeGenOpt::Level OL) : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, getEffectiveRelocModel(RM), CM, OL), TLOF(make_unique()), Subtarget(TT, CPU, FS, *this) { + initAsmInfo(); + setMachineOutliner(true); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/addGlobalInstructionSelect.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/addGlobalInstructionSelect.cpp new file mode 100644 index 0000000000000000000000000000000000000000..53a717c5a28993e11ab524b64f8f9b5dde960abc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/addGlobalInstructionSelect.cpp @@ -0,0 +1,4 @@ +bool RISCVPassConfig::addGlobalInstructionSelect() { + addPass(new InstructionSelect()); + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/addIRPasses.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/addIRPasses.cpp new file mode 100644 index 0000000000000000000000000000000000000000..249cfd6b8fbbd2f318e66c2e9edcc522e72786ce --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/addIRPasses.cpp @@ -0,0 +1,4 @@ +void RISCVPassConfig::addIRPasses() { + addPass(createAtomicExpandPass()); + TargetPassConfig::addIRPasses(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/addIRTranslator.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/addIRTranslator.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e40ddbd47024c1bb26c2d10c54d2d2fb0c3c73f0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/addIRTranslator.cpp @@ -0,0 +1,4 @@ +bool RISCVPassConfig::addIRTranslator() { + addPass(new IRTranslator(getOptLevel())); + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/addInstSelector.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/addInstSelector.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bceda22a3721c766e191bd621bc2068efb9440e4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/addInstSelector.cpp @@ -0,0 +1,4 @@ +bool RISCVPassConfig::addInstSelector() { + addPass(createRISCVISelDag(getRISCVTargetMachine())); + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/addLegalizeMachineIR.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/addLegalizeMachineIR.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1932ec43e2cbb1e9ec97351c4421aa1d7c006317 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/addLegalizeMachineIR.cpp @@ -0,0 +1,4 @@ +bool RISCVPassConfig::addLegalizeMachineIR() { + addPass(new Legalizer()); + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/addPreEmitPass.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/addPreEmitPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c2ff69c52170cecce0743c34b95be10f32f76ce5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/addPreEmitPass.cpp @@ -0,0 +1,3 @@ +void RISCVPassConfig::addPreEmitPass() { + addPass(&BranchRelaxationPassID); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/addPreEmitPass2.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/addPreEmitPass2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c38087130942d1670807ab16f94ce2e515968fea --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/addPreEmitPass2.cpp @@ -0,0 +1,4 @@ +void RISCVPassConfig::addPreEmitPass() { + addPass(createRISCVExpandPseudoPass()); + addPass(createRISCVExpandAtomicPseudoPass()); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/addPreRegAlloc.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/addPreRegAlloc.cpp new file mode 100644 index 0000000000000000000000000000000000000000..91d224213b9714fe986f9b542807c866994eef03 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/addPreRegAlloc.cpp @@ -0,0 +1,8 @@ +void RISCVPassConfig::addPreRegAlloc() { + addPass(createRISCVExpandSDMAPass()); + addPass(createRISCVExpandSSRPass()); + if (TM->getOptLevel() != CodeGenOpt::None) { + addPass(createRISCVMergeBaseOffsetOptPass()); + addPass(createRISCVCleanupVSETVLIPass()); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/addPreSched2.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/addPreSched2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4ca661dadbfb7d390a899a4418bf15b9e1daeb40 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/addPreSched2.cpp @@ -0,0 +1,2 @@ +void RISCVPassConfig::addPreSched2() { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/addRegBankSelect.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/addRegBankSelect.cpp new file mode 100644 index 0000000000000000000000000000000000000000..784ce6e69101604753ad0faae4ce064c8ac54a6b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/addRegBankSelect.cpp @@ -0,0 +1,4 @@ +bool RISCVPassConfig::addRegBankSelect() { + addPass(new RegBankSelect()); + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/computeDataLayout.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/computeDataLayout.cpp new file mode 100644 index 0000000000000000000000000000000000000000..708e44f701b3c83fd60458fe275223a2e0e880ae --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/computeDataLayout.cpp @@ -0,0 +1,7 @@ +static StringRef computeDataLayout(const Triple &TT) { + if (TT.isArch64Bit()) { + return "e-m:e-p:64:64-i64:64-i128:128-n64-S128"; + } + assert(TT.isArch32Bit() && "only RV32 and RV64 are currently supported"); + return "e-m:e-p:32:32-i64:64-n32-S128"; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/createPassConfig.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/createPassConfig.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e26ed90631bc09a534221d3b0d89d3d0fb4a2f08 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/createPassConfig.cpp @@ -0,0 +1,3 @@ +TargetPassConfig *RISCVTargetMachine::createPassConfig(PassManagerBase &PM) { + return new RISCVPassConfig(*this, PM); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/getEffectiveRelocModel.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/getEffectiveRelocModel.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f8e47bfda9700302b8897ba128ce6aaa4acfbb8d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/getEffectiveRelocModel.cpp @@ -0,0 +1,6 @@ +static Reloc::Model getEffectiveRelocModel(const Triple &TT, Optional RM) { + if (!RM.hasValue()) { + return Reloc::Static; + } + return *RM; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/getObjFileLowering.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/getObjFileLowering.cpp new file mode 100644 index 0000000000000000000000000000000000000000..191f39130017a606dd77f12beee5e067e30a1edd --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/getObjFileLowering.cpp @@ -0,0 +1,3 @@ +TargetLoweringObjectFile *getObjFileLowering() const override { + return TLOF.get(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/getSubtargetImpl.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/getSubtargetImpl.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3910b1ff75ce36bb25563a278318b819a66dd309 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/getSubtargetImpl.cpp @@ -0,0 +1,25 @@ +const RISCVSubtarget *RISCVTargetMachine::getSubtargetImpl(const Function &F) const { + Attribute TuneAttr = F.getFnAttribute("tune-cpu"); + Attribute CPUAttr = F.getFnAttribute("target-cpu"); + Attribute FSAttr = F.getFnAttribute("target-features"); + std::string CPU = CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU; + std::string TuneCPU = TuneAttr.isValid() ? TuneAttr.getValueAsString().str() : CPU; + std::string FS = FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS; + std::string Key = CPU + TuneCPU + FS; + auto &I = SubtargetMap[Key]; + if (!I) { + resetTargetOptions(F); + auto ABIName = Options.MCOptions.getABIName(); + if (const MDString *ModuleTargetABI = dyn_cast_or_null(F.getParent()->getModuleFlag("target-abi"))) { + auto TargetABI = RISCVABI::getTargetABI(ABIName); + if (TargetABI != RISCVABI::ABI_Unknown) { + if (ModuleTargetABI->getString() != ABIName) { + report_fatal_error("-target-abi option != target-abi module flag"); + } + } + ABIName = ModuleTargetABI->getString(); + } + I = std::make_unique(TargetTriple, CPU, TuneCPU, FS, ABIName, *this); + } + return I.get(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/getTargetMachine.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/getTargetMachine.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5a41a250abddaaf2f72411583edeb8514ecc15fb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/getTargetMachine.cpp @@ -0,0 +1,3 @@ +RISCVTargetMachine &getRISCVTargetMachine() const { + return getTM(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/getTargetTransformInfo.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/getTargetTransformInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..de21c28d38b6b1f01d074c67513e6cefd58f284b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/getTargetTransformInfo.cpp @@ -0,0 +1,3 @@ +TargetTransformInfo RISCVTargetMachine::getTargetTransformInfo(const Function &F) { + return TargetTransformInfo(RISCVTTIImpl(this, F)); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/isNoopAddrSpaceCast.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/isNoopAddrSpaceCast.cpp new file mode 100644 index 0000000000000000000000000000000000000000..40909ed282d63a3b6673b49e76d705f5bac453f3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetMachine/isNoopAddrSpaceCast.cpp @@ -0,0 +1,3 @@ +bool RISCVTargetMachine::isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const { + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetObjectFile/Initialize.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetObjectFile/Initialize.cpp new file mode 100644 index 0000000000000000000000000000000000000000..98b08bcc1f079b2714504cf436a5a7c3530e1885 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetObjectFile/Initialize.cpp @@ -0,0 +1,5 @@ +void RISCVELFTargetObjectFile::Initialize(MCContext &Ctx, const TargetMachine &TM) { + TargetLoweringObjectFileELF::Initialize(Ctx, TM); + SmallDataSection = getContext().getELFSection(".sdata", ELF::SHT_PROGBITS, ELF::SHF_WRITE | ELF::SHF_ALLOC); + SmallBSSSection = getContext().getELFSection(".sbss", ELF::SHT_NOBITS, ELF::SHF_WRITE | ELF::SHF_ALLOC); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetObjectFile/SelectSectionForGlobal.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetObjectFile/SelectSectionForGlobal.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b6e5fb66e33a68d6f5d4aa6fbd6fa67a49ee342a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetObjectFile/SelectSectionForGlobal.cpp @@ -0,0 +1,9 @@ +MCSection *RISCVELFTargetObjectFile::SelectSectionForGlobal(const GlobalObject *GO, SectionKind Kind, const TargetMachine &TM) const { + if (Kind.isBSS() && isGlobalInSmallSection(GO, TM)) { + return SmallBSSSection; + } + if (Kind.isData() && isGlobalInSmallSection(GO, TM)) { + return SmallDataSection; + } + return TargetLoweringObjectFileELF::SelectSectionForGlobal(GO, Kind, TM); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetObjectFile/getModuleMetadata.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetObjectFile/getModuleMetadata.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fbe0c45c090047e1d764d2795db62ec1e15fe255 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetObjectFile/getModuleMetadata.cpp @@ -0,0 +1,11 @@ +void RISCVELFTargetObjectFile::getModuleMetadata(Module &M) { + SmallVector ModuleFlags; + M.getModuleFlagsMetadata(ModuleFlags); + for (const auto &MFE : ModuleFlags) { + StringRef Key = MFE.Key->getString(); + if (Key == "SmallDataLimit") { + SSThreshold = mdconst::extract(MFE.Val)->getZExtValue(); + break; + } + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetObjectFile/getSectionForConstant.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetObjectFile/getSectionForConstant.cpp new file mode 100644 index 0000000000000000000000000000000000000000..88aa5000ec9d5a0ffc49ae8b1b6bb97bb7707153 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetObjectFile/getSectionForConstant.cpp @@ -0,0 +1,6 @@ +MCSection *RISCVELFTargetObjectFile::getSectionForConstant( const DataLayout &DL, SectionKind Kind, const Constant *C, Align &Alignment) const { + if (isConstantInSmallSection(DL, C)) { + return SmallDataSection; + } + return TargetLoweringObjectFileELF::getSectionForConstant(DL, Kind, C, Alignment); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetObjectFile/isConstantInSmallSection.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetObjectFile/isConstantInSmallSection.cpp new file mode 100644 index 0000000000000000000000000000000000000000..03070c7967520e2db15231715cdf5404fe77cef0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetObjectFile/isConstantInSmallSection.cpp @@ -0,0 +1,3 @@ +bool RISCVELFTargetObjectFile::isConstantInSmallSection(const DataLayout &DL, const Constant *CN) const { + return isInSmallSection(DL.getTypeAllocSize(CN->getType())); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetObjectFile/isGlobalInSmallSection.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetObjectFile/isGlobalInSmallSection.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d15ea59c38f894725279f9fb82f0731c79548e5a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetObjectFile/isGlobalInSmallSection.cpp @@ -0,0 +1,21 @@ +bool RISCVELFTargetObjectFile::isGlobalInSmallSection(const GlobalObject *GO, const TargetMachine &TM) const { + const GlobalVariable *GVA = dyn_cast(GO); + if (!GVA) { + return false; + } + if (GVA->hasSection()) { + StringRef Section = GVA->getSection(); + if (Section == ".sdata" || Section == ".sbss") { + return true; + } + return false; + } + if (((GVA->hasExternalLinkage() && GVA->isDeclaration()) || GVA->hasCommonLinkage())) { + return false; + } + Type *Ty = GVA->getValueType(); + if (!Ty->isSized()) { + return false; + } + return isInSmallSection(GVA->getParent()->getDataLayout().getTypeAllocSize(Ty)); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetObjectFile/isInSmallSection.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetObjectFile/isInSmallSection.cpp new file mode 100644 index 0000000000000000000000000000000000000000..77772fb82ad184a8a4d2455cbc1cf202550c1af0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetObjectFile/isInSmallSection.cpp @@ -0,0 +1,3 @@ +bool RISCVELFTargetObjectFile::isInSmallSection(uint64_t Size) const { + return Size > 0 && Size <= SSThreshold; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetTransformInfo/TTIImpl.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetTransformInfo/TTIImpl.cpp new file mode 100644 index 0000000000000000000000000000000000000000..22191cb2dea9757287f93e29e9e0f5d88a5abc6c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetTransformInfo/TTIImpl.cpp @@ -0,0 +1,2 @@ +explicit RISCVTTIImpl(const RISCVTargetMachine *TM, const Function &F) : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)), TLI(ST->getTargetLowering()) { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetTransformInfo/getIntImmCost.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetTransformInfo/getIntImmCost.cpp new file mode 100644 index 0000000000000000000000000000000000000000..01d7fd4a5292e1d82961e69efa3f3bd08f29ff0a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetTransformInfo/getIntImmCost.cpp @@ -0,0 +1,8 @@ +int RISCVTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) { + assert(Ty->isIntegerTy() && "getIntImmCost can only estimate cost of materialising integers"); + if (Imm == 0) { + return TTI::TCC_Free; + } + const DataLayout &DL = getDataLayout(); + return RISCVMatInt::getIntMatCost(Imm, DL.getTypeSizeInBits(Ty), getST()->is64Bit()); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetTransformInfo/getIntImmCostInst.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetTransformInfo/getIntImmCostInst.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0c01363a8faf86a4c31e05ebe57cad34936b229 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetTransformInfo/getIntImmCostInst.cpp @@ -0,0 +1,37 @@ +int RISCVTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, Instruction *Inst) { + assert(Ty->isIntegerTy() && "getIntImmCost can only estimate cost of materialising integers"); + if (Imm == 0) { + return TTI::TCC_Free; + } + bool Takes12BitImm = false; + unsigned ImmArgIdx = ~0U; + switch (Opcode) { + case Instruction::GetElementPtr: + return TTI::TCC_Free; + case Instruction::Add: + case Instruction::And: + case Instruction::Or: + case Instruction::Xor: + case Instruction::Mul: + Takes12BitImm = true; + break; + case Instruction::Sub: + case Instruction::Shl: + case Instruction::LShr: + case Instruction::AShr: + Takes12BitImm = true; + ImmArgIdx = 1; + break; + default: + break; + } + if (Takes12BitImm) { + if (Instruction::isCommutative(Opcode) || Idx == ImmArgIdx) { + if (Imm.getMinSignedBits() <= 64 && getTLI()->isLegalAddImmediate(Imm.getSExtValue())) { + return TTI::TCC_Free; + } + } + return getIntImmCost(Imm, Ty, CostKind); + } + return TTI::TCC_Free; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetTransformInfo/getIntImmCostIntrin.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetTransformInfo/getIntImmCostIntrin.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ff244e23aa7c352fb557907d1c8528e63c9cf942 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetTransformInfo/getIntImmCostIntrin.cpp @@ -0,0 +1,3 @@ +int RISCVTTIImpl::getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) { + return TTI::TCC_Free; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetTransformInfo/getST.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetTransformInfo/getST.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3085911b846be9fe97364305924fd1e72c52af7f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetTransformInfo/getST.cpp @@ -0,0 +1,3 @@ +const RISCVSubtarget *getST() const { + return ST; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetTransformInfo/getTLI.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetTransformInfo/getTLI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4e8723265e898db24c643b890ede218d98cd5b62 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Scheduling/TargetTransformInfo/getTLI.cpp @@ -0,0 +1,3 @@ +const RISCVTargetLowering *getTLI() const { + return TLI; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/CallLowering/CallLowering.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/CallLowering/CallLowering.cpp new file mode 100644 index 0000000000000000000000000000000000000000..44322d52c70e92f7e669a7c814a0825858d8a83d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/CallLowering/CallLowering.cpp @@ -0,0 +1,2 @@ +RISCVCallLowering::RISCVCallLowering(const RISCVTargetLowering &TLI) : CallLowering(&TLI) { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/CallLowering/lowerCall.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/CallLowering/lowerCall.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fc8637b1f0ea4b69b232a8c00e5c54df10bb470a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/CallLowering/lowerCall.cpp @@ -0,0 +1,3 @@ +bool RISCVCallLowering::lowerCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info) const { + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/CallLowering/lowerFormalArguments.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/CallLowering/lowerFormalArguments.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f8344a5c36b8b7f909b3f5bfff96e829687e6d80 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/CallLowering/lowerFormalArguments.cpp @@ -0,0 +1,6 @@ +bool RISCVCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef> VRegs, FunctionLoweringInfo &FLI) const { + if (F.arg_empty()) { + return true; + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/CallLowering/lowerReturn.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/CallLowering/lowerReturn.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9a0a34ed59d315e93fb2eb0040afebfc1ef94e7c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/CallLowering/lowerReturn.cpp @@ -0,0 +1,8 @@ +bool RISCVCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val, ArrayRef VRegs, FunctionLoweringInfo &FLI) const { + MachineInstrBuilder Ret = MIRBuilder.buildInstrNoInsert(RISCV::PseudoRET); + if (Val != nullptr) { + return false; + } + MIRBuilder.insertInstr(Ret); + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/FrameLowering/FrameLowering.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/FrameLowering/FrameLowering.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cc75bbabc713bf9ef22e7fb35f9ba8e802457383 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/FrameLowering/FrameLowering.cpp @@ -0,0 +1,2 @@ +explicit RISCVFrameLowering(const RISCVSubtarget &STI) : TargetFrameLowering(StackGrowsDown, Align(16), 0), STI(STI) { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/FrameLowering/adjustReg.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/FrameLowering/adjustReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c7dae994073558b0f037aa2e910c54258b035e8d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/FrameLowering/adjustReg.cpp @@ -0,0 +1,21 @@ +void RISCVFrameLowering::adjustReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register DestReg, Register SrcReg, int64_t Val, MachineInstr::MIFlag Flag) const { + MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); + const RISCVInstrInfo *TII = STI.getInstrInfo(); + if (DestReg == SrcReg && Val == 0) { + return ; + } + if (isInt<12>(Val)) { + BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), DestReg).addReg(SrcReg).addImm(Val).setMIFlag(Flag); + } + else { + unsigned Opc = RISCV::ADD; + bool isSub = Val < 0; + if (isSub) { + Val = -Val; + Opc = RISCV::SUB; + } + Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); + TII->movImm(MBB, MBBI, DL, ScratchReg, Val, Flag); + BuildMI(MBB, MBBI, DL, TII->get(Opc), DestReg).addReg(SrcReg).addReg(ScratchReg, RegState::Kill).setMIFlag(Flag); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/FrameLowering/canUseAsEpilogue.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/FrameLowering/canUseAsEpilogue.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bc50f8ce2fe6c77b83a82dd1c51e99b053cfcf64 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/FrameLowering/canUseAsEpilogue.cpp @@ -0,0 +1,16 @@ +bool RISCVFrameLowering::canUseAsEpilogue(const MachineBasicBlock &MBB) const { + const MachineFunction *MF = MBB.getParent(); + MachineBasicBlock *TmpMBB = const_cast(&MBB); + const auto *RVFI = MF->getInfo(); + if (!RVFI->useSaveRestoreLibCalls(*MF)) { + return true; + } + if (MBB.succ_size() > 1) { + return false; + } + MachineBasicBlock *SuccMBB = MBB.succ_empty() ? TmpMBB->getFallThrough() : *MBB.succ_begin(); + if (!SuccMBB) { + return true; + } + return SuccMBB->isReturnBlock() && SuccMBB->size() == 1; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/FrameLowering/canUseAsPrologue.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/FrameLowering/canUseAsPrologue.cpp new file mode 100644 index 0000000000000000000000000000000000000000..14ca7440ae53421c255bd958604dfcb5a32e346e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/FrameLowering/canUseAsPrologue.cpp @@ -0,0 +1,11 @@ +bool RISCVFrameLowering::canUseAsPrologue(const MachineBasicBlock &MBB) const { + MachineBasicBlock *TmpMBB = const_cast(&MBB); + const MachineFunction *MF = MBB.getParent(); + const auto *RVFI = MF->getInfo(); + if (!RVFI->useSaveRestoreLibCalls(*MF)) { + return true; + } + RegScavenger RS; + RS.enterBasicBlock(*TmpMBB); + return !RS.isRegUsed(RISCV::X5); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/FrameLowering/determineCalleeSaves.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/FrameLowering/determineCalleeSaves.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cc90cf82ab0d07d668daf8218552e032d84faba6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/FrameLowering/determineCalleeSaves.cpp @@ -0,0 +1,25 @@ +void RISCVFrameLowering::determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS) const { + TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS); + if (hasFP(MF)) { + SavedRegs.set(RISCV::X1); + SavedRegs.set(RISCV::X8); + } + if (hasBP(MF)) { + SavedRegs.set(RISCVABI::getBPReg()); + } + MachineFrameInfo &MFI = MF.getFrameInfo(); + if (MF.getFunction().hasFnAttribute("interrupt") && MFI.hasCalls()) { + static const MCPhysReg CSRegs[] = { RISCV::X1, RISCV::X5, RISCV::X6, RISCV::X7, RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31, 0}; + for (unsigned i = 0; CSRegs[i]; ++i) { + SavedRegs.set(CSRegs[i]); + } + if (MF.getSubtarget().hasStdExtF()) { + const MCPhysReg * Regs = MF.getRegInfo().getCalleeSavedRegs(); + for (unsigned i = 0; Regs[i]; ++i) { + if (RISCV::FPR16RegClass.contains(Regs[i]) || RISCV::FPR32RegClass.contains(Regs[i]) || RISCV::FPR64RegClass.contains(Regs[i])) { + SavedRegs.set(Regs[i]); + } + } + } + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/FrameLowering/eliminateCallFramePseudoInstr.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/FrameLowering/eliminateCallFramePseudoInstr.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1fa9f9d14dc9c6fc09c3c01a88db76d2312e69df --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/FrameLowering/eliminateCallFramePseudoInstr.cpp @@ -0,0 +1,15 @@ +MachineBasicBlock::iterator RISCVFrameLowering::eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const { + Register SPReg = RISCV::X2; + DebugLoc DL = MI->getDebugLoc(); + if (!hasReservedCallFrame(MF)) { + int64_t Amount = MI->getOperand(0).getImm(); + if (Amount != 0) { + Amount = alignSPAdjust(Amount); + if (MI->getOpcode() == RISCV::ADJCALLSTACKDOWN) { + Amount = -Amount; + } + adjustReg(MBB, MI, DL, SPReg, SPReg, Amount, MachineInstr::NoFlags); + } + } + return MBB.erase(MI); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/FrameLowering/emitEpilogue.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/FrameLowering/emitEpilogue.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4e2061f54290ae445a02f9c65b6d8720cb59e141 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/FrameLowering/emitEpilogue.cpp @@ -0,0 +1,88 @@ +void RISCVFrameLowering::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { + const RISCVRegisterInfo *RI = STI.getRegisterInfo(); + MachineFrameInfo &MFI = MF.getFrameInfo(); + auto *RVFI = MF.getInfo(); + Register FPReg = RISCV::X8; + Register SPReg = RISCV::X2; + if (MF.getFunction().getCallingConv() == CallingConv::GHC) { + return; + } + MachineBasicBlock::iterator MBBI = MBB.end(); + DebugLoc DL; + if (!MBB.empty()) { + MBBI = MBB.getFirstTerminator(); + if (MBBI == MBB.end()) { + MBBI = MBB.getLastNonDebugInstr(); + } + DL = MBBI->getDebugLoc(); + if (!MBBI->isTerminator()) { + MBBI = std::next(MBBI); + } + while (MBBI != MBB.begin() && std::prev(MBBI)->getFlag(MachineInstr::FrameDestroy)) { + --MBBI; + } + } + SmallVector NonLibcallCSI; + for (auto &CS : MFI.getCalleeSavedInfo()) { + if (CS.getFrameIdx() >= 0) { + NonLibcallCSI.push_back(CS); + } + } + const auto &CSI = NonLibcallCSI; + auto LastFrameDestroy = MBBI; + if (!CSI.empty()) { + LastFrameDestroy = std::prev(MBBI, CSI.size()); + } + uint64_t StackSize = MFI.getStackSize(); + uint64_t RealStackSize = StackSize + RVFI->getLibCallStackSize(); + uint64_t FPOffset = RealStackSize - RVFI->getVarArgsSaveSize(); + if (RI->needsStackRealignment(MF) || MFI.hasVarSizedObjects()) { + assert(hasFP(MF) && "frame pointer should not have been eliminated"); + adjustReg(MBB, LastFrameDestroy, DL, SPReg, FPReg, -FPOffset, MachineInstr::FrameDestroy); + } + uint64_t FirstSPAdjustAmount = 0; + const auto *RVFI = MF.getInfo(); + const MachineFrameInfo &MFI = MF.getFrameInfo(); + const std::vector &CSI = MFI.getCalleeSavedInfo(); + uint64_t StackSize = MFI.getStackSize(); + if (RVFI->getLibCallStackSize()) { + FirstSPAdjustAmount = 0; + } + if (!isInt<12>(StackSize) && (CSI.size() > 0)) { + FirstSPAdjustAmount = 2048 - getStackAlign().value(); + } + if (FirstSPAdjustAmount) { + uint64_t SecondSPAdjustAmount = MFI.getStackSize() - FirstSPAdjustAmount; + assert(SecondSPAdjustAmount > 0 && "SecondSPAdjustAmount should be greater than zero"); + adjustReg(MBB, LastFrameDestroy, DL, SPReg, SPReg, SecondSPAdjustAmount, MachineInstr::FrameDestroy); + } + if (FirstSPAdjustAmount) { + StackSize = FirstSPAdjustAmount; + } + adjustReg(MBB, MBBI, DL, SPReg, SPReg, StackSize, MachineInstr::FrameDestroy); + if (!MF.getFunction().hasFnAttribute(Attribute::ShadowCallStack)) { + return; + } + const auto &STI = MF.getSubtarget(); + Register RAReg = STI.getRegisterInfo()->getRARegister();. + std::vector &CSI = MF.getFrameInfo().getCalleeSavedInfo(); + if (std::none_of(CSI.begin(), CSI.end(), [&](CalleeSavedInfo &CSR) { return CSR.getReg() == RAReg; })) { + return; + } + Register SCSPReg = RISCVABI::getSCSPReg(); + auto &Ctx = MF.getFunction().getContext(); + if (!STI.isRegisterReservedByUser(SCSPReg)) { + Ctx.diagnose(DiagnosticInfoUnsupported{MF.getFunction(), "x18 not reserved by user for Shadow Call Stack."}); + return; + } + const auto *RVFI = MF.getInfo(); + if (RVFI->useSaveRestoreLibCalls(MF)) { + Ctx.diagnose(DiagnosticInfoUnsupported{MF.getFunction(), "Shadow Call Stack cannot be combined with Save/Restore LibCalls."}); + return; + } + const RISCVInstrInfo *TII = STI.getInstrInfo(); + bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit); + int64_t SlotSize = STI.getXLen() / 8; + BuildMI(MBB, MI, DL, TII->get(IsRV64 ? RISCV::LD : RISCV::LW)).addReg(RAReg, RegState::Define).addReg(SCSPReg).addImm(-SlotSize); + BuildMI(MBB, MI, DL, TII->get(RISCV::ADDI)).addReg(SCSPReg, RegState::Define).addReg(SCSPReg).addImm(-SlotSize); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/FrameLowering/emitPrologue.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/FrameLowering/emitPrologue.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8048950b0f019688715749d1f0850f32087a97ea --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/FrameLowering/emitPrologue.cpp @@ -0,0 +1,130 @@ +void RISCVFrameLowering::emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const { + MachineFrameInfo &MFI = MF.getFrameInfo(); + auto *RVFI = MF.getInfo(); + const RISCVRegisterInfo *RI = STI.getRegisterInfo(); + const RISCVInstrInfo *TII = STI.getInstrInfo(); + MachineBasicBlock::iterator MBBI = MBB.begin(); + Register FPReg = RISCV::X8; + Register SPReg = RISCV::X2; + Register BPReg = RISCVABI::getBPReg(); + DebugLoc DL; + if (MF.getFunction().getCallingConv() == CallingConv::GHC) { + return ; + } + if (!MF.getFunction().hasFnAttribute(Attribute::ShadowCallStack)) { + return; + } + const auto &STI = MF.getSubtarget(); + Register RAReg = STI.getRegisterInfo()->getRARegister();. + std::vector &CSI = MF.getFrameInfo().getCalleeSavedInfo(); + if (std::none_of(CSI.begin(), CSI.end(), [&](CalleeSavedInfo &CSR) { return CSR.getReg() == RAReg; })) { + return; + } + Register SCSPReg = RISCVABI::getSCSPReg(); + auto &Ctx = MF.getFunction().getContext(); + if (!STI.isRegisterReservedByUser(SCSPReg)) { + Ctx.diagnose(DiagnosticInfoUnsupported{MF.getFunction(), "x18 not reserved by user for Shadow Call Stack."}); + return; + } + const auto *RVFI = MF.getInfo(); + if (RVFI->useSaveRestoreLibCalls(MF)) { + Ctx.diagnose(DiagnosticInfoUnsupported{MF.getFunction(), "Shadow Call Stack cannot be combined with Save/Restore LibCalls."}); + return; + } + const RISCVInstrInfo *TII = STI.getInstrInfo(); + bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit); + int64_t SlotSize = STI.getXLen() / 8; + BuildMI(MBB, MI, DL, TII->get(IsRV64 ? RISCV::LD : RISCV::LW)).addReg(RAReg, RegState::Define).addReg(SCSPReg).addImm(-SlotSize); + BuildMI(MBB, MI, DL, TII->get(RISCV::ADDI)).addReg(SCSPReg, RegState::Define).addReg(SCSPReg).addImm(-SlotSize); + while (MBBI != MBB.end() && MBBI->getFlag(MachineInstr::FrameSetup)) { + ++MBBI; + } + MachineFrameInfo &MFI = MF.getFrameInfo(); + uint64_t FrameSize = MFI.getStackSize(); + Align StackAlign = getStackAlign(); + uint64_t MaxCallSize = alignTo(MFI.getMaxCallFrameSize(), StackAlign); + MFI.setMaxCallFrameSize(MaxCallSize); + FrameSize = alignTo(FrameSize, StackAlign); + MFI.setStackSize(FrameSize); + if (int LibCallRegs = getLibCallID(MF, MFI.getCalleeSavedInfo()) + 1) { + unsigned LibCallFrameSize = alignTo((STI.getXLen() / 8) * LibCallRegs, 16); + RVFI->setLibCallStackSize(LibCallFrameSize); + } + uint64_t StackSize = MFI.getStackSize(); + uint64_t RealStackSize = StackSize + RVFI->getLibCallStackSize(); + if (RealStackSize == 0 && !MFI.adjustsStack()) { + return ; + } + if (STI.isRegisterReservedByUser(SPReg)) { + MF.getFunction().getContext().diagnose(DiagnosticInfoUnsupported{MF.getFunction(), "Stack pointer required, but has been reserved."}); + } + uint64_t FirstSPAdjustAmount = 0; + const auto *RVFI = MF.getInfo(); + const MachineFrameInfo &MFI = MF.getFrameInfo(); + const std::vector &CSI = MFI.getCalleeSavedInfo(); + uint64_t StackSize = MFI.getStackSize(); + if (RVFI->getLibCallStackSize()) { + FirstSPAdjustAmount = 0; + } + if (!isInt<12>(StackSize) && (CSI.size() > 0)) { + FirstSPAdjustAmount = 2048 - getStackAlign().value(); + } + if (FirstSPAdjustAmount) { + StackSize = FirstSPAdjustAmount; + RealStackSize = FirstSPAdjustAmount; + } + adjustReg(MBB, MBBI, DL, SPReg, SPReg, -StackSize, MachineInstr::FrameSetup); + unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, RealStackSize)); + BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)).addCFIIndex(CFIIndex); + const auto &CSI = MFI.getCalleeSavedInfo(); + std::advance(MBBI, getNonLibcallCSI(CSI).size()); + for (const auto &Entry : CSI) { + int FrameIdx = Entry.getFrameIdx(); + int64_t Offset; + if (FrameIdx < 0) { + Offset = FrameIdx * (int64_t) STI.getXLen() / 8; + } + else { + Offset = MFI.getObjectOffset(Entry.getFrameIdx()) - RVFI->getLibCallStackSize(); + } + Register Reg = Entry.getReg(); + unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(nullptr, RI->getDwarfRegNum(Reg, true), Offset)); + BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)).addCFIIndex(CFIIndex); + } + if (hasFP(MF)) { + if (STI.isRegisterReservedByUser(FPReg)) { + MF.getFunction().getContext().diagnose(DiagnosticInfoUnsupported{MF.getFunction(), "Frame pointer required, but has been reserved."}); + } + adjustReg(MBB, MBBI, DL, FPReg, SPReg, RealStackSize - RVFI->getVarArgsSaveSize(), MachineInstr::FrameSetup); + unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfa(nullptr, RI->getDwarfRegNum(FPReg, true), RVFI->getVarArgsSaveSize())); + BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)).addCFIIndex(CFIIndex); + } + if (FirstSPAdjustAmount) { + uint64_t SecondSPAdjustAmount = MFI.getStackSize() - FirstSPAdjustAmount; + assert(SecondSPAdjustAmount > 0 && "SecondSPAdjustAmount should be greater than zero"); + adjustReg(MBB, MBBI, DL, SPReg, SPReg, -SecondSPAdjustAmount, MachineInstr::FrameSetup); + if (!hasFP(MF)) { + unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, MFI.getStackSize())); + BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)).addCFIIndex(CFIIndex); + } + } + if (hasFP(MF)) { + const RISCVRegisterInfo *RI = STI.getRegisterInfo(); + if (RI->needsStackRealignment(MF)) { + Align MaxAlignment = MFI.getMaxAlign(); + const RISCVInstrInfo *TII = STI.getInstrInfo(); + if (isInt<12>(-(int)MaxAlignment.value())) { + BuildMI(MBB, MBBI, DL, TII->get(RISCV::ANDI), SPReg).addReg(SPReg).addImm(-(int)MaxAlignment.value()); + } + else { + unsigned ShiftAmount = Log2(MaxAlignment); + Register VR = MF.getRegInfo().createVirtualRegister(&RISCV::GPRRegClass); + BuildMI(MBB, MBBI, DL, TII->get(RISCV::SRLI), VR).addReg(SPReg).addImm(ShiftAmount); + BuildMI(MBB, MBBI, DL, TII->get(RISCV::SLLI), SPReg).addReg(VR).addImm(ShiftAmount); + } + if (hasBP(MF)) { + BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), BPReg).addReg(SPReg).addImm(0); + } + } + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/FrameLowering/getFrameIndexReference.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/FrameLowering/getFrameIndexReference.cpp new file mode 100644 index 0000000000000000000000000000000000000000..08c62666cb52c52383f1b96f43d706c6bca38eb7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/FrameLowering/getFrameIndexReference.cpp @@ -0,0 +1,67 @@ +StackOffset RISCVFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg) const { + const MachineFrameInfo &MFI = MF.getFrameInfo(); + const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo(); + const auto *RVFI = MF.getInfo(); + SmallVector NonLibcallCSI; + for (auto &CS : MFI.getCalleeSavedInfo()) { + if (CS.getFrameIdx() >= 0) { + NonLibcallCSI.push_back(CS); + } + } + const auto &CSI = NonLibcallCSI; + int MinCSFI = 0; + int MaxCSFI = -1; + int Offset = MFI.getObjectOffset(FI) - getOffsetOfLocalArea() + MFI.getOffsetAdjustment(); + uint64_t FirstSPAdjustAmount = 0; + const auto *RVFI = MF.getInfo(); + const MachineFrameInfo &MFI = MF.getFrameInfo(); + const std::vector &CSI = MFI.getCalleeSavedInfo(); + uint64_t StackSize = MFI.getStackSize(); + if (RVFI->getLibCallStackSize()) { + FirstSPAdjustAmount = 0; + } + if (!isInt<12>(StackSize) && (CSI.size() > 0)) { + FirstSPAdjustAmount = 2048 - getStackAlign().value(); + } + if (CSI.size()) { + MinCSFI = CSI[0].getFrameIdx(); + MaxCSFI = CSI[CSI.size() - 1].getFrameIdx(); + } + if (FI >= MinCSFI && FI <= MaxCSFI) { + FrameReg = RISCV::X2; + if (FirstSPAdjustAmount) { + Offset += FirstSPAdjustAmount; + } + else { + Offset += MFI.getStackSize(); + } + } + else if (RI->needsStackRealignment(MF) && !MFI.isFixedObjectIndex(FI)) { + if (hasBP(MF)) { + FrameReg = RISCVABI::getBPReg(); + } + else { + FrameReg = RISCV::X2; + } + Offset += MFI.getStackSize(); + if (FI < 0) { + Offset += RVFI->getLibCallStackSize(); + } + } + else { + FrameReg = RI->getFrameRegister(MF); + if (hasFP(MF)) { + Offset += RVFI->getVarArgsSaveSize(); + if (FI >= 0) { + Offset -= RVFI->getLibCallStackSize(); + } + } + else { + Offset += MFI.getStackSize(); + if (FI < 0) { + Offset += RVFI->getLibCallStackSize(); + } + } + } + return StackOffset::getFixed(Offset); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/FrameLowering/hasBP.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/FrameLowering/hasBP.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5574f49a88f76684df7f258066e46968b3ca683e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/FrameLowering/hasBP.cpp @@ -0,0 +1,5 @@ +bool RISCVFrameLowering::hasBP(const MachineFunction &MF) const { + const MachineFrameInfo &MFI = MF.getFrameInfo(); + const TargetRegisterInfo *TRI = STI.getRegisterInfo(); + return MFI.hasVarSizedObjects() && TRI->needsStackRealignment(MF); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/FrameLowering/hasFP.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/FrameLowering/hasFP.cpp new file mode 100644 index 0000000000000000000000000000000000000000..52beb3a078d6d11924752420b10316994936a37a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/FrameLowering/hasFP.cpp @@ -0,0 +1,5 @@ +bool RISCVFrameLowering::hasFP(const MachineFunction &MF) const { + const MachineFrameInfo &MFI = MF.getFrameInfo(); + const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); + return MF.getTarget().Options.DisableFramePointerElim(MF) || RegInfo->needsStackRealignment(MF) || MFI.hasVarSizedObjects() || MFI.isFrameAddressTaken(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/FrameLowering/hasReservedCallFrame.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/FrameLowering/hasReservedCallFrame.cpp new file mode 100644 index 0000000000000000000000000000000000000000..33c01431709078493a443b5c20651203bcfb781a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/FrameLowering/hasReservedCallFrame.cpp @@ -0,0 +1,3 @@ +bool RISCVFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const { + return !MF.getFrameInfo().hasVarSizedObjects(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/FrameLowering/processFunctionBeforeFrameFinalized.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/FrameLowering/processFunctionBeforeFrameFinalized.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4fd3e4fc864c8feda05e9898c4e705651542721e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/FrameLowering/processFunctionBeforeFrameFinalized.cpp @@ -0,0 +1,9 @@ +void RISCVFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS) const { + const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); + MachineFrameInfo &MFI = MF.getFrameInfo(); + const TargetRegisterClass *RC = &RISCV::GPRRegClass; + if (!isInt<11>(MFI.estimateStackSize(MF))) { + int RegScavFI = MFI.CreateStackObject(RegInfo->getSpillSize(*RC), RegInfo->getSpillAlign(*RC), false); + RS->addScavengingFrameIndex(RegScavFI); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/FrameLowering/restoreCalleeSavedRegisters.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/FrameLowering/restoreCalleeSavedRegisters.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5aad41ddb0dbd296fef38f4f37bb326d9717d4fd --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/FrameLowering/restoreCalleeSavedRegisters.cpp @@ -0,0 +1,70 @@ +bool RISCVFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, MutableArrayRef CSI, const TargetRegisterInfo *TRI) const { + if (CSI.empty()) { + return true; + } + MachineFunction *MF = MBB.getParent(); + const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo(); + DebugLoc DL; + if (MI != MBB.end() && !MI->isDebugInstr()) { + DL = MI->getDebugLoc(); + } + SmallVector NonLibcallCSI2; + for (auto &CS : CSI) { + if (CS.getFrameIdx() >= 0) { + NonLibcallCSI2.push_back(CS); + } + } + const auto &NonLibcallCSI = NonLibcallCSI2; + for (auto &CS : reverse(NonLibcallCSI)) { + Register Reg = CS.getReg(); + const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); + TII.loadRegFromStackSlot(MBB, MI, Reg, CS.getFrameIdx(), RC, TRI); + assert(MI != MBB.begin() && "loadRegFromStackSlot didn't insert any code!"); + } + const char *RestoreLibCall; + static const char *const RestoreLibCalls[] = {"__riscv_restore_0", "__riscv_restore_1", "__riscv_restore_2", "__riscv_restore_3", "__riscv_restore_4", "__riscv_restore_5", "__riscv_restore_6", "__riscv_restore_7", "__riscv_restore_8", "__riscv_restore_9", "__riscv_restore_10", "__riscv_restore_11", "__riscv_restore_12"}; + int LibCallID; + const auto *RVFI = MF.getInfo(); + if (CSI.empty() || !RVFI->useSaveRestoreLibCalls(MF)) { + LibCallID = -1; + } + Register MaxReg = RISCV::NoRegister; + for (auto &CS : CSI) { + if (CS.getFrameIdx() < 0) { + MaxReg = std::max(MaxReg.id(), CS.getReg().id()); + } + } + if (MaxReg == RISCV::NoRegister) { + LibCallID = -1; + } + switch (MaxReg) { + default: + llvm_unreachable("Something has gone wrong!"); + case RISCV::X27: LibCallID = 12; + case RISCV::X26: LibCallID = 11; + case RISCV::X25: LibCallID = 10; + case RISCV::X24: LibCallID = 9; + case RISCV::X23: LibCallID = 8; + case RISCV::X22: LibCallID = 7; + case RISCV::X21: LibCallID = 6; + case RISCV::X20: LibCallID = 5; + case RISCV::X19: LibCallID = 4; + case RISCV::X18: LibCallID = 3; + case RISCV::X9: LibCallID = 2; + case RISCV::X8: LibCallID = 1; + case RISCV::X1: LibCallID = 0; + } + if (LibCallID == -1) { + RestoreLibCall = nullptr; + } + RestoreLibCall = RestoreLibCalls[LibCallID]; + const char *RestoreLibCall = getRestoreLibCallName(*MF, CSI); + if (RestoreLibCall) { + MachineBasicBlock::iterator NewMI = BuildMI(MBB, MI, DL, TII.get(RISCV::PseudoTAIL)).addExternalSymbol(RestoreLibCall, RISCVII::MO_CALL).setMIFlag(MachineInstr::FrameDestroy); + if (MI != MBB.end() && MI->getOpcode() == RISCV::PseudoRET) { + NewMI->copyImplicitOps(*MF, *MI); + MI->eraseFromParent(); + } + } + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/FrameLowering/spillCalleeSavedRegisters.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/FrameLowering/spillCalleeSavedRegisters.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7344391a22670e42b028c4323e619b6fe220c4cb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/FrameLowering/spillCalleeSavedRegisters.cpp @@ -0,0 +1,67 @@ +bool RISCVFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef CSI, const TargetRegisterInfo *TRI) const { + if (CSI.empty()) { + return true; + } + MachineFunction *MF = MBB.getParent(); + const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo(); + DebugLoc DL; + if (MI != MBB.end() && !MI->isDebugInstr()) { + DL = MI->getDebugLoc(); + } + const char *SpillLibCall; + static const char *const SpillLibCalls[] = {"__riscv_save_0", "__riscv_save_1", "__riscv_save_2", "__riscv_save_3", "__riscv_save_4", "__riscv_save_5", "__riscv_save_6", "__riscv_save_7", "__riscv_save_8", "__riscv_save_9", "__riscv_save_10", "__riscv_save_11", "__riscv_save_12"}; + int LibCallID; + const auto *RVFI = MF.getInfo(); + if (CSI.empty() || !RVFI->useSaveRestoreLibCalls(MF)) { + LibCallID = -1; + } + Register MaxReg = RISCV::NoRegister; + for (auto &CS : CSI) { + if (CS.getFrameIdx() < 0) { + MaxReg = std::max(MaxReg.id(), CS.getReg().id()); + } + } + if (MaxReg == RISCV::NoRegister) { + LibCallID = -1; + } + switch (MaxReg) { + default: + llvm_unreachable("Something has gone wrong!"); + case RISCV::X27: LibCallID = 12; + case RISCV::X26: LibCallID = 11; + case RISCV::X25: LibCallID = 10; + case RISCV::X24: LibCallID = 9; + case RISCV::X23: LibCallID = 8; + case RISCV::X22: LibCallID = 7; + case RISCV::X21: LibCallID = 6; + case RISCV::X20: LibCallID = 5; + case RISCV::X19: LibCallID = 4; + case RISCV::X18: LibCallID = 3; + case RISCV::X9: LibCallID = 2; + case RISCV::X8: LibCallID = 1; + case RISCV::X1: LibCallID = 0; + } + if (LibCallID == -1) { + SpillLibCall = nullptr; + } + SpillLibCall = SpillLibCalls[LibCallID]; + if (SpillLibCall) { + BuildMI(MBB, MI, DL, TII.get(RISCV::PseudoCALLReg), RISCV::X5).addExternalSymbol(SpillLibCall, RISCVII::MO_CALL).setMIFlag(MachineInstr::FrameSetup); + for (auto &CS : CSI) { + MBB.addLiveIn(CS.getReg()); + } + } + SmallVector NonLibcallCSI2; + for (auto &CS : CSI) { + if (CS.getFrameIdx() >= 0) { + NonLibcallCSI2.push_back(CS); + } + } + const auto &NonLibcallCSI = NonLibcallCSI2; + for (auto &CS : NonLibcallCSI) { + Register Reg = CS.getReg(); + const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); + TII.storeRegToStackSlot(MBB, MI, Reg, true, CS.getFrameIdx(), RC, TRI); + } + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelDAGToDAG/DAGToDAGISel.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelDAGToDAG/DAGToDAGISel.cpp new file mode 100644 index 0000000000000000000000000000000000000000..71b402e1f73281139075f655ca142ba3f6cd7f6c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelDAGToDAG/DAGToDAGISel.cpp @@ -0,0 +1,2 @@ +explicit RISCVDAGToDAGISel(RISCVTargetMachine &TargetMachine) : SelectionDAGISel(TargetMachine) { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelDAGToDAG/MatchSLLIUW.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelDAGToDAG/MatchSLLIUW.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9823b1da0db069cc49a64e482ac6c5d70e2b57fe --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelDAGToDAG/MatchSLLIUW.cpp @@ -0,0 +1,14 @@ +bool RISCVDAGToDAGISel::MatchSLLIUW(SDNode *N) const { + assert(N->getOpcode() == ISD::AND); + assert(N->getOperand(0).getOpcode() == ISD::SHL); + assert(isa(N->getOperand(1))); + assert(isa(N->getOperand(0).getOperand(1))); + if (!Subtarget->is64Bit()) { + return false; + } + SDValue Shl = N->getOperand(0); + uint64_t VC1 = N->getConstantOperandVal(1); + uint64_t VC2 = Shl.getConstantOperandVal(1); + assert(VC2 < 32 && "Unexpected immediate"); + return (VC1 >> VC2) == UINT64_C(0xFFFFFFFF); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelDAGToDAG/MatchSRLIUW.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelDAGToDAG/MatchSRLIUW.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4097aa333f59f157602a32e2c6261d1d073f1398 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelDAGToDAG/MatchSRLIUW.cpp @@ -0,0 +1,13 @@ +bool RISCVDAGToDAGISel::MatchSRLIUW(SDNode *N) const { + assert(N->getOpcode() == ISD::SRL); + assert(N->getOperand(0).getOpcode() == ISD::AND); + assert(isa(N->getOperand(1))); + assert(isa(N->getOperand(0).getOperand(1))); + if (!Subtarget->is64Bit()) { + return false; + } + SDValue And = N->getOperand(0); + uint64_t ShAmt = N->getConstantOperandVal(1); + uint64_t Mask = And.getConstantOperandVal(1); + return (Mask | maskTrailingOnes(ShAmt)) == 0xffffffff; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelDAGToDAG/PostprocessISelDAG.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelDAGToDAG/PostprocessISelDAG.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f6328e8bc19e4b307aa8cec3d75d5573277b5e72 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelDAGToDAG/PostprocessISelDAG.cpp @@ -0,0 +1,83 @@ +void RISCVDAGToDAGISel::PostprocessISelDAG() { + SelectionDAG::allnodes_iterator Position(CurDAG->getRoot().getNode()); + ++Position; + while (Position != CurDAG->allnodes_begin()) { + SDNode *N = &*--Position; + if (N->use_empty() || !N->isMachineOpcode()) + continue; + int OffsetOpIdx; + int BaseOpIdx; + switch (N->getMachineOpcode()) { + default: + continue; + case RISCV::LB: + case RISCV::LH: + case RISCV::LW: + case RISCV::LBU: + case RISCV::LHU: + case RISCV::LWU: + case RISCV::LD: + case RISCV::FLH: + case RISCV::FLW: + case RISCV::FLD: + BaseOpIdx = 0; + OffsetOpIdx = 1; + break; + case RISCV::SB: + case RISCV::SH: + case RISCV::SW: + case RISCV::SD: + case RISCV::FSH: + case RISCV::FSW: + case RISCV::FSD: + BaseOpIdx = 1; + OffsetOpIdx = 2; + break; + } + if (!isa(N->getOperand(OffsetOpIdx))) + continue; + SDValue Base = N->getOperand(BaseOpIdx); + if (!Base.isMachineOpcode() || Base.getMachineOpcode() != RISCV::ADDI) + continue; + SDValue ImmOperand = Base.getOperand(1); + uint64_t Offset2 = N->getConstantOperandVal(OffsetOpIdx); + if (auto Const = dyn_cast(ImmOperand)) { + int64_t Offset1 = Const->getSExtValue(); + int64_t CombinedOffset = Offset1 + Offset2; + if (!isInt<12>(CombinedOffset)) + continue; + ImmOperand = CurDAG->getTargetConstant(CombinedOffset, SDLoc(ImmOperand), ImmOperand.getValueType()); + } + else if (auto GA = dyn_cast(ImmOperand)) { + const DataLayout &DL = CurDAG->getDataLayout(); + Align Alignment = GA->getGlobal()->getPointerAlignment(DL); + if (Offset2 != 0 && Alignment <= Offset2) + continue; + int64_t Offset1 = GA->getOffset(); + int64_t CombinedOffset = Offset1 + Offset2; + ImmOperand = CurDAG->getTargetGlobalAddress(GA->getGlobal(), SDLoc(ImmOperand), ImmOperand.getValueType(), CombinedOffset, GA->getTargetFlags()); + } + else if (auto CP = dyn_cast(ImmOperand)) { + Align Alignment = CP->getAlign(); + if (Offset2 != 0 && Alignment <= Offset2) + continue; + int64_t Offset1 = CP->getOffset(); + int64_t CombinedOffset = Offset1 + Offset2; + ImmOperand = CurDAG->getTargetConstantPool(CP->getConstVal(), ImmOperand.getValueType(), CP->getAlign(), CombinedOffset, CP->getTargetFlags()); + } + else { + continue; + } + LLVM_DEBUG(dbgs() << "Folding add-immediate into mem-op:\nBase: "); + LLVM_DEBUG(Base->dump(CurDAG)); + LLVM_DEBUG(dbgs() << "\nN: "); + LLVM_DEBUG(N->dump(CurDAG)); + LLVM_DEBUG(dbgs() << "\n"); + if (BaseOpIdx == 0) + CurDAG->UpdateNodeOperands(N, Base.getOperand(0), ImmOperand, N->getOperand(2)); + else + CurDAG->UpdateNodeOperands(N, N->getOperand(0), Base.getOperand(0), ImmOperand, N->getOperand(3)); + if (Base.getNode()->use_empty()) + CurDAG->RemoveDeadNode(Base.getNode()); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelDAGToDAG/Select.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelDAGToDAG/Select.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7a7775f229ef2daf901972a36677bc646ce468e3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelDAGToDAG/Select.cpp @@ -0,0 +1,689 @@ +void RISCVDAGToDAGISel::Select(SDNode *Node) { + if (Node->isMachineOpcode()) { + LLVM_DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << "\n"); + Node->setNodeId(-1); + return; + } + unsigned Opcode = Node->getOpcode(); + MVT XLenVT = Subtarget->getXLenVT(); + SDLoc DL(Node); + EVT VT = Node->getValueType(0); + switch (Opcode) { + case ISD::ADD: { + if (auto *ConstOp = dyn_cast(Node->getOperand(1))) { + if (!(ConstOp->hasOneUse())) { + break; + } + int64_t Imm = ConstOp->getSExtValue(); + if (!(-4096 <= Imm && Imm <= -2049) && !(2048 <= Imm && Imm <= 4094)) { + break; + } + EVT VT = Node->getValueType(0); + const SDValue ImmOp0 = CurDAG->getTargetConstant(Imm - Imm / 2, DL, VT); + const SDValue ImmOp1 = CurDAG->getTargetConstant(Imm / 2, DL, VT); + auto *NodeAddi0 = CurDAG->getMachineNode(RISCV::ADDI, DL, VT, + Node->getOperand(0), ImmOp0); + auto *NodeAddi1 = CurDAG->getMachineNode(RISCV::ADDI, DL, VT, + SDValue(NodeAddi0, 0), ImmOp1); + ReplaceNode(Node, NodeAddi1); + return; + } + break; + } + case ISD::Constant: { + auto ConstNode = cast(Node); + if (VT == XLenVT && ConstNode->isNullValue()) { + SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL, RISCV::X0, XLenVT); + ReplaceNode(Node, New.getNode()); + return; + } + int64_t Imm = ConstNode->getSExtValue(); + if (XLenVT == MVT::i64) { + ReplaceNode(Node, selectImm(CurDAG, DL, Imm, XLenVT)); + return; + } + break; + } + case ISD::FrameIndex: { + SDValue Imm = CurDAG->getTargetConstant(0, DL, XLenVT); + int FI = cast(Node)->getIndex(); + SDValue TFI = CurDAG->getTargetFrameIndex(FI, VT); + ReplaceNode(Node, CurDAG->getMachineNode(RISCV::ADDI, DL, VT, TFI, Imm)); + return; + } + case ISD::INTRINSIC_W_CHAIN: { + unsigned IntNo = cast(Node->getOperand(1))->getZExtValue(); + switch (IntNo) { + default: + break; + case Intrinsic::riscv_vsetvli: { + if (!Subtarget->hasStdExtV()) { + break; + } + assert(Node->getNumOperands() == 5); + RISCVVSEW VSEW = static_cast(Node->getConstantOperandVal(3) & 0x7); + RISCVVLMUL VLMul = static_cast(Node->getConstantOperandVal(4) & 0x7); + unsigned VTypeI = RISCVVType::encodeVTYPE(VLMul, VSEW, true, false); + SDValue VTypeIOp = CurDAG->getTargetConstant(VTypeI, DL, XLenVT); + SDValue VLOperand = Node->getOperand(2); + if (auto *C = dyn_cast(VLOperand)) { + uint64_t AVL = C->getZExtValue(); + if (isUInt<5>(AVL)) { + SDValue VLImm = CurDAG->getTargetConstant(AVL, DL, XLenVT); + ReplaceNode(Node, CurDAG->getMachineNode(RISCV::PseudoVSETIVLI, DL, XLenVT, MVT::Other, VLImm, VTypeIOp, Node->getOperand(0))); + return; + } + } + ReplaceNode(Node, CurDAG->getMachineNode(RISCV::PseudoVSETVLI, DL, XLenVT, MVT::Other, VLOperand, VTypeIOp, Node->getOperand(0))); + return; + } + case Intrinsic::riscv_vsetvlimax: { + if (!Subtarget->hasStdExtV()) { + break; + } + assert(Node->getNumOperands() == 4); + RISCVVSEW VSEW = static_cast(Node->getConstantOperandVal(2) & 0x7); + RISCVVLMUL VLMul = static_cast(Node->getConstantOperandVal(3) & 0x7); + unsigned VTypeI = RISCVVType::encodeVTYPE(VLMul, VSEW, true, false); + SDValue VTypeIOp = CurDAG->getTargetConstant(VTypeI, DL, XLenVT); + SDValue VLOperand = CurDAG->getRegister(RISCV::X0, XLenVT); + ReplaceNode(Node, CurDAG->getMachineNode(RISCV::PseudoVSETVLI, DL, XLenVT, MVT::Other, VLOperand, VTypeIOp, Node->getOperand(0))); + return; + } + case Intrinsic::riscv_vlseg2: + case Intrinsic::riscv_vlseg3: + case Intrinsic::riscv_vlseg4: + case Intrinsic::riscv_vlseg5: + case Intrinsic::riscv_vlseg6: + case Intrinsic::riscv_vlseg7: + case Intrinsic::riscv_vlseg8: { + SDLoc DL(Node); + unsigned NF = Node->getNumValues() - 1; + EVT VT = Node->getValueType(0); + unsigned ScalarSize = VT.getScalarSizeInBits(); + MVT XLenVT = Subtarget->getXLenVT(); + RISCVVLMUL LMUL = getLMUL(VT); + SDValue SEW = CurDAG->getTargetConstant(ScalarSize, DL, XLenVT); + SmallVector Operands; + Operands.push_back(Node->getOperand(2)); + if (IsStrided) { + Operands.push_back(Node->getOperand(3)); + Operands.push_back(Node->getOperand(4)); + } + else { + Operands.push_back(Node->getOperand(3)); + } + Operands.push_back(SEW); + Operands.push_back(Node->getOperand(0)); + const RISCVZvlssegTable::RISCVZvlsseg *P = RISCVZvlssegTable::getPseudo(IntNo, ScalarSize, static_cast(LMUL), static_cast(RISCVVLMUL::LMUL_1)); + SDNode *Load = CurDAG->getMachineNode(P->Pseudo, DL, MVT::Untyped, MVT::Other, Operands); + SDValue SuperReg = SDValue(Load, 0); + for (unsigned I = 0; I < NF; ++I) + ReplaceUses(SDValue(Node, I), CurDAG->getTargetExtractSubreg(getSubregIndexByEVT(VT, I), DL, VT, SuperReg)); + ReplaceUses(SDValue(Node, NF), SDValue(Load, 1)); + CurDAG->RemoveDeadNode(Node); + return; + } + case Intrinsic::riscv_vlseg2_mask: + case Intrinsic::riscv_vlseg3_mask: + case Intrinsic::riscv_vlseg4_mask: + case Intrinsic::riscv_vlseg5_mask: + case Intrinsic::riscv_vlseg6_mask: + case Intrinsic::riscv_vlseg7_mask: + case Intrinsic::riscv_vlseg8_mask: { + SDLoc DL(Node); + unsigned NF = Node->getNumValues() - 1; + EVT VT = Node->getValueType(0); + unsigned ScalarSize = VT.getScalarSizeInBits(); + MVT XLenVT = Subtarget->getXLenVT(); + RISCVVLMUL LMUL = getLMUL(VT); + SDValue SEW = CurDAG->getTargetConstant(ScalarSize, DL, XLenVT); + SmallVector Regs(Node->op_begin() + 2, Node->op_begin() + 2 + NF); + SDValue MaskedOff = createTuple(*CurDAG, Regs, NF, LMUL); + SmallVector Operands; + Operands.push_back(MaskedOff); + Operands.push_back(Node->getOperand(NF + 2)); + if (IsStrided) { + Operands.push_back(Node->getOperand(NF + 3)); + Operands.push_back(Node->getOperand(NF + 4)); + Operands.push_back(Node->getOperand(NF + 5)); + } else { + Operands.push_back(Node->getOperand(NF + 3)); + Operands.push_back(Node->getOperand(NF + 4)); + } + Operands.push_back(SEW); + Operands.push_back(Node->getOperand(0)); + const RISCVZvlssegTable::RISCVZvlsseg *P = RISCVZvlssegTable::getPseudo(IntNo, ScalarSize, static_cast(LMUL), static_cast(RISCVVLMUL::LMUL_1)); + SDNode *Load = CurDAG->getMachineNode(P->Pseudo, DL, MVT::Untyped, MVT::Other, Operands); + SDValue SuperReg = SDValue(Load, 0); + for (unsigned I = 0; I < NF; ++I) + ReplaceUses(SDValue(Node, I), CurDAG->getTargetExtractSubreg(getSubregIndexByEVT(VT, I), DL, VT, SuperReg)); + ReplaceUses(SDValue(Node, NF), SDValue(Load, 1)); + CurDAG->RemoveDeadNode(Node); + return; + } + case Intrinsic::riscv_vlsseg2: + case Intrinsic::riscv_vlsseg3: + case Intrinsic::riscv_vlsseg4: + case Intrinsic::riscv_vlsseg5: + case Intrinsic::riscv_vlsseg6: + case Intrinsic::riscv_vlsseg7: + case Intrinsic::riscv_vlsseg8: { + SDLoc DL(Node); + unsigned NF = Node->getNumValues() - 1; + EVT VT = Node->getValueType(0); + unsigned ScalarSize = VT.getScalarSizeInBits(); + MVT XLenVT = Subtarget->getXLenVT(); + RISCVVLMUL LMUL = getLMUL(VT); + SDValue SEW = CurDAG->getTargetConstant(ScalarSize, DL, XLenVT); + SmallVector Operands; + Operands.push_back(Node->getOperand(2)); + if (IsStrided) { + Operands.push_back(Node->getOperand(3)); + Operands.push_back(Node->getOperand(4)); + } + else { + Operands.push_back(Node->getOperand(3)); + } + Operands.push_back(SEW); + Operands.push_back(Node->getOperand(0)); + const RISCVZvlssegTable::RISCVZvlsseg *P = RISCVZvlssegTable::getPseudo(IntNo, ScalarSize, static_cast(LMUL), static_cast(RISCVVLMUL::LMUL_1)); + SDNode *Load = CurDAG->getMachineNode(P->Pseudo, DL, MVT::Untyped, MVT::Other, Operands); + SDValue SuperReg = SDValue(Load, 0); + for (unsigned I = 0; I < NF; ++I) + ReplaceUses(SDValue(Node, I), CurDAG->getTargetExtractSubreg(getSubregIndexByEVT(VT, I), DL, VT, SuperReg)); + ReplaceUses(SDValue(Node, NF), SDValue(Load, 1)); + CurDAG->RemoveDeadNode(Node); + return; + } + case Intrinsic::riscv_vlsseg2_mask: + case Intrinsic::riscv_vlsseg3_mask: + case Intrinsic::riscv_vlsseg4_mask: + case Intrinsic::riscv_vlsseg5_mask: + case Intrinsic::riscv_vlsseg6_mask: + case Intrinsic::riscv_vlsseg7_mask: + case Intrinsic::riscv_vlsseg8_mask: { + SDLoc DL(Node); + unsigned NF = Node->getNumValues() - 1; + EVT VT = Node->getValueType(0); + unsigned ScalarSize = VT.getScalarSizeInBits(); + MVT XLenVT = Subtarget->getXLenVT(); + RISCVVLMUL LMUL = getLMUL(VT); + SDValue SEW = CurDAG->getTargetConstant(ScalarSize, DL, XLenVT); + SmallVector Regs(Node->op_begin() + 2, Node->op_begin() + 2 + NF); + SDValue MaskedOff = createTuple(*CurDAG, Regs, NF, LMUL); + SmallVector Operands; + Operands.push_back(MaskedOff); + Operands.push_back(Node->getOperand(NF + 2)); + if (IsStrided) { + Operands.push_back(Node->getOperand(NF + 3)); + Operands.push_back(Node->getOperand(NF + 4)); + Operands.push_back(Node->getOperand(NF + 5)); + } + else { + Operands.push_back(Node->getOperand(NF + 3)); + Operands.push_back(Node->getOperand(NF + 4)); + } + Operands.push_back(SEW); + Operands.push_back(Node->getOperand(0)); + const RISCVZvlssegTable::RISCVZvlsseg *P = RISCVZvlssegTable::getPseudo(IntNo, ScalarSize, static_cast(LMUL), static_cast(RISCVVLMUL::LMUL_1)); + SDNode *Load = CurDAG->getMachineNode(P->Pseudo, DL, MVT::Untyped, MVT::Other, Operands); + SDValue SuperReg = SDValue(Load, 0); + for (unsigned I = 0; I < NF; ++I) + ReplaceUses(SDValue(Node, I), CurDAG->getTargetExtractSubreg(getSubregIndexByEVT(VT, I), DL, VT, SuperReg)); + ReplaceUses(SDValue(Node, NF), SDValue(Load, 1)); + CurDAG->RemoveDeadNode(Node); + return; + } + case Intrinsic::riscv_vloxseg2: + case Intrinsic::riscv_vloxseg3: + case Intrinsic::riscv_vloxseg4: + case Intrinsic::riscv_vloxseg5: + case Intrinsic::riscv_vloxseg6: + case Intrinsic::riscv_vloxseg7: + case Intrinsic::riscv_vloxseg8: + case Intrinsic::riscv_vluxseg2: + case Intrinsic::riscv_vluxseg3: + case Intrinsic::riscv_vluxseg4: + case Intrinsic::riscv_vluxseg5: + case Intrinsic::riscv_vluxseg6: + case Intrinsic::riscv_vluxseg7: + case Intrinsic::riscv_vluxseg8: { + SDLoc DL(Node); + unsigned NF = Node->getNumValues() - 1; + EVT VT = Node->getValueType(0); + unsigned ScalarSize = VT.getScalarSizeInBits(); + MVT XLenVT = Subtarget->getXLenVT(); + RISCVVLMUL LMUL = getLMUL(VT); + SDValue SEW = CurDAG->getTargetConstant(ScalarSize, DL, XLenVT); + SDValue Operands[] = { + Node->getOperand(2), + Node->getOperand(3), + Node->getOperand(4), + SEW, Node->getOperand(0) + }; + EVT IndexVT = Node->getOperand(3)->getValueType(0); + RISCVVLMUL IndexLMUL = getLMUL(IndexVT); + unsigned IndexScalarSize = IndexVT.getScalarSizeInBits(); + const RISCVZvlssegTable::RISCVZvlsseg *P = RISCVZvlssegTable::getPseudo(IntNo, IndexScalarSize, static_cast(LMUL), static_cast(IndexLMUL)); + SDNode *Load = CurDAG->getMachineNode(P->Pseudo, DL, MVT::Untyped, MVT::Other, Operands); + SDValue SuperReg = SDValue(Load, 0); + for (unsigned I = 0; I < NF; ++I) + ReplaceUses(SDValue(Node, I), CurDAG->getTargetExtractSubreg(getSubregIndexByEVT(VT, I), DL,VT, SuperReg)); + ReplaceUses(SDValue(Node, NF), SDValue(Load, 1)); + CurDAG->RemoveDeadNode(Node); + return; + } + case Intrinsic::riscv_vloxseg2_mask: + case Intrinsic::riscv_vloxseg3_mask: + case Intrinsic::riscv_vloxseg4_mask: + case Intrinsic::riscv_vloxseg5_mask: + case Intrinsic::riscv_vloxseg6_mask: + case Intrinsic::riscv_vloxseg7_mask: + case Intrinsic::riscv_vloxseg8_mask: + case Intrinsic::riscv_vluxseg2_mask: + case Intrinsic::riscv_vluxseg3_mask: + case Intrinsic::riscv_vluxseg4_mask: + case Intrinsic::riscv_vluxseg5_mask: + case Intrinsic::riscv_vluxseg6_mask: + case Intrinsic::riscv_vluxseg7_mask: + case Intrinsic::riscv_vluxseg8_mask: { + SDLoc DL(Node); + unsigned NF = Node->getNumValues() - 1; + EVT VT = Node->getValueType(0); + unsigned ScalarSize = VT.getScalarSizeInBits(); + MVT XLenVT = Subtarget->getXLenVT(); + RISCVVLMUL LMUL = getLMUL(VT); + SDValue SEW = CurDAG->getTargetConstant(ScalarSize, DL, XLenVT); + SmallVector Regs(Node->op_begin() + 2, Node->op_begin() + 2 + NF); + SDValue MaskedOff = createTuple(*CurDAG, Regs, NF, LMUL); + SDValue Operands[] = { + MaskedOff, + Node->getOperand(NF + 2), + Node->getOperand(NF + 3), + Node->getOperand(NF + 4), + Node->getOperand(NF + 5), + SEW, + Node->getOperand(0) + }; + EVT IndexVT = Node->getOperand(NF + 3)->getValueType(0); + RISCVVLMUL IndexLMUL = getLMUL(IndexVT); + unsigned IndexScalarSize = IndexVT.getScalarSizeInBits(); + const RISCVZvlssegTable::RISCVZvlsseg *P = RISCVZvlssegTable::getPseudo(IntNo, IndexScalarSize, static_cast(LMUL), static_cast(IndexLMUL)); + SDNode *Load = CurDAG->getMachineNode(P->Pseudo, DL, MVT::Untyped, MVT::Other, Operands); + SDValue SuperReg = SDValue(Load, 0); + for (unsigned I = 0; I < NF; ++I) + ReplaceUses(SDValue(Node, I), CurDAG->getTargetExtractSubreg(getSubregIndexByEVT(VT, I), DL, VT, SuperReg)); + ReplaceUses(SDValue(Node, NF), SDValue(Load, 1)); + CurDAG->RemoveDeadNode(Node); + return; + } + } + break; + } + case ISD::INTRINSIC_VOID: { + unsigned IntNo = cast(Node->getOperand(1))->getZExtValue(); + switch (IntNo) { + case Intrinsic::riscv_vsseg2: + case Intrinsic::riscv_vsseg3: + case Intrinsic::riscv_vsseg4: + case Intrinsic::riscv_vsseg5: + case Intrinsic::riscv_vsseg6: + case Intrinsic::riscv_vsseg7: + case Intrinsic::riscv_vsseg8: { + SDLoc DL(Node); + unsigned NF = Node->getNumOperands() - 4; + if (IsStrided) + NF--; + EVT VT = Node->getOperand(2)->getValueType(0); + unsigned ScalarSize = VT.getScalarSizeInBits(); + MVT XLenVT = Subtarget->getXLenVT(); + RISCVVLMUL LMUL = getLMUL(VT); + SDValue SEW = CurDAG->getTargetConstant(ScalarSize, DL, XLenVT); + SmallVector Regs(Node->op_begin() + 2, Node->op_begin() + 2 + NF); + SDValue StoreVal = createTuple(*CurDAG, Regs, NF, LMUL); + SmallVector Operands; + Operands.push_back(StoreVal); + Operands.push_back(Node->getOperand(2 + NF)); + if (IsStrided) { + Operands.push_back(Node->getOperand(3 + NF)); + Operands.push_back(Node->getOperand(4 + NF)); + } + else { + Operands.push_back(Node->getOperand(3 + NF)); + } + Operands.push_back(SEW); + Operands.push_back(Node->getOperand(0)); + const RISCVZvlssegTable::RISCVZvlsseg *P = RISCVZvlssegTable::getPseudo(IntNo, ScalarSize, static_cast(LMUL), static_cast(RISCVVLMUL::LMUL_1)); + SDNode *Store = CurDAG->getMachineNode(P->Pseudo, DL, Node->getValueType(0), Operands); + ReplaceNode(Node, Store); + return; + } + case Intrinsic::riscv_vsseg2_mask: + case Intrinsic::riscv_vsseg3_mask: + case Intrinsic::riscv_vsseg4_mask: + case Intrinsic::riscv_vsseg5_mask: + case Intrinsic::riscv_vsseg6_mask: + case Intrinsic::riscv_vsseg7_mask: + case Intrinsic::riscv_vsseg8_mask: { + SDLoc DL(Node); + unsigned NF = Node->getNumOperands() - 5; + if (IsStrided) + NF--; + EVT VT = Node->getOperand(2)->getValueType(0); + unsigned ScalarSize = VT.getScalarSizeInBits(); + MVT XLenVT = Subtarget->getXLenVT(); + RISCVVLMUL LMUL = getLMUL(VT); + SDValue SEW = CurDAG->getTargetConstant(ScalarSize, DL, XLenVT); + SmallVector Regs(Node->op_begin() + 2, Node->op_begin() + 2 + NF); + SDValue StoreVal = createTuple(*CurDAG, Regs, NF, LMUL); + SmallVector Operands; + Operands.push_back(StoreVal); + Operands.push_back(Node->getOperand(2 + NF)); + if (IsStrided) { + Operands.push_back(Node->getOperand(3 + NF)); + Operands.push_back(Node->getOperand(4 + NF)); + Operands.push_back(Node->getOperand(5 + NF)); + } + else { + Operands.push_back(Node->getOperand(3 + NF)); + Operands.push_back(Node->getOperand(4 + NF)); + } + Operands.push_back(SEW); + Operands.push_back(Node->getOperand(0)); + const RISCVZvlssegTable::RISCVZvlsseg *P = RISCVZvlssegTable::getPseudo(IntNo, ScalarSize, static_cast(LMUL), static_cast(RISCVVLMUL::LMUL_1)); + SDNode *Store = CurDAG->getMachineNode(P->Pseudo, DL, Node->getValueType(0), Operands); + ReplaceNode(Node, Store); + return; + } + case Intrinsic::riscv_vssseg2: + case Intrinsic::riscv_vssseg3: + case Intrinsic::riscv_vssseg4: + case Intrinsic::riscv_vssseg5: + case Intrinsic::riscv_vssseg6: + case Intrinsic::riscv_vssseg7: + case Intrinsic::riscv_vssseg8: { + SDLoc DL(Node); + unsigned NF = Node->getNumOperands() - 4; + if (IsStrided) + NF--; + EVT VT = Node->getOperand(2)->getValueType(0); + unsigned ScalarSize = VT.getScalarSizeInBits(); + MVT XLenVT = Subtarget->getXLenVT(); + RISCVVLMUL LMUL = getLMUL(VT); + SDValue SEW = CurDAG->getTargetConstant(ScalarSize, DL, XLenVT); + SmallVector Regs(Node->op_begin() + 2, Node->op_begin() + 2 + NF); + SDValue StoreVal = createTuple(*CurDAG, Regs, NF, LMUL); + SmallVector Operands; + Operands.push_back(StoreVal); + Operands.push_back(Node->getOperand(2 + NF)); + if (IsStrided) { + Operands.push_back(Node->getOperand(3 + NF)); + Operands.push_back(Node->getOperand(4 + NF)); + } + else { + Operands.push_back(Node->getOperand(3 + NF)); + } + Operands.push_back(SEW); + Operands.push_back(Node->getOperand(0)); + const RISCVZvlssegTable::RISCVZvlsseg *P = RISCVZvlssegTable::getPseudo(IntNo, ScalarSize, static_cast(LMUL), static_cast(RISCVVLMUL::LMUL_1)); + SDNode *Store = CurDAG->getMachineNode(P->Pseudo, DL, Node->getValueType(0), Operands); + ReplaceNode(Node, Store); + return; + } + case Intrinsic::riscv_vssseg2_mask: + case Intrinsic::riscv_vssseg3_mask: + case Intrinsic::riscv_vssseg4_mask: + case Intrinsic::riscv_vssseg5_mask: + case Intrinsic::riscv_vssseg6_mask: + case Intrinsic::riscv_vssseg7_mask: + case Intrinsic::riscv_vssseg8_mask: { + SDLoc DL(Node); + unsigned NF = Node->getNumOperands() - 5; + if (IsStrided) + NF--; + EVT VT = Node->getOperand(2)->getValueType(0); + unsigned ScalarSize = VT.getScalarSizeInBits(); + MVT XLenVT = Subtarget->getXLenVT(); + RISCVVLMUL LMUL = getLMUL(VT); + SDValue SEW = CurDAG->getTargetConstant(ScalarSize, DL, XLenVT); + SmallVector Regs(Node->op_begin() + 2, Node->op_begin() + 2 + NF); + SDValue StoreVal = createTuple(*CurDAG, Regs, NF, LMUL); + SmallVector Operands; + Operands.push_back(StoreVal); + Operands.push_back(Node->getOperand(2 + NF)); + if (IsStrided) { + Operands.push_back(Node->getOperand(3 + NF)); + Operands.push_back(Node->getOperand(4 + NF)); + Operands.push_back(Node->getOperand(5 + NF)); + } + else { + Operands.push_back(Node->getOperand(3 + NF)); + Operands.push_back(Node->getOperand(4 + NF)); + } + Operands.push_back(SEW); + Operands.push_back(Node->getOperand(0)); + const RISCVZvlssegTable::RISCVZvlsseg *P = RISCVZvlssegTable::getPseudo(IntNo, ScalarSize, static_cast(LMUL), static_cast(RISCVVLMUL::LMUL_1)); + SDNode *Store = CurDAG->getMachineNode(P->Pseudo, DL, Node->getValueType(0), Operands); + ReplaceNode(Node, Store); + return; + } + case Intrinsic::riscv_vsoxseg2: + case Intrinsic::riscv_vsoxseg3: + case Intrinsic::riscv_vsoxseg4: + case Intrinsic::riscv_vsoxseg5: + case Intrinsic::riscv_vsoxseg6: + case Intrinsic::riscv_vsoxseg7: + case Intrinsic::riscv_vsoxseg8: + case Intrinsic::riscv_vsuxseg2: + case Intrinsic::riscv_vsuxseg3: + case Intrinsic::riscv_vsuxseg4: + case Intrinsic::riscv_vsuxseg5: + case Intrinsic::riscv_vsuxseg6: + case Intrinsic::riscv_vsuxseg7: + case Intrinsic::riscv_vsuxseg8: { + SDLoc DL(Node); + unsigned NF = Node->getNumOperands() - 5; + EVT VT = Node->getOperand(2)->getValueType(0); + unsigned ScalarSize = VT.getScalarSizeInBits(); + MVT XLenVT = Subtarget->getXLenVT(); + RISCVVLMUL LMUL = getLMUL(VT); + SDValue SEW = CurDAG->getTargetConstant(ScalarSize, DL, XLenVT); + SmallVector Regs(Node->op_begin() + 2, Node->op_begin() + 2 + NF); + SDValue StoreVal = createTuple(*CurDAG, Regs, NF, LMUL); + SDValue Operands[] = { + StoreVal, + Node->getOperand(2 + NF), + Node->getOperand(3 + NF), + Node->getOperand(4 + NF), + SEW, + Node->getOperand(0) + }; + EVT IndexVT = Node->getOperand(3 + NF)->getValueType(0); + RISCVVLMUL IndexLMUL = getLMUL(IndexVT); + unsigned IndexScalarSize = IndexVT.getScalarSizeInBits(); + const RISCVZvlssegTable::RISCVZvlsseg *P = RISCVZvlssegTable::getPseudo(IntNo, IndexScalarSize, static_cast(LMUL), static_cast(IndexLMUL)); + SDNode *Store = CurDAG->getMachineNode(P->Pseudo, DL, Node->getValueType(0), Operands); + ReplaceNode(Node, Store); + return; + } + case Intrinsic::riscv_vsoxseg2_mask: + case Intrinsic::riscv_vsoxseg3_mask: + case Intrinsic::riscv_vsoxseg4_mask: + case Intrinsic::riscv_vsoxseg5_mask: + case Intrinsic::riscv_vsoxseg6_mask: + case Intrinsic::riscv_vsoxseg7_mask: + case Intrinsic::riscv_vsoxseg8_mask: + case Intrinsic::riscv_vsuxseg2_mask: + case Intrinsic::riscv_vsuxseg3_mask: + case Intrinsic::riscv_vsuxseg4_mask: + case Intrinsic::riscv_vsuxseg5_mask: + case Intrinsic::riscv_vsuxseg6_mask: + case Intrinsic::riscv_vsuxseg7_mask: + case Intrinsic::riscv_vsuxseg8_mask: { + SDLoc DL(Node); + unsigned NF = Node->getNumOperands() - 6; + EVT VT = Node->getOperand(2)->getValueType(0); + unsigned ScalarSize = VT.getScalarSizeInBits(); + MVT XLenVT = Subtarget->getXLenVT(); + RISCVVLMUL LMUL = getLMUL(VT); + SDValue SEW = CurDAG->getTargetConstant(ScalarSize, DL, XLenVT); + SmallVector Regs(Node->op_begin() + 2, Node->op_begin() + 2 + NF); + SDValue StoreVal = createTuple(*CurDAG, Regs, NF, LMUL); + SDValue Operands[] = { + StoreVal, + Node->getOperand(2 + NF), + Node->getOperand(3 + NF), + Node->getOperand(4 + NF), + Node->getOperand(5 + NF), + SEW, + Node->getOperand(0) + }; + EVT IndexVT = Node->getOperand(3 + NF)->getValueType(0); + RISCVVLMUL IndexLMUL = getLMUL(IndexVT); + unsigned IndexScalarSize = IndexVT.getScalarSizeInBits(); + const RISCVZvlssegTable::RISCVZvlsseg *P = RISCVZvlssegTable::getPseudo(IntNo, IndexScalarSize, static_cast(LMUL), static_cast(IndexLMUL)); + SDNode *Store = CurDAG->getMachineNode(P->Pseudo, DL, Node->getValueType(0), Operands); + ReplaceNode(Node, Store); + return; + } + } + break; + } + case RISCVISD::VLSEGFF: { + SDLoc DL(Node); + unsigned IntNo = cast(Node->getOperand(1))->getZExtValue(); + unsigned NF = Node->getNumValues() - 2; + EVT VT = Node->getValueType(0); + unsigned ScalarSize = VT.getScalarSizeInBits(); + MVT XLenVT = Subtarget->getXLenVT(); + RISCVVLMUL LMUL = getLMUL(VT); + SDValue SEW = CurDAG->getTargetConstant(ScalarSize, DL, XLenVT); + SmallVector Operands; + Operands.push_back(Node->getOperand(2)); + Operands.push_back(Node->getOperand(3)); + Operands.push_back(SEW); + Operands.push_back(Node->getOperand(0)); + const RISCVZvlssegTable::RISCVZvlsseg *P = RISCVZvlssegTable::getPseudo(IntNo, ScalarSize, static_cast(LMUL), static_cast(RISCVVLMUL::LMUL_1)); + SDNode *Load = CurDAG->getMachineNode(P->Pseudo, DL, MVT::Untyped, MVT::Other, MVT::Glue, Operands); + SDValue SuperReg = SDValue(Load, 0); + for (unsigned I = 0; I < NF; ++I) + ReplaceUses(SDValue(Node, I), CurDAG->getTargetExtractSubreg(getSubregIndexByEVT(VT, I), DL, VT, SuperReg)); + ReplaceUses(SDValue(Node, NF), SDValue(Load, 1)); + ReplaceUses(SDValue(Node, NF + 1), SDValue(Load, 2)); + CurDAG->RemoveDeadNode(Node); + return; + } + case RISCVISD::VLSEGFF_MASK: { + SDLoc DL(Node); + unsigned IntNo = cast(Node->getOperand(1))->getZExtValue(); + unsigned NF = Node->getNumValues() - 2; + EVT VT = Node->getValueType(0); + unsigned ScalarSize = VT.getScalarSizeInBits(); + MVT XLenVT = Subtarget->getXLenVT(); + RISCVVLMUL LMUL = getLMUL(VT); + SDValue SEW = CurDAG->getTargetConstant(ScalarSize, DL, XLenVT); + SmallVector Regs(Node->op_begin() + 2, Node->op_begin() + 2 + NF); + SDValue MaskedOff = createTuple(*CurDAG, Regs, NF, LMUL); + SmallVector Operands; + Operands.push_back(MaskedOff); + Operands.push_back(Node->getOperand(NF + 2)); + Operands.push_back(Node->getOperand(NF + 3)); + Operands.push_back(Node->getOperand(NF + 4)); + Operands.push_back(SEW); + Operands.push_back(Node->getOperand(0)); + const RISCVZvlssegTable::RISCVZvlsseg *P = RISCVZvlssegTable::getPseudo(IntNo, ScalarSize, static_cast(LMUL), static_cast(RISCVVLMUL::LMUL_1)); + SDNode *Load = CurDAG->getMachineNode(P->Pseudo, DL, MVT::Untyped, MVT::Other, MVT::Glue, Operands); + SDValue SuperReg = SDValue(Load, 0); + for (unsigned I = 0; I < NF; ++I) + ReplaceUses(SDValue(Node, I), CurDAG->getTargetExtractSubreg(getSubregIndexByEVT(VT, I), DL, VT, SuperReg)); + ReplaceUses(SDValue(Node, NF), SDValue(Load, 1)); // Chain. + ReplaceUses(SDValue(Node, NF + 1), SDValue(Load, 2)); // Glue. + CurDAG->RemoveDeadNode(Node); + return; + } + case ISD::LOAD: { + LoadSDNode *Load = cast(Node); + if (Load->getAddressingMode() == ISD::UNINDEXED) + break; + SDValue Chain = Node->getOperand(0); + SDValue Base = Node->getOperand(1); + SDValue Offset = Node->getOperand(2); + bool simm12 = false; + bool signExtend = Load->getExtensionType() == ISD::SEXTLOAD; + if(auto ConstantOffset = dyn_cast(Offset)) { + int ConstantVal = ConstantOffset->getSExtValue(); + simm12 = isInt<12>(ConstantVal); + if (simm12) + Offset = CurDAG->getTargetConstant(ConstantVal, DL, Offset.getValueType()); + } + unsigned Opcode = 0; + switch (Load->getMemoryVT().getSimpleVT().SimpleTy) { + case MVT::i8: + if ( simm12 && signExtend) Opcode = RISCV::P_LB_ri_PostIncrement; + else if ( simm12 && !signExtend) Opcode = RISCV::P_LBU_ri_PostIncrement; + else if (!simm12 && signExtend) Opcode = RISCV::P_LB_rr_PostIncrement; + else Opcode = RISCV::P_LBU_rr_PostIncrement; + break; + case MVT::i16: + if ( simm12 && signExtend) Opcode = RISCV::P_LH_ri_PostIncrement; + else if ( simm12 && !signExtend) Opcode = RISCV::P_LHU_ri_PostIncrement; + else if (!simm12 && signExtend) Opcode = RISCV::P_LH_rr_PostIncrement; + else Opcode = RISCV::P_LHU_rr_PostIncrement; + break; + case MVT::i32: + if (simm12) Opcode = RISCV::P_LW_ri_PostIncrement; + else Opcode = RISCV::P_LW_rr_PostIncrement; + default: break; + } + if (!Opcode) break; + ReplaceNode(Node, CurDAG->getMachineNode(Opcode, DL, MVT::i32, MVT::i32, Chain.getSimpleValueType(), Base, Offset, Chain)); + return; + } + case ISD::VECTOR_SHUFFLE: { + ShuffleVectorSDNode *Shuffle = cast(Node); + SDValue Vec0 = Shuffle->getOperand(0); + SDValue Vec1 = Shuffle->getOperand(1); + unsigned Opcode; + int imm; + if (Vec1->getOpcode() == ISD::UNDEF) { + if (VT == MVT::v2i16) { + Opcode = RISCV::PV_SHUFFLE_SCI_H; + imm = (Shuffle->getMaskElt(1) & 1) << 1; + imm |= Shuffle->getMaskElt(0) & 1; + } + else { + switch (Shuffle->getMaskElt(3)) { + default: + case 0: Opcode = RISCV::PV_SHUFFLEI0_SCI_B; break; + case 1: Opcode = RISCV::PV_SHUFFLEI1_SCI_B; break; + case 2: Opcode = RISCV::PV_SHUFFLEI2_SCI_B; break; + case 3: Opcode = RISCV::PV_SHUFFLEI3_SCI_B; break; + } + imm = (Shuffle->getMaskElt(2) & 3) << 4; + imm |= (Shuffle->getMaskElt(1) & 3) << 2; + imm |= Shuffle->getMaskElt(0) & 3; + } + SDValue Imm = CurDAG->getTargetConstant(imm, SDLoc(Node), MVT::i32); + ReplaceNode(Node, CurDAG->getMachineNode(Opcode, DL, VT, Vec0, Imm)); + return; + } + if (VT == MVT::v2i16) { + Opcode = RISCV::PV_SHUFFLE2_H; + imm = (Shuffle->getMaskElt(1) & 1) << 16; + imm |= Shuffle->getMaskElt(0) & 1; + } + else { + Opcode = RISCV::PV_SHUFFLE2_B; + imm = (Shuffle->getMaskElt(3) & 3) << 24; + imm |= (Shuffle->getMaskElt(2) & 3) << 16; + imm |= (Shuffle->getMaskElt(1) & 3) << 8; + imm |= Shuffle->getMaskElt(0) & 3; + } + SDValue Imm = SDValue(selectImm(CurDAG, DL, imm, MVT::i32), 0); + ReplaceNode(Node, CurDAG->getMachineNode(Opcode, DL, VT, Vec0, Vec1, Imm)); + return; + } + } + SelectCode(Node); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelDAGToDAG/SelectAddrFI.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelDAGToDAG/SelectAddrFI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9379dd240442854fd152c1a8fed8a2b885473a0e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelDAGToDAG/SelectAddrFI.cpp @@ -0,0 +1,7 @@ +bool RISCVDAGToDAGISel::SelectAddrFI(SDValue Addr, SDValue &Base) { + if (auto FIN = dyn_cast(Addr)) { + Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), Subtarget->getXLenVT()); + return true; + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelDAGToDAG/SelectInlineAsmMemoryOperand.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelDAGToDAG/SelectInlineAsmMemoryOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..165beb5cae4ca44de1b3b5882179fb69421c957b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelDAGToDAG/SelectInlineAsmMemoryOperand.cpp @@ -0,0 +1,13 @@ +bool RISCVDAGToDAGISel::SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, std::vector &OutOps) { + switch (ConstraintID) { + case InlineAsm::Constraint_m: + OutOps.push_back(Op); + return false; + case InlineAsm::Constraint_A: + OutOps.push_back(Op); + return false; + default: + break; + } + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelDAGToDAG/createISelDag.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelDAGToDAG/createISelDag.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c6275786f621741ef641c1c9653dfc8c1c5fb094 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelDAGToDAG/createISelDag.cpp @@ -0,0 +1,3 @@ +FunctionPass *llvm::createRISCVISelDag(RISCVTargetMachine &TM) { + return new RISCVDAGToDAGISel(TM); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelDAGToDAG/getPassName.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelDAGToDAG/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b96cb682522bb4d42ce3557a54892030e1538f48 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelDAGToDAG/getPassName.cpp @@ -0,0 +1,3 @@ +StringRef getPassName() const override { + return "RISCV DAG->DAG Pattern Instruction Selection"; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelDAGToDAG/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelDAGToDAG/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5777ae33b7d6e056d8705bec6b95c6237351d2ce --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelDAGToDAG/runOnMachineFunction.cpp @@ -0,0 +1,4 @@ +bool runOnMachineFunction(MachineFunction &MF) override { + Subtarget = &MF.getSubtarget(); + return SelectionDAGISel::runOnMachineFunction(MF); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelDAGToDAG/selectVLOp.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelDAGToDAG/selectVLOp.cpp new file mode 100644 index 0000000000000000000000000000000000000000..02f2a0b029e45085011587a91e97581811fcfce9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelDAGToDAG/selectVLOp.cpp @@ -0,0 +1,22 @@ +bool RISCVDAGToDAGISel::selectVLOp(SDValue N, SDValue &VL) { + auto *C = dyn_cast(N); + if (C && C->isNullValue()) { + RISCVMatInt::InstSeq Seq; + RISCVMatInt::generateInstSeq(Imm, XLenVT == MVT::i64, Seq); + SDNode *Result = nullptr; + SDValue SrcReg = CurDAG->getRegister(RISCV::X0, XLenVT); + for (RISCVMatInt::Inst &Inst : Seq) { + SDValue SDImm = CurDAG->getTargetConstant(Inst.Imm, DL, XLenVT); + if (Inst.Opc == RISCV::LUI) + Result = CurDAG->getMachineNode(RISCV::LUI, DL, XLenVT, SDImm); + else + Result = CurDAG->getMachineNode(Inst.Opc, DL, XLenVT, SrcReg, SDImm); + SrcReg = SDValue(Result, 0); + } + VL = SDValue(selectImm(CurDAG, SDLoc(N), 0, Subtarget->getXLenVT()), 0); + } + else { + VL = N; + } + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelDAGToDAG/selectVSplat.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelDAGToDAG/selectVSplat.cpp new file mode 100644 index 0000000000000000000000000000000000000000..500365156eb27b9ec53e3c54d7bd31402e02bb80 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelDAGToDAG/selectVSplat.cpp @@ -0,0 +1,7 @@ +bool RISCVDAGToDAGISel::selectVSplat(SDValue N, SDValue &SplatVal) { + if (N.getOpcode() != ISD::SPLAT_VECTOR && N.getOpcode() != RISCVISD::SPLAT_VECTOR_I64) { + return false; + } + SplatVal = N.getOperand(0); + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelDAGToDAG/selectVSplatSimm5.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelDAGToDAG/selectVSplatSimm5.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3f19416c4249c3fa0ba66fedcff7a3e7eb734fdb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelDAGToDAG/selectVSplatSimm5.cpp @@ -0,0 +1,17 @@ +bool RISCVDAGToDAGISel::selectVSplatSimm5(SDValue N, SDValue &SplatVal) { + if ((N.getOpcode() != ISD::SPLAT_VECTOR && N.getOpcode() != RISCVISD::SPLAT_VECTOR_I64) || !isa(N.getOperand(0))) { + return false; + } + int64_t SplatImm = cast(N.getOperand(0))->getSExtValue(); + auto XLenVT = Subtarget->getXLenVT(); + assert(XLenVT == N.getOperand(0).getSimpleValueType() && "Unexpected splat operand type"); + auto EltVT = N.getValueType().getVectorElementType(); + if (EltVT.bitsLT(XLenVT)) { + SplatImm = SignExtend64(SplatImm, EltVT.getSizeInBits()); + } + if (!isInt<5>(SplatImm)) { + return false; + } + SplatVal = CurDAG->getTargetConstant(SplatImm, SDLoc(N), XLenVT); + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelDAGToDAG/selectVSplatUimm5.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelDAGToDAG/selectVSplatUimm5.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bdff0c6f5dc1586897ad9c7787e6a82ee582e996 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelDAGToDAG/selectVSplatUimm5.cpp @@ -0,0 +1,11 @@ +bool RISCVDAGToDAGISel::selectVSplatUimm5(SDValue N, SDValue &SplatVal) { + if ((N.getOpcode() != ISD::SPLAT_VECTOR && N.getOpcode() != RISCVISD::SPLAT_VECTOR_I64) || !isa(N.getOperand(0))) { + return false; + } + int64_t SplatImm = cast(N.getOperand(0))->getSExtValue(); + if (!isUInt<5>(SplatImm)) { + return false; + } + SplatVal = CurDAG->getTargetConstant(SplatImm, SDLoc(N), Subtarget->getXLenVT()); + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/CanLowerReturn.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/CanLowerReturn.cpp new file mode 100644 index 0000000000000000000000000000000000000000..313f69ae69dddca02aef0b43936b47304afc7ae2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/CanLowerReturn.cpp @@ -0,0 +1,171 @@ +bool RISCVTargetLowering::CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg, const SmallVectorImpl &Outs, LLVMContext &Context) const { + SmallVector RVLocs; + CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context); + Optional FirstMaskArgument; + if (Subtarget.hasStdExtV()) { + for (const auto &ArgIdx : enumerate(Args)) { + MVT ArgVT = ArgIdx.value().VT; + if (ArgVT.isScalableVector() && ArgVT.getVectorElementType().SimpleTy == MVT::i1) + return ArgIdx.index(); + } + return None; + } + for (unsigned i = 0, e = Outs.size(); i != e; ++i) { + MVT VT = Outs[i].VT; + ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; + RISCVABI::ABI ABI = MF.getSubtarget().getTargetABI(); + unsigned XLen = DL.getLargestLegalIntTypeSizeInBits(); + assert(XLen == 32 || XLen == 64); + MVT XLenVT = XLen == 32 ? MVT::i32 : MVT::i64; + if (IsRet && ValNo > 1) + return true; + bool UseGPRForF16_F32 = true; + bool UseGPRForF64 = true; + switch (ABI) { + default: + llvm_unreachable("Unexpected ABI"); + case RISCVABI::ABI_ILP32: + case RISCVABI::ABI_LP64: + break; + case RISCVABI::ABI_ILP32F: + case RISCVABI::ABI_LP64F: + UseGPRForF16_F32 = !IsFixed; + break; + case RISCVABI::ABI_ILP32D: + case RISCVABI::ABI_LP64D: + UseGPRForF16_F32 = !IsFixed; + UseGPRForF64 = !IsFixed; + break; + } + if (State.getFirstUnallocated(ArgFPR32s) == array_lengthof(ArgFPR32s)) { + UseGPRForF16_F32 = true; + UseGPRForF64 = true; + } + if (UseGPRForF16_F32 && (ValVT == MVT::f16 || ValVT == MVT::f32)) { + LocVT = XLenVT; + LocInfo = CCValAssign::BCvt; + } + else if (UseGPRForF64 && XLen == 64 && ValVT == MVT::f64) { + LocVT = MVT::i64; + LocInfo = CCValAssign::BCvt; + } + unsigned TwoXLenInBytes = (2 * XLen) / 8; + if (!IsFixed && ArgFlags.getNonZeroOrigAlign() == TwoXLenInBytes && DL.getTypeAllocSize(OrigTy) == TwoXLenInBytes) { + unsigned RegIdx = State.getFirstUnallocated(ArgGPRs); + if (RegIdx != array_lengthof(ArgGPRs) && RegIdx % 2 == 1) + State.AllocateReg(ArgGPRs); + } + SmallVectorImpl &PendingLocs = State.getPendingLocs(); + SmallVectorImpl &PendingArgFlags = State.getPendingArgFlags(); + assert(PendingLocs.size() == PendingArgFlags.size() && "PendingLocs and PendingArgFlags out of sync"); + if (UseGPRForF64 && XLen == 32 && ValVT == MVT::f64) { + assert(!ArgFlags.isSplit() && PendingLocs.empty() && "Can't lower f64 if it is split"); + Register Reg = State.AllocateReg(ArgGPRs); + LocVT = MVT::i32; + if (!Reg) { + unsigned StackOffset = State.AllocateStack(8, Align(8)); + State.addLoc(CCValAssign::getMem(ValNo, ValVT, StackOffset, LocVT, LocInfo)); + return false; + } + if (!State.AllocateReg(ArgGPRs)) + State.AllocateStack(4, Align(4)); + State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); + return false; + } + if (ArgFlags.isSplit() || !PendingLocs.empty()) { + LocVT = XLenVT; + LocInfo = CCValAssign::Indirect; + PendingLocs.push_back(CCValAssign::getPending(ValNo, ValVT, LocVT, LocInfo)); + PendingArgFlags.push_back(ArgFlags); + if (!ArgFlags.isSplitEnd()) { + return false; + } + } + if (ArgFlags.isSplitEnd() && PendingLocs.size() <= 2) { + assert(PendingLocs.size() == 2 && "Unexpected PendingLocs.size()"); + CCValAssign VA = PendingLocs[0]; + ISD::ArgFlagsTy AF = PendingArgFlags[0]; + PendingLocs.clear(); + PendingArgFlags.clear(); + unsigned XLenInBytes = XLen / 8; + if (Register Reg = State.AllocateReg(ArgGPRs)) { + State.addLoc(CCValAssign::getReg(VA1.getValNo(), VA1.getValVT(), Reg, VA1.getLocVT(), CCValAssign::Full)); + } else { + Align StackAlign = std::max(Align(XLenInBytes), ArgFlags1.getNonZeroOrigAlign()); + State.addLoc(CCValAssign::getMem(VA1.getValNo(), VA1.getValVT(), State.AllocateStack(XLenInBytes, StackAlign), VA1.getLocVT(), CCValAssign::Full)); + State.addLoc(CCValAssign::getMem(ValNo2, ValVT2, State.AllocateStack(XLenInBytes, Align(XLenInBytes)), LocVT2, CCValAssign::Full)); + return false; + } + if (Register Reg = State.AllocateReg(ArgGPRs)) { + State.addLoc(CCValAssign::getReg(ValNo2, ValVT2, Reg, LocVT2, CCValAssign::Full)); + } + else { + State.addLoc(CCValAssign::getMem(ValNo2, ValVT2, State.AllocateStack(XLenInBytes, Align(XLenInBytes)), LocVT2, CCValAssign::Full)); + } + return false; + } + Register Reg; + if (ValVT == MVT::f16 && !UseGPRForF16_F32) + Reg = State.AllocateReg(ArgFPR16s); + else if (ValVT == MVT::f32 && !UseGPRForF16_F32) + Reg = State.AllocateReg(ArgFPR32s); + else if (ValVT == MVT::f64 && !UseGPRForF64) + Reg = State.AllocateReg(ArgFPR64s); + else if (ValVT.isScalableVector()) { + const TargetRegisterClass *RC = TLI.getRegClassFor(ValVT); + if (RC == &RISCV::VRRegClass) { + if (FirstMaskArgument.hasValue() && ValNo == FirstMaskArgument.getValue()) { + Reg = State.AllocateReg(RISCV::V0); + } + else { + Reg = State.AllocateReg(ArgVRs); + } + } + else if (RC == &RISCV::VRM2RegClass) { + Reg = State.AllocateReg(ArgVRM2s); + } + else if (RC == &RISCV::VRM4RegClass) { + Reg = State.AllocateReg(ArgVRM4s); + } + else if (RC == &RISCV::VRM8RegClass) { + Reg = State.AllocateReg(ArgVRM8s); + } + else { + llvm_unreachable("Unhandled class register for ValueType"); + } + if (!Reg) { + LocInfo = CCValAssign::Indirect; + Reg = State.AllocateReg(ArgGPRs); + LocVT = XLenVT; + } + } else + Reg = State.AllocateReg(ArgGPRs); + unsigned StackOffset = Reg ? 0 : State.AllocateStack(XLen / 8, Align(XLen / 8)); + if (!PendingLocs.empty()) { + assert(ArgFlags.isSplitEnd() && "Expected ArgFlags.isSplitEnd()"); + assert(PendingLocs.size() > 2 && "Unexpected PendingLocs.size()"); + for (auto &It : PendingLocs) { + if (Reg) + It.convertToReg(Reg); + else + It.convertToMem(StackOffset); + State.addLoc(It); + } + PendingLocs.clear(); + PendingArgFlags.clear(); + return false; + } + assert((!UseGPRForF16_F32 || !UseGPRForF64 || LocVT == XLenVT || (TLI.getSubtarget().hasStdExtV() && ValVT.isScalableVector())) && "Expected an XLenVT or scalable vector types at this stage"); + if (Reg) { + State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); + return false; + } + if (ValVT.isFloatingPoint()) { + LocVT = ValVT; + LocInfo = CCValAssign::Full; + } + State.addLoc(CCValAssign::getMem(ValNo, ValVT, StackOffset, LocVT, LocInfo)); + return false; + } + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/ComputeNumSignBitsForTargetNode.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/ComputeNumSignBitsForTargetNode.cpp new file mode 100644 index 0000000000000000000000000000000000000000..63f9dcd4bfa99711bec59e8db8683e30194ac2a1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/ComputeNumSignBitsForTargetNode.cpp @@ -0,0 +1,45 @@ +unsigned RISCVTargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const { + if (Op.getOpcode() == RISCVISD::SLLW) { + return Op.getScalarValueSizeInBits(); + } + if (Op.getOpcode() == RISCVISD::SRAW) { + return Op.getScalarValueSizeInBits(); + } + if (Op.getOpcode() == RISCVISD::SRLW) { + return 33; + } + if (Op.getOpcode() == RISCVISD::DIVW) { + return 33; + } + if (Op.getOpcode() == RISCVISD::DIVUW) { + return 33; + } + if (Op.getOpcode() == RISCVISD::REMUW) { + return 33; + } + if (Op.getOpcode() == RISCVISD::ROLW) { + return 33; + } + if (Op.getOpcode() == RISCVISD::RORW) { + return 33; + } + if (Op.getOpcode() == RISCVISD::GREVIW) { + return 33; + } + if (Op.getOpcode() == RISCVISD::GORCIW) { + return 33; + } + if (Op.getOpcode() == RISCVISD::FSLW) { + return 33; + } + if (Op.getOpcode() == RISCVISD::FSRW) { + return 33; + } + if (Op.getOpcode() == RISCVISD::VMV_X_S) { + if (Op.getOperand(0).getScalarValueSizeInBits() > Subtarget.getXLen()) { + return 1; + } + return Subtarget.getXLen() - Op.getOperand(0).getScalarValueSizeInBits() + 1; + } + return 1; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/EmitInstrWithCustomInserter.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/EmitInstrWithCustomInserter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..78f8c6ed2abbddd3aa2e311bcd887beaf74bc0ea --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/EmitInstrWithCustomInserter.cpp @@ -0,0 +1,165 @@ +MachineBasicBlock *RISCVTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const { + uint64_t TSFlags = MI.getDesc().TSFlags; + if (TSFlags & RISCVII::HasSEWOpMask) { + unsigned NumOperands = MI.getNumExplicitOperands(); + int VLIndex = (TSFlags & RISCVII::HasVLOpMask) ? NumOperands - 2 : -1; + unsigned SEWIndex = NumOperands - 1; + bool WritesElement0 = TSFlags & RISCVII::WritesElement0Mask; + RISCVVLMUL VLMul = static_cast((TSFlags & RISCVII::VLMulMask) >> RISCVII::VLMulShift); + MachineFunction &MF = *BB->getParent(); + DebugLoc DL = MI.getDebugLoc(); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); + unsigned SEW = MI.getOperand(SEWIndex).getImm(); + assert(RISCVVType::isValidSEW(SEW) && "Unexpected SEW"); + RISCVVSEW ElementWidth = static_cast(Log2_32(SEW / 8)); + MachineRegisterInfo &MRI = MF.getRegInfo(); + MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, TII.get(RISCV::PseudoVSETVLI)); + if (VLIndex >= 0) { + Register DestReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); + MIB.addReg(DestReg, RegState::Define | RegState::Dead).addReg(MI.getOperand(VLIndex).getReg()); + } + else + MIB.addReg(RISCV::X0, RegState::Define | RegState::Dead).addReg(RISCV::X0, RegState::Kill); + bool TailAgnostic = true; + unsigned UseOpIdx; + if (MI.isRegTiedToUseOperand(0, &UseOpIdx) && !WritesElement0) { + TailAgnostic = false; + const MachineOperand &UseMO = MI.getOperand(UseOpIdx); + MachineInstr *UseMI = MRI.getVRegDef(UseMO.getReg()); + if (UseMI && UseMI->isImplicitDef()) + TailAgnostic = true; + } + unsigned VLMULBits = static_cast(VLMUL); + unsigned VSEWBits = static_cast(VSEW); + unsigned VTypeI = (VSEWBits << 3) | (VLMULBits & 0x7); + if (TailAgnostic) + VTypeI |= 0x40; + if (MaskAgnostic) + VTypeI |= 0x80; + MIB.addImm(RISCVVType::encodeVTYPE(VLMul, ElementWidth, TailAgnostic, false)); + MI.getOperand(SEWIndex).setImm(-1); + if (VLIndex >= 0) { + MI.getOperand(VLIndex).setReg(RISCV::NoRegister); + MI.getOperand(VLIndex).setIsKill(false); + } + } + switch (MI.getOpcode()) { + default: + llvm_unreachable("Unexpected instr type to insert"); + case RISCV::ReadCycleWide: + assert(!Subtarget.is64Bit() && "ReadCycleWrite is only to be used on riscv32"); + assert(MI.getOpcode() == RISCV::ReadCycleWide && "Unexpected instruction"); + MachineFunction &MF = *BB->getParent(); + const BasicBlock *LLVM_BB = BB->getBasicBlock(); + MachineFunction::iterator It = ++BB->getIterator(); + MachineBasicBlock *LoopMBB = MF.CreateMachineBasicBlock(LLVM_BB); + MF.insert(It, LoopMBB); + MachineBasicBlock *DoneMBB = MF.CreateMachineBasicBlock(LLVM_BB); + MF.insert(It, DoneMBB); + DoneMBB->splice(DoneMBB->begin(), BB, std::next(MachineBasicBlock::iterator(MI)), BB->end()); + DoneMBB->transferSuccessorsAndUpdatePHIs(BB); + BB->addSuccessor(LoopMBB); + MachineRegisterInfo &RegInfo = MF.getRegInfo(); + Register ReadAgainReg = RegInfo.createVirtualRegister(&RISCV::GPRRegClass); + Register LoReg = MI.getOperand(0).getReg(); + Register HiReg = MI.getOperand(1).getReg(); + DebugLoc DL = MI.getDebugLoc(); + const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo(); + BuildMI(LoopMBB, DL, TII->get(RISCV::CSRRS), HiReg).addImm(RISCVSysReg::lookupSysRegByName("CYCLEH")->Encoding).addReg(RISCV::X0); + BuildMI(LoopMBB, DL, TII->get(RISCV::CSRRS), LoReg).addImm(RISCVSysReg::lookupSysRegByName("CYCLE")->Encoding).addReg(RISCV::X0); + BuildMI(LoopMBB, DL, TII->get(RISCV::CSRRS), ReadAgainReg).addImm(RISCVSysReg::lookupSysRegByName("CYCLEH")->Encoding).addReg(RISCV::X0); + BuildMI(LoopMBB, DL, TII->get(RISCV::BNE)).addReg(HiReg).addReg(ReadAgainReg).addMBB(LoopMBB); + LoopMBB->addSuccessor(LoopMBB); + LoopMBB->addSuccessor(DoneMBB); + MI.eraseFromParent(); + return DoneMBB; + case RISCV::Select_GPR_Using_CC_GPR: + case RISCV::Select_FPR16_Using_CC_GPR: + case RISCV::Select_FPR32_Using_CC_GPR: + case RISCV::Select_FPR64_Using_CC_GPR: + and(2).getReg() != RHS || SequenceMBBI->getOperand(3).getImm() != CC || SelectDests.count(SequenceMBBI->getOperand(4).getReg()) || SelectDests.count(SequenceMBBI->getOperand(5).getReg())) + break; + LastSelectPseudo = &*SequenceMBBI; + SequenceMBBI->collectDebugValues(SelectDebugValues); + SelectDests.insert(SequenceMBBI->getOperand(0).getReg()); + else { + if (SequenceMBBI->hasUnmodeledSideEffects() || SequenceMBBI->mayLoadOrStore()) + break; + if (llvm::any_of(SequenceMBBI->operands(), [&](MachineOperand &MO) { + return MO.isReg() && MO.isUse() && SelectDests.count(MO.getReg()); + })) + break; + } + const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo(); + const BasicBlock *LLVM_BB = BB->getBasicBlock(); + DebugLoc DL = MI.getDebugLoc(); + MachineFunction::iterator I = ++BB->getIterator(); + MachineBasicBlock *HeadMBB = BB; + MachineFunction *F = BB->getParent(); + MachineBasicBlock *TailMBB = F->CreateMachineBasicBlock(LLVM_BB); + MachineBasicBlock *IfFalseMBB = F->CreateMachineBasicBlock(LLVM_BB); + F->insert(I, IfFalseMBB); + F->insert(I, TailMBB); + for (MachineInstr *DebugInstr : SelectDebugValues) { + TailMBB->push_back(DebugInstr->removeFromParent()); + } + TailMBB->splice(TailMBB->end(), HeadMBB, std::next(LastSelectPseudo->getIterator()), HeadMBB->end()); + TailMBB->transferSuccessorsAndUpdatePHIs(HeadMBB); + HeadMBB->addSuccessor(IfFalseMBB); + HeadMBB->addSuccessor(TailMBB); + unsigned Opcode = getBranchOpcodeForIntCondCode(CC); + BuildMI(HeadMBB, DL, TII.get(Opcode)).addReg(LHS).addReg(RHS).addMBB(TailMBB); + IfFalseMBB->addSuccessor(TailMBB); + auto SelectMBBI = MI.getIterator(); + auto SelectEnd = std::next(LastSelectPseudo->getIterator()); + auto InsertionPoint = TailMBB->begin(); + while (SelectMBBI != SelectEnd) { + auto Next = std::next(SelectMBBI); + if (isSelectPseudo(*SelectMBBI)) { + BuildMI(*TailMBB, InsertionPoint, SelectMBBI->getDebugLoc(), TII.get(RISCV::PHI), SelectMBBI->getOperand(0).getReg()).addReg(SelectMBBI->getOperand(4).getReg()).addMBB(HeadMBB).addReg(SelectMBBI->getOperand(5).getReg()).addMBB(IfFalseMBB); + SelectMBBI->eraseFromParent(); + } + SelectMBBI = Next; + } + F->getProperties().reset(MachineFunctionProperties::Property::NoPHIs); + return TailMBB; + case RISCV::BuildPairF64Pseudo: + assert(MI.getOpcode() == RISCV::BuildPairF64Pseudo && "Unexpected instruction"); + MachineFunction &MF = *BB->getParent(); + DebugLoc DL = MI.getDebugLoc(); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); + const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo(); + Register DstReg = MI.getOperand(0).getReg(); + Register LoReg = MI.getOperand(1).getReg(); + Register HiReg = MI.getOperand(2).getReg(); + const TargetRegisterClass *DstRC = &RISCV::FPR64RegClass; + int FI = MF.getInfo()->getMoveF64FrameIndex(MF); + MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(MF, FI); + MachineMemOperand *MMOLo = MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, Align(8)); + MachineMemOperand *MMOHi = MF.getMachineMemOperand(MPI.getWithOffset(4), MachineMemOperand::MOStore, 4, Align(8)); + BuildMI(*BB, MI, DL, TII.get(RISCV::SW)).addReg(LoReg, getKillRegState(MI.getOperand(1).isKill())).addFrameIndex(FI).addImm(0).addMemOperand(MMOLo); + BuildMI(*BB, MI, DL, TII.get(RISCV::SW)).addReg(HiReg, getKillRegState(MI.getOperand(2).isKill())).addFrameIndex(FI).addImm(4).addMemOperand(MMOHi); + TII.loadRegFromStackSlot(*BB, MI, DstReg, FI, DstRC, RI); + MI.eraseFromParent(); + return BB; + case RISCV::SplitF64Pseudo: + assert(MI.getOpcode() == RISCV::SplitF64Pseudo && "Unexpected instruction");= + MachineFunction &MF = *BB->getParent(); + DebugLoc DL = MI.getDebugLoc(); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); + const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo(); + Register LoReg = MI.getOperand(0).getReg(); + Register HiReg = MI.getOperand(1).getReg(); + Register SrcReg = MI.getOperand(2).getReg(); + const TargetRegisterClass *SrcRC = &RISCV::FPR64RegClass; + int FI = MF.getInfo()->getMoveF64FrameIndex(MF); + TII.storeRegToStackSlot(*BB, MI, SrcReg, MI.getOperand(2).isKill(), FI, SrcRC, RI); + MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(MF, FI); + MachineMemOperand *MMOLo = MF.getMachineMemOperand(MPI, MachineMemOperand::MOLoad, 4, Align(8)); + MachineMemOperand *MMOHi = MF.getMachineMemOperand( PI.getWithOffset(4), MachineMemOperand::MOLoad, 4, Align(8)); + BuildMI(*BB, MI, DL, TII.get(RISCV::LW), LoReg).addFrameIndex(FI).addImm(0).addMemOperand(MMOLo); + BuildMI(*BB, MI, DL, TII.get(RISCV::LW), HiReg).addFrameIndex(FI).addImm(4).addMemOperand(MMOHi); + MI.eraseFromParent(); + return BB; + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/LowerAsmOperandForConstraint.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/LowerAsmOperandForConstraint.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3120cdc9e0247fc2f5bbeaa81b831c974641b9fe --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/LowerAsmOperandForConstraint.cpp @@ -0,0 +1,34 @@ +void RISCVTargetLowering::LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector &Ops, SelectionDAG &DAG) const { + SDLoc DL(Op); + MVT XLenVT = Subtarget.getXLenVT(); + if (Constraint.length() == 1) { + if (Constraint[0] == 'I') { + if (auto *C = dyn_cast(Op)) { + uint64_t Val = C->getSExtValue(); + if (isInt<12>(Val)) { + Ops.push_back(DAG.getTargetConstant(Val, DL, XLenVT)); + } + } + return ; + } + if (Constraint[0] == 'J') { + if (auto *C = dyn_cast(Op)) { + uint64_t Val = C->getSExtValue(); + if (Val == 0) { + Ops.push_back(DAG.getTargetConstant(0, DL, XLenVT)); + } + } + return ; + } + if (Constraint[0] == 'K') { + if (auto *C = dyn_cast(Op)) { + uint64_t Val = C->getSExtValue(); + if (isUInt<5>(Val)) { + Ops.push_back(DAG.getTargetConstant(Val, DL, XLenVT)); + } + } + return ; + } + } + TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/LowerBlockAddress.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/LowerBlockAddress.cpp new file mode 100644 index 0000000000000000000000000000000000000000..97d4a427e101d5f49d5240064ece9c020a72ab75 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/LowerBlockAddress.cpp @@ -0,0 +1,4 @@ +SDValue RISCVTargetLowering::lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const { + BlockAddressSDNode *N = cast(Op); + return getAddr(N, DAG); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/LowerCall.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/LowerCall.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7af74735e1d7dc1c5b685944c4694f244897d869 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/LowerCall.cpp @@ -0,0 +1,197 @@ +SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI, SmallVectorImpl &InVals) const { + SelectionDAG &DAG = CLI.DAG; + SDLoc &DL = CLI.DL; + SmallVectorImpl &Outs = CLI.Outs; + SmallVectorImpl &OutVals = CLI.OutVals; + SmallVectorImpl &Ins = CLI.Ins; + SDValue Chain = CLI.Chain; + SDValue Callee = CLI.Callee; + bool &IsTailCall = CLI.IsTailCall; + CallingConv::ID CallConv = CLI.CallConv; + bool IsVarArg = CLI.IsVarArg; + EVT PtrVT = getPointerTy(DAG.getDataLayout()); + MVT XLenVT = Subtarget.getXLenVT(); + MachineFunction &MF = DAG.getMachineFunction(); + SmallVector ArgLocs; + CCState ArgCCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext()); + if (CallConv == CallingConv::Fast) + ArgCCInfo.AnalyzeCallOperands(Outs, CC_RISCV_FastCC); + else if (CallConv == CallingConv::GHC) + ArgCCInfo.AnalyzeCallOperands(Outs, CC_RISCV_GHC); + else + analyzeOutputArgs(MF, ArgCCInfo, Outs, false, &CLI); + if (IsTailCall) + IsTailCall = isEligibleForTailCallOptimization(ArgCCInfo, CLI, MF, ArgLocs); + if (IsTailCall) + ++NumTailCalls; + else if (CLI.CB && CLI.CB->isMustTailCall()) + report_fatal_error("failed to perform tail call elimination on a call site marked musttail"); + unsigned NumBytes = ArgCCInfo.getNextStackOffset(); + SmallVector ByValArgs; + for (unsigned i = 0, e = Outs.size(); i != e; ++i) { + ISD::ArgFlagsTy Flags = Outs[i].Flags; + if (!Flags.isByVal()) + continue; + SDValue Arg = OutVals[i]; + unsigned Size = Flags.getByValSize(); + Align Alignment = Flags.getNonZeroByValAlign(); + int FI = MF.getFrameInfo().CreateStackObject(Size, Alignment, false); + SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); + SDValue SizeNode = DAG.getConstant(Size, DL, XLenVT); + Chain = DAG.getMemcpy(Chain, DL, FIPtr, Arg, SizeNode, Alignment, false, false, IsTailCall, MachinePointerInfo(), MachinePointerInfo()); + ByValArgs.push_back(FIPtr); + } + if (!IsTailCall) + Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, CLI.DL); + SmallVector, 8> RegsToPass; + SmallVector MemOpChains; + SDValue StackPtr; + for (unsigned i = 0, j = 0, e = ArgLocs.size(); i != e; ++i) { + CCValAssign &VA = ArgLocs[i]; + SDValue ArgValue = OutVals[i]; + ISD::ArgFlagsTy Flags = Outs[i].Flags; + bool IsF64OnRV32DSoftABI = VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64; + if (IsF64OnRV32DSoftABI && VA.isRegLoc()) { + SDValue SplitF64 = DAG.getNode(RISCVISD::SplitF64, DL, DAG.getVTList(MVT::i32, MVT::i32), ArgValue); + SDValue Lo = SplitF64.getValue(0); + SDValue Hi = SplitF64.getValue(1); + Register RegLo = VA.getLocReg(); + RegsToPass.push_back(std::make_pair(RegLo, Lo)); + if (RegLo == RISCV::X17) { + if (!StackPtr.getNode()) + StackPtr = DAG.getCopyFromReg(Chain, DL, RISCV::X2, PtrVT); + MemOpChains.push_back(DAG.getStore(Chain, DL, Hi, StackPtr, MachinePointerInfo())); + } + else { + assert(RegLo < RISCV::X31 && "Invalid register pair"); + Register RegHigh = RegLo + 1; + RegsToPass.push_back(std::make_pair(RegHigh, Hi)); + } + continue; + } + if (VA.getLocInfo() == CCValAssign::Indirect) { + SDValue SpillSlot = DAG.CreateStackTemporary(Outs[i].ArgVT); + int FI = cast(SpillSlot)->getIndex(); + MemOpChains.push_back(DAG.getStore(Chain, DL, ArgValue, SpillSlot, MachinePointerInfo::getFixedStack(MF, FI))); + unsigned ArgIndex = Outs[i].OrigArgIndex; + assert(Outs[i].PartOffset == 0); + while (i + 1 != e && Outs[i + 1].OrigArgIndex == ArgIndex) { + SDValue PartValue = OutVals[i + 1]; + unsigned PartOffset = Outs[i + 1].PartOffset; + SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, SpillSlot, DAG.getIntPtrConstant(PartOffset, DL)); + MemOpChains.push_back(DAG.getStore(Chain, DL, PartValue, Address, MachinePointerInfo::getFixedStack(MF, FI))); + ++i; + } + ArgValue = SpillSlot; + } + else { + EVT LocVT = VA.getLocVT(); + switch (VA.getLocInfo()) { + default: + llvm_unreachable("Unexpected CCValAssign::LocInfo"); + case CCValAssign::Full: + break; + case CCValAssign::BCvt: + if (VA.getLocVT().isInteger() && VA.getValVT() == MVT::f16) + Val = DAG.getNode(RISCVISD::FMV_X_ANYEXTH, DL, VA.getLocVT(), Val); + else if (VA.getLocVT() == MVT::i64 && VA.getValVT() == MVT::f32) + Val = DAG.getNode(RISCVISD::FMV_X_ANYEXTW_RV64, DL, MVT::i64, Val); + else + Val = DAG.getNode(ISD::BITCAST, DL, LocVT, Val); + break; + } + ArgValue = Val; + } + if (Flags.isByVal()) + ArgValue = ByValArgs[j++]; + if (VA.isRegLoc()) { + RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue)); + } + else { + assert(VA.isMemLoc() && "Argument not register or memory"); + assert(!IsTailCall && "Tail call not allowed if stack is used for passing parameters"); + if (!StackPtr.getNode()) + StackPtr = DAG.getCopyFromReg(Chain, DL, RISCV::X2, PtrVT); + SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, DAG.getIntPtrConstant(VA.getLocMemOffset(), DL)); + MemOpChains.push_back(DAG.getStore(Chain, DL, ArgValue, Address, MachinePointerInfo())); + } + } + if (!MemOpChains.empty()) + Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains); + SDValue Glue; + for (auto &Reg : RegsToPass) { + Chain = DAG.getCopyToReg(Chain, DL, Reg.first, Reg.second, Glue); + Glue = Chain.getValue(1); + } + validateCCReservedRegs(RegsToPass, MF); + if (!IsTailCall && MF.getSubtarget().isRegisterReservedByUser(RISCV::X1)) + MF.getFunction().getContext().diagnose(DiagnosticInfoUnsupported{MF.getFunction(), "Return address register required, but has been reserved."}); + if (GlobalAddressSDNode *S = dyn_cast(Callee)) { + const GlobalValue *GV = S->getGlobal(); + unsigned OpFlags = RISCVII::MO_CALL; + if (!getTargetMachine().shouldAssumeDSOLocal(*GV->getParent(), GV)) + OpFlags = RISCVII::MO_PLT; + Callee = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, OpFlags); + } + else if (ExternalSymbolSDNode *S = dyn_cast(Callee)) { + unsigned OpFlags = RISCVII::MO_CALL; + if (!getTargetMachine().shouldAssumeDSOLocal(*MF.getFunction().getParent(), nullptr)) + OpFlags = RISCVII::MO_PLT; + Callee = DAG.getTargetExternalSymbol(S->getSymbol(), PtrVT, OpFlags); + } + SmallVector Ops; + Ops.push_back(Chain); + Ops.push_back(Callee); + for (auto &Reg : RegsToPass) + Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType())); + if (!IsTailCall) { + const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); + const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv); + assert(Mask && "Missing call preserved mask for calling convention"); + Ops.push_back(DAG.getRegisterMask(Mask)); + } + if (Glue.getNode()) + Ops.push_back(Glue); + SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); + if (IsTailCall) { + MF.getFrameInfo().setHasTailCall(); + return DAG.getNode(RISCVISD::TAIL, DL, NodeTys, Ops); + } + Chain = DAG.getNode(RISCVISD::CALL, DL, NodeTys, Ops); + DAG.addNoMergeSiteInfo(Chain.getNode(), CLI.NoMerge); + Glue = Chain.getValue(1); + Chain = DAG.getCALLSEQ_END(Chain, DAG.getConstant(NumBytes, DL, PtrVT, true), DAG.getConstant(0, DL, PtrVT, true), Glue, DL); + Glue = Chain.getValue(1); + SmallVector RVLocs; + CCState RetCCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext()); + analyzeInputArgs(MF, RetCCInfo, Ins, true); + for (auto &VA : RVLocs) { + SDValue RetValue = DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), Glue); + Chain = RetValue.getValue(1); + Glue = RetValue.getValue(2); + if (VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64) { + assert(VA.getLocReg() == ArgGPRs[0] && "Unexpected reg assignment"); + SDValue RetValue2 = DAG.getCopyFromReg(Chain, DL, ArgGPRs[1], MVT::i32, Glue); + Chain = RetValue2.getValue(1); + Glue = RetValue2.getValue(2); + RetValue = DAG.getNode(RISCVISD::BuildPairF64, DL, MVT::f64, RetValue, RetValue2); + } + switch (VA.getLocInfo()) { + default: + llvm_unreachable("Unexpected CCValAssign::LocInfo"); + case CCValAssign::Full: + break; + case CCValAssign::BCvt: + if (VA.getLocVT().isInteger() && VA.getValVT() == MVT::f16) + Val = DAG.getNode(RISCVISD::FMV_H_X, DL, MVT::f16, Val); + else if (VA.getLocVT() == MVT::i64 && VA.getValVT() == MVT::f32) + Val = DAG.getNode(RISCVISD::FMV_W_X_RV64, DL, MVT::f32, Val); + else + Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val); + break; + } + RetValue = Val; + InVals.push_back(RetValue); + } + return Chain; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/LowerConstantPool.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/LowerConstantPool.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8c2111e520eec0abbd9dce63ea31d3df135efd14 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/LowerConstantPool.cpp @@ -0,0 +1,4 @@ +SDValue RISCVTargetLowering::lowerConstantPool(SDValue Op, SelectionDAG &DAG) const { + ConstantPoolSDNode *N = cast(Op); + return getAddr(N, DAG); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/LowerFRAMEADDR.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/LowerFRAMEADDR.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7e10d42b15911726b9b98aaadba7f5bbd1bc60fd --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/LowerFRAMEADDR.cpp @@ -0,0 +1,18 @@ +SDValue RISCVTargetLowering::lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { + const RISCVRegisterInfo &RI = *Subtarget.getRegisterInfo(); + MachineFunction &MF = DAG.getMachineFunction(); + MachineFrameInfo &MFI = MF.getFrameInfo(); + MFI.setFrameAddressIsTaken(true); + Register FrameReg = RI.getFrameRegister(MF); + int XLenInBytes = Subtarget.getXLen() / 8; + EVT VT = Op.getValueType(); + SDLoc DL(Op); + SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), DL, FrameReg, VT); + unsigned Depth = cast(Op.getOperand(0))->getZExtValue(); + while (Depth--) { + int Offset = -(XLenInBytes * 2); + SDValue Ptr = DAG.getNode(ISD::ADD, DL, VT, FrameAddr, DAG.getIntPtrConstant(Offset, DL)); + FrameAddr = DAG.getLoad(VT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo()); + } + return FrameAddr; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/LowerFormalArguments.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/LowerFormalArguments.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7469ac29c8818f7827888c7dc5619a3b1397882e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/LowerFormalArguments.cpp @@ -0,0 +1,173 @@ +SDValue RISCVTargetLowering::LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl &InVals) const { + MachineFunction &MF = DAG.getMachineFunction(); + switch (CallConv) { + default: + report_fatal_error("Unsupported calling convention"); + case CallingConv::C: + case CallingConv::Fast: + break; + case CallingConv::GHC: + if (!MF.getSubtarget().getFeatureBits()[RISCV::FeatureStdExtF] || !MF.getSubtarget().getFeatureBits()[RISCV::FeatureStdExtD]) + report_fatal_error("GHC calling convention requires the F and D instruction set extensions"); + } + const Function &Func = MF.getFunction(); + if (Func.hasFnAttribute("interrupt")) { + if (!Func.arg_empty()) + report_fatal_error("Functions with the interrupt attribute cannot have arguments!"); + StringRef Kind = MF.getFunction().getFnAttribute("interrupt").getValueAsString(); + if (!(Kind == "user" || Kind == "supervisor" || Kind == "machine")) + report_fatal_error("Function interrupt attribute argument not supported!"); + } + EVT PtrVT = getPointerTy(DAG.getDataLayout()); + MVT XLenVT = Subtarget.getXLenVT(); + unsigned XLenInBytes = Subtarget.getXLen() / 8; + std::vector OutChains; + SmallVector ArgLocs; + CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext()); + if (CallConv == CallingConv::Fast) + CCInfo.AnalyzeFormalArguments(Ins, CC_RISCV_FastCC); + else if (CallConv == CallingConv::GHC) + CCInfo.AnalyzeFormalArguments(Ins, CC_RISCV_GHC); + else + analyzeInputArgs(MF, CCInfo, Ins, false); + for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { + CCValAssign &VA = ArgLocs[i]; + SDValue ArgValue; + if (VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64) { + assert(VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64 && "Unexpected VA"); + MachineFunction &MF = DAG.getMachineFunction(); + MachineFrameInfo &MFI = MF.getFrameInfo(); + MachineRegisterInfo &RegInfo = MF.getRegInfo(); + if (VA.isMemLoc()) { + int FI = MFI.CreateFixedObject(8, VA.getLocMemOffset(), true); + SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); + ArgValue = DAG.getLoad(MVT::f64, DL, Chain, FIN, MachinePointerInfo::getFixedStack(MF, FI)); + } + assert(VA.isRegLoc() && "Expected register VA assignment"); + Register LoVReg = RegInfo.createVirtualRegister(&RISCV::GPRRegClass); + RegInfo.addLiveIn(VA.getLocReg(), LoVReg); + SDValue Lo = DAG.getCopyFromReg(Chain, DL, LoVReg, MVT::i32); + SDValue Hi; + if (VA.getLocReg() == RISCV::X17) { + int FI = MFI.CreateFixedObject(4, 0, true); + SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); + Hi = DAG.getLoad(MVT::i32, DL, Chain, FIN, MachinePointerInfo::getFixedStack(MF, FI)); + } + else { + Register HiVReg = RegInfo.createVirtualRegister(&RISCV::GPRRegClass); + RegInfo.addLiveIn(VA.getLocReg() + 1, HiVReg); + Hi = DAG.getCopyFromReg(Chain, DL, HiVReg, MVT::i32); + } + ArgValue = DAG.getNode(RISCVISD::BuildPairF64, DL, MVT::f64, Lo, Hi); + } + else if (VA.isRegLoc()) { + MachineFunction &MF = DAG.getMachineFunction(); + MachineRegisterInfo &RegInfo = MF.getRegInfo(); + EVT LocVT = VA.getLocVT(); + SDValue Val; + const TargetRegisterClass *RC = TLI.getRegClassFor(LocVT.getSimpleVT()); + Register VReg = RegInfo.createVirtualRegister(RC); + RegInfo.addLiveIn(VA.getLocReg(), VReg); + Val = DAG.getCopyFromReg(Chain, DL, VReg, LocVT); + if (VA.getLocInfo() == CCValAssign::Indirect) { + return Val; + } + switch (VA.getLocInfo()) { + default: + llvm_unreachable("Unexpected CCValAssign::LocInfo"); + case CCValAssign::Full: + break; + case CCValAssign::BCvt: + if (VA.getLocVT().isInteger() && VA.getValVT() == MVT::f16) + Val = DAG.getNode(RISCVISD::FMV_H_X, DL, MVT::f16, Val); + else if (VA.getLocVT() == MVT::i64 && VA.getValVT() == MVT::f32) + Val = DAG.getNode(RISCVISD::FMV_W_X_RV64, DL, MVT::f32, Val); + else + Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val); + break; + } + ArgValue = Val; + } + else { + MachineFunction &MF = DAG.getMachineFunction(); + MachineRegisterInfo &RegInfo = MF.getRegInfo(); + EVT LocVT = VA.getLocVT(); + SDValue Val; + const TargetRegisterClass *RC = TLI.getRegClassFor(LocVT.getSimpleVT()); + Register VReg = RegInfo.createVirtualRegister(RC); + RegInfo.addLiveIn(VA.getLocReg(), VReg); + Val = DAG.getCopyFromReg(Chain, DL, VReg, LocVT); + if (VA.getLocInfo() == CCValAssign::Indirect) { + return Val; + } + switch (VA.getLocInfo()) { + default: + llvm_unreachable("Unexpected CCValAssign::LocInfo"); + case CCValAssign::Full: + break; + case CCValAssign::BCvt: + if (VA.getLocVT().isInteger() && VA.getValVT() == MVT::f16) + Val = DAG.getNode(RISCVISD::FMV_H_X, DL, MVT::f16, Val); + else if (VA.getLocVT() == MVT::i64 && VA.getValVT() == MVT::f32) + Val = DAG.getNode(RISCVISD::FMV_W_X_RV64, DL, MVT::f32, Val); + else + Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val); + break; + } + ArgValue = Val; + } + if (VA.getLocInfo() == CCValAssign::Indirect) { + InVals.push_back(DAG.getLoad(VA.getValVT(), DL, Chain, ArgValue, MachinePointerInfo())); + unsigned ArgIndex = Ins[i].OrigArgIndex; + assert(Ins[i].PartOffset == 0); + while (i + 1 != e && Ins[i + 1].OrigArgIndex == ArgIndex) { + CCValAssign &PartVA = ArgLocs[i + 1]; + unsigned PartOffset = Ins[i + 1].PartOffset; + SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, ArgValue, DAG.getIntPtrConstant(PartOffset, DL)); + InVals.push_back(DAG.getLoad(PartVA.getValVT(), DL, Chain, Address, MachinePointerInfo())); + ++i; + } + continue; + } + InVals.push_back(ArgValue); + } + if (IsVarArg) { + ArrayRef ArgRegs = makeArrayRef(ArgGPRs); + unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs); + const TargetRegisterClass *RC = &RISCV::GPRRegClass; + MachineFrameInfo &MFI = MF.getFrameInfo(); + MachineRegisterInfo &RegInfo = MF.getRegInfo(); + RISCVMachineFunctionInfo *RVFI = MF.getInfo(); + int VaArgOffset, VarArgsSaveSize; + if (ArgRegs.size() == Idx) { + VaArgOffset = CCInfo.getNextStackOffset(); + VarArgsSaveSize = 0; + } + else { + VarArgsSaveSize = XLenInBytes * (ArgRegs.size() - Idx); + VaArgOffset = -VarArgsSaveSize; + } + int FI = MFI.CreateFixedObject(XLenInBytes, VaArgOffset, true); + RVFI->setVarArgsFrameIndex(FI); + if (Idx % 2) { + MFI.CreateFixedObject(XLenInBytes, VaArgOffset - (int)XLenInBytes, true); + VarArgsSaveSize += XLenInBytes; + } + for (unsigned I = Idx; I < ArgRegs.size(); ++I, VaArgOffset += XLenInBytes) { + const Register Reg = RegInfo.createVirtualRegister(RC); + RegInfo.addLiveIn(ArgRegs[I], Reg); + SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, XLenVT); + FI = MFI.CreateFixedObject(XLenInBytes, VaArgOffset, true); + SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); + SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff, MachinePointerInfo::getFixedStack(MF, FI)); + cast(Store.getNode())->getMemOperand()->setValue((Value *)nullptr); + OutChains.push_back(Store); + } + RVFI->setVarArgsSaveSize(VarArgsSaveSize); + } + if (!OutChains.empty()) { + OutChains.push_back(Chain); + Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains); + } + return Chain; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/LowerGlobalAddress.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/LowerGlobalAddress.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c25fe7ba981ac3b403417bdc8e02f9bd6b4c8c15 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/LowerGlobalAddress.cpp @@ -0,0 +1,14 @@ +SDValue RISCVTargetLowering::lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const { + SDLoc DL(Op); + EVT Ty = Op.getValueType(); + GlobalAddressSDNode *N = cast(Op); + int64_t Offset = N->getOffset(); + MVT XLenVT = Subtarget.getXLenVT(); + const GlobalValue *GV = N->getGlobal(); + bool IsLocal = getTargetMachine().shouldAssumeDSOLocal(*GV->getParent(), GV); + SDValue Addr = getAddr(N, DAG, IsLocal); + if (Offset != 0) { + return DAG.getNode(ISD::ADD, DL, Ty, Addr, DAG.getConstant(Offset, DL, XLenVT)); + } + return Addr; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/LowerGlobalTLSAddress.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/LowerGlobalTLSAddress.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5d4b3eab18404fd36209d8bc0fe8ec8025c6bad1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/LowerGlobalTLSAddress.cpp @@ -0,0 +1,28 @@ +SDValue RISCVTargetLowering::lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { + SDLoc DL(Op); + EVT Ty = Op.getValueType(); + GlobalAddressSDNode *N = cast(Op); + int64_t Offset = N->getOffset(); + MVT XLenVT = Subtarget.getXLenVT(); + TLSModel::Model Model = getTargetMachine().getTLSModel(N->getGlobal()); + if (DAG.getMachineFunction().getFunction().getCallingConv() == CallingConv::GHC) { + report_fatal_error("In GHC calling convention TLS is not supported"); + } + SDValue Addr; + switch (Model) { + case TLSModel::LocalExec: + Addr = getStaticTLSAddr(N, DAG, false); + break; + case TLSModel::InitialExec: + Addr = getStaticTLSAddr(N, DAG, true); + break; + case TLSModel::LocalDynamic: + case TLSModel::GeneralDynamic: + Addr = getDynamicTLSAddr(N, DAG); + break; + } + if (Offset != 0) { + return DAG.getNode(ISD::ADD, DL, Ty, Addr, DAG.getConstant(Offset, DL, XLenVT)); + } + return Addr; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/LowerINTRINSIC_WO_CHAIN.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/LowerINTRINSIC_WO_CHAIN.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d271e260065b73f42c25f03d51b9b440bdc038bb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/LowerINTRINSIC_WO_CHAIN.cpp @@ -0,0 +1,30 @@ +SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const { + unsigned IntNo = cast(Op.getOperand(0))->getZExtValue(); + SDLoc DL(Op); + if (Subtarget.hasStdExtV()) { + if (const RISCVVIntrinsicsTable::RISCVVIntrinsicInfo *II = RISCVVIntrinsicsTable::getRISCVVIntrinsicInfo(IntNo)) { + if (II->ExtendedOperand) { + assert(II->ExtendedOperand < Op.getNumOperands()); + SmallVector Operands(Op->op_begin(), Op->op_end()); + SDValue &ScalarOp = Operands[II->ExtendedOperand]; + EVT OpVT = ScalarOp.getValueType(); + if (OpVT == MVT::i8 || OpVT == MVT::i16 || (OpVT == MVT::i32 && Subtarget.is64Bit())) { + unsigned ExtOpc = isa(ScalarOp) ? ISD::SIGN_EXTEND : ISD::ANY_EXTEND; + ScalarOp = DAG.getNode(ExtOpc, DL, Subtarget.getXLenVT(), ScalarOp); + return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, Op.getValueType(), Operands); + } + } + } + } + switch (IntNo) { + default: + return SDValue(); + case Intrinsic::thread_pointer: { + EVT PtrVT = getPointerTy(DAG.getDataLayout()); + return DAG.getRegister(RISCV::X4, PtrVT); + } + case Intrinsic::riscv_vmv_x_s: + assert(Op.getValueType() == Subtarget.getXLenVT() && "Unexpected VT!"); + return DAG.getNode(RISCVISD::VMV_X_S, DL, Op.getValueType(), Op.getOperand(1)); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/LowerINTRINSIC_W_CHAIN.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/LowerINTRINSIC_W_CHAIN.cpp new file mode 100644 index 0000000000000000000000000000000000000000..75222c60f17cae9305bbe5868ddff56b5bd22751 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/LowerINTRINSIC_W_CHAIN.cpp @@ -0,0 +1,122 @@ +SDValue RISCVTargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const { + unsigned IntNo = cast(Op.getOperand(1))->getZExtValue(); + SDLoc DL(Op); + if (Subtarget.hasStdExtV()) { + if (const RISCVVIntrinsicsTable::RISCVVIntrinsicInfo *II = RISCVVIntrinsicsTable::getRISCVVIntrinsicInfo(IntNo)) { + if (II->ExtendedOperand) { + unsigned ExtendOp = II->ExtendedOperand + 1; + assert(ExtendOp < Op.getNumOperands()); + SmallVector Operands(Op->op_begin(), Op->op_end()); + SDValue &ScalarOp = Operands[ExtendOp]; + EVT OpVT = ScalarOp.getValueType(); + if (OpVT == MVT::i8 || OpVT == MVT::i16 || (OpVT == MVT::i32 && Subtarget.is64Bit())) { + unsigned ExtOpc = isa(ScalarOp) ? ISD::SIGN_EXTEND : ISD::ANY_EXTEND; + ScalarOp = DAG.getNode(ExtOpc, DL, Subtarget.getXLenVT(), ScalarOp); + return DAG.getNode(ISD::INTRINSIC_W_CHAIN, DL, Op->getVTList(), Operands); + } + } + } + } + unsigned NF = 1; + switch (IntNo) { + default: + return SDValue(); + case Intrinsic::riscv_vleff: { + SDLoc DL(Op); + SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Other, MVT::Glue); + SDValue Load = DAG.getNode(RISCVISD::VLEFF, DL, VTs, Op.getOperand(0), Op.getOperand(2), Op.getOperand(3)); + VTs = DAG.getVTList(Op->getValueType(1), MVT::Other); + SDValue ReadVL = DAG.getNode(RISCVISD::READ_VL, DL, VTs, Load.getValue(2)); + return DAG.getMergeValues({Load, ReadVL, Load.getValue(1)}, DL); + } + case Intrinsic::riscv_vleff_mask: { + SDLoc DL(Op); + SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Other, MVT::Glue); + SDValue Load = DAG.getNode(RISCVISD::VLEFF_MASK, DL, VTs, Op.getOperand(0), Op.getOperand(2), Op.getOperand(3), Op.getOperand(4), Op.getOperand(5)); + VTs = DAG.getVTList(Op->getValueType(1), MVT::Other); + SDValue ReadVL = DAG.getNode(RISCVISD::READ_VL, DL, VTs, Load.getValue(2)); + return DAG.getMergeValues({Load, ReadVL, Load.getValue(1)}, DL); + } + case Intrinsic::riscv_vlseg8ff: + NF++; + LLVM_FALLTHROUGH; + case Intrinsic::riscv_vlseg7ff: + NF++; + LLVM_FALLTHROUGH; + case Intrinsic::riscv_vlseg6ff: + NF++; + LLVM_FALLTHROUGH; + case Intrinsic::riscv_vlseg5ff: + NF++; + LLVM_FALLTHROUGH; + case Intrinsic::riscv_vlseg4ff: + NF++; + LLVM_FALLTHROUGH; + case Intrinsic::riscv_vlseg3ff: + NF++; + LLVM_FALLTHROUGH; + case Intrinsic::riscv_vlseg2ff: { + NF++; + SDLoc DL(Op); + SmallVector EVTs(NF, Op.getValueType()); + EVTs.push_back(MVT::Other); + EVTs.push_back(MVT::Glue); + SDVTList VTs = DAG.getVTList(EVTs); + SDValue Load = DAG.getNode(RISCVISD::VLSEGFF, DL, VTs, Op.getOperand(0), Op.getOperand(1), Op.getOperand(2), Op.getOperand(3)); + VTs = DAG.getVTList(Op->getValueType(NF), MVT::Other); + SDValue ReadVL = DAG.getNode(RISCVISD::READ_VL, DL, VTs, Load.getValue(NF + 1)); + SmallVector Results; + for (unsigned i = 0; i < NF; ++i) { + Results.push_back(Load.getValue(i)); + } + Results.push_back(ReadVL); + Results.push_back(Load.getValue(NF)); + return DAG.getMergeValues(Results, DL); + } + case Intrinsic::riscv_vlseg8ff_mask: + NF++; + LLVM_FALLTHROUGH; + case Intrinsic::riscv_vlseg7ff_mask: + NF++; + LLVM_FALLTHROUGH; + case Intrinsic::riscv_vlseg6ff_mask: + NF++; + LLVM_FALLTHROUGH; + case Intrinsic::riscv_vlseg5ff_mask: + NF++; + LLVM_FALLTHROUGH; + case Intrinsic::riscv_vlseg4ff_mask: + NF++; + LLVM_FALLTHROUGH; + case Intrinsic::riscv_vlseg3ff_mask: + NF++; + LLVM_FALLTHROUGH; + case Intrinsic::riscv_vlseg2ff_mask: { + NF++; + SDLoc DL(Op); + SmallVector EVTs(NF, Op.getValueType()); + EVTs.push_back(MVT::Other); + EVTs.push_back(MVT::Glue); + SDVTList VTs = DAG.getVTList(EVTs); + SmallVector LoadOps; + LoadOps.push_back(Op.getOperand(0)); + LoadOps.push_back(Op.getOperand(1)); + for (unsigned i = 0; i < NF; ++i) { + LoadOps.push_back(Op.getOperand(2 + i)); + } + LoadOps.push_back(Op.getOperand(2 + NF)); + LoadOps.push_back(Op.getOperand(3 + NF)); + LoadOps.push_back(Op.getOperand(4 + NF)); + SDValue Load = DAG.getNode(RISCVISD::VLSEGFF_MASK, DL, VTs, LoadOps); + VTs = DAG.getVTList(Op->getValueType(NF), MVT::Other); + SDValue ReadVL = DAG.getNode(RISCVISD::READ_VL, DL, VTs, Load.getValue(NF + 1)); + SmallVector Results; + for (unsigned i = 0; i < NF; ++i) { + Results.push_back(Load.getValue(i)); + } + Results.push_back(ReadVL); + Results.push_back(Load.getValue(NF)); + return DAG.getMergeValues(Results, DL); + } + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/LowerJumpTable.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/LowerJumpTable.cpp new file mode 100644 index 0000000000000000000000000000000000000000..68048321fc1a4520cf96294b8748c120bfbe8b55 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/LowerJumpTable.cpp @@ -0,0 +1,4 @@ +SDValue RISCVTargetLowering::lowerJumpTable(SDValue Op, SelectionDAG &DAG) const { + JumpTableSDNode *N = cast(Op); + return getAddr(N, DAG); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/LowerOperation.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/LowerOperation.cpp new file mode 100644 index 0000000000000000000000000000000000000000..65190eb29c998ae548a8d652898fe5771b4c5e37 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/LowerOperation.cpp @@ -0,0 +1,133 @@ +SDValue RISCVTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { + if (Op.getOpcode() == ISD::GlobalAddress) { + return lowerGlobalAddress(Op, DAG); + } + if (Op.getOpcode() == ISD::BlockAddress) { + return lowerBlockAddress(Op, DAG); + } + if (Op.getOpcode() == ISD::ConstantPool) { + return lowerConstantPool(Op, DAG); + } + if (Op.getOpcode() == ISD::BlockAddress) { + return lowerBlockAddress(Op, DAG); + } + if (Op.getOpcode() == ISD::JumpTable) { + return lowerJumpTable(Op, DAG); + } + if (Op.getOpcode() == ISD::GlobalTLSAddress) { + return lowerGlobalTLSAddress(Op, DAG); + } + if (Op.getOpcode() == ISD::SELECT) { + return lowerSELECT(Op, DAG); + } + if (Op.getOpcode() == ISD::VASTART) { + return lowerVASTART(Op, DAG); + } + if (Op.getOpcode() == ISD::RETURNADDR) { + return lowerRETURNADDR(Op, DAG); + } + if (Op.getOpcode() == ISD::FRAMEADDR) { + return lowerFRAMEADDR(Op, DAG); + } + if (Op.getOpcode() == ISD::SHL_PARTS) { + return lowerShiftLeftParts(Op, DAG); + } + if (Op.getOpcode() == ISD::SRA_PARTS) { + return lowerShiftRightParts(Op, DAG, true); + } + if (Op.getOpcode() == ISD::SRL_PARTS) { + return lowerShiftRightParts(Op, DAG, false); + } + if (Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN) { + return LowerINTRINSIC_WO_CHAIN(Op, DAG); + } + if (Op.getOpcode() == ISD::INTRINSIC_W_CHAIN) { + return LowerINTRINSIC_W_CHAIN(Op, DAG); + } + if (Op.getOpcode() == ISD::ANY_EXTEND) { + return lowerVectorMaskExt(Op, DAG, 1); + } + if (Op.getOpcode() == ISD::ZERO_EXTEND) { + return lowerVectorMaskExt(Op, DAG, 1); + } + if (Op.getOpcode() == ISD::SIGN_EXTEND) { + return lowerVectorMaskExt(Op, DAG, -1); + } + if (Op.getOpcode() == ISD::SPLAT_VECTOR) { + return lowerSPLATVECTOR(Op, DAG); + } + if (Op.getOpcode() == ISD::INSERT_VECTOR_ELT) { + return lowerINSERT_VECTOR_ELT(Op, DAG); + } + if (Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT) { + return lowerEXTRACT_VECTOR_ELT(Op, DAG); + } + if (Op.getOpcode() == ISD::BITCAST) { + assert(((Subtarget.is64Bit() && Subtarget.hasStdExtF()) || Subtarget.hasStdExtZfh()) && "Unexpected custom legalisation"); + SDLoc DL(Op); + SDValue Op0 = Op.getOperand(0); + if (Op.getValueType() == MVT::f16 && Subtarget.hasStdExtZfh()) { + if (Op0.getValueType() != MVT::i16) + return SDValue(); + SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, Subtarget.getXLenVT(), Op0); + SDValue FPConv = DAG.getNode(RISCVISD::FMV_H_X, DL, MVT::f16, NewOp0); + return FPConv; + } + else if (Op.getValueType() == MVT::f32 && Subtarget.is64Bit() && Subtarget.hasStdExtF()) { + if (Op0.getValueType() != MVT::i32) + return SDValue(); + SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op0); + SDValue FPConv = DAG.getNode(RISCVISD::FMV_W_X_RV64, DL, MVT::f32, NewOp0); + return FPConv; + } + return SDValue(); + } + if (Op.getOpcode() == ISD::BSWAP) { + assert(Subtarget.hasStdExtZbp() && "Unexpected custom legalisation"); + MVT VT = Op.getSimpleValueType(); + SDLoc DL(Op); + unsigned Imm = VT.getSizeInBits() - 1; + if (Op.getOpcode() == ISD::BSWAP) + Imm &= ~0x7U; + return DAG.getNode(RISCVISD::GREVI, DL, VT, Op.getOperand(0), DAG.getTargetConstant(Imm, DL, Subtarget.getXLenVT())); + } + if (Op.getOpcode() == ISD::BITREVERSE) { + assert(Subtarget.hasStdExtZbp() && "Unexpected custom legalisation"); + MVT VT = Op.getSimpleValueType(); + SDLoc DL(Op); + unsigned Imm = VT.getSizeInBits() - 1; + if (Op.getOpcode() == ISD::BSWAP) + Imm &= ~0x7U; + return DAG.getNode(RISCVISD::GREVI, DL, VT, Op.getOperand(0), DAG.getTargetConstant(Imm, DL, Subtarget.getXLenVT())); + } + if (Op.getOpcode() == ISD::TRUNCATE) { + SDLoc DL(Op); + EVT VT = Op.getValueType(); + if (!VT.isVector()) + return Op; + if (VT.getVectorElementType() == MVT::i1) + return lowerVectorMaskTrunc(Op, DAG); + EVT DstEltVT = VT.getVectorElementType(); + SDValue Src = Op.getOperand(0); + EVT SrcVT = Src.getValueType(); + EVT SrcEltVT = SrcVT.getVectorElementType(); + assert(DstEltVT.bitsLT(SrcEltVT) && isPowerOf2_64(DstEltVT.getSizeInBits()) && isPowerOf2_64(SrcEltVT.getSizeInBits()) && "Unexpected vector truncate lowering"); + SDValue Result = Src; + LLVMContext &Context = *DAG.getContext(); + const ElementCount Count = SrcVT.getVectorElementCount(); + do { + SrcEltVT = EVT::getIntegerVT(Context, SrcEltVT.getSizeInBits() / 2); + EVT ResultVT = EVT::getVectorVT(Context, SrcEltVT, Count); + Result = DAG.getNode(RISCVISD::TRUNCATE_VECTOR, DL, ResultVT, Result); + } while (SrcEltVT != DstEltVT); + return Result; + } + if (Op.getOpcode() == ISD::VSCALE) { + MVT VT = Op.getSimpleValueType(); + SDLoc DL(Op); + SDValue VLENB = DAG.getNode(RISCVISD::READ_VLENB, DL, VT); + SDValue VScale = DAG.getNode(ISD::SRL, DL, VT, VLENB, DAG.getConstant(3, DL, VT)); + return DAG.getNode(ISD::MUL, DL, VT, VScale, Op.getOperand(0)); + } + report_fatal_error("unimplemented operand"); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/LowerRETURNADDR.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/LowerRETURNADDR.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cedd67999ef313543cc50253a91f0d00bc57396a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/LowerRETURNADDR.cpp @@ -0,0 +1,22 @@ +SDValue RISCVTargetLowering::lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const { + const RISCVRegisterInfo &RI = *Subtarget.getRegisterInfo(); + MachineFunction &MF = DAG.getMachineFunction(); + MachineFrameInfo &MFI = MF.getFrameInfo(); + MFI.setReturnAddressIsTaken(true); + MVT XLenVT = Subtarget.getXLenVT(); + int XLenInBytes = Subtarget.getXLen() / 8; + if (verifyReturnAddressArgumentIsConstant(Op, DAG)) { + return SDValue(); + } + EVT VT = Op.getValueType(); + SDLoc DL(Op); + unsigned Depth = cast(Op.getOperand(0))->getZExtValue(); + if (Depth) { + int Off = -XLenInBytes; + SDValue FrameAddr = lowerFRAMEADDR(Op, DAG); + SDValue Offset = DAG.getConstant(Off, DL, VT); + return DAG.getLoad(VT, DL, DAG.getEntryNode(), DAG.getNode(ISD::ADD, DL, VT, FrameAddr, Offset), MachinePointerInfo()); + } + Register Reg = MF.addLiveIn(RI.getRARegister(), getRegClassFor(XLenVT)); + return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, XLenVT); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/LowerReturn.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/LowerReturn.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1fe9a45c04e3607a7410233c686e1945b9b64220 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/LowerReturn.cpp @@ -0,0 +1,82 @@ +SDValue RISCVTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl &Outs, const SmallVectorImpl &OutVals, const SDLoc &DL, SelectionDAG &DAG) const { + const MachineFunction &MF = DAG.getMachineFunction(); + const RISCVSubtarget &STI = MF.getSubtarget(); + SmallVector RVLocs; + CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, *DAG.getContext()); + analyzeOutputArgs(DAG.getMachineFunction(), CCInfo, Outs, true, nullptr); + if (CallConv == CallingConv::GHC && !RVLocs.empty()) { + report_fatal_error("GHC functions return void only"); + } + SDValue Glue; + SmallVector RetOps(1, Chain); + for (unsigned i = 0, e = RVLocs.size(); i < e; ++i) { + SDValue Val = OutVals[i]; + CCValAssign &VA = RVLocs[i]; + assert(VA.isRegLoc() && "Can only return in registers!"); + if (VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64) { + assert(VA.isRegLoc() && "Expected return via registers"); + SDValue SplitF64 = DAG.getNode(RISCVISD::SplitF64, DL, DAG.getVTList(MVT::i32, MVT::i32), Val); + SDValue Lo = SplitF64.getValue(0); + SDValue Hi = SplitF64.getValue(1); + Register RegLo = VA.getLocReg(); + assert(RegLo < RISCV::X31 && "Invalid register pair"); + Register RegHi = RegLo + 1; + if (STI.isRegisterReservedByUser(RegLo) || STI.isRegisterReservedByUser(RegHi)) { + MF.getFunction().getContext().diagnose(DiagnosticInfoUnsupported{MF.getFunction(), "Return value register required, but has been reserved."}); + } + Chain = DAG.getCopyToReg(Chain, DL, RegLo, Lo, Glue); + Glue = Chain.getValue(1); + RetOps.push_back(DAG.getRegister(RegLo, MVT::i32)); + Chain = DAG.getCopyToReg(Chain, DL, RegHi, Hi, Glue); + Glue = Chain.getValue(1); + RetOps.push_back(DAG.getRegister(RegHi, MVT::i32)); + } + else { + EVT LocVT = VA.getLocVT(); + switch (VA.getLocInfo()) { + default: + llvm_unreachable("Unexpected CCValAssign::LocInfo"); + case CCValAssign::Full: + break; + case CCValAssign::BCvt: + if (VA.getLocVT().isInteger() && VA.getValVT() == MVT::f16) + Val = DAG.getNode(RISCVISD::FMV_X_ANYEXTH, DL, VA.getLocVT(), Val); + else if (VA.getLocVT() == MVT::i64 && VA.getValVT() == MVT::f32) + Val = DAG.getNode(RISCVISD::FMV_X_ANYEXTW_RV64, DL, MVT::i64, Val); + else + Val = DAG.getNode(ISD::BITCAST, DL, LocVT, Val); + break; + } + Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Glue); + if (STI.isRegisterReservedByUser(VA.getLocReg())) { + MF.getFunction().getContext().diagnose(DiagnosticInfoUnsupported{MF.getFunction(), "Return value register required, but has been reserved."}); + } + Glue = Chain.getValue(1); + RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); + } + } + RetOps[0] = Chain; + if (Glue.getNode()) { + RetOps.push_back(Glue); + } + const Function &Func = DAG.getMachineFunction().getFunction(); + if (Func.hasFnAttribute("interrupt")) { + if (!Func.getReturnType()->isVoidTy()) { + report_fatal_error("Functions with the interrupt attribute must have void return type!"); + } + MachineFunction &MF = DAG.getMachineFunction(); + StringRef Kind = MF.getFunction().getFnAttribute("interrupt").getValueAsString(); + unsigned RetOpc; + if (Kind == "user") { + RetOpc = RISCVISD::URET_FLAG; + } + else if (Kind == "supervisor") { + RetOpc = RISCVISD::SRET_FLAG; + } + else { + RetOpc = RISCVISD::MRET_FLAG; + } + return DAG.getNode(RetOpc, DL, MVT::Other, RetOps); + } + return DAG.getNode(RISCVISD::RET_FLAG, DL, MVT::Other, RetOps); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/LowerVASTART.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/LowerVASTART.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c2a8b1538a1e45039697e8f264bcdc901c75ab5e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/LowerVASTART.cpp @@ -0,0 +1,8 @@ +SDValue RISCVTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const { + MachineFunction &MF = DAG.getMachineFunction(); + RISCVMachineFunctionInfo *FuncInfo = MF.getInfo(); + SDLoc DL(Op); + SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), getPointerTy(MF.getDataLayout())); + const Value *SV = cast(Op.getOperand(2))->getValue(); + return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1), MachinePointerInfo(SV)); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/NodeType.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/NodeType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5b667b731b88f74eb2e0a2d08828d7fb845c2a26 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/NodeType.cpp @@ -0,0 +1,43 @@ +enum NodeType : unsigned { +FIRST_NUMBER = ISD::BUILTIN_OP_END, +RET_FLAG, +URET_FLAG, +SRET_FLAG, +MRET_FLAG, +CALL, +SELECT_CC, +BuildPairF64, +SplitF64, +TAIL, +SLLW, +SRAW, +SRLW, +DIVW, +DIVUW, +REMUW, +ROLW, +RORW, +FSRW, +FSLW, +FMV_H_X, +FMV_X_ANYEXTH, +FMV_W_X_RV64, +FMV_X_ANYEXTW_RV64, +READ_CYCLE_WIDE, +GREVI, +GREVIW, +GORCI, +GORCIW, +VMV_X_S, +SPLAT_VECTOR_I64, +READ_VLENB, +TRUNCATE_VECTOR, +VLEFF, +VLEFF_MASK, +VLSEGFF, +VLSEGFF_MASK, +READ_VL, +VSLIDEUP, +VSLIDEDOWN, +VID, +}; diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/PerformDAGCombine.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/PerformDAGCombine.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b5d7b0da4ad63e0b6d0d5a2618796ca7bacb4ee0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/PerformDAGCombine.cpp @@ -0,0 +1,348 @@ +SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { + SelectionDAG &DAG = DCI.DAG; + switch (N->getOpcode()) { + default: + break; + case RISCVISD::SplitF64: { + SDValue Op0 = N->getOperand(0); + if (Op0->getOpcode() == RISCVISD::BuildPairF64) + return DCI.CombineTo(N, Op0.getOperand(0), Op0.getOperand(1)); + SDLoc DL(N); + if (ConstantFPSDNode *C = dyn_cast(Op0)) { + APInt V = C->getValueAPF().bitcastToAPInt(); + SDValue Lo = DAG.getConstant(V.trunc(32), DL, MVT::i32); + SDValue Hi = DAG.getConstant(V.lshr(32).trunc(32), DL, MVT::i32); + return DCI.CombineTo(N, Lo, Hi); + } + if (!(Op0.getOpcode() == ISD::FNEG || Op0.getOpcode() == ISD::FABS) || !Op0.getNode()->hasOneUse()) + break; + SDValue NewSplitF64 = DAG.getNode(RISCVISD::SplitF64, DL, DAG.getVTList(MVT::i32, MVT::i32), Op0.getOperand(0)); + SDValue Lo = NewSplitF64.getValue(0); + SDValue Hi = NewSplitF64.getValue(1); + APInt SignBit = APInt::getSignMask(32); + if (Op0.getOpcode() == ISD::FNEG) { + SDValue NewHi = DAG.getNode(ISD::XOR, DL, MVT::i32, Hi, DAG.getConstant(SignBit, DL, MVT::i32)); + return DCI.CombineTo(N, Lo, NewHi); + } + assert(Op0.getOpcode() == ISD::FABS); + SDValue NewHi = DAG.getNode(ISD::AND, DL, MVT::i32, Hi, DAG.getConstant(~SignBit, DL, MVT::i32)); + return DCI.CombineTo(N, Lo, NewHi); + } + case RISCVISD::SLLW: + case RISCVISD::SRAW: + case RISCVISD::SRLW: + case RISCVISD::ROLW: + case RISCVISD::RORW: { + SDValue LHS = N->getOperand(0); + SDValue RHS = N->getOperand(1); + APInt LHSMask = APInt::getLowBitsSet(LHS.getValueSizeInBits(), 32); + APInt RHSMask = APInt::getLowBitsSet(RHS.getValueSizeInBits(), 5); + if (SimplifyDemandedBits(N->getOperand(0), LHSMask, DCI) || SimplifyDemandedBits(N->getOperand(1), RHSMask, DCI)) { + if (N->getOpcode() != ISD::DELETED_NODE) + DCI.AddToWorklist(N); + return SDValue(N, 0); + } + break; + } + case RISCVISD::FSLW: + case RISCVISD::FSRW: { + SDValue Op0 = N->getOperand(0); + SDValue Op1 = N->getOperand(1); + SDValue ShAmt = N->getOperand(2); + APInt OpMask = APInt::getLowBitsSet(Op0.getValueSizeInBits(), 32); + APInt ShAmtMask = APInt::getLowBitsSet(ShAmt.getValueSizeInBits(), 6); + if (SimplifyDemandedBits(Op0, OpMask, DCI) || SimplifyDemandedBits(Op1, OpMask, DCI) || SimplifyDemandedBits(ShAmt, ShAmtMask, DCI)) { + if (N->getOpcode() != ISD::DELETED_NODE) + DCI.AddToWorklist(N); + return SDValue(N, 0); + } + break; + } + case RISCVISD::GREVIW: + case RISCVISD::GORCIW: { + SDValue Op0 = N->getOperand(0); + APInt Mask = APInt::getLowBitsSet(Op0.getValueSizeInBits(), 32); + if (SimplifyDemandedBits(Op0, Mask, DCI)) { + if (N->getOpcode() != ISD::DELETED_NODE) DCI.AddToWorklist(N); + return SDValue(N, 0); + } + unsigned ShAmt1 = N->getConstantOperandVal(1); + SDValue Src = N->getOperand(0); + if (Src.getOpcode() != N->getOpcode()) + return SDValue(); + unsigned ShAmt2 = Src.getConstantOperandVal(1); + Src = Src.getOperand(0); + unsigned CombinedShAmt; + if (N->getOpcode() == RISCVISD::GORCI || N->getOpcode() == RISCVISD::GORCIW) + CombinedShAmt = ShAmt1 | ShAmt2; + else + CombinedShAmt = ShAmt1 ^ ShAmt2; + if (CombinedShAmt == 0) + return Src; + SDLoc DL(N); + return DAG.getNode(N->getOpcode(), DL, N->getValueType(0), Src, DAG.getTargetConstant(CombinedShAmt, DL, N->getOperand(1).getValueType())); + } + case RISCVISD::FMV_X_ANYEXTW_RV64: { + SDLoc DL(N); + SDValue Op0 = N->getOperand(0); + if (Op0->getOpcode() == RISCVISD::FMV_W_X_RV64) { + assert(Op0.getOperand(0).getValueType() == MVT::i64 && "Unexpected value type!"); + return Op0.getOperand(0); + } + if (!(Op0.getOpcode() == ISD::FNEG || Op0.getOpcode() == ISD::FABS) || !Op0.getNode()->hasOneUse()) + break; + SDValue NewFMV = DAG.getNode(RISCVISD::FMV_X_ANYEXTW_RV64, DL, MVT::i64, Op0.getOperand(0)); + APInt SignBit = APInt::getSignMask(32).sext(64); + if (Op0.getOpcode() == ISD::FNEG) + return DAG.getNode(ISD::XOR, DL, MVT::i64, NewFMV, DAG.getConstant(SignBit, DL, MVT::i64)); + assert(Op0.getOpcode() == ISD::FABS); + return DAG.getNode(ISD::AND, DL, MVT::i64, NewFMV, DAG.getConstant(~SignBit, DL, MVT::i64)); + } + case RISCVISD::GREVI: + case RISCVISD::GORCI: + unsigned ShAmt1 = N->getConstantOperandVal(1); + SDValue Src = N->getOperand(0); + if (Src.getOpcode() != N->getOpcode()) + return SDValue(); + unsigned ShAmt2 = Src.getConstantOperandVal(1); + Src = Src.getOperand(0); + unsigned CombinedShAmt; + if (N->getOpcode() == RISCVISD::GORCI || N->getOpcode() == RISCVISD::GORCIW) + CombinedShAmt = ShAmt1 | ShAmt2; + else + CombinedShAmt = ShAmt1 ^ ShAmt2; + if (CombinedShAmt == 0) + return Src; + SDLoc DL(N); + return DAG.getNode(N->getOpcode(), DL, N->getValueType(0), Src, DAG.getTargetConstant(CombinedShAmt, DL, N->getOperand(1).getValueType())); + case ISD::OR: + EVT VT = Op.getValueType(); + if (VT == Subtarget.getXLenVT() || (Subtarget.is64Bit() && VT == MVT::i32)) { + Optional Mask; + if (Op.getOpcode() == ISD::AND && isa(Op.getOperand(1))) { + Mask = Op.getConstantOperandVal(1); + Op = Op.getOperand(0); + } + if (Op.getOpcode() != ISD::SHL && Op.getOpcode() != ISD::SRL) + return None; + bool IsSHL = Op.getOpcode() == ISD::SHL; + if (!isa(Op.getOperand(1))) + return None; + auto ShAmt = Op.getConstantOperandVal(1); + if (!isPowerOf2_64(ShAmt)) + return None; + static const uint64_t BitmanipMasks[] = { + 0x5555555555555555ULL, 0x3333333333333333ULL, 0x0F0F0F0F0F0F0F0FULL, + 0x00FF00FF00FF00FFULL, 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL, + }; + unsigned MaskIdx = Log2_64(ShAmt); + if (MaskIdx >= array_lengthof(BitmanipMasks)) + return None; + auto Src = Op.getOperand(0); + unsigned Width = Op.getValueType() == MVT::i64 ? 64 : 32; + auto ExpMask = BitmanipMasks[MaskIdx] & maskTrailingOnes(Width); + bool SHLExpMask = IsSHL; + if (!Mask) { + if (Src.getOpcode() == ISD::AND && isa(Src.getOperand(1))) { + Mask = Src.getConstantOperandVal(1); + Src = Src.getOperand(0); + SHLExpMask = !SHLExpMask; + } + else { + Mask = maskTrailingOnes(Width); + *Mask &= (IsSHL ? *Mask << ShAmt : *Mask >> ShAmt); + } + } + if (SHLExpMask) + ExpMask <<= ShAmt; + if (Mask != ExpMask) + return None; + LHS = RISCVBitmanipPat{Src, (unsigned)ShAmt, IsSHL}; + Optional Mask; + if (Op.getOpcode() == ISD::AND && isa(Op.getOperand(1))) { + Mask = Op.getConstantOperandVal(1); + Op = Op.getOperand(0); + } + if (Op.getOpcode() != ISD::SHL && Op.getOpcode() != ISD::SRL) + return None; + bool IsSHL = Op.getOpcode() == ISD::SHL; + if (!isa(Op.getOperand(1))) + return None; + auto ShAmt = Op.getConstantOperandVal(1); + if (!isPowerOf2_64(ShAmt)) + return None; + static const uint64_t BitmanipMasks[] = { + 0x5555555555555555ULL, 0x3333333333333333ULL, 0x0F0F0F0F0F0F0F0FULL, + 0x00FF00FF00FF00FFULL, 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL, + }; + unsigned MaskIdx = Log2_64(ShAmt); + if (MaskIdx >= array_lengthof(BitmanipMasks)) + return None; + auto Src = Op.getOperand(0); + unsigned Width = Op.getValueType() == MVT::i64 ? 64 : 32; + auto ExpMask = BitmanipMasks[MaskIdx] & maskTrailingOnes(Width); + bool SHLExpMask = IsSHL; + if (!Mask) { + if (Src.getOpcode() == ISD::AND && isa(Src.getOperand(1))) { + Mask = Src.getConstantOperandVal(1); + Src = Src.getOperand(0); + SHLExpMask = !SHLExpMask; + } + else { + Mask = maskTrailingOnes(Width); + *Mask &= (IsSHL ? *Mask << ShAmt : *Mask >> ShAmt); + } + } + if (SHLExpMask) + ExpMask <<= ShAmt; + if (Mask != ExpMask) + return None; + RHS = RISCVBitmanipPat{Src, (unsigned)ShAmt, IsSHL}; + if (LHS && RHS && LHS->formsPairWith(*RHS)) { + SDLoc DL(Op); + return DAG.getNode(RISCVISD::GREVI, DL, VT, LHS->Op, DAG.getTargetConstant(LHS->ShAmt, DL, Subtarget.getXLenVT())); + } + } + auto GORC = SDValue(); + EVT VT = Op.getValueType(); + if (VT == Subtarget.getXLenVT() || (Subtarget.is64Bit() && VT == MVT::i32)) { + Optional Mask; + if (Op.getOpcode() == ISD::AND && isa(Op.getOperand(1))) { + Mask = Op.getConstantOperandVal(1); + Op = Op.getOperand(0); + } + if (Op.getOpcode() != ISD::SHL && Op.getOpcode() != ISD::SRL) + return None; + bool IsSHL = Op.getOpcode() == ISD::SHL; + if (!isa(Op.getOperand(1))) + return None; + auto ShAmt = Op.getConstantOperandVal(1); + if (!isPowerOf2_64(ShAmt)) + return None; + static const uint64_t BitmanipMasks[] = { + 0x5555555555555555ULL, 0x3333333333333333ULL, 0x0F0F0F0F0F0F0F0FULL, + 0x00FF00FF00FF00FFULL, 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL, + }; + unsigned MaskIdx = Log2_64(ShAmt); + if (MaskIdx >= array_lengthof(BitmanipMasks)) + return None; + auto Src = Op.getOperand(0); + unsigned Width = Op.getValueType() == MVT::i64 ? 64 : 32; + auto ExpMask = BitmanipMasks[MaskIdx] & maskTrailingOnes(Width); + bool SHLExpMask = IsSHL; + if (!Mask) { + if (Src.getOpcode() == ISD::AND && isa(Src.getOperand(1))) { + Mask = Src.getConstantOperandVal(1); + Src = Src.getOperand(0); + SHLExpMask = !SHLExpMask; + } + else { + Mask = maskTrailingOnes(Width); + *Mask &= (IsSHL ? *Mask << ShAmt : *Mask >> ShAmt); + } + } + if (SHLExpMask) + ExpMask <<= ShAmt; + if (Mask != ExpMask) + return None; + LHS = RISCVBitmanipPat{Src, (unsigned)ShAmt, IsSHL}; + Optional Mask; + if (Op.getOpcode() == ISD::AND && isa(Op.getOperand(1))) { + Mask = Op.getConstantOperandVal(1); + Op = Op.getOperand(0); + } + if (Op.getOpcode() != ISD::SHL && Op.getOpcode() != ISD::SRL) + return None; + bool IsSHL = Op.getOpcode() == ISD::SHL; + if (!isa(Op.getOperand(1))) + return None; + auto ShAmt = Op.getConstantOperandVal(1); + if (!isPowerOf2_64(ShAmt)) + return None; + static const uint64_t BitmanipMasks[] = { + 0x5555555555555555ULL, 0x3333333333333333ULL, 0x0F0F0F0F0F0F0F0FULL, + 0x00FF00FF00FF00FFULL, 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL, + }; + unsigned MaskIdx = Log2_64(ShAmt); + if (MaskIdx >= array_lengthof(BitmanipMasks)) + return None; + auto Src = Op.getOperand(0); + unsigned Width = Op.getValueType() == MVT::i64 ? 64 : 32; + auto ExpMask = BitmanipMasks[MaskIdx] & maskTrailingOnes(Width); + bool SHLExpMask = IsSHL; + if (!Mask) { + if (Src.getOpcode() == ISD::AND && isa(Src.getOperand(1))) { + Mask = Src.getConstantOperandVal(1); + Src = Src.getOperand(0); + SHLExpMask = !SHLExpMask; + } + else { + Mask = maskTrailingOnes(Width); + *Mask &= (IsSHL ? *Mask << ShAmt : *Mask >> ShAmt); + } + } + if (SHLExpMask) + ExpMask <<= ShAmt; + if (Mask != ExpMask) + return None; + RHS = RISCVBitmanipPat{Src, (unsigned)ShAmt, IsSHL}; + if (LHS && RHS && LHS->formsPairWith(*RHS)) { + SDLoc DL(Op); + return DAG.getNode(RISCVISD::GREVI, DL, VT, LHS->Op, DAG.getTargetConstant(LHS->ShAmt, DL, Subtarget.getXLenVT())); + } + } + auto GORC = SDValue(); + if (GORC) + return GORC; + break; + case RISCVISD::SELECT_CC: { + SDValue LHS = N->getOperand(0); + SDValue RHS = N->getOperand(1); + auto CCVal = static_cast(N->getConstantOperandVal(2)); + APInt Mask = APInt::getBitsSetFrom(LHS.getValueSizeInBits(), 1); + if (ISD::isIntEqualitySetCC(CCVal) && isNullConstant(RHS) && LHS.getOpcode() == ISD::XOR && isOneConstant(LHS.getOperand(1)) && DAG.MaskedValueIsZero(LHS.getOperand(0), Mask)) { + SDLoc DL(N); + CCVal = ISD::getSetCCInverse(CCVal, LHS.getValueType()); + SDValue TargetCC = DAG.getConstant(CCVal, DL, Subtarget.getXLenVT()); + return DAG.getNode(RISCVISD::SELECT_CC, DL, N->getValueType(0), {LHS.getOperand(0), RHS, TargetCC, N->getOperand(3), N->getOperand(4)}); + } + break; + } + case ISD::SETCC: { + SDValue LHS = N->getOperand(0); + SDValue RHS = N->getOperand(1); + if (LHS.getValueType().isScalableVector()) + break; + auto CC = cast(N->getOperand(2))->get(); + APInt Mask = APInt::getBitsSetFrom(LHS.getValueSizeInBits(), 1); + if (isOneConstant(RHS) && ISD::isIntEqualitySetCC(CC) && DAG.MaskedValueIsZero(LHS, Mask)) { + SDLoc DL(N); + SDValue Zero = DAG.getConstant(0, DL, LHS.getValueType()); + CC = ISD::getSetCCInverse(CC, LHS.getValueType()); + return DAG.getSetCC(DL, N->getValueType(0), LHS, Zero, CC); + } + break; + } + case ISD::BR: { + SDValue BrCond = N->getOperand(0); + if (BrCond->getOpcode() != ISD::BRCOND) + break; + SDValue Xor = BrCond->getOperand(1); + if (Xor->getOpcode() != ISD::XOR) + break; + if (auto True = dyn_cast(Xor->getOperand(1))){ + if (True->getSExtValue() != -1) break; + } + else break; + SDValue LoopDecrement = Xor->getOperand(0); + if (LoopDecrement->getOpcode() != ISD::INTRINSIC_W_CHAIN || LoopDecrement->getConstantOperandVal(1) != Intrinsic::loop_decrement) + break; + SDValue BB1 = N->getOperand(1); + SDValue LoopBranch = DAG.getNode(ISD::BRCOND, SDLoc(BrCond), MVT::Other, BrCond->getOperand(0), LoopDecrement, BB1); + SDValue BB2 = BrCond->getOperand(2); + SDValue ElseBranch = DAG.getNode(ISD::BR, SDLoc(N), MVT::Other, LoopBranch, BB2); + return DCI.CombineTo(N, ElseBranch); + } + } + return SDValue(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/ReplaceNodeResults.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/ReplaceNodeResults.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fcb7e257a67ab4aabcfa12a0a4d5afa2da879f4c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/ReplaceNodeResults.cpp @@ -0,0 +1,178 @@ +void RISCVTargetLowering::ReplaceNodeResults(SDNode *N, SmallVectorImpl &Results, SelectionDAG &DAG) const { + SDLoc DL(N); + switch (N->getOpcode()) { + default: + llvm_unreachable("Don't know how to custom type legalize this operation!"); + case ISD::STRICT_FP_TO_SINT: + case ISD::STRICT_FP_TO_UINT: + case ISD::FP_TO_SINT: + case ISD::FP_TO_UINT: { + bool IsStrict = N->isStrictFPOpcode(); + assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() && "Unexpected custom legalisation"); + SDValue Op0 = IsStrict ? N->getOperand(1) : N->getOperand(0); + if (getTypeAction(*DAG.getContext(), Op0.getValueType()) != TargetLowering::TypeSoftenFloat) + return; + RTLIB::Libcall LC; + if (N->getOpcode() == ISD::FP_TO_SINT || N->getOpcode() == ISD::STRICT_FP_TO_SINT) + LC = RTLIB::getFPTOSINT(Op0.getValueType(), N->getValueType(0)); + else + LC = RTLIB::getFPTOUINT(Op0.getValueType(), N->getValueType(0)); + MakeLibCallOptions CallOptions; + EVT OpVT = Op0.getValueType(); + CallOptions.setTypeListBeforeSoften(OpVT, N->getValueType(0), true); + SDValue Chain = IsStrict ? N->getOperand(0) : SDValue(); + SDValue Result; + std::tie(Result, Chain) = makeLibCall(DAG, LC, N->getValueType(0), Op0, CallOptions, DL, Chain); + Results.push_back(Result); + if (IsStrict) + Results.push_back(Chain); + break; + } + case ISD::READCYCLECOUNTER: { + assert(!Subtarget.is64Bit() && "READCYCLECOUNTER only has custom type legalization on riscv32"); + SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); + SDValue RCW = DAG.getNode(RISCVISD::READ_CYCLE_WIDE, DL, VTs, N->getOperand(0)); + Results.push_back( DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, RCW, RCW.getValue(1))); + Results.push_back(RCW.getValue(2)); + break; + } + case ISD::ADD: + case ISD::SUB: + case ISD::MUL: + assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() && "Unexpected custom legalisation"); + if (N->getOperand(1).getOpcode() == ISD::Constant) + return; + Results.push_back(customLegalizeToWOpWithSExt(N, DAG)); + SDLoc DL(N); + SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(0)); + SDValue NewOp1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(1)); + SDValue NewWOp = DAG.getNode(N->getOpcode(), DL, MVT::i64, NewOp0, NewOp1); + SDValue NewRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i64, NewWOp, DAG.getValueType(MVT::i32)); + return DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, NewRes); + break; + case ISD::SHL: + case ISD::SRA: + case ISD::SRL: + assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() && "Unexpected custom legalisation"); + if (N->getOperand(1).getOpcode() == ISD::Constant) + return; + Results.push_back(customLegalizeToWOp(N, DAG)); + SDLoc DL(N); + RISCVISD::NodeType WOpcode = getRISCVWOpcode(N->getOpcode()); + SDValue NewOp0 = DAG.getNode(ExtOpc, DL, MVT::i64, N->getOperand(0)); + SDValue NewOp1 = DAG.getNode(ExtOpc, DL, MVT::i64, N->getOperand(1)); + SDValue NewRes = DAG.getNode(WOpcode, DL, MVT::i64, NewOp0, NewOp1); + return DAG.getNode(ISD::TRUNCATE, DL, N->getValueType(0), NewRes); + break; + case ISD::ROTL: + case ISD::ROTR: + assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() && "Unexpected custom legalisation"); + Results.push_back(customLegalizeToWOp(N, DAG)); + SDLoc DL(N); + RISCVISD::NodeType WOpcode = getRISCVWOpcode(N->getOpcode()); + SDValue NewOp0 = DAG.getNode(ExtOpc, DL, MVT::i64, N->getOperand(0)); + SDValue NewOp1 = DAG.getNode(ExtOpc, DL, MVT::i64, N->getOperand(1)); + SDValue NewRes = DAG.getNode(WOpcode, DL, MVT::i64, NewOp0, NewOp1); + return DAG.getNode(ISD::TRUNCATE, DL, N->getValueType(0), NewRes); + break; + case ISD::SDIV: + case ISD::UDIV: + case ISD::UREM: { + MVT VT = N->getSimpleValueType(0); + assert((VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) && Subtarget.is64Bit() && Subtarget.hasStdExtM() && "Unexpected custom legalisation"); + if (N->getOperand(0).getOpcode() == ISD::Constant || N->getOperand(1).getOpcode() == ISD::Constant) + return; + unsigned ExtOpc = ISD::ANY_EXTEND; + if (VT != MVT::i32) + ExtOpc = N->getOpcode() == ISD::SDIV ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; + Results.push_back(customLegalizeToWOp(N, DAG, ExtOpc)); + SDLoc DL(N); + RISCVISD::NodeType WOpcode = getRISCVWOpcode(N->getOpcode()); + SDValue NewOp0 = DAG.getNode(ExtOpc, DL, MVT::i64, N->getOperand(0)); + SDValue NewOp1 = DAG.getNode(ExtOpc, DL, MVT::i64, N->getOperand(1)); + SDValue NewRes = DAG.getNode(WOpcode, DL, MVT::i64, NewOp0, NewOp1); + return DAG.getNode(ISD::TRUNCATE, DL, N->getValueType(0), NewRes); + break; + } + case ISD::BITCAST: { + assert(((N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() && Subtarget.hasStdExtF()) || (N->getValueType(0) == MVT::i16 && Subtarget.hasStdExtZfh())) && "Unexpected custom legalisation"); + SDValue Op0 = N->getOperand(0); + if (N->getValueType(0) == MVT::i16 && Subtarget.hasStdExtZfh()) { + if (Op0.getValueType() != MVT::f16) + return; + SDValue FPConv = DAG.getNode(RISCVISD::FMV_X_ANYEXTH, DL, Subtarget.getXLenVT(), Op0); + Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, FPConv)); + } + else if (N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() && Subtarget.hasStdExtF()) { + if (Op0.getValueType() != MVT::f32) + return; + SDValue FPConv = DAG.getNode(RISCVISD::FMV_X_ANYEXTW_RV64, DL, MVT::i64, Op0); + Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, FPConv)); + } + break; + } + case RISCVISD::GREVI: + case RISCVISD::GORCI: { + assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() && "Unexpected custom legalisation"); + SDLoc DL(N); + RISCVISD::NodeType WOpcode = getRISCVWOpcode(N->getOpcode()); + SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(0)); + SDValue NewRes = DAG.getNode(WOpcode, DL, MVT::i64, NewOp0, N->getOperand(1)); + Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, NewRes)); + break; + } + case ISD::BSWAP: + case ISD::BITREVERSE: { + assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() && Subtarget.hasStdExtZbp() && "Unexpected custom legalisation"); + SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(0)); + unsigned Imm = N->getOpcode() == ISD::BITREVERSE ? 31 : 24; + SDValue GREVIW = DAG.getNode(RISCVISD::GREVIW, DL, MVT::i64, NewOp0, DAG.getTargetConstant(Imm, DL, Subtarget.getXLenVT())); + Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, GREVIW)); + break; + } + case ISD::FSHL: + case ISD::FSHR: { + assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() && Subtarget.hasStdExtZbt() && "Unexpected custom legalisation"); + SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(0)); + SDValue NewOp1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(1)); + SDValue NewOp2 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(2)); + NewOp2 = DAG.getNode(ISD::AND, DL, MVT::i64, NewOp2, DAG.getConstant(0x1f, DL, MVT::i64)); + unsigned Opc = N->getOpcode() == ISD::FSHL ? RISCVISD::FSLW : RISCVISD::FSRW; + SDValue NewOp = DAG.getNode(Opc, DL, MVT::i64, NewOp0, NewOp1, NewOp2); + Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, NewOp)); + break; + } + case ISD::EXTRACT_VECTOR_ELT: { + SDLoc DL(N); + SDValue Vec = N->getOperand(0); + SDValue Idx = N->getOperand(1); + EVT VecVT = Vec.getValueType(); + assert(!Subtarget.is64Bit() && N->getValueType(0) == MVT::i64 && VecVT.getVectorElementType() == MVT::i64 && "Unexpected EXTRACT_VECTOR_ELT legalization"); + SDValue Slidedown = Vec; + if (!isNullConstant(Idx)) + Slidedown = DAG.getNode(RISCVISD::VSLIDEDOWN, DL, VecVT, DAG.getUNDEF(VecVT), Vec, Idx); + MVT XLenVT = Subtarget.getXLenVT(); + SDValue EltLo = DAG.getNode(RISCVISD::VMV_X_S, DL, XLenVT, Slidedown, Idx); + SDValue ThirtyTwoV = DAG.getNode(RISCVISD::SPLAT_VECTOR_I64, DL, VecVT, DAG.getConstant(32, DL, Subtarget.getXLenVT())); + SDValue LShr32 = DAG.getNode(ISD::SRL, DL, VecVT, Slidedown, ThirtyTwoV); + SDValue EltHi = DAG.getNode(RISCVISD::VMV_X_S, DL, XLenVT, LShr32, Idx); + Results.push_back(DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, EltLo, EltHi)); + break; + } + case ISD::INTRINSIC_WO_CHAIN: { + unsigned IntNo = cast(N->getOperand(0))->getZExtValue(); + switch (IntNo) { + default: + llvm_unreachable("Don't know how to custom type legalize this intrinsic!"); + case Intrinsic::riscv_vmv_x_s: { + EVT VT = N->getValueType(0); + assert((VT == MVT::i8 || VT == MVT::i16 || (Subtarget.is64Bit() && VT == MVT::i32)) && "Unexpected custom legalisation!"); + SDValue Extract = DAG.getNode(RISCVISD::VMV_X_S, DL, Subtarget.getXLenVT(), N->getOperand(1)); + Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, VT, Extract)); + break; + } + } + break; + } + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/TargetLowering.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/TargetLowering.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f36b91ccdbca211f36db98d0815a3bc0c3067159 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/TargetLowering.cpp @@ -0,0 +1,375 @@ +RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, const RISCVSubtarget &STI) : TargetLowering(TM), Subtarget(STI) { + if (Subtarget.isRV32E()) + report_fatal_error("Codegen not yet implemented for RV32E"); + RISCVABI::ABI ABI = Subtarget.getTargetABI(); + assert(ABI != RISCVABI::ABI_Unknown && "Improperly initialised target ABI"); + if ((ABI == RISCVABI::ABI_ILP32F || ABI == RISCVABI::ABI_LP64F) && !Subtarget.hasStdExtF()) { + errs() << "Hard-float 'f' ABI can't be used for a target that doesn't support the F instruction set extension (ignoring target-abi)\n"; + ABI = Subtarget.is64Bit() ? RISCVABI::ABI_LP64 : RISCVABI::ABI_ILP32; + } + else if ((ABI == RISCVABI::ABI_ILP32D || ABI == RISCVABI::ABI_LP64D) && !Subtarget.hasStdExtD()) { + errs() << "Hard-float 'd' ABI can't be used for a target that doesn't support the D instruction set extension (ignoring target-abi)\n"; + ABI = Subtarget.is64Bit() ? RISCVABI::ABI_LP64 : RISCVABI::ABI_ILP32; + } + switch (ABI) { + default: + report_fatal_error("Don't know how to lower this ABI"); + case RISCVABI::ABI_ILP32: + case RISCVABI::ABI_ILP32F: + case RISCVABI::ABI_ILP32D: + case RISCVABI::ABI_LP64: + case RISCVABI::ABI_LP64F: + case RISCVABI::ABI_LP64D: + break; + } + MVT XLenVT = Subtarget.getXLenVT(); + addRegisterClass(XLenVT, &RISCV::GPRRegClass); + if (Subtarget.hasStdExtZfh()) + addRegisterClass(MVT::f16, &RISCV::FPR16RegClass); + if (Subtarget.hasStdExtF()) + addRegisterClass(MVT::f32, &RISCV::FPR32RegClass); + if (Subtarget.hasStdExtD()) + addRegisterClass(MVT::f64, &RISCV::FPR64RegClass); + if (Subtarget.hasStdExtV()) { + addRegisterClass(RISCVVMVTs::vbool64_t, &RISCV::VRRegClass); + addRegisterClass(RISCVVMVTs::vbool32_t, &RISCV::VRRegClass); + addRegisterClass(RISCVVMVTs::vbool16_t, &RISCV::VRRegClass); + addRegisterClass(RISCVVMVTs::vbool8_t, &RISCV::VRRegClass); + addRegisterClass(RISCVVMVTs::vbool4_t, &RISCV::VRRegClass); + addRegisterClass(RISCVVMVTs::vbool2_t, &RISCV::VRRegClass); + addRegisterClass(RISCVVMVTs::vbool1_t, &RISCV::VRRegClass); + addRegisterClass(RISCVVMVTs::vint8mf8_t, &RISCV::VRRegClass); + addRegisterClass(RISCVVMVTs::vint8mf4_t, &RISCV::VRRegClass); + addRegisterClass(RISCVVMVTs::vint8mf2_t, &RISCV::VRRegClass); + addRegisterClass(RISCVVMVTs::vint8m1_t, &RISCV::VRRegClass); + addRegisterClass(RISCVVMVTs::vint8m2_t, &RISCV::VRM2RegClass); + addRegisterClass(RISCVVMVTs::vint8m4_t, &RISCV::VRM4RegClass); + addRegisterClass(RISCVVMVTs::vint8m8_t, &RISCV::VRM8RegClass); + addRegisterClass(RISCVVMVTs::vint16mf4_t, &RISCV::VRRegClass); + addRegisterClass(RISCVVMVTs::vint16mf2_t, &RISCV::VRRegClass); + addRegisterClass(RISCVVMVTs::vint16m1_t, &RISCV::VRRegClass); + addRegisterClass(RISCVVMVTs::vint16m2_t, &RISCV::VRM2RegClass); + addRegisterClass(RISCVVMVTs::vint16m4_t, &RISCV::VRM4RegClass); + addRegisterClass(RISCVVMVTs::vint16m8_t, &RISCV::VRM8RegClass); + addRegisterClass(RISCVVMVTs::vint32mf2_t, &RISCV::VRRegClass); + addRegisterClass(RISCVVMVTs::vint32m1_t, &RISCV::VRRegClass); + addRegisterClass(RISCVVMVTs::vint32m2_t, &RISCV::VRM2RegClass); + addRegisterClass(RISCVVMVTs::vint32m4_t, &RISCV::VRM4RegClass); + addRegisterClass(RISCVVMVTs::vint32m8_t, &RISCV::VRM8RegClass); + addRegisterClass(RISCVVMVTs::vint64m1_t, &RISCV::VRRegClass); + addRegisterClass(RISCVVMVTs::vint64m2_t, &RISCV::VRM2RegClass); + addRegisterClass(RISCVVMVTs::vint64m4_t, &RISCV::VRM4RegClass); + addRegisterClass(RISCVVMVTs::vint64m8_t, &RISCV::VRM8RegClass); + if (Subtarget.hasStdExtZfh()) { + addRegisterClass(RISCVVMVTs::vfloat16mf4_t, &RISCV::VRRegClass); + addRegisterClass(RISCVVMVTs::vfloat16mf2_t, &RISCV::VRRegClass); + addRegisterClass(RISCVVMVTs::vfloat16m1_t, &RISCV::VRRegClass); + addRegisterClass(RISCVVMVTs::vfloat16m2_t, &RISCV::VRM2RegClass); + addRegisterClass(RISCVVMVTs::vfloat16m4_t, &RISCV::VRM4RegClass); + addRegisterClass(RISCVVMVTs::vfloat16m8_t, &RISCV::VRM8RegClass); + } + if (Subtarget.hasStdExtF()) { + addRegisterClass(RISCVVMVTs::vfloat32mf2_t, &RISCV::VRRegClass); + addRegisterClass(RISCVVMVTs::vfloat32m1_t, &RISCV::VRRegClass); + addRegisterClass(RISCVVMVTs::vfloat32m2_t, &RISCV::VRM2RegClass); + addRegisterClass(RISCVVMVTs::vfloat32m4_t, &RISCV::VRM4RegClass); + addRegisterClass(RISCVVMVTs::vfloat32m8_t, &RISCV::VRM8RegClass); + } + if (Subtarget.hasStdExtD()) { + addRegisterClass(RISCVVMVTs::vfloat64m1_t, &RISCV::VRRegClass); + addRegisterClass(RISCVVMVTs::vfloat64m2_t, &RISCV::VRM2RegClass); + addRegisterClass(RISCVVMVTs::vfloat64m4_t, &RISCV::VRM4RegClass); + addRegisterClass(RISCVVMVTs::vfloat64m8_t, &RISCV::VRM8RegClass); + } + } + computeRegisterProperties(STI.getRegisterInfo()); + setStackPointerRegisterToSaveRestore(RISCV::X2); + for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) + setLoadExtAction(N, XLenVT, MVT::i1, Promote); + setOperationAction(ISD::DYNAMIC_STACKALLOC, XLenVT, Expand); + setOperationAction(ISD::BR_JT, MVT::Other, Expand); + setOperationAction(ISD::BR_CC, XLenVT, Expand); + setOperationAction(ISD::SELECT_CC, XLenVT, Expand); + setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); + setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); + setOperationAction(ISD::VASTART, MVT::Other, Custom); + setOperationAction(ISD::VAARG, MVT::Other, Expand); + setOperationAction(ISD::VACOPY, MVT::Other, Expand); + setOperationAction(ISD::VAEND, MVT::Other, Expand); + setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); + if (!Subtarget.hasStdExtZbb()) { + setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); + setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); + } + if (Subtarget.is64Bit()) { + setOperationAction(ISD::ADD, MVT::i32, Custom); + setOperationAction(ISD::SUB, MVT::i32, Custom); + setOperationAction(ISD::SHL, MVT::i32, Custom); + setOperationAction(ISD::SRA, MVT::i32, Custom); + setOperationAction(ISD::SRL, MVT::i32, Custom); + } + if (!Subtarget.hasStdExtM()) { + setOperationAction(ISD::MUL, XLenVT, Expand); + setOperationAction(ISD::MULHS, XLenVT, Expand); + setOperationAction(ISD::MULHU, XLenVT, Expand); + setOperationAction(ISD::SDIV, XLenVT, Expand); + setOperationAction(ISD::UDIV, XLenVT, Expand); + setOperationAction(ISD::SREM, XLenVT, Expand); + setOperationAction(ISD::UREM, XLenVT, Expand); + } + if (Subtarget.is64Bit() && Subtarget.hasStdExtM()) { + setOperationAction(ISD::MUL, MVT::i32, Custom); + setOperationAction(ISD::SDIV, MVT::i8, Custom); + setOperationAction(ISD::UDIV, MVT::i8, Custom); + setOperationAction(ISD::UREM, MVT::i8, Custom); + setOperationAction(ISD::SDIV, MVT::i16, Custom); + setOperationAction(ISD::UDIV, MVT::i16, Custom); + setOperationAction(ISD::UREM, MVT::i16, Custom); + setOperationAction(ISD::SDIV, MVT::i32, Custom); + setOperationAction(ISD::UDIV, MVT::i32, Custom); + setOperationAction(ISD::UREM, MVT::i32, Custom); + } + setOperationAction(ISD::SDIVREM, XLenVT, Expand); + setOperationAction(ISD::UDIVREM, XLenVT, Expand); + setOperationAction(ISD::SMUL_LOHI, XLenVT, Expand); + setOperationAction(ISD::UMUL_LOHI, XLenVT, Expand); + setOperationAction(ISD::SHL_PARTS, XLenVT, Custom); + setOperationAction(ISD::SRL_PARTS, XLenVT, Custom); + setOperationAction(ISD::SRA_PARTS, XLenVT, Custom); + if (Subtarget.hasStdExtZbb() || Subtarget.hasStdExtZbp()) { + if (Subtarget.is64Bit()) { + setOperationAction(ISD::ROTL, MVT::i32, Custom); + setOperationAction(ISD::ROTR, MVT::i32, Custom); + } + } + else { + setOperationAction(ISD::ROTL, XLenVT, Expand); + setOperationAction(ISD::ROTR, XLenVT, Expand); + } + if (Subtarget.hasStdExtZbp()) { + setOperationAction(ISD::BITREVERSE, XLenVT, Custom); + setOperationAction(ISD::BSWAP, XLenVT, Custom); + if (Subtarget.is64Bit()) { + setOperationAction(ISD::BITREVERSE, MVT::i32, Custom); + setOperationAction(ISD::BSWAP, MVT::i32, Custom); + } + } + else { + setOperationAction(ISD::BSWAP, XLenVT, Subtarget.hasStdExtZbb() ? Legal : Expand); + } + if (Subtarget.hasStdExtZbb()) { + setOperationAction(ISD::SMIN, XLenVT, Legal); + setOperationAction(ISD::SMAX, XLenVT, Legal); + setOperationAction(ISD::UMIN, XLenVT, Legal); + setOperationAction(ISD::UMAX, XLenVT, Legal); + } + else { + setOperationAction(ISD::CTTZ, XLenVT, Expand); + setOperationAction(ISD::CTLZ, XLenVT, Expand); + setOperationAction(ISD::CTPOP, XLenVT, Expand); + } + if (Subtarget.hasStdExtZbt()) { + setOperationAction(ISD::FSHL, XLenVT, Legal); + setOperationAction(ISD::FSHR, XLenVT, Legal); + setOperationAction(ISD::SELECT, XLenVT, Legal); + if (Subtarget.is64Bit()) { + setOperationAction(ISD::FSHL, MVT::i32, Custom); + setOperationAction(ISD::FSHR, MVT::i32, Custom); + } + } + else { + setOperationAction(ISD::SELECT, XLenVT, Custom); + } + ISD::CondCode FPCCToExpand[] = {ISD::SETOGT, ISD::SETOGE, ISD::SETONE, ISD::SETUEQ, ISD::SETUGT, ISD::SETUGE, ISD::SETULT, ISD::SETULE, ISD::SETUNE, ISD::SETGT, ISD::SETGE, ISD::SETNE, ISD::SETO, ISD::SETUO}; + ISD::NodeType FPOpToExpand[] = {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM, ISD::FP16_TO_FP, ISD::FP_TO_FP16}; + if (Subtarget.hasStdExtZfh()) + setOperationAction(ISD::BITCAST, MVT::i16, Custom); + if (Subtarget.hasStdExtZfh()) { + setOperationAction(ISD::FMINNUM, MVT::f16, Legal); + setOperationAction(ISD::FMAXNUM, MVT::f16, Legal); + for (auto CC : FPCCToExpand) + setCondCodeAction(CC, MVT::f16, Expand); + setOperationAction(ISD::SELECT_CC, MVT::f16, Expand); + setOperationAction(ISD::SELECT, MVT::f16, Custom); + setOperationAction(ISD::BR_CC, MVT::f16, Expand); + for (auto Op : FPOpToExpand) + setOperationAction(Op, MVT::f16, Expand); + } + if (Subtarget.hasStdExtF()) { + setOperationAction(ISD::FMINNUM, MVT::f32, Legal); + setOperationAction(ISD::FMAXNUM, MVT::f32, Legal); + for (auto CC : FPCCToExpand) + setCondCodeAction(CC, MVT::f32, Expand); + setOperationAction(ISD::SELECT_CC, MVT::f32, Expand); + setOperationAction(ISD::SELECT, MVT::f32, Custom); + setOperationAction(ISD::BR_CC, MVT::f32, Expand); + for (auto Op : FPOpToExpand) + setOperationAction(Op, MVT::f32, Expand); + setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand); + setTruncStoreAction(MVT::f32, MVT::f16, Expand); + } + if (Subtarget.hasStdExtF() && Subtarget.is64Bit()) + setOperationAction(ISD::BITCAST, MVT::i32, Custom); + if (Subtarget.hasStdExtD()) { + setOperationAction(ISD::FMINNUM, MVT::f64, Legal); + setOperationAction(ISD::FMAXNUM, MVT::f64, Legal); + for (auto CC : FPCCToExpand) + setCondCodeAction(CC, MVT::f64, Expand); + setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); + setOperationAction(ISD::SELECT, MVT::f64, Custom); + setOperationAction(ISD::BR_CC, MVT::f64, Expand); + setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand); + setTruncStoreAction(MVT::f64, MVT::f32, Expand); + for (auto Op : FPOpToExpand) + setOperationAction(Op, MVT::f64, Expand); + setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand); + setTruncStoreAction(MVT::f64, MVT::f16, Expand); + } + if (Subtarget.is64Bit()) { + setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); + setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); + setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Custom); + setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Custom); + } + setOperationAction(ISD::GlobalAddress, XLenVT, Custom); + setOperationAction(ISD::BlockAddress, XLenVT, Custom); + setOperationAction(ISD::ConstantPool, XLenVT, Custom); + setOperationAction(ISD::JumpTable, XLenVT, Custom); + setOperationAction(ISD::GlobalTLSAddress, XLenVT, Custom); + setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Subtarget.is64Bit() ? Legal : Custom); + setOperationAction(ISD::TRAP, MVT::Other, Legal); + setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal); + setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); + if (Subtarget.hasPULPExtV2()) { + for (auto VT : {XLenVT.SimpleTy, MVT::v2i16, MVT::v4i8}){ + setOperationAction(ISD::ABS, VT, Legal); + setOperationAction(ISD::SMIN, VT, Legal); + setOperationAction(ISD::UMIN, VT, Legal); + setOperationAction(ISD::SMAX, VT, Legal); + setOperationAction(ISD::UMAX, VT, Legal); + } + setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Legal); + setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal); + setOperationAction(ISD::CTLZ_ZERO_UNDEF, XLenVT, Legal); + setOperationAction(ISD::CTTZ, XLenVT, Legal); + setOperationAction(ISD::CTPOP, XLenVT, Legal); + setOperationAction(ISD::ROTR, XLenVT, Legal); + setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom); + for (auto VT : {MVT::v2i16, MVT::v4i8}){ + setOperationAction(ISD::SPLAT_VECTOR, VT, Legal); + setOperationAction(ISD::VECREDUCE_ADD, VT, Legal); + setOperationPromotedToType(ISD::LOAD, VT, MVT::i32); + setOperationPromotedToType(ISD::STORE, VT, MVT::i32); + setOperationAction(ISD::VSELECT, VT, Expand); + setOperationAction(ISD::MUL, VT, Expand); + setOperationAction(ISD::SDIV, VT, Expand); + setOperationAction(ISD::UDIV, VT, Expand); + setOperationAction(ISD::SREM, VT, Expand); + setOperationAction(ISD::UREM, VT, Expand); + setOperationAction(ISD::ROTR, VT, Expand); + setOperationAction(ISD::ROTL, VT, Expand); + setOperationAction(ISD::BSWAP, VT, Expand); + setOperationAction(ISD::CTTZ, VT, Expand); + setOperationAction(ISD::CTLZ, VT, Expand); + setOperationAction(ISD::CTPOP, VT, Expand); + setOperationAction(ISD::SDIVREM, VT, Expand); + setOperationAction(ISD::UDIVREM, VT, Expand); + setOperationAction(ISD::SMUL_LOHI, VT, Expand); + setOperationAction(ISD::UMUL_LOHI, VT, Expand); + } + setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, MVT::v2i8, Expand); + setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, MVT::v2i8, Expand); + setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i16, MVT::v2i8, Expand); + setTruncStoreAction(MVT::v2i16, MVT::v2i8, Expand); + setTargetDAGCombine(ISD::BR); + setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); + } + if (Subtarget.hasStdExtA()) { + setMaxAtomicSizeInBitsSupported(Subtarget.getXLen()); + setMinCmpXchgSizeInBits(32); + } + else { + setMaxAtomicSizeInBitsSupported(0); + } + if (Subtarget.hasPULPExtV2()) { + setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal); + setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal); + setIndexedLoadAction(ISD::POST_INC, MVT::i32, Legal); + setIndexedLoadAction(ISD::POST_INC, MVT::v2i16, Legal); + setIndexedLoadAction(ISD::POST_INC, MVT::v4i8, Legal); + setIndexedStoreAction(ISD::POST_INC, MVT::i8, Legal); + setIndexedStoreAction(ISD::POST_INC, MVT::i16, Legal); + setIndexedStoreAction(ISD::POST_INC, MVT::i32, Legal); + setIndexedStoreAction(ISD::POST_INC, MVT::v2i16, Legal); + setIndexedStoreAction(ISD::POST_INC, MVT::v4i8, Legal); + } + setBooleanContents(ZeroOrOneBooleanContent); + if (Subtarget.hasStdExtV()) { + setBooleanVectorContents(ZeroOrOneBooleanContent); + setOperationAction(ISD::VSCALE, XLenVT, Custom); + setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i8, Custom); + setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i16, Custom); + setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i8, Custom); + setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i16, Custom); + setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i32, Custom); + setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i32, Custom); + setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom); + if (Subtarget.is64Bit()) { + setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom); + setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom); + } + for (auto VT : MVT::integer_scalable_vector_valuetypes()) { + setOperationAction(ISD::SPLAT_VECTOR, VT, Legal); + setOperationAction(ISD::SMIN, VT, Legal); + setOperationAction(ISD::SMAX, VT, Legal); + setOperationAction(ISD::UMIN, VT, Legal); + setOperationAction(ISD::UMAX, VT, Legal); + setOperationAction(ISD::ROTL, VT, Expand); + setOperationAction(ISD::ROTR, VT, Expand); + if (isTypeLegal(VT)) { + setOperationAction(ISD::ANY_EXTEND, VT, Custom); + setOperationAction(ISD::SIGN_EXTEND, VT, Custom); + setOperationAction(ISD::ZERO_EXTEND, VT, Custom); + setOperationAction(ISD::TRUNCATE, VT, Custom); + setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); + setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); + } + } + if (!Subtarget.is64Bit()) { + setOperationAction(ISD::SPLAT_VECTOR, MVT::i64, Custom); + setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::i64, Custom); + setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::i64, Custom); + } + ISD::CondCode VFPCCToExpand[] = {ISD::SETO, ISD::SETONE, ISD::SETUEQ, ISD::SETUGT, ISD::SETUGE, ISD::SETULT, ISD::SETULE, ISD::SETUO, ISD::SETGT, ISD::SETOGT, ISD::SETGE, ISD::SETOGE, + }; + const auto SetCommonVFPActions = [&](MVT VT) { + setOperationAction(ISD::SPLAT_VECTOR, VT, Legal); + setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); + setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); + for (auto CC : VFPCCToExpand) + setCondCodeAction(CC, VT, Expand); + }; + if (Subtarget.hasStdExtZfh()) { + for (auto VT : {RISCVVMVTs::vfloat16mf4_t, RISCVVMVTs::vfloat16mf2_t, RISCVVMVTs::vfloat16m1_t, RISCVVMVTs::vfloat16m2_t, RISCVVMVTs::vfloat16m4_t, RISCVVMVTs::vfloat16m8_t}) + SetCommonVFPActions(VT); + } + if (Subtarget.hasStdExtF()) { + for (auto VT : {RISCVVMVTs::vfloat32mf2_t, RISCVVMVTs::vfloat32m1_t, RISCVVMVTs::vfloat32m2_t, RISCVVMVTs::vfloat32m4_t, RISCVVMVTs::vfloat32m8_t}) + SetCommonVFPActions(VT); + } + if (Subtarget.hasStdExtD()) { + for (auto VT : {RISCVVMVTs::vfloat64m1_t, RISCVVMVTs::vfloat64m2_t, RISCVVMVTs::vfloat64m4_t, RISCVVMVTs::vfloat64m8_t}) + SetCommonVFPActions(VT); + } + } + const Align FunctionAlignment(Subtarget.hasStdExtC() ? 2 : 4); + setMinFunctionAlignment(FunctionAlignment); + setPrefFunctionAlignment(FunctionAlignment); + setMinimumJumpTableEntries(5); + setJumpIsExpensive(); + setHasMultipleConditionRegisters(); + setTargetDAGCombine(ISD::SETCC); + if (Subtarget.hasStdExtZbp()) { + setTargetDAGCombine(ISD::OR); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/analyzeInputArgs.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/analyzeInputArgs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..48aa3497564c29edb79bfa481025bf26abae26e9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/analyzeInputArgs.cpp @@ -0,0 +1,191 @@ +void RISCVTargetLowering::analyzeInputArgs(MachineFunction &MF, CCState &CCInfo, const SmallVectorImpl &Ins, bool IsRet) const { + unsigned NumArgs = Ins.size(); + FunctionType *FType = MF.getFunction().getFunctionType(); + Optional FirstMaskArgument; + if (Subtarget.hasStdExtV()) { + FirstMaskArgument = None; + for (const auto &ArgIdx : enumerate(Args)) { + MVT ArgVT = ArgIdx.value().VT; + if (ArgVT.isScalableVector() && ArgVT.getVectorElementType().SimpleTy == MVT::i1) { + FirstMaskArgument = ArgIdx.index(); + } + } + } + for (unsigned i = 0; i != NumArgs; ++i) { + MVT ArgVT = Ins[i].VT; + ISD::ArgFlagsTy ArgFlags = Ins[i].Flags; + Type *ArgTy = nullptr; + if (IsRet) { + ArgTy = FType->getReturnType(); + } + else if (Ins[i].isOrigArg()) { + ArgTy = FType->getParamType(Ins[i].getOrigArgIndex()); + } + RISCVABI::ABI ABI = MF.getSubtarget().getTargetABI(); + unsigned XLen = DL.getLargestLegalIntTypeSizeInBits(); + assert(XLen == 32 || XLen == 64); + MVT XLenVT = XLen == 32 ? MVT::i32 : MVT::i64; + if (IsRet && ValNo > 1) { + return true; + } + bool UseGPRForF16_F32 = true; + bool UseGPRForF64 = true; + switch (ABI) { + default: + llvm_unreachable("Unexpected ABI"); + case RISCVABI::ABI_ILP32: + case RISCVABI::ABI_LP64: + break; + case RISCVABI::ABI_ILP32F: + case RISCVABI::ABI_LP64F: + UseGPRForF16_F32 = !IsFixed; + break; + case RISCVABI::ABI_ILP32D: + case RISCVABI::ABI_LP64D: + UseGPRForF16_F32 = !IsFixed; + UseGPRForF64 = !IsFixed; + break; + } + if (State.getFirstUnallocated(ArgFPR32s) == array_lengthof(ArgFPR32s)) { + UseGPRForF16_F32 = true; + UseGPRForF64 = true; + } + if (UseGPRForF16_F32 && (ValVT == MVT::f16 || ValVT == MVT::f32)) { + LocVT = XLenVT; + LocInfo = CCValAssign::BCvt; + } + else if (UseGPRForF64 && XLen == 64 && ValVT == MVT::f64) { + LocVT = MVT::i64; + LocInfo = CCValAssign::BCvt; + } + unsigned TwoXLenInBytes = (2 * XLen) / 8; + if (!IsFixed && ArgFlags.getNonZeroOrigAlign() == TwoXLenInBytes && DL.getTypeAllocSize(OrigTy) == TwoXLenInBytes) { + unsigned RegIdx = State.getFirstUnallocated(ArgGPRs); + if (RegIdx != array_lengthof(ArgGPRs) && RegIdx % 2 == 1) { + State.AllocateReg(ArgGPRs); + } + } + SmallVectorImpl &PendingLocs = State.getPendingLocs(); + SmallVectorImpl &PendingArgFlags = State.getPendingArgFlags(); + assert(PendingLocs.size() == PendingArgFlags.size() && "PendingLocs and PendingArgFlags out of sync"); + if (UseGPRForF64 && XLen == 32 && ValVT == MVT::f64) { + assert(!ArgFlags.isSplit() && PendingLocs.empty() && "Can't lower f64 if it is split"); + Register Reg = State.AllocateReg(ArgGPRs); + LocVT = MVT::i32; + if (!Reg) { + unsigned StackOffset = State.AllocateStack(8, Align(8)); + State.addLoc(CCValAssign::getMem(ValNo, ValVT, StackOffset, LocVT, LocInfo)); + return false; + } + if (!State.AllocateReg(ArgGPRs)) { + State.AllocateStack(4, Align(4)); + } + State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); + return false; + } + if (ArgFlags.isSplit() || !PendingLocs.empty()) { + LocVT = XLenVT; + LocInfo = CCValAssign::Indirect; + PendingLocs.push_back(CCValAssign::getPending(ValNo, ValVT, LocVT, LocInfo)); + PendingArgFlags.push_back(ArgFlags); + if (!ArgFlags.isSplitEnd()) { + return false; + } + } + if (ArgFlags.isSplitEnd() && PendingLocs.size() <= 2) { + assert(PendingLocs.size() == 2 && "Unexpected PendingLocs.size()"); + CCValAssign VA = PendingLocs[0]; + ISD::ArgFlagsTy AF = PendingArgFlags[0]; + PendingLocs.clear(); + PendingArgFlags.clear(); + unsigned XLenInBytes = XLen / 8; + if (Register Reg = State.AllocateReg(ArgGPRs)) { + State.addLoc(CCValAssign::getReg(VA1.getValNo(), VA1.getValVT(), Reg, VA1.getLocVT(), CCValAssign::Full)); + } + else { + Align StackAlign = std::max(Align(XLenInBytes), ArgFlags1.getNonZeroOrigAlign()); + State.addLoc(CCValAssign::getMem(VA1.getValNo(), VA1.getValVT(), State.AllocateStack(XLenInBytes, StackAlign), VA1.getLocVT(), CCValAssign::Full)); + State.addLoc(CCValAssign::getMem(ValNo2, ValVT2, State.AllocateStack(XLenInBytes, Align(XLenInBytes)), LocVT2, CCValAssign::Full)); + return false; + } + if (Register Reg = State.AllocateReg(ArgGPRs)) { + State.addLoc(CCValAssign::getReg(ValNo2, ValVT2, Reg, LocVT2, CCValAssign::Full)); + } + else { + State.addLoc(CCValAssign::getMem(ValNo2, ValVT2, State.AllocateStack(XLenInBytes, Align(XLenInBytes)), LocVT2, CCValAssign::Full)); + } + return false; + } + Register Reg; + if (ValVT == MVT::f16 && !UseGPRForF16_F32) { + Reg = State.AllocateReg(ArgFPR16s); + } + else if (ValVT == MVT::f32 && !UseGPRForF16_F32) { + Reg = State.AllocateReg(ArgFPR32s); + } + else if (ValVT == MVT::f64 && !UseGPRForF64) { + Reg = State.AllocateReg(ArgFPR64s); + } + else if (ValVT.isScalableVector()) { + const TargetRegisterClass *RC = TLI.getRegClassFor(ValVT); + if (RC == &RISCV::VRRegClass) { + if (FirstMaskArgument.hasValue() && ValNo == FirstMaskArgument.getValue()) { + Reg = State.AllocateReg(RISCV::V0); + } + else { + Reg = State.AllocateReg(ArgVRs); + } + } + else if (RC == &RISCV::VRM2RegClass) { + Reg = State.AllocateReg(ArgVRM2s); + } + else if (RC == &RISCV::VRM4RegClass) { + Reg = State.AllocateReg(ArgVRM4s); + } + else if (RC == &RISCV::VRM8RegClass) { + Reg = State.AllocateReg(ArgVRM8s); + } + else { + llvm_unreachable("Unhandled class register for ValueType"); + } + if (!Reg) { + LocInfo = CCValAssign::Indirect; + Reg = State.AllocateReg(ArgGPRs); + LocVT = XLenVT; + } + } + else { + Reg = State.AllocateReg(ArgGPRs); + } + unsigned StackOffset = Reg ? 0 : State.AllocateStack(XLen / 8, Align(XLen / 8)); + if (!PendingLocs.empty()) { + assert(ArgFlags.isSplitEnd() && "Expected ArgFlags.isSplitEnd()"); + assert(PendingLocs.size() > 2 && "Unexpected PendingLocs.size()"); + for (auto &It : PendingLocs) { + if (Reg) + It.convertToReg(Reg); + else + It.convertToMem(StackOffset); + State.addLoc(It); + } + PendingLocs.clear(); + PendingArgFlags.clear(); + return false; + } + assert((!UseGPRForF16_F32 || !UseGPRForF64 || LocVT == XLenVT || (TLI.getSubtarget().hasStdExtV() && ValVT.isScalableVector())) && "Expected an XLenVT or scalable vector types at this stage"); + if (Reg) { + State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); + return false; + } + if (ValVT.isFloatingPoint()) { + LocVT = ValVT; + LocInfo = CCValAssign::Full; + } + State.addLoc(CCValAssign::getMem(ValNo, ValVT, StackOffset, LocVT, LocInfo)); + return false; + if (CC_RISCV(MF.getDataLayout(), ABI, i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo, true, IsRet, ArgTy, *this, FirstMaskArgument)) { + LLVM_DEBUG(dbgs() << "InputArg #" << i << " has unhandled type " << EVT(ArgVT).getEVTString() << '\n'); + llvm_unreachable(nullptr); + } + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/analyzeOutputArgs.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/analyzeOutputArgs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c2c9f60ce6caff0ffd02b84657be3bcebbdb39e5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/analyzeOutputArgs.cpp @@ -0,0 +1,184 @@ +void RISCVTargetLowering::analyzeOutputArgs(MachineFunction &MF, CCState &CCInfo, const SmallVectorImpl &Outs, bool IsRet, CallLoweringInfo *CLI) const { + unsigned NumArgs = Outs.size(); + Optional FirstMaskArgument; + if (Subtarget.hasStdExtV()) { + FirstMaskArgument = None; + for (const auto &ArgIdx : enumerate(Args)) { + MVT ArgVT = ArgIdx.value().VT; + if (ArgVT.isScalableVector() && ArgVT.getVectorElementType().SimpleTy == MVT::i1) { + FirstMaskArgument = ArgIdx.index(); + } + } + } + for (unsigned i = 0; i != NumArgs; i++) { + MVT ArgVT = Outs[i].VT; + ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; + Type *OrigTy = CLI ? CLI->getArgs()[Outs[i].OrigArgIndex].Ty : nullptr; + RISCVABI::ABI ABI = MF.getSubtarget().getTargetABI(); + unsigned XLen = DL.getLargestLegalIntTypeSizeInBits(); + assert(XLen == 32 || XLen == 64); + MVT XLenVT = XLen == 32 ? MVT::i32 : MVT::i64; + if (IsRet && ValNo > 1) { + return true; + } + bool UseGPRForF16_F32 = true; + bool UseGPRForF64 = true; + switch (ABI) { + default: + llvm_unreachable("Unexpected ABI"); + case RISCVABI::ABI_ILP32: + case RISCVABI::ABI_LP64: + break; + case RISCVABI::ABI_ILP32F: + case RISCVABI::ABI_LP64F: + UseGPRForF16_F32 = !IsFixed; + break; + case RISCVABI::ABI_ILP32D: + case RISCVABI::ABI_LP64D: + UseGPRForF16_F32 = !IsFixed; + UseGPRForF64 = !IsFixed; + break; + } + if (State.getFirstUnallocated(ArgFPR32s) == array_lengthof(ArgFPR32s)) { + UseGPRForF16_F32 = true; + UseGPRForF64 = true; + } + if (UseGPRForF16_F32 && (ValVT == MVT::f16 || ValVT == MVT::f32)) { + LocVT = XLenVT; + LocInfo = CCValAssign::BCvt; + } + else if (UseGPRForF64 && XLen == 64 && ValVT == MVT::f64) { + LocVT = MVT::i64; + LocInfo = CCValAssign::BCvt; + } + unsigned TwoXLenInBytes = (2 * XLen) / 8; + if (!IsFixed && ArgFlags.getNonZeroOrigAlign() == TwoXLenInBytes && DL.getTypeAllocSize(OrigTy) == TwoXLenInBytes) { + unsigned RegIdx = State.getFirstUnallocated(ArgGPRs); + if (RegIdx != array_lengthof(ArgGPRs) && RegIdx % 2 == 1) { + State.AllocateReg(ArgGPRs); + } + } + SmallVectorImpl &PendingLocs = State.getPendingLocs(); + SmallVectorImpl &PendingArgFlags = State.getPendingArgFlags(); + assert(PendingLocs.size() == PendingArgFlags.size() && "PendingLocs and PendingArgFlags out of sync"); + if (UseGPRForF64 && XLen == 32 && ValVT == MVT::f64) { + assert(!ArgFlags.isSplit() && PendingLocs.empty() && "Can't lower f64 if it is split"); + Register Reg = State.AllocateReg(ArgGPRs); + LocVT = MVT::i32; + if (!Reg) { + unsigned StackOffset = State.AllocateStack(8, Align(8)); + State.addLoc(CCValAssign::getMem(ValNo, ValVT, StackOffset, LocVT, LocInfo)); + return false; + } + if (!State.AllocateReg(ArgGPRs)) { + State.AllocateStack(4, Align(4)); + } + State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); + return false; + } + if (ArgFlags.isSplit() || !PendingLocs.empty()) { + LocVT = XLenVT; + LocInfo = CCValAssign::Indirect; + PendingLocs.push_back(CCValAssign::getPending(ValNo, ValVT, LocVT, LocInfo)); + PendingArgFlags.push_back(ArgFlags); + if (!ArgFlags.isSplitEnd()) { + return false; + } + } + if (ArgFlags.isSplitEnd() && PendingLocs.size() <= 2) { + assert(PendingLocs.size() == 2 && "Unexpected PendingLocs.size()"); + CCValAssign VA = PendingLocs[0]; + ISD::ArgFlagsTy AF = PendingArgFlags[0]; + PendingLocs.clear(); + PendingArgFlags.clear(); + unsigned XLenInBytes = XLen / 8; + if (Register Reg = State.AllocateReg(ArgGPRs)) { + State.addLoc(CCValAssign::getReg(VA1.getValNo(), VA1.getValVT(), Reg, VA1.getLocVT(), CCValAssign::Full)); + } + else { + Align StackAlign = std::max(Align(XLenInBytes), ArgFlags1.getNonZeroOrigAlign()); + State.addLoc(CCValAssign::getMem(VA1.getValNo(), VA1.getValVT(), State.AllocateStack(XLenInBytes, StackAlign), VA1.getLocVT(), CCValAssign::Full)); + State.addLoc(CCValAssign::getMem(ValNo2, ValVT2, State.AllocateStack(XLenInBytes, Align(XLenInBytes)), LocVT2, CCValAssign::Full)); + return false; + } + if (Register Reg = State.AllocateReg(ArgGPRs)) { + State.addLoc(CCValAssign::getReg(ValNo2, ValVT2, Reg, LocVT2, CCValAssign::Full)); + } + else { + State.addLoc(CCValAssign::getMem(ValNo2, ValVT2, State.AllocateStack(XLenInBytes, Align(XLenInBytes)), LocVT2, CCValAssign::Full)); + } + return false; + } + Register Reg; + if (ValVT == MVT::f16 && !UseGPRForF16_F32) { + Reg = State.AllocateReg(ArgFPR16s); + } + else if (ValVT == MVT::f32 && !UseGPRForF16_F32) { + Reg = State.AllocateReg(ArgFPR32s); + } + else if (ValVT == MVT::f64 && !UseGPRForF64) { + Reg = State.AllocateReg(ArgFPR64s); + } + else if (ValVT.isScalableVector()) { + const TargetRegisterClass *RC = TLI.getRegClassFor(ValVT); + if (RC == &RISCV::VRRegClass) { + if (FirstMaskArgument.hasValue() && ValNo == FirstMaskArgument.getValue()) { + Reg = State.AllocateReg(RISCV::V0); + } + else { + Reg = State.AllocateReg(ArgVRs); + } + } + else if (RC == &RISCV::VRM2RegClass) { + Reg = State.AllocateReg(ArgVRM2s); + } + else if (RC == &RISCV::VRM4RegClass) { + Reg = State.AllocateReg(ArgVRM4s); + } + else if (RC == &RISCV::VRM8RegClass) { + Reg = State.AllocateReg(ArgVRM8s); + } + else { + llvm_unreachable("Unhandled class register for ValueType"); + } + if (!Reg) { + LocInfo = CCValAssign::Indirect; + Reg = State.AllocateReg(ArgGPRs); + LocVT = XLenVT; + } + } + else { + Reg = State.AllocateReg(ArgGPRs); + } + unsigned StackOffset = Reg ? 0 : State.AllocateStack(XLen / 8, Align(XLen / 8)); + if (!PendingLocs.empty()) { + assert(ArgFlags.isSplitEnd() && "Expected ArgFlags.isSplitEnd()"); + assert(PendingLocs.size() > 2 && "Unexpected PendingLocs.size()"); + for (auto &It : PendingLocs) { + if (Reg) + It.convertToReg(Reg); + else + It.convertToMem(StackOffset); + State.addLoc(It); + } + PendingLocs.clear(); + PendingArgFlags.clear(); + return false; + } + assert((!UseGPRForF16_F32 || !UseGPRForF64 || LocVT == XLenVT || (TLI.getSubtarget().hasStdExtV() && ValVT.isScalableVector())) && "Expected an XLenVT or scalable vector types at this stage"); + if (Reg) { + State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); + return false; + } + if (ValVT.isFloatingPoint()) { + LocVT = ValVT; + LocInfo = CCValAssign::Full; + } + State.addLoc(CCValAssign::getMem(ValNo, ValVT, StackOffset, LocVT, LocInfo)); + return false; + if (CC_RISCV(MF.getDataLayout(), ABI, i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo, Outs[i].IsFixed, IsRet, OrigTy, *this, FirstMaskArgument)) { + LLVM_DEBUG(dbgs() << "OutputArg #" << i << " has unhandled type " << EVT(ArgVT).getEVTString() << "\n"); + llvm_unreachable(nullptr); + } + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/computeKnownBitsForTargetNode.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/computeKnownBitsForTargetNode.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cb60f440f2c3d49c6bd08e043910840c8c738be3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/computeKnownBitsForTargetNode.cpp @@ -0,0 +1,27 @@ +void RISCVTargetLowering::computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const { + KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0); + APInt KnownZero2; + APInt KnownOne2; + unsigned BitWidth = Known.getBitWidth(); + unsigned Opc = Op.getOpcode(); + EVT VT = Op.getValueType(); + assert((Opc >= ISD::BUILTIN_OP_END || Opc == ISD::INTRINSIC_WO_CHAIN || Opc == ISD::INTRINSIC_W_CHAIN || Opc == ISD::INTRINSIC_VOID) && "Should use MaskedValueIsZero if you don't know whether Op is a target node!"); + Known.resetAll(); + if (Op.getOpcode() == RISCVISD::REMUW) { + KnownBits Known2; + Known = DAG.computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1); + Known2 = DAG.computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1); + Known = KnownBits::urem(Known.trunc(32), Known2.trunc(32)); + Known = Known.sext(BitWidth); + } + if (Op.getOpcode() == RISCVISD::DIVUW) { + KnownBits Known2; + Known = DAG.computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1); + Known2 = DAG.computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1); + Known = KnownBits::udiv(Known.trunc(32), Known2.trunc(32)); + Known = Known.sext(BitWidth); + } + if (Op.getOpcode() == RISCVISD::READ_VLENB) { + Known.Zero.setLowBits(3); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/convertSelectOfConstantsToMath.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/convertSelectOfConstantsToMath.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c1bfd4ff9c0142d140fa2d0204586a61289d84a5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/convertSelectOfConstantsToMath.cpp @@ -0,0 +1,3 @@ +bool convertSelectOfConstantsToMath(EVT VT) const override { + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/convertSetCCLogicToBitwiseLogic.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/convertSetCCLogicToBitwiseLogic.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e3721be5b16c34bcd975aeae2f4dce484d080226 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/convertSetCCLogicToBitwiseLogic.cpp @@ -0,0 +1,3 @@ +bool convertSetCCLogicToBitwiseLogic(EVT VT) const override { + return VT.isScalarInteger(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/decomposeMulByConstant.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/decomposeMulByConstant.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8a5c7fcf9043b0cab2a9beb5f9f97e9405099052 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/decomposeMulByConstant.cpp @@ -0,0 +1,24 @@ +bool RISCVTargetLowering::decomposeMulByConstant(LLVMContext &Context, EVT VT, SDValue C) const { + if (!VT.isScalarInteger()) { + return false; + } + if (Subtarget.hasStdExtM() && VT.getSizeInBits() > Subtarget.getXLen()) { + return false; + } + if (auto *ConstNode = dyn_cast(C.getNode())) { + const APInt &Imm = ConstNode->getAPIntValue(); + if ((Imm + 1).isPowerOf2() || (Imm - 1).isPowerOf2() || (1 - Imm).isPowerOf2() || (-1 - Imm).isPowerOf2()) { + return true; + } + if (Subtarget.hasStdExtM() && VT.getSizeInBits() >= Subtarget.getXLen()) { + return false; + } + if (!Imm.isSignedIntN(12) && Imm.countTrailingZeros() < 12) { + APInt ImmS = Imm.ashr(Imm.countTrailingZeros()); + if ((ImmS + 1).isPowerOf2() || (ImmS - 1).isPowerOf2() || (1 - ImmS).isPowerOf2()) { + return true; + } + } + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/emitLeadingFence.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/emitLeadingFence.cpp new file mode 100644 index 0000000000000000000000000000000000000000..509c7a0e3f0b5b7d1c9ddc616ed049a5f0648f15 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/emitLeadingFence.cpp @@ -0,0 +1,9 @@ +Instruction *RISCVTargetLowering::emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst, AtomicOrdering Ord) const { + if (isa(Inst) && Ord == AtomicOrdering::SequentiallyConsistent) { + return Builder.CreateFence(Ord); + } + if (isa(Inst) && isReleaseOrStronger(Ord)) { + return Builder.CreateFence(AtomicOrdering::Release); + } + return nullptr; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/emitMaskedAtomicCmpXchgIntrinsic.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/emitMaskedAtomicCmpXchgIntrinsic.cpp new file mode 100644 index 0000000000000000000000000000000000000000..abfa250a03dc885e387fa3aca22d89acdc995376 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/emitMaskedAtomicCmpXchgIntrinsic.cpp @@ -0,0 +1,18 @@ +Value *RISCVTargetLowering::emitMaskedAtomicCmpXchgIntrinsic(IRBuilder<> &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const { + unsigned XLen = Subtarget.getXLen(); + Value *Ordering = Builder.getIntN(XLen, static_cast(Ord)); + Intrinsic::ID CmpXchgIntrID = Intrinsic::riscv_masked_cmpxchg_i32; + if (XLen == 64) { + CmpVal = Builder.CreateSExt(CmpVal, Builder.getInt64Ty()); + NewVal = Builder.CreateSExt(NewVal, Builder.getInt64Ty()); + Mask = Builder.CreateSExt(Mask, Builder.getInt64Ty()); + CmpXchgIntrID = Intrinsic::riscv_masked_cmpxchg_i64; + } + Type *Tys[] = {AlignedAddr->getType()}; + Function *MaskedCmpXchg = Intrinsic::getDeclaration(CI->getModule(), CmpXchgIntrID, Tys); + Value *Result = Builder.CreateCall(MaskedCmpXchg, {AlignedAddr, CmpVal, NewVal, Mask, Ordering}); + if (XLen == 64) { + Result = Builder.CreateTrunc(Result, Builder.getInt32Ty()); + } + return Result; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/emitMaskedAtomicRMWIntrinsic.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/emitMaskedAtomicRMWIntrinsic.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c3ee2d975b835746f82a0da490b18a4385d0a50f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/emitMaskedAtomicRMWIntrinsic.cpp @@ -0,0 +1,70 @@ +Value *RISCVTargetLowering::emitMaskedAtomicRMWIntrinsic(IRBuilder<> &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const { + unsigned XLen = Subtarget.getXLen(); + Value *Ordering = Builder.getIntN(XLen, static_cast(AI->getOrdering())); + Type *Tys[] = {AlignedAddr->getType()}; + Function *LrwOpScwLoop = Intrinsic::getDeclaration(AI->getModule(), getIntrinsicForMaskedAtomicRMWBinOp(XLen, AI->getOperation()), Tys); + if (XLen == 32) { + switch (BinOp) { + default: + llvm_unreachable("Unexpected AtomicRMW BinOp"); + case AtomicRMWInst::Xchg: + return Intrinsic::riscv_masked_atomicrmw_xchg_i32; + case AtomicRMWInst::Add: + return Intrinsic::riscv_masked_atomicrmw_add_i32; + case AtomicRMWInst::Sub: + return Intrinsic::riscv_masked_atomicrmw_sub_i32; + case AtomicRMWInst::Nand: + return Intrinsic::riscv_masked_atomicrmw_nand_i32; + case AtomicRMWInst::Max: + return Intrinsic::riscv_masked_atomicrmw_max_i32; + case AtomicRMWInst::Min: + return Intrinsic::riscv_masked_atomicrmw_min_i32; + case AtomicRMWInst::UMax: + return Intrinsic::riscv_masked_atomicrmw_umax_i32; + case AtomicRMWInst::UMin: + return Intrinsic::riscv_masked_atomicrmw_umin_i32; + } + } + if (XLen == 64) { + switch (BinOp) { + default: + llvm_unreachable("Unexpected AtomicRMW BinOp"); + case AtomicRMWInst::Xchg: + return Intrinsic::riscv_masked_atomicrmw_xchg_i64; + case AtomicRMWInst::Add: + return Intrinsic::riscv_masked_atomicrmw_add_i64; + case AtomicRMWInst::Sub: + return Intrinsic::riscv_masked_atomicrmw_sub_i64; + case AtomicRMWInst::Nand: + return Intrinsic::riscv_masked_atomicrmw_nand_i64; + case AtomicRMWInst::Max: + return Intrinsic::riscv_masked_atomicrmw_max_i64; + case AtomicRMWInst::Min: + return Intrinsic::riscv_masked_atomicrmw_min_i64; + case AtomicRMWInst::UMax: + return Intrinsic::riscv_masked_atomicrmw_umax_i64; + case AtomicRMWInst::UMin: + return Intrinsic::riscv_masked_atomicrmw_umin_i64; + } + } + llvm_unreachable("Unexpected XLen\n"); + if (XLen == 64) { + Incr = Builder.CreateSExt(Incr, Builder.getInt64Ty()); + Mask = Builder.CreateSExt(Mask, Builder.getInt64Ty()); + ShiftAmt = Builder.CreateSExt(ShiftAmt, Builder.getInt64Ty()); + } + Value *Result; + if (AI->getOperation() == AtomicRMWInst::Min || AI->getOperation() == AtomicRMWInst::Max) { + const DataLayout &DL = AI->getModule()->getDataLayout(); + unsigned ValWidth = DL.getTypeStoreSizeInBits(AI->getValOperand()->getType()); + Value *SextShamt = Builder.CreateSub(Builder.getIntN(XLen, XLen - ValWidth), ShiftAmt); + Result = Builder.CreateCall(LrwOpScwLoop, {AlignedAddr, Incr, Mask, SextShamt, Ordering}); + } + else { + Result = Builder.CreateCall(LrwOpScwLoop, {AlignedAddr, Incr, Mask, Ordering}); + } + if (XLen == 64) { + Result = Builder.CreateTrunc(Result, Builder.getInt32Ty()); + } + return Result; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/emitTrailingFence.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/emitTrailingFence.cpp new file mode 100644 index 0000000000000000000000000000000000000000..787eeb8fc972fa00907f61c8d38b99dc41fd1fb5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/emitTrailingFence.cpp @@ -0,0 +1,8 @@ +Instruction *RISCVTargetLowering::emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst, AtomicOrdering Ord) const { + if (isAcquireOrStronger(Ord)) { + if (isa(Inst)) { + return Builder.CreateFence(AtomicOrdering::Acquire); + } + } + return nullptr; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/getAddr.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/getAddr.cpp new file mode 100644 index 0000000000000000000000000000000000000000..45b896e36009000a6701f992a091e5a60a139227 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/getAddr.cpp @@ -0,0 +1,25 @@ +template SDValue RISCVTargetLowering::getAddr(NodeTy *N, SelectionDAG &DAG, bool IsLocal) const { + SDLoc DL(N); + EVT Ty = getPointerTy(DAG.getDataLayout()); + if (isPositionIndependent()) { + SDValue Addr = getTargetNode(N, DL, Ty, DAG, 0); + if (IsLocal) { + return SDValue(DAG.getMachineNode(RISCV::PseudoLLA, DL, Ty, Addr), 0); + } + return SDValue(DAG.getMachineNode(RISCV::PseudoLA, DL, Ty, Addr), 0); + } + switch (getTargetMachine().getCodeModel()) { + default: + report_fatal_error("Unsupported code model for lowering"); + case CodeModel::Small: { + SDValue AddrHi = getTargetNode(N, DL, Ty, DAG, RISCVII::MO_HI); + SDValue AddrLo = getTargetNode(N, DL, Ty, DAG, RISCVII::MO_LO); + SDValue MNHi = SDValue(DAG.getMachineNode(RISCV::LUI, DL, Ty, AddrHi), 0); + return SDValue(DAG.getMachineNode(RISCV::ADDI, DL, Ty, MNHi, AddrLo), 0); + } + case CodeModel::Medium: { + SDValue Addr = getTargetNode(N, DL, Ty, DAG, 0); + return SDValue(DAG.getMachineNode(RISCV::PseudoLLA, DL, Ty, Addr), 0); + } + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/getConstraintType.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/getConstraintType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..915131641ca5dd4cc6c2356db00e6fd67b5b82b8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/getConstraintType.cpp @@ -0,0 +1,17 @@ +RISCVTargetLowering::ConstraintType RISCVTargetLowering::getConstraintType(StringRef Constraint) const { + if (Constraint.size() == 1) { + switch (Constraint[0]) { + default: + break; + case 'f': + return C_RegisterClass; + case 'I': + case 'J': + case 'K': + return C_Immediate; + case 'A': + return C_Memory; + } + } + return TargetLowering::getConstraintType(Constraint); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/getDynamicTLSAddr.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/getDynamicTLSAddr.cpp new file mode 100644 index 0000000000000000000000000000000000000000..46ed5ac12e9f62e6e019a25294f0fc96f25d8f4d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/getDynamicTLSAddr.cpp @@ -0,0 +1,16 @@ +SDValue RISCVTargetLowering::getDynamicTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG) const { + SDLoc DL(N); + EVT Ty = getPointerTy(DAG.getDataLayout()); + IntegerType *CallTy = Type::getIntNTy(*DAG.getContext(), Ty.getSizeInBits()); + const GlobalValue *GV = N->getGlobal(); + SDValue Addr = DAG.getTargetGlobalAddress(GV, DL, Ty, 0, 0); + SDValue Load = SDValue(DAG.getMachineNode(RISCV::PseudoLA_TLS_GD, DL, Ty, Addr), 0); + ArgListTy Args; + ArgListEntry Entry; + Entry.Node = Load; + Entry.Ty = CallTy; + Args.push_back(Entry); + TargetLowering::CallLoweringInfo CLI(DAG); + CLI.setDebugLoc(DL).setChain(DAG.getEntryNode()).setLibCallee(CallingConv::C, CallTy, DAG.getExternalSymbol("__tls_get_addr", Ty), std::move(Args)); + return LowerCallTo(CLI).first; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/getExceptionPointerRegister.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/getExceptionPointerRegister.cpp new file mode 100644 index 0000000000000000000000000000000000000000..eb02e54d876a19eac0a9f798a894bdb8ad094aa6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/getExceptionPointerRegister.cpp @@ -0,0 +1,3 @@ +Register RISCVTargetLowering::getExceptionPointerRegister(const Constant *PersonalityFn) const { + return RISCV::X10; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/getExceptionSelectorRegister.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/getExceptionSelectorRegister.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d21248ae6b5a38fab11aef82cb88fdc8ad6f6150 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/getExceptionSelectorRegister.cpp @@ -0,0 +1,3 @@ +Register RISCVTargetLowering::getExceptionSelectorRegister(const Constant *PersonalityFn) const { + return RISCV::X11; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/getExtendForAtomicCmpSwapArg.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/getExtendForAtomicCmpSwapArg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4fbe6c054b9796da3f9e9476976964f562a3e55a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/getExtendForAtomicCmpSwapArg.cpp @@ -0,0 +1,3 @@ +ISD::NodeType getExtendForAtomicCmpSwapArg() const override { + return ISD::SIGN_EXTEND; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/getExtendForAtomicOps.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/getExtendForAtomicOps.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8115491be720522f593d5b6c220ecf0659c42759 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/getExtendForAtomicOps.cpp @@ -0,0 +1,3 @@ +ISD::NodeType getExtendForAtomicOps() const override { + return ISD::SIGN_EXTEND; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/getInlineAsmMemConstraint.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/getInlineAsmMemConstraint.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b639b42ebb4b943ce1428b84bd6d6574cc675104 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/getInlineAsmMemConstraint.cpp @@ -0,0 +1,11 @@ +unsigned RISCVTargetLowering::getInlineAsmMemConstraint(StringRef ConstraintCode) const { + if (ConstraintCode.size() == 1) { + switch (ConstraintCode[0]) { + case 'A': + return InlineAsm::Constraint_A; + default: + break; + } + } + return TargetLowering::getInlineAsmMemConstraint(ConstraintCode); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/getRegForInlineAsmConstraint.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/getRegForInlineAsmConstraint.cpp new file mode 100644 index 0000000000000000000000000000000000000000..700e248e4992dd8745c5e6bbf6198c37e1d39e67 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/getRegForInlineAsmConstraint.cpp @@ -0,0 +1,349 @@ +std::pair RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const { + if (Constraint.size() == 1) { + if (Constraint[0] == 'r') { + return std::make_pair(0U, &RISCV::GPRRegClass); + } + if (Constraint[0] == 'f') { + if (Subtarget.hasStdExtF()) { + if (VT == MVT::f32) { + return std::make_pair(0U, &RISCV::FPR32RegClass); + } + } + if (Subtarget.hasStdExtD()) { + if (VT == MVT::f64) { + return std::make_pair(0U, &RISCV::FPR64RegClass); + } + } + if (Subtarget.hasStdExtZfh()) { + if (VT == MVT::f16) { + return std::make_pair(0U, &RISCV::FPR16RegClass); + } + } + if (Subtarget.hasStdExtXSmallfloat()) { + if (VT == MVT::v2f32) { + return std::make_pair(0U, &RISCV::FPR64RegClass); + } + if (VT == MVT::v4f16) { + return std::make_pair(0U, &RISCV::FPR64RegClass); + } + if (VT == MVT::v4bf16) { + return std::make_pair(0U, &RISCV::FPR64RegClass); + } + if (VT == MVT::v4i16) { + return std::make_pair(0U, &RISCV::FPR64RegClass); + } + if (VT == MVT::v8i8) { + return std::make_pair(0U, &RISCV::FPR64RegClass); + } + } + } + } + unsigned XRegFromAlias = RISCV::NoRegister; + if (Constraint.lower() == "{zero}") { + XRegFromAlias = RISCV::X0; + } + if (Constraint.lower() == "{ra}") { + XRegFromAlias = RISCV::X1; + } + if (Constraint.lower() == "{sp}") { + XRegFromAlias = RISCV::X2; + } + if (Constraint.lower() == "{gp}") { + XRegFromAlias = RISCV::X3; + } + if (Constraint.lower() == "{tp}") { + XRegFromAlias = RISCV::X4; + } + if (Constraint.lower() == "{t0}") { + XRegFromAlias = RISCV::X5; + } + if (Constraint.lower() == "{t1}") { + XRegFromAlias = RISCV::X6; + } + if (Constraint.lower() == "{t2}") { + XRegFromAlias = RISCV::X7; + } + if (Constraint.lower() == "{s0}") { + XRegFromAlias = RISCV::X8; + } + if (Constraint.lower() == "{fp}") { + XRegFromAlias = RISCV::X8; + } + if (Constraint.lower() == "{s1}") { + XRegFromAlias = RISCV::X9; + } + if (Constraint.lower() == "{a0}") { + XRegFromAlias = RISCV::X10; + } + if (Constraint.lower() == "{a1}") { + XRegFromAlias = RISCV::X11; + } + if (Constraint.lower() == "{a2}") { + XRegFromAlias = RISCV::X12; + } + if (Constraint.lower() == "{a3}") { + XRegFromAlias = RISCV::X13; + } + if (Constraint.lower() == "{a4}") { + XRegFromAlias = RISCV::X14; + } + if (Constraint.lower() == "{a5}") { + XRegFromAlias = RISCV::X15; + } + if (Constraint.lower() == "{a6}") { + XRegFromAlias = RISCV::X16; + } + if (Constraint.lower() == "{a7}") { + XRegFromAlias = RISCV::X17; + } + if (Constraint.lower() == "{s2}") { + XRegFromAlias = RISCV::X18; + } + if (Constraint.lower() == "{s3}") { + XRegFromAlias = RISCV::X19; + } + if (Constraint.lower() == "{s4}") { + XRegFromAlias = RISCV::X20; + } + if (Constraint.lower() == "{s5}") { + XRegFromAlias = RISCV::X21; + } + if (Constraint.lower() == "{s6}") { + XRegFromAlias = RISCV::X22; + } + if (Constraint.lower() == "{s7}") { + XRegFromAlias = RISCV::X23; + } + if (Constraint.lower() == "{s8}") { + XRegFromAlias = RISCV::X24; + } + if (Constraint.lower() == "{s9}") { + XRegFromAlias = RISCV::X25; + } + if (Constraint.lower() == "{s10}") { + XRegFromAlias = RISCV::X26; + } + if (Constraint.lower() == "{s11}") { + XRegFromAlias = RISCV::X27; + } + if (Constraint.lower() == "{t3}") { + XRegFromAlias = RISCV::X28; + } + if (Constraint.lower() == "{t4}") { + XRegFromAlias = RISCV::X29; + } + if (Constraint.lower() == "{t5}") { + XRegFromAlias = RISCV::X30; + } + if (Constraint.lower() == "{t6}") { + XRegFromAlias = RISCV::X31; + } + if (XRegFromAlias != RISCV::NoRegister) { + return std::make_pair(XRegFromAlias, &RISCV::GPRRegClass); + } + if (Subtarget.hasStdExtF()) { + unsigned FReg = RISCV::NoRegister; + if (Constraint.lower() == "{f0}") { + FReg = RISCV::F0_F; + } + if (Constraint.lower() == "{ft0}") { + FReg = RISCV::F0_F; + } + if (Constraint.lower() == "{f1}") { + FReg = RISCV::F1_F; + } + if (Constraint.lower() == "{ft1}") { + FReg = RISCV::F1_F; + } + if (Constraint.lower() == "{f2}") { + FReg = RISCV::F2_F; + } + if (Constraint.lower() == "{ft2}") { + FReg = RISCV::F2_F; + } + if (Constraint.lower() == "{f3}") { + FReg = RISCV::F3_F; + } + if (Constraint.lower() == "{ft3}") { + FReg = RISCV::F3_F; + } + if (Constraint.lower() == "{f4}") { + FReg = RISCV::F4_F; + } + if (Constraint.lower() == "{ft4}") { + FReg = RISCV::F4_F; + } + if (Constraint.lower() == "{f5}") { + FReg = RISCV::F5_F; + } + if (Constraint.lower() == "{ft5}") { + FReg = RISCV::F5_F; + } + if (Constraint.lower() == "{f6}") { + FReg = RISCV::F6_F; + } + if (Constraint.lower() == "{ft6}") { + FReg = RISCV::F6_F; + } + if (Constraint.lower() == "{f7}") { + FReg = RISCV::F7_F; + } + if (Constraint.lower() == "{ft7}") { + FReg = RISCV::F7_F; + } + if (Constraint.lower() == "{f8}") { + FReg = RISCV::F8_F; + } + if (Constraint.lower() == "{ft8}") { + FReg = RISCV::F8_F; + } + if (Constraint.lower() == "{f9}") { + FReg = RISCV::F9_F; + } + if (Constraint.lower() == "{ft9}") { + FReg = RISCV::F9_F; + } + if (Constraint.lower() == "{f10}") { + FReg = RISCV::F10_F; + } + if (Constraint.lower() == "{ft10}") { + FReg = RISCV::F10_F; + } + if (Constraint.lower() == "{f11}") { + FReg = RISCV::F11_F; + } + if (Constraint.lower() == "{ft11}") { + FReg = RISCV::F11_F; + } + if (Constraint.lower() == "{f12}") { + FReg = RISCV::F12_F; + } + if (Constraint.lower() == "{ft12}") { + FReg = RISCV::F12_F; + } + if (Constraint.lower() == "{f13}") { + FReg = RISCV::F13_F; + } + if (Constraint.lower() == "{ft13}") { + FReg = RISCV::F13_F; + } + if (Constraint.lower() == "{f14}") { + FReg = RISCV::F14_F; + } + if (Constraint.lower() == "{ft14}") { + FReg = RISCV::F14_F; + } + if (Constraint.lower() == "{f15}") { + FReg = RISCV::F15_F; + } + if (Constraint.lower() == "{ft15}") { + FReg = RISCV::F15_F; + } + if (Constraint.lower() == "{f16}") { + FReg = RISCV::F16_F; + } + if (Constraint.lower() == "{ft16}") { + FReg = RISCV::F16_F; + } + if (Constraint.lower() == "{f17}") { + FReg = RISCV::F17_F; + } + if (Constraint.lower() == "{ft17}") { + FReg = RISCV::F17_F; + } + if (Constraint.lower() == "{f18}") { + FReg = RISCV::F18_F; + } + if (Constraint.lower() == "{ft18}") { + FReg = RISCV::F18_F; + } + if (Constraint.lower() == "{f19}") { + FReg = RISCV::F19_F; + } + if (Constraint.lower() == "{ft19}") { + FReg = RISCV::F19_F; + } + if (Constraint.lower() == "{f20}") { + FReg = RISCV::F20_F; + } + if (Constraint.lower() == "{ft20}") { + FReg = RISCV::F20_F; + } + if (Constraint.lower() == "{f21}") { + FReg = RISCV::F21_F; + } + if (Constraint.lower() == "{ft21}") { + FReg = RISCV::F21_F; + } + if (Constraint.lower() == "{f22}") { + FReg = RISCV::F22_F; + } + if (Constraint.lower() == "{ft22}") { + FReg = RISCV::F22_F; + } + if (Constraint.lower() == "{f23}") { + FReg = RISCV::F23_F; + } + if (Constraint.lower() == "{ft23}") { + FReg = RISCV::F23_F; + } + if (Constraint.lower() == "{f24}") { + FReg = RISCV::F24_F; + } + if (Constraint.lower() == "{ft24}") { + FReg = RISCV::F24_F; + } + if (Constraint.lower() == "{f25}") { + FReg = RISCV::F25_F; + } + if (Constraint.lower() == "{ft25}") { + FReg = RISCV::F25_F; + } + if (Constraint.lower() == "{f26}") { + FReg = RISCV::F26_F; + } + if (Constraint.lower() == "{ft26}") { + FReg = RISCV::F26_F; + } + if (Constraint.lower() == "{f27}") { + FReg = RISCV::F27_F; + } + if (Constraint.lower() == "{ft27}") { + FReg = RISCV::F27_F; + } + if (Constraint.lower() == "{f28}") { + FReg = RISCV::F28_F; + } + if (Constraint.lower() == "{ft28}") { + FReg = RISCV::F28_F; + } + if (Constraint.lower() == "{f29}") { + FReg = RISCV::F29_F; + } + if (Constraint.lower() == "{ft29}") { + FReg = RISCV::F29_F; + } + if (Constraint.lower() == "{f30}") { + FReg = RISCV::F30_F; + } + if (Constraint.lower() == "{ft30}") { + FReg = RISCV::F30_F; + } + if (Constraint.lower() == "{f31}") { + FReg = RISCV::F31_F; + } + if (Constraint.lower() == "{ft31}") { + FReg = RISCV::F31_F; + } + if (FReg != RISCV::NoRegister) { + assert(RISCV::F0_32 <= FReg && FReg <= RISCV::F31_32 && "Unknown fp-reg"); + if (Subtarget.hasStdExtD()) { + unsigned RegNo = FReg - RISCV::F0_F; + unsigned DReg = RISCV::F0_D + RegNo; + return std::make_pair(DReg, &RISCV::FPR64RegClass); + } + return std::make_pair(FReg, &RISCV::FPR32RegClass); + } + } + return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/getRegisterByName.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/getRegisterByName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..26ad342c7f779b295cd18cd28b9b3f8724c1896c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/getRegisterByName.cpp @@ -0,0 +1,14 @@ +Register RISCVTargetLowering::getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const { + Register Reg = MatchRegisterAltName(RegName); + if (Reg == RISCV::NoRegister) { + Reg = MatchRegisterName(RegName); + } + if (Reg == RISCV::NoRegister) { + report_fatal_error(Twine("Invalid register name \"" + StringRef(RegName) + "\".")); + } + BitVector ReservedRegs = Subtarget.getRegisterInfo()->getReservedRegs(MF); + if (!ReservedRegs.test(Reg) && !Subtarget.isRegisterReservedByUser(Reg)) { + report_fatal_error(Twine("Trying to obtain non-reserved register \"" + StringRef(RegName) + "\".")); + } + return Reg; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/getSetCCResultType.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/getSetCCResultType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ca330ad9133ea7d3b3682e5e651961f59d6709eb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/getSetCCResultType.cpp @@ -0,0 +1,9 @@ +EVT RISCVTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &, EVT VT) const { + if (!VT.isVector()) { + return getPointerTy(DL); + } + if (Subtarget.hasStdExtV()) { + return MVT::getVectorVT(MVT::i1, VT.getVectorElementCount()); + } + return VT.changeVectorElementTypeToInteger(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/getStaticTLSAddr.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/getStaticTLSAddr.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8f231109058dae006fecd5590954e0a119396b49 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/getStaticTLSAddr.cpp @@ -0,0 +1,19 @@ +SDValue RISCVTargetLowering::getStaticTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG, bool UseGOT) const { + SDLoc DL(N); + EVT Ty = getPointerTy(DAG.getDataLayout()); + const GlobalValue *GV = N->getGlobal(); + MVT XLenVT = Subtarget.getXLenVT(); + if (UseGOT) { + SDValue Addr = DAG.getTargetGlobalAddress(GV, DL, Ty, 0, 0); + SDValue Load = SDValue(DAG.getMachineNode(RISCV::PseudoLA_TLS_IE, DL, Ty, Addr), 0); + SDValue TPReg = DAG.getRegister(RISCV::X4, XLenVT); + return DAG.getNode(ISD::ADD, DL, Ty, Load, TPReg); + } + SDValue AddrHi = DAG.getTargetGlobalAddress(GV, DL, Ty, 0, RISCVII::MO_TPREL_HI); + SDValue AddrAdd = DAG.getTargetGlobalAddress(GV, DL, Ty, 0, RISCVII::MO_TPREL_ADD); + SDValue AddrLo = DAG.getTargetGlobalAddress(GV, DL, Ty, 0, RISCVII::MO_TPREL_LO); + SDValue MNHi = SDValue(DAG.getMachineNode(RISCV::LUI, DL, Ty, AddrHi), 0); + SDValue TPReg = DAG.getRegister(RISCV::X4, XLenVT); + SDValue MNAdd = SDValue(DAG.getMachineNode(RISCV::PseudoAddTPRel, DL, Ty, MNHi, TPReg, AddrAdd), 0); + return SDValue(DAG.getMachineNode(RISCV::ADDI, DL, Ty, MNAdd, AddrLo), 0); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/getSubtarget.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/getSubtarget.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4d7571dffca9b46bd58d715c218cba477a279eed --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/getSubtarget.cpp @@ -0,0 +1,3 @@ +const RISCVSubtarget &getSubtarget() const { + return Subtarget; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/getTargetNodeName.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/getTargetNodeName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d2af7ef3833346212519e245d5021adcd5b7b5c8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/getTargetNodeName.cpp @@ -0,0 +1,123 @@ +const char *RISCVTargetLowering::getTargetNodeName(unsigned Opcode) const { + if ((RISCVISD::NodeType)Opcode == RISCVISD::RET_FLAG) { + return "RISCVISD::RET_FLAG"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::URET_FLAG) { + return "RISCVISD::URET_FLAG"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::SRET_FLAG) { + return "RISCVISD::SRET_FLAG"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::MRET_FLAG) { + return "RISCVISD::MRET_FLAG"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::CALL) { + return "RISCVISD::CALL"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::SELECT_CC) { + return "RISCVISD::SELECT_CC"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::BuildPairF64) { + return "RISCVISD::BuildPairF64"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::SplitF64) { + return "RISCVISD::SplitF64"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::TAIL) { + return "RISCVISD::TAIL"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::FMV_X_ANYEXTH) { + return "RISCVISD::FMV_X_ANYEXTH"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::FMV_W_X_RV64) { + return "RISCVISD::FMV_W_X_RV64"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::FMV_X_ANYEXTW_RV64) { + return "RISCVISD::FMV_X_ANYEXTW_RV64"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::READ_CYCLE_WIDE) { + return "RISCVISD::READ_CYCLE_WIDE"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::GREVI) { + return "RISCVISD::GREVI"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::GREVIW) { + return "RISCVISD::GREVIW"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::GORCI) { + return "RISCVISD::GORCI"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::GORCIW) { + return "RISCVISD::GORCIW"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::VMV_X_S) { + return "RISCVISD::VMV_X_S"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::SPLAT_VECTOR_I64) { + return "RISCVISD::SPLAT_VECTOR_I64"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::READ_VLENB) { + return "RISCVISD::READ_VLENB"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::TRUNCATE_VECTOR) { + return "RISCVISD::TRUNCATE_VECTOR"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::VLEFF) { + return "RISCVISD::VLEFF"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::VLEFF_MASK) { + return "RISCVISD::VLEFF_MASK"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::VLSEGFF) { + return "RISCVISD::VLSEGFF"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::VLSEGFF_MASK) { + return "RISCVISD::VLSEGFF_MASK"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::READ_VL) { + return "RISCVISD::READ_VL"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::VSLIDEUP) { + return "RISCVISD::VSLIDEUP"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::VSLIDEDOWN) { + return "RISCVISD::VSLIDEDOWN"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::VID) { + return "RISCVISD::VID"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::FMV_H_X) { + return "RISCVISD::FMV_H_X"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::FSRW) { + return "RISCVISD::FSRW"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::FSLW) { + return "RISCVISD::FSLW"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::RORW) { + return "RISCVISD::RORW"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::ROLW) { + return "RISCVISD::ROLW"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::REMUW) { + return "RISCVISD::REMUW"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::DIVUW) { + return "RISCVISD::DIVUW"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::DIVW) { + return "RISCVISD::DIVW"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::SRLW) { + return "RISCVISD::SRLW"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::SRAW) { + return "RISCVISD::SRAW"; + } + if ((RISCVISD::NodeType)Opcode == RISCVISD::SLLW) { + return "RISCVISD::SLLW"; + } + return nullptr; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/getTgtMemIntrinsic.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/getTgtMemIntrinsic.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4d8deda7d83d9f59a857e66fddd44324aa0de609 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/getTgtMemIntrinsic.cpp @@ -0,0 +1,93 @@ +bool RISCVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const { + if (Intrinsic == Intrinsic::riscv_masked_atomicrmw_xchg_i32) { + PointerType *PtrTy = cast(I.getArgOperand(0)->getType()); + Info.opc = ISD::INTRINSIC_W_CHAIN; + Info.memVT = MVT::getVT(PtrTy->getElementType()); + Info.ptrVal = I.getArgOperand(0); + Info.offset = 0; + Info.align = Align(4); + Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore | MachineMemOperand::MOVolatile; + return true; + } + if (Intrinsic == Intrinsic::riscv_masked_atomicrmw_add_i32) { + PointerType *PtrTy = cast(I.getArgOperand(0)->getType()); + Info.opc = ISD::INTRINSIC_W_CHAIN; + Info.memVT = MVT::getVT(PtrTy->getElementType()); + Info.ptrVal = I.getArgOperand(0); + Info.offset = 0; + Info.align = Align(4); + Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore | MachineMemOperand::MOVolatile; + return true; + } + if (Intrinsic == Intrinsic::riscv_masked_atomicrmw_sub_i32) { + PointerType *PtrTy = cast(I.getArgOperand(0)->getType()); + Info.opc = ISD::INTRINSIC_W_CHAIN; + Info.memVT = MVT::getVT(PtrTy->getElementType()); + Info.ptrVal = I.getArgOperand(0); + Info.offset = 0; + Info.align = Align(4); + Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore | MachineMemOperand::MOVolatile; + return true; + } + if (Intrinsic == Intrinsic::riscv_masked_atomicrmw_nand_i32) { + PointerType *PtrTy = cast(I.getArgOperand(0)->getType()); + Info.opc = ISD::INTRINSIC_W_CHAIN; + Info.memVT = MVT::getVT(PtrTy->getElementType()); + Info.ptrVal = I.getArgOperand(0); + Info.offset = 0; + Info.align = Align(4); + Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore | MachineMemOperand::MOVolatile; + return true; + } + if (Intrinsic == Intrinsic::riscv_masked_atomicrmw_max_i32) { + PointerType *PtrTy = cast(I.getArgOperand(0)->getType()); + Info.opc = ISD::INTRINSIC_W_CHAIN; + Info.memVT = MVT::getVT(PtrTy->getElementType()); + Info.ptrVal = I.getArgOperand(0); + Info.offset = 0; + Info.align = Align(4); + Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore | MachineMemOperand::MOVolatile; + return true; + } + if (Intrinsic == Intrinsic::riscv_masked_atomicrmw_min_i32) { + PointerType *PtrTy = cast(I.getArgOperand(0)->getType()); + Info.opc = ISD::INTRINSIC_W_CHAIN; + Info.memVT = MVT::getVT(PtrTy->getElementType()); + Info.ptrVal = I.getArgOperand(0); + Info.offset = 0; + Info.align = Align(4); + Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore | MachineMemOperand::MOVolatile; + return true; + } + if (Intrinsic == Intrinsic::riscv_masked_atomicrmw_umax_i32) { + PointerType *PtrTy = cast(I.getArgOperand(0)->getType()); + Info.opc = ISD::INTRINSIC_W_CHAIN; + Info.memVT = MVT::getVT(PtrTy->getElementType()); + Info.ptrVal = I.getArgOperand(0); + Info.offset = 0; + Info.align = Align(4); + Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore | MachineMemOperand::MOVolatile; + return true; + } + if (Intrinsic == Intrinsic::riscv_masked_atomicrmw_umin_i32) { + PointerType *PtrTy = cast(I.getArgOperand(0)->getType()); + Info.opc = ISD::INTRINSIC_W_CHAIN; + Info.memVT = MVT::getVT(PtrTy->getElementType()); + Info.ptrVal = I.getArgOperand(0); + Info.offset = 0; + Info.align = Align(4); + Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore | MachineMemOperand::MOVolatile; + return true; + } + if (Intrinsic == Intrinsic::riscv_masked_cmpxchg_i32) { + PointerType *PtrTy = cast(I.getArgOperand(0)->getType()); + Info.opc = ISD::INTRINSIC_W_CHAIN; + Info.memVT = MVT::getVT(PtrTy->getElementType()); + Info.ptrVal = I.getArgOperand(0); + Info.offset = 0; + Info.align = Align(4); + Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore | MachineMemOperand::MOVolatile; + return true; + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/hasBitPreservingFPLogic.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/hasBitPreservingFPLogic.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d1c41f213e055244de1922cb5a036fe323993663 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/hasBitPreservingFPLogic.cpp @@ -0,0 +1,3 @@ +bool RISCVTargetLowering::hasBitPreservingFPLogic(EVT VT) const { + return (VT == MVT::f16 && Subtarget.hasStdExtZfh()) || (VT == MVT::f32 && Subtarget.hasStdExtF()) || (VT == MVT::f64 && Subtarget.hasStdExtD()); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/isCheapToSpeculateCtlz.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/isCheapToSpeculateCtlz.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7d9f871f13e0b61779ec7b7ac0e64443ee06b43f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/isCheapToSpeculateCtlz.cpp @@ -0,0 +1,3 @@ +bool RISCVTargetLowering::isCheapToSpeculateCtlz() const { + return Subtarget.hasStdExtZbb(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/isCheapToSpeculateCttz.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/isCheapToSpeculateCttz.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d9a2e056622fab5c51755ed36e67138289278601 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/isCheapToSpeculateCttz.cpp @@ -0,0 +1,3 @@ +bool RISCVTargetLowering::isCheapToSpeculateCttz() const { + return Subtarget.hasStdExtZbb(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/isDesirableToCommuteWithShift.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/isDesirableToCommuteWithShift.cpp new file mode 100644 index 0000000000000000000000000000000000000000..972b11ab3501171966e3bfd4b96ec82355cbbcaa --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/isDesirableToCommuteWithShift.cpp @@ -0,0 +1,24 @@ +bool RISCVTargetLowering::isDesirableToCommuteWithShift(const SDNode *N, CombineLevel Level) const { + SDValue N0 = N->getOperand(0); + EVT Ty = N0.getValueType(); + if (Ty.isScalarInteger() && (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::OR)) { + auto *C1 = dyn_cast(N0->getOperand(1)); + auto *C2 = dyn_cast(N->getOperand(1)); + if (C1 && C2) { + const APInt &C1Int = C1->getAPIntValue(); + APInt ShiftedC1Int = C1Int << C2->getAPIntValue(); + if (ShiftedC1Int.getMinSignedBits() <= 64 && isLegalAddImmediate(ShiftedC1Int.getSExtValue())) { + return true; + } + if (C1Int.getMinSignedBits() <= 64 && isLegalAddImmediate(C1Int.getSExtValue())) { + return false; + } + int C1Cost = RISCVMatInt::getIntMatCost(C1Int, Ty.getSizeInBits(), Subtarget.is64Bit()); + int ShiftedC1Cost = RISCVMatInt::getIntMatCost(ShiftedC1Int, Ty.getSizeInBits(), Subtarget.is64Bit()); + if (C1Cost < ShiftedC1Cost) { + return false; + } + } + } + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/isEligibleForTailCallOptimization.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/isEligibleForTailCallOptimization.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4ade96d77d668102258fdfb941e8165d21a19205 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/isEligibleForTailCallOptimization.cpp @@ -0,0 +1,44 @@ + +bool RISCVTargetLowering::isEligibleForTailCallOptimization(CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF, const SmallVector &ArgLocs) const { + auto &Callee = CLI.Callee; + auto CalleeCC = CLI.CallConv; + auto &Outs = CLI.Outs; + auto &Caller = MF.getFunction(); + auto CallerCC = Caller.getCallingConv(); + if (Caller.hasFnAttribute("interrupt")) { + return false; + } + if (CCInfo.getNextStackOffset() != 0) { + return false; + } + for (auto &VA : ArgLocs) { + if (VA.getLocInfo() == CCValAssign::Indirect) { + return false; + } + } + auto IsCallerStructRet = Caller.hasStructRetAttr(); + auto IsCalleeStructRet = Outs.empty() ? false : Outs[0].Flags.isSRet(); + if (IsCallerStructRet || IsCalleeStructRet) { + return false; + } + if (GlobalAddressSDNode *G = dyn_cast(Callee)) { + const GlobalValue *GV = G->getGlobal(); + if (GV->hasExternalWeakLinkage()) { + return false; + } + } + const RISCVRegisterInfo *TRI = Subtarget.getRegisterInfo(); + const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC); + if (CalleeCC != CallerCC) { + const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC); + if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved)) { + return false; + } + } + for (auto &Arg : Outs) { + if (Arg.Flags.isByVal()) { + return false; + } + } + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/isFMAFasterThanFMulAndFAdd.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/isFMAFasterThanFMulAndFAdd.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2056d0ac4e9581359873184d0cedfb79ae3e2723 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/isFMAFasterThanFMulAndFAdd.cpp @@ -0,0 +1,17 @@ +bool RISCVTargetLowering::isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const { + VT = VT.getScalarType(); + if (!VT.isSimple()) { + return false; + } + switch (VT.getSimpleVT().SimpleTy) { + case MVT::f16: + return Subtarget.hasStdExtZfh(); + case MVT::f32: + return Subtarget.hasStdExtF(); + case MVT::f64: + return Subtarget.hasStdExtD(); + default: + break; + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/isFPImmLegal.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/isFPImmLegal.cpp new file mode 100644 index 0000000000000000000000000000000000000000..36936d70cb866640bf90c1d991e6af92243eec59 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/isFPImmLegal.cpp @@ -0,0 +1,21 @@ +bool RISCVTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const { + if (VT == MVT::f16) { + if (!Subtarget.hasStdExtZfh()) { + return false; + } + } + if (VT == MVT::f32) { + if (!Subtarget.hasStdExtF()) { + return false; + } + } + if (VT == MVT::f64) { + if (!Subtarget.hasStdExtD()) { + return false; + } + } + if (Imm.isNegZero()) { + return false; + } + return Imm.isZero(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/isLegalAddImmediate.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/isLegalAddImmediate.cpp new file mode 100644 index 0000000000000000000000000000000000000000..27342f01a75e9602e8823826937d056a8c10605f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/isLegalAddImmediate.cpp @@ -0,0 +1,3 @@ +bool RISCVTargetLowering::isLegalAddImmediate(int64_t Imm) const { + return isInt<12>(Imm); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/isLegalAddressingMode.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/isLegalAddressingMode.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c3fc00237148c4d20cfe2aea80e3a44e2f1aaad8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/isLegalAddressingMode.cpp @@ -0,0 +1,20 @@ +bool RISCVTargetLowering::isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I) const { + if (AM.BaseGV) { + return false; + } + if (!isInt<12>(AM.BaseOffs)) { + return false; + } + switch (AM.Scale) { + case 0: + break; + case 1: + if (!AM.HasBaseReg) { + break; + } + return false; + default: + return false; + } + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/isLegalICmpImmediate.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/isLegalICmpImmediate.cpp new file mode 100644 index 0000000000000000000000000000000000000000..50a187b1c95b0177261e158b1676e2eef2e5b294 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/isLegalICmpImmediate.cpp @@ -0,0 +1,3 @@ +bool RISCVTargetLowering::isLegalICmpImmediate(int64_t Imm) const { + return isInt<12>(Imm); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/isSExtCheaperThanZExt.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/isSExtCheaperThanZExt.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e8f8585225e31860fa294413e0d386f6e3ca4b51 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/isSExtCheaperThanZExt.cpp @@ -0,0 +1,3 @@ +bool RISCVTargetLowering::isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const { + return Subtarget.is64Bit() && SrcVT == MVT::i32 && DstVT == MVT::i64; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/isTruncateFree.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/isTruncateFree.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6d27755e3ae3c64b204a428d561db12e21d89e8d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/isTruncateFree.cpp @@ -0,0 +1,8 @@ +bool RISCVTargetLowering::isTruncateFree(Type *SrcTy, Type *DstTy) const { + if (Subtarget.is64Bit() || !SrcTy->isIntegerTy() || !DstTy->isIntegerTy()) { + return false; + } + unsigned SrcBits = SrcTy->getPrimitiveSizeInBits(); + unsigned DestBits = DstTy->getPrimitiveSizeInBits(); + return (SrcBits == 64 && DestBits == 32); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/isTruncateFree2.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/isTruncateFree2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0d212b5aaadd33f2042e323c9e69be7f2022ece5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/isTruncateFree2.cpp @@ -0,0 +1,8 @@ +bool RISCVTargetLowering::isTruncateFree(EVT SrcVT, EVT DstVT) const { + if (Subtarget.is64Bit() || SrcVT.isVector() || DstVT.isVector() || !SrcVT.isInteger() || !DstVT.isInteger()) { + return false; + } + unsigned SrcBits = SrcVT.getSizeInBits(); + unsigned DestBits = DstVT.getSizeInBits(); + return (SrcBits == 64 && DestBits == 32); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/isZExtFree.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/isZExtFree.cpp new file mode 100644 index 0000000000000000000000000000000000000000..75d97387f9027fe3ec4fac559ed7892b3b769ecd --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/isZExtFree.cpp @@ -0,0 +1,9 @@ +bool RISCVTargetLowering::isZExtFree(SDValue Val, EVT VT2) const { + if (auto *LD = dyn_cast(Val)) { + EVT MemVT = LD->getMemoryVT(); + if ((MemVT == MVT::i8 || MemVT == MVT::i16 || (Subtarget.is64Bit() && MemVT == MVT::i32)) && (LD->getExtensionType() == ISD::NON_EXTLOAD || LD->getExtensionType() == ISD::ZEXTLOAD)) { + return true; + } + } + return TargetLowering::isZExtFree(Val, VT2); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/lowerEXTRACT_VECTOR_ELT.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/lowerEXTRACT_VECTOR_ELT.cpp new file mode 100644 index 0000000000000000000000000000000000000000..050e83980f6a8e966d61e932a1c240c89fefcc43 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/lowerEXTRACT_VECTOR_ELT.cpp @@ -0,0 +1,12 @@ +SDValue RISCVTargetLowering::lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const { + SDLoc DL(Op); + SDValue Idx = Op.getOperand(1); + if (isNullConstant(Idx)) { + return Op; + } + SDValue Vec = Op.getOperand(0); + EVT EltVT = Op.getValueType(); + EVT VecVT = Vec.getValueType(); + SDValue Slidedown = DAG.getNode(RISCVISD::VSLIDEDOWN, DL, VecVT, DAG.getUNDEF(VecVT), Vec, Idx); + return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Slidedown, DAG.getConstant(0, DL, Subtarget.getXLenVT())); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/lowerINSERT_VECTOR_ELT.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/lowerINSERT_VECTOR_ELT.cpp new file mode 100644 index 0000000000000000000000000000000000000000..41468edf3120b3af736ffa9f92aa9d239535b7a0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/lowerINSERT_VECTOR_ELT.cpp @@ -0,0 +1,21 @@ + +SDValue RISCVTargetLowering::lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const { + SDLoc DL(Op); + EVT VecVT = Op.getValueType(); + SDValue Vec = Op.getOperand(0); + SDValue Val = Op.getOperand(1); + SDValue Idx = Op.getOperand(2); + if (Subtarget.is64Bit() || VecVT.getVectorElementType() != MVT::i64) { + if (isNullConstant(Idx)) + return Op; + SDValue Slidedown = DAG.getNode(RISCVISD::VSLIDEDOWN, DL, VecVT, DAG.getUNDEF(VecVT), Vec, Idx); + SDValue InsertElt0 = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VecVT, Slidedown, Val, DAG.getConstant(0, DL, Subtarget.getXLenVT())); + return DAG.getNode(RISCVISD::VSLIDEUP, DL, VecVT, Vec, InsertElt0, Idx); + } + SDValue SplattedVal = DAG.getSplatVector(VecVT, DL, Val); + SDValue SplattedIdx = DAG.getNode(RISCVISD::SPLAT_VECTOR_I64, DL, VecVT, Idx); + SDValue VID = DAG.getNode(RISCVISD::VID, DL, VecVT); + auto SetCCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VecVT); + SDValue Mask = DAG.getSetCC(DL, SetCCVT, VID, SplattedIdx, ISD::SETEQ); + return DAG.getNode(ISD::VSELECT, DL, VecVT, Mask, SplattedVal, Vec); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/lowerSELECT.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/lowerSELECT.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d178b704135564eb306892895a477348039fefb8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/lowerSELECT.cpp @@ -0,0 +1,21 @@ +SDValue RISCVTargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const { + SDValue CondV = Op.getOperand(0); + SDValue TrueV = Op.getOperand(1); + SDValue FalseV = Op.getOperand(2); + SDLoc DL(Op); + MVT XLenVT = Subtarget.getXLenVT(); + if (Op.getSimpleValueType() == XLenVT && CondV.getOpcode() == ISD::SETCC && CondV.getOperand(0).getSimpleValueType() == XLenVT) { + SDValue LHS = CondV.getOperand(0); + SDValue RHS = CondV.getOperand(1); + auto CC = cast(CondV.getOperand(2)); + ISD::CondCode CCVal = CC->get(); + normaliseSetCC(LHS, RHS, CCVal); + SDValue TargetCC = DAG.getConstant(CCVal, DL, XLenVT); + SDValue Ops[] = {LHS, RHS, TargetCC, TrueV, FalseV}; + return DAG.getNode(RISCVISD::SELECT_CC, DL, Op.getValueType(), Ops); + } + SDValue Zero = DAG.getConstant(0, DL, XLenVT); + SDValue SetNE = DAG.getConstant(ISD::SETNE, DL, XLenVT); + SDValue Ops[] = {CondV, Zero, SetNE, TrueV, FalseV}; + return DAG.getNode(RISCVISD::SELECT_CC, DL, Op.getValueType(), Ops); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/lowerSPLATVECTOR.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/lowerSPLATVECTOR.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a9078247c7a9a4149ed654f10dd7d4f9d2f34abd --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/lowerSPLATVECTOR.cpp @@ -0,0 +1,26 @@ +SDValue RISCVTargetLowering::lowerSPLATVECTOR(SDValue Op, SelectionDAG &DAG) const { + SDLoc DL(Op); + EVT VecVT = Op.getValueType(); + assert(!Subtarget.is64Bit() && VecVT.getVectorElementType() == MVT::i64 && "Unexpected SPLAT_VECTOR lowering"); + SDValue SplatVal = Op.getOperand(0); + if (auto *CVal = dyn_cast(SplatVal)) { + if (isInt<32>(CVal->getSExtValue())) + return DAG.getNode(RISCVISD::SPLAT_VECTOR_I64, DL, VecVT, DAG.getConstant(CVal->getSExtValue(), DL, MVT::i32)); + } + if (SplatVal.getOpcode() == ISD::SIGN_EXTEND && SplatVal.getOperand(0).getValueType() == MVT::i32) { + return DAG.getNode(RISCVISD::SPLAT_VECTOR_I64, DL, VecVT, SplatVal.getOperand(0)); + } + SDValue One = DAG.getConstant(1, DL, MVT::i32); + SDValue Zero = DAG.getConstant(0, DL, MVT::i32); + SDValue ThirtyTwoV = DAG.getConstant(32, DL, VecVT); + SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, SplatVal, Zero); + SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, SplatVal, One); + Lo = DAG.getNode(RISCVISD::SPLAT_VECTOR_I64, DL, VecVT, Lo); + Lo = DAG.getNode(ISD::SHL, DL, VecVT, Lo, ThirtyTwoV); + Lo = DAG.getNode(ISD::SRL, DL, VecVT, Lo, ThirtyTwoV); + if (isNullConstant(Hi)) + return Lo; + Hi = DAG.getNode(RISCVISD::SPLAT_VECTOR_I64, DL, VecVT, Hi); + Hi = DAG.getNode(ISD::SHL, DL, VecVT, Hi, ThirtyTwoV); + return DAG.getNode(ISD::OR, DL, VecVT, Lo, Hi); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/lowerShiftLeftParts.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/lowerShiftLeftParts.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8a781b0834469a4688ad73e9a4725749eac3b6f3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/lowerShiftLeftParts.cpp @@ -0,0 +1,24 @@ +SDValue RISCVTargetLowering::lowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const { + SDLoc DL(Op); + SDValue Lo = Op.getOperand(0); + SDValue Hi = Op.getOperand(1); + SDValue Shamt = Op.getOperand(2); + SDValue Zero = DAG.getConstant(0, DL, VT); + SDValue One = DAG.getConstant(1, DL, VT); + EVT VT = Lo.getValueType(); + SDValue MinusXLen = DAG.getConstant(-(int)Subtarget.getXLen(), DL, VT); + SDValue XLenMinus1 = DAG.getConstant(Subtarget.getXLen() - 1, DL, VT); + SDValue ShamtMinusXLen = DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusXLen); + SDValue XLenMinus1Shamt = DAG.getNode(ISD::SUB, DL, VT, XLenMinus1, Shamt); + SDValue LoTrue = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt); + SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo, One); + SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, XLenMinus1Shamt); + SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt); + SDValue HiTrue = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo); + SDValue HiFalse = DAG.getNode(ISD::SHL, DL, VT, Lo, ShamtMinusXLen); + SDValue CC = DAG.getSetCC(DL, VT, ShamtMinusXLen, Zero, ISD::SETLT); + Lo = DAG.getNode(ISD::SELECT, DL, VT, CC, LoTrue, Zero); + Hi = DAG.getNode(ISD::SELECT, DL, VT, CC, HiTrue, HiFalse); + SDValue Parts[2] = {Lo, Hi}; + return DAG.getMergeValues(Parts, DL); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/lowerShiftRightParts.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/lowerShiftRightParts.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a763204f45299f1efa455b96f65930c2e3e267ef --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/lowerShiftRightParts.cpp @@ -0,0 +1,26 @@ +SDValue RISCVTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const { + SDLoc DL(Op); + SDValue Lo = Op.getOperand(0); + SDValue Hi = Op.getOperand(1); + SDValue Shamt = Op.getOperand(2); + EVT VT = Lo.getValueType(); + unsigned ShiftRightOp = IsSRA ? ISD::SRA : ISD::SRL; + SDValue Zero = DAG.getConstant(0, DL, VT); + SDValue One = DAG.getConstant(1, DL, VT); + SDValue MinusXLen = DAG.getConstant(-(int)Subtarget.getXLen(), DL, VT); + SDValue XLenMinus1 = DAG.getConstant(Subtarget.getXLen() - 1, DL, VT); + SDValue ShamtMinusXLen = DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusXLen); + SDValue XLenMinus1Shamt = DAG.getNode(ISD::SUB, DL, VT, XLenMinus1, Shamt); + SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt); + SDValue ShiftLeftHi1 = DAG.getNode(ISD::SHL, DL, VT, Hi, One); + SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeftHi1, XLenMinus1Shamt); + SDValue LoTrue = DAG.getNode(ISD::OR, DL, VT, ShiftRightLo, ShiftLeftHi); + SDValue HiTrue = DAG.getNode(ShiftRightOp, DL, VT, Hi, Shamt); + SDValue LoFalse = DAG.getNode(ShiftRightOp, DL, VT, Hi, ShamtMinusXLen); + SDValue HiFalse = IsSRA ? DAG.getNode(ISD::SRA, DL, VT, Hi, XLenMinus1) : Zero; + SDValue CC = DAG.getSetCC(DL, VT, ShamtMinusXLen, Zero, ISD::SETLT); + Lo = DAG.getNode(ISD::SELECT, DL, VT, CC, LoTrue, LoFalse); + Hi = DAG.getNode(ISD::SELECT, DL, VT, CC, HiTrue, HiFalse); + SDValue Parts[2] = {Lo, Hi}; + return DAG.getMergeValues(Parts, DL); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/lowerVectorMaskExt.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/lowerVectorMaskExt.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9c860632f70220e7401fd9e8e3d7240d21e74964 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/lowerVectorMaskExt.cpp @@ -0,0 +1,20 @@ +SDValue RISCVTargetLowering::lowerVectorMaskExt(SDValue Op, SelectionDAG &DAG, int64_t ExtTrueVal) const { + SDLoc DL(Op); + EVT VecVT = Op.getValueType(); + SDValue Src = Op.getOperand(0); + if (!Src.getValueType().isVector() || Src.getValueType().getVectorElementType() != MVT::i1) { + return Op; + } + bool IsRV32E64 = !Subtarget.is64Bit() && VecVT.getVectorElementType() == MVT::i64; + SDValue SplatZero = DAG.getConstant(0, DL, Subtarget.getXLenVT()); + SDValue SplatTrueVal = DAG.getConstant(ExtTrueVal, DL, Subtarget.getXLenVT()); + if (!IsRV32E64) { + SplatZero = DAG.getSplatVector(VecVT, DL, SplatZero); + SplatTrueVal = DAG.getSplatVector(VecVT, DL, SplatTrueVal); + } + else { + SplatZero = DAG.getNode(RISCVISD::SPLAT_VECTOR_I64, DL, VecVT, SplatZero); + SplatTrueVal = DAG.getNode(RISCVISD::SPLAT_VECTOR_I64, DL, VecVT, SplatTrueVal); + } + return DAG.getNode(ISD::VSELECT, DL, VecVT, Src, SplatTrueVal, SplatZero); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/lowerVectorMaskTrunc.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/lowerVectorMaskTrunc.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c98f553f2d44e030d17fe05f422ae1fb199ece6f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/lowerVectorMaskTrunc.cpp @@ -0,0 +1,20 @@ +SDValue RISCVTargetLowering::lowerVectorMaskTrunc(SDValue Op, SelectionDAG &DAG) const { + SDLoc DL(Op); + EVT MaskVT = Op.getValueType(); + assert(MaskVT.isVector() && MaskVT.getVectorElementType() == MVT::i1 && "Unexpected type for vector mask lowering"); + SDValue Src = Op.getOperand(0); + EVT VecVT = Src.getValueType(); + bool IsRV32E64 = !Subtarget.is64Bit() && VecVT.getVectorElementType() == MVT::i64; + SDValue SplatOne = DAG.getConstant(1, DL, Subtarget.getXLenVT()); + SDValue SplatZero = DAG.getConstant(0, DL, Subtarget.getXLenVT()); + if (!IsRV32E64) { + SplatOne = DAG.getSplatVector(VecVT, DL, SplatOne); + SplatZero = DAG.getSplatVector(VecVT, DL, SplatZero); + } + else { + SplatOne = DAG.getNode(RISCVISD::SPLAT_VECTOR_I64, DL, VecVT, SplatOne); + SplatZero = DAG.getNode(RISCVISD::SPLAT_VECTOR_I64, DL, VecVT, SplatZero); + } + SDValue Trunc = DAG.getNode(ISD::AND, DL, VecVT, Src, SplatOne); + return DAG.getSetCC(DL, MaskVT, Trunc, SplatZero, ISD::SETNE); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/mayBeEmittedAsTailCall.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/mayBeEmittedAsTailCall.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ede8c5227cba93dac852a1d065fa68b425858673 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/mayBeEmittedAsTailCall.cpp @@ -0,0 +1,3 @@ +bool RISCVTargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const { + return CI->isTailCall(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/normaliseSetCC.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/normaliseSetCC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..81761d63f787d7ededa1a742cd4605cddb2a4530 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/normaliseSetCC.cpp @@ -0,0 +1,13 @@ +static void normaliseSetCC(SDValue &LHS, SDValue &RHS, ISD::CondCode &CC) { + switch (CC) { + default: + break; + case ISD::SETGT: + case ISD::SETLE: + case ISD::SETUGT: + case ISD::SETULE: + CC = ISD::getSetCCSwappedOperands(CC); + std::swap(LHS, RHS); + break; + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/normalizeSetCC.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/normalizeSetCC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f68f25a787d6d9d179404a12f57ee6bc55abf05a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/normalizeSetCC.cpp @@ -0,0 +1,2 @@ +static void normaliseSetCC(SDValue &LHS, SDValue &RHS, ISD::CondCode &CC) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/shouldConsiderGEPOffsetSplit.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/shouldConsiderGEPOffsetSplit.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d6227315c51762f79d2968256df1156d834e76e3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/shouldConsiderGEPOffsetSplit.cpp @@ -0,0 +1,3 @@ +bool shouldConsiderGEPOffsetSplit() const override { + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/shouldConvertConstantLoadToIntImm.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/shouldConvertConstantLoadToIntImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bf5f534d508b97390d1ee1ae00b5cc79a7861324 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/shouldConvertConstantLoadToIntImm.cpp @@ -0,0 +1,3 @@ +bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override { + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/shouldExpandAtomicCmpXchgInIR.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/shouldExpandAtomicCmpXchgInIR.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ac3aae03b6673555878d5192537d50cc530ff736 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/shouldExpandAtomicCmpXchgInIR.cpp @@ -0,0 +1,7 @@ +TargetLowering::AtomicExpansionKind RISCVTargetLowering::shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *CI) const { + unsigned Size = CI->getCompareOperand()->getType()->getPrimitiveSizeInBits(); + if (Size == 8 || Size == 16) { + return AtomicExpansionKind::MaskedIntrinsic; + } + return AtomicExpansionKind::None; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/shouldExpandAtomicRMWInIR.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/shouldExpandAtomicRMWInIR.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4625774d344f7f29a1166ef8ecbca7823323f687 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/shouldExpandAtomicRMWInIR.cpp @@ -0,0 +1,10 @@ +TargetLowering::AtomicExpansionKind RISCVTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const { + if (AI->isFloatingPointOperation()) { + return AtomicExpansionKind::CmpXChg; + } + unsigned Size = AI->getType()->getPrimitiveSizeInBits(); + if (Size == 8 || Size == 16) { + return AtomicExpansionKind::MaskedIntrinsic; + } + return AtomicExpansionKind::None; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/shouldExpandShift.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/shouldExpandShift.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b6604d98ac52fd4c5047c923e074351eea490f8f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/shouldExpandShift.cpp @@ -0,0 +1,6 @@ +bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override { + if (DAG.getMachineFunction().getFunction().hasMinSize()) { + return false; + } + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/shouldExtendTypeInLibCall.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/shouldExtendTypeInLibCall.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d32e64209e6b08e4763994b4f801e4c206f38c74 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/shouldExtendTypeInLibCall.cpp @@ -0,0 +1,7 @@ +bool RISCVTargetLowering::shouldExtendTypeInLibCall(EVT Type) const { + RISCVABI::ABI ABI = Subtarget.getTargetABI(); + if (ABI == RISCVABI::ABI_LP64 && (Type == MVT::f32)) { + return false; + } + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/shouldInsertFencesForAtomic.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/shouldInsertFencesForAtomic.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e56fe49efb7aebf69d2c959f42c622a45c409323 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/shouldInsertFencesForAtomic.cpp @@ -0,0 +1,3 @@ +bool shouldInsertFencesForAtomic(const Instruction *I) const override { + return isa(I) || isa(I); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/shouldSignExtendTypeInLibCall.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/shouldSignExtendTypeInLibCall.cpp new file mode 100644 index 0000000000000000000000000000000000000000..260ccec9da37823ed051c89f36e5a92ee1f5e02c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/shouldSignExtendTypeInLibCall.cpp @@ -0,0 +1,6 @@ +bool RISCVTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const { + if (Subtarget.is64Bit() && Type == MVT::i32) { + return true; + } + return IsSigned; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/targetShrinkDemandedConstant.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/targetShrinkDemandedConstant.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a4d16ec95b820e45afaa94d482643662493978f4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/targetShrinkDemandedConstant.cpp @@ -0,0 +1,44 @@ +bool RISCVTargetLowering::targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, TargetLoweringOpt &TLO) const { + if (!TLO.LegalOps) { + return false; + } + EVT VT = Op.getValueType(); + if (VT.isVector()) { + return false; + } + if (Op.getOpcode() != ISD::AND) { + return false; + } + ConstantSDNode *C = dyn_cast(Op.getOperand(1)); + if (!C) { + return false; + } + const APInt &Mask = C->getAPIntValue(); + APInt ShrunkMask = Mask & DemandedBits; + if (ShrunkMask.isSignedIntN(12)) { + return false; + } + APInt ExpandedMask = Mask | ~DemandedBits; + if (!ExpandedMask.isNegative()) { + return false; + } + unsigned MinSignedBits = ExpandedMask.getMinSignedBits(); + APInt NewMask = ShrunkMask; + if (MinSignedBits <= 12) { + NewMask.setBitsFrom(11); + } + else if (MinSignedBits <= 32 && !ShrunkMask.isSignedIntN(32)) { + NewMask.setBitsFrom(31); + } + else { + return false; + } + assert(NewMask.isSubsetOf(ExpandedMask)); + if (NewMask == Mask) { + return true; + } + SDLoc DL(Op); + SDValue NewC = TLO.DAG.getConstant(NewMask, DL, VT); + SDValue NewOp = TLO.DAG.getNode(ISD::AND, DL, VT, Op.getOperand(0), NewC); + return TLO.CombineTo(Op, NewOp); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/validateCCReservedRegs.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/validateCCReservedRegs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..18092d2a41f8aacf563ddf86d379df202fe8c4e1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/ISelLowering/validateCCReservedRegs.cpp @@ -0,0 +1,8 @@ +void RISCVTargetLowering::validateCCReservedRegs(const SmallVectorImpl> &Regs, MachineFunction &MF) const { + const Function &F = MF.getFunction(); + const RISCVSubtarget &STI = MF.getSubtarget(); + if (llvm::any_of(Regs, [&STI](auto Reg) { + return STI.isRegisterReservedByUser(Reg.first); + })) + F.getContext().diagnose(DiagnosticInfoUnsupported{F, "Argument register required, but has been reserved."}); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/InstructionSelector/InstructionSelector.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/InstructionSelector/InstructionSelector.cpp new file mode 100644 index 0000000000000000000000000000000000000000..53cc2835a41ac58f713da3322777b6baeda2bb12 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/InstructionSelector/InstructionSelector.cpp @@ -0,0 +1,9 @@ +RISCVInstructionSelector::RISCVInstructionSelector(const RISCVTargetMachine &TM, const RISCVSubtarget &STI,const RISCVRegisterBankInfo &RBI) : InstructionSelector(), STI(STI), TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()), RBI(RBI), +#define GET_GLOBALISEL_PREDICATES_INIT +#include "RISCVGenGlobalISel.inc" +#undef GET_GLOBALISEL_PREDICATES_INIT +#define GET_GLOBALISEL_TEMPORARIES_INIT +#include "RISCVGenGlobalISel.inc" +#undef GET_GLOBALISEL_TEMPORARIES_INIT +{ +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/InstructionSelector/createInstructionSelector.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/InstructionSelector/createInstructionSelector.cpp new file mode 100644 index 0000000000000000000000000000000000000000..db262f141398799e83acb55cc3b48da452774550 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/InstructionSelector/createInstructionSelector.cpp @@ -0,0 +1,3 @@ +InstructionSelector *createRISCVInstructionSelector(const RISCVTargetMachine &TM, RISCVSubtarget &Subtarget, RISCVRegisterBankInfo &RBI) { + return new RISCVInstructionSelector(TM, Subtarget, RBI); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/InstructionSelector/getName.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/InstructionSelector/getName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3070f67f8b2d72c6473a6bf2cc4639c82757caaa --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/InstructionSelector/getName.cpp @@ -0,0 +1,3 @@ +static const char *getName() { + return DEBUG_TYPE; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/InstructionSelector/select.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/InstructionSelector/select.cpp new file mode 100644 index 0000000000000000000000000000000000000000..333a38c3ab713a75f6667c26f37dfadbd1ac8adf --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/InstructionSelector/select.cpp @@ -0,0 +1,8 @@ +bool RISCVInstructionSelector::select(MachineInstr &I) { + if (!isPreISelGenericOpcode(I.getOpcode())) { + } + if (selectImpl(I, *CoverageInfo)) { + return true; + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/LegalizeInfo/LegalizerInfo.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/LegalizeInfo/LegalizerInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..58f919e738fbe34244db0d85687060525c38698e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/LegalizeInfo/LegalizerInfo.cpp @@ -0,0 +1,3 @@ +RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) { + computeTables(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/MCInstLower/lowerMachineInstrToMCInst.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/MCInstLower/lowerMachineInstrToMCInst.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2b5ff6b81c894f20f1d1f66973d1c9c51cf5dec5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/MCInstLower/lowerMachineInstrToMCInst.cpp @@ -0,0 +1,78 @@ +void llvm::LowerRISCVMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, const AsmPrinter &AP) { + const RISCVVPseudosTable::PseudoInfo *RVV = RISCVVPseudosTable::getPseudoInfo(MI->getOpcode()); + if (!RVV) { + return false; + } + OutMI.setOpcode(RVV->BaseInstr); + const MachineBasicBlock *MBB = MI->getParent(); + assert(MBB && "MI expected to be in a basic block"); + const MachineFunction *MF = MBB->getParent(); + assert(MF && "MBB expected to be in a machine function"); + const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo(); + assert(TRI && "TargetRegisterInfo expected"); + uint64_t TSFlags = MI->getDesc().TSFlags; + int NumOps = MI->getNumExplicitOperands(); + for (const MachineOperand &MO : MI->explicit_operands()) { + int OpNo = (int)MI->getOperandNo(&MO); + assert(OpNo >= 0 && "Operand number doesn't fit in an 'int' type"); + if ((TSFlags & RISCVII::HasVLOpMask) && OpNo == (NumOps - 2)) { + continue; + } + if ((TSFlags & RISCVII::HasSEWOpMask) && OpNo == (NumOps - 1)) { + continue; + } + if ((TSFlags & RISCVII::HasMergeOpMask) && OpNo == 1) { + assert(MI->getNumExplicitDefs() == 1); + continue; + } + MCOperand MCOp; + switch (MO.getType()) { + default: + llvm_unreachable("Unknown operand type"); + case MachineOperand::MO_Register: { + unsigned Reg = MO.getReg(); + if (RISCV::VRM2RegClass.contains(Reg) || RISCV::VRM4RegClass.contains(Reg) || RISCV::VRM8RegClass.contains(Reg)) { + Reg = TRI->getSubReg(Reg, RISCV::sub_vrm1_0); + assert(Reg && "Subregister does not exist"); + } + else if (RISCV::FPR16RegClass.contains(Reg)) { + Reg = TRI->getMatchingSuperReg(Reg, RISCV::sub_16, &RISCV::FPR32RegClass); + assert(Reg && "Subregister does not exist"); + } + else if (RISCV::FPR64RegClass.contains(Reg)) { + Reg = TRI->getSubReg(Reg, RISCV::sub_32); + assert(Reg && "Superregister does not exist"); + } + MCOp = MCOperand::createReg(Reg); + break; + } + case MachineOperand::MO_Immediate: + MCOp = MCOperand::createImm(MO.getImm()); + break; + } + OutMI.addOperand(MCOp); + } + if (TSFlags & RISCVII::HasDummyMaskOpMask) { + OutMI.addOperand(MCOperand::createReg(RISCV::NoRegister)); + } + return true; + OutMI.setOpcode(MI->getOpcode()); + for (const MachineOperand &MO : MI->operands()) { + MCOperand MCOp; + if (LowerRISCVMachineOperandToMCOperand(MO, MCOp, AP)) { + OutMI.addOperand(MCOp); + } + } + if (OutMI.getOpcode() == RISCV::PseudoReadVLENB) { + OutMI.setOpcode(RISCV::CSRRS); + OutMI.addOperand(MCOperand::createImm(RISCVSysReg::lookupSysRegByName("VLENB")->Encoding)); + OutMI.addOperand(MCOperand::createReg(RISCV::X0)); + return; + } + if (OutMI.getOpcode() == RISCV::PseudoReadVL) { + OutMI.setOpcode(RISCV::CSRRS); + OutMI.addOperand(MCOperand::createImm(RISCVSysReg::lookupSysRegByName("VL")->Encoding)); + OutMI.addOperand(MCOperand::createReg(RISCV::X0)); + return; + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/MCInstLower/lowerMachineOperandToMCOperand.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/MCInstLower/lowerMachineOperandToMCOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e3449796f21b6124dd5bde5e2cc45d1b32c568cb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/MCInstLower/lowerMachineOperandToMCOperand.cpp @@ -0,0 +1,37 @@ +bool llvm::LowerRISCVMachineOperandToMCOperand(const MachineOperand &MO, MCOperand &MCOp, const AsmPrinter &AP) { + switch (MO.getType()) { + case MachineOperand::MO_Register: + if (MO.isImplicit()) + return false; + MCOp = MCOperand::createReg(MO.getReg()); + break; + case MachineOperand::MO_RegisterMask: + return false; + case MachineOperand::MO_Immediate: + MCOp = MCOperand::createImm(MO.getImm()); + break; + case MachineOperand::MO_MachineBasicBlock: + MCOp = lowerSymbolOperand(MO, MO.getMBB()->getSymbol(), AP); + break; + case MachineOperand::MO_GlobalAddress: + MCOp = lowerSymbolOperand(MO, AP.getSymbol(MO.getGlobal()), AP); + break; + case MachineOperand::MO_BlockAddress: + MCOp = lowerSymbolOperand( + MO, AP.GetBlockAddressSymbol(MO.getBlockAddress()), AP); + break; + case MachineOperand::MO_ExternalSymbol: + MCOp = lowerSymbolOperand( + MO, AP.GetExternalSymbolSymbol(MO.getSymbolName()), AP); + break; + case MachineOperand::MO_ConstantPoolIndex: + MCOp = lowerSymbolOperand(MO, AP.GetCPISymbol(MO.getIndex()), AP); + break; + case MachineOperand::MO_JumpTableIndex: + MCOp = lowerSymbolOperand(MO, AP.GetJTISymbol(MO.getIndex()), AP); + break; + default: + report_fatal_error("LowerRISCVMachineInstrToMCInst: unknown operand type"); + } + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/MCInstLower/lowerSymbolOperand.cpp b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/MCInstLower/lowerSymbolOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8107e367a395520aca9a0bde41ed05df30ad152a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/RISCV/Selection/MCInstLower/lowerSymbolOperand.cpp @@ -0,0 +1,55 @@ +static MCOperand lowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym, const AsmPrinter &AP) { + MCContext &Ctx = AP.OutContext; + RISCVMCExpr::VariantKind Kind; + switch (MO.getTargetFlags()) { + default: + llvm_unreachable("Unknown target flag on GV operand"); + case RISCVII::MO_None: + Kind = RISCVMCExpr::VK_RISCV_None; + break; + case RISCVII::MO_CALL: + Kind = RISCVMCExpr::VK_RISCV_CALL; + break; + case RISCVII::MO_PLT: + Kind = RISCVMCExpr::VK_RISCV_CALL_PLT; + break; + case RISCVII::MO_LO: + Kind = RISCVMCExpr::VK_RISCV_LO; + break; + case RISCVII::MO_HI: + Kind = RISCVMCExpr::VK_RISCV_HI; + break; + case RISCVII::MO_PCREL_LO: + Kind = RISCVMCExpr::VK_RISCV_PCREL_LO; + break; + case RISCVII::MO_PCREL_HI: + Kind = RISCVMCExpr::VK_RISCV_PCREL_HI; + break; + case RISCVII::MO_GOT_HI: + Kind = RISCVMCExpr::VK_RISCV_GOT_HI; + break; + case RISCVII::MO_TPREL_LO: + Kind = RISCVMCExpr::VK_RISCV_TPREL_LO; + break; + case RISCVII::MO_TPREL_HI: + Kind = RISCVMCExpr::VK_RISCV_TPREL_HI; + break; + case RISCVII::MO_TPREL_ADD: + Kind = RISCVMCExpr::VK_RISCV_TPREL_ADD; + break; + case RISCVII::MO_TLS_GOT_HI: + Kind = RISCVMCExpr::VK_RISCV_TLS_GOT_HI; + break; + case RISCVII::MO_TLS_GD_HI: + Kind = RISCVMCExpr::VK_RISCV_TLS_GD_HI; + break; + } + const MCExpr *ME = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, Ctx); + if (!MO.isJTI() && !MO.isMBB() && MO.getOffset()) { + ME = MCBinaryExpr::createAdd(ME, MCConstantExpr::create(MO.getOffset(), Ctx), Ctx); + } + if (Kind != RISCVMCExpr::VK_RISCV_None) { + ME = RISCVMCExpr::create(ME, Kind, Ctx); + } + return MCOperand::createExpr(ME); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Allocation/RegisterInfo/RegisterInfo.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Allocation/RegisterInfo/RegisterInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d1fecc2d20536c3dae5be4e142bf11df8ead83b6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Allocation/RegisterInfo/RegisterInfo.cpp @@ -0,0 +1,2 @@ +XCoreRegisterInfo::XCoreRegisterInfo(const TargetInstrInfo &tii) : XCoreGenRegisterInfo(XCore::LR), TII(tii) { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Allocation/RegisterInfo/eliminateCallFramePseudoInstr.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Allocation/RegisterInfo/eliminateCallFramePseudoInstr.cpp new file mode 100644 index 0000000000000000000000000000000000000000..beefb6fa7ec0a0e779bd878d95065fa651872221 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Allocation/RegisterInfo/eliminateCallFramePseudoInstr.cpp @@ -0,0 +1,123 @@ +void XCoreRegisterInfo::eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const { + const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); + if (!TFI->hasReservedCallFrame(MF)) { + MachineInstr *Old = I; + uint64_t Amount = Old->getOperand(0).getImm(); + if (Amount != 0) { + unsigned Align = TFI->getStackAlignment(); + Amount = (Amount+Align-1)/Align*Align; + assert(Amount%4 == 0); + Amount /= 4; + bool isU6 = isImmU6(Amount); + if (!isU6 && !isImmU16(Amount)) { +#ifndef NDEBUG + errs() << "eliminateCallFramePseudoInstr size too big: " << Amount << "\n"; +#endif + llvm_unreachable(0); + } + MachineInstr *New; + if (Old->getOpcode() == XCore::ADJCALLSTACKDOWN) { + New=BuildMI(MF, Old->getDebugLoc(), TII.get(XCore::STACKUP)); + MBB.insert(I, New); + XCoreFunctionInfo *XFI = MF.getInfo(); + unsigned XCoreFunctionInfo::addStackExpression(const SDValue &Size) { + StackNode *words; + if (Val.getOpcode() != ISD::SHL) + return false; + if (const ConstantSDNode *CSDN = dyn_cast(Val.getOperand(1))) { + return CSDN->getConstantIntValue()->getZExtValue() == amount; + } + if ((Size, 2)) { + words = (Size.getNode()->getOperand(0).getNode()); + switch (N->getOpcode()) { + case ISD::ADD: + return new STBinOp(makeExpression(N->getOperand(0).getNode()), + makeExpression(N->getOperand(1).getNode()), STBinOp::STBinOpADD); + case ISD::SUB: + return new STBinOp(makeExpression(N->getOperand(0).getNode()), + makeExpression(N->getOperand(1).getNode()), STBinOp::STBinOpSUB); + case ISD::Constant: + if (const ConstantSDNode *CSDN = dyn_cast(N)) { + return new STInt(CSDN->getConstantIntValue()->getZExtValue()); + } + break; + case ISD::TargetExternalSymbol: + if (const ExternalSymbolSDNode *ES = + dyn_cast(N)) { + return new STString(ES->getSymbol()); + } + break; + case ISD::SHL: + return new STBinOp(makeExpression(N->getOperand(0).getNode()), + makeExpression(N->getOperand(1).getNode()), STBinOp::STBinOpSHL); + case ISD::OR: + return new STBinOp(makeExpression(N->getOperand(0).getNode()), + makeExpression(N->getOperand(1).getNode()), STBinOp::STBinOpOR); + case ISD::MUL: + return new STBinOp(makeExpression(N->getOperand(0).getNode()), + makeExpression(N->getOperand(1).getNode()), STBinOp::STBinOpMUL); + case ISD::AND: + return new STBinOp(makeExpression(N->getOperand(0).getNode()), + makeExpression(N->getOperand(1).getNode()), STBinOp::STBinOpAND); + case XCoreISD::ABS16Wrapper: + return makeExpression(N->getOperand(0).getNode()); + } + return new STUDef(); + } + else { + StackNode *bytes = (Size.getNode()); + switch (N->getOpcode()) { + case ISD::ADD: + return new STBinOp(makeExpression(N->getOperand(0).getNode()), + makeExpression(N->getOperand(1).getNode()), STBinOp::STBinOpADD); + case ISD::SUB: + return new STBinOp(makeExpression(N->getOperand(0).getNode()), + makeExpression(N->getOperand(1).getNode()), STBinOp::STBinOpSUB); + case ISD::Constant: + if (const ConstantSDNode *CSDN = dyn_cast(N)) { + return new STInt(CSDN->getConstantIntValue()->getZExtValue()); + } + break; + case ISD::TargetExternalSymbol: + if (const ExternalSymbolSDNode *ES = + dyn_cast(N)) { + return new STString(ES->getSymbol()); + } + break; + case ISD::SHL: + return new STBinOp(makeExpression(N->getOperand(0).getNode()), + makeExpression(N->getOperand(1).getNode()), STBinOp::STBinOpSHL); + case ISD::OR: + return new STBinOp(makeExpression(N->getOperand(0).getNode()), + makeExpression(N->getOperand(1).getNode()), STBinOp::STBinOpOR); + case ISD::MUL: + return new STBinOp(makeExpression(N->getOperand(0).getNode()), + makeExpression(N->getOperand(1).getNode()), STBinOp::STBinOpMUL); + case ISD::AND: + return new STBinOp(makeExpression(N->getOperand(0).getNode()), + makeExpression(N->getOperand(1).getNode()), STBinOp::STBinOpAND); + case XCoreISD::ABS16Wrapper: + return makeExpression(N->getOperand(0).getNode()); + } + return new STUDef(); + words = new STBinOp(bytes, new STInt(2), STBinOp::STBinOpSHR); + } + AllocaExpressions.push_back(words); + i = AllocaExpressions.size() - 1; + New=BuildMI(MF, Old->getDebugLoc(), TII.get(XCore::ALLOCA)).addImm(i); + MBB.insert(I, New); + int Opcode = isU6 ? XCore::EXTSP_u6 : XCore::EXTSP_lu6; + New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode)).addImm(Amount); + } + else { + assert(Old->getOpcode() == XCore::ADJCALLSTACKUP); + int Opcode = isU6 ? XCore::LDAWSP_ru6_RRegs : XCore::LDAWSP_lru6_RRegs; + New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode), XCore::SP).addImm(Amount); + MBB.insert(I, New); + New=BuildMI(MF, Old->getDebugLoc(), TII.get(XCore::STACKDOWN)); + } + MBB.insert(I, New); + } + } + MBB.erase(I); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Allocation/RegisterInfo/eliminateFrameIndex.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Allocation/RegisterInfo/eliminateFrameIndex.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fe7af47b9159a50bd28eefbf11bb92c631e33c0e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Allocation/RegisterInfo/eliminateFrameIndex.cpp @@ -0,0 +1,109 @@ +void XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, RegScavenger *RS) const { + assert(SPAdj == 0 && "Unexpected"); + MachineInstr &MI = *II; + DebugLoc dl = MI.getDebugLoc(); + unsigned i = 0; + while (!MI.getOperand(i).isFI()) { + ++i; + assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); + } + MachineOperand &FrameOp = MI.getOperand(i); + int FrameIndex = FrameOp.getIndex(); + MachineFunction &MF = *MI.getParent()->getParent(); + const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); + int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex); + int StackSize = MF.getFrameInfo()->getStackSize(); + #ifndef NDEBUG + DEBUG(errs() << "\nFunction : " << MF.getFunction()->getName() << "\n"); + DEBUG(errs() << "<--------->\n"); + DEBUG(MI.print(errs())); + DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n"); + DEBUG(errs() << "FrameOffset : " << Offset << "\n"); + DEBUG(errs() << "StackSize : " << StackSize << "\n"); + #endif + Offset += StackSize; + unsigned FrameReg = getFrameRegister(MF); + if (MI.isDebugValue()) { + MI.getOperand(i).ChangeToRegister(FrameReg, false); + MI.getOperand(i+1).ChangeToImmediate(Offset); + return; + } + Offset += MI.getOperand(i + 1).getImm(); + MI.getOperand(i + 1).ChangeToImmediate(0); + assert(Offset%4 == 0 && "Misaligned stack offset"); + DEBUG(errs() << "Offset : " << Offset << "\n" << "<--------->\n"); + Offset/=4; + bool FP = TFI->hasFP(MF); + unsigned Reg = MI.getOperand(0).getReg(); + bool isKill = MI.getOpcode() == XCore::STWFI && MI.getOperand(0).isKill(); + assert(XCore::GRRegsRegisterClass->contains(Reg) && "Unexpected register operand"); + MachineBasicBlock &MBB = *MI.getParent(); + if (FP) { + bool isUs = isImmUs(Offset); + if (!isUs) { + if (!RS) + report_fatal_error("eliminateFrameIndex Frame size too big: " + Twine(Offset)); + assert(RS && "Register scavenging must be on"); + unsigned Reg = RS->FindUnusedReg(RC); + if (Reg == 0) + Reg = RS->scavengeRegister(RC, II, SPAdj); + unsigned ScratchReg = Reg; + if (!isImmU16(Value)) { + report_fatal_error("loadConstant value too big " + Twine(Value)); + } + int Opcode = isImmU6(Value) ? XCore::LDC_ru6 : XCore::LDC_lru6; + BuildMI(MBB, I, dl, TII.get(Opcode), DstReg).addImm(Value); + switch (MI.getOpcode()) { + case XCore::LDWFI: + BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg).addReg(FrameReg).addReg(ScratchReg, RegState::Kill); + break; + case XCore::STWFI: + BuildMI(MBB, II, dl, TII.get(XCore::STW_l3r)).addReg(Reg, getKillRegState(isKill)).addReg(FrameReg).addReg(ScratchReg, RegState::Kill); + break; + case XCore::LDAWFI: + BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg).addReg(FrameReg).addReg(ScratchReg, RegState::Kill); + break; + default: + llvm_unreachable("Unexpected Opcode"); + } + } + else { + switch (MI.getOpcode()) { + case XCore::LDWFI: + BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg).addReg(FrameReg).addImm(Offset); + break; + case XCore::STWFI: + BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus)).addReg(Reg, getKillRegState(isKill)).addReg(FrameReg).addImm(Offset); + break; + case XCore::LDAWFI: + BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg).addReg(FrameReg).addImm(Offset); + break; + default: + llvm_unreachable("Unexpected Opcode"); + } + } + } + else { + bool isU6 = isImmU6(Offset); + if (!isU6 && !isImmU16(Offset)) + report_fatal_error("eliminateFrameIndex Frame size too big: " + Twine(Offset)); + switch (MI.getOpcode()) { + int NewOpcode; + case XCore::LDWFI: + NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6; + BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg).addImm(Offset); + break; + case XCore::STWFI: + NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6; + BuildMI(MBB, II, dl, TII.get(NewOpcode)).addReg(Reg, getKillRegState(isKill)).addImm(Offset); + break; + case XCore::LDAWFI: + NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6; + BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg).addImm(Offset); + break; + default: + llvm_unreachable("Unexpected Opcode"); + } + } + MBB.erase(II); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Allocation/RegisterInfo/getArgRegs.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Allocation/RegisterInfo/getArgRegs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fd2da3ecadfcde45a0b19c27fbed158ce7788d37 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Allocation/RegisterInfo/getArgRegs.cpp @@ -0,0 +1,3 @@ +const unsigned * XCoreRegisterInfo::getArgRegs(const MachineFunction *MF) { + return XCore_ArgRegs; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Allocation/RegisterInfo/getCalleeSavedRegs.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Allocation/RegisterInfo/getCalleeSavedRegs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7be2eba241c9c89dce26398f6f73df693f03c906 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Allocation/RegisterInfo/getCalleeSavedRegs.cpp @@ -0,0 +1,13 @@ +const unsigned* XCoreRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { + bool callsEHReturn = false; + if (MF) { + callsEHReturn = MF->getMMI().callsEHReturn(); + } + static const unsigned CalleeSavedRegs[] = { + XCore::R4, XCore::R5, XCore::R6, XCore::R7, XCore::R8, XCore::R9, XCore::R10, XCore::LR, 0 + }; + static const unsigned CalleeSavedRegsEHRet[] = { + XCore::R0, XCore::R1, XCore::R4, XCore::R5, XCore::R6, XCore::R7, XCore::R8, XCore::R9, XCore::R10, XCore::LR, 0 + }; + return callsEHReturn ? CalleeSavedRegsEHRet : CalleeSavedRegs; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Allocation/RegisterInfo/getFrameRegister.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Allocation/RegisterInfo/getFrameRegister.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b312e1f78d40b38ae95e510414363cb177cafdbf --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Allocation/RegisterInfo/getFrameRegister.cpp @@ -0,0 +1,4 @@ +unsigned XCoreRegisterInfo::getFrameRegister(const MachineFunction &MF) const { + const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); + return TFI->hasFP(MF) ? XCore::R10 : XCore::SP; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Allocation/RegisterInfo/getNumArgRegs.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Allocation/RegisterInfo/getNumArgRegs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..177f4cec251f21e8cf8c999bcb80ba83b4c1207d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Allocation/RegisterInfo/getNumArgRegs.cpp @@ -0,0 +1,3 @@ +unsigned XCoreRegisterInfo::getNumArgRegs(const MachineFunction *MF) { + return array_lengthof(XCore_ArgRegs); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Allocation/RegisterInfo/getReservedRegs.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Allocation/RegisterInfo/getReservedRegs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b0cf02377dda3af3ebfd8f92f46d8cdbc99d5c05 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Allocation/RegisterInfo/getReservedRegs.cpp @@ -0,0 +1,12 @@ +BitVector XCoreRegisterInfo::getReservedRegs(const MachineFunction &MF) const { + BitVector Reserved(getNumRegs()); + const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); + Reserved.set(XCore::CP); + Reserved.set(XCore::DP); + Reserved.set(XCore::SP); + Reserved.set(XCore::LR); + if (TFI->hasFP(MF)) { + Reserved.set(XCore::R10); + } + return Reserved; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Allocation/RegisterInfo/needsFrameMoves.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Allocation/RegisterInfo/needsFrameMoves.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6770ef7307bcca2808611b1bc34ed8cb898bd427 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Allocation/RegisterInfo/needsFrameMoves.cpp @@ -0,0 +1,3 @@ +bool XCoreRegisterInfo::needsFrameMoves(const MachineFunction &MF) { + return MF.getMMI().hasDebugInfo() || !MF.getFunction()->doesNotThrow(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Allocation/RegisterInfo/processFunctionBeforeFrameFinalized.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Allocation/RegisterInfo/processFunctionBeforeFrameFinalized.cpp new file mode 100644 index 0000000000000000000000000000000000000000..444a05f1b97eada860699df7a40184073d04d064 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Allocation/RegisterInfo/processFunctionBeforeFrameFinalized.cpp @@ -0,0 +1,2 @@ +void XCoreRegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Allocation/RegisterInfo/requiresRegisterScavenging.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Allocation/RegisterInfo/requiresRegisterScavenging.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b6f9252a5fd0031a96e24ebb87cbdc0bc1480a4d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Allocation/RegisterInfo/requiresRegisterScavenging.cpp @@ -0,0 +1,4 @@ +bool XCoreRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const { + const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); + return TFI->hasFP(MF); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Allocation/RegisterInfo/useFPForScavengingIndex.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Allocation/RegisterInfo/useFPForScavengingIndex.cpp new file mode 100644 index 0000000000000000000000000000000000000000..64ca571c936d039e9021bbfdbfffa7fad53b94d0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Allocation/RegisterInfo/useFPForScavengingIndex.cpp @@ -0,0 +1,3 @@ +bool XCoreRegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const { + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/AsmPrinter.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/AsmPrinter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..614ec59329d9523a9136dafa94481eb9c215eeab --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/AsmPrinter.cpp @@ -0,0 +1,2 @@ +explicit XCoreAsmPrinter(TargetMachine &TM, MCStreamer &Streamer) : AsmPrinter(TM, Streamer), XTAPrinter(OutStreamer, OutContext, this), RUW(Streamer, this), Subtarget(TM.getSubtarget()) { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/EmitBasicBlockStart.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/EmitBasicBlockStart.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4f92dd4593d9f96d1032a6950fba0458ec177e96 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/EmitBasicBlockStart.cpp @@ -0,0 +1,14 @@ +void XCoreAsmPrinter::EmitBasicBlockStart(const MachineBasicBlock *MBB) { + AsmPrinter::EmitBasicBlockStart(MBB); + if(DisableXtaInfo) + return; + CFMDNode *cfmd = MBB->getCFMetadata(); + if (!cfmd) + return; + MDNode *md = cfmd->getMetadata(); + if (!md) + return; + MCSymbol *SetLabel = asmPrinter->GetTempSymbol("xtalabel", LabelCounter++); + OutStreamer.EmitLabel(SetLabel); + xtaAsm_XtaLabels.push_back(std::make_pair(SetLabel, md)); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/EmitConstantPool.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/EmitConstantPool.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a2f476452106d8caefd30bd77be3bb50aa2633e7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/EmitConstantPool.cpp @@ -0,0 +1,32 @@ +void XCoreAsmPrinter::EmitConstantPool() { + const MachineConstantPool *MCP = MF->getConstantPool(); + const std::vector &CP = MCP->getConstants(); + if (CP.empty()) + return; + for (unsigned i = 0, e = CP.size(); i != e; ++i) { + const MachineConstantPoolEntry &CPE = CP[i]; + unsigned Align = CPE.getAlignment(); + SectionKind Kind; + switch (TM.getTargetData()->getTypeAllocSize(CPE.getType())) { + case 4: Kind = SectionKind::getMergeableConst4(); + break; + case 8: Kind = SectionKind::getMergeableConst8(); + break; + case 16: Kind = SectionKind::getMergeableConst16(); + break; + default: Kind = SectionKind::getMergeableConst(); + break; + } + const MCSection *S = getObjFileLowering().getSectionForConstant(Kind); + MCSymbol *Sym = GetCPISymbol(i); + OutStreamer.SwitchSection(S); + OutStreamer.EmitRawText("\t.cc_top " + Twine(Sym->getName()) + ".data"); + EmitAlignment(Log2_32(Align)); + OutStreamer.EmitLabel(Sym); + if (CPE.isMachineConstantPoolEntry()) + EmitMachineConstantPoolValue(CPE.Val.MachineCPVal); + else + EmitGlobalConstant(CPE.Val.ConstVal); + OutStreamer.EmitRawText("\t.cc_bottom " + Twine(Sym->getName()) + ".data"); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/EmitFunctionEntryLabel.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/EmitFunctionEntryLabel.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1ad2dfc0dad8ec4de360e69f3500fff19994aca5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/EmitFunctionEntryLabel.cpp @@ -0,0 +1,7 @@ +void XCoreAsmPrinter::EmitFunctionEntryLabel() { + td::set::const_iterator iter = XtaTaskStart.find(&F); + if (iter == XtaTaskStart.end()) { + OutStreamer.EmitRawText(StringRef("\t.xtataskstart")); + } + OutStreamer.EmitLabel(CurrentFnSym); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/EmitGlobalVariable.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/EmitGlobalVariable.cpp new file mode 100644 index 0000000000000000000000000000000000000000..05ee45deb6957993ce98c0f4421aa68aa29cb9da --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/EmitGlobalVariable.cpp @@ -0,0 +1,51 @@ +void XCoreAsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) { + if (!GV->hasInitializer() || EmitSpecialXCoreGlobal(GV) || + EmitSpecialLLVMGlobal(GV)) + return; + const TargetData *TD = TM.getTargetData(); + OutStreamer.SwitchSection(getObjFileLowering().SectionForGlobal(GV, Mang,TM)); + MCSymbol *GVSym = Mang->getSymbol(GV); + const Constant *C = GV->getInitializer(); + unsigned Align = (unsigned)TD->getPreferredTypeAlignmentShift(C->getType()); + OutStreamer.EmitRawText("\t.cc_top " + Twine(GVSym->getName()) + ".data"); + switch (GV->getLinkage()) { + case GlobalValue::AppendingLinkage: + report_fatal_error("AppendingLinkage is not supported by this target!"); + case GlobalValue::LinkOnceAnyLinkage: + case GlobalValue::LinkOnceODRLinkage: + case GlobalValue::WeakAnyLinkage: + case GlobalValue::WeakODRLinkage: + case GlobalValue::ExternalLinkage: + emitArrayBound(GVSym, GV); + OutStreamer.EmitSymbolAttribute(GVSym, MCSA_Global); + if (GV->hasWeakLinkage() || GV->hasLinkOnceLinkage()) + OutStreamer.EmitSymbolAttribute(GVSym, MCSA_Weak); + case GlobalValue::InternalLinkage: + case GlobalValue::PrivateLinkage: + break; + case GlobalValue::DLLImportLinkage: + llvm_unreachable("DLLImport linkage is not supported by this target!"); + case GlobalValue::DLLExportLinkage: + llvm_unreachable("DLLExport linkage is not supported by this target!"); + default: + llvm_unreachable("Unknown linkage type!"); + } + EmitAlignment(Align > 2 ? Align : 2, GV); + unsigned Size = TD->getTypeAllocSize(C->getType()); + if (GV->isThreadLocal()) { + Size *= MaxCores; + } + if (MAI->hasDotTypeDotSizeDirective()) { + OutStreamer.EmitSymbolAttribute(GVSym, MCSA_ELF_TypeObject); + OutStreamer.EmitRawText("\t.size " + Twine(GVSym->getName()) + "," + Twine(Size)); + } + OutStreamer.EmitLabel(GVSym); + EmitGlobalConstant(C); + if (GV->isThreadLocal()) { + for (unsigned i = 1; i < MaxCores; ++i) + EmitGlobalConstant(C); + } + if (Size < 4) + OutStreamer.EmitZeros(4 - Size, 0); + OutStreamer.EmitRawText("\t.cc_bottom " + Twine(GVSym->getName()) + ".data"); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/EmitInstruction.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/EmitInstruction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d75867435e9b65cda890b3fad8d01691670e61e9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/EmitInstruction.cpp @@ -0,0 +1,68 @@ +void XCoreAsmPrinter::EmitInstruction(const MachineInstr *MI) { + SmallString<128> Str; + raw_svector_ostream O(Str); + if(!DisableXtaInfo) { + DebugLoc DL = MI->getDebugLoc(); + MDNode *xtaCall = DL.getXtaCall(); + if (xtaCall && isValidCallInstruction(MI)) { + MCSymbol *SetLabel = asmPrinter->GetTempSymbol("xta.call_labels", CallCounter++); + OutStreamer.EmitLabel(SetLabel); + xtaAsm_CallLabels.push_back(std::make_pair(SetLabel, xtaCall)); + } + MDNode *xtaEndpoint = DL.getXtaEndpoint(); + if (xtaEndpoint && isValidEndpointInstruction(MI)) { + MCSymbol *SetLabel = asmPrinter->GetTempSymbol("xta.endpoint_labels", EPCounter++); + OutStreamer.EmitLabel(SetLabel); + xtaAsm_EndpointLabels.push_back(std::make_pair(SetLabel, xtaEndpoint)); + } + const XCoreFunctionInfo *XFI = MI->getParent()->getParent()->getInfo(); + if (MI->getOpcode() == XCore::LOOPMARKER) { + unsigned index = MI->getOperand(0).getImm(); + unsigned type = 0; + MDNode *xtaMD=0; + XFI->getLoopMetadata(index, &xtaMD, type); + unsigned loopLabelKind = MI->getParent()->getParent()->getFunction()->getParent()->getMDKindID("xta.loop_labels"); + unsigned loopKind = MI->getParent()->getParent()->getFunction()->getParent()->getMDKindID("xta.loop"); + if(type == loopLabelKind){ + MCSymbol *SetLabel = asmPrinter->GetTempSymbol("xta.loop_labels", LoopCounter++); + OutStreamer.EmitLabel(SetLabel); + xtaAsm_LoopLabels.push_back(std::make_pair(SetLabel, xtaMD)); + } else if(type == loopKind){ + ConstantInt *iterations = dyn_cast(xtaMD->getOperand(0)); + if (!iterations) + report_fatal_error("Incorrectly formatted XTA loop metadata"); + OutStreamer.EmitRawText(".xtaloop " + Twine(iterations->getZExtValue())); + } + } + } + switch (MI->getOpcode()) { + case XCore::DBG_VALUE: { + if (isVerbose() && OutStreamer.hasRawTextSupport()) { + SmallString<128> TmpStr; + raw_svector_ostream OS(TmpStr); + unsigned NOps = MI->getNumOperands(); + assert(NOps == 4); + OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: "; + DIVariable V(const_cast(MI->getOperand(NOps-1).getMetadata())); + OS << V.getName(); + OS << " <- "; + assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm()); + OS << '['; printOperand(MI, 0, OS); OS << '+'; printOperand(MI, 1, OS); + OS << ']'; + OS << "+"; + printOperand(MI, NOps-2, OS); + OutStreamer.EmitRawText(StringRef(OS.str())); + } + return; + } + case XCore::ADD_2rus: + if (MI->getOperand(2).getImm() == 0) { + O << "\tmov " << getRegisterName(MI->getOperand(0).getReg()) << ", " << getRegisterName(MI->getOperand(1).getReg()); + OutStreamer.EmitRawText(O.str()); + return; + } + break; + } + printInstruction(MI, O); + OutStreamer.EmitRawText(O.str()); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/LLVMInitializeAsmPrinter.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/LLVMInitializeAsmPrinter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..03364ca397dcf00e6539c69b81c8e23af7075c63 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/LLVMInitializeAsmPrinter.cpp @@ -0,0 +1,3 @@ +extern "C" void LLVMInitializeXCoreAsmPrinter() { + RegisterAsmPrinter X(TheXCoreTarget); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/PrintAsmMemoryOperand.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/PrintAsmMemoryOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..eddc670de9198a1c0e6dd410b6cbd81ab192f00b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/PrintAsmMemoryOperand.cpp @@ -0,0 +1,10 @@ +bool XCoreAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, const char *ExtraCode, raw_ostream &O) { + if (ExtraCode && ExtraCode[0]) { + return true; + } + printOperand(MI, OpNo, O); + O << '['; + printMemOperand(MI, OpNo + 1, O); + O << ']'; + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/PrintAsmOperand.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/PrintAsmOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4c48fa026e377f2b055e6f2cb0d15c7ce3afa56a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/PrintAsmOperand.cpp @@ -0,0 +1,4 @@ +bool XCoreAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo unsigned AsmVariant,const char *ExtraCode, raw_ostream &O) { + printOperand(MI, OpNo, O); + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/PrintSpecial.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/PrintSpecial.cpp new file mode 100644 index 0000000000000000000000000000000000000000..32f3f9af9873e2792df3467f1dab342cd6065f82 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/PrintSpecial.cpp @@ -0,0 +1,44 @@ +void XCoreAsmPrinter::PrintSpecial(const MachineInstr *MI, raw_ostream &OS, const char *Code) const { + if (strcmp(Code, "xtabranch") == 0) { + if (DisableXtaInfo) + return; + static unsigned Counter = 0; + unsigned EntrySize; + if (MI->getOpcode() == XCore::WAITEU_0R) { + const MachineBasicBlock *MBB = MI->getParent(); + OS << "\n\t.xtabranch"; + for (MachineBasicBlock::const_succ_iterator MBBiter = MBB->succ_begin(), E = MBB->succ_end(); MBBiter != E; ++MBBiter) { + if (MBBiter != MBB->succ_begin()) + OS << ","; + OS << " "; (*MBBiter)->getSymbol()->print(OS); + } + OS << "\n"; + return; + } + if (MI->getOpcode() == XCore::BR_JT) { + EntrySize = 2; + } + else { + assert(MI->getOpcode() == XCore::BR_JT32); + EntrySize = 4; + } + OS << "\n\t.xtabranch "; + unsigned JTI = MI->getOperand(0).getIndex(); + const MachineFunction *MF = MI->getParent()->getParent(); + const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo(); + const std::vector &JT = MJTI->getJumpTables(); + unsigned NumEntries = JT[JTI].MBBs.size(); + unsigned Offset = 2; + for (unsigned i = 0; i < NumEntries; i++) { + if (i != 0) + OS << ","; + OS << ".Ljumptable" << Counter << "+" << Offset; + Offset += EntrySize; + } + OS << "\n.Ljumptable" << Counter << ":\n\t\t"; + Counter++; + } + else { + AsmPrinter::PrintSpecial(MI, OS, Code); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/emitEndOfAsmFile.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/emitEndOfAsmFile.cpp new file mode 100644 index 0000000000000000000000000000000000000000..190920cbac038be92e3328237eb036d0ebacc938 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/emitEndOfAsmFile.cpp @@ -0,0 +1,648 @@ +void XCoreAsmPrinter::EmitEndOfAsmFile(Module &M) { + SmallString<32> NameBuf; + SmallSetVector WeakReferences; + for (Module::const_iterator I = M.begin(), E = M.end(); I != E; ++I) { + if (I->hasName() && !I->isIntrinsic()) { + std::map::const_iterator iter = + TypeStrings.find(&GV); + if (iter == TypeStrings.end()) { + return 0; + } + const std::string *TypeString = &iter->second; + if (TypeString) { + NameBuf.clear(); + Mang->getNameWithPrefix(NameBuf, I, false); + OutStreamer.EmitRawText("\t.typestring " + Twine(NameBuf) + ", \"" + Twine(*TypeString) + "\""); + } + std::map::const_iterator iter = OverlayInfo.find(&GV); + if (iter == OverlayInfo.end()) { + return 0; + } + const std::string *OverlayName = &iter->second; + if (OverlayName) { + NameBuf.clear(); + Mang->getNameWithPrefix(NameBuf, I, false); + if (OverlayName->empty()) { + OutStreamer.EmitRawText("\t.overlay_root " + Twine(NameBuf)); + } + else { + OutStreamer.EmitRawText("\t.overlay_root " + Twine(NameBuf) + "," + *OverlayName); + WeakReferences.insert(GetExternalSymbolSymbol(*OverlayName)); + } + } + std::map >::const_iterator iter = OverlayReferenceInfo.find(&GV); + if (iter == OverlayReferenceInfo.end()) { + return 0; + } + const std::vector *OverlayRefs = &iter->second; + if (OverlayRefs) { + for (std::vector::const_iterator R = OverlayRefs->begin(); R != OverlayRefs->end(); ++R) { + const std::string RefName = *R; + NameBuf.clear(); + Mang->getNameWithPrefix(NameBuf, I, false); + OutStreamer.EmitRawText("\t.overlay_reference " + Twine(NameBuf) + "," + RefName); + } + } + } + + for (Module::global_iterator I = M.global_begin(), E = M.global_end(); I != E; ++ I) { + if (I->hasName()) { + std::map::const_iterator iter = OverlayInfo.find(&GV); + if (iter == OverlayInfo.end()) { + return 0; + } + const std::string *TypeString = &iter->second; + if (TypeString) { + NameBuf.clear(); + Mang->getNameWithPrefix(NameBuf, I, false); + OutStreamer.EmitRawText("\t.typestring " + Twine(StringRef(&NameBuf[0], NameBuf.size())) + ", \"" + Twine(*TypeString) + "\""); + } + } + } + for (SmallSetVector::const_iterator I = WeakReferences.begin(), E = WeakReferences.end(); I != E; ++I) { + MCSymbol *Sym = *I; + OutStreamer.EmitSymbolAttribute(Sym, MCSA_Global); + OutStreamer.EmitSymbolAttribute(Sym, MCSA_Weak); + } + if (!DisableXtaInfo) { + const static XCoreXTAPrinter::MarkerSectionInfo callSectionInfo = { + ".xtacall", + ".xtacalltable", + "xta.call_labels", + false + }; + const static XCoreXTAPrinter::MarkerSectionInfo endpointSectionInfo = { + ".xtaendpoint", + ".xtaendpointtable", + "xta.endpoint_labels", + false + }; + const static XCoreXTAPrinter::MarkerSectionInfo labelSectionInfo = { + ".xtalabel", + ".xtalabeltable", + "xta.xta_labels", + true + }; + const static XCoreXTAPrinter::MarkerSectionInfo loopSectionInfo = { + ".xtalooplabel", + ".xtalooplabeltable", + "xta.loop_labels", + true + }; + std::vector lines; + std::vector labels; + std::vector ranges; + for (std::vector >::iterator it = nodes.begin(), e = nodes.end(); it != e; ++it) { + ConstantInt *type = dyn_cast(node->getOperand(0)); + if (!type) + report_fatal_error("Incorrectly formatted XTA label metadata"); + switch (type->getZExtValue()) { + case CFMDNode::CFMD_INLINE: + { + MDNode *child = dyn_cast(node->getOperand(1)); + MDString *s = dyn_cast(node->getOperand(2)); + SmallString<128> lblString; + raw_svector_ostream lbl(lblString); + for (unsigned i = 3, e = node->getNumOperands(); i < e; ++i) { + MDNode *n = dyn_cast(node->getOperand(i)); + MDString *lblName = dyn_cast(n->getOperand(1)); + if (!lbl.str().empty()) + lbl << ","; + lbl << lblName->getString(); + } + SmallString<128> Str; + raw_svector_ostream O(Str); + O << inlineInfo << s->getString(); + if (!lbl.str().empty()){ + O << "(" << lbl.str() << ")"; + } + O << ","; + (child, sym, O.str(), lines, labels, ranges); + break; + } + case CFMDNode::CFMD_AND: + report_fatal_error("Unsupported XTA label metadata type CFMD_AND"); + break; + case CFMDNode::CFMD_OR: + { + for (unsigned i = 1, e = node->getNumOperands(); i != e; ++i) { + MDNode *child = dyn_cast(node->getOperand(i)); + if (!child) + report_fatal_error("Incorrectly formatted XTA label metadata"); + (child, sym, inlineInfo, lines, labels, ranges); + } + break; + } + case CFMDNode::CFMD_LINE: + lines.push_back(XCoreXTAPrinter::LeafInfo(node, sym)); + break; + case CFMDNode::CFMD_LABEL: + labels.push_back(XCoreXTAPrinter::LeafInfo(node, sym, inlineInfo)); + break; + case CFMDNode::CFMD_LINE_RANGE: + ranges.push_back(XCoreXTAPrinter::LeafInfo(node, sym)); + break; + } + } + if (NamedMDNode *namedMarkers = M.getNamedMetadata(sectionInfo.anchorName)) { + for (unsigned i = 0, e = namedMarkers->getNumOperands(); i != e; ++i) { + MDNode *label = namedMarkers->getOperand(i); + markers.push_back(LeafInfo(label, 0)); + } + } + if (markers.empty()) + return; + std::sort(markers.begin(), markers.end(), labelInfoIsLess); + for (std::vector::iterator it = markers.begin(), e = markers.end(); it != e;) { + std::vector::iterator last = it; + ++last; + while (last != e && XTAMetadataLabelNode(it->leaf).getCompDir() == XTAMetadataLabelNode(last->leaf).getCompDir()) + ++last; + MCSymbol *StopLabel = emitSectionHeader(sectionInfo.nameSection, XTA_MARKER_VERSION); + OutStreamer.EmitBytes(XTAMetadataLabelNode(begin->leaf).getCompDir(), 0); // comp_dir. + OutStreamer.EmitBytes(StringRef("\0", 1), 0); + for (std::vector::iterator it = begin; it != end;) { + std::vector::iterator last = it; + ++last; + while (last != end && it->leaf == last->leaf) + ++last; + assert(labelMDNode); + XTAMetadataLabelNode label(labelMDNode); + if (!label.isValid()) + report_fatal_error("Unexpected XTA metadata format"); + OutStreamer.EmitBytes(label.getName(), 0); + OutStreamer.EmitBytes(StringRef("\0", 1), 0); + OutStreamer.EmitBytes(label.getFile(), 0); + OutStreamer.EmitBytes(StringRef("\0", 1), 0); + OutStreamer.EmitIntValue(label.getLineNum(), 4); + if (leafInfoRangeHasSymbol(begin, end)) { + MCSymbol *AddrStartLabel = asmPrinter->GetTempSymbol("addr_start", asmCounter++); + MCSymbol *AddrEndLabel = asmPrinter->GetTempSymbol("addr_end", asmCounter++); + const MCExpr *AddressesSize = MCBinaryExpr::CreateSub(MCSymbolRefExpr::Create(AddrEndLabel, OutContext), MCSymbolRefExpr::Create(AddrStartLabel, OutContext), OutContext); + OutStreamer.EmitValue(AddressesSize, 4); + OutStreamer.EmitLabel(AddrStartLabel); + for (std::vector::iterator it = begin; it != end; ++it) { + MCSymbol *sym = it->sym; + if (!sym) + continue; + OutStreamer.EmitRawText(".cc_top cc_" + Twine(ccCounter) + Twine(",") + sym->getName()); + OutStreamer.EmitValue(MCSymbolRefExpr::Create(sym, OutContext), 4); + OutStreamer.EmitBytes(it->inlineInfo, 0); + OutStreamer.EmitBytes(StringRef("\0", 1), 0); + OutStreamer.EmitRawText(".cc_bottom cc_" + Twine(ccCounter++)); + } + OutStreamer.EmitLabel(AddrEndLabel); + } + else { + OutStreamer.EmitIntValue(0, 4); + } + it = last; + } + OutStreamer.EmitLabel(StopLabel); + it = last; + } + if (sectionInfo.emitLineRanges) { + if (lines.empty()) + return; + std::sort(lines.begin(), lines.end(), lineInfoCompDirIsLess); + for (std::vector::iterator it = lines.begin(), e = lines.end(); + it != e;) { + std::vector::iterator last = it; + ++last; + while (last != e && T(it->leaf).getCompDir() == T(last->leaf).getCompDir()) + ++last; + MCSymbol *StopLabel = emitSectionHeader(sectionInfo.srcSection, XTA_MARKER_TABLE_VERSION); + OutStreamer.EmitBytes(T(begin->leaf).getCompDir(), 0); // comp_dir. + OutStreamer.EmitBytes(StringRef("\0", 1), 0); + for (std::vector::iterator it = begin, e = end; it != e; ++it) { + MCSymbol *sym = lineInfo.sym; + OutStreamer.EmitRawText(".cc_top cc_" + Twine(ccCounter) + Twine(",") + sym->getName()); + OutStreamer.EmitBytes(line.getFile(), 0); + OutStreamer.EmitBytes(StringRef("\0", 1), 0); + OutStreamer.EmitIntValue(line.getLineNum(), 4); + OutStreamer.EmitValue(MCSymbolRefExpr::Create(sym, OutContext), 4); + OutStreamer.EmitRawText(".cc_bottom cc_" + Twine(ccCounter++)); + } + OutStreamer.EmitLabel(StopLabel); + it = last; + } + } + else { + if (lines.empty()) + return; + std::sort(lines.begin(), lines.end(), lineInfoCompDirIsLess); + for (std::vector::iterator it = lines.begin(), e = lines.end(); + it != e;) { + std::vector::iterator last = it; + ++last; + while (last != e && T(it->leaf).getCompDir() == T(last->leaf).getCompDir()) + ++last; + MCSymbol *StopLabel = emitSectionHeader(sectionInfo.srcSection, XTA_MARKER_TABLE_VERSION); + OutStreamer.EmitBytes(T(begin->leaf).getCompDir(), 0); // comp_dir. + OutStreamer.EmitBytes(StringRef("\0", 1), 0); + for (std::vector::iterator it = begin, e = end; it != e; ++it) { + MCSymbol *sym = lineInfo.sym; + OutStreamer.EmitRawText(".cc_top cc_" + Twine(ccCounter) + Twine(",") + sym->getName()); + OutStreamer.EmitBytes(line.getFile(), 0); + OutStreamer.EmitBytes(StringRef("\0", 1), 0); + OutStreamer.EmitIntValue(line.getLineNum(), 4); + OutStreamer.EmitValue(MCSymbolRefExpr::Create(sym, OutContext), 4); + OutStreamer.EmitRawText(".cc_bottom cc_" + Twine(ccCounter++)); + } + OutStreamer.EmitLabel(StopLabel); + it = last; + } + } + std::vector::iterator last = it; + ++last; + while (last != e && XTAMetadataLabelNode(it->leaf).getCompDir() == XTAMetadataLabelNode(last->leaf).getCompDir()) + ++last; + MCSymbol *StopLabel = emitSectionHeader(sectionInfo.nameSection, XTA_MARKER_VERSION); + OutStreamer.EmitBytes(XTAMetadataLabelNode(begin->leaf).getCompDir(), 0); // comp_dir. + OutStreamer.EmitBytes(StringRef("\0", 1), 0); + for (std::vector::iterator it = begin; it != end;) { + std::vector::iterator last = it; + ++last; + while (last != end && it->leaf == last->leaf) + ++last; + assert(labelMDNode); + XTAMetadataLabelNode label(labelMDNode); + if (!label.isValid()) + report_fatal_error("Unexpected XTA metadata format"); + OutStreamer.EmitBytes(label.getName(), 0); + OutStreamer.EmitBytes(StringRef("\0", 1), 0); + OutStreamer.EmitBytes(label.getFile(), 0); + OutStreamer.EmitBytes(StringRef("\0", 1), 0); + OutStreamer.EmitIntValue(label.getLineNum(), 4); + if (leafInfoRangeHasSymbol(begin, end)) { + MCSymbol *AddrStartLabel = asmPrinter->GetTempSymbol("addr_start", asmCounter++); + MCSymbol *AddrEndLabel = asmPrinter->GetTempSymbol("addr_end", asmCounter++); + const MCExpr *AddressesSize = MCBinaryExpr::CreateSub(MCSymbolRefExpr::Create(AddrEndLabel, OutContext), MCSymbolRefExpr::Create(AddrStartLabel, OutContext), OutContext); + OutStreamer.EmitValue(AddressesSize, 4); + OutStreamer.EmitLabel(AddrStartLabel); + for (std::vector::iterator it = begin; it != end; ++it) { + MCSymbol *sym = it->sym; + if (!sym) + continue; + OutStreamer.EmitRawText(".cc_top cc_" + Twine(ccCounter) + Twine(",") + sym->getName()); + OutStreamer.EmitValue(MCSymbolRefExpr::Create(sym, OutContext), 4); + OutStreamer.EmitBytes(it->inlineInfo, 0); + OutStreamer.EmitBytes(StringRef("\0", 1), 0); + OutStreamer.EmitRawText(".cc_bottom cc_" + Twine(ccCounter++)); + } + OutStreamer.EmitLabel(AddrEndLabel); + } + else { + OutStreamer.EmitIntValue(0, 4); + } + it = last; + } + OutStreamer.EmitLabel(StopLabel); + it = last; + } + if (sectionInfo.emitLineRanges) { + if (lines.empty()) + return; + std::sort(lines.begin(), lines.end(), lineInfoCompDirIsLess); + for (std::vector::iterator it = lines.begin(), e = lines.end(); + it != e;) { + std::vector::iterator last = it; + ++last; + while (last != e && T(it->leaf).getCompDir() == T(last->leaf).getCompDir()) + ++last; + MCSymbol *StopLabel = emitSectionHeader(sectionInfo.srcSection, XTA_MARKER_TABLE_VERSION); + OutStreamer.EmitBytes(T(begin->leaf).getCompDir(), 0); // comp_dir. + OutStreamer.EmitBytes(StringRef("\0", 1), 0); + for (std::vector::iterator it = begin, e = end; it != e; ++it) { + MCSymbol *sym = lineInfo.sym; + OutStreamer.EmitRawText(".cc_top cc_" + Twine(ccCounter) + Twine(",") + sym->getName()); + OutStreamer.EmitBytes(line.getFile(), 0); + OutStreamer.EmitBytes(StringRef("\0", 1), 0); + OutStreamer.EmitIntValue(line.getLineNum(), 4); + OutStreamer.EmitValue(MCSymbolRefExpr::Create(sym, OutContext), 4); + OutStreamer.EmitRawText(".cc_bottom cc_" + Twine(ccCounter++)); + } + OutStreamer.EmitLabel(StopLabel); + it = last; + } + } + else { + if (lines.empty()) + return; + std::sort(lines.begin(), lines.end(), lineInfoCompDirIsLess); + for (std::vector::iterator it = lines.begin(), e = lines.end(); + it != e;) { + std::vector::iterator last = it; + ++last; + while (last != e && T(it->leaf).getCompDir() == T(last->leaf).getCompDir()) + ++last; + MCSymbol *StopLabel = emitSectionHeader(sectionInfo.srcSection, XTA_MARKER_TABLE_VERSION); + OutStreamer.EmitBytes(T(begin->leaf).getCompDir(), 0); // comp_dir. + OutStreamer.EmitBytes(StringRef("\0", 1), 0); + for (std::vector::iterator it = begin, e = end; it != e; ++it) { + MCSymbol *sym = lineInfo.sym; + OutStreamer.EmitRawText(".cc_top cc_" + Twine(ccCounter) + Twine(",") + sym->getName()); + OutStreamer.EmitBytes(line.getFile(), 0); + OutStreamer.EmitBytes(StringRef("\0", 1), 0); + OutStreamer.EmitIntValue(line.getLineNum(), 4); + OutStreamer.EmitValue(MCSymbolRefExpr::Create(sym, OutContext), 4); + OutStreamer.EmitRawText(".cc_bottom cc_" + Twine(ccCounter++)); + } + OutStreamer.EmitLabel(StopLabel); + it = last; + }std::vector::iterator last = it; + ++last; + while (last != e && XTAMetadataLabelNode(it->leaf).getCompDir() == XTAMetadataLabelNode(last->leaf).getCompDir()) + ++last; + MCSymbol *StopLabel = emitSectionHeader(sectionInfo.nameSection, XTA_MARKER_VERSION); + OutStreamer.EmitBytes(XTAMetadataLabelNode(begin->leaf).getCompDir(), 0); // comp_dir. + OutStreamer.EmitBytes(StringRef("\0", 1), 0); + for (std::vector::iterator it = begin; it != end;) { + std::vector::iterator last = it; + ++last; + while (last != end && it->leaf == last->leaf) + ++last; + assert(labelMDNode); + XTAMetadataLabelNode label(labelMDNode); + if (!label.isValid()) + report_fatal_error("Unexpected XTA metadata format"); + OutStreamer.EmitBytes(label.getName(), 0); + OutStreamer.EmitBytes(StringRef("\0", 1), 0); + OutStreamer.EmitBytes(label.getFile(), 0); + OutStreamer.EmitBytes(StringRef("\0", 1), 0); + OutStreamer.EmitIntValue(label.getLineNum(), 4); + if (leafInfoRangeHasSymbol(begin, end)) { + MCSymbol *AddrStartLabel = asmPrinter->GetTempSymbol("addr_start", asmCounter++); + MCSymbol *AddrEndLabel = asmPrinter->GetTempSymbol("addr_end", asmCounter++); + const MCExpr *AddressesSize = MCBinaryExpr::CreateSub(MCSymbolRefExpr::Create(AddrEndLabel, OutContext), MCSymbolRefExpr::Create(AddrStartLabel, OutContext), OutContext); + OutStreamer.EmitValue(AddressesSize, 4); + OutStreamer.EmitLabel(AddrStartLabel); + for (std::vector::iterator it = begin; it != end; ++it) { + MCSymbol *sym = it->sym; + if (!sym) + continue; + OutStreamer.EmitRawText(".cc_top cc_" + Twine(ccCounter) + Twine(",") + sym->getName()); + OutStreamer.EmitValue(MCSymbolRefExpr::Create(sym, OutContext), 4); + OutStreamer.EmitBytes(it->inlineInfo, 0); + OutStreamer.EmitBytes(StringRef("\0", 1), 0); + OutStreamer.EmitRawText(".cc_bottom cc_" + Twine(ccCounter++)); + } + OutStreamer.EmitLabel(AddrEndLabel); + } + else { + OutStreamer.EmitIntValue(0, 4); + } + it = last; + } + OutStreamer.EmitLabel(StopLabel); + it = last; + } + if (sectionInfo.emitLineRanges) { + if (lines.empty()) + return; + std::sort(lines.begin(), lines.end(), lineInfoCompDirIsLess); + for (std::vector::iterator it = lines.begin(), e = lines.end(); + it != e;) { + std::vector::iterator last = it; + ++last; + while (last != e && T(it->leaf).getCompDir() == T(last->leaf).getCompDir()) + ++last; + MCSymbol *StopLabel = emitSectionHeader(sectionInfo.srcSection, XTA_MARKER_TABLE_VERSION); + OutStreamer.EmitBytes(T(begin->leaf).getCompDir(), 0); // comp_dir. + OutStreamer.EmitBytes(StringRef("\0", 1), 0); + for (std::vector::iterator it = begin, e = end; it != e; ++it) { + MCSymbol *sym = lineInfo.sym; + OutStreamer.EmitRawText(".cc_top cc_" + Twine(ccCounter) + Twine(",") + sym->getName()); + OutStreamer.EmitBytes(line.getFile(), 0); + OutStreamer.EmitBytes(StringRef("\0", 1), 0); + OutStreamer.EmitIntValue(line.getLineNum(), 4); + OutStreamer.EmitValue(MCSymbolRefExpr::Create(sym, OutContext), 4); + OutStreamer.EmitRawText(".cc_bottom cc_" + Twine(ccCounter++)); + } + OutStreamer.EmitLabel(StopLabel); + it = last; + } + } + else { + if (lines.empty()) + return; + std::sort(lines.begin(), lines.end(), lineInfoCompDirIsLess); + for (std::vector::iterator it = lines.begin(), e = lines.end(); + it != e;) { + std::vector::iterator last = it; + ++last; + while (last != e && T(it->leaf).getCompDir() == T(last->leaf).getCompDir()) + ++last; + MCSymbol *StopLabel = emitSectionHeader(sectionInfo.srcSection, XTA_MARKER_TABLE_VERSION); + OutStreamer.EmitBytes(T(begin->leaf).getCompDir(), 0); // comp_dir. + OutStreamer.EmitBytes(StringRef("\0", 1), 0); + for (std::vector::iterator it = begin, e = end; it != e; ++it) { + MCSymbol *sym = lineInfo.sym; + OutStreamer.EmitRawText(".cc_top cc_" + Twine(ccCounter) + Twine(",") + sym->getName()); + OutStreamer.EmitBytes(line.getFile(), 0); + OutStreamer.EmitBytes(StringRef("\0", 1), 0); + OutStreamer.EmitIntValue(line.getLineNum(), 4); + OutStreamer.EmitValue(MCSymbolRefExpr::Create(sym, OutContext), 4); + OutStreamer.EmitRawText(".cc_bottom cc_" + Twine(ccCounter++)); + } + OutStreamer.EmitLabel(StopLabel); + it = last; + }std::vector::iterator last = it; + ++last; + while (last != e && XTAMetadataLabelNode(it->leaf).getCompDir() == XTAMetadataLabelNode(last->leaf).getCompDir()) + ++last; + MCSymbol *StopLabel = emitSectionHeader(sectionInfo.nameSection, XTA_MARKER_VERSION); + OutStreamer.EmitBytes(XTAMetadataLabelNode(begin->leaf).getCompDir(), 0); // comp_dir. + OutStreamer.EmitBytes(StringRef("\0", 1), 0); + for (std::vector::iterator it = begin; it != end;) { + std::vector::iterator last = it; + ++last; + while (last != end && it->leaf == last->leaf) + ++last; + assert(labelMDNode); + XTAMetadataLabelNode label(labelMDNode); + if (!label.isValid()) + report_fatal_error("Unexpected XTA metadata format"); + OutStreamer.EmitBytes(label.getName(), 0); + OutStreamer.EmitBytes(StringRef("\0", 1), 0); + OutStreamer.EmitBytes(label.getFile(), 0); + OutStreamer.EmitBytes(StringRef("\0", 1), 0); + OutStreamer.EmitIntValue(label.getLineNum(), 4); + if (leafInfoRangeHasSymbol(begin, end)) { + MCSymbol *AddrStartLabel = asmPrinter->GetTempSymbol("addr_start", asmCounter++); + MCSymbol *AddrEndLabel = asmPrinter->GetTempSymbol("addr_end", asmCounter++); + const MCExpr *AddressesSize = MCBinaryExpr::CreateSub(MCSymbolRefExpr::Create(AddrEndLabel, OutContext), MCSymbolRefExpr::Create(AddrStartLabel, OutContext), OutContext); + OutStreamer.EmitValue(AddressesSize, 4); + OutStreamer.EmitLabel(AddrStartLabel); + for (std::vector::iterator it = begin; it != end; ++it) { + MCSymbol *sym = it->sym; + if (!sym) + continue; + OutStreamer.EmitRawText(".cc_top cc_" + Twine(ccCounter) + Twine(",") + sym->getName()); + OutStreamer.EmitValue(MCSymbolRefExpr::Create(sym, OutContext), 4); + OutStreamer.EmitBytes(it->inlineInfo, 0); + OutStreamer.EmitBytes(StringRef("\0", 1), 0); + OutStreamer.EmitRawText(".cc_bottom cc_" + Twine(ccCounter++)); + } + OutStreamer.EmitLabel(AddrEndLabel); + } + else { + OutStreamer.EmitIntValue(0, 4); + } + it = last; + } + OutStreamer.EmitLabel(StopLabel); + it = last; + } + if (sectionInfo.emitLineRanges) { + if (lines.empty()) + return; + std::sort(lines.begin(), lines.end(), lineInfoCompDirIsLess); + for (std::vector::iterator it = lines.begin(), e = lines.end(); + it != e;) { + std::vector::iterator last = it; + ++last; + while (last != e && T(it->leaf).getCompDir() == T(last->leaf).getCompDir()) + ++last; + MCSymbol *StopLabel = emitSectionHeader(sectionInfo.srcSection, XTA_MARKER_TABLE_VERSION); + OutStreamer.EmitBytes(T(begin->leaf).getCompDir(), 0); // comp_dir. + OutStreamer.EmitBytes(StringRef("\0", 1), 0); + for (std::vector::iterator it = begin, e = end; it != e; ++it) { + MCSymbol *sym = lineInfo.sym; + OutStreamer.EmitRawText(".cc_top cc_" + Twine(ccCounter) + Twine(",") + sym->getName()); + OutStreamer.EmitBytes(line.getFile(), 0); + OutStreamer.EmitBytes(StringRef("\0", 1), 0); + OutStreamer.EmitIntValue(line.getLineNum(), 4); + OutStreamer.EmitValue(MCSymbolRefExpr::Create(sym, OutContext), 4); + OutStreamer.EmitRawText(".cc_bottom cc_" + Twine(ccCounter++)); + } + OutStreamer.EmitLabel(StopLabel); + it = last; + } + } + else { + if (lines.empty()) + return; + std::sort(lines.begin(), lines.end(), lineInfoCompDirIsLess); + for (std::vector::iterator it = lines.begin(), e = lines.end(); + it != e;) { + std::vector::iterator last = it; + ++last; + while (last != e && T(it->leaf).getCompDir() == T(last->leaf).getCompDir()) + ++last; + MCSymbol *StopLabel = emitSectionHeader(sectionInfo.srcSection, XTA_MARKER_TABLE_VERSION); + OutStreamer.EmitBytes(T(begin->leaf).getCompDir(), 0); // comp_dir. + OutStreamer.EmitBytes(StringRef("\0", 1), 0); + for (std::vector::iterator it = begin, e = end; it != e; ++it) { + MCSymbol *sym = lineInfo.sym; + OutStreamer.EmitRawText(".cc_top cc_" + Twine(ccCounter) + Twine(",") + sym->getName()); + OutStreamer.EmitBytes(line.getFile(), 0); + OutStreamer.EmitBytes(StringRef("\0", 1), 0); + OutStreamer.EmitIntValue(line.getLineNum(), 4); + OutStreamer.EmitValue(MCSymbolRefExpr::Create(sym, OutContext), 4); + OutStreamer.EmitRawText(".cc_bottom cc_" + Twine(ccCounter++)); + } + OutStreamer.EmitLabel(StopLabel); + it = last; + }std::vector::iterator last = it; + ++last; + while (last != e && XTAMetadataLabelNode(it->leaf).getCompDir() == XTAMetadataLabelNode(last->leaf).getCompDir()) + ++last; + MCSymbol *StopLabel = emitSectionHeader(sectionInfo.nameSection, XTA_MARKER_VERSION); + OutStreamer.EmitBytes(XTAMetadataLabelNode(begin->leaf).getCompDir(), 0); // comp_dir. + OutStreamer.EmitBytes(StringRef("\0", 1), 0); + for (std::vector::iterator it = begin; it != end;) { + std::vector::iterator last = it; + ++last; + while (last != end && it->leaf == last->leaf) + ++last; + assert(labelMDNode); + XTAMetadataLabelNode label(labelMDNode); + if (!label.isValid()) + report_fatal_error("Unexpected XTA metadata format"); + OutStreamer.EmitBytes(label.getName(), 0); + OutStreamer.EmitBytes(StringRef("\0", 1), 0); + OutStreamer.EmitBytes(label.getFile(), 0); + OutStreamer.EmitBytes(StringRef("\0", 1), 0); + OutStreamer.EmitIntValue(label.getLineNum(), 4); + if (leafInfoRangeHasSymbol(begin, end)) { + MCSymbol *AddrStartLabel = asmPrinter->GetTempSymbol("addr_start", asmCounter++); + MCSymbol *AddrEndLabel = asmPrinter->GetTempSymbol("addr_end", asmCounter++); + const MCExpr *AddressesSize = MCBinaryExpr::CreateSub(MCSymbolRefExpr::Create(AddrEndLabel, OutContext), MCSymbolRefExpr::Create(AddrStartLabel, OutContext), OutContext); + OutStreamer.EmitValue(AddressesSize, 4); + OutStreamer.EmitLabel(AddrStartLabel); + for (std::vector::iterator it = begin; it != end; ++it) { + MCSymbol *sym = it->sym; + if (!sym) + continue; + OutStreamer.EmitRawText(".cc_top cc_" + Twine(ccCounter) + Twine(",") + sym->getName()); + OutStreamer.EmitValue(MCSymbolRefExpr::Create(sym, OutContext), 4); + OutStreamer.EmitBytes(it->inlineInfo, 0); + OutStreamer.EmitBytes(StringRef("\0", 1), 0); + OutStreamer.EmitRawText(".cc_bottom cc_" + Twine(ccCounter++)); + } + OutStreamer.EmitLabel(AddrEndLabel); + } + else { + OutStreamer.EmitIntValue(0, 4); + } + it = last; + } + OutStreamer.EmitLabel(StopLabel); + it = last; + } + if (sectionInfo.emitLineRanges) { + if (lines.empty()) + return; + std::sort(lines.begin(), lines.end(), lineInfoCompDirIsLess); + for (std::vector::iterator it = lines.begin(), e = lines.end(); + it != e;) { + std::vector::iterator last = it; + ++last; + while (last != e && T(it->leaf).getCompDir() == T(last->leaf).getCompDir()) + ++last; + MCSymbol *StopLabel = emitSectionHeader(sectionInfo.srcSection, XTA_MARKER_TABLE_VERSION); + OutStreamer.EmitBytes(T(begin->leaf).getCompDir(), 0); // comp_dir. + OutStreamer.EmitBytes(StringRef("\0", 1), 0); + for (std::vector::iterator it = begin, e = end; it != e; ++it) { + MCSymbol *sym = lineInfo.sym; + OutStreamer.EmitRawText(".cc_top cc_" + Twine(ccCounter) + Twine(",") + sym->getName()); + OutStreamer.EmitBytes(line.getFile(), 0); + OutStreamer.EmitBytes(StringRef("\0", 1), 0); + OutStreamer.EmitIntValue(line.getLineNum(), 4); + OutStreamer.EmitValue(MCSymbolRefExpr::Create(sym, OutContext), 4); + OutStreamer.EmitRawText(".cc_bottom cc_" + Twine(ccCounter++)); + } + OutStreamer.EmitLabel(StopLabel); + it = last; + } + } + else { + if (lines.empty()) + return; + std::sort(lines.begin(), lines.end(), lineInfoCompDirIsLess); + for (std::vector::iterator it = lines.begin(), e = lines.end(); + it != e;) { + std::vector::iterator last = it; + ++last; + while (last != e && T(it->leaf).getCompDir() == T(last->leaf).getCompDir()) + ++last; + MCSymbol *StopLabel = emitSectionHeader(sectionInfo.srcSection, XTA_MARKER_TABLE_VERSION); + OutStreamer.EmitBytes(T(begin->leaf).getCompDir(), 0); // comp_dir. + OutStreamer.EmitBytes(StringRef("\0", 1), 0); + for (std::vector::iterator it = begin, e = end; it != e; ++it) { + MCSymbol *sym = lineInfo.sym; + OutStreamer.EmitRawText(".cc_top cc_" + Twine(ccCounter) + Twine(",") + sym->getName()); + OutStreamer.EmitBytes(line.getFile(), 0); + OutStreamer.EmitBytes(StringRef("\0", 1), 0); + OutStreamer.EmitIntValue(line.getLineNum(), 4); + OutStreamer.EmitValue(MCSymbolRefExpr::Create(sym, OutContext), 4); + OutStreamer.EmitRawText(".cc_bottom cc_" + Twine(ccCounter++)); + } + OutStreamer.EmitLabel(StopLabel); + it = last; + } + } + RUW.EndModule(M); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/emitStartOfAsmFile.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/emitStartOfAsmFile.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a21905edf906991b4e47ad670d0f50c77c63d762 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/emitStartOfAsmFile.cpp @@ -0,0 +1,91 @@ +void XCoreAsmPrinter::EmitStartOfAsmFile(Module &M) { + Meta = getAnalysisIfAvailable(); + assert(Meta && "XCoreAsmPrinter didn't require XCoreMetadata?"); + NamedMDNode *NMD = M.getNamedMetadata("xcore.typestrings"); + if (!NMD) + return; + for (unsigned i = 0, e = NMD->getNumOperands(); i != e; ++i) { + MDNode *N = cast_or_null(NMD->getOperand(i)); + if (!N) + continue; + if (N->getNumOperands() != 2) + continue; + GlobalValue *GV = cast_or_null(N->getOperand(0)); + MDString *S = cast_or_null(N->getOperand(1)); + if (!GV || !S) + continue; + TypeStrings.insert(std::make_pair(GV, S->getString())); + } + NamedMDNode *NMD = M.getNamedMetadata("xcore.overlay"); + if (!NMD) + return; + for (unsigned i = 0, e = NMD->getNumOperands(); i != e; ++i) { + MDNode *N = cast_or_null(NMD->getOperand(i)); + if (!N) + continue; + if (N->getNumOperands() < 1 || N->getNumOperands() > 2) + continue; + GlobalValue *GV = cast_or_null(N->getOperand(0)); + if (!GV) + continue; + std::string str; + if (N->getNumOperands() == 2) { + MDString *S = cast_or_null(N->getOperand(1)); + if (!S) + continue; + str = S->getString(); + } + OverlayInfo.insert(std::make_pair(GV, str)); + } + NamedMDNode *NMD = M.getNamedMetadata("xcore.overlay.reference"); + if (!NMD) + return; + for (unsigned i = 0, e = NMD->getNumOperands(); i != e; ++i) { + MDNode *N = cast_or_null(NMD->getOperand(i)); + if (!N) + continue; + if (N->getNumOperands() < 2) + continue; + GlobalValue *GV = cast_or_null(N->getOperand(0)); + if (!GV) + continue; + std::vector refs; + for (unsigned j = 1, e = N->getNumOperands(); j != e; ++j) { + MDString *S = cast_or_null(N->getOperand(j)); + if (!S) + continue; + refs.push_back(S->getString()); + } + OverlayReferenceInfo.insert(std::make_pair(GV, refs)); + } + NamedMDNode *NMD = M.getNamedMetadata("xcore.stack"); + if (!NMD) + return; + for (unsigned i = 0, e = NMD->getNumOperands(); i != e; ++i) { + MDNode *N = cast_or_null(NMD->getOperand(i)); + if (!N) + continue; + if (N->getNumOperands() != 2) + continue; + Function *F = cast_or_null(N->getOperand(0)); + ConstantInt *CI = cast_or_null(N->getOperand(1)); + if (!F || !CI) + continue; + StackAttributes.insert(std::make_pair(F, CI->getZExtValue())); + } + NamedMDNode *NMD = M.getNamedMetadata("xcore.xtataskstart"); + if (!NMD) + return; + for (unsigned i = 0, e = NMD->getNumOperands(); i != e; ++i) { + MDNode *N = cast_or_null(NMD->getOperand(i)); + if (!N) + continue; + if (N->getNumOperands() != 1) + continue; + Function *F = cast_or_null(N->getOperand(0)); + if (!F) + continue; + XtaTaskStart.insert(F); + } + Meta = M; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/getAnalysisUsage.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/getAnalysisUsage.cpp new file mode 100644 index 0000000000000000000000000000000000000000..656af2d7030d2b7f23236a4df7be09a85568795c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/getAnalysisUsage.cpp @@ -0,0 +1,5 @@ +void getAnalysisUsage(AnalysisUsage &AU) const { + AsmPrinter::getAnalysisUsage(AU); + AU.setPreservesAll(); + AU.addRequired(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/getDebugValueLocation.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/getDebugValueLocation.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b52d2337b7bd8a56dd2cb8cc6fd3f6a79e7fc1c0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/getDebugValueLocation.cpp @@ -0,0 +1,5 @@ +MachineLocation XCoreAsmPrinter::getDebugValueLocation(const MachineInstr *MI) const { + assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!"); + assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm() && "Unexpected MachineOperand types"); + return MachineLocation(MI->getOperand(0).getReg() MI->getOperand(1).getImm()); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/getPassName.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a9c75d959bc23c855ea600ab93a27f7c7ce7239a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/getPassName.cpp @@ -0,0 +1,3 @@ +virtual const char *getPassName() const { + return "XCore Assembly Printer"; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/printInlineJT.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/printInlineJT.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9534675771a3b46a89bf466409a674138f3b2e86 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/printInlineJT.cpp @@ -0,0 +1,14 @@ +void XCoreAsmPrinter::printInlineJT(const MachineInstr *MI, int opNum, raw_ostream &O, const std::string &directive) { + unsigned JTI = MI->getOperand(opNum).getIndex(); + const MachineFunction *MF = MI->getParent()->getParent(); + const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo(); + const std::vector &JT = MJTI->getJumpTables(); + const std::vector &JTBBs = JT[JTI].MBBs; + O << "\t" << directive << " "; + for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) { + MachineBasicBlock *MBB = JTBBs[i]; + if (i > 0) + O << ","; + O << *MBB->getSymbol(); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/printInlineJT32.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/printInlineJT32.cpp new file mode 100644 index 0000000000000000000000000000000000000000..357cdd2774a36b1693463b545ef78022c5632bba --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/printInlineJT32.cpp @@ -0,0 +1,14 @@ +void XCoreAsmPrinter::printInlineJT32(const MachineInstr *MI, int opNum, raw_ostream &O, const std::string &directive) { + unsigned JTI = MI->getOperand(opNum).getIndex(); + const MachineFunction *MF = MI->getParent()->getParent(); + const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo(); + const std::vector &JT = MJTI->getJumpTables(); + const std::vector &JTBBs = JT[JTI].MBBs; + O << "\t" << directive << " "; + for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) { + MachineBasicBlock *MBB = JTBBs[i]; + if (i > 0) + O << ","; + O << *MBB->getSymbol(); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/printMemOperand.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/printMemOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..17c61d25c6cbf07c419cb3d80f6528a6f228bf84 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/printMemOperand.cpp @@ -0,0 +1,7 @@ +void XCoreAsmPrinter::printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O) { + printOperand(MI, opNum, O); + if (MI->getOperand(opNum+1).isImm() && MI->getOperand(opNum+1).getImm() == 0) + return; + O << "+"; + printOperand(MI, opNum+1, O); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/printOperand.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/printOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a4745fe309aac0d12cebafd265ca0698989f8cfb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/printOperand.cpp @@ -0,0 +1,33 @@ +void XCoreAsmPrinter::printOperand(const MachineInstr *MI, int opNum, raw_ostream &O) { + const MachineOperand &MO = MI->getOperand(opNum); + switch (MO.getType()) { + case MachineOperand::MO_Register: + O << getRegisterName(MO.getReg()); + break; + case MachineOperand::MO_Immediate: + O << MO.getImm(); + break; + case MachineOperand::MO_MachineBasicBlock: + O << *MO.getMBB()->getSymbol(); + break; + case MachineOperand::MO_GlobalAddress: + O << *Mang->getSymbol(MO.getGlobal()); + break; + case MachineOperand::MO_ExternalSymbol: + O << MO.getSymbolName(); + break; + case MachineOperand::MO_ConstantPoolIndex: + O << MAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber() + << '_' << MO.getIndex(); + break; + case MachineOperand::MO_JumpTableIndex: + O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber() + << '_' << MO.getIndex(); + break; + case MachineOperand::MO_BlockAddress: + O << *GetBlockAddressSymbol(MO.getBlockAddress()); + break; + default: + llvm_unreachable("not implemented"); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b3ec7b4088890ccde7150025701b0c5d602b0cae --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/runOnMachineFunction.cpp @@ -0,0 +1,544 @@ +bool XCoreAsmPrinter::runOnMachineFunction(MachineFunction &MF) { + SetupMachineFunction(MF); + const Function *F = MF.getFunction(); + OutStreamer.SwitchSection(getObjFileLowering().SectionForGlobal(F, Mang, TM)); + OutStreamer.EmitRawText("\t.cc_top " + Twine(CurrentFnSym->getName()) + ".function"); + EmitFunctionHeader(); + EmitFunctionBody(); + unsigned Alignment = MF.getAlignment(); + if (Alignment == 2) + EmitAlignment(MF.getAlignment(), MF.getFunction()); + OutStreamer.SwitchSection(getObjFileLowering().SectionForGlobal(F, Mang, TM)); + OutStreamer.EmitRawText("\t.cc_bottom " + Twine(CurrentFnSym->getName()) + ".function"); + CurrentFn = MF.getFunction(); + Buf.clear(); + raw_svector_ostream O(Buf); + XCoreResourceMDExtractor res(MF.getFunction()); + switch (Type) { + case PragmaStackWords: + { + uint64_t Value; + if (!Meta || !Meta->GetStackAttribute(*MF.getFunction(), Value)) + return false; + O << "\t.set\t"; + SmallString<32> NameBuf; + Asm->Mang->getNameWithPrefix(NameBuf, F, false); + O << NameBuf << getSuffix(Type); + O << ","; + O << Value; + break; + } + case StackWords: + { + const XCoreFunctionInfo *XFI = MF.getInfo(); + StackNode *exp = XFI->getNStackWords(); + if (exp->getID() == STUDefID) { + uint64_t Dummy; + if (Meta && Meta->GetStackAttribute(*MF.getFunction(), Dummy)) { + O << "\t.set\t"; + SmallString<32> NameBuf; + Asm->Mang->getNameWithPrefix(NameBuf, F, false); + O << NameBuf << getSuffix(Type); + O << ","; + SmallString<32> NameBuf; + Asm->Mang->getNameWithPrefix(NameBuf, F, false); + O << NameBuf << getSuffix(Type); + break; + } + return false; + } + O << "\t.set\t"; + SmallString<32> NameBuf; + Asm->Mang->getNameWithPrefix(NameBuf, F, false); + O << NameBuf << getSuffix(Type); + O << ","; + exp->toString(O); + break; + } + case MaxTimers: + { + StringRef s = res.getTimerResourceUsage(); + if (!s.empty()){ + O << "\t.set\t"; + SmallString<32> NameBuf; + Asm->Mang->getNameWithPrefix(NameBuf, F, false); + O << NameBuf << getSuffix(Type); + O << ","; + O << s; + } + break; + } + case MaxChanends: + { + StringRef s = res.getChanendResourceUsage(); + if(!s.empty()){ + O << "\t.set\t"; + SmallString<32> NameBuf; + Asm->Mang->getNameWithPrefix(NameBuf, F, false); + O << NameBuf << getSuffix(Type); + O << ","; + O << s; + } + break; + } + case MaxCores: + { + StringRef s = res.getThreadResourceUsage(); + if(!s.empty()){ + O << "\t.set\t"; + SmallString<32> NameBuf; + Asm->Mang->getNameWithPrefix(NameBuf, F, false); + O << NameBuf << getSuffix(Type); + O << ","; + O << s; + } + break; + } + } + O.flush(); + OutStreamer.EmitRawText(Buf.str()); + switch (MF.getFunction()->getLinkage()) { + default: assert(0 && "Unknown linkage type!"); + case Function::InternalLinkage: + case Function::PrivateLinkage: + break; + case GlobalValue::LinkOnceAnyLinkage: + case GlobalValue::LinkOnceODRLinkage: + case GlobalValue::WeakAnyLinkage: + case GlobalValue::WeakODRLinkage: + case GlobalValue::ExternalLinkage: + Buf.clear(); + Asm->Mang->getNameWithPrefix(Buf, MF.getFunction(), false); + Buf += getSuffix(Type); + MCSymbol *ResSym = Asm->GetExternalSymbolSymbol(Buf.str()); + OutStreamer.EmitSymbolAttribute(ResSym, MCSA_Global); + if (MF.getFunction()->getLinkage() != GlobalValue::ExternalLinkage) + OutStreamer.EmitSymbolAttribute(ResSym, MCSA_Weak); + break; + } + CurrentFn = MF.getFunction(); + Buf.clear(); + raw_svector_ostream O(Buf); + XCoreResourceMDExtractor res(MF.getFunction()); + switch (Type) { + case PragmaStackWords: + { + uint64_t Value; + if (!Meta || !Meta->GetStackAttribute(*MF.getFunction(), Value)) + return false; + O << "\t.set\t"; + SmallString<32> NameBuf; + Asm->Mang->getNameWithPrefix(NameBuf, F, false); + O << NameBuf << getSuffix(Type); + O << ","; + O << Value; + break; + } + case StackWords: + { + const XCoreFunctionInfo *XFI = MF.getInfo(); + StackNode *exp = XFI->getNStackWords(); + if (exp->getID() == STUDefID) { + uint64_t Dummy; + if (Meta && Meta->GetStackAttribute(*MF.getFunction(), Dummy)) { + O << "\t.set\t"; + SmallString<32> NameBuf; + Asm->Mang->getNameWithPrefix(NameBuf, F, false); + O << NameBuf << getSuffix(Type); + O << ","; + SmallString<32> NameBuf; + Asm->Mang->getNameWithPrefix(NameBuf, F, false); + O << NameBuf << getSuffix(Type); + break; + } + return false; + } + O << "\t.set\t"; + SmallString<32> NameBuf; + Asm->Mang->getNameWithPrefix(NameBuf, F, false); + O << NameBuf << getSuffix(Type); + O << ","; + exp->toString(O); + break; + } + case MaxTimers: + { + StringRef s = res.getTimerResourceUsage(); + if (!s.empty()){ + O << "\t.set\t"; + SmallString<32> NameBuf; + Asm->Mang->getNameWithPrefix(NameBuf, F, false); + O << NameBuf << getSuffix(Type); + O << ","; + O << s; + } + break; + } + case MaxChanends: + { + StringRef s = res.getChanendResourceUsage(); + if(!s.empty()){ + O << "\t.set\t"; + SmallString<32> NameBuf; + Asm->Mang->getNameWithPrefix(NameBuf, F, false); + O << NameBuf << getSuffix(Type); + O << ","; + O << s; + } + break; + } + case MaxCores: + { + StringRef s = res.getThreadResourceUsage(); + if(!s.empty()){ + O << "\t.set\t"; + SmallString<32> NameBuf; + Asm->Mang->getNameWithPrefix(NameBuf, F, false); + O << NameBuf << getSuffix(Type); + O << ","; + O << s; + } + break; + } + } + O.flush(); + OutStreamer.EmitRawText(Buf.str()); + switch (MF.getFunction()->getLinkage()) { + default: assert(0 && "Unknown linkage type!"); + case Function::InternalLinkage: + case Function::PrivateLinkage: + break; + case GlobalValue::LinkOnceAnyLinkage: + case GlobalValue::LinkOnceODRLinkage: + case GlobalValue::WeakAnyLinkage: + case GlobalValue::WeakODRLinkage: + case GlobalValue::ExternalLinkage: + Buf.clear(); + Asm->Mang->getNameWithPrefix(Buf, MF.getFunction(), false); + Buf += getSuffix(Type); + MCSymbol *ResSym = Asm->GetExternalSymbolSymbol(Buf.str()); + OutStreamer.EmitSymbolAttribute(ResSym, MCSA_Global); + if (MF.getFunction()->getLinkage() != GlobalValue::ExternalLinkage) + OutStreamer.EmitSymbolAttribute(ResSym, MCSA_Weak); + break; + } + CurrentFn = MF.getFunction(); + Buf.clear(); + raw_svector_ostream O(Buf); + XCoreResourceMDExtractor res(MF.getFunction()); + switch (Type) { + case PragmaStackWords: + { + uint64_t Value; + if (!Meta || !Meta->GetStackAttribute(*MF.getFunction(), Value)) + return false; + O << "\t.set\t"; + SmallString<32> NameBuf; + Asm->Mang->getNameWithPrefix(NameBuf, F, false); + O << NameBuf << getSuffix(Type); + O << ","; + O << Value; + break; + } + case StackWords: + { + const XCoreFunctionInfo *XFI = MF.getInfo(); + StackNode *exp = XFI->getNStackWords(); + if (exp->getID() == STUDefID) { + uint64_t Dummy; + if (Meta && Meta->GetStackAttribute(*MF.getFunction(), Dummy)) { + O << "\t.set\t"; + SmallString<32> NameBuf; + Asm->Mang->getNameWithPrefix(NameBuf, F, false); + O << NameBuf << getSuffix(Type); + O << ","; + SmallString<32> NameBuf; + Asm->Mang->getNameWithPrefix(NameBuf, F, false); + O << NameBuf << getSuffix(Type); + break; + } + return false; + } + O << "\t.set\t"; + SmallString<32> NameBuf; + Asm->Mang->getNameWithPrefix(NameBuf, F, false); + O << NameBuf << getSuffix(Type); + O << ","; + exp->toString(O); + break; + } + case MaxTimers: + { + StringRef s = res.getTimerResourceUsage(); + if (!s.empty()){ + O << "\t.set\t"; + SmallString<32> NameBuf; + Asm->Mang->getNameWithPrefix(NameBuf, F, false); + O << NameBuf << getSuffix(Type); + O << ","; + O << s; + } + break; + } + case MaxChanends: + { + StringRef s = res.getChanendResourceUsage(); + if(!s.empty()){ + O << "\t.set\t"; + SmallString<32> NameBuf; + Asm->Mang->getNameWithPrefix(NameBuf, F, false); + O << NameBuf << getSuffix(Type); + O << ","; + O << s; + } + break; + } + case MaxCores: + { + StringRef s = res.getThreadResourceUsage(); + if(!s.empty()){ + O << "\t.set\t"; + SmallString<32> NameBuf; + Asm->Mang->getNameWithPrefix(NameBuf, F, false); + O << NameBuf << getSuffix(Type); + O << ","; + O << s; + } + break; + } + } + O.flush(); + OutStreamer.EmitRawText(Buf.str()); + switch (MF.getFunction()->getLinkage()) { + default: assert(0 && "Unknown linkage type!"); + case Function::InternalLinkage: + case Function::PrivateLinkage: + break; + case GlobalValue::LinkOnceAnyLinkage: + case GlobalValue::LinkOnceODRLinkage: + case GlobalValue::WeakAnyLinkage: + case GlobalValue::WeakODRLinkage: + case GlobalValue::ExternalLinkage: + Buf.clear(); + Asm->Mang->getNameWithPrefix(Buf, MF.getFunction(), false); + Buf += getSuffix(Type); + MCSymbol *ResSym = Asm->GetExternalSymbolSymbol(Buf.str()); + OutStreamer.EmitSymbolAttribute(ResSym, MCSA_Global); + if (MF.getFunction()->getLinkage() != GlobalValue::ExternalLinkage) + OutStreamer.EmitSymbolAttribute(ResSym, MCSA_Weak); + break; + } + CurrentFn = MF.getFunction(); + Buf.clear(); + raw_svector_ostream O(Buf); + XCoreResourceMDExtractor res(MF.getFunction()); + switch (Type) { + case PragmaStackWords: + { + uint64_t Value; + if (!Meta || !Meta->GetStackAttribute(*MF.getFunction(), Value)) + return false; + O << "\t.set\t"; + SmallString<32> NameBuf; + Asm->Mang->getNameWithPrefix(NameBuf, F, false); + O << NameBuf << getSuffix(Type); + O << ","; + O << Value; + break; + } + case StackWords: + { + const XCoreFunctionInfo *XFI = MF.getInfo(); + StackNode *exp = XFI->getNStackWords(); + if (exp->getID() == STUDefID) { + uint64_t Dummy; + if (Meta && Meta->GetStackAttribute(*MF.getFunction(), Dummy)) { + O << "\t.set\t"; + SmallString<32> NameBuf; + Asm->Mang->getNameWithPrefix(NameBuf, F, false); + O << NameBuf << getSuffix(Type); + O << ","; + SmallString<32> NameBuf; + Asm->Mang->getNameWithPrefix(NameBuf, F, false); + O << NameBuf << getSuffix(Type); + break; + } + return false; + } + O << "\t.set\t"; + SmallString<32> NameBuf; + Asm->Mang->getNameWithPrefix(NameBuf, F, false); + O << NameBuf << getSuffix(Type); + O << ","; + exp->toString(O); + break; + } + case MaxTimers: + { + StringRef s = res.getTimerResourceUsage(); + if (!s.empty()){ + O << "\t.set\t"; + SmallString<32> NameBuf; + Asm->Mang->getNameWithPrefix(NameBuf, F, false); + O << NameBuf << getSuffix(Type); + O << ","; + O << s; + } + break; + } + case MaxChanends: + { + StringRef s = res.getChanendResourceUsage(); + if(!s.empty()){ + O << "\t.set\t"; + SmallString<32> NameBuf; + Asm->Mang->getNameWithPrefix(NameBuf, F, false); + O << NameBuf << getSuffix(Type); + O << ","; + O << s; + } + break; + } + case MaxCores: + { + StringRef s = res.getThreadResourceUsage(); + if(!s.empty()){ + O << "\t.set\t"; + SmallString<32> NameBuf; + Asm->Mang->getNameWithPrefix(NameBuf, F, false); + O << NameBuf << getSuffix(Type); + O << ","; + O << s; + } + break; + } + } + O.flush(); + OutStreamer.EmitRawText(Buf.str()); + switch (MF.getFunction()->getLinkage()) { + default: assert(0 && "Unknown linkage type!"); + case Function::InternalLinkage: + case Function::PrivateLinkage: + break; + case GlobalValue::LinkOnceAnyLinkage: + case GlobalValue::LinkOnceODRLinkage: + case GlobalValue::WeakAnyLinkage: + case GlobalValue::WeakODRLinkage: + case GlobalValue::ExternalLinkage: + Buf.clear(); + Asm->Mang->getNameWithPrefix(Buf, MF.getFunction(), false); + Buf += getSuffix(Type); + MCSymbol *ResSym = Asm->GetExternalSymbolSymbol(Buf.str()); + OutStreamer.EmitSymbolAttribute(ResSym, MCSA_Global); + if (MF.getFunction()->getLinkage() != GlobalValue::ExternalLinkage) + OutStreamer.EmitSymbolAttribute(ResSym, MCSA_Weak); + break; + } + CurrentFn = MF.getFunction(); + Buf.clear(); + raw_svector_ostream O(Buf); + XCoreResourceMDExtractor res(MF.getFunction()); + switch (Type) { + case PragmaStackWords: + { + uint64_t Value; + if (!Meta || !Meta->GetStackAttribute(*MF.getFunction(), Value)) + return false; + O << "\t.set\t"; + SmallString<32> NameBuf; + Asm->Mang->getNameWithPrefix(NameBuf, F, false); + O << NameBuf << getSuffix(Type); + O << ","; + O << Value; + break; + } + case StackWords: + { + const XCoreFunctionInfo *XFI = MF.getInfo(); + StackNode *exp = XFI->getNStackWords(); + if (exp->getID() == STUDefID) { + uint64_t Dummy; + if (Meta && Meta->GetStackAttribute(*MF.getFunction(), Dummy)) { + O << "\t.set\t"; + SmallString<32> NameBuf; + Asm->Mang->getNameWithPrefix(NameBuf, F, false); + O << NameBuf << getSuffix(Type); + O << ","; + SmallString<32> NameBuf; + Asm->Mang->getNameWithPrefix(NameBuf, F, false); + O << NameBuf << getSuffix(Type); + break; + } + return false; + } + O << "\t.set\t"; + SmallString<32> NameBuf; + Asm->Mang->getNameWithPrefix(NameBuf, F, false); + O << NameBuf << getSuffix(Type); + O << ","; + exp->toString(O); + break; + } + case MaxTimers: + { + StringRef s = res.getTimerResourceUsage(); + if (!s.empty()){ + O << "\t.set\t"; + SmallString<32> NameBuf; + Asm->Mang->getNameWithPrefix(NameBuf, F, false); + O << NameBuf << getSuffix(Type); + O << ","; + O << s; + } + break; + } + case MaxChanends: + { + StringRef s = res.getChanendResourceUsage(); + if(!s.empty()){ + O << "\t.set\t"; + SmallString<32> NameBuf; + Asm->Mang->getNameWithPrefix(NameBuf, F, false); + O << NameBuf << getSuffix(Type); + O << ","; + O << s; + } + break; + } + case MaxCores: + { + StringRef s = res.getThreadResourceUsage(); + if(!s.empty()){ + O << "\t.set\t"; + SmallString<32> NameBuf; + Asm->Mang->getNameWithPrefix(NameBuf, F, false); + O << NameBuf << getSuffix(Type); + O << ","; + O << s; + } + break; + } + } + O.flush(); + OutStreamer.EmitRawText(Buf.str()); + switch (MF.getFunction()->getLinkage()) { + default: assert(0 && "Unknown linkage type!"); + case Function::InternalLinkage: + case Function::PrivateLinkage: + break; + case GlobalValue::LinkOnceAnyLinkage: + case GlobalValue::LinkOnceODRLinkage: + case GlobalValue::WeakAnyLinkage: + case GlobalValue::WeakODRLinkage: + case GlobalValue::ExternalLinkage: + Buf.clear(); + Asm->Mang->getNameWithPrefix(Buf, MF.getFunction(), false); + Buf += getSuffix(Type); + MCSymbol *ResSym = Asm->GetExternalSymbolSymbol(Buf.str()); + OutStreamer.EmitSymbolAttribute(ResSym, MCSA_Global); + if (MF.getFunction()->getLinkage() != GlobalValue::ExternalLinkage) + OutStreamer.EmitSymbolAttribute(ResSym, MCSA_Weak); + break; + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/~AsmPrinter.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/~AsmPrinter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3a6d9e048a9bd7f969d18b8fdcd81036370e299c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Assembler/AsmPrinter/~AsmPrinter.cpp @@ -0,0 +1,2 @@ +virtual ~XCoreAsmPrinter(){ +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Emission/AsmInfo/MCAsmInfo.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Emission/AsmInfo/MCAsmInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4733a822df2aa0a0f484921d1777017bc16abae1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Emission/AsmInfo/MCAsmInfo.cpp @@ -0,0 +1,13 @@ +XCoreMCAsmInfo::XCoreMCAsmInfo(const Target &T, StringRef TT) { + SupportsDebugInformation = true; + Data16bitsDirective = "\t.short\t"; + Data32bitsDirective = "\t.long\t"; + Data64bitsDirective = 0; + ZeroDirective = "\t.space\t"; + CommentString = "#"; + PrivateGlobalPrefix = ".L"; + AscizDirective = ".asciiz"; + WeakRefDirective = "\t.weak\t"; + HasLEB128 = true; + ExceptionsType = ExceptionHandling::DwarfCFI; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Emission/MCTargetDesc/LLVMInitializeTargetMC.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Emission/MCTargetDesc/LLVMInitializeTargetMC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b96e682790667f5b346ff629dda280e5e0801cd1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Emission/MCTargetDesc/LLVMInitializeTargetMC.cpp @@ -0,0 +1,7 @@ +extern "C" void LLVMInitializeXCoreTargetMC() { + RegisterMCAsmInfoFn X(TheXCoreTarget, createXCoreMCAsmInfo); + TargetRegistry::RegisterMCCodeGenInfo(TheXCoreTarget, createXCoreMCCodeGenInfo); + TargetRegistry::RegisterMCInstrInfo(TheXCoreTarget, createXCoreMCInstrInfo); + TargetRegistry::RegisterMCRegInfo(TheXCoreTarget, createXCoreMCRegisterInfo); + TargetRegistry::RegisterMCSubtargetInfo(TheXCoreTarget, createXCoreMCSubtargetInfo); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Emission/MCTargetDesc/createMCAsmInfo.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Emission/MCTargetDesc/createMCAsmInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ed19128f49910c2d27948bbae9b32790e7ef3dcf --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Emission/MCTargetDesc/createMCAsmInfo.cpp @@ -0,0 +1,7 @@ +static MCAsmInfo *createXCoreMCAsmInfo(const Target &T, StringRef TT) { + MCAsmInfo *MAI = new XCoreMCAsmInfo(T, TT); + MachineLocation Dst(MachineLocation::VirtualFP); + MachineLocation Src(XCore::SP, 0); + MAI->addInitialFrameState(0, Dst, Src); + return MAI; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Emission/MCTargetDesc/createMCCodeGenInfo.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Emission/MCTargetDesc/createMCCodeGenInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0c4b20b67ea4e426d3f2d55142424bdf78fea950 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Emission/MCTargetDesc/createMCCodeGenInfo.cpp @@ -0,0 +1,5 @@ +static MCCodeGenInfo *createXCoreMCCodeGenInfo(StringRef TT, Reloc::Model RM, CodeModel::Model CM) { + MCCodeGenInfo *X = new MCCodeGenInfo(); + X->InitMCCodeGenInfo(RM, CM); + return X; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Emission/MCTargetDesc/createMCInstrInfo.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Emission/MCTargetDesc/createMCInstrInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4e75e5c57f4a8670b3a19900854883936a35c76e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Emission/MCTargetDesc/createMCInstrInfo.cpp @@ -0,0 +1,5 @@ +static MCInstrInfo *createXCoreMCInstrInfo() { + MCInstrInfo *X = new MCInstrInfo(); + InitXCoreMCInstrInfo(X); + return X; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Emission/MCTargetDesc/createMCRegisterInfo.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Emission/MCTargetDesc/createMCRegisterInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ca4b3f5c5570458299c2e681f5eddf09b8946111 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Emission/MCTargetDesc/createMCRegisterInfo.cpp @@ -0,0 +1,5 @@ +static MCRegisterInfo *createXCoreMCRegisterInfo(StringRef TT) { + MCRegisterInfo *X = new MCRegisterInfo(); + InitXCoreMCRegisterInfo(X, XCore::LR); + return X; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Emission/MCTargetDesc/createMCSubtargetInfo.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Emission/MCTargetDesc/createMCSubtargetInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..30d8d16f0edc5d7d1c93f17dfdf424e8b8c24efe --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Emission/MCTargetDesc/createMCSubtargetInfo.cpp @@ -0,0 +1,5 @@ +static MCSubtargetInfo *createXCoreMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS) { + MCSubtargetInfo *X = new MCSubtargetInfo(); + InitXCoreMCSubtargetInfo(X, TT, CPU, FS); + return X; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/FrameToArgsOffsetElim/FTAOElim.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/FrameToArgsOffsetElim/FTAOElim.cpp new file mode 100644 index 0000000000000000000000000000000000000000..246aed2bd7e0440bdeb11d57132d657b58c40e08 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/FrameToArgsOffsetElim/FTAOElim.cpp @@ -0,0 +1,2 @@ +XCoreFTAOElim() : FunctionPass(ID) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/FrameToArgsOffsetElim/XCoreFTAOElim.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/FrameToArgsOffsetElim/XCoreFTAOElim.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f7a1a1415db832540fb6c850d4cf6ede91113354 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/FrameToArgsOffsetElim/XCoreFTAOElim.cpp @@ -0,0 +1,2 @@ +XCoreFTAOElim() : MachineFunctionPass(ID) { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/FrameToArgsOffsetElim/createPass.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/FrameToArgsOffsetElim/createPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e893e3245ee3dc509be977cc7b1eb1255547fe20 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/FrameToArgsOffsetElim/createPass.cpp @@ -0,0 +1,3 @@ +FunctionPass *llvm::createXCoreFrameToArgsOffsetEliminationPass() { + return new XCoreFTAOElim(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/FrameToArgsOffsetElim/getPassName.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/FrameToArgsOffsetElim/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0bf93850ec6ecb540f8396365e3f5949ef7f6c22 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/FrameToArgsOffsetElim/getPassName.cpp @@ -0,0 +1,3 @@ +virtual const char *getPassName() const { + return "XCore FRAME_TO_ARGS_OFFSET Elimination"; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/FrameToArgsOffsetElim/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/FrameToArgsOffsetElim/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..eb7ca2a958fa44349a149b0010861c1dec6790c4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/FrameToArgsOffsetElim/runOnMachineFunction.cpp @@ -0,0 +1,23 @@ +bool XCoreFTAOElim::runOnMachineFunction(MachineFunction &MF) { + const TargetInstrInfo *TII = MF.getTarget().getInstrInfo(); + unsigned StackSize = MF.getFrameInfo()->getStackSize(); + if (!isImmU16(StackSize)) { + errs() << "FrameToArgsOffsetElimination stack size too big: " << StackSize << "\n"; + abort(); + } + unsigned Opc = isImmU6(StackSize) ? XCore::LDC_ru6 : XCore::LDC_lru6; + unsigned Imm = StackSize; + for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); MFI != E; ++MFI) { + MachineBasicBlock *MBB = MFI; + for (MachineBasicBlock::iterator MBBI = MBB->begin(), EE = MBB->end(); MBBI != EE; ++MBBI) { + if (MBBI->getOpcode() == XCore::FRAME_TO_ARGS_OFFSET) { + MachineInstr *OldInst = MBBI; + DebugLoc dl = OldInst->getDebugLoc(); + unsigned Dest = OldInst->getOperand(0).getReg(); + MBBI = BuildMI(*MBB, MBBI, dl, TII->get(Opc)).addReg(Dest).addImm(Imm); + OldInst->eraseFromParent(); + } + } + } + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/LoopMetadataLowering/LoopMetadataLowering.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/LoopMetadataLowering/LoopMetadataLowering.cpp new file mode 100644 index 0000000000000000000000000000000000000000..953838522ff09e67f0ad79402ddcb1be9866d438 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/LoopMetadataLowering/LoopMetadataLowering.cpp @@ -0,0 +1,3 @@ +XCoreLoopMetadataLowering() : FunctionPass(ID) { + initializeXCoreLoopMetadataLoweringPass(*PassRegistry::getPassRegistry()); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/LoopMetadataLowering/createPass.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/LoopMetadataLowering/createPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7b0f222770864ea550b4f88f072a2204cdc08137 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/LoopMetadataLowering/createPass.cpp @@ -0,0 +1,3 @@ +FunctionPass *llvm::createXCoreLoopMetadataLowering() { + return new XCoreLoopMetadataLowering(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/LoopMetadataLowering/getAnalysisUsage.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/LoopMetadataLowering/getAnalysisUsage.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8ec5bdd161c9d6eef14102c9f0ba289dd4c38162 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/LoopMetadataLowering/getAnalysisUsage.cpp @@ -0,0 +1,3 @@ +virtual void getAnalysisUsage(AnalysisUsage &AU) const { + AU.setPreservesAll(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/LoopMetadataLowering/runOnFunction.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/LoopMetadataLowering/runOnFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..aa2527ee5cb19412db7ea64955f9c6877af6b3d4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/LoopMetadataLowering/runOnFunction.cpp @@ -0,0 +1,23 @@ +bool XCoreLoopMetadataLowering::runOnFunction(Function &F) { + bool madeChange = false; + Module * m = F.getParent(); + unsigned loopKind = m->getMDKindID("xta.loop"); + unsigned xtaLoopLabelKind = m->getMDKindID("xta.loop_labels"); + + for (inst_iterator I = inst_begin(F), E = inst_end(F); I != E; ++I){ + Instruction * inst = &*I; + if(MDNode * md = inst->getMetadata(loopKind)){ + IRBuilder<> Builder(inst->getParent(), inst); + Function * Fn = Intrinsic::getDeclaration(m, Intrinsic::xcore_loopmarker); + Builder.CreateCall2(Fn, ConstantInt::get(Type::getInt32Ty(m->getContext()), loopKind, false), md); + madeChange = true; + } + if(MDNode * md = inst->getMetadata(xtaLoopLabelKind)){ + IRBuilder<> Builder(inst->getParent(), inst); + Function * Fn = Intrinsic::getDeclaration(m, Intrinsic::xcore_loopmarker); + Builder.CreateCall2(Fn, ConstantInt::get(Type::getInt32Ty(m->getContext()), xtaLoopLabelKind, false), md); + madeChange = true; + } + } + return madeChange; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/LoopMetadataLowering/~LoopMetadataLowering.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/LoopMetadataLowering/~LoopMetadataLowering.cpp new file mode 100644 index 0000000000000000000000000000000000000000..334a46043fe3b9906b82a6db0e92df8bb8bd45d0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/LoopMetadataLowering/~LoopMetadataLowering.cpp @@ -0,0 +1,2 @@ +virtual ~XCoreLoopMetadataLowering() { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/SimpleBranchOpt/SimpleBranchOpt.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/SimpleBranchOpt/SimpleBranchOpt.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b56f5e661a14b3fce1648465e707b50625802200 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/SimpleBranchOpt/SimpleBranchOpt.cpp @@ -0,0 +1,2 @@ +XCoreSimpleBranchOpt() : MachineFunctionPass(ID) { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/SimpleBranchOpt/createPass.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/SimpleBranchOpt/createPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..38e44dc8ea977c2ac5e5393a3c7160d52fa13906 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/SimpleBranchOpt/createPass.cpp @@ -0,0 +1,3 @@ +FunctionPass *llvm::createXCoreSimpleBranchOptPass() { + return new XCoreSimpleBranchOpt(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/SimpleBranchOpt/getPassName.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/SimpleBranchOpt/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6cb41569b49b33efcd76a81eb0b0391914668029 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/SimpleBranchOpt/getPassName.cpp @@ -0,0 +1,3 @@ +virtual const char *getPassName() const { + return "XCore branch to trap optimization"; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/SimpleBranchOpt/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/SimpleBranchOpt/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5ed1ab1b7c93f98d50c55ffa5b03dec8940da1f0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/SimpleBranchOpt/runOnMachineFunction.cpp @@ -0,0 +1,9 @@ +bool XCoreSimpleBranchOpt::runOnMachineFunction(MachineFunction &MF) { + const TargetInstrInfo *TII = MF.getTarget().getInstrInfo(); + for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; I++) { + MachineBasicBlock *MBB = I, *TBB = 0, *FBB = 0; + SmallVector Cond; + TII->AnalyzeBranch(*MBB, TBB, FBB, Cond, true); + } + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/StackAnalysisPrepare/StackAnalysisPrepare.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/StackAnalysisPrepare/StackAnalysisPrepare.cpp new file mode 100644 index 0000000000000000000000000000000000000000..862b2fca603aabf1244b580f72f603faddc8f834 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/StackAnalysisPrepare/StackAnalysisPrepare.cpp @@ -0,0 +1,3 @@ +XCoreStackAnalysisPrepare() : FunctionPass(ID) { + initializeXCoreStackAnalysisPreparePass(*PassRegistry::getPassRegistry()); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/StackAnalysisPrepare/createPass.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/StackAnalysisPrepare/createPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4f8195dd1360a5a7264e251088fea5e7dbc2d24d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/StackAnalysisPrepare/createPass.cpp @@ -0,0 +1,3 @@ +FunctionPass *llvm::createRISCVMergeBaseOffsetOptPass() { + return new RISCVMergeBaseOffsetOpt(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/StackAnalysisPrepare/getAnalysisUsage.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/StackAnalysisPrepare/getAnalysisUsage.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8ec5bdd161c9d6eef14102c9f0ba289dd4c38162 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/StackAnalysisPrepare/getAnalysisUsage.cpp @@ -0,0 +1,3 @@ +virtual void getAnalysisUsage(AnalysisUsage &AU) const { + AU.setPreservesAll(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/StackAnalysisPrepare/runOnFunction.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/StackAnalysisPrepare/runOnFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..94f78304b8664a741bc46620f58a2d8b88fdacae --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/StackAnalysisPrepare/runOnFunction.cpp @@ -0,0 +1,43 @@ +bool XCoreStackAnalysisPrepare::runOnFunction(Function &F) { + bool madeChange = false; + for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB) { + BasicBlock *B = &*BB; + for (BasicBlock::iterator I = B->begin(), IE = B->end(); I != IE; ++I) { + Instruction *Inst = &*I; + if (AllocaInst *AI = dyn_cast(Inst)) { + BasicBlock * b = I->getParent(); + if (isa (I) || isa (I) || isa (I) ||isa (I) || isa (I) || isa (I) ||isa (I) || isa (I) ||isa (I)) + return true; + if (IntrinsicInst *II = dyn_cast(I)) { + return (II->getIntrinsicID() == Intrinsic::xcore_stackusage); + } + return false; + if (!(I)) { + return false; + } + bool madeChange = false; + if (I->getParent() != B) { + BasicBlock::iterator InsertPt = B->getFirstNonPHI(); + if (I->hasOneUse()) { + I->moveBefore(parent); + } else { + Instruction *clone = I->clone(); + B->getInstList().insert(InsertPt, clone); + if (parent) + parent->replaceUsesOfWith(I, clone); + I = clone; + } + madeChange = true; + } + assert(!b->empty() && "cannot leave a BB empty"); + for (unsigned n = 0; n < I->getNumOperands(); n++) { + if (Instruction *i = dyn_cast(I->getOperand(n))) { + madeChange |= moveOperandsToBB(B, i, I); + } + } + madeChange |= madeChange; + } + } + } + return madeChange; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/StackAnalysisPrepare/~StackAnalysisPrepare.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/StackAnalysisPrepare/~StackAnalysisPrepare.cpp new file mode 100644 index 0000000000000000000000000000000000000000..04c2c39fd51f6d0d6b44d401dad1ca0c5eb96c65 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/StackAnalysisPrepare/~StackAnalysisPrepare.cpp @@ -0,0 +1,2 @@ +~XCoreStackAnalysisPrepare() { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/StackUsage/StackUsage.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/StackUsage/StackUsage.cpp new file mode 100644 index 0000000000000000000000000000000000000000..93090e5fd6422089facd4ba5525665b2bbfdbc5a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/StackUsage/StackUsage.cpp @@ -0,0 +1,2 @@ +XCoreStackUsage() : MachineFunctionPass(ID) { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/StackUsage/createPass.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/StackUsage/createPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..94143def502229a4af9738a503f4d8620ab9acf2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/StackUsage/createPass.cpp @@ -0,0 +1,3 @@ +FunctionPass *llvm::createXCoreStackUsage() { + return new XCoreStackUsage(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/StackUsage/getAnalysisUsage.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/StackUsage/getAnalysisUsage.cpp new file mode 100644 index 0000000000000000000000000000000000000000..30b5884ebae5ffdb33d795c44dfee8aa7371896d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/StackUsage/getAnalysisUsage.cpp @@ -0,0 +1,4 @@ +void getAnalysisUsage(AnalysisUsage &AU) const { + AU.setPreservesAll(); + MachineFunctionPass::getAnalysisUsage(AU); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/StackUsage/getPassName.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/StackUsage/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..eef2a2f09a7a36f5fc066077ac16a643340d8ebc --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/StackUsage/getPassName.cpp @@ -0,0 +1,3 @@ +const char *getPassName() const { + return "Calculates XCore stack usage"; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/StackUsage/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/StackUsage/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..500dde26b4a556a57f3e33632ecff91a3c69bf90 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Optimization/StackUsage/runOnMachineFunction.cpp @@ -0,0 +1,240 @@ +bool XCoreStackUsage::runOnMachineFunction(MachineFunction &Fn) { + XFI = Fn.getInfo (); + DEBUG(dbgs() << "XCore Stack Usage on function: " << Fn.getFunction()->getNameStr() <<"\n"); + int stackOffset = Fn.getFrameInfo()->getStackSize() / 4; + if(Fn.empty()){ + return true; + } + DEBUG(Fn.dump()); + MachineBasicBlock *MBB = &*Fn.begin(); + MachineInstr * MI = 0; + if(!MBB->empty()){ + MI = &*MBB->begin(); + } + StackContext StackContext(MI, stackOffset); + StackContext * currentStack = stackContext; + bool success = true; + for (MachineBasicBlock::iterator II = MBB->begin(), IE = MBB->end(); II != IE; ++II) { + MachineInstr * MI = &*II; + if (currentStack->seenInstr(MI, true)) { + return true; + } + else { + StackContext * parent = currentStack->getParent(); + while(parent){ + if(parent->seenInstr(MI, false)){ + return false; + } + parent = parent->getParent(); + } + } + if (MI->getOpcode() == XCore::STACKSAVE) { + StackContext * parent = currentStack->getParent(); + while(parent){ + if(parent->getSave() == MI){ + return false; + } + parent = parent->getParent(); + } + StackContext * nestedStack = new StackContext(MI, true); + currentStack->addChildStack(nestedStack); + currentStack = nestedStack; + } + if (MI->getOpcode() == XCore::STACKUP) { + StackContext * parent = currentStack->getParent(); + while(parent){ + if(parent->getSave() == MI){ + return false; + } + parent = parent->getParent(); + } + StackContext * nestedStack = new StackContext(MI, false); + currentStack->addChildStack(nestedStack); + currentStack = nestedStack; + } + if (MI->getDebugLoc().getIndirectCallInfo()) { + currentStack->addIndirectCallInfo(MI); + } + else if (MI->getDebugLoc().getParInfo()) { + currentStack->addParInfo(MI); + } + else if (MI->getOpcode() == XCore::WAITNONLOCAL || MI->getOpcode() == XCore::CHECKNONLOCAL) { + return false; + } + else if (MI->getDesc().isCall()) { + if (!currentStack->addFunction(MI)) + return false; + } + if (MI->getOpcode() == XCore::ALLOCA) { + StackNode * exp = XFI->getStackExpression(MI->getOperand(0).getImm()); + if(exp) + currentStack->addAlloca(exp); + + } + if (MI->getOpcode() == XCore::STACKDOWN) { + currentStack->endChildStack(MI); + currentStack = currentStack->getParent(); + } + if (MI->getOpcode() == XCore::STACKRESTORE) { + currentStack->endChildStack(MI); + while(currentStack->getParent()){ + currentStack = currentStack->getParent(); + if(currentStack->isSave()){ + currentStack = currentStack->getParent(); + break; + } + } + } + } + for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(), SE = + MBB->succ_end(); SI != SE; ++SI) { + MachineBasicBlock* SUCC = *SI; + success &= walkFunction(SUCC, currentStack); + } + return success; + if(walkFunction(Fn.begin(), &StackContext)){ + DEBUG(StackContext.dump()); + StackNode * nstackwords = StackContext.getNStackWords(); + XFI->setNStackWords(nstackwords); + DEBUG(nstackwords->toString(dbgs())); + DEBUG(dbgs()<<"\n"); + } + else { + XFI->setNStackWords(new STUDef()); + } + static llvm::Optional getCalledFunctionName(MachineInstr * MI) { + if(MI->getDesc().isIndirectBranch()) { + return llvm::Optional(); + } + for (unsigned i = 0; i < MI->getNumOperands(); ++i) { + if (MI->getOperand(i).isGlobal()) { + const GlobalValue *GV = MI->getOperand(i).getGlobal(); + if (const GlobalAlias *GA = dyn_cast(GV)) { + GV = GA->resolveAliasedGlobal(); + } + if (const Function *F = dyn_cast(GV)) { + return llvm::Optional(getMangledName(F)); + } else { + return llvm::Optional(); + } + } + if (MI->getOperand(i).isSymbol()) { + return llvm::Optional(MI->getOperand(i).getSymbolName()); + } + } + return llvm::Optional(); + assert(MI->getDesc().isCall() && "MI is not a function call."); + llvm::Optional name = getCalledFunctionName(MI); + if (name.hasValue()) { + seqFuncs.push_back(new STString(name.getValue(), true)); + return true; + } + else { + seqFuncs.push_back(new STUDef()); + return false; + } + llvm::Optional override; + if (MI->getDesc().isCall()) { + override = getCalledFunctionName(MI); + } + MDNode *meta = MI->getDebugLoc().getIndirectCallInfo(); + int n = meta->getNumOperands(); + for (int i = 0; i < n; ++i) { + MDString *callName = dyn_cast(meta->getOperand(i)); + if (!callName) + continue; + std::string s = callName->getString().str() + ".nstackwords"; + if (override.hasValue()) { + std::string o = override.getValue() + ".nstackwords"; + s = "($D " + o + " ? " + o + " $: " + s + ")"; + } + seqFuncs.push_back(new STString(s, false)); + } + llvm::Optional override; + MDNode *meta = MI->getDebugLoc().getParInfo(); + int n = meta->getNumOperands(); + std::string s = "(par.extra_stackwords"; + for (int i = 0; i < n; ++i) { + GlobalValue *call= dyn_cast(meta->getOperand(i)); + if (!call) + continue; + s += " + 1 + " + call->getName().str() + ".nstackwords"; + } + s += ")"; + seqFuncs.push_back(new STString(s, false)); + if (nStackWords) { + return nStackWords; + } + std::vector all; + for (std::vector::iterator I = nestedStacks.begin(), E = + nestedStacks.end(); I != E; ++I) { + all.push_back((*I)->getNStackWords()); + } + all.insert(all.end(), seqFuncs.begin(), seqFuncs.end()); + if (fixedStackSize) { + StackNode * l_lhs = new STSum(seqAllocs); + StackNode * l_rhs = new STMax(all); + StackNode * lhs = new STBinOp(l_lhs,l_rhs,STBinOp::STBinOpADD); + StackNode * rhs = new STInt(fixedStackSize); + nStackWords = new STBinOp(lhs, rhs, STBinOp::STBinOpADD); + } + else { + nStackWords = new STBinOp(new STSum(seqAllocs), new STMax(all), STBinOp::STBinOpADD); + } + StackNodeSumMaxCleaner cleaner; + StackNodeZeroEliminator zeroEliminator; + StackNodeMaxDuplicateCleaner maxDuplicateCleaner; + StackNodeUnDefProp unDefProp; + bool modified = true; + while (modified) { + modified = false; + while (maxDuplicateCleaner.run(&nStackWords)) { + modified = true; + } + while (cleaner.run(&nStackWords)) { + modified = true; + } + while (zeroEliminator.run(&nStackWords)) { + modified = true; + } + while (unDefProp.run(&nStackWords)) { + modified = true; + } + + } + return nStackWords; + indent(i); + dbgs() << "Stack begin: " << this <<" " ; + if(stackSaveInst) + stackSaveInst->dump(); + indent(i); + dbgs() << "Allocas:\n"; + for (std::vector::iterator I = seqAllocs.begin(), E = + seqAllocs.end(); I != E; ++I) { + indent(i); + (*I)->dump(); + dbgs() << "\n"; + } + indent(i); + dbgs() << "Functions:\n"; + for (std::vector::iterator I = seqFuncs.begin(), E = + seqFuncs.end(); I != E; ++I) { + indent(i); + (*I)->dump(); + dbgs() << "\n"; + } + indent(i); + dbgs() << "nestedStacks:\n"; + for (std::vector::iterator I = nestedStacks.begin(), E = + nestedStacks.end(); I != E; ++I) { + (*I)->dump(i + 1); + } + if (stackRestoreInst) { + indent(i); + dbgs() << "Stack end: "; + stackRestoreInst->dump(); + } + dbgs() <<"\n"; +} + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/GetCondBranchFromCond.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/GetCondBranchFromCond.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8045234dec87e223cc5abc9872f40ea9dccc2c79 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/GetCondBranchFromCond.cpp @@ -0,0 +1,9 @@ +static inline unsigned GetCondBranchFromCond(XCore::CondCode CC) { + switch (CC) { + default: llvm_unreachable("Illegal condition code!"); + case XCore::COND_TRUE : + return XCore::BRFT_lru6; + case XCore::COND_FALSE : + return XCore::BRFF_lru6; + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/GetCondFromBranchOpc.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/GetCondFromBranchOpc.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b99ad0ed50c5077b5b3b87b47d214bb2f1bb911a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/GetCondFromBranchOpc.cpp @@ -0,0 +1,11 @@ +static XCore::CondCode GetCondFromBranchOpc(unsigned BrOpc) { + if (IsBRT(BrOpc)) { + return XCore::COND_TRUE; + } + else if (IsBRF(BrOpc)) { + return XCore::COND_FALSE; + } + else { + return XCore::COND_INVALID; + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/GetInstSizeInBytes.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/GetInstSizeInBytes.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fee66a8d59ed802caac67018acbef5f4d4d9133d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/GetInstSizeInBytes.cpp @@ -0,0 +1,28 @@ +unsigned XCoreInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { + const MCInstrDesc &TID = MI->getDesc(); + switch(MI->getOpcode()) { + case XCore::INLINEASM: + return 4; + case XCore::BR_JT: + case XCore::BR_JT32: { + const MachineFunction * MF = MI->getParent()->getParent(); + const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo(); + unsigned EntrySize; + if (MI->getOpcode() == XCore::BR_JT) { + EntrySize = 4; + } + else { + assert(MI->getOpcode() == XCore::BR_JT32); + EntrySize = 4; + } + unsigned JTI = MI->getOperand(0).getIndex(); + const std::vector &JT = MJTI->getJumpTables(); + unsigned NumEntries = JT[JTI].MBBs.size(); + return NumEntries * EntrySize; + } + break; + default: + unsigned TSFlags = TID.TSFlags; + return (TSFlags & XCoreII::XCore_NumBytesMask); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/GetOppositeBranchCondition.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/GetOppositeBranchCondition.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c3fdd738bf27cc9d3e9137980791824e2aeb0bae --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/GetOppositeBranchCondition.cpp @@ -0,0 +1,9 @@ +static inline XCore::CondCode GetOppositeBranchCondition(XCore::CondCode CC) { + switch (CC) { + default: llvm_unreachable("Illegal condition code!"); + case XCore::COND_TRUE : + return XCore::COND_FALSE; + case XCore::COND_FALSE : + return XCore::COND_TRUE; + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/InstrInfo.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/InstrInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0cbdb9b4f5c294950fb070579e6be045758b03e3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/InstrInfo.cpp @@ -0,0 +1,2 @@ +XCoreInstrInfo::XCoreInstrInfo() : XCoreGenInstrInfo(XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP), RI(*this) { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/IsBRF.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/IsBRF.cpp new file mode 100644 index 0000000000000000000000000000000000000000..80e3781fc9e0dcf5ef871a6378c6f109699380e7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/IsBRF.cpp @@ -0,0 +1,3 @@ +static inline bool IsBRF(unsigned BrOpc) { + return BrOpc == XCore::BRFF_ru6|| BrOpc == XCore::BRFF_lru6 || BrOpc == XCore::BRBF_ru6 || BrOpc == XCore::BRBF_lru6; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/IsBRT.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/IsBRT.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6f26d2341a263e1a79b71fc7a52c2e27df285cd1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/IsBRT.cpp @@ -0,0 +1,3 @@ +static inline bool IsBRT(unsigned BrOpc) { + return BrOpc == XCore::BRFT_ru6 || BrOpc == XCore::BRFT_lru6 || BrOpc == XCore::BRBT_ru6 || BrOpc == XCore::BRBT_lru6; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/IsBRU.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/IsBRU.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a0c66d763af767db111636123563bbd32f4b336a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/IsBRU.cpp @@ -0,0 +1,3 @@ +static inline bool IsBRU(unsigned BrOpc) { + return BrOpc == XCore::BRFU_u6 || BrOpc == XCore::BRFU_lu6 || BrOpc == XCore::BRBU_u6 || BrOpc == XCore::BRBU_lu6; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/IsBR_JT.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/IsBR_JT.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6d508048d910b99edf952fa47de39ad4497b485e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/IsBR_JT.cpp @@ -0,0 +1,3 @@ +static inline bool IsBR_JT(unsigned BrOpc) { + return BrOpc == XCore::BR_JT || BrOpc == XCore::BR_JT32; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/IsCondBranch.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/IsCondBranch.cpp new file mode 100644 index 0000000000000000000000000000000000000000..55335fd6d65c002404540e7a59bac4431ed1408b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/IsCondBranch.cpp @@ -0,0 +1,3 @@ +static inline bool IsCondBranch(unsigned BrOpc) { + return BrOpc == XCore::BRFT_ru6 || BrOpc == XCore::BRFT_lru6 || BrOpc == XCore::BRBT_ru6 || BrOpc == XCore::BRBT_lru6 || BrOpc == XCore::BRFF_ru6|| BrOpc == XCore::BRFF_lru6 || BrOpc == XCore::BRBF_ru6 || BrOpc == XCore::BRBF_lru6; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/analyzeBranch.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/analyzeBranch.cpp new file mode 100644 index 0000000000000000000000000000000000000000..62bb8956a9d7066d799fb2744edd2235cde2a043 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/analyzeBranch.cpp @@ -0,0 +1,68 @@ +bool XCoreInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl &Cond, bool AllowModify) const { + MachineBasicBlock::iterator I = MBB.end(); + if (I == MBB.begin()) + return false; + --I; + while (I->isDebugValue()) { + if (I == MBB.begin()) + return false; + --I; + } + if (!isUnpredicatedTerminator(I)) + return false; + MachineInstr *LastInst = I; + if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { + if (IsBRU(LastInst->getOpcode())) { + TBB = LastInst->getOperand(0).getMBB(); + return false; + } + XCore::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode()); + if (BranchCode == XCore::COND_INVALID) + return true; + if (AllowModify && EliminateCondBranchToTrap(MBB, LastInst, LastInst->getOperand(1).getMBB(), BranchCode)) + return false; + TBB = LastInst->getOperand(1).getMBB(); + Cond.push_back(MachineOperand::CreateImm(BranchCode)); + Cond.push_back(LastInst->getOperand(0)); + return false; + } + MachineInstr *SecondLastInst = I; + if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I)) + return true; + unsigned SecondLastOpc = SecondLastInst->getOpcode(); + XCore::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc); + if (BranchCode != XCore::COND_INVALID + && IsBRU(LastInst->getOpcode())) { + if (AllowModify && EliminateCondBranchToTrap(MBB, SecondLastInst, SecondLastInst->getOperand(1).getMBB(), BranchCode)) { + TBB = LastInst->getOperand(0).getMBB(); + return false; + } + if (AllowModify && IsTrapBB(*LastInst->getOperand(0).getMBB())) { + TBB = SecondLastInst->getOperand(1).getMBB(); + BuildMI(MBB, SecondLastInst, LastInst->getDebugLoc(), get(GetECallFromCond(GetOppositeBranchCondition(BranchCode)))).addReg(SecondLastInst->getOperand(0).getReg()); + BuildMI(MBB, SecondLastInst, LastInst->getDebugLoc(), get(XCore::BRFU_lu6)).addMBB(TBB); + SecondLastInst->eraseFromParent(); + LastInst->eraseFromParent(); + return false; + } + TBB = SecondLastInst->getOperand(1).getMBB(); + Cond.push_back(MachineOperand::CreateImm(BranchCode)); + Cond.push_back(SecondLastInst->getOperand(0)); + FBB = LastInst->getOperand(0).getMBB(); + return false; + } + if (IsBRU(SecondLastInst->getOpcode()) && IsBRU(LastInst->getOpcode())) { + TBB = SecondLastInst->getOperand(0).getMBB(); + I = LastInst; + if (AllowModify) + I->eraseFromParent(); + return false; + } + if (IsBR_JT(SecondLastInst->getOpcode()) && IsBRU(LastInst->getOpcode())) { + I = LastInst; + if (AllowModify) + I->eraseFromParent(); + return true; + } + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/copyPhysReg.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/copyPhysReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cc5a1e736e77d424593dd4752d4e0f6ae31917ad --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/copyPhysReg.cpp @@ -0,0 +1,17 @@ +void XCoreInstrInfo::copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const { + bool GRDest = XCore::GRRegsRegClass.contains(DestReg); + bool GRSrc = XCore::GRRegsRegClass.contains(SrcReg); + if (GRDest && GRSrc) { + BuildMI(MBB, I, DL, get(XCore::ADD_2rus), DestReg).addReg(SrcReg, getKillRegState(KillSrc)).addImm(0); + return; + } + if (GRDest && SrcReg == XCore::SP) { + BuildMI(MBB, I, DL, get(XCore::LDAWSP_ru6), DestReg).addImm(0); + return; + } + if (DestReg == XCore::SP && GRSrc) { + BuildMI(MBB, I, DL, get(XCore::SETSP_1r)).addReg(SrcReg, getKillRegState(KillSrc)); + return; + } + llvm_unreachable("Impossible reg-to-reg copy"); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/emitFrameIndexDebugValue.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/emitFrameIndexDebugValue.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4693db1fcde710a743704634bdb2e46d4c8f82f0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/emitFrameIndexDebugValue.cpp @@ -0,0 +1,4 @@ +MachineInstr* XCoreInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, int FrameIx, uint64_t Offset, const MDNode *MDPtr, DebugLoc DL) const { + MachineInstrBuilder MIB = BuildMI(MF, DL, get(XCore::DBG_VALUE)).addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr); + return &*MIB; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/enum CondCode.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/enum CondCode.cpp new file mode 100644 index 0000000000000000000000000000000000000000..da9ddb9ff187eda9a196ac20fb9a734eaaa44e3e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/enum CondCode.cpp @@ -0,0 +1,5 @@ +enum CondCode { + COND_TRUE, + COND_FALSE, + COND_INVALID +}; diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/getRegisterInfo.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/getRegisterInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1b93d4da5ba29665781d3577daae3e901243d6b7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/getRegisterInfo.cpp @@ -0,0 +1,3 @@ +virtual const TargetRegisterInfo &getRegisterInfo() const { + return RI; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/insertBranch.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/insertBranch.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9c4ce411ab9de4965afa8574044f6230c1d691e2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/insertBranch.cpp @@ -0,0 +1,19 @@ +unsigned XCoreInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl &Cond, DebugLoc DL)const{ + assert(TBB && "InsertBranch must not be told to insert a fallthrough"); + assert((Cond.size() == 2 || Cond.size() == 0) && "Unexpected number of components!"); + if (FBB == 0) { + if (Cond.empty()) { + BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(TBB); + } + else { + unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); + BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()).addMBB(TBB); + } + return 1; + } + assert(Cond.size() == 2 && "Unexpected number of components!"); + unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); + BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()).addMBB(TBB); + BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(FBB); + return 2; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/isLoadFromStackSlot.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/isLoadFromStackSlot.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5991d4866b8624bb1ca8561f5b5a28f85828c2a5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/isLoadFromStackSlot.cpp @@ -0,0 +1,10 @@ +unsigned XCoreInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const{ + int Opcode = MI->getOpcode(); + if (Opcode == XCore::LDWFI) { + if ((MI->getOperand(1).isFI()) && (MI->getOperand(2).isImm()) && (isZeroImm(MI->getOperand(2)))) { + FrameIndex = MI->getOperand(1).getIndex(); + return MI->getOperand(0).getReg(); + } + } + return 0; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/isStoreToStackSlot.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/isStoreToStackSlot.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c14bf6bb565c560dbf072204e74412aea519978c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/isStoreToStackSlot.cpp @@ -0,0 +1,10 @@ +unsigned XCoreInstrInfo::isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const { + int Opcode = MI->getOpcode(); + if (Opcode == XCore::STWFI) { + if ((MI->getOperand(1).isFI()) && (MI->getOperand(2).isImm()) && (isZeroImm(MI->getOperand(2)))) { + FrameIndex = MI->getOperand(1).getIndex(); + return MI->getOperand(0).getReg(); + } + } + return 0; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/isZeroImm.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/isZeroImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..dca82641f569cc614ef0dc6cd2fb91c28f894ecd --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/isZeroImm.cpp @@ -0,0 +1,3 @@ +static bool isZeroImm(const MachineOperand &op) { + return op.isImm() && op.getImm() == 0; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/loadRegFromStackSlot.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/loadRegFromStackSlot.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d705f450aff94caf71f0a83dc9b19b4bde58e14d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/loadRegFromStackSlot.cpp @@ -0,0 +1,6 @@ +void XCoreInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const { + DebugLoc DL; + if (I != MBB.end()) + DL = I->getDebugLoc(); + BuildMI(MBB, I, DL, get(XCore::LDWFI), DestReg).addFrameIndex(FrameIndex).addImm(0); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/removeBranch.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/removeBranch.cpp new file mode 100644 index 0000000000000000000000000000000000000000..19fb98e911cf122195cef93a18ebe4f3a7cc4797 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/removeBranch.cpp @@ -0,0 +1,22 @@ +unsigned XCoreInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { + MachineBasicBlock::iterator I = MBB.end(); + if (I == MBB.begin()) + return 0; + --I; + while (I->isDebugValue()) { + if (I == MBB.begin()) + return 0; + --I; + } + if (!IsBRU(I->getOpcode()) && !IsCondBranch(I->getOpcode())) + return 0; + I->eraseFromParent(); + I = MBB.end(); + if (I == MBB.begin()) + return 1; + --I; + if (!IsCondBranch(I->getOpcode())) + return 1; + I->eraseFromParent(); + return 2; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/reverseBranchCondition.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/reverseBranchCondition.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5c6a78b4ecc17db49750d2836a6fa1ec29fabbd4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/reverseBranchCondition.cpp @@ -0,0 +1,5 @@ +bool XCoreInstrInfo::ReverseBranchCondition(SmallVectorImpl &Cond) const { + assert((Cond.size() == 2) && "Invalid XCore branch condition!"); + Cond[0].setImm(GetOppositeBranchCondition((XCore::CondCode)Cond[0].getImm())); + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/storeRegToStackSlot.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/storeRegToStackSlot.cpp new file mode 100644 index 0000000000000000000000000000000000000000..55c1cf1faf52f971d3cbe3458c3d0603c7d3c4b0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/InstrInfo/storeRegToStackSlot.cpp @@ -0,0 +1,8 @@ +void XCoreInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const { + DebugLoc DL; + if (I != MBB.end()) + DL = I->getDebugLoc(); + MachineFrameInfo * MFI = MBB.getParent()->getFrameInfo(); + MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIndex), MachineMemOperand::MOStore, MFI->getObjectSize(FrameIndex), MFI->getObjectAlignment(FrameIndex)); + BuildMI(MBB, I, DL, get(XCore::STWFI)).addReg(SrcReg, getKillRegState(isKill)).addFrameIndex(FrameIndex).addMemOperand(MMO).addImm(0); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/MachineFunctionInfo/Call.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/MachineFunctionInfo/Call.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a873854d75e7effaf87a21964d121778a32509b5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/MachineFunctionInfo/Call.cpp @@ -0,0 +1,2 @@ +XCoreCall(unsigned T) : Type(T) { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/MachineFunctionInfo/ExternalSymbolCall.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/MachineFunctionInfo/ExternalSymbolCall.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9fc91e5f81b57378e02ac9cbf92f7a34a77c2661 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/MachineFunctionInfo/ExternalSymbolCall.cpp @@ -0,0 +1,2 @@ +XCoreExternalSymbolCall(const char *S) : XCoreCall(XCoreCall::ExternalSymbolType), Sym(S){ +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/MachineFunctionInfo/FunctionCall.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/MachineFunctionInfo/FunctionCall.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e0572101f7a7aaeb1204fd2f43acb96bc08d6787 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/MachineFunctionInfo/FunctionCall.cpp @@ -0,0 +1,2 @@ +XCoreFunctionCall(const Function *F) : XCoreCall(XCoreCall::FunctionType), Fn(F) { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/MachineFunctionInfo/FunctionInfo.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/MachineFunctionInfo/FunctionInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cc1e06f08120f2cbecf8ee233a09968afe128f7b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/MachineFunctionInfo/FunctionInfo.cpp @@ -0,0 +1,2 @@ +XCoreFunctionInfo() : LRSpillSlotSet(false), LRSpillSlot(0), FPSpillSlot(0), VarArgsFrameIndex(0), ReturnStackOffsetSet(false), ReturnStackOffset(0), HasIndirectCalls(false), NStackWords(0){ +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/MachineFunctionInfo/FunctionInfo2.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/MachineFunctionInfo/FunctionInfo2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d1b7c5eb5a79b8ad988072c8f7db2f9f7498aeab --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/MachineFunctionInfo/FunctionInfo2.cpp @@ -0,0 +1,2 @@ +explicit XCoreFunctionInfo(MachineFunction &MF) : LRSpillSlotSet(false), LRSpillSlot(0), FPSpillSlot(0), VarArgsFrameIndex(0), ReturnStackOffsetSet(false), ReturnStackOffset(0), HasIndirectCalls(false), NStackWords(0) { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/MachineFunctionInfo/classof1.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/MachineFunctionInfo/classof1.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d67b237b26c99f3113f6662255dc8040d9a394d6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/MachineFunctionInfo/classof1.cpp @@ -0,0 +1,3 @@ +static inline bool classof(const XCoreCall *) { + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/MachineFunctionInfo/classof2.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/MachineFunctionInfo/classof2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..006db3209de2ff39a514628ea92aeb7aecfe2b0b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/MachineFunctionInfo/classof2.cpp @@ -0,0 +1,3 @@ +static inline bool classof(const XCoreFunctionCall *) { + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/MachineFunctionInfo/classof3.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/MachineFunctionInfo/classof3.cpp new file mode 100644 index 0000000000000000000000000000000000000000..62928f0c20b177d8ff3869ea63180efae444fa78 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/MachineFunctionInfo/classof3.cpp @@ -0,0 +1,3 @@ +static inline bool classof(const XCoreCall *C) { + return C->getType() == XCoreCall::FunctionType; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/MachineFunctionInfo/classof4.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/MachineFunctionInfo/classof4.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d67b237b26c99f3113f6662255dc8040d9a394d6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/MachineFunctionInfo/classof4.cpp @@ -0,0 +1,3 @@ +static inline bool classof(const XCoreCall *) { + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/MachineFunctionInfo/classof5.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/MachineFunctionInfo/classof5.cpp new file mode 100644 index 0000000000000000000000000000000000000000..006db3209de2ff39a514628ea92aeb7aecfe2b0b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/MachineFunctionInfo/classof5.cpp @@ -0,0 +1,3 @@ +static inline bool classof(const XCoreFunctionCall *) { + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/MachineFunctionInfo/getCalls.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/MachineFunctionInfo/getCalls.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bfb175ecb391e0791d505ddb515a2560432a07a5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/MachineFunctionInfo/getCalls.cpp @@ -0,0 +1,3 @@ +const std::vector &getCalls() const { + return Calls; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/MachineFunctionInfo/getFunction.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/MachineFunctionInfo/getFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1139cffe0aab3f0e3efb65acc6f4d7469a236e57 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/MachineFunctionInfo/getFunction.cpp @@ -0,0 +1,3 @@ +const Function *getFunction() { + return Fn; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/MachineFunctionInfo/getHasIndirectCalls.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/MachineFunctionInfo/getHasIndirectCalls.cpp new file mode 100644 index 0000000000000000000000000000000000000000..681160f10d173e926d85c4b339dcc0fbfb012023 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/MachineFunctionInfo/getHasIndirectCalls.cpp @@ -0,0 +1,3 @@ +bool getHasIndirectCalls() const { + return HasIndirectCalls; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/MachineFunctionInfo/getSymbol.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/MachineFunctionInfo/getSymbol.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c81941c6cd5f95e5b359d4e04e9853c2567e0a81 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/MachineFunctionInfo/getSymbol.cpp @@ -0,0 +1,3 @@ +const char *getSymbol() { + return Sym; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/MachineFunctionInfo/getType.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/MachineFunctionInfo/getType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a7baf176b84d7c10036b8ba1b7da0b4f1562f5d0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/MachineFunctionInfo/getType.cpp @@ -0,0 +1,3 @@ +unsigned getType() const { + return Type; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/MachineFunctionInfo/getVarArgsFrameIndex.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/MachineFunctionInfo/getVarArgsFrameIndex.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2ad7e3a6df3da4abe5143ddf276a5a8dd208c0d1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/MachineFunctionInfo/getVarArgsFrameIndex.cpp @@ -0,0 +1,3 @@ +int getVarArgsFrameIndex() const { + return VarArgsFrameIndex; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/MachineFunctionInfo/setHasIndirectCalls.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/MachineFunctionInfo/setHasIndirectCalls.cpp new file mode 100644 index 0000000000000000000000000000000000000000..dc77a18f5e94329038670fb719c9966a60a23fd2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/MachineFunctionInfo/setHasIndirectCalls.cpp @@ -0,0 +1,3 @@ +void setHasIndirectCalls(bool val) { + HasIndirectCalls = val; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/MachineFunctionInfo/setVarArgsFrameIndex.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/MachineFunctionInfo/setVarArgsFrameIndex.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f57e9f48831fa353d584c49669f0413fc095c594 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/MachineFunctionInfo/setVarArgsFrameIndex.cpp @@ -0,0 +1,3 @@ +void setVarArgsFrameIndex(int Index) { + VarArgsFrameIndex = Index; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/MachineFunctionInfo/~FunctionInfo.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/MachineFunctionInfo/~FunctionInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1e64dd97c27d485da7508db96fd01222af9b2648 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/MachineFunctionInfo/~FunctionInfo.cpp @@ -0,0 +1,32 @@ +XCoreFunctionInfo::~XCoreFunctionInfo() { + for (std::vector::iterator it = Calls.begin(),end = Calls.end(); it != end; ++it) { + delete(*it); + } + for(std::vector ::iterator I = ResourceSymbolNames.begin(), E = ResourceSymbolNames.end(); I!=E; ++I){ + delete (*I); + } + if (sn->isLeaf()) { + delete sn; + return; + } + std::vector *children = sn->getChildren(); + for(unsigned i = 0, e = children->size(); i != e; ++i) { + deleteTree((*children)[i]); + } + children->clear(); + delete sn; + for (unsigned i = 0, e = AllocaExpressions.size(); i != e; ++i){ + if (AllocaExpressions[i]) { + if (sn->isLeaf()) { + delete sn; + return; + } + std::vector *children = sn->getChildren(); + for(unsigned i = 0, e = children->size(); i != e; ++i) { + deleteTree((*children)[i]); + } + children->clear(); + delete sn; + } + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/Subtarget/Subtarget.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/Subtarget/Subtarget.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b70e36db9ee4fb0cd1e5595ba9e01e7196318d4e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/Subtarget/Subtarget.cpp @@ -0,0 +1,2 @@ +XCoreSubtarget::XCoreSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS) : XCoreGenSubtargetInfo(TT, CPU, FS) { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/TargetInfo/LLVMInitializeTargetInfo.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/TargetInfo/LLVMInitializeTargetInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d05f6c22bf6a89bc603ad7054161cd248dd73054 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/TargetInfo/LLVMInitializeTargetInfo.cpp @@ -0,0 +1,3 @@ +extern "C" void LLVMInitializeXCoreTargetInfo() { + RegisterTarget X(TheXCoreTarget, "xcore", "XCore"); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/TargetMachine/LLVMInitializeTarget.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/TargetMachine/LLVMInitializeTarget.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c0368df6a5a79d4044bbfc289cebbc8c67349bf4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/TargetMachine/LLVMInitializeTarget.cpp @@ -0,0 +1,3 @@ +extern "C" void LLVMInitializeXCoreTarget() { + RegisterTargetMachine X(TheXCoreTarget); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/TargetMachine/TargetMachine.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/TargetMachine/TargetMachine.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d2dc20e11ca67beea0621309e8d5cd2c7fc3dcbf --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/TargetMachine/TargetMachine.cpp @@ -0,0 +1,2 @@ +XCoreTargetMachine::XCoreTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, Reloc::Model RM, CodeModel::Model CM) : LLVMTargetMachine(T, TT, CPU, FS, RM, CM), Subtarget(TT, CPU, FS), DataLayout("e-p:32:32:32-a0:0:32-f32:32:32-f64:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-v64:32:32-v128:32:32-n32"), InstrInfo(), FrameLowering(Subtarget), TLInfo(*this), TSInfo(*this) { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/TargetMachine/addInstSelector.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/TargetMachine/addInstSelector.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2946990d59d37b36bef9afba365587b8658f7e38 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/TargetMachine/addInstSelector.cpp @@ -0,0 +1,4 @@ +bool XCoreTargetMachine::addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel) { + PM.add(createXCoreISelDag(*this, OptLevel)); + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/TargetMachine/addPreEmitPass.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/TargetMachine/addPreEmitPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1bec6b8cd05e4dcd9a0e716ef69d1ecff3054a64 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/TargetMachine/addPreEmitPass.cpp @@ -0,0 +1,7 @@ +bool XCoreTargetMachine::addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel) { + if (OptLevel == 0) + PM.add(createXCoreSimpleBranchOptPass()); + PM.add(createXCoreFrameToArgsOffsetEliminationPass()); + PM.add(createXCoreStackUsage()); + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/TargetMachine/addPreISel.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/TargetMachine/addPreISel.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8adef4ad7e0fdbab03f159d42f5353437df9a124 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/TargetMachine/addPreISel.cpp @@ -0,0 +1,6 @@ +bool XCoreTargetMachine::addPreISel(PassManagerBase &PM, CodeGenOpt::Level OptLevel) { + PM.add(createXCoreStackAnalysisPrepare()); + PM.add(createXCoreLoopMetadataLowering()); + PM.add(createXCoreLowerTwoStageResourceAllocPass()); + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/TargetMachine/getFrameLowering.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/TargetMachine/getFrameLowering.cpp new file mode 100644 index 0000000000000000000000000000000000000000..660b7cc2c49a72f4ad0fb4de75183275609a2c3f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/TargetMachine/getFrameLowering.cpp @@ -0,0 +1,3 @@ +const TargetFrameLowering *getFrameLowering() const override { + return FrameLowering.get(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/TargetMachine/getInstrInfo.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/TargetMachine/getInstrInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..60c000dd8827314181cd9800c1596197e1427aee --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/TargetMachine/getInstrInfo.cpp @@ -0,0 +1,3 @@ +virtual const XCoreInstrInfo *getInstrInfo() const { + return &InstrInfo; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/TargetMachine/getRegisterInfo.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/TargetMachine/getRegisterInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8dc5612eefd93fd87866dea18ff17cb69e824ef5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/TargetMachine/getRegisterInfo.cpp @@ -0,0 +1,3 @@ +virtual const TargetRegisterInfo *getRegisterInfo() const { + return &InstrInfo.getRegisterInfo(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/TargetMachine/getSelectionDAGInfo.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/TargetMachine/getSelectionDAGInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bd5488660f0be42eacec786e2943a99d7170621a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/TargetMachine/getSelectionDAGInfo.cpp @@ -0,0 +1,3 @@ +virtual const XCoreSelectionDAGInfo* getSelectionDAGInfo() const { + return &TSInfo; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/TargetMachine/getSubtargetImpl.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/TargetMachine/getSubtargetImpl.cpp new file mode 100644 index 0000000000000000000000000000000000000000..412be8adc425311bd70ca5a8c4285accdcddc6e1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/TargetMachine/getSubtargetImpl.cpp @@ -0,0 +1,3 @@ +virtual const XCoreSubtarget *getSubtargetImpl() const { + return &Subtarget; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/TargetMachine/getTargetData.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/TargetMachine/getTargetData.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8c037d6ca3ebec3c8f54c7a1ebfc37d2eb5a669e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/TargetMachine/getTargetData.cpp @@ -0,0 +1,3 @@ +virtual const TargetData *getTargetData() const { + return &DataLayout; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/TargetMachine/getTargetLowering.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/TargetMachine/getTargetLowering.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b42659094823dfea1c2cc4795868c08213f8ea1b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/TargetMachine/getTargetLowering.cpp @@ -0,0 +1,3 @@ +virtual const XCoreTargetLowering *getTargetLowering() const { + return &TLInfo; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/TargetObjectFile/Initialize.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/TargetObjectFile/Initialize.cpp new file mode 100644 index 0000000000000000000000000000000000000000..41b78e99795c9e32e35213f0799596f1984c7baf --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/TargetObjectFile/Initialize.cpp @@ -0,0 +1,17 @@ +void XCoreTargetObjectFile::Initialize(MCContext &Ctx, const TargetMachine &TM){ + TargetLoweringObjectFileELF::Initialize(Ctx, TM); + DataSection = Ctx.getELFSection(".dp.data", ELF::SHT_PROGBITS, ELF::SHF_ALLOC | ELF::SHF_WRITE | ELF::XCORE_SHF_DP_SECTION, SectionKind::getDataRel()); + BSSSection = Ctx.getELFSection(".dp.bss", ELF::SHT_NOBITS, ELF::SHF_ALLOC | ELF::SHF_WRITE | ELF::XCORE_SHF_DP_SECTION, SectionKind::getBSS()); + MergeableConst4Section = 0; + MergeableConst8Section = 0; + MergeableConst16Section = 0; + TLSDataSection = DataSection; + TLSBSSSection = BSSSection; + ReadOnlySection = Ctx.getELFSection(".dp.rodata", ELF::SHT_PROGBITS, ELF::SHF_ALLOC | ELF::SHF_WRITE | ELF::XCORE_SHF_DP_SECTION, SectionKind::getReadOnlyWithRel()); + CPMergeableConst4Section = Ctx.getELFSection(".cp.rodata.cst4", ELF::SHT_PROGBITS, ELF::SHF_ALLOC | ELF::SHF_MERGE | ELF::XCORE_SHF_CP_SECTION, SectionKind::getMergeableConst4()); + CPMergeableConst8Section = Ctx.getELFSection(".cp.rodata.cst8", ELF::SHT_PROGBITS, ELF::SHF_ALLOC | ELF::SHF_MERGE | ELF::XCORE_SHF_CP_SECTION, SectionKind::getMergeableConst8()); + CPMergeableConst16Section = Ctx.getELFSection(".cp.rodata.cst16", ELF::SHT_PROGBITS, ELF::SHF_ALLOC | ELF::SHF_MERGE | ELF::XCORE_SHF_CP_SECTION, SectionKind::getMergeableConst16()); + CPReadOnlySection = Ctx.getELFSection(".cp.rodata", ELF::SHT_PROGBITS, ELF::SHF_ALLOC | ELF::XCORE_SHF_CP_SECTION, SectionKind::getReadOnlyWithRel()); + DataRelSection = DataRelLocalSection = DataSection; + DataRelROSection = DataRelROLocalSection = ReadOnlySection; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/TargetObjectFile/SelectSectionForGlobal.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/TargetObjectFile/SelectSectionForGlobal.cpp new file mode 100644 index 0000000000000000000000000000000000000000..dcaf9990c314d17bb0ed154ee8a30a5fa7bccbad --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/TargetObjectFile/SelectSectionForGlobal.cpp @@ -0,0 +1,14 @@ +const MCSection *XCoreTargetObjectFile::SelectSectionForGlobal(const GlobalValue *GV, SectionKind Kind, Mangler *Mang, const TargetMachine &TM) const { + bool EmitUniquedSection = Kind.isText() ? TM.getFunctionSections() : TM.getDataSections(); + if ((GV->isWeakForLinker() || EmitUniquedSection) && !Kind.isCommon() && !Kind.isBSS()) { + const char *Prefix = getSectionPrefixForGlobal(Kind); + SmallString<128> Name; + Name.append(Prefix, Prefix+strlen(Prefix)); + Mang->getNameWithPrefix(Name, GV, false); + return getContext().getELFSection(Name.str(), getXCoreSectionType(Kind), getXCoreSectionFlags(Kind, false), Kind); + } + if (Kind.isMergeable1ByteCString() || Kind.isMergeable2ByteCString() || Kind.isMergeable4ByteCString()) { + return ReadOnlySection; + } + return TargetLoweringObjectFileELF::SelectSectionForGlobal(GV, Kind, Mang, TM); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/TargetObjectFile/getExplicitSectionGlobal.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/TargetObjectFile/getExplicitSectionGlobal.cpp new file mode 100644 index 0000000000000000000000000000000000000000..850f716665cabbd1bf1fbf0d42daab9be185d1b4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/TargetObjectFile/getExplicitSectionGlobal.cpp @@ -0,0 +1,24 @@ +const MCSection *XCoreTargetObjectFile::getExplicitSectionGlobal(const GlobalValue *GV, SectionKind Kind, Mangler *Mang, const TargetMachine &TM) const { + const char *SectionName = GV->getSection().c_str(); + if (strncmp(Name, ".cp.", 4) == 0) + Kind = SectionKind::getReadOnly(); + bool IsCPRel = strncmp(SectionName, ".cp.", 4) == 0; + unsigned Flags = 0; + if (!K.isMetadata()) + Flags |= ELF::SHF_ALLOC; + if (K.isText()) + Flags |= ELF::SHF_EXECINSTR; + else if (IsCPRel) + Flags |= ELF::XCORE_SHF_CP_SECTION; + else + Flags |= ELF::XCORE_SHF_DP_SECTION; + if (K.isWriteable()) + Flags |= ELF::SHF_WRITE; + if (K.isMergeableCString() || K.isMergeableConst4() || K.isMergeableConst8() || K.isMergeableConst16()) + Flags |= ELF::SHF_MERGE; + if (K.isMergeableCString()) + Flags |= ELF::SHF_STRINGS; + if (K.isBSS() || K.isThreadBSS()) + return ELF::SHT_NOBITS; + return getContext().getELFSection(SectionName, ELF::SHT_PROGBITS, (Kind, IsCPRel), Kind); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/TargetObjectFile/getSectionForConstant.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/TargetObjectFile/getSectionForConstant.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5b064f2f755a23e0274200389495bf3163f6537f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Scheduling/TargetObjectFile/getSectionForConstant.cpp @@ -0,0 +1,9 @@ +const MCSection *XCoreTargetObjectFile::getSectionForConstant(SectionKind Kind) const { + if (Kind.isMergeableConst4()) + return CPMergeableConst4Section; + if (Kind.isMergeableConst8()) + return CPMergeableConst8Section; + if (Kind.isMergeableConst16()) + return CPMergeableConst16Section; + return CPReadOnlySection; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/FrameLowering/FrameLowering.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/FrameLowering/FrameLowering.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e6aef485d2d1cb243594d8d2dbb9627f8cc0a1b4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/FrameLowering/FrameLowering.cpp @@ -0,0 +1,2 @@ +XCoreFrameLowering::XCoreFrameLowering(const XCoreSubtarget &sti) : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 4, 0), STI(sti) { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/FrameLowering/emitEpilogue.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/FrameLowering/emitEpilogue.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cc3d23c9ef249e7aa039f4c29c40ffc898570c16 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/FrameLowering/emitEpilogue.cpp @@ -0,0 +1,63 @@ +void XCoreFrameLowering::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { + MachineFrameInfo *MFI = MF.getFrameInfo(); + MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); + const XCoreInstrInfo &TII = *static_cast(MF.getTarget().getInstrInfo()); + XCoreFunctionInfo *XFI = MF.getInfo(); + unsigned RetOpcode = MBBI->getOpcode(); + DebugLoc dl = MBBI->getDebugLoc(); + switch (RetOpcode) { + case XCore::RETSP_u6: + case XCore::RETSP_lu6: + case XCore::EH_RETURN: + break; + default: + assert(0 && "Can only insert epilog into returning blocks"); + } + bool FP = hasFP(MF); + if (FP) { + unsigned FramePtr = XCore::R10; + BuildMI(MBB, MBBI, dl, TII.get(XCore::SETSP_1r)).addReg(FramePtr); + } + int FrameSize = MFI->getStackSize(); + assert(FrameSize%4 == 0 && "Misaligned frame size"); + FrameSize/=4; + bool isU6 = isImmU6(FrameSize); + if (!isU6 && !isImmU16(FrameSize)) { + report_fatal_error("emitEpilogue Frame size too big: " + Twine(FrameSize)); + } + if (FP) { + int FPSpillOffset = MFI->getObjectOffset(XFI->getFPSpillSlot()); + FPSpillOffset += FrameSize*4; + loadFromStack(MBB, MBBI, XCore::R10, FPSpillOffset, dl, TII); + } + if (RetOpcode == XCore::EH_RETURN) { + unsigned EhStackReg = MBBI->getOperand(0).getReg(); + unsigned EhHandlerReg = MBBI->getOperand(1).getReg(); + BuildMI(MBB, MBBI, dl, TII.get(XCore::SETSP_1r)).addReg(EhStackReg); + BuildMI(MBB, MBBI, dl, TII.get(XCore::BAU_1r)).addReg(EhHandlerReg); + MBB.erase(MBBI); + } + else { + bool restoreLR = XFI->hasLRSpillSlot(); + if (restoreLR && (FrameSize == 0 || MFI->getObjectOffset(XFI->getLRSpillSlot()) != 0)) { + int LRSpillOffset = MFI->getObjectOffset(XFI->getLRSpillSlot()); + LRSpillOffset += FrameSize*4; + loadFromStack(MBB, MBBI, XCore::LR, LRSpillOffset, dl, TII); + restoreLR = false; + } + if (FrameSize) { + XCoreFunctionInfo *XFI = MF.getInfo(); + if (restoreLR) { + assert(MFI->getObjectOffset(XFI->getLRSpillSlot()) == 0); + assert(MBBI->getOpcode() == XCore::RETSP_u6|| MBBI->getOpcode() == XCore::RETSP_lu6); + int Opcode = (isU6) ? XCore::RETSP_u6 : XCore::RETSP_lu6; + BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize); + MBB.erase(MBBI); + } + else { + int Opcode = (isU6) ? XCore::LDAWSP_ru6_RRegs : XCore::LDAWSP_lru6_RRegs; + BuildMI(MBB, MBBI, dl, TII.get(Opcode), XCore::SP).addImm(FrameSize); + } + } + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/FrameLowering/emitPrologue.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/FrameLowering/emitPrologue.cpp new file mode 100644 index 0000000000000000000000000000000000000000..40dfe657cc4413d62664297c16f6a64194040a5a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/FrameLowering/emitPrologue.cpp @@ -0,0 +1,101 @@ +void XCoreFrameLowering::emitPrologue(MachineFunction &MF) const { + MachineBasicBlock &MBB = MF.front(); + MachineBasicBlock::iterator MBBI = MBB.begin(); + MachineFrameInfo *MFI = MF.getFrameInfo(); + MachineModuleInfo *MMI = &MF.getMMI(); + const XCoreRegisterInfo *RegInfo =static_cast(MF.getTarget().getRegisterInfo()); + const XCoreInstrInfo &TII =*static_cast(MF.getTarget().getInstrInfo()); + XCoreFunctionInfo *XFI = MF.getInfo(); + DebugLoc dl; + if (MFI->getMaxAlignment() > getStackAlignment()) + report_fatal_error("emitPrologue unsupported alignment: " +Twine(MFI->getMaxAlignment())); + bool FP = hasFP(MF); + bool Nested = MF.getFunction()-> + getAttributes().hasAttrSomewhere(Attribute::Nest); + + if (Nested) { + loadFromStack(MBB, MBBI, XCore::R11, 0, dl, TII); + } + int FrameSize = MFI->getStackSize(); + assert(FrameSize%4 == 0 && "Misaligned frame size"); + FrameSize/=4; + bool isU6 = isImmU6(FrameSize); + if (!isU6 && !isImmU16(FrameSize)) { + report_fatal_error("emitPrologue Frame size too big: " + Twine(FrameSize)); + } + bool emitFrameMoves = RegInfo->needsFrameMoves(MF); + bool saveLR = XFI->hasLRSpillSlot(); + if (FrameSize) { + bool LRSavedOnEntry = false; + int Opcode; + if (saveLR && (MFI->getObjectOffset(XFI->getLRSpillSlot()) == 0)) { + Opcode = (isU6) ? XCore::ENTSP_u6 : XCore::ENTSP_lu6; + MBB.addLiveIn(XCore::LR); + saveLR = false; + LRSavedOnEntry = true; + } + else { + Opcode = (isU6) ? XCore::EXTSP_u6 : XCore::EXTSP_lu6; + } + BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize); + if (emitFrameMoves) { + std::vector &Moves = MMI->getFrameMoves(); + MCSymbol *FrameLabel = MMI->getContext().CreateTempSymbol(); + BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(FrameLabel); + MachineLocation SPDst(MachineLocation::VirtualFP); + MachineLocation SPSrc(MachineLocation::VirtualFP, -FrameSize * 4); + Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc)); + if (LRSavedOnEntry) { + MachineLocation CSDst(MachineLocation::VirtualFP, 0); + MachineLocation CSSrc(XCore::LR); + Moves.push_back(MachineMove(FrameLabel, CSDst, CSSrc)); + } + } + } + if (saveLR) { + int LRSpillOffset = MFI->getObjectOffset(XFI->getLRSpillSlot()); + storeToStack(MBB, MBBI, XCore::LR, LRSpillOffset + FrameSize*4, dl, TII); + MBB.addLiveIn(XCore::LR); + if (emitFrameMoves) { + MCSymbol *SaveLRLabel = MMI->getContext().CreateTempSymbol(); + BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(SaveLRLabel); + MachineLocation CSDst(MachineLocation::VirtualFP, LRSpillOffset); + MachineLocation CSSrc(XCore::LR); + MMI->getFrameMoves().push_back(MachineMove(SaveLRLabel, CSDst, CSSrc)); + } + } + if (FP) { + int FPSpillOffset = MFI->getObjectOffset(XFI->getFPSpillSlot()); + storeToStack(MBB, MBBI, XCore::R10, FPSpillOffset + FrameSize*4, dl, TII); + MBB.addLiveIn(XCore::R10); + if (emitFrameMoves) { + MCSymbol *SaveR10Label = MMI->getContext().CreateTempSymbol(); + BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(SaveR10Label); + MachineLocation CSDst(MachineLocation::VirtualFP, FPSpillOffset); + MachineLocation CSSrc(XCore::R10); + MMI->getFrameMoves().push_back(MachineMove(SaveR10Label, CSDst, CSSrc)); + } + unsigned FramePtr = XCore::R10; + BuildMI(MBB, MBBI, dl, TII.get(XCore::LDAWSP_ru6), FramePtr).addImm(0); + if (emitFrameMoves) { + MCSymbol *FrameLabel = MMI->getContext().CreateTempSymbol(); + BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(FrameLabel); + MachineLocation SPDst(FramePtr); + MachineLocation SPSrc(MachineLocation::VirtualFP); + MMI->getFrameMoves().push_back(MachineMove(FrameLabel, SPDst, SPSrc)); + } + } + if (emitFrameMoves) { + std::vector &Moves = MMI->getFrameMoves(); + std::vector >&SpillLabels = XFI->getSpillLabels(); + for (unsigned I = 0, E = SpillLabels.size(); I != E; ++I) { + MCSymbol *SpillLabel = SpillLabels[I].first; + CalleeSavedInfo &CSI = SpillLabels[I].second; + int Offset = MFI->getObjectOffset(CSI.getFrameIdx()); + unsigned Reg = CSI.getReg(); + MachineLocation CSDst(MachineLocation::VirtualFP, Offset); + MachineLocation CSSrc(Reg); + Moves.push_back(MachineMove(SpillLabel, CSDst, CSSrc)); + } + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/FrameLowering/hasFP.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/FrameLowering/hasFP.cpp new file mode 100644 index 0000000000000000000000000000000000000000..47a17358857419ec15b9dbb54fae1413c21313aa --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/FrameLowering/hasFP.cpp @@ -0,0 +1,3 @@ +bool XCoreFrameLowering::hasFP(const MachineFunction &MF) const { + return DisableFramePointerElim(MF) || MF.getFrameInfo()->hasVarSizedObjects(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/FrameLowering/isShrinkWrappingProfitable.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/FrameLowering/isShrinkWrappingProfitable.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9a9b7d5ea121e38506f149e2e37d592c5506391d --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/FrameLowering/isShrinkWrappingProfitable.cpp @@ -0,0 +1,3 @@ +bool XCoreFrameLowering::isShrinkWrappingProfitable() const { + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/FrameLowering/processFunctionBeforeCalleeSavedScan.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/FrameLowering/processFunctionBeforeCalleeSavedScan.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a5cf2ad8dfaa41c81f3eeb3f5278a10b82425a05 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/FrameLowering/processFunctionBeforeCalleeSavedScan.cpp @@ -0,0 +1,42 @@ +void XCoreFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, RegScavenger *RS) const { + MachineFrameInfo *MFI = MF.getFrameInfo(); + const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo(); + bool LRUsed = MF.getRegInfo().isPhysRegUsed(XCore::LR); + bool isVarArg = MF.getFunction()->isVarArg(); + const TargetRegisterClass *RC = XCore::GRRegsRegisterClass; + XCoreFunctionInfo *XFI = MF.getInfo(); + for (const unsigned *Reg = RegInfo->getCalleeSavedRegs(); *Reg; ++Reg) { + MF.front().addLiveIn(*Reg); + } + MachineFrameInfo *MFI = MF.getFrameInfo(); + const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo(); + if (MFI->getNumObjects() > 0) + return true; + for (const unsigned *Reg = RegInfo->getCalleeSavedRegs(); *Reg; ++Reg) { + if (MF.getRegInfo().isPhysRegUsed(*Reg)) + return true; + } + return false; + if (!LRUsed && !isVarArg && (MF)) { + LRUsed = true; + } + if (LRUsed) { + MF.getRegInfo().setPhysRegUnused(XCore::LR); + if (!XFI->hasLRSpillSlot()) { + int FrameIdx; + if (! isVarArg) { + FrameIdx = MFI->CreateFixedObject(RC->getSize(), 0, true); + } + else { + FrameIdx = MFI->CreateStackObject(RC->getSize(), RC->getAlignment(), false); + } + XFI->setLRSpillSlot(FrameIdx); + } + } + if (RegInfo->requiresRegisterScavenging(MF)) { + RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), RC->getAlignment(), false)); + } + if (hasFP(MF)) { + XFI->setFPSpillSlot(MFI->CreateStackObject(RC->getSize(), RC->getAlignment(), false)); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/FrameLowering/processFunctionBeforeFrameFinalized.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/FrameLowering/processFunctionBeforeFrameFinalized.cpp new file mode 100644 index 0000000000000000000000000000000000000000..dfe0caee410efc6371750eeb465adee3233778f9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/FrameLowering/processFunctionBeforeFrameFinalized.cpp @@ -0,0 +1,2 @@ +void XCoreFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF) const { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/FrameLowering/restoreCalleeSavedRegisters.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/FrameLowering/restoreCalleeSavedRegisters.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d3e3a0199671386e51a6daa14820ca81a8dd5880 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/FrameLowering/restoreCalleeSavedRegisters.cpp @@ -0,0 +1,21 @@ +bool XCoreFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector &CSI, const TargetRegisterInfo *TRI) const{ + MachineFunction *MF = MBB.getParent(); + const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo(); + bool AtStart = MI == MBB.begin(); + MachineBasicBlock::iterator BeforeI = MI; + if (!AtStart) + --BeforeI; + for (std::vector::const_iterator it = CSI.begin(); it != CSI.end(); ++it) { + unsigned Reg = it->getReg(); + const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); + TII.loadRegFromStackSlot(MBB, MI, it->getReg(), it->getFrameIdx(), RC, TRI); + assert(MI != MBB.begin() && "loadRegFromStackSlot didn't insert any code!"); + if (AtStart) + MI = MBB.begin(); + else { + MI = BeforeI; + ++MI; + } + } + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/FrameLowering/spillCalleeSavedRegisters.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/FrameLowering/spillCalleeSavedRegisters.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c87c83b04a838611a04a2f638ca93505ac69f7ba --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/FrameLowering/spillCalleeSavedRegisters.cpp @@ -0,0 +1,23 @@ +bool XCoreFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector &CSI, const TargetRegisterInfo *TRI) const { + if (CSI.empty()) + return true; + MachineFunction *MF = MBB.getParent(); + const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo(); + XCoreFunctionInfo *XFI = MF->getInfo(); + bool emitFrameMoves = XCoreRegisterInfo::needsFrameMoves(*MF); + DebugLoc DL; + if (MI != MBB.end()) + DL = MI->getDebugLoc(); + for (std::vector::const_iterator it = CSI.begin(); it != CSI.end(); ++it) { + MBB.addLiveIn(it->getReg()); + unsigned Reg = it->getReg(); + const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); + TII.storeRegToStackSlot(MBB, MI, Reg, true, it->getFrameIdx(), RC, TRI); + if (emitFrameMoves) { + MCSymbol *SaveLabel = MF->getContext().CreateTempSymbol(); + BuildMI(MBB, MI, DL, TII.get(XCore::PROLOG_LABEL)).addSym(SaveLabel); + XFI->getSpillLabels().push_back(std::make_pair(SaveLabel, *it)); + } + } + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/FrameLowering/stackSlotSize.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/FrameLowering/stackSlotSize.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4f3bde47d2e05bb35eefcf52c3a8542b631b6530 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/FrameLowering/stackSlotSize.cpp @@ -0,0 +1,3 @@ +static int stackSlotSize() { + return 4; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelDAGToDAG/DAGToDAGISel.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelDAGToDAG/DAGToDAGISel.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f6ff5c770b0c31f201ee41350319275f34ed8bbb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelDAGToDAG/DAGToDAGISel.cpp @@ -0,0 +1,2 @@ +XCoreDAGToDAGISel(XCoreTargetMachine &TM, CodeGenOpt::Level OptLevel) : SelectionDAGISel(TM, OptLevel), Lowering(*TM.getTargetLowering()), Subtarget(*TM.getSubtargetImpl()) { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelDAGToDAG/Select.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelDAGToDAG/Select.cpp new file mode 100644 index 0000000000000000000000000000000000000000..443ffb549b47d550e5cd1a2d79ef2f091eed8e96 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelDAGToDAG/Select.cpp @@ -0,0 +1,157 @@ +SDNode *XCoreDAGToDAGISel::Select(SDNode *N) { + DebugLoc dl = N->getDebugLoc(); + switch (N->getOpcode()) { + default: break; + case ISD::Constant: { + uint64_t Val = cast(N)->getZExtValue(); + if (immMskBitp(N)) { + SDValue MskSize = getI32Imm(32 - CountLeadingZeros_32(Val)); + return CurDAG->getMachineNode(XCore::MKMSK_rus, dl, MVT::i32, MskSize); + } + else if (!isUInt<16>(Val)) { + SDValue CPIdx = CurDAG->getTargetConstantPool(ConstantInt::get( Type::getInt32Ty(*CurDAG->getContext()), Val), TLI.getPointerTy()); + SDNode *node = CurDAG->getMachineNode(XCore::LDWCP_lru6, dl, MVT::i32, MVT::Other, CPIdx, getI32Imm(0), CurDAG->getEntryNode()); + MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1); + MemOp[0] = MF->getMachineMemOperand(MachinePointerInfo::getConstantPool(), MachineMemOperand::MOLoad, 4, 4); + cast(node)->setMemRefs(MemOp, MemOp + 1); + return node; + } + break; + } + case XCoreISD::OUTPW: { + if (immBitp(cast(N->getOperand(3)))){ + return SelectCode(N); + } else { + SDValue SetpscOps[] = { N->getOperand(1), N->getOperand(3), N->getOperand(0)}; + SDNode *setpsc = CurDAG->getMachineNode(XCore::SETPSC_l2r, dl, MVT::Other, SetpscOps,3); + SDValue Ops[] = { N->getOperand(1), N->getOperand(2) ,SDValue(setpsc, 0)}; + return CurDAG->getMachineNode(XCore::OUT_2r, dl, MVT::Other, Ops, 3); + } + } + case XCoreISD::INPW: { + if (immBitp(cast(N->getOperand(2)))){ + return SelectCode(N); + } + else { + SDValue SetpscOps[] = { N->getOperand(1), N->getOperand(2), N->getOperand(0)}; + SDNode *setpsc = CurDAG->getMachineNode(XCore::SETPSC_l2r, dl, MVT::Other, SetpscOps,3); + SDValue Ops[] = { N->getOperand(1),SDValue(setpsc, 0)}; + return CurDAG->getMachineNode( XCore::IN_2r, dl, MVT::i32,MVT::Other, Ops, 2); + } + } + case XCoreISD::LADD: { + SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2) }; + return CurDAG->getMachineNode(XCore::LADD_l5r, dl, MVT::i32, MVT::i32,Ops, 3); + } + case XCoreISD::LSUB: { + SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2) }; + return CurDAG->getMachineNode(XCore::LSUB_l5r, dl, MVT::i32, MVT::i32,Ops, 3); + } + case XCoreISD::MACCU: { + SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2), N->getOperand(3) }; + return CurDAG->getMachineNode(XCore::MACCU_l4r, dl, MVT::i32, MVT::i32,Ops, 4); + } + case XCoreISD::MACCS: { + SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2), N->getOperand(3) }; + return CurDAG->getMachineNode(XCore::MACCS_l4r, dl, MVT::i32, MVT::i32, Ops, 4); + } + case XCoreISD::LMUL: { + SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2), N->getOperand(3) }; + return CurDAG->getMachineNode(XCore::LMUL_l6r, dl, MVT::i32, MVT::i32,Ops, 4); + } + case ISD::INTRINSIC_WO_CHAIN: { + unsigned IntNo = cast(N->getOperand(0))->getZExtValue(); + switch (IntNo) { + case Intrinsic::xcore_crc8: + SDValue Ops[] = { N->getOperand(1), N->getOperand(2), N->getOperand(3) }; + return CurDAG->getMachineNode(XCore::CRC8_l4r, dl, MVT::i32, MVT::i32, Ops, 3); + } + break; + } + case ISD::INTRINSIC_VOID: { + unsigned IntNo = cast(N->getOperand(1))->getZExtValue(); + switch (IntNo) { + case Intrinsic::xcore_loopmarker: + MachineFunction &MF = CurDAG->getMachineFunction(); + XCoreFunctionInfo *XFI = MF.getInfo(); + MDNode * md = const_cast(cast(N->getOperand(3))->getMD()); + unsigned type = cast(N->getOperand(2))->getZExtValue(); + LoopLables.push_back(std::make_pair(md, type)); + unsigned index = LoopLables.size() -1; + return CurDAG->SelectNodeTo(N, XCore::LOOPMARKER, MVT::Other, CurDAG->getConstant(index, MVT::i32, true), N->getOperand(0)); + } + break; + } + case ISD::BRIND: + SDValue Chain = N->getOperand(0); + SDValue Addr = N->getOperand(1); + DebugLoc dl = Addr->getDebugLoc(); + if (Addr->getOpcode() != ISD::INTRINSIC_W_CHAIN) + return 0; + unsigned IntNo = cast(Addr->getOperand(1))->getZExtValue(); + if (IntNo != Intrinsic::xcore_waitevent && IntNo != Intrinsic::xcore_checkevent &&IntNo != Intrinsic::xcore_waitevent_nonlocal && IntNo != Intrinsic::xcore_checkevent_nonlocal) + return 0; + SDValue EventIntrinsicChainOut(Addr.getNode(), 1); + if (!EventIntrinsicChainOut.use_empty()) { + SDValue EventIntrinsicChainIn = Addr->getOperand(0); + SDValue NewChain = replaceInChain(CurDAG, Chain, EventIntrinsicChainOut, EventIntrinsicChainIn); + if (!NewChain.getNode()) + return 0; + Chain = NewChain; + } + switch (IntNo) { + default: llvm_unreachable("Unexpected intrinsic"); + case Intrinsic::xcore_checkevent:{ + SDValue nextAddr = Addr->getOperand(2); + SDValue constOne = getI32Imm(1); + SDValue Glue = SDValue(CurDAG->getMachineNode(XCore::SETSR_branch_u6, dl, MVT::Glue, constOne, Chain), 0); + Glue = SDValue(CurDAG->getMachineNode(XCore::CLRSR_branch_u6, dl, MVT::Glue, constOne, Glue), 0); + if (nextAddr->getOpcode() == XCoreISD::PCRelativeWrapper && nextAddr->getOperand(0)->getOpcode() == ISD::TargetBlockAddress) { + return CurDAG->SelectNodeTo(N, XCore::BRFU_lu6, MVT::Other, nextAddr->getOperand(0), Glue); + } + return CurDAG->SelectNodeTo(N, XCore::BAU_1r, MVT::Other, nextAddr, Glue); + } + case Intrinsic::xcore_waitevent: + return CurDAG->SelectNodeTo(N, XCore::WAITEU_0R, MVT::Other, Chain); + case Intrinsic::xcore_waitevent_nonlocal: { + SDValue nextAddr = Addr->getOperand(2); + SDValue Glue = SDValue(CurDAG->getMachineNode(XCore::WAITNONLOCAL, dl, MVT::Glue, Chain), 0); + if (nextAddr->getOpcode() == XCoreISD::PCRelativeWrapper && nextAddr->getOperand(0)->getOpcode() == ISD::TargetBlockAddress) { + return CurDAG->SelectNodeTo(N, XCore::BRFU_lu6, MVT::Other, nextAddr->getOperand(0), Glue); + } + return CurDAG->SelectNodeTo(N, XCore::BAU_1r, MVT::Other, nextAddr, Glue); + } + case Intrinsic::xcore_checkevent_nonlocal:{ + SDValue nextAddr = Addr->getOperand(3); + SDValue Glue =SDValue(CurDAG->getMachineNode(XCore::CHECKNONLOCAL, dl, MVT::Glue, Addr->getOperand(2),Chain), 0); + if (nextAddr->getOpcode() == XCoreISD::PCRelativeWrapper && nextAddr->getOperand(0)->getOpcode() == ISD::TargetBlockAddress) { + return CurDAG->SelectNodeTo(N, XCore::BRFU_lu6, MVT::Other, nextAddr->getOperand(0), Glue); + } + return CurDAG->SelectNodeTo(N, XCore::BAU_1r, MVT::Other, nextAddr, Glue); + } + } + if (SDNode *ResNode = (N)) + return ResNode; + break; + } + return SelectCode(N); + if (Chain == Old) + return New; + if (Chain->getOpcode() != ISD::TokenFactor) + return SDValue(); + SmallVector Ops; + bool found = false; + for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i) { + if (Chain->getOperand(i) == Old) { + Ops.push_back(New); + found = true; + } + else { + Ops.push_back(Chain->getOperand(i)); + } + } + if (!found) + return SDValue(); + return CurDAG->getNode(ISD::TokenFactor, Chain->getDebugLoc(), MVT::Other, &Ops[0], Ops.size()); +} + diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelDAGToDAG/SelectADDRcpii.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelDAGToDAG/SelectADDRcpii.cpp new file mode 100644 index 0000000000000000000000000000000000000000..068d7f348b53413eede51e03a8c239044a7bb0d8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelDAGToDAG/SelectADDRcpii.cpp @@ -0,0 +1,16 @@ +bool XCoreDAGToDAGISel::SelectADDRcpii(SDValue Addr, SDValue &Base, SDValue &Offset) { + if (Addr.getOpcode() == XCoreISD::CPRelativeWrapper) { + Base = Addr.getOperand(0); + Offset = CurDAG->getTargetConstant(0, MVT::i32); + return true; + } + if (Addr.getOpcode() == ISD::ADD) { + ConstantSDNode *CN = 0; + if ((Addr.getOperand(0).getOpcode() == XCoreISD::CPRelativeWrapper) && (CN = dyn_cast(Addr.getOperand(1)))&& (CN->getSExtValue() % 4 == 0 && CN->getSExtValue() >= 0)) { + Base = Addr.getOperand(0).getOperand(0); + Offset = CurDAG->getTargetConstant(CN->getSExtValue(), MVT::i32); + return true; + } + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelDAGToDAG/SelectADDRdpii.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelDAGToDAG/SelectADDRdpii.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0f379ac66e0cb5dfe3f1534e702cb84f5b948daf --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelDAGToDAG/SelectADDRdpii.cpp @@ -0,0 +1,16 @@ +bool XCoreDAGToDAGISel::SelectADDRdpii(SDValue Addr, SDValue &Base, SDValue &Offset) { + if (Addr.getOpcode() == XCoreISD::DPRelativeWrapper) { + Base = Addr.getOperand(0); + Offset = CurDAG->getTargetConstant(0, MVT::i32); + return true; + } + if (Addr.getOpcode() == ISD::ADD) { + ConstantSDNode *CN = 0; + if ((Addr.getOperand(0).getOpcode() == XCoreISD::DPRelativeWrapper) && (CN = dyn_cast(Addr.getOperand(1)))&& (CN->getSExtValue() % 4 == 0 && CN->getSExtValue() >= 0)) { + Base = Addr.getOperand(0).getOperand(0); + Offset = CurDAG->getTargetConstant(CN->getSExtValue(), MVT::i32); + return true; + } + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelDAGToDAG/SelectADDRspii.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelDAGToDAG/SelectADDRspii.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6d1a933df08c8ba9a84b25166e0c9fb8bbed7e8b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelDAGToDAG/SelectADDRspii.cpp @@ -0,0 +1,17 @@ +bool XCoreDAGToDAGISel::SelectADDRspii(SDValue Addr, SDValue &Base, SDValue &Offset) { + FrameIndexSDNode *FIN = 0; + if ((FIN = dyn_cast(Addr))) { + Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); + Offset = CurDAG->getTargetConstant(0, MVT::i32); + return true; + } + if (Addr.getOpcode() == ISD::ADD) { + ConstantSDNode *CN = 0; + if ((FIN = dyn_cast(Addr.getOperand(0))) && (CN = dyn_cast(Addr.getOperand(1))) && (CN->getSExtValue() % 4 == 0 && CN->getSExtValue() >= 0)) { + Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); + Offset = CurDAG->getTargetConstant(CN->getSExtValue(), MVT::i32); + return true; + } + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelDAGToDAG/SelectInlineAsmMemoryOperand.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelDAGToDAG/SelectInlineAsmMemoryOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..95ffddfad0c68d01fb31ed048024910704b6563a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelDAGToDAG/SelectInlineAsmMemoryOperand.cpp @@ -0,0 +1,20 @@ +bool XCoreDAGToDAGISel::SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode, std::vector &OutOps) { + SDValue Op0, Op1, Op2; + switch (ConstraintCode) { + default: return true; + case 'm': + if (SelectADDRcpii(Op, Op1, Op2)) { + Op0 = CurDAG->getRegister(XCore::CP, MVT::i32); + break; + } + if (SelectADDRdpii(Op, Op1, Op2)) { + Op0 = CurDAG->getRegister(XCore::DP, MVT::i32); + break; + } + return true; + } + OutOps.push_back(Op0); + OutOps.push_back(Op1); + OutOps.push_back(Op2); + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelDAGToDAG/createISelDag.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelDAGToDAG/createISelDag.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c65ba55db2256f60cad58168594502eb4f680143 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelDAGToDAG/createISelDag.cpp @@ -0,0 +1,3 @@ +FunctionPass *llvm::createXCoreISelDag(XCoreTargetMachine &TM, CodeGenOpt::Level OptLevel) { + return new XCoreDAGToDAGISel(TM, OptLevel); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelDAGToDAG/getI32Imm.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelDAGToDAG/getI32Imm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d51d5122efde046a2ef7c278e421815b53f354c4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelDAGToDAG/getI32Imm.cpp @@ -0,0 +1,3 @@ +inline SDValue getI32Imm(unsigned Imm) { + return CurDAG->getTargetConstant(Imm, MVT::i32); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelDAGToDAG/getPassName.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelDAGToDAG/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..dd6769f852d474c5692772fbd3af20bc99c1d272 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelDAGToDAG/getPassName.cpp @@ -0,0 +1,3 @@ +virtual const char *getPassName() const { + return "XCore DAG->DAG Pattern Instruction Selection"; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelDAGToDAG/immBitp.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelDAGToDAG/immBitp.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2c09a5aaf2f472f859db0ee4f22e263b4748a45e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelDAGToDAG/immBitp.cpp @@ -0,0 +1,7 @@ +inline bool immBitp(SDNode *inN) const { + if(!isa(inN)) + return false; + ConstantSDNode *N = cast(inN); + uint32_t value = (uint32_t)N->getZExtValue(); + return (value >= 1 && value <= 8) || value == 16 || value == 24 || value == 32; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelDAGToDAG/immMskBitp.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelDAGToDAG/immMskBitp.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c16460c084c2923709f756af85189e6dac857bf6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelDAGToDAG/immMskBitp.cpp @@ -0,0 +1,9 @@ +inline bool immMskBitp(SDNode *inN) const { + ConstantSDNode *N = cast(inN); + uint32_t value = (uint32_t)N->getZExtValue(); + if (!isMask_32(value)) { + return false; + } + int msksize = 32 - CountLeadingZeros_32(value); + return (msksize >= 1 && msksize <= 8) || msksize == 16 || msksize == 24 || msksize == 32; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/CanLowerReturn.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/CanLowerReturn.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b1dda74c086f58b6461e22c0e0a3e44393a8be19 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/CanLowerReturn.cpp @@ -0,0 +1,9 @@ +bool XCoreTargetLowering::CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl &Outs, LLVMContext &Context) const { + SmallVector RVLocs; + CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), RVLocs, Context); + if (!CCInfo.CheckReturn(Outs, RetCC_XCore)) + return false; + if (CCInfo.getNextStackOffset() != 0 && isVarArg) + return false; + return true; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/EmitInstrWithCustomInserter.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/EmitInstrWithCustomInserter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5c0760cc729bff93dab4b46948dd409962a5f4db --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/EmitInstrWithCustomInserter.cpp @@ -0,0 +1,25 @@ +MachineBasicBlock *XCoreTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *BB) const { + const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo(); + DebugLoc dl = MI->getDebugLoc(); + assert((MI->getOpcode() == XCore::SELECT_CC) && "Unexpected instr type to insert"); + const BasicBlock *LLVM_BB = BB->getBasicBlock(); + MachineFunction::iterator It = BB; + ++It; + MachineBasicBlock *thisMBB = BB; + MachineFunction *F = BB->getParent(); + MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); + MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); + F->insert(It, copy0MBB); + F->insert(It, sinkMBB); + sinkMBB->splice(sinkMBB->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); + sinkMBB->transferSuccessorsAndUpdatePHIs(BB); + BB->addSuccessor(copy0MBB); + BB->addSuccessor(sinkMBB); + BuildMI(BB, dl, TII.get(XCore::BRFT_lru6)).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); + BB = copy0MBB; + BB->addSuccessor(sinkMBB); + BB = sinkMBB; + BuildMI(*BB, BB->begin(), dl, TII.get(XCore::PHI), MI->getOperand(0).getReg()).addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB).addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); + MI->eraseFromParent(); + return BB; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/ExpandADDSUB.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/ExpandADDSUB.cpp new file mode 100644 index 0000000000000000000000000000000000000000..df98267ee2b1601286e61658a9d08cea579f3669 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/ExpandADDSUB.cpp @@ -0,0 +1,62 @@ +SDValue XCoreTargetLowering::ExpandADDSUB(SDNode *N, SelectionDAG &DAG) const { + assert(N->getValueType(0) == MVT::i64 && (N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && "Unknown operand to lower!"); + if (N->getOpcode() == ISD::ADD) { + SDValue XCoreTargetLowering:: + SDValue Mul; + SDValue Other; + if (N->getOperand(0).getOpcode() == ISD::MUL) { + Mul = N->getOperand(0); + Other = N->getOperand(1); + } + else if (N->getOperand(1).getOpcode() == ISD::MUL) { + Mul = N->getOperand(1); + Other = N->getOperand(0); + } + else { + return SDValue(); + } + DebugLoc dl = N->getDebugLoc(); + SDValue LL, RL, AddendL, AddendH; + LL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Mul.getOperand(0), DAG.getConstant(0, MVT::i32)); + RL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Mul.getOperand(1), DAG.getConstant(0, MVT::i32)); + AddendL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Other, DAG.getConstant(0, MVT::i32)); + AddendH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Other, DAG.getConstant(1, MVT::i32)); + APInt HighMask = APInt::getHighBitsSet(64, 32); + unsigned LHSSB = DAG.ComputeNumSignBits(Mul.getOperand(0)); + unsigned RHSSB = DAG.ComputeNumSignBits(Mul.getOperand(1)); + if (DAG.MaskedValueIsZero(Mul.getOperand(0), HighMask) && DAG.MaskedValueIsZero(Mul.getOperand(1), HighMask)) { + SDValue Hi = DAG.getNode(XCoreISD::MACCU, dl, DAG.getVTList(MVT::i32, MVT::i32), AddendH, AddendL, LL, RL); + SDValue Lo(Hi.getNode(), 1); + return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); + } + if (LHSSB > 32 && RHSSB > 32) { + SDValue Hi = DAG.getNode(XCoreISD::MACCS, dl, DAG.getVTList(MVT::i32, MVT::i32), AddendH, AddendL, LL, RL); + SDValue Lo(Hi.getNode(), 1); + return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); + } + SDValue LH, RH; + LH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Mul.getOperand(0), DAG.getConstant(1, MVT::i32)); + RH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Mul.getOperand(1), DAG.getConstant(1, MVT::i32)); + SDValue Hi = DAG.getNode(XCoreISD::MACCU, dl, DAG.getVTList(MVT::i32, MVT::i32), AddendH, AddendL, LL, RL); + SDValue Lo(Hi.getNode(), 1); + RH = DAG.getNode(ISD::MUL, dl, MVT::i32, LL, RH); + LH = DAG.getNode(ISD::MUL, dl, MVT::i32, LH, RL); + Hi = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, RH); + Hi = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, LH); + SDValue Result = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); + if (Result.getNode() != 0) + return Result; + } + DebugLoc dl = N->getDebugLoc(); + SDValue LHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0), DAG.getConstant(0, MVT::i32)); + SDValue LHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0), DAG.getConstant(1, MVT::i32)); + SDValue RHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(1), DAG.getConstant(0, MVT::i32)); + SDValue RHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(1), DAG.getConstant(1, MVT::i32)); + unsigned Opcode = (N->getOpcode() == ISD::ADD) ? XCoreISD::LADD : CoreISD::LSUB; + SDValue Zero = DAG.getConstant(0, MVT::i32); + SDValue Carry = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32), LHSL, RHSL, Zero); + SDValue Lo(Carry.getNode(), 1); + SDValue Ignored = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32), LHSH, RHSH, Carry); + SDValue Hi(Ignored.getNode(), 1); + return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerADJUST_TRAMPOLINE.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerADJUST_TRAMPOLINE.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a7e79660297ec1580149891154481ad37f082fad --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerADJUST_TRAMPOLINE.cpp @@ -0,0 +1,3 @@ +SDValue XCoreTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const { + return Op.getOperand(0); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerATOMIC_FENCE.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerATOMIC_FENCE.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1ab9cb7cbe15bc311704c1991792b303f0009b70 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerATOMIC_FENCE.cpp @@ -0,0 +1,4 @@ +SDValue XCoreTargetLowering::LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const { + DebugLoc dl = Op.getDebugLoc(); + return DAG.getNode(XCoreISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0)); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerBR_JT.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerBR_JT.cpp new file mode 100644 index 0000000000000000000000000000000000000000..419da941fe5671f6c51816d5e22bc07eec63f64a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerBR_JT.cpp @@ -0,0 +1,18 @@ +SDValue XCoreTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const { + SDValue Chain = Op.getOperand(0); + SDValue Table = Op.getOperand(1); + SDValue Index = Op.getOperand(2); + DebugLoc dl = Op.getDebugLoc(); + JumpTableSDNode *JT = cast(Table); + unsigned JTI = JT->getIndex(); + MachineFunction &MF = DAG.getMachineFunction(); + const MachineJumpTableInfo *MJTI = MF.getJumpTableInfo(); + SDValue TargetJT = DAG.getTargetJumpTable(JT->getIndex(), MVT::i32); + unsigned NumEntries = MJTI->getJumpTables()[JTI].MBBs.size(); + if (NumEntries <= 32) { + return DAG.getNode(XCoreISD::BR_JT, dl, MVT::Other, Chain, TargetJT, Index); + } + assert((NumEntries >> 31) == 0); + SDValue ScaledIndex = DAG.getNode(ISD::SHL, dl, MVT::i32, Index, DAG.getConstant(1, MVT::i32)); + return DAG.getNode(XCoreISD::BR_JT32, dl, MVT::Other, Chain, TargetJT, ScaledIndex); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerBlockAddress.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerBlockAddress.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5716b4d9cfe759024a0653bcd24d6fb37c222d98 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerBlockAddress.cpp @@ -0,0 +1,6 @@ +SDValue XCoreTargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const { + DebugLoc DL = Op.getDebugLoc(); + const BlockAddress *BA = cast(Op)->getBlockAddress(); + SDValue Result = DAG.getBlockAddress(BA, getPointerTy(), true); + return DAG.getNode(XCoreISD::PCRelativeWrapper, DL, getPointerTy(), Result); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerCall.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerCall.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a3aae8354c3b215d96516552270e082531cf3a15 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerCall.cpp @@ -0,0 +1,148 @@ +SDValue XCoreTargetLowering::LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl &Outs, const SmallVectorImpl &OutVals, const SmallVectorImpl &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl &InVals) const { + isTailCall = false; + switch (CallConv) { + default: + llvm_unreachable("Unsupported calling convention"); + case CallingConv::Fast: + case CallingConv::C: + MachineFunction &MF = DAG.getMachineFunction(); + XCoreFunctionInfo *XFI = MF.getInfo(); + if (GlobalAddressSDNode *G = dyn_cast(Callee)) { + const GlobalValue *GV = G->getGlobal(); + if (const GlobalAlias *GA = dyn_cast(GV)) { + GV = GA->resolveAliasedGlobal(); + } + if (const Function *F = dyn_cast(G->getGlobal())) { + XFI->addCall(F); + } + else { + XFI->setHasIndirectCalls(true); + } + } + else if (ExternalSymbolSDNode *E = dyn_cast(Callee)) { + XFI->addCall(E->getSymbol()); + } + else { + XFI->setHasIndirectCalls(true); + } + SmallVector ArgLocs; + CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), getTargetMachine(), ArgLocs, *DAG.getContext()); + CCInfo.AllocateStack(4, 4); + CCInfo.AnalyzeCallOperands(Outs, CC_XCore); + SmallVector RVLocs; + CCState RetCCInfo(CallConv, isVarArg, DAG.getMachineFunction(), getTargetMachine(), RVLocs, *DAG.getContext()); + RetCCInfo.AllocateStack(CCInfo.getNextStackOffset(), 4); + RetCCInfo.AnalyzeCallResult(Ins, RetCC_XCore); + bool hasResultReturnedOnStack = RetCCInfo.getNextStackOffset() != CCInfo.getNextStackOffset(); + unsigned NumBytes = RetCCInfo.getNextStackOffset(); + Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy(), true)); + SmallVector, 4> RegsToPass; + SmallVector MemOpChains; + for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { + CCValAssign &VA = ArgLocs[i]; + SDValue Arg = OutVals[i]; + switch (VA.getLocInfo()) { + default: llvm_unreachable("Unknown loc info!"); + case CCValAssign::Full: + break; + case CCValAssign::SExt: + Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); + break; + case CCValAssign::ZExt: + Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); + break; + case CCValAssign::AExt: + Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); + break; + } + if (VA.isRegLoc()) { + RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); + } + else { + assert(VA.isMemLoc()); + int Offset = VA.getLocMemOffset(); + MemOpChains.push_back(DAG.getNode(XCoreISD::STWSP, dl, MVT::Other, Chain, Arg, DAG.getConstant(Offset/4, MVT::i32))); + } + } + if (!MemOpChains.empty()) + Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOpChains[0], MemOpChains.size()); + SDValue InFlag; + for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { + Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, RegsToPass[i].second, InFlag); + InFlag = Chain.getValue(1); + } + if (GlobalAddressSDNode *G = dyn_cast(Callee)) + Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32); + else if (ExternalSymbolSDNode *E = dyn_cast(Callee)) + Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32); + SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); + SmallVector Ops; + Ops.push_back(Chain); + Ops.push_back(Callee); + for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) + Ops.push_back(DAG.getRegister(RegsToPass[i].first, RegsToPass[i].second.getValueType())); + if (InFlag.getNode()) + Ops.push_back(InFlag); + Chain = DAG.getNode(XCoreISD::BL, dl, NodeTys, &Ops[0], Ops.size()); + InFlag = Chain.getValue(1); + if (hasResultReturnedOnStack) { + SmallVector, 4> ResultMemLocs; + for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { + const CCValAssign &VA = RVLocs[i]; + if (VA.isRegLoc()) { + Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getValVT(), InFlag).getValue(1); + InFlag = Chain.getValue(2); + InVals.push_back(Chain.getValue(0)); + } + else { + assert(VA.isMemLoc()); + ResultMemLocs.push_back(std::make_pair(VA.getLocMemOffset(), InVals.size())); + InVals.push_back(SDValue()); + } + } + SmallVector MemOpChains; + for (unsigned i = 0, e = ResultMemLocs.size(); i != e; ++i) { + int offset = ResultMemLocs[i].first; + unsigned index = ResultMemLocs[i].second; + SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other); + SDValue Ops[] = { Chain, DAG.getConstant(offset/4, MVT::i32) }; + SDValue load = DAG.getNode(XCoreISD::LDWSP, dl, VTs, Ops, 2); + InVals[index] = load; + MemOpChains.push_back(load.getValue(1)); + } + if (!MemOpChains.empty()) + Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOpChains[0], MemOpChains.size()); + Chain = DAG.getCALLSEQ_END(Chain, DAG.getConstant(NumBytes, getPointerTy(), true), DAG.getConstant(0, getPointerTy(), true), SDValue()); + } + else { + Chain = DAG.getCALLSEQ_END(Chain, DAG.getConstant(NumBytes, getPointerTy(), true), DAG.getConstant(0, getPointerTy(), true), InFlag); + SmallVector, 4> ResultMemLocs; + for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { + const CCValAssign &VA = RVLocs[i]; + if (VA.isRegLoc()) { + Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getValVT(), InFlag).getValue(1); + InFlag = Chain.getValue(2); + InVals.push_back(Chain.getValue(0)); + } + else { + assert(VA.isMemLoc()); + ResultMemLocs.push_back(std::make_pair(VA.getLocMemOffset(), InVals.size())); + InVals.push_back(SDValue()); + } + } + SmallVector MemOpChains; + for (unsigned i = 0, e = ResultMemLocs.size(); i != e; ++i) { + int offset = ResultMemLocs[i].first; + unsigned index = ResultMemLocs[i].second; + SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other); + SDValue Ops[] = { Chain, DAG.getConstant(offset/4, MVT::i32) }; + SDValue load = DAG.getNode(XCoreISD::LDWSP, dl, VTs, Ops, 2); + InVals[index] = load; + MemOpChains.push_back(load.getValue(1)); + } + if (!MemOpChains.empty()) + Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOpChains[0], MemOpChains.size()); + } + return Chain; + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerConstantPool.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerConstantPool.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bf61dd0ba9834cd0452cfb166ff86416201f40ec --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerConstantPool.cpp @@ -0,0 +1,13 @@ +SDValue XCoreTargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const { + ConstantPoolSDNode *CP = cast(Op); + DebugLoc dl = CP->getDebugLoc(); + EVT PtrVT = Op.getValueType(); + SDValue Res; + if (CP->isMachineConstantPoolEntry()) { + Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT, CP->getAlignment()); + } + else { + Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment()); + } + return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, Res); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerDYNAMIC_STACKALLOC.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerDYNAMIC_STACKALLOC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..88d5d526203df641000d44edb3d15bcf4bb6a554 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerDYNAMIC_STACKALLOC.cpp @@ -0,0 +1,28 @@ +SDValue XCoreTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const { + SDNode *Node = Op.getNode(); + unsigned SPReg = this->getStackPointerRegisterToSaveRestore(); + assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and not tell us which reg is the stack pointer!"); + DebugLoc dl = Node->getDebugLoc(); + EVT VT = Node->getValueType(0); + SDValue Tmp1 = SDValue(Node, 0); + SDValue Tmp2 = SDValue(Node, 1); + SDValue Tmp3 = Node->getOperand(2); + SDValue Chain = Tmp1.getOperand(0); + MachineFunction &MF = DAG.getMachineFunction(); + XCoreFunctionInfo *XFI = MF.getInfo(); + Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true)); + SDValue Size = Tmp2.getOperand(1); + SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT); + Chain = SP.getValue(1); + unsigned Align = cast(Tmp3)->getZExtValue(); + unsigned StackAlign = TM.getFrameLowering()->getStackAlignment(); + if (Align > StackAlign) + SP = DAG.getNode(ISD::AND, dl, VT, SP, DAG.getConstant(-(uint64_t)Align, VT)); + Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); + Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); + unsigned i = XFI->addStackExpression(Size); + Chain = DAG.getNode(XCoreISD::ALLOCA, dl, MVT::Other, Chain, DAG.getConstant(i, MVT::i32)); + Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true), DAG.getIntPtrConstant(0, true), SDValue()); + SDValue Ops[] = { Tmp1, Tmp2 }; + return DAG.getMergeValues(Ops, 2, dl); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerEH_RETURN.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerEH_RETURN.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0e056b7d246b21d3d053dc7909620ab8d9fe15c9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerEH_RETURN.cpp @@ -0,0 +1,22 @@ +SDValue XCoreTargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const { + MachineFunction &MF = DAG.getMachineFunction(); + SDValue Chain = Op.getOperand(0); + SDValue Offset = Op.getOperand(1); + SDValue Handler = Op.getOperand(2); + DebugLoc dl = Op.getDebugLoc(); + const TargetRegisterInfo *RegInfo = getTargetMachine().getRegisterInfo(); + SDValue Stack = DAG.getCopyFromReg(DAG.getEntryNode(), dl, RegInfo->getFrameRegister(MF), MVT::i32); + SDValue FrameToArgs = DAG.getNode(XCoreISD::FRAME_TO_ARGS_OFFSET, dl, MVT::i32); + Stack = DAG.getNode(ISD::ADD, dl, MVT::i32, Stack, FrameToArgs); + Stack = DAG.getNode(ISD::ADD, dl, MVT::i32, Stack, Offset); + unsigned StackReg = XCore::R2; + unsigned HandlerReg = XCore::R3; + SDValue OutChains[] = { + DAG.getCopyToReg(Chain, dl, StackReg, Stack), + DAG.getCopyToReg(Chain, dl, HandlerReg, Handler) + }; + Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 2); + MF.getRegInfo().addLiveOut(StackReg); + MF.getRegInfo().addLiveOut(HandlerReg); + return DAG.getNode(XCoreISD::EH_RETURN, dl, MVT::Other, Chain, DAG.getRegister(StackReg, MVT::i32), DAG.getRegister(HandlerReg, MVT::i32)); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerFRAMEADDR.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerFRAMEADDR.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1fbbfdc8c5a0562bcd31c791e6600d70b4d0659e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerFRAMEADDR.cpp @@ -0,0 +1,8 @@ +SDValue XCoreTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { + DebugLoc dl = Op.getDebugLoc(); + if (cast(Op.getOperand(0))->getZExtValue() > 0) + return SDValue(); + MachineFunction &MF = DAG.getMachineFunction(); + const TargetRegisterInfo *RegInfo = getTargetMachine().getRegisterInfo(); + return DAG.getCopyFromReg(DAG.getEntryNode(), dl, RegInfo->getFrameRegister(MF), MVT::i32); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerFRAME_TO_ARGS_OFFSET.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerFRAME_TO_ARGS_OFFSET.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3f27c2ffe8407edfe6c97e4a3d599d600c3ddfdb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerFRAME_TO_ARGS_OFFSET.cpp @@ -0,0 +1,4 @@ +SDValue XCoreTargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const { + DebugLoc dl = Op.getDebugLoc(); + return DAG.getNode(XCoreISD::FRAME_TO_ARGS_OFFSET, dl, MVT::i32); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerFormalArguments.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerFormalArguments.cpp new file mode 100644 index 0000000000000000000000000000000000000000..14fb9c0ef10f4873f3c2e7fda713893d01756ecb --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerFormalArguments.cpp @@ -0,0 +1,77 @@ +SDValue XCoreTargetLowering::LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl &InVals) const { + switch (CallConv) { + default: + llvm_unreachable("Unsupported calling convention"); + case CallingConv::C: + case CallingConv::Fast: + MachineFunction &MF = DAG.getMachineFunction(); + MachineFrameInfo *MFI = MF.getFrameInfo(); + MachineRegisterInfo &RegInfo = MF.getRegInfo(); + XCoreFunctionInfo *XFI = MF.getInfo(); + SmallVector ArgLocs; + CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), getTargetMachine(), ArgLocs, *DAG.getContext()); + CCInfo.AnalyzeFormalArguments(Ins, CC_XCore); + unsigned StackSlotSize = XCoreFrameLowering::stackSlotSize(); + unsigned LRSaveSize = StackSlotSize; + if (!isVarArg) + XFI->setReturnStackOffset(CCInfo.getNextStackOffset() + LRSaveSize); + for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { + CCValAssign &VA = ArgLocs[i]; + if (VA.isRegLoc()) { + EVT RegVT = VA.getLocVT(); + switch (RegVT.getSimpleVT().SimpleTy) { + default: { +#ifndef NDEBUG + errs() << "LowerFormalArguments Unhandled argument type: " << RegVT.getSimpleVT().SimpleTy << "\n"; +#endif + llvm_unreachable(0); + } + case MVT::i32: + unsigned VReg = RegInfo.createVirtualRegister( XCore::GRRegsRegisterClass); + RegInfo.addLiveIn(VA.getLocReg(), VReg); + InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); + } + } + else { + assert(VA.isMemLoc()); + unsigned ObjSize = VA.getLocVT().getSizeInBits()/8; + if (ObjSize > StackSlotSize) { + errs() << "LowerFormalArguments Unhandled argument type: " << EVT(VA.getLocVT()).getEVTString() << "\n"; + } + int FI = MFI->CreateFixedObject(ObjSize, LRSaveSize + VA.getLocMemOffset(), true); + SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); + InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN, MachinePointerInfo::getFixedStack(FI), false, false, 0)); + } + } + if (isVarArg) { + static const unsigned ArgRegs[] = { + XCore::R0, XCore::R1, XCore::R2, XCore::R3 + }; + XCoreFunctionInfo *XFI = MF.getInfo(); + unsigned FirstVAReg = CCInfo.getFirstUnallocated(ArgRegs, array_lengthof(ArgRegs)); + if (FirstVAReg < array_lengthof(ArgRegs)) { + SmallVector MemOps; + int offset = 0; + for (int i = array_lengthof(ArgRegs) - 1; i >= (int)FirstVAReg; --i) { + int FI = MFI->CreateFixedObject(4, offset, true); + if (i == (int)FirstVAReg) { + XFI->setVarArgsFrameIndex(FI); + } + offset -= StackSlotSize; + SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); + unsigned VReg = RegInfo.createVirtualRegister( XCore::GRRegsRegisterClass); + RegInfo.addLiveIn(ArgRegs[i], VReg); + SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); + SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, MachinePointerInfo(), false, false, 0); + MemOps.push_back(Store); + } + if (!MemOps.empty()) + Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOps[0], MemOps.size()); + } + else { + XFI->setVarArgsFrameIndex(MFI->CreateFixedObject(4, LRSaveSize + CCInfo.getNextStackOffset(), true)); + } + } + return Chain; + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerGlobalAddress.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerGlobalAddress.cpp new file mode 100644 index 0000000000000000000000000000000000000000..96d04e6abbdaf6ce41befc01d4314cbadadebaac --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerGlobalAddress.cpp @@ -0,0 +1,15 @@ +SDValue XCoreTargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const { + const GlobalValue *GV = cast(Op)->getGlobal(); + SDValue GA = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(), MVT::i32); + DebugLoc dl = GA.getDebugLoc(); + const GlobalValue *UnderlyingGV = GV; + if (const GlobalAlias *GA = dyn_cast(GV)) + UnderlyingGV = GA->resolveAliasedGlobal(); + if (const GlobalVariable *GVar = dyn_cast(UnderlyingGV)) { + if (GVar->hasSection() && GVar->getSection().substr(0, 4) == ".cp.") { + return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, GA); + } + return DAG.getNode(XCoreISD::DPRelativeWrapper, dl, MVT::i32, GA); + } + return DAG.getNode(XCoreISD::PCRelativeWrapper, dl, MVT::i32, GA); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerGlobalTLSAddress.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerGlobalTLSAddress.cpp new file mode 100644 index 0000000000000000000000000000000000000000..09a51374af890f0e24e0c4684abb2b8288148119 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerGlobalTLSAddress.cpp @@ -0,0 +1,37 @@ +SDValue XCoreTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { + DebugLoc dl = Op.getDebugLoc(); + const GlobalValue *GV = cast(Op)->getGlobal(); + SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32); + const GlobalVariable *GVar = dyn_cast(GV); + if (!GVar) { + if (const GlobalAlias *GA = dyn_cast(GV)) + GVar = dyn_cast_or_null(GA->resolveAliasedGlobal()); + } + if (! GVar) { + llvm_unreachable("Thread local object not a GlobalVariable?"); + return SDValue(); + } + Type *Ty = cast(GV->getType())->getElementType(); + if (!Ty->isSized() || isZeroLengthArray(Ty)) { +#ifndef NDEBUG + errs() << "Size of thread local object " << GVar->getName() << " is unknown\n"; +#endif + llvm_unreachable(0); + } + SDValue base; + DebugLoc dl = GA.getDebugLoc(); + const GlobalValue *UnderlyingGV = GV; + if (const GlobalAlias *GA = dyn_cast(GV)) + UnderlyingGV = GA->resolveAliasedGlobal(); + if (const GlobalVariable *GVar = dyn_cast(UnderlyingGV)) { + if (GVar->hasSection() && GVar->getSection().substr(0, 4) == ".cp.") { + base = DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, GA); + } + base = DAG.getNode(XCoreISD::DPRelativeWrapper, dl, MVT::i32, GA); + } + base = DAG.getNode(XCoreISD::PCRelativeWrapper, dl, MVT::i32, GA); + const TargetData *TD = TM.getTargetData(); + unsigned Size = TD->getTypeAllocSize(Ty); + SDValue offset = DAG.getNode(ISD::MUL, dl, MVT::i32, BuildGetId(DAG, dl), DAG.getConstant(Size, MVT::i32)); + return DAG.getNode(ISD::ADD, dl, MVT::i32, base, offset); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerINIT_TRAMPOLINE.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerINIT_TRAMPOLINE.cpp new file mode 100644 index 0000000000000000000000000000000000000000..41459cb37370bb1f4e7cf71cda6a50fdbe2d9d98 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerINIT_TRAMPOLINE.cpp @@ -0,0 +1,20 @@ +SDValue XCoreTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const { + SDValue Chain = Op.getOperand(0); + SDValue Trmp = Op.getOperand(1); + SDValue FPtr = Op.getOperand(2); + SDValue Nest = Op.getOperand(3); + const Value *TrmpAddr = cast(Op.getOperand(4))->getValue(); + SDValue OutChains[5]; + SDValue Addr = Trmp; + DebugLoc dl = Op.getDebugLoc(); + OutChains[0] = DAG.getStore(Chain, dl, DAG.getConstant(0x0a3cd805, MVT::i32), Addr, MachinePointerInfo(TrmpAddr), false, false, 0); + Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, DAG.getConstant(4, MVT::i32)); + OutChains[1] = DAG.getStore(Chain, dl, DAG.getConstant(0xd80456c0, MVT::i32), Addr, MachinePointerInfo(TrmpAddr, 4), false, false, 0); + Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, DAG.getConstant(8, MVT::i32)); + OutChains[2] = DAG.getStore(Chain, dl, DAG.getConstant(0x27fb0a3c, MVT::i32), Addr, MachinePointerInfo(TrmpAddr, 8), false, false, 0); + Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, DAG.getConstant(12, MVT::i32)); + OutChains[3] = DAG.getStore(Chain, dl, Nest, Addr, MachinePointerInfo(TrmpAddr, 12), false, false, 0); + Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, DAG.getConstant(16, MVT::i32)); + OutChains[4] = DAG.getStore(Chain, dl, FPtr, Addr, MachinePointerInfo(TrmpAddr, 16), false, false, 0); + return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 5); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerINTRINSIC_WO_CHAIN.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerINTRINSIC_WO_CHAIN.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ba5dc4e6f98d9d1265d70a9cbb37cb69d30f648f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerINTRINSIC_WO_CHAIN.cpp @@ -0,0 +1,44 @@ +SDValue XCoreTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const { + DebugLoc dl = Op.getDebugLoc(); + unsigned IntNo = cast(Op.getOperand(0))->getZExtValue(); + switch (IntNo) { + case Intrinsic::xcore_stackusage: + case Intrinsic::xcore_arraybound: + case Intrinsic::xcore_savedstateusage: { + if (Op.getOperand(1)->getOpcode() != XCoreISD::PCRelativeWrapper && Op.getOperand(1)->getOpcode() != XCoreISD::DPRelativeWrapper && Op.getOperand(1)->getOpcode() != XCoreISD::CPRelativeWrapper) + break; + GlobalAddressSDNode *G = dyn_cast(Op.getOperand(1).getOperand(0)); + if (!G) + break; + const GlobalValue *GV = G->getGlobal(); + if (const GlobalAlias *GA = dyn_cast(GV)) { + GV = GA->resolveAliasedGlobal(); + } + MachineFunction &MF = DAG.getMachineFunction(); + XCoreFunctionInfo *XFI = MF.getInfo(); + const char *SymName = XFI->getResourceSymbolName(GV, getResourceSymbolSuffix(IntNo)); + SDValue StackUsageSym = DAG.getTargetExternalSymbol(SymName, MVT::i32); + return DAG.getNode(XCoreISD::ABS16Wrapper, dl, MVT::i32, StackUsageSym); + } + case Intrinsic::xcore_maxargsize: { + if (Op.getOperand(1)->getOpcode() != XCoreISD::PCRelativeWrapper && Op.getOperand(1)->getOpcode() != XCoreISD::DPRelativeWrapper && Op.getOperand(1)->getOpcode() != XCoreISD::CPRelativeWrapper) + break; + GlobalAddressSDNode *G = dyn_cast(Op.getOperand(1).getOperand(0)); + unsigned paramArgNum = 2; + ConstantSDNode *C = dyn_cast(Op.getOperand(paramArgNum)); + if (!G || !C) + break; + const GlobalValue *GV = G->getGlobal(); + unsigned paramNum = C->getZExtValue(); + if (const GlobalAlias *GA = dyn_cast(GV)) { + GV = GA->resolveAliasedGlobal(); + } + MachineFunction &MF = DAG.getMachineFunction(); + XCoreFunctionInfo *XFI = MF.getInfo(); + const char *SymName = XFI->getMaxArgName(GV, paramNum); + SDValue StackUsageSym = DAG.getTargetExternalSymbol(SymName, MVT::i32); + return DAG.getNode(XCoreISD::ABS16Wrapper, dl, MVT::i32, StackUsageSym); + } + } + return SDValue(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerLOAD.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerLOAD.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6b31ae7f9a13ec3005d81188dc3e1b8526810d29 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerLOAD.cpp @@ -0,0 +1,53 @@ +SDValue XCoreTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const { + LoadSDNode *LD = cast(Op); + assert(LD->getExtensionType() == ISD::NON_EXTLOAD && "Unexpected extension type"); + assert(LD->getMemoryVT() == MVT::i32 && "Unexpected load EVT"); + if (allowsUnalignedMemoryAccesses(LD->getMemoryVT())) + return SDValue(); + unsigned ABIAlignment = getTargetData()-> getABITypeAlignment(LD->getMemoryVT().getTypeForEVT(*DAG.getContext())); + if (LD->getAlignment() >= ABIAlignment) + return SDValue(); + SDValue Chain = LD->getChain(); + SDValue BasePtr = LD->getBasePtr(); + DebugLoc DL = Op.getDebugLoc(); + SDValue Base; + int64_t Offset; + if (!LD->isVolatile() && IsWordAlignedBasePlusConstantOffset(BasePtr, Base, Offset)) { + if (Offset % 4 == 0) { + return DAG.getLoad(getPointerTy(), DL, Chain, BasePtr, MachinePointerInfo(), false, false, 0); + } + SDValue LowOffset = DAG.getConstant(Offset & ~0x3, MVT::i32); + SDValue HighOffset = DAG.getConstant((Offset & ~0x3) + 4, MVT::i32); + SDValue LowShift = DAG.getConstant((Offset & 0x3) * 8, MVT::i32); + SDValue HighShift = DAG.getConstant(32 - (Offset & 0x3) * 8, MVT::i32); + SDValue LowAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, Base, LowOffset); + SDValue HighAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, Base, HighOffset); + SDValue Low = DAG.getLoad(getPointerTy(), DL, Chain, LowAddr, MachinePointerInfo(), false, false, 0); + SDValue High = DAG.getLoad(getPointerTy(), DL, Chain, HighAddr, MachinePointerInfo(), false, false, 0); + SDValue LowShifted = DAG.getNode(ISD::SRL, DL, MVT::i32, Low, LowShift); + SDValue HighShifted = DAG.getNode(ISD::SHL, DL, MVT::i32, High, HighShift); + SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, LowShifted, HighShifted); + Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Low.getValue(1), High.getValue(1)); + SDValue Ops[] = { Result, Chain }; + return DAG.getMergeValues(Ops, 2, DL); + } + if (LD->getAlignment() == 2) { + SDValue Low = DAG.getExtLoad(ISD::ZEXTLOAD, DL, MVT::i32, Chain, BasePtr, LD->getPointerInfo(), MVT::i16, LD->isVolatile(), LD->isNonTemporal(), 2); + SDValue HighAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, DAG.getConstant(2, MVT::i32)); + SDValue High = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain, HighAddr, LD->getPointerInfo().getWithOffset(2), MVT::i16, LD->isVolatile(), LD->isNonTemporal(), 2); + SDValue HighShifted = DAG.getNode(ISD::SHL, DL, MVT::i32, High, DAG.getConstant(16, MVT::i32)); + SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Low, HighShifted); + Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Low.getValue(1), High.getValue(1)); + SDValue Ops[] = { Result, Chain }; + return DAG.getMergeValues(Ops, 2, DL); + } + Type *IntPtrTy = getTargetData()->getIntPtrType(*DAG.getContext()); + TargetLowering::ArgListTy Args; + TargetLowering::ArgListEntry Entry; + Entry.Ty = IntPtrTy; + Entry.Node = BasePtr; + Args.push_back(Entry); + std::pair CallResult = LowerCallTo(Chain, IntPtrTy, false, false, false, false, 0, CallingConv::C, false, true, DAG.getExternalSymbol("__misaligned_load", getPointerTy()), Args, DAG, DL); + SDValue Ops[] = { CallResult.first, CallResult.second }; + return DAG.getMergeValues(Ops, 2, DL); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerOperation.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerOperation.cpp new file mode 100644 index 0000000000000000000000000000000000000000..947877d5d9846378db8161b32060e689837682d8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerOperation.cpp @@ -0,0 +1,56 @@ +SDValue XCoreTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { + switch (Op.getOpcode()) { + case ISD::EH_RETURN: + return LowerEH_RETURN(Op, DAG); + case ISD::GlobalAddress: + return LowerGlobalAddress(Op, DAG); + case ISD::GlobalTLSAddress: + return LowerGlobalTLSAddress(Op, DAG); + case ISD::BlockAddress: + return LowerBlockAddress(Op, DAG); + case ISD::ConstantPool: + return LowerConstantPool(Op, DAG); + case ISD::BR_JT: + return LowerBR_JT(Op, DAG); + case ISD::LOAD: + return LowerLOAD(Op, DAG); + case ISD::STORE: + return LowerSTORE(Op, DAG); + case ISD::SELECT_CC: + return LowerSELECT_CC(Op, DAG); + case ISD::VAARG: + return LowerVAARG(Op, DAG); + case ISD::VASTART: + return LowerVASTART(Op, DAG); + case ISD::SMUL_LOHI: + return LowerSMUL_LOHI(Op, DAG); + case ISD::UMUL_LOHI: + return LowerUMUL_LOHI(Op, DAG); + case ISD::ADD: + case ISD::SUB: + return ExpandADDSUB(Op.getNode(), DAG); + case ISD::FRAMEADDR: + return LowerFRAMEADDR(Op, DAG); + case ISD::FRAME_TO_ARGS_OFFSET: + return LowerFRAME_TO_ARGS_OFFSET(Op, DAG); + case ISD::RETURNADDR: + return LowerRETURNADDR(Op, DAG); + case ISD::INIT_TRAMPOLINE: + return LowerINIT_TRAMPOLINE(Op, DAG); + case ISD::ADJUST_TRAMPOLINE: + return LowerADJUST_TRAMPOLINE(Op, DAG); + case ISD::INTRINSIC_WO_CHAIN: + return LowerINTRINSIC_WO_CHAIN(Op, DAG); + case ISD::STACKSAVE: + return LowerSTACKSAVE(Op, DAG); + case ISD::STACKRESTORE: + return LowerSTACKRESTORE(Op, DAG); + case ISD::DYNAMIC_STACKALLOC: + return LowerDYNAMIC_STACKALLOC(Op, DAG); + case ISD::ATOMIC_FENCE: + return LowerATOMIC_FENCE(Op, DAG); + default: + llvm_unreachable("unimplemented operand"); + return SDValue(); + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerRETURNADDR.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerRETURNADDR.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b75acc632eb5ef77bbf79092f515774eef1a2f43 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerRETURNADDR.cpp @@ -0,0 +1,26 @@ +SDValue XCoreTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const { + DebugLoc dl = Op.getDebugLoc(); + if (cast(Op.getOperand(0))->getZExtValue() > 0) + return SDValue(); + MachineFunction &MF = DAG.getMachineFunction(); + MachineFrameInfo *MFI = MF.getFrameInfo(); + XCoreFunctionInfo *XFI = MF.getInfo(); + if (XFI->LRSpillSlotSet) { + assert(LRSpillSlotSet && "LR Spill slot no set"); + return LRSpillSlot; + } + bool isVarArg = MF.getFunction()->isVarArg(); + int FrameIdx; + const TargetRegisterClass *RC = XCore::GRRegsRegisterClass; + if (!isVarArg) { + FrameIdx = MFI->CreateFixedObject(RC->getSize(), 0, true); + } + else { + FrameIdx = MFI->CreateStackObject(RC->getSize(), RC->getAlignment(), true); + } + assert(!LRSpillSlotSet && "LR Spill slot set twice"); + LRSpillSlotSet = true; + LRSpillSlot = FrameIdx; + int FI = FrameIdx; + return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), DAG.getFrameIndex(FI, MVT::i32), MachinePointerInfo::getFixedStack(FI), false, false, 0); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerReturn.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerReturn.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7d92be893cd8b1fdd7f6eeb36c3a93a59b536dab --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerReturn.cpp @@ -0,0 +1,43 @@ +SDValue XCoreTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl &Outs, const SmallVectorImpl &OutVals, DebugLoc dl, SelectionDAG &DAG) const { + XCoreFunctionInfo *XFI = DAG.getMachineFunction().getInfo(); + MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); + SmallVector RVLocs; + CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), getTargetMachine(), RVLocs, *DAG.getContext()); + if (!isVarArg) + CCInfo.AllocateStack(XFI->getReturnStackOffset(), 4); + CCInfo.AnalyzeReturn(Outs, RetCC_XCore); + if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { + for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) + if (RVLocs[i].isRegLoc()) + DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); + } + SDValue Flag; + SmallVector MemOpChains; + for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { + CCValAssign &VA = RVLocs[i]; + if (VA.isRegLoc()) + continue; + assert(VA.isMemLoc()); + if (isVarArg) { + report_fatal_error("Can't return value from vararg function in memory"); + } + int Offset = VA.getLocMemOffset(); + unsigned ObjSize = VA.getLocVT().getSizeInBits()/8; + int FI = MFI->CreateFixedObject(ObjSize, Offset, false); + SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); + MemOpChains.push_back(DAG.getStore(Chain, dl, OutVals[i], FIN, MachinePointerInfo::getFixedStack(FI), false, false, 0)); + } + if (!MemOpChains.empty()) + Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOpChains[0], MemOpChains.size()); + for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { + CCValAssign &VA = RVLocs[i]; + if (!VA.isRegLoc()) + continue; + Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag); + Flag = Chain.getValue(1); + } + if (Flag.getNode()) + return DAG.getNode(XCoreISD::RETSP, dl, MVT::Other, Chain, DAG.getConstant(0, MVT::i32), Flag); + else + return DAG.getNode(XCoreISD::RETSP, dl, MVT::Other, Chain, DAG.getConstant(0, MVT::i32)); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerSELECT_CC.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerSELECT_CC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b71a4128a90404148d2c00b6bf5a284d0abf97c2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerSELECT_CC.cpp @@ -0,0 +1,5 @@ +SDValue XCoreTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { + DebugLoc dl = Op.getDebugLoc(); + SDValue Cond = DAG.getNode(ISD::SETCC, dl, MVT::i32, Op.getOperand(2), Op.getOperand(3), Op.getOperand(4)); + return DAG.getNode(ISD::SELECT, dl, MVT::i32, Cond, Op.getOperand(0), Op.getOperand(1)); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerSMUL_LOHI.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerSMUL_LOHI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..56af17795ab02bb27da3d1843f661b518a72112b --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerSMUL_LOHI.cpp @@ -0,0 +1,12 @@ + +SDValue XCoreTargetLowering::LowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const { + assert(Op.getValueType() == MVT::i32 && Op.getOpcode() == ISD::SMUL_LOHI && "Unexpected operand to lower!"); + DebugLoc dl = Op.getDebugLoc(); + SDValue LHS = Op.getOperand(0); + SDValue RHS = Op.getOperand(1); + SDValue Zero = DAG.getConstant(0, MVT::i32); + SDValue Hi = DAG.getNode(XCoreISD::MACCS, dl, DAG.getVTList(MVT::i32, MVT::i32), Zero, Zero, LHS, RHS); + SDValue Lo(Hi.getNode(), 1); + SDValue Ops[] = { Lo, Hi }; + return DAG.getMergeValues(Ops, 2, dl); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerSTACKSAVE.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerSTACKSAVE.cpp new file mode 100644 index 0000000000000000000000000000000000000000..88dd4a14b3d16d388a51aa7779eabe03a9fa83b6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerSTACKSAVE.cpp @@ -0,0 +1,10 @@ +SDValue XCoreTargetLowering::LowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const { + SmallVector Ops, Results; + SDNode *Node = Op.getNode(); + DebugLoc dl = Node->getDebugLoc(); + unsigned SP = this->getStackPointerRegisterToSaveRestore(); + SDValue chain = DAG.getNode(XCoreISD::STACKSAVE, dl, MVT::Other, Node->getOperand(0)); + Results.push_back(DAG.getCopyFromReg(chain, dl, SP, Node->getValueType(0))); + Results.push_back(Results[0].getValue(1)); + return Results[Op.getResNo()]; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerSTORE.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerSTORE.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ec164cdbbee7ea55c820613252567eff822041bd --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerSTORE.cpp @@ -0,0 +1,34 @@ +SDValue XCoreTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const { + StoreSDNode *ST = cast(Op); + assert(!ST->isTruncatingStore() && "Unexpected store type"); + assert(ST->getMemoryVT() == MVT::i32 && "Unexpected store EVT"); + if (allowsUnalignedMemoryAccesses(ST->getMemoryVT())) { + return SDValue(); + } + unsigned ABIAlignment = getTargetData()->getABITypeAlignment(ST->getMemoryVT().getTypeForEVT(*DAG.getContext())); + if (ST->getAlignment() >= ABIAlignment) { + return SDValue(); + } + SDValue Chain = ST->getChain(); + SDValue BasePtr = ST->getBasePtr(); + SDValue Value = ST->getValue(); + DebugLoc dl = Op.getDebugLoc(); + if (ST->getAlignment() == 2) { + SDValue Low = Value; + SDValue High = DAG.getNode(ISD::SRL, dl, MVT::i32, Value, DAG.getConstant(16, MVT::i32)); + SDValue StoreLow = DAG.getTruncStore(Chain, dl, Low, BasePtr, ST->getPointerInfo(), MVT::i16, ST->isVolatile(), ST->isNonTemporal(), 2); + SDValue HighAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, BasePtr, DAG.getConstant(2, MVT::i32)); + SDValue StoreHigh = DAG.getTruncStore(Chain, dl, High, HighAddr, ST->getPointerInfo().getWithOffset(2), MVT::i16, ST->isVolatile(), ST->isNonTemporal(), 2); + return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, StoreLow, StoreHigh); + } + Type *IntPtrTy = getTargetData()->getIntPtrType(*DAG.getContext()); + TargetLowering::ArgListTy Args; + TargetLowering::ArgListEntry Entry; + Entry.Ty = IntPtrTy; + Entry.Node = BasePtr; + Args.push_back(Entry); + Entry.Node = Value; + Args.push_back(Entry); + std::pair CallResult = LowerCallTo(Chain, Type::getVoidTy(*DAG.getContext()), false, false, false, false, 0, CallingConv::C, false, true, DAG.getExternalSymbol("__misaligned_store", getPointerTy()), Args, DAG, dl); + return CallResult.second; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerUMUL_LOHI.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerUMUL_LOHI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4f8f2c69b172e71f7821741f67893ddcb7cac14f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerUMUL_LOHI.cpp @@ -0,0 +1,11 @@ +SDValue XCoreTargetLowering::LowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const { + assert(Op.getValueType() == MVT::i32 && Op.getOpcode() == ISD::UMUL_LOHI && "Unexpected operand to lower!"); + DebugLoc dl = Op.getDebugLoc(); + SDValue LHS = Op.getOperand(0); + SDValue RHS = Op.getOperand(1); + SDValue Zero = DAG.getConstant(0, MVT::i32); + SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl, DAG.getVTList(MVT::i32, MVT::i32), LHS, RHS, Zero, Zero); + SDValue Lo(Hi.getNode(), 1); + SDValue Ops[] = { Lo, Hi }; + return DAG.getMergeValues(Ops, 2, dl); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerVAARG.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerVAARG.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bf69a3cc177e9e2bd7ad7da5151ee914fb8af199 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerVAARG.cpp @@ -0,0 +1,11 @@ +SDValue XCoreTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const { + llvm_unreachable("unimplemented"); + SDNode *Node = Op.getNode(); + DebugLoc dl = Node->getDebugLoc(); + const Value *V = cast(Node->getOperand(2))->getValue(); + EVT VT = Node->getValueType(0); + SDValue VAList = DAG.getLoad(getPointerTy(), dl, Node->getOperand(0), Node->getOperand(1), MachinePointerInfo(V), false, false, 0); + SDValue Tmp3 = DAG.getNode(ISD::ADD, dl, getPointerTy(), VAList, DAG.getConstant(VT.getSizeInBits(), getPointerTy())); + Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Node->getOperand(1), MachinePointerInfo(V), false, false, 0); + return DAG.getLoad(VT, dl, Tmp3, VAList, MachinePointerInfo(), false, false, 0); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerVASTART.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerVASTART.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6371174ad1f20e37b5ff89375670b2574bb2c250 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/LowerVASTART.cpp @@ -0,0 +1,7 @@ +SDValue XCoreTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { + DebugLoc dl = Op.getDebugLoc(); + MachineFunction &MF = DAG.getMachineFunction(); + XCoreFunctionInfo *XFI = MF.getInfo(); + SDValue Addr = DAG.getFrameIndex(XFI->getVarArgsFrameIndex(), MVT::i32); + return DAG.getStore(Op.getOperand(0), dl, Addr, Op.getOperand(1), MachinePointerInfo(), false, false, 0); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/NodeType.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/NodeType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9a1ee15c8b3b2429e290055b06727738ecfdd0e4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/NodeType.cpp @@ -0,0 +1,30 @@ +enum NodeType { + FIRST_NUMBER = ISD::BUILTIN_OP_END, + BL, + PCRelativeWrapper, + DPRelativeWrapper, + CPRelativeWrapper, + ABS16Wrapper, + LDWSP, + STWSP, + RETSP, + OUTPW, + INPW, + LADD, + LSUB, + LMUL, + MACCU, + MACCS, + BR_JT, + BR_JT32, + FRAME_TO_ARGS_OFFSET, + EH_RETURN, + MEMBARRIER, + RETURN_REG_HOLDER, + STACKSAVE, + STACKRESTORE, + STACKUP, + STACKDOWN, + ALLOCA, + LOOPMARKER +}; diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/PerformDAGCombine.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/PerformDAGCombine.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4fe03b109553d27111a8471ed9b45495d035e21c --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/PerformDAGCombine.cpp @@ -0,0 +1,211 @@ +SDValue XCoreTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { + SelectionDAG &DAG = DCI.DAG; + DebugLoc dl = N->getDebugLoc(); + switch (N->getOpcode()) { + default: break; + case ISD::INTRINSIC_W_CHAIN: + switch (cast(N->getOperand(1))->getZExtValue()) { + case Intrinsic::xcore_in: { + const SDValue op = N->getOperand(0); + if (isSetPSC(op)) { + if (op->getOperand(2) != N->getOperand(2)) + break; + SDValue Chain = op->getOperand(0); + SDValue Resource = N->getOperand(2); + SDValue Width = op->getOperand(3); + return DAG.getNode(XCoreISD::INPW, dl, + DAG.getVTList(N->getValueType(0), N->getValueType(1)), + Chain, Resource, Width); + } + break; + } + } + break; + case ISD::INTRINSIC_VOID: + switch (cast(N->getOperand(1))->getZExtValue()) { + case Intrinsic::xcore_out: { + const SDValue op = N->getOperand(0); + if (isSetPSC(op)) { + if (op->getOperand(2) != N->getOperand(2)) + break; + SDValue Chain = op->getOperand(0); + SDValue Resource = N->getOperand(2); + SDValue OutVal = N->getOperand(3); + SDValue Width = op->getOperand(3); + return DAG.getNode(XCoreISD::OUTPW, dl, MVT::Other, Chain, Resource, OutVal, Width); + } + break; + } + case Intrinsic::xcore_outt: + case Intrinsic::xcore_outct: + case Intrinsic::xcore_chkct: { + SDValue OutVal = N->getOperand(3); + if (OutVal.hasOneUse()) { + unsigned BitWidth = OutVal.getValueSizeInBits(); + APInt DemandedMask = APInt::getLowBitsSet(BitWidth, 8); + APInt KnownZero, KnownOne; + TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), !DCI.isBeforeLegalizeOps()); + const TargetLowering &TLI = DAG.getTargetLoweringInfo(); + if (TLO.ShrinkDemandedConstant(OutVal, DemandedMask) || TLI.SimplifyDemandedBits(OutVal, DemandedMask, KnownZero, KnownOne, TLO)) + DCI.CommitTargetLoweringOpt(TLO); + } + break; + } + case Intrinsic::xcore_setpt: { + SDValue Time = N->getOperand(3); + if (Time.hasOneUse()) { + unsigned BitWidth = Time.getValueSizeInBits(); + APInt DemandedMask = APInt::getLowBitsSet(BitWidth, 16); + APInt KnownZero, KnownOne; + TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), !DCI.isBeforeLegalizeOps()); + const TargetLowering &TLI = DAG.getTargetLoweringInfo(); + if (TLO.ShrinkDemandedConstant(Time, DemandedMask) || TLI.SimplifyDemandedBits(Time, DemandedMask, KnownZero, KnownOne, TLO)) + DCI.CommitTargetLoweringOpt(TLO); + } + break; + } + } + break; + case XCoreISD::LADD: { + SDValue N0 = N->getOperand(0); + SDValue N1 = N->getOperand(1); + SDValue N2 = N->getOperand(2); + ConstantSDNode *N0C = dyn_cast(N0); + ConstantSDNode *N1C = dyn_cast(N1); + EVT VT = N0.getValueType(); + if (N0C && !N1C) + return DAG.getNode(XCoreISD::LADD, dl, DAG.getVTList(VT, VT), N1, N0, N2); + if (N0C && N0C->isNullValue() && N1C && N1C->isNullValue()) { + SDValue Carry = DAG.getConstant(0, VT); + SDValue Result = DAG.getNode(ISD::AND, dl, VT, N2, DAG.getConstant(1, VT)); + SDValue Ops [] = { Carry, Result }; + return DAG.getMergeValues(Ops, 2, dl); + } + if (N1C && N1C->isNullValue() && N->hasNUsesOfValue(0, 0)) { + APInt KnownZero, KnownOne; + APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); + DAG.ComputeMaskedBits(N2, Mask, KnownZero, KnownOne); + if (~(KnownZero | APInt(VT.getSizeInBits(), 1)) == 0) { + SDValue Carry = DAG.getConstant(0, VT); + SDValue Result = DAG.getNode(ISD::ADD, dl, VT, N0, N2); + SDValue Ops [] = { Carry, Result }; + return DAG.getMergeValues(Ops, 2, dl); + } + } + } + break; + case XCoreISD::LSUB: { + SDValue N0 = N->getOperand(0); + SDValue N1 = N->getOperand(1); + SDValue N2 = N->getOperand(2); + ConstantSDNode *N0C = dyn_cast(N0); + ConstantSDNode *N1C = dyn_cast(N1); + EVT VT = N0.getValueType(); + if (N0C && N0C->isNullValue() && N1C && N1C->isNullValue()) { + APInt KnownZero, KnownOne; + APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); + DAG.ComputeMaskedBits(N2, Mask, KnownZero, KnownOne); + if (~(KnownZero | APInt(VT.getSizeInBits(), 1)) == 0) { + SDValue Borrow = N2; + SDValue Result = DAG.getNode(ISD::SUB, dl, MVT::i32, DAG.getConstant(0, MVT::i32), N2); + SDValue Ops [] = { Borrow, Result }; + return DAG.getMergeValues(Ops, 2, dl); + } + } + if (N1C && N1C->isNullValue() && N->hasNUsesOfValue(0, 0)) { + APInt KnownZero, KnownOne; + APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); + DAG.ComputeMaskedBits(N2, Mask, KnownZero, KnownOne); + if (~(KnownZero | APInt(VT.getSizeInBits(), 1)) == 0) { + SDValue Borrow = DAG.getConstant(0, VT); + SDValue Result = DAG.getNode(ISD::SUB, dl, VT, N0, N2); + SDValue Ops [] = { Borrow, Result }; + return DAG.getMergeValues(Ops, 2, dl); + } + } + } + break; + case XCoreISD::LMUL: { + SDValue N0 = N->getOperand(0); + SDValue N1 = N->getOperand(1); + SDValue N2 = N->getOperand(2); + SDValue N3 = N->getOperand(3); + ConstantSDNode *N0C = dyn_cast(N0); + ConstantSDNode *N1C = dyn_cast(N1); + EVT VT = N0.getValueType(); + if ((N0C && !N1C) || (N0C && N1C && N0C->getZExtValue() < N1C->getZExtValue())) + return DAG.getNode(XCoreISD::LMUL, dl, DAG.getVTList(VT, VT), N1, N0, N2, N3); + if (N1C && N1C->isNullValue()) { + if (N->hasNUsesOfValue(0, 0)) { + SDValue Lo = DAG.getNode(ISD::ADD, dl, VT, N2, N3); + SDValue Ops [] = { Lo, Lo }; + return DAG.getMergeValues(Ops, 2, dl); + } + return DAG.getNode(XCoreISD::LADD, dl, DAG.getVTList(VT, VT), N2, N3, N1); + } + ConstantSDNode *N2C = dyn_cast(N2); + ConstantSDNode *N3C = dyn_cast(N3); + if (N2C && N3C && N->hasNUsesOfValue(0, 0)) { + SDValue Mul = DAG.getNode(ISD::MUL, dl, VT, N0, N1); + SDValue AddRHS = DAG.FoldConstantArithmetic(ISD::ADD, VT, N2C, N3C); + SDValue Add = DAG.getNode(ISD::ADD, dl, VT, Mul, AddRHS); + SDValue Ops [] = { Add, Add }; + return DAG.getMergeValues(Ops, 2, dl); + } + if (N2C && N3C) + return DAG.getNode(XCoreISD::LMUL, dl, DAG.getVTList(VT, VT), N0, N1, N3, N2); + if (N3C && N3C->isNullValue() && N->hasNUsesOfValue(0, 0)) { + SDValue Mul = DAG.getNode(ISD::MUL, dl, VT, N0, N1); + SDValue Add = DAG.getNode(ISD::ADD, dl, VT, Mul, N2); + SDValue Ops [] = { Add, Add }; + return DAG.getMergeValues(Ops, 2, dl); + } + } + break; + case ISD::ADD: { + SDValue Mul0, Mul1, Addend0, Addend1; +#if 0 + if (N->getValueType(0) == MVT::i32 && isADDADDMUL(SDValue(N, 0), Mul0, Mul1, Addend0, Addend1, true)) { + SDValue Zero = DAG.getConstant(0, MVT::i32); + SDValue Ignored = DAG.getNode(XCoreISD::LMUL, dl, DAG.getVTList(MVT::i32, MVT::i32), Mul0, Mul1, Addend0, Addend1); + SDValue Result(Ignored.getNode(), 1); + return Result; + } +#endif + APInt HighMask = APInt::getHighBitsSet(64, 32); + if (N->getValueType(0) == MVT::i64 && isADDADDMUL(SDValue(N, 0), Mul0, Mul1, Addend0, Addend1, false) && DAG.MaskedValueIsZero(Mul0, HighMask) && DAG.MaskedValueIsZero(Mul1, HighMask) && DAG.MaskedValueIsZero(Addend0, HighMask) && DAG.MaskedValueIsZero(Addend1, HighMask)) { + SDValue Mul0L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Mul0, DAG.getConstant(0, MVT::i32)); + SDValue Mul1L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Mul1, DAG.getConstant(0, MVT::i32)); + SDValue Addend0L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Addend0, DAG.getConstant(0, MVT::i32)); + SDValue Addend1L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Addend1, DAG.getConstant(0, MVT::i32)); + SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl, DAG.getVTList(MVT::i32, MVT::i32), Mul0L, Mul1L, Addend0L, Addend1L); + SDValue Lo(Hi.getNode(), 1); + return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); + } + } + break; + case ISD::STORE: { + StoreSDNode *ST = cast(N); + if (!DCI.isBeforeLegalize() || allowsUnalignedMemoryAccesses(ST->getMemoryVT()) || ST->isVolatile() || ST->isIndexed()) { + break; + } + SDValue Chain = ST->getChain(); + unsigned StoreBits = ST->getMemoryVT().getStoreSizeInBits(); + if (StoreBits % 8) { + break; + } + unsigned ABIAlignment = getTargetData()->getABITypeAlignment(ST->getMemoryVT().getTypeForEVT(*DCI.DAG.getContext())); + unsigned Alignment = ST->getAlignment(); + if (Alignment >= ABIAlignment) { + break; + } + if (LoadSDNode *LD = dyn_cast(ST->getValue())) { + if (LD->hasNUsesOfValue(1, 0) && ST->getMemoryVT() == LD->getMemoryVT() && LD->getAlignment() == Alignment && !LD->isVolatile() && !LD->isIndexed() && Chain.reachesChainWithoutSideEffects(SDValue(LD, 1))) { + return DAG.getMemmove(Chain, dl, ST->getBasePtr(), LD->getBasePtr(), DAG.getConstant(StoreBits/8, MVT::i32), Alignment, false, ST->getPointerInfo(), LD->getPointerInfo()); + } + } + break; + } + } + return SDValue(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/ReplaceNodeResults.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/ReplaceNodeResults.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4e2fa8425501ba6638136e12a8901efee0df4c33 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/ReplaceNodeResults.cpp @@ -0,0 +1,11 @@ +void XCoreTargetLowering::ReplaceNodeResults(SDNode *N, SmallVectorImpl&Results, SelectionDAG &DAG) const { + switch (N->getOpcode()) { + default: + llvm_unreachable("Don't know how to custom expand this!"); + return; + case ISD::ADD: + case ISD::SUB: + Results.push_back(ExpandADDSUB(N, DAG)); + return; + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/TargetLowering.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/TargetLowering.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f6b970bf50533c78ff8eb44151f8591a567f1f66 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/TargetLowering.cpp @@ -0,0 +1,67 @@ +XCoreTargetLowering::XCoreTargetLowering(XCoreTargetMachine &XTM) : TargetLowering(XTM, new XCoreTargetObjectFile()), TM(XTM), Subtarget(*XTM.getSubtargetImpl()) { + addRegisterClass(MVT::i32, XCore::GRRegsRegisterClass); + computeRegisterProperties(); + setIntDivIsCheap(false); + setStackPointerRegisterToSaveRestore(XCore::SP); + setSchedulingPreference(Sched::RegPressure); + setBooleanContents(ZeroOrOneBooleanContent); + setBooleanVectorContents(ZeroOrOneBooleanContent); + setOperationAction(ISD::BR_CC, MVT::Other, Expand); + setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); + setOperationAction(ISD::ADDC, MVT::i32, Expand); + setOperationAction(ISD::ADDE, MVT::i32, Expand); + setOperationAction(ISD::SUBC, MVT::i32, Expand); + setOperationAction(ISD::SUBE, MVT::i32, Expand); + setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); + setOperationAction(ISD::ADD, MVT::i64, Custom); + setOperationAction(ISD::SUB, MVT::i64, Custom); + setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom); + setOperationAction(ISD::UMUL_LOHI, MVT::i32, Custom); + setOperationAction(ISD::MULHS, MVT::i32, Expand); + setOperationAction(ISD::MULHU, MVT::i32, Expand); + setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); + setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); + setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); + setOperationAction(ISD::CTPOP, MVT::i32, Expand); + setOperationAction(ISD::ROTL , MVT::i32, Expand); + setOperationAction(ISD::ROTR , MVT::i32, Expand); + setOperationAction(ISD::TRAP, MVT::Other, Legal); + setOperationAction(ISD::BR_JT, MVT::Other, Custom); + setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); + setOperationAction(ISD::BlockAddress, MVT::i32 , Custom); + setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); + setOperationAction(ISD::ConstantPool, MVT::i32, Custom); + setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); + setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); + setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); + setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand); + setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Expand); + setOperationAction(ISD::LOAD, MVT::i32, Custom); + setOperationAction(ISD::STORE, MVT::i32, Custom); + setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom); + setOperationAction(ISD::VAEND, MVT::Other, Expand); + setOperationAction(ISD::VACOPY, MVT::Other, Expand); + setOperationAction(ISD::VAARG, MVT::Other, Custom); + setOperationAction(ISD::VASTART, MVT::Other, Custom); + setOperationAction(ISD::STACKSAVE, MVT::Other, Custom); + setOperationAction(ISD::STACKRESTORE, MVT::Other, Custom); + setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom); + setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); + setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); + setOperationAction(ISD::EH_RETURN, MVT::Other, Custom); + setExceptionPointerRegister(XCore::R0); + setExceptionSelectorRegister(XCore::R1); + setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom); + setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom); + setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom); + maxStoresPerMemset = maxStoresPerMemsetOptSize = 4; + maxStoresPerMemmove = maxStoresPerMemmoveOptSiz = maxStoresPerMemcpy = maxStoresPerMemcpyOptSize = 2; + benefitFromCodePlacementOpt = true; + setTargetDAGCombine(ISD::STORE); + setTargetDAGCombine(ISD::ADD); + setTargetDAGCombine(ISD::INTRINSIC_VOID); + setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN); + setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); + setMinFunctionAlignment(1); + setPrefFunctionAlignment(2); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/computeMaskedBitsForTargetNode.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/computeMaskedBitsForTargetNode.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0a6a6a59496007195bb1f7b7e2615c40a9c9837f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/computeMaskedBitsForTargetNode.cpp @@ -0,0 +1,32 @@ +void XCoreTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, const APInt &Mask, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth) const { + KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); + switch (Op.getOpcode()) { + default: break; + case XCoreISD::LADD: + case XCoreISD::LSUB: + if (Op.getResNo() == 0) { + KnownZero = APInt::getHighBitsSet(Mask.getBitWidth(),Mask.getBitWidth() - 1); + } + break; + case ISD::INTRINSIC_W_CHAIN: { + unsigned IntNo = cast(Op.getOperand(1))->getZExtValue(); + switch (IntNo) { + case Intrinsic::xcore_int: + case Intrinsic::xcore_inct: + KnownZero = APInt::getHighBitsSet(Mask.getBitWidth(), Mask.getBitWidth() - 8); + break; + case Intrinsic::xcore_testct: + KnownZero = APInt::getHighBitsSet(Mask.getBitWidth(), Mask.getBitWidth() - 1); + break; + case Intrinsic::xcore_testwct: + KnownZero = APInt::getHighBitsSet(Mask.getBitWidth(), Mask.getBitWidth() - 3); + break; + case Intrinsic::xcore_getts: + KnownZero = APInt::getHighBitsSet(Mask.getBitWidth(), Mask.getBitWidth() - 16); + break; + } + } + break; + } + KnownZero &= Mask; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/enum NodeType.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/enum NodeType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7dbfada60499fd466d80b554df14092a07c7992f --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/enum NodeType.cpp @@ -0,0 +1,26 @@ +enum NodeType { + ISD::ADD, + ISD::SUB, + ISD::MUL, + ISD::SDIV, + ISD::UDIV, + ISD::SREM, + ISD::UREM, + ISD::SMUL_LOHI, + ISD::UMUL_LOHI, + ISD::SDIVREM, + ISD::UDIVREM, + ISD::AND, + ISD::OR, + ISD::XOR, + ISD::SHL, + ISD::SRA, + ISD::SRL, + ISD::CTLZ, + ISD::CTLZ_ZERO_UNDEF, + ISD::CTTZ, + ISD::CTTZ_ZERO_UNDEF, + ISD::CTPOP, + ISD::SELECT, + ISD::SELECT_CC, +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/getJumpTableEncoding.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/getJumpTableEncoding.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cb0be2290182886ca5cafde35b5b3f4ec6b7bbf2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/getJumpTableEncoding.cpp @@ -0,0 +1,3 @@ +unsigned XCoreTargetLowering::getJumpTableEncoding() const { + return MachineJumpTableInfo::EK_Inline; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/getRegForInlineAsmConstraint.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/getRegForInlineAsmConstraint.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4001e7e59af509ba2ee14f220400970fa5224c72 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/getRegForInlineAsmConstraint.cpp @@ -0,0 +1,13 @@ +std::pair XCoreTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const { + if (Constraint.size() == 1) { + switch (Constraint[0]) { + default : + break; + case 'r': + if (VT.getSizeInBits() <= 32) { + return std::make_pair(0U, XCore::GRRegsRegisterClass); + } + } + } + return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/getShiftAmountTy.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/getShiftAmountTy.cpp new file mode 100644 index 0000000000000000000000000000000000000000..89dc8c9c1c2cda3be8fa11e4ff697346590dd063 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/getShiftAmountTy.cpp @@ -0,0 +1,3 @@ +virtual MVT getShiftAmountTy(EVT LHSTy) const { + return MVT::i32; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/getTargetNodeName.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/getTargetNodeName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..31a988e9d6ac50c53966dce12aa3a58bbbffebf1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/getTargetNodeName.cpp @@ -0,0 +1,46 @@ +const char *XCoreTargetLowering::getTargetNodeName(unsigned Opcode) const { + switch (Opcode) { + case XCoreISD::BL : + return "XCoreISD::BL"; + case XCoreISD::PCRelativeWrapper : + return "XCoreISD::PCRelativeWrapper"; + case XCoreISD::DPRelativeWrapper : + return "XCoreISD::DPRelativeWrapper"; + case XCoreISD::CPRelativeWrapper : + return "XCoreISD::CPRelativeWrapper"; + case XCoreISD::ABS16Wrapper : + return "XCoreISD::ABS16Wrapper"; + case XCoreISD::LDWSP : + return "XCoreISD::LDWSP"; + case XCoreISD::STWSP : + return "XCoreISD::STWSP"; + case XCoreISD::RETSP : + return "XCoreISD::RETSP"; + case XCoreISD::LADD : + return "XCoreISD::LADD"; + case XCoreISD::OUTPW : + return "XCoreISD::OUTPW"; + case XCoreISD::INPW : + return "XCoreISD::INPW"; + case XCoreISD::LSUB : + return "XCoreISD::LSUB"; + case XCoreISD::LMUL : + return "XCoreISD::LMUL"; + case XCoreISD::MACCU : + return "XCoreISD::MACCU"; + case XCoreISD::MACCS : + return "XCoreISD::MACCS"; + case XCoreISD::BR_JT : + return "XCoreISD::BR_JT"; + case XCoreISD::BR_JT32 : + return "XCoreISD::BR_JT32"; + case XCoreISD::FRAME_TO_ARGS_OFFSET : + return "XCoreISD::FRAME_TO_ARGS_OFFSET"; + case XCoreISD::EH_RETURN : + return "XCoreISD::EH_RETURN"; + case XCoreISD::MEMBARRIER : + return "XCoreISD::MEMBARRIER"; + default : + return NULL; + } +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/isLegalAddImmediate.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/isLegalAddImmediate.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d49ed42164af8d1d5fc83b341e857d7d24d2ea6e --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/isLegalAddImmediate.cpp @@ -0,0 +1,3 @@ +bool XCoreTargetLowering::isLegalAddImmediate(int64_t Imm) const { + return isImmUs(Imm) || isImmUs4(Imm) || isImmUs(-Imm) || isImmUs4(-Imm); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/isLegalAddressingMode.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/isLegalAddressingMode.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3a52d819ba2f3415709b2ea7e1a31ba114f4a70a --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/isLegalAddressingMode.cpp @@ -0,0 +1,28 @@ +bool XCoreTargetLowering::isLegalAddressingMode(const AddrMode &AM, Type *Ty) const { + if (Ty->getTypeID() == Type::VoidTyID) + return AM.Scale == 0 && isImmUs(AM.BaseOffs) && isImmUs4(AM.BaseOffs); + const TargetData *TD = TM.getTargetData(); + unsigned Size = TD->getTypeAllocSize(Ty); + if (AM.BaseGV) { + return Size >= 4 && !AM.HasBaseReg && AM.Scale == 0 && AM.BaseOffs%4 == 0; + } + switch (Size) { + case 1: + if (AM.Scale == 0) { + return isImmUs(AM.BaseOffs); + } + return AM.Scale == 1 && AM.BaseOffs == 0; + case 2: + case 3: + if (AM.Scale == 0) { + return isImmUs2(AM.BaseOffs); + } + return AM.Scale == 2 && AM.BaseOffs == 0; + default: + if (AM.Scale == 0) { + return isImmUs4(AM.BaseOffs); + } + return AM.Scale == 4 && AM.BaseOffs == 0; + } + return false; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/isLegalICmpImmediate.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/isLegalICmpImmediate.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4bbf90dc1c01680efb3151e7def7fbe0cf9cfea1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/ISelLowering/isLegalICmpImmediate.cpp @@ -0,0 +1,3 @@ +bool XCoreTargetLowering::isLegalICmpImmediate(int64_t Imm) const { + return val >= 0 && val <= 11; +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/SelectionDAGInfo/EmitTargetCodeForMemcpy.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/SelectionDAGInfo/EmitTargetCodeForMemcpy.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fdf851619a2023d364c88e468a8e10f94ea80e81 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/SelectionDAGInfo/EmitTargetCodeForMemcpy.cpp @@ -0,0 +1,14 @@ +SDValue XCoreSelectionDAGInfo::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const { + unsigned SizeBitWidth = Size.getValueType().getSizeInBits(); + if ((Align & 3) == 0 && DAG.MaskedValueIsZero(Size, APInt(SizeBitWidth, 3))) { + TargetLowering::ArgListTy Args; + TargetLowering::ArgListEntry Entry; + Entry.Ty = TLI.getTargetData()->getIntPtrType(*DAG.getContext()); + Entry.Node = Dst; Args.push_back(Entry); + Entry.Node = Src; Args.push_back(Entry); + Entry.Node = Size; Args.push_back(Entry); + std::pair CallResult = TLI.LowerCallTo(Chain, Type::getVoidTy(*DAG.getContext()), false, false, false, false, 0, TLI.getLibcallCallingConv(RTLIB::MEMCPY), false, false, DAG.getExternalSymbol("__memcpy_4", TLI.getPointerTy()), Args, DAG, dl); + return CallResult.second; + } + return SDValue(); +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/SelectionDAGInfo/SelectionDAGInfo.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/SelectionDAGInfo/SelectionDAGInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fde8beca3c06603dc51017ae842a289c990b8256 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/SelectionDAGInfo/SelectionDAGInfo.cpp @@ -0,0 +1,2 @@ +XCoreSelectionDAGInfo::XCoreSelectionDAGInfo(const XCoreTargetMachine &TM) : TargetSelectionDAGInfo(TM), TLI(*TM.getTargetLowering()) { +} diff --git a/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/SelectionDAGInfo/~SelectionDAGInfo.cpp b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/SelectionDAGInfo/~SelectionDAGInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e44e6f5cc19eabbc12d2f5562eaaf1408446aac3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/Std_Code/XCore/Selection/SelectionDAGInfo/~SelectionDAGInfo.cpp @@ -0,0 +1,2 @@ +XCoreSelectionDAGInfo::~XCoreSelectionDAGInfo() { +} diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Allocation/RegisterBankInfo/RegisterBankInfo.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Allocation/RegisterBankInfo/RegisterBankInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ca18419a68e985917f1941d9a6aa0abcd34bda5e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Allocation/RegisterBankInfo/RegisterBankInfo.cpp @@ -0,0 +1,2 @@ +PULPRegisterBankInfo :: PULPRegisterBankInfo ( const TargetRegisterInfo & TRI ) : PULPGenRegisterBankInfo ( ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Allocation/RegisterInfo/RegisterInfo.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Allocation/RegisterInfo/RegisterInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0f7a6be1e26ce148d5ad1febda8375ba27379912 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Allocation/RegisterInfo/RegisterInfo.cpp @@ -0,0 +1,2 @@ +PULPRegisterInfo :: PULPRegisterInfo ( unsigned HwMode ) : PULPGenRegisterInfo ( PULP :: X1 , 0 , 0 , 0 , HwMode ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Allocation/RegisterInfo/eliminateFrameIndex.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Allocation/RegisterInfo/eliminateFrameIndex.cpp new file mode 100644 index 0000000000000000000000000000000000000000..307ce8d4f6e49a2cfeee5b0a365a56ed4b6f4ac5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Allocation/RegisterInfo/eliminateFrameIndex.cpp @@ -0,0 +1,23 @@ +void PULPRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { +assert ( SPAdj == 0 && "Unexpected non-zero SPAdj value" ) ; +MachineInstr & MI = * II ; +MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; +MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; +DebugLoc DL = MI . getDebugLoc ( ) ; +const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; +DebugLoc dl = MI . getDebugLoc ( ) ; +int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; +Register FrameReg ; +int Offset = getFrameLowering ( MF ) -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) + MI . getOperand ( FIOperandNum + 1 ) . getImm ( ) ; +if ( ! isInt < 16 > ( Offset ) ) { +report_fatal_error ( "Frame offsets outside of the signed 16-bit range not supported" ) ; +} +MachineBasicBlock & MBB = * MI . getParent ( ) ; +unsigned DstReg = MI . getOperand ( 0 ) . getReg ( ) ; +int64_t spOffset = MF . getFrameInfo ( ) -> getObjectOffset ( frameIndex ) ; +bool FrameRegIsKill = true ; +int64_t Offset = spOffset + ( int64_t ) stackSize ; +MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false , false , FrameRegIsKill ) ; +MI . getOperand ( FIOperandNum + 1 ) . ChangeToImmediate ( Offset ) ; +MI . getOperand ( OffsetOperandNo ) . ChangeToImmediate ( Offset ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Allocation/RegisterInfo/getCallPreservedMask.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Allocation/RegisterInfo/getCallPreservedMask.cpp new file mode 100644 index 0000000000000000000000000000000000000000..be0593e6471d5d2691d585d75e4305f6d2fb6c72 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Allocation/RegisterInfo/getCallPreservedMask.cpp @@ -0,0 +1,24 @@ +const uint32_t * PULPRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { +if ( CC == CallingConv :: GHC ) { +return CSR_NoRegs_RegMask ; +} +if ( Subtarget . getTargetABI ( ) == PULPABI :: ABI_ILP32 ) { +return CSR_ILP32_LP64_RegMask ; +} +if ( Subtarget . getTargetABI ( ) == PULPABI :: ABI_LP64 ) { +return CSR_ILP32_LP64_RegMask ; +} +if ( Subtarget . getTargetABI ( ) == PULPABI :: ABI_ILP32F ) { +return CSR_ILP32F_LP64F_RegMask ; +} +if ( Subtarget . getTargetABI ( ) == PULPABI :: ABI_LP64F ) { +return CSR_ILP32F_LP64F_RegMask ; +} +if ( Subtarget . getTargetABI ( ) == PULPABI :: ABI_ILP32D ) { +return CSR_ILP32D_LP64D_RegMask ; +} +if ( Subtarget . getTargetABI ( ) == PULPABI :: ABI_LP64D ) { +return CSR_ILP32D_LP64D_RegMask ; +} +llvm_unreachable ( "Unrecognized ABI" ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Allocation/RegisterInfo/getCalleeSavedRegs.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Allocation/RegisterInfo/getCalleeSavedRegs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2156dab6de93e1e71c3b2d17d5c9ca42067adc22 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Allocation/RegisterInfo/getCalleeSavedRegs.cpp @@ -0,0 +1,34 @@ +const MCPhysReg * PULPRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { +auto & Subtarget = MF -> getSubtarget < PULPSubtarget > ( ) ; +if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: GHC ) { +return CSR_NoRegs_SaveList ; +} +if ( MF -> getFunction ( ) . hasFnAttribute ( "interrupt" ) ) { +if ( Subtarget . hasStdExtD ( ) ) { +return CSR_XLEN_F64_Interrupt_SaveList ; +} +if ( Subtarget . hasStdExtF ( ) ) { +return CSR_XLEN_F32_Interrupt_SaveList ; +} +return CSR_Interrupt_SaveList ; +} +if ( Subtarget . getTargetABI ( ) == PULPABI :: ABI_ILP32 ) { +return CSR_ILP32_LP64_SaveList ; +} +if ( Subtarget . getTargetABI ( ) == PULPABI :: ABI_LP64 ) { +return CSR_ILP32_LP64_SaveList ; +} +if ( Subtarget . getTargetABI ( ) == PULPABI :: ABI_ILP32F ) { +return CSR_ILP32F_LP64F_SaveList ; +} +if ( Subtarget . getTargetABI ( ) == PULPABI :: ABI_LP64F ) { +return CSR_ILP32F_LP64F_SaveList ; +} +if ( Subtarget . getTargetABI ( ) == PULPABI :: ABI_ILP32D ) { +return CSR_ILP32D_LP64D_SaveList ; +} +if ( Subtarget . getTargetABI ( ) == PULPABI :: ABI_LP64D ) { +return CSR_ILP32D_LP64D_SaveList ; +} +llvm_unreachable ( "Unrecognized ABI" ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Allocation/RegisterInfo/getFrameRegister.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Allocation/RegisterInfo/getFrameRegister.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c88ca259851f992789d6f892eac0cc9055492291 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Allocation/RegisterInfo/getFrameRegister.cpp @@ -0,0 +1,4 @@ +Register PULPRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { +const TargetFrameLowering * TFI = getFrameLowering ( MF ) ; +return TFI -> hasFP ( MF ) ? PULP :: X8 : PULP :: X2 ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Allocation/RegisterInfo/getNoPreservedMask.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Allocation/RegisterInfo/getNoPreservedMask.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2ecd2035925c4a09d22874b22b444b8aa7977c9d --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Allocation/RegisterInfo/getNoPreservedMask.cpp @@ -0,0 +1,3 @@ +const uint32_t * PULPRegisterInfo :: getNoPreservedMask ( ) const { +return CSR_NoRegs_RegMask ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Allocation/RegisterInfo/getPointerRegClass.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Allocation/RegisterInfo/getPointerRegClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bf50717cae939db934a1465be403f4a2831c7088 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Allocation/RegisterInfo/getPointerRegClass.cpp @@ -0,0 +1,3 @@ +const TargetRegisterClass * getPointerRegClass ( const MachineFunction & MF , unsigned Kind = 0 ) const override { +return & PULP :: GPRRegClass ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Allocation/RegisterInfo/getReservedRegs.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Allocation/RegisterInfo/getReservedRegs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7b4ea25e86abc3e5bc463257c0e2de0b4eff81b8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Allocation/RegisterInfo/getReservedRegs.cpp @@ -0,0 +1,25 @@ +BitVector PULPRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { +const PULPFrameLowering * TFI = getFrameLowering ( MF ) ; +BitVector Reserved ( getNumRegs ( ) ) ; +for ( size_t Reg = 0 ; Reg < getNumRegs ( ) ; Reg ++ ) { +if ( MF . getSubtarget < PULPSubtarget > ( ) . isRegisterReservedByUser ( Reg ) ) { +markSuperRegs ( Reserved , Reg ) ; +} +} +if ( TFI -> hasBP ( MF ) ) { +markSuperRegs ( Reserved , PULP :: X9 ) ; +} +if ( TFI -> hasFP ( MF ) ) { +markSuperRegs ( Reserved , PULP :: X8 ) ; +} +markSuperRegs ( Reserved , PULP :: X0 ) ; +markSuperRegs ( Reserved , PULP :: X2 ) ; +markSuperRegs ( Reserved , PULP :: X3 ) ; +markSuperRegs ( Reserved , PULP :: X4 ) ; +markSuperRegs ( Reserved , PULP :: VL ) ; +markSuperRegs ( Reserved , PULP :: VTYPE ) ; +markSuperRegs ( Reserved , PULP :: VXSAT ) ; +markSuperRegs ( Reserved , PULP :: VXRM ) ; +assert ( checkAllSuperRegsMarked ( Reserved ) ) ; +return Reserved ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Allocation/RegisterInfo/hasReservedSpillSlot.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Allocation/RegisterInfo/hasReservedSpillSlot.cpp new file mode 100644 index 0000000000000000000000000000000000000000..17a7cdd240c417d73bb23373a6b756a50fffb5ce --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Allocation/RegisterInfo/hasReservedSpillSlot.cpp @@ -0,0 +1,6 @@ +bool PULPRegisterInfo :: hasReservedSpillSlot ( const MachineFunction & MF , Register Reg , int & FrameIdx ) const { +const auto * FI = MF . getInfo < PULPMachineFunctionInfo > ( ) ; +FrameIdx = FI -> getCRSpillFrameIndex ( ) ; +return true ; +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Allocation/RegisterInfo/isAsmClobberable.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Allocation/RegisterInfo/isAsmClobberable.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e1192ca89d9b62c31d6f5f45ae5a75a61719043e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Allocation/RegisterInfo/isAsmClobberable.cpp @@ -0,0 +1,3 @@ +bool PULPRegisterInfo :: isAsmClobberable ( const MachineFunction & MF , MCRegister PhysReg ) const { +return ! MF . getSubtarget < PULPSubtarget > ( ) . isRegisterReservedByUser ( PhysReg ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Allocation/RegisterInfo/isConstantPhysReg.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Allocation/RegisterInfo/isConstantPhysReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f2659261a3ed52e1f1f41d6308ee4acbee02c2af --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Allocation/RegisterInfo/isConstantPhysReg.cpp @@ -0,0 +1,5 @@ +bool PULPRegisterInfo :: isConstantPhysReg ( MCRegister PhysReg ) const { +if ( PhysReg == PULP :: X0 ) { +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Allocation/RegisterInfo/requiresFrameIndexScavenging.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Allocation/RegisterInfo/requiresFrameIndexScavenging.cpp new file mode 100644 index 0000000000000000000000000000000000000000..91452a8e068d51b582b56820d11be174835fb85a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Allocation/RegisterInfo/requiresFrameIndexScavenging.cpp @@ -0,0 +1,3 @@ +bool requiresFrameIndexScavenging ( const MachineFunction & MF ) const override { +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Allocation/RegisterInfo/requiresRegisterScavenging.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Allocation/RegisterInfo/requiresRegisterScavenging.cpp new file mode 100644 index 0000000000000000000000000000000000000000..be9254bdaf75d4ec168e9353281ffdaf92a1c0f6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Allocation/RegisterInfo/requiresRegisterScavenging.cpp @@ -0,0 +1,3 @@ +bool requiresRegisterScavenging ( const MachineFunction & MF ) const override { +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/AsmParser.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/AsmParser.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a0017bb8cee827c4d9e7f9c482e3a45fda5e2ef7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/AsmParser.cpp @@ -0,0 +1,7 @@ +PULPAsmParser ( const MCSubtargetInfo & STI , MCAsmParser & Parser , const MCInstrInfo & MII , const MCTargetOptions & Options ) : MCTargetAsmParser ( Options , STI , MII ) { +Parser . addAliasForDirective ( ".half" , ".2byte" ) ; +Parser . addAliasForDirective ( ".hword" , ".2byte" ) ; +Parser . addAliasForDirective ( ".word" , ".4byte" ) ; +Parser . addAliasForDirective ( ".dword" , ".8byte" ) ; +setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/KindTy.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/KindTy.cpp new file mode 100644 index 0000000000000000000000000000000000000000..26577a75b88d8eaab0fd8482d40f85ef7b9af5c0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/KindTy.cpp @@ -0,0 +1,7 @@ +enum class KindTy { +Token , +Register , +Immediate , +SystemRegister , +VType , +} Kind ; \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/LLVMInitializeAsmParser.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/LLVMInitializeAsmParser.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a3e735c7d1f1f07a6b445e4d144c76ad599147f3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/LLVMInitializeAsmParser.cpp @@ -0,0 +1,4 @@ +extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializePULPAsmParser ( ) { +RegisterMCAsmParser < PULPAsmParser > X ( getThePULP32Target ( ) ) ; +RegisterMCAsmParser < PULPAsmParser > Y ( getThePULP64Target ( ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/MatchAndEmitInstruction.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/MatchAndEmitInstruction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9bfecaa8c93ebc754d2d55ac753934158fe2c809 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/MatchAndEmitInstruction.cpp @@ -0,0 +1,166 @@ +bool PULPAsmParser :: MatchAndEmitInstruction ( SMLoc IDLoc , unsigned & Opcode , OperandVector & Operands , MCStreamer & Out , uint64_t & ErrorInfo , bool MatchingInlineAsm ) { +MCInst Inst ; +FeatureBitset MissingFeatures ; +auto Result = MatchInstructionImpl ( Operands , Inst , ErrorInfo , MissingFeatures , MatchingInlineAsm ) ; +if ( Result == Match_Success ) { +if ( validateInstruction ( Inst , Operands ) ) { +return true ; +} +return processInstruction ( Inst , IDLoc , Operands , Out ) ; +} +if ( Result == Match_MissingFeature ) { +assert ( MissingFeatures . any ( ) && "Unknown missing features!" ) ; +bool FirstFeature = true ; +std :: string Msg = "instruction requires the following:" ; +for ( unsigned i = 0 , e = MissingFeatures . size ( ) ; i != e ; ++ i ) { +if ( MissingFeatures [ i ] ) { +Msg = Msg + FirstFeature ? " " : ", " ; +Msg = Msg + getSubtargetFeatureName ( i ) ; +FirstFeature = false ; +} +} +return Error ( IDLoc , Msg ) ; +} +if ( Result == Match_MnemonicFail ) { +FeatureBitset FBS = ComputeAvailableFeatures ( getSTI ( ) . getFeatureBits ( ) ) ; +std :: string Suggestion = PULPMnemonicSpellCheck ( ( ( PULPOperand & ) * Operands [ 0 ] ) . getToken ( ) , FBS ) ; +return Error ( IDLoc , "unrecognized instruction mnemonic" + Suggestion ) ; +} +if ( Result == Match_InvalidOperand ) { +SMLoc ErrorLoc = IDLoc ; +if ( ErrorInfo != ~ 0ULL ) { +if ( ErrorInfo >= Operands . size ( ) ) { +return Error ( ErrorLoc , "too few operands for instruction" ) ; +} +ErrorLoc = ( ( PULPOperand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; +if ( ErrorLoc == SMLoc ( ) ) { +ErrorLoc = IDLoc ; +} +} +return Error ( ErrorLoc , "invalid operand for instruction" ) ; +} +if ( Result > FIRST_TARGET_MATCH_RESULT_TY ) { +SMLoc ErrorLoc = IDLoc ; +if ( ErrorInfo != ~ 0ULL ) { +if ( ErrorInfo >= Operands . size ( ) ) { +return Error ( ErrorLoc , "too few operands for instruction" ) ; +} +} +} +if ( Result == Match_RequiresMsbNotLessThanLsb ) { +SMLoc ErrorStart = Operands [ 3 ] -> getStartLoc ( ) ; +return Error ( ErrorStart , "msb is less than lsb" , SMRange ( ErrorStart , Operands [ 4 ] -> getEndLoc ( ) ) ) ; +} +if ( Result == Match_RequiresOpnd2NotR0R1 ) { +return Error ( Operands [ 2 ] -> getStartLoc ( ) , "must not be $r0 or $r1" ) ; +} +if ( Result == Match_InvalidUImm2 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , 0 , ( 1 << 2 ) - 1 ) ; +} +if ( Result == Match_InvalidUImm2plus1 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , 1 , ( 1 << 2 ) ) ; +} +if ( Result == Match_InvalidUImm3 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , 0 , ( 1 << 3 ) - 1 ) ; +} +if ( Result == Match_InvalidUImm5 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , 0 , ( 1 << 5 ) - 1 ) ; +} +if ( Result == Match_InvalidUImm6 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , 0 , ( 1 << 6 ) - 1 ) ; +} +if ( Result == Match_InvalidUImm12 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , 0 , ( 1 << 12 ) - 1 ) ; +} +if ( Result == Match_InvalidUImm15 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , 0 , ( 1 << 15 ) - 1 ) ; +} +if ( Result == Match_InvalidUImm15 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , 0 , ( 1 << 15 ) - 1 ) ; +} +if ( Result == Match_InvalidUImm15 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , 0 , ( 1 << 15 ) - 1 ) ; +} +if ( Result == Match_InvalidUImm15 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , 0 , ( 1 << 15 ) - 1 ) ; +} +if ( Result == Match_InvalidUImm15 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , 0 , ( 1 << 15 ) - 1 ) ; +} +if ( Result == Match_InvalidUImm15 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , 0 , ( 1 << 15 ) - 1 ) ; +} +if ( Result == Match_InvalidSImm12 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( 1 << 11 ) , ( 1 << 11 ) - 1 ) ; +} +if ( Result == Match_InvalidSImm12 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( 1 << 11 ) , ( 1 << 11 ) - 1 ) ; +} +if ( Result == Match_InvalidSImm12 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( 1 << 11 ) , ( 1 << 11 ) - 1 ) ; +} +if ( Result == Match_InvalidSImm12 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( 1 << 11 ) , ( 1 << 11 ) - 1 ) ; +} +if ( Result == Match_InvalidSImm12 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( 1 << 11 ) , ( 1 << 11 ) - 1 ) ; +} +if ( Result == Match_InvalidSImm14lsl2 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( 1 << 15 ) , ( 1 << 15 ) - 1 , "immediate must be a multiple of 4 in the range" ) ; +} +if ( Result == Match_InvalidSImm16 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( 1 << 15 ) , ( 1 << 15 ) - 1 ) ; +} +if ( Result == Match_InvalidSImm16lsl2 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( 1 << 17 ) , ( 1 << 17 ) - 1 , "immediate must be a multiple of 4 in the range" ) ; +} +if ( Result == Match_InvalidSImm16lsl2 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( 1 << 17 ) , ( 1 << 17 ) - 1 , "immediate must be a multiple of 4 in the range" ) ; +} +if ( Result == Match_InvalidSImm16lsl2 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( 1 << 17 ) , ( 1 << 17 ) - 1 , "immediate must be a multiple of 4 in the range" ) ; +} +if ( Result == Match_InvalidSImm16lsl2 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( 1 << 17 ) , ( 1 << 17 ) - 1 , "immediate must be a multiple of 4 in the range" ) ; +} +if ( Result == Match_InvalidSImm16lsl2 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( 1 << 17 ) , ( 1 << 17 ) - 1 , "immediate must be a multiple of 4 in the range" ) ; +} +if ( Result == Match_InvalidSImm16lsl2 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( 1 << 17 ) , ( 1 << 17 ) - 1 , "immediate must be a multiple of 4 in the range" ) ; +} +if ( Result == Match_InvalidSImm20 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( 1 << 19 ) , ( 1 << 19 ) - 1 ) ; +} +if ( Result == Match_InvalidSImm21lsl2 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( 1 << 22 ) , ( 1 << 22 ) - 4 , "immediate must be a multiple of 4 in the range" ) +} +if ( Result == Match_InvalidSImm21lsl2 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( 1 << 22 ) , ( 1 << 22 ) - 4 , "immediate must be a multiple of 4 in the range" ) +} +if ( Result == Match_InvalidSImm21lsl2 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( 1 << 22 ) , ( 1 << 22 ) - 4 , "immediate must be a multiple of 4 in the range" ) +} +if ( Result == Match_InvalidSImm26lsl2 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( 1 << 27 ) , ( 1 << 27 ) - 4 , "immediate must be a multiple of 4 in the range" ) ; +} +if ( Result == Match_InvalidSImm26lsl2 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( 1 << 27 ) , ( 1 << 27 ) - 4 , "immediate must be a multiple of 4 in the range" ) ; +} +if ( Result == Match_InvalidSImm26lsl2 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( 1 << 27 ) , ( 1 << 27 ) - 4 , "immediate must be a multiple of 4 in the range" ) ; +} +if ( Result == Match_InvalidSImm26lsl2 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( 1 << 27 ) , ( 1 << 27 ) - 4 , "immediate must be a multiple of 4 in the range" ) ; +} +if ( Result == Match_InvalidSImm26lsl2 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( 1 << 27 ) , ( 1 << 27 ) - 4 , "immediate must be a multiple of 4 in the range" ) ; +} +if ( Result == Match_InvalidSImm26lsl2 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( 1 << 27 ) , ( 1 << 27 ) - 4 , "immediate must be a multiple of 4 in the range" ) ; +} +if ( Result == Match_InvalidSImm26lsl2 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( 1 << 27 ) , ( 1 << 27 ) - 4 , "immediate must be a multiple of 4 in the range" ) ; +} +llvm_unreachable ( "Unknown match type detected!" ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/Operand.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/Operand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ce94f6645440d76acc5f23ab1503004b60fc5420 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/Operand.cpp @@ -0,0 +1,2 @@ +PULPOperand ( KindTy K ) : MCParsedAsmOperand ( ) , Kind ( K ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/Operand2.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/Operand2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..70ba022fc2b134b42d034a1741b9aa26ddfb703c --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/Operand2.cpp @@ -0,0 +1,16 @@ +PULPOperand ( const PULPOperand & o ) : MCParsedAsmOperand ( ) { +Kind = o . Kind ; +StartLoc = o . StartLoc ; +EndLoc = o . EndLoc ; +if ( Kind == KindTy :: Register ) { +Reg = o . Reg ; +} +if ( Kind == KindTy :: Immediate ) { +} +if ( Kind == KindTy :: Token ) { +} +if ( Kind == KindTy :: SystemRegister ) { +} +if ( Kind == KindTy :: VType ) { +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/ParseDirective.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/ParseDirective.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e22d15c41e72b806be78ef863416ed43f676feb4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/ParseDirective.cpp @@ -0,0 +1,10 @@ +bool PULPAsmParser :: ParseDirective ( AsmToken DirectiveID ) { +StringRef IDVal = DirectiveID . getString ( ) ; +if ( IDVal == ".option" ) { +return ParseDirectiveHSACodeObjectVersion ( ) ; +} +if ( IDVal == ".attribute" ) { +return ParseDirectiveHSACodeObjectISA ( ) ; +} +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/ParseInstruction.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/ParseInstruction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..40144f83d01c812e44b6add5ce186e4ced84a079 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/ParseInstruction.cpp @@ -0,0 +1,22 @@ +bool PULPAsmParser :: ParseInstruction ( ParseInstructionInfo & Info , StringRef Name , SMLoc NameLoc , OperandVector & Operands ) { +Operands . push_back ( PULPOperand :: createToken ( Name , NameLoc ) ) ; +if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) { +return false ; +} +if ( parseOperand ( Operands ) ) { +return true ; +} +for ( ; getLexer ( ) . is ( AsmToken :: Comma ) ; ) { +getLexer ( ) . Lex ( ) ; +if ( parseOperand ( Operands ) ) { +return true ; +} +} +if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { +SMLoc Loc = getLexer ( ) . getLoc ( ) ; +getParser ( ) . eatToEndOfStatement ( ) ; +return Error ( Loc , "unexpected token" ) ; +} +getParser ( ) . Lex ( ) ; +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/ParseRegister.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/ParseRegister.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c4de8738cec50d419e8f4d8802ba124cb359c253 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/ParseRegister.cpp @@ -0,0 +1,6 @@ +bool PULPAsmParser :: ParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc ) { +if ( tryParseRegister ( RegNo , StartLoc , EndLoc ) != MatchOperand_Success ) { +return Error ( StartLoc , "invalid register name" ) ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/addCSRSystemRegisterOperands.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/addCSRSystemRegisterOperands.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6b014312f9d2f313df503bedb185eeb4e023460b --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/addCSRSystemRegisterOperands.cpp @@ -0,0 +1,4 @@ +void addCSRSystemRegisterOperands ( MCInst & Inst , unsigned N ) const { +assert ( N == 1 && "Invalid number of operands!" ) ; +Inst . addOperand ( MCOperand :: createImm ( SysReg . Encoding ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/addExpr.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/addExpr.cpp new file mode 100644 index 0000000000000000000000000000000000000000..18dcad2acd83890c6545765b065c6ccd1b36bb80 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/addExpr.cpp @@ -0,0 +1,12 @@ +void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { +assert ( Expr && "Expr shouldn't be null!" ) ; +int64_t Imm = 0 ; +PULPMCExpr :: VariantKind VK = PULPMCExpr :: VK_PULP_None ; +bool IsConstant = evaluateConstantImm ( Expr , Imm , VK ) ; +if ( IsConstant ) { +Inst . addOperand ( MCOperand :: createImm ( Imm ) ) ; +} +if ( ! IsConstant ) { +Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ; +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/addFRMArgOperands.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/addFRMArgOperands.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1c7cefcbc2a13fab240d8157c57ba776c7be3f75 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/addFRMArgOperands.cpp @@ -0,0 +1,4 @@ +void addFRMArgOperands ( MCInst & Inst , unsigned N ) const { +assert ( N == 1 && "Invalid number of operands!" ) ; +Inst . addOperand ( MCOperand :: createImm ( getRoundingMode ( ) ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/addFenceArgOperands.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/addFenceArgOperands.cpp new file mode 100644 index 0000000000000000000000000000000000000000..49d00e2a6d268ba6e0c27bf10807fbc11e780b1d --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/addFenceArgOperands.cpp @@ -0,0 +1,6 @@ +void addFenceArgOperands ( MCInst & Inst , unsigned N ) const { +assert ( N == 1 && "Invalid number of operands!" ) ; +const MCConstantExpr * CE = cast < MCConstantExpr > ( getImm ( ) ) ; +unsigned RegNum = getCondCode ( ) == PULPCC :: AL ? 0 : PULP :: CPSR ; +Inst . addOperand ( MCOperand :: createReg ( RegNum ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/addImmOperands.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/addImmOperands.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8eba21454fa5e4a4bfc9ff898d4e04daf6f0ea8b --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/addImmOperands.cpp @@ -0,0 +1,4 @@ +void addImmOperands ( MCInst & Inst , unsigned N ) const { +assert ( N == 1 && "Invalid number of operands!" ) ; +addExpr ( Inst , getImm ( ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/addRegOperands.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/addRegOperands.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b214ebb9cbbf9f71b9975893c8d9359e39b9d067 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/addRegOperands.cpp @@ -0,0 +1,4 @@ +void addRegOperands ( MCInst & Inst , unsigned N ) const { +assert ( N == 1 && "Invalid number of operands!" ) ; +Inst . addOperand ( MCOperand :: createReg ( getReg ( ) ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/addVTypeIOperands.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/addVTypeIOperands.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e3348483b699c85655a59ab63bb64559976801bd --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/addVTypeIOperands.cpp @@ -0,0 +1,4 @@ +void addVTypeIOperands ( MCInst & Inst , unsigned N ) const { +assert ( N == 1 && "Invalid number of operands!" ) ; +Inst . addOperand ( MCOperand :: createImm ( getVType ( ) ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/classifySymbolRef.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/classifySymbolRef.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e244a5b2712defef72cfb2824676727587990875 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/classifySymbolRef.cpp @@ -0,0 +1,20 @@ +bool PULPAsmParser :: classifySymbolRef ( const MCExpr * Expr , MCExpr :: VariantKind & Kind , ) { +Addend = 0 ; +if ( const PULPMCExpr * AE = dyn_cast < PULPMCExpr > ( Expr ) ) { +ELFRefKind = AE -> getKind ( ) ; +Expr = AE -> getSubExpr ( ) ; +} +if ( SE ) { +return true ; +MCValue Res ; +bool Relocatable = Expr -> evaluateAsRelocatable ( Res , nullptr , nullptr ) ; +if ( ! Relocatable ) { +return false ; +} +if ( ! Res . getSymA ( ) ) { +return false ; +if ( Res . getSymB ( ) ) { +return false ; +Addend = Res . getConstant ( ) ; +return ELFRefKind == PULPMCExpr :: VK_INVALID || DarwinRefKind == MCSymbolRefExpr :: VK_PULP_None ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/convertFPR64ToFPR16.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/convertFPR64ToFPR16.cpp new file mode 100644 index 0000000000000000000000000000000000000000..de07b0027863462223117d61cf91acd3c8710f4b --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/convertFPR64ToFPR16.cpp @@ -0,0 +1,4 @@ +static MCRegister convertFPR64ToFPR16 ( MCRegister Reg ) { +assert ( Reg >= PULP :: F0_D && Reg <= PULP :: F31_D && "Invalid register" ) ; +return Reg - PULP :: F0_D + PULP :: F0_H ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/convertFPR64ToFPR32.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/convertFPR64ToFPR32.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cdf4d6c805f30c1595b6aff7dd393aa6829b9d60 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/convertFPR64ToFPR32.cpp @@ -0,0 +1,4 @@ +static MCRegister convertFPR64ToFPR32 ( MCRegister Reg ) { +assert ( Reg >= PULP :: F0_D && Reg <= PULP :: F31_D && "Invalid register" ) ; +return Reg - PULP :: F0_D + PULP :: F0_F ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/createImm.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/createImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..976b15261950ac9a50b49df0c9680ca328d17ee6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/createImm.cpp @@ -0,0 +1,8 @@ +static std :: unique_ptr < PULPOperand > createImm ( const MCExpr * Val , SMLoc S , SMLoc E , bool IsRV64 ) { +auto Op = std :: make_unique < PULPOperand > ( KindTy :: Immediate ) ; +Op -> Imm . Val = Val ; +Op -> StartLoc = S ; +Op -> EndLoc = E ; +Op -> IsRV64 = IsRV64 ; +return Op ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/createReg.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/createReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b219ba307bd75c80c094aa7b5b732860b42228e3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/createReg.cpp @@ -0,0 +1,8 @@ +static std :: unique_ptr < PULPOperand > createReg ( unsigned RegNo , SMLoc S , SMLoc E , bool IsRV64 ) { +auto Op = std :: make_unique < PULPOperand > ( KindTy :: Register ) ; +Op -> Reg . RegNum = RegNo ; +Op -> StartLoc = S ; +Op -> EndLoc = E ; +Op -> IsRV64 = IsRV64 ; +return Op ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/createSysReg.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/createSysReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9e8b156b98236403de05bd35cca86bbccf829494 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/createSysReg.cpp @@ -0,0 +1,10 @@ +static std :: unique_ptr < PULPOperand > createSysReg ( StringRef Str , SMLoc S , unsigned Encoding , bool IsRV64 ) { +auto Op = std :: make_unique < PULPOperand > ( KindTy :: SystemRegister ) ; +Op -> SysReg . Data = Str . data ( ) ; +Op -> SysReg . Length = Str . size ( ) ; +Op -> SysReg . Encoding = Encoding ; +Op -> StartLoc = S ; +Op -> EndLoc = S ; +Op -> IsRV64 = IsRV64 ; +return Op ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/createToken.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/createToken.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7c38f06a20440dd2ef2207cc7c96022563bf8034 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/createToken.cpp @@ -0,0 +1,8 @@ +static std :: unique_ptr < PULPOperand > createToken ( StringRef Str , SMLoc S , bool IsRV64 ) { +auto Op = std :: make_unique < PULPOperand > ( KindTy :: Token ) ; +Op -> Tok = Str ; +Op -> StartLoc = S ; +Op -> EndLoc = S ; +Op -> IsRV64 = IsRV64 ; +return Op ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/createVType.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/createVType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9e942ed5ab1e4c00c2398290a1abebb2ce3f9bd8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/createVType.cpp @@ -0,0 +1,7 @@ +static std :: unique_ptr < PULPOperand > createVType ( unsigned VTypeI , SMLoc S , bool IsRV64 ) { +auto Op = std :: make_unique < PULPOperand > ( KindTy :: VType ) ; +Op -> VType . Val = VTypeI ; +Op -> StartLoc = S ; +Op -> IsRV64 = IsRV64 ; +return Op ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/defaultMaskRegOp.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/defaultMaskRegOp.cpp new file mode 100644 index 0000000000000000000000000000000000000000..54f05808fb373ef8a61db7190295a9862a26dd5f --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/defaultMaskRegOp.cpp @@ -0,0 +1,3 @@ +std :: unique_ptr < PULPOperand > PULPAsmParser :: defaultMaskRegOp ( ) const { +return PULPOperand :: createImm ( this , 0 , SMLoc ( ) , PULPOperand :: ImmTyDLC ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/emitToStreamer.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/emitToStreamer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d44c8b9131f9ffd3298a9d7f438206b654c3b0db --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/emitToStreamer.cpp @@ -0,0 +1,9 @@ +void PULPAsmParser :: emitToStreamer ( MCStreamer & S , const MCInst & Inst ) { +MCInst CInst ; +bool Res = false ; +Res = compressInst ( CInst , Inst , getSTI ( ) , S . getContext ( ) ) ; +if ( Res ) { +PULPNumInstrsCompressed = PULPNumInstrsCompressed + 1 ; +} +S . emitInstruction ( ( Res ? CInst : Inst ) , getSTI ( ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/evaluateConstantImm.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/evaluateConstantImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ae5d6c9e2aa26d5ddff273149c1e516cb22b5d78 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/evaluateConstantImm.cpp @@ -0,0 +1,12 @@ +static bool evaluateConstantImm ( const MCExpr * Expr , int64_t & Imm , PULPMCExpr :: VariantKind & VK ) const { +if ( auto * RE = dyn_cast < PULPMCExpr > ( Expr ) ) { +VK = RE -> getKind ( ) ; +return RE -> evaluateAsConstant ( Imm ) ; +} +if ( auto CE = dyn_cast < MCConstantExpr > ( Expr ) ) { +VK = PULPMCExpr :: VK_PULP_None ; +Imm = CE -> getValue ( ) ; +return true ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/generateImmOutOfRangeError.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/generateImmOutOfRangeError.cpp new file mode 100644 index 0000000000000000000000000000000000000000..feb182cac8d263fbcaa7f4192ee9899553b13ef3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/generateImmOutOfRangeError.cpp @@ -0,0 +1,4 @@ +bool PULPAsmParser :: generateImmOutOfRangeError ( OperandVector & Operands , uint64_t ErrorInfo , int64_t Lower , int64_t Upper , Twine Msg = "immediate must be an integer in the range" ) { +SMLoc ErrorLoc = ( ( PULPOperand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; +return Error ( ErrorLoc , Msg + " [" + Twine ( Lower ) + ", " + Twine ( Upper ) + "]" ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/getEndLoc.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/getEndLoc.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e37ce2784f719036de35e1f8d8504cae1121c2bc --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/getEndLoc.cpp @@ -0,0 +1,3 @@ +SMLoc getEndLoc ( ) const override { +return EndLoc ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/getFeatureBits.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/getFeatureBits.cpp new file mode 100644 index 0000000000000000000000000000000000000000..080034f18946182156ba430e043bdb8f9e5689a8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/getFeatureBits.cpp @@ -0,0 +1,3 @@ +bool getFeatureBits ( uint64_t Feature ) { +return getSTI ( ) . getFeatureBits ( ) [ Feature ] ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/getImm.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/getImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a295b3267dd5db0827725099e6a0db869691db64 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/getImm.cpp @@ -0,0 +1,4 @@ +const MCExpr * getImm ( ) const { +assert ( Kind == KindTy :: Immediate && "Invalid type access!" ) ; +return Imm . Val ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/getLoc.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/getLoc.cpp new file mode 100644 index 0000000000000000000000000000000000000000..35c966acc0c7ad3f7a0e321c17de19bd2ea70c74 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/getLoc.cpp @@ -0,0 +1,3 @@ +SMLoc getLoc ( ) const { +return getParser ( ) . getTok ( ) . getLoc ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/getReg.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/getReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..462f8d464a8e61f2fabbd74202b7d383d8eb9362 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/getReg.cpp @@ -0,0 +1,4 @@ +unsigned getReg ( ) const override { +assert ( Kind == KindTy :: Register && "Invalid type access!" ) ; +return Reg . RegNum . id ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/getRoundingMode.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/getRoundingMode.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b48b464a4825c33dc44a8279f74692c8de7cf7e9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/getRoundingMode.cpp @@ -0,0 +1,3 @@ +PULPFPRndMode :: RoundingMode getRoundingMode ( ) const { +return ( MI . getDesc ( ) . TSFlags >> PULPII :: AddrModePos ) & PULPII :: AddrModeMask ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/getStartLoc.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/getStartLoc.cpp new file mode 100644 index 0000000000000000000000000000000000000000..07cb9bb6e768b7938b667280b2a7b15561f5e6a2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/getStartLoc.cpp @@ -0,0 +1,3 @@ +SMLoc getStartLoc ( ) const override { +return StartLoc ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/getSysReg.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/getSysReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a1ebf9426b9608f4137ea7501f3b08bfab0d3808 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/getSysReg.cpp @@ -0,0 +1,4 @@ +StringRef getSysReg ( ) const { +assert ( Kind == KindTy :: SystemRegister && "Invalid type access!" ) ; +return StringRef ( SysReg . Data , SysReg . Length ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/getTargetStreamer.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/getTargetStreamer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4d3e152cef9399d3298689025b6df27239beff5a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/getTargetStreamer.cpp @@ -0,0 +1,4 @@ +PULPTargetStreamer & getTargetStreamer ( ) { +MCTargetStreamer & TS = * getParser ( ) . getStreamer ( ) . getTargetStreamer ( ) ; +return static_cast < PULPTargetStreamer & > ( TS ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/getToken.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/getToken.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ac25596a2291a838d72813f271e931ccf4073a7d --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/getToken.cpp @@ -0,0 +1,4 @@ +StringRef getToken ( ) const { +assert ( Kind == KindTy :: Token && "Invalid type access!" ) ; +return Tok ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/getVType.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/getVType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f576808a24bb8b7dbf54d64605d91a3963ced115 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/getVType.cpp @@ -0,0 +1,4 @@ +unsigned getVType ( ) const { +assert ( Kind == KindTy :: VType && "Invalid type access!" ) ; +return VType . Val ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isBareSimmNLsb0.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isBareSimmNLsb0.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c9c55d391d00f0ddff67dcdc715080e2155ea5fb --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isBareSimmNLsb0.cpp @@ -0,0 +1,13 @@ +template < int N > bool isBareSimmNLsb0 ( ) const { +if ( ! isImm ( ) ) { +return false ; +} +PULPMCExpr :: VariantKind VK = PULPMCExpr :: VK_PULP_None ; +int64_t Imm ; +bool IsValid ; +IsValid = isShiftedInt < N - 1 , 1 > ( Imm ) ; +} +IsValid = PULPAsmParser :: classifySymbolRef ( getImm ( ) , VK ) ; +} +return IsValid && VK == PULPMCExpr :: VK_PULP_None ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isBareSymbol.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isBareSymbol.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4b01aa67442a80c804df1727867f68683f36a63d --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isBareSymbol.cpp @@ -0,0 +1,14 @@ +bool isBareSymbol ( ) const { +int64_t Imm ; +PULPMCExpr :: VariantKind VK = PULPMCExpr :: VK_PULP_None ; +if ( ! isImm ( ) ) { +return false ; +} +if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return false ; +} +if ( ! evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return PULPAsmParser :: classifySymbolRef ( getImm ( ) , VK ) && VK == PULPMCExpr :: VK_PULP_None ; +} +return PULPAsmParser :: classifySymbolRef ( getImm ( ) , VK ) && VK == PULPMCExpr :: VK_PULP_None ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isCLUIImm.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isCLUIImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7a758bfbbdcd7dbf64f25b3137cb6801e41d1427 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isCLUIImm.cpp @@ -0,0 +1,11 @@ +bool isCLUIImm ( ) const { +if ( ! isImm ( ) ) { +return false ; +} +int64_t Imm ; +PULPMCExpr :: VariantKind VK = PULPMCExpr :: VK_PULP_None ; +if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return ( Imm != 0 ) && ( isUInt < 5 > ( Imm ) || ( Imm >= 0xfffe0 && Imm <= 0xfffff ) ) && VK == PULPMCExpr :: VK_PULP_None ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isCSRSystemRegister.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isCSRSystemRegister.cpp new file mode 100644 index 0000000000000000000000000000000000000000..79a474c7b17dcd11436567b0a61bfa51e62dc75f --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isCSRSystemRegister.cpp @@ -0,0 +1,3 @@ +bool isCSRSystemRegister ( ) const { +return Kind == KindTy :: SystemRegister ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isCallSymbol.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isCallSymbol.cpp new file mode 100644 index 0000000000000000000000000000000000000000..596437cc6a2aeb214d2d0b66113a3a24c82281ec --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isCallSymbol.cpp @@ -0,0 +1,11 @@ +bool isCallSymbol ( ) const { +int64_t Imm ; +PULPMCExpr :: VariantKind VK = PULPMCExpr :: VK_PULP_None ; +if ( ! isImm ( ) ) { +return false ; +} +if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return false ; +} +return PULPAsmParser :: classifySymbolRef ( getImm ( ) , VK ) && ( VK == PULPMCExpr :: VK_PULP_CALL || VK == PULPMCExpr :: VK_PULP_CALL_PLT ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isFRMArg.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isFRMArg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..30217c2871ef7359224eef4da11f3facd547fd50 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isFRMArg.cpp @@ -0,0 +1,10 @@ +bool isFRMArg ( ) const { +if ( ! isImm ( ) ) { +return false ; +} +return ( ( Value & ~ 0xffff ) == 0xffff0000 ) ; +return isShiftedInt < 7 , 1 > ( getConstantImm ( ) ) ; +return isUInt < 5 > ( CE -> getValue ( ) ) ; +return isUInt < 3 > ( Value ) ; +if ( Val & 0x3 ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isFenceArg.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isFenceArg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9f694d687ac9afb99bfa633df54d5fe9dbb85c4a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isFenceArg.cpp @@ -0,0 +1,10 @@ +bool isFenceArg ( ) const { +if ( ! isImm ( ) ) { +return false ; +} +return ( ( Value & ~ 0xffff ) == 0xffff0000 ) ; +return isShiftedInt < 7 , 1 > ( getConstantImm ( ) ) ; +return isUInt < 5 > ( CE -> getValue ( ) ) ; +return isUInt < 3 > ( Value ) ; +if ( Val & 0x3 ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isGPR.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isGPR.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f851d37242bd59b934086fa87b86ac0fc8286861 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isGPR.cpp @@ -0,0 +1,3 @@ +bool isGPR ( ) const { +return Kind == KindTy :: Register && PULPMCRegisterClasses [ PULP :: GPRRegClassID ] . contains ( Reg . RegNum ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isImm.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..64ea89f602caa02e1bd59a59834d9a28d2bb6af7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isImm.cpp @@ -0,0 +1,3 @@ +bool isImm ( ) const override { +return Kind == KindTy :: Immediate ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isImmXLenLI.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isImmXLenLI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..10b9e9a622e533fb1f68e77bac93fd5368eff199 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isImmXLenLI.cpp @@ -0,0 +1,11 @@ +bool isImmXLenLI ( ) const { +if ( ! isImm ( ) ) { +return false ; +} +int64_t Imm ; +PULPMCExpr :: VariantKind VK = PULPMCExpr :: VK_PULP_None ; +if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return VK == PULPMCExpr::VK_PULP_LO || VK == PULPMCExpr::VK_PULP_PCREL_LO || VK == PULPMCExpr::VK_PULP_None && (isRV64() || (isInt<32>(Imm) || isUInt<32>(Imm))) ; +} +return VK == PULPMCExpr :: VK_PULP_LO || VK == PULPMCExpr :: VK_PULP_PCREL_LO ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isMem.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isMem.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bbe89a41bb139dfc739a67a4bac398d6d354d13e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isMem.cpp @@ -0,0 +1,3 @@ +bool isMem ( ) const override { +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isPseudoJumpSymbol.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isPseudoJumpSymbol.cpp new file mode 100644 index 0000000000000000000000000000000000000000..01e45618be862e8cbbaf0d80ea3b150ec88b4e04 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isPseudoJumpSymbol.cpp @@ -0,0 +1,11 @@ +bool isPseudoJumpSymbol ( ) const { +int64_t Imm ; +PULPMCExpr :: VariantKind VK = PULPMCExpr :: VK_PULP_None ; +if ( ! isImm ( ) ) { +return false ; +} +if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return false ; +} +return PULPAsmParser :: classifySymbolRef ( getImm ( ) , VK ) && VK == PULPMCExpr :: VK_PULP_CALL ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isRV32E.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isRV32E.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5bd24a827bc86d53d1fb7c9bf7815fc699f4250e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isRV32E.cpp @@ -0,0 +1,3 @@ +bool isRV32E ( ) const { +return getSTI ( ) . hasFeature ( PULP :: FeatureRV32E ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isRV64-2.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isRV64-2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3021409c1be9313d9e3c296a554215adb8c06a49 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isRV64-2.cpp @@ -0,0 +1,3 @@ +bool isRV64 ( ) const { +return getSTI ( ) . hasFeature ( PULP :: Feature64Bit ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isRV64.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isRV64.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2b8327f239930562cfd20ff962aeefd2b2c8d911 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isRV64.cpp @@ -0,0 +1,3 @@ +bool isRV64 ( ) const { +return IsRV64 ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isReg.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..574f31b9597b3a47ea097df3635d56d107ec07ae --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isReg.cpp @@ -0,0 +1,3 @@ +bool isReg ( ) const override { +return Kind == KindTy :: Register ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isSImm10Lsb0000NonZero.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isSImm10Lsb0000NonZero.cpp new file mode 100644 index 0000000000000000000000000000000000000000..73836dcd1461c0b830a5da7cf3fd41c591983a96 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isSImm10Lsb0000NonZero.cpp @@ -0,0 +1,11 @@ +bool isSImm10Lsb0000NonZero ( ) const { +if ( ! isImm ( ) ) { +return false ; +} +int64_t Imm ; +PULPMCExpr :: VariantKind VK = PULPMCExpr :: VK_PULP_None ; +if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return ( Imm != 0 ) && isShiftedInt < 6 , 4 > ( Imm ) && VK == PULPMCExpr :: VK_PULP_None ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isSImm12.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isSImm12.cpp new file mode 100644 index 0000000000000000000000000000000000000000..13ff6ad21a713c1c3e3321ec851eaa00db31353b --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isSImm12.cpp @@ -0,0 +1,14 @@ +bool isSImm12 ( ) const { +if ( ! isImm ( ) ) { +return false ; +} +int64_t Imm ; +PULPMCExpr :: VariantKind VK = PULPMCExpr :: VK_PULP_None ; +if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return isInt<12>(Imm) && (VK == PULPMCExpr::VK_PULP_None || VK == PULPMCExpr::VK_PULP_LO || VK == PULPMCExpr::VK_PULP_PCREL_LO || VK == PULPMCExpr::VK_PULP_TPREL_LO) ; +} +if ( ! evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return PULPAsmParser :: classifySymbolRef ( getImm ( ) , VK ) && ( VK == PULPMCExpr :: VK_PULP_LO || VK == PULPMCExpr :: VK_PULP_PCREL_LO || VK == PULPMCExpr :: VK_PULP_TPREL_LO ) ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isSImm12Lsb0.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isSImm12Lsb0.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1d9614d3321d4278d55a8bbddd5c546c134fdac8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isSImm12Lsb0.cpp @@ -0,0 +1,14 @@ +bool isSImm12Lsb0 ( ) const { +if ( ! isImm ( ) ) { +return false ; +} +int64_t Imm ; +PULPMCExpr :: VariantKind VK = PULPMCExpr :: VK_PULP_None ; +if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return isShiftedInt < 11 , 1 > ( Imm ) && VK == PULPMCExpr :: VK_PULP_None ; +} +if ( ! evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return PULPAsmParser :: classifySymbolRef ( getImm ( ) , VK ) && VK == PULPMCExpr :: VK_PULP_None ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isSImm13Lsb0.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isSImm13Lsb0.cpp new file mode 100644 index 0000000000000000000000000000000000000000..00330ab2f534c0e004a6c4599bc0f7315b4a00a3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isSImm13Lsb0.cpp @@ -0,0 +1,14 @@ +bool isSImm13Lsb0 ( ) const { +if ( ! isImm ( ) ) { +return false ; +} +int64_t Imm ; +PULPMCExpr :: VariantKind VK = PULPMCExpr :: VK_PULP_None ; +if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return isShiftedInt < 12 , 1 > ( Imm ) && VK == PULPMCExpr :: VK_PULP_None ; +} +if ( ! evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return PULPAsmParser :: classifySymbolRef ( getImm ( ) , VK ) && VK == PULPMCExpr :: VK_PULP_None ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isSImm21Lsb0JAL.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isSImm21Lsb0JAL.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c15a529cf19f881e5161c1338b77010e3b3874fb --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isSImm21Lsb0JAL.cpp @@ -0,0 +1,14 @@ +bool isSImm21Lsb0JAL ( ) const { +if ( ! isImm ( ) ) { +return false ; +} +int64_t Imm ; +PULPMCExpr :: VariantKind VK = PULPMCExpr :: VK_PULP_None ; +if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return isShiftedInt < 20 , 1 > ( Imm ) && VK == PULPMCExpr :: VK_PULP_None ; +} +if ( ! evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return PULPAsmParser :: classifySymbolRef ( getImm ( ) , VK ) && VK == PULPMCExpr :: VK_PULP_None ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isSImm5.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isSImm5.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ca63301cdc4ffdaa12f8cc8c3e8257d076e4a55c --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isSImm5.cpp @@ -0,0 +1,11 @@ +bool isSImm5 ( ) const { +if ( ! isImm ( ) ) { +return false ; +} +int64_t Imm ; +PULPMCExpr :: VariantKind VK = PULPMCExpr :: VK_PULP_None ; +if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return isInt < 5 > ( Imm ) && VK == PULPMCExpr :: VK_PULP_None ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isSImm5Plus1.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isSImm5Plus1.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f86f9b10bcabf2bca32a9271efe4569bd97b4e03 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isSImm5Plus1.cpp @@ -0,0 +1,11 @@ +bool isSImm5Plus1 ( ) const { +if ( ! isImm ( ) ) { +return false ; +} +int64_t Imm ; +PULPMCExpr :: VariantKind VK = PULPMCExpr :: VK_PULP_None ; +if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return isInt < 5 > ( Imm - 1 ) && VK == PULPMCExpr :: VK_PULP_None ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isSImm6.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isSImm6.cpp new file mode 100644 index 0000000000000000000000000000000000000000..31e126c41eefa203616612b0ac80c7cfb3658712 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isSImm6.cpp @@ -0,0 +1,11 @@ +bool isSImm6 ( ) const { +if ( ! isImm ( ) ) { +return false ; +} +int64_t Imm ; +PULPMCExpr :: VariantKind VK = PULPMCExpr :: VK_PULP_None ; +if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return isInt < 6 > ( Imm ) && VK == PULPMCExpr :: VK_PULP_None ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isSImm6NonZero.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isSImm6NonZero.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5eaa93d23d952fc34608be26400da486963a7759 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isSImm6NonZero.cpp @@ -0,0 +1,11 @@ +bool isSImm6NonZero ( ) const { +if ( ! isImm ( ) ) { +return false ; +} +int64_t Imm ; +PULPMCExpr :: VariantKind VK = PULPMCExpr :: VK_PULP_None ; +if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return isInt<6>(Imm) && (Imm != 0) && VK == PULPMCExpr::VK_PULP_None ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isSImm9Lsb0.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isSImm9Lsb0.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9d33c9cb0cddcd93332589c6bb02ff63280f49af --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isSImm9Lsb0.cpp @@ -0,0 +1,14 @@ +bool isSImm9Lsb0 ( ) const { +if ( ! isImm ( ) ) { +return false ; +} +int64_t Imm ; +PULPMCExpr :: VariantKind VK = PULPMCExpr :: VK_PULP_None ; +if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return isShiftedInt < 8 , 1 > ( Imm ) && VK == PULPMCExpr :: VK_PULP_None ; +} +if ( ! evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return PULPAsmParser :: classifySymbolRef ( getImm ( ) , VK ) && VK == PULPMCExpr :: VK_PULP_None ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isSystemRegister.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isSystemRegister.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d2b5c274c624fa3378b43fcdd1feb3fd91cc3ce4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isSystemRegister.cpp @@ -0,0 +1,3 @@ +bool isSystemRegister ( ) const { +return Kind == KindTy :: SystemRegister ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isTPRelAddSymbol.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isTPRelAddSymbol.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fde582f59d8fdcb9b81c6b8c6528a028709991a0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isTPRelAddSymbol.cpp @@ -0,0 +1,14 @@ +bool isTPRelAddSymbol ( ) const { +int64_t Imm ; +PULPMCExpr :: VariantKind VK = PULPMCExpr :: VK_PULP_None ; +if ( ! isImm ( ) ) { +return false ; +} +if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return false ; +} +if ( ! evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return PULPAsmParser :: classifySymbolRef ( getImm ( ) , VK ) && VK == PULPMCExpr :: VK_PULP_TPREL_ADD ; +} +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isToken.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isToken.cpp new file mode 100644 index 0000000000000000000000000000000000000000..765ad841fd47a89abdd004cc3850313674615334 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isToken.cpp @@ -0,0 +1,3 @@ +bool isToken ( ) const override { +return Kind == KindTy :: Token ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isUImm1.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isUImm1.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a44711ce23d8294ec199934c4cc5d6561d511607 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isUImm1.cpp @@ -0,0 +1,11 @@ +bool isUImm1 ( ) const { +if ( ! isImm ( ) ) { +return false ; +} +int64_t Imm ; +PULPMCExpr :: VariantKind VK = PULPMCExpr :: VK_PULP_None ; +if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return isUInt < 1 > ( Imm ) && VK == PULPMCExpr :: VK_PULP_None ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isUImm10Lsb00NonZero.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isUImm10Lsb00NonZero.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7a6caca2a780f86955dd7a1cf880d16e0d0e2654 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isUImm10Lsb00NonZero.cpp @@ -0,0 +1,11 @@ +bool isUImm10Lsb00NonZero ( ) const { +if ( ! isImm ( ) ) { +return false ; +} +int64_t Imm ; +PULPMCExpr :: VariantKind VK = PULPMCExpr :: VK_PULP_None ; +if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return isShiftedUInt < 8 , 2 > ( Imm ) && ( Imm != 0 ) && VK == PULPMCExpr :: VK_PULP_None ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isUImm12.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isUImm12.cpp new file mode 100644 index 0000000000000000000000000000000000000000..242993d2e42d32a2547c9157a68762eae04184e2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isUImm12.cpp @@ -0,0 +1,14 @@ +bool isUImm12 ( ) const { +if ( ! isImm ( ) ) { +return false ; +} +int64_t Imm ; +PULPMCExpr :: VariantKind VK = PULPMCExpr :: VK_PULP_None ; +if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return isUInt < 12 > ( Imm ) && ( VK == PULPMCExpr :: VK_PULP_None || VK == PULPMCExpr :: VK_PULP_LO || VK == PULPMCExpr :: VK_PULP_PCREL_LO || VK == PULPMCExpr :: VK_PULP_TPREL_LO ) ; +} +if ( ! evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return PULPAsmParser :: classifySymbolRef ( getImm ( ) , VK ) && ( VK == PULPMCExpr :: VK_PULP_LO || VK == PULPMCExpr :: VK_PULP_PCREL_LO || VK == PULPMCExpr :: VK_PULP_TPREL_LO ) ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isUImm12M1.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isUImm12M1.cpp new file mode 100644 index 0000000000000000000000000000000000000000..962a2d77f20cd4885a032118cc6149ca32dd2ef6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isUImm12M1.cpp @@ -0,0 +1,11 @@ +bool isUImm12M1 ( ) const { +if ( ! isImm ( ) ) { +return false ; +} +int64_t Imm ; +PULPMCExpr :: VariantKind VK = PULPMCExpr :: VK_PULP_None ; +if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return isUInt<12>(Imm) && (Imm != 0) && VK == PULPMCExpr::VK_PULP_None ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isUImm13Lsb0.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isUImm13Lsb0.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f50f279f40313cef1226d8779b6f2174856c1251 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isUImm13Lsb0.cpp @@ -0,0 +1,11 @@ +bool isUImm13Lsb0 ( ) const { +if ( ! isImm ( ) ) { +return false ; +} +int64_t Imm ; +PULPMCExpr :: VariantKind VK = PULPMCExpr :: VK_PULP_None ; +if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return isShiftedUInt < 12 , 1 > ( Imm ) && VK == PULPMCExpr :: VK_PULP_None ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isUImm20AUIPC.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isUImm20AUIPC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5c7feab0c583a2ae255eb42320f1669dcb8482a7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isUImm20AUIPC.cpp @@ -0,0 +1,14 @@ +bool isUImm20AUIPC ( ) const { +int64_t Imm ; +PULPMCExpr :: VariantKind VK = PULPMCExpr :: VK_PULP_None ; +if ( ! isImm ( ) ) { +return false ; +} +if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return isUInt<20>(Imm) && (VK == PULPMCExpr::VK_PULP_None || VK == PULPMCExpr::VK_PULP_PCREL_HI || VK == PULPMCExpr::VK_PULP_GOT_HI || VK == PULPMCExpr::VK_PULP_TLS_GOT_HI || VK == PULPMCExpr::VK_PULP_TLS_GD_HI) ; +} +if ( ! evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return PULPAsmParser :: classifySymbolRef ( getImm ( ) , VK ) && ( VK == PULPMCExpr :: VK_PULP_PCREL_HI || VK == PULPMCExpr :: VK_PULP_GOT_HI || VK == PULPMCExpr :: VK_PULP_TLS_GOT_HI || VK == PULPMCExpr :: VK_PULP_TLS_GD_HI ) ; +} +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isUImm20LUI.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isUImm20LUI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..56268c5e34a7c274910dd13ac06930c43935718a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isUImm20LUI.cpp @@ -0,0 +1,14 @@ +bool isUImm20LUI ( ) const { +int64_t Imm ; +PULPMCExpr :: VariantKind VK = PULPMCExpr :: VK_PULP_None ; +if ( ! isImm ( ) ) { +return false ; +} +if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return isUInt < 20 > ( Imm ) && ( VK == PULPMCExpr :: VK_PULP_None || VK == PULPMCExpr :: VK_PULP_HI || VK == PULPMCExpr :: VK_PULP_TPREL_HI ) ; +} +if ( ! evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return PULPAsmParser :: classifySymbolRef ( getImm ( ) , VK ) && ( VK == PULPMCExpr :: VK_PULP_HI || VK == PULPMCExpr :: VK_PULP_TPREL_HI ) ; +} +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isUImm3.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isUImm3.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9e1e77b7fb53b22bc94cbdd783b8330dac688aaa --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isUImm3.cpp @@ -0,0 +1,11 @@ +bool isUImm3 ( ) const { +if ( ! isImm ( ) ) { +return false ; +} +int64_t Imm ; +PULPMCExpr :: VariantKind VK = PULPMCExpr :: VK_PULP_None ; +if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return isUInt < 3 > ( Imm ) && VK == PULPMCExpr :: VK_PULP_None ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isUImm4.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isUImm4.cpp new file mode 100644 index 0000000000000000000000000000000000000000..05cbd883894edcc7466e46e10d59af9bea51dcfe --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isUImm4.cpp @@ -0,0 +1,11 @@ +bool isUImm4 ( ) const { +if ( ! isImm ( ) ) { +return false ; +} +int64_t Imm ; +PULPMCExpr :: VariantKind VK = PULPMCExpr :: VK_PULP_None ; +if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return isUInt < 4 > ( Imm ) && VK == PULPMCExpr :: VK_PULP_None ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isUImm5.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isUImm5.cpp new file mode 100644 index 0000000000000000000000000000000000000000..21e44843070ac30950cbf2b70d6443d6b31af736 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isUImm5.cpp @@ -0,0 +1,11 @@ +bool isUImm5 ( ) const { +if ( ! isImm ( ) ) { +return false ; +} +int64_t Imm ; +PULPMCExpr :: VariantKind VK = PULPMCExpr :: VK_PULP_None ; +if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return isUInt < 5 > ( Imm ) && VK == PULPMCExpr :: VK_PULP_None ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isUImm6.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isUImm6.cpp new file mode 100644 index 0000000000000000000000000000000000000000..24fa394380f9bdae7f73c0a8afcb305a19e313ff --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isUImm6.cpp @@ -0,0 +1,11 @@ +bool isUImm6 ( ) const { +if ( ! isImm ( ) ) { +return false ; +} +int64_t Imm ; +PULPMCExpr :: VariantKind VK = PULPMCExpr :: VK_PULP_None ; +if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return isUInt < 6 > ( Imm ) && VK == PULPMCExpr :: VK_PULP_None ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isUImm6Lsb0.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isUImm6Lsb0.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f7ff5e6f3ae9a5cae2812cb91ffd1b3ce63fc3f2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isUImm6Lsb0.cpp @@ -0,0 +1,14 @@ +bool isUImm6Lsb0 ( ) const { +if ( ! isImm ( ) ) { +return false ; +} +int64_t Imm ; +PULPMCExpr :: VariantKind VK = PULPMCExpr :: VK_PULP_None ; +if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return isShiftedUInt < 5 , 1 > ( Imm ) && VK == PULPMCExpr :: VK_PULP_None ; +} +if ( ! evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return PULPAsmParser :: classifySymbolRef ( getImm ( ) , VK ) && VK == PULPMCExpr :: VK_PULP_None ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isUImm7Lsb00.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isUImm7Lsb00.cpp new file mode 100644 index 0000000000000000000000000000000000000000..234e70b993399b34e74f3118acb283b3dd585367 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isUImm7Lsb00.cpp @@ -0,0 +1,11 @@ +bool isUImm7Lsb00 ( ) const { +if ( ! isImm ( ) ) { +return false ; +} +int64_t Imm ; +PULPMCExpr :: VariantKind VK = PULPMCExpr :: VK_PULP_None ; +if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return isShiftedUInt < 5 , 2 > ( Imm ) && VK == PULPMCExpr :: VK_PULP_None ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isUImm8Lsb00.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isUImm8Lsb00.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bc8a864719e3081c55ac25b1827081e15afbce89 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isUImm8Lsb00.cpp @@ -0,0 +1,11 @@ +bool isUImm8Lsb00 ( ) const { +if ( ! isImm ( ) ) { +return false ; +} +int64_t Imm ; +PULPMCExpr :: VariantKind VK = PULPMCExpr :: VK_PULP_None ; +if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return isShiftedUInt < 6 , 2 > ( Imm ) && VK == PULPMCExpr :: VK_PULP_None ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isUImm8Lsb000.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isUImm8Lsb000.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3edbe1fb000634889c5a86ef314510a5932416b2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isUImm8Lsb000.cpp @@ -0,0 +1,11 @@ +bool isUImm8Lsb000 ( ) const { +if ( ! isImm ( ) ) { +return false ; +} +int64_t Imm ; +PULPMCExpr :: VariantKind VK = PULPMCExpr :: VK_PULP_None ; +if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return isShiftedUInt < 5 , 3 > ( Imm ) && VK == PULPMCExpr :: VK_PULP_None ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isUImm9Lsb000.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isUImm9Lsb000.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f4b30a84b0491361f910dbb1e1775b061b5341ed --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isUImm9Lsb000.cpp @@ -0,0 +1,11 @@ +bool isUImm9Lsb000 ( ) const { +if ( ! isImm ( ) ) { +return false ; +} +int64_t Imm ; +PULPMCExpr :: VariantKind VK = PULPMCExpr :: VK_PULP_None ; +if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return isShiftedUInt < 6 , 3 > ( Imm ) && VK == PULPMCExpr :: VK_PULP_None ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isUImmLog2XLen.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isUImmLog2XLen.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0ef71938c542f8f9cbd5c7bdf26b9259ef32218f --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isUImmLog2XLen.cpp @@ -0,0 +1,11 @@ +bool isUImmLog2XLen ( ) const { +if ( ! isImm ( ) ) { +return false ; +} +int64_t Imm ; +PULPMCExpr :: VariantKind VK = PULPMCExpr :: VK_PULP_None ; +if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return VK == PULPMCExpr :: VK_PULP_None && ( ( isRV64 ( ) && isUInt < 6 > ( Imm ) ) || isUInt < 5 > ( Imm ) ) ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isUImmLog2XLenHalf.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isUImmLog2XLenHalf.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f0ccdbdf6e8a7610a8465bbe19873119e728743d --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isUImmLog2XLenHalf.cpp @@ -0,0 +1,11 @@ +bool isUImmLog2XLenHalf ( ) const { +if ( ! isImm ( ) ) { +return false ; +} +int64_t Imm ; +PULPMCExpr :: VariantKind VK = PULPMCExpr :: VK_PULP_None ; +if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return VK == PULPMCExpr :: VK_PULP_None && ( ( isRV64 ( ) && isUInt < 5 > ( Imm ) ) || isUInt < 4 > ( Imm ) ) ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isUImmLog2XLenNonZero.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isUImmLog2XLenNonZero.cpp new file mode 100644 index 0000000000000000000000000000000000000000..898311b34db8a957451340d173fc709b2b0c2f48 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isUImmLog2XLenNonZero.cpp @@ -0,0 +1,11 @@ +bool isUImmLog2XLenNonZero ( ) const { +if ( ! isImm ( ) ) { +return false ; +} +int64_t Imm ; +PULPMCExpr :: VariantKind VK = PULPMCExpr :: VK_PULP_None ; +if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return VK == PULPMCExpr :: VK_PULP_None && Imm && ( ( isRV64 ( ) && isUInt < 6 > ( Imm ) ) || isUInt < 5 > ( Imm ) ) ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isV0Reg.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isV0Reg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..821a317bf574e6abc52a8d22b258241264ab83bb --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isV0Reg.cpp @@ -0,0 +1,3 @@ +bool isV0Reg ( ) const override { +return Kind == KindTy :: Register && Reg . RegNum == PULP :: V0 ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isVType.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isVType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..858133aed67c3eb7ce07c8f10dc3ca4fb5309a37 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isVType.cpp @@ -0,0 +1,3 @@ +bool isVType ( ) const { +return Kind == KindTy :: VType ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isVTypeI.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isVTypeI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2514871342beee8b97897aa604e92fab3063408a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/isVTypeI.cpp @@ -0,0 +1,3 @@ +bool isVTypeI ( ) const { +return Kind == KindTy :: VType ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/matchRegisterNameHelper.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/matchRegisterNameHelper.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8ba50723bd06bd8fd34a52d61dff3d53ca63c9f5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/matchRegisterNameHelper.cpp @@ -0,0 +1,7 @@ +static bool matchRegisterNameHelper ( bool IsRV32E , MCRegister & RegNo , StringRef Name ) { +RegNo = MatchRegisterName ( Name ) ; +if ( RegNo == PULP :: NoRegister ) { +RegNo = MatchRegisterAltName ( Name ) ; +} +return RegNo == PULP :: NoRegister ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/parseAtomicMemOp.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/parseAtomicMemOp.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bcb34753eed032c47105536c04aac6f753d293fb --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/parseAtomicMemOp.cpp @@ -0,0 +1,19 @@ +OperandMatchResultTy PULPAsmParser :: parseAtomicMemOp ( OperandVector & Operands ) { +if ( getLexer ( ) . isNot ( AsmToken :: LParen ) ) { +Error ( getLoc ( ) , "expected '('" ) ; +return MatchOperand_ParseFail ; +} +getParser ( ) . Lex ( ) ; +Operands . push_back ( PULPOperand :: createToken ( "(" , getLoc ( ) ) ) ; +if ( parseRegister ( Operands ) != MatchOperand_Success ) { +Error ( getLoc ( ) , "expected register" ) ; +return MatchOperand_ParseFail ; +} +if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { +Error ( getLoc ( ) , "expected ')'" ) ; +return MatchOperand_ParseFail ; +} +getParser ( ) . Lex ( ) ; +Operands . push_back ( PULPOperand :: createToken ( ")" , getLoc ( ) ) ) ; +return MatchOperand_Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/parseBareSymbol.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/parseBareSymbol.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a41273a85527866f77e296b2c066caef801731c3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/parseBareSymbol.cpp @@ -0,0 +1,56 @@ +OperandMatchResultTy PULPAsmParser :: parseBareSymbol ( OperandVector & Operands ) { +SMLoc S = getLoc ( ) ; +SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) - 1 ) ; +const MCExpr * Res ; +if ( getLexer ( ) . getKind ( ) != AsmToken :: Identifier ) { +return MatchOperand_NoMatch ; +} +StringRef Identifier ; +AsmToken Tok = getLexer ( ) . getTok ( ) ; +if ( getParser ( ) . parseIdentifier ( Identifier ) ) { +return MatchOperand_ParseFail ; +} +MCExpr :: VariantKind Kind = PULPMCExpr :: VK_PULP_None ; +if ( Identifier . consume_back ( "@plt" ) ) { +Error ( getLoc ( ) , "'@plt' operand not valid for instruction" ) ; +return MatchOperand_ParseFail ; +} +MCSymbol * Sym = getContext ( ) . getOrCreateSymbol ( Identifier ) ; +if ( Sym -> isVariable ( ) ) { +const MCExpr * V = Sym -> getVariableValue ( false ) ; +if ( ! isa < MCSymbolRefExpr > ( V ) ) { +getLexer ( ) . UnLex ( Tok ) ; +return MatchOperand_NoMatch ; +} +Res = V ; +} +if ( ! Sym -> isVariable ( ) ) { +} +MCBinaryExpr :: Opcode Opcode ; +if ( getLexer ( ) . getKind ( ) == AsmToken :: Plus ) { +Opcode = MCBinaryExpr :: Add ; +getLexer ( ) . Lex ( ) ; +const MCExpr * Expr ; +if ( getParser ( ) . parseExpression ( Expr ) ) { +return MatchOperand_ParseFail ; +} +Res = MCBinaryExpr :: create ( Opcode , Res , Expr , getContext ( ) ) ; +Operands . push_back ( PULPOperand :: createImm ( Res , S , E , isRV64 ( ) ) ) ; +return MatchOperand_Success ; +} +if ( getLexer ( ) . getKind ( ) == AsmToken :: Minus ) { +Opcode = MCBinaryExpr :: Sub ; +getLexer ( ) . Lex ( ) ; +const MCExpr * Expr ; +if ( getParser ( ) . parseExpression ( Expr ) ) { +return MatchOperand_ParseFail ; +} +Res = MCBinaryExpr :: create ( Opcode , Res , Expr , getContext ( ) ) ; +Operands . push_back ( PULPOperand :: createImm ( Res , S , E , isRV64 ( ) ) ) ; +return MatchOperand_Success ; +} +if ( Kind != PULPMCExpr :: VK_PULP_Invalid ) { +Res = PULPMCExpr :: create ( Res , Kind , getContext ( ) ) ; +Operands . push_back ( PULPOperand :: createImm ( Res , S , E , isRV64 ( ) ) ) ; +return MatchOperand_Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/parseCSRSyestemRegister.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/parseCSRSyestemRegister.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a2dab26acc75f3bd26d9e3b6b4782554f23c93cc --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/parseCSRSyestemRegister.cpp @@ -0,0 +1,5 @@ +OperandMatchResultTy PULPAsmParser :: parseCSRSystemRegister ( OperandVector & Operands , bool AllowParens ) { +SMLoc S = getLoc ( ) ; +SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) - 1 ) ; +return MatchOperand_NoMatch ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/parseCallSymbol.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/parseCallSymbol.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c8d89dc42f1d9596ba80e80ccd3342554a347937 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/parseCallSymbol.cpp @@ -0,0 +1,46 @@ +OperandMatchResultTy PULPAsmParser :: parseCallSymbol ( OperandVector & Operands ) { +SMLoc S = getLoc ( ) ; +SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) - 1 ) ; +const MCExpr * Res ; +if ( getLexer ( ) . getKind ( ) != AsmToken :: Identifier ) { +return MatchOperand_NoMatch ; +} +StringRef Identifier ; +AsmToken Tok = getLexer ( ) . getTok ( ) ; +if ( getParser ( ) . parseIdentifier ( Identifier ) ) { +return MatchOperand_ParseFail ; +} +MCExpr :: VariantKind Kind = PULPMCExpr :: VK_PULP_None ; +if ( Identifier . consume_back ( "@plt" ) ) { +Kind = PULPMCExpr :: VK_CALL_PLT ; +} +MCSymbol * Sym = getContext ( ) . getOrCreateSymbol ( Identifier ) ; +if ( Sym -> isVariable ( ) ) { +const MCExpr * V = Sym -> getVariableValue ( false ) ; +if ( ! isa < MCSymbolRefExpr > ( V ) ) { +getLexer ( ) . UnLex ( Tok ) ; +return MatchOperand_ParseFail ; +if ( ! Sym -> isVariable ( ) ) { +MCBinaryExpr :: Opcode Opcode ; +if ( getLexer ( ) . getKind ( ) == AsmToken :: Plus ) { +Opcode = MCBinaryExpr :: Add ; +getLexer ( ) . Lex ( ) ; +const MCExpr * Expr ; +if ( getParser ( ) . parseExpression ( Expr ) ) { +return MatchOperand_ParseFail ; +Res = MCBinaryExpr :: create ( Opcode , Res , Expr , getContext ( ) ) ; +Operands . push_back ( PULPOperand :: createImm ( Res , S , E , isRV64 ( ) ) ) ; +return MatchOperand_Success ; +if ( getLexer ( ) . getKind ( ) == AsmToken :: Minus ) { +Opcode = MCBinaryExpr :: Sub ; +getLexer ( ) . Lex ( ) ; +const MCExpr * Expr ; +if ( getParser ( ) . parseExpression ( Expr ) ) { +return MatchOperand_ParseFail ; +Res = MCBinaryExpr :: create ( Opcode , Res , Expr , getContext ( ) ) ; +Operands . push_back ( PULPOperand :: createImm ( Res , S , E , isRV64 ( ) ) ) ; +return MatchOperand_Success ; +if ( Kind != PULPMCExpr :: VK_PULP_None ) { +Operands . push_back ( PULPOperand :: createImm ( Res , S , E , isRV64 ( ) ) ) ; +return MatchOperand_Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/parseImmediate.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/parseImmediate.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a4ba12881a11d96e7997a9f63836624d1d2291fa --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/parseImmediate.cpp @@ -0,0 +1,72 @@ +OperandMatchResultTy PULPAsmParser :: parseImmediate ( OperandVector & Operands ) { +SMLoc S = getLoc ( ) ; +SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) - 1 ) ; +const MCExpr * Res ; +if ( getLexer ( ) . getKind ( ) == AsmToken :: LParen ) { +if ( getParser ( ) . parseExpression ( Res ) ) { +return MatchOperand_ParseFail ; +} +Operands . push_back ( PULPOperand :: createImm ( Res , S , E , isRV64 ( ) ) ) ; +return MatchOperand_Success ; +} +if ( getLexer ( ) . getKind ( ) == AsmToken :: Minus ) { +if ( getParser ( ) . parseExpression ( Res ) ) { +return MatchOperand_ParseFail ; +} +Operands . push_back ( PULPOperand :: createImm ( Res , S , E , isRV64 ( ) ) ) ; +return MatchOperand_Success ; +} +if ( getLexer ( ) . getKind ( ) == AsmToken :: Plus ) { +if ( getParser ( ) . parseExpression ( Res ) ) { +return MatchOperand_ParseFail ; +} +Operands . push_back ( PULPOperand :: createImm ( Res , S , E , isRV64 ( ) ) ) ; +return MatchOperand_Success ; +} +if ( getLexer ( ) . getKind ( ) == AsmToken :: Integer ) { +if ( getParser ( ) . parseExpression ( Res ) ) { +return MatchOperand_ParseFail ; +} +Operands . push_back ( PULPOperand :: createImm ( Res , S , E , isRV64 ( ) ) ) ; +return MatchOperand_Success ; +} +if ( getLexer ( ) . getKind ( ) == AsmToken :: String ) { +if ( getParser ( ) . parseExpression ( Res ) ) { +return MatchOperand_ParseFail ; +} +Operands . push_back ( PULPOperand :: createImm ( Res , S , E , isRV64 ( ) ) ) ; +return MatchOperand_Success ; +} +if ( getLexer ( ) . getKind ( ) == AsmToken :: Identifier ) { +if ( getParser ( ) . parseExpression ( Res ) ) { +return MatchOperand_ParseFail ; +} +Operands . push_back ( PULPOperand :: createImm ( Res , S , E , isRV64 ( ) ) ) ; +return MatchOperand_Success ; +} +if ( getLexer ( ) . getKind ( ) == AsmToken :: Dot ) { +if ( getParser ( ) . parseExpression ( Res ) ) { +return MatchOperand_ParseFail ; +} +Operands . push_back ( PULPOperand :: createImm ( Res , S , E , isRV64 ( ) ) ) ; +return MatchOperand_Success ; +} +if ( getLexer ( ) . getKind ( ) == AsmToken :: Tilde ) { +if ( getParser ( ) . parseExpression ( Res ) ) { +return MatchOperand_ParseFail ; +} +Operands . push_back ( PULPOperand :: createImm ( Res , S , E , isRV64 ( ) ) ) ; +return MatchOperand_Success ; +} +if ( getLexer ( ) . getKind ( ) == AsmToken :: Exclaim ) { +if ( getParser ( ) . parseExpression ( Res ) ) { +return MatchOperand_ParseFail ; +} +Operands . push_back ( PULPOperand :: createImm ( Res , S , E , isRV64 ( ) ) ) ; +return MatchOperand_Success ; +} +if ( getLexer ( ) . getKind ( ) == AsmToken :: Percent ) { +return parseOperandWithModifier ( Operands ) ; +} +return MatchOperand_NoMatch ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/parseJALOffset.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/parseJALOffset.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0e31f93d617272ba25fb3a360115eb8476219598 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/parseJALOffset.cpp @@ -0,0 +1,31 @@ +OperandMatchResultTy PULPAsmParser :: parseJALOffset ( OperandVector & Operands ) { +SMLoc S = getLoc ( ) ; +SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) - 1 ) ; +if ( getLexer ( ) . getKind ( ) != AsmToken :: Identifier ) { +return MatchOperand_NoMatch ; +StringRef Identifier ; +AsmToken Tok = getLexer ( ) . getTok ( ) ; +if ( getParser ( ) . parseIdentifier ( Identifier ) ) { +return MatchOperand_ParseFail ; +if ( Sym -> isVariable ( ) ) { +if ( ! isa < MCSymbolRefExpr > ( V ) ) { +getLexer ( ) . UnLex ( Tok ) ; +return MatchOperand_ParseFail ; +if ( ! Sym -> isVariable ( ) ) { +if ( getLexer ( ) . getKind ( ) == AsmToken :: Plus ) { +getLexer ( ) . Lex ( ) ; +const MCExpr * Expr ; +if ( getParser ( ) . parseExpression ( Expr ) ) { +return MatchOperand_ParseFail ; +Operands . push_back ( PULPOperand :: createImm ( Res , S , E , isRV64 ( ) ) ) ; +return MatchOperand_Success ; +if ( getLexer ( ) . getKind ( ) == AsmToken :: Minus ) { +getLexer ( ) . Lex ( ) ; +const MCExpr * Expr ; +if ( getParser ( ) . parseExpression ( Expr ) ) { +return MatchOperand_ParseFail ; +Operands . push_back ( PULPOperand :: createImm ( Res , S , E , isRV64 ( ) ) ) ; +return MatchOperand_Success ; +Operands . push_back ( PULPOperand :: createImm ( Res , S , E , isRV64 ( ) ) ) ; +return MatchOperand_Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/parseMaskReg.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/parseMaskReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..724cf44c349ad2f6d58c760886cf175ac0ed0145 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/parseMaskReg.cpp @@ -0,0 +1,16 @@ +OperandMatchResultTy PULPAsmParser :: parseMaskReg ( OperandVector & Operands ) { +SMLoc S = getLoc ( ) ; +SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) - 1 ) ; +if ( getLexer ( ) . getKind ( ) != AsmToken :: Identifier ) { +return MatchOperand_NoMatch ; +} +StringRef Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; +MCRegister RegNo ; +matchRegisterNameHelper ( RegNo , Name ) ; +if ( RegNo == PULP :: NoRegister ) { +return MatchOperand_NoMatch ; +} +getLexer ( ) . Lex ( ) ; +Operands . push_back ( PULPOperand :: createReg ( RegNo , S , E ) ) ; +return MatchOperand_Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/parseMemOpBaseReg.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/parseMemOpBaseReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9605e1a3fe5faf374e4ac5c33b31c5ff92ff48b0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/parseMemOpBaseReg.cpp @@ -0,0 +1,19 @@ +OperandMatchResultTy PULPAsmParser :: parseMemOpBaseReg ( OperandVector & Operands ) { +if ( getLexer ( ) . isNot ( AsmToken :: LParen ) ) { +Error ( getLoc ( ) , "expected '('" ) ; +return MatchOperand_ParseFail ; +} +getParser ( ) . Lex ( ) ; +Operands . push_back ( PULPOperand :: createToken ( "(" , getLoc ( ) , isRV64 ( ) ) ) ; +if ( parseRegister ( Operands ) != MatchOperand_Success ) { +Error ( getLoc ( ) , "expected register" ) ; +return MatchOperand_ParseFail ; +} +if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { +Error ( getLoc ( ) , "expected ')'" ) ; +return MatchOperand_ParseFail ; +} +getParser ( ) . Lex ( ) ; +Operands . push_back ( PULPOperand :: createToken ( ")" , getLoc ( ) , isRV64 ( ) ) ) ; +return MatchOperand_Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/parseOperand.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/parseOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ed44f3eb7777559d78790984d7275a79758b70f1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/parseOperand.cpp @@ -0,0 +1,20 @@ +bool PULPAsmParser :: parseOperand ( OperandVector & Operands , StringRef Mnemonic ) { +OperandMatchResultTy Result = MatchOperandParserImpl ( Operands , Mnemonic , true ) ; +if ( Result == MatchOperand_Success ) { +return false ; +} +if ( Result == MatchOperand_ParseFail ) { +return true ; +} +if ( parseRegister ( Operands , true ) == MatchOperand_Success ) { +return false ; +} +if ( parseImmediate ( Operands ) == MatchOperand_Success ) { +if ( getLexer ( ) . is ( AsmToken :: LParen ) ) { +return parseMemOpBaseReg ( Operands ) != MatchOperand_Success ; +} +return false ; +} +Error ( getLoc ( ) , "unknown operand" ) ; +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/parseOperandWithModifier.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/parseOperandWithModifier.cpp new file mode 100644 index 0000000000000000000000000000000000000000..16bb49ab1862dc9bb73651eec385a6df9b74f166 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/parseOperandWithModifier.cpp @@ -0,0 +1,32 @@ +OperandMatchResultTy PULPAsmParser :: parseOperandWithModifier ( OperandVector & Operands ) { +SMLoc S = getLoc ( ) ; +SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) - 1 ) ; +if ( getLexer ( ) . getKind ( ) != AsmToken :: Percent ) { +Error ( getLoc ( ) , "expected '%' for operand modifier" ) ; +return MatchOperand_ParseFail ; +} +getParser ( ) . Lex ( ) ; +if ( getLexer ( ) . getKind ( ) != AsmToken :: Identifier ) { +Error ( getLoc ( ) , "expected valid identifier for operand modifier" ) ; +return MatchOperand_ParseFail ; +} +StringRef Identifier = getParser ( ) . getTok ( ) . getIdentifier ( ) ; +PULPMCExpr :: VariantKind VK = PULPMCExpr :: getVariantKindForName ( Identifier ) ; +if ( VK == PULPMCExpr :: VK_PULP_Invalid ) { +Error ( getLoc ( ) , "unrecognized operand modifier" ) ; +return MatchOperand_ParseFail ; +} +getParser ( ) . Lex ( ) ; +if ( getLexer ( ) . getKind ( ) != AsmToken :: LParen ) { +Error ( getLoc ( ) , "expected '('" ) ; +return MatchOperand_ParseFail ; +} +getParser ( ) . Lex ( ) ; +const MCExpr * SubExpr ; +if ( getParser ( ) . parseParenExpression ( SubExpr , E ) ) { +return MatchOperand_ParseFail ; +} +const MCExpr * ModExpr = PULPMCExpr :: create ( VK , SubExpr , getContext ( ) ) ; +Operands . push_back ( PULPOperand :: createImm ( ModExpr , S , E , isRV64 ( ) ) ) ; +return MatchOperand_Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/parsePseudoJumpSymbol.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/parsePseudoJumpSymbol.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ac24b3f9925f37bf9f679a0af2dccf9b850b417c --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/parsePseudoJumpSymbol.cpp @@ -0,0 +1,43 @@ +OperandMatchResultTy PULPAsmParser :: parsePseudoJumpSymbol ( OperandVector & Operands ) { +SMLoc S = getLoc ( ) ; +SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) - 1 ) ; +const MCExpr * Res ; +if ( getLexer ( ) . getKind ( ) != AsmToken :: Identifier ) { +return MatchOperand_NoMatch ; +StringRef Identifier ; +AsmToken Tok = getLexer ( ) . getTok ( ) ; +if ( getParser ( ) . parseIdentifier ( Identifier ) ) { +Error ( getLoc ( ) , "unknown identifier" ) ; +return MatchOperand_ParseFail ; +} +MCSymbol * Sym = getContext ( ) . getOrCreateSymbol ( Identifier ) ; +if ( Sym -> isVariable ( ) ) { +const MCExpr * V = Sym -> getVariableValue ( false ) ; +if ( ! isa < MCSymbolRefExpr > ( V ) ) { +getLexer ( ) . UnLex ( Tok ) ; +Error ( getLoc ( ) , "unknown symbol" ) ; +return MatchOperand_ParseFail ; +Res = V ; +if ( ! Sym -> isVariable ( ) ) { +if ( getLexer ( ) . getKind ( ) == AsmToken :: Plus ) { +Opcode = MCBinaryExpr :: Add ; +getLexer ( ) . Lex ( ) ; +const MCExpr * Expr ; +if ( getParser ( ) . parseExpression ( Expr ) ) { +Error ( getLoc ( ) , "unknown expression" ) ; +return MatchOperand_ParseFail ; +Operands . push_back ( PULPOperand :: createImm ( Res , S , E , isRV64 ( ) ) ) ; +return MatchOperand_Success ; +if ( getLexer ( ) . getKind ( ) == AsmToken :: Minus ) { +getLexer ( ) . Lex ( ) ; +const MCExpr * Expr ; +if ( getParser ( ) . parseExpression ( Expr ) ) { +Error ( getLoc ( ) , "unknown expression" ) ; +return MatchOperand_ParseFail ; +Res = MCBinaryExpr :: create ( Opcode , Res , Expr , getContext ( ) ) ; +Operands . push_back ( PULPOperand :: createImm ( Res , S , E , isRV64 ( ) ) ) ; +return MatchOperand_Success ; +if ( Kind != PULPMCExpr :: VK_PULP_None ) { +Operands . push_back ( PULPOperand :: createImm ( Res , S , E , isRV64 ( ) ) ) ; +return MatchOperand_Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/parseRegister2.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/parseRegister2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4ec5623c37d081638d31f2e57424114acffd777b --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/parseRegister2.cpp @@ -0,0 +1,12 @@ +OperandMatchResultTy PULPAsmParser :: parseRegister ( OperandVector & Operands , bool AllowParens ) { +getLexer ( ) . Lex ( ) ; +SMLoc S = getLoc ( ) ; +StringRef Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; +unsigned RegNo = MatchRegisterName ( Name ) ; +if ( RegNo == 0 ) { +} +Operands . push_back ( PULPOperand :: createReg ( RegNo , S , E ) ) ; +getLexer ( ) . Lex ( ) ; +Operands . push_back ( PULPOperand :: createReg ( RegNo , S , E ) ) ; +return MatchOperand_Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/parseVTypeI.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/parseVTypeI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5654080a3b187b8272b3c8ed01587e23a17c342d --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/parseVTypeI.cpp @@ -0,0 +1,42 @@ +OperandMatchResultTy PULPAsmParser :: parseVTypeI ( OperandVector & Operands ) { +SMLoc S = getLoc ( ) ; +SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) - 1 ) ; +const MCExpr * Res ; +if ( getLexer ( ) . getKind ( ) != AsmToken :: Identifier ) { +return MatchOperand_NoMatch ; +} +StringRef Identifier ; +AsmToken Tok = getLexer ( ) . getTok ( ) ; +if ( getParser ( ) . parseIdentifier ( Identifier ) ) { +Error ( getLoc ( ) , "unknown identifier" ) ; +return MatchOperand_ParseFail ; +MCSymbol * Sym = getContext ( ) . getOrCreateSymbol ( Identifier ) ; +if ( Sym -> isVariable ( ) ) { +const MCExpr * V = Sym -> getVariableValue ( false ) ; +if ( ! isa < MCSymbolRefExpr > ( V ) ) { +getLexer ( ) . UnLex ( Tok ) ; +Error ( getLoc ( ) , "unknown symbol" ) ; +return MatchOperand_ParseFail ; +Res = V ; +if ( ! Sym -> isVariable ( ) ) { +MCBinaryExpr :: Opcode Opcode ; +if ( getLexer ( ) . getKind ( ) == AsmToken :: Plus ) { +getLexer ( ) . Lex ( ) ; +const MCExpr * Expr ; +if ( getParser ( ) . parseExpression ( Expr ) ) { +Error ( getLoc ( ) , "unknown expression" ) ; +return MatchOperand_ParseFail ; +Operands . push_back ( PULPOperand :: createImm ( Res , S , E , isRV64 ( ) ) ) ; +return MatchOperand_Success ; +if ( getLexer ( ) . getKind ( ) == AsmToken :: Minus ) { +getLexer ( ) . Lex ( ) ; +const MCExpr * Expr ; +if ( getParser ( ) . parseExpression ( Expr ) ) { +Error ( getLoc ( ) , "unknown expression" ) ; +return MatchOperand_ParseFail ; +Operands . push_back ( PULPOperand :: createImm ( Res , S , E , isRV64 ( ) ) ) ; +return MatchOperand_Success ; +if ( Kind != PULPMCExpr :: VK_PULP_None ) { +Operands . push_back ( PULPOperand :: createImm ( Res , S , E , isRV64 ( ) ) ) ; +return MatchOperand_Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/print.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/print.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a5f3c376b1ff726cf240aa6395af8524515c9140 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/print.cpp @@ -0,0 +1,14 @@ +void print ( raw_ostream & OS ) const override { +if ( Kind == KindTy :: Token ) { +} +if ( Kind == KindTy :: Register ) { +} +if ( Kind == KindTy :: Immediate ) { +OS << getImm ( ) ; +} +if ( Kind == KindTy :: SystemRegister ) { +OS << "Register<" << Reg . RegNum << ">" ; +} +if ( Kind == KindTy :: VType ) { +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/setFeatureBits.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/setFeatureBits.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e3842effdce3debb109d5ef4f747e2c8306b202a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/setFeatureBits.cpp @@ -0,0 +1,6 @@ +void setFeatureBits ( uint64_t Feature , StringRef FeatureString ) { +if ( ! ( getSTI ( ) . getFeatureBits ( ) [ Feature ] ) ) { +MCSubtargetInfo & STI = copySTI ( ) ; +setAvailableFeatures ( ComputeAvailableFeatures ( STI . ToggleFeature ( FeatureString ) ) ) ; +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/tryParseRegister.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/tryParseRegister.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1223d542786d6a119f5d0309d611721679d6359e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/tryParseRegister.cpp @@ -0,0 +1,12 @@ +OperandMatchResultTy PULPAsmParser :: tryParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc ) { +const AsmToken & Tok = getParser ( ) . getTok ( ) ; +StartLoc = Tok . getLoc ( ) ; +EndLoc = Tok . getEndLoc ( ) ; +RegNo = 0 ; +StringRef Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; +if ( matchRegisterNameHelper ( isRV32E ( ) , ( MCRegister & ) RegNo , Name ) ) { +return MatchOperand_NoMatch ; +} +getParser ( ) . Lex ( ) ; +return MatchOperand_Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/validateTargetOperandClass.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/validateTargetOperandClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9ada0ba2b2acf61da477c39188e24e688a28af39 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmParser/validateTargetOperandClass.cpp @@ -0,0 +1,26 @@ +unsigned PULPAsmParser :: validateTargetOperandClass ( MCParsedAsmOperand & AsmOp , unsigned Kind ) { +PULPOperand & Op = static_cast < PULPOperand & > ( AsmOp ) ; +if ( ! Op . isReg ( ) ) { +return Match_InvalidOperand ; +} +MCRegister Reg = Op . getReg ( ) ; +if ( PULPMCRegisterClasses [ PULP :: FPR64RegClassID ] . contains ( Reg ) ) { +if ( Kind == MCK_FPR32 ) { +Op . Reg . RegNum = convertFPR64ToFPR32 ( Reg ) ; +return Match_Success ; +} +} +if ( PULPMCRegisterClasses [ PULP :: FPR64CRegClassID ] . contains ( Reg ) ) { +if ( Kind == MCK_FPR32C ) { +Op . Reg . RegNum = convertFPR64ToFPR32 ( Reg ) ; +return Match_Success ; +} +} +if ( PULPMCRegisterClasses [ PULP :: FPR64RegClassID ] . contains ( Reg ) ) { +if ( Kind == MCK_FPR16 ) { +Op . Reg . RegNum = convertFPR64ToFPR16 ( Reg ) ; +return Match_Success ; +} +} +return Match_InvalidOperand ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmPrinter/AsmPrinter.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmPrinter/AsmPrinter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d1cb12f7fdc9eba5c070efc786c654e994c5a8de --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmPrinter/AsmPrinter.cpp @@ -0,0 +1,2 @@ +explicit PULPAsmPrinter ( TargetMachine & TM , std :: unique_ptr < MCStreamer > Streamer ) : AsmPrinter ( TM , std :: move ( Streamer ) ) , STI ( TM . getMCSubtargetInfo ( ) ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmPrinter/EmitToStreamer.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmPrinter/EmitToStreamer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e56a4978050a1b1cae881bc40a41eed68bedc88b --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmPrinter/EmitToStreamer.cpp @@ -0,0 +1,8 @@ +void PULPAsmPrinter :: EmitToStreamer ( MCStreamer & S , const MCInst & Inst ) { +MCInst CInst ; +bool Res = compressInst ( CInst , Inst , * STI , OutStreamer -> getContext ( ) ) ; +if ( Res ) { +PULPNumInstrsCompressed = PULPNumInstrsCompressed + 1 ; +} +AsmPrinter :: EmitToStreamer ( * OutStreamer , Res ? CInst : Inst ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmPrinter/LLVMInitializeAsmPrinter.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmPrinter/LLVMInitializeAsmPrinter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..35de9759dc4e117057bef34a2d8ca4cbe79288c7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmPrinter/LLVMInitializeAsmPrinter.cpp @@ -0,0 +1,4 @@ +extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializePULPAsmPrinter ( ) { +RegisterAsmPrinter < PULPAsmPrinter > X ( getThePULP32Target ( ) ) ; +RegisterAsmPrinter < PULPAsmPrinter > Y ( getThePULP64Target ( ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmPrinter/PrintAsmMemoryOperand.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmPrinter/PrintAsmMemoryOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..60f24b92ca4fd4848f23b0ea98555afb402c5333 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmPrinter/PrintAsmMemoryOperand.cpp @@ -0,0 +1,11 @@ +bool PULPAsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & OS ) { +if ( ! ExtraCode ) { +const MachineOperand & MO = MI -> getOperand ( OpNo ) ; +if ( ! MO . isReg ( ) ) { +return true ; +} +OS << "0(" << PULPInstPrinter :: getRegisterName ( MO . getReg ( ) ) << ")" ; +return false ; +} +return AsmPrinter :: PrintAsmMemoryOperand ( MI , OpNo , ExtraCode , OS ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmPrinter/PrintAsmOperand.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmPrinter/PrintAsmOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..83fcd08b9044ab869795cb3f4c893cc06238cd26 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmPrinter/PrintAsmOperand.cpp @@ -0,0 +1,47 @@ +bool PULPAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & OS ) { +if ( ! AsmPrinter :: PrintAsmOperand ( MI , OpNo , ExtraCode , OS ) ) { +return false ; +} +const MachineOperand & MO = MI -> getOperand ( OpNo ) ; +if ( ExtraCode ) { +if ( ExtraCode [ 0 ] ) { +if ( ExtraCode [ 1 ] != 0 ) { +return true ; +} +if ( ExtraCode [ 0 ] == 'z' ) { +if ( MO . isImm ( ) ) { +if ( MO . getImm ( ) == 0 ) { +OS << PULPInstPrinter :: getRegisterName ( PULP::X0 ) ; +return false ; +} +} +} +if ( ExtraCode [ 0 ] == 'i' ) { +return false ; +if ( ! MO . isReg ( ) ) { +OS << 'i' ; +} +return false ; +} +return true ; +} +} +if ( MO . getType ( ) == MachineOperand :: MO_Immediate ) { +OS << MO . getImm ( ) ; +return false ; +} +if ( MO . getType ( ) == MachineOperand :: MO_Register ) { +OS << PULPInstPrinter :: getRegisterName ( MO . getReg ( ) ) ; +return false ; +} +if ( MO . getType ( ) == MachineOperand :: MO_GlobalAddress ) { +PrintSymbolOperand ( MO , OS ) ; +return false ; +} +if ( MO . getType ( ) == MachineOperand :: MO_BlockAddress ) { +MCSymbol * Sym = GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ; +Sym -> print ( OS , MAI ) ; +return false ; +} +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmPrinter/emitAttributes.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmPrinter/emitAttributes.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6eb8d08d8654c7fdeaa4741f944a832ebfece64a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmPrinter/emitAttributes.cpp @@ -0,0 +1,9 @@ +void PULPAsmPrinter :: emitAttributes ( ) { +PULPTargetStreamer & CTS = static_cast < PULPTargetStreamer & > ( * OutStreamer -> getTargetStreamer ( ) ) ; +const Triple & TT = TM . getTargetTriple ( ) ; +StringRef CPU = TM . getTargetCPU ( ) ; +StringRef FS = TM . getTargetFeatureString ( ) ; +const PULPTargetMachine & CTM = static_cast < const PULPTargetMachine & > ( TM ) ; +const PULPSubtarget STI ( TT , CPU , CPU , FS , "" , CTM ) ; +CTS . emitTargetAttributes ( STI ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmPrinter/emitEndOfAsmFile.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmPrinter/emitEndOfAsmFile.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0e38ed76295f8ad0fd1ca1a100bcfa3c3380a13f --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmPrinter/emitEndOfAsmFile.cpp @@ -0,0 +1,6 @@ +void PULPAsmPrinter :: emitEndOfAsmFile ( Module & M ) { +PULPTargetStreamer & CTS = static_cast < PULPTargetStreamer & > ( * OutStreamer -> getTargetStreamer ( ) ) ; +if ( TM . getTargetTriple ( ) . isOSBinFormatELF ( ) ) { +CTS . finishAttributeSection ( ) ; +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmPrinter/emitInstruction.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmPrinter/emitInstruction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2a556eeba32f05b445af3fa39e4d60c3caa3d8b3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmPrinter/emitInstruction.cpp @@ -0,0 +1,8 @@ +void PULPAsmPrinter :: emitInstruction ( const MachineInstr * MI ) { +if ( emitPseudoExpansionLowering ( * OutStreamer , MI ) ) { +return ; +} +MCInst TmpInst ; +LowerPULPMachineInstrToMCInst ( MI , TmpInst , * this ) ; +EmitToStreamer ( * OutStreamer , TmpInst ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmPrinter/emitStartOfAsmFile.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmPrinter/emitStartOfAsmFile.cpp new file mode 100644 index 0000000000000000000000000000000000000000..79d6cdeb201825dd876c33db2cbce05d699c5fad --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmPrinter/emitStartOfAsmFile.cpp @@ -0,0 +1,5 @@ +void PULPAsmPrinter :: emitStartOfAsmFile ( Module & M ) { +if ( TM . getTargetTriple ( ) . isOSBinFormatELF ( ) ) { +emitAttributes ( ) ; +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmPrinter/getPassName.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmPrinter/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9fad6be9a969e9e459d66c2376c417b8caa47a4e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmPrinter/getPassName.cpp @@ -0,0 +1,3 @@ +StringRef getPassName ( ) const override { +return "PULP Assembly Printer" ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmPrinter/lowerOperand.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmPrinter/lowerOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5b740d3077addd416254f68794367cde5cbf0f4e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmPrinter/lowerOperand.cpp @@ -0,0 +1,3 @@ +bool lowerOperand ( const MachineOperand & MO , MCOperand & MCOp ) const { +return LowerPULPMachineOperandToMCOperand ( MO , MCOp , * this ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmPrinter/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmPrinter/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c06658e1683e9b1a8db078e3dbf198f1aa8ad2d0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Assembler/AsmPrinter/runOnMachineFunction.cpp @@ -0,0 +1,8 @@ +bool PULPAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { +MCSubtargetInfo & NewSTI = OutStreamer -> getContext ( ) . getSubtargetCopy ( * TM . getMCSubtargetInfo ( ) ) ; +NewSTI . setFeatureBits ( MF . getSubtarget ( ) . getFeatureBits ( ) ) ; +STI = & NewSTI ; +SetupMachineFunction ( MF ) ; +emitFunctionBody ( ) ; +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/DecodeFPR16RegisterClass.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/DecodeFPR16RegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..08b354af1d98a9f083ccba19d7b6016e452c5e83 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/DecodeFPR16RegisterClass.cpp @@ -0,0 +1,8 @@ +static DecodeStatus DecodeFPR16RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { +if ( RegNo >= 32 ) { +return MCDisassembler :: Fail ; +} +MCRegister Reg = PULP :: F0_H + RegNo ; +Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; +return MCDisassembler :: Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/DecodeFPR32CRegisterClass.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/DecodeFPR32CRegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..09ecb49105527b9c0a975416955aaff8f110f47b --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/DecodeFPR32CRegisterClass.cpp @@ -0,0 +1,8 @@ +static DecodeStatus DecodeFPR32CRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { +if ( RegNo >= 8 ) { +return MCDisassembler :: Fail ; +} +MCRegister Reg = PULP :: F8_F + RegNo ; +Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; +return MCDisassembler :: Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/DecodeFPR32RegisterClass.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/DecodeFPR32RegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e8cce6a44e58650c841137b0149dbc02cafddc96 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/DecodeFPR32RegisterClass.cpp @@ -0,0 +1,8 @@ +static DecodeStatus DecodeFPR32RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { +if ( RegNo >= 32 ) { +return MCDisassembler :: Fail ; +} +MCRegister Reg = PULP :: F0_F + RegNo ; +Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; +return MCDisassembler :: Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/DecodeFPR64CRegisterClass.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/DecodeFPR64CRegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..be2dffc7df1c64381abae49b8b1c9bbd65e18790 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/DecodeFPR64CRegisterClass.cpp @@ -0,0 +1,8 @@ +static DecodeStatus DecodeFPR64CRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { +if ( RegNo >= 8 ) { +return MCDisassembler :: Fail ; +} +MCRegister Reg = PULP :: F8_D + RegNo ; +Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; +return MCDisassembler :: Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/DecodeFPR64RegisterClass.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/DecodeFPR64RegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..59244e5d1e335b593f69ca0ceaef7af4bdcb9908 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/DecodeFPR64RegisterClass.cpp @@ -0,0 +1,8 @@ +static DecodeStatus DecodeFPR64RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { +if ( RegNo >= 32 ) { +return MCDisassembler :: Fail ; +} +MCRegister Reg = PULP :: F0_D + RegNo ; +Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; +return MCDisassembler :: Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/DecodeGPRCRegisterClass.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/DecodeGPRCRegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..81806bd98433df778610b76fcd71407ada1a0d76 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/DecodeGPRCRegisterClass.cpp @@ -0,0 +1,8 @@ +static DecodeStatus DecodeGPRCRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { +if ( RegNo >= 8 ) { +return MCDisassembler :: Fail ; +} +MCRegister Reg = PULP :: X8 + RegNo ; +Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; +return MCDisassembler :: Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/DecodeGPRNoX0RegisterClass.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/DecodeGPRNoX0RegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..56ff4ef117332d294d29a991c66a0c16ddc875eb --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/DecodeGPRNoX0RegisterClass.cpp @@ -0,0 +1,6 @@ +static DecodeStatus DecodeGPRNoX0RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { +if ( RegNo == 0 ) { +return MCDisassembler :: Fail ; +} +return DecodeGPRRegisterClass ( Inst , RegNo , Address , Decoder ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/DecodeGPRNoX0X2RegisterClass.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/DecodeGPRNoX0X2RegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d8457ffe1102124e0dd4741d2b73b167a715d018 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/DecodeGPRNoX0X2RegisterClass.cpp @@ -0,0 +1,6 @@ +static DecodeStatus DecodeGPRNoX0X2RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { +if ( RegNo == 2 ) { +return MCDisassembler :: Fail ; +} +return DecodeGPRNoX0RegisterClass ( Inst , RegNo , Address , Decoder ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/DecodeGPRRegisterClass.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/DecodeGPRRegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..eb8d5daff772c2abc2cc3d46585b336a1a61e27a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/DecodeGPRRegisterClass.cpp @@ -0,0 +1,8 @@ +static DecodeStatus DecodeGPRRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { +if ( RegNo >= 32 ) { +return MCDisassembler :: Fail ; +} +MCRegister Register = PULP :: X0 + RegNo ; +Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; +return MCDisassembler :: Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/DecodePulpV2RegisterClass.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/DecodePulpV2RegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0624ed7b2915f6d5db3c3bc9728352418a5caee3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/DecodePulpV2RegisterClass.cpp @@ -0,0 +1,3 @@ +static DecodeStatus DecodePulpV2RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { +return DecodeGPRRegisterClass ( Inst , RegNo , Address , Decoder ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/DecodePulpV4RegisterClass.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/DecodePulpV4RegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..489321e8e2a3e5bb7e3b14839421a2f833146194 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/DecodePulpV4RegisterClass.cpp @@ -0,0 +1,3 @@ +static DecodeStatus DecodePulpV4RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { +return DecodeGPRRegisterClass ( Inst , RegNo , Address , Decoder ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/DecodeVRRegisterClass.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/DecodeVRRegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4770fdfb4b977ebd711dc20dd7280dccf05d3783 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/DecodeVRRegisterClass.cpp @@ -0,0 +1,8 @@ +static DecodeStatus DecodeVRRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { +if ( RegNo >= 32 ) { +return MCDisassembler :: Fail ; +} +MCRegister Register = PULP :: V0 + RegNo ; +Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; +return MCDisassembler :: Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/Disassembler.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/Disassembler.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6fba5d0b7a64444929258a8e122d683d683c913e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/Disassembler.cpp @@ -0,0 +1,2 @@ +PULPDisassembler ( const MCSubtargetInfo & STI , MCContext & Ctx , MCInstrInfo const * MCII ) : MCDisassembler ( STI , Ctx ) , MCII ( MCII ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/LLVMInitializeDisassembler.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/LLVMInitializeDisassembler.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6eb5f846d359f610f8c3de66fd49058bb6d676a7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/LLVMInitializeDisassembler.cpp @@ -0,0 +1,4 @@ +extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializePULPDisassembler ( ) { +TargetRegistry :: RegisterMCDisassembler ( getThePULP32Target ( ) , createPULPDisassembler ) ; +TargetRegistry :: RegisterMCDisassembler ( getThePULP64Target ( ) , createPULPDisassembler ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/addImplySP.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/addImplySP.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6984337e1c0b2b554e16973e592a86dd8700e618 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/addImplySP.cpp @@ -0,0 +1,43 @@ +static void addImplySP ( MCInst & Inst , int64_t Address , const void * Decoder ) { +if ( Inst . getOpcode ( ) == PULP :: C_LWSP ) { +DecodeGPRRegisterClass ( Inst , 2 , Address , Decoder ) ; +return ; +} +if ( Inst . getOpcode ( ) == PULP :: C_LDSP ) { +DecodeGPRRegisterClass ( Inst , 2 , Address , Decoder ) ; +return ; +} +if ( Inst . getOpcode ( ) == PULP :: C_SWSP ) { +DecodeGPRRegisterClass ( Inst , 2 , Address , Decoder ) ; +return ; +} +if ( Inst . getOpcode ( ) == PULP :: C_SDSP ) { +DecodeGPRRegisterClass ( Inst , 2 , Address , Decoder ) ; +return ; +} +if ( Inst . getOpcode ( ) == PULP :: C_FLWSP ) { +DecodeGPRRegisterClass ( Inst , 2 , Address , Decoder ) ; +return ; +} +if ( Inst . getOpcode ( ) == PULP :: C_FLDSP ) { +DecodeGPRRegisterClass ( Inst , 2 , Address , Decoder ) ; +return ; +} +if ( Inst . getOpcode ( ) == PULP :: C_FSWSP ) { +DecodeGPRRegisterClass ( Inst , 2 , Address , Decoder ) ; +return ; +} +if ( Inst . getOpcode ( ) == PULP :: C_FSDSP ) { +DecodeGPRRegisterClass ( Inst , 2 , Address , Decoder ) ; +return ; +} +if ( Inst . getOpcode ( ) == PULP :: C_ADDI4SPN ) { +DecodeGPRRegisterClass ( Inst , 2 , Address , Decoder ) ; +return ; +} +if ( Inst . getOpcode ( ) == PULP :: C_ADDI16SP ) { +DecodeGPRRegisterClass ( Inst , 2 , Address , Decoder ) ; +DecodeGPRRegisterClass ( Inst , 2 , Address , Decoder ) ; +return ; +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/createDisassembler.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/createDisassembler.cpp new file mode 100644 index 0000000000000000000000000000000000000000..01cee6cb5b76c41282d69791c85d78bc2388cc15 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/createDisassembler.cpp @@ -0,0 +1,3 @@ +static MCDisassembler * createPULPDisassembler ( const Target & T , const MCSubtargetInfo & STI , MCContext & Ctx ) { +return new PULPDisassembler ( STI , Ctx , T . createMCInstrInfo ( ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/decodeCLUIImmOperand.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/decodeCLUIImmOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5c57b9b63caf407ad7192aaed4e2f2f0915396be --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/decodeCLUIImmOperand.cpp @@ -0,0 +1,5 @@ +static DecodeStatus decodeCLUIImmOperand ( MCInst & Inst , uint64_t Imm , uint64_t Address , const void * Decoder ) { +assert ( isUInt < 6 > ( Imm ) ) && "Invalid immediate" ) ; +Inst . addOperand ( MCOperand :: createImm ( Imm > 31 ? ( SignExtend64 < 6 > ( Imm ) & 0xfffff ) : Imm ) ) ; +return MCDisassembler :: Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/decodeFRMArg.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/decodeFRMArg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ee39fe41a1d7a2989ce659dd881e764ff20b9bb2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/decodeFRMArg.cpp @@ -0,0 +1,8 @@ +static DecodeStatus decodeFRMArg ( MCInst & Inst , uint64_t Imm , uint64_t Address , const void * Decoder ) { +assert ( isUInt < 3 > ( Imm ) ) ; +if ( ! A64Imms :: isLogicalImmBits ( RegWidth , Bits , Imm ) ) { +return MCDisassembler :: Fail ; +} +Inst . addOperand ( MCOperand :: createImm ( Imm ) ) ; +return MCDisassembler :: Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/decodeRVCInstrRdRs1Rs2.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/decodeRVCInstrRdRs1Rs2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2ccc40a6af115452415a83ccf45a94001eba8130 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/decodeRVCInstrRdRs1Rs2.cpp @@ -0,0 +1,13 @@ +static DecodeStatus decodeRVCInstrRdRs1Rs2 ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { +unsigned d = fieldFromInstruction ( Insn , 7 , 5 ) ; +unsigned const9 = 0 ; +unsigned s1 = fieldFromInstruction ( Insn , 2 , 5 ) ; +DecodeStatus status = DecodeGPRRegisterClass ( Inst , d , Address , Decoder ) ; +if ( status != MCDisassembler :: Success ) { +return status ; +Inst . addOperand ( MCOperand :: createImm ( const9 ) ) ; +status = DecodeGPRRegisterClass ( Inst , s1 , Address , Decoder ) ; +if ( status != MCDisassembler :: Success ) { +return status ; +return MCDisassembler :: Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/decodeRVCInstrRdRs1UImm.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/decodeRVCInstrRdRs1UImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..da13f76689fe7263b763ab73458ee0c884ae8fab --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/decodeRVCInstrRdRs1UImm.cpp @@ -0,0 +1,10 @@ +static DecodeStatus decodeRVCInstrRdRs1UImm ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { +unsigned char op = ( insn >> 5 ) & 1 ; +unsigned char cmode = ( insn >> 8 ) & 0xF ; +unsigned char Imm8 = ( ( insn >> 24 ) & 1 ) << 7 | ( ( insn >> 16 ) & 7 ) << 4 | ( insn & 0xF ) ; +unsigned Offset = ( Insn & 0xffff ) ; +if ( Bits >= 16 ) { +return MCDisassembler :: Fail ; +} +return MCDisassembler :: Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/decodeRVCInstrRdRs2.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/decodeRVCInstrRdRs2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b6fe70e90426d71fb0e173b67252d7ff580dda1d --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/decodeRVCInstrRdRs2.cpp @@ -0,0 +1,13 @@ +static DecodeStatus decodeRVCInstrRdRs2 ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { +unsigned Rd = fieldFromInstruction ( Insn , 7 , 5 ) ; +unsigned Rs2 = fieldFromInstruction ( Insn , 2 , 5 ) ; +DecodeStatus status = DecodeGPRRegisterClass ( Inst , Rd , Address , Decoder ) ; +if ( status != MCDisassembler :: Success ) { +return status ; +} +status = DecodeGPRRegisterClass ( Inst , Rs2 , Address , Decoder ) ; +if ( status != MCDisassembler :: Success ) { +return status ; +} +return MCDisassembler :: Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/decodeRVCInstrRdSImm.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/decodeRVCInstrRdSImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f7c00f52c104a5b6628597191543ac6cf4dc8106 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/decodeRVCInstrRdSImm.cpp @@ -0,0 +1,18 @@ +static DecodeStatus decodeRVCInstrRdSImm ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { +unsigned char op = ( insn >> 5 ) & 1 ; +unsigned char cmode = ( insn >> 8 ) & 0xF ; +unsigned char Imm8 = ( ( insn >> 24 ) & 1 ) << 7 | ( ( insn >> 16 ) & 7 ) << 4 | ( insn & 0xF ) ; +unsigned Offset = ( Insn & 0xffff ) ; +if ( Bits >= 16 ) { +return MCDisassembler :: Fail ; +} +int64_t Imm = Bits + 1 ; +const JmpExtraValues * extra = ( reinterpret_cast < const JmpExtraValues * > ( Addr ) ) ; +uint64_t address = extra -> Address + extra -> Imm ; +if ( ! tryAddingSymbolicOperand ( address , 0 , true , 0 , Inst , Decoder ) ) { +Inst . addOperand ( MCOperand :: createImm ( extra -> Imm ) ) ; +} +unsigned Register = PredicateTable [ extra -> Predicate ] ; +Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; +return MCDisassembler :: Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/decodeRVCInstrSImm.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/decodeRVCInstrSImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0b3b7efb37c77265cefc5bea79aaf992cdecdb90 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/decodeRVCInstrSImm.cpp @@ -0,0 +1,18 @@ +static DecodeStatus decodeRVCInstrSImm ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { +unsigned char op = ( insn >> 5 ) & 1 ; +unsigned char cmode = ( insn >> 8 ) & 0xF ; +unsigned char Imm8 = ( ( insn >> 24 ) & 1 ) << 7 | ( ( insn >> 16 ) & 7 ) << 4 | ( insn & 0xF ) ; +unsigned Offset = ( Insn & 0xffff ) ; +if ( Bits >= 16 ) { +return MCDisassembler :: Fail ; +} +int64_t Imm = Bits + 1 ; +const JmpExtraValues * extra = ( reinterpret_cast < const JmpExtraValues * > ( Addr ) ) ; +uint64_t address = extra -> Address + extra -> Imm ; +if ( ! tryAddingSymbolicOperand ( address , 0 , true , 0 , Inst , Decoder ) ) { +Inst . addOperand ( MCOperand :: createImm ( extra -> Imm ) ) ; +} +unsigned Register = PredicateTable [ extra -> Predicate ] ; +Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; +return MCDisassembler :: Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/decodeSImmNonZeroOperand.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/decodeSImmNonZeroOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..992cc6c7a54db0d62e19897ac2e09341bf7660d9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/decodeSImmNonZeroOperand.cpp @@ -0,0 +1,9 @@ +template < unsigned N > static DecodeStatus decodeSImmNonZeroOperand ( MCInst & Inst , uint64_t Imm , int64_t Address , const void * Decoder ) { +if ( Imm == 0 ) { +return MCDisassembler :: Fail ; +} +assert ( isUInt < N > ( Imm ) && "Invalid immediate" ) ; +addImplySP ( Inst , Address , Decoder ) ; +Inst . addOperand ( MCOperand :: createImm ( SignExtend64 < N > ( Imm ) ) ) ; +return MCDisassembler :: Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/decodeSImmOperand.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/decodeSImmOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c89f4af3b6e532a7cc8a1dd52b006ba415a839ec --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/decodeSImmOperand.cpp @@ -0,0 +1,6 @@ +template < unsigned N > static DecodeStatus decodeSImmOperand ( MCInst & Inst , uint64_t Imm , int64_t Address , const void * Decoder ) { +assert ( isUInt < N > ( Imm ) && "Invalid immediate" ) ; +addImplySP ( Inst , Address , Decoder ) ; +Inst . addOperand ( MCOperand :: createImm ( SignExtend64 < N > ( Imm ) ) ) ; +return MCDisassembler :: Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/decodeSImmOperandAndLsl1.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/decodeSImmOperandAndLsl1.cpp new file mode 100644 index 0000000000000000000000000000000000000000..15963ce120e841adbc2f7e17ae57d854431f5c0a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/decodeSImmOperandAndLsl1.cpp @@ -0,0 +1,5 @@ +template < unsigned N > static DecodeStatus decodeSImmOperandAndLsl1 ( MCInst & Inst , uint64_t Imm , int64_t Address , const void * Decoder ) { +assert ( isUInt < N > ( Imm ) && "Invalid immediate" ) ; +Inst . addOperand ( MCOperand :: createImm ( SignExtend64 < N > ( Imm << 1 ) ) ) ; +return MCDisassembler :: Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/decodeUImmMinus1Operand.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/decodeUImmMinus1Operand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c9ebb73c32d8cb45f92f0e1e6df9ac435862e000 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/decodeUImmMinus1Operand.cpp @@ -0,0 +1,6 @@ +template < unsigned N > static DecodeStatus decodeUImmMinus1Operand ( MCInst & Inst , uint64_t Imm , int64_t Address , const void * Decoder ) { +assert ( isUInt < N > ( Imm + 1 ) && "Invalid immediate" ) ; +addImplySP ( Inst , Address , Decoder ) ; +Inst . addOperand ( MCOperand :: createImm ( Imm + 1 ) ) ; +return MCDisassembler :: Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/decodeUImmNonZeroOperand.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/decodeUImmNonZeroOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..886faa3bb851945909f1de7e3c6d8b33d9176807 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/decodeUImmNonZeroOperand.cpp @@ -0,0 +1,9 @@ +template < unsigned N > static DecodeStatus decodeUImmNonZeroOperand ( MCInst & Inst , uint64_t Imm , int64_t Address , const void * Decoder ) { +if ( Imm == 0 ) { +return MCDisassembler :: Fail ; +} +assert ( isUInt < N > ( Imm ) && "Invalid immediate" ) ; +addImplySP ( Inst , Address , Decoder ) ; +Inst . addOperand ( MCOperand :: createImm ( Imm ) ) ; +return MCDisassembler :: Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/decodeUImmOperand.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/decodeUImmOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..202289bb54a00b03168ee8c05ae14e224c690da1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/decodeUImmOperand.cpp @@ -0,0 +1,6 @@ +template < unsigned N > static DecodeStatus decodeUImmOperand ( MCInst & Inst , uint64_t Imm , int64_t Address , const void * Decoder ) { +assert ( isUInt < N > ( Imm ) && "Invalid immediate" ) ; +addImplySP ( Inst , Address , Decoder ) ; +Inst . addOperand ( MCOperand :: createImm ( Imm ) ) ; +return MCDisassembler :: Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/decodeVMaskReg.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/decodeVMaskReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..91ca4d691f82e4fd4b399947a7fe20d768dfa5ef --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/decodeVMaskReg.cpp @@ -0,0 +1,14 @@ +static DecodeStatus decodeVMaskReg ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { +MCRegister Reg = PULP :: NoRegister ; +return MCDisassembler :: Success ; +return MCDisassembler :: Success ; +if ( RegNo == 0 ) { +Inst . addOperand ( MCOperand :: createReg ( PULP :: V0 ) ) ; +return MCDisassembler :: Success ; +} +if ( RegNo == 1 ) { +Inst . addOperand ( MCOperand :: createReg ( PULP :: NoRegister ) ) ; +return MCDisassembler :: Success ; +} +return MCDisassembler :: Fail ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/getInstruction.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/getInstruction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..36a8bf92b78af07f79b911977d975abe14f898c1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Disassembler/Disassembler/getInstruction.cpp @@ -0,0 +1,69 @@ +DecodeStatus PULPDisassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & CS ) const { +DecodeStatus Result ; +if ( Bytes . size ( ) < 2 ) { +Size = 0 ; +return Fail ; +} +if ( ( Bytes [ 1 ] & 0xF7 ) >> 3 < 0x08 ) { +if ( Bytes . size ( ) < 4 ) { +Size = 0 ; +return Fail ; +} +if ( Bytes . size ( ) >= 8 ) { +uint64_t Insn64 ; +if ( ! readInstruction64 ( Bytes , Address , Size , Insn64 ) ) { +return Fail ; +} +Result = decodeInstruction ( DecoderTable64 , Instr , Insn64 , Address , this , STI ) ; +if ( Success == Result ) { +LLVM_DEBUG ( dbgs ( ) << "Successfully decoded 64-bit instruction." ) ; +return Result ; +} +LLVM_DEBUG ( dbgs ( ) << "Not a 64-bit instruction, falling back to 32-bit." ) ; +} +uint32_t Insn32 ; +if ( ! readInstruction32 ( Bytes , Address , Size , Insn32 ) ) { +return Fail ; +} +return decodeInstruction ( DecoderTable32 , Instr , Insn32 , Address , this , STI ) ; +} +if ( ( Bytes [ 1 ] & 0xF7 ) >> 3 >= 0x08 ) { +if ( Bytes . size ( ) >= 6 ) { +uint64_t Insn48 ; +if ( ! readInstruction48 ( Bytes , Address , Size , Insn48 ) ) { +return Fail ; +} +Result = decodeInstruction ( DecoderTable48 , Instr , Insn48 , Address , this , STI ) ; +if ( Success == Result ) { +LLVM_DEBUG ( dbgs ( ) << "Successfully decoded 16-bit instruction with limm." ) ; +return Result ; +} +LLVM_DEBUG ( dbgs ( ) << "Not a 16-bit instruction with limm, try without it." ) ; +} +uint32_t Insn16 ; +if ( ! readInstruction16 ( Bytes , Address , Size , Insn16 ) ) { +return Fail ; +} +return decodeInstruction ( DecoderTable16 , Instr , Insn16 , Address , this , STI ) ; +} +uint32_t Inst ; +if ( Bytes [ 0 ] & 1 == 1 ) { +if ( Bytes . size ( ) < 3 ) { +Size = 0 ; +return MCDisassembler :: Fail ; +} +Inst = Bytes [ 0 ] | ( Bytes [ 1 ] << 8 ) | ( Bytes [ 2 ] << 16 ) ; +LLVM_DEBUG ( dbgs ( ) << "Trying PULP 24bit table :\n" ) ; +Result = decodeInstruction ( DecoderTable24 , MI , Inst , Address , this , STI ) ; +} +if ( Bytes [ 0 ] & 1 != 1 ) { +if ( Bytes . size ( ) < 2 ) { +Size = 0 ; +return MCDisassembler :: Fail ; +} +Inst = support :: endian :: read16le ( Bytes . data ( ) ) ; +LLVM_DEBUG ( dbgs ( ) << "Trying PULP 16bit table :\n" ) ; +Result = decodeInstruction ( DecoderTable16 , MI , Inst , Address , this , STI ) ; +} +return Result ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/AsmBackend.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/AsmBackend.cpp new file mode 100644 index 0000000000000000000000000000000000000000..24d484539e4deacf841deb9838e3fe17d862239d --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/AsmBackend.cpp @@ -0,0 +1,2 @@ +PULPAsmBackend ( const MCSubtargetInfo & STI , uint8_t OSABI , bool Is64Bit , const MCTargetOptions & Options ) : MCAsmBackend ( support :: little ) , STI ( STI ) , OSABI ( OSABI ) , Is64Bit ( Is64Bit ) , TargetOptions ( Options ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/adjustFixupValue.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/adjustFixupValue.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cedec69e79d5468d216540276f98f6db91b85116 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/adjustFixupValue.cpp @@ -0,0 +1,89 @@ +static uint64_t adjustFixupValue ( const MCFixup & Fixup , uint64_t Value , MCContext & Ctx ) { +unsigned Kind ; +Kind = Fixup . getTargetKind ( ) ; +if ( Kind == FK_Data_1 ) { +return Value ; +} +if ( Kind == FK_Data_2 ) { +return Value ; +} +if ( Kind == FK_Data_4 ) { +return Value ; +} +if ( Kind == FK_Data_8 ) { +return Value ; +} +if ( Kind == FK_Data_6b ) { +return Value ; +} +if ( Kind == PULP :: fixup_PULP_lo12_i ) { +return Value & 0xfff ; +} +if ( Kind == PULP :: fixup_PULP_pcrel_lo12_i ) { +return Value & 0xfff ; +} +if ( Kind == PULP :: fixup_PULP_tprel_lo12_i ) { +return Value & 0xfff ; +} +if ( Kind == PULP :: fixup_PULP_loop_setup ) { +return Value >> 1 ; +} +if ( Kind == PULP :: fixup_PULP_loop_setupi ) { +return Value >> 1 ; +} +if ( Kind == PULP :: fixup_PULP_lo12_s ) { +return ( ( ( Value >> 5 ) & 0x7f ) << 25 ) | ( ( Value & 0x1f ) << 7 ) ; +} +if ( Kind == PULP :: fixup_PULP_pcrel_lo12_s ) { +return ( ( ( Value >> 5 ) & 0x7f ) << 25 ) | ( ( Value & 0x1f ) << 7 ) ; +} +if ( Kind == PULP :: fixup_PULP_tprel_lo12_s ) { +return ( ( ( Value >> 5 ) & 0x7f ) << 25 ) | ( ( Value & 0x1f ) << 7 ) ; +} +if ( Kind == PULP :: fixup_PULP_hi20 ) { +return ( ( Value + 0x800 ) >> 12 ) & 0xfffff ; +} +if ( Kind == PULP :: fixup_PULP_pcrel_hi20 ) { +return ( ( Value + 0x800 ) >> 12 ) & 0xfffff ; +} +if ( Kind == PULP :: fixup_PULP_tprel_hi20 ) { +return ( ( Value + 0x800 ) >> 12 ) & 0xfffff ; +} +if ( Kind == PULP :: fixup_PULP_call ) { +return ( ( Value + 0x800ULL ) & 0xfffff000ULL ) | ( ( ( Value & 0xfffULL ) << 20 ) << 32 ) ; +} +if ( Kind == PULP :: fixup_PULP_call_plt ) { +return ( ( Value + 0x800ULL ) & 0xfffff000ULL ) | ( ( ( Value & 0xfffULL ) << 20 ) << 32 ) ; +} +if ( Kind == PULP :: fixup_PULP_rvc_jump ) { +return ( ( ( Value >> 11 ) & 0x1 ) << 10 ) | ( ( ( Value >> 4 ) & 0x1 ) << 9 ) | ( ( ( Value >> 8 ) & 0x3 ) << 7 ) | ( ( Value >> 10 ) & 0x1 ) << 6 ) | ( ( Value >> 6 ) & 0x1 ) << 5 ) | ( ( Value >> 7 ) & 0x1 ) << 4 ) | ( ( Value >> 1 ) & 0x7 ) << 1 ) ; +} +if ( Kind == PULP :: fixup_PULP_rvc_branch ) { +return ( ( ( Value >> 8 ) & 0x1 ) << 12 ) | ( ( ( Value >> 3 ) & 0x3 ) << 5 ) | ( ( ( Value >> 6 ) & 0x3 ) << 3 ) ; +} +if ( Kind == PULP :: fixup_PULP_tls_got_hi20 ) { +} +if ( Kind == PULP :: fixup_PULP_tls_gd_hi20 ) { +} +if ( Kind == PULP :: fixup_PULP_got_hi20 ) { +} +if ( Kind == PULP :: fixup_PULP_branch ) { +if ( ! isInt < 13 > ( Value ) ) { +Ctx . reportError ( Fixup . getLoc ( ) , "fixup value out of range" ) ; +} +if ( Value & 0x1 ) { +Ctx . reportError ( Fixup . getLoc ( ) , "fixup value must be 2-byte aligned." ) ; +} +return ( ( ( Value >> 12 ) & 0x1 ) << 31 ) | ( ( ( Value >> 5 ) & 0x3f ) << 25 ) | ( ( ( Value >> 1 ) & 0x1 ) << 7 ) ; +} +if ( Kind == PULP :: fixup_PULP_jal ) { +if ( ! isInt < 21 > ( Value ) ) { +Ctx . reportError ( Fixup . getLoc ( ) , "fixup value out of range" ) ; +} +if ( Value & 0x1 ) { +Ctx . reportError ( Fixup . getLoc ( ) , "fixup value must be 2-byte aligned." ) ; +} +return ( ( ( Value >> 20 ) & 0x1 ) << 19 ) | ( ( ( Value >> 11 ) & 0x1 ) << 8 ) ; +} +llvm_unreachable ( "Unknown fixup kind!" ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/applyFixup.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/applyFixup.cpp new file mode 100644 index 0000000000000000000000000000000000000000..dabe9fd329c1e442c34e7601af8db1cab4515db1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/applyFixup.cpp @@ -0,0 +1,25 @@ +void PULPAsmBackend :: applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved , const MCSubtargetInfo * STI ) const { +MCFixupKind Kind ; +Kind = Fixup . getKind ( ) ; +if ( Kind >= FirstLiteralRelocationKind ) { +return ; +} +MCContext & Ctx = Asm . getContext ( ) ; +if ( ! Value ) { +return ; +} +MCFixupKindInfo Info ; +Info = getFixupKindInfo ( Kind ) ; +Value = adjustFixupValue ( Fixup , Value , Ctx ) << Info . TargetOffset ; +unsigned Offset ; +Offset = Fixup . getOffset ( ) ; +unsigned NumBytes ; +NumBytes = alignTo ( Info . TargetSize + Info . TargetOffset , 8 ) / 8 ; +assert ( Offset + NumBytes <= Data . size ( ) && "Invalid fixup offset!" ) ; +if ( MCAsmBackend :: Endian == support :: little ) { +unsigned i ; +for ( i = 0 ; i != NumBytes ; ++ i ) { +Data [ Offset + i ] = Data [ Offset + i ] | uint8_t ( ( Value >> ( i * 8 ) ) & 0xff ) ; +} +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/createAsmBackend.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/createAsmBackend.cpp new file mode 100644 index 0000000000000000000000000000000000000000..dabd6662b40887d4ec71d502d98492e99890fa46 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/createAsmBackend.cpp @@ -0,0 +1,5 @@ +MCAsmBackend * llvm :: createPULPAsmBackend ( const Target & T , const MCSubtargetInfo & STI , const MCRegisterInfo & MRI , const MCTargetOptions & Options ) { +const Triple & TT = STI . getTargetTriple ( ) ; +uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TT . getOS ( ) ) ; +return new PULPAsmBackend ( STI , OSABI , TT . isArch64Bit ( ) , Options ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/createObjectTargetWriter.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/createObjectTargetWriter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f6b9ff5cfb0328013a649f77b23cdbd3cd8483d2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/createObjectTargetWriter.cpp @@ -0,0 +1,4 @@ +std :: unique_ptr < MCObjectTargetWriter > PULPAsmBackend :: createObjectTargetWriter ( ) const { +StringRef CPU ( "Default" ) ; +return createPULPELFObjectWriter ( OSABI , Is64Bit ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/evaluateTargetFixup.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/evaluateTargetFixup.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ea2d10760edca36021c049ba610fb0d85b23c8c6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/evaluateTargetFixup.cpp @@ -0,0 +1,2 @@ +bool PULPAsmBackend :: evaluateTargetFixup ( const MCAssembler & Asm , const MCAsmLayout & Layout , const MCFixup & Fixup , const MCFragment * DF , const MCValue & Target , uint64_t & Value , bool & WasForced ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/fixupNeedsRelaxation.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/fixupNeedsRelaxation.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6824221f10a156ddf44d2dae960a7bc794ab14c1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/fixupNeedsRelaxation.cpp @@ -0,0 +1,3 @@ +bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override { +llvm_unreachable ( "Handled by fixupNeedsRelaxationAdvanced" ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/fixupNeedsRelaxationAdvanced.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/fixupNeedsRelaxationAdvanced.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5b1ddd00b6a330ea57661a936128a4f723404183 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/fixupNeedsRelaxationAdvanced.cpp @@ -0,0 +1,16 @@ +bool PULPAsmBackend :: fixupNeedsRelaxationAdvanced ( const MCFixup & Fixup , bool Resolved , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout , const bool WasForced ) const { +if ( ! Resolved ) { +if ( ! WasForced ) { +return true ; +} +} +int64_t Offset ; +Offset = int64_t ( Value ) ; +if ( Fixup . getTargetKind ( ) == PULP :: fixup_PULP_rvc_branch ) { +return Offset > 254 || Offset < - 256 ; +} +if ( Fixup . getTargetKind ( ) == PULP :: fixup_PULP_rvc_jump ) { +return Offset > 2046 || Offset < -2048 ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/getFixupKind.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/getFixupKind.cpp new file mode 100644 index 0000000000000000000000000000000000000000..56b7c17f69d57ea67f93fe78570a0be9d7e28e82 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/getFixupKind.cpp @@ -0,0 +1,11 @@ +Optional < MCFixupKind > PULPAsmBackend :: getFixupKind ( StringRef Name ) const { +if ( STI . getTargetTriple ( ) . isOSBinFormatELF ( ) ) { +unsigned Type ; +Type = llvm :: StringSwitch < unsigned > ( Name ) +. Default ( - 1u ) ; +if ( Type != - 1u ) { +return static_cast < MCFixupKind > ( FirstLiteralRelocationKind + Type ) ; +} +} +return None ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/getFixupKindInfo.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/getFixupKindInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..853679194b96290465b052ebccebf0ff5aaa4851 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/getFixupKindInfo.cpp @@ -0,0 +1,35 @@ +const MCFixupKindInfo & PULPAsmBackend :: getFixupKindInfo ( MCFixupKind Kind ) const { +const static MCFixupKindInfo Infos [ PULP :: NumTargetFixupKinds ] = { +{ "fixup_PULP_hi20" , 12 , 20 , 0 } , +{ "fixup_PULP_lo12_i" , 20 , 12 , 0 } , +{ "fixup_PULP_lo12_s" , 0 , 32 , 0 } , +{ "fixup_PULP_pcrel_hi20" , 12 , 20 , MCFixupKindInfo :: FKF_IsPCRel } , +{ "fixup_PULP_pcrel_lo12_i" , 20 , 12 , MCFixupKindInfo :: FKF_IsPCRel } , +{ "fixup_PULP_pcrel_lo12_s" , 0 , 32 , MCFixupKindInfo :: FKF_IsPCRel } , +{ "fixup_PULP_got_hi20" , 12 , 20 , MCFixupKindInfo :: FKF_IsPCRel } , +{ "fixup_PULP_tprel_hi20" , 12 , 20 , 0 } , +{ "fixup_PULP_tprel_lo12_i" , 20 , 12 , 0 } , +{ "fixup_PULP_tprel_lo12_s" , 0 , 32 , 0 } , +{ "fixup_PULP_tprel_add" , 0 , 0 , 0 } , +{ "fixup_PULP_tls_got_hi20" , 12 , 20 , MCFixupKindInfo :: FKF_IsPCRel } , +{ "fixup_PULP_tls_gd_hi20" , 12 , 20 , MCFixupKindInfo :: FKF_IsPCRel } , +{ "fixup_PULP_jal" , 12 , 20 , MCFixupKindInfo :: FKF_IsPCRel } , +{ "fixup_PULP_branch" , 0 , 32 , MCFixupKindInfo :: FKF_IsPCRel } , +{ "fixup_PULP_rvc_jump" , 2 , 11 , MCFixupKindInfo :: FKF_IsPCRel } , +{ "fixup_PULP_rvc_branch" , 0 , 16 , MCFixupKindInfo :: FKF_IsPCRel } , +{ "fixup_PULP_call" , 0 , 64 , MCFixupKindInfo :: FKF_IsPCRel } , +{ "fixup_PULP_call_plt" , 0 , 64 , MCFixupKindInfo :: FKF_IsPCRel } , +{ "fixup_PULP_relax" , 0 , 0 , 0 } , +{ "fixup_PULP_align" , 0 , 0 , 0 } , +{ "fixup_PULP_loop_setup" , 20 , 12 , MCFixupKindInfo :: FKF_IsPCRel } , +{ "fixup_PULP_loop_setupi" , 15 , 5 , MCFixupKindInfo :: FKF_IsPCRel } +} ; +if ( Kind >= FirstLiteralRelocationKind ) { +return MCAsmBackend :: getFixupKindInfo ( FK_NONE ) ; +} +if ( Kind < FirstTargetFixupKind ) { +return MCAsmBackend :: getFixupKindInfo ( Kind ) ; +} +assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && "Invalid kind!" ) ; +return Infos [ Kind - FirstTargetFixupKind ] ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/getNumFixupKinds.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/getNumFixupKinds.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f4fe6e5468f88cd3d3b95bd8361cd48f627577e0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/getNumFixupKinds.cpp @@ -0,0 +1,3 @@ +unsigned getNumFixupKinds ( ) const override { +return PULP :: NumTargetFixupKinds ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/getRelaxedOpcode.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/getRelaxedOpcode.cpp new file mode 100644 index 0000000000000000000000000000000000000000..278c0cc76e473e6406be5828b642072bd5c2c931 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/getRelaxedOpcode.cpp @@ -0,0 +1,15 @@ +unsigned PULPAsmBackend :: getRelaxedOpcode ( unsigned Op ) const { +if ( Op == PULP :: C_BEQZ ) { +return PULP :: BEQ ; +} +if ( Op == PULP :: C_BNEZ ) { +return PULP :: BNE ; +} +if ( Op == PULP :: C_J ) { +return PULP :: JAL ; +} +if ( Op == PULP :: C_JAL ) { +return PULP :: JAL ; +} +return Op ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/getTargetABI.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/getTargetABI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e2a5361219e721c25ce26aebe56fec7a9b3b3a80 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/getTargetABI.cpp @@ -0,0 +1,3 @@ +PULPABI :: ABI getTargetABI ( ) const { +return TargetABI ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/getTargetOptions.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/getTargetOptions.cpp new file mode 100644 index 0000000000000000000000000000000000000000..05f473298a9cd8a5b183051967a9322c84a1a94b --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/getTargetOptions.cpp @@ -0,0 +1,3 @@ +const MCTargetOptions & getTargetOptions ( ) const { +return TargetOptions ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/mayNeedRelaxation.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/mayNeedRelaxation.cpp new file mode 100644 index 0000000000000000000000000000000000000000..528430a7b2a1531754b1acd714da7ccb49b05669 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/mayNeedRelaxation.cpp @@ -0,0 +1,15 @@ +bool PULPAsmBackend :: mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo & STI ) const { +if ( Inst . getOpcode ( ) == PULP :: C_BEQZ ) { +return true ; +} +if ( Inst . getOpcode ( ) == PULP :: C_BNEZ ) { +return true ; +} +if ( Inst . getOpcode ( ) == PULP :: C_J ) { +return true ; +} +if ( Inst . getOpcode ( ) == PULP :: C_JAL ) { +return true ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/relaxInstruction.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/relaxInstruction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..822a402de6cea47a1a6ba812bd79bd6dd18e331e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/relaxInstruction.cpp @@ -0,0 +1,32 @@ +void PULPAsmBackend :: relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , MCInst & Res ) const { +MCInst Res ; +if ( Inst . getOpcode ( ) == PULP :: C_BEQZ ) { +Res . setOpcode ( PULP :: BEQ ) ; +Res . addOperand ( Inst . getOperand ( 0 ) ) ; +Res . addOperand ( Inst . getOperand ( 1 ) ) ; +Inst = std :: move ( Res ) ; +return ; +} +if ( Inst . getOpcode ( ) == PULP :: C_BNEZ ) { +Res . setOpcode ( PULP :: BNE ) ; +Res . addOperand ( Inst . getOperand ( 0 ) ) ; +Res . addOperand ( Inst . getOperand ( 1 ) ) ; +Inst = std :: move ( Res ) ; +return ; +} +if ( Inst . getOpcode ( ) == PULP :: C_J ) { +Res . setOpcode ( PULP :: JAL ) ; +Res . addOperand ( MCOperand :: createReg ( PULP :: X0 ) ) ; +Res . addOperand ( Inst . getOperand ( 0 ) ) ; +Inst = std :: move ( Res ) ; +return ; +} +if ( Inst . getOpcode ( ) == PULP :: C_JAL ) { +Res . setOpcode ( PULP :: JAL ) ; +Res . addOperand ( MCOperand :: createReg ( PULP :: X1 ) ) ; +Res . addOperand ( Inst . getOperand ( 0 ) ) ; +Inst = std :: move ( Res ) ; +return ; +} +llvm_unreachable ( "Opcode not expected!" ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/requiresDiffExpressionRelocations.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/requiresDiffExpressionRelocations.cpp new file mode 100644 index 0000000000000000000000000000000000000000..eb2bcffee489f3110fed5e13dcdb38e9e8805d92 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/requiresDiffExpressionRelocations.cpp @@ -0,0 +1,3 @@ +bool requiresDiffExpressionRelocations ( ) const override { +return STI . getFeatureBits ( ) [ PULP :: FeatureRelax ] ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/setForceRelocs.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/setForceRelocs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b44816c017c6bd035ed1453ab624e78566974b0a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/setForceRelocs.cpp @@ -0,0 +1,3 @@ +void setForceRelocs ( ) { +ForceRelocs = true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/shouldForceRelocation.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/shouldForceRelocation.cpp new file mode 100644 index 0000000000000000000000000000000000000000..806046d67f520c7fb7e7fbd2064545c3e9b789cc --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/shouldForceRelocation.cpp @@ -0,0 +1,22 @@ +bool PULPAsmBackend :: shouldForceRelocation ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target ) { +if ( Fixup . getTargetKind ( ) >= FirstLiteralRelocationKind ) { +return true ; +} +if ( Fixup . getTargetKind ( ) == FK_Data_1 ) { +} +if ( Fixup . getTargetKind ( ) == FK_Data_2 ) { +} +if ( Fixup . getTargetKind ( ) == FK_Data_4 ) { +} +if ( Fixup . getTargetKind ( ) == FK_Data_8 ) { +} +if ( Fixup . getTargetKind ( ) == PULP :: fixup_PULP_got_hi20 ) { +return true ; +} +if ( Fixup . getTargetKind ( ) == PULP :: fixup_PULP_tls_got_hi20 ) { +return true ; +} +if ( Fixup . getTargetKind ( ) == PULP :: fixup_PULP_tls_gd_hi20 ) { +return true ; +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/shouldInsertExtraNopBytesForCodeAlign.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/shouldInsertExtraNopBytesForCodeAlign.cpp new file mode 100644 index 0000000000000000000000000000000000000000..81c50b8e4f3deba537909b890265eb536531a750 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/shouldInsertExtraNopBytesForCodeAlign.cpp @@ -0,0 +1,2 @@ +bool PULPAsmBackend :: shouldInsertExtraNopBytesForCodeAlign ( MCAssembler & Asm , const MCAsmLayout & Layout , MCAlignFragment & AF ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/shouldInsertFixupForCodeAlign.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/shouldInsertFixupForCodeAlign.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1f4fbb1c6becfdf47f5827e2509aceded27313f2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/shouldInsertFixupForCodeAlign.cpp @@ -0,0 +1,2 @@ +bool PULPAsmBackend :: shouldInsertFixupForCodeAlign ( MCAssembler & Asm , const MCAsmLayout & Layout , MCAlignFragment & AF ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/willForceRelocations.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/willForceRelocations.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a43284016aa45e2c1ea1f41925d773e828f9c67a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/willForceRelocations.cpp @@ -0,0 +1,3 @@ +bool willForceRelocations ( ) const { +return STI . getFeatureBits ( ) [ PULP :: FeatureRelax ] ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/writeNopData.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/writeNopData.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9b4165982f797f20da5603b1bed12d3e04f33e42 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/writeNopData.cpp @@ -0,0 +1,14 @@ +bool PULPAsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count ) const { +if ( Count % 2 != 0 ) { +return false ; +} +uint64_t NopCount = Count / 4 ; +uint64_t i ; +for ( i = 0 ; i < NopCount ; ++ i ) { +OS . write ( "\x13\0\0\0" , 4 ) ; +} +if ( Count % 4 == 2 ) { +OS . write ( "\x01\0" , 2 ) ; +} +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/~AsmBackend.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/~AsmBackend.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e7e335aecb6bb50dec6fc8508a171446cd094a51 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmBackend/~AsmBackend.cpp @@ -0,0 +1,2 @@ +~ PULPAsmBackend ( ) override { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmInfo/MCAsmInfo.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmInfo/MCAsmInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..227571e26d6dcf0e4e8a509d9da11613b05d6d3c --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmInfo/MCAsmInfo.cpp @@ -0,0 +1,10 @@ +PULPMCAsmInfo :: PULPMCAsmInfo ( const Triple & TT ) { +CodePointerSize = TT . isArch64Bit ( ) ? 8 : 4 ; +CalleeSaveStackSlotSize = TT . isArch64Bit ( ) ? 8 : 4 ; +CommentString = "#" ; +AlignmentIsInBytes = false ; +SupportsDebugInformation = true ; +ExceptionsType = ExceptionHandling :: DwarfCFI ; +Data16bitsDirective = "\t.half\t" ; +Data32bitsDirective = "\t.word\t" ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmInfo/anchor.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmInfo/anchor.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c47b5946452936592ff5affced053487a8599f78 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmInfo/anchor.cpp @@ -0,0 +1,2 @@ +void PULPMCAsmInfo :: anchor ( ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmInfo/getExprForFDESymbol.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmInfo/getExprForFDESymbol.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f4832ffbee13bafe8b43783032c374f57e2f1079 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/AsmInfo/getExprForFDESymbol.cpp @@ -0,0 +1,7 @@ +const MCExpr * PULPMCAsmInfo :: getExprForFDESymbol ( const MCSymbol * Sym , unsigned Encoding , MCStreamer & Streamer ) const { +if ( Encoding & dwarf :: DW_EH_PE_pcrel ) { +MCContext & Ctx = Streamer . getContext ( ) ; +return PULPMCExpr :: create ( MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_PULP_None , Ctx ) , PULPMCExpr :: VK_32_PCREL , Ctx ) ; +} +return MCAsmInfo :: getExprForFDESymbol ( Sym , Encoding , Streamer ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/BaseInfo/ABI.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/BaseInfo/ABI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..344e5390354582b3fcc0654dedcf88d18f31172b --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/BaseInfo/ABI.cpp @@ -0,0 +1,10 @@ +enum ABI { +ABI_ILP32 , +ABI_ILP32F , +ABI_ILP32D , +ABI_ILP32E , +ABI_LP64 , +ABI_LP64F , +ABI_LP64D , +ABI_Unknown +} ; \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/BaseInfo/FenceField.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/BaseInfo/FenceField.cpp new file mode 100644 index 0000000000000000000000000000000000000000..951b42ade0ebffe40b0910851cdb0d179096c57e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/BaseInfo/FenceField.cpp @@ -0,0 +1,6 @@ +enum FenceField { +I = 8 , +O = 4 , +R = 2 , +W = 1 +} ; \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/BaseInfo/II.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/BaseInfo/II.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f22e5d241f5349952f05b0f4da6faa973010d741 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/BaseInfo/II.cpp @@ -0,0 +1,53 @@ +namespace PULPII { +enum { +InstFormatPseudo = 0 , +InstFormatR = 1 , +InstFormatR4 = 2 , +InstFormatI = 3 , +InstFormatS = 4 , +InstFormatB = 5 , +InstFormatU = 6 , +InstFormatJ = 7 , +InstFormatCR = 8 , +InstFormatCI = 9 , +InstFormatCSS = 10 , +InstFormatCIW = 11 , +InstFormatCL = 12 , +InstFormatCS = 13 , +InstFormatCA = 14 , +InstFormatCB = 15 , +InstFormatCJ = 16 , +InstFormatOther = 17 , +InstFormatMask = 31 , +ConstraintShift = 5 , +ConstraintMask = 0b111 << ConstraintShift , +VLMulSh ConstraintShift = 3 , +VLMulMask = 0b111 << VLMulShift , +HasDummyMaskOpShift = VLMulShift + 3 , +HasDummyMaskOpMask = 1 << HasDummyMaskOpShift , +WritesElement0Shift HasDummyMaskOpShift + 1 , +WritesElement0Mask = 1 << WritesElement0Shift , +HasMergeOpShift = WritesElement0Shift + 1 , +HasMergeOpMask = 1 << HasMergeOpShift , +HasSEWOpShift = HasSEWOpShift + 1 , +HasSEWOpMask = 1 << HasSEWOpShift , +HasVLOpShift = HasSEWOpShift + 1 , +HasVLOpMask = 1 << HasVLOpShift , +} ; +enum { +MO_None = 0 , +MO_CALL = 1 , +MO_PLT = 2 , +MO_LO = 3 , +MO_HI = 4 , +MO_PCREL_LO = 5 , +MO_PCREL_HI = 6 , +MO_GOT_HI = 7 , +MO_TPREL_LO = 8 , +MO_TPREL_HI = 9 , +MO_TPREL_ADD = 10 , +MO_TLS_GOT_HI = 11 , +MO_TLS_GD_HI = 12 , +MO_DIRECT_FLAG_MASK = 15 +} ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/BaseInfo/OperandType.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/BaseInfo/OperandType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..81022c53abe76556935172dc05a22c93030da9e5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/BaseInfo/OperandType.cpp @@ -0,0 +1,12 @@ +enum OperandType : unsigned { +OPERAND_FIRST_PULP_IMM = MCOI :: OPERAND_FIRST_TARGET , +OPERAND_UIMM4 = OPERAND_FIRST_PULP_IMM , +OPERAND_UIMM5 , +OPERAND_UIMM12 , +OPERAND_UIMM12M1 , +OPERAND_UIMM3 , +OPERAND_SIMM12 , +OPERAND_UIMM20 , +OPERAND_UIMMLOG2XLEN , +OPERAND_LAST_PULP_IMM OPERAND_UIMMLOG2XLEN +} ; \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/BaseInfo/RISCVVSEW.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/BaseInfo/RISCVVSEW.cpp new file mode 100644 index 0000000000000000000000000000000000000000..60795532f533987057867755321e75674abc3a2a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/BaseInfo/RISCVVSEW.cpp @@ -0,0 +1,10 @@ +enum class PULPVSEW { +SEW_8 = 0 , +SEW_16 , +SEW_32 , +SEW_64 , +SEW_128 , +SEW_256 , +SEW_512 , +SEW_1024 , +} ; \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/BaseInfo/RVVConstraintType.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/BaseInfo/RVVConstraintType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..04397cb26419a3b482dac55f78f74f9f2246284c --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/BaseInfo/RVVConstraintType.cpp @@ -0,0 +1,6 @@ +enum RVVConstraintType { +NoConstraint = 0 , +VS2Constraint = 0b001 , +VS1Constraint = 0b010 , +VMConstraint = 0b100 +} ; \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/BaseInfo/RoundingMode.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/BaseInfo/RoundingMode.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cea4c4f62e6b6477a15b997dfeb3942a5b63578a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/BaseInfo/RoundingMode.cpp @@ -0,0 +1,9 @@ +enum RoundingMode { +RNE = 0 , +RTZ = 1 , +RDN = 2 , +RUP = 3 , +RMM = 4 , +DYN = 7 , +Invalid +} ; \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/BaseInfo/VLMUL.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/BaseInfo/VLMUL.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d4bdd002834cf184de3a3cb1c9c0ed536f658020 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/BaseInfo/VLMUL.cpp @@ -0,0 +1,10 @@ +enum class PULPVLMUL { +LMUL_1 = 0 , +LMUL_2 , +LMUL_4 , +LMUL_8 , +LMUL_RESERVED , +LMUL_F8 , +LMUL_F4 , +LMUL_F2 +} ; \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/BaseInfo/VMTs.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/BaseInfo/VMTs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..98d11433e43d425ab972f7677297c9063fba5103 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/BaseInfo/VMTs.cpp @@ -0,0 +1,37 @@ +enum PULPVMVTs { +vint8mf8_t = MVT :: nxv1i8 , +vint8mf4_t = MVT :: nxv2i8 , +vint8mf2_t = MVT :: nxv4i8 , +vint8m1_t = MVT :: nxv8i8 , +vint8m2_t = MVT :: nxv16i8 , +vint8m4_t = MVT :: nxv32i8 , +vint8m8_t = MVT :: nxv64i8 , +vint16mf4_t = MVT :: nxv1i16 , +vint16mf2_t = MVT :: nxv2i16 , +vint16m1_t = MVT :: nxv4i16 , +vint16m2_t = MVT :: nxv8i16 , +vint16m4_t = MVT :: nxv16i16 , +vint16m8_t = MVT :: nxv32i16 , +vint32mf2_t = MVT :: nxv1i32 , +vint32m1_t = MVT :: nxv2i32 , +vint32m2_t = MVT :: nxv4i32 , +vint32m4_t = MVT :: nxv8i32 , +vint32m8_t = MVT :: nxv16i32 , +vint64m1_t = MVT :: nxv1i64 , +vint64m2_t = MVT :: nxv2i64 , +vint64m4_t = MVT :: nxv4i64 , +vint64m8_t = MVT :: nxv8i64 , +vfloat16mf4_t = MVT :: nxv1f16 , +vfloat16mf2_t = MVT :: nxv2f16 , +vfloat16m1_t = MVT :: nxv4f16 , +vfloat16m2_t = MVT :: nxv8f16 , +vfloat16m4_t = MVT :: nxv16f16 , +vfloat16m8_t = MVT :: nxv32f16 , +vfloat32mf2_t = MVT :: nxv1f32 , +vfloat32m1_t = MVT :: nxv2f32 , +vfloat32m2_t = MVT :: nxv4f32 , +vfloat32m4_t = MVT :: nxv8f32 , +vfloat32m8_t = MVT :: nxv16f32 , +vfloat64m1_t = MVT :: nxv1f64 , +vfloat64m2_t = +} ; \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/BaseInfo/computeTargetABI.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/BaseInfo/computeTargetABI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5fa52e122725f782f792aeda1fe915f7677e6699 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/BaseInfo/computeTargetABI.cpp @@ -0,0 +1,14 @@ +ABI computeTargetABI ( const Triple & TT , FeatureBitset FeatureBits , StringRef ABIName ) { +auto TargetABI = getTargetABI ( ABIName ) ; +if ( ! ABIName . empty ( ) ) { +if ( TT . isPULP64 ( ) ) { +TargetABI = PULPABIInfo :: N64 ( ) ; +} +} +if ( ! ABIName . empty ( ) ) { +if ( ! TT . isPULP64 ( ) ) { +TargetABI = PULPABIInfo :: O32 ( ) ; +} +} +return TargetABI ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/BaseInfo/getTargetABI.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/BaseInfo/getTargetABI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b2a6bf078a014887a1743d788e548c67a7b2b39c --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/BaseInfo/getTargetABI.cpp @@ -0,0 +1,24 @@ +ABI getTargetABI ( StringRef Str ) { +if ( Str == "ilp32" ) { +return ABI_ILP32 ; +} +if ( Str == "ilp32f" ) { +return ABI_ILP32F ; +} +if ( Str == "ilp32d" ) { +return ABI_ILP32D ; +} +if ( Str == "ilp32e" ) { +return ABI_ILP32E ; +} +if ( Str == "lp64" ) { +return ABI_LP64 ; +} +if ( Str == "lp64f" ) { +return ABI_LP64F ; +} +if ( Str == "lp64d" ) { +return ABI_LP64D ; +} +return ABI_Unknown ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/BaseInfo/roundingModeToString.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/BaseInfo/roundingModeToString.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b5a29d5669cb6dd2ed9319eab5aa4efe3242354a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/BaseInfo/roundingModeToString.cpp @@ -0,0 +1,21 @@ +inline static StringRef roundingModeToString ( RoundingMode RndMod ) { +if ( RndMod == PULPFPRndMode::RNE ) { +return "rne" ; +} +if ( RndMod == PULPFPRndMode::RTZ ) { +return "rtz" ; +} +if ( RndMod == PULPFPRndMode::RDN ) { +return "rdn" ; +} +if ( RndMod == PULPFPRndMode::RUP ) { +return "rup" ; +} +if ( RndMod == PULPFPRndMode::RMM ) { +return "rmm" ; +} +if ( RndMod == PULPFPRndMode::DYN ) { +return "dyn" ; +} +llvm_unreachable ( "Unknown floating point rounding mode" ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/BaseInfo/stringToRoundingMode.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/BaseInfo/stringToRoundingMode.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0d7efba8ca0b44081f153ed729c2568ae08eb4dc --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/BaseInfo/stringToRoundingMode.cpp @@ -0,0 +1,21 @@ +inline static RoundingMode stringToRoundingMode ( StringRef Str ) { +if ( Str == "rne" ) { +return PULPFPRndMode::RNE ; +} +if ( Str == "rtz" ) { +return PULPFPRndMode::RTZ ; +} +if ( Str == "rdn" ) { +return PULPFPRndMode::RDN ; +} +if ( Str == "rup" ) { +return PULPFPRndMode::RUP ; +} +if ( Str == "rmm" ) { +return PULPFPRndMode::RMM ; +} +if ( Str == "dyn" ) { +return PULPFPRndMode::DYN ; +} +return PULPFPRndMode::Invalid ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/BaseInfo/validate.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/BaseInfo/validate.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f87f8d9df4e6e209200b63471299274b467fe694 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/BaseInfo/validate.cpp @@ -0,0 +1,7 @@ +void validate ( const Triple & TT , const FeatureBitset & FeatureBits ) { +if ( ! isABI_O32 ( ) ) { +if ( ! useOddSPReg ( ) ) { +report_fatal_error ( "RV32E can't be enabled for an RV64 target" ) ; +} +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFObjectWriter/ELFObjectWriter.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFObjectWriter/ELFObjectWriter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..31b98b689bb4bf72c473a700cc253fe257144423 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFObjectWriter/ELFObjectWriter.cpp @@ -0,0 +1,2 @@ +PULPELFObjectWriter :: PULPELFObjectWriter ( uint8_t OSABI , bool Is64Bit ) : MCELFObjectTargetWriter ( Is64Bit , OSABI , EM_PULP , true ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFObjectWriter/createELFObjectWriter.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFObjectWriter/createELFObjectWriter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..96abdde135d390a814ad80404beecf995840dd7c --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFObjectWriter/createELFObjectWriter.cpp @@ -0,0 +1,3 @@ +std :: unique_ptr < MCObjectTargetWriter > llvm :: createPULPELFObjectWriter ( uint8_t OSABI , bool Is64Bit ) { +return std :: make_unique < PULPELFObjectWriter > ( OSABI , Is64Bit ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFObjectWriter/getRelocType.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFObjectWriter/getRelocType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..59566baccf9d3c6f1e46dd012c8dc3f7584dd504 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFObjectWriter/getRelocType.cpp @@ -0,0 +1,140 @@ +unsigned PULPELFObjectWriter :: getRelocType ( MCContext & Ctx , const MCValue & Target , const MCFixup & Fixup , bool IsPCRel ) const { +const PULPMCExpr * SExpr ; +if ( SExpr = dyn_cast < PULPMCExpr > ( Fixup . getValue ( ) ) ) { +if ( SExpr -> getKind ( ) == PULPMCExpr :: VK_32_PCREL ) { +return ELF :: R_PULP_32_PCREL ; +} +} +const MCExpr * Expr ; +Expr = Fixup . getValue ( ) ; +unsigned Kind ; +Kind = Fixup . getTargetKind ( ) ; +if ( Kind >= FirstLiteralRelocationKind ) { +return Kind - FirstLiteralRelocationKind ; +} +if ( IsPCRel ) { +if ( Kind == FK_PCRel_4 ) { +return ELF :: R_PULP_32_PCREL ; +} +if ( Kind == PULP :: fixup_PULP_pcrel_hi20 ) { +return ELF :: R_PULP_PCREL_HI20 ; +} +if ( Kind == PULP :: fixup_PULP_pcrel_lo12_i ) { +return ELF :: R_PULP_PCREL_LO12_I ; +} +if ( Kind == PULP :: fixup_PULP_pcrel_lo12_s ) { +return ELF :: R_PULP_PCREL_LO12_S ; +} +if ( Kind == FK_Data_4 ) { +return ELF :: R_PULP_32_PCREL ; +} +if ( Kind == PULP :: fixup_PULP_got_hi20 ) { +return ELF :: R_PULP_GOT_HI20 ; +} +if ( Kind == PULP :: fixup_PULP_tls_got_hi20 ) { +return ELF :: R_PULP_TLS_GOT_HI20 ; +} +if ( Kind == PULP :: fixup_PULP_tls_gd_hi20 ) { +return ELF :: R_PULP_TLS_GD_HI20 ; +} +if ( Kind == PULP :: fixup_PULP_jal ) { +return ELF :: R_PULP_JAL ; +} +if ( Kind == PULP :: fixup_PULP_branch ) { +return ELF :: R_PULP_BRANCH ; +} +if ( Kind == PULP :: fixup_PULP_rvc_jump ) { +return ELF :: R_PULP_RVC_JUMP ; +} +if ( Kind == PULP :: fixup_PULP_rvc_branch ) { +return ELF :: R_PULP_RVC_BRANCH ; +} +if ( Kind == PULP :: fixup_PULP_call ) { +return ELF :: R_PULP_CALL ; +} +if ( Kind == PULP :: fixup_PULP_call_plt ) { +return ELF :: R_PULP_CALL_PLT ; +} +if ( Kind == PULP :: fixup_PULP_loop_setup ) { +return ELF :: R_PULP_LOOP_SETUP ; +} +if ( Kind == PULP :: fixup_PULP_loop_setupi ) { +return ELF :: R_PULP_LOOP_SETUPI ; +} +Ctx . reportError ( Fixup . getLoc ( ) , "Unsupported relocation type" ) ; +return ELF :: R_PULP_NONE ; +} +if ( Kind == FK_Data_4 ) { +return ELF :: R_PULP_32 ; +} +if ( Kind == FK_Data_8 ) { +return ELF :: R_PULP_64 ; +} +if ( Kind == FK_Data_Add_1 ) { +return ELF :: R_PULP_ADD8 ; +} +if ( Kind == FK_Data_Add_2 ) { +return ELF :: R_PULP_ADD16 ; +} +if ( Kind == FK_Data_Add_4 ) { +return ELF :: R_PULP_ADD32 ; +} +if ( Kind == FK_Data_Add_8 ) { +return ELF :: R_PULP_ADD64 ; +} +if ( Kind == FK_Data_1 ) { +Ctx . reportError ( Fixup . getLoc ( ) , "1-byte data relocations not supported" ) ; +return ELF :: R_PULP_NONE ; +} +if ( Kind == FK_Data_2 ) { +Ctx . reportError ( Fixup . getLoc ( ) , "2-byte data relocations not supported" ) ; +return ELF :: R_PULP_NONE ; +} +if ( Kind == FK_Data_Add_6b ) { +return ELF :: R_PULP_SET6 ; +} +if ( Kind == FK_Data_Sub_1 ) { +return ELF :: R_PULP_SUB8 ; +} +if ( Kind == FK_Data_Sub_2 ) { +return ELF :: R_PULP_SUB16 ; +} +if ( Kind == FK_Data_Sub_4 ) { +return ELF :: R_PULP_SUB32 ; +} +if ( Kind == FK_Data_Sub_8 ) { +return ELF :: R_PULP_SUB64 ; +} +if ( Kind == FK_Data_Sub_6b ) { +return ELF :: R_PULP_SUB6 ; +} +if ( Kind == PULP :: fixup_PULP_hi20 ) { +return ELF :: R_PULP_HI20 ; +} +if ( Kind == PULP :: fixup_PULP_lo12_i ) { +return ELF :: R_PULP_LO12_I ; +} +if ( Kind == PULP :: fixup_PULP_lo12_s ) { +return ELF :: R_PULP_LO12_S ; +} +if ( Kind == PULP :: fixup_PULP_tprel_hi20 ) { +return ELF :: R_PULP_TPREL_HI20 ; +} +if ( Kind == PULP :: fixup_PULP_tprel_lo12_i ) { +return ELF :: R_PULP_TPREL_LO12_I ; +} +if ( Kind == PULP :: fixup_PULP_tprel_lo12_s ) { +return ELF :: R_PULP_TPREL_LO12_S ; +} +if ( Kind == PULP :: fixup_PULP_tprel_add ) { +return ELF :: R_PULP_TPREL_ADD ; +} +if ( Kind == PULP :: fixup_PULP_relax ) { +return ELF :: R_PULP_RELAX ; +} +if ( Kind == PULP :: fixup_PULP_align ) { +return ELF :: R_PULP_ALIGN ; +} +Ctx . reportError ( Fixup . getLoc ( ) , "Unsupported relocation type" ) ; +return ELF :: R_PULP_NONE ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFObjectWriter/needsRelocateWithSymbol.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFObjectWriter/needsRelocateWithSymbol.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d32e5d47cdf21c903c9c0bba5ef56efc3a118a62 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFObjectWriter/needsRelocateWithSymbol.cpp @@ -0,0 +1,3 @@ +bool needsRelocateWithSymbol ( const MCSymbol & Sym , unsigned Type ) const override { +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFObjectWriter/~ELFObjectWriter.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFObjectWriter/~ELFObjectWriter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d37d2a9a3430b7b74a6df173422d63f3e6907b5e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFObjectWriter/~ELFObjectWriter.cpp @@ -0,0 +1,2 @@ +PULPELFObjectWriter :: ~ PULPELFObjectWriter ( ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/AttributeItem.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/AttributeItem.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5d4a8b8d43739a9660b269fe60e4c13f60b08b9e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/AttributeItem.cpp @@ -0,0 +1,6 @@ +struct AttributeItem { +AttributeType Type ; +unsigned Tag ; +unsigned IntValue ; +std :: string StringValue ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/AttributeType.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/AttributeType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..11e84b4eac2ba89f7bac001f476bce2df9b96af0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/AttributeType.cpp @@ -0,0 +1,6 @@ +enum class AttributeType { +Hidden , +Numeric , +Text , +NumericAndText +} ; \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/TargetELFStreamer.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/TargetELFStreamer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d6ffeb56d67ab3455936bd2c17aba9404b381714 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/TargetELFStreamer.cpp @@ -0,0 +1,21 @@ +PULPTargetELFStreamer :: PULPTargetELFStreamer ( MCStreamer & S , const MCSubtargetInfo & STI ) : PULPTargetStreamer ( S ) , CurrentVendor ( "PULP" ) { +MCAssembler & MCA ; +MCA = getStreamer ( ) . getAssembler ( ) ; +const FeatureBitset & Features ; +Features = STI . getFeatureBits ( ) ; +PULPMCAsmBackend & MAB ; +MAB = static_cast < PULPMCAsmBackend & > ( MCA . getBackend ( ) ) ; +unsigned EFlags ; +EFlags = MCA . getELFHeaderEFlags ( ) ; +PULPABI :: ABI ABI ; +ABI = MAB . getTargetABI ( ) ; +if ( Features [ PULP :: FeatureStdExtC ] ) { +EFlags = EFlags | ELF :: EF_PULP_RVC ; +} +EFlags = EFlags | ELF :: EF_PULP_FLOAT_ABI_SINGLE ; +EFlags = EFlags | ELF :: EF_PULP_FLOAT_ABI_SINGLE ; +EFlags = EFlags | ELF :: EF_PULP_FLOAT_ABI_DOUBLE ; +EFlags = EFlags | ELF :: EF_PULP_FLOAT_ABI_DOUBLE ; +EFlags = EFlags | ELF :: EF_PULP_RVE ; +MCA . setELFHeaderEFlags ( EFlags ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/calculateContentSize.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/calculateContentSize.cpp new file mode 100644 index 0000000000000000000000000000000000000000..08de53c9fe56e417a8349d0c5fa70b3e08d95553 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/calculateContentSize.cpp @@ -0,0 +1,29 @@ +size_t PULPTargetELFStreamer :: calculateContentSize ( ) const { +size_t Result ; +Result = 0 ; +size_t i ; +for ( i = 0 ; i < Contents . size ( ) ; ++ i ) { +AttributeItem item ; +item = Contents [ i ] ; +if ( item . Type == AttributeType :: Hidden ) { +continue ; +} +if ( item . Type == AttributeType :: Numeric ) { +Result = Result + getULEB128Size ( item . Tag ) ; +Result = Result + getULEB128Size ( item . IntValue ) ; +continue ; +} +if ( item . Type == AttributeType :: Text ) { +Result = Result + getULEB128Size ( item . Tag ) ; +Result = Result + item . StringValue . size ( ) + 1 ; +continue ; +} +if ( item . Type == AttributeType :: NumericAndText ) { +Result = Result + getULEB128Size ( item . Tag ) ; +Result = Result + getULEB128Size ( item . IntValue ) ; +Result = Result + item . StringValue . size ( ) + 1 ; +continue ; +} +} +return Result ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/emitAttribute.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/emitAttribute.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c7fa743543411a5977b60fa062cf6e12b4ee33d4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/emitAttribute.cpp @@ -0,0 +1,3 @@ +void PULPTargetELFStreamer :: emitAttribute ( unsigned Attribute , unsigned Value ) { +setAttributeItem ( Attribute , Value , true ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionNoPIC.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionNoPIC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3769c6f75dd7bc54169267ec548d0453b6f7f763 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionNoPIC.cpp @@ -0,0 +1,2 @@ +void PULPTargetELFStreamer :: emitDirectiveOptionNoPIC ( ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionNoRVC.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionNoRVC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..84ec457f710e910bb12e66f4e8a98d76f956a02a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionNoRVC.cpp @@ -0,0 +1,2 @@ +void PULPTargetELFStreamer :: emitDirectiveOptionNoRVC ( ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionNoRelax.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionNoRelax.cpp new file mode 100644 index 0000000000000000000000000000000000000000..47958aef573e44aeefbdbde61ca93eb3f74edcc1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionNoRelax.cpp @@ -0,0 +1,2 @@ +void PULPTargetELFStreamer :: emitDirectiveOptionNoRelax ( ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionPIC.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionPIC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..27cc3f4e2fe15ab1f05486c4968af4010a8d2dea --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionPIC.cpp @@ -0,0 +1,2 @@ +void PULPTargetELFStreamer :: emitDirectiveOptionPIC ( ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionPop.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionPop.cpp new file mode 100644 index 0000000000000000000000000000000000000000..efc9d5cdd85d07c80e8f66a6356960f35ac3856b --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionPop.cpp @@ -0,0 +1,2 @@ +void PULPTargetELFStreamer :: emitDirectiveOptionPop ( ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionPush.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionPush.cpp new file mode 100644 index 0000000000000000000000000000000000000000..09c011e895ba357df2479b477aaf333135f09d7f --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionPush.cpp @@ -0,0 +1,2 @@ +void PULPTargetELFStreamer :: emitDirectiveOptionPush ( ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionRVC.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionRVC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0f1743ee6a9af4393a9e93565374c9e7b65a2ec6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionRVC.cpp @@ -0,0 +1,2 @@ +void PULPTargetELFStreamer :: emitDirectiveOptionRVC ( ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionRelax.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionRelax.cpp new file mode 100644 index 0000000000000000000000000000000000000000..17216e8388da5bf43be1a21db1fcb309f2ce1664 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/emitDirectiveOptionRelax.cpp @@ -0,0 +1,2 @@ +void PULPTargetELFStreamer :: emitDirectiveOptionRelax ( ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/emitIntTextAttribute.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/emitIntTextAttribute.cpp new file mode 100644 index 0000000000000000000000000000000000000000..930bb8773438fab381a82a9889a3af706517d5b6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/emitIntTextAttribute.cpp @@ -0,0 +1,3 @@ +void PULPTargetELFStreamer :: emitIntTextAttribute ( unsigned Attribute , unsigned IntValue , StringRef StringValue ) { +setAttributeItems ( Attribute , IntValue , StringValue , true ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/emitTextAttribute.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/emitTextAttribute.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0cb2883fb06e2a7c3f8eccd4300cab832cebd8da --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/emitTextAttribute.cpp @@ -0,0 +1,3 @@ +void PULPTargetELFStreamer :: emitTextAttribute ( unsigned Attribute , StringRef String ) { +setAttributeItem ( Attribute , String , true ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/finishAttributeSection.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/finishAttributeSection.cpp new file mode 100644 index 0000000000000000000000000000000000000000..31dc2186b1f11826efd699f17003eb2e96f78284 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/finishAttributeSection.cpp @@ -0,0 +1,45 @@ +void PULPTargetELFStreamer :: finishAttributeSection ( ) { +if ( Contents . empty ( ) ) { +return ; +} +MCELFStreamer & Streamer = getStreamer ( ) ; +if ( AttributeSection ) { +Streamer . SwitchSection ( AttributeSection ) ; +} +if ( ! AttributeSection ) { +AttributeSection = Streamer . getContext ( ) . getELFSection ( ".PULP_lower.attributes" , ELF :: SHT_PULP_ATTRIBUTES , 0 ) ; +Streamer . SwitchSection ( AttributeSection ) ; +Streamer . emitInt8 ( ELFAttrs :: Format_Version ) ; +} +const size_t VendorHeaderSize = 4 + CurrentVendor . size ( ) + 1 ; +const size_t TagHeaderSize = 1 + 4 ; +const size_t ContentsSize = calculateContentSize ( ) ; +Streamer . emitInt32 ( VendorHeaderSize + TagHeaderSize + ContentsSize ) ; +Streamer . emitBytes ( CurrentVendor ) ; +Streamer . emitInt8 ( 0 ) ; +Streamer . emitInt8 ( ELFAttrs :: File ) ; +Streamer . emitInt32 ( TagHeaderSize + ContentsSize ) ; +size_t i ; +for ( i = 0 ; i < Contents . size ( ) ; ++ i ) { +AttributeItem item ; +item = Contents [ i ] ; +Streamer . emitULEB128IntValue ( item . Tag ) ; +if ( item . Type == AttributeType :: Numeric ) { +Streamer . emitULEB128IntValue ( item . IntValue ) ; +continue ; +} +if ( item . Type == AttributeType :: Text ) { +Streamer . emitBytes ( item . StringValue ) ; +Streamer . emitInt8 ( 0 ) ; +continue ; +} +if ( item . Type == AttributeType :: NumericAndText ) { +Streamer . emitULEB128IntValue ( item . IntValue ) ; +Streamer . emitBytes ( item . StringValue ) ; +Streamer . emitInt8 ( 0 ) ; +continue ; +} +llvm_unreachable ( "Invalid attribute type" ) ; +} +Contents . clear ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/getAttributeItem.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/getAttributeItem.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b4c4f3a04f8aff4a632364d2dd166a8131e8ce0a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/getAttributeItem.cpp @@ -0,0 +1,9 @@ +AttributeItem * getAttributeItem ( unsigned Attribute ) { +size_t i ; +for ( i = 0 ; i < Contents . size ( ) ; ++ i ) { +if ( Contents [ i ] . Tag == Attribute ) { +return & Contents [ i ] ; +} +} +return nullptr ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/getStreamer.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/getStreamer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4092dca19a88ce96bff6ea03fbfbed16ffbc16b2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/getStreamer.cpp @@ -0,0 +1,3 @@ +MCELFStreamer & PULPTargetELFStreamer :: getStreamer ( ) { +return static_cast < MCELFStreamer & > ( Streamer ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/setAttributeItem1.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/setAttributeItem1.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4226193c148e049fab7718f81ce0f0309e9557d9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/setAttributeItem1.cpp @@ -0,0 +1,12 @@ +void setAttributeItem ( unsigned Attribute , unsigned Value , bool OverwriteExisting ) { +AttributeItem * Item ; +if ( Item = getAttributeItem ( Attribute ) ) { +if ( ! OverwriteExisting ) { +return ; +} +Item -> Type = AttributeType :: Numeric ; +Item -> IntValue = Value ; +return ; +} +Contents . push_back ( { AttributeType :: Numeric , Attribute , Value , "" } ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/setAttributeItem2.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/setAttributeItem2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b05a1b3223da60321ec2a64b1c6e99126cbe4e0e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/setAttributeItem2.cpp @@ -0,0 +1,12 @@ +void setAttributeItem ( unsigned Attribute , StringRef Value , bool OverwriteExisting ) { +AttributeItem * Item ; +if ( Item = getAttributeItem ( Attribute ) ) { +if ( ! OverwriteExisting ) { +return ; +} +Item -> Type = AttributeType :: Text ; +Item -> StringValue = std :: string ( Value ) ; +return ; +} +Contents . push_back ( { AttributeType :: Text , Attribute , 0 , std :: string ( Value ) } ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/setAttributeItems.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/setAttributeItems.cpp new file mode 100644 index 0000000000000000000000000000000000000000..52f682e8808f82b0ac277c275f668b743d449d66 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/ELFStreamer/setAttributeItems.cpp @@ -0,0 +1,13 @@ +void setAttributeItems ( unsigned Attribute , unsigned IntValue , StringRef StringValue , bool OverwriteExisting ) { +AttributeItem * Item ; +if ( Item = getAttributeItem ( Attribute ) ) { +if ( ! OverwriteExisting ) { +return ; +} +Item -> Type = AttributeType :: NumericAndText ; +Item -> IntValue = IntValue ; +Item -> StringValue = std :: string ( StringValue ) ; +return ; +} +Contents . push_back ( { AttributeType :: NumericAndText , Attribute , IntValue , std :: string ( StringValue ) } ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/FixupKind/enumFixups.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/FixupKind/enumFixups.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ab953719246e1e37356da491ec2593fd0d4f512a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/FixupKind/enumFixups.cpp @@ -0,0 +1,27 @@ +enum Fixups { +fixup_PULP_hi20 = FirstTargetFixupKind , +fixup_PULP_lo12_i , +fixup_PULP_lo12_s , +fixup_PULP_pcrel_hi20 , +fixup_PULP_pcrel_lo12_i , +fixup_PULP_pcrel_lo12_s , +fixup_PULP_got_hi20 , +fixup_PULP_tprel_hi20 , +fixup_PULP_tprel_lo12_i , +fixup_PULP_tprel_lo12_s , +fixup_PULP_tprel_add , +fixup_PULP_tls_got_hi20 , +fixup_PULP_tls_gd_hi20 , +fixup_PULP_jal , +fixup_PULP_branch , +fixup_PULP_rvc_jump , +fixup_PULP_rvc_branch , +fixup_PULP_call , +fixup_PULP_call_plt , +fixup_PULP_relax , +fixup_PULP_align , +fixup_PULP_loop_setup , +fixup_PULP_loop_setupi , +fixup_PULP_invalid , +NumTargetFixupKinds = fixup_PULP_invalid - FirstTargetFixupKind +} ; \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/InstPrinter/InstPrinter.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/InstPrinter/InstPrinter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e1d69105062c1831a018759c97d868f47f55e4b1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/InstPrinter/InstPrinter.cpp @@ -0,0 +1,2 @@ +PULPInstPrinter ( const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) : MCInstPrinter ( MAI , MII , MRI ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/InstPrinter/applyTargetSpecificCLOption.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/InstPrinter/applyTargetSpecificCLOption.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6ad9b15ac504f9456567f7c0675eccc063e1aa67 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/InstPrinter/applyTargetSpecificCLOption.cpp @@ -0,0 +1,11 @@ +bool PULPInstPrinter :: applyTargetSpecificCLOption ( StringRef Opt ) { +if ( Opt == "numeric" ) { +ArchRegNames = true ; +return true ; +} +if ( Opt == "no-aliases" ) { +NoAliases = true ; +return true ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/InstPrinter/getRegisterName.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/InstPrinter/getRegisterName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8d808eac711fb43d43bf4ea48e63661d71474b52 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/InstPrinter/getRegisterName.cpp @@ -0,0 +1,3 @@ +const char * PULPInstPrinter :: getRegisterName ( unsigned RegNo ) { +return getRegisterName ( RegNo , ArchRegNames ? PULP :: NoRegAltName : PULP :: ABIRegAltName ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/InstPrinter/printAtomicMemOp.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/InstPrinter/printAtomicMemOp.cpp new file mode 100644 index 0000000000000000000000000000000000000000..360edebaf959d336e884373e92a4e2f964841fc8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/InstPrinter/printAtomicMemOp.cpp @@ -0,0 +1,10 @@ +void PULPInstPrinter :: printAtomicMemOp ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { +const MCOperand & Op1 ; +Op1 = MI -> getOperand ( OpNo ) ; +const MCOperand & Op2 ; +Op2 = MI -> getOperand ( OpNo + 1 ) ; +OS << ")" ; +printRegName ( O , Op1 . getReg ( ) ) ; +unsigned Offset ; +OS << ")" ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/InstPrinter/printBranchOperand.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/InstPrinter/printBranchOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8c5935f45d4d64c9da042e07014a80001e475433 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/InstPrinter/printBranchOperand.cpp @@ -0,0 +1,17 @@ +void PULPInstPrinter :: printBranchOperand ( const MCInst * MI , uint64_t Address , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & OS ) { +const MCOperand & MO = MI -> getOperand ( OpNo ) ; +if ( ! MO . isImm ( ) ) { +return printOperand ( MI , OpNo , STI , OS ) ; +} +if ( PrintBranchImmAsAddress ) { +uint64_t Target ; +Target = Address + MO . getImm ( ) ; +if ( ! STI . hasFeature ( PULP :: Feature64Bit ) ) { +Target = Target & 0xffffffff ; +} +OS << formatHex ( Target ) ; +} +if ( ! PrintBranchImmAsAddress ) { +OS << MO . getImm ( ) ; +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/InstPrinter/printCSRSystemRegister.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/InstPrinter/printCSRSystemRegister.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f49beac7b1f755ebdcef233aabddbefa6c9576f0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/InstPrinter/printCSRSystemRegister.cpp @@ -0,0 +1,16 @@ +void PULPInstPrinter :: printCSRSystemRegister ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { +unsigned Val ; +Val = MI -> getOperand ( OpNo ) . getImm ( ) ; +return ; +const SysReg :: SysReg * Reg ; +Reg = SysReg :: lookupSysRegByEncoding ( Val ) ; +if ( Reg ) { +if ( Reg -> haveRequiredFeatures ( STI . getFeatureBits ( ) ) ) { +OS << Reg -> Name ; +} +} +if ( ! Reg ) { +return ; +if ( ! Reg -> haveRequiredFeatures ( STI . getFeatureBits ( ) ) ) { +return ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/InstPrinter/printFRMArg.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/InstPrinter/printFRMArg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0dd8cc5dee2138ccd45c2158ad2d3fdd5070ff87 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/InstPrinter/printFRMArg.cpp @@ -0,0 +1,4 @@ +void PULPInstPrinter :: printFRMArg ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { +auto FRMArg = MI -> getOperand ( OpNo ) . getImm ( ) ; +OS << FPRndMode :: roundingModeToString ( MO . getImm ( ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/InstPrinter/printFenceArg.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/InstPrinter/printFenceArg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..425fb947d9e83bfbe88c57a1457f3fcabb2265e0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/InstPrinter/printFenceArg.cpp @@ -0,0 +1,11 @@ +void PULPInstPrinter :: printFenceArg ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { +unsigned FenceArg = MI -> getOperand ( OpNo ) . getImm ( ) ; +assert ( ( FenceArg >> 4 ) == 0 ) && "Invalid immediate in printFenceArg!" ) ; +OS << 'i' ; +OS << 'o' ; +OS << 'r' ; +OS << 'w' ; +if ( FenceArg == 0 ) { +OS << "unknown" ; +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/InstPrinter/printInst.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/InstPrinter/printInst.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b18a6bdb6a25cd30b6d4dd9fdb2073483bfacfb8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/InstPrinter/printInst.cpp @@ -0,0 +1,22 @@ +void PULPInstPrinter :: printInst ( const MCInst * MI , uint64_t Address , StringRef Annot , const MCSubtargetInfo & STI , raw_ostream & O ) { +bool Res ; +Res = false ; +const MCInst * NewMI ; +MCInst UncompressedMI ; +if ( ! printAliasInstr ( MI , STI , O ) ) { +printInstruction ( NewMI , Address , STI , O ) ; +printAnnotation ( O , Annot ) ; +return ; +} +printInstruction ( NewMI , Address , STI , O ) ; +printAnnotation ( O , Annot ) ; +return ; +} +if ( ! printAliasInstr ( NewMI , Address , STI , O ) ) { +printInstruction ( NewMI , Address , STI , O ) ; +printAnnotation ( O , Annot ) ; +return ; +} +printInstruction ( NewMI , Address , STI , O ) ; +printAnnotation ( O , Annot ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/InstPrinter/printOperand.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/InstPrinter/printOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c41c3aeef1a8f4bd68ba6cd15500ce8e8133b2e4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/InstPrinter/printOperand.cpp @@ -0,0 +1,14 @@ +void PULPInstPrinter :: printOperand ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & OS , const char * Modifier ) { +assert ( ( Modifier == 0 || Modifier [ 0 ] == 0 ) && "No modifiers supported" ) ; +const MCOperand & Op = MI -> getOperand ( OpNo ) ; +if ( Op . isReg ( ) ) { +OS << getRegisterName ( Op . getReg ( ) ) ; +return ; +} +if ( Op . isImm ( ) ) { +OS << Op . getImm ( ) ; +return ; +} +assert ( Op . isExpr ( ) && "Unknown operand kind in printOperand" ) ; +Op . getExpr ( ) -> print ( OS , & MAI ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/InstPrinter/printRegName.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/InstPrinter/printRegName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1593b5db251b410e059dd36929f103669af6ce83 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/InstPrinter/printRegName.cpp @@ -0,0 +1,3 @@ +void PULPInstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { +OS << getRegisterName ( RegNo ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/InstPrinter/printVMaskReg.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/InstPrinter/printVMaskReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..91f881764167a81cca17eab6a371d75ac420a4c6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/InstPrinter/printVMaskReg.cpp @@ -0,0 +1,9 @@ +void PULPInstPrinter :: printVMaskReg ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { +const MCOperand & Op1 ; +Op1 = MI -> getOperand ( OpNo ) ; +const MCOperand & Op2 ; +Op2 = MI -> getOperand ( OpNo + 1 ) ; +OS << ", " ; +printRegName ( O , Op1 . getReg ( ) ) ; +OS << ".t" ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/InstPrinter/printVTypeI.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/InstPrinter/printVTypeI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f2b2f53421bc0591e82767a79f3f4d155dfddb1c --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/InstPrinter/printVTypeI.cpp @@ -0,0 +1,5 @@ +void PULPInstPrinter :: printVTypeI ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { +unsigned Imm ; +Imm = MI -> getOperand ( OpNo ) . getImm ( ) ; +PULPVType :: printVType ( Imm , O ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCCodeEmitter/MCCodeEmitter.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCCodeEmitter/MCCodeEmitter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..07fc8b1e5fbecddbec29c534040fb035dcbabbc1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCCodeEmitter/MCCodeEmitter.cpp @@ -0,0 +1,2 @@ +PULPMCCodeEmitter ( MCContext & ctx , MCInstrInfo const & MCII ) : Ctx ( ctx ) , MCII ( MCII ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCCodeEmitter/createMCCodeEmitter.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCCodeEmitter/createMCCodeEmitter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..629ea285de77ecfccb3ac3a92bd074d0415c9c4a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCCodeEmitter/createMCCodeEmitter.cpp @@ -0,0 +1,3 @@ +MCCodeEmitter * llvm :: createPULPMCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , MCContext & Ctx ) { +return new PULPMCCodeEmitter ( Ctx , MCII ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCCodeEmitter/encodeInstruction.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCCodeEmitter/encodeInstruction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..38ab93f798ad2b7e11256ddb1f3361af6ddc7d36 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCCodeEmitter/encodeInstruction.cpp @@ -0,0 +1,50 @@ +void PULPMCCodeEmitter :: encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { +verifyInstructionPredicates ( MI , computeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; +Desc = MCII . get ( MI . getOpcode ( ) ) ; +unsigned Size ; +Size = Desc . getSize ( ) ; +if ( MI . getOpcode ( ) == PULP :: PseudoCALLReg ) { +expand_TLSDESCCALL ( MI , OS , Fixups , STI ) ; +MCNumEmitted = MCNumEmitted + 0 ; +return ; +} +if ( MI . getOpcode ( ) == PULP :: PseudoCALL ) { +expand_CompilerBarrier ( MI , OS , Fixups , STI ) ; +MCNumEmitted = MCNumEmitted + 0 ; +return ; +} +if ( MI . getOpcode ( ) == PULP :: PseudoTAIL ) { +expand_SPACE ( MI , OS , Fixups , STI ) ; +MCNumEmitted = MCNumEmitted + 0 ; +return ; +} +if ( MI . getOpcode ( ) == PULP :: PseudoJump ) { +expand_EH_SjLj_Setup ( MI , OS , Fixups , STI ) ; +MCInst TmpInst ; +uint16_t Binary ; +uint32_t Binary ; +const MCExpr * CallExpr ; +CallExpr = MI . getOperand ( 0 ) . getExpr ( ) ; +TmpInst = MCInstBuilder ( PULP :: JS ) . addImm ( 0 ) ; +TmpInst = MCInstBuilder ( PULP :: J ) . addImm ( - 2 ) ; +Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; +expand_COPY_TO_REGCLASS ( MI , OS , Fixups , STI ) ; +return ; +} +if ( Size == 2 ) { +uint16_t Bits ; +Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ; +support :: endian :: write < uint16_t > ( OS , Bits , support :: little ) ; +MCNumEmitted = MCNumEmitted + 1 ; +return ; +} +if ( Size == 4 ) { +uint32_t Bits ; +Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ; +support :: endian :: write < uint32_t > ( OS , Bits , support :: little ) ; +MCNumEmitted = MCNumEmitted + 1 ; +return ; +} +llvm_unreachable ( "Unhandled encodeInstruction length!" ) ; +MCNumEmitted = MCNumEmitted + 1 ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCCodeEmitter/getImmOpValue.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCCodeEmitter/getImmOpValue.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4881a608bb3ebc8b94add56d8c6c02f1bf3eed23 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCCodeEmitter/getImmOpValue.cpp @@ -0,0 +1,72 @@ +unsigned PULPMCCodeEmitter :: getImmOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { +const MCOperand & MO ; +MO = MI . getOperand ( OpIdx ) ; +if ( MO . isReg ( ) ) { +return Ctx . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) ) ; +} +if ( MO . isImm ( ) ) { +return static_cast < unsigned > ( MO . getImm ( ) ) ; +} +PULP :: Fixups FixupKind ; +FixupKind = PULP :: Fixups ( 0 ) ; +MCExpr :: ExprKind Kind ; +if ( Kind == MCExpr :: Constant ) { +return cast < MCConstantExpr > ( Expr ) -> getValue ( ) ; +} +if ( Kind == MCExpr :: Binary ) { +} +assert ( Kind == MCExpr :: SymbolRef && "unknown MCExpr kind" ) ; +if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == PULPMCExpr :: VK_PULP_LO ) { +FixupKind = PULP :: fixup_PULP_lo12_i ; +Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; +return 0 ; +} +if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == PULPMCExpr :: VK_PULP_HI ) { +FixupKind = PULP :: fixup_PULP_hi20 ; +Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; +return 0 ; +} +if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == PULPMCExpr :: VK_PULP_PCREL_LO ) { +FixupKind = PULP :: fixup_PULP_pcrel_lo12_i ; +Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; +return 0 ; +} +if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == PULPMCExpr :: VK_PULP_PCREL_HI ) { +FixupKind = PULP :: fixup_PULP_pcrel_hi20 ; +Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; +return 0 ; +} +if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == PULPMCExpr :: VK_PULP_GOT_HI ) { +FixupKind = PULP :: fixup_PULP_got_hi20 ; +Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; +return 0 ; +} +if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == PULPMCExpr :: VK_PULP_TPREL_LO ) { +FixupKind = PULP :: fixup_PULP_tprel_lo12_s ; +Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; +return 0 ; +} +if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == PULPMCExpr :: VK_PULP_TPREL_HI ) { +FixupKind = PULP :: fixup_PULP_tprel_hi20 ; +Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; +return 0 ; +} +if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == PULPMCExpr :: VK_PULP_TLS_GOT_HI ) { +FixupKind = PULP :: fixup_PULP_tls_got_hi20 ; +Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; +return 0 ; +} +if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == PULPMCExpr :: VK_PULP_TLS_GD_HI ) { +FixupKind = PULP :: fixup_PULP_tls_gd_hi20 ; +Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; +return 0 ; +} +if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == PULPMCExpr :: VK_PULP_CALL ) { +FixupKind = PULP :: fixup_PULP_call ; +Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; +return 0 ; +} +llvm_unreachable ( "Unknown fixup kind!" ) ; +Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; +return 0 ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCCodeEmitter/getImmOpValueAsr1.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCCodeEmitter/getImmOpValueAsr1.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e6437f2ea306e6313b9b3f2ae411e0de1ec4fd85 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCCodeEmitter/getImmOpValueAsr1.cpp @@ -0,0 +1,72 @@ +unsigned PULPMCCodeEmitter :: getImmOpValueAsr1 ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { +const MCOperand & MO ; +MO = MI . getOperand ( OpIdx ) ; +if ( MO . isReg ( ) ) { +return Ctx . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) ) ; +} +if ( MO . isImm ( ) ) { +return static_cast < unsigned > ( MO . getImm ( ) ) ; +} +PULP :: Fixups FixupKind ; +FixupKind = PULP :: Fixups ( 0 ) ; +MCExpr :: ExprKind Kind ; +if ( Kind == MCExpr :: Constant ) { +return cast < MCConstantExpr > ( Expr ) -> getValue ( ) ; +} +if ( Kind == MCExpr :: Binary ) { +} +assert ( Kind == MCExpr :: SymbolRef && "unknown MCExpr kind" ) ; +if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == PULPMCExpr :: VK_PULP_LO ) { +FixupKind = PULP :: fixup_PULP_lo12_i ; +Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; +return 0 ; +} +if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == PULPMCExpr :: VK_PULP_HI ) { +FixupKind = PULP :: fixup_PULP_hi20 ; +Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; +return 0 ; +} +if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == PULPMCExpr :: VK_PULP_PCREL_LO ) { +FixupKind = PULP :: fixup_PULP_pcrel_lo12_i ; +Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; +return 0 ; +} +if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == PULPMCExpr :: VK_PULP_PCREL_HI ) { +FixupKind = PULP :: fixup_PULP_pcrel_hi20 ; +Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; +return 0 ; +} +if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == PULPMCExpr :: VK_PULP_GOT_HI ) { +FixupKind = PULP :: fixup_PULP_got_hi20 ; +Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; +return 0 ; +} +if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == PULPMCExpr :: VK_PULP_TPREL_LO ) { +FixupKind = PULP :: fixup_PULP_tprel_lo12_s ; +Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; +return 0 ; +} +if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == PULPMCExpr :: VK_PULP_TPREL_HI ) { +FixupKind = PULP :: fixup_PULP_tprel_hi20 ; +Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; +return 0 ; +} +if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == PULPMCExpr :: VK_PULP_TLS_GOT_HI ) { +FixupKind = PULP :: fixup_PULP_tls_got_hi20 ; +Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; +return 0 ; +} +if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == PULPMCExpr :: VK_PULP_TLS_GD_HI ) { +FixupKind = PULP :: fixup_PULP_tls_gd_hi20 ; +Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; +return 0 ; +} +if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == PULPMCExpr :: VK_PULP_CALL ) { +FixupKind = PULP :: fixup_PULP_call ; +Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; +return 0 ; +} +llvm_unreachable ( "Unknown fixup kind!" ) ; +Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; +return 0 ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCCodeEmitter/getImmOpValueMinus1.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCCodeEmitter/getImmOpValueMinus1.cpp new file mode 100644 index 0000000000000000000000000000000000000000..df6611aa45ebcd358e4559e2ae0c07044adb646c --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCCodeEmitter/getImmOpValueMinus1.cpp @@ -0,0 +1,24 @@ +unsigned PULPMCCodeEmitter :: getImmOpValueMinus1 ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { +const MCOperand & MO ; +MO = MI . getOperand ( OpIdx ) ; +if ( MO . isReg ( ) ) { +return Ctx . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) ) ; +} +if ( MO . isImm ( ) ) { +return static_cast < unsigned > ( MO . getImm ( ) ) ; +} +PULP :: Fixups FixupKind ; +FixupKind = PULP :: Fixups ( 0 ) ; +MCExpr :: ExprKind Kind ; +if ( Kind == MCExpr :: Constant ) { +return cast < MCConstantExpr > ( Expr ) -> getValue ( ) ; +} +if ( Kind == MCExpr :: Binary ) { +} +assert ( Kind == MCExpr :: SymbolRef && "unknown MCExpr kind" ) ; +Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; +return 0 ; +llvm_unreachable ( "Unknown fixup kind!" ) ; +Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; +return 0 ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCCodeEmitter/getMachineOpValue.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCCodeEmitter/getMachineOpValue.cpp new file mode 100644 index 0000000000000000000000000000000000000000..dcce3a1e3e7da3576ed3985f055cc8980e43f6d2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCCodeEmitter/getMachineOpValue.cpp @@ -0,0 +1,44 @@ +unsigned PULPMCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { +if ( MO . isReg ( ) ) { +return Ctx . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) ) ; +} +if ( MO . isImm ( ) ) { +return static_cast < unsigned > ( MO . getImm ( ) ) ; +} +if ( MO . isExpr ( ) ) { +if ( MI . getOpcode ( ) == PULP :: LOOP0setup ) { +Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( PULP :: fixup_PULP_loop_setup ) , MI . getLoc ( ) ) ) ; +} +if ( MI . getOpcode ( ) == PULP :: LOOP1setup ) { +Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( PULP :: fixup_PULP_loop_setup ) , MI . getLoc ( ) ) ) ; +} +if ( MI . getOpcode ( ) == PULP :: LOOP0setupi ) { +Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( PULP :: fixup_PULP_loop_setupi ) , MI . getLoc ( ) ) ) ; +} +if ( MI . getOpcode ( ) == PULP :: LOOP1setupi ) { +Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( PULP :: fixup_PULP_loop_setupi ) , MI . getLoc ( ) ) ) ; +} +if ( MI . getOpcode ( ) == PULP :: LOOP0starti ) { +Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( PULP :: fixup_PULP_loop_setup ) , MI . getLoc ( ) ) ) ; +} +if ( MI . getOpcode ( ) == PULP :: LOOP1starti ) { +Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( PULP :: fixup_PULP_loop_setup ) , MI . getLoc ( ) ) ) ; +} +if ( MI . getOpcode ( ) == PULP :: LOOP0endi ) { +Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( PULP :: fixup_PULP_loop_setup ) , MI . getLoc ( ) ) ) ; +} +if ( MI . getOpcode ( ) == PULP :: LOOP1endi ) { +Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( PULP :: fixup_PULP_loop_setup ) , MI . getLoc ( ) ) ) ; +} +if ( MI . getOpcode ( ) == PULP :: LOOP0counti ) { +Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( PULP :: fixup_PULP_loop_setup ) , MI . getLoc ( ) ) ) ; +} +if ( MI . getOpcode ( ) == PULP :: LOOP1counti ) { +Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( PULP :: fixup_PULP_loop_setup ) , MI . getLoc ( ) ) ) ; +} +MCNumFixups = MCNumFixups + 1 ; +return 0 ; +} +llvm_unreachable ( "Unhandled expression!" ) ; +return 0 ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCCodeEmitter/getVMaskReg.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCCodeEmitter/getVMaskReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f009ea02a33e875fab9025859e806bdf7d333b61 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCCodeEmitter/getVMaskReg.cpp @@ -0,0 +1,11 @@ +unsigned PULPMCCodeEmitter :: getVMaskReg ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { +auto MO = MI . getOperand ( OpNo ) ; +assert ( MO . isReg ( ) && "Expected a register." ) ; +if ( MO . getReg ( ) == PULP :: V0 ) { +return 0x00 ; +} +if ( MO . getReg ( ) == PULP :: NoRegister ) { +return 1 ; +} +llvm_unreachable ( "Invalid mask register." ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCCodeEmitter/~MCCodeEmitter.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCCodeEmitter/~MCCodeEmitter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3e2ace444d66f22b70548320d683379d6a82d93a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCCodeEmitter/~MCCodeEmitter.cpp @@ -0,0 +1,2 @@ +~ PULPMCCodeEmitter ( ) override { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCExpr/MCExpr.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCExpr/MCExpr.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5a801e2642c61d947a367189fde416c2e13d7608 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCExpr/MCExpr.cpp @@ -0,0 +1,2 @@ +explicit PULPMCExpr ( const MCExpr * Expr , VariantKind Kind ) : Expr ( Expr ) , Kind ( Kind ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCExpr/classof1.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCExpr/classof1.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2b052897719aaca60ef09baece651fd4286e607f --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCExpr/classof1.cpp @@ -0,0 +1,3 @@ +static bool classof ( const MCExpr * E ) { +return E -> getKind ( ) == MCExpr :: Target ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCExpr/classof2.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCExpr/classof2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..be4aa051d4a3d4ac02c2b026b7e4e7ee1734c31f --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCExpr/classof2.cpp @@ -0,0 +1,3 @@ +static bool classof ( const PULPMCExpr * ) { +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCExpr/create.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCExpr/create.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8a90abc2f0ef3f0912971fdf37f1bff6abf5500b --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCExpr/create.cpp @@ -0,0 +1,3 @@ +const PULPMCExpr * PULPMCExpr :: create ( const MCExpr * Expr , VariantKind Kind , MCContext & Ctx ) { +return new ( Ctx ) PULPMCExpr ( Expr , Kind ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCExpr/enumVariantKind.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCExpr/enumVariantKind.cpp new file mode 100644 index 0000000000000000000000000000000000000000..309ecabf4e6ee0b73e414172fb11af99674df330 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCExpr/enumVariantKind.cpp @@ -0,0 +1,17 @@ +enum VariantKind { +VK_PULP_None , +VK_PULP_LO , +VK_PULP_HI , +VK_PULP_PCREL_LO , +VK_PULP_PCREL_HI , +VK_PULP_GOT_HI , +VK_PULP_TPREL_LO , +VK_PULP_TPREL_HI , +VK_PULP_TPREL_ADD , +VK_PULP_TLS_GOT_HI , +VK_PULP_TLS_GD_HI , +VK_PULP_CALL , +VK_PULP_CALL_PLT , +VK_PULP_32_PCREL , +VK_PULP_Invalid , +} ; \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCExpr/evaluateAsConstant.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCExpr/evaluateAsConstant.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4dfa46a1a411c781109a358584a7cb06fceca83e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCExpr/evaluateAsConstant.cpp @@ -0,0 +1,9 @@ +bool PULPMCExpr :: evaluateAsConstant ( int64_t & Res ) const { +MCValue Value ; +return false ; +} +if ( ! Value . isAbsolute ( ) ) { +return false ; +} +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCExpr/evaluateAsInt64.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCExpr/evaluateAsInt64.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b5534ce0805dabc8fb125923bb6633ca635cb0da --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCExpr/evaluateAsInt64.cpp @@ -0,0 +1,11 @@ +int64_t PULPMCExpr :: evaluateAsInt64 ( int64_t Value ) const { +if ( Kind == PULPMCExpr :: VK_PULP_LO ) { +Value = static_cast < uint64_t > ( ( Value << 52 ) >> 52 ) ; +return Value ; +} +if ( Kind == PULPMCExpr :: VK_PULP_HI ) { +Value = static_cast < uint64_t > ( ( Value + 0x800 ) >> 12 ) ; +return Value ; +} +llvm_unreachable ( "Invalid kind" ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCExpr/evaluateAsRelocatableImpl.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCExpr/evaluateAsRelocatableImpl.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4e8fb7851c59422e04c4f778c834be70a55b7a5e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCExpr/evaluateAsRelocatableImpl.cpp @@ -0,0 +1,41 @@ +bool PULPMCExpr :: evaluateAsRelocatableImpl ( MCValue & Res , const MCAsmLayout * Layout , const MCFixup * Fixup ) const { +MCValue Value ; +if ( ! getSubExpr ( ) -> evaluateAsRelocatable ( Res , Layout , Fixup ) ) { +return false ; +} +if ( Res . getSymA ( ) ) { +if ( Res . getSymB ( ) ) { +if ( getKind ( ) == PULPMCExpr :: VK_PULP_LO ) { +return false ; +} +if ( getKind ( ) == PULPMCExpr :: VK_PULP_HI ) { +return false ; +} +if ( getKind ( ) == PULPMCExpr :: VK_PULP_PCREL_LO ) { +return false ; +} +if ( getKind ( ) == PULPMCExpr :: VK_PULP_PCREL_HI ) { +return false ; +} +if ( getKind ( ) == PULPMCExpr :: VK_PULP_GOT_HI ) { +return false ; +} +if ( getKind ( ) == PULPMCExpr :: VK_PULP_TPREL_LO ) { +return false ; +} +if ( getKind ( ) == PULPMCExpr :: VK_PULP_TPREL_HI ) { +return false ; +} +if ( getKind ( ) == PULPMCExpr :: VK_PULP_TPREL_ADD ) { +return false ; +} +if ( getKind ( ) == PULPMCExpr :: VK_PULP_TLS_GOT_HI ) { +return false ; +} +if ( getKind ( ) == PULPMCExpr :: VK_PULP_TLS_GD_HI ) { +return false ; +} +} +} +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCExpr/findAssociatedFragment.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCExpr/findAssociatedFragment.cpp new file mode 100644 index 0000000000000000000000000000000000000000..00a5c41996b4821d7075c77e4ac4311bbd9c40e3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCExpr/findAssociatedFragment.cpp @@ -0,0 +1,3 @@ +MCFragment * findAssociatedFragment ( ) const override { +return getSubExpr ( ) -> findAssociatedFragment ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCExpr/fixELFSymbolsInTLSFixups.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCExpr/fixELFSymbolsInTLSFixups.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4e562c0d13371d3edd2790e816fdff60997e1a60 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCExpr/fixELFSymbolsInTLSFixups.cpp @@ -0,0 +1,11 @@ +void PULPMCExpr :: fixELFSymbolsInTLSFixups ( MCAssembler & Asm ) const { +if ( getKind ( ) == PULPMCExpr :: VK_PULP_TPREL_HI ) { +fixELFSymbolsInTLSFixupsImpl ( getSubExpr ( ) , Asm ) ; +} +if ( getKind ( ) == PULPMCExpr :: VK_PULP_TLS_GOT_HI ) { +fixELFSymbolsInTLSFixupsImpl ( getSubExpr ( ) , Asm ) ; +} +if ( getKind ( ) == PULPMCExpr :: VK_PULP_TLS_GD_HI ) { +fixELFSymbolsInTLSFixupsImpl ( getSubExpr ( ) , Asm ) ; +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCExpr/fixELFSymbolsInTLSFixupsImpl.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCExpr/fixELFSymbolsInTLSFixupsImpl.cpp new file mode 100644 index 0000000000000000000000000000000000000000..09abc3a6f4c60e0906522ecfba24bdbe49a286fd --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCExpr/fixELFSymbolsInTLSFixupsImpl.cpp @@ -0,0 +1,20 @@ +static void fixELFSymbolsInTLSFixupsImpl ( const MCExpr * Expr , MCAssembler & Asm ) { +if ( Expr -> getKind ( ) == MCExpr :: Target ) { +llvm_unreachable ( "Can't handle nested target expression" ) ; +} +if ( Expr -> getKind ( ) == MCExpr :: Constant ) { +} +if ( Expr -> getKind ( ) == MCExpr :: Binary ) { +const MCBinaryExpr * BE ; +BE = cast < MCBinaryExpr > ( Expr ) ; +fixELFSymbolsInTLSFixupsImpl ( BE -> getLHS ( ) , Asm ) ; +fixELFSymbolsInTLSFixupsImpl ( BE -> getRHS ( ) , Asm ) ; +} +if ( Expr -> getKind ( ) == MCExpr :: SymbolRef ) { +const MCSymbolRefExpr & SymRef = * cast < MCSymbolRefExpr > ( Expr ) ; +cast < MCSymbolELF > ( SymRef . getSymbol ( ) ) . setType ( ELF :: STT_TLS ) ; +} +if ( Expr -> getKind ( ) == MCExpr :: Unary ) { +fixELFSymbolsInTLSFixupsImpl ( cast < MCUnaryExpr > ( Expr ) -> getSubExpr ( ) , Asm ) ; +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCExpr/getKind.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCExpr/getKind.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d711002a252a9dd02f4cfd37981b41932cfcd805 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCExpr/getKind.cpp @@ -0,0 +1,3 @@ +VariantKind getKind ( ) const { +return Kind ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCExpr/getPCRelHiFixup.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCExpr/getPCRelHiFixup.cpp new file mode 100644 index 0000000000000000000000000000000000000000..eb574d8989caaf6fd17b4c6d8a8c8c5c738925d1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCExpr/getPCRelHiFixup.cpp @@ -0,0 +1,2 @@ +const MCFixup * PULPMCExpr :: getPCRelHiFixup ( const MCFragment * * DFOut ) const { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCExpr/getSubExpr.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCExpr/getSubExpr.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d7e2553d1d84be4fd14ae6489f4304e9c6da6514 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCExpr/getSubExpr.cpp @@ -0,0 +1,3 @@ +const MCExpr * getSubExpr ( ) const { +return Expr ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCExpr/getVariantKindForName.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCExpr/getVariantKindForName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adc27d48ce3ba77c6f857737117ab2251210e4ef --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCExpr/getVariantKindForName.cpp @@ -0,0 +1,33 @@ +PULPMCExpr :: VariantKind PULPMCExpr :: getVariantKindForName ( StringRef name ) { +if ( name == "lo" ) { +return PULPMCExpr :: VK_PULP_LO ; +} +if ( name == "hi" ) { +return PULPMCExpr :: VK_PULP_HI ; +} +if ( name == "pcrel_lo" ) { +return PULPMCExpr :: VK_PULP_PCREL_LO ; +} +if ( name == "pcrel_hi" ) { +return PULPMCExpr :: VK_PULP_PCREL_HI ; +} +if ( name == "got_pcrel_hi" ) { +return PULPMCExpr :: VK_PULP_GOT_HI ; +} +if ( name == "tprel_lo" ) { +return PULPMCExpr :: VK_PULP_TPREL_LO ; +} +if ( name == "tprel_hi" ) { +return PULPMCExpr :: VK_PULP_TPREL_HI ; +} +if ( name == "tprel_add" ) { +return PULPMCExpr :: VK_PULP_TPREL_ADD ; +} +if ( name == "tls_ie_pcrel_hi" ) { +return PULPMCExpr :: VK_PULP_TLS_GOT_HI ; +} +if ( name == "tls_gd_pcrel_hi" ) { +return PULPMCExpr :: VK_PULP_TLS_GD_HI ; +} +return PULPMCExpr :: VK_PULP_Invalid ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCExpr/getVariantKindName.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCExpr/getVariantKindName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..aa320e8791fa22bda9e097a674cb91c2f4279192 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCExpr/getVariantKindName.cpp @@ -0,0 +1,33 @@ +StringRef PULPMCExpr :: getVariantKindName ( VariantKind Kind ) { +if ( Kind == PULPMCExpr :: VK_PULP_LO ) { +return "lo" ; +} +if ( Kind == PULPMCExpr :: VK_PULP_HI ) { +return "hi" ; +} +if ( Kind == PULPMCExpr :: VK_PULP_PCREL_LO ) { +return "pcrel_lo" ; +} +if ( Kind == PULPMCExpr :: VK_PULP_PCREL_HI ) { +return "pcrel_hi" ; +} +if ( Kind == PULPMCExpr :: VK_PULP_GOT_HI ) { +return "got_pcrel_hi" ; +} +if ( Kind == PULPMCExpr :: VK_PULP_TPREL_LO ) { +return "tprel_lo" ; +} +if ( Kind == PULPMCExpr :: VK_PULP_TPREL_HI ) { +return "tprel_hi" ; +} +if ( Kind == PULPMCExpr :: VK_PULP_TPREL_ADD ) { +return "tprel_add" ; +} +if ( Kind == PULPMCExpr :: VK_PULP_TLS_GOT_HI ) { +return "tls_ie_pcrel_hi" ; +} +if ( Kind == PULPMCExpr :: VK_PULP_TLS_GD_HI ) { +return "tls_gd_pcrel_hi" ; +} +llvm_unreachable ( "Invalid ELF symbol kind" ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCExpr/printImpl.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCExpr/printImpl.cpp new file mode 100644 index 0000000000000000000000000000000000000000..aee1e419c590cad29f41c574b30bb1c8b2b9f05b --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCExpr/printImpl.cpp @@ -0,0 +1,70 @@ +void PULPMCExpr :: printImpl ( raw_ostream & OS , const MCAsmInfo * MAI ) const { +VariantKind Kind ; +Kind = getKind ( ) ; +if ( Kind == PULPMCExpr :: VK_PULP_PCREL_LO ) { +OS << "%pcrel_lo(" ; +Expr -> print ( OS , MAI ) ; +OS << ")" ; +} +if ( Kind == PULPMCExpr :: VK_PULP_PCREL_HI ) { +OS << "%pcrel_hi(" ; +Expr -> print ( OS , MAI ) ; +OS << ")" ; +} +if ( Kind == PULPMCExpr :: VK_PULP_TPREL_LO ) { +OS << "%tprel_lo(" ; +Expr -> print ( OS , MAI ) ; +OS << ")" ; +} +if ( Kind == PULPMCExpr :: VK_PULP_TPREL_HI ) { +OS << "%tprel_hi(" ; +Expr -> print ( OS , MAI ) ; +OS << ")" ; +} +if ( Kind == PULPMCExpr :: VK_PULP_TPREL_ADD ) { +OS << "%tprel_add(" ; +Expr -> print ( OS , MAI ) ; +OS << ")" ; +} +if ( Kind == PULPMCExpr :: VK_PULP_LO ) { +OS << "%lo(" ; +Expr -> print ( OS , MAI ) ; +OS << ")" ; +} +if ( Kind == PULPMCExpr :: VK_PULP_HI ) { +OS << "%hi(" ; +Expr -> print ( OS , MAI ) ; +OS << ")" ; +} +if ( Kind == PULPMCExpr :: VK_PULP_GOT_HI ) { +OS << "%got_pcrel_hi(" ; +Expr -> print ( OS , MAI ) ; +OS << ")" ; +} +if ( Kind == PULPMCExpr :: VK_PULP_TLS_GOT_HI ) { +OS << "%tls_ie_pcrel_hi(" ; +Expr -> print ( OS , MAI ) ; +OS << ")" ; +} +if ( Kind == PULPMCExpr :: VK_PULP_TLS_GD_HI ) { +OS << "%tls_gd_pcrel_hi(" ; +Expr -> print ( OS , MAI ) ; +OS << ")" ; +} +if ( Kind == PULPMCExpr :: VK_PULP_CALL_PLT ) { +OS << "" ; +Expr -> print ( OS , MAI ) ; +OS << "@plt" ; +} +if ( Kind == PULPMCExpr :: VK_PULP_CALL ) { +OS << "" ; +Expr -> print ( OS , MAI ) ; +OS << "" ; +} +if ( Kind == PULPMCExpr :: VK_PULP_None ) { +OS << "" ; +Expr -> print ( OS , MAI ) ; +OS << "" ; +} +llvm_unreachable ( "Invalid ELF symbol kind" ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCExpr/visitUsedExpr.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCExpr/visitUsedExpr.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c1e7599b75de72f3d5ac53a0ab8ae534294d877f --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCExpr/visitUsedExpr.cpp @@ -0,0 +1,3 @@ +void PULPMCExpr :: visitUsedExpr ( MCStreamer & Streamer ) const { +Streamer . visitUsedExpr ( * getSubExpr ( ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCTargetDesc/InstrAnalysis.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCTargetDesc/InstrAnalysis.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b215b170843fd48bb87e157968d6f9da9361981c --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCTargetDesc/InstrAnalysis.cpp @@ -0,0 +1,2 @@ +explicit PULPMCInstrAnalysis ( const MCInstrInfo * Info ) : MCInstrAnalysis ( Info ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCTargetDesc/LLVMInitializeTargetMC.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCTargetDesc/LLVMInitializeTargetMC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7989b7052da93c03583f329d868b799a47d5a747 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCTargetDesc/LLVMInitializeTargetMC.cpp @@ -0,0 +1,15 @@ +extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializePULPTargetMC ( ) { +for ( Target * T : { & getThePULP32Target ( ) , & getThePULP64Target ( ) } ) { +TargetRegistry :: RegisterMCAsmInfo ( * T , createPULPMCAsmInfo ) ; +TargetRegistry :: RegisterMCInstrInfo ( * T , createPULPMCInstrInfo ) ; +TargetRegistry :: RegisterMCRegInfo ( * T , createPULPMCRegisterInfo ) ; +TargetRegistry :: RegisterMCAsmBackend ( * T , createPULPAsmBackend ) ; +TargetRegistry :: RegisterMCCodeEmitter ( * T , createPULPMCCodeEmitter ) ; +TargetRegistry :: RegisterMCInstPrinter ( * T , createPULPMCInstPrinter ) ; +TargetRegistry :: RegisterMCSubtargetInfo ( * T , createPULPMCSubtargetInfo ) ; +TargetRegistry :: RegisterObjectTargetStreamer ( * T , createPULPObjectTargetStreamer ) ; +TargetRegistry :: RegisterMCInstrAnalysis ( * T , createPULPInstrAnalysis ) ; +TargetRegistry :: RegisterAsmTargetStreamer ( * T , createPULPAsmTargetStreamer ) ; +TargetRegistry :: RegisterNullTargetStreamer ( * T , createPULPNullTargetStreamer ) ; +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCTargetDesc/createAsmTargetStreamer.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCTargetDesc/createAsmTargetStreamer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6b94eb1d03fd28255fc5fea6c469da98001a67e6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCTargetDesc/createAsmTargetStreamer.cpp @@ -0,0 +1,3 @@ +static MCTargetStreamer * createPULPAsmTargetStreamer ( MCStreamer & S , formatted_raw_ostream & OS , MCInstPrinter * InstPrint , bool isVerboseAsm ) { +return new PULPTargetAsmStreamer ( S , OS ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCTargetDesc/createInstrAnalysis.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCTargetDesc/createInstrAnalysis.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2e8782b271e1f1d0ddf9bd0916554e7c1c9bcdf6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCTargetDesc/createInstrAnalysis.cpp @@ -0,0 +1,3 @@ +static MCInstrAnalysis * createPULPInstrAnalysis ( const MCInstrInfo * Info ) { +return new PULPMCInstrAnalysis ( Info ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCTargetDesc/createMCAsmInfo.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCTargetDesc/createMCAsmInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..85ac1af3350f2d2a2ddc16be83913c5b532acb3c --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCTargetDesc/createMCAsmInfo.cpp @@ -0,0 +1,9 @@ +static MCAsmInfo * createPULPMCAsmInfo ( const MCRegisterInfo & MRI , const Triple & TT , const MCTargetOptions & Options ) { +MCAsmInfo * MAI ; +MAI = new PULPMCAsmInfo ( TT ) ; +MCRegister Reg ; +Reg = MRI . getDwarfRegNum ( PULP :: X2 , true ) ; +MCCFIInstruction Inst = MCCFIInstruction :: cfiDefCfa ( nullptr , Reg , 0 ) ; +MAI -> addInitialFrameState ( Inst ) ; +return MAI ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCTargetDesc/createMCInstPrinter.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCTargetDesc/createMCInstPrinter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d9fd1e454106525336457dc9384a594c59c70dac --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCTargetDesc/createMCInstPrinter.cpp @@ -0,0 +1,3 @@ +static MCInstPrinter * createPULPMCInstPrinter ( const Triple & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) { +return new PULPInstPrinter ( MAI , MII , MRI ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCTargetDesc/createMCInstrInfo.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCTargetDesc/createMCInstrInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3071d8391440e65411b747299fe2dfc6363df83c --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCTargetDesc/createMCInstrInfo.cpp @@ -0,0 +1,6 @@ +static MCInstrInfo * createPULPMCInstrInfo ( ) { +MCInstrInfo * X ; +X = new MCInstrInfo ( ) ; +InitPULPMCInstrInfo ( X ) ; +return X ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCTargetDesc/createMCRegisterInfo.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCTargetDesc/createMCRegisterInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4555aa31b04d1c8192ffd5d3c74275f3748059a0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCTargetDesc/createMCRegisterInfo.cpp @@ -0,0 +1,6 @@ +static MCRegisterInfo * createPULPMCRegisterInfo ( const Triple & TT ) { +MCRegisterInfo * X ; +X = new MCRegisterInfo ( ) ; +InitPULPMCRegisterInfo ( X , PULP :: X1 ) ; +return X ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCTargetDesc/createMCSubtargetInfo.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCTargetDesc/createMCSubtargetInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7bb0c940a5faff0b5058e8158343f2c6801759b8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCTargetDesc/createMCSubtargetInfo.cpp @@ -0,0 +1,13 @@ +static MCSubtargetInfo * createPULPMCSubtargetInfo ( const Triple & TT , StringRef CPU , StringRef FS ) { +std :: string CPUName ; +CPUName = std :: string ( CPU ) ; +if ( CPUName . empty ( ) ) { +if ( TT . isArch64Bit ( ) ) { +CPUName = "generic-rv64" ; +} +if ( ! TT . isArch64Bit ( ) ) { +CPUName = "generic-rv32" ; +} +} +return createPULPMCSubtargetInfoImpl ( TT , CPUName , CPUName , FS ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCTargetDesc/createNullTargetStreamer.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCTargetDesc/createNullTargetStreamer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d317aee919208f7ff4f29a7a82b8224521436012 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCTargetDesc/createNullTargetStreamer.cpp @@ -0,0 +1,3 @@ +static MCTargetStreamer * createPULPNullTargetStreamer ( MCStreamer & S ) { +return new PULPTargetStreamer ( S ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCTargetDesc/createObjectTargetStreamer.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCTargetDesc/createObjectTargetStreamer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..10e3b1629be2f6631c1bed9a1aca81ff3981bca1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCTargetDesc/createObjectTargetStreamer.cpp @@ -0,0 +1,7 @@ +static MCTargetStreamer * createPULPObjectTargetStreamer ( MCStreamer & S , const MCSubtargetInfo & STI ) { +const Triple & TT = STI . getTargetTriple ( ) ; +if ( TT . isOSBinFormatELF ( ) ) { +return new PULPTargetELFStreamer ( S , STI ) ; +} +return new PULPTargetELFStreamer ( S , STI ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCTargetDesc/evaluateBranch.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCTargetDesc/evaluateBranch.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f9353ec9d4b9afe93b70f5d226d85e19830d0c94 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MCTargetDesc/evaluateBranch.cpp @@ -0,0 +1,55 @@ +bool evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size , uint64_t & Target ) const { +if ( Inst . getOpcode ( ) == PULP :: BEQ ) { +Target = Addr + Inst . getOperand ( 2 ) . getImm ( ) ; +return true ; +} +if ( Inst . getOpcode ( ) == PULP :: BNE ) { +Target = Addr + Inst . getOperand ( 2 ) . getImm ( ) ; +return true ; +} +if ( Inst . getOpcode ( ) == PULP :: BLT ) { +Target = Addr + Inst . getOperand ( 2 ) . getImm ( ) ; +return true ; +} +if ( Inst . getOpcode ( ) == PULP :: BGE ) { +Target = Addr + Inst . getOperand ( 2 ) . getImm ( ) ; +return true ; +} +if ( Inst . getOpcode ( ) == PULP :: BLTU ) { +Target = Addr + Inst . getOperand ( 2 ) . getImm ( ) ; +return true ; +} +if ( Inst . getOpcode ( ) == PULP :: BGEU ) { +Target = Addr + Inst . getOperand ( 2 ) . getImm ( ) ; +return true ; +} +if ( Inst . getOpcode ( ) == PULP :: C_BEQZ ) { +Target = Addr + Inst . getOperand ( 1 ) . getImm ( ) ; +return true ; +} +if ( Inst . getOpcode ( ) == PULP :: C_BNEZ ) { +Target = Addr + Inst . getOperand ( 1 ) . getImm ( ) ; +return true ; +} +if ( Inst . getOpcode ( ) == PULP :: JAL ) { +Target = Addr + Inst . getOperand ( 1 ) . getImm ( ) ; +return true ; +} +if ( Inst . getOpcode ( ) == PULP :: C_JAL ) { +Target = Addr + Inst . getOperand ( 0 ) . getImm ( ) ; +return true ; +} +if ( Inst . getOpcode ( ) == PULP :: C_J ) { +Target = Addr + Inst . getOperand ( 0 ) . getImm ( ) ; +return true ; +} +if ( Inst . getOpcode ( ) == PULP :: P_BEQIMM ) { +Target = Addr + Inst . getOperand ( 1 ) . getImm ( ) ; +return true ; +} +if ( Inst . getOpcode ( ) == PULP :: P_BNEIMM ) { +Target = Addr + Inst . getOperand ( 1 ) . getImm ( ) ; +return true ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MatInt/generateInstSeq.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MatInt/generateInstSeq.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ddc6ae15a0d43899bbcceee8789b59998772a4e3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MatInt/generateInstSeq.cpp @@ -0,0 +1,32 @@ +MatInt :: InstSeq MatInt :: generateInstSeq ( int64_t Val ) { +InstSeq Insts ; +if ( Highest12 != 0 ) { +if ( SignExtend64 < 52 > ( Val ) == 0 ) { +Insts . push_back ( Inst ( PULP :: LU52I_D , SignExtend64 < 12 > ( Highest12 ) ) ) ; +return Insts ; +} +} +if ( Hi20 == 0 ) { +Insts . push_back ( Inst ( PULP :: ORI , Lo12 ) ) ; +} +if ( Hi20 != 0 ) { +if ( SignExtend32 < 1 > ( Lo12 >> 11 ) == SignExtend32 < 20 > ( Hi20 ) ) { +Insts . push_back ( Inst ( PULP :: ADDI_W , SignExtend64 < 12 > ( Lo12 ) ) ) ; +} +} +if ( Hi20 != 0 ) { +if ( SignExtend32 < 1 > ( Lo12 >> 11 ) != SignExtend32 < 20 > ( Hi20 ) ) { +Insts . push_back ( Inst ( PULP :: LU12I_W , SignExtend64 < 20 > ( Hi20 ) ) ) ; +if ( Lo12 != 0 ) { +Insts . push_back ( Inst ( PULP :: ORI , Lo12 ) ) ; +} +} +} +if ( SignExtend32 < 1 > ( Hi20 >> 19 ) != SignExtend32 < 20 > ( Higher20 ) ) { +Insts . push_back ( Inst ( PULP :: LU32I_D , SignExtend64 < 20 > ( Higher20 ) ) ) ; +} +if ( SignExtend32 < 1 > ( Higher20 >> 19 ) != SignExtend32 < 12 > ( Highest12 ) ) { +Insts . push_back ( Inst ( PULP :: LU52I_D , SignExtend64 < 12 > ( Highest12 ) ) ) ; +} +return Insts ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MatInt/getIntMatCost.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MatInt/getIntMatCost.cpp new file mode 100644 index 0000000000000000000000000000000000000000..98bcc8a891aab82616d0c0346d7724187bc88265 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MatInt/getIntMatCost.cpp @@ -0,0 +1,3 @@ +int getIntMatCost ( const APInt & Val , unsigned Size , bool IsRV64 ) { +return std :: max ( 1 , Cost ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MatInt/structInst.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MatInt/structInst.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f25780f5a7195e77e9196dea579a14a99922338c --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/MatInt/structInst.cpp @@ -0,0 +1,6 @@ +struct Inst { +unsigned Opc ; +int64_t Imm ; +Inst ( unsigned Opc , int64_t Imm ) : Opc ( Opc ) , Imm ( Imm ) { +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/TargetAsmStreamer.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/TargetAsmStreamer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3fd9887c8b2db9bcc132412344695be54dea83d7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/TargetAsmStreamer.cpp @@ -0,0 +1,2 @@ +PULPTargetAsmStreamer :: PULPTargetAsmStreamer ( MCStreamer & S , formatted_raw_ostream & OS ) : PULPTargetStreamer ( S ) , OS ( OS ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/TargetStreamer.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/TargetStreamer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f32649e14787fd1970274129d540e0cc19fc5d0e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/TargetStreamer.cpp @@ -0,0 +1,2 @@ +PULPTargetStreamer :: PULPTargetStreamer ( MCStreamer & S ) : MCTargetStreamer ( S ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitAttribute.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitAttribute.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5871ec90c0beaadb1e938a1d9a38781a5721f2ae --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitAttribute.cpp @@ -0,0 +1,3 @@ +void PULPTargetAsmStreamer :: emitAttribute ( unsigned Attribute , unsigned Value ) { +OS << "\t.attribute\t" << Attribute << ", " << Twine ( Value ) << "\n" ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitAttribute2.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitAttribute2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9eb900f4fdad9ab2de4645eab7b08ad27af6dafc --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitAttribute2.cpp @@ -0,0 +1,2 @@ +void PULPTargetStreamer :: emitAttribute ( unsigned Attribute , unsigned Value ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionNoPIC.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionNoPIC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3d354b0a8b78d99a8450980a7be68eadeab64027 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionNoPIC.cpp @@ -0,0 +1,3 @@ +void PULPTargetAsmStreamer :: emitDirectiveOptionNoPIC ( ) { +OS << "\t.option\tnopic\n" ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionNoPIC2.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionNoPIC2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..90b5a9c00f1db2ea64746cda077779ed28d7688d --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionNoPIC2.cpp @@ -0,0 +1,2 @@ +void PULPTargetStreamer :: emitDirectiveOptionNoPIC ( ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionNoRVC.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionNoRVC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..afbcbe6dd5cc251c2bd1e4ea45702f628f94f503 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionNoRVC.cpp @@ -0,0 +1,3 @@ +void PULPTargetAsmStreamer :: emitDirectiveOptionNoRVC ( ) { +OS << "\t.option\tnorvc\n" ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionNoRVC2.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionNoRVC2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..109d66264d23183b601914b6c46c390842eee447 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionNoRVC2.cpp @@ -0,0 +1,2 @@ +void PULPTargetStreamer :: emitDirectiveOptionNoRVC ( ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionNoRelax.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionNoRelax.cpp new file mode 100644 index 0000000000000000000000000000000000000000..36dbde68ceebe75909af78e691dfc2bb32994d89 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionNoRelax.cpp @@ -0,0 +1,3 @@ +void PULPTargetAsmStreamer :: emitDirectiveOptionNoRelax ( ) { +OS << "\t.option\tnorelax\n" ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionNoRelax2.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionNoRelax2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f7342f32426ea1846e670001fd296df0b320df3a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionNoRelax2.cpp @@ -0,0 +1,2 @@ +void PULPTargetStreamer :: emitDirectiveOptionNoRelax ( ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionPIC.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionPIC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..21a6b06456b1a69bde0daff6fb0f47f213c1edf4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionPIC.cpp @@ -0,0 +1,3 @@ +void PULPTargetAsmStreamer :: emitDirectiveOptionPIC ( ) { +OS << "\t.option\tpic\n" ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionPIC2.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionPIC2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..540c35197e0924cc26d66baae9036f73fafcbdc2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionPIC2.cpp @@ -0,0 +1,2 @@ +void PULPTargetStreamer :: emitDirectiveOptionPIC ( ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionPop.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionPop.cpp new file mode 100644 index 0000000000000000000000000000000000000000..035d22f257d7564921cda90ce150f9ef24d9de1b --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionPop.cpp @@ -0,0 +1,3 @@ +void PULPTargetAsmStreamer :: emitDirectiveOptionPop ( ) { +OS << "\t.option\tpop\n" ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionPop2.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionPop2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..da14688e8e0ec22170bacec29380c1e35fd9ca40 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionPop2.cpp @@ -0,0 +1,2 @@ +void PULPTargetStreamer :: emitDirectiveOptionPop ( ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionPush.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionPush.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c10a53f320ec7572a8f7ef0399f367b7a7abdfbe --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionPush.cpp @@ -0,0 +1,3 @@ +void PULPTargetAsmStreamer :: emitDirectiveOptionPush ( ) { +OS << "\t.option\tpush\n" ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionPush2.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionPush2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b7f46ba1b159b31f46197c81c0e6c9e5bf95a8a6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionPush2.cpp @@ -0,0 +1,2 @@ +void PULPTargetStreamer :: emitDirectiveOptionPush ( ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionRVC.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionRVC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..811393879c976038e2f3b58591caec3376a46a8d --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionRVC.cpp @@ -0,0 +1,3 @@ +void PULPTargetAsmStreamer :: emitDirectiveOptionRVC ( ) { +OS << "\t.option\trvc\n" ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionRVC2.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionRVC2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1f37473d31354c790cd2b23628b2f1c6df90806a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionRVC2.cpp @@ -0,0 +1,2 @@ +void PULPTargetStreamer :: emitDirectiveOptionRVC ( ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionRelax.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionRelax.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ad8e233cd44d9dff51b8a5480216b012decd6d8a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionRelax.cpp @@ -0,0 +1,3 @@ +void PULPTargetAsmStreamer :: emitDirectiveOptionRelax ( ) { +OS << "\t.option\trelax\n" ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionRelax2.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionRelax2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0400daf42b8fc61d915754ffd777dd78d1a97d87 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitDirectiveOptionRelax2.cpp @@ -0,0 +1,2 @@ +void PULPTargetStreamer :: emitDirectiveOptionRelax ( ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitIntTextAttribute.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitIntTextAttribute.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e559a0f22eedad3247f9d9d8bfe83c52248008f6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitIntTextAttribute.cpp @@ -0,0 +1,2 @@ +void PULPTargetAsmStreamer :: emitIntTextAttribute ( unsigned Attribute , unsigned IntValue , StringRef StringValue ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitIntTextAttribute2.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitIntTextAttribute2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..95d0f6131b9bf81142645aced73336d06d948f00 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitIntTextAttribute2.cpp @@ -0,0 +1,2 @@ +void PULPTargetStreamer :: emitIntTextAttribute ( unsigned Attribute , unsigned IntValue , StringRef StringValue ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitTargetAttributes.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitTargetAttributes.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f766af87d29c5e76fcfc4a19e717923b203de53d --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitTargetAttributes.cpp @@ -0,0 +1,123 @@ +void PULPTargetStreamer :: emitTargetAttributes ( const MCSubtargetInfo & STI ) { +StringRef CPU ; +CPU = STI . getCPU ( ) ; +PULP :: ArchKind ArchID ; +ArchID = PULP :: parseCPUArch ( CPU ) ; +if ( ArchID == PULP :: ArchKind :: CK804 ) { +ArchID = PULP :: ArchKind :: CK803 ; +} +StringRef CPU_ARCH ; +CPU_ARCH = PULP :: getArchName ( ArchID ) ; +if ( ArchID == PULP :: ArchKind :: INVALID ) { +} +emitTextAttribute ( PULPAttrs :: PULP_ARCH_NAME | zm - split | CPU_ARCH , PULPAttrs :: PULP_ARCH_NAME | zm - split | CPU_ARCH ) ; +emitTextAttribute ( PULPAttrs :: PULP_CPU_NAME | zm - split | CPU , PULPAttrs :: PULP_CPU_NAME | zm - split | CPU ) ; +unsigned ISAFlag ; +ISAFlag = 0 ; +if ( STI . hasFeature ( PULP :: Feature64Bit ) ) { +ISAFlag = ISAFlag | PULPAttrs :: V2_ISA_E1 ; +} +if ( STI . hasFeature ( PULP :: FeatureRV32E ) ) { +ISAFlag = ISAFlag | PULPAttrs :: V2_ISA_1E2 ; +} +if ( STI . hasFeature ( PULP :: FeatureStdExtM ) ) { +ISAFlag = ISAFlag | PULPAttrs :: V2_ISA_2E3 ; +} +if ( STI . hasFeature ( PULP :: FeatureStdExtA ) ) { +ISAFlag = ISAFlag | PULPAttrs :: ISA_MP ; +} +if ( STI . hasFeature ( PULP :: FeatureStdExtF ) ) { +ISAFlag = ISAFlag | PULPAttrs :: V2_ISA_3E3R1 ; +} +if ( STI . hasFeature ( PULP :: FeatureStdExtD ) ) { +ISAFlag = ISAFlag | PULPAttrs :: V2_ISA_3E3R2 ; +} +if ( STI . hasFeature ( PULP :: FeatureStdExtC ) ) { +ISAFlag = ISAFlag | PULPAttrs :: V2_ISA_3E3R3 ; +} +if ( STI . hasFeature ( PULP :: FeatureStdExtB ) ) { +ISAFlag = ISAFlag | PULPAttrs :: V2_ISA_3E7 ; +} +if ( STI . hasFeature ( PULP :: FeatureStdExtV ) ) { +ISAFlag = ISAFlag | PULPAttrs :: ISA_MP_1E2 ; +} +if ( STI . hasFeature ( PULP :: FeatureExtZfh ) ) { +ISAFlag = ISAFlag | PULPAttrs :: V2_ISA_7E10 ; +} +if ( STI . hasFeature ( PULP :: FeatureExtZba ) ) { +ISAFlag = ISAFlag | PULPAttrs :: V2_ISA_10E60 ; +} +if ( STI . hasFeature ( PULP :: FeatureExtZbb ) ) { +ISAFlag = ISAFlag | PULPAttrs :: ISA_TRUST ; +} +if ( STI . hasFeature ( PULP :: FeatureExtZbc ) ) { +ISAFlag = ISAFlag | PULPAttrs :: ISA_JAVA ; +} +if ( STI . hasFeature ( PULP :: FeatureExtZbe ) ) { +ISAFlag = ISAFlag | PULPAttrs :: ISA_CACHE ; +} +if ( STI . hasFeature ( PULP :: FeatureExtZbf ) ) { +ISAFlag = ISAFlag | PULPAttrs :: ISA_NVIC ; +} +if ( STI . hasFeature ( PULP :: FeatureExtZbm ) ) { +ISAFlag = ISAFlag | PULPAttrs :: ISA_DSP ; +} +if ( STI . hasFeature ( PULP :: FeatureExtZbp ) ) { +ISAFlag = ISAFlag | PULPAttrs :: ISA_DSP_1E2 ; +} +if ( STI . hasFeature ( PULP :: FeatureExtZbproposedc ) ) { +ISAFlag = ISAFlag | PULPAttrs :: V2_ISA_DSPE60 ; +} +if ( STI . hasFeature ( PULP :: FeatureExtZbr ) ) { +ISAFlag = ISAFlag | PULPAttrs :: ISA_DSP_ENHANCE ; +} +if ( STI . hasFeature ( PULP :: FeatureExtZbs ) ) { +ISAFlag = ISAFlag | PULPAttrs :: ISA_DSP_SILAN ; +} +if ( STI . hasFeature ( PULP :: FeatureExtZbt ) ) { +ISAFlag = ISAFlag | PULPAttrs :: ISA_VDSP ; +} +if ( STI . hasFeature ( PULP :: FeatureExtZvamo ) ) { +ISAFlag = ISAFlag | PULPAttrs :: ISA_VDSP_2 ; +} +if ( STI . hasFeature ( PULP :: FeatureStdExtZvlsseg ) ) { +ISAFlag = ISAFlag | PULPAttrs :: ISA_VDSP_2E3 ; +} +ISAFlag = ISAFlag | PULPAttrs :: ISA_VDSP_2E60F ; +emitAttribute ( PULPAttrs :: PULP_ISA_FLAGS | zm - split | ISAFlag , PULPAttrs :: PULP_ISA_FLAGS | zm - split | ISAFlag ) ; +unsigned ISAExtFlag ; +ISAExtFlag = 0 ; +ISAExtFlag = ISAExtFlag | PULPAttrs :: ISA_FLOAT_E1 ; +ISAExtFlag = ISAExtFlag | PULPAttrs :: ISA_FLOAT_1E2 ; +ISAExtFlag = ISAExtFlag | PULPAttrs :: ISA_FLOAT_1E3 ; +ISAExtFlag = ISAExtFlag | PULPAttrs :: ISA_FLOAT_3E4 ; +ISAExtFlag = ISAExtFlag | PULPAttrs :: ISA_FLOAT_7E60 ; +emitAttribute ( PULPAttrs :: PULP_ISA_EXT_FLAGS | zm - split | ISAExtFlag , PULPAttrs :: PULP_ISA_EXT_FLAGS | zm - split | ISAExtFlag ) ; +emitAttribute ( PULPAttrs :: PULP_DSP_VERSION | zm - split | PULPAttrs :: DSP_VERSION_EXTENSION , PULPAttrs :: PULP_DSP_VERSION | zm - split | PULPAttrs :: DSP_VERSION_EXTENSION ) ; +emitAttribute ( PULPAttrs :: PULP_DSP_VERSION | zm - split | PULPAttrs :: DSP_VERSION_2 , PULPAttrs :: PULP_DSP_VERSION | zm - split | PULPAttrs :: DSP_VERSION_2 ) ; +emitAttribute ( PULPAttrs :: PULP_VDSP_VERSION | zm - split | PULPAttrs :: VDSP_VERSION_2 , PULPAttrs :: PULP_VDSP_VERSION | zm - split | PULPAttrs :: VDSP_VERSION_2 ) ; +emitAttribute ( PULPAttrs :: PULP_FPU_VERSION | zm - split | PULPAttrs :: FPU_VERSION_2 , PULPAttrs :: PULP_FPU_VERSION | zm - split | PULPAttrs :: FPU_VERSION_2 ) ; +emitAttribute ( PULPAttrs :: PULP_FPU_VERSION | zm - split | PULPAttrs :: FPU_VERSION_2 , PULPAttrs :: PULP_FPU_VERSION | zm - split | PULPAttrs :: FPU_VERSION_2 ) ; +emitAttribute ( PULPAttrs :: PULP_FPU_VERSION | zm - split | PULPAttrs :: FPU_VERSION_3 , PULPAttrs :: PULP_FPU_VERSION | zm - split | PULPAttrs :: FPU_VERSION_3 ) ; +emitAttribute ( PULPAttrs :: PULP_FPU_VERSION | zm - split | PULPAttrs :: FPU_VERSION_3 , PULPAttrs :: PULP_FPU_VERSION | zm - split | PULPAttrs :: FPU_VERSION_3 ) ; +emitAttribute ( PULPAttrs :: PULP_FPU_VERSION | zm - split | PULPAttrs :: FPU_VERSION_3 , PULPAttrs :: PULP_FPU_VERSION | zm - split | PULPAttrs :: FPU_VERSION_3 ) ; +bool hasAnyFloatExt ; +hasAnyFloatExt = STI . hasFeature ( PULP :: FeatureFPUV2_SF ) || STI . hasFeature ( PULP :: FeatureFPUV2_DF ) || STI . hasFeature ( PULP :: FeatureFPUV3_HF ) || STI . hasFeature ( PULP :: FeatureFPUV3_SF ) || STI . hasFeature ( PULP :: FeatureFPUV3_DF ) ; +if ( ! hasAnyFloatExt ) { +emitAttribute ( PULPAttrs :: PULP_FPU_ABI | zm - split | PULPAttrs :: FPU_ABI_SOFTFP , PULPAttrs :: PULP_FPU_ABI | zm - split | PULPAttrs :: FPU_ABI_SOFTFP ) ; +emitAttribute ( PULPAttrs :: PULP_FPU_ABI | zm - split | PULPAttrs :: FPU_ABI_SOFTFP , PULPAttrs :: PULP_FPU_ABI | zm - split | PULPAttrs :: FPU_ABI_SOFTFP ) ; +emitAttribute ( PULPAttrs :: PULP_FPU_ABI | zm - split | PULPAttrs :: FPU_ABI_SOFTFP , PULPAttrs :: PULP_FPU_ABI | zm - split | PULPAttrs :: FPU_ABI_SOFTFP ) ; +emitAttribute ( PULPAttrs :: PULP_FPU_ABI | zm - split | PULPAttrs :: FPU_ABI_SOFTFP , PULPAttrs :: PULP_FPU_ABI | zm - split | PULPAttrs :: FPU_ABI_SOFTFP ) ; +unsigned HardFPFlag ; +HardFPFlag = 0 ; +HardFPFlag = HardFPFlag | PULPAttrs :: FPU_HARDFP_HALF ; +HardFPFlag = HardFPFlag | PULPAttrs :: FPU_HARDFP_SINGLE ; +HardFPFlag = HardFPFlag | PULPAttrs :: FPU_HARDFP_SINGLE ; +HardFPFlag = HardFPFlag | PULPAttrs :: FPU_HARDFP_DOUBLE ; +HardFPFlag = HardFPFlag | PULPAttrs :: FPU_HARDFP_DOUBLE ; +if ( HardFPFlag != 0 ) { +emitAttribute ( PULPAttrs :: PULP_FPU_DENORMAL | zm - split | PULPAttrs :: NEEDED , PULPAttrs :: PULP_FPU_DENORMAL | zm - split | PULPAttrs :: NEEDED ) ; +emitAttribute ( PULPAttrs :: PULP_FPU_EXCEPTION | zm - split | PULPAttrs :: NEEDED , PULPAttrs :: PULP_FPU_EXCEPTION | zm - split | PULPAttrs :: NEEDED ) ; +emitTextAttribute ( PULPAttrs :: PULP_FPU_NUMBER_MODULE | zm - split | "IEEE 754" , PULPAttrs :: PULP_FPU_NUMBER_MODULE | zm - split | "IEEE 754" ) ; +emitAttribute ( PULPAttrs :: PULP_FPU_HARDFP | zm - split | HardFPFlag , PULPAttrs :: PULP_FPU_HARDFP | zm - split | HardFPFlag ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitTextAttribute.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitTextAttribute.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a7f0590e63b460e39ca6cc5b20cab0ef1de15ca8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitTextAttribute.cpp @@ -0,0 +1,3 @@ +void PULPTargetAsmStreamer :: emitTextAttribute ( unsigned Attribute , StringRef String ) { +OS << "\t.attribute\t" << Attribute << ", \"" << String << "\"\n" ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitTextAttribute2.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitTextAttribute2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a89abce423eb68bdc298d3d2be7183696c598f02 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/emitTextAttribute2.cpp @@ -0,0 +1,2 @@ +void PULPTargetStreamer :: emitTextAttribute ( unsigned Attribute , StringRef String ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/finish.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/finish.cpp new file mode 100644 index 0000000000000000000000000000000000000000..abec0429f881dac5db9a177bfabd3237ecbf8ad3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/finish.cpp @@ -0,0 +1,3 @@ +void PULPTargetStreamer :: finish ( ) { +finishAttributeSection ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/finishAttributeSection.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/finishAttributeSection.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a53591cd00f7c19fbfb0a46f3b29267752ec6b42 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/finishAttributeSection.cpp @@ -0,0 +1,2 @@ +void PULPTargetAsmStreamer :: finishAttributeSection ( ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/finishAttributeSection2.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/finishAttributeSection2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0bcc4dd2b98dac99df3db89a10f6c56f6382c243 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Emission/TargetStreamer/finishAttributeSection2.cpp @@ -0,0 +1,2 @@ +void PULPTargetStreamer :: finishAttributeSection ( ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/CleanupVSETVLI/CleanupVSETVLI.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/CleanupVSETVLI/CleanupVSETVLI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8a74bdb9a84fd3d15c5e543b49150824b229a2f5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/CleanupVSETVLI/CleanupVSETVLI.cpp @@ -0,0 +1,3 @@ +PULPCleanupVSETVLI ( ) : MachineFunctionPass ( ID ) { +initializePULPCleanupVSETVLIPass ( * PassRegistry :: getPassRegistry ( ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/CleanupVSETVLI/createPass.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/CleanupVSETVLI/createPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..61f65ea15343c96b6ec89be3ddea38fe6f37a3ff --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/CleanupVSETVLI/createPass.cpp @@ -0,0 +1,3 @@ +FunctionPass * llvm :: createPULPCleanupVSETVLIPass ( ) { +return new PULPCleanupVSETVLI ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/CleanupVSETVLI/getAnalysisUsage.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/CleanupVSETVLI/getAnalysisUsage.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ead5f1a786d8e94c38aaeccf54e965a7633f1381 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/CleanupVSETVLI/getAnalysisUsage.cpp @@ -0,0 +1,4 @@ +void getAnalysisUsage ( AnalysisUsage & AU ) const override { +AU . setPreservesCFG ( ) ; +MachineFunctionPass :: getAnalysisUsage ( AU ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/CleanupVSETVLI/getPassName.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/CleanupVSETVLI/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fe5dd1adfa5bb36bae4ebe8618f90add4d94c953 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/CleanupVSETVLI/getPassName.cpp @@ -0,0 +1,3 @@ +StringRef getPassName ( ) const override { +return PULP_CLEANUP_VSETVLI_NAME ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/CleanupVSETVLI/getRequiredProperties.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/CleanupVSETVLI/getRequiredProperties.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0adda88e88df06602241df5ea12b1b2b61a75d55 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/CleanupVSETVLI/getRequiredProperties.cpp @@ -0,0 +1,3 @@ +MachineFunctionProperties getRequiredProperties ( ) const override { +return MachineFunctionProperties ( ) . set ( MachineFunctionProperties :: Property :: IsSSA ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/CleanupVSETVLI/runOnMachineBasicBlock.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/CleanupVSETVLI/runOnMachineBasicBlock.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3b1139cf483e480d519cdbd2bd9f26bb4687465f --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/CleanupVSETVLI/runOnMachineBasicBlock.cpp @@ -0,0 +1,11 @@ +bool PULPCleanupVSETVLI :: runOnMachineBasicBlock ( MachineBasicBlock & MBB ) { +bool Changed = false ; +for ( MachineBasicBlock :: iterator I = MBB . instr_begin ( ) ; I != MBB . instr_end ( ) ; ++ I ) { +Changed = true ; +Changed = true ; +continue ; +Changed = true ; +Changed = true ; +} +return Changed ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/CleanupVSETVLI/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/CleanupVSETVLI/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bbde87ee40ffebec072781cc8580ee50120fd96e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/CleanupVSETVLI/runOnMachineFunction.cpp @@ -0,0 +1,13 @@ +bool PULPCleanupVSETVLI :: runOnMachineFunction ( MachineFunction & MF ) { +if ( skipFunction ( MF . getFunction ( ) ) ) { +return false ; +} +bool Changed = false ; +if ( ! ST . hasStdExtV ( ) ) { +return false ; +} +for ( MachineBasicBlock & MBB : MF ) { +Changed = Changed | runOnMachineBasicBlock ( MBB ) ; +} +return Changed ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandAtomicPseudoInsts/ExpandAtomicPseudo.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandAtomicPseudoInsts/ExpandAtomicPseudo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b9955556873257824b2e943301c7a01f9d38c027 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandAtomicPseudoInsts/ExpandAtomicPseudo.cpp @@ -0,0 +1,3 @@ +PULPExpandAtomicPseudo ( ) : MachineFunctionPass ( ID ) { +initializePULPExpandAtomicPseudoPass ( * PassRegistry :: getPassRegistry ( ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandAtomicPseudoInsts/createPass.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandAtomicPseudoInsts/createPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7afd2bb82feefd21426d7afd42f396117cc9006e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandAtomicPseudoInsts/createPass.cpp @@ -0,0 +1,3 @@ +FunctionPass * llvm :: createPULPExpandAtomicPseudoPass ( ) { +return new PULPExpandAtomicPseudo ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandAtomicPseudoInsts/expandMBB.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandAtomicPseudoInsts/expandMBB.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5f98aa477e18908f178c3c9cebed29ff846854e3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandAtomicPseudoInsts/expandMBB.cpp @@ -0,0 +1,10 @@ +bool PULPExpandAtomicPseudo :: expandMBB ( MachineBasicBlock & MBB ) { +bool Modified = false ; +MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , E = MBB . end ( ) ; +for ( ; MBBI != E ; ) { +MachineBasicBlock :: iterator NMBBI = std :: next ( MBBI ) ; +Modified = Modified | expandMI ( MBB , MBBI , NMBBI ) ; +MBBI = NMBBI ; +} +return Modified ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandAtomicPseudoInsts/expandMI.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandAtomicPseudoInsts/expandMI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4131b6c3779c492885ba4a17bb95cdfa65414038 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandAtomicPseudoInsts/expandMI.cpp @@ -0,0 +1,42 @@ +bool PULPExpandAtomicPseudo :: expandMI ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , MachineBasicBlock :: iterator & NextMBBI ) { +if ( MBBI -> getOpcode ( ) == PULP :: PseudoAtomicLoadNand32 ) { +return expandAtomicCmpSwap ( MBB , MBBI , NMBB ) ; +} +if ( MBBI -> getOpcode ( ) == PULP :: PseudoAtomicLoadNand64 ) { +return expandAtomicCmpSwap ( MBB , MBBI , NMBB ) ; +} +if ( MBBI -> getOpcode ( ) == PULP :: PseudoMaskedAtomicSwap32 ) { +return expandAtomicCmpSwapSubword ( MBB , MBBI , NMBB ) ; +} +if ( MBBI -> getOpcode ( ) == PULP :: PseudoMaskedAtomicLoadAdd32 ) { +return expandAtomicCmpSwapSubword ( MBB , MBBI , NMBB ) ; +} +if ( MBBI -> getOpcode ( ) == PULP :: PseudoMaskedAtomicLoadSub32 ) { +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +} +if ( MBBI -> getOpcode ( ) == PULP :: PseudoMaskedAtomicLoadNand32 ) { +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +} +if ( MBBI -> getOpcode ( ) == PULP :: PseudoMaskedAtomicLoadMax32 ) { +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +} +if ( MBBI -> getOpcode ( ) == PULP :: PseudoMaskedAtomicLoadMin32 ) { +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +} +if ( MBBI -> getOpcode ( ) == PULP :: PseudoMaskedAtomicLoadUMax32 ) { +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +} +if ( MBBI -> getOpcode ( ) == PULP :: PseudoMaskedAtomicLoadUMin32 ) { +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +} +if ( MBBI -> getOpcode ( ) == PULP :: PseudoCmpXchg32 ) { +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +} +if ( MBBI -> getOpcode ( ) == PULP :: PseudoCmpXchg64 ) { +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +} +if ( MBBI -> getOpcode ( ) == PULP :: PseudoMaskedCmpXchg32 ) { +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandAtomicPseudoInsts/getPassName.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandAtomicPseudoInsts/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4b1aefad2264dd70b08814b093dc54695dbc6096 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandAtomicPseudoInsts/getPassName.cpp @@ -0,0 +1,3 @@ +StringRef getPassName ( ) const override { +return PULP_EXPAND_ATOMIC_PSEUDO_NAME ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandAtomicPseudoInsts/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandAtomicPseudoInsts/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ec9aa80cdc99633ba2bef5e2e9c1632feefa6ea8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandAtomicPseudoInsts/runOnMachineFunction.cpp @@ -0,0 +1,8 @@ +bool PULPExpandAtomicPseudo :: runOnMachineFunction ( MachineFunction & MF ) { +TII = static_cast < const PULPInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; +bool Modified = false ; +for ( auto & MBB : MF ) { +Modified = Modified | expandMBB ( MBB ) ; +} +return Modified ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandPseudoInsts/ExpandPseudo.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandPseudoInsts/ExpandPseudo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..38f31d94a8180e193fba77348c717343bfdebba1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandPseudoInsts/ExpandPseudo.cpp @@ -0,0 +1,3 @@ +PULPExpandPseudo ( ) : MachineFunctionPass ( ID ) { +initializePULPExpandPseudoPass ( * PassRegistry :: getPassRegistry ( ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandPseudoInsts/createPass.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandPseudoInsts/createPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..39f7818769a14b096ce87e337822b80c2cce886d --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandPseudoInsts/createPass.cpp @@ -0,0 +1,3 @@ +FunctionPass * createPULPExpandPseudoPass ( ) { +return new PULPExpandPseudo ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandPseudoInsts/expandMBB.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandPseudoInsts/expandMBB.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3cb82547693da888a53a13fdf1118108e1850cc7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandPseudoInsts/expandMBB.cpp @@ -0,0 +1,10 @@ +bool PULPExpandPseudo :: expandMBB ( MachineBasicBlock & MBB ) { +bool Modified = false ; +MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , E = MBB . end ( ) ; +for ( ; MBBI != E ; ) { +MachineBasicBlock :: iterator NMBBI = std :: next ( MBBI ) ; +Modified = Modified | expandMI ( MBB , MBBI , NMBBI ) ; +MBBI = NMBBI ; +} +return Modified ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandPseudoInsts/expandMI.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandPseudoInsts/expandMI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a4f9e54c8b55143332cfff858d98b83cb3e0dc7d --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandPseudoInsts/expandMI.cpp @@ -0,0 +1,63 @@ +bool PULPExpandPseudo :: expandMI ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , MachineBasicBlock :: iterator & NextMBBI ) { +if ( MBBI -> getOpcode ( ) == PULP :: PseudoLLA ) { +return expandAtomicCmpSwap ( MBB , MBBI , NMBB ) ; +} +if ( MBBI -> getOpcode ( ) == PULP :: PseudoLA ) { +return expandAtomicCmpSwap ( MBB , MBBI , NMBB ) ; +} +if ( MBBI -> getOpcode ( ) == PULP :: PseudoLA_TLS_IE ) { +return expandAtomicCmpSwapSubword ( MBB , MBBI , NMBB ) ; +} +if ( MBBI -> getOpcode ( ) == PULP :: PseudoLA_TLS_GD ) { +return expandAtomicCmpSwapSubword ( MBB , MBBI , NMBB ) ; +} +if ( MBBI -> getOpcode ( ) == PULP :: PseudoVSETVLI ) { +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +} +if ( MBBI -> getOpcode ( ) == PULP :: PseudoVSETIVLI ) { +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +} +if ( MBBI -> getOpcode ( ) == PULP :: PseudoVMCLR_M_B1 ) { +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +} +if ( MBBI -> getOpcode ( ) == PULP :: PseudoVMCLR_M_B2 ) { +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +} +if ( MBBI -> getOpcode ( ) == PULP :: PseudoVMCLR_M_B4 ) { +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +} +if ( MBBI -> getOpcode ( ) == PULP :: PseudoVMCLR_M_B8 ) { +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +} +if ( MBBI -> getOpcode ( ) == PULP :: PseudoVMCLR_M_B16 ) { +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +} +if ( MBBI -> getOpcode ( ) == PULP :: PseudoVMCLR_M_B32 ) { +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +} +if ( MBBI -> getOpcode ( ) == PULP :: PseudoVMCLR_M_B64 ) { +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +} +if ( MBBI -> getOpcode ( ) == PULP :: PseudoVMSET_M_B1 ) { +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +} +if ( MBBI -> getOpcode ( ) == PULP :: PseudoVMSET_M_B2 ) { +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +} +if ( MBBI -> getOpcode ( ) == PULP :: PseudoVMSET_M_B4 ) { +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +} +if ( MBBI -> getOpcode ( ) == PULP :: PseudoVMSET_M_B8 ) { +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +} +if ( MBBI -> getOpcode ( ) == PULP :: PseudoVMSET_M_B16 ) { +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +} +if ( MBBI -> getOpcode ( ) == PULP :: PseudoVMSET_M_B32 ) { +return expandAtomicBinOp ( MBB , MBBI , NMBB ) ; +} +if ( MBBI -> getOpcode ( ) == PULP :: PseudoVMSET_M_B64 ) { +return expandAtomicBinOp ( MBB , MBBI , NMBB ) ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandPseudoInsts/getPassName.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandPseudoInsts/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..594dfc162e7c79e60a8a6ae498b91e840c1ac128 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandPseudoInsts/getPassName.cpp @@ -0,0 +1,3 @@ +StringRef getPassName ( ) const override { +return PULP_EXPAND_PSEUDO_NAME ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandPseudoInsts/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandPseudoInsts/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..69c92883e163858ad472c622dedcd08807a4ef2f --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandPseudoInsts/runOnMachineFunction.cpp @@ -0,0 +1,8 @@ +bool PULPExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) { +TII = static_cast < const PULPInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; +bool Modified = false ; +for ( auto & MBB : MF ) { +Modified = Modified | expandMBB ( MBB ) ; +} +return Modified ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandSDMAInsts/ExpandSDMA.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandSDMAInsts/ExpandSDMA.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ec10837f7c8fd22ddc85f1e1bebd704d18a0ac79 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandSDMAInsts/ExpandSDMA.cpp @@ -0,0 +1,3 @@ +PULPExpandSDMA ( ) : MachineFunctionPass ( ID ) { +initializePULPExpandSDMAPass ( * PassRegistry :: getPassRegistry ( ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandSDMAInsts/ExpandSDMAInsts.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandSDMAInsts/ExpandSDMAInsts.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b09cb138b81e142b9f132beb0e5141b14486f039 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandSDMAInsts/ExpandSDMAInsts.cpp @@ -0,0 +1,3 @@ +RISCVExpandSDMA() : MachineFunctionPass(ID) { + initializeRISCVExpandSDMAPass(*PassRegistry::getPassRegistry()); +} diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandSDMAInsts/createPass.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandSDMAInsts/createPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..29ee610664b05d847dad84f4dd6dffd2659d5168 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandSDMAInsts/createPass.cpp @@ -0,0 +1,3 @@ +FunctionPass * createPULPExpandSDMAPass ( ) { +return new PULPExpandSDMA ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandSDMAInsts/expandMBB.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandSDMAInsts/expandMBB.cpp new file mode 100644 index 0000000000000000000000000000000000000000..35b97012d193d8974353401e63ff594112a38d42 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandSDMAInsts/expandMBB.cpp @@ -0,0 +1,10 @@ +bool PULPExpandSDMA :: expandMBB ( MachineBasicBlock & MBB ) { +bool Modified = false ; +MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , E = MBB . end ( ) ; +for ( ; MBBI != E ; ) { +MachineBasicBlock :: iterator NMBBI = std :: next ( MBBI ) ; +Modified = Modified | expandMI ( MBB , MBBI , NMBBI ) ; +MBBI = NMBBI ; +} +return Modified ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandSDMAInsts/expandMI.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandSDMAInsts/expandMI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..19d4714b83cf0b580e3a52ae648417386d5e731e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandSDMAInsts/expandMI.cpp @@ -0,0 +1,37 @@ +bool PULPExpandSDMAInsts :: expandMI ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , MachineBasicBlock :: iterator & NextMBBI ) { +return expandAtomicCmpSwap ( MBB , MBBI , NMBB ) ; +return expandAtomicCmpSwap ( MBB , MBBI , NMBB ) ; +return expandAtomicCmpSwapSubword ( MBB , MBBI , NMBB ) ; +return expandAtomicCmpSwapSubword ( MBB , MBBI , NMBB ) ; +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +return expandAtomicBinOp ( MBB , MBBI , NMBB ) ; +return expandAtomicBinOp ( MBB , MBBI , NMBB ) ; +return expandAtomicBinOp ( MBB , MBBI , NMBB ) ; +return expandAtomicBinOp ( MBB , MBBI , NMBB ) ; +return expandAtomicBinOp ( MBB , MBBI , NMBB ) ; +return expandAtomicBinOp ( MBB , MBBI , NMBB ) ; +return expandAtomicBinOp ( MBB , MBBI , NMBB ) ; +return expandAtomicBinOp ( MBB , MBBI , NMBB ) ; +return expandAtomicBinOp ( MBB , MBBI , NMBB ) ; +return expandAtomicBinOp ( MBB , MBBI , NMBB ) ; +return expandAtomicBinOp ( MBB , MBBI , NMBB ) ; +return expandAtomicBinOp ( MBB , MBBI , NMBB ) ; +return expandAtomicBinOp ( MBB , MBBI , NMBB ) ; +return expandAtomicBinOp ( MBB , MBBI , NMBB ) ; +return expandAtomicBinOp ( MBB , MBBI , NMBB ) ; +return expandAtomicBinOp ( MBB , MBBI , NMBB ) ; +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandSDMAInsts/getPassName.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandSDMAInsts/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b4b9aa065df6b57dfa392976496c0c01fc68da42 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandSDMAInsts/getPassName.cpp @@ -0,0 +1,3 @@ +StringRef getPassName ( ) const override { +return PULP_EXPAND_SDMA_NAME ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandSDMAInsts/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandSDMAInsts/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..69c92883e163858ad472c622dedcd08807a4ef2f --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandSDMAInsts/runOnMachineFunction.cpp @@ -0,0 +1,8 @@ +bool PULPExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) { +TII = static_cast < const PULPInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; +bool Modified = false ; +for ( auto & MBB : MF ) { +Modified = Modified | expandMBB ( MBB ) ; +} +return Modified ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandSSRInsts/ExpandSSR.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandSSRInsts/ExpandSSR.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fa757aa1fd9eaedaca391e3d7e85b7cbdce96b27 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandSSRInsts/ExpandSSR.cpp @@ -0,0 +1,4 @@ +//zmCorrectzm +RISCVExpandSSR() : MachineFunctionPass(ID) { + initializeRISCVExpandSSRPass(*PassRegistry::getPassRegistry()); +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandSSRInsts/ExpandSSRInsts.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandSSRInsts/ExpandSSRInsts.cpp new file mode 100644 index 0000000000000000000000000000000000000000..446c274c42ec018df5525243647514bb4fa07d9d --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandSSRInsts/ExpandSSRInsts.cpp @@ -0,0 +1,3 @@ +PULPExpandSSR ( ) : MachineFunctionPass ( ID ) { +initializePULPExpandSSRPass ( * PassRegistry :: getPassRegistry ( ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandSSRInsts/createPass.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandSSRInsts/createPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ef147cb04d030b7fbbf048d7711316a96edeb3ed --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandSSRInsts/createPass.cpp @@ -0,0 +1,3 @@ +FunctionPass * createPULPExpandSSRPass ( ) { +return new PULPExpandSSR ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandSSRInsts/expandMBB.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandSSRInsts/expandMBB.cpp new file mode 100644 index 0000000000000000000000000000000000000000..703a337770042aab369e2e1d65f68852d16d5763 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandSSRInsts/expandMBB.cpp @@ -0,0 +1,10 @@ +bool PULPExpandSSR :: expandMBB ( MachineBasicBlock & MBB ) { +bool Modified = false ; +MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , E = MBB . end ( ) ; +for ( ; MBBI != E ; ) { +MachineBasicBlock :: iterator NMBBI = std :: next ( MBBI ) ; +Modified = Modified | expandMI ( MBB , MBBI , NMBBI ) ; +MBBI = NMBBI ; +} +return Modified ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandSSRInsts/expandMI.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandSSRInsts/expandMI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b7f1bb06ce44662b318ccfad64a07990e9d527e4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandSSRInsts/expandMI.cpp @@ -0,0 +1,37 @@ +bool PULPExpandSSRInsts :: expandMI ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , MachineBasicBlock :: iterator & NextMBBI ) { +return expandAtomicCmpSwap ( MBB , MBBI , NMBB ) ; +return expandAtomicCmpSwap ( MBB , MBBI , NMBB ) ; +return expandAtomicCmpSwapSubword ( MBB , MBBI , NMBB ) ; +return expandAtomicCmpSwapSubword ( MBB , MBBI , NMBB ) ; +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +return expandAtomicBinOp ( MBB , MBBI , NMBB ) ; +return expandAtomicBinOp ( MBB , MBBI , NMBB ) ; +return expandAtomicBinOp ( MBB , MBBI , NMBB ) ; +return expandAtomicBinOp ( MBB , MBBI , NMBB ) ; +return expandAtomicBinOp ( MBB , MBBI , NMBB ) ; +return expandAtomicBinOp ( MBB , MBBI , NMBB ) ; +return expandAtomicBinOp ( MBB , MBBI , NMBB ) ; +return expandAtomicBinOp ( MBB , MBBI , NMBB ) ; +return expandAtomicBinOp ( MBB , MBBI , NMBB ) ; +return expandAtomicBinOp ( MBB , MBBI , NMBB ) ; +return expandAtomicBinOp ( MBB , MBBI , NMBB ) ; +return expandAtomicBinOp ( MBB , MBBI , NMBB ) ; +return expandAtomicBinOp ( MBB , MBBI , NMBB ) ; +return expandAtomicBinOp ( MBB , MBBI , NMBB ) ; +return expandAtomicBinOp ( MBB , MBBI , NMBB ) ; +return expandAtomicBinOp ( MBB , MBBI , NMBB ) ; +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandSSRInsts/getPassName.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandSSRInsts/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a4fa0fb6f72d127a2d93f64ecf0ad52e91cd41da --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandSSRInsts/getPassName.cpp @@ -0,0 +1,3 @@ +StringRef getPassName ( ) const override { +return PULP_EXPAND_SSR_NAME ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandSSRInsts/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandSSRInsts/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9ae52bc13eab7fd11f1ba03ba294ef5982dab53e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/ExpandSSRInsts/runOnMachineFunction.cpp @@ -0,0 +1,8 @@ +bool PULPExpandSSRInsts :: runOnMachineFunction ( MachineFunction & MF ) { +TII = static_cast < const PULPInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; +bool Modified = false ; +for ( auto & MBB : MF ) { +Modified = Modified | expandMBB ( MBB ) ; +} +return Modified ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/MergeBaseOffset/MergeBaseOffsetOpt.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/MergeBaseOffset/MergeBaseOffsetOpt.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bb64e637365b930f09897a9341991ae2f7b757cb --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/MergeBaseOffset/MergeBaseOffsetOpt.cpp @@ -0,0 +1,2 @@ +PULPMergeBaseOffsetOpt ( ) : MachineFunctionPass ( ID ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/MergeBaseOffset/createPass.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/MergeBaseOffset/createPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4a2bc73c41981e43a16177f47e6487db23648630 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/MergeBaseOffset/createPass.cpp @@ -0,0 +1,3 @@ +FunctionPass * llvm :: createPULPMergeBaseOffsetOptPass ( ) { +return new PULPMergeBaseOffsetOpt ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/MergeBaseOffset/getPassName.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/MergeBaseOffset/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a9985fc3aee7f96543facf9785b217c4291c5d4e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/MergeBaseOffset/getPassName.cpp @@ -0,0 +1,3 @@ +StringRef getPassName ( ) const override { +return PULP_MERGE_BASE_OFFSET_NAME ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/MergeBaseOffset/getRequiredProperties.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/MergeBaseOffset/getRequiredProperties.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0adda88e88df06602241df5ea12b1b2b61a75d55 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/MergeBaseOffset/getRequiredProperties.cpp @@ -0,0 +1,3 @@ +MachineFunctionProperties getRequiredProperties ( ) const override { +return MachineFunctionProperties ( ) . set ( MachineFunctionProperties :: Property :: IsSSA ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/MergeBaseOffset/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/MergeBaseOffset/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0fa2c9cd1050ff57f7fbef1fce389eb2ca05fee5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/MergeBaseOffset/runOnMachineFunction.cpp @@ -0,0 +1,18 @@ +bool PULPMergeBaseOffset :: runOnMachineFunction ( MachineFunction & MF ) { +if ( skipFunction ( * F . getFunction ( ) ) ) { +return false ; +} +bool Changed = false ; +const Subtarget & ST = MF . getSubtarget < Subtarget > ( ) ; +TII = ST . getInstrInfo ( ) ; +TRI = ST . getRegisterInfo ( ) ; +MRI = & MF . getRegInfo ( ) ; +ClobberedRegs . resize ( TRI -> getNumRegs ( ) ) ; +if ( ST . isV9 ( ) ) { +return false ; +} +for ( MachineBasicBlock & MBB : MF ) { +Changed = Changed | runOnMachineBasicBlock ( MBB ) ; +} +return Changed ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPFixupHwLoops/FixupHwLoops.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPFixupHwLoops/FixupHwLoops.cpp new file mode 100644 index 0000000000000000000000000000000000000000..316b34c4cf0c8e5d9e4236ab94f33861df884864 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPFixupHwLoops/FixupHwLoops.cpp @@ -0,0 +1,3 @@ +PULPFixupHwLoops() : MachineFunctionPass(ID) { + initializePULPFixupHwLoopsPass(*PassRegistry::getPassRegistry()); +} diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPFixupHwLoops/PULPFixupHwLoops.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPFixupHwLoops/PULPFixupHwLoops.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f2e20f163bb9a495009a9912f6d423e741d1b569 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPFixupHwLoops/PULPFixupHwLoops.cpp @@ -0,0 +1,3 @@ +PULPFixupHwLoops ( ) : MachineFunctionPass ( ID ) { +initializePULPFixupHwLoopsPass ( * PassRegistry :: getPassRegistry ( ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPFixupHwLoops/createPULPFixupHwLoops.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPFixupHwLoops/createPULPFixupHwLoops.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9228c6d2483d6a53cbfa3ed48c0366f7bb8826bb --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPFixupHwLoops/createPULPFixupHwLoops.cpp @@ -0,0 +1,3 @@ +FunctionPass *llvm::createPULPFixupHwLoops() { + return new PULPFixupHwLoops(); +} diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPFixupHwLoops/createPass.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPFixupHwLoops/createPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..63b442a8b8053c2c1d2694a0a5a19fb9ed2c47dd --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPFixupHwLoops/createPass.cpp @@ -0,0 +1,3 @@ +FunctionPass * llvm :: createPULPFixupHwLoops ( ) { +return new PULPFixupHwLoops ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPFixupHwLoops/getAnalysisUsage.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPFixupHwLoops/getAnalysisUsage.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f094f032585ed58ef522e13ff3f7e356125fea65 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPFixupHwLoops/getAnalysisUsage.cpp @@ -0,0 +1,5 @@ +void getAnalysisUsage ( AnalysisUsage & AU ) const override { +AU . addRequired < MachineDominatorTree > ( ) ; +AU . addRequired < MachineLoopInfo > ( ) ; +MachineFunctionPass :: getAnalysisUsage ( AU ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPFixupHwLoops/getPassName.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPFixupHwLoops/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2ddac9f96a3fc44c9d6529ecca363e0d38ec0507 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPFixupHwLoops/getPassName.cpp @@ -0,0 +1,3 @@ +StringRef getPassName ( ) const override { +return "PULP Hardware Loop Fixup" ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPFixupHwLoops/getRequiredProperties.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPFixupHwLoops/getRequiredProperties.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3c30a670ece262053445746835921f39923610ca --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPFixupHwLoops/getRequiredProperties.cpp @@ -0,0 +1,3 @@ +MachineFunctionProperties getRequiredProperties ( ) const override { +return MachineFunctionProperties ( ) . set ( MachineFunctionProperties :: Property :: NoVRegs ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPFixupHwLoops/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPFixupHwLoops/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d3a3ebaed08b513825924bee37642929c5ead392 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPFixupHwLoops/runOnMachineFunction.cpp @@ -0,0 +1,14 @@ +bool PULPFixupHwLoops :: runOnMachineFunction ( MachineFunction & MF ) { +LLVM_DEBUG ( dbgs ( ) << "------------ PULP FixupHw Loops ------------\n" ) ; +bool Changed = false ; +MLI = & getAnalysis < MachineLoopInfo > ( ) ; +MDT = & getAnalysis < MachineDominatorTree > ( ) ; +TII = MF . getSubtarget < PULPSubtarget > ( ) . getInstrInfo ( ) ; +for ( auto & L : * MLI ) +if ( ! L -> getParentLoop ( ) ) { +bool L0Used = false ; +bool L1Used = false ; +Changed = Changed | convertToHardwareLoop ( L , L0Used , L1Used ) ; +} +return Changed ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/CountValue.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/CountValue.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ee8c980c44d93f1d05491bc44ed5f820d1fe34b5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/CountValue.cpp @@ -0,0 +1,10 @@ +explicit CountValue ( CountValueType t , unsigned v , unsigned u = 0 ) { +Kind = t ; +if ( Kind == CV_Register ) { +Contents . R . Reg = v ; +Contents . R . Sub = u ; +} +if ( Kind != CV_Register ) { +Contents . ImmVal = v ; +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/HardWareLoops.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/HardWareLoops.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6c8a3b75db790109fddd7331458b05b266d8eb82 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/HardWareLoops.cpp @@ -0,0 +1,2 @@ +PULPHardwareLoops ( ) : MachineFunctionPass ( ID ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/PULPHardwareLoops.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/PULPHardwareLoops.cpp new file mode 100644 index 0000000000000000000000000000000000000000..059b70f62c067de93e000828574ee0e617720529 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/PULPHardwareLoops.cpp @@ -0,0 +1,2 @@ +PULPHardwareLoops() : MachineFunctionPass(ID) { +} diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/checkForImmediate.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/checkForImmediate.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f284e32f96ba536c62f236bf53657fefe28acbbe --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/checkForImmediate.cpp @@ -0,0 +1,218 @@ +bool PULPHardwareLoops :: checkForImmediate ( const MachineOperand & MO , int64_t & Val ) const { +if ( MO . isImm ( ) ) { +Val = MO . getImm ( ) ; +return true ; +} +if ( ! MO . isReg ( ) ) { +return false ; +} +int64_t TV ; +Register R = MO . getReg ( ) ; +if ( ! R . isVirtual ( ) ) { +return false ; +} +MachineInstr * DI = MRI -> getVRegDef ( R ) ; +unsigned DOpc = DI -> getOpcode ( ) ; +if ( DOpc == TargetOpcode :: COPY ) { +if ( ! checkForImmediate ( DI -> getOperand ( 1 ) , TV ) ) { +return false ; +} +if ( MO . getSubReg ( ) == PULP :: subreg_loreg ) { +Val = TV & 0xFFFFFFFFULL ; +} +if ( MO . getSubReg ( ) == PULP :: subreg_hireg ) { +Val = TV & 0xFFFFFFFFULL ; +Val = ( TV >> 32 ) & 0xFFFFFFFFULL ; +} +Val = TV ; +return true ; +} +if ( DOpc == PULP :: A2_tfrsi ) { +if ( ! checkForImmediate ( DI -> getOperand ( 1 ) , TV ) ) { +return false ; +} +if ( MO . getSubReg ( ) == PULP :: subreg_loreg ) { +Val = TV & 0xFFFFFFFFULL ; +} +if ( MO . getSubReg ( ) == PULP :: subreg_hireg ) { +Val = TV & 0xFFFFFFFFULL ; +Val = ( TV >> 32 ) & 0xFFFFFFFFULL ; +} +Val = TV ; +return true ; +} +if ( DOpc == PULP :: A2_tfrpi ) { +if ( ! checkForImmediate ( DI -> getOperand ( 1 ) , TV ) ) { +return false ; +} +if ( MO . getSubReg ( ) == PULP :: subreg_loreg ) { +Val = TV & 0xFFFFFFFFULL ; +} +if ( MO . getSubReg ( ) == PULP :: subreg_hireg ) { +Val = TV & 0xFFFFFFFFULL ; +Val = ( TV >> 32 ) & 0xFFFFFFFFULL ; +} +Val = TV ; +return true ; +} +if ( DOpc == PULP :: CONST32_Int_Real ) { +if ( ! checkForImmediate ( DI -> getOperand ( 1 ) , TV ) ) { +return false ; +} +if ( MO . getSubReg ( ) == PULP :: subreg_loreg ) { +Val = TV & 0xFFFFFFFFULL ; +} +if ( MO . getSubReg ( ) == PULP :: subreg_hireg ) { +Val = TV & 0xFFFFFFFFULL ; +Val = ( TV >> 32 ) & 0xFFFFFFFFULL ; +} +Val = TV ; +return true ; +} +if ( DOpc == PULP :: CONST64_Int_Real ) { +if ( ! checkForImmediate ( DI -> getOperand ( 1 ) , TV ) ) { +return false ; +} +if ( MO . getSubReg ( ) == PULP :: subreg_loreg ) { +Val = TV & 0xFFFFFFFFULL ; +} +if ( MO . getSubReg ( ) == PULP :: subreg_hireg ) { +Val = TV & 0xFFFFFFFFULL ; +Val = ( TV >> 32 ) & 0xFFFFFFFFULL ; +} +Val = TV ; +return true ; +} +if ( DOpc == PULP :: A2_combineii ) { +const MachineOperand & S1 = DI -> getOperand ( 1 ) ; +const MachineOperand & S2 = DI -> getOperand ( 2 ) ; +int64_t V1 ; +int64_t V2 ; +if ( ! checkForImmediate ( S1 , V1 ) ) { +return false ; +} +if ( ! checkForImmediate ( S2 , V2 ) ) { +return false ; +} +TV = V2 | ( V1 << 32 ) ; +if ( MO . getSubReg ( ) == PULP :: subreg_loreg ) { +Val = TV & 0xFFFFFFFFULL ; +} +if ( MO . getSubReg ( ) == PULP :: subreg_hireg ) { +Val = TV & 0xFFFFFFFFULL ; +Val = ( TV >> 32 ) & 0xFFFFFFFFULL ; +} +Val = TV ; +return true ; +} +if ( DOpc == PULP :: A4_combineir ) { +const MachineOperand & S1 = DI -> getOperand ( 1 ) ; +const MachineOperand & S2 = DI -> getOperand ( 2 ) ; +int64_t V1 ; +int64_t V2 ; +if ( ! checkForImmediate ( S1 , V1 ) ) { +return false ; +} +if ( ! checkForImmediate ( S2 , V2 ) ) { +return false ; +} +TV = V2 | ( V1 << 32 ) ; +if ( MO . getSubReg ( ) == PULP :: subreg_loreg ) { +Val = TV & 0xFFFFFFFFULL ; +} +if ( MO . getSubReg ( ) == PULP :: subreg_hireg ) { +Val = TV & 0xFFFFFFFFULL ; +Val = ( TV >> 32 ) & 0xFFFFFFFFULL ; +} +Val = TV ; +return true ; +} +if ( DOpc == PULP :: A4_combineii ) { +const MachineOperand & S1 = DI -> getOperand ( 1 ) ; +const MachineOperand & S2 = DI -> getOperand ( 2 ) ; +int64_t V1 ; +int64_t V2 ; +if ( ! checkForImmediate ( S1 , V1 ) ) { +return false ; +} +if ( ! checkForImmediate ( S2 , V2 ) ) { +return false ; +} +TV = V2 | ( V1 << 32 ) ; +if ( MO . getSubReg ( ) == PULP :: subreg_loreg ) { +Val = TV & 0xFFFFFFFFULL ; +} +if ( MO . getSubReg ( ) == PULP :: subreg_hireg ) { +Val = TV & 0xFFFFFFFFULL ; +Val = ( TV >> 32 ) & 0xFFFFFFFFULL ; +} +Val = TV ; +return true ; +} +if ( DOpc == PULP :: A4_combineri ) { +const MachineOperand & S1 = DI -> getOperand ( 1 ) ; +const MachineOperand & S2 = DI -> getOperand ( 2 ) ; +int64_t V1 ; +int64_t V2 ; +if ( ! checkForImmediate ( S1 , V1 ) ) { +return false ; +} +if ( ! checkForImmediate ( S2 , V2 ) ) { +return false ; +} +TV = V2 | ( V1 << 32 ) ; +if ( MO . getSubReg ( ) == PULP :: subreg_loreg ) { +Val = TV & 0xFFFFFFFFULL ; +} +if ( MO . getSubReg ( ) == PULP :: subreg_hireg ) { +Val = TV & 0xFFFFFFFFULL ; +Val = ( TV >> 32 ) & 0xFFFFFFFFULL ; +} +Val = TV ; +return true ; +} +if ( DOpc == PULP :: A2_combinew ) { +const MachineOperand & S1 = DI -> getOperand ( 1 ) ; +const MachineOperand & S2 = DI -> getOperand ( 2 ) ; +int64_t V1 ; +int64_t V2 ; +if ( ! checkForImmediate ( S1 , V1 ) ) { +return false ; +} +if ( ! checkForImmediate ( S2 , V2 ) ) { +return false ; +} +TV = V2 | ( V1 << 32 ) ; +if ( MO . getSubReg ( ) == PULP :: subreg_loreg ) { +Val = TV & 0xFFFFFFFFULL ; +} +if ( MO . getSubReg ( ) == PULP :: subreg_hireg ) { +Val = TV & 0xFFFFFFFFULL ; +Val = ( TV >> 32 ) & 0xFFFFFFFFULL ; +} +Val = TV ; +return true ; +} +if ( DOpc == TargetOpcode :: REG_SEQUENCE ) { +const MachineOperand & S1 = DI -> getOperand ( 1 ) ; +const MachineOperand & S3 = DI -> getOperand ( 3 ) ; +int64_t V1 ; +int64_t V3 ; +if ( ! checkForImmediate ( S1 , V1 ) ) { +return false ; +} +if ( ! checkForImmediate ( S3 , V3 ) ) { +return false ; +} +unsigned Sub2 = DI -> getOperand ( 2 ) . getImm ( ) ; +unsigned Sub4 = DI -> getOperand ( 4 ) . getImm ( ) ; +if ( MO . getSubReg ( ) == PULP :: subreg_loreg ) { +TV = V1 | ( V3 << 32 ) ; +} +if ( MO . getSubReg ( ) == PULP :: subreg_hireg ) { +TV = V3 | ( V1 << 32 ) ; +} +llvm_unreachable ( "Unexpected form of REG_SEQUENCE" ) ; +return true ; +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/containsInvalidInstruction.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/containsInvalidInstruction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ee654739abe4fe280d9b835c5824b2db4cf2eaae --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/containsInvalidInstruction.cpp @@ -0,0 +1,11 @@ +bool PULPHardwareLoops :: containsInvalidInstruction ( MachineLoop * L ) const { +for ( MachineBasicBlock * MBB : L -> getBlocks ( ) ) { +for ( MachineInstr & MI : * MBB ) { +if ( isInvalidLoopOperation ( MI ) ) { +LLVM_DEBUG ( dbgs ( ) << "\nCannot convert to hwloop due to:" ; MI . dump ( ) ; ) ; +return true ; +} +} +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/convertToHardwareLoop.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/convertToHardwareLoop.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bbf503d3e8209a118f1b3e619a8b0c6fa04f622c --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/convertToHardwareLoop.cpp @@ -0,0 +1,156 @@ +bool PULPHardwareLoops :: convertToHardwareLoop ( MachineLoop * L , bool & RecL0used , bool & RecL1used ) { +assert ( L -> getHeader ( ) && "Loop without a header?" ) ; +bool Changed = false ; +bool L0Used = false ; +bool L1Used = false ; +for ( MachineLoop :: iterator I = L -> begin ( ) , E = L -> end ( ) ; I != E ; ++ I ) { +Changed = Changed | convertToHardwareLoop ( * I , RecL0used , RecL1used ) ; +L0Used = L0Used | RecL0used ; +L1Used = L1Used | RecL1used ; +} +if ( Changed ) { +if ( L0Used ) { +if ( L1Used ) { +return Changed ; +} +} +} +unsigned LOOP_i ; +unsigned LOOP_r ; +unsigned ENDLOOP ; +unsigned IsInnerHWLoop = 1 ; +if ( L0Used ) { +LOOP_i = PULP :: J2_loop1i ; +LOOP_r = PULP :: J2_loop1r ; +ENDLOOP = PULP :: ENDLOOP1 ; +IsInnerHWLoop = 0 ; +} +if ( ! L0Used ) { +LOOP_i = PULP :: J2_loop0i ; +LOOP_r = PULP :: J2_loop0r ; +ENDLOOP = PULP :: ENDLOOP0 ; +} +if ( containsInvalidInstruction ( L , IsInnerHWLoop ) ) { +return false ; +} +MachineBasicBlock * LastMBB = getExitingBlock ( L ) ; +if ( ! LastMBB ) { +return false ; +} +MachineBasicBlock :: iterator LastI = LastMBB -> getFirstTerminator ( ) ; +if ( LastI == LastMBB -> end ( ) ) { +return false ; +} +if ( ! fixupInductionVariable ( L ) ) { +return false ; +} +MachineBasicBlock * Preheader = L -> getLoopPreheader ( ) ; +if ( ! Preheader ) { +Preheader = createPreheaderForLoop ( L ) ; +if ( ! Preheader ) { +return false ; +} +} +MachineBasicBlock :: iterator InsertPos = Preheader -> getFirstTerminator ( ) ; +SmallVector < MachineInstr * , 2 > OldInsts ; +CountValue * TripCount = getLoopTripCount ( L , OldInsts ) ; +if ( ! TripCount ) { +return false ; +} +if ( TripCount -> isReg ( ) ) { +MachineInstr * TCDef = MRI -> getVRegDef ( TripCount -> getReg ( ) ) ; +MachineBasicBlock * BBDef = TCDef -> getParent ( ) ; +if ( ! MDT -> dominates ( BBDef , Preheader ) ) { +return false ; +} +} +MachineBasicBlock * TopBlock = L -> getTopBlock ( ) ; +MachineBasicBlock * ExitingBlock = getExitingBlock ( L ) ; +MachineBasicBlock * LoopStart = 0 ; +if ( ExitingBlock != L -> getLoopLatch ( ) ) { +MachineBasicBlock * TB = 0 , * FB = 0 ; +SmallVector < MachineOperand , 2 > Cond ; +if ( TII -> analyzeBranch ( * ExitingBlock , TB , FB , Cond , false ) ) { +return false ; +} +if ( L -> contains ( TB ) ) { +LoopStart = TB ; +} +if ( L -> contains ( FB ) ) { +LoopStart = FB ; +} +if ( ! L -> contains ( TB ) ) { +if ( ! L -> contains ( FB ) ) { +return false ; +} +} +} +if ( ExitingBlock == L -> getLoopLatch ( ) ) { +LoopStart = TopBlock ; +} +DEBUG ( dbgs ( ) << "Change to hardware loop at " ; L -> dump ( ) ) ; +DebugLoc DL ; +if ( InsertPos != Preheader -> end ( ) ) { +DL = InsertPos -> getDebugLoc ( ) ; +} +if ( TripCount -> isReg ( ) ) { +unsigned CountReg = MRI -> createVirtualRegister ( & PULP :: IntRegsRegClass ) ; +BuildMI ( * Preheader , InsertPos , DL , TII -> get ( TargetOpcode :: COPY ) , CountReg ) . addReg ( TripCount -> getReg ( ) , 0 , TripCount -> getSubReg ( ) ) ; +BuildMI ( * Preheader , InsertPos , DL , TII -> get ( LOOP_r ) ) . addMBB ( LoopStart ) . addReg ( CountReg ) ; +} +if ( ! TripCount -> isReg ( ) ) { +assert ( TripCount -> isImm ( ) && "Expecting immediate value for trip count" ) ; +int64_t CountImm = TripCount -> getImm ( ) ; +if ( ! TII -> isValidOffset ( LOOP_i , CountImm ) ) { +unsigned CountReg = MRI -> createVirtualRegister ( & PULP :: IntRegsRegClass ) ; +BuildMI ( * Preheader , InsertPos , DL , TII -> get ( PULP :: A2_tfrsi ) , CountReg ) . addImm ( CountImm ) ; +BuildMI ( * Preheader , InsertPos , DL , TII -> get ( LOOP_r ) ) . addMBB ( LoopStart ) . addReg ( CountReg ) ; +} +if ( TII -> isValidOffset ( LOOP_i , CountImm ) ) { +BuildMI ( * Preheader , InsertPos , DL , TII -> get ( LOOP_i ) ) . addMBB ( LoopStart ) . addImm ( CountImm ) ; +} +} +LoopStart -> setHasAddressTaken ( ) ; +BlockAddress :: get ( const_cast < BasicBlock * > ( LoopStart -> getBasicBlock ( ) ) ) ; +DebugLoc LastIDL = LastI -> getDebugLoc ( ) ; +BuildMI ( * LastMBB , LastI , LastIDL , TII -> get ( ENDLOOP ) ) . addMBB ( LoopStart ) ; +if ( LastI -> getOpcode ( ) == PULP :: J2_jumpt ) { +MachineBasicBlock * BranchTarget = LastI -> getOperand ( 1 ) . getMBB ( ) ; +LastI = LastMBB -> erase ( LastI ) ; +if ( ! L -> contains ( BranchTarget ) ) { +if ( LastI != LastMBB -> end ( ) ) { +LastI = LastMBB -> erase ( LastI ) ; +} +SmallVector < MachineOperand , 0 > Cond ; +TII -> InsertBranch ( * LastMBB , BranchTarget , nullptr , Cond , LastIDL ) ; +} +} +if ( LastI -> getOpcode ( ) == PULP :: J2_jumpf ) { +MachineBasicBlock * BranchTarget = LastI -> getOperand ( 1 ) . getMBB ( ) ; +LastI = LastMBB -> erase ( LastI ) ; +if ( ! L -> contains ( BranchTarget ) ) { +if ( LastI != LastMBB -> end ( ) ) { +LastI = LastMBB -> erase ( LastI ) ; +} +SmallVector < MachineOperand , 0 > Cond ; +TII -> InsertBranch ( * LastMBB , BranchTarget , nullptr , Cond , LastIDL ) ; +} +} +if ( LastI -> getOpcode ( ) != PULP :: J2_jumpt ) { +if ( LastI -> getOpcode ( ) != PULP :: J2_jumpf ) { +LastMBB -> erase ( LastI ) ; +} +} +delete TripCount ; +for ( unsigned i = 0 ; i < OldInsts . size ( ) ; ++ i ) { +removeIfDead ( OldInsts [ i ] ) ; +} +NumHWLoops = NumHWLoops + 1 ; +if ( L0Used ) { +RecL1used = true ; +} +if ( ! L0Used ) { +RecL0used = true ; +} +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/createPULPHardwareLoops.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/createPULPHardwareLoops.cpp new file mode 100644 index 0000000000000000000000000000000000000000..22e78cc2e7b7238ff9e98a897b042dbb37b79065 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/createPULPHardwareLoops.cpp @@ -0,0 +1,3 @@ +FunctionPass *llvm::createPULPHardwareLoops() { + return new PULPHardwareLoops(); +} diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/createPass.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/createPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..12ea7bdf624696e5a6d397719648ee8c6038e9b0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/createPass.cpp @@ -0,0 +1,3 @@ +FunctionPass * llvm :: createPULPHardwareLoops ( ) { +return new PULPHardwareLoops ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/enumCountValueType.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/enumCountValueType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ed7f2c9968b3fed4477bd9c3d08bb562c76ac4fb --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/enumCountValueType.cpp @@ -0,0 +1,4 @@ +enum CountValueType { +CV_Register , +CV_Immediate +} ; \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/enumKind.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/enumKind.cpp new file mode 100644 index 0000000000000000000000000000000000000000..de0cf91473ebe1e290307572f8ca6f52f0a64904 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/enumKind.cpp @@ -0,0 +1,15 @@ +enum Kind { +EQ = 0x01 , +NE = 0x02 , +L = 0x04 , +G = 0x08 , +U = 0x40 , +LTs = L , +LEs = L | EQ , +GTs = G , +GEs = G | EQ , +LTu = L | U , +LEu = L | EQ | U , +GTu = G | U , +GEu = G | EQ | U +} ; \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/findInductionRegister.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/findInductionRegister.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8854a0e598bd9b25b8c4b823e49620bfd9e17e4a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/findInductionRegister.cpp @@ -0,0 +1,86 @@ +bool PULPHardwareLoops :: findInductionRegister ( MachineLoop * L , unsigned & Reg , int64_t & IVBump , MachineInstr * & IVOp ) const { +MachineBasicBlock * Preheader = MLI -> findLoopPreheader ( L , SpecPreheader ) ; +MachineBasicBlock * Header = L -> getHeader ( ) ; +MachineBasicBlock * Latch = L -> getLoopLatch ( ) ; +MachineBasicBlock * ExitingBlock = L -> findLoopControlBlock ( ) ; +if ( ! Header ) { +return false ; +} +if ( ! Preheader ) { +return false ; +} +if ( ! Latch ) { +return false ; +} +if ( ! ExitingBlock ) { +return false ; +} +using RegisterBump = std :: pair < unsigned , int64_t > ; +using InductionMap = std :: map < unsigned , RegisterBump > ; +InductionMap IndMap ; +using instr_iterator = MachineBasicBlock :: instr_iterator ; +for ( instr_iterator I = Header -> instr_begin ( ) , E = Header -> instr_end ( ) ; I != E && I -> isPHI ( ) ; ++ I ) { +MachineInstr * Phi = & * I ; +for ( unsigned i = 1 , n = Phi -> getNumOperands ( ) ; i < n ; i += 2 ) { +if ( Phi -> getOperand ( i + 1 ) . getMBB ( ) != Latch ) { +continue ; +} +unsigned PhiOpReg = Phi -> getOperand ( i ) . getReg ( ) ; +MachineInstr * DI = MRI -> getVRegDef ( PhiOpReg ) ; +if ( DI -> getDesc ( ) . getOpcode ( ) == PULP :: ADDI ) { +unsigned IndReg = DI -> getOperand ( 1 ) . getReg ( ) ; +MachineOperand & Opnd2 = DI -> getOperand ( 2 ) ; +int64_t V ; +if ( MRI -> getVRegDef ( IndReg ) == Phi ) { +if ( checkForImmediate ( Opnd2 , V ) ) { +unsigned UpdReg = DI -> getOperand ( 0 ) . getReg ( ) ; +IndMap . insert ( std :: make_pair ( UpdReg , std :: make_pair ( IndReg , V ) ) ) ; +} +} +} +} +} +SmallVector < MachineOperand , 2 > Cond ; +MachineBasicBlock * TB = nullptr , * FB = nullptr ; +bool NotAnalyzed = TII -> analyzeBranch ( * ExitingBlock , TB , FB , Cond , false ) ; +if ( NotAnalyzed ) { +return false ; +} +unsigned PredR , PredPos , PredRegFlags ; +if ( ! TII -> getPredReg ( Cond , PredR , PredPos , PredRegFlags ) ) { +return false ; +} +MachineInstr * PredI = MRI -> getVRegDef ( PredR ) ; +if ( ! PredI -> isCompare ( ) ) { +return false ; +} +unsigned CmpReg1 = 0 , CmpReg2 = 0 ; +int CmpImm = 0 , CmpMask = 0 ; +bool CmpAnalyzed = TII -> analyzeCompare ( * PredI , CmpReg1 , CmpReg2 , CmpMask , CmpImm ) ; +if ( ! CmpAnalyzed ) { +return false ; +} +InductionMap :: iterator IndMapEnd = IndMap . end ( ) ; +InductionMap :: iterator F = IndMapEnd ; +if ( CmpReg1 != 0 ) { +InductionMap :: iterator F1 = IndMap . find ( CmpReg1 ) ; +if ( F1 != IndMapEnd ) { +F = F1 ; +} +} +if ( CmpReg2 != 0 ) { +InductionMap :: iterator F2 = IndMap . find ( CmpReg2 ) ; +if ( F2 != IndMapEnd ) { +if ( F != IndMapEnd ) +return false ; +F = F2 ; +} +} +if ( F == IndMapEnd ) { +return false ; +} +Reg = F -> second . first ; +IVBump = F -> second . second ; +IVOp = MRI -> getVRegDef ( F -> first ) ; +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/getAnalysisUsage.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/getAnalysisUsage.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b1d3ea994619de753f89111198b51a819a611528 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/getAnalysisUsage.cpp @@ -0,0 +1,6 @@ +void getAnalysisUsage ( AnalysisUsage & AU ) const override { +AU . setPreservesCFG ( ) ; +AU . addRequired < MachineDominatorTree > ( ) ; +AU . addRequired < MachineLoopInfo > ( ) ; +MachineFunctionPass :: getAnalysisUsage ( AU ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/getComparisonKind.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/getComparisonKind.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0a0e7ce9ebaad0c036a08499ce2301e77c2004fa --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/getComparisonKind.cpp @@ -0,0 +1,28 @@ +PULPHardWareLoops :: Comparison :: Kind PULPHardwareLoops :: getComparisonKind ( unsigned CondOpc , MachineOperand * InitialValue , const MachineOperand * EndValue , int64_t IVBump ) const { +Comparison :: Kind Cmp = ( Comparison :: Kind ) 0 ; +if ( CondOpc == PULP :: BEQ ) { +return Comparison :: EQ ; +} +if ( CondOpc == PULP :: BNE ) { +return Comparison :: NE ; +} +if ( CondOpc == PULP :: BLT ) { +return Comparison :: NE ; +} +if ( CondOpc == PULP :: BLTU ) { +return Comparison :: LTs ; +} +if ( CondOpc == PULP :: BGE ) { +return Comparison :: LTu ; +} +if ( CondOpc == PULP :: BGEU ) { +return Comparison :: GEs ; +} +if ( CondOpc == PULP :: P_BNEIMM ) { +return Comparison :: NE ; +} +if ( CondOpc == PULP :: P_BEQIMM ) { +return Comparison :: EQ ; +} +return ( Comparison :: Kind ) 0 ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/getImm.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/getImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..61a9973ed8aa33286e17f9a6b7cec48dffcc69f8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/getImm.cpp @@ -0,0 +1,4 @@ +unsigned getImm ( ) const { +assert ( isImm ( ) && "Wrong CountValue accessor" ) ; +return Contents . ImmVal ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/getLoopTripCount.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/getLoopTripCount.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cd697bc04edab9d1db48bd0a6809f2c9e238af8a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/getLoopTripCount.cpp @@ -0,0 +1,173 @@ +CountValue * PULPHardwareLoops :: getLoopTripCount ( MachineLoop * L , SmallVectorImpl < MachineInstr * > & OldInsts ) { +MachineBasicBlock * TopMBB = L -> getTopBlock ( ) ; +MachineBasicBlock :: pred_iterator PI = TopMBB -> pred_begin ( ) ; +assert ( PI != TopMBB -> pred_end ( ) && "Loop must have more than one incoming edge!" ) ; +MachineBasicBlock * Backedge = * PI ++ ; +if ( PI == TopMBB -> pred_end ( ) ) { +return nullptr ; +} +MachineBasicBlock * Incoming = * PI ++ ; +if ( PI != TopMBB -> pred_end ( ) ) { +return nullptr ; +} +if ( L -> contains ( Incoming ) ) { +if ( L -> contains ( Backedge ) ) { +return nullptr ; +} +std :: swap ( Incoming , Backedge ) ; +} +if ( ! L -> contains ( Incoming ) ) { +if ( ! L -> contains ( Backedge ) ) { +return nullptr ; +} +} +MachineBasicBlock * ExitingBlock = L -> findLoopControlBlock ( ) ; +if ( ! ExitingBlock ) { +return nullptr ; +} +unsigned IVReg = 0 ; +int64_t IVBump = 0 ; +MachineInstr * IVOp ; +bool FoundIV = findInductionRegister ( L , IVReg , IVBump , IVOp ) ; +if ( ! FoundIV ) { +return nullptr ; +} +MachineBasicBlock * Preheader = MLI -> findLoopPreheader ( L , SpecPreheader ) ; +MachineOperand * InitialValue = nullptr ; +MachineInstr * IV_Phi = MRI -> getVRegDef ( IVReg ) ; +MachineBasicBlock * Latch = L -> getLoopLatch ( ) ; +for ( unsigned i = 1 , n = IV_Phi -> getNumOperands ( ) ; i < n ; i += 2 ) { +MachineBasicBlock * MBB = IV_Phi -> getOperand ( i + 1 ) . getMBB ( ) ; +if ( MBB == Preheader ) { +InitialValue = & IV_Phi -> getOperand ( i ) ; +} +if ( MBB != Preheader ) { +if ( MBB == Latch ) { +IVReg = IV_Phi -> getOperand ( i ) . getReg ( ) ; +} +} +} +if ( ! InitialValue ) { +return nullptr ; +} +SmallVector < MachineOperand , 2 > Cond ; +MachineBasicBlock * TB = nullptr ; +MachineBasicBlock * FB = nullptr ; +bool NotAnalyzed = TII -> analyzeBranch ( * ExitingBlock , TB , FB , Cond , false ) ; +if ( NotAnalyzed ) { +return nullptr ; +} +MachineBasicBlock * Header = L -> getHeader ( ) ; +assert ( TB && "Exit block without a branch?" ) ; +if ( ExitingBlock != Latch ) { +if ( TB == Latch ) { +MachineBasicBlock * LTB = nullptr ; +MachineBasicBlock * LFB = nullptr ; +SmallVector < MachineOperand , 2 > LCond ; +bool NotAnalyzed = TII -> analyzeBranch ( * Latch , LTB , LFB , LCond , false ) ; +if ( NotAnalyzed ) { +return nullptr ; +} +TB = ( LTB == Header ) ? LTB : LFB ; +} +if ( TB != Latch ) { +if ( FB == Latch ) { +MachineBasicBlock * LTB = nullptr ; +MachineBasicBlock * LFB = nullptr ; +SmallVector < MachineOperand , 2 > LCond ; +bool NotAnalyzed = TII -> analyzeBranch ( * Latch , LTB , LFB , LCond , false ) ; +if ( NotAnalyzed ) { +return nullptr ; +} +FB = ( LTB == Header ) ? LTB : LFB ; +} +} +} +assert ( ( ! FB || TB == Header || FB == Header ) && "Branches not to header?" ) ; +if ( ! TB ) { +return nullptr ; +} +if ( FB ) { +if ( TB != Header ) { +if ( FB != Header ) { +return nullptr ; +} +} +} +bool Negated = TII -> predOpcodeHasNot ( Cond ) ^ ( TB != Header ) ; +unsigned PredReg ; +unsigned PredPos ; +unsigned PredRegFlags ; +if ( ! TII -> getPredReg ( Cond , PredReg , PredPos , PredRegFlags ) ) { +return nullptr ; +} +MachineInstr * CondI = MRI -> getVRegDef ( PredReg ) ; +unsigned CondOpc = CondI -> getOpcode ( ) ; +unsigned CmpReg1 ; +unsigned CmpReg2 ; +int Mask = 0 ; +int ImmValue = 0 ; +bool AnalyzedCmp = TII -> analyzeCompare ( * CondI , CmpReg1 , CmpReg2 , Mask , ImmValue ) ; +if ( ! AnalyzedCmp ) { +return nullptr ; +} +OldInsts . push_back ( CondI ) ; +OldInsts . push_back ( IVOp ) ; +Comparison :: Kind Cmp ; +bool isSwapped = false ; +const MachineOperand & Op1 = CondI -> getOperand ( 1 ) ; +const MachineOperand & Op2 = CondI -> getOperand ( 2 ) ; +const MachineOperand * EndValue = nullptr ; +if ( Op1 . isReg ( ) ) { +if ( Op2 . isImm ( ) ) { +EndValue = & Op2 ; +} +if ( ! Op2 . isImm ( ) ) { +if ( Op1 . getReg ( ) == IVReg ) { +EndValue = & Op2 ; +} +} +if ( ! Op2 . isImm ( ) ) { +if ( Op1 . getReg ( ) != IVReg ) { +EndValue = & Op1 ; +isSwapped = true ; +} +} +} +if ( ! EndValue ) { +return nullptr ; +} +Cmp = getComparisonKind ( CondOpc , InitialValue , EndValue , IVBump ) ; +if ( ! Cmp ) { +return nullptr ; +} +if ( Negated ) { +Cmp = Comparison :: getNegatedComparison ( Cmp ) ; +} +if ( isSwapped ) { +Cmp = Comparison :: getSwappedComparison ( Cmp ) ; +} +if ( InitialValue -> isReg ( ) ) { +unsigned R = InitialValue -> getReg ( ) ; +MachineBasicBlock * DefBB = MRI -> getVRegDef ( R ) -> getParent ( ) ; +if ( ! MDT -> properlyDominates ( DefBB , Header ) ) { +int64_t V ; +if ( ! checkForImmediate ( * InitialValue , V ) ) { +return nullptr ; +} +} +OldInsts . push_back ( MRI -> getVRegDef ( R ) ) ; +} +if ( EndValue -> isReg ( ) ) { +unsigned R = EndValue -> getReg ( ) ; +MachineBasicBlock * DefBB = MRI -> getVRegDef ( R ) -> getParent ( ) ; +if ( ! MDT -> properlyDominates ( DefBB , Header ) ) { +int64_t V ; +if ( ! checkForImmediate ( * EndValue , V ) ) { +return nullptr ; +} +} +OldInsts . push_back ( MRI -> getVRegDef ( R ) ) ; +} +return computeCount ( L , InitialValue , EndValue , IVReg , IVBump , Cmp ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/getNegatedComparison.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/getNegatedComparison.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2412e32e79ee9f8b82866a4230dee4038eb8250a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/getNegatedComparison.cpp @@ -0,0 +1,15 @@ +static Kind getNegatedComparison ( Kind Cmp ) { +if ( Cmp & L ) { +return ( Kind ) ( ( Cmp ^ ( L | G ) ) ^ EQ ) ; +} +if ( Cmp & G ) { +return ( Kind ) ( ( Cmp ^ ( L | G ) ) ^ EQ ) ; +} +if ( Cmp & NE ) { +return ( Kind ) ( Cmp ^ ( EQ | NE ) ) ; +} +if ( Cmp & EQ ) { +return ( Kind ) ( Cmp ^ ( EQ | NE ) ) ; +} +return ( Kind ) 0 ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/getPassName.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0b752ec7167fbcf4cc686e4dd9e0e9e71ef1388d --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/getPassName.cpp @@ -0,0 +1,3 @@ +StringRef getPassName ( ) const override { +return "PULP Hardware Loops" ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/getReg.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/getReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5a5b2c5e0312f971a08d886e42c8e74a2864bfed --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/getReg.cpp @@ -0,0 +1,4 @@ +unsigned getReg ( ) const { +assert ( isReg ( ) && "Wrong CountValue accessor" ) ; +return Contents . R . Reg ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/getSubReg.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/getSubReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..09c6a1ee80848a50e8171505de85cd829f5d6701 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/getSubReg.cpp @@ -0,0 +1,4 @@ +unsigned getSubReg ( ) const { +assert ( isReg ( ) && "Wrong CountValue accessor" ) ; +return Contents . R . Sub ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/getSwappedComparison.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/getSwappedComparison.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7c6ed44d6c64562d2eb723fb9c7446954ed9187c --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/getSwappedComparison.cpp @@ -0,0 +1,10 @@ +static Kind getSwappedComparison ( Kind Cmp ) { +assert ( ( ! ( ( Cmp & L ) && ( Cmp & G ) ) ) && "Malformed comparison operator" ) ; +if ( Cmp & L ) { +return ( Kind ) ( Cmp ^ ( L | G ) ) ; +} +if ( Cmp & G ) { +return ( Kind ) ( Cmp ^ ( L | G ) ) ; +} +return Cmp ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/isDead.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/isDead.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4d515edb75bcef3225d017ab73686855b8f626c0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/isDead.cpp @@ -0,0 +1,42 @@ +bool PULPHardwareLoops :: isDead ( const MachineInstr * MI , SmallVectorImpl < MachineInstr * > & DeadPhis ) const { +for ( unsigned i = 0 , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { +const MachineOperand & MO = MI -> getOperand ( i ) ; +if ( MO . isReg ( ) && MO . isDef ( ) ) { +unsigned Reg = MO . getReg ( ) ; +if ( ! MRI -> use_nodbg_empty ( Reg ) ) { +MachineRegisterInfo :: use_nodbg_iterator I = MRI -> use_nodbg_begin ( Reg ) ; +MachineRegisterInfo :: use_nodbg_iterator End = MRI -> use_nodbg_end ( ) ; +if ( std :: next ( I ) == End ) { +if ( I -> getParent ( ) -> isPHI ( ) ) { +MachineInstr * OnePhi = I . getOperand ( ) . getParent ( ) ; +for ( unsigned j = 0 , f = OnePhi -> getNumOperands ( ) ; j != f ; ++ j ) { +const MachineOperand & OPO = OnePhi -> getOperand ( j ) ; +if ( OPO . isReg ( ) ) { +if ( OPO . isDef ( ) ) { +unsigned OPReg = OPO . getReg ( ) ; +MachineRegisterInfo :: use_nodbg_iterator nextJ ; +for ( MachineRegisterInfo :: use_nodbg_iterator J = MRI -> use_nodbg_begin ( OPReg ) ; J != End ; J = nextJ ) { +nextJ = std :: next ( J ) ; +MachineOperand & Use = * J ; +MachineInstr * UseMI = Use . getParent ( ) ; +if ( MI != UseMI ) { +return false ; +} +} +} +} +} +} +DeadPhis . push_back ( OnePhi ) ; +} +if ( std :: next ( I ) != End ) { +return false ; +} +if ( ! I -> getParent ( ) -> isPHI ( ) ) { +return false ; +} +} +} +} +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/isImm.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/isImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..680c98be8c03fd333032f8f00b0a1a98ea862ae7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/isImm.cpp @@ -0,0 +1,3 @@ +bool isImm ( ) const { +return Kind == CV_Immediate ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/isInvalidLoopOperation.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/isInvalidLoopOperation.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b92780621f8345b3e7924637298a02ddf20317ea --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/isInvalidLoopOperation.cpp @@ -0,0 +1,36 @@ +bool PULPHardwareLoops :: isInvalidLoopOperation ( const MachineInstr * MI ) const { +if ( MI -> getDesc ( ) . isCall ( ) ) { +return true ; +} +if ( isHardwareLoop ( MI ) ) { +return true ; +} +for ( unsigned i = 0 , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { +const MachineOperand & MO = MI -> getOperand ( i ) ; +if ( ! MO . isReg ( ) ) { +continue ; +} +if ( ! MO . isDef ( ) ) { +continue ; +} +if ( MO . getReg ( ) == PULP :: LC0 ) { +return true ; +} +if ( MO . getReg ( ) == PULP :: LC1 ) { +return true ; +} +if ( MO . getReg ( ) == PULP :: SA0 ) { +return true ; +} +if ( MO . getReg ( ) == PULP :: SA1 ) { +return true ; +} +if ( MO . getReg ( ) == PULP :: CTR ) { +return true ; +} +if ( MO . getReg ( ) == PULP :: CTR8 ) { +return true ; +} +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/isLoopFeeder.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/isLoopFeeder.cpp new file mode 100644 index 0000000000000000000000000000000000000000..80a0cb3a9afcd42a5c021e28f26ec397434b7d0c --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/isLoopFeeder.cpp @@ -0,0 +1,14 @@ +bool PULPHardwareLoops :: isLoopFeeder ( MachineLoop * L , MachineBasicBlock * A , MachineInstr * MI , const MachineOperand * MO , LoopFeederMap & LoopFeederPhi ) const { +if ( LoopFeederPhi . find ( MO -> getReg ( ) ) == LoopFeederPhi . end ( ) ) { +LLVM_DEBUG ( dbgs ( ) << "\nhw_loop head, " << printMBBReference ( * * L -> block_begin ( ) ) ) ; +for ( MachineBasicBlock * MBB : L -> getBlocks ( ) ) { +if ( A == MBB ) { +return false ; +} +} +MachineInstr * Def = MRI -> getVRegDef ( MO -> getReg ( ) ) ; +LoopFeederPhi . insert ( std :: make_pair ( MO -> getReg ( ) , Def ) ) ; +return true ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/isReg.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/isReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c02a2f99d0033d1211ac86164fca924d4fb7a003 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/isReg.cpp @@ -0,0 +1,3 @@ +bool isReg ( ) const { +return Kind == CV_Register ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/isSigned.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/isSigned.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d728346e98cf1c2b2809437cc84328a2cefce4d6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/isSigned.cpp @@ -0,0 +1,3 @@ +static bool isSigned ( Kind Cmp ) { +return ( Cmp & ( L | G ) && ! ( Cmp & U ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/isUnsigned.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/isUnsigned.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c4f08102b8f8ca2a83f98f07a8863cdbe6eeab70 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/isUnsigned.cpp @@ -0,0 +1,3 @@ +static bool isUnsigned ( Kind Cmp ) { +return ( Cmp & U ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/loopCountMayWrapOrUnderFlow.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/loopCountMayWrapOrUnderFlow.cpp new file mode 100644 index 0000000000000000000000000000000000000000..279bed7ed3c56d07c7518ba49e46deaa0ff875ca --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/loopCountMayWrapOrUnderFlow.cpp @@ -0,0 +1,73 @@ +bool PULPHardwareLoops :: loopCountMayWrapOrUnderFlow ( const MachineOperand * InitVal , const MachineOperand * EndVal , MachineBasicBlock * MBB , MachineLoop * L , LoopFeederMap & LoopFeederPhi ) const { +if ( ! InitVal -> isReg ( ) ) { +return false ; +} +if ( ! EndVal -> isImm ( ) ) { +return false ; +} +int64_t Imm ; +if ( checkForImmediate ( * InitVal , Imm ) ) { +return EndVal -> getImm ( ) == Imm ; +} +Register Reg = InitVal -> getReg ( ) ; +if ( ! Reg . isVirtual ( ) ) { +return true ; +} +MachineInstr * Def = MRI -> getVRegDef ( Reg ) ; +if ( ! Def ) { +return true ; +} +if ( Def -> isPHI ( ) ) { +if ( ! phiMayWrapOrUnderflow ( Def , EndVal , Def -> getParent ( ) , L , LoopFeederPhi ) ) { +return false ; +} +} +if ( Def -> isCopy ( ) ) { +if ( ! loopCountMayWrapOrUnderFlow ( & ( Def -> getOperand ( 1 ) ) , EndVal , Def -> getParent ( ) , L , LoopFeederPhi ) ) { +return false ; +} +} +for ( MachineRegisterInfo :: use_instr_nodbg_iterator I = MRI -> use_instr_nodbg_begin ( Reg ) , E = MRI -> use_instr_nodbg_end ( ) ; I != E ; ++ I ) { +MachineInstr * MI = & * I ; +Register CmpReg1 = 0 ; +Register CmpReg2 = 0 ; +int CmpMask = 0 ; +int CmpValue = 0 ; +if ( ! TII -> analyzeCompare ( * MI , CmpReg1 , CmpReg2 , CmpMask , CmpValue ) ) { +continue ; +} +MachineBasicBlock * TBB = nullptr ; +MachineBasicBlock * FBB = nullptr ; +SmallVector < MachineOperand , 2 > Cond ; +if ( TII -> analyzeBranch ( * MI -> getParent ( ) , TBB , FBB , Cond , false ) ) { +continue ; +} +Comparison :: Kind Cmp = getComparisonKind ( MI -> getOpcode ( ) , nullptr , nullptr , 0 ) ; +if ( Cmp == 0 ) { +continue ; +} +if ( TII -> predOpcodeHasNot ( Cond ) ^ ( TBB != MBB ) ) { +Cmp = Comparison :: getNegatedComparison ( Cmp ) ; +} +if ( CmpReg2 != 0 ) { +if ( CmpReg2 == Reg ) { +Cmp = Comparison :: getSwappedComparison ( Cmp ) ; +} +} +if ( Comparison :: isSigned ( Cmp ) ) { +return false ; +} +if ( Cmp & Comparison :: G ) { +return false ; +} +if ( Cmp == Comparison :: NE ) { +return false ; +} +} +if ( ! Def -> isCopy ( ) ) { +if ( ! Def -> isPHI ( ) ) { +return false ; +} +} +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/phiMayWrapOrUnderflow.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/phiMayWrapOrUnderflow.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9a12f0aed9270681a899e1f9239853a444f90b5c --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/phiMayWrapOrUnderflow.cpp @@ -0,0 +1,11 @@ +bool PULPHardwareLoops :: phiMayWrapOrUnderflow ( MachineInstr * Phi , const MachineOperand * EndVal , MachineBasicBlock * MBB , MachineLoop * L , LoopFeederMap & LoopFeederPhi ) const { +assert ( Phi -> isPHI ( ) && "Expecting a Phi." ) ; +for ( int i = 1 , n = Phi -> getNumOperands ( ) ; i < n ; i += 2 ) { +if ( isLoopFeeder ( L , MBB , Phi , & ( Phi -> getOperand ( i ) ) , LoopFeederPhi ) ) { +if ( loopCountMayWrapOrUnderFlow ( & ( Phi -> getOperand ( i ) ) , EndVal , Phi -> getParent ( ) , L , LoopFeederPhi ) ) { +return true ; +} +} +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/print.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/print.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3ec36822e1fb42512cca1ae2e4f555c41b35dad3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/print.cpp @@ -0,0 +1,8 @@ +void print ( raw_ostream & OS , const TargetRegisterInfo * TRI = nullptr ) const { +if ( isReg ( ) ) { +OS << "register: " << printReg ( Contents . R . Reg , TRI , Contents . R . Sub ) << '\n' ; +} +if ( isImm ( ) ) { +OS << "immediate: " << Contents . ImmVal << '\n' ; +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/removeIfDead.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/removeIfDead.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6ac31f30839c62263d76d277dab25f3ff1d3abc6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/removeIfDead.cpp @@ -0,0 +1,32 @@ +void PULPHardwareLoops :: removeIfDead ( MachineInstr * MI ) { +SmallVector < MachineInstr * , 1 > DeadPhis ; +if ( isDead ( MI , DeadPhis ) ) { +LLVM_DEBUG ( dbgs ( ) << "HW looping will remove: " << * MI ) ; +for ( unsigned i = 0 , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { +const MachineOperand & MO = MI -> getOperand ( i ) ; +if ( ! MO . isReg ( ) ) { +continue ; +} +if ( ! MO . isDef ( ) ) { +continue ; +} +unsigned Reg = MO . getReg ( ) ; +MachineRegisterInfo :: use_iterator nextI ; +for ( MachineRegisterInfo :: use_iterator I = MRI -> use_begin ( Reg ) , E = MRI -> use_end ( ) ; I != E ; I = nextI ) { +nextI = std :: next ( I ) ; +MachineOperand & Use = * I ; +MachineInstr * UseMI = I -> getParent ( ) ; +if ( UseMI == MI ) { +continue ; +} +if ( Use . isDebug ( ) ) { +UseMI -> getOperand ( 0 ) . setReg ( 0U ) ; +} +} +} +MI -> eraseFromParent ( ) ; +for ( unsigned i = 0 ; i < DeadPhis . size ( ) ; ++ i ) { +DeadPhis [ i ] -> eraseFromParent ( ) ; +} +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..16633673f1c397ec72c6b5f26831b0a8ff146777 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/runOnMachineFunction.cpp @@ -0,0 +1,14 @@ +bool PULPFrepLoops :: runOnMachineFunction ( MachineFunction & MF ) { +LLVM_DEBUG ( dbgs ( ) << "------------ PULP Frep Loops ------------\n" ) ; +bool Changed = false ; +MLI = & getAnalysis < MachineLoopInfo > ( ) ; +MDT = & getAnalysis < MachineDominatorTree > ( ) ; +TII = MF . getSubtarget < PULPSubtarget > ( ) . getInstrInfo ( ) ; +for ( auto & L : * MLI ) +if ( ! L -> getParentLoop ( ) ) { +bool L0Used = false ; +bool L1Used = false ; +Changed = Changed | convertToHardwareLoop ( L , L0Used , L1Used ) ; +} +return Changed ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/unionValues.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/unionValues.cpp new file mode 100644 index 0000000000000000000000000000000000000000..96b70faea4c2d1cf3c27369e98a584955a9138d0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/PULPHardWareLoops/unionValues.cpp @@ -0,0 +1,7 @@ +union Values { +struct { +unsigned Reg ; +unsigned Sub ; +} R ; +unsigned ImmVal ; +} Contents ; \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/CountValue.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/CountValue.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ee8c980c44d93f1d05491bc44ed5f820d1fe34b5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/CountValue.cpp @@ -0,0 +1,10 @@ +explicit CountValue ( CountValueType t , unsigned v , unsigned u = 0 ) { +Kind = t ; +if ( Kind == CV_Register ) { +Contents . R . Reg = v ; +Contents . R . Sub = u ; +} +if ( Kind != CV_Register ) { +Contents . ImmVal = v ; +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/FrepLoop.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/FrepLoop.cpp new file mode 100644 index 0000000000000000000000000000000000000000..13936cfca703d35d770e43949d27e63bbf244673 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/FrepLoop.cpp @@ -0,0 +1,3 @@ +explicit FrepLoop ( MachineLoop * ML ) { +L = ML ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/FrepLoopsPass.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/FrepLoopsPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..76de241fa75ec2b2b96de00673900aec866a6bc1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/FrepLoopsPass.cpp @@ -0,0 +1,3 @@ +PULPFrepLoops ( ) : MachineFunctionPass ( ID ) { +initializePULPFrepLoopsPass ( * PassRegistry :: getPassRegistry ( ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/SNITCHFrepLoops.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/SNITCHFrepLoops.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9b4e37e0af58cc8245b4eba37735a07b26093555 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/SNITCHFrepLoops.cpp @@ -0,0 +1,3 @@ +SNITCHFrepLoops() : MachineFunctionPass(ID) { + initializeSNITCHFrepLoopsPass(*PassRegistry::getPassRegistry()); +} diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/checkForImmediate.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/checkForImmediate.cpp new file mode 100644 index 0000000000000000000000000000000000000000..035417a4a3d7b0eb531137a5d1163be7121d09ac --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/checkForImmediate.cpp @@ -0,0 +1,218 @@ +bool PULPFrepLoops :: checkForImmediate ( const MachineOperand & MO , int64_t & Val ) const { +if ( MO . isImm ( ) ) { +Val = MO . getImm ( ) ; +return true ; +} +if ( ! MO . isReg ( ) ) { +return false ; +} +int64_t TV ; +Register R = MO . getReg ( ) ; +if ( ! R . isVirtual ( ) ) { +return false ; +} +MachineInstr * DI = MRI -> getVRegDef ( R ) ; +unsigned DOpc = DI -> getOpcode ( ) ; +if ( DOpc == TargetOpcode :: COPY ) { +if ( ! checkForImmediate ( DI -> getOperand ( 1 ) , TV ) ) { +return false ; +} +if ( MO . getSubReg ( ) == PULP :: subreg_loreg ) { +Val = TV & 0xFFFFFFFFULL ; +} +if ( MO . getSubReg ( ) == PULP :: subreg_hireg ) { +Val = TV & 0xFFFFFFFFULL ; +Val = ( TV >> 32 ) & 0xFFFFFFFFULL ; +} +Val = TV ; +return true ; +} +if ( DOpc == PULP :: A2_tfrsi ) { +if ( ! checkForImmediate ( DI -> getOperand ( 1 ) , TV ) ) { +return false ; +} +if ( MO . getSubReg ( ) == PULP :: subreg_loreg ) { +Val = TV & 0xFFFFFFFFULL ; +} +if ( MO . getSubReg ( ) == PULP :: subreg_hireg ) { +Val = TV & 0xFFFFFFFFULL ; +Val = ( TV >> 32 ) & 0xFFFFFFFFULL ; +} +Val = TV ; +return true ; +} +if ( DOpc == PULP :: A2_tfrpi ) { +if ( ! checkForImmediate ( DI -> getOperand ( 1 ) , TV ) ) { +return false ; +} +if ( MO . getSubReg ( ) == PULP :: subreg_loreg ) { +Val = TV & 0xFFFFFFFFULL ; +} +if ( MO . getSubReg ( ) == PULP :: subreg_hireg ) { +Val = TV & 0xFFFFFFFFULL ; +Val = ( TV >> 32 ) & 0xFFFFFFFFULL ; +} +Val = TV ; +return true ; +} +if ( DOpc == PULP :: CONST32_Int_Real ) { +if ( ! checkForImmediate ( DI -> getOperand ( 1 ) , TV ) ) { +return false ; +} +if ( MO . getSubReg ( ) == PULP :: subreg_loreg ) { +Val = TV & 0xFFFFFFFFULL ; +} +if ( MO . getSubReg ( ) == PULP :: subreg_hireg ) { +Val = TV & 0xFFFFFFFFULL ; +Val = ( TV >> 32 ) & 0xFFFFFFFFULL ; +} +Val = TV ; +return true ; +} +if ( DOpc == PULP :: CONST64_Int_Real ) { +if ( ! checkForImmediate ( DI -> getOperand ( 1 ) , TV ) ) { +return false ; +} +if ( MO . getSubReg ( ) == PULP :: subreg_loreg ) { +Val = TV & 0xFFFFFFFFULL ; +} +if ( MO . getSubReg ( ) == PULP :: subreg_hireg ) { +Val = TV & 0xFFFFFFFFULL ; +Val = ( TV >> 32 ) & 0xFFFFFFFFULL ; +} +Val = TV ; +return true ; +} +if ( DOpc == PULP :: A2_combineii ) { +const MachineOperand & S1 = DI -> getOperand ( 1 ) ; +const MachineOperand & S2 = DI -> getOperand ( 2 ) ; +int64_t V1 ; +int64_t V2 ; +if ( ! checkForImmediate ( S1 , V1 ) ) { +return false ; +} +if ( ! checkForImmediate ( S2 , V2 ) ) { +return false ; +} +TV = V2 | ( V1 << 32 ) ; +if ( MO . getSubReg ( ) == PULP :: subreg_loreg ) { +Val = TV & 0xFFFFFFFFULL ; +} +if ( MO . getSubReg ( ) == PULP :: subreg_hireg ) { +Val = TV & 0xFFFFFFFFULL ; +Val = ( TV >> 32 ) & 0xFFFFFFFFULL ; +} +Val = TV ; +return true ; +} +if ( DOpc == PULP :: A4_combineir ) { +const MachineOperand & S1 = DI -> getOperand ( 1 ) ; +const MachineOperand & S2 = DI -> getOperand ( 2 ) ; +int64_t V1 ; +int64_t V2 ; +if ( ! checkForImmediate ( S1 , V1 ) ) { +return false ; +} +if ( ! checkForImmediate ( S2 , V2 ) ) { +return false ; +} +TV = V2 | ( V1 << 32 ) ; +if ( MO . getSubReg ( ) == PULP :: subreg_loreg ) { +Val = TV & 0xFFFFFFFFULL ; +} +if ( MO . getSubReg ( ) == PULP :: subreg_hireg ) { +Val = TV & 0xFFFFFFFFULL ; +Val = ( TV >> 32 ) & 0xFFFFFFFFULL ; +} +Val = TV ; +return true ; +} +if ( DOpc == PULP :: A4_combineii ) { +const MachineOperand & S1 = DI -> getOperand ( 1 ) ; +const MachineOperand & S2 = DI -> getOperand ( 2 ) ; +int64_t V1 ; +int64_t V2 ; +if ( ! checkForImmediate ( S1 , V1 ) ) { +return false ; +} +if ( ! checkForImmediate ( S2 , V2 ) ) { +return false ; +} +TV = V2 | ( V1 << 32 ) ; +if ( MO . getSubReg ( ) == PULP :: subreg_loreg ) { +Val = TV & 0xFFFFFFFFULL ; +} +if ( MO . getSubReg ( ) == PULP :: subreg_hireg ) { +Val = TV & 0xFFFFFFFFULL ; +Val = ( TV >> 32 ) & 0xFFFFFFFFULL ; +} +Val = TV ; +return true ; +} +if ( DOpc == PULP :: A4_combineri ) { +const MachineOperand & S1 = DI -> getOperand ( 1 ) ; +const MachineOperand & S2 = DI -> getOperand ( 2 ) ; +int64_t V1 ; +int64_t V2 ; +if ( ! checkForImmediate ( S1 , V1 ) ) { +return false ; +} +if ( ! checkForImmediate ( S2 , V2 ) ) { +return false ; +} +TV = V2 | ( V1 << 32 ) ; +if ( MO . getSubReg ( ) == PULP :: subreg_loreg ) { +Val = TV & 0xFFFFFFFFULL ; +} +if ( MO . getSubReg ( ) == PULP :: subreg_hireg ) { +Val = TV & 0xFFFFFFFFULL ; +Val = ( TV >> 32 ) & 0xFFFFFFFFULL ; +} +Val = TV ; +return true ; +} +if ( DOpc == PULP :: A2_combinew ) { +const MachineOperand & S1 = DI -> getOperand ( 1 ) ; +const MachineOperand & S2 = DI -> getOperand ( 2 ) ; +int64_t V1 ; +int64_t V2 ; +if ( ! checkForImmediate ( S1 , V1 ) ) { +return false ; +} +if ( ! checkForImmediate ( S2 , V2 ) ) { +return false ; +} +TV = V2 | ( V1 << 32 ) ; +if ( MO . getSubReg ( ) == PULP :: subreg_loreg ) { +Val = TV & 0xFFFFFFFFULL ; +} +if ( MO . getSubReg ( ) == PULP :: subreg_hireg ) { +Val = TV & 0xFFFFFFFFULL ; +Val = ( TV >> 32 ) & 0xFFFFFFFFULL ; +} +Val = TV ; +return true ; +} +if ( DOpc == TargetOpcode :: REG_SEQUENCE ) { +const MachineOperand & S1 = DI -> getOperand ( 1 ) ; +const MachineOperand & S3 = DI -> getOperand ( 3 ) ; +int64_t V1 ; +int64_t V3 ; +if ( ! checkForImmediate ( S1 , V1 ) ) { +return false ; +} +if ( ! checkForImmediate ( S3 , V3 ) ) { +return false ; +} +unsigned Sub2 = DI -> getOperand ( 2 ) . getImm ( ) ; +unsigned Sub4 = DI -> getOperand ( 4 ) . getImm ( ) ; +if ( MO . getSubReg ( ) == PULP :: subreg_loreg ) { +TV = V1 | ( V3 << 32 ) ; +} +if ( MO . getSubReg ( ) == PULP :: subreg_hireg ) { +TV = V3 | ( V1 << 32 ) ; +} +llvm_unreachable ( "Unexpected form of REG_SEQUENCE" ) ; +return true ; +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/containsInvalidInstruction.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/containsInvalidInstruction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ee654739abe4fe280d9b835c5824b2db4cf2eaae --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/containsInvalidInstruction.cpp @@ -0,0 +1,11 @@ +bool PULPHardwareLoops :: containsInvalidInstruction ( MachineLoop * L ) const { +for ( MachineBasicBlock * MBB : L -> getBlocks ( ) ) { +for ( MachineInstr & MI : * MBB ) { +if ( isInvalidLoopOperation ( MI ) ) { +LLVM_DEBUG ( dbgs ( ) << "\nCannot convert to hwloop due to:" ; MI . dump ( ) ; ) ; +return true ; +} +} +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/convertToHardwareLoop.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/convertToHardwareLoop.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bbf503d3e8209a118f1b3e619a8b0c6fa04f622c --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/convertToHardwareLoop.cpp @@ -0,0 +1,156 @@ +bool PULPHardwareLoops :: convertToHardwareLoop ( MachineLoop * L , bool & RecL0used , bool & RecL1used ) { +assert ( L -> getHeader ( ) && "Loop without a header?" ) ; +bool Changed = false ; +bool L0Used = false ; +bool L1Used = false ; +for ( MachineLoop :: iterator I = L -> begin ( ) , E = L -> end ( ) ; I != E ; ++ I ) { +Changed = Changed | convertToHardwareLoop ( * I , RecL0used , RecL1used ) ; +L0Used = L0Used | RecL0used ; +L1Used = L1Used | RecL1used ; +} +if ( Changed ) { +if ( L0Used ) { +if ( L1Used ) { +return Changed ; +} +} +} +unsigned LOOP_i ; +unsigned LOOP_r ; +unsigned ENDLOOP ; +unsigned IsInnerHWLoop = 1 ; +if ( L0Used ) { +LOOP_i = PULP :: J2_loop1i ; +LOOP_r = PULP :: J2_loop1r ; +ENDLOOP = PULP :: ENDLOOP1 ; +IsInnerHWLoop = 0 ; +} +if ( ! L0Used ) { +LOOP_i = PULP :: J2_loop0i ; +LOOP_r = PULP :: J2_loop0r ; +ENDLOOP = PULP :: ENDLOOP0 ; +} +if ( containsInvalidInstruction ( L , IsInnerHWLoop ) ) { +return false ; +} +MachineBasicBlock * LastMBB = getExitingBlock ( L ) ; +if ( ! LastMBB ) { +return false ; +} +MachineBasicBlock :: iterator LastI = LastMBB -> getFirstTerminator ( ) ; +if ( LastI == LastMBB -> end ( ) ) { +return false ; +} +if ( ! fixupInductionVariable ( L ) ) { +return false ; +} +MachineBasicBlock * Preheader = L -> getLoopPreheader ( ) ; +if ( ! Preheader ) { +Preheader = createPreheaderForLoop ( L ) ; +if ( ! Preheader ) { +return false ; +} +} +MachineBasicBlock :: iterator InsertPos = Preheader -> getFirstTerminator ( ) ; +SmallVector < MachineInstr * , 2 > OldInsts ; +CountValue * TripCount = getLoopTripCount ( L , OldInsts ) ; +if ( ! TripCount ) { +return false ; +} +if ( TripCount -> isReg ( ) ) { +MachineInstr * TCDef = MRI -> getVRegDef ( TripCount -> getReg ( ) ) ; +MachineBasicBlock * BBDef = TCDef -> getParent ( ) ; +if ( ! MDT -> dominates ( BBDef , Preheader ) ) { +return false ; +} +} +MachineBasicBlock * TopBlock = L -> getTopBlock ( ) ; +MachineBasicBlock * ExitingBlock = getExitingBlock ( L ) ; +MachineBasicBlock * LoopStart = 0 ; +if ( ExitingBlock != L -> getLoopLatch ( ) ) { +MachineBasicBlock * TB = 0 , * FB = 0 ; +SmallVector < MachineOperand , 2 > Cond ; +if ( TII -> analyzeBranch ( * ExitingBlock , TB , FB , Cond , false ) ) { +return false ; +} +if ( L -> contains ( TB ) ) { +LoopStart = TB ; +} +if ( L -> contains ( FB ) ) { +LoopStart = FB ; +} +if ( ! L -> contains ( TB ) ) { +if ( ! L -> contains ( FB ) ) { +return false ; +} +} +} +if ( ExitingBlock == L -> getLoopLatch ( ) ) { +LoopStart = TopBlock ; +} +DEBUG ( dbgs ( ) << "Change to hardware loop at " ; L -> dump ( ) ) ; +DebugLoc DL ; +if ( InsertPos != Preheader -> end ( ) ) { +DL = InsertPos -> getDebugLoc ( ) ; +} +if ( TripCount -> isReg ( ) ) { +unsigned CountReg = MRI -> createVirtualRegister ( & PULP :: IntRegsRegClass ) ; +BuildMI ( * Preheader , InsertPos , DL , TII -> get ( TargetOpcode :: COPY ) , CountReg ) . addReg ( TripCount -> getReg ( ) , 0 , TripCount -> getSubReg ( ) ) ; +BuildMI ( * Preheader , InsertPos , DL , TII -> get ( LOOP_r ) ) . addMBB ( LoopStart ) . addReg ( CountReg ) ; +} +if ( ! TripCount -> isReg ( ) ) { +assert ( TripCount -> isImm ( ) && "Expecting immediate value for trip count" ) ; +int64_t CountImm = TripCount -> getImm ( ) ; +if ( ! TII -> isValidOffset ( LOOP_i , CountImm ) ) { +unsigned CountReg = MRI -> createVirtualRegister ( & PULP :: IntRegsRegClass ) ; +BuildMI ( * Preheader , InsertPos , DL , TII -> get ( PULP :: A2_tfrsi ) , CountReg ) . addImm ( CountImm ) ; +BuildMI ( * Preheader , InsertPos , DL , TII -> get ( LOOP_r ) ) . addMBB ( LoopStart ) . addReg ( CountReg ) ; +} +if ( TII -> isValidOffset ( LOOP_i , CountImm ) ) { +BuildMI ( * Preheader , InsertPos , DL , TII -> get ( LOOP_i ) ) . addMBB ( LoopStart ) . addImm ( CountImm ) ; +} +} +LoopStart -> setHasAddressTaken ( ) ; +BlockAddress :: get ( const_cast < BasicBlock * > ( LoopStart -> getBasicBlock ( ) ) ) ; +DebugLoc LastIDL = LastI -> getDebugLoc ( ) ; +BuildMI ( * LastMBB , LastI , LastIDL , TII -> get ( ENDLOOP ) ) . addMBB ( LoopStart ) ; +if ( LastI -> getOpcode ( ) == PULP :: J2_jumpt ) { +MachineBasicBlock * BranchTarget = LastI -> getOperand ( 1 ) . getMBB ( ) ; +LastI = LastMBB -> erase ( LastI ) ; +if ( ! L -> contains ( BranchTarget ) ) { +if ( LastI != LastMBB -> end ( ) ) { +LastI = LastMBB -> erase ( LastI ) ; +} +SmallVector < MachineOperand , 0 > Cond ; +TII -> InsertBranch ( * LastMBB , BranchTarget , nullptr , Cond , LastIDL ) ; +} +} +if ( LastI -> getOpcode ( ) == PULP :: J2_jumpf ) { +MachineBasicBlock * BranchTarget = LastI -> getOperand ( 1 ) . getMBB ( ) ; +LastI = LastMBB -> erase ( LastI ) ; +if ( ! L -> contains ( BranchTarget ) ) { +if ( LastI != LastMBB -> end ( ) ) { +LastI = LastMBB -> erase ( LastI ) ; +} +SmallVector < MachineOperand , 0 > Cond ; +TII -> InsertBranch ( * LastMBB , BranchTarget , nullptr , Cond , LastIDL ) ; +} +} +if ( LastI -> getOpcode ( ) != PULP :: J2_jumpt ) { +if ( LastI -> getOpcode ( ) != PULP :: J2_jumpf ) { +LastMBB -> erase ( LastI ) ; +} +} +delete TripCount ; +for ( unsigned i = 0 ; i < OldInsts . size ( ) ; ++ i ) { +removeIfDead ( OldInsts [ i ] ) ; +} +NumHWLoops = NumHWLoops + 1 ; +if ( L0Used ) { +RecL1used = true ; +} +if ( ! L0Used ) { +RecL0used = true ; +} +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/createPass.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/createPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8f53e20d5f654191a88633fc0a94a9d966670635 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/createPass.cpp @@ -0,0 +1,3 @@ +FunctionPass * createPULPFrepLoopsPass ( ) { +return new PULPFrepLoops ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/createSNITCHFrepLoopsPass.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/createSNITCHFrepLoopsPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..08c67b5d3aca9dafc9d664780176f3a1114b9854 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/createSNITCHFrepLoopsPass.cpp @@ -0,0 +1,3 @@ +FunctionPass *createSNITCHFrepLoopsPass() { + return new SNITCHFrepLoops(); +} diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/enumCountValueType.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/enumCountValueType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ed7f2c9968b3fed4477bd9c3d08bb562c76ac4fb --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/enumCountValueType.cpp @@ -0,0 +1,4 @@ +enum CountValueType { +CV_Register , +CV_Immediate +} ; \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/enumKind.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/enumKind.cpp new file mode 100644 index 0000000000000000000000000000000000000000..de0cf91473ebe1e290307572f8ca6f52f0a64904 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/enumKind.cpp @@ -0,0 +1,15 @@ +enum Kind { +EQ = 0x01 , +NE = 0x02 , +L = 0x04 , +G = 0x08 , +U = 0x40 , +LTs = L , +LEs = L | EQ , +GTs = G , +GEs = G | EQ , +LTu = L | U , +LEu = L | EQ | U , +GTu = G | U , +GEu = G | EQ | U +} ; \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/findBranchInstruction.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/findBranchInstruction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6f017b2997a1970a44c430388c4b7753fcd9dc22 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/findBranchInstruction.cpp @@ -0,0 +1,86 @@ +const MachineInstr * PULPFrepLoops :: findBranchInstruction ( MachineLoop * L ) { +MachineBasicBlock * Preheader = MLI -> findLoopPreheader ( L , SpecPreheader ) ; +MachineBasicBlock * Header = L -> getHeader ( ) ; +MachineBasicBlock * Latch = L -> getLoopLatch ( ) ; +MachineBasicBlock * ExitingBlock = L -> findLoopControlBlock ( ) ; +if ( ! Header ) { +return false ; +} +if ( ! Preheader ) { +return false ; +} +if ( ! Latch ) { +return false ; +} +if ( ! ExitingBlock ) { +return false ; +} +using RegisterBump = std :: pair < unsigned , int64_t > ; +using InductionMap = std :: map < unsigned , RegisterBump > ; +InductionMap IndMap ; +using instr_iterator = MachineBasicBlock :: instr_iterator ; +for ( instr_iterator I = Header -> instr_begin ( ) , E = Header -> instr_end ( ) ; I != E && I -> isPHI ( ) ; ++ I ) { +MachineInstr * Phi = & * I ; +for ( unsigned i = 1 , n = Phi -> getNumOperands ( ) ; i < n ; i += 2 ) { +if ( Phi -> getOperand ( i + 1 ) . getMBB ( ) != Latch ) { +continue ; +} +unsigned PhiOpReg = Phi -> getOperand ( i ) . getReg ( ) ; +MachineInstr * DI = MRI -> getVRegDef ( PhiOpReg ) ; +if ( DI -> getDesc ( ) . getOpcode ( ) == PULP :: ADDI ) { +unsigned IndReg = DI -> getOperand ( 1 ) . getReg ( ) ; +MachineOperand & Opnd2 = DI -> getOperand ( 2 ) ; +int64_t V ; +if ( MRI -> getVRegDef ( IndReg ) == Phi ) { +if ( checkForImmediate ( Opnd2 , V ) ) { +unsigned UpdReg = DI -> getOperand ( 0 ) . getReg ( ) ; +IndMap . insert ( std :: make_pair ( UpdReg , std :: make_pair ( IndReg , V ) ) ) ; +} +} +} +} +} +SmallVector < MachineOperand , 2 > Cond ; +MachineBasicBlock * TB = nullptr , * FB = nullptr ; +bool NotAnalyzed = TII -> analyzeBranch ( * ExitingBlock , TB , FB , Cond , false ) ; +if ( NotAnalyzed ) { +return false ; +} +unsigned PredR , PredPos , PredRegFlags ; +if ( ! TII -> getPredReg ( Cond , PredR , PredPos , PredRegFlags ) ) { +return false ; +} +MachineInstr * PredI = MRI -> getVRegDef ( PredR ) ; +if ( ! PredI -> isCompare ( ) ) { +return false ; +} +unsigned CmpReg1 = 0 , CmpReg2 = 0 ; +int CmpImm = 0 , CmpMask = 0 ; +bool CmpAnalyzed = TII -> analyzeCompare ( * PredI , CmpReg1 , CmpReg2 , CmpMask , CmpImm ) ; +if ( ! CmpAnalyzed ) { +return false ; +} +InductionMap :: iterator IndMapEnd = IndMap . end ( ) ; +InductionMap :: iterator F = IndMapEnd ; +if ( CmpReg1 != 0 ) { +InductionMap :: iterator F1 = IndMap . find ( CmpReg1 ) ; +if ( F1 != IndMapEnd ) { +F = F1 ; +} +} +if ( CmpReg2 != 0 ) { +InductionMap :: iterator F2 = IndMap . find ( CmpReg2 ) ; +if ( F2 != IndMapEnd ) { +if ( F != IndMapEnd ) +return false ; +F = F2 ; +} +} +if ( F == IndMapEnd ) { +return false ; +} +Reg = F -> second . first ; +IVBump = F -> second . second ; +IVOp = MRI -> getVRegDef ( F -> first ) ; +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/findInductionRegister.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/findInductionRegister.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8854a0e598bd9b25b8c4b823e49620bfd9e17e4a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/findInductionRegister.cpp @@ -0,0 +1,86 @@ +bool PULPHardwareLoops :: findInductionRegister ( MachineLoop * L , unsigned & Reg , int64_t & IVBump , MachineInstr * & IVOp ) const { +MachineBasicBlock * Preheader = MLI -> findLoopPreheader ( L , SpecPreheader ) ; +MachineBasicBlock * Header = L -> getHeader ( ) ; +MachineBasicBlock * Latch = L -> getLoopLatch ( ) ; +MachineBasicBlock * ExitingBlock = L -> findLoopControlBlock ( ) ; +if ( ! Header ) { +return false ; +} +if ( ! Preheader ) { +return false ; +} +if ( ! Latch ) { +return false ; +} +if ( ! ExitingBlock ) { +return false ; +} +using RegisterBump = std :: pair < unsigned , int64_t > ; +using InductionMap = std :: map < unsigned , RegisterBump > ; +InductionMap IndMap ; +using instr_iterator = MachineBasicBlock :: instr_iterator ; +for ( instr_iterator I = Header -> instr_begin ( ) , E = Header -> instr_end ( ) ; I != E && I -> isPHI ( ) ; ++ I ) { +MachineInstr * Phi = & * I ; +for ( unsigned i = 1 , n = Phi -> getNumOperands ( ) ; i < n ; i += 2 ) { +if ( Phi -> getOperand ( i + 1 ) . getMBB ( ) != Latch ) { +continue ; +} +unsigned PhiOpReg = Phi -> getOperand ( i ) . getReg ( ) ; +MachineInstr * DI = MRI -> getVRegDef ( PhiOpReg ) ; +if ( DI -> getDesc ( ) . getOpcode ( ) == PULP :: ADDI ) { +unsigned IndReg = DI -> getOperand ( 1 ) . getReg ( ) ; +MachineOperand & Opnd2 = DI -> getOperand ( 2 ) ; +int64_t V ; +if ( MRI -> getVRegDef ( IndReg ) == Phi ) { +if ( checkForImmediate ( Opnd2 , V ) ) { +unsigned UpdReg = DI -> getOperand ( 0 ) . getReg ( ) ; +IndMap . insert ( std :: make_pair ( UpdReg , std :: make_pair ( IndReg , V ) ) ) ; +} +} +} +} +} +SmallVector < MachineOperand , 2 > Cond ; +MachineBasicBlock * TB = nullptr , * FB = nullptr ; +bool NotAnalyzed = TII -> analyzeBranch ( * ExitingBlock , TB , FB , Cond , false ) ; +if ( NotAnalyzed ) { +return false ; +} +unsigned PredR , PredPos , PredRegFlags ; +if ( ! TII -> getPredReg ( Cond , PredR , PredPos , PredRegFlags ) ) { +return false ; +} +MachineInstr * PredI = MRI -> getVRegDef ( PredR ) ; +if ( ! PredI -> isCompare ( ) ) { +return false ; +} +unsigned CmpReg1 = 0 , CmpReg2 = 0 ; +int CmpImm = 0 , CmpMask = 0 ; +bool CmpAnalyzed = TII -> analyzeCompare ( * PredI , CmpReg1 , CmpReg2 , CmpMask , CmpImm ) ; +if ( ! CmpAnalyzed ) { +return false ; +} +InductionMap :: iterator IndMapEnd = IndMap . end ( ) ; +InductionMap :: iterator F = IndMapEnd ; +if ( CmpReg1 != 0 ) { +InductionMap :: iterator F1 = IndMap . find ( CmpReg1 ) ; +if ( F1 != IndMapEnd ) { +F = F1 ; +} +} +if ( CmpReg2 != 0 ) { +InductionMap :: iterator F2 = IndMap . find ( CmpReg2 ) ; +if ( F2 != IndMapEnd ) { +if ( F != IndMapEnd ) +return false ; +F = F2 ; +} +} +if ( F == IndMapEnd ) { +return false ; +} +Reg = F -> second . first ; +IVBump = F -> second . second ; +IVOp = MRI -> getVRegDef ( F -> first ) ; +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/getAnalysisUsage.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/getAnalysisUsage.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f094f032585ed58ef522e13ff3f7e356125fea65 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/getAnalysisUsage.cpp @@ -0,0 +1,5 @@ +void getAnalysisUsage ( AnalysisUsage & AU ) const override { +AU . addRequired < MachineDominatorTree > ( ) ; +AU . addRequired < MachineLoopInfo > ( ) ; +MachineFunctionPass :: getAnalysisUsage ( AU ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/getComparisonKind.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/getComparisonKind.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e6384f0de23448ecb81ca6aabc3ce26cac784a10 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/getComparisonKind.cpp @@ -0,0 +1,22 @@ +PULPFrepLoops :: Comparison :: Kind PULPFrepLoops :: getComparisonKind ( unsigned CondOpc , MachineOperand * InitialValue , const MachineOperand * EndValue , int64_t IVBump ) const { +Comparison :: Kind Cmp = ( Comparison :: Kind ) 0 ; +if ( CondOpc == PULP :: BEQ ) { +return Comparison :: EQ ; +} +if ( CondOpc == PULP :: BNE ) { +return Comparison :: NE ; +} +if ( CondOpc == PULP :: BLT ) { +return Comparison :: LTs ; +} +if ( CondOpc == PULP :: BLTU ) { +return Comparison :: LTu ; +} +if ( CondOpc == PULP :: BGE ) { +return Comparison :: GEs ; +} +if ( CondOpc == PULP :: BGEU ) { +return Comparison :: GEs ; +} +return ( Comparison :: Kind ) 0 ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/getImm.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/getImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..61a9973ed8aa33286e17f9a6b7cec48dffcc69f8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/getImm.cpp @@ -0,0 +1,4 @@ +unsigned getImm ( ) const { +assert ( isImm ( ) && "Wrong CountValue accessor" ) ; +return Contents . ImmVal ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/getLoopTripCount.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/getLoopTripCount.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6a9d8e36c26eb6332d9222cc741ca28162baca95 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/getLoopTripCount.cpp @@ -0,0 +1,173 @@ +CountValue * PULPFrepLoops :: getLoopTripCount ( MachineLoop * L , SmallVectorImpl < MachineInstr * > & OldInsts ) { +MachineBasicBlock * TopMBB = L -> getTopBlock ( ) ; +MachineBasicBlock :: pred_iterator PI = TopMBB -> pred_begin ( ) ; +assert ( PI != TopMBB -> pred_end ( ) && "Loop must have more than one incoming edge!" ) ; +MachineBasicBlock * Backedge = * PI ++ ; +if ( PI == TopMBB -> pred_end ( ) ) { +return nullptr ; +} +MachineBasicBlock * Incoming = * PI ++ ; +if ( PI != TopMBB -> pred_end ( ) ) { +return nullptr ; +} +if ( L -> contains ( Incoming ) ) { +if ( L -> contains ( Backedge ) ) { +return nullptr ; +} +std :: swap ( Incoming , Backedge ) ; +} +if ( ! L -> contains ( Incoming ) ) { +if ( ! L -> contains ( Backedge ) ) { +return nullptr ; +} +} +MachineBasicBlock * ExitingBlock = L -> findLoopControlBlock ( ) ; +if ( ! ExitingBlock ) { +return nullptr ; +} +unsigned IVReg = 0 ; +int64_t IVBump = 0 ; +MachineInstr * IVOp ; +bool FoundIV = findInductionRegister ( L , IVReg , IVBump , IVOp ) ; +if ( ! FoundIV ) { +return nullptr ; +} +MachineBasicBlock * Preheader = MLI -> findLoopPreheader ( L , SpecPreheader ) ; +MachineOperand * InitialValue = nullptr ; +MachineInstr * IV_Phi = MRI -> getVRegDef ( IVReg ) ; +MachineBasicBlock * Latch = L -> getLoopLatch ( ) ; +for ( unsigned i = 1 , n = IV_Phi -> getNumOperands ( ) ; i < n ; i += 2 ) { +MachineBasicBlock * MBB = IV_Phi -> getOperand ( i + 1 ) . getMBB ( ) ; +if ( MBB == Preheader ) { +InitialValue = & IV_Phi -> getOperand ( i ) ; +} +if ( MBB != Preheader ) { +if ( MBB == Latch ) { +IVReg = IV_Phi -> getOperand ( i ) . getReg ( ) ; +} +} +} +if ( ! InitialValue ) { +return nullptr ; +} +SmallVector < MachineOperand , 2 > Cond ; +MachineBasicBlock * TB = nullptr ; +MachineBasicBlock * FB = nullptr ; +bool NotAnalyzed = TII -> analyzeBranch ( * ExitingBlock , TB , FB , Cond , false ) ; +if ( NotAnalyzed ) { +return nullptr ; +} +MachineBasicBlock * Header = L -> getHeader ( ) ; +assert ( TB && "Exit block without a branch?" ) ; +if ( ExitingBlock != Latch ) { +if ( TB == Latch ) { +MachineBasicBlock * LTB = nullptr ; +MachineBasicBlock * LFB = nullptr ; +SmallVector < MachineOperand , 2 > LCond ; +bool NotAnalyzed = TII -> analyzeBranch ( * Latch , LTB , LFB , LCond , false ) ; +if ( NotAnalyzed ) { +return nullptr ; +} +TB = ( LTB == Header ) ? LTB : LFB ; +} +if ( TB != Latch ) { +if ( FB == Latch ) { +MachineBasicBlock * LTB = nullptr ; +MachineBasicBlock * LFB = nullptr ; +SmallVector < MachineOperand , 2 > LCond ; +bool NotAnalyzed = TII -> analyzeBranch ( * Latch , LTB , LFB , LCond , false ) ; +if ( NotAnalyzed ) { +return nullptr ; +} +FB = ( LTB == Header ) ? LTB : LFB ; +} +} +} +assert ( ( ! FB || TB == Header || FB == Header ) && "Branches not to header?" ) ; +if ( ! TB ) { +return nullptr ; +} +if ( FB ) { +if ( TB != Header ) { +if ( FB != Header ) { +return nullptr ; +} +} +} +bool Negated = TII -> predOpcodeHasNot ( Cond ) ^ ( TB != Header ) ; +unsigned PredReg ; +unsigned PredPos ; +unsigned PredRegFlags ; +if ( ! TII -> getPredReg ( Cond , PredReg , PredPos , PredRegFlags ) ) { +return nullptr ; +} +MachineInstr * CondI = MRI -> getVRegDef ( PredReg ) ; +unsigned CondOpc = CondI -> getOpcode ( ) ; +unsigned CmpReg1 ; +unsigned CmpReg2 ; +int Mask = 0 ; +int ImmValue = 0 ; +bool AnalyzedCmp = TII -> analyzeCompare ( * CondI , CmpReg1 , CmpReg2 , Mask , ImmValue ) ; +if ( ! AnalyzedCmp ) { +return nullptr ; +} +OldInsts . push_back ( CondI ) ; +OldInsts . push_back ( IVOp ) ; +Comparison :: Kind Cmp ; +bool isSwapped = false ; +const MachineOperand & Op1 = CondI -> getOperand ( 1 ) ; +const MachineOperand & Op2 = CondI -> getOperand ( 2 ) ; +const MachineOperand * EndValue = nullptr ; +if ( Op1 . isReg ( ) ) { +if ( Op2 . isImm ( ) ) { +EndValue = & Op2 ; +} +if ( ! Op2 . isImm ( ) ) { +if ( Op1 . getReg ( ) == IVReg ) { +EndValue = & Op2 ; +} +} +if ( ! Op2 . isImm ( ) ) { +if ( Op1 . getReg ( ) != IVReg ) { +EndValue = & Op1 ; +isSwapped = true ; +} +} +} +if ( ! EndValue ) { +return nullptr ; +} +Cmp = getComparisonKind ( CondOpc , InitialValue , EndValue , IVBump ) ; +if ( ! Cmp ) { +return nullptr ; +} +if ( Negated ) { +Cmp = Comparison :: getNegatedComparison ( Cmp ) ; +} +if ( isSwapped ) { +Cmp = Comparison :: getSwappedComparison ( Cmp ) ; +} +if ( InitialValue -> isReg ( ) ) { +unsigned R = InitialValue -> getReg ( ) ; +MachineBasicBlock * DefBB = MRI -> getVRegDef ( R ) -> getParent ( ) ; +if ( ! MDT -> properlyDominates ( DefBB , Header ) ) { +int64_t V ; +if ( ! checkForImmediate ( * InitialValue , V ) ) { +return nullptr ; +} +} +OldInsts . push_back ( MRI -> getVRegDef ( R ) ) ; +} +if ( EndValue -> isReg ( ) ) { +unsigned R = EndValue -> getReg ( ) ; +MachineBasicBlock * DefBB = MRI -> getVRegDef ( R ) -> getParent ( ) ; +if ( ! MDT -> properlyDominates ( DefBB , Header ) ) { +int64_t V ; +if ( ! checkForImmediate ( * EndValue , V ) ) { +return nullptr ; +} +} +OldInsts . push_back ( MRI -> getVRegDef ( R ) ) ; +} +return computeCount ( L , InitialValue , EndValue , IVReg , IVBump , Cmp ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/getNegatedComparison.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/getNegatedComparison.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2412e32e79ee9f8b82866a4230dee4038eb8250a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/getNegatedComparison.cpp @@ -0,0 +1,15 @@ +static Kind getNegatedComparison ( Kind Cmp ) { +if ( Cmp & L ) { +return ( Kind ) ( ( Cmp ^ ( L | G ) ) ^ EQ ) ; +} +if ( Cmp & G ) { +return ( Kind ) ( ( Cmp ^ ( L | G ) ) ^ EQ ) ; +} +if ( Cmp & NE ) { +return ( Kind ) ( Cmp ^ ( EQ | NE ) ) ; +} +if ( Cmp & EQ ) { +return ( Kind ) ( Cmp ^ ( EQ | NE ) ) ; +} +return ( Kind ) 0 ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/getPassName.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..058a1bf6f230944504a09707a41666a39e4b52e3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/getPassName.cpp @@ -0,0 +1,3 @@ +StringRef getPassName ( ) const override { +return PULP_FREP_LOOPS_NAME ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/getReg.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/getReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5a5b2c5e0312f971a08d886e42c8e74a2864bfed --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/getReg.cpp @@ -0,0 +1,4 @@ +unsigned getReg ( ) const { +assert ( isReg ( ) && "Wrong CountValue accessor" ) ; +return Contents . R . Reg ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/getSubReg.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/getSubReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..09c6a1ee80848a50e8171505de85cd829f5d6701 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/getSubReg.cpp @@ -0,0 +1,4 @@ +unsigned getSubReg ( ) const { +assert ( isReg ( ) && "Wrong CountValue accessor" ) ; +return Contents . R . Sub ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/getSwappedComparison.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/getSwappedComparison.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7c6ed44d6c64562d2eb723fb9c7446954ed9187c --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/getSwappedComparison.cpp @@ -0,0 +1,10 @@ +static Kind getSwappedComparison ( Kind Cmp ) { +assert ( ( ! ( ( Cmp & L ) && ( Cmp & G ) ) ) && "Malformed comparison operator" ) ; +if ( Cmp & L ) { +return ( Kind ) ( Cmp ^ ( L | G ) ) ; +} +if ( Cmp & G ) { +return ( Kind ) ( Cmp ^ ( L | G ) ) ; +} +return Cmp ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/isDead.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/isDead.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4ea04d9231f1d04fdc41097df9556d433c3eec3c --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/isDead.cpp @@ -0,0 +1,42 @@ +bool PULPFrepLoops :: isDead ( const MachineInstr * MI , SmallVectorImpl < MachineInstr * > & DeadPhis ) const { +for ( unsigned i = 0 , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { +const MachineOperand & MO = MI -> getOperand ( i ) ; +if ( MO . isReg ( ) && MO . isDef ( ) ) { +unsigned Reg = MO . getReg ( ) ; +if ( ! MRI -> use_nodbg_empty ( Reg ) ) { +MachineRegisterInfo :: use_nodbg_iterator I = MRI -> use_nodbg_begin ( Reg ) ; +MachineRegisterInfo :: use_nodbg_iterator End = MRI -> use_nodbg_end ( ) ; +if ( std :: next ( I ) == End ) { +if ( I -> getParent ( ) -> isPHI ( ) ) { +MachineInstr * OnePhi = I . getOperand ( ) . getParent ( ) ; +for ( unsigned j = 0 , f = OnePhi -> getNumOperands ( ) ; j != f ; ++ j ) { +const MachineOperand & OPO = OnePhi -> getOperand ( j ) ; +if ( OPO . isReg ( ) ) { +if ( OPO . isDef ( ) ) { +unsigned OPReg = OPO . getReg ( ) ; +MachineRegisterInfo :: use_nodbg_iterator nextJ ; +for ( MachineRegisterInfo :: use_nodbg_iterator J = MRI -> use_nodbg_begin ( OPReg ) ; J != End ; J = nextJ ) { +nextJ = std :: next ( J ) ; +MachineOperand & Use = * J ; +MachineInstr * UseMI = Use . getParent ( ) ; +if ( MI != UseMI ) { +return false ; +} +} +} +} +} +} +DeadPhis . push_back ( OnePhi ) ; +} +if ( std :: next ( I ) != End ) { +return false ; +} +if ( ! I -> getParent ( ) -> isPHI ( ) ) { +return false ; +} +} +} +} +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/isImm.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/isImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..680c98be8c03fd333032f8f00b0a1a98ea862ae7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/isImm.cpp @@ -0,0 +1,3 @@ +bool isImm ( ) const { +return Kind == CV_Immediate ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/isInvalidLoopOperation.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/isInvalidLoopOperation.cpp new file mode 100644 index 0000000000000000000000000000000000000000..adb8290834c47612bb2bc3515809feb03ef97cb4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/isInvalidLoopOperation.cpp @@ -0,0 +1,36 @@ +bool PULPFrepLoops :: isInvalidLoopOperation ( const MachineInstr * MI ) const { +if ( MI -> getDesc ( ) . isCall ( ) ) { +return true ; +} +if ( isHardwareLoop ( MI ) ) { +return true ; +} +for ( unsigned i = 0 , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { +const MachineOperand & MO = MI -> getOperand ( i ) ; +if ( ! MO . isReg ( ) ) { +continue ; +} +if ( ! MO . isDef ( ) ) { +continue ; +} +if ( MO . getReg ( ) == PULP :: LC0 ) { +return true ; +} +if ( MO . getReg ( ) == PULP :: LC1 ) { +return true ; +} +if ( MO . getReg ( ) == PULP :: SA0 ) { +return true ; +} +if ( MO . getReg ( ) == PULP :: SA1 ) { +return true ; +} +if ( MO . getReg ( ) == PULP :: CTR ) { +return true ; +} +if ( MO . getReg ( ) == PULP :: CTR8 ) { +return true ; +} +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/isReg.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/isReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c02a2f99d0033d1211ac86164fca924d4fb7a003 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/isReg.cpp @@ -0,0 +1,3 @@ +bool isReg ( ) const { +return Kind == CV_Register ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/isSigned.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/isSigned.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d728346e98cf1c2b2809437cc84328a2cefce4d6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/isSigned.cpp @@ -0,0 +1,3 @@ +static bool isSigned ( Kind Cmp ) { +return ( Cmp & ( L | G ) && ! ( Cmp & U ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/isUnsigned.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/isUnsigned.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c4f08102b8f8ca2a83f98f07a8863cdbe6eeab70 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/isUnsigned.cpp @@ -0,0 +1,3 @@ +static bool isUnsigned ( Kind Cmp ) { +return ( Cmp & U ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/print.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/print.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3ec36822e1fb42512cca1ae2e4f555c41b35dad3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/print.cpp @@ -0,0 +1,8 @@ +void print ( raw_ostream & OS , const TargetRegisterInfo * TRI = nullptr ) const { +if ( isReg ( ) ) { +OS << "register: " << printReg ( Contents . R . Reg , TRI , Contents . R . Sub ) << '\n' ; +} +if ( isImm ( ) ) { +OS << "immediate: " << Contents . ImmVal << '\n' ; +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/removeIfDead.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/removeIfDead.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d4baf1936c92afdbb5884279572e9fbd612ec316 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/removeIfDead.cpp @@ -0,0 +1,32 @@ +void PULPFrepLoops :: removeIfDead ( MachineInstr * MI ) { +SmallVector < MachineInstr * , 1 > DeadPhis ; +if ( isDead ( MI , DeadPhis ) ) { +LLVM_DEBUG ( dbgs ( ) << "HW looping will remove: " << * MI ) ; +for ( unsigned i = 0 , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { +const MachineOperand & MO = MI -> getOperand ( i ) ; +if ( ! MO . isReg ( ) ) { +continue ; +} +if ( ! MO . isDef ( ) ) { +continue ; +} +unsigned Reg = MO . getReg ( ) ; +MachineRegisterInfo :: use_iterator nextI ; +for ( MachineRegisterInfo :: use_iterator I = MRI -> use_begin ( Reg ) , E = MRI -> use_end ( ) ; I != E ; I = nextI ) { +nextI = std :: next ( I ) ; +MachineOperand & Use = * I ; +MachineInstr * UseMI = I -> getParent ( ) ; +if ( UseMI == MI ) { +continue ; +} +if ( Use . isDebug ( ) ) { +UseMI -> getOperand ( 0 ) . setReg ( 0U ) ; +} +} +} +MI -> eraseFromParent ( ) ; +for ( unsigned i = 0 ; i < DeadPhis . size ( ) ; ++ i ) { +DeadPhis [ i ] -> eraseFromParent ( ) ; +} +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..933b78b0c65013f30b6e0f88d80805678b437bc8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/runOnMachineFunction.cpp @@ -0,0 +1,14 @@ +bool PULPHardwareLoops :: runOnMachineFunction ( MachineFunction & MF ) { +LLVM_DEBUG ( dbgs ( ) << "------------ PULP Frep Loops ------------\n" ) ; +bool Changed = false ; +MLI = & getAnalysis < MachineLoopInfo > ( ) ; +MDT = & getAnalysis < MachineDominatorTree > ( ) ; +TII = MF . getSubtarget < PULPSubtarget > ( ) . getInstrInfo ( ) ; +for ( auto & L : * MLI ) +if ( ! L -> getParentLoop ( ) ) { +bool L0Used = false ; +bool L1Used = false ; +Changed = Changed | convertToHardwareLoop ( L , L0Used , L1Used ) ; +} +return Changed ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/unionValues.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/unionValues.cpp new file mode 100644 index 0000000000000000000000000000000000000000..96b70faea4c2d1cf3c27369e98a584955a9138d0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Optimization/SNITCHFrepLoops/unionValues.cpp @@ -0,0 +1,7 @@ +union Values { +struct { +unsigned Reg ; +unsigned Sub ; +} R ; +unsigned ImmVal ; +} Contents ; \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/InstrInfo.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/InstrInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..215d7ed4e5a82ed3dbae80f42cf769f77e3bed8b --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/InstrInfo.cpp @@ -0,0 +1,2 @@ +PULPInstrInfo :: PULPInstrInfo ( PULPSubtarget & STI ) : PULPGenInstrInfo ( PULP :: ADJCALLSTACKDOWN , PULP :: ADJCALLSTACKUP ) , STI ( STI ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/analyzeBranch.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/analyzeBranch.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4ce181d01786c7e2e743941273c59db2ed955d10 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/analyzeBranch.cpp @@ -0,0 +1,60 @@ +bool PULPInstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { +TBB = nullptr ; +FBB = nullptr ; +Cond . clear ( ) ; +MachineBasicBlock :: iterator I = MBB . getLastNonDebugInstr ( ) ; +if ( I == MBB . end ( ) ) { +return false ; +} +if ( ! isUnpredicatedTerminator ( * I ) ) { +return false ; +} +MachineBasicBlock :: iterator FirstUncondOrIndirectBr = MBB . end ( ) ; +int NumTerminators = 0 ; +for ( auto J = I . getReverse ( ) ; J != MBB . rend ( ) && isUnpredicatedTerminator ( * J ) ; J ++ ) { +NumTerminators = NumTerminators + 1 ; +if ( J -> getDesc ( ) . isUnconditionalBranch ( ) ) { +FirstUncondOrIndirectBr = J . getReverse ( ) ; +} +if ( J -> getDesc ( ) . isIndirectBranch ( ) ) { +FirstUncondOrIndirectBr = J . getReverse ( ) ; +} +} +if ( AllowModify ) { +if ( FirstUncondOrIndirectBr != MBB . end ( ) ) { +for ( ; std :: next ( FirstUncondOrIndirectBr ) != MBB . end ( ) ; ) { +std :: next ( FirstUncondOrIndirectBr ) -> eraseFromParent ( ) ; +NumTerminators = NumTerminators - 1 ; +} +I = FirstUncondOrIndirectBr ; +} +} +if ( I -> getDesc ( ) . isIndirectBranch ( ) ) { +return true ; +} +if ( NumTerminators > 2 ) { +return true ; +} +if ( NumTerminators == 1 ) { +if ( I -> getDesc ( ) . isUnconditionalBranch ( ) ) { +TBB = getBranchDestBlock ( * I ) ; +return false ; +} +} +if ( NumTerminators == 1 ) { +if ( I -> getDesc ( ) . isConditionalBranch ( ) ) { +parseCondBranch ( * I , TBB , Cond ) ; +return false ; +} +} +if ( NumTerminators == 2 ) { +if ( I -> getDesc ( ) . isUnconditionalBranch ( ) ) { +if ( std :: prev ( I ) -> getDesc ( ) . isConditionalBranch ( ) ) { +parseCondBranch ( * std :: prev ( I ) , TBB , Cond ) ; +FBB = getBranchDestBlock ( * I ) ; +return false ; +} +} +} +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/areMemAccessesTriviallyDisjoint.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/areMemAccessesTriviallyDisjoint.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b8ba306b6e3da46ee987e08c38605e80b48cab43 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/areMemAccessesTriviallyDisjoint.cpp @@ -0,0 +1,36 @@ +bool PULPInstrInfo :: areMemAccessesTriviallyDisjoint ( const MachineInstr & MIa , const MachineInstr & MIb ) const { +assert ( MIa . mayLoadOrStore ( ) && "MIa must be a load or store." ) ; +assert ( MIb . mayLoadOrStore ( ) && "MIb must be a load or store." ) ; +if ( MIa . hasUnmodeledSideEffects ( ) ) { +return false ; +} +if ( MIb . hasUnmodeledSideEffects ( ) ) { +return false ; +} +if ( MIa . hasOrderedMemoryRef ( ) ) { +return false ; +} +if ( MIb . hasOrderedMemoryRef ( ) ) { +return false ; +} +const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ; +const MachineOperand * BaseOpA = nullptr ; +const MachineOperand * BaseOpB = nullptr ; +int64_t OffsetA = 0 ; +int64_t OffsetB = 0 ; +unsigned WidthA = 0 ; +unsigned WidthB = 0 ; +if ( getMemOperandWithOffsetWidth ( MIa , BaseOpA , OffsetA , WidthA , TRI ) ) { +if ( getMemOperandWithOffsetWidth ( MIb , BaseOpB , OffsetB , WidthB , TRI ) ) { +if ( BaseOpA -> isIdenticalTo ( * BaseOpB ) ) { +int LowOffset = std :: min ( OffsetA , OffsetB ) ; +int HighOffset = std :: max ( OffsetA , OffsetB ) ; +int LowWidth = ( LowOffset == OffsetA ) ? WidthA : WidthB ; +if ( LowOffset + LowWidth <= HighOffset ) { +return true ; +} +} +} +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/buildOutlinedFrame.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/buildOutlinedFrame.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3b5946b00f2c714a9b67ed058b6b5d48abb0c313 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/buildOutlinedFrame.cpp @@ -0,0 +1,45 @@ +void PULPInstrInfo :: buildOutlinedFrame ( MachineBasicBlock & MBB , MachineFunction & MF , const outliner :: OutlinedFunction & OF ) const { +if ( OF . FrameConstructionID == MachineOutlinerThunk ) { +MachineInstr * Call = & * -- MBB . instr_end ( ) ; +bool isThumb = Subtarget . isThumb ( ) ; +unsigned FuncOp = isThumb ? 2 : 0 ; +unsigned Opc = Call -> getOperand ( FuncOp ) . isReg ( ) ? isThumb ? PULP :: tTAILJMPr : PULP :: TAILJMPr : isThumb ? Subtarget . isTargetMachO ( ) ? PULP :: tTAILJMPd : PULP :: tTAILJMPdND : PULP :: TAILJMPd ; +MachineInstrBuilder MIB = BuildMI ( MBB , MBB . end ( ) , DebugLoc ( ) , get ( Opc ) ) . add ( Call -> getOperand ( FuncOp ) ) ; +if ( isThumb ) { +if ( ! Call -> getOperand ( FuncOp ) . isReg ( ) ) { +MIB . add ( predOps ( PULPCC :: AL ) ) ; +} +} +Call -> eraseFromParent ( ) ; +} +if ( llvm :: any_of ( MBB . instrs ( ) , IsNonTailCall ) ) { +MachineBasicBlock :: iterator It = MBB . begin ( ) ; +MachineBasicBlock :: iterator Et = MBB . end ( ) ; +if ( OF . FrameConstructionID == MachineOutlinerTailCall ) { +Et = std :: prev ( MBB . end ( ) ) ; +} +if ( OF . FrameConstructionID == MachineOutlinerThunk ) { +Et = std :: prev ( MBB . end ( ) ) ; +} +if ( ! MBB . isLiveIn ( PULP :: LR ) ) { +MBB . addLiveIn ( PULP :: LR ) ; +} +saveLROnStack ( MBB , It ) ; +emitCFIForLRSaveOnStack ( MBB , It ) ; +fixupPostOutline ( MBB ) ; +restoreLRFromStack ( MBB , Et ) ; +emitCFIForLRRestoreFromStack ( MBB , Et ) ; +} +if ( OF . FrameConstructionID == MachineOutlinerTailCall ) { +return ; +} +return ; +if ( OF . FrameConstructionID != MachineOutlinerDefault ) { +if ( OF . Candidates [ 0 ] . CallConstructionID != MachineOutlinerDefault ) { +return ; +} +} +fixupPostOutline ( MBB ) ; +MachineInstr * retq = BuildMI ( MF , DebugLoc ( ) , get ( PULP :: RET64 ) ) ; +MBB . insert ( MBB . end ( ) , retq ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/copyPhysReg.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/copyPhysReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fb8dcde578c472b0d999acee2452f889fc2d55fb --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/copyPhysReg.cpp @@ -0,0 +1,31 @@ +void PULPInstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , MCRegister DstReg , MCRegister SrcReg , bool KillSrc ) const { +if ( PULP :: GPRRegClass . contains ( DstReg , SrcReg ) ) { +BuildMI ( MBB , MBBI , DL , get ( PULP::ADDI ) , DstReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addReg ( PULP :: R0 ) ; +return ; +} +if ( PULP :: FPR16RegClass . contains ( DestReg , SrcReg ) ) { +BuildMI ( MBB , MBBI , DL , get ( PULP :: FSGNJ_H ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; +return ; +} +if ( PULP :: FPR32RegClass . contains ( DestReg , SrcReg ) ) { +BuildMI ( MBB , MBBI , DL , get ( PULP :: FSGNJ_S ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; +return ; +} +if ( PULP :: FPR64RegClass . contains ( DestReg , SrcReg ) ) { +BuildMI ( MBB , MBBI , DL , get ( PULP :: FSGNJ_D ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; +return ; +} +if ( PULP :: VRRegClass . contains ( DestReg , SrcReg ) ) { +BuildMI ( MBB , MBBI , DL , get ( PULP :: PseudoVMV1R_V ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; +return ; +} +if ( PULP :: VRM2RegClass . contains ( DestReg , SrcReg ) ) { +BuildMI ( MBB , MBBI , DL , get ( PULP :: PseudoVMV2R_V ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; +return ; +} +if ( PULP :: VRM4RegClass . contains ( DestReg , SrcReg ) ) { +BuildMI ( MBB , MBBI , DL , get ( PULP :: PseudoVMV4R_V ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; +return ; +} +llvm_unreachable ( "Impossible reg-to-reg copy" ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/decomposeMachineOperandsTargetFlags.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/decomposeMachineOperandsTargetFlags.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b7f010a1c2821bfe4cbf61900dfc038220ae3a1e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/decomposeMachineOperandsTargetFlags.cpp @@ -0,0 +1,4 @@ +std :: pair < unsigned , unsigned > PULPInstrInfo :: decomposeMachineOperandsTargetFlags ( unsigned TF ) const { +const unsigned Mask = PULPII :: MO_DIRECT_FLAG_MASK ; +return std :: make_pair ( TF & Mask , TF & ~ Mask ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/getBranchDestBlock.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/getBranchDestBlock.cpp new file mode 100644 index 0000000000000000000000000000000000000000..483736fe80b4a40e10947e10787dd0186c751934 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/getBranchDestBlock.cpp @@ -0,0 +1,4 @@ +MachineBasicBlock * PULPInstrInfo :: getBranchDestBlock ( const MachineInstr & MI ) const { +assert ( MI . getDesc ( ) . isBranch ( ) && "Unexpected opcode!" ) ; +return MI . getOperand ( MI . getNumExplicitOperands ( ) - 1 ) . getMBB ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/getInstSizeInBytes.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/getInstSizeInBytes.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f7c36448cfe3d869b9a34e69241814fafba04edd --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/getInstSizeInBytes.cpp @@ -0,0 +1,35 @@ +unsigned PULPInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { +const MachineBasicBlock & MBB = * MI . getParent ( ) ; +const MachineFunction * MF = MBB . getParent ( ) ; +const MCAsmInfo * MAI = MF -> getTarget ( ) . getMCAsmInfo ( ) ; +unsigned Opcode = MI . getOpcode ( ) ; +if ( Opcode == TargetOpcode :: INLINEASM ) { +const MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ; +const char * AsmStr = MI -> getOperand ( 0 ) . getSymbolName ( ) ; +return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ; +return 0 ; +} +return MI -> getDesc ( ) . getSize ( ) ; +if ( Opcode == TargetOpcode :: EH_LABEL ) { +return 0 ; +} +if ( Opcode == TargetOpcode :: IMPLICIT_DEF ) { +return 0 ; +} +if ( Opcode == TargetOpcode :: KILL ) { +return 0 ; +} +if ( Opcode == PULP :: PseudoCALLReg ) { +return 16 ; +} +if ( Opcode == TargetOpcode :: INLINEASM_BR ) { +return 12 ; +} +if ( Opcode == PULP :: PseudoCALL ) { +return 12 ; +} +if ( Opcode == PULP :: PseudoJump ) { +return 12 ; +} +return MI . getDesc ( ) . getSize ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/getMemOperandWithOffsetWidth.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/getMemOperandWithOffsetWidth.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f9c17d094866fac11bff3fac016b1c5ca47c919a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/getMemOperandWithOffsetWidth.cpp @@ -0,0 +1,21 @@ +bool PULPInstrInfo :: getMemOperandWithOffsetWidth ( const MachineInstr & LdSt , const MachineOperand * & BaseReg , int64_t & Offset , unsigned & Width , const TargetRegisterInfo * TRI ) const { +if ( ! LdSt . mayLoadOrStore ( ) ) { +return false ; +} +if ( LdSt . getNumExplicitOperands ( ) != 3 ) { +return false ; +} +if ( ! LdSt . getOperand ( 2 ) . isImm ( ) ) { +return false ; +} +if ( ! LdSt . getOperand ( 1 ) . isReg ( ) ) { +return false ; +} +if ( ! LdSt . hasOneMemOperand ( ) ) { +return false ; +} +Width = ( * LdSt . memoperands_begin ( ) ) -> getSize ( ) ; +Offset = LdSt . getOperand ( 2 ) . getImm ( ) ; +BaseReg = & LdSt . getOperand ( 1 ) ; +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/getOutliningCandidateInfo.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/getOutliningCandidateInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b719f3cdc68c920b65b874f8e1be9b67b5931365 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/getOutliningCandidateInfo.cpp @@ -0,0 +1,23 @@ +outliner :: OutlinedFunction PULPInstrInfo :: getOutliningCandidateInfo ( std :: vector < outliner :: Candidate > & RepeatedSequenceLocs ) const { +unsigned CFICount = 0 ; +MachineBasicBlock :: iterator MBBI = RepeatedSequenceLocs [ 0 ] . front ( ) ; +for ( unsigned Loc = RepeatedSequenceLocs [ 0 ] . getStartIdx ( ) ; Loc < RepeatedSequenceLocs [ 0 ] . getEndIdx ( ) + 1 ; Loc ++ ) { +if ( MBBI -> isCFIInstruction ( ) ) { +MBBI = MBBI + 1 ; +for ( outliner :: Candidate & C : RepeatedSequenceLocs ) { +std :: vector < MCCFIInstruction > CFIInstructions = C . getMF ( ) -> getFrameInstructions ( ) ; +if ( CFICount > 0 ) { +if ( CFICount != CFIInstructions . size ( ) ) { +return outliner :: OutlinedFunction ( ) ; +if ( RepeatedSequenceLocs [ 0 ] . back ( ) -> isTerminator ( ) ) { +for ( outliner :: Candidate & C : RepeatedSequenceLocs ) { +C . setCallInfo ( MachineOutlinerTailCall , 1 ) ; +} +return outliner :: OutlinedFunction ( RepeatedSequenceLocs , SequenceSize , 0 , MachineOutlinerTailCall ) ; +if ( CFICount > 0 ) { +return outliner :: OutlinedFunction ( ) ; +for ( outliner :: Candidate & C : RepeatedSequenceLocs ) { +C . setCallInfo ( MachineOutlinerDefault , 1 ) ; +} +return outliner :: OutlinedFunction ( RepeatedSequenceLocs , SequenceSize , 1 , MachineOutlinerDefault ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/getOutliningType.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/getOutliningType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0588a546f60f5c64de1a1941b94b5d1589a182d0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/getOutliningType.cpp @@ -0,0 +1,68 @@ +outliner :: InstrType PULPInstrInfo :: getOutliningType ( MachineBasicBlock :: iterator & MBBI , unsigned Flags ) const { +achineInstr & MI = * MBBI ; +MachineBasicBlock * MBB = MI . getParent ( ) ; +const TargetRegisterInfo * TRI = MBB -> getParent ( ) -> getSubtarget ( ) . getRegisterInfo ( ) ; +if ( MI . isDebugValue ( ) ) { +return MachineOutlinerInstrType :: Invisible ; +} +if ( MI . isIndirectDebugValue ( ) ) { +return MachineOutlinerInstrType :: Invisible ; +} +if ( isTailCall ( MI ) ) { +return MachineOutlinerInstrType :: Legal ; +} +if ( MI . isTerminator ( ) ) { +if ( MI . getParent ( ) -> succ_empty ( ) ) { +return MachineOutlinerInstrType :: Legal ; +} +return MachineOutlinerInstrType :: Illegal ; +} +if ( MI . isReturn ( ) ) { +if ( MI . getParent ( ) -> succ_empty ( ) ) { +return MachineOutlinerInstrType :: Legal ; +} +return MachineOutlinerInstrType :: Illegal ; +} +if ( MI . modifiesRegister ( OpcodeRSP , & RI ) ) { +return MachineOutlinerInstrType :: Illegal ; +} +if ( MI . readsRegister ( OpcodeRSP , & RI ) ) { +return MachineOutlinerInstrType :: Illegal ; +} +if ( MI . getDesc ( ) . hasImplicitUseOfPhysReg ( OpcodeRSP ) ) { +return MachineOutlinerInstrType :: Illegal ; +} +if ( MI . getDesc ( ) . hasImplicitDefOfPhysReg ( OpcodeRSP ) ) { +return MachineOutlinerInstrType :: Illegal ; +} +if ( MI . readsRegister ( OpcodeRIP , & RI ) ) { +return MachineOutlinerInstrType :: Illegal ; +} +if ( MI . getDesc ( ) . hasImplicitUseOfPhysReg ( OpcodeRIP ) ) { +return MachineOutlinerInstrType :: Illegal ; +} +if ( MI . getDesc ( ) . hasImplicitDefOfPhysReg ( OpcodeRIP ) ) { +return MachineOutlinerInstrType :: Illegal ; +} +if ( MI . isPosition ( ) ) { +return MachineOutlinerInstrType :: Illegal ; +} +for ( const MachineOperand & MOP : MI . operands ( ) ) { +if ( MOP . isCPI ( ) ) { +return MachineOutlinerInstrType :: Illegal ; +} +if ( MOP . isJTI ( ) ) { +return MachineOutlinerInstrType :: Illegal ; +} +if ( MOP . isCFIIndex ( ) ) { +return MachineOutlinerInstrType :: Illegal ; +} +if ( MOP . isFI ( ) ) { +return MachineOutlinerInstrType :: Illegal ; +} +if ( MOP . isTargetIndex ( ) ) { +return MachineOutlinerInstrType :: Illegal ; +} +} +return MachineOutlinerInstrType :: Legal ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/getSerializableDirectMachineOperandTargetFlags.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/getSerializableDirectMachineOperandTargetFlags.cpp new file mode 100644 index 0000000000000000000000000000000000000000..052a970ba05e5c03368e753f04fee87f04a62f92 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/getSerializableDirectMachineOperandTargetFlags.cpp @@ -0,0 +1,5 @@ +ArrayRef < std :: pair < unsigned , const char * >> PULPInstrInfo :: getSerializableDirectMachineOperandTargetFlags ( ) const { +using namespace PULPII ; +static const std :: pair < unsigned , const char * > TargetFlags [ ] = { { MO_CALL , "riscv-call" } , { MO_PLT , "riscv-call" } , { MO_LP , "riscv-plt" } , { MO_LO , "riscv-lo" } , { MO_HI , "riscv-hi" } , { MO_PCREL_LO , "riscv-pcrel-lo" } , { MO_PCREL_HI , "riscv-pcrel-hi" } , { MO_GOT_HI , "riscv-got-hi" } , { MO_TPREL_LO , "riscv-tls-got-hi" } , { MO_TLS_GD_HI , "riscv-tls-gd-hi" } , { MO_TLS_GD_HI , "riscv-tls-gd-hi" } , { MO_TPREL_ADD , "riscv-tprel-add" } , { MO_TLS_GOT_HI , "riscv-tls-got-hi" } , { MO +return makeArrayRef ( TargetFlags ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/insertBranch.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/insertBranch.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0abe51d787ba696ecc1a89f98927804e3159e6ff --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/insertBranch.cpp @@ -0,0 +1,27 @@ +unsigned PULPInstrInfo :: insertBranch ( MachineBasicBlock & MBB , MachineBasicBlock * TBB , MachineBasicBlock * FBB , ArrayRef < MachineOperand > Cond , const DebugLoc & DL , int * BytesAdded ) const { +if ( BytesAdded ) { +* BytesAdded = 0 ; +} +assert ( TBB && "insertBranch must not be told to insert a fallthrough" ) ; +assert ( ( Cond . size ( ) == 3 || Cond . size ( ) == 0 ) && "PULP branch conditions have two components!" ) ; +if ( Cond . empty ( ) ) { +MachineInstr & MI = * BuildMI ( & MBB , DL , get ( PULP :: PseudoBR ) ) . addMBB ( TBB ) ; +if ( BytesAdded ) { +* BytesAdded = * BytesAdded + getInstSizeInBytes ( MI ) ; +} +return 1 ; +} +unsigned Opc = Cond [ 0 ] . getImm ( ) ; +MachineInstr & CondMI = * BuildMI ( & MBB , DL , get ( Opc ) ) . add ( Cond [ 1 ] ) . add ( Cond [ 2 ] ) . addMBB ( TBB ) ; +if ( BytesAdded ) { +* BytesAdded = * BytesAdded + getInstSizeInBytes ( CondMI ) ; +} +if ( ! FBB ) { +return 1 ; +} +MachineInstr & MI = * BuildMI ( & MBB , DL , get ( PULP :: PseudoBR ) ) . addMBB ( FBB ) ; +if ( BytesAdded ) { +* BytesAdded = * BytesAdded + getInstSizeInBytes ( MI ) ; +} +return 2 ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/insertIndirectBranch.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/insertIndirectBranch.cpp new file mode 100644 index 0000000000000000000000000000000000000000..73b132845630aadeefc8108adf01f98c2018390e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/insertIndirectBranch.cpp @@ -0,0 +1,23 @@ +unsigned PULPInstrInfo :: insertIndirectBranch ( MachineBasicBlock & MBB , MachineBasicBlock & DestBB , const DebugLoc & DL , int64_t BrOffset , RegScavenger * RS ) const { +assert ( RS && "RegScavenger required for long branching" ) ; +assert ( MBB . empty ( ) && "new block should be inserted for expanding unconditional branch" ) ; +assert ( MBB . pred_size ( ) == 1 ) ; +MachineFunction * MF = MBB . getParent ( ) ; +MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; +unsigned PCReg = MRI . createVirtualRegister ( & PULP :: SReg_64RegClass ) ; +Register ScratchReg = MRI . createVirtualRegister ( & PULP :: GPRRCRegClass ) ; +auto I = MBB . end ( ) ; +MachineInstr * GetPC = BuildMI ( MBB , I , DL , get ( PULP :: S_GETPC_B64 ) , PCReg ) ; +if ( BrOffset >= 0 ) { +BuildMI ( MBB , I , DL , get ( PULP :: PseudoJump ) ) . addReg ( PCReg , RegState :: Define , PULP :: sub0 ) . addReg ( PCReg , 0 , PULP :: sub0 ) . addMBB ( & DestBB , PULP :: TF_LONG_BRANCH_BACKWARD ) ; +MachineInstr * MI = BuildMI ( MBB , I , DL , get ( PULP :: JMP ) ) . addReg ( ScratchReg ) ; +RS -> enterBasicBlockEnd ( MBB ) ; +unsigned Scav = RS -> scavengeRegisterBackwards ( PULP :: SReg_64RegClass , MachineBasicBlock :: iterator ( GetPC ) , false , 0 ) ; +MRI . replaceRegWith ( PCReg , Scav ) ; +unsigned Scav = RS -> scavengeRegisterBackwards ( PULP :: GPRRCRegClass , MI -> getIterator ( ) , false , 0 ) ; +assert ( Scav != PULP :: NoRegister && "No register is scavenged!" ) ; +MRI . replaceRegWith ( ScratchReg , Scav ) ; +MRI . clearVirtRegs ( ) ; +RS -> setRegUsed ( Scav ) ; +return 20 ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/insertOutlinedCall.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/insertOutlinedCall.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2777cf70047940f4453af06844d4af50c5226f7f --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/insertOutlinedCall.cpp @@ -0,0 +1,6 @@ +MachineBasicBlock :: iterator PULPInstrInfo :: insertOutlinedCall ( Module & M , MachineBasicBlock & MBB , MachineBasicBlock :: iterator & It , MachineFunction & MF , outliner :: Candidate & C ) const { +It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( PULP :: JMP_1 ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; +return It ; +It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( PULP :: CALL64pcrel32 ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; +return It ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/isAsCheapAsAMove.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/isAsCheapAsAMove.cpp new file mode 100644 index 0000000000000000000000000000000000000000..197a59efee091ba41afa2ec9e99be5707984bf1f --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/isAsCheapAsAMove.cpp @@ -0,0 +1,19 @@ +bool PULPInstrInfo :: isAsCheapAsAMove ( const MachineInstr & MI ) const { +const unsigned Opcode = MI . getOpcode ( ) ; +if ( Opcode == PULP :: FSGNJ_D ) { +return ( MI . getOperand ( 1 ) . isReg ( ) && MI . getOperand ( 1 ) . getReg ( ) == PULP :: ZERO ) ; +} +if ( Opcode == PULP :: FSGNJ_S ) { +return ( MI . getOperand ( 1 ) . isReg ( ) && MI . getOperand ( 1 ) . getReg ( ) == PULP :: ZERO ) ; +} +if ( Opcode == PULP :: ADDI ) { +return ( MI . getOperand ( 1 ) . isReg ( ) && MI . getOperand ( 1 ) . getReg ( ) == PULP :: ZERO ) ; +} +if ( Opcode == PULP :: ORI ) { +return ( MI . getOperand ( 1 ) . isReg ( ) && MI . getOperand ( 1 ) . getReg ( ) == PULP :: ZERO ) ; +} +if ( Opcode == PULP :: XORI ) { +return ( MI . getOperand ( 1 ) . isReg ( ) && MI . getOperand ( 1 ) . getReg ( ) == PULP :: ZERO ) ; +} +return MI . isAsCheapAsAMove ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/isBranchOffsetInRange.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/isBranchOffsetInRange.cpp new file mode 100644 index 0000000000000000000000000000000000000000..11a57adf5987e09748865732f8d9ea1a8c687ab1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/isBranchOffsetInRange.cpp @@ -0,0 +1,36 @@ +bool PULPInstrInfo :: isBranchOffsetInRange ( unsigned BranchOpc , int64_t BrOffset ) const { +if ( BranchOpc == PULP :: BEQ ) { +return isIntN ( 13 , BrOffset ) ; +} +if ( BranchOpc == PULP :: BNE ) { +return isIntN ( 13 , BrOffset ) ; +} +if ( BranchOpc == PULP :: BLT ) { +return isIntN ( 13 , BrOffset ) ; +} +if ( BranchOpc == PULP :: BGE ) { +return isIntN ( 13 , BrOffset ) ; +} +if ( BranchOpc == PULP :: BLTU ) { +return isIntN ( 13 , BrOffset ) ; +} +if ( BranchOpc == PULP :: BGEU ) { +return isIntN ( 13 , BrOffset ) ; +} +if ( BranchOpc == PULP :: JAL ) { +return isIntN ( 21 , BrOffset ) ; +} +if ( BranchOpc == PULP :: PseudoBR ) { +return isIntN ( 21 , BrOffset ) ; +} +if ( BranchOpc == PULP :: PseudoJump ) { +return isIntN ( 32 , SignExtend64 ( BrOffset + 0x800 , STI . getZLen ( ) ) ) ; +} +if ( BranchOpc == PULP :: P_BEQIMM ) { +return isIntN ( 13 , BrOffset ) ; +} +if ( BranchOpc == PULP :: P_BNEIMM ) { +return isIntN ( 13 , BrOffset ) ; +} +llvm_unreachable ( "Unexpected opcode!" ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/isCopyInstrImpl.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/isCopyInstrImpl.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fc2ea802e7368fea65d3f735325e8ede614f194d --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/isCopyInstrImpl.cpp @@ -0,0 +1,25 @@ +Optional < DestSourcePair > PULPInstrInfo :: isCopyInstrImpl ( const MachineInstr & MI ) const { +if ( MI . isMoveReg ( ) ) { +return DestSourcePair { MI . getOperand ( 0 ) , MI . getOperand ( 1 ) } ; +} +if ( MI . getOpcode ( ) == PULP :: ADDI ) { +if ( MI . getOperand ( 2 ) . getImm ( ) == 0x0 ) { +return DestSourcePair { MI . getOperand ( 0 ) , MI . getOperand ( 1 ) } ; +} +} +if ( MI . getOpcode ( ) == PULP::FSGNJ_D ) { +if ( MI . getOperand ( 1 ) . getReg ( ) == PULP :: WZR ) { +if ( MI . getOperand ( 3 ) . getImm ( ) == 0x0 ) { +return DestSourcePair { MI . getOperand ( 0 ) , MI . getOperand ( 2 ) } ; +} +} +} +if ( MI . getOpcode ( ) == PULP::FSGNJ_S ) { +if ( MI . getOperand ( 1 ) . getReg ( ) == PULP :: XZR ) { +if ( MI . getOperand ( 3 ) . getImm ( ) == 0x0 ) { +return DestSourcePair { MI . getOperand ( 0 ) , MI . getOperand ( 2 ) } ; +} +} +} +return None ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/isFunctionSafeToOutlineFrom.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/isFunctionSafeToOutlineFrom.cpp new file mode 100644 index 0000000000000000000000000000000000000000..686fa2f918a2895d7d81909d5775e0e33981a05e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/isFunctionSafeToOutlineFrom.cpp @@ -0,0 +1,12 @@ +bool PULPInstrInfo :: isFunctionSafeToOutlineFrom ( MachineFunction & MF , bool OutlineFromLinkOnceODRs ) const { +const Function & F = MF . getFunction ( ) ; +if ( ! OutlineFromLinkOnceODRs ) { +if ( F . hasLinkOnceODRLinkage ( ) ) { +return false ; +} +} +if ( F . hasSection ( ) ) { +return false ; +} +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/isLoadFromStackSlot.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/isLoadFromStackSlot.cpp new file mode 100644 index 0000000000000000000000000000000000000000..efa61131d11a5807427c43c99cde07fea28c35b7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/isLoadFromStackSlot.cpp @@ -0,0 +1,103 @@ +unsigned PULPInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { +if ( MI . getOpcode ( ) == PULP::LB ) { +if ( MI . getOperand ( 1 ) . isFI ( ) ) { +if ( MI . getOperand ( 2 ) . isImm ( ) ) { +if ( MI . getOperand ( 2 ) . getImm ( ) == 0 ) { +FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; +return MI . getOperand ( 0 ) . getReg ( ) ; +} +} +} +} +if ( MI . getOpcode ( ) == PULP :: LBU ) { +if ( MI . getOperand ( 1 ) . isFI ( ) ) { +if ( MI . getOperand ( 2 ) . isImm ( ) ) { +if ( MI . getOperand ( 2 ) . getImm ( ) == 0 ) { +FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; +return MI . getOperand ( 0 ) . getReg ( ) ; +} +} +} +} +if ( MI . getOpcode ( ) == PULP :: LH ) { +if ( MI . getOperand ( 1 ) . isFI ( ) ) { +if ( MI . getOperand ( 2 ) . isImm ( ) ) { +if ( MI . getOperand ( 2 ) . getImm ( ) == 0 ) { +FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; +return MI . getOperand ( 0 ) . getReg ( ) ; +} +} +} +} +if ( MI . getOpcode ( ) == PULP :: LHU ) { +if ( MI . getOperand ( 1 ) . isFI ( ) ) { +if ( MI . getOperand ( 2 ) . isImm ( ) ) { +if ( MI . getOperand ( 2 ) . getImm ( ) == 0 ) { +FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; +return MI . getOperand ( 0 ) . getReg ( ) ; +} +} +} +} +if ( MI . getOpcode ( ) == PULP::FLH ) { +if ( MI . getOperand ( 1 ) . isFI ( ) ) { +if ( MI . getOperand ( 2 ) . isImm ( ) ) { +if ( MI . getOperand ( 2 ) . getImm ( ) == 0 ) { +FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; +return MI . getOperand ( 0 ) . getReg ( ) ; +} +} +} +} +if ( MI . getOpcode ( ) == PULP :: LW ) { +if ( MI . getOperand ( 1 ) . isFI ( ) ) { +if ( MI . getOperand ( 2 ) . isImm ( ) ) { +if ( MI . getOperand ( 2 ) . getImm ( ) == 0 ) { +FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; +return MI . getOperand ( 0 ) . getReg ( ) ; +} +} +} +} +if ( MI . getOpcode ( ) == PULP::FLW ) { +if ( MI . getOperand ( 1 ) . isFI ( ) ) { +if ( MI . getOperand ( 2 ) . isImm ( ) ) { +if ( MI . getOperand ( 2 ) . getImm ( ) == 0 ) { +FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; +return MI . getOperand ( 0 ) . getReg ( ) ; +} +} +} +} +if ( MI . getOpcode ( ) == PULP :: LWU ) { +if ( MI . getOperand ( 1 ) . isFI ( ) ) { +if ( MI . getOperand ( 2 ) . isImm ( ) ) { +if ( MI . getOperand ( 2 ) . getImm ( ) == 0 ) { +FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; +return MI . getOperand ( 0 ) . getReg ( ) ; +} +} +} +} +if ( MI . getOpcode ( ) == PULP :: LD ) { +if ( MI . getOperand ( 1 ) . isFI ( ) ) { +if ( MI . getOperand ( 2 ) . isImm ( ) ) { +if ( MI . getOperand ( 2 ) . getImm ( ) == 0 ) { +FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; +return MI . getOperand ( 0 ) . getReg ( ) ; +} +} +} +} +if ( MI . getOpcode ( ) == PULP :: FLD ) { +if ( MI . getOperand ( 1 ) . isFI ( ) ) { +if ( MI . getOperand ( 2 ) . isImm ( ) ) { +if ( MI . getOperand ( 2 ) . getImm ( ) == 0 ) { +FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; +return MI . getOperand ( 0 ) . getReg ( ) ; +} +} +} +} +return 0 ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/isMBBSafeToOutlineFrom.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/isMBBSafeToOutlineFrom.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4e9ae1632ecb6a54096e6399148d56ae67b2e0e7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/isMBBSafeToOutlineFrom.cpp @@ -0,0 +1,3 @@ +bool PULPInstrInfo :: isMBBSafeToOutlineFrom ( MachineBasicBlock & MBB , unsigned & Flags ) const { +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/isSchedulingBoundary.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/isSchedulingBoundary.cpp new file mode 100644 index 0000000000000000000000000000000000000000..571d654b8f2d2c84c557e259318414054b78b0e7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/isSchedulingBoundary.cpp @@ -0,0 +1,18 @@ +bool PULPInstrInfo :: isSchedulingBoundary ( const MachineInstr & MI , const MachineBasicBlock * MBB , const MachineFunction & MF ) const { +if ( TargetInstrInfo :: isSchedulingBoundary ( MI , MBB , MF ) ) { +return true ; +} +if ( MI . getOpcode ( ) == PULP :: LOOP0setup ) { +return true ; +} +if ( MI . getOpcode ( ) == PULP :: LOOP1setup ) { +return true ; +} +if ( MI . getOpcode ( ) == PULP :: LOOP0setupi ) { +return true ; +} +if ( MI . getOpcode ( ) == PULP::LOOP1setupi ) { +return true ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/isStoreToStackSlot.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/isStoreToStackSlot.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1e344ba60d0acde779215174046e226983181aaa --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/isStoreToStackSlot.cpp @@ -0,0 +1,73 @@ +unsigned PULPInstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { +if ( MI . getOpcode ( ) == PULP :: SB ) { +if ( MI . getOperand ( 1 ) . isFI ( ) ) { +if ( MI . getOperand ( 2 ) . isImm ( ) ) { +if ( MI . getOperand ( 2 ) . getImm ( ) == 0 ) { +FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; +return MI . getOperand ( 0 ) . getReg ( ) ; +} +} +} +} +if ( MI . getOpcode ( ) == PULP :: SH ) { +if ( MI . getOperand ( 1 ) . isFI ( ) ) { +if ( MI . getOperand ( 2 ) . isImm ( ) ) { +if ( MI . getOperand ( 2 ) . getImm ( ) == 0 ) { +FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; +return MI . getOperand ( 0 ) . getReg ( ) ; +} +} +} +} +if ( MI . getOpcode ( ) == PULP :: SW ) { +if ( MI . getOperand ( 1 ) . isFI ( ) ) { +if ( MI . getOperand ( 2 ) . isImm ( ) ) { +if ( MI . getOperand ( 2 ) . getImm ( ) == 0 ) { +FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; +return MI . getOperand ( 0 ) . getReg ( ) ; +} +} +} +} +if ( MI . getOpcode ( ) == PULP :: FSH ) { +if ( MI . getOperand ( 1 ) . isFI ( ) ) { +if ( MI . getOperand ( 2 ) . isImm ( ) ) { +if ( MI . getOperand ( 2 ) . getImm ( ) == 0 ) { +FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; +return MI . getOperand ( 0 ) . getReg ( ) ; +} +} +} +} +if ( MI . getOpcode ( ) == PULP :: FSW ) { +if ( MI . getOperand ( 1 ) . isFI ( ) ) { +if ( MI . getOperand ( 2 ) . isImm ( ) ) { +if ( MI . getOperand ( 2 ) . getImm ( ) == 0 ) { +FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; +return MI . getOperand ( 0 ) . getReg ( ) ; +} +} +} +} +if ( MI . getOpcode ( ) == PULP :: SD ) { +if ( MI . getOperand ( 1 ) . isFI ( ) ) { +if ( MI . getOperand ( 2 ) . isImm ( ) ) { +if ( MI . getOperand ( 2 ) . getImm ( ) == 0 ) { +FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; +return MI . getOperand ( 0 ) . getReg ( ) ; +} +} +} +} +if ( MI . getOpcode ( ) == PULP :: FSD ) { +if ( MI . getOperand ( 1 ) . isFI ( ) ) { +if ( MI . getOperand ( 2 ) . isImm ( ) ) { +if ( MI . getOperand ( 2 ) . getImm ( ) == 0 ) { +FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; +return MI . getOperand ( 0 ) . getReg ( ) ; +} +} +} +} +return 0 ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/loadRegFromStackSlot.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/loadRegFromStackSlot.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cb2cda5148c586ed3a8c8a2513b71a5bfa5b8622 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/loadRegFromStackSlot.cpp @@ -0,0 +1,31 @@ +void PULPInstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , Register DstReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { +DebugLoc DL ; +if ( I != MBB . end ( ) ) { +DL = I -> getDebugLoc ( ) ; +} +MachineFunction * MF = MBB . getParent ( ) ; +const MachineFrameInfo & MFI = MF -> getFrameInfo ( ) ; +MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlign ( FI ) ) ; +unsigned Opcode ; +if ( PULP :: GPRRegClass . hasSubClassEq ( RC ) ) { +Opcode = TRI -> getRegSizeInBits ( PULP :: GPRRegClass ) == 32 ? PULP :: LW : PULP :: LD ; +BuildMI ( MBB , I , DL , get ( Opcode ) , DstReg ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ; +return ; +} +if ( PULP :: FPR16RegClass . hasSubClassEq ( RC ) ) { +Opcode = PULP::FLH ; +BuildMI ( MBB , I , DL , get ( Opcode ) , DstReg ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ; +return ; +} +if ( PULP :: FPR32RegClass . hasSubClassEq ( RC ) ) { +Opcode = PULP::FLW ; +BuildMI ( MBB , I , DL , get ( Opcode ) , DstReg ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ; +return ; +} +if ( PULP :: FPR64RegClass . hasSubClassEq ( RC ) ) { +Opcode = PULP :: FLD ; +BuildMI ( MBB , I , DL , get ( Opcode ) , DstReg ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ; +return ; +} +llvm_unreachable ( "Can't load this register from stack slot" ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/movImm.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/movImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..48ba98010ec588b8ea4aa16f5ba545eed86dd48c --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/movImm.cpp @@ -0,0 +1,21 @@ +void PULPInstrInfo :: movImm ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , Register DstReg , uint64_t Val , MachineInstr :: MIFlag Flag ) const { +assert ( ( Seq . size ( ) > 0 ) ? "movImm" : "movImm" ) ) ; +MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; +DstReg = MRI . createVirtualRegister ( & PULP :: GPRRegClass ) ; +BuildMI ( MBB , MBBI , DL , get ( PULP :: MOVI32 ) , DstReg ) . addImm ( Val & 0xFFFF ) . setMIFlags ( Flag ) ; +BuildMI ( MBB , MBBI , DL , get ( PULP :: MOVIH32 ) , DstReg ) . addImm ( ( Val >> 16 ) & 0xFFFF ) . setMIFlags ( Flag ) ; +if ( ! STI . hasE2 ( ) ) { +DstReg = MRI . createVirtualRegister ( & PULP :: mGPRRegClass ) ; +BuildMI ( MBB , MBBI , DL , get ( PULP :: MOVI16 ) , DstReg ) . addImm ( Val & 0xFF ) . setMIFlags ( Flag ) ; +return DstReg ; +BuildMI ( MBB , MBBI , DL , get ( PULP :: MOVI16 ) , DstReg ) . addImm ( ( Val >> 8 ) & 0xFF ) . setMIFlags ( Flag ) ; +if ( ( Val & 0xFF ) != 0 ) { +return DstReg ; +BuildMI ( MBB , MBBI , DL , get ( PULP :: MOVI16 ) , DstReg ) . addImm ( ( Val >> 16 ) & 0xFF ) . setMIFlags ( Flag ) ; +if ( ( Val & 0xFF ) != 0 ) { +return DstReg ; +BuildMI ( MBB , MBBI , DL , get ( PULP :: MOVI16 ) , DstReg ) . addImm ( ( Val >> 24 ) & 0xFF ) . setMIFlags ( Flag ) ; +if ( ( Val & 0xFF ) != 0 ) { +return DstReg ; +return DstReg ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/parseCondBranch.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/parseCondBranch.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ee61a6f99c524feca29f0c4363a86c730ce1069a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/parseCondBranch.cpp @@ -0,0 +1,7 @@ +static void parseCondBranch ( MachineInstr & LastInst , MachineBasicBlock * & Target , SmallVectorImpl < MachineOperand > & Cond ) { +assert ( LastInst . getDesc ( ) . isConditionalBranch ( ) && "Unknown conditional branch" ) ; +Target = LastInst . getOperand ( 2 ) . getMBB ( ) ; +Cond . push_back ( MachineOperand :: CreateImm ( LastInst . getOpcode ( ) ) ) ; +Cond . push_back ( LastInst . getOperand ( 0 ) ) ; +Cond . push_back ( LastInst . getOperand ( 1 ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/removeBranch.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/removeBranch.cpp new file mode 100644 index 0000000000000000000000000000000000000000..79327225bd7fc3cd1b8afa9434da684dbe6be343 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/removeBranch.cpp @@ -0,0 +1,31 @@ +unsigned PULPInstrInfo :: removeBranch ( MachineBasicBlock & MBB , int * BytesRemoved ) const { +if ( BytesRemoved ) { +* BytesRemoved = 0 ; +} +MachineBasicBlock :: iterator I = MBB . getLastNonDebugInstr ( ) ; +if ( I == MBB . end ( ) ) { +return 0 ; +} +if ( ! I -> getDesc ( ) . isUnconditionalBranch ( ) ) { +if ( ! I -> getDesc ( ) . isConditionalBranch ( ) ) { +return 0 ; +} +} +if ( BytesRemoved ) { +* BytesRemoved = * BytesRemoved + getInstSizeInBytes ( * I ) ; +} +I -> eraseFromParent ( ) ; +I = MBB . end ( ) ; +if ( I == MBB . begin ( ) ) { +return 1 ; +} +I -- ; +if ( ! I -> getDesc ( ) . isConditionalBranch ( ) ) { +return 1 ; +} +if ( BytesRemoved ) { +* BytesRemoved = * BytesRemoved + getInstSizeInBytes ( * I ) ; +} +I -> eraseFromParent ( ) ; +return 2 ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/reverseBranchCondition.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/reverseBranchCondition.cpp new file mode 100644 index 0000000000000000000000000000000000000000..535116b08f06b3f0ccc5cfa7ed4394cf24352d11 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/reverseBranchCondition.cpp @@ -0,0 +1,37 @@ +bool PULPInstrInfo :: reverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const { +assert ( ( Cond . size ( ) == 3 ) && "Invalid branch condition!" ) ; +if ( Cond [ 0 ] . getImm ( ) == PULP :: BEQ ) { +Cond [ 0 ] . setImm ( PULP :: BNE ) ; +return false ; +} +if ( Cond [ 0 ] . getImm ( ) == PULP :: BNE ) { +Cond [ 0 ] . setImm ( PULP :: BEQ ) ; +return false ; +} +if ( Cond [ 0 ] . getImm ( ) == PULP :: BLT ) { +Cond [ 0 ] . setImm ( PULP :: BGE ) ; +return false ; +} +if ( Cond [ 0 ] . getImm ( ) == PULP :: BGE ) { +Cond [ 0 ] . setImm ( PULP :: BLT ) ; +return false ; +} +if ( Cond [ 0 ] . getImm ( ) == PULP :: BLTU ) { +Cond [ 0 ] . setImm ( PULP :: BGEU ) ; +return false ; +} +if ( Cond [ 0 ] . getImm ( ) == PULP :: BGEU ) { +Cond [ 0 ] . setImm ( PULP :: BLTU ) ; +return false ; +} +if ( Cond [ 0 ] . getImm ( ) == PULP :: P_BEQIMM ) { +Cond [ 0 ] . setImm ( PULP :: P_BNEIMM ) ; +return false ; +} +if ( Cond [ 0 ] . getImm ( ) == PULP :: P_BNEIMM ) { +Cond [ 0 ] . setImm ( PULP :: P_BEQIMM ) ; +return false ; +} +llvm_unreachable ( "Unrecognized conditional branch" ) ; +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/storeRegToStackSlot.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/storeRegToStackSlot.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d24e0adda35dd6d872f141fb893726d0a9138f4e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/storeRegToStackSlot.cpp @@ -0,0 +1,32 @@ +void PULPInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , Register SrcReg , bool IsKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { +DebugLoc DL ; +if ( I != MBB . end ( ) ) { +DL = I -> getDebugLoc ( ) ; +} +MachineFunction & MF = * MBB . getParent ( ) ; +const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; +MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , MFI . getObjectAlign ( FI ) ) ; +MachineFunctionInfo * CFI = MF . getInfo < MachineFunctionInfo > ( ) ; +unsigned Opcode ; +if ( PULP :: GPRRegClass . hasSubClassEq ( RC ) ) { +Opcode = TRI -> getRegSizeInBits ( PULP :: GPRRegClass ) == 32 ? PULP :: SW : PULP :: SD ; +BuildMI ( MBB , I , DL , get ( Opcode ) ) . addReg ( SrcReg , getKillRegState ( IsKill ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ; +return ; +} +if ( PULP :: FPR16RegClass . hasSubClassEq ( RC ) ) { +Opcode = PULP :: FSH ; +BuildMI ( MBB , I , DL , get ( Opcode ) ) . addReg ( SrcReg , getKillRegState ( IsKill ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ; +return ; +} +if ( PULP :: FPR32RegClass . hasSubClassEq ( RC ) ) { +Opcode = PULP :: FSW ; +BuildMI ( MBB , I , DL , get ( Opcode ) ) . addReg ( SrcReg , getKillRegState ( IsKill ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ; +return ; +} +if ( PULP :: FPR64RegClass . hasSubClassEq ( RC ) ) { +Opcode = PULP :: FSD ; +BuildMI ( MBB , I , DL , get ( Opcode ) ) . addReg ( SrcReg , getKillRegState ( IsKill ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ; +return ; +} +llvm_unreachable ( "Can't store this register to stack slot" ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/verifyInstruction.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/verifyInstruction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fcc10dbebee6a317646b16a7267e491c9f33c58c --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/InstrInfo/verifyInstruction.cpp @@ -0,0 +1,26 @@ +bool zmntarzmInstrInfo :: verifyInstruction ( const MachineInstr & MI , StringRef & ErrInfo ) const { +return false ; +return false ; +for ( const MachineOperand & MO : llvm :: drop_begin ( MI . operands ( ) , 2 ) ) { +continue ; +if ( ! MO . isReg ( ) ) { +continue ; +return false ; +return false ; +} +for ( const MachineOperand & MO : llvm :: drop_begin ( MI . operands ( ) , 2 ) ) { +continue ; +if ( ! MO . isReg ( ) ) { +continue ; +return false ; +return false ; +for ( const MachineOperand & MO : llvm :: drop_begin ( MI . operands ( ) , 2 ) ) { +continue ; +if ( ! MO . isReg ( ) ) { +continue ; +return false ; +return false ; +ErrInfo = "Incorrect array index for MVE_VMOV_q_rr" ; +return false ; +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/MachineFunctionInfo/MachineFunctionInfo.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/MachineFunctionInfo/MachineFunctionInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..dec350caa0d7e69e8fca201c97e14571afe45b39 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/MachineFunctionInfo/MachineFunctionInfo.cpp @@ -0,0 +1,2 @@ +PULPMachineFunctionInfo ( const MachineFunction & MF ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/MachineFunctionInfo/getLibCallStackSize.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/MachineFunctionInfo/getLibCallStackSize.cpp new file mode 100644 index 0000000000000000000000000000000000000000..dd76ab5ba3323d65a4477bccc65534dc7962a22e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/MachineFunctionInfo/getLibCallStackSize.cpp @@ -0,0 +1,3 @@ +unsigned getLibCallStackSize ( ) const { +return LibCallStackSize ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/MachineFunctionInfo/getMoveF64FrameIndex.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/MachineFunctionInfo/getMoveF64FrameIndex.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1506385c39ba129264d05e3aeef80f525f072626 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/MachineFunctionInfo/getMoveF64FrameIndex.cpp @@ -0,0 +1,3 @@ +int getMoveF64FrameIndex ( MachineFunction & MF ) { +return VarArgsFrameIndex ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/MachineFunctionInfo/getUsedSSR.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/MachineFunctionInfo/getUsedSSR.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cf3059c9836b6dd477ebf27a54167e1208d90ffc --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/MachineFunctionInfo/getUsedSSR.cpp @@ -0,0 +1,3 @@ +unsigned getUsedSSR ( ) const { +return UsedSSR ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/MachineFunctionInfo/getVarArgsFrameIndex.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/MachineFunctionInfo/getVarArgsFrameIndex.cpp new file mode 100644 index 0000000000000000000000000000000000000000..dc86317bf4ffdb2157afe0cc9f496c3f8454b58d --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/MachineFunctionInfo/getVarArgsFrameIndex.cpp @@ -0,0 +1,3 @@ +int getVarArgsFrameIndex ( ) const { +return VarArgsFrameIndex ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/MachineFunctionInfo/getVarArgsSaveSize.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/MachineFunctionInfo/getVarArgsSaveSize.cpp new file mode 100644 index 0000000000000000000000000000000000000000..984c1825c54e81864add7c3ce18abcc8f75abfb1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/MachineFunctionInfo/getVarArgsSaveSize.cpp @@ -0,0 +1,3 @@ +unsigned getVarArgsSaveSize ( ) const { +return VarArgsSaveSize ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/MachineFunctionInfo/setLibCallStackSize.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/MachineFunctionInfo/setLibCallStackSize.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5abdcaac1a49937450075b01349b77aad5cba33e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/MachineFunctionInfo/setLibCallStackSize.cpp @@ -0,0 +1,3 @@ +void setLibCallStackSize ( unsigned Size ) { +LibCallStackSize = Size ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/MachineFunctionInfo/setUsedSSR.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/MachineFunctionInfo/setUsedSSR.cpp new file mode 100644 index 0000000000000000000000000000000000000000..120e16da41cbeb7ef433d94aac262b11322e235d --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/MachineFunctionInfo/setUsedSSR.cpp @@ -0,0 +1,3 @@ +void setUsedSSR ( unsigned SSR ) { +UsedSSR = SSR ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/MachineFunctionInfo/setVarArgsFrameIndex.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/MachineFunctionInfo/setVarArgsFrameIndex.cpp new file mode 100644 index 0000000000000000000000000000000000000000..66ec61362627179d015c191feff7e83b189ae468 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/MachineFunctionInfo/setVarArgsFrameIndex.cpp @@ -0,0 +1,3 @@ +void setVarArgsFrameIndex ( int Index ) { +VarArgsFrameIndex = Index ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/MachineFunctionInfo/setVarArgsSaveSize.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/MachineFunctionInfo/setVarArgsSaveSize.cpp new file mode 100644 index 0000000000000000000000000000000000000000..65028936eed662052285bdc438536ed2db9e126d --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/MachineFunctionInfo/setVarArgsSaveSize.cpp @@ -0,0 +1,3 @@ +void setVarArgsSaveSize ( int Size ) { +VarArgsSaveSize = Size ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/MachineFunctionInfo/useSaveRestoreLibCalls.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/MachineFunctionInfo/useSaveRestoreLibCalls.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7bf2af87f47f7fccd53a9869143ed96dbc2a7d2b --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/MachineFunctionInfo/useSaveRestoreLibCalls.cpp @@ -0,0 +1,4 @@ +bool useSaveRestoreLibCalls ( const MachineFunction & MF ) const { +return UseLongCalls ; +return UseRetpolineIndirectCalls ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/Subtarget.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/Subtarget.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a5d2323fed8e6241a94d307b24fc139b97a0fc51 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/Subtarget.cpp @@ -0,0 +1,7 @@ +PULPSubtarget :: PULPSubtarget ( const Triple & TT , StringRef CPU , StringRef TuneCPU , StringRef FS , StringRef ABIName , const TargetMachine & TM ) : PULPGenSubtargetInfo ( TT , CPU , TuneCPU , FS ) , UserReservedRegister ( PULP :: NUM_TARGET_REGS ) , FrameLowering ( initializeSubtargetDependencies ( TT , CPU , TuneCPU , FS , ABIName ) ) , InstrInfo ( * this ) , RegInfo ( getHwMode ( ) ) , TLInfo ( TM , * this ) { +CallLoweringInfo . reset ( new PULPCallLowering ( * getTargetLowering ( ) ) ) ; +Legalizer . reset ( new PULPLegalizerInfo ( * this ) ) ; +auto * RBI = new PULPRegisterBankInfo ( * getRegisterInfo ( ) ) ; +RegBankInfo . reset ( RBI ) ; +InstSelector . reset ( createPULPInstructionSelector ( * static_cast < const PULPTargetMachine * > ( & TM ) , * this , * RBI ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/anchor.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/anchor.cpp new file mode 100644 index 0000000000000000000000000000000000000000..88e30455bc00b667a0e07b1c0d8bf3ab6ef51963 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/anchor.cpp @@ -0,0 +1,2 @@ +void PULPSubtarget :: anchor ( ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/enableLinkerRelax.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/enableLinkerRelax.cpp new file mode 100644 index 0000000000000000000000000000000000000000..70a8d18a0f4959c58f34faee220172dc3452205e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/enableLinkerRelax.cpp @@ -0,0 +1,3 @@ +bool enableLinkerRelax ( ) const { +return EnableLinkerRelax ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/enableMachineScheduler.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/enableMachineScheduler.cpp new file mode 100644 index 0000000000000000000000000000000000000000..51af53569dda58106126bb9616c9b0e228522932 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/enableMachineScheduler.cpp @@ -0,0 +1,3 @@ +bool enableMachineScheduler ( ) const override { +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/enableRVCHintInstrs.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/enableRVCHintInstrs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..88c4f2c9ef4b883b0ff22bc15363b377cf8c1e96 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/enableRVCHintInstrs.cpp @@ -0,0 +1,3 @@ +bool enableRVCHintInstrs ( ) const { +return EnableRVCHintInstrs ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/enableSaveRestore.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/enableSaveRestore.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5523878c63a3fec5d0d102911de8a2fb644c25da --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/enableSaveRestore.cpp @@ -0,0 +1,3 @@ +bool enableSaveRestore ( ) const { +return EnableSaveRestore ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/getCallLowering.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/getCallLowering.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5a8365a13e63882bafd738000cff8a090f0160b3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/getCallLowering.cpp @@ -0,0 +1,3 @@ +const CallLowering * PULPSubtarget :: getCallLowering ( ) const { +return CallLoweringInfo . get ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/getFrameLowering.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/getFrameLowering.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5bbed15ea719d6d42255c0a92a1f394ddde43a0d --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/getFrameLowering.cpp @@ -0,0 +1,3 @@ +const PULPFrameLowering * getFrameLowering ( ) const override { +return & FrameLowering ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/getInstrInfo.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/getInstrInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..41bce5f76393a63852e1f0b159240cccc3d55f14 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/getInstrInfo.cpp @@ -0,0 +1,3 @@ +const PULPInstrInfo * getInstrInfo ( ) const override { +return & InstrInfo ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/getInstructionSelector.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/getInstructionSelector.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fcb22050146181e46f479d20d687089bb86a5c3f --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/getInstructionSelector.cpp @@ -0,0 +1,3 @@ +InstructionSelector * PULPSubtarget :: getInstructionSelector ( ) const { +return InstSelector . get ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/getLegalizerInfo.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/getLegalizerInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6f452b57138601c1ae86145e1495564c493e7bd7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/getLegalizerInfo.cpp @@ -0,0 +1,3 @@ +const LegalizerInfo * PULPSubtarget :: getLegalizerInfo ( ) const { +return Legalizer . get ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/getRegBankInfo.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/getRegBankInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c5cee3aa868061494bbb2d7bbeb9fef151c919bd --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/getRegBankInfo.cpp @@ -0,0 +1,3 @@ +const RegisterBankInfo * PULPSubtarget :: getRegBankInfo ( ) const { +return RegBankInfo . get ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/getRegisterInfo.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/getRegisterInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..70af2237e212bb543bccb120911f80c58a77f711 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/getRegisterInfo.cpp @@ -0,0 +1,3 @@ +const PULPRegisterInfo * getRegisterInfo ( ) const override { +return & RegInfo ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/getSelectionDAGInfo.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/getSelectionDAGInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..83c31a22c7236b0e11e56881d95a0f360d309ab2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/getSelectionDAGInfo.cpp @@ -0,0 +1,3 @@ +const SelectionDAGTargetInfo * getSelectionDAGInfo ( ) const override { +return & TSInfo ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/getTargetABI.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/getTargetABI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e2a5361219e721c25ce26aebe56fec7a9b3b3a80 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/getTargetABI.cpp @@ -0,0 +1,3 @@ +PULPABI :: ABI getTargetABI ( ) const { +return TargetABI ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/getTargetLowering.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/getTargetLowering.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2b73263bed8668c8348fa210c03fd28a2277d00e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/getTargetLowering.cpp @@ -0,0 +1,3 @@ +const PULPTargetLowering * getTargetLowering ( ) const override { +return & TLInfo ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/getXLen.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/getXLen.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a6e3bde5f9b6b485447a8bce8a0091f1a0340c94 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/getXLen.cpp @@ -0,0 +1,3 @@ +unsigned getXLen ( ) const { +return XLen ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/getXLenVT.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/getXLenVT.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6d4f4a2499c523fc8594ec194a1d030d0dad1e92 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/getXLenVT.cpp @@ -0,0 +1,3 @@ +MVT getXLenVT ( ) const { +return XLenVT ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXdma.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXdma.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fe9c424ea6f2aed686d7d43e3159a33bda4c7319 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXdma.cpp @@ -0,0 +1,3 @@ +bool hasExtXdma ( ) const { +return HasExtXdma ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfalthalf.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfalthalf.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3009034d61fd80a08c01dac822559712989ecdf2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfalthalf.cpp @@ -0,0 +1,3 @@ +bool hasExtXfalthalf ( ) const { +return HasExtXfalthalf ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfaltquarter.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfaltquarter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bab4daab1eee65c295bf4f69e40a236a339b47b9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfaltquarter.cpp @@ -0,0 +1,3 @@ +bool hasExtXfaltquarter ( ) const { +return HasExtXfaltquarter ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfauxalthalf.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfauxalthalf.cpp new file mode 100644 index 0000000000000000000000000000000000000000..88369b5f7705891c6636665e5afc49e99f8adeb8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfauxalthalf.cpp @@ -0,0 +1,3 @@ +bool hasExtXfauxalthalf ( ) const { +return HasExtXfauxalthalf ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfauxaltquarter.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfauxaltquarter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..237e500d36b35492c0584866abdcd38a20e5b2e8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfauxaltquarter.cpp @@ -0,0 +1,3 @@ +bool hasExtXfauxaltquarter ( ) const { +return HasExtXfauxaltquarter ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfauxhalf.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfauxhalf.cpp new file mode 100644 index 0000000000000000000000000000000000000000..164d2b559b215992ac5dd61cdee28950af74d821 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfauxhalf.cpp @@ -0,0 +1,3 @@ +bool hasExtXfauxhalf ( ) const { +return HasExtXfauxhalf ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfauxquarter.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfauxquarter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..12190b04f61d74eae2cb3e2b59342c9fc9e1cca0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfauxquarter.cpp @@ -0,0 +1,3 @@ +bool hasExtXfauxquarter ( ) const { +return HasExtXfauxquarter ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfauxvecalthalf.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfauxvecalthalf.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cb8ba2fc2f6afe98c7c6bf4fd389fcc7ed0578d5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfauxvecalthalf.cpp @@ -0,0 +1,3 @@ +bool hasExtXfauxvecalthalf ( ) const { +return HasExtXfauxvecalthalf ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfauxvecaltquarter.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfauxvecaltquarter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8ae742fdd06c0a952cee9360313f256773f1e781 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfauxvecaltquarter.cpp @@ -0,0 +1,3 @@ +bool hasExtXfauxvecaltquarter ( ) const { +return HasExtXfauxvecaltquarter ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfauxvechalf.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfauxvechalf.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ab66044e38a430bad413da5473a483a960629d1d --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfauxvechalf.cpp @@ -0,0 +1,3 @@ +bool hasExtXfauxvechalf ( ) const { +return HasExtXfauxvechalf ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfauxvecquarter.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfauxvecquarter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1f211da2a9a94789f6c005440d7171f7cdbd380c --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfauxvecquarter.cpp @@ -0,0 +1,3 @@ +bool hasExtXfauxvecquarter ( ) const { +return HasExtXfauxvecquarter ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfauxvecsingle.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfauxvecsingle.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a1ab3f27f885f9f093b121d2e39591c76440eaf4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfauxvecsingle.cpp @@ -0,0 +1,3 @@ +bool hasExtXfauxvecsingle ( ) const { +return HasExtXfauxvecsingle ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfexpauxvecalthalf.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfexpauxvecalthalf.cpp new file mode 100644 index 0000000000000000000000000000000000000000..23fb8a403af5615e9766755d61bf31026c360d9e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfexpauxvecalthalf.cpp @@ -0,0 +1,3 @@ +bool hasExtXfexpauxvecalthalf ( ) const { +return HasExtXfexpauxvecalthalf ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfexpauxvecaltquarter.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfexpauxvecaltquarter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c81e30ef0d5ef0080ebc1f6c2fabe2818aa8d163 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfexpauxvecaltquarter.cpp @@ -0,0 +1,3 @@ +bool hasExtXfexpauxvecaltquarter ( ) const { +return HasExtXfexpauxvecaltquarter ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfexpauxvechalf.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfexpauxvechalf.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7d29f3d4a7443be13b47e6f853b3492830aaf0b9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfexpauxvechalf.cpp @@ -0,0 +1,3 @@ +bool hasExtXfexpauxvechalf ( ) const { +return HasExtXfexpauxvechalf ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfexpauxvecquarter.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfexpauxvecquarter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2485f99aedadba92788e867bdbf05595fa3ca6ab --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfexpauxvecquarter.cpp @@ -0,0 +1,3 @@ +bool hasExtXfexpauxvecquarter ( ) const { +return HasExtXfexpauxvecquarter ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfquarter.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfquarter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1e3a5aafd523e1384ad62b424d88de1e4c99de60 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfquarter.cpp @@ -0,0 +1,3 @@ +bool hasExtXfquarter ( ) const { +return HasExtXfquarter ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfrep.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfrep.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9572b27b2650a20c1e651c8000b84b3bfc23dcff --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfrep.cpp @@ -0,0 +1,3 @@ +bool hasExtXfrep ( ) const { +return HasExtXfrep ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfvecalthalf.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfvecalthalf.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0aec901fb8bb8ee5d373d4e2f560c46934ff7065 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfvecalthalf.cpp @@ -0,0 +1,3 @@ +bool hasExtXfvecalthalf ( ) const { +return HasExtXfvecalthalf ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfvecaltquarter.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfvecaltquarter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cdc24e81790f4baa40491898d6ad8be7abea1ce5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfvecaltquarter.cpp @@ -0,0 +1,3 @@ +bool hasExtXfvecaltquarter ( ) const { +return HasExtXfvecaltquarter ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfvechalf.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfvechalf.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3f9ad1761fa085b00baab742c675f574678b7ef2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfvechalf.cpp @@ -0,0 +1,3 @@ +bool hasExtXfvechalf ( ) const { +return HasExtXfvechalf ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfvecquarter.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfvecquarter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9e071bfba2f0bdf9dfb25c346bd716eaaffc3814 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfvecquarter.cpp @@ -0,0 +1,3 @@ +bool hasExtXfvecquarter ( ) const { +return HasExtXfvecquarter ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfvecsingle.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfvecsingle.cpp new file mode 100644 index 0000000000000000000000000000000000000000..47173c96cc91a36b2b5c4d64fca2e1581e2258e6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXfvecsingle.cpp @@ -0,0 +1,3 @@ +bool hasExtXfvecsingle ( ) const { +return HasExtXfvecsingle ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXmempool.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXmempool.cpp new file mode 100644 index 0000000000000000000000000000000000000000..311dfa7acbaf30e4204ad4e76b4ecb02b02fc810 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXmempool.cpp @@ -0,0 +1,3 @@ +bool hasExtXmempool ( ) const { +return HasExtXmempool ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXsmallfloat.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXsmallfloat.cpp new file mode 100644 index 0000000000000000000000000000000000000000..86dee38376b5ab12493c76375b8a768e803fe679 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXsmallfloat.cpp @@ -0,0 +1,66 @@ +bool hasExtXsmallfloat ( ) const { +if ( HasExtXfalthalf ) { +return true ; +} +if ( HasExtXfquarter ) { +return true ; +} +if ( HasExtXfaltquarter ) { +return true ; +} +if ( HasExtXfvecsingle ) { +return true ; +} +if ( HasExtXfvechalf ) { +return true ; +} +if ( HasExtXfvecalthalf ) { +return true ; +} +if ( HasExtXfvecquarter ) { +return true ; +} +if ( HasExtXfvecaltquarter ) { +return true ; +} +if ( HasExtXfauxhalf ) { +return true ; +} +if ( HasExtXfauxalthalf ) { +return true ; +} +if ( HasExtXfauxquarter ) { +return true ; +} +if ( HasExtXfauxaltquarter ) { +return true ; +} +if ( HasExtXfauxvecsingle ) { +return true ; +} +if ( HasExtXfauxvechalf ) { +return true ; +} +if ( HasExtXfauxvecalthalf ) { +return true ; +} +if ( HasExtXfauxvecquarter ) { +return true ; +} +if ( HasExtXfauxvecaltquarter ) { +return true ; +} +if ( HasExtXfexpauxvechalf ) { +return true ; +} +if ( HasExtXfexpauxvecalthalf ) { +return true ; +} +if ( HasExtXfexpauxvecquarter ) { +return true ; +} +if ( HasExtXfexpauxvecaltquarter ) { +return true ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXssr.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXssr.cpp new file mode 100644 index 0000000000000000000000000000000000000000..48c1fc1917c48139a2d35cdececafe4e577e654f --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasExtXssr.cpp @@ -0,0 +1,3 @@ +bool hasExtXssr ( ) const { +return HasExtXssr ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasPULPExtV2.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasPULPExtV2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..655a005f88888e9a146b42979893f0809a54a652 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasPULPExtV2.cpp @@ -0,0 +1,3 @@ +bool hasPULPExtV2 ( ) const { +return HasPULPExtV2 ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtA.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtA.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f2e661f51d43203396d1e225cbc8278eace7b4df --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtA.cpp @@ -0,0 +1,3 @@ +bool hasStdExtA ( ) const { +return HasStdExtA ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtB.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtB.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ce5e9fb80677325f4d15acae0c205541ba3f0a86 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtB.cpp @@ -0,0 +1,3 @@ +bool hasStdExtB ( ) const { +return HasStdExtB ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtC.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6afa2dea62227c40e77b1d809e422cc828634c13 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtC.cpp @@ -0,0 +1,3 @@ +bool hasStdExtC ( ) const { +return HasStdExtC ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtD.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtD.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e777c791d438d140046213757adc02b4ad72943b --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtD.cpp @@ -0,0 +1,3 @@ +bool hasStdExtD ( ) const { +return HasStdExtD ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtF.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtF.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6604f1a6d0b9bd50209386800e4b95b032d791ad --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtF.cpp @@ -0,0 +1,3 @@ +bool hasStdExtF ( ) const { +return HasStdExtF ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtM.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtM.cpp new file mode 100644 index 0000000000000000000000000000000000000000..21ed588c30fce8b938d0734277487193cd84c592 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtM.cpp @@ -0,0 +1,3 @@ +bool hasStdExtM ( ) const { +return HasStdExtM ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtV.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtV.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a73c0d3f407b71b90ca2ba8539d287063ccf6f3e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtV.cpp @@ -0,0 +1,3 @@ +bool hasStdExtV ( ) const { +return HasStdExtV ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtZba.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtZba.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b5a9225770f654fcd514c1da5ab6e925fd96804a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtZba.cpp @@ -0,0 +1,3 @@ +bool hasStdExtZba ( ) const { +return HasStdExtZba ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtZbb.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtZbb.cpp new file mode 100644 index 0000000000000000000000000000000000000000..28a3678f936fee5641edcb5075f2abf9fdfe7335 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtZbb.cpp @@ -0,0 +1,3 @@ +bool hasStdExtZbb ( ) const { +return HasStdExtZbb ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtZbc.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtZbc.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5d024a63261d9fb21603c6b130f22b925d50b933 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtZbc.cpp @@ -0,0 +1,3 @@ +bool hasStdExtZbc ( ) const { +return HasStdExtZbc ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtZbe.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtZbe.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ebad6fe9769e6edcc5bc81d781126d04df82694e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtZbe.cpp @@ -0,0 +1,3 @@ +bool hasStdExtZbe ( ) const { +return HasStdExtZbe ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtZbf.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtZbf.cpp new file mode 100644 index 0000000000000000000000000000000000000000..dbc5d68d500b25105271947368d1a77de4d31b40 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtZbf.cpp @@ -0,0 +1,3 @@ +bool hasStdExtZbf ( ) const { +return HasStdExtZbf ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtZbm.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtZbm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..efaa1d7da6ca38abca75b0da6b48aced6cd1696d --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtZbm.cpp @@ -0,0 +1,3 @@ +bool hasStdExtZbm ( ) const { +return HasStdExtZbm ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtZbp.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtZbp.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b5396d1bb87eb10eee1d64fb4d8315b808898b02 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtZbp.cpp @@ -0,0 +1,3 @@ +bool hasStdExtZbp ( ) const { +return HasStdExtZbp ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtZbproposedc.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtZbproposedc.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7c12b3ad22e06eb29ebda5ab08e3dddda0e9f320 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtZbproposedc.cpp @@ -0,0 +1,3 @@ +bool hasStdExtZbproposedc ( ) const { +return HasStdExtZbproposedc ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtZbr.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtZbr.cpp new file mode 100644 index 0000000000000000000000000000000000000000..65e76b1debf4bcd1997f16adfa040bb88faf6617 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtZbr.cpp @@ -0,0 +1,3 @@ +bool hasStdExtZbr ( ) const { +return HasStdExtZbr ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtZbs.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtZbs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..98ab2c86bcc3ffd2a227696236b28d03e20fe466 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtZbs.cpp @@ -0,0 +1,3 @@ +bool hasStdExtZbs ( ) const { +return HasStdExtZbs ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtZbt.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtZbt.cpp new file mode 100644 index 0000000000000000000000000000000000000000..10ad75e226f3fc188a0b8134df8a8284a1ed10b3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtZbt.cpp @@ -0,0 +1,3 @@ +bool hasStdExtZbt ( ) const { +return HasStdExtZbt ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtZfh.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtZfh.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a754f5f42aa332191c6959d7b43fe6e6657d2d1a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtZfh.cpp @@ -0,0 +1,3 @@ +bool hasStdExtZfh ( ) const { +return HasStdExtZfh ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtZvamo.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtZvamo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fe9c8a54a357a1f5f9686c085c4f28943257ae0f --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtZvamo.cpp @@ -0,0 +1,3 @@ +bool hasStdExtZvamo ( ) const { +return HasStdExtZvamo ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtZvlsseg.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtZvlsseg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9740e1eb0dce59980aa951a67fca0ad5a27ad003 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/hasStdExtZvlsseg.cpp @@ -0,0 +1,3 @@ +bool hasStdExtZvlsseg ( ) const { +return HasStdExtZvlsseg ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/initializeSubtargetDependencies.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/initializeSubtargetDependencies.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5562388ba774934d86c579a717eea19ac879a34f --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/initializeSubtargetDependencies.cpp @@ -0,0 +1,17 @@ +PULPSubtarget & PULPSubtarget :: initializeSubtargetDependencies ( const Triple & TT , StringRef CPU , StringRef TuneCPU , StringRef FS , StringRef ABIName ) { +std :: string CPUName = CPU ; +bool Is64Bit = TT . isArch64Bit ( ) ; +if ( CPU . empty ( ) ) { +CPUName = Is64Bit ? "generic-la64" : "generic-la32" ; +} +if ( TuneCPU . empty ( ) ) { +TuneCPU = CPUName ; +} +ParseSubtargetFeatures ( CPUName , TuneCPU , FS ) ; +if ( Is64Bit ) { +GRLenVT = MVT :: i64 ; +GRLen = 64 ; +} +TargetABI = Is64Bit ? PULPABI :: ABI_LP64D : PULPABI :: ABI_ILP32D ; +return * this ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/is64Bit.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/is64Bit.cpp new file mode 100644 index 0000000000000000000000000000000000000000..44cd572e277dadcf0f1bd6ba82d9e10c25d718c0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/is64Bit.cpp @@ -0,0 +1,3 @@ +bool is64Bit ( ) const { +return HasRV64 ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/isPULP.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/isPULP.cpp new file mode 100644 index 0000000000000000000000000000000000000000..42fba830a512d7708d5062031df4142d37aa0609 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/isPULP.cpp @@ -0,0 +1,3 @@ +bool isPULP ( ) const { +return IsPULP ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/isRV32E.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/isRV32E.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d3e892bba6b18878664cc247c83bf009dbe49640 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/isRV32E.cpp @@ -0,0 +1,3 @@ +bool isRV32E ( ) const { +return IsRV32E ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/isRegisterReservedByUser.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/isRegisterReservedByUser.cpp new file mode 100644 index 0000000000000000000000000000000000000000..215b11b8089680f6135e3d2ae941e293b1c51b85 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/Subtarget/isRegisterReservedByUser.cpp @@ -0,0 +1,4 @@ +bool isRegisterReservedByUser ( Register R ) const { +assert ( R < PULP :: NUM_TARGET_REGS && "Register out of range" ) ; +return UserReservedRegister [ R ] ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetInfo/LLVMInitializeTargetInfo.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetInfo/LLVMInitializeTargetInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e797fda060833ebe4090d580eb0d8c72c77cc3e3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetInfo/LLVMInitializeTargetInfo.cpp @@ -0,0 +1,4 @@ +extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializePULPTargetInfo ( ) { +RegisterTarget < Triple :: PULP32 > X ( getThePULP32Target ( ) , "PULP32" , "32-bit PULP" , "PULP" ) ; +RegisterTarget < Triple :: PULP64 > Y ( getThePULP64Target ( ) , "PULP64" , "64-bit PULP" , "PULP" ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetInfo/getThe32Target.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetInfo/getThe32Target.cpp new file mode 100644 index 0000000000000000000000000000000000000000..99e1c1f759361b6abe2a63ae526e5783ed512bcd --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetInfo/getThe32Target.cpp @@ -0,0 +1,4 @@ +Target & llvm :: getThePULP32Target ( ) { +static Target ThePULP32Target ; +return ThePULP32Target ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetInfo/getThe64Target.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetInfo/getThe64Target.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9715d77fe8c65801fad6c96543a293d29280744d --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetInfo/getThe64Target.cpp @@ -0,0 +1,4 @@ +Target & llvm :: getThePULP64Target ( ) { +static Target ThePULP64Target ; +return ThePULP64Target ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/LLVMInitializeTarget.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/LLVMInitializeTarget.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ee0ff876464d19ee5c5279741c3a7cf5c224b24e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/LLVMInitializeTarget.cpp @@ -0,0 +1,12 @@ +extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializePULPTarget ( ) { +RegisterTargetMachine < PULPTargetMachine > X ( getThePULP32Target ( ) ) ; +RegisterTargetMachine < PULPTargetMachine > Y ( getThePULP64Target ( ) ) ; +auto * PR = PassRegistry :: getPassRegistry ( ) ; +initializeGlobalISel ( * PR ) ; +initializePULPMergeBaseOffsetOptPass ( * PR ) ; +initializePULPExpandSSRPass ( * PR ) ; +initializePULPFrepLoopPass ( * PR ) ; +initializePULPExpandSDMAPass ( * PR ) ; +initializePULPExpandPseudoPass ( * PR ) ; +initializePULPCleanupVSETVLIPass ( * PR ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/PassConfig.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/PassConfig.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8d98ca95e2918d43eb3d8514ddc55aadde8ab9ef --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/PassConfig.cpp @@ -0,0 +1,2 @@ +PULPPassConfig ( PULPTargetMachine & TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/TargetMachine.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/TargetMachine.cpp new file mode 100644 index 0000000000000000000000000000000000000000..53846d1e5c992fb2127a00c9c76e0bc4d445df96 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/TargetMachine.cpp @@ -0,0 +1,3 @@ +PULPTargetMachine :: PULPTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( RM ) , CM , OL ) , TLOF ( make_unique < TargetObjectFile > ( ) ) , Subtarget ( TT , CPU , FS , * this ) { +initAsmInfo ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/addGlobalInstructionSelect.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/addGlobalInstructionSelect.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2e54057db3f5f5dd4877a8136a85cebfb21452d5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/addGlobalInstructionSelect.cpp @@ -0,0 +1,4 @@ +bool PULPPassConfig :: addGlobalInstructionSelect ( ) { +addPass ( new InstructionSelect ( ) ) ; +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/addIRPasses.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/addIRPasses.cpp new file mode 100644 index 0000000000000000000000000000000000000000..89e855f951071b6e7221a83ea4d2d381b56d1085 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/addIRPasses.cpp @@ -0,0 +1,4 @@ +void PULPPassConfig :: addIRPasses ( ) { +addPass ( createAtomicExpandPass ( ) ) ; +TargetPassConfig :: addIRPasses ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/addIRTranslator.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/addIRTranslator.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6848710e5833cf1f0d09d434942fd7d615249f97 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/addIRTranslator.cpp @@ -0,0 +1,4 @@ +bool PULPPassConfig :: addIRTranslator ( ) { +addPass ( new IRTranslator ( getOptLevel ( ) ) ) ; +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/addInstSelector.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/addInstSelector.cpp new file mode 100644 index 0000000000000000000000000000000000000000..48be69f530d3cef75db77002055fcf8c1a16b3e1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/addInstSelector.cpp @@ -0,0 +1,4 @@ +bool PULPPassConfig :: addInstSelector ( ) { +addPass ( createPULPISelDag ( getPULPTargetMachine ( ) ) ) ; +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/addLegalizeMachineIR.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/addLegalizeMachineIR.cpp new file mode 100644 index 0000000000000000000000000000000000000000..025029726f16ba1085721bb0f51045fe28431d5d --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/addLegalizeMachineIR.cpp @@ -0,0 +1,4 @@ +bool PULPPassConfig :: addLegalizeMachineIR ( ) { +addPass ( new Legalizer ( ) ) ; +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/addPreEmitPass.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/addPreEmitPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f73822f1b0fb3073a5793449d851f429fe3c6af9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/addPreEmitPass.cpp @@ -0,0 +1,3 @@ +void PULPPassConfig :: addPreEmitPass ( ) { +addPass ( & BranchRelaxationPassID ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/addPreEmitPass2.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/addPreEmitPass2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5958376e90ea2b59ad8510ad43fb245e8ed23caf --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/addPreEmitPass2.cpp @@ -0,0 +1,5 @@ +void PULPPassConfig :: addPreEmitPass2 ( ) { +addPass ( createPULPExpandPseudoPass ( ) ) ; +addPass ( createPULPExpandAtomicPseudoPass ( ) ) ; +addPass ( createPULPFixupHwLoops ( ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/addPreRegAlloc.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/addPreRegAlloc.cpp new file mode 100644 index 0000000000000000000000000000000000000000..200ea4650c836ba4adfe574c87c58b1da2dc6f84 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/addPreRegAlloc.cpp @@ -0,0 +1,8 @@ +void PULPPassConfig :: addPreRegAlloc ( ) { +if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { +if ( EnableAdvSIMDScalar ) { +addPass ( createPULPAdvSIMDScalar ( ) ) ; +addPass ( & PeepholeOptimizerID ) ; +} +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/addPreSched2.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/addPreSched2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e838d3370e9eae9a6c5af6e3cb490a275e8bac95 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/addPreSched2.cpp @@ -0,0 +1,2 @@ +void PULPPassConfig :: addPreSched2 ( ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/addRegBankSelect.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/addRegBankSelect.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a77f455584537679760a029f7c220d00d6761e98 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/addRegBankSelect.cpp @@ -0,0 +1,4 @@ +bool PULPPassConfig :: addRegBankSelect ( ) { +addPass ( new RegBankSelect ( ) ) ; +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/computeDataLayout.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/computeDataLayout.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e269813941069ddc6f79665edc9b1dc98b70ebc7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/computeDataLayout.cpp @@ -0,0 +1,10 @@ +static StringRef computeDataLayout ( const Triple & TT ) { +if ( TT . isArch64Bit ( ) ) { +return "e-m:e-p:64:64-i64:64-i128:128-n64-S128" ; +} +assert ( TT . isArch32Bit ( ) && "only RV32 and RV64 is currently supported" ) ; +if ( TT . getVendor ( ) == Triple :: HERO ) { +return "e-m:e-p:32:32-p1:64:32-i64:64-n32-S128-P0-A0" ; +} +return "e-m:e-p:32:32-i64:64-n32-S128" ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/createPassConfig.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/createPassConfig.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f878015918400ca994abe14d9c6b6ddf4cb72803 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/createPassConfig.cpp @@ -0,0 +1,3 @@ +TargetPassConfig * TargetMachine :: createPassConfig ( PassManagerBase & PM ) { +return new PULPPassConfig ( * this , PM ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/getEffectiveRelocModel.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/getEffectiveRelocModel.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9424f05ebb3cbbd3ce9eff02ee928b811b620b67 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/getEffectiveRelocModel.cpp @@ -0,0 +1,6 @@ +static Reloc :: Model getEffectiveRelocModel ( const Triple & TT , Optional < Reloc :: Model > RM ) { +if ( ! RM . hasValue ( ) ) { +return Reloc :: Static ; +} +return * RM ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/getObjFileLowering.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/getObjFileLowering.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6174dfa05f7cbe9092209bade1a1dee2435f5e04 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/getObjFileLowering.cpp @@ -0,0 +1,3 @@ +TargetLoweringObjectFile * getObjFileLowering ( ) const override { +return TLOF . get ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/getSubtargetImpl.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/getSubtargetImpl.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0b2bce729a5fed56e869190c341c51b6b402f879 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/getSubtargetImpl.cpp @@ -0,0 +1,25 @@ +const PULPSubtarget * PULPTargetMachine :: getSubtargetImpl ( const Function & F ) const { +Attribute TuneAttr = F . getFnAttribute ( "tune-cpu" ) ; +Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; +Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; +std :: string CPU = CPUAttr . isValid ( ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; +std :: string TuneCPU = TuneAttr . isValid ( ) ? TuneAttr . getValueAsString ( ) . str ( ) : CPU ; +std :: string FS = FSAttr . isValid ( ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; +std :: string Key = CPU + TuneCPU + FS ; +auto & I = SubtargetMap [ Key ] ; +if ( ! I ) { +resetTargetOptions ( F ) ; +auto ABIName = Options . MCOptions . getABIName ( ) ; +if ( const MDString * ModuleTargetABI = dyn_cast_or_null < MDString > ( F . getParent ( ) -> getModuleFlag ( "target-abi" ) ) ) { +auto TargetABI = PULPABI :: getTargetABI ( ABIName ) ; +if ( TargetABI != PULPABI :: ABI_Unknown ) { +if ( ModuleTargetABI -> getString ( ) != ABIName ) { +report_fatal_error ( "-target-abi option != target-abi module flag" ) ; +} +} +ABIName = ModuleTargetABI -> getString ( ) ; +} +I = std :: make_unique < PULPSubtarget > ( TargetTriple , CPU , TuneCPU , FS , ABIName , * this ) ; +} +return I . get ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/getTargetMachine.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/getTargetMachine.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b6f7900c59a3ba6809e562704d5d33c3fefcba65 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/getTargetMachine.cpp @@ -0,0 +1,3 @@ +PULPTargetMachine & getPULPTargetMachine ( ) const { +return getTM < PULPTargetMachine > ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/getTargetTransformInfo.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/getTargetTransformInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..37011fd448c968457fe7e6eb3e0fc317d4cec726 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/getTargetTransformInfo.cpp @@ -0,0 +1,3 @@ +TargetTransformInfo PULPTargetMachine :: getTargetTransformInfo ( const Function & F ) { +return TargetTransformInfo ( PULPTTIImpl ( this , F ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/isNoopAddrSpaceCast.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/isNoopAddrSpaceCast.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ba852ada71e64e222c63045b5d352a5135aedb29 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/isNoopAddrSpaceCast.cpp @@ -0,0 +1,3 @@ +bool PULPTargetMachine :: isNoopAddrSpaceCast ( unsigned SrcAS , unsigned DestAS ) const { +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/setTargetOptionsWithModuleMetadata.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/setTargetOptionsWithModuleMetadata.cpp new file mode 100644 index 0000000000000000000000000000000000000000..66f3233ce462bbcd95e92c3d5c6453c1765eb60c --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetMachine/setTargetOptionsWithModuleMetadata.cpp @@ -0,0 +1,23 @@ +void PULPTargetMachine :: setTargetOptionsWithModuleMetadata ( const Module & M LLVM_ATTRIBUTE_UNUSED ) { +constexpr StringLiteral DeadKeys [ ] = { ValVerKey } ; +StringSet < > DeadKeySet ; +for ( auto & Key : DeadKeys ) { +if ( M . getModuleFlag ( Key ) ) { +DeadKeySet . insert ( Key ) ; +} +} +if ( DeadKeySet . empty ( ) ) { +return ; +} +SmallVector < Module :: ModuleFlagEntry , 8 > ModuleFlags ; +M . getModuleFlagsMetadata ( ModuleFlags ) ; +NamedMDNode * MDFlags = M . getModuleFlagsMetadata ( ) ; +MDFlags -> eraseFromParent ( ) ; +for ( auto & Flag : ModuleFlags ) { +StringRef Key = Flag . Key -> getString ( ) ; +if ( DeadKeySet . contains ( Key ) ) { +continue ; +} +M . addModuleFlag ( Flag . Behavior , Key , Flag . Val ) ; +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetObjectFile/Initialize.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetObjectFile/Initialize.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e90a31ca6ed22f65dbeebcb53ffe68d40f77772b --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetObjectFile/Initialize.cpp @@ -0,0 +1,5 @@ +void PULPELFTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { +TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; +SmallDataSection = getContext ( ) . getELFSection ( ".sdata" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; +SmallBSSSection = getContext ( ) . getELFSection ( ".sbss" , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetObjectFile/SelectSectionForGlobal.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetObjectFile/SelectSectionForGlobal.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cc78dc414b87c5bd03df0ef01a6b7712982a47f8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetObjectFile/SelectSectionForGlobal.cpp @@ -0,0 +1,13 @@ +MCSection * PULPELFTargetObjectFile :: SelectSectionForGlobal ( const GlobalObject * GO , SectionKind Kind , const TargetMachine & TM ) const { +if ( Kind . isBSS ( ) ) { +if ( isGlobalInSmallSection ( GO , TM ) ) { +return SmallBSSSection ; +} +} +if ( Kind . isData ( ) ) { +if ( isGlobalInSmallSection ( GO , TM ) ) { +return SmallDataSection ; +} +} +return TargetLoweringObjectFileELF :: SelectSectionForGlobal ( GO , Kind , TM ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetObjectFile/getModuleMetadata.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetObjectFile/getModuleMetadata.cpp new file mode 100644 index 0000000000000000000000000000000000000000..84bb6c56c9dbc97b815c0af6bf6624e7d97a9d6a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetObjectFile/getModuleMetadata.cpp @@ -0,0 +1,23 @@ +void PULPELFTargetObjectFile :: getModuleMetadata ( Module & M ) { +constexpr StringLiteral DeadKeys [ ] = { ValVerKey } ; +StringSet < > DeadKeySet ; +for ( auto & Key : DeadKeys ) { +if ( M . getModuleFlag ( Key ) ) { +DeadKeySet . insert ( Key ) ; +} +} +if ( DeadKeySet . empty ( ) ) { +return ; +} +SmallVector < Module :: ModuleFlagEntry , 8 > ModuleFlags ; +M . getModuleFlagsMetadata ( ModuleFlags ) ; +NamedMDNode * MDFlags = M . getModuleFlagsMetadata ( ) ; +MDFlags -> eraseFromParent ( ) ; +for ( auto & Flag : ModuleFlags ) { +StringRef Key = Flag . Key -> getString ( ) ; +if ( DeadKeySet . contains ( Key ) ) { +continue ; +} +M . addModuleFlag ( Flag . Behavior , Key , Flag . Val ) ; +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetObjectFile/getSectionForConstant.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetObjectFile/getSectionForConstant.cpp new file mode 100644 index 0000000000000000000000000000000000000000..641db18231fa94f60506f117957c3e508ee106a9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetObjectFile/getSectionForConstant.cpp @@ -0,0 +1,6 @@ +MCSection * PULPELFTargetObjectFile :: getSectionForConstant ( const DataLayout & DL , SectionKind Kind , const Constant * C , Align & Alignment ) const { +if ( isConstantInSmallSection ( DL , C ) ) { +return SmallDataSection ; +} +return TargetLoweringObjectFileELF :: getSectionForConstant ( DL , Kind , C , Alignment ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetObjectFile/isConstantInSmallSection.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetObjectFile/isConstantInSmallSection.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4bf38d3cb3c4ceb2081f51a95db8e57c8932949b --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetObjectFile/isConstantInSmallSection.cpp @@ -0,0 +1,3 @@ +bool PULPELFTargetObjectFile :: isConstantInSmallSection ( const DataLayout & DL , const Constant * CN ) const { +return isInSmallSection ( DL . getTypeAllocSize ( CN -> getType ( ) ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetObjectFile/isGlobalInSmallSection.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetObjectFile/isGlobalInSmallSection.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a6b23dea4216f64922521a118dfde35700085f25 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetObjectFile/isGlobalInSmallSection.cpp @@ -0,0 +1,12 @@ +bool PULPTargetObjectFile :: isGlobalInSmallSection ( const GlobalObject * GO , const TargetMachine & TM ) const { +if ( GO == nullptr ) { +return TM . getCodeModel ( ) == CodeModel :: Small ; +} +if ( GO -> isDeclaration ( ) ) { +return isGlobalInSmallSectionImpl ( GO , TM ) ; +} +if ( GO -> hasAvailableExternallyLinkage ( ) ) { +return isGlobalInSmallSectionImpl ( GO , TM ) ; +} +return isGlobalInSmallSection ( GO , TM , getKindForGlobal ( GO , TM ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetObjectFile/isInSmallSection.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetObjectFile/isInSmallSection.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5300e35df49d0511cfba12c4f83de9b0f0ee366a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetObjectFile/isInSmallSection.cpp @@ -0,0 +1,3 @@ +bool PULPELFTargetObjectFile :: isInSmallSection ( uint64_t Size ) const { +return Size > 0 && Size <= SSThreshold ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetTransformInfo/TTIImpl.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetTransformInfo/TTIImpl.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d658c44122256f95dfe0e40a16541ff66d475491 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetTransformInfo/TTIImpl.cpp @@ -0,0 +1,2 @@ +explicit PULPTTIImpl ( const PULPTargetMachine * TM , const Function & F ) : BaseT ( TM , F . getParent ( ) -> getDataLayout ( ) ) , ST ( TM -> getSubtargetImpl ( F ) ) , TLI ( ST -> getTargetLowering ( ) ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetTransformInfo/getIntImmCost.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetTransformInfo/getIntImmCost.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3fe40d9eb032baa80ed019aa9ac1f5086c2c3937 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetTransformInfo/getIntImmCost.cpp @@ -0,0 +1,6 @@ +int PULPTTIImpl :: getIntImmCost ( const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind ) { +if ( Imm == 0 ) { +return TTI :: TCC_Free ; +} +return PULPMatInt::getIntMatCost(Imm, DL.getTypeSizeInBits(Ty), getST()->is64Bit()) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetTransformInfo/getIntImmCostInst.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetTransformInfo/getIntImmCostInst.cpp new file mode 100644 index 0000000000000000000000000000000000000000..174d925f5605ea1f4ad0c168fe1f0510661cbcab --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetTransformInfo/getIntImmCostInst.cpp @@ -0,0 +1,71 @@ +int PULPTTIImpl :: getIntImmCostInst ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind , Instruction * Inst ) { +assert ( Ty -> isIntegerTy ( ) && "getIntImmCost can only estimate cost of materialising integers" ) ; +if ( Opcode == Instruction :: GetElementPtr ) { +return TTI :: TCC_Free ; +} +if ( Opcode == Instruction :: Add ) { +if ( Imm . getBitWidth ( ) <= 64 ) { +if ( Ty -> getPrimitiveSizeInBits ( ) == 8 ) { +return TTI :: TCC_Free ; +} +} +} +if ( Opcode == Instruction :: And ) { +if ( Imm . getBitWidth ( ) <= 64 ) { +if ( isInt < 32 > ( Imm . getSExtValue ( ) ) ) { +return TTI :: TCC_Free ; +} +} +return getIntImmCost ( Imm , Ty , CostKind ) ; +} +if ( Opcode == Instruction :: Or ) { +if ( Imm . getBitWidth ( ) <= 64 ) { +if ( isInt < 32 > ( Imm . getSExtValue ( ) ) ) { +return TTI :: TCC_Free ; +} +} +return getIntImmCost ( Imm , Ty , CostKind ) ; +} +if ( Opcode == Instruction :: Xor ) { +if ( Imm . getBitWidth ( ) <= 64 ) { +if ( isInt < 32 > ( Imm . getSExtValue ( ) ) ) { +return TTI :: TCC_Free ; +} +} +return getIntImmCost ( Imm , Ty , CostKind ) ; +} +if ( Opcode == Instruction :: Mul ) { +if ( Imm . getBitWidth ( ) <= 64 ) { +if ( isInt < 32 > ( Imm . getSExtValue ( ) ) ) { +return TTI :: TCC_Free ; +} +} +return getIntImmCost ( Imm , Ty , CostKind ) ; +} +if ( Opcode == Instruction :: Sub ) { +if ( Imm . getBitWidth ( ) <= 64 ) { +if ( isInt < 32 > ( Imm . getSExtValue ( ) ) ) { +return TTI :: TCC_Free ; +} +} +return getIntImmCost ( Imm , Ty , CostKind ) ; +} +if ( Opcode == Instruction :: Shl ) { +if ( Imm . getBitWidth ( ) <= 64 ) { +if ( isInt < 32 > ( Imm . getSExtValue ( ) ) ) { +return TTI :: TCC_Free ; +} +} +} +if ( Opcode == Instruction :: LShr ) { +if ( Imm . getBitWidth ( ) <= 64 ) { +if ( Ty -> getPrimitiveSizeInBits ( ) <= 32 ) { +return TTI :: TCC_Free ; +} +} +} +if ( Opcode == Instruction :: AShr ) { +return TTI :: TCC_Free ; +} +return TTI :: TCC_Free ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetTransformInfo/getIntImmCostIntrin.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetTransformInfo/getIntImmCostIntrin.cpp new file mode 100644 index 0000000000000000000000000000000000000000..687335d569416b2f632bada71895423e78301e1b --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetTransformInfo/getIntImmCostIntrin.cpp @@ -0,0 +1,3 @@ +int PULPTTIImpl :: getIntImmCostIntrin ( Intrinsic :: ID IID , unsigned Idx , const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind ) { +return TTI :: TCC_Free ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetTransformInfo/getST.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetTransformInfo/getST.cpp new file mode 100644 index 0000000000000000000000000000000000000000..eaacee90dd5a704417d08b0ded1af204f68512e8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetTransformInfo/getST.cpp @@ -0,0 +1,3 @@ +const PULPSubtarget * getST ( ) const { +return ST ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetTransformInfo/getTLI.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetTransformInfo/getTLI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..272b63030f382ea7c4ea6fc26923abd0bc321ad3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetTransformInfo/getTLI.cpp @@ -0,0 +1,3 @@ +const PULPTargetLowering * getTLI ( ) const { +return TLI ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetTransformInfo/isLoweredToCall.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetTransformInfo/isLoweredToCall.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a3bc6bfb8b4ea9f5836a152e665de12cba2aee1c --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetTransformInfo/isLoweredToCall.cpp @@ -0,0 +1,9 @@ +bool PULPTTIImpl :: isLoweredToCall ( const Function * F ) { +if ( ! F -> isIntrinsic ( ) ) { +BaseT :: isLoweredToCall ( F ) ; +} +if ( F -> getName ( ) . startswith ( "llvm.PULP_lower" ) ) { +return false ; +} +return BaseT :: isLoweredToCall ( F ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetTransformInfo/shouldFavorPostInc.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetTransformInfo/shouldFavorPostInc.cpp new file mode 100644 index 0000000000000000000000000000000000000000..25cc01cb9449b4de1a266ee4285e8e4a20907fa6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Scheduling/TargetTransformInfo/shouldFavorPostInc.cpp @@ -0,0 +1,6 @@ +bool PULPTTIImpl :: shouldFavorPostInc ( ) const { +if ( ST -> hasPULPExtV2 ( ) ) { +return true ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/CallLowering/CallLowering.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/CallLowering/CallLowering.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f148a59bf28097d834f8735509ac8eb35eb71887 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/CallLowering/CallLowering.cpp @@ -0,0 +1,2 @@ +PULPCallLowering :: PULPCallLowering ( const PULPTargetLowering & TLI ) : CallLowering ( & TLI ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/CallLowering/lowerCall.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/CallLowering/lowerCall.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d84f053e84fec3bffcd99a79d13349820044ebff --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/CallLowering/lowerCall.cpp @@ -0,0 +1,3 @@ +bool PULPCallLowering :: lowerCall ( MachineIRBuilder & MIRBuilder , CallLoweringInfo & Info ) const { +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/CallLowering/lowerFormalArguments.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/CallLowering/lowerFormalArguments.cpp new file mode 100644 index 0000000000000000000000000000000000000000..30f788cf6208dd00686d12511330fda677163c6a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/CallLowering/lowerFormalArguments.cpp @@ -0,0 +1,6 @@ +bool PULPCallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < ArrayRef < Register >> VRegs , FunctionLoweringInfo & FLI ) const { +if ( F . arg_empty ( ) ) { +return true ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/CallLowering/lowerReturn.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/CallLowering/lowerReturn.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0c29f4b207cace56001c9bb8d6b673fc2ad75815 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/CallLowering/lowerReturn.cpp @@ -0,0 +1,8 @@ +bool PULPCallLowering :: lowerReturn ( MachineIRBuilder & MIRBuilder , const Value * Val , ArrayRef < Register > VRegs , FunctionLoweringInfo & FLI ) const { +MachineInstrBuilder Ret = MIRBuilder . buildInstrNoInsert ( PULP :: PseudoRET ) ; +if ( Val != nullptr ) { +return false ; +} +MIRBuilder . insertInstr ( Ret ) ; +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/FrameLowering/FrameLowering.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/FrameLowering/FrameLowering.cpp new file mode 100644 index 0000000000000000000000000000000000000000..903e9eea1293fd7173a722fde4752eaf684ccaa2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/FrameLowering/FrameLowering.cpp @@ -0,0 +1,2 @@ +explicit PULPSubtarget & STI ) : TargetFrameLowering ( StackGrowsDown , 4 , 0 ) , STI ( STI ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/FrameLowering/adjustReg.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/FrameLowering/adjustReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7166711db0ea0fc444c65ad4c958cd3d09209bca --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/FrameLowering/adjustReg.cpp @@ -0,0 +1,22 @@ +void PULPFrameLowering :: adjustReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , Register DestReg , Register SrcReg , int64_t Val , MachineInstr :: MIFlag Flag ) const { +MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; +const PULPInstrInfo * TII = STI . getInstrInfo ( ) ; +if ( DestReg == SrcReg ) { +if ( Val == 0 ) { +return ; +} +} +if ( DestReg != SrcReg ) { +if ( isInt < 12 > ( Val ) ) { +BuildMI ( MBB , MBBI , DL , TII -> get ( PULP :: ADDI ) , DestReg ) . addReg ( SrcReg ) . addImm ( Val ) . setMIFlag ( Flag ) ; +} +if ( ! isInt < 12 > ( Val ) ) { +unsigned Opc = PULP :: ADD ; +bool isSub = Val < 0 ; +if ( isSub ) { +Opc = PULP :: SUB ; +} +Register ScratchReg = MRI . createVirtualRegister ( & PULP :: GPRRegClass ) ; +BuildMI ( MBB , MBBI , DL , TII -> get ( Opc ) , DestReg ) . addReg ( SrcReg ) . addReg ( ScratchReg , RegState :: Kill ) . setMIFlag ( Flag ) ; +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/FrameLowering/canUseAsEpilogue.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/FrameLowering/canUseAsEpilogue.cpp new file mode 100644 index 0000000000000000000000000000000000000000..62a9bb54630ef743a516a9558641755de580fe4c --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/FrameLowering/canUseAsEpilogue.cpp @@ -0,0 +1,4 @@ +bool PULPFrameLowering :: canUseAsEpilogue ( const MachineBasicBlock & MBB ) const { +return false ; +return SuccMBB -> isReturnBlock ( ) && SuccMBB -> size ( ) == 1 ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/FrameLowering/canUseAsPrologue.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/FrameLowering/canUseAsPrologue.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8553a120623a3803280c7f765bb6d1fb113dafc1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/FrameLowering/canUseAsPrologue.cpp @@ -0,0 +1,4 @@ +bool PULPFrameLowering :: canUseAsPrologue ( const MachineBasicBlock & MBB ) const { +const MachineFunction * MF = MBB . getParent ( ) ; +return !RS.isRegUsed(PULP::X5) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/FrameLowering/determineCalleeSaves.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/FrameLowering/determineCalleeSaves.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8d636cc08c16a3eb1045e16cb7aa7d4ee026d231 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/FrameLowering/determineCalleeSaves.cpp @@ -0,0 +1,66 @@ +void PULPFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { +TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; +PULPMachineFunctionInfo * CFI = MF . getInfo < PULPMachineFunctionInfo > ( ) ; +MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; +if ( hasFP ( MF ) ) { +SavedRegs . set ( PULP :: R8 ) ; +} +if ( hasBP ( MF ) ) { +SavedRegs . set ( PULP :: R7 ) ; +} +if ( MF . getFunction ( ) . hasFnAttribute ( "interrupt" ) ) { +if ( MFI . hasCalls ( ) ) { +static const MCPhysReg CSRegs [ ] = { PULP :: R0 , PULP :: R1 , PULP :: R2 , PULP :: R3 , PULP :: R12 , PULP :: R13 , 0 } ; +for ( unsigned i = 0 ; CSRegs [ i ] ; ++ i ) { +SavedRegs . set ( CSRegs [ i ] ) ; +} +static const MCPhysReg CSHRegs [ ] = { PULP :: R18 , PULP :: R19 , PULP :: R20 , PULP :: R21 , PULP :: R22 , PULP :: R23 , PULP :: R24 , PULP :: R25 , 0 } ; +for ( unsigned i = 0 ; CSHRegs [ i ] ; ++ i ) { +SavedRegs . set ( CSHRegs [ i ] ) ; +} +static const MCPhysReg CSF32Regs [ ] = { PULP :: F8_32 , PULP :: F9_32 , PULP :: F10_32 , PULP :: F11_32 , PULP :: F12_32 , PULP :: F13_32 , PULP :: F14_32 , PULP :: F15_32 , 0 } ; +static const MCPhysReg CSF64Regs [ ] = { PULP :: F8_64 , PULP :: F9_64 , PULP :: F10_64 , PULP :: F11_64 , PULP :: F12_64 , PULP :: F13_64 , PULP :: F14_64 , PULP :: F15_64 , 0 } ; +const MCPhysReg * FRegs = NULL ; +FRegs = CSF64Regs ; +FRegs = CSF64Regs ; +FRegs = CSF32Regs ; +FRegs = CSF32Regs ; +if ( FRegs != NULL ) { +const MCPhysReg * Regs = MF . getRegInfo ( ) . getCalleeSavedRegs ( ) ; +for ( unsigned i = 0 ; Regs [ i ] ; ++ i ) { +unsigned x = 0 ; +for ( ; FRegs [ x ] ; ++ x ) { +if ( FRegs [ x ] == Regs [ i ] ) { +break ; +} +} +if ( FRegs [ x ] == 0 ) { +SavedRegs . set ( Regs [ i ] ) ; +unsigned x = 0 ; +for ( ; FRegs [ x ] ; ++ x ) { +if ( FRegs [ x ] == Regs [ i ] ) { +break ; +if ( FRegs [ x ] == 0 ) { +SavedRegs . set ( Regs [ i ] ) ; +} +} +CFI -> setLRIsSpilled ( SavedRegs . test ( PULP :: R15 ) ) ; +unsigned CSStackSize = 0 ; +for ( unsigned Reg : SavedRegs . set_bits ( ) ) { +auto RegSize = TRI -> getRegSizeInBits ( Reg , MRI ) / 8 ; +CFI -> setCalleeSaveAreaSize ( CSStackSize ) ; +uint64_t Limit = estimateRSStackSizeLimit ( MF , STI ) ; +bool BigFrame = ( MFI . estimateStackSize ( MF ) + CSStackSize >= Limit ) ; +if ( BigFrame ) { +const TargetRegisterClass * RC = & PULP :: GPRRegClass ; +unsigned size = TRI -> getSpillSize ( * RC ) ; +Align align = TRI -> getSpillAlign ( * RC ) ; +if ( CFI -> isCRSpilled ( ) ) { +const TargetRegisterClass * RC = & PULP :: GPRRegClass ; +unsigned size = TRI -> getSpillSize ( * RC ) ; +Align align = TRI -> getSpillAlign ( * RC ) ; +if ( ! STI . hasE2 ( ) ) { +const TargetRegisterClass * RC = & PULP :: GPRRegClass ; +unsigned size = TRI -> getSpillSize ( * RC ) ; +Align align = TRI -> getSpillAlign ( * RC ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/FrameLowering/eliminateCallFramePseudoInstr.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/FrameLowering/eliminateCallFramePseudoInstr.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3090b9774d92b5582d1afe499461606e086813c9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/FrameLowering/eliminateCallFramePseudoInstr.cpp @@ -0,0 +1,15 @@ +MachineBasicBlock :: iterator PULPFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const { +Register SPReg = PULP :: X2 ; +DebugLoc DL = MI -> getDebugLoc ( ) ; +if ( ! hasReservedCallFrame ( MF ) ) { +int64_t Amount = MI -> getOperand ( 0 ) . getImm ( ) ; +if ( Amount != 0 ) { +Amount = alignSPAdjust ( Amount ) ; +if ( MI -> getOpcode ( ) == PULP :: ADJCALLSTACKDOWN ) { +Amount = - Amount ; +} +adjustReg ( MBB , MI , DL , SPReg , SPReg , Amount , MachineInstr :: NoFlags ) ; +} +} +return MBB . erase ( MI ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/FrameLowering/emitEpilogue.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/FrameLowering/emitEpilogue.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b8e0b98eae277442ebaaa937802cf8eac4089443 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/FrameLowering/emitEpilogue.cpp @@ -0,0 +1,33 @@ +void PULPFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { +const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; +MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; +PULPMachineFunctionInfo * CFI = MF . getInfo < PULPMachineFunctionInfo > ( ) ; +Register FPReg = getFPReg ( STI ) ; +Register SPReg = getSPReg ( STI ) ; +MachineBasicBlock :: iterator MBBI = MBB . end ( ) ; +DebugLoc DL ; +DL = MBBI -> getDebugLoc ( ) ; +if ( ! MBB . empty ( ) ) { +MBBI = MBB . getFirstTerminator ( ) ; +if ( MBBI == MBB . end ( ) ) { +MBBI = MBB . getLastNonDebugInstr ( ) ; +} +if ( ! MBBI -> isTerminator ( ) ) { +MBBI = std :: next ( MBBI ) ; +} +} +const auto & CSI = MFI . getCalleeSavedInfo ( ) ; +auto LastFrameDestroy = MBBI ; +if ( ! CSI . empty ( ) ) { +LastFrameDestroy = std :: prev ( MBBI , CSI . size ( ) ) ; +} +uint64_t StackSize = MFI . getStackSize ( ) ; +uint64_t ActualSize = CFI -> getCalleeSaveAreaSize ( ) + CFI -> getVarArgsSaveSize ( ) ; +if ( hasFP ( MF ) ) { +BuildMI ( MBB , LastFrameDestroy , DL , TII -> get ( TargetOpcode :: COPY ) , SPReg ) . addReg ( FPReg ) . setMIFlag ( MachineInstr :: NoFlags ) ; +} +if ( ! hasFP ( MF ) ) { +adjustReg ( MBB , LastFrameDestroy , DL , SPReg , SPReg , ( StackSize - ActualSize ) , MachineInstr :: FrameDestroy ) ; +} +adjustReg ( MBB , MBBI , DL , SPReg , SPReg , ActualSize , MachineInstr :: FrameDestroy ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/FrameLowering/emitPrologue.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/FrameLowering/emitPrologue.cpp new file mode 100644 index 0000000000000000000000000000000000000000..01a8b3710584081db87d35243397c5450962d749 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/FrameLowering/emitPrologue.cpp @@ -0,0 +1,55 @@ +void PULPFrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { +const RegisterInfo * RI = STI . getRegisterInfo ( ) ; +MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; +MachineFunctionInfo * CFI = MF . getInfo < MachineFunctionInfo > ( ) ; +Register SPReg = getSPReg ( STI ) ; +Register BPReg = getBPReg ( STI ) ; +const PULPInstrInfo * TII = STI . getInstrInfo ( ) ; +MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; +const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; +const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; +DebugLoc DL ; +if ( MF . getFunction ( ) . hasFnAttribute ( "interrupt" ) ) { +determineFrameLayout ( MF ) ; +uint64_t StackSize = MFI . getStackSize ( ) ; +if ( StackSize == 0 ) { +if ( ! MFI . adjustsStack ( ) ) { +return ; +const auto & CSI = MFI . getCalleeSavedInfo ( ) ; +unsigned spillAreaSize = CFI -> getCalleeSaveAreaSize ( ) ; +uint64_t ActualSize = spillAreaSize + CFI -> getVarArgsSaveSize ( ) ; +adjustReg ( MBB , MBBI , DL , SPReg , SPReg , - ( static_cast < int64_t > ( ActualSize ) ) , MachineInstr :: NoFlags ) ; +unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfaOffset ( nullptr , ActualSize ) ) ; +std :: advance ( MBBI , CSI . size ( ) ) ; +for ( const auto & Entry : CSI ) { +int64_t Offset = MFI . getObjectOffset ( Entry . getFrameIdx ( ) ) ; +unsigned Num = TRI -> getRegSizeInBits ( Reg , MRI ) / 32 ; +for ( unsigned i = 0 ; i < Num ; i ++ ) { +unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , RI -> getDwarfRegNum ( Reg , true ) + i , Offset + i * 4 ) ) ; +BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; +} +if ( hasFP ( MF ) ) { +unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaRegister ( nullptr , RI -> getDwarfRegNum ( FPReg , true ) ) ) ; +adjustReg ( MBB , MBBI , DL , SPReg , SPReg , - ( static_cast < int64_t > ( StackSize - ActualSize ) ) , MachineInstr :: NoFlags ) ; +if ( RI -> hasStackRealignment ( MF ) ) { +Align MaxAlignment = MFI . getMaxAlign ( ) ; +if ( isUInt < 12 > ( ~ ( - ( int ) MaxAlignment . value ( ) ) ) ) { +BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) , SPReg ) . addReg ( SPReg ) . addImm ( ~ ( - ( int ) MaxAlignment . value ( ) ) ) ; +if ( ! STI . hasE2 ( ) ) { +if ( ! STI . hasE2 ( ) ) { +if ( ! isUInt < 12 > ( ~ ( - ( int ) MaxAlignment . value ( ) ) ) ) { +BuildMI ( MBB , MBBI , DL , TII -> get ( PULP::ANDI ) , SPReg ) . addReg ( VR ) . addImm ( ShiftAmount ) ; +if ( ! STI . hasE2 ( ) ) { +Register VR = MF . getRegInfo ( ) . createVirtualRegister ( & PULP :: mGPRRegClass ) ; +BuildMI ( MBB , MBBI , DL , TII -> get ( PULP :: ANDI ) , VR ) . addReg ( SPReg ) ; +BuildMI ( MBB , MBBI , DL , TII -> get ( PULP::SRLI ) , VR ) . addReg ( VR ) . addImm ( ShiftAmount ) ; +BuildMI ( MBB , MBBI , DL , TII -> get ( PULP :: SLLI ) , SPReg ) . addReg ( VR ) ; +} +if ( hasBP ( MF ) ) { +BuildMI ( MBB , MBBI , DL , TII -> get ( PULP::ADDI ) , BPReg ) . addReg ( SPReg ) ; +} +} +if ( ! hasFP ( MF ) ) { +adjustReg ( MBB , MBBI , DL , SPReg , SPReg , - ( static_cast < int64_t > ( StackSize - ActualSize ) ) , MachineInstr :: NoFlags ) ; +unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfaOffset ( nullptr , MFI . getStackSize ( ) ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/FrameLowering/getFrameIndexReference.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/FrameLowering/getFrameIndexReference.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e433fa325b525de3b924d51c98e3be0c162d853f --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/FrameLowering/getFrameIndexReference.cpp @@ -0,0 +1,55 @@ +StackOffset PULPFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , Register & FrameReg ) const { +const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; +const TargetRegisterInfo * RI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; +const auto * CFI = MF . getInfo < MachineFunctionInfo > ( ) ; +const auto & CSI = MFI . getCalleeSavedInfo ( ) ; +int MinCSFI = 0 ; +int MaxCSFI = - 1 ; +int Offset = MFI . getObjectOffset ( FI ) + MFI . getOffsetAdjustment ( ) ; +if ( CSI . size ( ) ) { +MinCSFI = CSI [ 0 ] . getFrameIdx ( ) ; +MaxCSFI = CSI [ CSI . size ( ) - 1 ] . getFrameIdx ( ) ; +} +if ( FI >= MinCSFI ) { +if ( FI <= MaxCSFI ) { +FrameReg = PULP :: X2 ; +Offset = Offset + CFI -> getVarArgsSaveSize ( ) + CFI -> getCalleeSaveAreaSize ( ) ; +} +} +if ( RI -> hasStackRealignment ( MF ) ) { +if ( ! MFI . isFixedObjectIndex ( FI ) ) { +FrameReg = PULP :: X9 ; +Offset = Offset + MFI . getStackSize ( ) ; +} +if ( MFI . isFixedObjectIndex ( FI ) ) { +FrameReg = getFPReg ( STI ) ; +Offset = Offset + CFI -> getVarArgsSaveSize ( ) + CFI -> getCalleeSaveAreaSize ( ) ; +} +if ( FI > MaxCSFI ) { +if ( ! MFI . isFixedObjectIndex ( FI ) ) { +Offset = Offset + MFI . getStackSize ( ) ; +} +if ( MFI . isFixedObjectIndex ( FI ) ) { +FrameReg = getFPReg ( STI ) ; +Offset = Offset + CFI -> getVarArgsSaveSize ( ) + CFI -> getCalleeSaveAreaSize ( ) ; +} +} +} +int64_t FrameOffset = MF . getFrameInfo ( ) . getObjectOffset ( FI ) ; +if ( ! hasFP ( MF ) ) { +return StackOffset :: getFixed ( FrameOffset + MF . getFrameInfo ( ) . getStackSize ( ) ) ; +} +if ( RI -> needsStackRealignment ( MF ) ) { +if ( ! MFI . isFixedObjectIndex ( FI ) ) { +if ( hasBP ( MF ) ) { +FrameReg = PULP :: X9 ; +} +if ( ! hasBP ( MF ) ) { +FrameReg = PULP :: X2 ; +} +return StackOffset :: getFixed ( FrameOffset + MF . getFrameInfo ( ) . getStackSize ( ) ) ; +} +} +FrameReg = RI -> getFrameRegister ( MF ) ; +return StackOffset :: getFixed ( Offset ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/FrameLowering/hasBP.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/FrameLowering/hasBP.cpp new file mode 100644 index 0000000000000000000000000000000000000000..dc703371e6d4a7dff01632cd8a601fbb12708ce2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/FrameLowering/hasBP.cpp @@ -0,0 +1,5 @@ +bool PULPFrameLowering :: hasBP ( const MachineFunction & MF ) const { +const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; +const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ; +return MFI . hasVarSizedObjects ( ) && TRI -> needsStackRealignment ( MF ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/FrameLowering/hasFP.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/FrameLowering/hasFP.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f4b3147a8aee14d873c7e885d29732db6a9ba332 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/FrameLowering/hasFP.cpp @@ -0,0 +1,5 @@ +bool PULPFrameLowering :: hasFP ( const MachineFunction & MF ) const { +const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; +const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; +return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || RegInfo -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/FrameLowering/hasReservedCallFrame.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/FrameLowering/hasReservedCallFrame.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5acc7e11ddf64f3376c7ed135d57362b166ee6d3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/FrameLowering/hasReservedCallFrame.cpp @@ -0,0 +1,3 @@ +bool PULPFrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { +return ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/FrameLowering/processFunctionBeforeFrameFinalized.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/FrameLowering/processFunctionBeforeFrameFinalized.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6fa31340782d714e7a5d86ab7790f9bc2e2a54c3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/FrameLowering/processFunctionBeforeFrameFinalized.cpp @@ -0,0 +1,9 @@ +void PULPFrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { +const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; +MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; +const TargetRegisterClass * RC = & PULP :: GPRRegClass ; +if ( ! isInt < 11 > ( MFI . estimateStackSize ( MF ) ) ) { +int RegScavFI = MFI . CreateStackObject ( RegInfo -> getSpillSize ( * RC ) , RegInfo -> getSpillAlign ( * RC ) , false ) ; +RS -> addScavengingFrameIndex ( RegScavFI ) ; +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/FrameLowering/restoreCalleeSavedRegisters.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/FrameLowering/restoreCalleeSavedRegisters.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cb2e4591184cdd537ccbfd4087077cfd35b30ce3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/FrameLowering/restoreCalleeSavedRegisters.cpp @@ -0,0 +1,19 @@ +bool PULPFrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , MutableArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { +if ( CSI . empty ( ) ) { +return true ; +} +MachineFunction * MF = MBB . getParent ( ) ; +const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ; +DebugLoc DL ; +if ( MI != MBB . end ( ) ) { +if ( ! MI -> isDebugInstr ( ) ) { +DL = MI -> getDebugLoc ( ) ; +} +} +for ( auto & CS : reverse ( CSI ) ) { +Register Reg = CS . getReg ( ) ; +TII . loadRegFromStackSlot ( MBB , MI , Reg , CS . getFrameIdx ( ) , RC , TRI ) ; +assert ( MI != MBB . begin ( ) && "loadRegFromStackSlot didn't insert any code!" ) ; +} +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/FrameLowering/spillCalleeSavedRegisters.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/FrameLowering/spillCalleeSavedRegisters.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f6628096b81352d333fa08ebdccba49f4f4cd5a8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/FrameLowering/spillCalleeSavedRegisters.cpp @@ -0,0 +1,30 @@ +bool PULPFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { +if ( CSI . empty ( ) ) { +return false ; +} +DebugLoc DL ; +unsigned CalleeFrameSize = 0 ; +DebugLoc DL = MBB . findDebugLoc ( MI ) ; +DebugLoc dl ; +if ( MI != MBB . end ( ) ) { +DL = MI -> getDebugLoc ( ) ; +} +MachineFunction * MF = MBB . getParent ( ) ; +const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ; +DebugLoc DL ; +if ( MI != MBB . end ( ) ) { +DL = MI -> getDebugLoc ( ) ; +if ( ! MI -> isDebugInstr ( ) ) { +DL = MI -> getDebugLoc ( ) ; +} +} +for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { +unsigned Reg = CS . getReg ( ) ; +MachineFunction * MF = MBB . getParent ( ) ; +BuildMI ( MBB , MI , DL , TII . get ( PULP :: PseudoCALL ) ) . addReg ( Reg , getKillRegState ( IsNotLiveIn ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ; +Register Reg = CS . getReg ( ) ; +const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; +TII -> storeRegToStackSlot ( MBB , MBBI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ; +} +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelDAGToDAG/DAGToDAGISel.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelDAGToDAG/DAGToDAGISel.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b1dc2908e4cd5f64cd2c641decc34a912f7d9f6b --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelDAGToDAG/DAGToDAGISel.cpp @@ -0,0 +1,2 @@ +explicit PULPDAGToDAGISel ( PULPTargetMachine & TargetMachine ) : SelectionDAGISel ( TargetMachine ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelDAGToDAG/MatchSLLIUW.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelDAGToDAG/MatchSLLIUW.cpp new file mode 100644 index 0000000000000000000000000000000000000000..95e798d3721fbc5256a21b7b93656e3572f0893c --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelDAGToDAG/MatchSLLIUW.cpp @@ -0,0 +1,2 @@ +bool PULPDAGToDAGISel :: MatchSLLIUW ( SDNode * N ) const { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelDAGToDAG/MatchSRLIUW.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelDAGToDAG/MatchSRLIUW.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e7f2f80b43df5e9e855bbddab419f93060c32afe --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelDAGToDAG/MatchSRLIUW.cpp @@ -0,0 +1,2 @@ +bool PULPDAGToDAGISel :: MatchSRLIUW ( SDNode * N ) const { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelDAGToDAG/PostprocessISelDAG.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelDAGToDAG/PostprocessISelDAG.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b692e9a17b7ac3a5b6558496683133124c56fef7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelDAGToDAG/PostprocessISelDAG.cpp @@ -0,0 +1,106 @@ +void PULPDAGToDAGISel :: PostprocessISelDAG ( ) { +bool IsModified = false ; +if ( TM . getOptLevel ( ) == CodeGenOpt :: None ) { +SelectionDAG :: allnodes_iterator Position ( CurDAG -> getRoot ( ) . getNode ( ) ) ; +Position = Position + 1 ; +for ( ; IsModified ; ) { +IsModified = false ; +SelectionDAG :: allnodes_iterator Position = CurDAG -> allnodes_begin ( ) ; +for ( ; Position != CurDAG -> allnodes_end ( ) ; ) { +SDNode * Node = & * Position ++ ; +MachineSDNode * MachineNode = dyn_cast < MachineSDNode > ( Node ) ; +if ( ! MachineNode ) { +continue ; +} +SDNode * ResNode = Lowering . PostISelFolding ( MachineNode , * CurDAG ) ; +if ( ResNode != Node ) { +if ( ResNode ) { +ReplaceUses ( Node , ResNode ) ; +} +IsModified = true ; +} +} +CurDAG -> RemoveDeadNodes ( ) ; +DNode * N = Position - 1 ; +Position = Posiiton - 1 +if ( N -> use_empty ( ) ) { +continue ; +} +if ( ! N -> isMachineOpcode ( ) ) { +continue ; +} +unsigned FirstOp ; +unsigned StorageOpcode = N -> getMachineOpcode ( ) ; +if ( StorageOpcode == PULP::LB ) { +FirstOp = 0 ; +} +if ( StorageOpcode == PULP :: LH ) { +FirstOp = 0 ; +} +if ( StorageOpcode == PULP :: LW ) { +FirstOp = 0 ; +} +if ( StorageOpcode == PULP :: LBU ) { +FirstOp = 0 ; +} +if ( StorageOpcode == PULP :: LHU ) { +FirstOp = 0 ; +} +if ( StorageOpcode == PULP :: LWU ) { +FirstOp = 0 ; +} +if ( StorageOpcode == PULP :: LD ) { +FirstOp = 1 ; +} +if ( StorageOpcode == PULP::FLH ) { +FirstOp = 1 ; +} +if ( StorageOpcode == PULP::FLW ) { +FirstOp = 1 ; +} +if ( StorageOpcode == PULP :: FLD ) { +FirstOp = 1 ; +} +if ( StorageOpcode == PULP :: SB ) { +FirstOp = 1 ; +} +if ( ! isa < ConstantSDNode > ( N -> getOperand ( FirstOp ) ) ) { +continue ; +} +if ( N -> getConstantOperandVal ( FirstOp ) != 0 ) { +continue ; +} +SDValue Base = N -> getOperand ( FirstOp + 1 ) ; +if ( ! Base . isMachineOpcode ( ) ) { +continue ; +} +unsigned Flags = 0 ; +bool ReplaceFlags = true ; +ReplaceFlags = false ; +Flags = PULPII :: MO_DTPREL_LO ; +Flags = PULPII :: MO_TLSLD_LO ; +Flags = PULPII :: MO_TOC_LO ; +DEBUG ( dbgs ( ) << "Folding add-immediate into mem-op:\nBase: " ) ; +SDValue ImmOpnd = Base . getOperand ( 1 ) ; +if ( ReplaceFlags ) { +if ( GlobalAddressSDNode * GA = dyn_cast < GlobalAddressSDNode > ( ImmOpnd ) ) { +SDLoc dl ( GA ) ; +const GlobalValue * GV = GA -> getGlobal ( ) ; +ImmOpnd = CurDAG -> getTargetGlobalAddress ( GV , dl , MVT :: i64 , 0 , Flags ) ; +} +if ( ConstantPoolSDNode * CP = dyn_cast < ConstantPoolSDNode > ( ImmOpnd ) ) { +const Constant * C = CP -> getConstVal ( ) ; +ImmOpnd = CurDAG -> getTargetConstantPool ( C , MVT :: i64 , CP -> getAlignment ( ) , 0 , Flags ) ; +} +} +if ( FirstOp == 1 ) { +( void ) CurDAG -> UpdateNodeOperands ( N , N -> getOperand ( 0 ) , ImmOpnd , Base . getOperand ( 0 ) , N -> getOperand ( 3 ) ) ; +} +if ( FirstOp != 1 ) { +( void ) CurDAG -> UpdateNodeOperands ( N , N -> getOperand ( 0 ) , ImmOpnd , Base . getOperand ( 0 ) , N -> getOperand ( 3 ) ) ; +} +if ( Base . getNode ( ) -> use_empty ( ) ) { +CurDAG -> RemoveDeadNode ( Base . getNode ( ) ) ; +} +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelDAGToDAG/Select.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelDAGToDAG/Select.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e42919cf19a3d8e76fe877fb2e21fdf483614e72 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelDAGToDAG/Select.cpp @@ -0,0 +1,66 @@ +void PULPDAGToDAGISel :: Select ( SDNode * Node ) { +unsigned Opcode = Node -> getOpcode ( ) ; +if ( Node -> isMachineOpcode ( ) ) { +LLVM_DEBUG ( dbgs ( ) << "== " ; Node -> dump ( CurDAG ) ; dbgs ( ) << "\n" ) ; +Node -> setNodeId ( - 1 ) ; +return ; +} +EVT NodeTy = Node -> getValueType ( 0 ) ; +unsigned MultOpc ; +SDLoc Dl ( Node ) ; +unsigned Opcode = Node -> getOpcode ( ) ; +bool IsSelected = false ; +if ( Opcode == ISD :: ADD ) { +SDValue Chain = Node -> getOperand ( 0 ) ; +SDValue Skb = Node -> getOperand ( 2 ) ; +SDValue N3 = Node -> getOperand ( 3 ) ; +SDValue R6Reg = CurDAG -> getRegister ( PULP :: R6 , MVT :: i64 ) ; +Chain = CurDAG -> getCopyToReg ( Chain , DL , R6Reg , Skb , SDValue ( ) ) ; +Node = CurDAG -> UpdateNodeOperands ( Node , Chain , N1 , R6Reg , N3 ) ; +break ; +if ( IntNo == ISD :: Constant ) { +SDLoc DL ( Node ) ; +SDValue Chain = Node -> getOperand ( 0 ) ; +SDValue Skb = Node -> getOperand ( 2 ) ; +SDValue N3 = Node -> getOperand ( 3 ) ; +SDValue R6Reg = CurDAG -> getRegister ( PULP :: R6 , MVT :: i64 ) ; +Chain = CurDAG -> getCopyToReg ( Chain , DL , R6Reg , Skb , SDValue ( ) ) ; +Node = CurDAG -> UpdateNodeOperands ( Node , Chain , N1 , R6Reg , N3 ) ; +break ; +} +if ( IntNo == ISD :: FrameIndex ) { +SDLoc DL ( Node ) ; +SDValue Chain = Node -> getOperand ( 0 ) ; +SDValue Skb = Node -> getOperand ( 2 ) ; +SDValue N3 = Node -> getOperand ( 3 ) ; +SDValue R6Reg = CurDAG -> getRegister ( PULP :: R6 , MVT :: i64 ) ; +Chain = CurDAG -> getCopyToReg ( Chain , DL , R6Reg , Skb , SDValue ( ) ) ; +Node = CurDAG -> UpdateNodeOperands ( Node , Chain , N1 , R6Reg , N3 ) ; +break ; +} +} +if ( Opcode == ISD :: INTRINSIC_W_CHAIN ) { +int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ; +EVT VT = Node -> getValueType ( 0 ) ; +SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ; +unsigned Opc = PULP :: MOV_rr ; +ReplaceNode ( Node , CurDAG -> getMachineNode ( Opc , SDLoc ( Node ) , VT , TFI ) ) ; +return ; +} +if ( Opcode == ISD :: INTRINSIC_VOID ) { +const ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Node ) ; +unsigned Size = CN -> getValueSizeInBits ( 0 ) ; +int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ; +ReplaceNode ( Node , CurDAG -> getMachineNode ( Subtarget -> hasE2 ( ) ? PULP :: ADDI32 : PULP :: ADDI16XZ , Dl , MVT :: i32 , TFI , Imm ) ) ; +IsSelected = true ; +selectFrameIndex ( Node ) ; +ReplaceNode ( Node , CurDAG -> getMachineNode ( PULP :: ADDI , DL , VT , TFI , Imm ) ) ; +return ; +} +SDNode * ResNode = SelectCode ( Node ) ; +return ResNode ; +if ( IsSelected ) { +return ; +} +SelectCode ( Node ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelDAGToDAG/SelectAddrFI.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelDAGToDAG/SelectAddrFI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8fbf4a2214f637e6eccc01c52f7cc1b0c9cf1763 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelDAGToDAG/SelectAddrFI.cpp @@ -0,0 +1,7 @@ +bool PULPDAGToDAGISel :: SelectAddrFI ( SDValue Addr , SDValue & Base ) { +if ( auto FIN = dyn_cast < FrameIndexSDNode > ( Addr ) ) { +Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , Subtarget -> getXLenVT ( ) ) ; +return true ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelDAGToDAG/SelectInlineAsmMemoryOperand.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelDAGToDAG/SelectInlineAsmMemoryOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4509a401e6c43b431e223768d8ba5ec2a51e2838 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelDAGToDAG/SelectInlineAsmMemoryOperand.cpp @@ -0,0 +1,12 @@ +bool PULPDAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , unsigned ConstraintID , std :: vector < SDValue > & OutOps ) { +if ( ConstraintID == InlineAsm :: Constraint_m ) { +OutOps . push_back ( Op ) ; +return false ; +} +if ( ConstraintID == InlineAsm :: Constraint_A ) { +OutOps . push_back ( Op ) ; +return false ; +} +llvm_unreachable ( "Unexpected asm memory constraint" ) ; +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelDAGToDAG/createISelDag.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelDAGToDAG/createISelDag.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6c3030ea31ab2bbe2899c273ffe78ae1ea2cb654 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelDAGToDAG/createISelDag.cpp @@ -0,0 +1,3 @@ +FunctionPass * llvm :: createPULPISelDag ( PULPTargetMachine & TM ) { +return new PULPDAGToDAGISel ( TM ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelDAGToDAG/getPassName.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelDAGToDAG/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..27db29b6084b37c3094e16c49b5b6b3cbaf61c4f --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelDAGToDAG/getPassName.cpp @@ -0,0 +1,3 @@ +StringRef getPassName ( ) const override { +return "PULP DAG->DAG Pattern Instruction Selection" ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelDAGToDAG/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelDAGToDAG/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3ea920d1371515e7e58918ea8d68eb5287146de2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelDAGToDAG/runOnMachineFunction.cpp @@ -0,0 +1,4 @@ +bool runOnMachineFunction ( MachineFunction & MF ) override { +Subtarget = & MF . getSubtarget < PULPSubtarget > ( ) ; +return SelectionDAGISel :: runOnMachineFunction ( MF ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelDAGToDAG/selectVLOp.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelDAGToDAG/selectVLOp.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e37cd9ddbb8e4a39b365e49ab0036ede53f1312d --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelDAGToDAG/selectVLOp.cpp @@ -0,0 +1,9 @@ +bool PULPDAGToDAGISel :: selectVLOp ( SDValue N , SDValue & VL ) { +const ConstantFPSDNode * CN = dyn_cast < ConstantFPSDNode > ( N ) ; +Val = N ; +if ( v ) { +if ( ! ( v & ( v - 1 ) ) ) { +return true ; +} +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelDAGToDAG/selectVSplat.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelDAGToDAG/selectVSplat.cpp new file mode 100644 index 0000000000000000000000000000000000000000..83d708061c474ce9d75e8e12e8f69778633b9456 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelDAGToDAG/selectVSplat.cpp @@ -0,0 +1,10 @@ +bool PULPDAGToDAGISel :: selectVSplat ( SDValue N , SDValue & SplatVal ) { +const ConstantFPSDNode * CN = dyn_cast < ConstantFPSDNode > ( N ) ; +if ( ConstantSDNode * Imm = dyn_cast < ConstantSDNode > ( N . getNode ( ) ) ) { +} +if ( ! ( ConstantSDNode * Imm = dyn_cast < ConstantSDNode > ( N . getNode ( ) ) ) ) { +} +int bit = 0x1f - __builtin_clz ( v ) ; +imm = CurDAG -> getTargetConstant ( bit , MVT :: i32 ) ; +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelDAGToDAG/selectVSplatSimm5.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelDAGToDAG/selectVSplatSimm5.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4b17ff2744359b56cf3b47ea78d1c0ad380cbda8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelDAGToDAG/selectVSplatSimm5.cpp @@ -0,0 +1,10 @@ +bool PULPDAGToDAGISel :: selectVSplatSimm5 ( SDValue N , SDValue & SplatVal ) { +const ConstantFPSDNode * CN = dyn_cast < ConstantFPSDNode > ( N ) ; +if ( ConstantSDNode * Imm = dyn_cast < ConstantSDNode > ( N . getNode ( ) ) ) { +} +if ( ! ( ConstantSDNode * Imm = dyn_cast < ConstantSDNode > ( N . getNode ( ) ) ) ) { +} +int bit = 0x1f - __builtin_clz ( v ) ; +imm = CurDAG -> getTargetConstant ( bit , MVT :: i32 ) ; +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelDAGToDAG/selectVSplatUimm5.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelDAGToDAG/selectVSplatUimm5.cpp new file mode 100644 index 0000000000000000000000000000000000000000..53accdf0a0231bc08b357f1c20570eb6ab59d22c --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelDAGToDAG/selectVSplatUimm5.cpp @@ -0,0 +1,9 @@ +bool PULPDAGToDAGISel :: selectVSplatUimm5 ( SDValue N , SDValue & SplatVal ) { +const ConstantFPSDNode * CN = dyn_cast < ConstantFPSDNode > ( N ) ; +if ( ConstantSDNode * Imm = dyn_cast < ConstantSDNode > ( N . getNode ( ) ) ) { +} +if ( ! ( ConstantSDNode * Imm = dyn_cast < ConstantSDNode > ( N . getNode ( ) ) ) ) { +} +imm = CurDAG -> getTargetConstant ( bit , MVT :: i32 ) ; +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/CanLowerReturn.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/CanLowerReturn.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e7b0e4f3f81dff6d5185324b3d24b8e8bbf0f0b0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/CanLowerReturn.cpp @@ -0,0 +1,14 @@ +bool PULPTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool IsVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { +CCAssignFn * RetCC = CallConv == CallingConv :: WebKit_JS ? RetCC_PULP_WebKit_JS : RetCC_PULP_AAPCS ; +SmallVector < CCValAssign , 16 > RVLocs ; +CCState CCInfo ( CallConv , isVarArg , MF , RVLocs , Context ) ; +CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , Context ) ; +auto CCFunction = CCAssignFnForReturn ( CallConv ) ; +for ( unsigned i = 0 , e = Outs . size ( ) ; i != e ; ++ i ) { +MVT VT = Outs [ i ] . VT ; +if ( VT == MVT :: i128 ) { +return false ; +} +} +return CCInfo . CheckReturn ( Outs , RetCC ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/ComputeNumSignBitsForTargetNode.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/ComputeNumSignBitsForTargetNode.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f118a22c9ad89d07507166874e9392b65da000a8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/ComputeNumSignBitsForTargetNode.cpp @@ -0,0 +1,39 @@ +unsigned PULPTargetLowering :: ComputeNumSignBitsForTargetNode ( SDValue Op , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { +if ( Op . getOpcode ( ) == PULPISD :: SLLW ) { +return Op . getScalarValueSizeInBits ( ) ; +} +if ( Op . getOpcode ( ) == PULPISD :: SRAW ) { +return Op . getScalarValueSizeInBits ( ) ; +} +if ( Op . getOpcode ( ) == PULPISD :: SRLW ) { +return 33 ; +} +if ( Op . getOpcode ( ) == PULPISD :: DIVW ) { +return 33 ; +} +if ( Op . getOpcode ( ) == PULPISD :: DIVUW ) { +return 33 ; +} +if ( Op . getOpcode ( ) == PULPISD :: REMUW ) { +return 33 ; +} +if ( Op . getOpcode ( ) == PULPISD::VMV_X_S ) { +ConstantSDNode * Width = dyn_cast < ConstantSDNode > ( Op . getOperand ( 2 ) ) ; +if ( ! Width ) { +return 1 ; +} +unsigned SignBits = 32 - Width -> getZExtValue ( ) + 1 ; +if ( ! isNullConstant ( Op . getOperand ( 1 ) ) ) { +return SignBits ; +} +unsigned Op0SignBits = DAG . ComputeNumSignBits ( Op . getOperand ( 0 ) , Depth + 1 ) ; +SDValue Src = Op . getOperand ( 0 ) ; +unsigned Tmp = DAG . ComputeNumSignBits ( Src , Depth + 1 ) ; +Tmp = Tmp + VTBits - Src . getScalarValueSizeInBits ( ) ; +} +if ( Op . getOpcode ( ) == PULPISD :: ROLW ) { +unsigned Tmp = DAG . ComputeNumSignBits ( Src , Depth + 1 ) ; +return 33 ; +} +return 1 ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/EmitInstrWithCustomInserter.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/EmitInstrWithCustomInserter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3f9d01d0d52cd284f3f8bf94df716cea0055ce66 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/EmitInstrWithCustomInserter.cpp @@ -0,0 +1,22 @@ +MachineBasicBlock * PULPTargetLowering :: EmitInstrWithCustomInserter ( MachineInstr & MI , MachineBasicBlock * BB ) const { +if ( MI . getOpcode ( ) == PULP :: Select_GPR_Using_CC_GPR ) { +return expandSelectCC ( MI , BB , PULP :: BCOND ) ; +} +if ( MI . getOpcode ( ) == PULP :: Select_FPR16_Using_CC_GPR ) { +return expandSelectCC ( MI , BB , PULP :: BCOND ) ; +} +if ( MI . getOpcode ( ) == PULP :: Select_FPR32_Using_CC_GPR ) { +return expandSelectCC ( MI , BB , PULP :: BCOND ) ; +} +if ( MI . getOpcode ( ) == PULP :: Select_FPR64_Using_CC_GPR ) { +return expandSelectCC ( MI , BB , PULP :: BCOND ) ; +} +if ( MI . getOpcode ( ) == PULP :: BuildPairF64Pseudo ) { +return expandSelectCC ( MI , BB , PULP :: FBCOND ) ; +return EmitSelectInstr ( MI , MBB ) ; +} +if ( MI . getOpcode ( ) == PULP :: SplitF64Pseudo ) { +return expandSelectCC ( MI , BB , PULP :: FBCOND ) ; +} +llvm_unreachable ( "Unexpected instruction for custom inserter!" ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/LowerAsmOperandForConstraint.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/LowerAsmOperandForConstraint.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c0c4e8f3a468d2db19c10954ce33adb623485fa9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/LowerAsmOperandForConstraint.cpp @@ -0,0 +1,35 @@ +void PULPTargetLowering :: LowerAsmOperandForConstraint ( SDValue Op , std :: string & Constraint , std :: vector < SDValue > & Ops , SelectionDAG & DAG ) const { +SDLoc DL ( Op ) ; +SDValue Result ; +MVT XLenVT = Subtarget . getXLenVT ( ) ; +if ( Constraint . length ( ) == 1 ) { +if ( Constraint [ 0 ] == 'I' ) { +if ( auto * C = dyn_cast < ConstantSDNode > ( Op ) ) { +uint64_t Val = C -> getSExtValue ( ) ; +if ( isInt < 12 > ( Val ) ) { +Ops . push_back ( DAG . getTargetConstant ( Val , DL , XLenVT ) ) ; +} +} +return ; +} +if ( Constraint [ 0 ] == 'J' ) { +if ( auto * C = dyn_cast < ConstantSDNode > ( Op ) ) { +uint64_t Val = C -> getSExtValue ( ) ; +if ( Val == 0 ) { +Ops . push_back ( DAG . getTargetConstant ( 0 , DL , XLenVT ) ) ; +} +} +return ; +} +if ( Constraint [ 0 ] == 'K' ) { +if ( auto * C = dyn_cast < ConstantSDNode > ( Op ) ) { +uint64_t Val = C -> getSExtValue ( ) ; +if ( isUInt < 5 > ( Val ) ) { +Ops . push_back ( DAG . getTargetConstant ( Val , DL , XLenVT ) ) ; +} +} +return ; +} +} +TargetLowering :: LowerAsmOperandForConstraint ( Op , Constraint , Ops , DAG ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/LowerBlockAddress.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/LowerBlockAddress.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7423a42a3736436c160b860a97355e7f9c401b06 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/LowerBlockAddress.cpp @@ -0,0 +1,4 @@ +SDValue PULPTargetLowering :: lowerBlockAddress ( SDValue Op , SelectionDAG & DAG ) const { +BlockAddressSDNode * N = cast < BlockAddressSDNode > ( Op ) ; +return getAddr ( N , DAG ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/LowerCall.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/LowerCall.cpp new file mode 100644 index 0000000000000000000000000000000000000000..aa3b194a89c2574c5bc371a36f4b3b923cf9745a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/LowerCall.cpp @@ -0,0 +1,348 @@ +SDValue PULPTargetLowering :: LowerCall ( CallLoweringInfo & CLI , SmallVectorImpl < SDValue > & InVals ) const { +SelectionDAG & DAG = CLI . DAG ; +SDLoc & DL = CLI . DL ; +SmallVectorImpl < ISD :: OutputArg > & Outs = CLI . Outs ; +SmallVectorImpl < SDValue > & OutVals = CLI . OutVals ; +SmallVectorImpl < ISD :: InputArg > & Ins = CLI . Ins ; +DebugLoc & dl = CLI . DL ; +SmallVector < ISD :: OutputArg , 32 > & Outs = CLI . Outs ; +SmallVector < SDValue , 32 > & OutVals = CLI . OutVals ; +SmallVector < ISD :: InputArg , 32 > & Ins = CLI . Ins ; +SDValue Chain = CLI . Chain ; +SDValue Callee = CLI . Callee ; +bool & isTailCall = CLI . IsTailCall ; +CallingConv :: ID CallConv = CLI . CallConv ; +bool isVarArg = CLI . IsVarArg ; +const char * PULP16HelperFunction = 0 ; +bool needPULP16Helper = false ; +if ( Subtarget -> inMips16Mode ( ) ) { +bool lookupHelper = true ; +if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { +if ( noHelperNeeded . find ( S -> getSymbol ( ) ) != noHelperNeeded . end ( ) ) { +lookupHelper = false ; +} +} +if ( lookupHelper ) { +PULP16HelperFunction = getPULP16HelperFunction ( CLI . RetTy , CLI . Args , needPULP16Helper ) ; +} +} +MachineFunction & MF = DAG . getMachineFunction ( ) ; +isTailCall = false ; +MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; +const TargetFrameLowering * TFL = MF . getTarget ( ) . getFrameLowering ( ) ; +bool IsPIC = getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ; +SmallVector < CCValAssign , 16 > ArgLocs ; +CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; +const Function * F = nullptr ; +if ( const GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { +const GlobalValue * GV = G -> getGlobal ( ) ; +F = cast < Function > ( GV ) ; +Callee = DAG . getTargetGlobalAddress ( GV , DL , getPointerTy ( DAG . getDataLayout ( ) ) ) ; +} +if ( const ExternalSymbolSDNode * ES = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { +Callee = DAG . getTargetExternalSymbol ( ES -> getSymbol ( ) , getPointerTy ( DAG . getDataLayout ( ) ) ) ; +} +analyzeArguments ( & CLI , F , & DAG . getDataLayout ( ) , & Outs , 0 , CallConv , ArgLocs , CCInfo , true , isVarArg ) ; +unsigned NumBytes = CCInfo . getNextStackOffset ( ) ; +CCState CCInfo ( CallConv , isVarArg , DAG . getTarget ( ) , ArgLocs , * DAG . getContext ( ) ) ; +CCInfo . AnalyzeCallOperands ( Outs , CC_PULP32 ) ; +unsigned ArgsSize = CCInfo . getNextStackOffset ( ) ; +ArgsSize = ( ArgsSize + 7 ) & ~ 7 ; +MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; +SmallVector < SDValue , 8 > ByValArgs ; +for ( unsigned i = 0 , e = Outs . size ( ) ; i != e ; ++ i ) { +ISD :: ArgFlagsTy Flags = Outs [ i ] . Flags ; +if ( ! Flags . isByVal ( ) ) { +continue ; +} +SDValue Arg = OutVals [ i ] ; +unsigned Size = Flags . getByValSize ( ) ; +unsigned Align = Flags . getByValAlign ( ) ; +int FI = MFI -> CreateStackObject ( Size , Align , false ) ; +SDValue FIPtr = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; +SDValue SizeNode = DAG . getConstant ( Size , MVT :: i32 ) ; +Chain = DAG . getMemcpy ( Chain , dl , FIPtr , Arg , SizeNode , Align , false , ( Size <= 32 ) , MachinePointerInfo ( ) , MachinePointerInfo ( ) ) ; +ByValArgs . push_back ( FIPtr ) ; +} +Chain = DAG . getCALLSEQ_START ( Chain , DAG . getIntPtrConstant ( NumBytes , DL , true ) , DL ) ; +SmallVector < std :: pair < unsigned , SDValue > , 8 > RegsToPass ; +unsigned AI ; +unsigned AE ; +bool HasStackArgs = false ; +CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , ArgLocs , * DAG . getContext ( ) ) ; +PULPCC PULPCCInfo ( CallConv , IsO32 , CCInfo ) ; +PULPCCInfo . analyzeCallOperands ( Outs , isVarArg ) ; +unsigned NextStackOffset = CCInfo . getNextStackOffset ( ) ; +if ( isTailCall ) { +isTailCall = IsEligibleForTailCallOptimization ( PULPCCInfo , NextStackOffset , * MF . getInfo < PULPFunctionInfo > ( ) ) ; +} +if ( isTailCall ) { +NumTailCalls = NumTailCalls + 1 ; +} +unsigned StackAlignment = TFL -> getStackAlignment ( ) ; +NextStackOffset = RoundUpToAlignment ( NextStackOffset , StackAlignment ) ; +SDValue NextStackOffsetVal = DAG . getIntPtrConstant ( NextStackOffset , true ) ; +if ( ! isTailCall ) { +Chain = DAG . getCALLSEQ_START ( Chain , NextStackOffsetVal ) ; +} +SDValue StackPtr = DAG . getCopyFromReg ( Chain , dl , IsN64 ? PULP :: SP_64 : PULP :: SP , getPointerTy ( ) ) ; +std :: deque < std :: pair < unsigned , SDValue > > RegsToPass ; +SmallVector < SDValue , 8 > MemOpChains ; +PULPCC :: byval_iterator ByValArg = PULPCCInfo . byval_begin ( ) ; +const unsigned StackOffset = 92 ; +bool hasStructRetAttr = false ; +for ( AI = 0 , AE = ArgLocs . size ( ) ; AI != AE ; ++ AI ) { +CCValAssign & VA = ArgLocs [ AI ] ; +EVT RegVT = VA . getLocVT ( ) ; +SDValue Arg = OutVals [ AI ] ; +CCValAssign & VA = ArgLocs [ i ] ; +MVT ValVT = VA . getValVT ( ) , LocVT = VA . getLocVT ( ) ; +if ( Flags . isByVal ( ) ) { +assert ( ! isTailCall && "Do not tail-call optimize if there is a byval argument." ) ; +passByValArg ( Chain , dl , RegsToPass , MemOpChains , StackPtr , MFI , DAG , Arg , PULPCCInfo , * ByValArg , Flags , Subtarget -> isLittle ( ) ) ; +ByValArg = ByValArg + 1 ; +continue ; +Arg = ByValArgs [ byvalArgIdx ++ ] ; +} +Arg = DAG . getNode ( ISD :: SIGN_EXTEND , DL , RegVT , Arg ) ; +if ( ValVT == MVT :: f32 ) { +if ( LocVT == MVT :: i32 ) { +Arg = DAG . getNode ( ISD :: BITCAST , dl , LocVT , Arg ) ; +} +} +if ( ValVT == MVT :: f64 ) { +if ( LocVT == MVT :: i64 ) { +Arg = DAG . getNode ( ISD :: BITCAST , dl , LocVT , Arg ) ; +} +} +if ( LocVT == MVT :: i32 ) { +if ( ValVT == MVT :: f64 ) { +SDValue Lo = DAG . getNode ( PULPISD :: ExtractElementF64 , dl , MVT :: i32 , Arg , DAG . getConstant ( 0 , MVT :: i32 ) ) ; +SDValue Hi = DAG . getNode ( PULPISD :: ExtractElementF64 , dl , MVT :: i32 , Arg , DAG . getConstant ( 1 , MVT :: i32 ) ) ; +std :: swap ( Lo , Hi ) ; +unsigned LocRegLo = VA . getLocReg ( ) ; +unsigned LocRegHigh = getNextIntArgReg ( LocRegLo ) ; +RegsToPass . push_back ( std :: make_pair ( LocRegLo , Lo ) ) ; +RegsToPass . push_back ( std :: make_pair ( LocRegHigh , Hi ) ) ; +continue ; +} +} +Arg = DAG . getNode ( ISD :: ZERO_EXTEND , DL , RegVT , Arg ) ; +Arg = DAG . getNode ( ISD :: ANY_EXTEND , DL , RegVT , Arg ) ; +Arg = DAG . getNode ( ISD :: BITCAST , DL , RegVT , Arg ) ; +if ( VA . isMemLoc ( ) ) { +HasStackArgs = true ; +break ; +} +RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; +if ( Flags . isSRet ( ) ) { +SDValue StackPtr = DAG . getRegister ( PULP :: O6 , MVT :: i32 ) ; +SDValue PtrOff = DAG . getIntPtrConstant ( 64 ) ; +PtrOff = DAG . getNode ( ISD :: ADD , dl , MVT :: i32 , StackPtr , PtrOff ) ; +MemOpChains . push_back ( DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo ( ) , false , false , 0 ) ) ; +hasStructRetAttr = true ; +continue ; +} +if ( VA . needsCustom ( ) ) { +if ( VA . isMemLoc ( ) ) { +unsigned Offset = VA . getLocMemOffset ( ) + StackOffset ; +if ( Offset % 8 == 0 ) { +SDValue StackPtr = DAG . getRegister ( PULP :: O6 , MVT :: i32 ) ; +SDValue PtrOff = DAG . getIntPtrConstant ( Offset ) ; +PtrOff = DAG . getNode ( ISD :: ADD , dl , MVT :: i32 , StackPtr , PtrOff ) ; +MemOpChains . push_back ( DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo ( ) , false , false , 0 ) ) ; +continue ; +} +} +SDValue StackPtr = DAG . CreateStackTemporary ( MVT :: f64 , MVT :: i32 ) ; +SDValue Store = DAG . getStore ( DAG . getEntryNode ( ) , dl , Arg , StackPtr , MachinePointerInfo ( ) , false , false , 0 ) ; +SDValue Hi = DAG . getLoad ( MVT :: i32 , dl , Store , StackPtr , MachinePointerInfo ( ) , false , false , 0 ) ; +StackPtr = DAG . getNode ( ISD :: ADD , dl , StackPtr . getValueType ( ) , StackPtr , DAG . getIntPtrConstant ( 4 ) ) ; +SDValue Lo = DAG . getLoad ( MVT :: i32 , dl , Store , StackPtr , MachinePointerInfo ( ) , false , false , 0 ) ; +if ( VA . isRegLoc ( ) ) { +RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Hi ) ) ; +CCValAssign & NextVA = ArgLocs [ ++ i ] ; +if ( NextVA . isRegLoc ( ) ) { +RegsToPass . push_back ( std :: make_pair ( NextVA . getLocReg ( ) , Lo ) ) ; +} +if ( ! NextVA . isRegLoc ( ) ) { +unsigned Offset = NextVA . getLocMemOffset ( ) + StackOffset ; +SDValue StackPtr = DAG . getRegister ( PULP :: O6 , MVT :: i32 ) ; +SDValue PtrOff = DAG . getIntPtrConstant ( Offset ) ; +PtrOff = DAG . getNode ( ISD :: ADD , dl , MVT :: i32 , StackPtr , PtrOff ) ; +MemOpChains . push_back ( DAG . getStore ( Chain , dl , Lo , PtrOff , MachinePointerInfo ( ) , false , false , 0 ) ) ; +} +} +if ( ! VA . isRegLoc ( ) ) { +unsigned Offset = VA . getLocMemOffset ( ) + StackOffset ; +SDValue StackPtr = DAG . getRegister ( PULP :: O6 , MVT :: i32 ) ; +SDValue PtrOff = DAG . getIntPtrConstant ( Offset ) ; +PtrOff = DAG . getNode ( ISD :: ADD , dl , MVT :: i32 , StackPtr , PtrOff ) ; +MemOpChains . push_back ( DAG . getStore ( Chain , dl , Hi , PtrOff , MachinePointerInfo ( ) , false , false , 0 ) ) ; +PtrOff = DAG . getIntPtrConstant ( Offset + 4 ) ; +PtrOff = DAG . getNode ( ISD :: ADD , dl , MVT :: i32 , StackPtr , PtrOff ) ; +MemOpChains . push_back ( DAG . getStore ( Chain , dl , Lo , PtrOff , MachinePointerInfo ( ) , false , false , 0 ) ) ; +} +continue ; +} +if ( VA . isRegLoc ( ) ) { +if ( VA . getLocVT ( ) != MVT :: f32 ) { +RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; +continue ; +} +Arg = DAG . getNode ( ISD :: BITCAST , dl , MVT :: i32 , Arg ) ; +RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; +continue ; +} +assert ( VA . isMemLoc ( ) ) ; +MemOpChains . push_back ( passArgOnStack ( StackPtr , VA . getLocMemOffset ( ) , Chain , Arg , dl , isTailCall , DAG ) ) ; +SDValue StackPtr = DAG . getRegister ( PULP :: O6 , MVT :: i32 ) ; +SDValue PtrOff = DAG . getIntPtrConstant ( VA . getLocMemOffset ( ) + StackOffset ) ; +PtrOff = DAG . getNode ( ISD :: ADD , dl , MVT :: i32 , StackPtr , PtrOff ) ; +MemOpChains . push_back ( DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo ( ) , false , false , 0 ) ) ; +} +if ( HasStackArgs ) { +for ( AE = AI , AI = ArgLocs . size ( ) ; AI != AE ; -- AI ) { +unsigned Loc = AI - 1 ; +CCValAssign & VA = ArgLocs [ Loc ] ; +SDValue Arg = OutVals [ Loc ] ; +assert ( VA . isMemLoc ( ) ) ; +SDValue PtrOff = DAG . getNode ( ISD :: ADD , DL , getPointerTy ( DAG . getDataLayout ( ) ) , DAG . getRegister ( PULP :: SP , getPointerTy ( DAG . getDataLayout ( ) ) ) , DAG . getIntPtrConstant ( VA . getLocMemOffset ( ) + 1 , DL ) ) ; +Chain = DAG . getStore ( Chain , DL , Arg , PtrOff , MachinePointerInfo :: getStack ( MF , VA . getLocMemOffset ( ) ) , 0 ) ; +} +} +if ( ! MemOpChains . empty ( ) ) { +Chain = DAG . getCopyToReg ( Chain , DL , Reg . first , Reg . second , InFlag ) ; +} +bool IsPICCall = ( IsN64 || IsPIC ) ; +bool GlobalOrExternal = false , InternalLinkage = false ; +SDValue CalleeLo ; +if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { +if ( IsPICCall ) { +InternalLinkage = G -> getGlobal ( ) -> hasInternalLinkage ( ) ; +if ( InternalLinkage ) { +Callee = getAddrLocal ( Callee , DAG , HasPULP64 ) ; +} +if ( LargeGOT ) { +Callee = getAddrGlobalLargeGOT ( Callee , DAG , PULPII :: MO_CALL_HI16 , PULPII :: MO_CALL_LO16 ) ; +} +if ( ! InternalLinkage ) { +if ( ! LargeGOT ) { +Callee = getAddrGlobal ( Callee , DAG , PULPII :: MO_GOT_CALL ) ; +} +} +} +if ( ! IsPICCall ) { +Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , dl , getPointerTy ( ) , 0 , PULPII :: MO_NO_FLAG ) ; +} +GlobalOrExternal = true ; +} +if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { +if ( ! IsN64 ) { +if ( ! IsPIC ) { +Callee = DAG . getTargetExternalSymbol ( S -> getSymbol ( ) , getPointerTy ( ) , PULPII :: MO_NO_FLAG ) ; +} +} +if ( LargeGOT ) { +Callee = getAddrGlobalLargeGOT ( Callee , DAG , PULPII :: MO_CALL_HI16 , PULPII :: MO_CALL_LO16 ) ; +} +if ( ! LargeGOT ) { +Callee = getAddrGlobal ( Callee , DAG , PULPII :: MO_GOT_CALL ) ; +} +GlobalOrExternal = true ; +} +SDValue JumpTarget = Callee ; +if ( IsPICCall ) { +unsigned T9Reg = IsN64 ? PULP :: T9_64 : PULP :: T9 ; +unsigned V0Reg = PULP :: V0 ; +if ( needPULP16Helper ) { +RegsToPass . push_front ( std :: make_pair ( V0Reg , Callee ) ) ; +JumpTarget = DAG . getExternalSymbol ( PULP16HelperFunction , getPointerTy ( ) ) ; +JumpTarget = getAddrGlobal ( JumpTarget , DAG , PULPII :: MO_GOT ) ; +} +if ( ! needPULP16Helper ) { +RegsToPass . push_front ( std :: make_pair ( T9Reg , Callee ) ) ; +JumpTarget = SDValue ( ) ; +} +} +if ( ! GlobalOrExternal ) { +unsigned T9Reg = IsN64 ? PULP :: T9_64 : PULP :: T9 ; +unsigned V0Reg = PULP :: V0 ; +if ( needPULP16Helper ) { +RegsToPass . push_front ( std :: make_pair ( V0Reg , Callee ) ) ; +JumpTarget = DAG . getExternalSymbol ( PULP16HelperFunction , getPointerTy ( ) ) ; +JumpTarget = getAddrGlobal ( JumpTarget , DAG , PULPII :: MO_GOT ) ; +} +if ( ! needPULP16Helper ) { +RegsToPass . push_front ( std :: make_pair ( T9Reg , Callee ) ) ; +JumpTarget = SDValue ( ) ; +} +} +if ( IsPICCall ) { +if ( ! InternalLinkage ) { +unsigned GPReg = IsN64 ? PULP :: GP_64 : PULP :: GP ; +EVT Ty = IsN64 ? MVT :: i64 : MVT :: i32 ; +RegsToPass . push_back ( std :: make_pair ( GPReg , GetGlobalReg ( DAG , Ty ) ) ) ; +} +} +SDValue InFlag ; +for ( auto Reg : RegsToPass ) { +unsigned Reg = RegsToPass [ i ] . first ; +Reg = Reg - PULP :: I0 + PULP :: O0 ; +Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( NumBytes , DL , true ) , DAG . getIntPtrConstant ( 0 , DL , true ) , InFlag , DL ) ; +InFlag = Chain . getValue ( 1 ) ; +} +unsigned SRetArgSize = ( hasStructRetAttr ) ? getSRetArgSize ( DAG , Callee ) : 0 ; +if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { +Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , dl , MVT :: i32 ) ; +} +if ( ExternalSymbolSDNode * E = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { +Callee = DAG . getTargetExternalSymbol ( E -> getSymbol ( ) , MVT :: i32 ) ; +} +SDVTList NodeTys = DAG . getVTList ( MVT :: Other , MVT :: Glue ) ; +SmallVector < SDValue , 8 > Ops ; +Ops . push_back ( Chain ) ; +Ops . push_back ( Callee ) ; +SmallVector < SDValue , 8 > Ops ( 1 , Chain ) ; +if ( JumpTarget . getNode ( ) ) { +Ops . push_back ( JumpTarget ) ; +} +if ( hasStructRetAttr ) { +Ops . push_back ( DAG . getTargetConstant ( SRetArgSize , MVT :: i32 ) ) ; +} +for ( auto Reg : RegsToPass ) { +Ops . push_back ( DAG . getRegister ( Reg . first , Reg . second . getValueType ( ) ) ) ; +Ops . push_back ( DAG . getRegister ( RegsToPass [ i ] . first , RegsToPass [ i ] . second . getValueType ( ) ) ) ; +unsigned Reg = RegsToPass [ i ] . first ; +Reg = Reg - PULP :: I0 + PULP :: O0 ; +Ops . push_back ( DAG . getRegister ( Reg , RegsToPass [ i ] . second . getValueType ( ) ) ) ; +} +const PULPTargetMachine & TM = ( const PULPTargetMachine & ) getTargetMachine ( ) ; +const TargetRegisterInfo * TRI = TM . getSubtargetImpl ( ) -> getRegisterInfo ( ) ; +const uint32_t * Mask = TRI -> getCallPreservedMask ( DAG . getMachineFunction ( ) , CallConv ) ; +assert ( Mask && "Missing call preserved mask for calling convention" ) ; +Ops . push_back ( DAG . getRegisterMask ( Mask ) ) ; +if ( InFlag . getNode ( ) ) { +Ops . push_back ( InFlag ) ; +} +if ( isTailCall ) { +return DAG . getNode ( PULPISD :: TailCall , dl , MVT :: Other , & Ops [ 0 ] , Ops . size ( ) ) ; +} +Chain = DAG . getNode ( PULPISD :: CALL , DL , NodeTys , Ops ) ; +InFlag = Chain . getValue ( 1 ) ; +Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( NumBytes , DL , true ) , DAG . getIntPtrConstant ( 0 , DL , true ) , InFlag , DL ) ; +if ( ! Ins . empty ( ) ) { +InFlag = Chain . getValue ( 1 ) ; +} +InFlag = Chain . getValue ( 1 ) ; +SmallVector < CCValAssign , 16 > RVLocs ; +CCState RVInfo ( CallConv , isVarArg , DAG . getTarget ( ) , RVLocs , * DAG . getContext ( ) ) ; +RVInfo . AnalyzeCallResult ( Ins , RetCC_PULP32 ) ; +for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { +unsigned Reg = RVLocs [ i ] . getLocReg ( ) ; +Reg = Reg - PULP :: I0 + PULP :: O0 ; +Chain = DAG . getCopyFromReg ( Chain , dl , Reg , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ; +InFlag = Chain . getValue ( 2 ) ; +InVals . push_back ( Chain . getValue ( 0 ) ) ; +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/LowerConstantPool.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/LowerConstantPool.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0b28c64377364169881fa109e093226d61a4a224 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/LowerConstantPool.cpp @@ -0,0 +1,4 @@ +SDValue PULPTargetLowering :: lowerConstantPool ( SDValue Op , SelectionDAG & DAG ) const { +ConstantPoolSDNode * N = cast < ConstantPoolSDNode > ( Op ) ; +return getAddr ( N , DAG ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/LowerFRAMEADDR.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/LowerFRAMEADDR.cpp new file mode 100644 index 0000000000000000000000000000000000000000..063f553d01ac4989c93016ae18c3c3153ed55702 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/LowerFRAMEADDR.cpp @@ -0,0 +1,19 @@ +SDValue PULPTargetLowering :: lowerFRAMEADDR ( SDValue Op , SelectionDAG & DAG ) const { +const PULPRegisterInfo & RI = * Subtarget . getRegisterInfo ( ) ; +MachineFunction & MF = DAG . getMachineFunction ( ) ; +MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; +MFI . setFrameAddressIsTaken ( true ) ; +Register FrameReg = RI . getFrameRegister ( MF ) ; +int XLenInBytes = Subtarget . getZLen ( ) / 8 ; +EVT VT = Op . getValueType ( ) ; +SDLoc DL ( Op ) ; +SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , FrameReg , VT ) ; +unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( 0 ) ) -> getZExtValue ( ) ; +for ( ; Depth > 0 ; ) { +int Offset = - ( XLenInBytes * 2 ) ; +SDValue Ptr = DAG . getNode ( ISD :: ADD , DL , VT , FrameAddr , DAG . getIntPtrConstant ( Offset , DL ) ) ; +FrameAddr = DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , Ptr , MachinePointerInfo ( ) ) ; +Depth = Depth - 1 ; +} +return FrameAddr ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/LowerFormalArguments.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/LowerFormalArguments.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e448d1aa48b6eb3bd7f9d0cffb9f93cf01856041 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/LowerFormalArguments.cpp @@ -0,0 +1,149 @@ +SDValue PULPTargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , const SDLoc & DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { +if ( CallCConv != CallingConv :: C ) { +if ( CallCConv != CallingConv :: Fast ) { +report_fatal_error ( "Unsupported calling convention" ) ; +} +} +LLVM_DEBUG ( dbgs ( ) << "ISelDAG: Lowering formal arguments\n" ) ; +if ( isVarArg ) { +LLVM_DEBUG ( dbgs ( ) << "ISelDAG: Can't lower variadic arguments\n" ) ; +return SDValue ( ) ; +} +MachineFunction & MF = DAG . getMachineFunction ( ) ; +std :: vector < SDValue > OutChains ; +unsigned ArgsBaseOffset = 176 ; +unsigned ArgsPreserved = 64 ; +PULPMachineFunctionInfo * FuncInfo = MF . getInfo < PULPMachineFunctionInfo > ( ) ; +MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; +MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; +SmallVector < CCValAssign , 16 > ArgLocs ; +CCState CCInfo ( CallConv , IsVarArg , MF , ArgLocs , * DAG . getContext ( ) ) ; +CCInfo . AnalyzeFormalArguments ( Ins , CCAssignFnForCall ( CallConv , IsVarArg ) ) ; +CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; +CCInfo . AllocateStack ( ArgsPreserved , Align ( 8 ) ) ; +CCInfo . AnalyzeFormalArguments ( Ins , CC_PULP ) ; +CCState CCInfo ( CallConv , isVarArg , MF , ArgLocs , * DAG . getContext ( ) ) ; +CCInfo . AnalyzeFormalArguments ( Ins , CCAssignFnForCall ( CallConv , isVarArg ) ) ; +Chain = DAG . getNode ( PULPISD :: ENTRY_FLAG , DL , MVT :: Other , { Chain , DAG . getRegister ( PULP :: a1 , MVT :: i32 ) , DAG . getTargetConstant ( 4 , DL , MVT :: i32 ) } ) ; +CCInfo . AnalyzeFormalArguments ( Ins , getCCAssignFn ( CallConv ) ) ; +if ( MFI . hasVAStart ( ) ) { +FuncInfo -> setVarArgsFrameIndex ( MFI . CreateFixedObject ( 1 , CCInfo . getNextStackOffset ( ) , true ) ) ; +} +SDValue ArgValue ; +for ( unsigned i = 0 , e = ArgLocs . size ( ) ; i != e ; ++ i ) { +CCValAssign & VA = ArgLocs [ i ] ; +SDValue ArgValue ; +bool IsF64OnPULP = VA . getLocVT ( ) == MVT :: i32 && VA . getValVT ( ) == MVT :: f64 ; +if ( IsF64OnPULP ) { +ArgValue = unpack64 ( DAG , Chain , VA , DL ) ; +} +if ( ! IsF64OnPULP ) { +if ( VA . isRegLoc ( ) ) { +ArgValue = unpackFromRegLoc ( Subtarget , DAG , Chain , VA , DL ) ; +} +} +if ( ! IsF64OnPULP ) { +if ( ! VA . isRegLoc ( ) ) { +ArgValue = unpackFromMemLoc ( DAG , Chain , VA , DL ) ; +} +} +InVals . push_back ( ArgValue ) ; +if ( VA . isRegLoc ( ) ) { +unsigned VReg = MF . addLiveIn ( VA . getLocReg ( ) , getRegClassFor ( VA . getLocVT ( ) ) ) ; +SDValue Arg = DAG . getCopyFromReg ( Chain , DL , VReg , VA . getLocVT ( ) ) ; +if ( VA . getValVT ( ) == MVT :: i32 ) { +if ( VA . needsCustom ( ) ) { +Arg = DAG . getNode ( ISD :: SRL , DL , VA . getLocVT ( ) , Arg , DAG . getConstant ( 32 , DL , MVT :: i32 ) ) ; +} +} +if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) { +Arg = DAG . getNode ( ISD :: AssertSext , DL , VA . getLocVT ( ) , Arg , DAG . getValueType ( VA . getValVT ( ) ) ) ; +} +if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) { +Arg = DAG . getNode ( ISD :: AssertZext , DL , VA . getLocVT ( ) , Arg , DAG . getValueType ( VA . getValVT ( ) ) ) ; +} +if ( VA . isExtInLoc ( ) ) { +Arg = DAG . getNode ( ISD :: TRUNCATE , DL , VA . getValVT ( ) , Arg ) ; +} +InVals . push_back ( Arg ) ; +continue ; +} +unsigned Offset = VA . getLocMemOffset ( ) + ArgsBaseOffset ; +unsigned ValSize = VA . getValVT ( ) . getSizeInBits ( ) / 8 ; +int FI = MF . getFrameInfo ( ) . CreateFixedObject ( ValSize , Offset , true ) ; +InVals . push_back ( DAG . getLoad ( VA . getValVT ( ) , DL , Chain , DAG . getFrameIndex ( FI , getPointerTy ( MF . getDataLayout ( ) ) ) , MachinePointerInfo :: getFixedStack ( MF , FI ) ) ) ; +if ( VA . isRegLoc ( ) ) { +EVT RegVT = VA . getLocVT ( ) ; +const TargetRegisterClass * RC ; +if ( RegVT == MVT :: i32 ) { +RC = & PULP :: GPRRegClass ; +} +if ( RegVT == MVT :: f32 ) { +RC = & PULP :: FPRRegClass ; +} +unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ; +SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , RegVT ) ; +if ( VA . getLocInfo ( ) == CCValAssign :: Full ) { +InVals . push_back ( ArgValue ) ; +} +if ( VA . getLocInfo ( ) == CCValAssign :: BCvt ) { +ArgValue = DAG . getNode ( ISD :: BITCAST , DL , VA . getValVT ( ) , ArgValue ) ; +InVals . push_back ( ArgValue ) ; +} +} +SDValue Val = DAG . getLoad ( VA . getLocInfo ( ) == CCValAssign :: AExt ? VA . getValVT ( ) : VA . getLocVT ( ) , DL , Chain , DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) ) ; +if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) { +MFI . setObjectZExt ( FI , true ) ; +Val = DAG . getNode ( ISD :: AssertZext , DL , VA . getLocVT ( ) , Val , DAG . getValueType ( VA . getValVT ( ) ) ) ; +} +if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) { +MFI . setObjectSExt ( FI , true ) ; +Val = DAG . getNode ( ISD :: AssertSext , DL , VA . getLocVT ( ) , Val , DAG . getValueType ( VA . getValVT ( ) ) ) ; +} +InVals . push_back ( DAG . getNode ( ISD :: TRUNCATE , DL , VA . getValVT ( ) , Val ) ) ; +} +if ( IsVarArg ) { +const unsigned XLenInBytes = 4 ; +const MVT XLenVT = MVT :: i32 ; +ArrayRef < MCPhysReg > ArgRegs = makeArrayRef ( GPRArgRegs ) ; +unsigned Idx = CCInfo . getFirstUnallocated ( ArgRegs ) ; +const TargetRegisterClass * RC = & PULP :: GPRRegClass ; +MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; +MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; +PULPMachineFunctionInfo * PULPFI = MF . getInfo < PULPMachineFunctionInfo > ( ) ; +int VaArgOffset ; +int VarArgsSaveSize ; +if ( ArgRegs . size ( ) == Idx ) { +VaArgOffset = CCInfo . getNextStackOffset ( ) ; +VarArgsSaveSize = 0 ; +} +if ( ArgRegs . size ( ) != Idx ) { +VarArgsSaveSize = XLenInBytes * ( ArgRegs . size ( ) - Idx ) ; +VaArgOffset = - VarArgsSaveSize ; +} +int FI = MFI . CreateFixedObject ( XLenInBytes , VaArgOffset , true ) ; +PULPFI -> setVarArgsFrameIndex ( FI ) ; +for ( unsigned i = Idx ; i < ArgRegs . size ( ) ; ++ i , VaArgOffset += XLenInBytes ) { +const Register Reg = RegInfo . createVirtualRegister ( RC ) ; +RegInfo . addLiveIn ( ArgRegs [ i ] , Reg ) ; +SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , XLenVT ) ; +FI = MFI . CreateFixedObject ( XLenInBytes , VaArgOffset , true ) ; +SDValue PtrOff = DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) ; +SDValue Store = DAG . getStore ( Chain , DL , ArgValue , PtrOff , MachinePointerInfo :: getFixedStack ( MF , FI ) ) ; +cast < StoreSDNode > ( Store . getNode ( ) ) -> getMemOperand ( ) -> setValue ( ( Value * ) nullptr ) ; +OutChains . push_back ( Store ) ; +} +PULPFI -> setVarArgsSaveSize ( VarArgsSaveSize ) ; +} +if ( ! OutChains . empty ( ) ) { +OutChains . push_back ( Chain ) ; +Chain = DAG . getNode ( ISD :: TokenFactor , DL , MVT :: Other , OutChains ) ; +} +if ( ! IsVarArg ) { +return Chain ; +} +unsigned ArgOffset = ArgLocs . size ( ) * 8 ; +PULPMachineFunctionInfo * FuncInfo = MF . getInfo < PULPMachineFunctionInfo > ( ) ; +FuncInfo -> setVarArgsFrameOffset ( ArgOffset + ArgsBaseOffset ) ; +return Chain ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/LowerGlobalAddress.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/LowerGlobalAddress.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5bfaf57e5f7ff0059e78e48f6528ea97330a9285 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/LowerGlobalAddress.cpp @@ -0,0 +1,14 @@ +SDValue PULPTargetLowering :: lowerGlobalAddress ( SDValue Op , SelectionDAG & DAG ) const { +SDLoc DL ( Op ) ; +EVT Ty = Op . getValueType ( ) ; +GlobalAddressSDNode * N = cast < GlobalAddressSDNode > ( Op ) ; +int64_t Offset = N -> getOffset ( ) ; +MVT XLenVT = Subtarget . getXLenVT ( ) ; +const GlobalValue * GV = N -> getGlobal ( ) ; +bool IsLocal = getTargetMachine ( ) . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ; +SDValue Addr = getAddr ( N , DAG , IsLocal ) ; +if ( Offset ) { +return DAG . getNode ( ISD :: ADD , DL , Ty , Addr , DAG . getConstant ( Offset , DL , XLenVT ) ) ; +} +return Addr ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/LowerGlobalTLSAddress.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/LowerGlobalTLSAddress.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a1c50fd6ac9d167adc5603667f9c2fc2ca03b2eb --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/LowerGlobalTLSAddress.cpp @@ -0,0 +1,28 @@ +SDValue PULPTargetLowering :: lowerGlobalTLSAddress ( SDValue Op , SelectionDAG & DAG ) const { +SDLoc DL ( Op ) ; +EVT Ty = Op . getValueType ( ) ; +GlobalAddressSDNode * N = cast < GlobalAddressSDNode > ( Op ) ; +int64_t Offset = N -> getOffset ( ) ; +MVT XLenVT = Subtarget . getXLenVT ( ) ; +TLSModel :: Model Model = getTargetMachine ( ) . getTLSModel ( N -> getGlobal ( ) ) ; +if ( DAG . getMachineFunction ( ) . getFunction ( ) . getCallingConv ( ) == CallingConv :: GHC ) { +report_fatal_error ( "In GHC calling convention TLS is not supported" ) ; +} +SDValue Addr ; +if ( Model == TLSModel :: LocalExec ) { +Addr = getStaticTLSAddr ( N , DAG , false ) ; +} +if ( Model == TLSModel :: InitialExec ) { +Addr = getStaticTLSAddr ( N , DAG , true ) ; +} +if ( Model == TLSModel :: LocalDynamic ) { +Addr = getDynamicTLSAddr ( N , DAG ) ; +} +if ( Model == TLSModel :: GeneralDynamic ) { +Addr = getDynamicTLSAddr ( N , DAG ) ; +} +if ( Offset != 0 ) { +return DAG . getNode ( ISD :: ADD , DL , Ty , Addr , DAG . getConstant ( Offset , DL , XLenVT ) ) ; +} +return Addr ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/LowerINTRINSIC_WO_CHAIN.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/LowerINTRINSIC_WO_CHAIN.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d02699653bda3af654bacdd8ae228b7dfe41386c --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/LowerINTRINSIC_WO_CHAIN.cpp @@ -0,0 +1,29 @@ +SDValue PULPTargetLowering :: LowerINTRINSIC_WO_CHAIN ( SDValue Op , SelectionDAG & DAG ) const { +MVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; +unsigned IntNo = cast < ConstantSDNode > ( Op . getOperand ( 0 ) ) -> getZExtValue ( ) ; +DebugLoc DL = Op . getDebugLoc ( ) ; +SDLoc DL ( Op ) ; +SmallVector < SDValue , 16 > Ops ( std :: next ( Op -> op_begin ( ) ) , Op -> op_end ( ) ) ; +unsigned Size = Ops . size ( ) ; +bool SmallTuple = Size <= PULPTargetMachine :: SmallTupleLimit ; +Ops . push_back ( DAG . getConstant ( Size , DL , MVT :: i257 , SmallTuple ) ) ; +unsigned Cmd = SmallTuple ? PULPISD :: TUPLE : PULPISD :: TUPLEVAR ; +MachineFunction & MF = DAG . getMachineFunction ( ) ; +MVT VT = Op . getSimpleValueType ( ) ; +const PULPTargetMachine * TM = static_cast < const PULPTargetMachine * > ( & DAG . getTarget ( ) ) ; +TM -> getStrList ( ) -> push_back ( std :: string ( ( Twine ( "GCC_except_table" ) + Twine ( MF . getFunctionNumber ( ) ) ) . str ( ) ) ) ; +SDValue Addr = DAG . getTargetExternalSymbol ( TM -> getStrList ( ) -> back ( ) . c_str ( ) , VT , 0 ) ; +if ( isPositionIndependent ( ) ) { +Addr = makeHiLoPair ( Addr , PULPMCExpr :: VK_PULP_GOTOFF_HI32 , PULPMCExpr :: VK_PULP_GOTOFF_LO32 , DAG ) ; +SDValue GlobalBase = DAG . getNode ( PULPISD :: GLOBAL_BASE_REG , DL , VT ) ; +return DAG . getNode ( ISD :: ADD , DL , VT , GlobalBase , Addr ) ; +} +EVT VT = Op . getValueType ( ) ; +const PULPTargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; +MVT PtrVT = TLI . getPointerTy ( DAG . getDataLayout ( ) ) ; +auto & Context = MF . getMMI ( ) . getContext ( ) ; +MCSymbol * S = Context . getOrCreateSymbol ( Twine ( "GCC_except_table" ) + Twine ( MF . getFunctionNumber ( ) ) ) ; +EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; +return DAG . getRegister ( PULP :: G7 , PtrVT ) ; +return SDValue ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/LowerINTRINSIC_W_CHAIN.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/LowerINTRINSIC_W_CHAIN.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bdfd9a6f88c88e9e63eb9203cb2cf584709d4232 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/LowerINTRINSIC_W_CHAIN.cpp @@ -0,0 +1,68 @@ +SDValue PULPTargetLowering :: LowerINTRINSIC_W_CHAIN ( SDValue Op , SelectionDAG & DAG ) const { +unsigned IntNo = Op . getConstantOperandVal ( 1 ) ; +if ( IntNo == Intrinsic :: PULP_vleff ) { +return lowerDSPIntr ( Op , DAG , PULPISD :: EXTP ) ; +} +if ( IntNo == Intrinsic :: PULP_vleff_mask ) { +return lowerDSPIntr ( Op , DAG , PULPISD :: EXTPDP ) ; +} +if ( IntNo == Intrinsic :: PULP_vlseg8ff ) { +return lowerDSPIntr ( Op , DAG , PULPISD :: EXTR_W ) ; +} +if ( IntNo == Intrinsic :: PULP_vlseg7ff ) { +return lowerDSPIntr ( Op , DAG , PULPISD :: EXTR_R_W ) ; +} +if ( IntNo == Intrinsic :: PULP_vlseg6ff ) { +return lowerDSPIntr ( Op , DAG , PULPISD :: EXTR_RS_W ) ; +} +if ( IntNo == Intrinsic :: PULP_vlseg5ff ) { +return lowerDSPIntr ( Op , DAG , PULPISD :: EXTR_S_H ) ; +} +if ( IntNo == Intrinsic :: PULP_vlseg4ff ) { +return lowerDSPIntr ( Op , DAG , PULPISD :: MTHLIP ) ; +} +if ( IntNo == Intrinsic :: PULP_vlseg2ff ) { +return lowerDSPIntr ( Op , DAG , PULPISD :: MULSAQ_S_W_PH ) ; +} +if ( IntNo == Intrinsic :: PULP_vlseg8ff_mask ) { +return lowerDSPIntr ( Op , DAG , PULPISD :: MAQ_S_W_PHL ) ; +} +if ( IntNo == Intrinsic :: PULP_vlseg7ff_mask ) { +return lowerDSPIntr ( Op , DAG , PULPISD :: MAQ_S_W_PHR ) ; +} +if ( IntNo == Intrinsic :: PULP_vlseg6ff_mask ) { +return lowerDSPIntr ( Op , DAG , PULPISD :: MAQ_SA_W_PHL ) ; +} +if ( IntNo == Intrinsic :: PULP_vlseg5ff_mask ) { +return lowerDSPIntr ( Op , DAG , PULPISD :: MAQ_SA_W_PHR ) ; +} +if ( IntNo == Intrinsic :: PULP_vlseg4ff_mask ) { +return lowerDSPIntr ( Op , DAG , PULPISD :: DPAQ_S_W_PH ) ; +} +if ( IntNo == Intrinsic :: PULP_vlseg3ff_mask ) { +return lowerDSPIntr ( Op , DAG , PULPISD :: DPSQ_S_W_PH ) ; +} +if ( IntNo == Intrinsic :: PULP_vlseg2ff_mask ) { +auto Node = cast < MemIntrinsicSDNode > ( Op . getNode ( ) ) ; +SDLoc DL ( Op ) ; +SDValue Chain = Node -> getChain ( ) ; +SDValue Dst = Op . getOperand ( 2 ) ; +SDValue Val = Op . getOperand ( 3 ) ; +Val = DAG . getAnyExtOrTrunc ( Val , DL , MVT :: i64 ) ; +SDValue Size = Op . getOperand ( 4 ) ; +auto Alignment = Node -> getMemOperand ( ) -> getAlign ( ) ; +bool IsVol = Node -> isVolatile ( ) ; +auto DstPtrInfo = Node -> getPointerInfo ( ) ; +const auto & SDI = static_cast < const PULPSelectionDAGInfo & > ( DAG . getSelectionDAGInfo ( ) ) ; +SDValue MS = SDI . EmitMOPS ( PULPISD :: MOPS_MEMSET_TAGGING , DAG , DL , Chain , Dst , Val , Size , Alignment , IsVol , DstPtrInfo , MachinePointerInfo { } ) ; +} +unsigned Opcode ; +unsigned CCValid ; +if ( isIntrinsicWithCCAndChain ( Op , Opcode , CCValid ) ) { +SDNode * Node = emitIntrinsicWithCCAndChain ( DAG , Op , Opcode ) ; +SDValue CC = getCCResult ( DAG , SDValue ( Node , 0 ) ) ; +DAG . ReplaceAllUsesOfValueWith ( SDValue ( Op . getNode ( ) , 0 ) , CC ) ; +return SDValue ( ) ; +} +return SDValue ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/LowerJumpTable.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/LowerJumpTable.cpp new file mode 100644 index 0000000000000000000000000000000000000000..032d5f9b603800d7ea396c77063c034d185b6d18 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/LowerJumpTable.cpp @@ -0,0 +1,4 @@ +SDValue PULPTargetLowering :: lowerJumpTable ( SDValue Op , SelectionDAG & DAG ) const { +JumpTableSDNode * N = cast < JumpTableSDNode > ( Op ) ; +return getAddr ( N , DAG ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/LowerOperation.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/LowerOperation.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c1958cdc181adf57d058f17448108d0fbf973dba --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/LowerOperation.cpp @@ -0,0 +1,60 @@ +SDValue PULPTargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { +if ( Op . getOpcode ( ) == ISD :: FRAMEADDR ) { +return LowerFrameIndex ( Op , DAG ) ; +} +if ( Op . getOpcode ( ) == ISD :: GlobalAddress ) { +return LowerGlobalAddress ( Op , DAG ) ; +} +if ( Op . getOpcode ( ) == ISD :: JumpTable ) { +return LowerJumpTable ( Op , DAG ) ; +} +if ( Op . getOpcode ( ) == ISD :: BlockAddress ) { +return lowerBlockAddress ( Op , DAG ) ; +} +if ( Op . getOpcode ( ) == ISD :: ConstantPool ) { +return lowerConstantPool ( Op , DAG ) ; +} +if ( Op . getOpcode ( ) == ISD :: GlobalTLSAddress ) { +return lowerGlobalTLSAddress ( Op , DAG ) ; +} +if ( Op . getOpcode ( ) == ISD :: SELECT ) { +return lowerSELECT ( Op , DAG ) ; +} +if ( Op . getOpcode ( ) == ISD :: VASTART ) { +return lowerVASTART ( Op , DAG ) ; +} +if ( Op . getOpcode ( ) == ISD :: RETURNADDR ) { +return lowerRETURNADDR ( Op , DAG ) ; +} +if ( Op . getOpcode ( ) == ISD :: SHL_PARTS ) { +return lowerShiftLeftParts ( Op , DAG ) ; +} +if ( Op . getOpcode ( ) == ISD :: SRA_PARTS ) { +return lowerShiftRightParts ( Op , DAG , true ) ; +} +if ( Op . getOpcode ( ) == ISD :: SRL_PARTS ) { +return lowerShiftRightParts ( Op , DAG , false ) ; +} +if ( Op . getOpcode ( ) == ISD :: INTRINSIC_WO_CHAIN ) { +return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; +} +if ( Op . getOpcode ( ) == ISD :: INTRINSIC_W_CHAIN ) { +return LowerINTRINSIC_W_CHAIN ( Op , DAG ) ; +} +if ( Op . getOpcode ( ) == ISD :: ANY_EXTEND ) { +return lowerVectorMaskExt ( Op , DAG , 1 ) ; +} +if ( Op . getOpcode ( ) == ISD :: ZERO_EXTEND ) { +return lowerVectorMaskExt ( Op , DAG , 1 ) ; +} +if ( Op . getOpcode ( ) == ISD :: SIGN_EXTEND ) { +return lowerVectorMaskExt ( Op , DAG , - 1 ) ; +} +if ( Op . getOpcode ( ) == ISD :: SPLAT_VECTOR ) { +return lowerSPLATVECTOR ( Op , DAG ) ; +} +if ( Op . getOpcode ( ) == ISD :: INSERT_VECTOR_ELT ) { +return lowerINSERT_VECTOR_ELT ( Op , DAG ) ; +} +report_fatal_error ( "unimplemented operand" ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/LowerRETURNADDR.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/LowerRETURNADDR.cpp new file mode 100644 index 0000000000000000000000000000000000000000..876718e14358a48083a74ca770d5015b38da7b75 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/LowerRETURNADDR.cpp @@ -0,0 +1,20 @@ +SDValue PULPTargetLowering :: lowerRETURNADDR ( SDValue Op , SelectionDAG & DAG ) const { +const PULPRegisterInfo & RI = * Subtarget . getRegisterInfo ( ) ; +MachineFunction & MF = DAG . getMachineFunction ( ) ; +MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; +MFI . setReturnAddressIsTaken ( true ) ; +int XLenInBytes = Subtarget . getZLen ( ) / 8 ; +if ( verifyReturnAddressArgumentIsConstant ( Op , DAG ) ) { +return SDValue ( ) ; +} +EVT VT = Op . getValueType ( ) ; +SDLoc DL ( Op ) ; +unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( 0 ) ) -> getZExtValue ( ) ; +if ( Depth ) { +int Off = - XLenInBytes ; +SDValue FrameAddr = lowerFRAMEADDR ( Op , DAG ) ; +SDValue Offset = DAG . getConstant ( Off , DL , VT ) ; +return DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , DAG . getNode ( ISD :: ADD , DL , VT , FrameAddr , Offset ) , MachinePointerInfo ( ) ) ; +} +return DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , Reg , XLenVT ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/LowerReturn.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/LowerReturn.cpp new file mode 100644 index 0000000000000000000000000000000000000000..949e6f2081755023b49e6db44fbb5261c2b8a195 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/LowerReturn.cpp @@ -0,0 +1,155 @@ +SDValue PULPTargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SDLoc & DL , SelectionDAG & DAG ) const { +report_fatal_error ( "VarArg not supported" ) ; +} +MachineFunction & MF = DAG . getMachineFunction ( ) ; +SmallVector < CCValAssign , 16 > RVLocs ; +CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; +CCInfo . AnalyzeReturn ( Outs , RetCC_PULP ) ; +if ( DAG . getMachineFunction ( ) . getRegInfo ( ) . liveout_empty ( ) ) { +for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) +if ( RVLocs [ i ] . isRegLoc ( ) ) { +DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ; +} +for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { +if ( RVLocs [ i ] . isRegLoc ( ) ) { +DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ; +} +} +} +if ( MF . getRegInfo ( ) . liveout_empty ( ) ) { +for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { +if ( RVLocs [ i ] . isRegLoc ( ) ) { +MF . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ; +} +} +} +SDValue Flag ; +analyzeOutputArgs ( CCInfo , Outs , CC_PULP ) ; +analyzeOutputArgs ( DAG . getMachineFunction ( ) , CCInfo , Outs , true , nullptr ) ; +SDValue Glue ; +SmallVector < SDValue , 4 > RetOps ( 1 , Chain ) ; +RetOps . push_back ( SDValue ( ) ) ; +for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { +SDValue Val = OutVals [ i ] ; +CCValAssign & VA = RVLocs [ i ] ; +SDValue ResValue = Outs [ i ] . Val ; +assert ( VA . isRegLoc ( ) && "Can only return in registers!" ) ; +if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) { +ResValue = DAG . getNode ( ISD :: SIGN_EXTEND , dl , VA . getLocVT ( ) , ResValue ) ; +} +if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) { +ResValue = DAG . getNode ( ISD :: ZERO_EXTEND , dl , VA . getLocVT ( ) , ResValue ) ; +} +if ( VA . getLocInfo ( ) == CCValAssign :: AExt ) { +ResValue = DAG . getNode ( ISD :: ANY_EXTEND , dl , VA . getLocVT ( ) , ResValue ) ; +} +Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; +Flag = Chain . getValue ( 1 ) ; +Glue = Chain . getValue ( 1 ) ; +RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; +bool IsF64OnPULP = VA . getLocVT ( ) == MVT :: i32 && VA . getValVT ( ) == MVT :: f64 ; +if ( IsF64OnPULP ) { +SDValue Split64 = DAG . getNode ( PULPISD :: BITCAST_TO_LOHI , DL , DAG . getVTList ( MVT :: i32 , MVT :: i32 ) , Val ) ; +SDValue Lo = Split64 . getValue ( 0 ) ; +SDValue Hi = Split64 . getValue ( 1 ) ; +Register RegLo = VA . getLocReg ( ) ; +assert ( RegLo < PULP :: R31 && "Invalid register pair" ) ; +Register RegHi = RegLo + 1 ; +Chain = DAG . getCopyToReg ( Chain , DL , RegLo , Lo , Glue ) ; +Glue = Chain . getValue ( 1 ) ; +RetOps . push_back ( DAG . getRegister ( RegLo , MVT :: i32 ) ) ; +Chain = DAG . getCopyToReg ( Chain , DL , RegHi , Hi , Glue ) ; +Glue = Chain . getValue ( 1 ) ; +RetOps . push_back ( DAG . getRegister ( RegHi , MVT :: i32 ) ) ; +} +if ( ! IsF64OnPULP ) { { +} +RetOps [ 0 ] = Chain ; +if ( Glue . getNode ( ) ) { +RetOps . push_back ( Glue ) ; +} +if ( DAG . getMachineFunction ( ) . getFunction ( ) . hasFnAttribute ( "interrupt" ) ) { +return DAG . getNode ( PULPISD :: NIR , DL , MVT :: Other , RetOps ) ; +} +return DAG . getNode ( PULPISD :: RET , DL , MVT :: Other , RetOps ) ; +if ( VA . getLocVT ( ) != MVT :: i32 ) { +Val = convertValVTToLocVT ( DAG , Val , VA , DL ) ; +Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Val , Glue ) ; +Glue = Chain . getValue ( 1 ) ; +RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; +} +if ( VA . getValVT ( ) != MVT :: f64 ) { +Val = convertValVTToLocVT ( DAG , Val , VA , DL ) ; +Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Val , Glue ) ; +Glue = Chain . getValue ( 1 ) ; +RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; +} +} +if ( DAG . getMachineFunction ( ) . getFunction ( ) . hasStructRetAttr ( ) ) { +MachineFunction & MF = DAG . getMachineFunction ( ) ; +PULPMachineFunctionInfo * PULPMFI = MF . getInfo < PULPMachineFunctionInfo > ( ) ; +Register Reg = PULPMFI -> getSRetReturnReg ( ) ; +Chain = DAG . getCopyToReg ( Chain , DL , PULP :: RV , Val , Flag ) ; +Flag = Chain . getValue ( 1 ) ; +RetOps . push_back ( DAG . getRegister ( PULP :: RV , getPointerTy ( DAG . getDataLayout ( ) ) ) ) ; +} +if ( MF . getFunction ( ) . hasStructRetAttr ( ) ) { +PULPMachineFunctionInfo * FuncInfo = MF . getInfo < PULPMachineFunctionInfo > ( ) ; +unsigned Reg = FuncInfo -> getSRetReturnReg ( ) ; +if ( ! Reg ) { +llvm_unreachable ( "sret virtual register not created in entry block" ) ; +} +SDValue Val = DAG . getCopyFromReg ( Chain , dl , Reg , getPointerTy ( DAG . getDataLayout ( ) ) ) ; +unsigned R12 = PULP :: R12 ; +Chain = DAG . getCopyToReg ( Chain , dl , R12 , Val , Flag ) ; +Flag = Chain . getValue ( 1 ) ; +RetOps . push_back ( DAG . getRegister ( R12 , getPointerTy ( DAG . getDataLayout ( ) ) ) ) ; +} +unsigned Opc = ( CallConv == CallingConv :: PULP_INTR ? PULPISD :: RETI_FLAG : PULPISD :: RET_FLAG ) ; +unsigned RetAddrOffset = 8 ; +if ( MF . getFunction ( ) -> hasStructRetAttr ( ) ) { +PULPMachineFunctionInfo * SFI = MF . getInfo < PULPMachineFunctionInfo > ( ) ; +PULPMachineFunctionInfo * FI = MF . getInfo < PULPMachineFunctionInfo > ( ) ; +if ( ! Reg ) { +llvm_unreachable ( "sret virtual register not created in the entry block" ) ; +} +Chain = DAG . getCopyToReg ( Chain , dl , PULP :: I0 , Val , Flag ) ; +Chain = DAG . getCopyToReg ( Chain , DL , PULP :: R0 , Val , Flag ) ; +Flag = Chain . getValue ( 1 ) ; +RetOps . push_back ( DAG . getRegister ( PULP :: I0 , getPointerTy ( ) ) ) ; +RetAddrOffset = 12 ; +if ( MF . getRegInfo ( ) . liveout_empty ( ) ) { +MF . getRegInfo ( ) . addLiveOut ( PULP :: R0 ) ; +} +} +RetOps [ 0 ] = Chain ; +unsigned Opc = PULPISD :: RET_FLAG ; +if ( DAG . getMachineFunction ( ) . getFunction ( ) -> hasStructRetAttr ( ) ) { +MachineFunction & MF = DAG . getMachineFunction ( ) ; +PULPFunctionInfo * PULPFI = MF . getInfo < PULPFunctionInfo > ( ) ; +unsigned Reg = PULPFI -> getSRetReturnReg ( ) ; +if ( ! Reg ) { +llvm_unreachable ( "sret virtual register not created in the entry block" ) ; +} +SDValue Val = DAG . getCopyFromReg ( Chain , dl , Reg , getPointerTy ( ) ) ; +Chain = DAG . getCopyToReg ( Chain , dl , PULP :: V0 , Val , Flag ) ; +Flag = Chain . getValue ( 1 ) ; +} +RetOps [ 1 ] = DAG . getConstant ( RetAddrOffset , MVT :: i32 ) ; +SDValue LinkReg = DAG . getRegister ( PULP :: LinkRegister , getPointerTy ( ) ) ; +if ( Flag . getNode ( ) ) { +RetOps . push_back ( Flag ) ; +return DAG . getNode ( PULPISD :: Ret , dl , MVT :: Other , Chain , DAG . getRegister ( PULP :: RA , MVT :: i32 ) , Flag ) ; +} +if ( Glue . getNode ( ) ) { +RetOps . push_back ( Glue ) ; +} +const Function & Func = DAG . getMachineFunction ( ) . getFunction ( ) ; +if ( Func . hasFnAttribute ( "interrupt" ) ) { +llvm_unreachable ( "interrupts not supported" ) ; +} +if ( ! Flag . getNode ( ) ) { +return DAG . getNode ( PULPISD :: Ret , dl , MVT :: Other , Chain , DAG . getRegister ( PULP :: RA , MVT :: i32 ) ) ; +return DAG . getNode ( T64ISD :: JRP , DL , MVT :: Other , Chain , LinkReg ) ; +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/LowerVASTART.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/LowerVASTART.cpp new file mode 100644 index 0000000000000000000000000000000000000000..dad3b3a138bcc4a400def849bfaf4bad94186f7f --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/LowerVASTART.cpp @@ -0,0 +1,8 @@ +SDValue PULPTargetLowering :: lowerVASTART ( SDValue Op , SelectionDAG & DAG ) const { +MachineFunction & MF = DAG . getMachineFunction ( ) ; +const PULPMachineFunctionInfo * FuncInfo = MF . getInfo < PULPMachineFunctionInfo > ( ) ; +SDLoc DL ( Op ) ; +SDValue FI = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , getPointerTy ( MF . getDataLayout ( ) ) ) ; +const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( 2 ) ) -> getValue ( ) ; +return DAG . getStore ( Op . getOperand ( 0 ) , DL , FI , Op . getOperand ( 1 ) , MachinePointerInfo ( SV ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/NodeType.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/NodeType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..16f1222fb7662f8a978a0205d7d36b3d76930d7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/NodeType.cpp @@ -0,0 +1,43 @@ +enum NodeType : unsigned { +FIRST_NUMBER = ISD :: BUILTIN_OP_END , +RET_FLAG , +URET_FLAG , +SRET_FLAG , +MRET_FLAG , +CALL , +SELECT_CC , +BuildPairF64 , +SplitF64 , +TAIL , +SLLW , +SRAW , +SRLW , +DIVW , +DIVUW , +REMUW , +ROLW , +RORW , +FSRW , +FSLW , +FMV_H_X , +FMV_X_ANYEXTH , +FMV_W_X_RV64 , +FMV_X_ANYEXTW_RV64 , +READ_CYCLE_WIDE , +GREVI , +GREVIW , +GORCI , +GORCIW , +VMV_X_S , +SPLAT_VECTOR_I64 , +READ_VLENB , +TRUNCATE_VECTOR , +VLEFF , +VLEFF_MASK , +VLSEGFF , +VLSEGFF_MASK , +READ_VL , +VSLIDEUP , +VSLIDEDOWN , +VID , +} ; \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/PerformDAGCombine.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/PerformDAGCombine.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3f851f61a473ef9fecef8944582258da8eead320 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/PerformDAGCombine.cpp @@ -0,0 +1,42 @@ +SDValue PULPTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { +if ( N -> getOpcode ( ) == PULPISD :: SplitF64 ) { +} +if ( N -> getOpcode ( ) == PULPISD :: SLLW ) { +} +if ( N -> getOpcode ( ) == PULPISD :: SRAW ) { +} +if ( N -> getOpcode ( ) == PULPISD :: SRLW ) { +} +if ( N -> getOpcode ( ) == PULPISD :: ROLW ) { +} +SelectionDAG & DAG = DCI . DAG ; +SDValue Val ; +if ( N -> getOpcode ( ) == PULPISD :: RORW ) { +} +if ( N -> getOpcode ( ) == PULPISD :: FSLW ) { +} +if ( N -> getOpcode ( ) == PULPISD :: FSRW ) { +} +if ( N -> getOpcode ( ) == PULPISD::GREVIW ) { +} +if ( N -> getOpcode ( ) == PULPISD :: GORCIW ) { +} +if ( N -> getOpcode ( ) == PULPISD::FMV_X_ANYEXTW_RV64 ) { +} +if ( N -> getOpcode ( ) == PULPISD::GREVI ) { +Val = performSETCCCombine ( N , DAG ) ; +} +if ( Val . getNode ( ) ) { +return Val ; +} +if ( N -> getOpcode ( ) == PULPISD :: GORCI ) { +return combineBSWAP ( N , DCI ) ; +} +if ( N -> getOpcode ( ) == PULPISD :: OR ) { +} +if ( N -> getOpcode ( ) == PULPISD :: SELECT_CC ) { +} +if ( N -> getOpcode ( ) == PULPISD :: SETCC ) { +} +return SDValue ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/ReplaceNodeResults.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/ReplaceNodeResults.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2580d701217217868ac91bb37c7ad4d800ad447e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/ReplaceNodeResults.cpp @@ -0,0 +1,211 @@ +void PULPTargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { +SDValue Res ; +if ( N -> getOpcode ( ) == ISD :: STRICT_FP_TO_SINT ) { +ExpandREAD_REGISTER ( N , Results , DAG ) ; +if ( Res . getNode ( ) ) { +Results . push_back ( Res ) ; +} +return ; +} +if ( N -> getOpcode ( ) == ISD :: STRICT_FP_TO_UINT ) { +Res = ExpandBITCAST ( N , DAG , Subtarget ) ; +if ( Res . getNode ( ) ) { +Results . push_back ( Res ) ; +} +return ; +} +if ( N -> getOpcode ( ) == ISD :: FP_TO_SINT ) { +ReplaceBITCASTResults ( N , Results , DAG ) ; +if ( Res . getNode ( ) ) { +Results . push_back ( Res ) ; +} +return ; +} +if ( N -> getOpcode ( ) == ISD :: FP_TO_UINT ) { +Results . push_back ( LowerVECREDUCE ( SDValue ( N , 0 ) , DAG ) ) ; +if ( Res . getNode ( ) ) { +Results . push_back ( Res ) ; +} +return ; +} +if ( N -> getOpcode ( ) == ISD :: READCYCLECOUNTER ) { +Results . push_back ( LowerVECREDUCE ( SDValue ( N , 0 ) , DAG ) ) ; +if ( Res . getNode ( ) ) { +Results . push_back ( Res ) ; +} +return ; +} +if ( N -> getOpcode ( ) == ISD :: ADD ) { +Results . push_back ( LowerVECREDUCE ( SDValue ( N , 0 ) , DAG ) ) ; +Res = LowerREM ( N , DAG ) ; +if ( Res . getNode ( ) ) { +Results . push_back ( Res ) ; +} +return ; +} +if ( N -> getOpcode ( ) == ISD :: SUB ) { +Results . push_back ( LowerVECREDUCE ( SDValue ( N , 0 ) , DAG ) ) ; +Res = LowerREM ( N , DAG ) ; +if ( Res . getNode ( ) ) { +Results . push_back ( Res ) ; +} +return ; +} +if ( N -> getOpcode ( ) == ISD :: FSHL ) { +Results . push_back ( LowerVECREDUCE ( SDValue ( N , 0 ) , DAG ) ) ; +Res = LowerDivRem ( SDValue ( N , 0 ) , DAG ) ; +Results . push_back ( Res . getValue ( 0 ) ) ; +Results . push_back ( Res . getValue ( 1 ) ) ; +return ; +} +if ( N -> getOpcode ( ) == ISD :: MUL ) { +Results . push_back ( LowerCTPOP ( SDValue ( N , 0 ) , DAG ) ) ; +Res = LowerDivRem ( SDValue ( N , 0 ) , DAG ) ; +Results . push_back ( Res . getValue ( 0 ) ) ; +Results . push_back ( Res . getValue ( 1 ) ) ; +return ; +} +if ( N -> getOpcode ( ) == ISD :: SHL ) { +ReplaceReductionResults ( N , Results , DAG , ISD :: ADD , PULPISD :: SADDV ) ; +Res = LowerSADDSUBSAT ( SDValue ( N , 0 ) , DAG , Subtarget ) ; +Results . push_back ( Res ) ; +return ; +} +if ( N -> getOpcode ( ) == ISD :: SRA ) { +ReplaceReductionResults ( N , Results , DAG , ISD :: ADD , PULPISD :: UADDV ) ; +Res = LowerSADDSUBSAT ( SDValue ( N , 0 ) , DAG , Subtarget ) ; +Results . push_back ( Res ) ; +return ; +} +if ( N -> getOpcode ( ) == ISD :: SRL ) { +ReplaceReductionResults ( N , Results , DAG , ISD :: SMIN , PULPISD :: SMINVV ) ; +ReplaceREADCYCLECOUNTER ( N , Results , DAG , Subtarget ) ; +Results . push_back ( Res ) ; +return ; +} +if ( N -> getOpcode ( ) == ISD :: ROTL ) { +ReplaceReductionResults ( N , Results , DAG , ISD :: UMINV , PULPISD :: UMINV ) ; +return ; +return ExpandDIV_Windows ( SDValue ( N , 0 ) , DAG , N -> getOpcode ( ) == ISD :: SDIV , Results ) ; +} +if ( N -> getOpcode ( ) == ISD :: ROTR ) { +return ; +} +if ( N -> getOpcode ( ) == ISD :: SDIV ) { +ReplaceReductionResults ( N , Results , DAG , ISD :: UMAX , PULPISD :: UMAXVV ) ; +return ; +} +if ( N -> getOpcode ( ) == ISD :: UDIV ) { +if ( N -> getOperand ( 0 ) . getValueType ( ) != MVT :: f128 ) { +return ; +} +if ( N -> getValueType ( 0 ) != MVT :: i64 ) { +return ; +} +libCall = RTLIB :: FPTOSINT_F128_I64 ; +Results . push_back ( LowerF128Op ( SDValue ( N , 0 ) , DAG , getLibcallName ( libCall ) , 1 ) ) ; +return ; +} +if ( N -> getOpcode ( ) == ISD :: UREM ) { +if ( ! LoadNode -> isVolatile ( ) ) { +return ; +} +if ( LoadNode -> getMemoryVT ( ) != MVT :: i128 ) { +return ; +} +SDValue Result = DAG . getMemIntrinsicNode ( PULPISD :: LDP , SDLoc ( N ) , DAG . getVTList ( { MVT :: i64 , MVT :: i64 , MVT :: Other } ) , { LoadNode -> getChain ( ) , LoadNode -> getBasePtr ( ) } , LoadNode -> getMemoryVT ( ) , LoadNode -> getMemOperand ( ) ) ; +SDValue Pair = DAG . getNode ( ISD :: BUILD_PAIR , SDLoc ( N ) , MVT :: i128 , Result . getValue ( 0 ) , Result . getValue ( 1 ) ) ; +Results . append ( { Pair , Result . getValue ( 2 ) } ) ; +if ( N -> getOperand ( 0 ) . getValueType ( ) != MVT :: f128 ) { +return ; +} +if ( N -> getValueType ( 0 ) != MVT :: i64 ) { +return ; +} +libCall = RTLIB :: FPTOUINT_F128_I64 ; +Results . push_back ( LowerF128Op ( SDValue ( N , 0 ) , DAG , getLibcallName ( libCall ) , 1 ) ) ; +return ; +} +if ( N -> getOpcode ( ) == ISD :: BITCAST ) { +ReplaceCMP_SWAP_128Results ( N , Results , DAG , Subtarget ) ; +ReplaceExtractSubVectorResults ( N , Results , DAG ) ; +SDValue Lo = DAG . getCopyFromReg ( N -> getOperand ( 0 ) , DL , PULP :: ASR23 , MVT :: i32 ) ; +SDValue Hi = DAG . getCopyFromReg ( Lo , DL , PULP :: G0 , MVT :: i32 ) ; +SDValue Ops [ ] = { Lo , Hi } ; +SDValue Pair = DAG . getNode ( ISD :: BUILD_PAIR , DL , MVT :: i64 , Ops ) ; +Results . push_back ( Pair ) ; +return ; +} +if ( N -> getOpcode ( ) == PULPISD::GREVI ) { +LoadSDNode * LoadNode = cast < LoadSDNode > ( N ) ; +if ( ! LoadNode -> isVolatile ( ) ) { +return ; +} +if ( LoadNode -> getMemoryVT ( ) != MVT :: i128 ) { +return ; +} +SDValue Result = DAG . getMemIntrinsicNode ( PULPISD :: LDP , SDLoc ( N ) , DAG . getVTList ( { MVT :: i64 , MVT :: i64 , MVT :: Other } ) , { LoadNode -> getChain ( ) , LoadNode -> getBasePtr ( ) } , LoadNode -> getMemoryVT ( ) , LoadNode -> getMemOperand ( ) ) ; +SDValue Pair = DAG . getNode ( ISD :: BUILD_PAIR , SDLoc ( N ) , MVT :: i128 , Result . getValue ( 0 ) , Result . getValue ( 1 ) ) ; +Results . append ( { Pair , Result . getValue ( 2 ) } ) ; +if ( N -> getValueType ( 0 ) != MVT :: f128 ) { +return ; +} +if ( N -> getOperand ( 0 ) . getValueType ( ) != MVT :: i64 ) { +return ; +} +libCall = RTLIB :: SINTTOFP_I64_F128 ; +Results . push_back ( LowerF128Op ( SDValue ( N , 0 ) , DAG , getLibcallName ( libCall ) , 1 ) ) ; +return ; +return ReplaceLongIntrinsic ( N , Results , DAG ) ; +} +if ( N -> getOpcode ( ) == PULPISD :: GORCI ) { +ReplaceExtractSubVectorResults ( N , Results , DAG ) ; +ReplaceLongIntrinsic ( N , Results , DAG ) ; +if ( N -> getValueType ( 0 ) != MVT :: f128 ) { +return ; +} +if ( N -> getOperand ( 0 ) . getValueType ( ) != MVT :: i64 ) { +return ; +} +libCall = RTLIB :: UINTTOFP_I64_F128 ; +Results . push_back ( LowerF128Op ( SDValue ( N , 0 ) , DAG , getLibcallName ( libCall ) , 1 ) ) ; +return ; +} +if ( N -> getOpcode ( ) == ISD :: BSWAP ) { +EVT VT = N -> getValueType ( 0 ) ; +ConstantSDNode * CN = cast < ConstantSDNode > ( N -> getOperand ( 0 ) ) ; +Intrinsic :: ID IntID = static_cast < Intrinsic :: ID > ( CN -> getZExtValue ( ) ) ; +if ( IntID == Intrinsic :: aarch64_sve_clasta_n ) { +SDLoc DL ( N ) ; +auto Op2 = DAG . getNode ( ISD :: ANY_EXTEND , DL , MVT :: i32 , N -> getOperand ( 2 ) ) ; +auto V = DAG . getNode ( PULPISD :: CLASTA_N , DL , MVT :: i32 , N -> getOperand ( 1 ) , Op2 , N -> getOperand ( 3 ) ) ; +Results . push_back ( DAG . getNode ( ISD :: TRUNCATE , DL , VT , V ) ) ; +return ; +} +SDLoc DL ( N ) ; +auto V = DAG . getNode ( PULPISD :: LASTA , DL , MVT :: i32 , N -> getOperand ( 1 ) , N -> getOperand ( 2 ) ) ; +Results . push_back ( DAG . getNode ( ISD :: TRUNCATE , DL , VT , V ) ) ; +return ; +SDLoc DL ( N ) ; +auto V = DAG . getNode ( PULPISD :: LASTB , DL , MVT :: i32 , N -> getOperand ( 1 ) , N -> getOperand ( 2 ) ) ; +Results . push_back ( DAG . getNode ( ISD :: TRUNCATE , DL , VT , V ) ) ; +return ; +LowerLOAD ( N , Results , DAG ) ; +if ( Res . getNode ( ) ) { +Results . push_back ( Res ) ; +} +LoadSDNode * Ld = cast < LoadSDNode > ( N ) ; +if ( Ld -> getValueType ( 0 ) != MVT :: i64 ) { +return ; +} +if ( Ld -> getMemoryVT ( ) != MVT :: i64 ) { +return ; +} +SDLoc DL ( N ) ; +SDValue LoadRes = DAG . getExtLoad ( Ld -> getExtensionType ( ) , DL , MVT :: v2i32 , Ld -> getChain ( ) , Ld -> getBasePtr ( ) , Ld -> getPointerInfo ( ) , MVT :: v2i32 , Ld -> getAlignment ( ) , Ld -> getMemOperand ( ) -> getFlags ( ) , Ld -> getAAInfo ( ) ) ; +SDValue Res = DAG . getNode ( ISD :: BITCAST , DL , MVT :: i64 , LoadRes ) ; +Results . push_back ( Res ) ; +Results . push_back ( LoadRes . getValue ( 1 ) ) ; +return ; +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/TargetLowering.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/TargetLowering.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e7411187ad154c0288f403b11ece3e58842fe129 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/TargetLowering.cpp @@ -0,0 +1,42 @@ +PULPTargetLowering :: PULPTargetLowering ( const TargetMachine & TM , const PULPSubtarget & STI ) : TargetLowering ( TM ) , Subtarget ( STI ) { +computeRegisterProperties ( STI . getRegisterInfo ( ) ) ; +setStackPointerRegisterToSaveRestore ( PULP :: X1 ) ; +for ( auto N : { ISD :: EXTLOAD , ISD :: SEXTLOAD , ISD :: ZEXTLOAD } ) { +} +setBooleanContents ( ZeroOrOneBooleanContent ) ; +addRegisterClass ( MVT :: i32 , & PULP :: GPRRegClass ) ; +TRI = STI . getRegisterInfo ( ) ; +computeRegisterProperties ( TRI ) ; +auto * RegInfo = Subtarget . getRegisterInfo ( ) ; +setBooleanVectorContents ( ZeroOrNegativeOneBooleanContent ) ; +setBooleanContents ( ZeroOrOneBooleanContent , ZeroOrNegativeOneBooleanContent ) ; +} +} +for ( auto CC : FPCCToExtend ) { +setLoadExtAction ( ISD :: SEXTLOAD , VT , MVT :: i1 , Promote ) ; +setLoadExtAction ( ISD :: ZEXTLOAD , VT , MVT :: i1 , Promote ) ; +if ( F16VT . isValid ( ) ) { +} +} +if ( Subtarget . atLeastM68020 ( ) ) { +} +setBooleanContents ( ZeroOrOneBooleanContent ) ; +setMinimumJumpTableEntries ( INT_MAX ) ; +setCondCodeAction ( CC , VT , Expand ) ; +computeRegisterProperties ( STI . getRegisterInfo ( ) ) ; +setBooleanContents ( UndefinedBooleanContent ) ; +setBooleanVectorContents ( ZeroOrNegativeOneBooleanContent ) ; +setMaxAtomicSizeInBitsSupported ( 0 ) ; +setStackPointerRegisterToSaveRestore ( PULP :: R14 ) ; +const Align FunctionAlignment ( 2 ) ; +setStackPointerRegisterToSaveRestore ( PULP :: R3 ) ; +setMinFunctionAlignment ( FunctionAlignment ) ; +setSchedulingPreference ( Sched :: Source ) ; +setJumpIsExpensive ( true ) ; +setLibcallCallingConv ( static_cast < RTLIB :: Libcall > ( I ) , CallingConv :: Fast ) ; +setBooleanContents ( ZeroOrOneBooleanContent ) ; +computeRegisterProperties ( ) ; +computeRegisterProperties ( STI . getRegisterInfo ( ) ) ; +setMinFunctionAlignment ( Align :: Constant < 2 > ( ) ) ; +setStackPointerRegisterToSaveRestore ( ABI . IsN64 ( ) ? PULP :: SP_64 : PULP :: SP ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/allowsMisalignedMemoryAccesses.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/allowsMisalignedMemoryAccesses.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e5adec0ac0cfdef9a2c0cd4f5dfb2a7a871f2b87 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/allowsMisalignedMemoryAccesses.cpp @@ -0,0 +1,9 @@ +bool PULPTargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned AddrSpace = 0 , unsigned Align = 1 , MachineMemOperand :: Flags Flags = MachineMemOperand :: MONone , bool * Fast = nullptr ) const { +if ( Subtarget . hasPULPExtV2 ( ) ) { +if ( Fast ) { +* Fast = false ; +} +return true ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/analyzeInputArgs.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/analyzeInputArgs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6ede24b6a0b7177a524e4ae524b7fd78f4ab04f3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/analyzeInputArgs.cpp @@ -0,0 +1,16 @@ +void PULPTargetLowering :: analyzeInputArgs ( MachineFunction & MF , CCState & CCInfo , const SmallVectorImpl < ISD :: InputArg > & Ins , bool IsRet ) const { +unsigned NumArgs = Ins . size ( ) ; +FunctionType * FType = MF . getFunction ( ) . getFunctionType ( ) ; +for ( unsigned i = 0 ; i != NumArgs ; ++ i ) { +MVT ArgVT = Ins [ i ] . VT ; +ISD :: ArgFlagsTy ArgFlags = Ins [ i ] . Flags ; +if ( IsRet ) { +} +if ( ! IsRet ) { +if ( CC_ ( i , ArgVT , ArgVT , CCValAssign :: Full , ArgFlags , CCInfo ) ) { +} +} +if ( Fn ( i , ArgVT , CCValAssign :: Full , CCInfo ) ) { +} +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/analyzeOutputArgs.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/analyzeOutputArgs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ca0e3c66bc1bab448f440282a348fa1eb7a9db07 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/analyzeOutputArgs.cpp @@ -0,0 +1,15 @@ +void PULPTargetLowering :: analyzeOutputArgs ( MachineFunction & MF , CCState & CCInfo , const SmallVectorImpl < ISD :: OutputArg > & Outs , bool IsRet , CallLoweringInfo * CLI ) const { +unsigned NumArgs = Outs . size ( ) ; +for ( unsigned i = 0 ; i != NumArgs ; i ++ ) { +MVT ArgVT = Outs [ i ] . VT ; +ISD :: ArgFlagsTy ArgFlags = Outs [ i ] . Flags ; +if ( IsRet ) { +if ( RetCC_ ( i , ArgVT , ArgVT , CCValAssign :: Full , ArgFlags , CCInfo ) ) { +} +} +if ( ! IsRet ) { +if ( CC_ ( i , ArgVT , ArgVT , CCValAssign :: Full , ArgFlags , CCInfo ) ) { +} +} +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/computeKnownBitsForTargetNode.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/computeKnownBitsForTargetNode.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c952ca87093d5b444e1b852127d1527f83cf2767 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/computeKnownBitsForTargetNode.cpp @@ -0,0 +1,26 @@ +void PULPTargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , KnownBits & Known , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { +KnownZero = KnownOne = APInt ( KnownOne . getBitWidth ( ) , 0 ) ; +APInt KnownZero2 ; +APInt KnownOne2 ; +unsigned BitWidth = Known . getBitWidth ( ) ; +unsigned Opc = Op . getOpcode ( ) ; +EVT VT = Op . getValueType ( ) ; +Known . resetAll ( ) ; +if ( Op . getOpcode ( ) == PULPISD :: REMUW ) { +Known . Zero . setBitsFrom ( 1 ) ; +} +if ( Op . getOpcode ( ) == PULPISD :: DIVUW ) { +KnownBits Known2 ; +DAG . computeKnownBits ( Op . getOperand ( 0 ) , Known , Depth + 1 ) ; +DAG . computeKnownBits ( Op . getOperand ( 1 ) , Known2 , Depth + 1 ) ; +Known . Zero = Known . Zero & Known2 . Zero ; +Known . One = Known . One & Known2 . One ; +Known . Zero . setBitsFrom ( 1 ) ; +} +if ( Op . getOpcode ( ) == PULPISD :: READ_VLENB ) { +if ( Op . getResNo ( ) == 0 ) { +return ; +} +Known . Zero . setBitsFrom ( 1 ) ; +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/convertSelectOfConstantsToMath.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/convertSelectOfConstantsToMath.cpp new file mode 100644 index 0000000000000000000000000000000000000000..51269f50ce2e5fc7c824cfa4100384d706db162c --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/convertSelectOfConstantsToMath.cpp @@ -0,0 +1,3 @@ +bool convertSelectOfConstantsToMath ( EVT VT ) const override { +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/convertSetCCLogicToBitwiseLogic.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/convertSetCCLogicToBitwiseLogic.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3178e743bf8e6612f2326e0390c95e0ed53bbb73 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/convertSetCCLogicToBitwiseLogic.cpp @@ -0,0 +1,3 @@ +bool convertSetCCLogicToBitwiseLogic ( EVT VT ) const override { +return VT . isScalarInteger ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/decomposeMulByConstant.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/decomposeMulByConstant.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8bfb242c00aa2d97a251bd7e786de70ab66c5eb2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/decomposeMulByConstant.cpp @@ -0,0 +1,18 @@ +bool PULPTargetLowering :: decomposeMulByConstant ( LLVMContext & Context , EVT VT , SDValue C ) const { +if ( ! VT . isScalarInteger ( ) ) { +return false ; +} +if ( auto * ConstNode = dyn_cast < ConstantSDNode > ( C . getNode ( ) ) ) { +if ( ! ConstNode -> getAPIntValue ( ) . isSignedIntN ( 64 ) ) { +return false ; +} +int64_t Imm = ConstNode -> getSExtValue ( ) ; +unsigned Shift = countTrailingZeros < uint64_t > ( Imm ) ; +Imm = Imm >> Shift ; +if ( isInt < 16 > ( Imm ) ) { +return false ; +} +uint64_t UImm = static_cast < uint64_t > ( Imm ) ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/emitLeadingFence.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/emitLeadingFence.cpp new file mode 100644 index 0000000000000000000000000000000000000000..82fd66d2e78b6bdb5284b3af82a5cc398902fe36 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/emitLeadingFence.cpp @@ -0,0 +1,20 @@ +Instruction * PULPTargetLowering :: emitLeadingFence ( IRBuilder < > & Builder , Instruction * Inst , AtomicOrdering Ord ) const { +return nullptr ; +return nullptr ; +if ( Ord == AtomicOrdering :: SequentiallyConsistent ) { +if ( ! Inst -> hasAtomicStore ( ) ) { +return nullptr ; +} +} +if ( Ord == AtomicOrdering :: Release ) { +return makeDMB ( Builder , PULP_MB :: ISHST ) ; +return makeDMB ( Builder , PULP_MB :: ISH ) ; +} +return makeDMB ( Builder , PULP_MB :: ISHST ) ; +return makeDMB ( Builder , PULP_MB :: ISH ) ; +return callIntrinsic ( Builder , Intrinsic :: ppc_sync ) ; +if ( isAtLeastRelease ( Ord ) ) { +return callIntrinsic ( Builder , Intrinsic :: ppc_lwsync ) ; +} +return nullptr ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/emitMaskedAtomicCmpXchgIntrinsic.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/emitMaskedAtomicCmpXchgIntrinsic.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a97c828a558f2787940a9716a5aba05e155b3f5b --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/emitMaskedAtomicCmpXchgIntrinsic.cpp @@ -0,0 +1,19 @@ +Value * PULPTargetLowering :: emitMaskedAtomicCmpXchgIntrinsic ( IRBuilder < > & Builder , AtomicCmpXchgInst * CI , Value * AlignedAddr , Value * CmpVal , Value * NewVal , Value * Mask , AtomicOrdering Ord ) const { +Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; +Type * ValTy = CmpVal -> getType ( ) ; +Function * IntCmpXchg = Intrinsic :: getDeclaration ( M , Intrinsic :: ppc_cmpxchg_i128 ) ; +Type * Int64Ty = Type :: getInt64Ty ( M -> getContext ( ) ) ; +Value * CmpLo = Builder . CreateTrunc ( CmpVal , Int64Ty , "cmp_lo" ) ; +Value * CmpHi = Builder . CreateTrunc ( Builder . CreateLShr ( CmpVal , 64 ) , Int64Ty , "cmp_hi" ) ; +Value * NewLo = Builder . CreateTrunc ( NewVal , Int64Ty , "new_lo" ) ; +Value * NewHi = Builder . CreateTrunc ( Builder . CreateLShr ( NewVal , 64 ) , Int64Ty , "new_hi" ) ; +Value * Addr = Builder . CreateBitCast ( AlignedAddr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; +emitLeadingFence ( Builder , CI , Ord ) ; +Value * LoHi = Builder . CreateCall ( IntCmpXchg , { Addr , CmpLo , CmpHi , NewLo , NewHi } ) ; +emitTrailingFence ( Builder , CI , Ord ) ; +Value * Lo = Builder . CreateExtractValue ( LoHi , 0 , "lo" ) ; +Value * Hi = Builder . CreateExtractValue ( LoHi , 1 , "hi" ) ; +Lo = Builder . CreateZExt ( Lo , ValTy , "lo64" ) ; +Hi = Builder . CreateZExt ( Hi , ValTy , "hi64" ) ; +return Builder . CreateOr ( Lo , Builder . CreateShl ( Hi , ConstantInt :: get ( ValTy , 64 ) ) , "val64" ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/emitMaskedAtomicRMWIntrinsic.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/emitMaskedAtomicRMWIntrinsic.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b26de04093385e3d926768f24e72b36c50b1ce4e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/emitMaskedAtomicRMWIntrinsic.cpp @@ -0,0 +1,15 @@ +Value * PULPTargetLowering :: emitMaskedAtomicRMWIntrinsic ( IRBuilder < > & Builder , AtomicRMWInst * AI , Value * AlignedAddr , Value * Incr , Value * Mask , Value * ShiftAmt , AtomicOrdering Ord ) const { +Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; +Type * ValTy = AlignedAddr -> getType ( ) -> getPointerElementType ( ) ; +Function * RMW = Intrinsic :: getDeclaration ( M , getIntrinsicForAtomicRMWBinOp128 ( AI -> getOperation ( ) ) ) ; +Type * Int64Ty = Type :: getInt64Ty ( M -> getContext ( ) ) ; +Value * IncrLo = Builder . CreateTrunc ( Incr , Int64Ty , "incr_lo" ) ; +Value * IncrHi = Builder . CreateTrunc ( Builder . CreateLShr ( Incr , 64 ) , Int64Ty , "incr_hi" ) ; +Value * Addr = Builder . CreateBitCast ( AlignedAddr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; +Value * LoHi = Builder . CreateCall ( RMW , { Addr , IncrLo , IncrHi } ) ; +Value * Lo = Builder . CreateExtractValue ( LoHi , 0 , "lo" ) ; +Value * Hi = Builder . CreateExtractValue ( LoHi , 1 , "hi" ) ; +Lo = Builder . CreateZExt ( Lo , ValTy , "lo64" ) ; +Hi = Builder . CreateZExt ( Hi , ValTy , "hi64" ) ; +return Builder . CreateOr ( Lo , Builder . CreateShl ( Hi , ConstantInt :: get ( ValTy , 64 ) ) , "val64" ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/emitTrailingFence.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/emitTrailingFence.cpp new file mode 100644 index 0000000000000000000000000000000000000000..996a8872d79d74a075d6821698276a10fab9b465 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/emitTrailingFence.cpp @@ -0,0 +1,14 @@ +Instruction * PULPTargetLowering :: emitTrailingFence ( IRBuilder < > & Builder , Instruction * Inst , AtomicOrdering Ord ) const { +if ( Ord == AtomicOrdering :: AcquireRelease ) { +if ( Ord == AtomicOrdering :: SequentiallyConsistent ) { +if ( Ord == AtomicOrdering :: Monotonic ) { +return nullptr ; +return nullptr ; +if ( isAcquireOrStronger ( Ord ) ) { +if ( isa < LoadInst > ( Inst ) ) { +return Builder . CreateCall ( Intrinsic :: getDeclaration ( Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) , Intrinsic :: ppc_cfence , { Inst -> getType ( ) } ) , { Inst } ) ; +} +} +return callIntrinsic ( Builder , Intrinsic :: ppc_lwsync ) ; +return nullptr ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/getAddr.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/getAddr.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ccf6f5e31521de6add25f9beddcadca47c2a2e53 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/getAddr.cpp @@ -0,0 +1,20 @@ +template < class NodeTy > SDValue PULPTargetLowering :: getAddr ( NodeTy * N , SelectionDAG & DAG , bool IsLocal ) const { +SDLoc DL ( N ) ; +EVT Ty = getPointerTy ( DAG . getDataLayout ( ) ) ; +unsigned Flag = PULPII :: MO_None ; +if ( isPositionIndependent ( ) ) { +SDValue GPReg = DAG . getRegister ( PULP :: GP_REG , MVT :: i32 ) ; +SDValue Wrapper = DAG . getNode ( PULPISD :: GOT_ADDR , DL , Ty , GPReg , getTargetNode ( N , Ty , DAG , PULP :: MO_GOT ) ) ; +return DAG . getLoad ( Ty , DL , DAG . getEntryNode ( ) , Wrapper , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) ) ; +} +SDValue TV = getTargetNode ( N , DL , Ty , DAG , Flag ) ; +if ( ! isPositionIndependent ( ) ) { +SDValue Hi = getTargetNode ( N , Ty , DAG , PULP :: MO_ABS_HI ) ; +SDValue Lo = getTargetNode ( N , Ty , DAG , PULP :: MO_ABS_LO ) ; +SDValue MoveHi = DAG . getNode ( PULPISD :: MOVEHI , DL , MVT :: i32 , Hi ) ; +} +if ( IsLocal ) { +DAG . getNode ( ISD :: ADD , DL , Ty , { DAG . getGLOBAL_OFFSET_TABLE ( Ty ) , Addr } ) ; +} +return DAG . getLoad ( Ty , DL , DAG . getEntryNode ( ) , Result , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/getConstraintType.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/getConstraintType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6ed4dbe58daa41ec565f9a05e745f22c291e7f69 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/getConstraintType.cpp @@ -0,0 +1,20 @@ +PULPTargetLowering :: ConstraintType PULPTargetLowering :: getConstraintType ( StringRef Constraint ) const { +if ( Constraint . size ( ) == 1 ) { +if ( Constraint [ 0 ] == 'f' ) { +return C_RegisterClass ; +} +if ( Constraint [ 0 ] == 'I' ) { +return C_Immediate ; +} +if ( Constraint [ 0 ] == 'J' ) { +return C_Immediate ; +} +if ( Constraint [ 0 ] == 'K' ) { +return C_Immediate ; +} +if ( Constraint [ 0 ] == 'A' ) { +return C_Memory ; +} +} +return TargetLowering :: getConstraintType ( Constraint ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/getDynamicTLSAddr.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/getDynamicTLSAddr.cpp new file mode 100644 index 0000000000000000000000000000000000000000..90e5bb50f8b4ba50d9d99116a50cefd9b24f7ebf --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/getDynamicTLSAddr.cpp @@ -0,0 +1,19 @@ +SDValue PULPTargetLowering :: getDynamicTLSAddr ( GlobalAddressSDNode * N , SelectionDAG & DAG ) const { +MachineFunction & MF = DAG . getMachineFunction ( ) ; +PULPMachineFunctionInfo * CFI = MF . getInfo < PULPMachineFunctionInfo > ( ) ; +unsigned PULPPCLabelIndex = CFI -> createPICLabelUId ( ) ; +SDLoc DL ( N ) ; +EVT Ty = getPointerTy ( DAG . getDataLayout ( ) ) ; +IntegerType * CallTy = Type :: getIntNTy ( * DAG . getContext ( ) , Ty . getSizeInBits ( ) ) ; +SDValue PICLabel = DAG . getTargetConstant ( PULPPCLabelIndex , DL , MVT :: i32 ) ; +SDValue Addr = DAG . getTargetGlobalAddress ( GV , DL , Ty , 0 , 0 ) ; +SDValue Load = SDValue ( DAG . getMachineNode ( PULP :: PseudoLA_TLS_GD , DL , Ty , Addr ) , 0 ) ; +ArgListTy Args ; +ArgListEntry Entry ; +Entry . Node = Load ; +Entry . Ty = CallTy ; +Args . push_back ( Entry ) ; +TargetLowering :: CallLoweringInfo CLI ( DAG ) ; +CLI . setDebugLoc ( DL ) . setChain ( DAG . getEntryNode ( ) ) . setLibCallee ( CallingConv :: C , CallTy , DAG . getExternalSymbol ( "__tls_get_addr" , Ty ) , std :: move ( Args ) ) ; +return LowerCallTo ( CLI ) . first ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/getExceptionPointerRegister.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/getExceptionPointerRegister.cpp new file mode 100644 index 0000000000000000000000000000000000000000..11862fe12810c0835ec468000a37f5a56f96e7d6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/getExceptionPointerRegister.cpp @@ -0,0 +1,3 @@ +Register PULPTargetLowering :: getExceptionPointerRegister ( const Constant * PersonalityFn ) const { +return PULP :: X10 ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/getExceptionSelectorRegister.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/getExceptionSelectorRegister.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1c77af1175724813214262e456457fae52384678 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/getExceptionSelectorRegister.cpp @@ -0,0 +1,3 @@ +Register PULPTargetLowering :: getExceptionSelectorRegister ( const Constant * PersonalityFn ) const { +return PULP :: X11 ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/getExtendForAtomicCmpSwapArg.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/getExtendForAtomicCmpSwapArg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..38de26de656308f961676867af71fc387570f00a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/getExtendForAtomicCmpSwapArg.cpp @@ -0,0 +1,3 @@ +ISD :: NodeType getExtendForAtomicCmpSwapArg ( ) const override { +return ISD :: SIGN_EXTEND ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/getExtendForAtomicOps.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/getExtendForAtomicOps.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b9c2d6c3acd41ab5253583248f7de9c051d4481b --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/getExtendForAtomicOps.cpp @@ -0,0 +1,3 @@ +ISD :: NodeType getExtendForAtomicOps ( ) const override { +return ISD :: SIGN_EXTEND ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/getInlineAsmMemConstraint.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/getInlineAsmMemConstraint.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a0a3fed08cef4df7c751a7bb65a19c3f91d597d5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/getInlineAsmMemConstraint.cpp @@ -0,0 +1,8 @@ +unsigned PULPTargetLowering :: getInlineAsmMemConstraint ( StringRef ConstraintCode ) const { +if ( ConstraintCode . size ( ) == 1 ) { +if ( ConstraintCode [ 0 ] == 'A' ) { +return InlineAsm :: Constraint_A ; +} +} +return TargetLowering :: getInlineAsmMemConstraint ( ConstraintCode ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/getPointerMemTy.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/getPointerMemTy.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ae1e522b40bc5ebbd0e271791e66de2e803983d3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/getPointerMemTy.cpp @@ -0,0 +1,6 @@ +MVT PULPTargetLowering :: getPointerMemTy ( const DataLayout & DL , uint32_t AS ) const { +if ( AS == UINT32_MAX ) { +AS = 0 ; +} +return MVT :: getIntegerVT ( AS ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/getPointerTy.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/getPointerTy.cpp new file mode 100644 index 0000000000000000000000000000000000000000..76ae0fbe4ae7e037459a193b12d6016c4812e9b0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/getPointerTy.cpp @@ -0,0 +1,6 @@ +MVT PULPTargetLowering :: getPointerTy ( const DataLayout & DL , uint32_t AS ) const { +if ( AS == UINT32_MAX ) { +AS = 0 ; +} +return MVT :: getIntegerVT ( AS ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/getPostIndexedAddressParts.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/getPostIndexedAddressParts.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1b11f1ef3981c52124fa7515356887f1f2c6aa30 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/getPostIndexedAddressParts.cpp @@ -0,0 +1,103 @@ +bool PULPTargetLowering :: getPostIndexedAddressParts ( SDNode * N , SDNode * Op , SDValue & Base , SDValue & Offset , ISD :: MemIndexedMode & AM , SelectionDAG & DAG ) const { +EVT VT ; +SDValue Ptr ; +if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { +VT = LD -> getMemoryVT ( ) ; +Ptr = LD -> getBasePtr ( ) ; +bool IsInc ; +if ( ! getIndexedAddressParts ( Op , Base , Offset , AM , IsInc , DAG ) ) { +return false ; +} +if ( Ptr != Base ) { +return false ; +} +AM = IsInc ? ISD :: POST_INC : ISD :: POST_DEC ; +return true ; +} +if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { +VT = ST -> getMemoryVT ( ) ; +Ptr = ST -> getBasePtr ( ) ; +bool IsInc ; +if ( ! getIndexedAddressParts ( Op , Base , Offset , AM , IsInc , DAG ) ) { +return false ; +} +if ( Ptr != Base ) { +return false ; +} +AM = IsInc ? ISD :: POST_INC : ISD :: POST_DEC ; +return true ; +} +VT = LD -> getMemoryVT ( ) ; +if ( LD -> getExtensionType ( ) != ISD :: NON_EXTLOAD ) { +return false ; +} +if ( VT != MVT :: i8 && VT != MVT :: i16 ) { +return false ; +} +if ( Op -> getOpcode ( ) != ISD :: ADD && Op -> getOpcode ( ) != ISD :: SUB ) { +return false ; +} +if ( const ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( Op -> getOperand ( 1 ) ) ) { +int RHSC = RHS -> getSExtValue ( ) ; +if ( Op -> getOpcode ( ) == ISD :: SUB ) { +RHSC = - RHSC ; +} +if ( ( VT == MVT :: i16 && RHSC != 2 ) || ( VT == MVT :: i8 && RHSC != 1 ) ) { +return false ; +} +Base = Op -> getOperand ( 0 ) ; +AM = ISD :: POST_INC ; +return true ; +} +} +if ( const StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { +VT = ST -> getMemoryVT ( ) ; +if ( PULP :: isProgramMemoryAccess ( ST ) ) { +return false ; +} +if ( VT != MVT :: i8 && VT != MVT :: i16 ) { +return false ; +} +if ( Op -> getOpcode ( ) != ISD :: ADD && Op -> getOpcode ( ) != ISD :: SUB ) { +return false ; +} +if ( const ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( Op -> getOperand ( 1 ) ) ) { +int RHSC = RHS -> getSExtValue ( ) ; +if ( Op -> getOpcode ( ) == ISD :: SUB ) { +RHSC = - RHSC ; +} +if ( ( VT == MVT :: i16 && RHSC != 2 ) || ( VT == MVT :: i8 && RHSC != 1 ) ) { +return false ; +} +Base = Op -> getOperand ( 0 ) ; +AM = ISD :: POST_INC ; +return true ; +} +} +LoadSDNode * LD = cast < LoadSDNode > ( N ) ; +if ( LD -> getExtensionType ( ) != ISD :: NON_EXTLOAD ) { +return false ; +} +EVT VT = LD -> getMemoryVT ( ) ; +if ( VT != MVT :: i8 && VT != MVT :: i16 ) { +return false ; +} +if ( Op -> getOpcode ( ) == ISD :: ADD ) { +AM = ISD :: POST_INC ; +Base = Op -> getOperand ( 0 ) ; +Offset = DAG . getConstant ( RHSC , VT ) ; +if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( Op -> getOperand ( 1 ) ) ) { +uint64_t RHSC = RHS -> getZExtValue ( ) ; +if ( VT == MVT :: i16 ) { +if ( RHSC != 2 ) { +return false ; +} +} +return false ; +} +} +return true ; +} +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/getRegForInlineAsmConstraint.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/getRegForInlineAsmConstraint.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c4981bc936dd3c96c80cbadc102f1442d24acfc6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/getRegForInlineAsmConstraint.cpp @@ -0,0 +1,326 @@ +std :: pair < unsigned , const TargetRegisterClass * > PULPTargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { +if ( Constraint . size ( ) == 1 ) { +if ( Constraint [ 0 ] == 'r' ) { +return std :: make_pair ( 0U , & PULP :: GPRRegClass ) ; +} +if ( Constraint [ 0 ] == 'f' ) { +if ( Subtarget . hasStdExtF ( ) ) { +if ( VT == MVT :: f32 ) { +return std :: make_pair ( 0U , & PULP :: FPR32RegClass ) ; +} +} +if ( Subtarget . hasStdExtD ( ) ) { +if ( VT == MVT :: f64 ) { +return std :: make_pair ( 0U , & PULP :: FPR64RegClass ) ; +} +} +} +} +return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; +unsigned XRegFromAlias = PULP :: NoRegister ; +if ( Constraint . lower ( ) == "{zero}" ) { +XRegFromAlias = PULP :: X0 ; +} +if ( Constraint . lower ( ) == "{ra}" ) { +XRegFromAlias = PULP :: X1 ; +} +if ( Constraint . lower ( ) == "{sp}" ) { +XRegFromAlias = PULP :: X2 ; +} +if ( Constraint . lower ( ) == "{gp}" ) { +XRegFromAlias = PULP :: X3 ; +} +if ( Constraint . lower ( ) == "{tp}" ) { +XRegFromAlias = PULP :: X4 ; +} +if ( Constraint . lower ( ) == "{t0}" ) { +XRegFromAlias = PULP :: X5 ; +} +if ( Constraint . lower ( ) == "{t1}" ) { +XRegFromAlias = PULP :: X6 ; +} +if ( Constraint . lower ( ) == "{t2}" ) { +XRegFromAlias = PULP :: X7 ; +} +if ( Constraint . lower ( ) == "{s0}" ) { +XRegFromAlias = PULP :: X8 ; +} +if ( Constraint . lower ( ) == "{fp}" ) { +XRegFromAlias = PULP :: X8 ; +} +if ( Constraint . lower ( ) == "{s1}" ) { +XRegFromAlias = PULP :: X9 ; +} +if ( Constraint . lower ( ) == "{a0}" ) { +XRegFromAlias = PULP :: X10 ; +} +if ( Constraint . lower ( ) == "{a1}" ) { +XRegFromAlias = PULP :: X11 ; +} +if ( Constraint . lower ( ) == "{a2}" ) { +XRegFromAlias = PULP :: X12 ; +} +if ( Constraint . lower ( ) == "{a3}" ) { +XRegFromAlias = PULP :: X13 ; +} +if ( Constraint . lower ( ) == "{a4}" ) { +XRegFromAlias = PULP :: X14 ; +} +if ( Constraint . lower ( ) == "{a5}" ) { +XRegFromAlias = PULP :: X15 ; +} +if ( Constraint . lower ( ) == "{a6}" ) { +XRegFromAlias = PULP :: X16 ; +} +if ( Constraint . lower ( ) == "{a7}" ) { +XRegFromAlias = PULP :: X17 ; +} +if ( Constraint . lower ( ) == "{s2}" ) { +XRegFromAlias = PULP :: X18 ; +} +if ( Constraint . lower ( ) == "{s3}" ) { +XRegFromAlias = PULP :: X19 ; +} +if ( Constraint . lower ( ) == "{s4}" ) { +XRegFromAlias = PULP :: X20 ; +} +if ( Constraint . lower ( ) == "{s5}" ) { +XRegFromAlias = PULP :: X21 ; +} +if ( Constraint . lower ( ) == "{s6}" ) { +XRegFromAlias = PULP :: X22 ; +} +if ( Constraint . lower ( ) == "{s7}" ) { +XRegFromAlias = PULP :: X23 ; +} +if ( Constraint . lower ( ) == "{s8}" ) { +XRegFromAlias = PULP :: X24 ; +} +if ( Constraint . lower ( ) == "{s9}" ) { +XRegFromAlias = PULP :: X25 ; +} +if ( Constraint . lower ( ) == "{s10}" ) { +XRegFromAlias = PULP :: X26 ; +} +if ( Constraint . lower ( ) == "{s11}" ) { +XRegFromAlias = PULP :: X27 ; +} +if ( Constraint . lower ( ) == "{t3}" ) { +XRegFromAlias = PULP :: X28 ; +} +if ( Constraint . lower ( ) == "{t4}" ) { +XRegFromAlias = PULP :: X29 ; +} +if ( Constraint . lower ( ) == "{t5}" ) { +XRegFromAlias = PULP :: X30 ; +} +if ( Constraint . lower ( ) == "{t6}" ) { +XRegFromAlias = PULP :: X31 ; +} +if ( XRegFromAlias != PULP :: NoRegister ) { +return std :: make_pair ( XRegFromAlias , & PULP :: GPRRegClass ) ; +} +if ( Subtarget . hasStdExtF ( ) ) { +unsigned FReg = PULP :: NoRegister ; +if ( Constraint . lower ( ) == "{f0}" ) { +FReg = PULP :: F0_F ; +} +if ( Constraint . lower ( ) == "{ft0}" ) { +FReg = PULP :: F0_F ; +} +if ( Constraint . lower ( ) == "{f1}" ) { +FReg = PULP :: F1_F ; +} +if ( Constraint . lower ( ) == "{ft1}" ) { +FReg = PULP :: F1_F ; +} +if ( Constraint . lower ( ) == "{f2}" ) { +FReg = PULP :: F2_F ; +} +if ( Constraint . lower ( ) == "{ft2}" ) { +FReg = PULP :: F2_F ; +} +if ( Constraint . lower ( ) == "{f3}" ) { +FReg = PULP :: F3_F ; +} +if ( Constraint . lower ( ) == "{ft3}" ) { +FReg = PULP :: F3_F ; +} +if ( Constraint . lower ( ) == "{f4}" ) { +FReg = PULP :: F4_F ; +} +if ( Constraint . lower ( ) == "{ft4}" ) { +FReg = PULP :: F4_F ; +} +if ( Constraint . lower ( ) == "{f5}" ) { +FReg = PULP :: F5_F ; +} +if ( Constraint . lower ( ) == "{ft5}" ) { +FReg = PULP :: F5_F ; +} +if ( Constraint . lower ( ) == "{f6}" ) { +FReg = PULP :: F6_F ; +} +if ( Constraint . lower ( ) == "{ft6}" ) { +FReg = PULP :: F6_F ; +} +if ( Constraint . lower ( ) == "{f7}" ) { +FReg = PULP :: F7_F ; +} +if ( Constraint . lower ( ) == "{ft7}" ) { +FReg = PULP :: F7_F ; +} +if ( Constraint . lower ( ) == "{f8}" ) { +FReg = PULP :: F8_F ; +} +if ( Constraint . lower ( ) == "{ft8}" ) { +FReg = PULP :: F8_F ; +} +if ( Constraint . lower ( ) == "{f9}" ) { +FReg = PULP :: F9_F ; +} +if ( Constraint . lower ( ) == "{ft9}" ) { +FReg = PULP :: F9_F ; +} +if ( Constraint . lower ( ) == "{f10}" ) { +FReg = PULP :: F10_F ; +} +if ( Constraint . lower ( ) == "{ft10}" ) { +FReg = PULP :: F10_F ; +} +if ( Constraint . lower ( ) == "{f11}" ) { +FReg = PULP :: F11_F ; +} +if ( Constraint . lower ( ) == "{ft11}" ) { +FReg = PULP :: F11_F ; +} +if ( Constraint . lower ( ) == "{f12}" ) { +FReg = PULP :: F12_F ; +} +if ( Constraint . lower ( ) == "{ft12}" ) { +FReg = PULP :: F12_F ; +} +if ( Constraint . lower ( ) == "{f13}" ) { +FReg = PULP :: F13_F ; +} +if ( Constraint . lower ( ) == "{ft13}" ) { +FReg = PULP :: F13_F ; +} +if ( Constraint . lower ( ) == "{f14}" ) { +FReg = PULP :: F14_F ; +} +if ( Constraint . lower ( ) == "{ft14}" ) { +FReg = PULP :: F14_F ; +} +if ( Constraint . lower ( ) == "{f15}" ) { +FReg = PULP :: F15_F ; +} +if ( Constraint . lower ( ) == "{ft15}" ) { +FReg = PULP :: F15_F ; +} +if ( Constraint . lower ( ) == "{f16}" ) { +FReg = PULP :: F16_F ; +} +if ( Constraint . lower ( ) == "{ft16}" ) { +FReg = PULP :: F16_F ; +} +if ( Constraint . lower ( ) == "{f17}" ) { +FReg = PULP :: F17_F ; +} +if ( Constraint . lower ( ) == "{ft17}" ) { +FReg = PULP :: F17_F ; +} +if ( Constraint . lower ( ) == "{f18}" ) { +FReg = PULP :: F18_F ; +} +if ( Constraint . lower ( ) == "{ft18}" ) { +FReg = PULP :: F18_F ; +} +if ( Constraint . lower ( ) == "{f19}" ) { +FReg = PULP :: F19_F ; +} +if ( Constraint . lower ( ) == "{ft19}" ) { +FReg = PULP :: F19_F ; +} +if ( Constraint . lower ( ) == "{f20}" ) { +FReg = PULP :: F20_F ; +} +if ( Constraint . lower ( ) == "{ft20}" ) { +FReg = PULP :: F20_F ; +} +if ( Constraint . lower ( ) == "{f21}" ) { +FReg = PULP :: F21_F ; +} +if ( Constraint . lower ( ) == "{ft21}" ) { +FReg = PULP :: F21_F ; +} +if ( Constraint . lower ( ) == "{f22}" ) { +FReg = PULP :: F22_F ; +} +if ( Constraint . lower ( ) == "{ft22}" ) { +FReg = PULP :: F22_F ; +} +if ( Constraint . lower ( ) == "{f23}" ) { +FReg = PULP :: F23_F ; +} +if ( Constraint . lower ( ) == "{ft23}" ) { +FReg = PULP :: F23_F ; +} +if ( Constraint . lower ( ) == "{f24}" ) { +FReg = PULP :: F24_F ; +} +if ( Constraint . lower ( ) == "{ft24}" ) { +FReg = PULP :: F24_F ; +} +if ( Constraint . lower ( ) == "{f25}" ) { +FReg = PULP :: F25_F ; +} +if ( Constraint . lower ( ) == "{ft25}" ) { +FReg = PULP :: F25_F ; +} +if ( Constraint . lower ( ) == "{f26}" ) { +FReg = PULP :: F26_F ; +} +if ( Constraint . lower ( ) == "{ft26}" ) { +FReg = PULP :: F26_F ; +} +if ( Constraint . lower ( ) == "{f27}" ) { +FReg = PULP :: F27_F ; +} +if ( Constraint . lower ( ) == "{ft27}" ) { +FReg = PULP :: F27_F ; +} +if ( Constraint . lower ( ) == "{f28}" ) { +FReg = PULP :: F28_F ; +} +if ( Constraint . lower ( ) == "{ft28}" ) { +FReg = PULP :: F28_F ; +} +if ( Constraint . lower ( ) == "{f29}" ) { +FReg = PULP :: F29_F ; +} +if ( Constraint . lower ( ) == "{ft29}" ) { +FReg = PULP :: F29_F ; +} +if ( Constraint . lower ( ) == "{f30}" ) { +FReg = PULP :: F30_F ; +} +if ( Constraint . lower ( ) == "{ft30}" ) { +FReg = PULP :: F30_F ; +} +if ( Constraint . lower ( ) == "{f31}" ) { +FReg = PULP :: F31_F ; +} +if ( Constraint . lower ( ) == "{ft31}" ) { +FReg = PULP :: F31_F ; +} +if ( FReg != PULP :: NoRegister ) { +assert ( PULP :: F0_32 <= FReg && FReg <= PULP :: F31_32 && "Unknown fp-reg" ) ; +if ( Subtarget . hasStdExtD ( ) ) { +unsigned RegNo = FReg - PULP :: F0_32 ; +unsigned DReg = PULP :: F0_64 + RegNo ; +} +} +} +return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/getRegisterByName.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/getRegisterByName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9208c63ec4ea6627a79fe878b86793de0a2c3c59 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/getRegisterByName.cpp @@ -0,0 +1,6 @@ +Register PULPTargetLowering :: getRegisterByName ( const char * RegName , LLT VT , const MachineFunction & MF ) const { +Register Reg = MatchRegisterAltName ( RegName ) ; +if ( Reg ) { +return Reg ; +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/getScalarShiftAmountTy.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/getScalarShiftAmountTy.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ff6e60c22622cb8d354ac3e5e548f0162db96cbd --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/getScalarShiftAmountTy.cpp @@ -0,0 +1,3 @@ +MVT PULPTargetLowering :: getScalarShiftAmountTy ( const DataLayout & DL , EVT ) const { +return Subtarget . getXLenVT ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/getSetCCResultType.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/getSetCCResultType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1ca67544380671d3d5b917b5c4df6ea4cc7323ca --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/getSetCCResultType.cpp @@ -0,0 +1,8 @@ +EVT PULPTargetLowering :: getSetCCResultType ( const DataLayout & DL , LLVMContext & , EVT VT ) const { +if ( ! VT . isVector ( ) ) { +return getPointerTy ( DL ) ; +} +if ( Subtarget . hasStdExtV ( ) ) { +return MVT :: getVectorVT ( MVT :: i1 , VT . getVectorElementCount ( ) ) ; +return VT . changeVectorElementTypeToInteger ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/getStaticTLSAddr.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/getStaticTLSAddr.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fb2533d06f5c7940c0c93d33cdf5da0426cd63d0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/getStaticTLSAddr.cpp @@ -0,0 +1,24 @@ +SDValue PULPTargetLowering :: getStaticTLSAddr ( GlobalAddressSDNode * N , SelectionDAG & DAG , bool UseGOT ) const { +MachineFunction & MF = DAG . getMachineFunction ( ) ; +PULPMachineFunctionInfo * CFI = MF . getInfo < PULPMachineFunctionInfo > ( ) ; +unsigned PULPPCLabelIndex = CFI -> createPICLabelUId ( ) ; +SDLoc DL ( N ) ; +EVT Ty = getPointerTy ( DAG . getDataLayout ( ) ) ; +PULPCP :: PULPCPModifier Flag = UseGOT ? PULPCP :: TLSIE : PULPCP :: TLSLE ; +bool AddCurrentAddr = UseGOT ? true : false ; +unsigned char PCAjust = UseGOT ? 4 : 0 ; +PULPConstantPoolValue * CPV = PULPConstantPoolConstant :: Create ( N -> getGlobal ( ) , PULPCP :: CPValue , PCAjust , Flag , AddCurrentAddr , PULPPCLabelIndex ) ; +SDValue CAddr = DAG . getTargetConstantPool ( CPV , Ty ) ; +SDValue Load ; +if ( UseGOT ) { +SDValue PICLabel = DAG . getTargetConstant ( PULPPCLabelIndex , DL , MVT :: i32 ) ; +auto * LRWGRS = DAG . getMachineNode ( PULP :: PseudoTLSLA32 , DL , { Ty , Ty } , { CAddr , PICLabel } ) ; +auto LRWADDGRS = DAG . getNode ( ISD :: ADD , DL , Ty , SDValue ( LRWGRS , 0 ) , SDValue ( LRWGRS , 1 ) ) ; +Load = DAG . getLoad ( Ty , DL , DAG . getEntryNode ( ) , LRWADDGRS , MachinePointerInfo ( N -> getGlobal ( ) ) ) ; +} +if ( ! UseGOT ) { +Load = SDValue ( DAG . getMachineNode ( PULP :: LRW32 , DL , Ty , CAddr ) , 0 ) ; +} +SDValue TPReg = DAG . getRegister ( PULP :: R31 , MVT :: i32 ) ; +return DAG . getNode ( ISD :: ADD , DL , Ty , Load , TPReg ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/getSubtarget.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/getSubtarget.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ed71f24d87e162c3480ec8d3d77679b6e84ff410 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/getSubtarget.cpp @@ -0,0 +1,3 @@ +const PULPSubtarget & getSubtarget ( ) const { +return Subtarget ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/getTargetNodeName.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/getTargetNodeName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d6c7d1ffde7e428d618ee5a7ab3b90ab9e679864 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/getTargetNodeName.cpp @@ -0,0 +1,123 @@ +const char * PULPTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { +if ( ( PULPISD :: NodeType ) Opcode == PULPISD :: RET_FLAG ) { +return "PULPISD::RET_FLAG" ; +} +if ( ( PULPISD :: NodeType ) Opcode == PULPISD::URET_FLAG ) { +return "PULPISD::URET_FLAG" ; +} +if ( ( PULPISD :: NodeType ) Opcode == PULPISD :: SRET_FLAG ) { +return "PULPISD::SRET_FLAG" ; +} +if ( ( PULPISD :: NodeType ) Opcode == PULPISD :: MRET_FLAG ) { +return "PULPISD::MRET_FLAG" ; +} +if ( ( PULPISD :: NodeType ) Opcode == PULPISD :: CALL ) { +return "PULPISD::CALL" ; +} +if ( ( PULPISD :: NodeType ) Opcode == PULPISD :: SELECT_CC ) { +return "PULPISD::SELECT_CC" ; +} +if ( ( PULPISD :: NodeType ) Opcode == PULPISD :: BuildPairF64 ) { +return "PULPISD::BuildPairF64" ; +} +if ( ( PULPISD :: NodeType ) Opcode == PULPISD :: SplitF64 ) { +return "PULPISD::SplitF64" ; +} +if ( ( PULPISD :: NodeType ) Opcode == PULPISD ::TAIL ) { +return "PULPISD::TAIL" ; +} +if ( ( PULPISD :: NodeType ) Opcode == PULPISD :: FMV_X_ANYEXTH ) { +return "PULPISD::FMV_X_ANYEXTH" ; +} +if ( ( PULPISD :: NodeType ) Opcode == PULPISD :: FMV_W_X_RV64 ) { +return "PULPISD::FMV_W_X_RV64" ; +} +if ( ( PULPISD :: NodeType ) Opcode == PULPISD :: FMV_X_ANYEXTW_RV64 ) { +return "PULPISD::FMV_X_ANYEXTW_RV64" ; +} +if ( ( PULPISD :: NodeType ) Opcode == PULPISD :: READ_CYCLE_WIDE ) { +return "PULPISD::READ_CYCLE_WIDE" ; +} +if ( ( PULPISD :: NodeType ) Opcode == PULPISD::GREVI ) { +return "PULPISD::GREVI" ; +} +if ( ( PULPISD :: NodeType ) Opcode == PULPISD::GREVIW ) { +return "PULPISD::GREVIW" ; +} +if ( ( PULPISD :: NodeType ) Opcode == PULPISD :: GORCI ) { +return "PULPISD::GORCI" ; +} +if ( ( PULPISD :: NodeType ) Opcode == PULPISD :: GORCIW ) { +return "PULPISD::GORCIW" ; +} +if ( ( PULPISD :: NodeType ) Opcode == PULPISD::VMV_X_S ) { +return "PULPISD::VMV_X_S" ; +} +if ( ( PULPISD :: NodeType ) Opcode == PULPISD :: SPLAT_VECTOR_I64 ) { +return "PULPISD::SPLAT_VECTOR_I64" ; +} +if ( ( PULPISD :: NodeType ) Opcode == PULPISD :: READ_VLENB ) { +return "PULPISD::READ_VLENB" ; +} +if ( ( PULPISD :: NodeType ) Opcode == PULPISD :: TRUNCATE_VECTOR ) { +return "PULPISD::TRUNCATE_VECTOR" ; +} +if ( ( PULPISD :: NodeType ) Opcode == PULPISD :: VLEFF ) { +return "PULPISD::VLEFF" ; +} +if ( ( PULPISD :: NodeType ) Opcode == PULPISD :: VLEFF_MASK ) { +return "PULPISD::VLEFF_MASK" ; +} +if ( ( PULPISD :: NodeType ) Opcode == PULPISD::VLSEGFF ) { +return "PULPISD::VLSEGFF" ; +} +if ( ( PULPISD :: NodeType ) Opcode == PULPISD :: VLSEGFF_MASK ) { +return "PULPISD::VLSEGFF_MASK" ; +} +if ( ( PULPISD :: NodeType ) Opcode == PULPISD :: READ_VL ) { +return "PULPISD::READ_VL" ; +} +if ( ( PULPISD :: NodeType ) Opcode == PULPISD :: VSLIDEUP ) { +return "PULPISD::VSLIDEUP" ; +} +if ( ( PULPISD :: NodeType ) Opcode == PULPISD :: VSLIDEDOWN ) { +return "PULPISD::VSLIDEDOWN" ; +} +if ( ( PULPISD :: NodeType ) Opcode == PULPISD :: VID ) { +return "PULPISD::VID" ; +} +if ( ( PULPISD :: NodeType ) Opcode == PULPISD :: FMV_H_X ) { +return "PULPISD::FMV_H_X" ; +} +if ( ( PULPISD :: NodeType ) Opcode == PULPISD :: FSRW ) { +return "PULPISD::FSRW" ; +} +if ( ( PULPISD :: NodeType ) Opcode == PULPISD :: FSLW ) { +return "PULPISD::FSLW" ; +} +if ( ( PULPISD :: NodeType ) Opcode == PULPISD :: RORW ) { +return "PULPISD::RORW" ; +} +if ( ( PULPISD :: NodeType ) Opcode == PULPISD :: ROLW ) { +return "PULPISD::ROLW" ; +} +if ( ( PULPISD :: NodeType ) Opcode == PULPISD :: REMUW ) { +return "PULPISD::REMUW" ; +} +if ( ( PULPISD :: NodeType ) Opcode == PULPISD :: DIVUW ) { +return "PULPISD::DIVUW" ; +} +if ( ( PULPISD :: NodeType ) Opcode == PULPISD :: DIVW ) { +return "PULPISD::DIVW" ; +} +if ( ( PULPISD :: NodeType ) Opcode == PULPISD :: SRLW ) { +return "PULPISD::SRLW" ; +} +if ( ( PULPISD :: NodeType ) Opcode == PULPISD :: SRAW ) { +return "PULPISD::SRAW" ; +} +if ( ( PULPISD :: NodeType ) Opcode == PULPISD :: SLLW ) { +return "PULPISD::SLLW" ; +} +return nullptr ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/getTgtMemIntrinsic.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/getTgtMemIntrinsic.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e35236f2f4ebbb1cd7c1877b715e6f0491508d4d --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/getTgtMemIntrinsic.cpp @@ -0,0 +1,111 @@ +bool PULPTargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & I , MachineFunction & MF , unsigned Intrinsic ) const { +if ( Intrinsic == Intrinsic :: PULP_masked_atomicrmw_xchg_i32 ) { +PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( 0 ) -> getType ( ) ) ; +Info . opc = ISD :: INTRINSIC_W_CHAIN ; +Info . memVT = MVT :: getVT ( PtrTy -> getElementType ( ) ) ; +Info . ptrVal = I . getArgOperand ( 0 ) ; +Info . offset = 0 ; +Info . align = I . getModule ( ) -> getDataLayout ( ) . getABITypeAlignment ( PtrTy -> getElementType ( ) ) ; +Info . vol = true ; +Info . readMem = true ; +Info . writeMem = false ; +return true ; +} +if ( Intrinsic == Intrinsic :: PULP_masked_atomicrmw_add_i32 ) { +PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( 0 ) -> getType ( ) ) ; +Info . opc = ISD :: INTRINSIC_W_CHAIN ; +Info . memVT = MVT :: getVT ( PtrTy -> getElementType ( ) ) ; +Info . ptrVal = I . getArgOperand ( 0 ) ; +Info . offset = 0 ; +Info . align = I . getModule ( ) -> getDataLayout ( ) . getABITypeAlignment ( PtrTy -> getElementType ( ) ) ; +Info . vol = true ; +Info . readMem = true ; +Info . writeMem = false ; +return true ; +} +if ( Intrinsic == Intrinsic :: PULP_masked_atomicrmw_sub_i32 ) { +PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( 0 ) -> getType ( ) ) ; +Info . opc = ISD :: INTRINSIC_W_CHAIN ; +Info . memVT = MVT :: getVT ( PtrTy -> getElementType ( ) ) ; +Info . ptrVal = I . getArgOperand ( 0 ) ; +Info . offset = 0 ; +Info . align = I . getModule ( ) -> getDataLayout ( ) . getABITypeAlignment ( PtrTy -> getElementType ( ) ) ; +Info . vol = true ; +Info . readMem = true ; +Info . writeMem = false ; +return true ; +} +if ( Intrinsic == Intrinsic :: PULP_masked_atomicrmw_nand_i32 ) { +PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( 0 ) -> getType ( ) ) ; +Info . opc = ISD :: INTRINSIC_W_CHAIN ; +Info . memVT = MVT :: getVT ( PtrTy -> getElementType ( ) ) ; +Info . ptrVal = I . getArgOperand ( 0 ) ; +Info . offset = 0 ; +Info . align = I . getModule ( ) -> getDataLayout ( ) . getABITypeAlignment ( PtrTy -> getElementType ( ) ) ; +Info . vol = true ; +Info . readMem = true ; +Info . writeMem = false ; +return true ; +} +if ( Intrinsic == Intrinsic :: PULP_masked_atomicrmw_max_i32 ) { +PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( 1 ) -> getType ( ) ) ; +Info . opc = ISD :: INTRINSIC_W_CHAIN ; +Info . memVT = MVT :: getVT ( PtrTy -> getElementType ( ) ) ; +Info . ptrVal = I . getArgOperand ( 1 ) ; +Info . offset = 0 ; +Info . align = I . getModule ( ) -> getDataLayout ( ) . getABITypeAlignment ( PtrTy -> getElementType ( ) ) ; +Info . vol = true ; +Info . readMem = false ; +Info . writeMem = true ; +return true ; +} +if ( Intrinsic == Intrinsic :: PULP_masked_atomicrmw_min_i32 ) { +PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( 1 ) -> getType ( ) ) ; +Info . opc = ISD :: INTRINSIC_W_CHAIN ; +Info . memVT = MVT :: getVT ( PtrTy -> getElementType ( ) ) ; +Info . ptrVal = I . getArgOperand ( 1 ) ; +Info . offset = 0 ; +Info . align = I . getModule ( ) -> getDataLayout ( ) . getABITypeAlignment ( PtrTy -> getElementType ( ) ) ; +Info . vol = true ; +Info . readMem = false ; +Info . writeMem = true ; +return true ; +} +if ( Intrinsic == Intrinsic :: PULP_masked_atomicrmw_umax_i32 ) { +PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( 0 ) -> getType ( ) ) ; +Info . opc = ISD :: INTRINSIC_W_CHAIN ; +Info . memVT = MVT :: getVT ( PtrTy -> getElementType ( ) ) ; +Info . ptrVal = I . getArgOperand ( 0 ) ; +Info . offset = 0 ; +Info . align = I . getModule ( ) -> getDataLayout ( ) . getABITypeAlignment ( PtrTy -> getElementType ( ) ) ; +Info . vol = true ; +Info . readMem = true ; +Info . writeMem = false ; +return true ; +} +if ( Intrinsic == Intrinsic :: PULP_masked_atomicrmw_umin_i32 ) { +PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( 0 ) -> getType ( ) ) ; +Info . opc = ISD :: INTRINSIC_W_CHAIN ; +Info . memVT = MVT :: getVT ( PtrTy -> getElementType ( ) ) ; +Info . ptrVal = I . getArgOperand ( 0 ) ; +Info . offset = 0 ; +Info . align = I . getModule ( ) -> getDataLayout ( ) . getABITypeAlignment ( PtrTy -> getElementType ( ) ) ; +Info . vol = true ; +Info . readMem = true ; +Info . writeMem = false ; +return true ; +} +if ( Intrinsic == Intrinsic :: PULP_masked_cmpxchg_i32 ) { +PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( 0 ) -> getType ( ) ) ; +Info . opc = ISD :: INTRINSIC_W_CHAIN ; +Info . memVT = MVT :: getVT ( PtrTy -> getElementType ( ) ) ; +Info . ptrVal = I . getArgOperand ( 0 ) ; +Info . offset = 0 ; +Info . align = I . getModule ( ) -> getDataLayout ( ) . getABITypeAlignment ( PtrTy -> getElementType ( ) ) ; +Info . vol = true ; +Info . readMem = true ; +Info . writeMem = false ; +return true ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/hasBitPreservingFPLogic.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/hasBitPreservingFPLogic.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d4552dcf7c1a160c396098bcd09fbe790334b593 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/hasBitPreservingFPLogic.cpp @@ -0,0 +1,3 @@ +bool PULPTargetLowering :: hasBitPreservingFPLogic ( EVT VT ) const { +return ( VT == MVT :: f16 && Subtarget . hasStdExtZfh ( ) ) || ( VT == MVT :: f32 && Subtarget . hasStdExtF ( ) ) || ( VT == MVT :: f64 && Subtarget . hasStdExtD ( ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/isCheapToSpeculateCtlz.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/isCheapToSpeculateCtlz.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ab97cf8e870b7659c51864fb3f0d20219773d9a6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/isCheapToSpeculateCtlz.cpp @@ -0,0 +1,3 @@ +bool PULPTargetLowering :: isCheapToSpeculateCtlz ( ) const { +return Subtarget . hasStdExtZbb ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/isCheapToSpeculateCttz.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/isCheapToSpeculateCttz.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e010f3676b5d999508058ceff64c57c200ab5702 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/isCheapToSpeculateCttz.cpp @@ -0,0 +1,3 @@ +bool PULPTargetLowering :: isCheapToSpeculateCttz ( ) const { +return Subtarget . hasStdExtZbb ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/isDesirableToCommuteWithShift.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/isDesirableToCommuteWithShift.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cb72dd49b6acc869b803c7c1671e2ccdea8c96b0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/isDesirableToCommuteWithShift.cpp @@ -0,0 +1,8 @@ +bool PULPTargetLowering :: isDesirableToCommuteWithShift ( const SDNode * N , CombineLevel Level ) const { +if ( Level == BeforeLegalizeTypes ) { +return true ; +return true ; +if ( N -> getOpcode ( ) != ISD :: SHL ) { +return true ; +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/isEligibleForTailCallOptimization.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/isEligibleForTailCallOptimization.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ba886ad6db60a9ac25891e5911cdd9f8b55c363d --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/isEligibleForTailCallOptimization.cpp @@ -0,0 +1,23 @@ +bool PULPTargetLowering :: isEligibleForTailCallOptimization ( CCState & CCInfo , CallLoweringInfo & CLI , MachineFunction & MF , const SmallVector < CCValAssign , 16 > & ArgLocs ) const { +MachineFunction & MF = DAG . getMachineFunction ( ) ; +const Function & CallerF = MF . getFunction ( ) ; +CallingConv :: ID CallerCC = CallerF . getCallingConv ( ) ; +bool CCMatch = CallerCC == CalleeCC ; +for ( Function :: const_arg_iterator i = CallerF . arg_begin ( ) , e = CallerF . arg_end ( ) ; i != e ; ++ i ) { +if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { +const GlobalValue * GV = G -> getGlobal ( ) ; +if ( GV -> hasExternalWeakLinkage ( ) ) { +return false ; +} +if ( GV -> hasExternalWeakLinkage ( ) ) { +if ( TT . isOSBinFormatELF ( ) ) { +return false ; +} +if ( GV -> hasExternalWeakLinkage ( ) ) { +return false ; +} +} +assert ( ( ! isVarArg || CalleeCC == CallingConv :: C ) && "Unexpected variadic calling convention" ) ; +for ( const CCValAssign & ArgLoc : ArgLocs ) { +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/isFMAFasterThanFMulAndFAdd.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/isFMAFasterThanFMulAndFAdd.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bca1724a727e44fe609587b697e8f176cf656c31 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/isFMAFasterThanFMulAndFAdd.cpp @@ -0,0 +1,16 @@ +bool PULPTargetLowering :: isFMAFasterThanFMulAndFAdd ( const MachineFunction & MF , EVT VT ) const { +VT = VT . getScalarType ( ) ; +if ( ! VT . isSimple ( ) ) { +return false ; +} +if ( VT . getSimpleVT ( ) . SimpleTy == MVT :: f16 ) { +return Subtarget . hasStdExtZfh ( ) ; +} +if ( VT . getSimpleVT ( ) . SimpleTy == MVT :: f32 ) { +return Subtarget . hasStdExtF ( ) ; +} +if ( VT . getSimpleVT ( ) . SimpleTy == MVT :: f64 ) { +return Subtarget . hasStdExtD ( ) ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/isFPImmLegal.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/isFPImmLegal.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3555f387699cdb2ba5f50921f63b45fb9801425b --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/isFPImmLegal.cpp @@ -0,0 +1,24 @@ +bool PULPTargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT , bool ForCodeSize ) const { +if ( VT == MVT :: f16 ) { +if ( Subtarget . hasFullFP16 ( ) ) { +return PULP_AM :: getFP16Imm ( Imm ) != - 1 ; +} +} +if ( VT == MVT :: f32 ) { +return PULP_AM :: getFP32Imm ( Imm ) != - 1 ; +} +if ( VT == MVT :: f64 ) { +if ( Subtarget . isFPOnlySP ( ) ) { +return PULP_AM :: getFP64Imm ( Imm ) != - 1 ; +} +} +if ( VT != MVT :: f32 ) { +if ( VT != MVT :: f64 ) { +return false ; +} +} +if ( Imm . isNegZero ( ) ) { +return false ; +} +return Imm . isZero ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/isLegalAddImmediate.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/isLegalAddImmediate.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e3bc18af81d1121bb2570363f02f0a239d0104fe --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/isLegalAddImmediate.cpp @@ -0,0 +1,3 @@ +bool PULPTargetLowering :: isLegalAddImmediate ( int64_t Imm ) const { +return isInt < 12 > ( Imm ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/isLegalAddressingMode.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/isLegalAddressingMode.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7c2d8472817232e72f9cfee58f83e5c0f252c0e4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/isLegalAddressingMode.cpp @@ -0,0 +1,17 @@ +bool PULPTargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS , Instruction * I ) const { +if ( AM . BaseGV ) { +return false ; +} +if ( ! isInt < 12 > ( AM . BaseOffs ) ) { +return false ; +} +if ( AM . Scale == 0 ) { +return true ; +} +if ( AM . Scale == 1 ) { +if ( ! AM . HasBaseReg ) { +return true ; +} +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/isLegalICmpImmediate.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/isLegalICmpImmediate.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6927605b4aa0fb7c3767a056a900c1e84835f908 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/isLegalICmpImmediate.cpp @@ -0,0 +1,3 @@ +bool PULPTargetLowering :: isLegalICmpImmediate ( int64_t Imm ) const { +return isInt < 12 > ( Imm ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/isSExtCheaperThanZExt.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/isSExtCheaperThanZExt.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5becfee2532fbb11c3b12c5ace7d7646abae1e5e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/isSExtCheaperThanZExt.cpp @@ -0,0 +1,3 @@ +bool PULPTargetLowering :: isSExtCheaperThanZExt ( EVT VT1 , EVT VT2 ) const { +return Subtarget . is64Bit ( ) && VT1 == MVT :: i32 && VT2 == MVT :: i64 ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/isTruncateFree.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/isTruncateFree.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3abd186c4e148834917d153558cc3396ea915fd5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/isTruncateFree.cpp @@ -0,0 +1,14 @@ +bool PULPTargetLowering :: isTruncateFree ( Type * SrcTy , Type * DstTy ) const { +if ( Subtarget . is64Bit ( ) ) { +return false ; +} +if ( ! SrcTy -> isIntegerTy ( ) ) { +return false ; +} +if ( ! DstTy -> isIntegerTy ( ) ) { +return false ; +} +unsigned NumBits1 = SrcTy -> getPrimitiveSizeInBits ( ) ; +unsigned NumBits2 = DstTy -> getPrimitiveSizeInBits ( ) ; +return NumBits1 == 64 && NumBits2 == 32 ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/isTruncateFree2.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/isTruncateFree2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4d46fa6aaca7d0f9fad8f18e7988d63c31685219 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/isTruncateFree2.cpp @@ -0,0 +1,20 @@ +bool PULPTargetLowering :: isTruncateFree ( EVT SrcVT , EVT DstVT ) const { +if ( Subtarget . is64Bit ( ) ) { +return false ; +} +if ( SrcVT . isVector ( ) ) { +return false ; +} +if ( DstVT . isVector ( ) ) { +return false ; +} +if ( ! SrcVT . isInteger ( ) ) { +return false ; +} +if ( ! DstVT . isInteger ( ) ) { +return false ; +} +unsigned SrcBits = SrcVT . getSizeInBits ( ) ; +unsigned DestBits = DstVT . getSizeInBits ( ) ; +return ( SrcBits == 64 && DestBits == 32 ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/isZExtFree.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/isZExtFree.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3a2a6620bfc6c3f84fcd715277073d7ea639dd0f --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/isZExtFree.cpp @@ -0,0 +1,37 @@ +bool PULPTargetLowering :: isZExtFree ( SDValue Val , EVT VT2 ) const { +if ( auto * LD = dyn_cast < LoadSDNode > ( Val ) ) { +EVT MemVT = LD -> getMemoryVT ( ) ; +if ( MemVT == MVT :: i1 ) { +if ( LD -> getExtensionType ( ) == ISD :: NON_EXTLOAD ) { +return true ; +if ( LD -> getExtensionType ( ) == ISD :: ZEXTLOAD ) { +return true ; +if ( MemVT == MVT :: i8 ) { +if ( LD -> getExtensionType ( ) == ISD :: NON_EXTLOAD ) { +return true ; +} +if ( LD -> getExtensionType ( ) == ISD :: ZEXTLOAD ) { +return true ; +} +} +if ( MemVT == MVT :: i16 ) { +if ( LD -> getExtensionType ( ) == ISD :: NON_EXTLOAD ) { +return true ; +} +if ( LD -> getExtensionType ( ) == ISD :: ZEXTLOAD ) { +return true ; +} +} +if ( MemVT == MVT :: i32 ) { +if ( Subtarget . is64Bit ( ) ) { +if ( LD -> getExtensionType ( ) == ISD :: NON_EXTLOAD ) { +return true ; +} +if ( LD -> getExtensionType ( ) == ISD :: ZEXTLOAD ) { +return true ; +} +} +} +} +return TargetLowering :: isZExtFree ( Val , VT2 ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/lowerEXTRACT_VECTOR_ELT.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/lowerEXTRACT_VECTOR_ELT.cpp new file mode 100644 index 0000000000000000000000000000000000000000..558362a3fcb73fba37e6ab7f39660684b0398c1a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/lowerEXTRACT_VECTOR_ELT.cpp @@ -0,0 +1,15 @@ +SDValue PULPTargetLowering :: lowerEXTRACT_VECTOR_ELT ( SDValue Op , SelectionDAG & DAG ) const { +return Op ; +return Op ; +return Op ; +return Op ; +return Op ; +return Op ; +SDLoc DL ( Op ) ; +SDValue Idx = Op . getOperand ( 1 ) ; +Result = DAG . getNode ( ISD :: TRUNCATE , SL , MVT :: i16 , Result ) ; +MVT VecTy = ty ( Vec ) ; +return Op ; +return Op ; +SDValue Res = DAG . getNode ( ISD :: EXTRACT_VECTOR_ELT , DL , IntVT , DAG . getNode ( ISD :: BITCAST , DL , IntVecVT , Op0 ) , Op1 ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/lowerINSERT_VECTOR_ELT.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/lowerINSERT_VECTOR_ELT.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a248cf3b8692c79d2d6fb934268b9bf206cd240c --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/lowerINSERT_VECTOR_ELT.cpp @@ -0,0 +1,10 @@ +SDValue PULPTargetLowering :: lowerINSERT_VECTOR_ELT ( SDValue Op , SelectionDAG & DAG ) const { +SDLoc dl ( Op ) ; +SDValue V1 = Op . getOperand ( 0 ) ; +SDValue V2 = Op . getOperand ( 1 ) ; +SDLoc SL ( Op ) ; +SDValue Vec = Op . getOperand ( 0 ) ; +SDValue Val = DAG . getNode ( ISD :: BITCAST , SL , MVT :: i16 , Op . getOperand ( 1 ) ) ; +SDValue BCVec = DAG . getNode ( ISD :: BITCAST , SL , MVT :: i32 , Vec ) ; +SDValue Res = DAG . getNode ( ISD :: INSERT_VECTOR_ELT , DL , IntVecVT , DAG . getNode ( ISD :: BITCAST , DL , IntVecVT , Op0 ) , DAG . getNode ( ISD :: BITCAST , DL , IntVT , Op1 ) , Op2 ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/lowerSELECT.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/lowerSELECT.cpp new file mode 100644 index 0000000000000000000000000000000000000000..23149df7b3294e491f553c82310777dad7f6c246 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/lowerSELECT.cpp @@ -0,0 +1,27 @@ +SDValue PULPTargetLowering :: lowerSELECT ( SDValue Op , SelectionDAG & DAG ) const { +SDValue CondV = Op . getOperand ( 0 ) ; +SDValue TrueV = Op . getOperand ( 1 ) ; +SDValue FalseV = Op . getOperand ( 2 ) ; +SDLoc DL ( Op ) ; +MVT XLenVT = Subtarget . getXLenVT ( ) ; +if ( Op . getSimpleValueType ( ) == XLenVT ) { +if ( CondV . getOperand ( 0 ) . getSimpleValueType ( ) == XLenVT ) { +if ( CondV . getOpcode ( ) == ISD :: SETCC ) { +SDValue LHS = CondV . getOperand ( 0 ) ; +SDValue RHS = CondV . getOperand ( 1 ) ; +auto CC = cast < CondCodeSDNode > ( CondV . getOperand ( 2 ) ) ; +ISD :: CondCode CCVal = CC -> get ( ) ; +normaliseSetCC ( LHS , RHS , CCVal ) ; +SDValue TargetCC = DAG . getConstant ( CCVal , DL , XLenVT ) ; +auto VTs = Op . getValueType ( ) ; +SDValue Ops [ ] = { LHS , RHS , TargetCC , TrueV , FalseV } ; +return DAG . getNode ( PULPISD :: SELECT_CC , DL , VTs , Ops ) ; +} +} +} +SDValue Zero = DAG . getConstant ( 0 , DL , XLenVT ) ; +SDValue SetNE = DAG . getConstant ( ISD :: SETNE , DL , XLenVT ) ; +auto VTs = Op . getValueType ( ) ; +SDValue Ops [ ] = { CondV , Zero , SetNE , TrueV , FalseV } ; +return DAG . getNode ( PULPISD :: SELECT_CC , DL , VTs , Ops ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/lowerSPLATVECTOR.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/lowerSPLATVECTOR.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c18daff9957439f0afcef3d1ac14bb62e999bd81 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/lowerSPLATVECTOR.cpp @@ -0,0 +1,19 @@ +SDValue PULPTargetLowering :: lowerSPLATVECTOR ( SDValue Op , SelectionDAG & DAG ) const { +assert ( ! Subtarget . is64Bit ( ) && VecVT . getVectorElementType ( ) == MVT :: i64 && "Unexpected SPLAT_VECTOR lowering" ) ; +SDLoc DL ( Op ) ; +SDValue N1 = Op . getOperand ( 0 ) ; +unsigned SrcSize = N1 . getValueType ( ) . getSizeInBits ( ) ; +SDValue WideSrc = SrcSize == 128 ? N1 : widenVec ( DAG , N1 , DL ) ; +unsigned TrgNumElts = TrgVT . getVectorNumElements ( ) ; +SmallVector < int , 16 > ShuffV ; +if ( Subtarget . isLittleEndian ( ) ) { +for ( unsigned i = 0 ; i < TrgNumElts ; ++ i ) { +ShuffV . push_back ( i * SizeMult ) ; +if ( Subtarget . isBigEndian ( ) ) { +for ( unsigned i = 1 ; i < TrgNumElts ; ++ i ) { +ShuffV . push_back ( i * SizeMult - 1 ) ; +for ( unsigned i = TrgNumElts ; i < WideNumElts ; ++ i ) { +ShuffV . push_back ( WideNumElts + 1 ) ; +SDValue Conv = DAG . getNode ( ISD :: BITCAST , DL , WideVT , WideSrc ) ; +return DAG . getVectorShuffle ( WideVT , DL , Conv , DAG . getUNDEF ( WideVT ) , ShuffV ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/lowerShiftLeftParts.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/lowerShiftLeftParts.cpp new file mode 100644 index 0000000000000000000000000000000000000000..32efafbbde1b3fa427f3f608dae8cf3e5d10fbaa --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/lowerShiftLeftParts.cpp @@ -0,0 +1,40 @@ +SDValue PULPTargetLowering :: lowerShiftLeftParts ( SDValue Op , SelectionDAG & DAG ) const { +EVT VT = Op . getValueType ( ) ; +unsigned VTBits = VT . getSizeInBits ( ) ; +SDLoc DL ( Op ) ; +MVT VT = Subtarget . isGP64bit ( ) ? MVT :: i64 : MVT :: i32 ; +SDValue Lo = Op . getOperand ( 0 ) ; +SDValue Hi = Op . getOperand ( 1 ) ; +SDValue Shamt = Op . getOperand ( 2 ) ; +SDValue RevShAmt = DAG . getNode ( ISD :: SUB , DL , MVT :: i64 , DAG . getConstant ( VTBits , MVT :: i64 ) , Shamt ) ; +SDValue Tmp1 = DAG . getNode ( ISD :: SRL , DL , VT , Lo , RevShAmt ) ; +SDValue ExtraShAmt = DAG . getNode ( ISD :: SUB , DL , MVT :: i64 , Shamt , DAG . getConstant ( VTBits , MVT :: i64 ) ) ; +SDValue Tmp2 = DAG . getNode ( ISD :: SHL , DL , VT , Hi , Shamt ) ; +SDValue Tmp3 = DAG . getNode ( ISD :: SHL , DL , VT , Lo , ExtraShAmt ) ; +SDValue FalseVal = DAG . getNode ( ISD :: OR , DL , VT , Tmp1 , Tmp2 ) ; +SDValue Tmp4 = DAG . getNode ( ISD :: SHL , DL , VT , Lo , Shamt ) ; +SDValue CmpOp = getSelectableIntSetCC ( ExtraShAmt , DAG . getConstant ( 0 , MVT :: i64 ) , ISD :: SETGE , A64cc , DAG , DL ) ; +SDValue CCR = DAG . getRegister ( PULP :: CPSR , MVT :: i32 ) ; +SDValue Cmp = getPULPCmp ( ExtraShAmt , DAG . getConstant ( 0 , MVT :: i32 ) , ISD :: SETGE , PULPcc , DAG , DL ) ; +SDValue Ops [ 2 ] = { Lo , Hi } ; +EVT VT = Lo . getValueType ( ) ; +SDValue Zero = DAG . getConstant ( 0 , DL , VT ) ; +SDValue One = DAG . getConstant ( 1 , DL , VT ) ; +SDValue MinusRegisterSize = DAG . getConstant ( - 32 , DL , VT ) ; +SDValue RegisterSizeMinus1 = DAG . getConstant ( 32 - 1 , DL , VT ) ; +SDValue ShamtMinusRegisterSize = DAG . getNode ( ISD :: ADD , DL , VT , Shamt , MinusRegisterSize ) ; +SDValue RegisterSizeMinus1Shamt = DAG . getNode ( ISD :: XOR , DL , VT , RegisterSizeMinus1 , Shamt ) ; +SDValue LoTrue = DAG . getNode ( ISD :: SHL , DL , VT , Lo , Shamt ) ; +SDValue Not = DAG . getNode ( ISD :: XOR , DL , MVT :: i32 , Shamt , DAG . getConstant ( - 1 , MVT :: i32 ) ) ; +SDValue ShiftLeftHi = DAG . getNode ( ISD :: SHL , DL , VT , Hi , Shamt ) ; +SDValue HiTrue = DAG . getNode ( ISD :: OR , DL , VT , ShiftLeftHi , ShiftRightLo ) ; +SDValue HiFalse = DAG . getNode ( ISD :: SHL , DL , VT , Lo , ShamtMinusRegisterSize ) ; +SDValue CC = DAG . getSetCC ( DL , MVT :: i8 , ShamtMinusRegisterSize , Zero , ISD :: SETLT ) ; +SDValue Or = DAG . getNode ( ISD :: OR , DL , VT , ShiftLeftHi , ShiftRightLo ) ; +SDValue ShiftLeftLo = DAG . getNode ( ISD :: SHL , DL , VT , Lo , Shamt ) ; +SDValue Cond = DAG . getNode ( ISD :: AND , DL , MVT :: i32 , Shamt , DAG . getConstant ( VT . getSizeInBits ( ) , MVT :: i32 ) ) ; +Lo = DAG . getNode ( ISD :: SELECT , DL , VT , CC , LoTrue , Zero ) ; +Hi = DAG . getNode ( ISD :: SELECT , DL , VT , CC , HiTrue , HiFalse ) ; +SDValue Ops [ 2 ] = { Lo , Hi } ; +return DAG . getMergeValues (Parts , DL ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/lowerShiftRightParts.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/lowerShiftRightParts.cpp new file mode 100644 index 0000000000000000000000000000000000000000..695328e40a05a6181a5f5029293851e757041c0d --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/lowerShiftRightParts.cpp @@ -0,0 +1,56 @@ +SDValue PULPTargetLowering :: lowerShiftRightParts ( SDValue Op , SelectionDAG & DAG , bool IsSRA ) const { +EVT VT = Op . getValueType ( ) ; +unsigned VTBits = VT . getSizeInBits ( ) ; +SDLoc DL ( Op ) ; +SDValue ShOpLo = Op . getOperand ( 0 ) ; +SDValue ShOpHi = Op . getOperand ( 1 ) ; +SDValue ShAmt = Op . getOperand ( 2 ) ; +unsigned Opc = ( Op . getOpcode ( ) == ISD :: SRA_PARTS ) ? ISD :: SRA : ISD :: SRL ; +SDValue RevShAmt = DAG . getNode ( ISD :: SUB , DL , MVT :: i64 , DAG . getConstant ( VTBits , DL , MVT :: i64 ) , ShAmt ) ; +SDValue Tmp1 = DAG . getNode ( ISD :: SRL , DL , VT , ShOpLo , ShAmt ) ; +SDValue ExtraShAmt = DAG . getNode ( ISD :: SUB , DL , MVT :: i64 , ShAmt , DAG . getConstant ( VTBits , DL , MVT :: i64 ) ) ; +SDValue Tmp2 = DAG . getNode ( ISD :: SHL , DL , VT , ShOpHi , RevShAmt ) ; +SDValue FalseVal = DAG . getNode ( ISD :: OR , DL , VT , Tmp1 , Tmp2 ) ; +SDValue TrueVal = DAG . getNode ( Opc , DL , VT , ShOpHi , ExtraShAmt ) ; +SDValue CCR = DAG . getRegister ( PULP :: CPSR , MVT :: i32 ) ; +SDValue Cmp = emitComparison ( ExtraShAmt , DAG . getConstant ( 0 , DL , MVT :: i64 ) , ISD :: SETGE , DL , DAG ) ; +SDValue CCVal = DAG . getConstant ( PULPCC :: GE , DL , MVT :: i32 ) ; +SDValue FalseValLo = DAG . getNode ( ISD :: OR , DL , VT , Tmp1 , Tmp2 ) ; +SDValue TrueValLo = DAG . getNode ( Opc , DL , VT , ShOpHi , ExtraShAmt ) ; +SDValue Lo = Op . getOperand ( 0 ) ; +SDValue FalseValHi = DAG . getNode ( Opc , DL , VT , ShOpHi , ShAmt ) ; +SDValue TrueValHi = Opc == ISD :: SRA ? DAG . getNode ( Opc , DL , VT , ShOpHi , DAG . getConstant ( VTBits - 1 , DL , MVT :: i64 ) ) : DAG . getConstant ( 0 , DL , VT ) ; +SDValue Hi = Op . getOperand ( 1 ) ; +SDValue Lo = DAG . getNode ( PULPISD :: CMOV , DL , VT , FalseVal , TrueVal , PULPcc , CCR , Cmp ) ; +SDValue Ops [ 2 ] = { Lo , Hi } ; +SDValue Lo = Op . getOperand ( 0 ) , Hi = Op . getOperand ( 1 ) ; +SDValue Shamt = Op . getOperand ( 2 ) ; +EVT VT = Lo . getValueType ( ) ; +unsigned ShiftRightOp = IsSRA ? ISD :: SRA : ISD :: SRL ; +SDValue Zero = DAG . getConstant ( 0 , DL , VT ) ; +SDValue One = DAG . getConstant ( 1 , DL , VT ) ; +SDValue MinusRegisterSize = DAG . getConstant ( - 32 , DL , VT ) ; +SDValue RegisterSizeMinus1 = DAG . getConstant ( 32 - 1 , DL , VT ) ; +SDValue ShamtMinusRegisterSize = DAG . getNode ( ISD :: ADD , DL , VT , Shamt , MinusRegisterSize ) ; +SDValue RegisterSizeMinus1Shamt = DAG . getNode ( ISD :: XOR , DL , VT , RegisterSizeMinus1 , Shamt ) ; +SDValue ShiftRightLo = DAG . getNode ( ISD :: SRL , DL , VT , Lo , Shamt ) ; +SDValue ShiftLeftHi1 = DAG . getNode ( ISD :: SHL , DL , VT , Hi , One ) ; +MVT VT = Subtarget . isGP64bit ( ) ? MVT :: i64 : MVT :: i32 ; +SDValue Not = DAG . getNode ( ISD :: XOR , DL , MVT :: i32 , Shamt , DAG . getConstant ( - 1 , MVT :: i32 ) ) ; +SDValue ShiftLeft1Hi = DAG . getNode ( ISD :: SHL , DL , VT , Hi , DAG . getConstant ( 1 , VT ) ) ; +SDValue ShiftLeftHi = DAG . getNode ( ISD :: SHL , DL , VT , ShiftLeftHi1 , RegisterSizeMinus1Shamt ) ; +SDValue LoTrue = DAG . getNode ( ISD :: OR , DL , VT , ShiftRightLo , ShiftLeftHi ) ; +SDValue HiTrue = DAG . getNode ( ShiftRightOp , DL , VT , Hi , Shamt ) ; +SDValue LoFalse = DAG . getNode ( ShiftRightOp , DL , VT , Hi , ShamtMinusRegisterSize ) ; +SDValue HiFalse = IsSRA ? DAG . getNode ( ISD :: SRA , DL , VT , Hi , RegisterSizeMinus1 ) : Zero ; +SDValue CC = DAG . getSetCC ( DL , MVT :: i8 , ShamtMinusRegisterSize , Zero , ISD :: SETLT ) ; +SDValue ShiftRightLo = DAG . getNode ( ISD :: SRL , DL , VT , Lo , Shamt ) ; +SDValue Or = DAG . getNode ( ISD :: OR , DL , VT , ShiftLeftHi , ShiftRightLo ) ; +SDValue ShiftRightHi = DAG . getNode ( IsSRA ? ISD :: SRA : ISD :: SRL , DL , VT , Hi , Shamt ) ; +SDValue Cond = DAG . getNode ( ISD :: AND , DL , MVT :: i32 , Shamt , DAG . getConstant ( VT . getSizeInBits ( ) , MVT :: i32 ) ) ; +SDValue Ext = DAG . getNode ( ISD :: SRA , DL , VT , Hi , DAG . getConstant ( VT . getSizeInBits ( ) - 1 , VT ) ) ; +Lo = DAG . getNode ( ISD :: SELECT , DL , VT , CC , LoTrue , LoFalse ) ; +Hi = DAG . getNode ( ISD :: SELECT , DL , VT , CC , HiTrue , HiFalse ) ; +SDValue Ops [ 2 ] = { Lo , Hi } ; +return DAG . getMergeValues (Parts , DL ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/lowerVectorMaskExt.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/lowerVectorMaskExt.cpp new file mode 100644 index 0000000000000000000000000000000000000000..64bb770e60ba8a1e654383a2649754db51f0a552 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/lowerVectorMaskExt.cpp @@ -0,0 +1,15 @@ +static SDValue PULPTargetLowering :: lowerVectorMaskExt ( SDValue Op , SelectionDAG & DAG , int64_t ExtTrueVal ) const { +SDLoc DL ( N ) ; +EVT VT = N -> getValueType ( 0 ) ; +if ( VT . getSizeInBits ( ) . getKnownMinSize ( ) != PULP :: SVEBitsPerBlock ) { +return SDValue ( ) ; +} +unsigned ElemSize = VT . getVectorElementType ( ) . getSizeInBits ( ) / 8 ; +unsigned ByteSize = VT . getSizeInBits ( ) . getKnownMinSize ( ) / 8 ; +EVT ByteVT = EVT :: getVectorVT ( Ctx , MVT :: i8 , { ByteSize , true } ) ; +if ( ! ST -> hasMVEFloatOps ( ) ) { +return SDValue ( ) ; +} +SDLoc DL ( BV ) ; +EVT VT = BV . getValueType ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/lowerVectorMaskTrunc.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/lowerVectorMaskTrunc.cpp new file mode 100644 index 0000000000000000000000000000000000000000..800493cf3c473611d53360e63c9b301b46c032f5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/lowerVectorMaskTrunc.cpp @@ -0,0 +1,33 @@ +SDValue PULPTargetLowering :: lowerVectorMaskTrunc ( SDValue Op , SelectionDAG & DAG ) const { +assert ( MaskVT . isVector ( ) && MaskVT . getVectorElementType ( ) == MVT :: i1 ) && "Unexpected type for vector mask lowering" ) ; +if ( ! ST -> hasMVEFloatOps ( ) ) { +return SDValue ( ) ; +SDLoc dl ( BV ) ; +if ( VT != MVT :: v8f16 ) { +return SDValue ( ) ; +if ( BV . getOperand ( 0 ) . getOpcode ( ) != ISD :: FP_ROUND ) { +return SDValue ( ) ; +if ( BV . getOperand ( 0 ) . getOperand ( 0 ) . getOpcode ( ) != ISD :: EXTRACT_VECTOR_ELT ) { +return SDValue ( ) ; +if ( BV . getOperand ( 0 ) . getOperand ( 0 ) . getConstantOperandVal ( 1 ) != 0 ) { +return SDValue ( ) ; +if ( BV . getOperand ( 1 ) . getOpcode ( ) != ISD :: FP_ROUND ) { +return SDValue ( ) ; +if ( BV . getOperand ( 1 ) . getOperand ( 0 ) . getOpcode ( ) != ISD :: EXTRACT_VECTOR_ELT ) { +return SDValue ( ) ; +if ( BV . getOperand ( 1 ) . getOperand ( 0 ) . getConstantOperandVal ( 1 ) != 0 ) { +return SDValue ( ) ; +SDValue Op0 = BV . getOperand ( 0 ) . getOperand ( 0 ) . getOperand ( 0 ) ; +SDValue Op1 = BV . getOperand ( 1 ) . getOperand ( 0 ) . getOperand ( 0 ) ; +if ( Op0 . getValueType ( ) != MVT :: v4f32 ) { +return SDValue ( ) ; +if ( Op1 . getValueType ( ) != MVT :: v4f32 ) { +return SDValue ( ) ; +for ( unsigned i = 1 ; i < 4 ; i ++ ) { +if ( ! Check ( BV . getOperand ( i * 2 + 0 ) , Op0 , i ) ) { +return SDValue ( ) ; +if ( ! Check ( BV . getOperand ( i * 2 + 1 ) , Op1 , i ) ) { +return SDValue ( ) ; +SDValue N1 = DAG . getNode ( PULPISD :: VCVTN , dl , VT , DAG . getUNDEF ( VT ) , Op0 , DAG . getConstant ( 0 , dl , MVT :: i32 ) ) ; +return DAG . getNode ( PULPISD :: VCVTN , dl , VT , N1 , Op1 , DAG . getConstant ( 1 , dl , MVT :: i32 ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/mayBeEmittedAsTailCall.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/mayBeEmittedAsTailCall.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b3ca378221a4d1b65e734cd3e2d93978dfe980ce --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/mayBeEmittedAsTailCall.cpp @@ -0,0 +1,6 @@ +bool PULPTargetLowering :: mayBeEmittedAsTailCall ( const CallInst * CI ) const { +if ( CI -> isTailCall ( ) ) { +return true ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/normaliseSetCC.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/normaliseSetCC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5e8ca14d17c2c96e01f50cf003b660fd552090a8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/normaliseSetCC.cpp @@ -0,0 +1,22 @@ +static void normaliseSetCC ( SDValue & LHS , SDValue & RHS , ISD :: CondCode & CC ) { +if ( CC == ISD :: SETGT ) { +CC = ISD :: getSetCCSwappedOperands ( CC ) ; +std :: swap ( LHS , RHS ) ; +return ; +} +if ( CC == ISD :: SETLE ) { +CC = ISD :: getSetCCSwappedOperands ( CC ) ; +std :: swap ( LHS , RHS ) ; +return ; +} +if ( CC == ISD :: SETUGT ) { +CC = ISD :: getSetCCSwappedOperands ( CC ) ; +std :: swap ( LHS , RHS ) ; +return ; +} +if ( CC == ISD :: SETULE ) { +CC = ISD :: getSetCCSwappedOperands ( CC ) ; +std :: swap ( LHS , RHS ) ; +return ; +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/normalizeSetCC.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/normalizeSetCC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f68f25a787d6d9d179404a12f57ee6bc55abf05a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/normalizeSetCC.cpp @@ -0,0 +1,2 @@ +static void normaliseSetCC(SDValue &LHS, SDValue &RHS, ISD::CondCode &CC) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/shouldConsiderGEPOffsetSplit.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/shouldConsiderGEPOffsetSplit.cpp new file mode 100644 index 0000000000000000000000000000000000000000..aea7b13466bda38ef605e932c0424e464e006d3c --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/shouldConsiderGEPOffsetSplit.cpp @@ -0,0 +1,3 @@ +bool shouldConsiderGEPOffsetSplit ( ) const override { +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/shouldConvertConstantLoadToIntImm.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/shouldConvertConstantLoadToIntImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c6c4f52e649ae4b4b1a72eabf7992953c6c65f9e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/shouldConvertConstantLoadToIntImm.cpp @@ -0,0 +1,3 @@ +bool shouldConvertConstantLoadToIntImm ( const APInt & Imm , Type * Ty ) const override { +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/shouldExpandAtomicCmpXchgInIR.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/shouldExpandAtomicCmpXchgInIR.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2aa225c436b3855dea54fb39ad09e7c595f7fad3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/shouldExpandAtomicCmpXchgInIR.cpp @@ -0,0 +1,10 @@ +TargetLowering :: AtomicExpansionKind PULPTargetLowering :: shouldExpandAtomicCmpXchgInIR ( AtomicCmpXchgInst * AI ) const { +unsigned Size = AI -> getCompareOperand ( ) -> getType ( ) -> getPrimitiveSizeInBits ( ) ; +if ( Size == 8 ) { +return AtomicExpansionKind :: MaskedIntrinsic ; +} +if ( Size == 16 ) { +return AtomicExpansionKind :: MaskedIntrinsic ; +} +return AtomicExpansionKind :: None ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/shouldExpandAtomicRMWInIR.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/shouldExpandAtomicRMWInIR.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fbd97b79bfb91e98e96322d3133ca9ec2266d436 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/shouldExpandAtomicRMWInIR.cpp @@ -0,0 +1,13 @@ +TargetLowering :: AtomicExpansionKind PULPTargetLowering :: shouldExpandAtomicRMWInIR ( AtomicRMWInst * AI ) const { +if ( AI -> isFloatingPointOperation ( ) ) { +return AtomicExpansionKind :: CmpXChg ; +} +unsigned Size = AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; +if ( Size == 8 ) { +return AtomicExpansionKind :: MaskedIntrinsic ; +} +if ( Size == 16 ) { +return AtomicExpansionKind :: MaskedIntrinsic ; +} +return AtomicExpansionKind :: None ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/shouldExpandShift.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/shouldExpandShift.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c810809a86725d91ae1c0fa0178381f6acebb69a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/shouldExpandShift.cpp @@ -0,0 +1,7 @@ +bool shouldExpandShift ( SelectionDAG & DAG , SDNode * N ) const override { +if ( DAG . getMachineFunction ( ) . getFunction ( ) . hasMinSize ( ) ) { +return false ; +return false ; +} +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/shouldExtendTypeInLibCall.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/shouldExtendTypeInLibCall.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e7a858a420453d330b766ad05a378a95a9c1fc8e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/shouldExtendTypeInLibCall.cpp @@ -0,0 +1,8 @@ +bool PULPTargetLowering :: shouldExtendTypeInLibCall ( EVT Type ) const { +if ( Subtarget . abiUsesSoftFloat ( ) ) { +if ( Type == MVT :: i32 ) { +return true ; +} +} +return IsSigned ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/shouldInsertFencesForAtomic.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/shouldInsertFencesForAtomic.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1428347bf80aab4226352f9fbf46158c4494c134 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/shouldInsertFencesForAtomic.cpp @@ -0,0 +1,3 @@ +bool shouldInsertFencesForAtomic ( const Instruction * I ) const override { +return isa < LoadInst > ( I ) || isa < StoreInst > ( I ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/shouldSignExtendTypeInLibCall.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/shouldSignExtendTypeInLibCall.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a2a0eea6065fa55bd62c7709f95648468f727949 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/shouldSignExtendTypeInLibCall.cpp @@ -0,0 +1,8 @@ +bool PULPTargetLowering :: shouldSignExtendTypeInLibCall ( EVT Type , bool IsSigned ) const { +if ( Subtarget . is64Bit ( ) ) { +if ( Type == MVT :: i32 ) { +return true ; +} +} +return IsSigned ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/targetShrinkDemandedConstant.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/targetShrinkDemandedConstant.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b7e8870f5dd0101633fd2ee54f9175ead8b7e19d --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/targetShrinkDemandedConstant.cpp @@ -0,0 +1,33 @@ +bool PULPTargetLowering :: targetShrinkDemandedConstant ( SDValue Op , const APInt & DemandedBits , const APInt & DemandedElts , TargetLoweringOpt & TLO ) const { +if ( ! TLO . LegalOps ) { +return false ; +} +EVT VT = Op . getValueType ( ) ; +if ( VT . isVector ( ) ) { +return false ; +} +if ( Op . getOpcode ( ) != ISD :: AND ) { +return false ; +} +unsigned Size = VT . getSizeInBits ( ) ; +ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op . getOperand ( 1 ) ) ; +if ( ! C ) { +return false ; +} +const APInt & Mask = C -> getAPIntValue ( ) ; +APInt ExpandedMask = Mask | ~ Demanded ; +if ( ShrunkMask == 0 ) { +return false ; +} +if ( ExpandedMask == ~ 0U ) { +return TLO . CombineTo ( Op , Op . getOperand ( 0 ) ) ; +} +if ( NewMask == Mask ) { +return true ; +} +return false ; +return false ; +SDLoc DL ( Op ) ; +SDValue NewOp = TLO . DAG . getNode ( ISD :: AND , DL , VT , Op . getOperand ( 0 ) , NewC ) ; +return TLO . CombineTo ( Op , NewOp ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/validateCCReservedRegs.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/validateCCReservedRegs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fafa5f6a2b05130d924fdb210802fe1676afd061 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/ISelLowering/validateCCReservedRegs.cpp @@ -0,0 +1,11 @@ +void PULPTargetLowering :: validateCCReservedRegs ( const SmallVectorImpl < std :: pair < llvm :: Register , llvm :: SDValue >> & Regs , MachineFunction & MF ) const { +auto * CA = dyn_cast < ConstantSDNode > ( Ptr ) ; +if ( ! CA ) { +return true ; +unsigned Addr = CA -> getZExtValue ( ) ; +return true ; +std :: string ErrMsg ; +raw_string_ostream O ( ErrMsg ) ; +if ( DebugLoc DL = dl . getDebugLoc ( ) ) { +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/InstructionSelector/InstructionSelector.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/InstructionSelector/InstructionSelector.cpp new file mode 100644 index 0000000000000000000000000000000000000000..53cc2835a41ac58f713da3322777b6baeda2bb12 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/InstructionSelector/InstructionSelector.cpp @@ -0,0 +1,9 @@ +RISCVInstructionSelector::RISCVInstructionSelector(const RISCVTargetMachine &TM, const RISCVSubtarget &STI,const RISCVRegisterBankInfo &RBI) : InstructionSelector(), STI(STI), TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()), RBI(RBI), +#define GET_GLOBALISEL_PREDICATES_INIT +#include "RISCVGenGlobalISel.inc" +#undef GET_GLOBALISEL_PREDICATES_INIT +#define GET_GLOBALISEL_TEMPORARIES_INIT +#include "RISCVGenGlobalISel.inc" +#undef GET_GLOBALISEL_TEMPORARIES_INIT +{ +} diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/InstructionSelector/createInstructionSelector.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/InstructionSelector/createInstructionSelector.cpp new file mode 100644 index 0000000000000000000000000000000000000000..36a916d86a6c0dd8d478ddf77801efb086d2d5d8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/InstructionSelector/createInstructionSelector.cpp @@ -0,0 +1,3 @@ +InstructionSelector * createPULPInstructionSelector ( const PULPTargetMachine & TM , PULPSubtarget & Subtarget , PULPRegisterBankInfo & RBI ) { +return new PULPInstructionSelector ( TM , Subtarget , RBI ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/InstructionSelector/getName.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/InstructionSelector/getName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..740b6f1fbb4a3afc4ded45f1aa79d0fb35ce8a43 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/InstructionSelector/getName.cpp @@ -0,0 +1,3 @@ +static const char * getName ( ) { +return DEBUG_TYPE ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/InstructionSelector/select.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/InstructionSelector/select.cpp new file mode 100644 index 0000000000000000000000000000000000000000..723dc3af215037e113da03fe158966f459da7741 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/InstructionSelector/select.cpp @@ -0,0 +1,9 @@ +bool PULPInstructionSelector :: select ( MachineInstr & I ) { +if ( ! isPreISelGenericOpcode ( I . getOpcode ( ) ) ) { +return true ; +} +if ( selectImpl ( I , * CoverageInfo ) ) { +return true ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/LegalizeInfo/LegalizerInfo.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/LegalizeInfo/LegalizerInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..785229528175cfa66168fa509b605449a41d45d4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/LegalizeInfo/LegalizerInfo.cpp @@ -0,0 +1,3 @@ +PULPLegalizerInfo :: PULPLegalizerInfo ( const PULPSubtarget & ST ) { +computeTables ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/MCInstLower/lowerMachineInstrToMCInst.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/MCInstLower/lowerMachineInstrToMCInst.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e7c5990a18b07e178c2bbb5817ccee060a72bfb7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/MCInstLower/lowerMachineInstrToMCInst.cpp @@ -0,0 +1,13 @@ +void llvm :: LowerMachineInstrToMCInst ( const MachineInstr * MI , MCInst & OutMI , const AsmPrinter & AP ) { +OutMI . setOpcode ( MI -> getOpcode ( ) ) ; +for ( const MachineOperand & MO : MI -> operands ( ) ) { +MCOperand MCOp ; +if ( MCOp . isValid ( ) ) { +OutMI . addOperand ( LowerOperand ( MI , MO , AP ) ) ; +} +LowerMachineOperandToMCOperand ( MO , MCOp , AP ) ; +if ( LowerMachineOperandToMCOperand ( MO , MCOp , AP ) ) { +OutMI . addOperand ( MCOp ) ; +} +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/MCInstLower/lowerMachineOperandToMCOperand.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/MCInstLower/lowerMachineOperandToMCOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0f0533765f5ac434785b9d1a7a84045a27a59004 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/MCInstLower/lowerMachineOperandToMCOperand.cpp @@ -0,0 +1,41 @@ +bool llvm :: LowerPULPMachineOperandToMCOperand ( const MachineOperand & MO , MCOperand & MCOp , const AsmPrinter & AP ) { +if ( MO . getType ( ) == MachineOperand :: MO_ConstantPoolIndex ) { +MCOp = lowerSymbolOperand ( MO , AP . GetCPISymbol ( MO . getIndex ( ) ) , AP ) ; +return true ; +} +if ( MO . getType ( ) == MachineOperand :: MO_JumpTableIndex ) { +MCOp = lowerSymbolOperand ( MO , AP . GetJTISymbol ( MO . getIndex ( ) ) , AP ) ; +return true ; +} +if ( MO . getType ( ) == MachineOperand :: MO_Register ) { +if ( MO . isImplicit ( ) ) { +return false ; +} +MCOp = MCOperand :: createReg ( MO . getReg ( ) ) ; +return true ; +} +if ( MO . getType ( ) == MachineOperand :: MO_Immediate ) { +MCOp = MCOperand :: createImm ( MO . getImm ( ) ) ; +return true ; +} +if ( MO . getType ( ) == MachineOperand :: MO_RegisterMask ) { +return false ; +} +if ( MO . getType ( ) == MachineOperand :: MO_MachineBasicBlock ) { +MCOp = lowerSymbolOperand ( MO , MO . getMBB ( ) -> getSymbol ( ) , AP ) ; +return true ; +} +if ( MO . getType ( ) == MachineOperand :: MO_GlobalAddress ) { +MCOp = lowerSymbolOperand ( MO , AP . getSymbol ( MO . getGlobal ( ) ) , AP ) ; +return true ; +} +if ( MO . getType ( ) == MachineOperand :: MO_BlockAddress ) { +MCOp = lowerSymbolOperand ( MO , AP . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) , AP ) ; +return true ; +} +if ( MO . getType ( ) == MachineOperand :: MO_ExternalSymbol ) { +MCOp = lowerSymbolOperand ( MO , AP . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) , AP ) ; +return true ; +} +report_fatal_error ( "LowerPULPMachineInstrToMCInst: unknown operand type" ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/MCInstLower/lowerSymbolOperand.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/MCInstLower/lowerSymbolOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..47b4acba43b53387df33f0c6a777c8b529f855a4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/PULP/Selection/MCInstLower/lowerSymbolOperand.cpp @@ -0,0 +1,65 @@ +static MCOperand lowerSymbolOperand ( const MachineOperand & MO , MCSymbol * Sym , const AsmPrinter & AP ) { +MCContext & Ctx = AP . OutContext ; +const MCExpr * Expr = nullptr ; +Expr = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_PULP_None , Ctx ) ; +if ( ! MO . isJTI ( ) ) { +if ( ! MO . isMBB ( ) ) { +if ( MO . getOffset ( ) ) { +Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( MO . getOffset ( ) , Ctx ) , Ctx ) ; +} +} +} +if ( MO . getTargetFlags ( ) == PULPII :: MO_CALL ) { +Expr = PULPMCExpr :: create ( Expr , PULPMCExpr :: VK_CALL , Ctx ) ; +return MCOperand :: createExpr ( Expr ) ; +} +if ( MO . getTargetFlags ( ) == PULPII :: MO_PLT ) { +Expr = PULPMCExpr :: create ( Expr , PULPMCExpr :: VK_CALL_PLT , Ctx ) ; +return MCOperand :: createExpr ( Expr ) ; +} +if ( MO . getTargetFlags ( ) == PULPII :: MO_LO ) { +Expr = PULPMCExpr :: create ( Expr , PULPMCExpr :: VK_PULP_LO , Ctx ) ; +return MCOperand :: createExpr ( Expr ) ; +} +if ( MO . getTargetFlags ( ) == PULPII :: MO_HI ) { +Expr = PULPMCExpr :: create ( Expr , PULPMCExpr :: VK_HI , Ctx ) ; +return MCOperand :: createExpr ( Expr ) ; +} +if ( MO . getTargetFlags ( ) == PULPII :: MO_PCREL_LO ) { +Expr = PULPMCExpr :: create ( Expr , PULPMCExpr :: VK_PCREL_LO , Ctx ) ; +return MCOperand :: createExpr ( Expr ) ; +} +if ( MO . getTargetFlags ( ) == PULPII :: MO_PCREL_HI ) { +Expr = PULPMCExpr :: create ( Expr , PULPMCExpr :: VK_PCREL_HI , Ctx ) ; +return MCOperand :: createExpr ( Expr ) ; +} +if ( MO . getTargetFlags ( ) == PULPII :: MO_GOT_HI ) { +Expr = PULPMCExpr :: create ( Expr , PULPMCExpr :: VK_GOT_HI , Ctx ) ; +return MCOperand :: createExpr ( Expr ) ; +} +if ( MO . getTargetFlags ( ) == PULPII :: MO_TPREL_LO ) { +Expr = PULPMCExpr :: create ( Expr , PULPMCExpr :: VK_TPREL_LO , Ctx ) ; +return MCOperand :: createExpr ( Expr ) ; +} +if ( MO . getTargetFlags ( ) == PULPII :: MO_TPREL_HI ) { +Expr = PULPMCExpr :: create ( Expr , PULPMCExpr :: VK_TPREL_HI , Ctx ) ; +return MCOperand :: createExpr ( Expr ) ; +} +if ( MO . getTargetFlags ( ) == PULPII :: MO_TPREL_ADD ) { +Expr = PULPMCExpr :: create ( Expr , PULPMCExpr :: VK_TPREL_ADD , Ctx ) ; +return MCOperand :: createExpr ( Expr ) ; +} +if ( MO . getTargetFlags ( ) == PULPII :: MO_TLS_GOT_HI ) { +Expr = PULPMCExpr :: create ( Expr , PULPMCExpr :: VK_TLS_GOT_HI , Ctx ) ; +return MCOperand :: createExpr ( Expr ) ; +} +if ( MO . getTargetFlags ( ) == PULPII :: MO_TLS_GD_HI ) { +Expr = PULPMCExpr :: create ( Expr , PULPMCExpr :: VK_TLS_GD_HI , Ctx ) ; +return MCOperand :: createExpr ( Expr ) ; +} +if ( MO . getTargetFlags ( ) == PULPII :: MO_None ) { +return MCOperand :: createExpr ( Expr ) ; +} +llvm_unreachable ( "Unknown target flag on GV operand" ) ; +return MCOperand :: createExpr ( Expr ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Allocation/RegisterBankInfo/RegisterBankInfo.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Allocation/RegisterBankInfo/RegisterBankInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1add09d08880f2db739eefe2393f190a9eaca8a3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Allocation/RegisterBankInfo/RegisterBankInfo.cpp @@ -0,0 +1,2 @@ +RISCVRegisterBankInfo :: RISCVRegisterBankInfo ( const TargetRegisterInfo & TRI ) : RISCVGenRegisterBankInfo ( ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Allocation/RegisterInfo/RegisterInfo.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Allocation/RegisterInfo/RegisterInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f79fc08b171f29239f4cd187430f5f1dc491d328 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Allocation/RegisterInfo/RegisterInfo.cpp @@ -0,0 +1,2 @@ +RISCVRegisterInfo :: RISCVRegisterInfo ( unsigned HwMode ) : RISCVGenRegisterInfo ( RISCV :: X1 , 0 , 0 , 0 , HwMode ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Allocation/RegisterInfo/eliminateFrameIndex.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Allocation/RegisterInfo/eliminateFrameIndex.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6e71132e0611a4fc2affa7eb3d92dcdc248ece51 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Allocation/RegisterInfo/eliminateFrameIndex.cpp @@ -0,0 +1,23 @@ +void RISCVRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { +assert ( SPAdj == 0 && "Unexpected non-zero SPAdj value" ) ; +MachineInstr & MI = * II ; +MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; +MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; +DebugLoc DL = MI . getDebugLoc ( ) ; +const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; +DebugLoc dl = MI . getDebugLoc ( ) ; +int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; +Register FrameReg ; +int Offset = getFrameLowering ( MF ) -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) + MI . getOperand ( FIOperandNum + 1 ) . getImm ( ) ; +if ( ! isInt < 16 > ( Offset ) ) { +report_fatal_error ( "Frame offsets outside of the signed 16-bit range not supported" ) ; +} +MachineBasicBlock & MBB = * MI . getParent ( ) ; +unsigned DstReg = MI . getOperand ( 0 ) . getReg ( ) ; +int64_t spOffset = MF . getFrameInfo ( ) -> getObjectOffset ( frameIndex ) ; +bool FrameRegIsKill = true ; +int64_t Offset = spOffset + ( int64_t ) stackSize ; +MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false , false , FrameRegIsKill ) ; +MI . getOperand ( FIOperandNum + 1 ) . ChangeToImmediate ( Offset ) ; +MI . getOperand ( OffsetOperandNo ) . ChangeToImmediate ( Offset ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Allocation/RegisterInfo/getCallPreservedMask.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Allocation/RegisterInfo/getCallPreservedMask.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e7240a6a9dab8ad35a7b79f780aa47e7babe7008 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Allocation/RegisterInfo/getCallPreservedMask.cpp @@ -0,0 +1,24 @@ +const uint32_t * RISCVRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { +if ( CC == CallingConv :: GHC ) { +return CSR_NoRegs_RegMask ; +} +if ( Subtarget . getTargetABI ( ) == RISCVABI :: ABI_ILP32 ) { +return CSR_ILP32_LP64_RegMask ; +} +if ( Subtarget . getTargetABI ( ) == RISCVABI :: ABI_LP64 ) { +return CSR_ILP32_LP64_RegMask ; +} +if ( Subtarget . getTargetABI ( ) == RISCVABI :: ABI_ILP32F ) { +return CSR_ILP32F_LP64F_RegMask ; +} +if ( Subtarget . getTargetABI ( ) == RISCVABI :: ABI_LP64F ) { +return CSR_ILP32F_LP64F_RegMask ; +} +if ( Subtarget . getTargetABI ( ) == RISCVABI :: ABI_ILP32D ) { +return CSR_ILP32D_LP64D_RegMask ; +} +if ( Subtarget . getTargetABI ( ) == RISCVABI :: ABI_LP64D ) { +return CSR_ILP32D_LP64D_RegMask ; +} +llvm_unreachable ( "Unrecognized ABI" ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Allocation/RegisterInfo/getCalleeSavedRegs.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Allocation/RegisterInfo/getCalleeSavedRegs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4ec26207993da3434ec1d081707da2360dd52b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Allocation/RegisterInfo/getCalleeSavedRegs.cpp @@ -0,0 +1,34 @@ +const MCPhysReg * RISCVRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { +auto & Subtarget = MF -> getSubtarget < RISCVSubtarget > ( ) ; +if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: GHC ) { +return CSR_NoRegs_SaveList ; +} +if ( MF -> getFunction ( ) . hasFnAttribute ( "interrupt" ) ) { +if ( Subtarget . hasStdExtD ( ) ) { +return CSR_XLEN_F64_Interrupt_SaveList ; +} +if ( Subtarget . hasStdExtF ( ) ) { +return CSR_XLEN_F32_Interrupt_SaveList ; +} +return CSR_Interrupt_SaveList ; +} +if ( Subtarget . getTargetABI ( ) == RISCVABI :: ABI_ILP32 ) { +return CSR_ILP32_LP64_SaveList ; +} +if ( Subtarget . getTargetABI ( ) == RISCVABI :: ABI_LP64 ) { +return CSR_ILP32_LP64_SaveList ; +} +if ( Subtarget . getTargetABI ( ) == RISCVABI :: ABI_ILP32F ) { +return CSR_ILP32F_LP64F_SaveList ; +} +if ( Subtarget . getTargetABI ( ) == RISCVABI :: ABI_LP64F ) { +return CSR_ILP32F_LP64F_SaveList ; +} +if ( Subtarget . getTargetABI ( ) == RISCVABI :: ABI_ILP32D ) { +return CSR_ILP32D_LP64D_SaveList ; +} +if ( Subtarget . getTargetABI ( ) == RISCVABI :: ABI_LP64D ) { +return CSR_ILP32D_LP64D_SaveList ; +} +llvm_unreachable ( "Unrecognized ABI" ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Allocation/RegisterInfo/getFrameRegister.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Allocation/RegisterInfo/getFrameRegister.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0d1da0f9acab65b2533040e7a58d12abada064ea --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Allocation/RegisterInfo/getFrameRegister.cpp @@ -0,0 +1,4 @@ +Register RISCVRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { +const TargetFrameLowering * TFI = getFrameLowering ( MF ) ; +return TFI -> hasFP ( MF ) ? RISCV :: X8 : RISCV :: X2 ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Allocation/RegisterInfo/getNoPreservedMask.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Allocation/RegisterInfo/getNoPreservedMask.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ed18e1e23c8b7323a731c98382757d9b66fe6247 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Allocation/RegisterInfo/getNoPreservedMask.cpp @@ -0,0 +1,3 @@ +const uint32_t * RISCVRegisterInfo :: getNoPreservedMask ( ) const { +return CSR_NoRegs_RegMask ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Allocation/RegisterInfo/getPointerRegClass.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Allocation/RegisterInfo/getPointerRegClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..742e55bdbc0ddd13dd295ae57342172fec5ebf79 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Allocation/RegisterInfo/getPointerRegClass.cpp @@ -0,0 +1,3 @@ +const TargetRegisterClass * getPointerRegClass ( const MachineFunction & MF , unsigned Kind = 0 ) const override { +return & RISCV :: GPRRegClass ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Allocation/RegisterInfo/getReservedRegs.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Allocation/RegisterInfo/getReservedRegs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cd8a250163b184f365310dbb6fc8ef74ac264527 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Allocation/RegisterInfo/getReservedRegs.cpp @@ -0,0 +1,25 @@ +BitVector RISCVRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { +const RISCVFrameLowering * TFI = getFrameLowering ( MF ) ; +BitVector Reserved ( getNumRegs ( ) ) ; +for ( size_t Reg = 0 ; Reg < getNumRegs ( ) ; Reg ++ ) { +if ( MF . getSubtarget < RISCVSubtarget > ( ) . isRegisterReservedByUser ( Reg ) ) { +markSuperRegs ( Reserved , Reg ) ; +} +} +if ( TFI -> hasBP ( MF ) ) { +markSuperRegs ( Reserved , RISCV :: X9 ) ; +} +if ( TFI -> hasFP ( MF ) ) { +markSuperRegs ( Reserved , RISCV :: X8 ) ; +} +markSuperRegs ( Reserved , RISCV :: X0 ) ; +markSuperRegs ( Reserved , RISCV :: X2 ) ; +markSuperRegs ( Reserved , RISCV :: X3 ) ; +markSuperRegs ( Reserved , RISCV :: X4 ) ; +markSuperRegs ( Reserved , RISCV :: VL ) ; +markSuperRegs ( Reserved , RISCV :: VTYPE ) ; +markSuperRegs ( Reserved , RISCV :: VXSAT ) ; +markSuperRegs ( Reserved , RISCV :: VXRM ) ; +assert ( checkAllSuperRegsMarked ( Reserved ) ) ; +return Reserved ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Allocation/RegisterInfo/hasReservedSpillSlot.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Allocation/RegisterInfo/hasReservedSpillSlot.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e77772edeb88ec5519eda06ec4fa73fdb724b462 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Allocation/RegisterInfo/hasReservedSpillSlot.cpp @@ -0,0 +1,6 @@ +bool RISCVRegisterInfo :: hasReservedSpillSlot ( const MachineFunction & MF , Register Reg , int & FrameIdx ) const { +const auto * FI = MF . getInfo < RISCVMachineFunctionInfo > ( ) ; +FrameIdx = FI -> getCRSpillFrameIndex ( ) ; +return true ; +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Allocation/RegisterInfo/isAsmClobberable.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Allocation/RegisterInfo/isAsmClobberable.cpp new file mode 100644 index 0000000000000000000000000000000000000000..beafac1ae15d09ff2d6444f0795e271d38248a08 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Allocation/RegisterInfo/isAsmClobberable.cpp @@ -0,0 +1,3 @@ +bool RISCVRegisterInfo :: isAsmClobberable ( const MachineFunction & MF , MCRegister PhysReg ) const { +return ! MF . getSubtarget < RISCVSubtarget > ( ) . isRegisterReservedByUser ( PhysReg ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Allocation/RegisterInfo/isConstantPhysReg.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Allocation/RegisterInfo/isConstantPhysReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f311d54adc36039b21a9a9e4c68202d764756e8a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Allocation/RegisterInfo/isConstantPhysReg.cpp @@ -0,0 +1,5 @@ +bool RISCVRegisterInfo :: isConstantPhysReg ( MCRegister PhysReg ) const { +if ( PhysReg == RISCV :: X0 ) { +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Allocation/RegisterInfo/requiresFrameIndexScavenging.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Allocation/RegisterInfo/requiresFrameIndexScavenging.cpp new file mode 100644 index 0000000000000000000000000000000000000000..91452a8e068d51b582b56820d11be174835fb85a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Allocation/RegisterInfo/requiresFrameIndexScavenging.cpp @@ -0,0 +1,3 @@ +bool requiresFrameIndexScavenging ( const MachineFunction & MF ) const override { +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Allocation/RegisterInfo/requiresRegisterScavenging.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Allocation/RegisterInfo/requiresRegisterScavenging.cpp new file mode 100644 index 0000000000000000000000000000000000000000..be9254bdaf75d4ec168e9353281ffdaf92a1c0f6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Allocation/RegisterInfo/requiresRegisterScavenging.cpp @@ -0,0 +1,3 @@ +bool requiresRegisterScavenging ( const MachineFunction & MF ) const override { +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/AsmParser.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/AsmParser.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a86c5a557236794fde26bd984c155fdd246cc4f8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/AsmParser.cpp @@ -0,0 +1,7 @@ +RISCVAsmParser ( const MCSubtargetInfo & STI , MCAsmParser & Parser , const MCInstrInfo & MII , const MCTargetOptions & Options ) : MCTargetAsmParser ( Options , STI , MII ) { +Parser . addAliasForDirective ( ".half" , ".2byte" ) ; +Parser . addAliasForDirective ( ".hword" , ".2byte" ) ; +Parser . addAliasForDirective ( ".word" , ".4byte" ) ; +Parser . addAliasForDirective ( ".dword" , ".8byte" ) ; +setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/KindTy.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/KindTy.cpp new file mode 100644 index 0000000000000000000000000000000000000000..26577a75b88d8eaab0fd8482d40f85ef7b9af5c0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/KindTy.cpp @@ -0,0 +1,7 @@ +enum class KindTy { +Token , +Register , +Immediate , +SystemRegister , +VType , +} Kind ; \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/LLVMInitializeAsmParser.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/LLVMInitializeAsmParser.cpp new file mode 100644 index 0000000000000000000000000000000000000000..192e316f9c13c0a47d1c73e87fb4cde3ecc85f5e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/LLVMInitializeAsmParser.cpp @@ -0,0 +1,4 @@ +extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVAsmParser ( ) { +RegisterMCAsmParser < RISCVAsmParser > X ( getTheRISCV32Target ( ) ) ; +RegisterMCAsmParser < RISCVAsmParser > Y ( getTheRISCV64Target ( ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/MatchAndEmitInstruction.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/MatchAndEmitInstruction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f57f3b02768f7166fc1eda00735ec9416eeb2930 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/MatchAndEmitInstruction.cpp @@ -0,0 +1,166 @@ +bool RISCVAsmParser :: MatchAndEmitInstruction ( SMLoc IDLoc , unsigned & Opcode , OperandVector & Operands , MCStreamer & Out , uint64_t & ErrorInfo , bool MatchingInlineAsm ) { +MCInst Inst ; +FeatureBitset MissingFeatures ; +auto Result = MatchInstructionImpl ( Operands , Inst , ErrorInfo , MissingFeatures , MatchingInlineAsm ) ; +if ( Result == Match_Success ) { +if ( validateInstruction ( Inst , Operands ) ) { +return true ; +} +return processInstruction ( Inst , IDLoc , Operands , Out ) ; +} +if ( Result == Match_MissingFeature ) { +assert ( MissingFeatures . any ( ) && "Unknown missing features!" ) ; +bool FirstFeature = true ; +std :: string Msg = "instruction requires the following:" ; +for ( unsigned i = 0 , e = MissingFeatures . size ( ) ; i != e ; ++ i ) { +if ( MissingFeatures [ i ] ) { +Msg = Msg + FirstFeature ? " " : ", " ; +Msg = Msg + getSubtargetFeatureName ( i ) ; +FirstFeature = false ; +} +} +return Error ( IDLoc , Msg ) ; +} +if ( Result == Match_MnemonicFail ) { +FeatureBitset FBS = ComputeAvailableFeatures ( getSTI ( ) . getFeatureBits ( ) ) ; +std :: string Suggestion = RISCVMnemonicSpellCheck ( ( ( RISCVOperand & ) * Operands [ 0 ] ) . getToken ( ) , FBS ) ; +return Error ( IDLoc , "unrecognized instruction mnemonic" + Suggestion ) ; +} +if ( Result == Match_InvalidOperand ) { +SMLoc ErrorLoc = IDLoc ; +if ( ErrorInfo != ~ 0ULL ) { +if ( ErrorInfo >= Operands . size ( ) ) { +return Error ( ErrorLoc , "too few operands for instruction" ) ; +} +ErrorLoc = ( ( RISCVOperand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; +if ( ErrorLoc == SMLoc ( ) ) { +ErrorLoc = IDLoc ; +} +} +return Error ( ErrorLoc , "invalid operand for instruction" ) ; +} +if ( Result > FIRST_TARGET_MATCH_RESULT_TY ) { +SMLoc ErrorLoc = IDLoc ; +if ( ErrorInfo != ~ 0ULL ) { +if ( ErrorInfo >= Operands . size ( ) ) { +return Error ( ErrorLoc , "too few operands for instruction" ) ; +} +} +} +if ( Result == Match_RequiresMsbNotLessThanLsb ) { +SMLoc ErrorStart = Operands [ 3 ] -> getStartLoc ( ) ; +return Error ( ErrorStart , "msb is less than lsb" , SMRange ( ErrorStart , Operands [ 4 ] -> getEndLoc ( ) ) ) ; +} +if ( Result == Match_RequiresOpnd2NotR0R1 ) { +return Error ( Operands [ 2 ] -> getStartLoc ( ) , "must not be $r0 or $r1" ) ; +} +if ( Result == Match_InvalidUImm2 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , 0 , ( 1 << 2 ) - 1 ) ; +} +if ( Result == Match_InvalidUImm2plus1 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , 1 , ( 1 << 2 ) ) ; +} +if ( Result == Match_InvalidUImm3 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , 0 , ( 1 << 3 ) - 1 ) ; +} +if ( Result == Match_InvalidUImm5 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , 0 , ( 1 << 5 ) - 1 ) ; +} +if ( Result == Match_InvalidUImm6 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , 0 , ( 1 << 6 ) - 1 ) ; +} +if ( Result == Match_InvalidUImm12 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , 0 , ( 1 << 12 ) - 1 ) ; +} +if ( Result == Match_InvalidUImm15 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , 0 , ( 1 << 15 ) - 1 ) ; +} +if ( Result == Match_InvalidUImm15 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , 0 , ( 1 << 15 ) - 1 ) ; +} +if ( Result == Match_InvalidUImm15 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , 0 , ( 1 << 15 ) - 1 ) ; +} +if ( Result == Match_InvalidUImm15 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , 0 , ( 1 << 15 ) - 1 ) ; +} +if ( Result == Match_InvalidUImm15 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , 0 , ( 1 << 15 ) - 1 ) ; +} +if ( Result == Match_InvalidUImm15 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , 0 , ( 1 << 15 ) - 1 ) ; +} +if ( Result == Match_InvalidSImm12 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( 1 << 11 ) , ( 1 << 11 ) - 1 ) ; +} +if ( Result == Match_InvalidSImm12 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( 1 << 11 ) , ( 1 << 11 ) - 1 ) ; +} +if ( Result == Match_InvalidSImm12 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( 1 << 11 ) , ( 1 << 11 ) - 1 ) ; +} +if ( Result == Match_InvalidSImm12 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( 1 << 11 ) , ( 1 << 11 ) - 1 ) ; +} +if ( Result == Match_InvalidSImm12 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( 1 << 11 ) , ( 1 << 11 ) - 1 ) ; +} +if ( Result == Match_InvalidSImm14lsl2 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( 1 << 15 ) , ( 1 << 15 ) - 1 , "immediate must be a multiple of 4 in the range" ) ; +} +if ( Result == Match_InvalidSImm16 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( 1 << 15 ) , ( 1 << 15 ) - 1 ) ; +} +if ( Result == Match_InvalidSImm16lsl2 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( 1 << 17 ) , ( 1 << 17 ) - 1 , "immediate must be a multiple of 4 in the range" ) ; +} +if ( Result == Match_InvalidSImm16lsl2 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( 1 << 17 ) , ( 1 << 17 ) - 1 , "immediate must be a multiple of 4 in the range" ) ; +} +if ( Result == Match_InvalidSImm16lsl2 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( 1 << 17 ) , ( 1 << 17 ) - 1 , "immediate must be a multiple of 4 in the range" ) ; +} +if ( Result == Match_InvalidSImm16lsl2 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( 1 << 17 ) , ( 1 << 17 ) - 1 , "immediate must be a multiple of 4 in the range" ) ; +} +if ( Result == Match_InvalidSImm16lsl2 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( 1 << 17 ) , ( 1 << 17 ) - 1 , "immediate must be a multiple of 4 in the range" ) ; +} +if ( Result == Match_InvalidSImm16lsl2 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( 1 << 17 ) , ( 1 << 17 ) - 1 , "immediate must be a multiple of 4 in the range" ) ; +} +if ( Result == Match_InvalidSImm20 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( 1 << 19 ) , ( 1 << 19 ) - 1 ) ; +} +if ( Result == Match_InvalidSImm21lsl2 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( 1 << 22 ) , ( 1 << 22 ) - 4 , "immediate must be a multiple of 4 in the range" ) +} +if ( Result == Match_InvalidSImm21lsl2 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( 1 << 22 ) , ( 1 << 22 ) - 4 , "immediate must be a multiple of 4 in the range" ) +} +if ( Result == Match_InvalidSImm21lsl2 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( 1 << 22 ) , ( 1 << 22 ) - 4 , "immediate must be a multiple of 4 in the range" ) +} +if ( Result == Match_InvalidSImm26lsl2 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( 1 << 27 ) , ( 1 << 27 ) - 4 , "immediate must be a multiple of 4 in the range" ) ; +} +if ( Result == Match_InvalidSImm26lsl2 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( 1 << 27 ) , ( 1 << 27 ) - 4 , "immediate must be a multiple of 4 in the range" ) ; +} +if ( Result == Match_InvalidSImm26lsl2 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( 1 << 27 ) , ( 1 << 27 ) - 4 , "immediate must be a multiple of 4 in the range" ) ; +} +if ( Result == Match_InvalidSImm26lsl2 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( 1 << 27 ) , ( 1 << 27 ) - 4 , "immediate must be a multiple of 4 in the range" ) ; +} +if ( Result == Match_InvalidSImm26lsl2 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( 1 << 27 ) , ( 1 << 27 ) - 4 , "immediate must be a multiple of 4 in the range" ) ; +} +if ( Result == Match_InvalidSImm26lsl2 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( 1 << 27 ) , ( 1 << 27 ) - 4 , "immediate must be a multiple of 4 in the range" ) ; +} +if ( Result == Match_InvalidSImm26lsl2 ) { +return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( 1 << 27 ) , ( 1 << 27 ) - 4 , "immediate must be a multiple of 4 in the range" ) ; +} +llvm_unreachable ( "Unknown match type detected!" ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/Operand.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/Operand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fa4acadd0b0b5bf6a3b5c36a8fee02f45e28be93 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/Operand.cpp @@ -0,0 +1,2 @@ +RISCVOperand ( KindTy K ) : MCParsedAsmOperand ( ) , Kind ( K ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/Operand2.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/Operand2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..086baba405c7dc571781a34231424e8f88aec36f --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/Operand2.cpp @@ -0,0 +1,16 @@ +RISCVOperand ( const RISCVOperand & o ) : MCParsedAsmOperand ( ) { +Kind = o . Kind ; +StartLoc = o . StartLoc ; +EndLoc = o . EndLoc ; +if ( Kind == KindTy :: Register ) { +Reg = o . Reg ; +} +if ( Kind == KindTy :: Immediate ) { +} +if ( Kind == KindTy :: Token ) { +} +if ( Kind == KindTy :: SystemRegister ) { +} +if ( Kind == KindTy :: VType ) { +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/ParseDirective.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/ParseDirective.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3db3fed1932a2e522de573f811c2594bfc35e130 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/ParseDirective.cpp @@ -0,0 +1,10 @@ +bool RISCVAsmParser :: ParseDirective ( AsmToken DirectiveID ) { +StringRef IDVal = DirectiveID . getString ( ) ; +if ( IDVal == ".option" ) { +return ParseDirectiveHSACodeObjectVersion ( ) ; +} +if ( IDVal == ".attribute" ) { +return ParseDirectiveHSACodeObjectISA ( ) ; +} +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/ParseInstruction.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/ParseInstruction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..39de644cbfebfa23c47161c1c06301a1b733d382 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/ParseInstruction.cpp @@ -0,0 +1,22 @@ +bool RISCVAsmParser :: ParseInstruction ( ParseInstructionInfo & Info , StringRef Name , SMLoc NameLoc , OperandVector & Operands ) { +Operands . push_back ( RISCVOperand :: createToken ( Name , NameLoc ) ) ; +if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) { +return false ; +} +if ( parseOperand ( Operands ) ) { +return true ; +} +for ( ; getLexer ( ) . is ( AsmToken :: Comma ) ; ) { +getLexer ( ) . Lex ( ) ; +if ( parseOperand ( Operands ) ) { +return true ; +} +} +if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { +SMLoc Loc = getLexer ( ) . getLoc ( ) ; +getParser ( ) . eatToEndOfStatement ( ) ; +return Error ( Loc , "unexpected token" ) ; +} +getParser ( ) . Lex ( ) ; +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/ParseRegister.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/ParseRegister.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f2f165eeb5dd80092bfd0eac08bd4ba9f623891c --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/ParseRegister.cpp @@ -0,0 +1,6 @@ +bool RISCVAsmParser :: ParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc ) { +if ( tryParseRegister ( RegNo , StartLoc , EndLoc ) != MatchOperand_Success ) { +return Error ( StartLoc , "invalid register name" ) ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/addCSRSystemRegisterOperands.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/addCSRSystemRegisterOperands.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6b014312f9d2f313df503bedb185eeb4e023460b --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/addCSRSystemRegisterOperands.cpp @@ -0,0 +1,4 @@ +void addCSRSystemRegisterOperands ( MCInst & Inst , unsigned N ) const { +assert ( N == 1 && "Invalid number of operands!" ) ; +Inst . addOperand ( MCOperand :: createImm ( SysReg . Encoding ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/addExpr.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/addExpr.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7d49a50577b415d6d67804de0d5a2e050afd3b52 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/addExpr.cpp @@ -0,0 +1,12 @@ +void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { +assert ( Expr && "Expr shouldn't be null!" ) ; +int64_t Imm = 0 ; +RISCVMCExpr :: VariantKind VK = RISCVMCExpr :: VK_RISCV_None ; +bool IsConstant = evaluateConstantImm ( Expr , Imm , VK ) ; +if ( IsConstant ) { +Inst . addOperand ( MCOperand :: createImm ( Imm ) ) ; +} +if ( ! IsConstant ) { +Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ; +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/addFRMArgOperands.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/addFRMArgOperands.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1c7cefcbc2a13fab240d8157c57ba776c7be3f75 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/addFRMArgOperands.cpp @@ -0,0 +1,4 @@ +void addFRMArgOperands ( MCInst & Inst , unsigned N ) const { +assert ( N == 1 && "Invalid number of operands!" ) ; +Inst . addOperand ( MCOperand :: createImm ( getRoundingMode ( ) ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/addFenceArgOperands.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/addFenceArgOperands.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4568edfef1f2d1cd993ef7944449029b211f1b7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/addFenceArgOperands.cpp @@ -0,0 +1,6 @@ +void addFenceArgOperands ( MCInst & Inst , unsigned N ) const { +assert ( N == 1 && "Invalid number of operands!" ) ; +const MCConstantExpr * CE = cast < MCConstantExpr > ( getImm ( ) ) ; +unsigned RegNum = getCondCode ( ) == RISCVCC :: AL ? 0 : RISCV :: CPSR ; +Inst . addOperand ( MCOperand :: createReg ( RegNum ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/addImmOperands.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/addImmOperands.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8eba21454fa5e4a4bfc9ff898d4e04daf6f0ea8b --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/addImmOperands.cpp @@ -0,0 +1,4 @@ +void addImmOperands ( MCInst & Inst , unsigned N ) const { +assert ( N == 1 && "Invalid number of operands!" ) ; +addExpr ( Inst , getImm ( ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/addRegOperands.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/addRegOperands.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b214ebb9cbbf9f71b9975893c8d9359e39b9d067 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/addRegOperands.cpp @@ -0,0 +1,4 @@ +void addRegOperands ( MCInst & Inst , unsigned N ) const { +assert ( N == 1 && "Invalid number of operands!" ) ; +Inst . addOperand ( MCOperand :: createReg ( getReg ( ) ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/addVTypeIOperands.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/addVTypeIOperands.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e3348483b699c85655a59ab63bb64559976801bd --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/addVTypeIOperands.cpp @@ -0,0 +1,4 @@ +void addVTypeIOperands ( MCInst & Inst , unsigned N ) const { +assert ( N == 1 && "Invalid number of operands!" ) ; +Inst . addOperand ( MCOperand :: createImm ( getVType ( ) ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/classifySymbolRef.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/classifySymbolRef.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0835d389c5c6c3d548376d2dc2f280d2e4eb1bae --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/classifySymbolRef.cpp @@ -0,0 +1,20 @@ +bool RISCVAsmParser :: classifySymbolRef ( const MCExpr * Expr , MCExpr :: VariantKind & Kind , ) { +Addend = 0 ; +if ( const RISCVMCExpr * AE = dyn_cast < RISCVMCExpr > ( Expr ) ) { +ELFRefKind = AE -> getKind ( ) ; +Expr = AE -> getSubExpr ( ) ; +} +if ( SE ) { +return true ; +MCValue Res ; +bool Relocatable = Expr -> evaluateAsRelocatable ( Res , nullptr , nullptr ) ; +if ( ! Relocatable ) { +return false ; +} +if ( ! Res . getSymA ( ) ) { +return false ; +if ( Res . getSymB ( ) ) { +return false ; +Addend = Res . getConstant ( ) ; +return ELFRefKind == RISCVMCExpr :: VK_INVALID || DarwinRefKind == MCSymbolRefExpr :: VK_RISCV_None ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/convertFPR64ToFPR16.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/convertFPR64ToFPR16.cpp new file mode 100644 index 0000000000000000000000000000000000000000..24169e0ef75323e8421848c07cc538db6e6b6abd --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/convertFPR64ToFPR16.cpp @@ -0,0 +1,4 @@ +static MCRegister convertFPR64ToFPR16 ( MCRegister Reg ) { +assert ( Reg >= RISCV :: F0_D && Reg <= RISCV :: F31_D && "Invalid register" ) ; +return Reg - RISCV :: F0_D + RISCV :: F0_H ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/convertFPR64ToFPR32.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/convertFPR64ToFPR32.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8f96b5202f11ef1aa8cc90197f2434f6b414ebae --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/convertFPR64ToFPR32.cpp @@ -0,0 +1,4 @@ +static MCRegister convertFPR64ToFPR32 ( MCRegister Reg ) { +assert ( Reg >= RISCV :: F0_D && Reg <= RISCV :: F31_D && "Invalid register" ) ; +return Reg - RISCV :: F0_D + RISCV :: F0_F ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/createImm.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/createImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3c49656e851eb59e931c7d01366afdae9f3149dd --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/createImm.cpp @@ -0,0 +1,8 @@ +static std :: unique_ptr < RISCVOperand > createImm ( const MCExpr * Val , SMLoc S , SMLoc E , bool IsRV64 ) { +auto Op = std :: make_unique < RISCVOperand > ( KindTy :: Immediate ) ; +Op -> Imm . Val = Val ; +Op -> StartLoc = S ; +Op -> EndLoc = E ; +Op -> IsRV64 = IsRV64 ; +return Op ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/createReg.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/createReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1d347bc39004e628b6ecde6295ee09a1f58e4dc6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/createReg.cpp @@ -0,0 +1,8 @@ +static std :: unique_ptr < RISCVOperand > createReg ( unsigned RegNo , SMLoc S , SMLoc E , bool IsRV64 ) { +auto Op = std :: make_unique < RISCVOperand > ( KindTy :: Register ) ; +Op -> Reg . RegNum = RegNo ; +Op -> StartLoc = S ; +Op -> EndLoc = E ; +Op -> IsRV64 = IsRV64 ; +return Op ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/createSysReg.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/createSysReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cb45636e0f1c1175181524b450aa3f9b5609c970 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/createSysReg.cpp @@ -0,0 +1,10 @@ +static std :: unique_ptr < RISCVOperand > createSysReg ( StringRef Str , SMLoc S , unsigned Encoding , bool IsRV64 ) { +auto Op = std :: make_unique < RISCVOperand > ( KindTy :: SystemRegister ) ; +Op -> SysReg . Data = Str . data ( ) ; +Op -> SysReg . Length = Str . size ( ) ; +Op -> SysReg . Encoding = Encoding ; +Op -> StartLoc = S ; +Op -> EndLoc = S ; +Op -> IsRV64 = IsRV64 ; +return Op ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/createToken.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/createToken.cpp new file mode 100644 index 0000000000000000000000000000000000000000..555bd8bf39d3e50bfcb4f014482b733a55d09896 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/createToken.cpp @@ -0,0 +1,8 @@ +static std :: unique_ptr < RISCVOperand > createToken ( StringRef Str , SMLoc S , bool IsRV64 ) { +auto Op = std :: make_unique < RISCVOperand > ( KindTy :: Token ) ; +Op -> Tok = Str ; +Op -> StartLoc = S ; +Op -> EndLoc = S ; +Op -> IsRV64 = IsRV64 ; +return Op ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/createVType.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/createVType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..05acc68d6da5e321fcab471e59a7d688ea5817fd --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/createVType.cpp @@ -0,0 +1,7 @@ +static std :: unique_ptr < RISCVOperand > createVType ( unsigned VTypeI , SMLoc S , bool IsRV64 ) { +auto Op = std :: make_unique < RISCVOperand > ( KindTy :: VType ) ; +Op -> VType . Val = VTypeI ; +Op -> StartLoc = S ; +Op -> IsRV64 = IsRV64 ; +return Op ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/defaultMaskRegOp.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/defaultMaskRegOp.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e89b565eaea9d2767590dd9e99669173f3f03dfa --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/defaultMaskRegOp.cpp @@ -0,0 +1,3 @@ +std :: unique_ptr < RISCVOperand > RISCVAsmParser :: defaultMaskRegOp ( ) const { +return RISCVOperand :: createImm ( this , 0 , SMLoc ( ) , RISCVOperand :: ImmTyDLC ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/emitToStreamer.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/emitToStreamer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8d2ffe597ac05b9d91576ef723a462e4cb99122a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/emitToStreamer.cpp @@ -0,0 +1,9 @@ +void RISCVAsmParser :: emitToStreamer ( MCStreamer & S , const MCInst & Inst ) { +MCInst CInst ; +bool Res = false ; +Res = compressInst ( CInst , Inst , getSTI ( ) , S . getContext ( ) ) ; +if ( Res ) { +RISCVNumInstrsCompressed = RISCVNumInstrsCompressed + 1 ; +} +S . emitInstruction ( ( Res ? CInst : Inst ) , getSTI ( ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/evaluateConstantImm.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/evaluateConstantImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1d3a2a265507019314316ce57f872d67180347fa --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/evaluateConstantImm.cpp @@ -0,0 +1,12 @@ +static bool evaluateConstantImm ( const MCExpr * Expr , int64_t & Imm , RISCVMCExpr :: VariantKind & VK ) const { +if ( auto * RE = dyn_cast < RISCVMCExpr > ( Expr ) ) { +VK = RE -> getKind ( ) ; +return RE -> evaluateAsConstant ( Imm ) ; +} +if ( auto CE = dyn_cast < MCConstantExpr > ( Expr ) ) { +VK = RISCVMCExpr :: VK_RISCV_None ; +Imm = CE -> getValue ( ) ; +return true ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/generateImmOutOfRangeError.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/generateImmOutOfRangeError.cpp new file mode 100644 index 0000000000000000000000000000000000000000..001aedf0e0b037067d6361233363876127444c7d --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/generateImmOutOfRangeError.cpp @@ -0,0 +1,4 @@ +bool RISCVAsmParser :: generateImmOutOfRangeError ( OperandVector & Operands , uint64_t ErrorInfo , int64_t Lower , int64_t Upper , Twine Msg = "immediate must be an integer in the range" ) { +SMLoc ErrorLoc = ( ( RISCVOperand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; +return Error ( ErrorLoc , Msg + " [" + Twine ( Lower ) + ", " + Twine ( Upper ) + "]" ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/getEndLoc.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/getEndLoc.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e37ce2784f719036de35e1f8d8504cae1121c2bc --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/getEndLoc.cpp @@ -0,0 +1,3 @@ +SMLoc getEndLoc ( ) const override { +return EndLoc ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/getFeatureBits.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/getFeatureBits.cpp new file mode 100644 index 0000000000000000000000000000000000000000..080034f18946182156ba430e043bdb8f9e5689a8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/getFeatureBits.cpp @@ -0,0 +1,3 @@ +bool getFeatureBits ( uint64_t Feature ) { +return getSTI ( ) . getFeatureBits ( ) [ Feature ] ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/getImm.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/getImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a295b3267dd5db0827725099e6a0db869691db64 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/getImm.cpp @@ -0,0 +1,4 @@ +const MCExpr * getImm ( ) const { +assert ( Kind == KindTy :: Immediate && "Invalid type access!" ) ; +return Imm . Val ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/getLoc.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/getLoc.cpp new file mode 100644 index 0000000000000000000000000000000000000000..35c966acc0c7ad3f7a0e321c17de19bd2ea70c74 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/getLoc.cpp @@ -0,0 +1,3 @@ +SMLoc getLoc ( ) const { +return getParser ( ) . getTok ( ) . getLoc ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/getReg.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/getReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..462f8d464a8e61f2fabbd74202b7d383d8eb9362 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/getReg.cpp @@ -0,0 +1,4 @@ +unsigned getReg ( ) const override { +assert ( Kind == KindTy :: Register && "Invalid type access!" ) ; +return Reg . RegNum . id ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/getRoundingMode.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/getRoundingMode.cpp new file mode 100644 index 0000000000000000000000000000000000000000..de24b7fc6b7408ca24cd1ebfe5d1ca9723fbe819 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/getRoundingMode.cpp @@ -0,0 +1,3 @@ +RISCVFPRndMode :: RoundingMode getRoundingMode ( ) const { +return ( MI . getDesc ( ) . TSFlags >> RISCVII :: AddrModePos ) & RISCVII :: AddrModeMask ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/getStartLoc.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/getStartLoc.cpp new file mode 100644 index 0000000000000000000000000000000000000000..07cb9bb6e768b7938b667280b2a7b15561f5e6a2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/getStartLoc.cpp @@ -0,0 +1,3 @@ +SMLoc getStartLoc ( ) const override { +return StartLoc ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/getSysReg.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/getSysReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a1ebf9426b9608f4137ea7501f3b08bfab0d3808 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/getSysReg.cpp @@ -0,0 +1,4 @@ +StringRef getSysReg ( ) const { +assert ( Kind == KindTy :: SystemRegister && "Invalid type access!" ) ; +return StringRef ( SysReg . Data , SysReg . Length ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/getTargetStreamer.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/getTargetStreamer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2299ed2126abc10e946f1e7b5279458e8ba1702b --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/getTargetStreamer.cpp @@ -0,0 +1,4 @@ +RISCVTargetStreamer & getTargetStreamer ( ) { +MCTargetStreamer & TS = * getParser ( ) . getStreamer ( ) . getTargetStreamer ( ) ; +return static_cast < RISCVTargetStreamer & > ( TS ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/getToken.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/getToken.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ac25596a2291a838d72813f271e931ccf4073a7d --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/getToken.cpp @@ -0,0 +1,4 @@ +StringRef getToken ( ) const { +assert ( Kind == KindTy :: Token && "Invalid type access!" ) ; +return Tok ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/getVType.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/getVType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f576808a24bb8b7dbf54d64605d91a3963ced115 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/getVType.cpp @@ -0,0 +1,4 @@ +unsigned getVType ( ) const { +assert ( Kind == KindTy :: VType && "Invalid type access!" ) ; +return VType . Val ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isBareSimmNLsb0.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isBareSimmNLsb0.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3ec73ffd582eed6cca1c17ecafb95eaf880334dc --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isBareSimmNLsb0.cpp @@ -0,0 +1,13 @@ +template < int N > bool isBareSimmNLsb0 ( ) const { +if ( ! isImm ( ) ) { +return false ; +} +RISCVMCExpr :: VariantKind VK = RISCVMCExpr :: VK_RISCV_None ; +int64_t Imm ; +bool IsValid ; +IsValid = isShiftedInt < N - 1 , 1 > ( Imm ) ; +} +IsValid = RISCVAsmParser :: classifySymbolRef ( getImm ( ) , VK ) ; +} +return IsValid && VK == RISCVMCExpr :: VK_RISCV_None ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isBareSymbol.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isBareSymbol.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2aad3be461d6eace2f023d2bf3eca117e37e57d5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isBareSymbol.cpp @@ -0,0 +1,14 @@ +bool isBareSymbol ( ) const { +int64_t Imm ; +RISCVMCExpr :: VariantKind VK = RISCVMCExpr :: VK_RISCV_None ; +if ( ! isImm ( ) ) { +return false ; +} +if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return false ; +} +if ( ! evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return RISCVAsmParser :: classifySymbolRef ( getImm ( ) , VK ) && VK == RISCVMCExpr :: VK_RISCV_None ; +} +return RISCVAsmParser :: classifySymbolRef ( getImm ( ) , VK ) && VK == RISCVMCExpr :: VK_RISCV_None ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isCLUIImm.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isCLUIImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..91dae47ea7fee123dc58b56fce1e03eb8a399dcf --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isCLUIImm.cpp @@ -0,0 +1,11 @@ +bool isCLUIImm ( ) const { +if ( ! isImm ( ) ) { +return false ; +} +int64_t Imm ; +RISCVMCExpr :: VariantKind VK = RISCVMCExpr :: VK_RISCV_None ; +if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return ( Imm != 0 ) && ( isUInt < 5 > ( Imm ) || ( Imm >= 0xfffe0 && Imm <= 0xfffff ) ) && VK == RISCVMCExpr :: VK_RISCV_None ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isCSRSystemRegister.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isCSRSystemRegister.cpp new file mode 100644 index 0000000000000000000000000000000000000000..79a474c7b17dcd11436567b0a61bfa51e62dc75f --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isCSRSystemRegister.cpp @@ -0,0 +1,3 @@ +bool isCSRSystemRegister ( ) const { +return Kind == KindTy :: SystemRegister ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isCallSymbol.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isCallSymbol.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fdf3ffb54a06c01710ac46d8b30186f47136d891 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isCallSymbol.cpp @@ -0,0 +1,11 @@ +bool isCallSymbol ( ) const { +int64_t Imm ; +RISCVMCExpr :: VariantKind VK = RISCVMCExpr :: VK_RISCV_None ; +if ( ! isImm ( ) ) { +return false ; +} +if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return false ; +} +return RISCVAsmParser :: classifySymbolRef ( getImm ( ) , VK ) && ( VK == RISCVMCExpr :: VK_RISCV_CALL || VK == RISCVMCExpr :: VK_RISCV_CALL_PLT ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isFRMArg.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isFRMArg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..31a6c3beb5eae984e9dce91f643307e2a26d6593 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isFRMArg.cpp @@ -0,0 +1,5 @@ +bool isFRMArg ( ) const { +if ( ! isImm ( ) ) { +return false ; +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isFenceArg.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isFenceArg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2677e25f34f570a7edeae8b7b906179ea9295293 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isFenceArg.cpp @@ -0,0 +1,5 @@ +bool isFenceArg ( ) const { +if ( ! isImm ( ) ) { +return false ; +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isGPR.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isGPR.cpp new file mode 100644 index 0000000000000000000000000000000000000000..787bd50e91ed60f013f12074fdc474208365e761 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isGPR.cpp @@ -0,0 +1,3 @@ +bool isGPR ( ) const { +return Kind == KindTy :: Register && RISCVMCRegisterClasses [ RISCV :: GPRRegClassID ] . contains ( Reg . RegNum ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isImm.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..64ea89f602caa02e1bd59a59834d9a28d2bb6af7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isImm.cpp @@ -0,0 +1,3 @@ +bool isImm ( ) const override { +return Kind == KindTy :: Immediate ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isImmXLenLI.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isImmXLenLI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..096bdbe2352ebf980f84d58886ea67b223baf081 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isImmXLenLI.cpp @@ -0,0 +1,11 @@ +bool isImmXLenLI ( ) const { +if ( ! isImm ( ) ) { +return false ; +} +int64_t Imm ; +RISCVMCExpr :: VariantKind VK = RISCVMCExpr :: VK_RISCV_None ; +if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return VK == RISCVMCExpr::VK_RISCV_LO || VK == RISCVMCExpr::VK_RISCV_PCREL_LO || VK == RISCVMCExpr::VK_RISCV_None && (isRV64() || (isInt<32>(Imm) || isUInt<32>(Imm))) ; +} +return VK == RISCVMCExpr :: VK_RISCV_LO || VK == RISCVMCExpr :: VK_RISCV_PCREL_LO ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isMem.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isMem.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bbe89a41bb139dfc739a67a4bac398d6d354d13e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isMem.cpp @@ -0,0 +1,3 @@ +bool isMem ( ) const override { +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isPseudoJumpSymbol.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isPseudoJumpSymbol.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1e6d5f388818dc3fa82defda1d6a7bab6dfc3a85 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isPseudoJumpSymbol.cpp @@ -0,0 +1,11 @@ +bool isPseudoJumpSymbol ( ) const { +int64_t Imm ; +RISCVMCExpr :: VariantKind VK = RISCVMCExpr :: VK_RISCV_None ; +if ( ! isImm ( ) ) { +return false ; +} +if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return false ; +} +return RISCVAsmParser :: classifySymbolRef ( getImm ( ) , VK ) && VK == RISCVMCExpr :: VK_RISCV_CALL ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isRV32E.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isRV32E.cpp new file mode 100644 index 0000000000000000000000000000000000000000..36b04b2740c389d1272dddb7081aff3306a4d29b --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isRV32E.cpp @@ -0,0 +1,3 @@ +bool isRV32E ( ) const { +return getSTI ( ) . hasFeature ( RISCV :: FeatureRV32E ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isRV64-2.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isRV64-2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f4c9963cb5cfcc788a16b2e5a4174572ea86ebab --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isRV64-2.cpp @@ -0,0 +1,3 @@ +bool isRV64 ( ) const { +return getSTI ( ) . hasFeature ( RISCV :: Feature64Bit ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isRV64.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isRV64.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2b8327f239930562cfd20ff962aeefd2b2c8d911 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isRV64.cpp @@ -0,0 +1,3 @@ +bool isRV64 ( ) const { +return IsRV64 ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isReg.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..574f31b9597b3a47ea097df3635d56d107ec07ae --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isReg.cpp @@ -0,0 +1,3 @@ +bool isReg ( ) const override { +return Kind == KindTy :: Register ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isSImm10Lsb0000NonZero.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isSImm10Lsb0000NonZero.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ce65543183c407964fc4cb1f70d43bb3f74ce823 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isSImm10Lsb0000NonZero.cpp @@ -0,0 +1,11 @@ +bool isSImm10Lsb0000NonZero ( ) const { +if ( ! isImm ( ) ) { +return false ; +} +int64_t Imm ; +RISCVMCExpr :: VariantKind VK = RISCVMCExpr :: VK_RISCV_None ; +if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return ( Imm != 0 ) && isShiftedInt < 6 , 4 > ( Imm ) && VK == RISCVMCExpr :: VK_RISCV_None ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isSImm12.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isSImm12.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9f499477f292a10bae67d14fa6f8fda19d864451 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isSImm12.cpp @@ -0,0 +1,14 @@ +bool isSImm12 ( ) const { +if ( ! isImm ( ) ) { +return false ; +} +int64_t Imm ; +RISCVMCExpr :: VariantKind VK = RISCVMCExpr :: VK_RISCV_None ; +if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return isInt<12>(Imm) && (VK == RISCVMCExpr::VK_RISCV_None || VK == RISCVMCExpr::VK_RISCV_LO || VK == RISCVMCExpr::VK_RISCV_PCREL_LO || VK == RISCVMCExpr::VK_RISCV_TPREL_LO) ; +} +if ( ! evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return RISCVAsmParser :: classifySymbolRef ( getImm ( ) , VK ) && ( VK == RISCVMCExpr :: VK_RISCV_LO || VK == RISCVMCExpr :: VK_RISCV_PCREL_LO || VK == RISCVMCExpr :: VK_RISCV_TPREL_LO ) ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isSImm12Lsb0.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isSImm12Lsb0.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a20346ee23a2c1a4c0e83d3d185aa648e3f5b909 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isSImm12Lsb0.cpp @@ -0,0 +1,14 @@ +bool isSImm12Lsb0 ( ) const { +if ( ! isImm ( ) ) { +return false ; +} +int64_t Imm ; +RISCVMCExpr :: VariantKind VK = RISCVMCExpr :: VK_RISCV_None ; +if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return isShiftedInt < 11 , 1 > ( Imm ) && VK == RISCVMCExpr :: VK_RISCV_None ; +} +if ( ! evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return RISCVAsmParser :: classifySymbolRef ( getImm ( ) , VK ) && VK == RISCVMCExpr :: VK_RISCV_None ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isSImm13Lsb0.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isSImm13Lsb0.cpp new file mode 100644 index 0000000000000000000000000000000000000000..847dabb3f59066c7129e3aed3c543462b1437ae3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isSImm13Lsb0.cpp @@ -0,0 +1,14 @@ +bool isSImm13Lsb0 ( ) const { +if ( ! isImm ( ) ) { +return false ; +} +int64_t Imm ; +RISCVMCExpr :: VariantKind VK = RISCVMCExpr :: VK_RISCV_None ; +if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return isShiftedInt < 12 , 1 > ( Imm ) && VK == RISCVMCExpr :: VK_RISCV_None ; +} +if ( ! evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return RISCVAsmParser :: classifySymbolRef ( getImm ( ) , VK ) && VK == RISCVMCExpr :: VK_RISCV_None ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isSImm21Lsb0JAL.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isSImm21Lsb0JAL.cpp new file mode 100644 index 0000000000000000000000000000000000000000..467c562fffb3f6c9778bf32aead8d41d9ab95b44 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isSImm21Lsb0JAL.cpp @@ -0,0 +1,14 @@ +bool isSImm21Lsb0JAL ( ) const { +if ( ! isImm ( ) ) { +return false ; +} +int64_t Imm ; +RISCVMCExpr :: VariantKind VK = RISCVMCExpr :: VK_RISCV_None ; +if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return isShiftedInt < 20 , 1 > ( Imm ) && VK == RISCVMCExpr :: VK_RISCV_None ; +} +if ( ! evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return RISCVAsmParser :: classifySymbolRef ( getImm ( ) , VK ) && VK == RISCVMCExpr :: VK_RISCV_None ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isSImm5.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isSImm5.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f0a1a807774cc7eb36d5f3881828e5721e83a89f --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isSImm5.cpp @@ -0,0 +1,11 @@ +bool isSImm5 ( ) const { +if ( ! isImm ( ) ) { +return false ; +} +int64_t Imm ; +RISCVMCExpr :: VariantKind VK = RISCVMCExpr :: VK_RISCV_None ; +if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return isInt < 5 > ( Imm ) && VK == RISCVMCExpr :: VK_RISCV_None ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isSImm5Plus1.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isSImm5Plus1.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f1a73a5d4d7796abed063e73b1ebdd6cdadd4d47 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isSImm5Plus1.cpp @@ -0,0 +1,11 @@ +bool isSImm5Plus1 ( ) const { +if ( ! isImm ( ) ) { +return false ; +} +int64_t Imm ; +RISCVMCExpr :: VariantKind VK = RISCVMCExpr :: VK_RISCV_None ; +if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return isInt < 5 > ( Imm - 1 ) && VK == RISCVMCExpr :: VK_RISCV_None ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isSImm6.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isSImm6.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c39e40102920ed529fccc0a1fd06995b18691898 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isSImm6.cpp @@ -0,0 +1,11 @@ +bool isSImm6 ( ) const { +if ( ! isImm ( ) ) { +return false ; +} +int64_t Imm ; +RISCVMCExpr :: VariantKind VK = RISCVMCExpr :: VK_RISCV_None ; +if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return isInt < 6 > ( Imm ) && VK == RISCVMCExpr :: VK_RISCV_None ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isSImm6NonZero.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isSImm6NonZero.cpp new file mode 100644 index 0000000000000000000000000000000000000000..46457438d4851d77ee1c69b1ea96e34006d91936 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isSImm6NonZero.cpp @@ -0,0 +1,11 @@ +bool isSImm6NonZero ( ) const { +if ( ! isImm ( ) ) { +return false ; +} +int64_t Imm ; +RISCVMCExpr :: VariantKind VK = RISCVMCExpr :: VK_RISCV_None ; +if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return isInt<6>(Imm) && (Imm != 0) && VK == RISCVMCExpr::VK_RISCV_None ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isSImm9Lsb0.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isSImm9Lsb0.cpp new file mode 100644 index 0000000000000000000000000000000000000000..de5c79dd364671ac04324387dbd67ea515aadfc3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isSImm9Lsb0.cpp @@ -0,0 +1,14 @@ +bool isSImm9Lsb0 ( ) const { +if ( ! isImm ( ) ) { +return false ; +} +int64_t Imm ; +RISCVMCExpr :: VariantKind VK = RISCVMCExpr :: VK_RISCV_None ; +if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return isShiftedInt < 8 , 1 > ( Imm ) && VK == RISCVMCExpr :: VK_RISCV_None ; +} +if ( ! evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return RISCVAsmParser :: classifySymbolRef ( getImm ( ) , VK ) && VK == RISCVMCExpr :: VK_RISCV_None ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isSystemRegister.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isSystemRegister.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d2b5c274c624fa3378b43fcdd1feb3fd91cc3ce4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isSystemRegister.cpp @@ -0,0 +1,3 @@ +bool isSystemRegister ( ) const { +return Kind == KindTy :: SystemRegister ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isTPRelAddSymbol.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isTPRelAddSymbol.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8e9559676426c90045b5599ca30e9a6464af1829 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isTPRelAddSymbol.cpp @@ -0,0 +1,14 @@ +bool isTPRelAddSymbol ( ) const { +int64_t Imm ; +RISCVMCExpr :: VariantKind VK = RISCVMCExpr :: VK_RISCV_None ; +if ( ! isImm ( ) ) { +return false ; +} +if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return false ; +} +if ( ! evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return RISCVAsmParser :: classifySymbolRef ( getImm ( ) , VK ) && VK == RISCVMCExpr :: VK_RISCV_TPREL_ADD ; +} +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isToken.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isToken.cpp new file mode 100644 index 0000000000000000000000000000000000000000..765ad841fd47a89abdd004cc3850313674615334 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isToken.cpp @@ -0,0 +1,3 @@ +bool isToken ( ) const override { +return Kind == KindTy :: Token ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isUImm10Lsb00NonZero.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isUImm10Lsb00NonZero.cpp new file mode 100644 index 0000000000000000000000000000000000000000..43eca991b15a3c62b9805fd1a4bbcf5a1e5cb543 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isUImm10Lsb00NonZero.cpp @@ -0,0 +1,11 @@ +bool isUImm10Lsb00NonZero ( ) const { +if ( ! isImm ( ) ) { +return false ; +} +int64_t Imm ; +RISCVMCExpr :: VariantKind VK = RISCVMCExpr :: VK_RISCV_None ; +if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return isShiftedUInt < 8 , 2 > ( Imm ) && ( Imm != 0 ) && VK == RISCVMCExpr :: VK_RISCV_None ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isUImm20AUIPC.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isUImm20AUIPC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ea45806aaf5369ff93cc6d54cbe6a930c2128af8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isUImm20AUIPC.cpp @@ -0,0 +1,14 @@ +bool isUImm20AUIPC ( ) const { +int64_t Imm ; +RISCVMCExpr :: VariantKind VK = RISCVMCExpr :: VK_RISCV_None ; +if ( ! isImm ( ) ) { +return false ; +} +if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return isUInt<20>(Imm) && (VK == RISCVMCExpr::VK_RISCV_None || VK == RISCVMCExpr::VK_RISCV_PCREL_HI || VK == RISCVMCExpr::VK_RISCV_GOT_HI || VK == RISCVMCExpr::VK_RISCV_TLS_GOT_HI || VK == RISCVMCExpr::VK_RISCV_TLS_GD_HI) ; +} +if ( ! evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return RISCVAsmParser :: classifySymbolRef ( getImm ( ) , VK ) && ( VK == RISCVMCExpr :: VK_RISCV_PCREL_HI || VK == RISCVMCExpr :: VK_RISCV_GOT_HI || VK == RISCVMCExpr :: VK_RISCV_TLS_GOT_HI || VK == RISCVMCExpr :: VK_RISCV_TLS_GD_HI ) ; +} +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isUImm20LUI.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isUImm20LUI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..477fda5e65cd14715a59f28945e312eba9fd2713 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isUImm20LUI.cpp @@ -0,0 +1,14 @@ +bool isUImm20LUI ( ) const { +int64_t Imm ; +RISCVMCExpr :: VariantKind VK = RISCVMCExpr :: VK_RISCV_None ; +if ( ! isImm ( ) ) { +return false ; +} +if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return isUInt < 20 > ( Imm ) && ( VK == RISCVMCExpr :: VK_RISCV_None || VK == RISCVMCExpr :: VK_RISCV_HI || VK == RISCVMCExpr :: VK_RISCV_TPREL_HI ) ; +} +if ( ! evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return RISCVAsmParser :: classifySymbolRef ( getImm ( ) , VK ) && ( VK == RISCVMCExpr :: VK_RISCV_HI || VK == RISCVMCExpr :: VK_RISCV_TPREL_HI ) ; +} +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isUImm5.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isUImm5.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c2c3a2dfa2068ac84c7ba9238b70d2b6ca5907d1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isUImm5.cpp @@ -0,0 +1,11 @@ +bool isUImm5 ( ) const { +if ( ! isImm ( ) ) { +return false ; +} +int64_t Imm ; +RISCVMCExpr :: VariantKind VK = RISCVMCExpr :: VK_RISCV_None ; +if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return isUInt < 5 > ( Imm ) && VK == RISCVMCExpr :: VK_RISCV_None ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isUImm7Lsb00.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isUImm7Lsb00.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8f46e5d90c0f0ae1ba4cb1d4dcf08bcf9fa1fcc1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isUImm7Lsb00.cpp @@ -0,0 +1,11 @@ +bool isUImm7Lsb00 ( ) const { +if ( ! isImm ( ) ) { +return false ; +} +int64_t Imm ; +RISCVMCExpr :: VariantKind VK = RISCVMCExpr :: VK_RISCV_None ; +if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return isShiftedUInt < 5 , 2 > ( Imm ) && VK == RISCVMCExpr :: VK_RISCV_None ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isUImm8Lsb00.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isUImm8Lsb00.cpp new file mode 100644 index 0000000000000000000000000000000000000000..beb1b5a5774dde0fef0aacb5d9290c3318b49a06 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isUImm8Lsb00.cpp @@ -0,0 +1,11 @@ +bool isUImm8Lsb00 ( ) const { +if ( ! isImm ( ) ) { +return false ; +} +int64_t Imm ; +RISCVMCExpr :: VariantKind VK = RISCVMCExpr :: VK_RISCV_None ; +if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return isShiftedUInt < 6 , 2 > ( Imm ) && VK == RISCVMCExpr :: VK_RISCV_None ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isUImm8Lsb000.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isUImm8Lsb000.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3da771073a66c7847a8188c4d1bdc2bfa6daae3e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isUImm8Lsb000.cpp @@ -0,0 +1,11 @@ +bool isUImm8Lsb000 ( ) const { +if ( ! isImm ( ) ) { +return false ; +} +int64_t Imm ; +RISCVMCExpr :: VariantKind VK = RISCVMCExpr :: VK_RISCV_None ; +if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return isShiftedUInt < 5 , 3 > ( Imm ) && VK == RISCVMCExpr :: VK_RISCV_None ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isUImm9Lsb000.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isUImm9Lsb000.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f19dc0df26f186737e1afb1b8455d20a6c40dc95 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isUImm9Lsb000.cpp @@ -0,0 +1,11 @@ +bool isUImm9Lsb000 ( ) const { +if ( ! isImm ( ) ) { +return false ; +} +int64_t Imm ; +RISCVMCExpr :: VariantKind VK = RISCVMCExpr :: VK_RISCV_None ; +if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return isShiftedUInt < 6 , 3 > ( Imm ) && VK == RISCVMCExpr :: VK_RISCV_None ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isUImmLog2XLen.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isUImmLog2XLen.cpp new file mode 100644 index 0000000000000000000000000000000000000000..20aa6e9f965b6377569fd23c932904800fd5d220 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isUImmLog2XLen.cpp @@ -0,0 +1,11 @@ +bool isUImmLog2XLen ( ) const { +if ( ! isImm ( ) ) { +return false ; +} +int64_t Imm ; +RISCVMCExpr :: VariantKind VK = RISCVMCExpr :: VK_RISCV_None ; +if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return VK == RISCVMCExpr :: VK_RISCV_None && ( ( isRV64 ( ) && isUInt < 6 > ( Imm ) ) || isUInt < 5 > ( Imm ) ) ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isUImmLog2XLenHalf.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isUImmLog2XLenHalf.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c6b2472887895d47c6cf1e822e58a3eac3ccf124 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isUImmLog2XLenHalf.cpp @@ -0,0 +1,11 @@ +bool isUImmLog2XLenHalf ( ) const { +if ( ! isImm ( ) ) { +return false ; +} +int64_t Imm ; +RISCVMCExpr :: VariantKind VK = RISCVMCExpr :: VK_RISCV_None ; +if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return VK == RISCVMCExpr :: VK_RISCV_None && ( ( isRV64 ( ) && isUInt < 5 > ( Imm ) ) || isUInt < 4 > ( Imm ) ) ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isUImmLog2XLenNonZero.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isUImmLog2XLenNonZero.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e9183f91d4ba6a9794d5d7f134b9b4945cb0a228 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isUImmLog2XLenNonZero.cpp @@ -0,0 +1,11 @@ +bool isUImmLog2XLenNonZero ( ) const { +if ( ! isImm ( ) ) { +return false ; +} +int64_t Imm ; +RISCVMCExpr :: VariantKind VK = RISCVMCExpr :: VK_RISCV_None ; +if ( evaluateConstantImm ( getImm ( ) , Imm , VK ) ) { +return VK == RISCVMCExpr :: VK_RISCV_None && Imm && ( ( isRV64 ( ) && isUInt < 6 > ( Imm ) ) || isUInt < 5 > ( Imm ) ) ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isV0Reg.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isV0Reg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0a92c8791c349da4f026754dae3ec38d1193d9d7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isV0Reg.cpp @@ -0,0 +1,3 @@ +bool isV0Reg ( ) const override { +return Kind == KindTy :: Register && Reg . RegNum == RISCV :: V0 ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isVType.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isVType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..858133aed67c3eb7ce07c8f10dc3ca4fb5309a37 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isVType.cpp @@ -0,0 +1,3 @@ +bool isVType ( ) const { +return Kind == KindTy :: VType ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isVTypeI.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isVTypeI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2514871342beee8b97897aa604e92fab3063408a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/isVTypeI.cpp @@ -0,0 +1,3 @@ +bool isVTypeI ( ) const { +return Kind == KindTy :: VType ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/matchRegisterNameHelper.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/matchRegisterNameHelper.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5004edcd18a3fb0ddadbc6dcaa383cc595c4d952 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/matchRegisterNameHelper.cpp @@ -0,0 +1,7 @@ +static bool matchRegisterNameHelper ( bool IsRV32E , MCRegister & RegNo , StringRef Name ) { +RegNo = MatchRegisterName ( Name ) ; +if ( RegNo == RISCV :: NoRegister ) { +RegNo = MatchRegisterAltName ( Name ) ; +} +return RegNo == RISCV :: NoRegister ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/parseAtomicMemOp.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/parseAtomicMemOp.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e6591e7c9aa5c818786ab79e1a3bcd8470211792 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/parseAtomicMemOp.cpp @@ -0,0 +1,19 @@ +OperandMatchResultTy RISCVAsmParser :: parseAtomicMemOp ( OperandVector & Operands ) { +if ( getLexer ( ) . isNot ( AsmToken :: LParen ) ) { +Error ( getLoc ( ) , "expected '('" ) ; +return MatchOperand_ParseFail ; +} +getParser ( ) . Lex ( ) ; +Operands . push_back ( RISCVOperand :: createToken ( "(" , getLoc ( ) ) ) ; +if ( parseRegister ( Operands ) != MatchOperand_Success ) { +Error ( getLoc ( ) , "expected register" ) ; +return MatchOperand_ParseFail ; +} +if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { +Error ( getLoc ( ) , "expected ')'" ) ; +return MatchOperand_ParseFail ; +} +getParser ( ) . Lex ( ) ; +Operands . push_back ( RISCVOperand :: createToken ( ")" , getLoc ( ) ) ) ; +return MatchOperand_Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/parseBareSymbol.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/parseBareSymbol.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c24b1e25320352042226b0fd9d0dddcd1d63bd91 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/parseBareSymbol.cpp @@ -0,0 +1,56 @@ +OperandMatchResultTy RISCVAsmParser :: parseBareSymbol ( OperandVector & Operands ) { +SMLoc S = getLoc ( ) ; +SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) - 1 ) ; +const MCExpr * Res ; +if ( getLexer ( ) . getKind ( ) != AsmToken :: Identifier ) { +return MatchOperand_NoMatch ; +} +StringRef Identifier ; +AsmToken Tok = getLexer ( ) . getTok ( ) ; +if ( getParser ( ) . parseIdentifier ( Identifier ) ) { +return MatchOperand_ParseFail ; +} +MCExpr :: VariantKind Kind = RISCVMCExpr :: VK_RISCV_None ; +if ( Identifier . consume_back ( "@plt" ) ) { +Error ( getLoc ( ) , "'@plt' operand not valid for instruction" ) ; +return MatchOperand_ParseFail ; +} +MCSymbol * Sym = getContext ( ) . getOrCreateSymbol ( Identifier ) ; +if ( Sym -> isVariable ( ) ) { +const MCExpr * V = Sym -> getVariableValue ( false ) ; +if ( ! isa < MCSymbolRefExpr > ( V ) ) { +getLexer ( ) . UnLex ( Tok ) ; +return MatchOperand_NoMatch ; +} +Res = V ; +} +if ( ! Sym -> isVariable ( ) ) { +} +MCBinaryExpr :: Opcode Opcode ; +if ( getLexer ( ) . getKind ( ) == AsmToken :: Plus ) { +Opcode = MCBinaryExpr :: Add ; +getLexer ( ) . Lex ( ) ; +const MCExpr * Expr ; +if ( getParser ( ) . parseExpression ( Expr ) ) { +return MatchOperand_ParseFail ; +} +Res = MCBinaryExpr :: create ( Opcode , Res , Expr , getContext ( ) ) ; +Operands . push_back ( RISCVOperand :: createImm ( Res , S , E , isRV64 ( ) ) ) ; +return MatchOperand_Success ; +} +if ( getLexer ( ) . getKind ( ) == AsmToken :: Minus ) { +Opcode = MCBinaryExpr :: Sub ; +getLexer ( ) . Lex ( ) ; +const MCExpr * Expr ; +if ( getParser ( ) . parseExpression ( Expr ) ) { +return MatchOperand_ParseFail ; +} +Res = MCBinaryExpr :: create ( Opcode , Res , Expr , getContext ( ) ) ; +Operands . push_back ( RISCVOperand :: createImm ( Res , S , E , isRV64 ( ) ) ) ; +return MatchOperand_Success ; +} +if ( Kind != RISCVMCExpr :: VK_RISCV_Invalid ) { +Res = RISCVMCExpr :: create ( Res , Kind , getContext ( ) ) ; +Operands . push_back ( RISCVOperand :: createImm ( Res , S , E , isRV64 ( ) ) ) ; +return MatchOperand_Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/parseCSRSyestemRegister.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/parseCSRSyestemRegister.cpp new file mode 100644 index 0000000000000000000000000000000000000000..059c1b534b6c01d6277e0c1b118b5e06c63dd6ba --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/parseCSRSyestemRegister.cpp @@ -0,0 +1,4 @@ +OperandMatchResultTy RISCVAsmParser :: parseCSRSystemRegister ( OperandVector & Operands , bool AllowParens ) { +SMLoc S = getLoc ( ) ; +return MatchOperand_NoMatch ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/parseCallSymbol.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/parseCallSymbol.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e3c140063e49a7ebbf204cb3fbd292f003a9ddeb --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/parseCallSymbol.cpp @@ -0,0 +1,46 @@ +OperandMatchResultTy RISCVAsmParser :: parseCallSymbol ( OperandVector & Operands ) { +SMLoc S = getLoc ( ) ; +SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) - 1 ) ; +const MCExpr * Res ; +if ( getLexer ( ) . getKind ( ) != AsmToken :: Identifier ) { +return MatchOperand_NoMatch ; +} +StringRef Identifier ; +AsmToken Tok = getLexer ( ) . getTok ( ) ; +if ( getParser ( ) . parseIdentifier ( Identifier ) ) { +return MatchOperand_ParseFail ; +} +MCExpr :: VariantKind Kind = RISCVMCExpr :: VK_RISCV_None ; +if ( Identifier . consume_back ( "@plt" ) ) { +Kind = RISCVMCExpr :: VK_CALL_PLT ; +} +MCSymbol * Sym = getContext ( ) . getOrCreateSymbol ( Identifier ) ; +if ( Sym -> isVariable ( ) ) { +const MCExpr * V = Sym -> getVariableValue ( false ) ; +if ( ! isa < MCSymbolRefExpr > ( V ) ) { +getLexer ( ) . UnLex ( Tok ) ; +return MatchOperand_ParseFail ; +if ( ! Sym -> isVariable ( ) ) { +MCBinaryExpr :: Opcode Opcode ; +if ( getLexer ( ) . getKind ( ) == AsmToken :: Plus ) { +Opcode = MCBinaryExpr :: Add ; +getLexer ( ) . Lex ( ) ; +const MCExpr * Expr ; +if ( getParser ( ) . parseExpression ( Expr ) ) { +return MatchOperand_ParseFail ; +Res = MCBinaryExpr :: create ( Opcode , Res , Expr , getContext ( ) ) ; +Operands . push_back ( RISCVOperand :: createImm ( Res , S , E , isRV64 ( ) ) ) ; +return MatchOperand_Success ; +if ( getLexer ( ) . getKind ( ) == AsmToken :: Minus ) { +Opcode = MCBinaryExpr :: Sub ; +getLexer ( ) . Lex ( ) ; +const MCExpr * Expr ; +if ( getParser ( ) . parseExpression ( Expr ) ) { +return MatchOperand_ParseFail ; +Res = MCBinaryExpr :: create ( Opcode , Res , Expr , getContext ( ) ) ; +Operands . push_back ( RISCVOperand :: createImm ( Res , S , E , isRV64 ( ) ) ) ; +return MatchOperand_Success ; +if ( Kind != RISCVMCExpr :: VK_RISCV_None ) { +Operands . push_back ( RISCVOperand :: createImm ( Res , S , E , isRV64 ( ) ) ) ; +return MatchOperand_Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/parseImmediate.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/parseImmediate.cpp new file mode 100644 index 0000000000000000000000000000000000000000..62afeeb9658dad4d9fa7f134cdfb883d77ea53bf --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/parseImmediate.cpp @@ -0,0 +1,72 @@ +OperandMatchResultTy RISCVAsmParser :: parseImmediate ( OperandVector & Operands ) { +SMLoc S = getLoc ( ) ; +SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) - 1 ) ; +const MCExpr * Res ; +if ( getLexer ( ) . getKind ( ) == AsmToken :: LParen ) { +if ( getParser ( ) . parseExpression ( Res ) ) { +return MatchOperand_ParseFail ; +} +Operands . push_back ( RISCVOperand :: createImm ( Res , S , E , isRV64 ( ) ) ) ; +return MatchOperand_Success ; +} +if ( getLexer ( ) . getKind ( ) == AsmToken :: Minus ) { +if ( getParser ( ) . parseExpression ( Res ) ) { +return MatchOperand_ParseFail ; +} +Operands . push_back ( RISCVOperand :: createImm ( Res , S , E , isRV64 ( ) ) ) ; +return MatchOperand_Success ; +} +if ( getLexer ( ) . getKind ( ) == AsmToken :: Plus ) { +if ( getParser ( ) . parseExpression ( Res ) ) { +return MatchOperand_ParseFail ; +} +Operands . push_back ( RISCVOperand :: createImm ( Res , S , E , isRV64 ( ) ) ) ; +return MatchOperand_Success ; +} +if ( getLexer ( ) . getKind ( ) == AsmToken :: Integer ) { +if ( getParser ( ) . parseExpression ( Res ) ) { +return MatchOperand_ParseFail ; +} +Operands . push_back ( RISCVOperand :: createImm ( Res , S , E , isRV64 ( ) ) ) ; +return MatchOperand_Success ; +} +if ( getLexer ( ) . getKind ( ) == AsmToken :: String ) { +if ( getParser ( ) . parseExpression ( Res ) ) { +return MatchOperand_ParseFail ; +} +Operands . push_back ( RISCVOperand :: createImm ( Res , S , E , isRV64 ( ) ) ) ; +return MatchOperand_Success ; +} +if ( getLexer ( ) . getKind ( ) == AsmToken :: Identifier ) { +if ( getParser ( ) . parseExpression ( Res ) ) { +return MatchOperand_ParseFail ; +} +Operands . push_back ( RISCVOperand :: createImm ( Res , S , E , isRV64 ( ) ) ) ; +return MatchOperand_Success ; +} +if ( getLexer ( ) . getKind ( ) == AsmToken :: Dot ) { +if ( getParser ( ) . parseExpression ( Res ) ) { +return MatchOperand_ParseFail ; +} +Operands . push_back ( RISCVOperand :: createImm ( Res , S , E , isRV64 ( ) ) ) ; +return MatchOperand_Success ; +} +if ( getLexer ( ) . getKind ( ) == AsmToken :: Tilde ) { +if ( getParser ( ) . parseExpression ( Res ) ) { +return MatchOperand_ParseFail ; +} +Operands . push_back ( RISCVOperand :: createImm ( Res , S , E , isRV64 ( ) ) ) ; +return MatchOperand_Success ; +} +if ( getLexer ( ) . getKind ( ) == AsmToken :: Exclaim ) { +if ( getParser ( ) . parseExpression ( Res ) ) { +return MatchOperand_ParseFail ; +} +Operands . push_back ( RISCVOperand :: createImm ( Res , S , E , isRV64 ( ) ) ) ; +return MatchOperand_Success ; +} +if ( getLexer ( ) . getKind ( ) == AsmToken :: Percent ) { +return parseOperandWithModifier ( Operands ) ; +} +return MatchOperand_NoMatch ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/parseJALOffset.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/parseJALOffset.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e9ac8c17b8e92448e526b1f456f328e85bd9df01 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/parseJALOffset.cpp @@ -0,0 +1,31 @@ +OperandMatchResultTy RISCVAsmParser :: parseJALOffset ( OperandVector & Operands ) { +SMLoc S = getLoc ( ) ; +SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) - 1 ) ; +if ( getLexer ( ) . getKind ( ) != AsmToken :: Identifier ) { +return MatchOperand_NoMatch ; +StringRef Identifier ; +AsmToken Tok = getLexer ( ) . getTok ( ) ; +if ( getParser ( ) . parseIdentifier ( Identifier ) ) { +return MatchOperand_ParseFail ; +if ( Sym -> isVariable ( ) ) { +if ( ! isa < MCSymbolRefExpr > ( V ) ) { +getLexer ( ) . UnLex ( Tok ) ; +return MatchOperand_ParseFail ; +if ( ! Sym -> isVariable ( ) ) { +if ( getLexer ( ) . getKind ( ) == AsmToken :: Plus ) { +getLexer ( ) . Lex ( ) ; +const MCExpr * Expr ; +if ( getParser ( ) . parseExpression ( Expr ) ) { +return MatchOperand_ParseFail ; +Operands . push_back ( RISCVOperand :: createImm ( Res , S , E , isRV64 ( ) ) ) ; +return MatchOperand_Success ; +if ( getLexer ( ) . getKind ( ) == AsmToken :: Minus ) { +getLexer ( ) . Lex ( ) ; +const MCExpr * Expr ; +if ( getParser ( ) . parseExpression ( Expr ) ) { +return MatchOperand_ParseFail ; +Operands . push_back ( RISCVOperand :: createImm ( Res , S , E , isRV64 ( ) ) ) ; +return MatchOperand_Success ; +Operands . push_back ( RISCVOperand :: createImm ( Res , S , E , isRV64 ( ) ) ) ; +return MatchOperand_Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/parseMaskReg.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/parseMaskReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..37d07db50fc1f55972abfa0142398b880d70a8c9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/parseMaskReg.cpp @@ -0,0 +1,16 @@ +OperandMatchResultTy RISCVAsmParser :: parseMaskReg ( OperandVector & Operands ) { +SMLoc S = getLoc ( ) ; +SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) - 1 ) ; +if ( getLexer ( ) . getKind ( ) != AsmToken :: Identifier ) { +return MatchOperand_NoMatch ; +} +StringRef Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; +MCRegister RegNo ; +matchRegisterNameHelper ( RegNo , Name ) ; +if ( RegNo == RISCV :: NoRegister ) { +return MatchOperand_NoMatch ; +} +getLexer ( ) . Lex ( ) ; +Operands . push_back ( RISCVOperand :: createReg ( RegNo , S , E ) ) ; +return MatchOperand_Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/parseMemOpBaseReg.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/parseMemOpBaseReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..57a16411610f177fb51e4937d2c79c0980f53667 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/parseMemOpBaseReg.cpp @@ -0,0 +1,19 @@ +OperandMatchResultTy RISCVAsmParser :: parseMemOpBaseReg ( OperandVector & Operands ) { +if ( getLexer ( ) . isNot ( AsmToken :: LParen ) ) { +Error ( getLoc ( ) , "expected '('" ) ; +return MatchOperand_ParseFail ; +} +getParser ( ) . Lex ( ) ; +Operands . push_back ( RISCVOperand :: createToken ( "(" , getLoc ( ) , isRV64 ( ) ) ) ; +if ( parseRegister ( Operands ) != MatchOperand_Success ) { +Error ( getLoc ( ) , "expected register" ) ; +return MatchOperand_ParseFail ; +} +if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { +Error ( getLoc ( ) , "expected ')'" ) ; +return MatchOperand_ParseFail ; +} +getParser ( ) . Lex ( ) ; +Operands . push_back ( RISCVOperand :: createToken ( ")" , getLoc ( ) , isRV64 ( ) ) ) ; +return MatchOperand_Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/parseOperand.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/parseOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2fa93104ba95d2a88e11d695b47e7d9c90d860eb --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/parseOperand.cpp @@ -0,0 +1,20 @@ +bool RISCVAsmParser :: parseOperand ( OperandVector & Operands , StringRef Mnemonic ) { +OperandMatchResultTy Result = MatchOperandParserImpl ( Operands , Mnemonic , true ) ; +if ( Result == MatchOperand_Success ) { +return false ; +} +if ( Result == MatchOperand_ParseFail ) { +return true ; +} +if ( parseRegister ( Operands , true ) == MatchOperand_Success ) { +return false ; +} +if ( parseImmediate ( Operands ) == MatchOperand_Success ) { +if ( getLexer ( ) . is ( AsmToken :: LParen ) ) { +return parseMemOpBaseReg ( Operands ) != MatchOperand_Success ; +} +return false ; +} +Error ( getLoc ( ) , "unknown operand" ) ; +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/parseOperandWithModifier.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/parseOperandWithModifier.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b00d17f0926f8e5e0df9dad63b4769dcfa6027cb --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/parseOperandWithModifier.cpp @@ -0,0 +1,32 @@ +OperandMatchResultTy RISCVAsmParser :: parseOperandWithModifier ( OperandVector & Operands ) { +SMLoc S = getLoc ( ) ; +SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) - 1 ) ; +if ( getLexer ( ) . getKind ( ) != AsmToken :: Percent ) { +Error ( getLoc ( ) , "expected '%' for operand modifier" ) ; +return MatchOperand_ParseFail ; +} +getParser ( ) . Lex ( ) ; +if ( getLexer ( ) . getKind ( ) != AsmToken :: Identifier ) { +Error ( getLoc ( ) , "expected valid identifier for operand modifier" ) ; +return MatchOperand_ParseFail ; +} +StringRef Identifier = getParser ( ) . getTok ( ) . getIdentifier ( ) ; +RISCVMCExpr :: VariantKind VK = RISCVMCExpr :: getVariantKindForName ( Identifier ) ; +if ( VK == RISCVMCExpr :: VK_RISCV_Invalid ) { +Error ( getLoc ( ) , "unrecognized operand modifier" ) ; +return MatchOperand_ParseFail ; +} +getParser ( ) . Lex ( ) ; +if ( getLexer ( ) . getKind ( ) != AsmToken :: LParen ) { +Error ( getLoc ( ) , "expected '('" ) ; +return MatchOperand_ParseFail ; +} +getParser ( ) . Lex ( ) ; +const MCExpr * SubExpr ; +if ( getParser ( ) . parseParenExpression ( SubExpr , E ) ) { +return MatchOperand_ParseFail ; +} +const MCExpr * ModExpr = RISCVMCExpr :: create ( VK , SubExpr , getContext ( ) ) ; +Operands . push_back ( RISCVOperand :: createImm ( ModExpr , S , E , isRV64 ( ) ) ) ; +return MatchOperand_Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/parsePseudoJumpSymbol.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/parsePseudoJumpSymbol.cpp new file mode 100644 index 0000000000000000000000000000000000000000..28089435ce97510894a6db4b5ae109cb4c6c572e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/parsePseudoJumpSymbol.cpp @@ -0,0 +1,43 @@ +OperandMatchResultTy RISCVAsmParser :: parsePseudoJumpSymbol ( OperandVector & Operands ) { +SMLoc S = getLoc ( ) ; +SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) - 1 ) ; +const MCExpr * Res ; +if ( getLexer ( ) . getKind ( ) != AsmToken :: Identifier ) { +return MatchOperand_NoMatch ; +StringRef Identifier ; +AsmToken Tok = getLexer ( ) . getTok ( ) ; +if ( getParser ( ) . parseIdentifier ( Identifier ) ) { +Error ( getLoc ( ) , "unknown identifier" ) ; +return MatchOperand_ParseFail ; +} +MCSymbol * Sym = getContext ( ) . getOrCreateSymbol ( Identifier ) ; +if ( Sym -> isVariable ( ) ) { +const MCExpr * V = Sym -> getVariableValue ( false ) ; +if ( ! isa < MCSymbolRefExpr > ( V ) ) { +getLexer ( ) . UnLex ( Tok ) ; +Error ( getLoc ( ) , "unknown symbol" ) ; +return MatchOperand_ParseFail ; +Res = V ; +if ( ! Sym -> isVariable ( ) ) { +if ( getLexer ( ) . getKind ( ) == AsmToken :: Plus ) { +Opcode = MCBinaryExpr :: Add ; +getLexer ( ) . Lex ( ) ; +const MCExpr * Expr ; +if ( getParser ( ) . parseExpression ( Expr ) ) { +Error ( getLoc ( ) , "unknown expression" ) ; +return MatchOperand_ParseFail ; +Operands . push_back ( RISCVOperand :: createImm ( Res , S , E , isRV64 ( ) ) ) ; +return MatchOperand_Success ; +if ( getLexer ( ) . getKind ( ) == AsmToken :: Minus ) { +getLexer ( ) . Lex ( ) ; +const MCExpr * Expr ; +if ( getParser ( ) . parseExpression ( Expr ) ) { +Error ( getLoc ( ) , "unknown expression" ) ; +return MatchOperand_ParseFail ; +Res = MCBinaryExpr :: create ( Opcode , Res , Expr , getContext ( ) ) ; +Operands . push_back ( RISCVOperand :: createImm ( Res , S , E , isRV64 ( ) ) ) ; +return MatchOperand_Success ; +if ( Kind != RISCVMCExpr :: VK_RISCV_None ) { +Operands . push_back ( RISCVOperand :: createImm ( Res , S , E , isRV64 ( ) ) ) ; +return MatchOperand_Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/parseRegister2.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/parseRegister2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..da461c3e070254982b71f830c0cda81a74b58bca --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/parseRegister2.cpp @@ -0,0 +1,12 @@ +OperandMatchResultTy RISCVAsmParser :: parseRegister ( OperandVector & Operands , bool AllowParens ) { +getLexer ( ) . Lex ( ) ; +SMLoc S = getLoc ( ) ; +StringRef Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; +unsigned RegNo = MatchRegisterName ( Name ) ; +if ( RegNo == 0 ) { +} +Operands . push_back ( RISCVOperand :: createReg ( RegNo , S , E ) ) ; +getLexer ( ) . Lex ( ) ; +Operands . push_back ( RISCVOperand :: createReg ( RegNo , S , E ) ) ; +return MatchOperand_Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/parseVTypeI.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/parseVTypeI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f9453627863d856327ea039c34b85fb4a8fff9df --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/parseVTypeI.cpp @@ -0,0 +1,42 @@ +OperandMatchResultTy RISCVAsmParser :: parseVTypeI ( OperandVector & Operands ) { +SMLoc S = getLoc ( ) ; +SMLoc E = SMLoc :: getFromPointer ( S . getPointer ( ) - 1 ) ; +const MCExpr * Res ; +if ( getLexer ( ) . getKind ( ) != AsmToken :: Identifier ) { +return MatchOperand_NoMatch ; +} +StringRef Identifier ; +AsmToken Tok = getLexer ( ) . getTok ( ) ; +if ( getParser ( ) . parseIdentifier ( Identifier ) ) { +Error ( getLoc ( ) , "unknown identifier" ) ; +return MatchOperand_ParseFail ; +MCSymbol * Sym = getContext ( ) . getOrCreateSymbol ( Identifier ) ; +if ( Sym -> isVariable ( ) ) { +const MCExpr * V = Sym -> getVariableValue ( false ) ; +if ( ! isa < MCSymbolRefExpr > ( V ) ) { +getLexer ( ) . UnLex ( Tok ) ; +Error ( getLoc ( ) , "unknown symbol" ) ; +return MatchOperand_ParseFail ; +Res = V ; +if ( ! Sym -> isVariable ( ) ) { +MCBinaryExpr :: Opcode Opcode ; +if ( getLexer ( ) . getKind ( ) == AsmToken :: Plus ) { +getLexer ( ) . Lex ( ) ; +const MCExpr * Expr ; +if ( getParser ( ) . parseExpression ( Expr ) ) { +Error ( getLoc ( ) , "unknown expression" ) ; +return MatchOperand_ParseFail ; +Operands . push_back ( RISCVOperand :: createImm ( Res , S , E , isRV64 ( ) ) ) ; +return MatchOperand_Success ; +if ( getLexer ( ) . getKind ( ) == AsmToken :: Minus ) { +getLexer ( ) . Lex ( ) ; +const MCExpr * Expr ; +if ( getParser ( ) . parseExpression ( Expr ) ) { +Error ( getLoc ( ) , "unknown expression" ) ; +return MatchOperand_ParseFail ; +Operands . push_back ( RISCVOperand :: createImm ( Res , S , E , isRV64 ( ) ) ) ; +return MatchOperand_Success ; +if ( Kind != RISCVMCExpr :: VK_RISCV_None ) { +Operands . push_back ( RISCVOperand :: createImm ( Res , S , E , isRV64 ( ) ) ) ; +return MatchOperand_Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/print.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/print.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a5f3c376b1ff726cf240aa6395af8524515c9140 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/print.cpp @@ -0,0 +1,14 @@ +void print ( raw_ostream & OS ) const override { +if ( Kind == KindTy :: Token ) { +} +if ( Kind == KindTy :: Register ) { +} +if ( Kind == KindTy :: Immediate ) { +OS << getImm ( ) ; +} +if ( Kind == KindTy :: SystemRegister ) { +OS << "Register<" << Reg . RegNum << ">" ; +} +if ( Kind == KindTy :: VType ) { +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/setFeatureBits.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/setFeatureBits.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e3842effdce3debb109d5ef4f747e2c8306b202a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/setFeatureBits.cpp @@ -0,0 +1,6 @@ +void setFeatureBits ( uint64_t Feature , StringRef FeatureString ) { +if ( ! ( getSTI ( ) . getFeatureBits ( ) [ Feature ] ) ) { +MCSubtargetInfo & STI = copySTI ( ) ; +setAvailableFeatures ( ComputeAvailableFeatures ( STI . ToggleFeature ( FeatureString ) ) ) ; +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/tryParseRegister.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/tryParseRegister.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c9e404b088afc46ccfbcd9337b714eaa8f83f69c --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/tryParseRegister.cpp @@ -0,0 +1,12 @@ +OperandMatchResultTy RISCVAsmParser :: tryParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc ) { +const AsmToken & Tok = getParser ( ) . getTok ( ) ; +StartLoc = Tok . getLoc ( ) ; +EndLoc = Tok . getEndLoc ( ) ; +RegNo = 0 ; +StringRef Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; +if ( matchRegisterNameHelper ( isRV32E ( ) , ( MCRegister & ) RegNo , Name ) ) { +return MatchOperand_NoMatch ; +} +getParser ( ) . Lex ( ) ; +return MatchOperand_Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/validateTargetOperandClass.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/validateTargetOperandClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8a172a68df22f4035b1504f173213c8778d78942 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmParser/validateTargetOperandClass.cpp @@ -0,0 +1,26 @@ +unsigned RISCVAsmParser :: validateTargetOperandClass ( MCParsedAsmOperand & AsmOp , unsigned Kind ) { +RISCVOperand & Op = static_cast < RISCVOperand & > ( AsmOp ) ; +if ( ! Op . isReg ( ) ) { +return Match_InvalidOperand ; +} +MCRegister Reg = Op . getReg ( ) ; +if ( RISCVMCRegisterClasses [ RISCV :: FPR64RegClassID ] . contains ( Reg ) ) { +if ( Kind == MCK_FPR32 ) { +Op . Reg . RegNum = convertFPR64ToFPR32 ( Reg ) ; +return Match_Success ; +} +} +if ( RISCVMCRegisterClasses [ RISCV :: FPR64CRegClassID ] . contains ( Reg ) ) { +if ( Kind == MCK_FPR32C ) { +Op . Reg . RegNum = convertFPR64ToFPR32 ( Reg ) ; +return Match_Success ; +} +} +if ( RISCVMCRegisterClasses [ RISCV :: FPR64RegClassID ] . contains ( Reg ) ) { +if ( Kind == MCK_FPR16 ) { +Op . Reg . RegNum = convertFPR64ToFPR16 ( Reg ) ; +return Match_Success ; +} +} +return Match_InvalidOperand ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmPrinter/AsmPrinter.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmPrinter/AsmPrinter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..16f537e752720d289295cf8da9cab4006ae1998d --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmPrinter/AsmPrinter.cpp @@ -0,0 +1,2 @@ +explicit RISCVAsmPrinter ( TargetMachine & TM , std :: unique_ptr < MCStreamer > Streamer ) : AsmPrinter ( TM , std :: move ( Streamer ) ) , STI ( TM . getMCSubtargetInfo ( ) ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmPrinter/EmitToStreamer.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmPrinter/EmitToStreamer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..646c88cbb09fd6dce5d8fa32492e94516c01b61d --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmPrinter/EmitToStreamer.cpp @@ -0,0 +1,8 @@ +void RISCVAsmPrinter :: EmitToStreamer ( MCStreamer & S , const MCInst & Inst ) { +MCInst CInst ; +bool Res = compressInst ( CInst , Inst , * STI , OutStreamer -> getContext ( ) ) ; +if ( Res ) { +RISCVNumInstrsCompressed = RISCVNumInstrsCompressed + 1 ; +} +AsmPrinter :: EmitToStreamer ( * OutStreamer , Res ? CInst : Inst ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmPrinter/LLVMInitializeAsmPrinter.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmPrinter/LLVMInitializeAsmPrinter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b24e72e9d94a1dfbcc584f27efc95ca49dbaeacd --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmPrinter/LLVMInitializeAsmPrinter.cpp @@ -0,0 +1,4 @@ +extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVAsmPrinter ( ) { +RegisterAsmPrinter < RISCVAsmPrinter > X ( getTheRISCV32Target ( ) ) ; +RegisterAsmPrinter < RISCVAsmPrinter > Y ( getTheRISCV64Target ( ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmPrinter/PrintAsmMemoryOperand.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmPrinter/PrintAsmMemoryOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6b370b61cf848ad846739f5b74af65bf0c582f85 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmPrinter/PrintAsmMemoryOperand.cpp @@ -0,0 +1,11 @@ +bool RISCVAsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & OS ) { +if ( ! ExtraCode ) { +const MachineOperand & MO = MI -> getOperand ( OpNo ) ; +if ( ! MO . isReg ( ) ) { +return true ; +} +OS << "0(" << RISCVInstPrinter :: getRegisterName ( MO . getReg ( ) ) << ")" ; +return false ; +} +return AsmPrinter :: PrintAsmMemoryOperand ( MI , OpNo , ExtraCode , OS ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmPrinter/PrintAsmOperand.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmPrinter/PrintAsmOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..dec09de81efbe7a48a4cb6201d6caa443a7e39cd --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmPrinter/PrintAsmOperand.cpp @@ -0,0 +1,47 @@ +bool RISCVAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & OS ) { +if ( ! AsmPrinter :: PrintAsmOperand ( MI , OpNo , ExtraCode , OS ) ) { +return false ; +} +const MachineOperand & MO = MI -> getOperand ( OpNo ) ; +if ( ExtraCode ) { +if ( ExtraCode [ 0 ] ) { +if ( ExtraCode [ 1 ] != 0 ) { +return true ; +} +if ( ExtraCode [ 0 ] == 'z' ) { +if ( MO . isImm ( ) ) { +if ( MO . getImm ( ) == 0 ) { +OS << RISCVInstPrinter :: getRegisterName ( RISCV::X0 ) ; +return false ; +} +} +} +if ( ExtraCode [ 0 ] == 'i' ) { +return false ; +if ( ! MO . isReg ( ) ) { +OS << 'i' ; +} +return false ; +} +return true ; +} +} +if ( MO . getType ( ) == MachineOperand :: MO_Immediate ) { +OS << MO . getImm ( ) ; +return false ; +} +if ( MO . getType ( ) == MachineOperand :: MO_Register ) { +OS << RISCVInstPrinter :: getRegisterName ( MO . getReg ( ) ) ; +return false ; +} +if ( MO . getType ( ) == MachineOperand :: MO_GlobalAddress ) { +PrintSymbolOperand ( MO , OS ) ; +return false ; +} +if ( MO . getType ( ) == MachineOperand :: MO_BlockAddress ) { +MCSymbol * Sym = GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ; +Sym -> print ( OS , MAI ) ; +return false ; +} +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmPrinter/emitAttributes.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmPrinter/emitAttributes.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3c99bad1d08c8201d92c0ef5b3c190e59513a5ed --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmPrinter/emitAttributes.cpp @@ -0,0 +1,9 @@ +void RISCVAsmPrinter :: emitAttributes ( ) { +RISCVTargetStreamer & CTS = static_cast < RISCVTargetStreamer & > ( * OutStreamer -> getTargetStreamer ( ) ) ; +const Triple & TT = TM . getTargetTriple ( ) ; +StringRef CPU = TM . getTargetCPU ( ) ; +StringRef FS = TM . getTargetFeatureString ( ) ; +const RISCVTargetMachine & CTM = static_cast < const RISCVTargetMachine & > ( TM ) ; +const RISCVSubtarget STI ( TT , CPU , CPU , FS , "" , CTM ) ; +CTS . emitTargetAttributes ( STI ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmPrinter/emitEndOfAsmFile.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmPrinter/emitEndOfAsmFile.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e06f058109d00ca5001bc10d865daae2c4b41c6f --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmPrinter/emitEndOfAsmFile.cpp @@ -0,0 +1,6 @@ +void RISCVAsmPrinter :: emitEndOfAsmFile ( Module & M ) { +RISCVTargetStreamer & CTS = static_cast < RISCVTargetStreamer & > ( * OutStreamer -> getTargetStreamer ( ) ) ; +if ( TM . getTargetTriple ( ) . isOSBinFormatELF ( ) ) { +CTS . finishAttributeSection ( ) ; +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmPrinter/emitInstruction.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmPrinter/emitInstruction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b47b09669bf20c8919d0e1a57ee54bd5d20b8904 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmPrinter/emitInstruction.cpp @@ -0,0 +1,8 @@ +void RISCVAsmPrinter :: emitInstruction ( const MachineInstr * MI ) { +if ( emitPseudoExpansionLowering ( * OutStreamer , MI ) ) { +return ; +} +MCInst TmpInst ; +LowerRISCVMachineInstrToMCInst ( MI , TmpInst , * this ) ; +EmitToStreamer ( * OutStreamer , TmpInst ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmPrinter/emitStartOfAsmFile.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmPrinter/emitStartOfAsmFile.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0d36026aab81bf16ac6a460144e015eb3624e364 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmPrinter/emitStartOfAsmFile.cpp @@ -0,0 +1,5 @@ +void RISCVAsmPrinter :: emitStartOfAsmFile ( Module & M ) { +if ( TM . getTargetTriple ( ) . isOSBinFormatELF ( ) ) { +emitAttributes ( ) ; +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmPrinter/getPassName.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmPrinter/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0b50c92eaed08ada36e5d2710491c498e29eb559 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmPrinter/getPassName.cpp @@ -0,0 +1,3 @@ +StringRef getPassName ( ) const override { +return "RISCV Assembly Printer" ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmPrinter/lowerOperand.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmPrinter/lowerOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cd0179bbd2efa82b653523e52ed6180f781702d8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmPrinter/lowerOperand.cpp @@ -0,0 +1,3 @@ +bool lowerOperand ( const MachineOperand & MO , MCOperand & MCOp ) const { +return LowerRISCVMachineOperandToMCOperand ( MO , MCOp , * this ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmPrinter/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmPrinter/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a0aec73549b527596768d6913e6804b300d261b5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Assembler/AsmPrinter/runOnMachineFunction.cpp @@ -0,0 +1,8 @@ +bool RISCVAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { +MCSubtargetInfo & NewSTI = OutStreamer -> getContext ( ) . getSubtargetCopy ( * TM . getMCSubtargetInfo ( ) ) ; +NewSTI . setFeatureBits ( MF . getSubtarget ( ) . getFeatureBits ( ) ) ; +STI = & NewSTI ; +SetupMachineFunction ( MF ) ; +emitFunctionBody ( ) ; +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/DecodeFPR16RegisterClass.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/DecodeFPR16RegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..438ed8eb4fa7b43dcc12846335d3f240cfd037a6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/DecodeFPR16RegisterClass.cpp @@ -0,0 +1,8 @@ +static DecodeStatus DecodeFPR16RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { +if ( RegNo >= 32 ) { +return MCDisassembler :: Fail ; +} +MCRegister Reg = RISCV :: F0_H + RegNo ; +Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; +return MCDisassembler :: Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/DecodeFPR32CRegisterClass.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/DecodeFPR32CRegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3c586c67826896e027b66fee36e0690d8a61a43d --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/DecodeFPR32CRegisterClass.cpp @@ -0,0 +1,8 @@ +static DecodeStatus DecodeFPR32CRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { +if ( RegNo >= 8 ) { +return MCDisassembler :: Fail ; +} +MCRegister Reg = RISCV :: F8_F + RegNo ; +Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; +return MCDisassembler :: Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/DecodeFPR32RegisterClass.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/DecodeFPR32RegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d0ea3c7ef976150683c0d854bec296f02c68066a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/DecodeFPR32RegisterClass.cpp @@ -0,0 +1,8 @@ +static DecodeStatus DecodeFPR32RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { +if ( RegNo >= 32 ) { +return MCDisassembler :: Fail ; +} +MCRegister Reg = RISCV :: F0_F + RegNo ; +Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; +return MCDisassembler :: Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/DecodeFPR64CRegisterClass.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/DecodeFPR64CRegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..38418f32892bf605a6524b1314e101fc126eea43 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/DecodeFPR64CRegisterClass.cpp @@ -0,0 +1,8 @@ +static DecodeStatus DecodeFPR64CRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { +if ( RegNo >= 8 ) { +return MCDisassembler :: Fail ; +} +MCRegister Reg = RISCV :: F8_D + RegNo ; +Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; +return MCDisassembler :: Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/DecodeFPR64RegisterClass.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/DecodeFPR64RegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ab271487b79b35ef83f33318b1cc7bd7b2aca17e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/DecodeFPR64RegisterClass.cpp @@ -0,0 +1,8 @@ +static DecodeStatus DecodeFPR64RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { +if ( RegNo >= 32 ) { +return MCDisassembler :: Fail ; +} +MCRegister Reg = RISCV :: F0_D + RegNo ; +Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; +return MCDisassembler :: Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/DecodeGPRCRegisterClass.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/DecodeGPRCRegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d3f7831de2c4b62d12a9fa5e980962d44681dfed --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/DecodeGPRCRegisterClass.cpp @@ -0,0 +1,8 @@ +static DecodeStatus DecodeGPRCRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { +if ( RegNo >= 8 ) { +return MCDisassembler :: Fail ; +} +MCRegister Reg = RISCV :: X8 + RegNo ; +Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; +return MCDisassembler :: Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/DecodeGPRNoX0RegisterClass.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/DecodeGPRNoX0RegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..56ff4ef117332d294d29a991c66a0c16ddc875eb --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/DecodeGPRNoX0RegisterClass.cpp @@ -0,0 +1,6 @@ +static DecodeStatus DecodeGPRNoX0RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { +if ( RegNo == 0 ) { +return MCDisassembler :: Fail ; +} +return DecodeGPRRegisterClass ( Inst , RegNo , Address , Decoder ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/DecodeGPRNoX0X2RegisterClass.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/DecodeGPRNoX0X2RegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d8457ffe1102124e0dd4741d2b73b167a715d018 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/DecodeGPRNoX0X2RegisterClass.cpp @@ -0,0 +1,6 @@ +static DecodeStatus DecodeGPRNoX0X2RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { +if ( RegNo == 2 ) { +return MCDisassembler :: Fail ; +} +return DecodeGPRNoX0RegisterClass ( Inst , RegNo , Address , Decoder ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/DecodeGPRRegisterClass.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/DecodeGPRRegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..65cd7f3b2c491ff9143a9b0365b2ccea182c366a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/DecodeGPRRegisterClass.cpp @@ -0,0 +1,8 @@ +static DecodeStatus DecodeGPRRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { +if ( RegNo >= 32 ) { +return MCDisassembler :: Fail ; +} +MCRegister Register = RISCV :: X0 + RegNo ; +Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; +return MCDisassembler :: Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/DecodeVRRegisterClass.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/DecodeVRRegisterClass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ffdf5bac4f0d26ee10fdda324016a778bf92f8f5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/DecodeVRRegisterClass.cpp @@ -0,0 +1,8 @@ +static DecodeStatus DecodeVRRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { +if ( RegNo >= 32 ) { +return MCDisassembler :: Fail ; +} +MCRegister Register = RISCV :: V0 + RegNo ; +Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; +return MCDisassembler :: Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/Disassembler.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/Disassembler.cpp new file mode 100644 index 0000000000000000000000000000000000000000..aaf52b15eb2b9451e7ae90324881988a0d52dd4c --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/Disassembler.cpp @@ -0,0 +1,2 @@ +RISCVDisassembler ( const MCSubtargetInfo & STI , MCContext & Ctx , MCInstrInfo const * MCII ) : MCDisassembler ( STI , Ctx ) , MCII ( MCII ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/LLVMInitializeDisassembler.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/LLVMInitializeDisassembler.cpp new file mode 100644 index 0000000000000000000000000000000000000000..69876f765610d0dc2d475e4c602703f8c8640aca --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/LLVMInitializeDisassembler.cpp @@ -0,0 +1,4 @@ +extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVDisassembler ( ) { +TargetRegistry :: RegisterMCDisassembler ( getTheRISCV32Target ( ) , createRISCVDisassembler ) ; +TargetRegistry :: RegisterMCDisassembler ( getTheRISCV64Target ( ) , createRISCVDisassembler ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/addImplySP.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/addImplySP.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5277347cfb4d3050b42af9cbc68e6e485a862cba --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/addImplySP.cpp @@ -0,0 +1,43 @@ +static void addImplySP ( MCInst & Inst , int64_t Address , const void * Decoder ) { +if ( Inst . getOpcode ( ) == RISCV :: C_LWSP ) { +DecodeGPRRegisterClass ( Inst , 2 , Address , Decoder ) ; +return ; +} +if ( Inst . getOpcode ( ) == RISCV :: C_LDSP ) { +DecodeGPRRegisterClass ( Inst , 2 , Address , Decoder ) ; +return ; +} +if ( Inst . getOpcode ( ) == RISCV :: C_SWSP ) { +DecodeGPRRegisterClass ( Inst , 2 , Address , Decoder ) ; +return ; +} +if ( Inst . getOpcode ( ) == RISCV :: C_SDSP ) { +DecodeGPRRegisterClass ( Inst , 2 , Address , Decoder ) ; +return ; +} +if ( Inst . getOpcode ( ) == RISCV :: C_FLWSP ) { +DecodeGPRRegisterClass ( Inst , 2 , Address , Decoder ) ; +return ; +} +if ( Inst . getOpcode ( ) == RISCV :: C_FLDSP ) { +DecodeGPRRegisterClass ( Inst , 2 , Address , Decoder ) ; +return ; +} +if ( Inst . getOpcode ( ) == RISCV :: C_FSWSP ) { +DecodeGPRRegisterClass ( Inst , 2 , Address , Decoder ) ; +return ; +} +if ( Inst . getOpcode ( ) == RISCV :: C_FSDSP ) { +DecodeGPRRegisterClass ( Inst , 2 , Address , Decoder ) ; +return ; +} +if ( Inst . getOpcode ( ) == RISCV :: C_ADDI4SPN ) { +DecodeGPRRegisterClass ( Inst , 2 , Address , Decoder ) ; +return ; +} +if ( Inst . getOpcode ( ) == RISCV :: C_ADDI16SP ) { +DecodeGPRRegisterClass ( Inst , 2 , Address , Decoder ) ; +DecodeGPRRegisterClass ( Inst , 2 , Address , Decoder ) ; +return ; +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/createDisassembler.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/createDisassembler.cpp new file mode 100644 index 0000000000000000000000000000000000000000..429c0843517943db25dd2e35cbc21449bd692d0e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/createDisassembler.cpp @@ -0,0 +1,3 @@ +static MCDisassembler * createRISCVDisassembler ( const Target & T , const MCSubtargetInfo & STI , MCContext & Ctx ) { +return new RISCVDisassembler ( STI , Ctx , T . createMCInstrInfo ( ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/decodeCLUIImmOperand.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/decodeCLUIImmOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5c57b9b63caf407ad7192aaed4e2f2f0915396be --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/decodeCLUIImmOperand.cpp @@ -0,0 +1,5 @@ +static DecodeStatus decodeCLUIImmOperand ( MCInst & Inst , uint64_t Imm , uint64_t Address , const void * Decoder ) { +assert ( isUInt < 6 > ( Imm ) ) && "Invalid immediate" ) ; +Inst . addOperand ( MCOperand :: createImm ( Imm > 31 ? ( SignExtend64 < 6 > ( Imm ) & 0xfffff ) : Imm ) ) ; +return MCDisassembler :: Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/decodeFRMArg.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/decodeFRMArg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ee39fe41a1d7a2989ce659dd881e764ff20b9bb2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/decodeFRMArg.cpp @@ -0,0 +1,8 @@ +static DecodeStatus decodeFRMArg ( MCInst & Inst , uint64_t Imm , uint64_t Address , const void * Decoder ) { +assert ( isUInt < 3 > ( Imm ) ) ; +if ( ! A64Imms :: isLogicalImmBits ( RegWidth , Bits , Imm ) ) { +return MCDisassembler :: Fail ; +} +Inst . addOperand ( MCOperand :: createImm ( Imm ) ) ; +return MCDisassembler :: Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/decodeRVCInstrRdRs1Rs2.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/decodeRVCInstrRdRs1Rs2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2ccc40a6af115452415a83ccf45a94001eba8130 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/decodeRVCInstrRdRs1Rs2.cpp @@ -0,0 +1,13 @@ +static DecodeStatus decodeRVCInstrRdRs1Rs2 ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { +unsigned d = fieldFromInstruction ( Insn , 7 , 5 ) ; +unsigned const9 = 0 ; +unsigned s1 = fieldFromInstruction ( Insn , 2 , 5 ) ; +DecodeStatus status = DecodeGPRRegisterClass ( Inst , d , Address , Decoder ) ; +if ( status != MCDisassembler :: Success ) { +return status ; +Inst . addOperand ( MCOperand :: createImm ( const9 ) ) ; +status = DecodeGPRRegisterClass ( Inst , s1 , Address , Decoder ) ; +if ( status != MCDisassembler :: Success ) { +return status ; +return MCDisassembler :: Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/decodeRVCInstrRdRs1UImm.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/decodeRVCInstrRdRs1UImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..da13f76689fe7263b763ab73458ee0c884ae8fab --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/decodeRVCInstrRdRs1UImm.cpp @@ -0,0 +1,10 @@ +static DecodeStatus decodeRVCInstrRdRs1UImm ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { +unsigned char op = ( insn >> 5 ) & 1 ; +unsigned char cmode = ( insn >> 8 ) & 0xF ; +unsigned char Imm8 = ( ( insn >> 24 ) & 1 ) << 7 | ( ( insn >> 16 ) & 7 ) << 4 | ( insn & 0xF ) ; +unsigned Offset = ( Insn & 0xffff ) ; +if ( Bits >= 16 ) { +return MCDisassembler :: Fail ; +} +return MCDisassembler :: Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/decodeRVCInstrRdRs2.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/decodeRVCInstrRdRs2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b6fe70e90426d71fb0e173b67252d7ff580dda1d --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/decodeRVCInstrRdRs2.cpp @@ -0,0 +1,13 @@ +static DecodeStatus decodeRVCInstrRdRs2 ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { +unsigned Rd = fieldFromInstruction ( Insn , 7 , 5 ) ; +unsigned Rs2 = fieldFromInstruction ( Insn , 2 , 5 ) ; +DecodeStatus status = DecodeGPRRegisterClass ( Inst , Rd , Address , Decoder ) ; +if ( status != MCDisassembler :: Success ) { +return status ; +} +status = DecodeGPRRegisterClass ( Inst , Rs2 , Address , Decoder ) ; +if ( status != MCDisassembler :: Success ) { +return status ; +} +return MCDisassembler :: Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/decodeRVCInstrRdSImm.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/decodeRVCInstrRdSImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f7c00f52c104a5b6628597191543ac6cf4dc8106 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/decodeRVCInstrRdSImm.cpp @@ -0,0 +1,18 @@ +static DecodeStatus decodeRVCInstrRdSImm ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { +unsigned char op = ( insn >> 5 ) & 1 ; +unsigned char cmode = ( insn >> 8 ) & 0xF ; +unsigned char Imm8 = ( ( insn >> 24 ) & 1 ) << 7 | ( ( insn >> 16 ) & 7 ) << 4 | ( insn & 0xF ) ; +unsigned Offset = ( Insn & 0xffff ) ; +if ( Bits >= 16 ) { +return MCDisassembler :: Fail ; +} +int64_t Imm = Bits + 1 ; +const JmpExtraValues * extra = ( reinterpret_cast < const JmpExtraValues * > ( Addr ) ) ; +uint64_t address = extra -> Address + extra -> Imm ; +if ( ! tryAddingSymbolicOperand ( address , 0 , true , 0 , Inst , Decoder ) ) { +Inst . addOperand ( MCOperand :: createImm ( extra -> Imm ) ) ; +} +unsigned Register = PredicateTable [ extra -> Predicate ] ; +Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; +return MCDisassembler :: Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/decodeRVCInstrSImm.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/decodeRVCInstrSImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0b3b7efb37c77265cefc5bea79aaf992cdecdb90 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/decodeRVCInstrSImm.cpp @@ -0,0 +1,18 @@ +static DecodeStatus decodeRVCInstrSImm ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { +unsigned char op = ( insn >> 5 ) & 1 ; +unsigned char cmode = ( insn >> 8 ) & 0xF ; +unsigned char Imm8 = ( ( insn >> 24 ) & 1 ) << 7 | ( ( insn >> 16 ) & 7 ) << 4 | ( insn & 0xF ) ; +unsigned Offset = ( Insn & 0xffff ) ; +if ( Bits >= 16 ) { +return MCDisassembler :: Fail ; +} +int64_t Imm = Bits + 1 ; +const JmpExtraValues * extra = ( reinterpret_cast < const JmpExtraValues * > ( Addr ) ) ; +uint64_t address = extra -> Address + extra -> Imm ; +if ( ! tryAddingSymbolicOperand ( address , 0 , true , 0 , Inst , Decoder ) ) { +Inst . addOperand ( MCOperand :: createImm ( extra -> Imm ) ) ; +} +unsigned Register = PredicateTable [ extra -> Predicate ] ; +Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; +return MCDisassembler :: Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/decodeSImmNonZeroOperand.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/decodeSImmNonZeroOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..992cc6c7a54db0d62e19897ac2e09341bf7660d9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/decodeSImmNonZeroOperand.cpp @@ -0,0 +1,9 @@ +template < unsigned N > static DecodeStatus decodeSImmNonZeroOperand ( MCInst & Inst , uint64_t Imm , int64_t Address , const void * Decoder ) { +if ( Imm == 0 ) { +return MCDisassembler :: Fail ; +} +assert ( isUInt < N > ( Imm ) && "Invalid immediate" ) ; +addImplySP ( Inst , Address , Decoder ) ; +Inst . addOperand ( MCOperand :: createImm ( SignExtend64 < N > ( Imm ) ) ) ; +return MCDisassembler :: Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/decodeSImmOperand.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/decodeSImmOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c89f4af3b6e532a7cc8a1dd52b006ba415a839ec --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/decodeSImmOperand.cpp @@ -0,0 +1,6 @@ +template < unsigned N > static DecodeStatus decodeSImmOperand ( MCInst & Inst , uint64_t Imm , int64_t Address , const void * Decoder ) { +assert ( isUInt < N > ( Imm ) && "Invalid immediate" ) ; +addImplySP ( Inst , Address , Decoder ) ; +Inst . addOperand ( MCOperand :: createImm ( SignExtend64 < N > ( Imm ) ) ) ; +return MCDisassembler :: Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/decodeSImmOperandAndLsl1.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/decodeSImmOperandAndLsl1.cpp new file mode 100644 index 0000000000000000000000000000000000000000..15963ce120e841adbc2f7e17ae57d854431f5c0a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/decodeSImmOperandAndLsl1.cpp @@ -0,0 +1,5 @@ +template < unsigned N > static DecodeStatus decodeSImmOperandAndLsl1 ( MCInst & Inst , uint64_t Imm , int64_t Address , const void * Decoder ) { +assert ( isUInt < N > ( Imm ) && "Invalid immediate" ) ; +Inst . addOperand ( MCOperand :: createImm ( SignExtend64 < N > ( Imm << 1 ) ) ) ; +return MCDisassembler :: Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/decodeUImmNonZeroOperand.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/decodeUImmNonZeroOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..886faa3bb851945909f1de7e3c6d8b33d9176807 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/decodeUImmNonZeroOperand.cpp @@ -0,0 +1,9 @@ +template < unsigned N > static DecodeStatus decodeUImmNonZeroOperand ( MCInst & Inst , uint64_t Imm , int64_t Address , const void * Decoder ) { +if ( Imm == 0 ) { +return MCDisassembler :: Fail ; +} +assert ( isUInt < N > ( Imm ) && "Invalid immediate" ) ; +addImplySP ( Inst , Address , Decoder ) ; +Inst . addOperand ( MCOperand :: createImm ( Imm ) ) ; +return MCDisassembler :: Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/decodeUImmOperand.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/decodeUImmOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..202289bb54a00b03168ee8c05ae14e224c690da1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/decodeUImmOperand.cpp @@ -0,0 +1,6 @@ +template < unsigned N > static DecodeStatus decodeUImmOperand ( MCInst & Inst , uint64_t Imm , int64_t Address , const void * Decoder ) { +assert ( isUInt < N > ( Imm ) && "Invalid immediate" ) ; +addImplySP ( Inst , Address , Decoder ) ; +Inst . addOperand ( MCOperand :: createImm ( Imm ) ) ; +return MCDisassembler :: Success ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/decodeVMaskReg.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/decodeVMaskReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..618789d584de399cdb9b44593e652bdcadbed945 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/decodeVMaskReg.cpp @@ -0,0 +1,14 @@ +static DecodeStatus decodeVMaskReg ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { +MCRegister Reg = RISCV :: NoRegister ; +return MCDisassembler :: Success ; +return MCDisassembler :: Success ; +if ( RegNo == 0 ) { +Inst . addOperand ( MCOperand :: createReg ( RISCV :: V0 ) ) ; +return MCDisassembler :: Success ; +} +if ( RegNo == 1 ) { +Inst . addOperand ( MCOperand :: createReg ( RISCV :: NoRegister ) ) ; +return MCDisassembler :: Success ; +} +return MCDisassembler :: Fail ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/getInstruction.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/getInstruction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..74ff7e3b6cf9a344c5ce073b2fd8a390bcc46284 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Disassembler/Disassembler/getInstruction.cpp @@ -0,0 +1,69 @@ +DecodeStatus RISCVDisassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & CS ) const { +DecodeStatus Result ; +if ( Bytes . size ( ) < 2 ) { +Size = 0 ; +return Fail ; +} +if ( ( Bytes [ 1 ] & 0xF7 ) >> 3 < 0x08 ) { +if ( Bytes . size ( ) < 4 ) { +Size = 0 ; +return Fail ; +} +if ( Bytes . size ( ) >= 8 ) { +uint64_t Insn64 ; +if ( ! readInstruction64 ( Bytes , Address , Size , Insn64 ) ) { +return Fail ; +} +Result = decodeInstruction ( DecoderTable64 , Instr , Insn64 , Address , this , STI ) ; +if ( Success == Result ) { +LLVM_DEBUG ( dbgs ( ) << "Successfully decoded 64-bit instruction." ) ; +return Result ; +} +LLVM_DEBUG ( dbgs ( ) << "Not a 64-bit instruction, falling back to 32-bit." ) ; +} +uint32_t Insn32 ; +if ( ! readInstruction32 ( Bytes , Address , Size , Insn32 ) ) { +return Fail ; +} +return decodeInstruction ( DecoderTable32 , Instr , Insn32 , Address , this , STI ) ; +} +if ( ( Bytes [ 1 ] & 0xF7 ) >> 3 >= 0x08 ) { +if ( Bytes . size ( ) >= 6 ) { +uint64_t Insn48 ; +if ( ! readInstruction48 ( Bytes , Address , Size , Insn48 ) ) { +return Fail ; +} +Result = decodeInstruction ( DecoderTable48 , Instr , Insn48 , Address , this , STI ) ; +if ( Success == Result ) { +LLVM_DEBUG ( dbgs ( ) << "Successfully decoded 16-bit instruction with limm." ) ; +return Result ; +} +LLVM_DEBUG ( dbgs ( ) << "Not a 16-bit instruction with limm, try without it." ) ; +} +uint32_t Insn16 ; +if ( ! readInstruction16 ( Bytes , Address , Size , Insn16 ) ) { +return Fail ; +} +return decodeInstruction ( DecoderTable16 , Instr , Insn16 , Address , this , STI ) ; +} +uint32_t Inst ; +if ( Bytes [ 0 ] & 1 == 1 ) { +if ( Bytes . size ( ) < 3 ) { +Size = 0 ; +return MCDisassembler :: Fail ; +} +Inst = Bytes [ 0 ] | ( Bytes [ 1 ] << 8 ) | ( Bytes [ 2 ] << 16 ) ; +LLVM_DEBUG ( dbgs ( ) << "Trying RISCV 24bit table :\n" ) ; +Result = decodeInstruction ( DecoderTable24 , MI , Inst , Address , this , STI ) ; +} +if ( Bytes [ 0 ] & 1 != 1 ) { +if ( Bytes . size ( ) < 2 ) { +Size = 0 ; +return MCDisassembler :: Fail ; +} +Inst = support :: endian :: read16le ( Bytes . data ( ) ) ; +LLVM_DEBUG ( dbgs ( ) << "Trying RISCV 16bit table :\n" ) ; +Result = decodeInstruction ( DecoderTable16 , MI , Inst , Address , this , STI ) ; +} +return Result ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/AsmBackend.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/AsmBackend.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f3ccad163ecc1f7ba6605caf2a1e494c8d965401 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/AsmBackend.cpp @@ -0,0 +1,2 @@ +RISCVAsmBackend ( const MCSubtargetInfo & STI , uint8_t OSABI , bool Is64Bit , const MCTargetOptions & Options ) : MCAsmBackend ( support :: little ) , STI ( STI ) , OSABI ( OSABI ) , Is64Bit ( Is64Bit ) , TargetOptions ( Options ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/adjustFixupValue.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/adjustFixupValue.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4fbaab906d82133cff812ce8b9b5fd7d29ee3573 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/adjustFixupValue.cpp @@ -0,0 +1,82 @@ +static uint64_t adjustFixupValue ( const MCFixup & Fixup , uint64_t Value , MCContext & Ctx ) { +unsigned Kind ; +Kind = Fixup . getTargetKind ( ) ; +if ( Kind == FK_Data_1 ) { +return Value ; +} +if ( Kind == FK_Data_2 ) { +return Value ; +} +if ( Kind == FK_Data_4 ) { +return Value ; +} +if ( Kind == FK_Data_8 ) { +return Value ; +} +if ( Kind == FK_Data_6b ) { +return Value ; +} +if ( Kind == RISCV :: fixup_RISCV_lo12_i ) { +return Value & 0xfff ; +} +if ( Kind == RISCV :: fixup_RISCV_pcrel_lo12_i ) { +return Value & 0xfff ; +} +if ( Kind == RISCV :: fixup_RISCV_tprel_lo12_i ) { +return Value & 0xfff ; +} +if ( Kind == RISCV :: fixup_RISCV_lo12_s ) { +return ( ( ( Value >> 5 ) & 0x7f ) << 25 ) | ( ( Value & 0x1f ) << 7 ) ; +if ( Kind == RISCV :: fixup_RISCV_pcrel_lo12_s ) { +return ( ( ( Value >> 5 ) & 0x7f ) << 25 ) | ( ( Value & 0x1f ) << 7 ) ; +} +if ( Kind == RISCV :: fixup_RISCV_tprel_lo12_s ) { +return ( ( ( Value >> 5 ) & 0x7f ) << 25 ) | ( ( Value & 0x1f ) << 7 ) ; +} +if ( Kind == RISCV :: fixup_RISCV_hi20 ) { +return ( ( Value + 0x800 ) >> 12 ) & 0xfffff ; +} +if ( Kind == RISCV :: fixup_RISCV_pcrel_hi20 ) { +return ( ( Value + 0x800 ) >> 12 ) & 0xfffff ; +} +if ( Kind == RISCV :: fixup_RISCV_tprel_hi20 ) { +return ( ( Value + 0x800 ) >> 12 ) & 0xfffff ; +} +if ( Kind == RISCV :: fixup_RISCV_call ) { +return ( ( Value + 0x800ULL ) & 0xfffff000ULL ) | ( ( ( Value & 0xfffULL ) << 20 ) << 32 ) ; +} +if ( Kind == RISCV :: fixup_RISCV_call_plt ) { +return ( ( Value + 0x800ULL ) & 0xfffff000ULL ) | ( ( ( Value & 0xfffULL ) << 20 ) << 32 ) ; +} +if ( Kind == RISCV :: fixup_RISCV_rvc_jump ) { +return ( ( ( Value >> 11 ) & 0x1 ) << 10 ) | ( ( ( Value >> 4 ) & 0x1 ) << 9 ) | ( ( ( Value >> 8 ) & 0x3 ) << 7 ) | ( ( Value >> 10 ) & 0x1 ) << 6 ) | ( ( Value >> 6 ) & 0x1 ) << 5 ) | ( ( Value >> 7 ) & 0x1 ) << 4 ) | ( ( Value >> 1 ) & 0x7 ) << 1 ) ; +} +if ( Kind == RISCV :: fixup_RISCV_rvc_branch ) { +return ( ( ( Value >> 8 ) & 0x1 ) << 12 ) | ( ( ( Value >> 3 ) & 0x3 ) << 5 ) | ( ( ( Value >> 6 ) & 0x3 ) << 3 ) ; +} +if ( Kind == RISCV :: fixup_RISCV_tls_got_hi20 ) { +} +if ( Kind == RISCV :: fixup_RISCV_tls_gd_hi20 ) { +} +if ( Kind == RISCV :: fixup_RISCV_got_hi20 ) { +} +if ( Kind == RISCV :: fixup_RISCV_branch ) { +if ( ! isInt < 13 > ( Value ) ) { +Ctx . reportError ( Fixup . getLoc ( ) , "fixup value out of range" ) ; +} +if ( Value & 0x1 ) { +Ctx . reportError ( Fixup . getLoc ( ) , "fixup value must be 2-byte aligned." ) ; +} +return ( ( ( Value >> 12 ) & 0x1 ) << 31 ) | ( ( ( Value >> 5 ) & 0x3f ) << 25 ) | ( ( ( Value >> 1 ) & 0x1 ) << 7 ) ; +} +if ( Kind == RISCV :: fixup_RISCV_jal ) { +if ( ! isInt < 21 > ( Value ) ) { +Ctx . reportError ( Fixup . getLoc ( ) , "fixup value out of range" ) ; +} +if ( Value & 0x1 ) { +Ctx . reportError ( Fixup . getLoc ( ) , "fixup value must be 2-byte aligned." ) ; +} +return ( ( ( Value >> 20 ) & 0x1 ) << 19 ) | ( ( ( Value >> 11 ) & 0x1 ) << 8 ) ; +} +llvm_unreachable ( "Unknown fixup kind!" ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/applyFixup.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/applyFixup.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ef1791179287245f5d5790048f77538bb0544142 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/applyFixup.cpp @@ -0,0 +1,25 @@ +void RISCVAsmBackend :: applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved , const MCSubtargetInfo * STI ) const { +MCFixupKind Kind ; +Kind = Fixup . getKind ( ) ; +if ( Kind >= FirstLiteralRelocationKind ) { +return ; +} +MCContext & Ctx = Asm . getContext ( ) ; +if ( ! Value ) { +return ; +} +MCFixupKindInfo Info ; +Info = getFixupKindInfo ( Kind ) ; +Value = adjustFixupValue ( Fixup , Value , Ctx ) << Info . TargetOffset ; +unsigned Offset ; +Offset = Fixup . getOffset ( ) ; +unsigned NumBytes ; +NumBytes = alignTo ( Info . TargetSize + Info . TargetOffset , 8 ) / 8 ; +assert ( Offset + NumBytes <= Data . size ( ) && "Invalid fixup offset!" ) ; +if ( MCAsmBackend :: Endian == support :: little ) { +unsigned i ; +for ( i = 0 ; i != NumBytes ; ++ i ) { +Data [ Offset + i ] = Data [ Offset + i ] | uint8_t ( ( Value >> ( i * 8 ) ) & 0xff ) ; +} +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/createAsmBackend.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/createAsmBackend.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0a02ecfbf52f1df5a0ecc4b8c126cb96cea2139d --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/createAsmBackend.cpp @@ -0,0 +1,5 @@ +MCAsmBackend * llvm :: createRISCVAsmBackend ( const Target & T , const MCSubtargetInfo & STI , const MCRegisterInfo & MRI , const MCTargetOptions & Options ) { +const Triple & TT = STI . getTargetTriple ( ) ; +uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TT . getOS ( ) ) ; +return new RISCVAsmBackend ( STI , OSABI , TT . isArch64Bit ( ) , Options ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/createObjectTargetWriter.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/createObjectTargetWriter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e5a626f4079ae4a47f94b480285452f41ce66146 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/createObjectTargetWriter.cpp @@ -0,0 +1,4 @@ +std :: unique_ptr < MCObjectTargetWriter > RISCVAsmBackend :: createObjectTargetWriter ( ) const { +StringRef CPU ( "Default" ) ; +return createRISCVELFObjectWriter ( OSABI , Is64Bit ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/evaluateTargetFixup.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/evaluateTargetFixup.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a28a0b16ce7a196c9c530a8fb7ee36b719ebad42 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/evaluateTargetFixup.cpp @@ -0,0 +1,2 @@ +bool RISCVAsmBackend :: evaluateTargetFixup ( const MCAssembler & Asm , const MCAsmLayout & Layout , const MCFixup & Fixup , const MCFragment * DF , const MCValue & Target , uint64_t & Value , bool & WasForced ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/fixupNeedsRelaxation.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/fixupNeedsRelaxation.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6824221f10a156ddf44d2dae960a7bc794ab14c1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/fixupNeedsRelaxation.cpp @@ -0,0 +1,3 @@ +bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override { +llvm_unreachable ( "Handled by fixupNeedsRelaxationAdvanced" ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/fixupNeedsRelaxationAdvanced.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/fixupNeedsRelaxationAdvanced.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b687e7d7b0e0dcd5058c1fa9a94a4087b72e5d73 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/fixupNeedsRelaxationAdvanced.cpp @@ -0,0 +1,16 @@ +bool RISCVAsmBackend :: fixupNeedsRelaxationAdvanced ( const MCFixup & Fixup , bool Resolved , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout , const bool WasForced ) const { +if ( ! Resolved ) { +if ( ! WasForced ) { +return true ; +} +} +int64_t Offset ; +Offset = int64_t ( Value ) ; +if ( Fixup . getTargetKind ( ) == RISCV :: fixup_RISCV_rvc_branch ) { +return Offset > 254 || Offset < - 256 ; +} +if ( Fixup . getTargetKind ( ) == RISCV :: fixup_RISCV_rvc_jump ) { +return Offset > 2046 || Offset < -2048 ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/getFixupKind.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/getFixupKind.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0cc5ce29f9ae415aa8ef91f87dcdb22a8cbc67cb --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/getFixupKind.cpp @@ -0,0 +1,11 @@ +Optional < MCFixupKind > RISCVAsmBackend :: getFixupKind ( StringRef Name ) const { +if ( STI . getTargetTriple ( ) . isOSBinFormatELF ( ) ) { +unsigned Type ; +Type = llvm :: StringSwitch < unsigned > ( Name ) +. Default ( - 1u ) ; +if ( Type != - 1u ) { +return static_cast < MCFixupKind > ( FirstLiteralRelocationKind + Type ) ; +} +} +return None ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/getFixupKindInfo.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/getFixupKindInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b5c6c142f38f5d2e3016ed2d6002331a469f3414 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/getFixupKindInfo.cpp @@ -0,0 +1,33 @@ +const MCFixupKindInfo & RISCVAsmBackend :: getFixupKindInfo ( MCFixupKind Kind ) const { +const static MCFixupKindInfo Infos [ RISCV :: NumTargetFixupKinds ] = { +{ "fixup_RISCV_hi20" , 12 , 20 , 0 } , +{ "fixup_RISCV_lo12_i" , 20 , 12 , 0 } , +{ "fixup_RISCV_lo12_s" , 0 , 32 , 0 } , +{ "fixup_RISCV_pcrel_hi20" , 12 , 20 , MCFixupKindInfo :: FKF_IsPCRel } , +{ "fixup_RISCV_pcrel_lo12_i" , 20 , 12 , MCFixupKindInfo :: FKF_IsPCRel } , +{ "fixup_RISCV_pcrel_lo12_s" , 0 , 32 , MCFixupKindInfo :: FKF_IsPCRel } , +{ "fixup_RISCV_got_hi20" , 12 , 20 , MCFixupKindInfo :: FKF_IsPCRel } , +{ "fixup_RISCV_tprel_hi20" , 12 , 20 , 0 } , +{ "fixup_RISCV_tprel_lo12_i" , 20 , 12 , 0 } , +{ "fixup_RISCV_tprel_lo12_s" , 0 , 32 , 0 } , +{ "fixup_RISCV_tprel_add" , 0 , 0 , 0 } , +{ "fixup_RISCV_tls_got_hi20" , 12 , 20 , MCFixupKindInfo :: FKF_IsPCRel } , +{ "fixup_RISCV_tls_gd_hi20" , 12 , 20 , MCFixupKindInfo :: FKF_IsPCRel } , +{ "fixup_RISCV_jal" , 12 , 20 , MCFixupKindInfo :: FKF_IsPCRel } , +{ "fixup_RISCV_branch" , 0 , 32 , MCFixupKindInfo :: FKF_IsPCRel } , +{ "fixup_RISCV_rvc_jump" , 2 , 11 , MCFixupKindInfo :: FKF_IsPCRel } , +{ "fixup_RISCV_rvc_branch" , 0 , 16 , MCFixupKindInfo :: FKF_IsPCRel } , +{ "fixup_RISCV_call" , 0 , 64 , MCFixupKindInfo :: FKF_IsPCRel } , +{ "fixup_RISCV_call_plt" , 0 , 64 , MCFixupKindInfo :: FKF_IsPCRel } , +{ "fixup_RISCV_relax" , 0 , 0 , 0 } , +{ "fixup_RISCV_align" , 0 , 0 , 0 } +} ; +if ( Kind >= FirstLiteralRelocationKind ) { +return MCAsmBackend :: getFixupKindInfo ( FK_NONE ) ; +} +if ( Kind < FirstTargetFixupKind ) { +return MCAsmBackend :: getFixupKindInfo ( Kind ) ; +} +assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && "Invalid kind!" ) ; +return Infos [ Kind - FirstTargetFixupKind ] ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/getNumFixupKinds.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/getNumFixupKinds.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2e384712e31f1224918b8164a855d6593c11d35f --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/getNumFixupKinds.cpp @@ -0,0 +1,3 @@ +unsigned getNumFixupKinds ( ) const override { +return RISCV :: NumTargetFixupKinds ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/getRelaxedOpcode.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/getRelaxedOpcode.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7c7458d9fc88972746f70e586856a9a018c2c189 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/getRelaxedOpcode.cpp @@ -0,0 +1,15 @@ +unsigned RISCVAsmBackend :: getRelaxedOpcode ( unsigned Op ) const { +if ( Op == RISCV :: C_BEQZ ) { +return RISCV :: BEQ ; +} +if ( Op == RISCV :: C_BNEZ ) { +return RISCV :: BNE ; +} +if ( Op == RISCV :: C_J ) { +return RISCV :: JAL ; +} +if ( Op == RISCV :: C_JAL ) { +return RISCV :: JAL ; +} +return Op ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/getTargetABI.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/getTargetABI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..16ae15472632097d3075aff0875c283e8990edc2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/getTargetABI.cpp @@ -0,0 +1,3 @@ +RISCVABI :: ABI getTargetABI ( ) const { +return TargetABI ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/getTargetOptions.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/getTargetOptions.cpp new file mode 100644 index 0000000000000000000000000000000000000000..05f473298a9cd8a5b183051967a9322c84a1a94b --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/getTargetOptions.cpp @@ -0,0 +1,3 @@ +const MCTargetOptions & getTargetOptions ( ) const { +return TargetOptions ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/mayNeedRelaxation.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/mayNeedRelaxation.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5d314eb6f86b70b1e6f50774e935a9ef84737203 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/mayNeedRelaxation.cpp @@ -0,0 +1,15 @@ +bool RISCVAsmBackend :: mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo & STI ) const { +if ( Inst . getOpcode ( ) == RISCV :: C_BEQZ ) { +return true ; +} +if ( Inst . getOpcode ( ) == RISCV :: C_BNEZ ) { +return true ; +} +if ( Inst . getOpcode ( ) == RISCV :: C_J ) { +return true ; +} +if ( Inst . getOpcode ( ) == RISCV :: C_JAL ) { +return true ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/relaxInstruction.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/relaxInstruction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..40dde0e565ddd30e63ddcb4942df4aa5a4b4ce0a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/relaxInstruction.cpp @@ -0,0 +1,32 @@ +void RISCVAsmBackend :: relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , MCInst & Res ) const { +MCInst Res ; +if ( Inst . getOpcode ( ) == RISCV :: C_BEQZ ) { +Res . setOpcode ( RISCV :: BEQ ) ; +Res . addOperand ( Inst . getOperand ( 0 ) ) ; +Res . addOperand ( Inst . getOperand ( 1 ) ) ; +Inst = std :: move ( Res ) ; +return ; +} +if ( Inst . getOpcode ( ) == RISCV :: C_BNEZ ) { +Res . setOpcode ( RISCV :: BNE ) ; +Res . addOperand ( Inst . getOperand ( 0 ) ) ; +Res . addOperand ( Inst . getOperand ( 1 ) ) ; +Inst = std :: move ( Res ) ; +return ; +} +if ( Inst . getOpcode ( ) == RISCV :: C_J ) { +Res . setOpcode ( RISCV :: JAL ) ; +Res . addOperand ( MCOperand :: createReg ( RISCV :: X0 ) ) ; +Res . addOperand ( Inst . getOperand ( 0 ) ) ; +Inst = std :: move ( Res ) ; +return ; +} +if ( Inst . getOpcode ( ) == RISCV :: C_JAL ) { +Res . setOpcode ( RISCV :: JAL ) ; +Res . addOperand ( MCOperand :: createReg ( RISCV :: X1 ) ) ; +Res . addOperand ( Inst . getOperand ( 0 ) ) ; +Inst = std :: move ( Res ) ; +return ; +} +llvm_unreachable ( "Opcode not expected!" ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/requiresDiffExpressionRelocations.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/requiresDiffExpressionRelocations.cpp new file mode 100644 index 0000000000000000000000000000000000000000..70b0bfdc43c4485cd0e1c2f2d81a025929be3415 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/requiresDiffExpressionRelocations.cpp @@ -0,0 +1,3 @@ +bool requiresDiffExpressionRelocations ( ) const override { +return STI . getFeatureBits ( ) [ RISCV :: FeatureRelax ] ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/setForceRelocs.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/setForceRelocs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b44816c017c6bd035ed1453ab624e78566974b0a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/setForceRelocs.cpp @@ -0,0 +1,3 @@ +void setForceRelocs ( ) { +ForceRelocs = true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/shouldForceRelocation.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/shouldForceRelocation.cpp new file mode 100644 index 0000000000000000000000000000000000000000..dcb6104e7c19c2dc80342346e6d6f8f51d27f869 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/shouldForceRelocation.cpp @@ -0,0 +1,22 @@ +bool RISCVAsmBackend :: shouldForceRelocation ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target ) { +if ( Fixup . getTargetKind ( ) >= FirstLiteralRelocationKind ) { +return true ; +} +if ( Fixup . getTargetKind ( ) == FK_Data_1 ) { +} +if ( Fixup . getTargetKind ( ) == FK_Data_2 ) { +} +if ( Fixup . getTargetKind ( ) == FK_Data_4 ) { +} +if ( Fixup . getTargetKind ( ) == FK_Data_8 ) { +} +if ( Fixup . getTargetKind ( ) == RISCV :: fixup_RISCV_got_hi20 ) { +return true ; +} +if ( Fixup . getTargetKind ( ) == RISCV :: fixup_RISCV_tls_got_hi20 ) { +return true ; +} +if ( Fixup . getTargetKind ( ) == RISCV :: fixup_RISCV_tls_gd_hi20 ) { +return true ; +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/shouldInsertExtraNopBytesForCodeAlign.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/shouldInsertExtraNopBytesForCodeAlign.cpp new file mode 100644 index 0000000000000000000000000000000000000000..42eb8482a306174c0d6de48ca59f669d887a152e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/shouldInsertExtraNopBytesForCodeAlign.cpp @@ -0,0 +1,2 @@ +bool RISCVAsmBackend :: shouldInsertExtraNopBytesForCodeAlign ( MCAssembler & Asm , const MCAsmLayout & Layout , MCAlignFragment & AF ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/shouldInsertFixupForCodeAlign.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/shouldInsertFixupForCodeAlign.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bbaa8a8cef726ec33ab224b5ec9eb1ee20e30791 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/shouldInsertFixupForCodeAlign.cpp @@ -0,0 +1,2 @@ +bool RISCVAsmBackend :: shouldInsertFixupForCodeAlign ( MCAssembler & Asm , const MCAsmLayout & Layout , MCAlignFragment & AF ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/willForceRelocations.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/willForceRelocations.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ea95b54b2648866cf36a85d4fbc49f76091a9e35 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/willForceRelocations.cpp @@ -0,0 +1,3 @@ +bool willForceRelocations ( ) const { +return STI . getFeatureBits ( ) [ RISCV :: FeatureRelax ] ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/writeNopData.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/writeNopData.cpp new file mode 100644 index 0000000000000000000000000000000000000000..07ba71c0e99b3fc21ff907fa36e4a982d4b34be0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/writeNopData.cpp @@ -0,0 +1,14 @@ +bool RISCVAsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count ) const { +if ( Count % 2 != 0 ) { +return false ; +} +uint64_t NopCount = Count / 4 ; +uint64_t i ; +for ( i = 0 ; i < NopCount ; ++ i ) { +OS . write ( "\x13\0\0\0" , 4 ) ; +} +if ( Count % 4 == 2 ) { +OS . write ( "\x01\0" , 2 ) ; +} +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/~AsmBackend.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/~AsmBackend.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e505164f0c43be83f2076dbdb87f868bffa3c7fa --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmBackend/~AsmBackend.cpp @@ -0,0 +1,2 @@ +~ RISCVAsmBackend ( ) override { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmInfo/MCAsmInfo.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmInfo/MCAsmInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..09ec79aa5652e41d9c97fdd975557b6633e9c38b --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmInfo/MCAsmInfo.cpp @@ -0,0 +1,10 @@ +RISCVMCAsmInfo :: RISCVMCAsmInfo ( const Triple & TT ) { +CodePointerSize = TT . isArch64Bit ( ) ? 8 : 4 ; +CalleeSaveStackSlotSize = TT . isArch64Bit ( ) ? 8 : 4 ; +CommentString = "#" ; +AlignmentIsInBytes = false ; +SupportsDebugInformation = true ; +ExceptionsType = ExceptionHandling :: DwarfCFI ; +Data16bitsDirective = "\t.half\t" ; +Data32bitsDirective = "\t.word\t" ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmInfo/anchor.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmInfo/anchor.cpp new file mode 100644 index 0000000000000000000000000000000000000000..96bc88165c00542f48dd672a1d987b5a47b732d8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmInfo/anchor.cpp @@ -0,0 +1,2 @@ +void RISCVMCAsmInfo :: anchor ( ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmInfo/getExprForFDESymbol.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmInfo/getExprForFDESymbol.cpp new file mode 100644 index 0000000000000000000000000000000000000000..759b43e0954d2bb35a82f614cea5d58a28769b52 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/AsmInfo/getExprForFDESymbol.cpp @@ -0,0 +1,7 @@ +const MCExpr * RISCVMCAsmInfo :: getExprForFDESymbol ( const MCSymbol * Sym , unsigned Encoding , MCStreamer & Streamer ) const { +if ( Encoding & dwarf :: DW_EH_PE_pcrel ) { +MCContext & Ctx = Streamer . getContext ( ) ; +return RISCVMCExpr :: create ( MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_RISCV_None , Ctx ) , RISCVMCExpr :: VK_32_PCREL , Ctx ) ; +} +return MCAsmInfo :: getExprForFDESymbol ( Sym , Encoding , Streamer ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/BaseInfo/ABI.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/BaseInfo/ABI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..344e5390354582b3fcc0654dedcf88d18f31172b --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/BaseInfo/ABI.cpp @@ -0,0 +1,10 @@ +enum ABI { +ABI_ILP32 , +ABI_ILP32F , +ABI_ILP32D , +ABI_ILP32E , +ABI_LP64 , +ABI_LP64F , +ABI_LP64D , +ABI_Unknown +} ; \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/BaseInfo/FenceField.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/BaseInfo/FenceField.cpp new file mode 100644 index 0000000000000000000000000000000000000000..951b42ade0ebffe40b0910851cdb0d179096c57e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/BaseInfo/FenceField.cpp @@ -0,0 +1,6 @@ +enum FenceField { +I = 8 , +O = 4 , +R = 2 , +W = 1 +} ; \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/BaseInfo/II.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/BaseInfo/II.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9ae6a489bc110aa986382c2d5a8cdb90626bcd11 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/BaseInfo/II.cpp @@ -0,0 +1,53 @@ +namespace RISCVII { +enum { +InstFormatPseudo = 0 , +InstFormatR = 1 , +InstFormatR4 = 2 , +InstFormatI = 3 , +InstFormatS = 4 , +InstFormatB = 5 , +InstFormatU = 6 , +InstFormatJ = 7 , +InstFormatCR = 8 , +InstFormatCI = 9 , +InstFormatCSS = 10 , +InstFormatCIW = 11 , +InstFormatCL = 12 , +InstFormatCS = 13 , +InstFormatCA = 14 , +InstFormatCB = 15 , +InstFormatCJ = 16 , +InstFormatOther = 17 , +InstFormatMask = 31 , +ConstraintShift = 5 , +ConstraintMask = 0b111 << ConstraintShift , +VLMulSh ConstraintShift = 3 , +VLMulMask = 0b111 << VLMulShift , +HasDummyMaskOpShift = VLMulShift + 3 , +HasDummyMaskOpMask = 1 << HasDummyMaskOpShift , +WritesElement0Shift HasDummyMaskOpShift + 1 , +WritesElement0Mask = 1 << WritesElement0Shift , +HasMergeOpShift = WritesElement0Shift + 1 , +HasMergeOpMask = 1 << HasMergeOpShift , +HasSEWOpShift = HasSEWOpShift + 1 , +HasSEWOpMask = 1 << HasSEWOpShift , +HasVLOpShift = HasSEWOpShift + 1 , +HasVLOpMask = 1 << HasVLOpShift , +} ; +enum { +MO_None = 0 , +MO_CALL = 1 , +MO_PLT = 2 , +MO_LO = 3 , +MO_HI = 4 , +MO_PCREL_LO = 5 , +MO_PCREL_HI = 6 , +MO_GOT_HI = 7 , +MO_TPREL_LO = 8 , +MO_TPREL_HI = 9 , +MO_TPREL_ADD = 10 , +MO_TLS_GOT_HI = 11 , +MO_TLS_GD_HI = 12 , +MO_DIRECT_FLAG_MASK = 15 +} ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/BaseInfo/OperandType.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/BaseInfo/OperandType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..983a9fbcced1c3b9f1bcf68032806605ed8aedd0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/BaseInfo/OperandType.cpp @@ -0,0 +1,8 @@ +enum OperandType : unsigned { +OPERAND_FIRST_RISCV_IMM = MCOI :: OPERAND_FIRST_TARGET , +OPERAND_UIMM4 = OPERAND_FIRST_RISCV_IMM , +OPERAND_UIMM5 , +OPERAND_UIMM12 , +OPERAND_UIMMLOG2XLEN , +OPERAND_LAST_RISCV_IMM OPERAND_UIMMLOG2XLEN +} ; \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/BaseInfo/RISCVVSEW.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/BaseInfo/RISCVVSEW.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6fd82173267ffe1a141a4ccf55b89e4cae9ba1b9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/BaseInfo/RISCVVSEW.cpp @@ -0,0 +1,10 @@ +enum class RISCVVSEW { +SEW_8 = 0 , +SEW_16 , +SEW_32 , +SEW_64 , +SEW_128 , +SEW_256 , +SEW_512 , +SEW_1024 , +} ; \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/BaseInfo/RVVConstraintType.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/BaseInfo/RVVConstraintType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..04397cb26419a3b482dac55f78f74f9f2246284c --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/BaseInfo/RVVConstraintType.cpp @@ -0,0 +1,6 @@ +enum RVVConstraintType { +NoConstraint = 0 , +VS2Constraint = 0b001 , +VS1Constraint = 0b010 , +VMConstraint = 0b100 +} ; \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/BaseInfo/RoundingMode.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/BaseInfo/RoundingMode.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cea4c4f62e6b6477a15b997dfeb3942a5b63578a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/BaseInfo/RoundingMode.cpp @@ -0,0 +1,9 @@ +enum RoundingMode { +RNE = 0 , +RTZ = 1 , +RDN = 2 , +RUP = 3 , +RMM = 4 , +DYN = 7 , +Invalid +} ; \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/BaseInfo/VLMUL.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/BaseInfo/VLMUL.cpp new file mode 100644 index 0000000000000000000000000000000000000000..97cedb5d2821dadb7b2885640b07b3950e394658 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/BaseInfo/VLMUL.cpp @@ -0,0 +1,10 @@ +enum class RISCVVLMUL { +LMUL_1 = 0 , +LMUL_2 , +LMUL_4 , +LMUL_8 , +LMUL_RESERVED , +LMUL_F8 , +LMUL_F4 , +LMUL_F2 +} ; \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/BaseInfo/VMTs.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/BaseInfo/VMTs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..508a687e2d6c50092cfbbbf2c693aacd4a16482d --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/BaseInfo/VMTs.cpp @@ -0,0 +1,37 @@ +enum RISCVVMVTs { +vint8mf8_t = MVT :: nxv1i8 , +vint8mf4_t = MVT :: nxv2i8 , +vint8mf2_t = MVT :: nxv4i8 , +vint8m1_t = MVT :: nxv8i8 , +vint8m2_t = MVT :: nxv16i8 , +vint8m4_t = MVT :: nxv32i8 , +vint8m8_t = MVT :: nxv64i8 , +vint16mf4_t = MVT :: nxv1i16 , +vint16mf2_t = MVT :: nxv2i16 , +vint16m1_t = MVT :: nxv4i16 , +vint16m2_t = MVT :: nxv8i16 , +vint16m4_t = MVT :: nxv16i16 , +vint16m8_t = MVT :: nxv32i16 , +vint32mf2_t = MVT :: nxv1i32 , +vint32m1_t = MVT :: nxv2i32 , +vint32m2_t = MVT :: nxv4i32 , +vint32m4_t = MVT :: nxv8i32 , +vint32m8_t = MVT :: nxv16i32 , +vint64m1_t = MVT :: nxv1i64 , +vint64m2_t = MVT :: nxv2i64 , +vint64m4_t = MVT :: nxv4i64 , +vint64m8_t = MVT :: nxv8i64 , +vfloat16mf4_t = MVT :: nxv1f16 , +vfloat16mf2_t = MVT :: nxv2f16 , +vfloat16m1_t = MVT :: nxv4f16 , +vfloat16m2_t = MVT :: nxv8f16 , +vfloat16m4_t = MVT :: nxv16f16 , +vfloat16m8_t = MVT :: nxv32f16 , +vfloat32mf2_t = MVT :: nxv1f32 , +vfloat32m1_t = MVT :: nxv2f32 , +vfloat32m2_t = MVT :: nxv4f32 , +vfloat32m4_t = MVT :: nxv8f32 , +vfloat32m8_t = MVT :: nxv16f32 , +vfloat64m1_t = MVT :: nxv1f64 , +vfloat64m2_t = +} ; \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/BaseInfo/computeTargetABI.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/BaseInfo/computeTargetABI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..56ee11a8c5a4fc5157f8a49121c5cd3de26b08ec --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/BaseInfo/computeTargetABI.cpp @@ -0,0 +1,14 @@ +ABI computeTargetABI ( const Triple & TT , FeatureBitset FeatureBits , StringRef ABIName ) { +auto TargetABI = getTargetABI ( ABIName ) ; +if ( ! ABIName . empty ( ) ) { +if ( TT . isRISCV64 ( ) ) { +TargetABI = RISCVABIInfo :: N64 ( ) ; +} +} +if ( ! ABIName . empty ( ) ) { +if ( ! TT . isRISCV64 ( ) ) { +TargetABI = RISCVABIInfo :: O32 ( ) ; +} +} +return TargetABI ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/BaseInfo/getTargetABI.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/BaseInfo/getTargetABI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b2a6bf078a014887a1743d788e548c67a7b2b39c --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/BaseInfo/getTargetABI.cpp @@ -0,0 +1,24 @@ +ABI getTargetABI ( StringRef Str ) { +if ( Str == "ilp32" ) { +return ABI_ILP32 ; +} +if ( Str == "ilp32f" ) { +return ABI_ILP32F ; +} +if ( Str == "ilp32d" ) { +return ABI_ILP32D ; +} +if ( Str == "ilp32e" ) { +return ABI_ILP32E ; +} +if ( Str == "lp64" ) { +return ABI_LP64 ; +} +if ( Str == "lp64f" ) { +return ABI_LP64F ; +} +if ( Str == "lp64d" ) { +return ABI_LP64D ; +} +return ABI_Unknown ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/BaseInfo/roundingModeToString.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/BaseInfo/roundingModeToString.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d7fad2b0de6d6e1503cbd283b5003e0ab6da3a42 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/BaseInfo/roundingModeToString.cpp @@ -0,0 +1,21 @@ +inline static StringRef roundingModeToString ( RoundingMode RndMod ) { +if ( RndMod == RISCVFPRndMode::RNE ) { +return "rne" ; +} +if ( RndMod == RISCVFPRndMode::RTZ ) { +return "rtz" ; +} +if ( RndMod == RISCVFPRndMode::RDN ) { +return "rdn" ; +} +if ( RndMod == RISCVFPRndMode::RUP ) { +return "rup" ; +} +if ( RndMod == RISCVFPRndMode::RMM ) { +return "rmm" ; +} +if ( RndMod == RISCVFPRndMode::DYN ) { +return "dyn" ; +} +llvm_unreachable ( "Unknown floating point rounding mode" ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/BaseInfo/stringToRoundingMode.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/BaseInfo/stringToRoundingMode.cpp new file mode 100644 index 0000000000000000000000000000000000000000..58c60f6342330ee237368718c3e54cfee614f7ce --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/BaseInfo/stringToRoundingMode.cpp @@ -0,0 +1,21 @@ +inline static RoundingMode stringToRoundingMode ( StringRef Str ) { +if ( Str == "rne" ) { +return RISCVFPRndMode::RNE ; +} +if ( Str == "rtz" ) { +return RISCVFPRndMode::RTZ ; +} +if ( Str == "rdn" ) { +return RISCVFPRndMode::RDN ; +} +if ( Str == "rup" ) { +return RISCVFPRndMode::RUP ; +} +if ( Str == "rmm" ) { +return RISCVFPRndMode::RMM ; +} +if ( Str == "dyn" ) { +return RISCVFPRndMode::DYN ; +} +return RISCVFPRndMode::Invalid ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/BaseInfo/validate.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/BaseInfo/validate.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f87f8d9df4e6e209200b63471299274b467fe694 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/BaseInfo/validate.cpp @@ -0,0 +1,7 @@ +void validate ( const Triple & TT , const FeatureBitset & FeatureBits ) { +if ( ! isABI_O32 ( ) ) { +if ( ! useOddSPReg ( ) ) { +report_fatal_error ( "RV32E can't be enabled for an RV64 target" ) ; +} +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFObjectWriter/ELFObjectWriter.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFObjectWriter/ELFObjectWriter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f59b3cb6e8893de00e9e8dd359ecf960dab21710 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFObjectWriter/ELFObjectWriter.cpp @@ -0,0 +1,2 @@ +RISCVELFObjectWriter :: RISCVELFObjectWriter ( uint8_t OSABI , bool Is64Bit ) : MCELFObjectTargetWriter ( Is64Bit , OSABI , EM_RISCV , true ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFObjectWriter/createELFObjectWriter.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFObjectWriter/createELFObjectWriter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8ceb74bbf8dcf76925d64be0135800a6901b3e80 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFObjectWriter/createELFObjectWriter.cpp @@ -0,0 +1,3 @@ +std :: unique_ptr < MCObjectTargetWriter > llvm :: createRISCVELFObjectWriter ( uint8_t OSABI , bool Is64Bit ) { +return std :: make_unique < RISCVELFObjectWriter > ( OSABI , Is64Bit ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFObjectWriter/getRelocType.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFObjectWriter/getRelocType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e320521f0ce7649704031005ff44f9cbafcc7d06 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFObjectWriter/getRelocType.cpp @@ -0,0 +1,134 @@ +unsigned RISCVELFObjectWriter :: getRelocType ( MCContext & Ctx , const MCValue & Target , const MCFixup & Fixup , bool IsPCRel ) const { +const RISCVMCExpr * SExpr ; +if ( SExpr = dyn_cast < RISCVMCExpr > ( Fixup . getValue ( ) ) ) { +if ( SExpr -> getKind ( ) == RISCVMCExpr :: VK_32_PCREL ) { +return ELF :: R_RISCV_32_PCREL ; +} +} +const MCExpr * Expr ; +Expr = Fixup . getValue ( ) ; +unsigned Kind ; +Kind = Fixup . getTargetKind ( ) ; +if ( Kind >= FirstLiteralRelocationKind ) { +return Kind - FirstLiteralRelocationKind ; +} +if ( IsPCRel ) { +if ( Kind == FK_PCRel_4 ) { +return ELF :: R_RISCV_32_PCREL ; +} +if ( Kind == RISCV :: fixup_RISCV_pcrel_hi20 ) { +return ELF :: R_RISCV_PCREL_HI20 ; +} +if ( Kind == RISCV :: fixup_RISCV_pcrel_lo12_i ) { +return ELF :: R_RISCV_PCREL_LO12_I ; +} +if ( Kind == RISCV :: fixup_RISCV_pcrel_lo12_s ) { +return ELF :: R_RISCV_PCREL_LO12_S ; +} +if ( Kind == FK_Data_4 ) { +return ELF :: R_RISCV_32_PCREL ; +} +if ( Kind == RISCV :: fixup_RISCV_got_hi20 ) { +return ELF :: R_RISCV_GOT_HI20 ; +} +if ( Kind == RISCV :: fixup_RISCV_tls_got_hi20 ) { +return ELF :: R_RISCV_TLS_GOT_HI20 ; +} +if ( Kind == RISCV :: fixup_RISCV_tls_gd_hi20 ) { +return ELF :: R_RISCV_TLS_GD_HI20 ; +} +if ( Kind == RISCV :: fixup_RISCV_jal ) { +return ELF :: R_RISCV_JAL ; +} +if ( Kind == RISCV :: fixup_RISCV_branch ) { +return ELF :: R_RISCV_BRANCH ; +} +if ( Kind == RISCV :: fixup_RISCV_rvc_jump ) { +return ELF :: R_RISCV_RVC_JUMP ; +} +if ( Kind == RISCV :: fixup_RISCV_rvc_branch ) { +return ELF :: R_RISCV_RVC_BRANCH ; +} +if ( Kind == RISCV :: fixup_RISCV_call ) { +return ELF :: R_RISCV_CALL ; +} +if ( Kind == RISCV :: fixup_RISCV_call_plt ) { +return ELF :: R_RISCV_CALL_PLT ; +} +Ctx . reportError ( Fixup . getLoc ( ) , "Unsupported relocation type" ) ; +return ELF :: R_RISCV_NONE ; +} +if ( Kind == FK_Data_4 ) { +return ELF :: R_RISCV_32 ; +} +if ( Kind == FK_Data_8 ) { +return ELF :: R_RISCV_64 ; +} +if ( Kind == FK_Data_Add_1 ) { +return ELF :: R_RISCV_ADD8 ; +} +if ( Kind == FK_Data_Add_2 ) { +return ELF :: R_RISCV_ADD16 ; +} +if ( Kind == FK_Data_Add_4 ) { +return ELF :: R_RISCV_ADD32 ; +} +if ( Kind == FK_Data_Add_8 ) { +return ELF :: R_RISCV_ADD64 ; +} +if ( Kind == FK_Data_1 ) { +Ctx . reportError ( Fixup . getLoc ( ) , "1-byte data relocations not supported" ) ; +return ELF :: R_RISCV_NONE ; +} +if ( Kind == FK_Data_2 ) { +Ctx . reportError ( Fixup . getLoc ( ) , "2-byte data relocations not supported" ) ; +return ELF :: R_RISCV_NONE ; +} +if ( Kind == FK_Data_Add_6b ) { +return ELF :: R_RISCV_SET6 ; +} +if ( Kind == FK_Data_Sub_1 ) { +return ELF :: R_RISCV_SUB8 ; +} +if ( Kind == FK_Data_Sub_2 ) { +return ELF :: R_RISCV_SUB16 ; +} +if ( Kind == FK_Data_Sub_4 ) { +return ELF :: R_RISCV_SUB32 ; +} +if ( Kind == FK_Data_Sub_8 ) { +return ELF :: R_RISCV_SUB64 ; +} +if ( Kind == FK_Data_Sub_6b ) { +return ELF :: R_RISCV_SUB6 ; +} +if ( Kind == RISCV :: fixup_RISCV_hi20 ) { +return ELF :: R_RISCV_HI20 ; +} +if ( Kind == RISCV :: fixup_RISCV_lo12_i ) { +return ELF :: R_RISCV_LO12_I ; +} +if ( Kind == RISCV :: fixup_RISCV_lo12_s ) { +return ELF :: R_RISCV_LO12_S ; +} +if ( Kind == RISCV :: fixup_RISCV_tprel_hi20 ) { +return ELF :: R_RISCV_TPREL_HI20 ; +} +if ( Kind == RISCV :: fixup_RISCV_tprel_lo12_i ) { +return ELF :: R_RISCV_TPREL_LO12_I ; +} +if ( Kind == RISCV :: fixup_RISCV_tprel_lo12_s ) { +return ELF :: R_RISCV_TPREL_LO12_S ; +} +if ( Kind == RISCV :: fixup_RISCV_tprel_add ) { +return ELF :: R_RISCV_TPREL_ADD ; +} +if ( Kind == RISCV :: fixup_RISCV_relax ) { +return ELF :: R_RISCV_RELAX ; +} +if ( Kind == RISCV :: fixup_RISCV_align ) { +return ELF :: R_RISCV_ALIGN ; +} +Ctx . reportError ( Fixup . getLoc ( ) , "Unsupported relocation type" ) ; +return ELF :: R_RISCV_NONE ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFObjectWriter/needsRelocateWithSymbol.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFObjectWriter/needsRelocateWithSymbol.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d32e5d47cdf21c903c9c0bba5ef56efc3a118a62 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFObjectWriter/needsRelocateWithSymbol.cpp @@ -0,0 +1,3 @@ +bool needsRelocateWithSymbol ( const MCSymbol & Sym , unsigned Type ) const override { +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFObjectWriter/~ELFObjectWriter.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFObjectWriter/~ELFObjectWriter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ff04c0f4361cc2216f531f31de770817c1973c32 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFObjectWriter/~ELFObjectWriter.cpp @@ -0,0 +1,2 @@ +RISCVELFObjectWriter :: ~ RISCVELFObjectWriter ( ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/AttributeItem.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/AttributeItem.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5d4a8b8d43739a9660b269fe60e4c13f60b08b9e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/AttributeItem.cpp @@ -0,0 +1,6 @@ +struct AttributeItem { +AttributeType Type ; +unsigned Tag ; +unsigned IntValue ; +std :: string StringValue ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/AttributeType.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/AttributeType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..11e84b4eac2ba89f7bac001f476bce2df9b96af0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/AttributeType.cpp @@ -0,0 +1,6 @@ +enum class AttributeType { +Hidden , +Numeric , +Text , +NumericAndText +} ; \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/TargetELFStreamer.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/TargetELFStreamer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c6e12429a45a353e00b78ac06140a37e2f380364 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/TargetELFStreamer.cpp @@ -0,0 +1,21 @@ +RISCVTargetELFStreamer :: RISCVTargetELFStreamer ( MCStreamer & S , const MCSubtargetInfo & STI ) : RISCVTargetStreamer ( S ) , CurrentVendor ( "RISCV" ) { +MCAssembler & MCA ; +MCA = getStreamer ( ) . getAssembler ( ) ; +const FeatureBitset & Features ; +Features = STI . getFeatureBits ( ) ; +RISCVMCAsmBackend & MAB ; +MAB = static_cast < RISCVMCAsmBackend & > ( MCA . getBackend ( ) ) ; +unsigned EFlags ; +EFlags = MCA . getELFHeaderEFlags ( ) ; +RISCVABI :: ABI ABI ; +ABI = MAB . getTargetABI ( ) ; +if ( Features [ RISCV :: FeatureStdExtC ] ) { +EFlags = EFlags | ELF :: EF_RISCV_RVC ; +} +EFlags = EFlags | ELF :: EF_RISCV_FLOAT_ABI_SINGLE ; +EFlags = EFlags | ELF :: EF_RISCV_FLOAT_ABI_SINGLE ; +EFlags = EFlags | ELF :: EF_RISCV_FLOAT_ABI_DOUBLE ; +EFlags = EFlags | ELF :: EF_RISCV_FLOAT_ABI_DOUBLE ; +EFlags = EFlags | ELF :: EF_RISCV_RVE ; +MCA . setELFHeaderEFlags ( EFlags ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/calculateContentSize.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/calculateContentSize.cpp new file mode 100644 index 0000000000000000000000000000000000000000..223eb9cec883b2156a786b7ea36eaa0a955d8f7f --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/calculateContentSize.cpp @@ -0,0 +1,29 @@ +size_t RISCVTargetELFStreamer :: calculateContentSize ( ) const { +size_t Result ; +Result = 0 ; +size_t i ; +for ( i = 0 ; i < Contents . size ( ) ; ++ i ) { +AttributeItem item ; +item = Contents [ i ] ; +if ( item . Type == AttributeType :: Hidden ) { +continue ; +} +if ( item . Type == AttributeType :: Numeric ) { +Result = Result + getULEB128Size ( item . Tag ) ; +Result = Result + getULEB128Size ( item . IntValue ) ; +continue ; +} +if ( item . Type == AttributeType :: Text ) { +Result = Result + getULEB128Size ( item . Tag ) ; +Result = Result + item . StringValue . size ( ) + 1 ; +continue ; +} +if ( item . Type == AttributeType :: NumericAndText ) { +Result = Result + getULEB128Size ( item . Tag ) ; +Result = Result + getULEB128Size ( item . IntValue ) ; +Result = Result + item . StringValue . size ( ) + 1 ; +continue ; +} +} +return Result ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/emitAttribute.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/emitAttribute.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f741530d375c3cbf0363365222dd8bda3a0c8411 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/emitAttribute.cpp @@ -0,0 +1,3 @@ +void RISCVTargetELFStreamer :: emitAttribute ( unsigned Attribute , unsigned Value ) { +setAttributeItem ( Attribute , Value , true ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionNoPIC.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionNoPIC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..07f53856a0f83f3f5d85bb7eb1eba3d943c81cf3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionNoPIC.cpp @@ -0,0 +1,2 @@ +void RISCVTargetELFStreamer :: emitDirectiveOptionNoPIC ( ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionNoRVC.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionNoRVC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c7bc1941da3c7983e3aae98aa1e217fd2e505b73 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionNoRVC.cpp @@ -0,0 +1,2 @@ +void RISCVTargetELFStreamer :: emitDirectiveOptionNoRVC ( ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionNoRelax.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionNoRelax.cpp new file mode 100644 index 0000000000000000000000000000000000000000..432808af0bf195674ccb6456bbd734c3f0c2e030 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionNoRelax.cpp @@ -0,0 +1,2 @@ +void RISCVTargetELFStreamer :: emitDirectiveOptionNoRelax ( ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionPIC.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionPIC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..221d2413d391623adaf82613647e6d2a62160f5b --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionPIC.cpp @@ -0,0 +1,2 @@ +void RISCVTargetELFStreamer :: emitDirectiveOptionPIC ( ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionPop.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionPop.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7801d7a5bfb8715cc3a8519097a296c207a9cdfd --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionPop.cpp @@ -0,0 +1,2 @@ +void RISCVTargetELFStreamer :: emitDirectiveOptionPop ( ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionPush.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionPush.cpp new file mode 100644 index 0000000000000000000000000000000000000000..15fef759efa24f392ad24c09a68450eef41b0a54 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionPush.cpp @@ -0,0 +1,2 @@ +void RISCVTargetELFStreamer :: emitDirectiveOptionPush ( ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionRVC.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionRVC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..39cd0aac779cb60dc47ba36e533136e981c4c7df --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionRVC.cpp @@ -0,0 +1,2 @@ +void RISCVTargetELFStreamer :: emitDirectiveOptionRVC ( ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionRelax.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionRelax.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2e4a732ca57a30667c7149a2099611993919d44d --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/emitDirectiveOptionRelax.cpp @@ -0,0 +1,2 @@ +void RISCVTargetELFStreamer :: emitDirectiveOptionRelax ( ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/emitIntTextAttribute.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/emitIntTextAttribute.cpp new file mode 100644 index 0000000000000000000000000000000000000000..22d67c49f25f2c40c9462c67be2f74a6c68393d8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/emitIntTextAttribute.cpp @@ -0,0 +1,3 @@ +void RISCVTargetELFStreamer :: emitIntTextAttribute ( unsigned Attribute , unsigned IntValue , StringRef StringValue ) { +setAttributeItems ( Attribute , IntValue , StringValue , true ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/emitTextAttribute.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/emitTextAttribute.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a5e987c047ba1af38369070668127c9f1b87b0b4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/emitTextAttribute.cpp @@ -0,0 +1,3 @@ +void RISCVTargetELFStreamer :: emitTextAttribute ( unsigned Attribute , StringRef String ) { +setAttributeItem ( Attribute , String , true ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/finishAttributeSection.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/finishAttributeSection.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e7adeebfc9e9d262fb5020554a13040f8a04c336 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/finishAttributeSection.cpp @@ -0,0 +1,45 @@ +void RISCVTargetELFStreamer :: finishAttributeSection ( ) { +if ( Contents . empty ( ) ) { +return ; +} +MCELFStreamer & Streamer = getStreamer ( ) ; +if ( AttributeSection ) { +Streamer . SwitchSection ( AttributeSection ) ; +} +if ( ! AttributeSection ) { +AttributeSection = Streamer . getContext ( ) . getELFSection ( ".RISCV_lower.attributes" , ELF :: SHT_RISCV_ATTRIBUTES , 0 ) ; +Streamer . SwitchSection ( AttributeSection ) ; +Streamer . emitInt8 ( ELFAttrs :: Format_Version ) ; +} +const size_t VendorHeaderSize = 4 + CurrentVendor . size ( ) + 1 ; +const size_t TagHeaderSize = 1 + 4 ; +const size_t ContentsSize = calculateContentSize ( ) ; +Streamer . emitInt32 ( VendorHeaderSize + TagHeaderSize + ContentsSize ) ; +Streamer . emitBytes ( CurrentVendor ) ; +Streamer . emitInt8 ( 0 ) ; +Streamer . emitInt8 ( ELFAttrs :: File ) ; +Streamer . emitInt32 ( TagHeaderSize + ContentsSize ) ; +size_t i ; +for ( i = 0 ; i < Contents . size ( ) ; ++ i ) { +AttributeItem item ; +item = Contents [ i ] ; +Streamer . emitULEB128IntValue ( item . Tag ) ; +if ( item . Type == AttributeType :: Numeric ) { +Streamer . emitULEB128IntValue ( item . IntValue ) ; +continue ; +} +if ( item . Type == AttributeType :: Text ) { +Streamer . emitBytes ( item . StringValue ) ; +Streamer . emitInt8 ( 0 ) ; +continue ; +} +if ( item . Type == AttributeType :: NumericAndText ) { +Streamer . emitULEB128IntValue ( item . IntValue ) ; +Streamer . emitBytes ( item . StringValue ) ; +Streamer . emitInt8 ( 0 ) ; +continue ; +} +llvm_unreachable ( "Invalid attribute type" ) ; +} +Contents . clear ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/getAttributeItem.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/getAttributeItem.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b4c4f3a04f8aff4a632364d2dd166a8131e8ce0a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/getAttributeItem.cpp @@ -0,0 +1,9 @@ +AttributeItem * getAttributeItem ( unsigned Attribute ) { +size_t i ; +for ( i = 0 ; i < Contents . size ( ) ; ++ i ) { +if ( Contents [ i ] . Tag == Attribute ) { +return & Contents [ i ] ; +} +} +return nullptr ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/getStreamer.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/getStreamer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..de4607b8b5b09fac89677943345a853723f8fbe5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/getStreamer.cpp @@ -0,0 +1,3 @@ +MCELFStreamer & RISCVTargetELFStreamer :: getStreamer ( ) { +return static_cast < MCELFStreamer & > ( Streamer ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/setAttributeItem1.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/setAttributeItem1.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4226193c148e049fab7718f81ce0f0309e9557d9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/setAttributeItem1.cpp @@ -0,0 +1,12 @@ +void setAttributeItem ( unsigned Attribute , unsigned Value , bool OverwriteExisting ) { +AttributeItem * Item ; +if ( Item = getAttributeItem ( Attribute ) ) { +if ( ! OverwriteExisting ) { +return ; +} +Item -> Type = AttributeType :: Numeric ; +Item -> IntValue = Value ; +return ; +} +Contents . push_back ( { AttributeType :: Numeric , Attribute , Value , "" } ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/setAttributeItem2.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/setAttributeItem2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b05a1b3223da60321ec2a64b1c6e99126cbe4e0e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/setAttributeItem2.cpp @@ -0,0 +1,12 @@ +void setAttributeItem ( unsigned Attribute , StringRef Value , bool OverwriteExisting ) { +AttributeItem * Item ; +if ( Item = getAttributeItem ( Attribute ) ) { +if ( ! OverwriteExisting ) { +return ; +} +Item -> Type = AttributeType :: Text ; +Item -> StringValue = std :: string ( Value ) ; +return ; +} +Contents . push_back ( { AttributeType :: Text , Attribute , 0 , std :: string ( Value ) } ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/setAttributeItems.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/setAttributeItems.cpp new file mode 100644 index 0000000000000000000000000000000000000000..52f682e8808f82b0ac277c275f668b743d449d66 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/ELFStreamer/setAttributeItems.cpp @@ -0,0 +1,13 @@ +void setAttributeItems ( unsigned Attribute , unsigned IntValue , StringRef StringValue , bool OverwriteExisting ) { +AttributeItem * Item ; +if ( Item = getAttributeItem ( Attribute ) ) { +if ( ! OverwriteExisting ) { +return ; +} +Item -> Type = AttributeType :: NumericAndText ; +Item -> IntValue = IntValue ; +Item -> StringValue = std :: string ( StringValue ) ; +return ; +} +Contents . push_back ( { AttributeType :: NumericAndText , Attribute , IntValue , std :: string ( StringValue ) } ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/FixupKind/enumFixups.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/FixupKind/enumFixups.cpp new file mode 100644 index 0000000000000000000000000000000000000000..db37e8df1e60ff64c601e16ed87caeade2b8381b --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/FixupKind/enumFixups.cpp @@ -0,0 +1,25 @@ +enum Fixups { +fixup_RISCV_hi20 = FirstTargetFixupKind , +fixup_RISCV_lo12_i , +fixup_RISCV_lo12_s , +fixup_RISCV_pcrel_hi20 , +fixup_RISCV_pcrel_lo12_i , +fixup_RISCV_pcrel_lo12_s , +fixup_RISCV_got_hi20 , +fixup_RISCV_tprel_hi20 , +fixup_RISCV_tprel_lo12_i , +fixup_RISCV_tprel_lo12_s , +fixup_RISCV_tprel_add , +fixup_RISCV_tls_got_hi20 , +fixup_RISCV_tls_gd_hi20 , +fixup_RISCV_jal , +fixup_RISCV_branch , +fixup_RISCV_rvc_jump , +fixup_RISCV_rvc_branch , +fixup_RISCV_call , +fixup_RISCV_call_plt , +fixup_RISCV_relax , +fixup_RISCV_align , +fixup_RISCV_invalid , +NumTargetFixupKinds = fixup_RISCV_invalid - FirstTargetFixupKind +} ; \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/InstPrinter/InstPrinter.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/InstPrinter/InstPrinter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..03a6f9a80a02f24cd41edcabd9292eba3dc4bd47 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/InstPrinter/InstPrinter.cpp @@ -0,0 +1,2 @@ +RISCVInstPrinter ( const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) : MCInstPrinter ( MAI , MII , MRI ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/InstPrinter/applyTargetSpecificCLOption.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/InstPrinter/applyTargetSpecificCLOption.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c405ea7e972c44d59814982604638618bba03a6a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/InstPrinter/applyTargetSpecificCLOption.cpp @@ -0,0 +1,11 @@ +bool RISCVInstPrinter :: applyTargetSpecificCLOption ( StringRef Opt ) { +if ( Opt == "numeric" ) { +ArchRegNames = true ; +return true ; +} +if ( Opt == "no-aliases" ) { +NoAliases = true ; +return true ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/InstPrinter/getRegisterName.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/InstPrinter/getRegisterName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..16f9a93427519381712835e6c00ec73754042e56 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/InstPrinter/getRegisterName.cpp @@ -0,0 +1,3 @@ +const char * RISCVInstPrinter :: getRegisterName ( unsigned RegNo ) { +return getRegisterName ( RegNo , ArchRegNames ? RISCV :: NoRegAltName : RISCV :: ABIRegAltName ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/InstPrinter/printAtomicMemOp.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/InstPrinter/printAtomicMemOp.cpp new file mode 100644 index 0000000000000000000000000000000000000000..14bfb76e67751e7652cdbe3aa2da7d48bd797ecb --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/InstPrinter/printAtomicMemOp.cpp @@ -0,0 +1,10 @@ +void RISCVInstPrinter :: printAtomicMemOp ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { +const MCOperand & Op1 ; +Op1 = MI -> getOperand ( OpNo ) ; +const MCOperand & Op2 ; +Op2 = MI -> getOperand ( OpNo + 1 ) ; +OS << ")" ; +printRegName ( O , Op1 . getReg ( ) ) ; +unsigned Offset ; +OS << ")" ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/InstPrinter/printBranchOperand.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/InstPrinter/printBranchOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a7734627aef205882093bc642208d07a76f0ab3b --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/InstPrinter/printBranchOperand.cpp @@ -0,0 +1,17 @@ +void RISCVInstPrinter :: printBranchOperand ( const MCInst * MI , uint64_t Address , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & OS ) { +const MCOperand & MO = MI -> getOperand ( OpNo ) ; +if ( ! MO . isImm ( ) ) { +return printOperand ( MI , OpNo , STI , OS ) ; +} +if ( PrintBranchImmAsAddress ) { +uint64_t Target ; +Target = Address + MO . getImm ( ) ; +if ( ! STI . hasFeature ( RISCV :: Feature64Bit ) ) { +Target = Target & 0xffffffff ; +} +OS << formatHex ( Target ) ; +} +if ( ! PrintBranchImmAsAddress ) { +OS << MO . getImm ( ) ; +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/InstPrinter/printCSRSystemRegister.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/InstPrinter/printCSRSystemRegister.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1e2b7cc822366a4a57165cd9980ee1fc32395d13 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/InstPrinter/printCSRSystemRegister.cpp @@ -0,0 +1,16 @@ +void RISCVInstPrinter :: printCSRSystemRegister ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { +unsigned Val ; +Val = MI -> getOperand ( OpNo ) . getImm ( ) ; +return ; +const SysReg :: SysReg * Reg ; +Reg = SysReg :: lookupSysRegByEncoding ( Val ) ; +if ( Reg ) { +if ( Reg -> haveRequiredFeatures ( STI . getFeatureBits ( ) ) ) { +OS << Reg -> Name ; +} +} +if ( ! Reg ) { +return ; +if ( ! Reg -> haveRequiredFeatures ( STI . getFeatureBits ( ) ) ) { +return ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/InstPrinter/printFRMArg.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/InstPrinter/printFRMArg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ec50ac32da1905f2d50100a94432ba69b071e958 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/InstPrinter/printFRMArg.cpp @@ -0,0 +1,4 @@ +void RISCVInstPrinter :: printFRMArg ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { +auto FRMArg = MI -> getOperand ( OpNo ) . getImm ( ) ; +OS << FPRndMode :: roundingModeToString ( MO . getImm ( ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/InstPrinter/printFenceArg.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/InstPrinter/printFenceArg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d71d61a78dd1ca1f479a6ce346e8138bc6098a9a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/InstPrinter/printFenceArg.cpp @@ -0,0 +1,11 @@ +void RISCVInstPrinter :: printFenceArg ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { +unsigned FenceArg = MI -> getOperand ( OpNo ) . getImm ( ) ; +assert ( ( FenceArg >> 4 ) == 0 ) && "Invalid immediate in printFenceArg!" ) ; +OS << 'i' ; +OS << 'o' ; +OS << 'r' ; +OS << 'w' ; +if ( FenceArg == 0 ) { +OS << "unknown" ; +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/InstPrinter/printInst.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/InstPrinter/printInst.cpp new file mode 100644 index 0000000000000000000000000000000000000000..de8dd9b0d62309b6d04f18522701890f656d7481 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/InstPrinter/printInst.cpp @@ -0,0 +1,22 @@ +void RISCVInstPrinter :: printInst ( const MCInst * MI , uint64_t Address , StringRef Annot , const MCSubtargetInfo & STI , raw_ostream & O ) { +bool Res ; +Res = false ; +const MCInst * NewMI ; +MCInst UncompressedMI ; +if ( ! printAliasInstr ( MI , STI , O ) ) { +printInstruction ( NewMI , Address , STI , O ) ; +printAnnotation ( O , Annot ) ; +return ; +} +printInstruction ( NewMI , Address , STI , O ) ; +printAnnotation ( O , Annot ) ; +return ; +} +if ( ! printAliasInstr ( NewMI , Address , STI , O ) ) { +printInstruction ( NewMI , Address , STI , O ) ; +printAnnotation ( O , Annot ) ; +return ; +} +printInstruction ( NewMI , Address , STI , O ) ; +printAnnotation ( O , Annot ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/InstPrinter/printOperand.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/InstPrinter/printOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3a9e827c04ab195840f49a22f931c46a7a0ff36a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/InstPrinter/printOperand.cpp @@ -0,0 +1,14 @@ +void RISCVInstPrinter :: printOperand ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & OS , const char * Modifier ) { +assert ( ( Modifier == 0 || Modifier [ 0 ] == 0 ) && "No modifiers supported" ) ; +const MCOperand & Op = MI -> getOperand ( OpNo ) ; +if ( Op . isReg ( ) ) { +OS << getRegisterName ( Op . getReg ( ) ) ; +return ; +} +if ( Op . isImm ( ) ) { +OS << Op . getImm ( ) ; +return ; +} +assert ( Op . isExpr ( ) && "Unknown operand kind in printOperand" ) ; +Op . getExpr ( ) -> print ( OS , & MAI ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/InstPrinter/printRegName.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/InstPrinter/printRegName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3872b5d15950fcf2abb0abe7e5ba43aaa200d695 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/InstPrinter/printRegName.cpp @@ -0,0 +1,3 @@ +void RISCVInstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { +OS << getRegisterName ( RegNo ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/InstPrinter/printVMaskReg.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/InstPrinter/printVMaskReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..153e43ff1c490952d24e15ee86d401bb0195617f --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/InstPrinter/printVMaskReg.cpp @@ -0,0 +1,9 @@ +void RISCVInstPrinter :: printVMaskReg ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { +const MCOperand & Op1 ; +Op1 = MI -> getOperand ( OpNo ) ; +const MCOperand & Op2 ; +Op2 = MI -> getOperand ( OpNo + 1 ) ; +OS << ", " ; +printRegName ( O , Op1 . getReg ( ) ) ; +OS << ".t" ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/InstPrinter/printVTypeI.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/InstPrinter/printVTypeI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2f6634da035e2d3267361cf4afcea7cc660407a9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/InstPrinter/printVTypeI.cpp @@ -0,0 +1,5 @@ +void RISCVInstPrinter :: printVTypeI ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { +unsigned Imm ; +Imm = MI -> getOperand ( OpNo ) . getImm ( ) ; +RISCVVType :: printVType ( Imm , O ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCCodeEmitter/MCCodeEmitter.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCCodeEmitter/MCCodeEmitter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..91e70b43e2bd64ca7b4a3b6bba93fe842b01a9c6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCCodeEmitter/MCCodeEmitter.cpp @@ -0,0 +1,2 @@ +RISCVMCCodeEmitter ( MCContext & ctx , MCInstrInfo const & MCII ) : Ctx ( ctx ) , MCII ( MCII ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCCodeEmitter/createMCCodeEmitter.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCCodeEmitter/createMCCodeEmitter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0bc1dd8240e3d519882ac752d968f2a5de249c52 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCCodeEmitter/createMCCodeEmitter.cpp @@ -0,0 +1,3 @@ +MCCodeEmitter * llvm :: createRISCVMCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , MCContext & Ctx ) { +return new RISCVMCCodeEmitter ( Ctx , MCII ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCCodeEmitter/encodeInstruction.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCCodeEmitter/encodeInstruction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b4558db02096e21988ad2489892b6e2849bfa92a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCCodeEmitter/encodeInstruction.cpp @@ -0,0 +1,50 @@ +void RISCVMCCodeEmitter :: encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { +verifyInstructionPredicates ( MI , computeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; +Desc = MCII . get ( MI . getOpcode ( ) ) ; +unsigned Size ; +Size = Desc . getSize ( ) ; +if ( MI . getOpcode ( ) == RISCV :: PseudoCALLReg ) { +expand_TLSDESCCALL ( MI , OS , Fixups , STI ) ; +MCNumEmitted = MCNumEmitted + 0 ; +return ; +} +if ( MI . getOpcode ( ) == RISCV :: PseudoCALL ) { +expand_CompilerBarrier ( MI , OS , Fixups , STI ) ; +MCNumEmitted = MCNumEmitted + 0 ; +return ; +} +if ( MI . getOpcode ( ) == RISCV :: PseudoTAIL ) { +expand_SPACE ( MI , OS , Fixups , STI ) ; +MCNumEmitted = MCNumEmitted + 0 ; +return ; +} +if ( MI . getOpcode ( ) == RISCV :: PseudoJump ) { +expand_EH_SjLj_Setup ( MI , OS , Fixups , STI ) ; +MCInst TmpInst ; +uint16_t Binary ; +uint32_t Binary ; +const MCExpr * CallExpr ; +CallExpr = MI . getOperand ( 0 ) . getExpr ( ) ; +TmpInst = MCInstBuilder ( RISCV :: JS ) . addImm ( 0 ) ; +TmpInst = MCInstBuilder ( RISCV :: J ) . addImm ( - 2 ) ; +Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; +expand_COPY_TO_REGCLASS ( MI , OS , Fixups , STI ) ; +return ; +} +if ( Size == 2 ) { +uint16_t Bits ; +Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ; +support :: endian :: write < uint16_t > ( OS , Bits , support :: little ) ; +MCNumEmitted = MCNumEmitted + 1 ; +return ; +} +if ( Size == 4 ) { +uint32_t Bits ; +Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ; +support :: endian :: write < uint32_t > ( OS , Bits , support :: little ) ; +MCNumEmitted = MCNumEmitted + 1 ; +return ; +} +llvm_unreachable ( "Unhandled encodeInstruction length!" ) ; +MCNumEmitted = MCNumEmitted + 1 ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCCodeEmitter/getImmOpValue.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCCodeEmitter/getImmOpValue.cpp new file mode 100644 index 0000000000000000000000000000000000000000..557abd8f4ab4b387e040a0a1b71a39bb6d7954ac --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCCodeEmitter/getImmOpValue.cpp @@ -0,0 +1,72 @@ +unsigned RISCVMCCodeEmitter :: getImmOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { +const MCOperand & MO ; +MO = MI . getOperand ( OpIdx ) ; +if ( MO . isReg ( ) ) { +return Ctx . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) ) ; +} +if ( MO . isImm ( ) ) { +return static_cast < unsigned > ( MO . getImm ( ) ) ; +} +RISCV :: Fixups FixupKind ; +FixupKind = RISCV :: Fixups ( 0 ) ; +MCExpr :: ExprKind Kind ; +if ( Kind == MCExpr :: Constant ) { +return cast < MCConstantExpr > ( Expr ) -> getValue ( ) ; +} +if ( Kind == MCExpr :: Binary ) { +} +assert ( Kind == MCExpr :: SymbolRef && "unknown MCExpr kind" ) ; +if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == RISCVMCExpr :: VK_RISCV_LO ) { +FixupKind = RISCV :: fixup_RISCV_lo12_i ; +Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; +return 0 ; +} +if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == RISCVMCExpr :: VK_RISCV_HI ) { +FixupKind = RISCV :: fixup_RISCV_hi20 ; +Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; +return 0 ; +} +if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == RISCVMCExpr :: VK_RISCV_PCREL_LO ) { +FixupKind = RISCV :: fixup_RISCV_pcrel_lo12_i ; +Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; +return 0 ; +} +if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == RISCVMCExpr :: VK_RISCV_PCREL_HI ) { +FixupKind = RISCV :: fixup_RISCV_pcrel_hi20 ; +Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; +return 0 ; +} +if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == RISCVMCExpr :: VK_RISCV_GOT_HI ) { +FixupKind = RISCV :: fixup_RISCV_got_hi20 ; +Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; +return 0 ; +} +if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == RISCVMCExpr :: VK_RISCV_TPREL_LO ) { +FixupKind = RISCV :: fixup_RISCV_tprel_lo12_s ; +Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; +return 0 ; +} +if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == RISCVMCExpr :: VK_RISCV_TPREL_HI ) { +FixupKind = RISCV :: fixup_RISCV_tprel_hi20 ; +Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; +return 0 ; +} +if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == RISCVMCExpr :: VK_RISCV_TLS_GOT_HI ) { +FixupKind = RISCV :: fixup_RISCV_tls_got_hi20 ; +Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; +return 0 ; +} +if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == RISCVMCExpr :: VK_RISCV_TLS_GD_HI ) { +FixupKind = RISCV :: fixup_RISCV_tls_gd_hi20 ; +Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; +return 0 ; +} +if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == RISCVMCExpr :: VK_RISCV_CALL ) { +FixupKind = RISCV :: fixup_RISCV_call ; +Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; +return 0 ; +} +llvm_unreachable ( "Unknown fixup kind!" ) ; +Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; +return 0 ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCCodeEmitter/getImmOpValueAsr1.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCCodeEmitter/getImmOpValueAsr1.cpp new file mode 100644 index 0000000000000000000000000000000000000000..dc087f34b1ae45d65d7ae6d8948ebb00f7d9ac75 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCCodeEmitter/getImmOpValueAsr1.cpp @@ -0,0 +1,72 @@ +unsigned RISCVMCCodeEmitter :: getImmOpValueAsr1 ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { +const MCOperand & MO ; +MO = MI . getOperand ( OpIdx ) ; +if ( MO . isReg ( ) ) { +return Ctx . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) ) ; +} +if ( MO . isImm ( ) ) { +return static_cast < unsigned > ( MO . getImm ( ) ) ; +} +RISCV :: Fixups FixupKind ; +FixupKind = RISCV :: Fixups ( 0 ) ; +MCExpr :: ExprKind Kind ; +if ( Kind == MCExpr :: Constant ) { +return cast < MCConstantExpr > ( Expr ) -> getValue ( ) ; +} +if ( Kind == MCExpr :: Binary ) { +} +assert ( Kind == MCExpr :: SymbolRef && "unknown MCExpr kind" ) ; +if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == RISCVMCExpr :: VK_RISCV_LO ) { +FixupKind = RISCV :: fixup_RISCV_lo12_i ; +Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; +return 0 ; +} +if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == RISCVMCExpr :: VK_RISCV_HI ) { +FixupKind = RISCV :: fixup_RISCV_hi20 ; +Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; +return 0 ; +} +if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == RISCVMCExpr :: VK_RISCV_PCREL_LO ) { +FixupKind = RISCV :: fixup_RISCV_pcrel_lo12_i ; +Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; +return 0 ; +} +if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == RISCVMCExpr :: VK_RISCV_PCREL_HI ) { +FixupKind = RISCV :: fixup_RISCV_pcrel_hi20 ; +Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; +return 0 ; +} +if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == RISCVMCExpr :: VK_RISCV_GOT_HI ) { +FixupKind = RISCV :: fixup_RISCV_got_hi20 ; +Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; +return 0 ; +} +if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == RISCVMCExpr :: VK_RISCV_TPREL_LO ) { +FixupKind = RISCV :: fixup_RISCV_tprel_lo12_s ; +Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; +return 0 ; +} +if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == RISCVMCExpr :: VK_RISCV_TPREL_HI ) { +FixupKind = RISCV :: fixup_RISCV_tprel_hi20 ; +Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; +return 0 ; +} +if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == RISCVMCExpr :: VK_RISCV_TLS_GOT_HI ) { +FixupKind = RISCV :: fixup_RISCV_tls_got_hi20 ; +Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; +return 0 ; +} +if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == RISCVMCExpr :: VK_RISCV_TLS_GD_HI ) { +FixupKind = RISCV :: fixup_RISCV_tls_gd_hi20 ; +Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; +return 0 ; +} +if ( cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == RISCVMCExpr :: VK_RISCV_CALL ) { +FixupKind = RISCV :: fixup_RISCV_call ; +Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; +return 0 ; +} +llvm_unreachable ( "Unknown fixup kind!" ) ; +Fixups . push_back ( MCFixup :: create ( 0 , MO . getExpr ( ) , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; +return 0 ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCCodeEmitter/getMachineOpValue.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCCodeEmitter/getMachineOpValue.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0f4e4b8f49492851005796a7a1079058bd2b9a37 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCCodeEmitter/getMachineOpValue.cpp @@ -0,0 +1,10 @@ +unsigned RISCVMCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { +if ( MO . isReg ( ) ) { +return Ctx . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) ) ; +} +if ( MO . isImm ( ) ) { +return static_cast < unsigned > ( MO . getImm ( ) ) ; +} +llvm_unreachable ( "Unhandled expression!" ) ; +return 0 ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCCodeEmitter/getVMaskReg.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCCodeEmitter/getVMaskReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1dc996a036c4b2da1019fd7acc6d204733e727b5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCCodeEmitter/getVMaskReg.cpp @@ -0,0 +1,11 @@ +unsigned RISCVMCCodeEmitter :: getVMaskReg ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { +auto MO = MI . getOperand ( OpNo ) ; +assert ( MO . isReg ( ) && "Expected a register." ) ; +if ( MO . getReg ( ) == RISCV :: V0 ) { +return 0x00 ; +} +if ( MO . getReg ( ) == RISCV :: NoRegister ) { +return 1 ; +} +llvm_unreachable ( "Invalid mask register." ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCCodeEmitter/~MCCodeEmitter.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCCodeEmitter/~MCCodeEmitter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..57285bc5a63128bbc884fa05d89c94e01e749b17 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCCodeEmitter/~MCCodeEmitter.cpp @@ -0,0 +1,2 @@ +~ RISCVMCCodeEmitter ( ) override { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCExpr/MCExpr.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCExpr/MCExpr.cpp new file mode 100644 index 0000000000000000000000000000000000000000..74f5e60780169fc028698eef8dc158ccc2a8db40 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCExpr/MCExpr.cpp @@ -0,0 +1,2 @@ +explicit RISCVMCExpr ( const MCExpr * Expr , VariantKind Kind ) : Expr ( Expr ) , Kind ( Kind ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCExpr/classof1.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCExpr/classof1.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2b052897719aaca60ef09baece651fd4286e607f --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCExpr/classof1.cpp @@ -0,0 +1,3 @@ +static bool classof ( const MCExpr * E ) { +return E -> getKind ( ) == MCExpr :: Target ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCExpr/classof2.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCExpr/classof2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..93cd72fefe4b02085f454f52c4bf2f5a49f24e98 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCExpr/classof2.cpp @@ -0,0 +1,3 @@ +static bool classof ( const RISCVMCExpr * ) { +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCExpr/create.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCExpr/create.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8a51ee50f0d3ca2586fb2c47480f8c2643d58c4d --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCExpr/create.cpp @@ -0,0 +1,3 @@ +const RISCVMCExpr * RISCVMCExpr :: create ( const MCExpr * Expr , VariantKind Kind , MCContext & Ctx ) { +return new ( Ctx ) RISCVMCExpr ( Expr , Kind ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCExpr/enumVariantKind.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCExpr/enumVariantKind.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9ce966d7803ce1640f58b8ba22ec83ff8348f03b --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCExpr/enumVariantKind.cpp @@ -0,0 +1,17 @@ +enum VariantKind { +VK_RISCV_None , +VK_RISCV_LO , +VK_RISCV_HI , +VK_RISCV_PCREL_LO , +VK_RISCV_PCREL_HI , +VK_RISCV_GOT_HI , +VK_RISCV_TPREL_LO , +VK_RISCV_TPREL_HI , +VK_RISCV_TPREL_ADD , +VK_RISCV_TLS_GOT_HI , +VK_RISCV_TLS_GD_HI , +VK_RISCV_CALL , +VK_RISCV_CALL_PLT , +VK_RISCV_32_PCREL , +VK_RISCV_Invalid , +} ; \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCExpr/evaluateAsConstant.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCExpr/evaluateAsConstant.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2c9260a3a6e5c4971230a8404128ebf2b47fe589 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCExpr/evaluateAsConstant.cpp @@ -0,0 +1,9 @@ +bool RISCVMCExpr :: evaluateAsConstant ( int64_t & Res ) const { +MCValue Value ; +return false ; +} +if ( ! Value . isAbsolute ( ) ) { +return false ; +} +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCExpr/evaluateAsInt64.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCExpr/evaluateAsInt64.cpp new file mode 100644 index 0000000000000000000000000000000000000000..af7a4bab966adc0b94128d2c35a08817b6d38863 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCExpr/evaluateAsInt64.cpp @@ -0,0 +1,11 @@ +int64_t RISCVMCExpr :: evaluateAsInt64 ( int64_t Value ) const { +if ( Kind == RISCVMCExpr :: VK_RISCV_LO ) { +Value = static_cast < uint64_t > ( ( Value << 52 ) >> 52 ) ; +return Value ; +} +if ( Kind == RISCVMCExpr :: VK_RISCV_HI ) { +Value = static_cast < uint64_t > ( ( Value + 0x800 ) >> 12 ) ; +return Value ; +} +llvm_unreachable ( "Invalid kind" ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCExpr/evaluateAsRelocatableImpl.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCExpr/evaluateAsRelocatableImpl.cpp new file mode 100644 index 0000000000000000000000000000000000000000..21d47913f73595e285cec77f5494ac51d58e77b5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCExpr/evaluateAsRelocatableImpl.cpp @@ -0,0 +1,41 @@ +bool RISCVMCExpr :: evaluateAsRelocatableImpl ( MCValue & Res , const MCAsmLayout * Layout , const MCFixup * Fixup ) const { +MCValue Value ; +if ( ! getSubExpr ( ) -> evaluateAsRelocatable ( Res , Layout , Fixup ) ) { +return false ; +} +if ( Res . getSymA ( ) ) { +if ( Res . getSymB ( ) ) { +if ( getKind ( ) == RISCVMCExpr :: VK_RISCV_LO ) { +return false ; +} +if ( getKind ( ) == RISCVMCExpr :: VK_RISCV_HI ) { +return false ; +} +if ( getKind ( ) == RISCVMCExpr :: VK_RISCV_PCREL_LO ) { +return false ; +} +if ( getKind ( ) == RISCVMCExpr :: VK_RISCV_PCREL_HI ) { +return false ; +} +if ( getKind ( ) == RISCVMCExpr :: VK_RISCV_GOT_HI ) { +return false ; +} +if ( getKind ( ) == RISCVMCExpr :: VK_RISCV_TPREL_LO ) { +return false ; +} +if ( getKind ( ) == RISCVMCExpr :: VK_RISCV_TPREL_HI ) { +return false ; +} +if ( getKind ( ) == RISCVMCExpr :: VK_RISCV_TPREL_ADD ) { +return false ; +} +if ( getKind ( ) == RISCVMCExpr :: VK_RISCV_TLS_GOT_HI ) { +return false ; +} +if ( getKind ( ) == RISCVMCExpr :: VK_RISCV_TLS_GD_HI ) { +return false ; +} +} +} +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCExpr/findAssociatedFragment.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCExpr/findAssociatedFragment.cpp new file mode 100644 index 0000000000000000000000000000000000000000..00a5c41996b4821d7075c77e4ac4311bbd9c40e3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCExpr/findAssociatedFragment.cpp @@ -0,0 +1,3 @@ +MCFragment * findAssociatedFragment ( ) const override { +return getSubExpr ( ) -> findAssociatedFragment ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCExpr/fixELFSymbolsInTLSFixups.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCExpr/fixELFSymbolsInTLSFixups.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1dd0c3c0369c870425307c557b40dfd78f60bfcf --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCExpr/fixELFSymbolsInTLSFixups.cpp @@ -0,0 +1,11 @@ +void RISCVMCExpr :: fixELFSymbolsInTLSFixups ( MCAssembler & Asm ) const { +if ( getKind ( ) == RISCVMCExpr :: VK_RISCV_TPREL_HI ) { +fixELFSymbolsInTLSFixupsImpl ( getSubExpr ( ) , Asm ) ; +} +if ( getKind ( ) == RISCVMCExpr :: VK_RISCV_TLS_GOT_HI ) { +fixELFSymbolsInTLSFixupsImpl ( getSubExpr ( ) , Asm ) ; +} +if ( getKind ( ) == RISCVMCExpr :: VK_RISCV_TLS_GD_HI ) { +fixELFSymbolsInTLSFixupsImpl ( getSubExpr ( ) , Asm ) ; +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCExpr/fixELFSymbolsInTLSFixupsImpl.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCExpr/fixELFSymbolsInTLSFixupsImpl.cpp new file mode 100644 index 0000000000000000000000000000000000000000..09abc3a6f4c60e0906522ecfba24bdbe49a286fd --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCExpr/fixELFSymbolsInTLSFixupsImpl.cpp @@ -0,0 +1,20 @@ +static void fixELFSymbolsInTLSFixupsImpl ( const MCExpr * Expr , MCAssembler & Asm ) { +if ( Expr -> getKind ( ) == MCExpr :: Target ) { +llvm_unreachable ( "Can't handle nested target expression" ) ; +} +if ( Expr -> getKind ( ) == MCExpr :: Constant ) { +} +if ( Expr -> getKind ( ) == MCExpr :: Binary ) { +const MCBinaryExpr * BE ; +BE = cast < MCBinaryExpr > ( Expr ) ; +fixELFSymbolsInTLSFixupsImpl ( BE -> getLHS ( ) , Asm ) ; +fixELFSymbolsInTLSFixupsImpl ( BE -> getRHS ( ) , Asm ) ; +} +if ( Expr -> getKind ( ) == MCExpr :: SymbolRef ) { +const MCSymbolRefExpr & SymRef = * cast < MCSymbolRefExpr > ( Expr ) ; +cast < MCSymbolELF > ( SymRef . getSymbol ( ) ) . setType ( ELF :: STT_TLS ) ; +} +if ( Expr -> getKind ( ) == MCExpr :: Unary ) { +fixELFSymbolsInTLSFixupsImpl ( cast < MCUnaryExpr > ( Expr ) -> getSubExpr ( ) , Asm ) ; +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCExpr/getKind.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCExpr/getKind.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d711002a252a9dd02f4cfd37981b41932cfcd805 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCExpr/getKind.cpp @@ -0,0 +1,3 @@ +VariantKind getKind ( ) const { +return Kind ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCExpr/getPCRelHiFixup.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCExpr/getPCRelHiFixup.cpp new file mode 100644 index 0000000000000000000000000000000000000000..81eb96a0f825e508a60d46709bf9a0a7e5d9b8e9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCExpr/getPCRelHiFixup.cpp @@ -0,0 +1,2 @@ +const MCFixup * RISCVMCExpr :: getPCRelHiFixup ( const MCFragment * * DFOut ) const { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCExpr/getSubExpr.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCExpr/getSubExpr.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d7e2553d1d84be4fd14ae6489f4304e9c6da6514 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCExpr/getSubExpr.cpp @@ -0,0 +1,3 @@ +const MCExpr * getSubExpr ( ) const { +return Expr ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCExpr/getVariantKindForName.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCExpr/getVariantKindForName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9a3adc41ddb642e655aeab7d1e1a20b610477920 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCExpr/getVariantKindForName.cpp @@ -0,0 +1,33 @@ +RISCVMCExpr :: VariantKind RISCVMCExpr :: getVariantKindForName ( StringRef name ) { +if ( name == "lo" ) { +return RISCVMCExpr :: VK_RISCV_LO ; +} +if ( name == "hi" ) { +return RISCVMCExpr :: VK_RISCV_HI ; +} +if ( name == "pcrel_lo" ) { +return RISCVMCExpr :: VK_RISCV_PCREL_LO ; +} +if ( name == "pcrel_hi" ) { +return RISCVMCExpr :: VK_RISCV_PCREL_HI ; +} +if ( name == "got_pcrel_hi" ) { +return RISCVMCExpr :: VK_RISCV_GOT_HI ; +} +if ( name == "tprel_lo" ) { +return RISCVMCExpr :: VK_RISCV_TPREL_LO ; +} +if ( name == "tprel_hi" ) { +return RISCVMCExpr :: VK_RISCV_TPREL_HI ; +} +if ( name == "tprel_add" ) { +return RISCVMCExpr :: VK_RISCV_TPREL_ADD ; +} +if ( name == "tls_ie_pcrel_hi" ) { +return RISCVMCExpr :: VK_RISCV_TLS_GOT_HI ; +} +if ( name == "tls_gd_pcrel_hi" ) { +return RISCVMCExpr :: VK_RISCV_TLS_GD_HI ; +} +return RISCVMCExpr :: VK_RISCV_Invalid ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCExpr/getVariantKindName.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCExpr/getVariantKindName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3a14113780d7b4ef21b6a7e00220b3c88cf7af90 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCExpr/getVariantKindName.cpp @@ -0,0 +1,33 @@ +StringRef RISCVMCExpr :: getVariantKindName ( VariantKind Kind ) { +if ( Kind == RISCVMCExpr :: VK_RISCV_LO ) { +return "lo" ; +} +if ( Kind == RISCVMCExpr :: VK_RISCV_HI ) { +return "hi" ; +} +if ( Kind == RISCVMCExpr :: VK_RISCV_PCREL_LO ) { +return "pcrel_lo" ; +} +if ( Kind == RISCVMCExpr :: VK_RISCV_PCREL_HI ) { +return "pcrel_hi" ; +} +if ( Kind == RISCVMCExpr :: VK_RISCV_GOT_HI ) { +return "got_pcrel_hi" ; +} +if ( Kind == RISCVMCExpr :: VK_RISCV_TPREL_LO ) { +return "tprel_lo" ; +} +if ( Kind == RISCVMCExpr :: VK_RISCV_TPREL_HI ) { +return "tprel_hi" ; +} +if ( Kind == RISCVMCExpr :: VK_RISCV_TPREL_ADD ) { +return "tprel_add" ; +} +if ( Kind == RISCVMCExpr :: VK_RISCV_TLS_GOT_HI ) { +return "tls_ie_pcrel_hi" ; +} +if ( Kind == RISCVMCExpr :: VK_RISCV_TLS_GD_HI ) { +return "tls_gd_pcrel_hi" ; +} +llvm_unreachable ( "Invalid ELF symbol kind" ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCExpr/printImpl.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCExpr/printImpl.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9f9951d519591034af7b4a12ecb632ea0fa5c993 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCExpr/printImpl.cpp @@ -0,0 +1,70 @@ +void RISCVMCExpr :: printImpl ( raw_ostream & OS , const MCAsmInfo * MAI ) const { +VariantKind Kind ; +Kind = getKind ( ) ; +if ( Kind == RISCVMCExpr :: VK_RISCV_PCREL_LO ) { +OS << "%pcrel_lo(" ; +Expr -> print ( OS , MAI ) ; +OS << ")" ; +} +if ( Kind == RISCVMCExpr :: VK_RISCV_PCREL_HI ) { +OS << "%pcrel_hi(" ; +Expr -> print ( OS , MAI ) ; +OS << ")" ; +} +if ( Kind == RISCVMCExpr :: VK_RISCV_TPREL_LO ) { +OS << "%tprel_lo(" ; +Expr -> print ( OS , MAI ) ; +OS << ")" ; +} +if ( Kind == RISCVMCExpr :: VK_RISCV_TPREL_HI ) { +OS << "%tprel_hi(" ; +Expr -> print ( OS , MAI ) ; +OS << ")" ; +} +if ( Kind == RISCVMCExpr :: VK_RISCV_TPREL_ADD ) { +OS << "%tprel_add(" ; +Expr -> print ( OS , MAI ) ; +OS << ")" ; +} +if ( Kind == RISCVMCExpr :: VK_RISCV_LO ) { +OS << "%lo(" ; +Expr -> print ( OS , MAI ) ; +OS << ")" ; +} +if ( Kind == RISCVMCExpr :: VK_RISCV_HI ) { +OS << "%hi(" ; +Expr -> print ( OS , MAI ) ; +OS << ")" ; +} +if ( Kind == RISCVMCExpr :: VK_RISCV_GOT_HI ) { +OS << "%got_pcrel_hi(" ; +Expr -> print ( OS , MAI ) ; +OS << ")" ; +} +if ( Kind == RISCVMCExpr :: VK_RISCV_TLS_GOT_HI ) { +OS << "%tls_ie_pcrel_hi(" ; +Expr -> print ( OS , MAI ) ; +OS << ")" ; +} +if ( Kind == RISCVMCExpr :: VK_RISCV_TLS_GD_HI ) { +OS << "%tls_gd_pcrel_hi(" ; +Expr -> print ( OS , MAI ) ; +OS << ")" ; +} +if ( Kind == RISCVMCExpr :: VK_RISCV_CALL_PLT ) { +OS << "" ; +Expr -> print ( OS , MAI ) ; +OS << "@plt" ; +} +if ( Kind == RISCVMCExpr :: VK_RISCV_CALL ) { +OS << "" ; +Expr -> print ( OS , MAI ) ; +OS << "" ; +} +if ( Kind == RISCVMCExpr :: VK_RISCV_None ) { +OS << "" ; +Expr -> print ( OS , MAI ) ; +OS << "" ; +} +llvm_unreachable ( "Invalid ELF symbol kind" ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCExpr/visitUsedExpr.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCExpr/visitUsedExpr.cpp new file mode 100644 index 0000000000000000000000000000000000000000..22979ea4ea4342aaffa71479dff1fe630575795a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCExpr/visitUsedExpr.cpp @@ -0,0 +1,3 @@ +void RISCVMCExpr :: visitUsedExpr ( MCStreamer & Streamer ) const { +Streamer . visitUsedExpr ( * getSubExpr ( ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCTargetDesc/InstrAnalysis.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCTargetDesc/InstrAnalysis.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8c8d655ed90d0e535f23950705d6db8245250a2b --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCTargetDesc/InstrAnalysis.cpp @@ -0,0 +1,2 @@ +explicit RISCVMCInstrAnalysis ( const MCInstrInfo * Info ) : MCInstrAnalysis ( Info ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCTargetDesc/LLVMInitializeTargetMC.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCTargetDesc/LLVMInitializeTargetMC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..350fce94db9142b9e84915918328fb5c9fd25d38 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCTargetDesc/LLVMInitializeTargetMC.cpp @@ -0,0 +1,15 @@ +extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTargetMC ( ) { +for ( Target * T : { & getTheRISCV32Target ( ) , & getTheRISCV64Target ( ) } ) { +TargetRegistry :: RegisterMCAsmInfo ( * T , createRISCVMCAsmInfo ) ; +TargetRegistry :: RegisterMCInstrInfo ( * T , createRISCVMCInstrInfo ) ; +TargetRegistry :: RegisterMCRegInfo ( * T , createRISCVMCRegisterInfo ) ; +TargetRegistry :: RegisterMCAsmBackend ( * T , createRISCVAsmBackend ) ; +TargetRegistry :: RegisterMCCodeEmitter ( * T , createRISCVMCCodeEmitter ) ; +TargetRegistry :: RegisterMCInstPrinter ( * T , createRISCVMCInstPrinter ) ; +TargetRegistry :: RegisterMCSubtargetInfo ( * T , createRISCVMCSubtargetInfo ) ; +TargetRegistry :: RegisterObjectTargetStreamer ( * T , createRISCVObjectTargetStreamer ) ; +TargetRegistry :: RegisterMCInstrAnalysis ( * T , createRISCVInstrAnalysis ) ; +TargetRegistry :: RegisterAsmTargetStreamer ( * T , createRISCVAsmTargetStreamer ) ; +TargetRegistry :: RegisterNullTargetStreamer ( * T , createRISCVNullTargetStreamer ) ; +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCTargetDesc/createAsmTargetStreamer.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCTargetDesc/createAsmTargetStreamer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2d898066b8b3cc2f64eeeecdae05676d8f19797c --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCTargetDesc/createAsmTargetStreamer.cpp @@ -0,0 +1,3 @@ +static MCTargetStreamer * createRISCVAsmTargetStreamer ( MCStreamer & S , formatted_raw_ostream & OS , MCInstPrinter * InstPrint , bool isVerboseAsm ) { +return new RISCVTargetAsmStreamer ( S , OS ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCTargetDesc/createInstrAnalysis.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCTargetDesc/createInstrAnalysis.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cda392bd1fdfd168dc12e589990c1d182c310e46 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCTargetDesc/createInstrAnalysis.cpp @@ -0,0 +1,3 @@ +static MCInstrAnalysis * createRISCVInstrAnalysis ( const MCInstrInfo * Info ) { +return new RISCVMCInstrAnalysis ( Info ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCTargetDesc/createMCAsmInfo.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCTargetDesc/createMCAsmInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ddd65210b53b415a0b8935692573e85d5ea1c18f --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCTargetDesc/createMCAsmInfo.cpp @@ -0,0 +1,9 @@ +static MCAsmInfo * createRISCVMCAsmInfo ( const MCRegisterInfo & MRI , const Triple & TT , const MCTargetOptions & Options ) { +MCAsmInfo * MAI ; +MAI = new RISCVMCAsmInfo ( TT ) ; +MCRegister Reg ; +Reg = MRI . getDwarfRegNum ( RISCV :: X2 , true ) ; +MCCFIInstruction Inst = MCCFIInstruction :: cfiDefCfa ( nullptr , Reg , 0 ) ; +MAI -> addInitialFrameState ( Inst ) ; +return MAI ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCTargetDesc/createMCInstPrinter.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCTargetDesc/createMCInstPrinter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e96cde3bf933e8ee2a2ef354886791ae9c7dfa46 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCTargetDesc/createMCInstPrinter.cpp @@ -0,0 +1,3 @@ +static MCInstPrinter * createRISCVMCInstPrinter ( const Triple & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) { +return new RISCVInstPrinter ( MAI , MII , MRI ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCTargetDesc/createMCInstrInfo.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCTargetDesc/createMCInstrInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e73ddd4733e04e1edf92cfda76290929b128a797 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCTargetDesc/createMCInstrInfo.cpp @@ -0,0 +1,6 @@ +static MCInstrInfo * createRISCVMCInstrInfo ( ) { +MCInstrInfo * X ; +X = new MCInstrInfo ( ) ; +InitRISCVMCInstrInfo ( X ) ; +return X ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCTargetDesc/createMCRegisterInfo.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCTargetDesc/createMCRegisterInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..43946198a2b9b408d08306384d66ad3a9952b012 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCTargetDesc/createMCRegisterInfo.cpp @@ -0,0 +1,6 @@ +static MCRegisterInfo * createRISCVMCRegisterInfo ( const Triple & TT ) { +MCRegisterInfo * X ; +X = new MCRegisterInfo ( ) ; +InitRISCVMCRegisterInfo ( X , RISCV :: X1 ) ; +return X ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCTargetDesc/createMCSubtargetInfo.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCTargetDesc/createMCSubtargetInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..caf62c59f120532ecc9285ec5c993a973fa86956 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCTargetDesc/createMCSubtargetInfo.cpp @@ -0,0 +1,13 @@ +static MCSubtargetInfo * createRISCVMCSubtargetInfo ( const Triple & TT , StringRef CPU , StringRef FS ) { +std :: string CPUName ; +CPUName = std :: string ( CPU ) ; +if ( CPUName . empty ( ) ) { +if ( TT . isArch64Bit ( ) ) { +CPUName = "generic-rv64" ; +} +if ( ! TT . isArch64Bit ( ) ) { +CPUName = "generic-rv32" ; +} +} +return createRISCVMCSubtargetInfoImpl ( TT , CPUName , CPUName , FS ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCTargetDesc/createNullTargetStreamer.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCTargetDesc/createNullTargetStreamer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e8dbeff80846172342c350c0fba9b3cae972d7bb --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCTargetDesc/createNullTargetStreamer.cpp @@ -0,0 +1,3 @@ +static MCTargetStreamer * createRISCVNullTargetStreamer ( MCStreamer & S ) { +return new RISCVTargetStreamer ( S ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCTargetDesc/createObjectTargetStreamer.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCTargetDesc/createObjectTargetStreamer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7c2a8a86d36dbfd322b39e4fc65dbab41c24ab0f --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCTargetDesc/createObjectTargetStreamer.cpp @@ -0,0 +1,7 @@ +static MCTargetStreamer * createRISCVObjectTargetStreamer ( MCStreamer & S , const MCSubtargetInfo & STI ) { +const Triple & TT = STI . getTargetTriple ( ) ; +if ( TT . isOSBinFormatELF ( ) ) { +return new RISCVTargetELFStreamer ( S , STI ) ; +} +return new RISCVTargetELFStreamer ( S , STI ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCTargetDesc/evaluateBranch.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCTargetDesc/evaluateBranch.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7d327bffc4c1702361f2deab6d326dbb8be885c5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MCTargetDesc/evaluateBranch.cpp @@ -0,0 +1,47 @@ +bool evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size , uint64_t & Target ) const { +if ( Inst . getOpcode ( ) == RISCV :: BEQ ) { +Target = Addr + Inst . getOperand ( 2 ) . getImm ( ) ; +return true ; +} +if ( Inst . getOpcode ( ) == RISCV :: BNE ) { +Target = Addr + Inst . getOperand ( 2 ) . getImm ( ) ; +return true ; +} +if ( Inst . getOpcode ( ) == RISCV :: BLT ) { +Target = Addr + Inst . getOperand ( 2 ) . getImm ( ) ; +return true ; +} +if ( Inst . getOpcode ( ) == RISCV :: BGE ) { +Target = Addr + Inst . getOperand ( 2 ) . getImm ( ) ; +return true ; +} +if ( Inst . getOpcode ( ) == RISCV :: BLTU ) { +Target = Addr + Inst . getOperand ( 2 ) . getImm ( ) ; +return true ; +} +if ( Inst . getOpcode ( ) == RISCV :: BGEU ) { +Target = Addr + Inst . getOperand ( 2 ) . getImm ( ) ; +return true ; +} +if ( Inst . getOpcode ( ) == RISCV :: C_BEQZ ) { +Target = Addr + Inst . getOperand ( 1 ) . getImm ( ) ; +return true ; +} +if ( Inst . getOpcode ( ) == RISCV :: C_BNEZ ) { +Target = Addr + Inst . getOperand ( 1 ) . getImm ( ) ; +return true ; +} +if ( Inst . getOpcode ( ) == RISCV :: JAL ) { +Target = Addr + Inst . getOperand ( 1 ) . getImm ( ) ; +return true ; +} +if ( Inst . getOpcode ( ) == RISCV :: C_JAL ) { +Target = Addr + Inst . getOperand ( 0 ) . getImm ( ) ; +return true ; +} +if ( Inst . getOpcode ( ) == RISCV :: C_J ) { +Target = Addr + Inst . getOperand ( 0 ) . getImm ( ) ; +return true ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MatInt/generateInstSeq.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MatInt/generateInstSeq.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7efac9c271d6fe90289ebbb66a0539c554440b7e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MatInt/generateInstSeq.cpp @@ -0,0 +1,32 @@ +MatInt :: InstSeq MatInt :: generateInstSeq ( int64_t Val ) { +InstSeq Insts ; +if ( Highest12 != 0 ) { +if ( SignExtend64 < 52 > ( Val ) == 0 ) { +Insts . push_back ( Inst ( RISCV :: LU52I_D , SignExtend64 < 12 > ( Highest12 ) ) ) ; +return Insts ; +} +} +if ( Hi20 == 0 ) { +Insts . push_back ( Inst ( RISCV :: ORI , Lo12 ) ) ; +} +if ( Hi20 != 0 ) { +if ( SignExtend32 < 1 > ( Lo12 >> 11 ) == SignExtend32 < 20 > ( Hi20 ) ) { +Insts . push_back ( Inst ( RISCV :: ADDI_W , SignExtend64 < 12 > ( Lo12 ) ) ) ; +} +} +if ( Hi20 != 0 ) { +if ( SignExtend32 < 1 > ( Lo12 >> 11 ) != SignExtend32 < 20 > ( Hi20 ) ) { +Insts . push_back ( Inst ( RISCV :: LU12I_W , SignExtend64 < 20 > ( Hi20 ) ) ) ; +if ( Lo12 != 0 ) { +Insts . push_back ( Inst ( RISCV :: ORI , Lo12 ) ) ; +} +} +} +if ( SignExtend32 < 1 > ( Hi20 >> 19 ) != SignExtend32 < 20 > ( Higher20 ) ) { +Insts . push_back ( Inst ( RISCV :: LU32I_D , SignExtend64 < 20 > ( Higher20 ) ) ) ; +} +if ( SignExtend32 < 1 > ( Higher20 >> 19 ) != SignExtend32 < 12 > ( Highest12 ) ) { +Insts . push_back ( Inst ( RISCV :: LU52I_D , SignExtend64 < 12 > ( Highest12 ) ) ) ; +} +return Insts ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MatInt/getIntMatCost.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MatInt/getIntMatCost.cpp new file mode 100644 index 0000000000000000000000000000000000000000..98bcc8a891aab82616d0c0346d7724187bc88265 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MatInt/getIntMatCost.cpp @@ -0,0 +1,3 @@ +int getIntMatCost ( const APInt & Val , unsigned Size , bool IsRV64 ) { +return std :: max ( 1 , Cost ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MatInt/structInst.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MatInt/structInst.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f25780f5a7195e77e9196dea579a14a99922338c --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/MatInt/structInst.cpp @@ -0,0 +1,6 @@ +struct Inst { +unsigned Opc ; +int64_t Imm ; +Inst ( unsigned Opc , int64_t Imm ) : Opc ( Opc ) , Imm ( Imm ) { +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/TargetAsmStreamer.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/TargetAsmStreamer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0a721f8eb40daba11267b011e7fd009f7dc683b0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/TargetAsmStreamer.cpp @@ -0,0 +1,2 @@ +RISCVTargetAsmStreamer :: RISCVTargetAsmStreamer ( MCStreamer & S , formatted_raw_ostream & OS ) : RISCVTargetStreamer ( S ) , OS ( OS ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/TargetStreamer.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/TargetStreamer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d01f2e2668a2d3980c1d615b5dac7e34580f2c23 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/TargetStreamer.cpp @@ -0,0 +1,2 @@ +RISCVTargetStreamer :: RISCVTargetStreamer ( MCStreamer & S ) : MCTargetStreamer ( S ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitAttribute.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitAttribute.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8d2f6bcc9f02c18f6dfffc45b2a441d5509bd2ac --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitAttribute.cpp @@ -0,0 +1,3 @@ +void RISCVTargetAsmStreamer :: emitAttribute ( unsigned Attribute , unsigned Value ) { +OS << "\t.attribute\t" << Attribute << ", " << Twine ( Value ) << "\n" ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitAttribute2.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitAttribute2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9c71365437e5525c859faf9ab85e96acff6ba2d9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitAttribute2.cpp @@ -0,0 +1,2 @@ +void RISCVTargetStreamer :: emitAttribute ( unsigned Attribute , unsigned Value ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionNoPIC.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionNoPIC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1b5d1c922b2b3bea325aea8b6ac2de8f47be9f36 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionNoPIC.cpp @@ -0,0 +1,3 @@ +void RISCVTargetAsmStreamer :: emitDirectiveOptionNoPIC ( ) { +OS << "\t.option\tnopic\n" ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionNoPIC2.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionNoPIC2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ab3899bf418f58b7b4e5212c1af782177d55d9eb --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionNoPIC2.cpp @@ -0,0 +1,2 @@ +void RISCVTargetStreamer :: emitDirectiveOptionNoPIC ( ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionNoRVC.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionNoRVC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..97cf2a0487cd3e7ae1f1596577ae00a35ad70ced --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionNoRVC.cpp @@ -0,0 +1,3 @@ +void RISCVTargetAsmStreamer :: emitDirectiveOptionNoRVC ( ) { +OS << "\t.option\tnorvc\n" ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionNoRVC2.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionNoRVC2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..318d7a6a2fa4d048f0f13ae059f800ec2651f53b --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionNoRVC2.cpp @@ -0,0 +1,2 @@ +void RISCVTargetStreamer :: emitDirectiveOptionNoRVC ( ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionNoRelax.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionNoRelax.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e87e33e49a8d077f34b1bd82bf9368d80af142b2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionNoRelax.cpp @@ -0,0 +1,3 @@ +void RISCVTargetAsmStreamer :: emitDirectiveOptionNoRelax ( ) { +OS << "\t.option\tnorelax\n" ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionNoRelax2.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionNoRelax2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3efb5c42b15eb074468dcc86a759fd6410a3899e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionNoRelax2.cpp @@ -0,0 +1,2 @@ +void RISCVTargetStreamer :: emitDirectiveOptionNoRelax ( ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionPIC.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionPIC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0c92e7a1938cfaeb0a5b036d16b97165a972cf3b --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionPIC.cpp @@ -0,0 +1,3 @@ +void RISCVTargetAsmStreamer :: emitDirectiveOptionPIC ( ) { +OS << "\t.option\tpic\n" ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionPIC2.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionPIC2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e53655e8d3280f15d8414304d565f008fc6b68d1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionPIC2.cpp @@ -0,0 +1,2 @@ +void RISCVTargetStreamer :: emitDirectiveOptionPIC ( ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionPop.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionPop.cpp new file mode 100644 index 0000000000000000000000000000000000000000..06983911a87102c692fafb3c575746d0b45b9b54 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionPop.cpp @@ -0,0 +1,3 @@ +void RISCVTargetAsmStreamer :: emitDirectiveOptionPop ( ) { +OS << "\t.option\tpop\n" ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionPop2.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionPop2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0e4e92d90e1cd1b98887606b7e0d0dc57234ab65 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionPop2.cpp @@ -0,0 +1,2 @@ +void RISCVTargetStreamer :: emitDirectiveOptionPop ( ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionPush.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionPush.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c9f9ac92a5170b85967cd1eb1b9244b2ef1cc9b2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionPush.cpp @@ -0,0 +1,3 @@ +void RISCVTargetAsmStreamer :: emitDirectiveOptionPush ( ) { +OS << "\t.option\tpush\n" ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionPush2.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionPush2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..580e02e74bb52568f1836dd485721b66dfdcd288 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionPush2.cpp @@ -0,0 +1,2 @@ +void RISCVTargetStreamer :: emitDirectiveOptionPush ( ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionRVC.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionRVC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4bde69c4cf1ed35df3766850e0a99bcafda98c36 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionRVC.cpp @@ -0,0 +1,3 @@ +void RISCVTargetAsmStreamer :: emitDirectiveOptionRVC ( ) { +OS << "\t.option\trvc\n" ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionRVC2.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionRVC2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ffdc32e50a23b50114a69b3e291c7348a9b32a81 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionRVC2.cpp @@ -0,0 +1,2 @@ +void RISCVTargetStreamer :: emitDirectiveOptionRVC ( ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionRelax.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionRelax.cpp new file mode 100644 index 0000000000000000000000000000000000000000..82ee65142c5a60213414a6da34836de1ba42ffa4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionRelax.cpp @@ -0,0 +1,3 @@ +void RISCVTargetAsmStreamer :: emitDirectiveOptionRelax ( ) { +OS << "\t.option\trelax\n" ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionRelax2.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionRelax2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8dab2eeb000df18a32573927e4d4c462920992b9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitDirectiveOptionRelax2.cpp @@ -0,0 +1,2 @@ +void RISCVTargetStreamer :: emitDirectiveOptionRelax ( ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitIntTextAttribute.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitIntTextAttribute.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b45dbed89d26e0c9394a5ad2ff22d3d537fb7caa --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitIntTextAttribute.cpp @@ -0,0 +1,2 @@ +void RISCVTargetAsmStreamer :: emitIntTextAttribute ( unsigned Attribute , unsigned IntValue , StringRef StringValue ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitIntTextAttribute2.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitIntTextAttribute2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a250e433567ad1cbe4cd0e1d97123f578c098477 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitIntTextAttribute2.cpp @@ -0,0 +1,2 @@ +void RISCVTargetStreamer :: emitIntTextAttribute ( unsigned Attribute , unsigned IntValue , StringRef StringValue ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitTargetAttributes.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitTargetAttributes.cpp new file mode 100644 index 0000000000000000000000000000000000000000..96d011affc21bae9b3722521731b4f393d2b1a0d --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitTargetAttributes.cpp @@ -0,0 +1,123 @@ +void RISCVTargetStreamer :: emitTargetAttributes ( const MCSubtargetInfo & STI ) { +StringRef CPU ; +CPU = STI . getCPU ( ) ; +RISCV :: ArchKind ArchID ; +ArchID = RISCV :: parseCPUArch ( CPU ) ; +if ( ArchID == RISCV :: ArchKind :: CK804 ) { +ArchID = RISCV :: ArchKind :: CK803 ; +} +StringRef CPU_ARCH ; +CPU_ARCH = RISCV :: getArchName ( ArchID ) ; +if ( ArchID == RISCV :: ArchKind :: INVALID ) { +} +emitTextAttribute ( RISCVAttrs :: RISCV_ARCH_NAME | zm - split | CPU_ARCH , RISCVAttrs :: RISCV_ARCH_NAME | zm - split | CPU_ARCH ) ; +emitTextAttribute ( RISCVAttrs :: RISCV_CPU_NAME | zm - split | CPU , RISCVAttrs :: RISCV_CPU_NAME | zm - split | CPU ) ; +unsigned ISAFlag ; +ISAFlag = 0 ; +if ( STI . hasFeature ( RISCV :: Feature64Bit ) ) { +ISAFlag = ISAFlag | RISCVAttrs :: V2_ISA_E1 ; +} +if ( STI . hasFeature ( RISCV :: FeatureRV32E ) ) { +ISAFlag = ISAFlag | RISCVAttrs :: V2_ISA_1E2 ; +} +if ( STI . hasFeature ( RISCV :: FeatureStdExtM ) ) { +ISAFlag = ISAFlag | RISCVAttrs :: V2_ISA_2E3 ; +} +if ( STI . hasFeature ( RISCV :: FeatureStdExtA ) ) { +ISAFlag = ISAFlag | RISCVAttrs :: ISA_MP ; +} +if ( STI . hasFeature ( RISCV :: FeatureStdExtF ) ) { +ISAFlag = ISAFlag | RISCVAttrs :: V2_ISA_3E3R1 ; +} +if ( STI . hasFeature ( RISCV :: FeatureStdExtD ) ) { +ISAFlag = ISAFlag | RISCVAttrs :: V2_ISA_3E3R2 ; +} +if ( STI . hasFeature ( RISCV :: FeatureStdExtC ) ) { +ISAFlag = ISAFlag | RISCVAttrs :: V2_ISA_3E3R3 ; +} +if ( STI . hasFeature ( RISCV :: FeatureStdExtB ) ) { +ISAFlag = ISAFlag | RISCVAttrs :: V2_ISA_3E7 ; +} +if ( STI . hasFeature ( RISCV :: FeatureStdExtV ) ) { +ISAFlag = ISAFlag | RISCVAttrs :: ISA_MP_1E2 ; +} +if ( STI . hasFeature ( RISCV :: FeatureExtZfh ) ) { +ISAFlag = ISAFlag | RISCVAttrs :: V2_ISA_7E10 ; +} +if ( STI . hasFeature ( RISCV :: FeatureExtZba ) ) { +ISAFlag = ISAFlag | RISCVAttrs :: V2_ISA_10E60 ; +} +if ( STI . hasFeature ( RISCV :: FeatureExtZbb ) ) { +ISAFlag = ISAFlag | RISCVAttrs :: ISA_TRUST ; +} +if ( STI . hasFeature ( RISCV :: FeatureExtZbc ) ) { +ISAFlag = ISAFlag | RISCVAttrs :: ISA_JAVA ; +} +if ( STI . hasFeature ( RISCV :: FeatureExtZbe ) ) { +ISAFlag = ISAFlag | RISCVAttrs :: ISA_CACHE ; +} +if ( STI . hasFeature ( RISCV :: FeatureExtZbf ) ) { +ISAFlag = ISAFlag | RISCVAttrs :: ISA_NVIC ; +} +if ( STI . hasFeature ( RISCV :: FeatureExtZbm ) ) { +ISAFlag = ISAFlag | RISCVAttrs :: ISA_DSP ; +} +if ( STI . hasFeature ( RISCV :: FeatureExtZbp ) ) { +ISAFlag = ISAFlag | RISCVAttrs :: ISA_DSP_1E2 ; +} +if ( STI . hasFeature ( RISCV :: FeatureExtZbproposedc ) ) { +ISAFlag = ISAFlag | RISCVAttrs :: V2_ISA_DSPE60 ; +} +if ( STI . hasFeature ( RISCV :: FeatureExtZbr ) ) { +ISAFlag = ISAFlag | RISCVAttrs :: ISA_DSP_ENHANCE ; +} +if ( STI . hasFeature ( RISCV :: FeatureExtZbs ) ) { +ISAFlag = ISAFlag | RISCVAttrs :: ISA_DSP_SILAN ; +} +if ( STI . hasFeature ( RISCV :: FeatureExtZbt ) ) { +ISAFlag = ISAFlag | RISCVAttrs :: ISA_VDSP ; +} +if ( STI . hasFeature ( RISCV :: FeatureExtZvamo ) ) { +ISAFlag = ISAFlag | RISCVAttrs :: ISA_VDSP_2 ; +} +if ( STI . hasFeature ( RISCV :: FeatureStdExtZvlsseg ) ) { +ISAFlag = ISAFlag | RISCVAttrs :: ISA_VDSP_2E3 ; +} +ISAFlag = ISAFlag | RISCVAttrs :: ISA_VDSP_2E60F ; +emitAttribute ( RISCVAttrs :: RISCV_ISA_FLAGS | zm - split | ISAFlag , RISCVAttrs :: RISCV_ISA_FLAGS | zm - split | ISAFlag ) ; +unsigned ISAExtFlag ; +ISAExtFlag = 0 ; +ISAExtFlag = ISAExtFlag | RISCVAttrs :: ISA_FLOAT_E1 ; +ISAExtFlag = ISAExtFlag | RISCVAttrs :: ISA_FLOAT_1E2 ; +ISAExtFlag = ISAExtFlag | RISCVAttrs :: ISA_FLOAT_1E3 ; +ISAExtFlag = ISAExtFlag | RISCVAttrs :: ISA_FLOAT_3E4 ; +ISAExtFlag = ISAExtFlag | RISCVAttrs :: ISA_FLOAT_7E60 ; +emitAttribute ( RISCVAttrs :: RISCV_ISA_EXT_FLAGS | zm - split | ISAExtFlag , RISCVAttrs :: RISCV_ISA_EXT_FLAGS | zm - split | ISAExtFlag ) ; +emitAttribute ( RISCVAttrs :: RISCV_DSP_VERSION | zm - split | RISCVAttrs :: DSP_VERSION_EXTENSION , RISCVAttrs :: RISCV_DSP_VERSION | zm - split | RISCVAttrs :: DSP_VERSION_EXTENSION ) ; +emitAttribute ( RISCVAttrs :: RISCV_DSP_VERSION | zm - split | RISCVAttrs :: DSP_VERSION_2 , RISCVAttrs :: RISCV_DSP_VERSION | zm - split | RISCVAttrs :: DSP_VERSION_2 ) ; +emitAttribute ( RISCVAttrs :: RISCV_VDSP_VERSION | zm - split | RISCVAttrs :: VDSP_VERSION_2 , RISCVAttrs :: RISCV_VDSP_VERSION | zm - split | RISCVAttrs :: VDSP_VERSION_2 ) ; +emitAttribute ( RISCVAttrs :: RISCV_FPU_VERSION | zm - split | RISCVAttrs :: FPU_VERSION_2 , RISCVAttrs :: RISCV_FPU_VERSION | zm - split | RISCVAttrs :: FPU_VERSION_2 ) ; +emitAttribute ( RISCVAttrs :: RISCV_FPU_VERSION | zm - split | RISCVAttrs :: FPU_VERSION_2 , RISCVAttrs :: RISCV_FPU_VERSION | zm - split | RISCVAttrs :: FPU_VERSION_2 ) ; +emitAttribute ( RISCVAttrs :: RISCV_FPU_VERSION | zm - split | RISCVAttrs :: FPU_VERSION_3 , RISCVAttrs :: RISCV_FPU_VERSION | zm - split | RISCVAttrs :: FPU_VERSION_3 ) ; +emitAttribute ( RISCVAttrs :: RISCV_FPU_VERSION | zm - split | RISCVAttrs :: FPU_VERSION_3 , RISCVAttrs :: RISCV_FPU_VERSION | zm - split | RISCVAttrs :: FPU_VERSION_3 ) ; +emitAttribute ( RISCVAttrs :: RISCV_FPU_VERSION | zm - split | RISCVAttrs :: FPU_VERSION_3 , RISCVAttrs :: RISCV_FPU_VERSION | zm - split | RISCVAttrs :: FPU_VERSION_3 ) ; +bool hasAnyFloatExt ; +hasAnyFloatExt = STI . hasFeature ( RISCV :: FeatureFPUV2_SF ) || STI . hasFeature ( RISCV :: FeatureFPUV2_DF ) || STI . hasFeature ( RISCV :: FeatureFPUV3_HF ) || STI . hasFeature ( RISCV :: FeatureFPUV3_SF ) || STI . hasFeature ( RISCV :: FeatureFPUV3_DF ) ; +if ( ! hasAnyFloatExt ) { +emitAttribute ( RISCVAttrs :: RISCV_FPU_ABI | zm - split | RISCVAttrs :: FPU_ABI_SOFTFP , RISCVAttrs :: RISCV_FPU_ABI | zm - split | RISCVAttrs :: FPU_ABI_SOFTFP ) ; +emitAttribute ( RISCVAttrs :: RISCV_FPU_ABI | zm - split | RISCVAttrs :: FPU_ABI_SOFTFP , RISCVAttrs :: RISCV_FPU_ABI | zm - split | RISCVAttrs :: FPU_ABI_SOFTFP ) ; +emitAttribute ( RISCVAttrs :: RISCV_FPU_ABI | zm - split | RISCVAttrs :: FPU_ABI_SOFTFP , RISCVAttrs :: RISCV_FPU_ABI | zm - split | RISCVAttrs :: FPU_ABI_SOFTFP ) ; +emitAttribute ( RISCVAttrs :: RISCV_FPU_ABI | zm - split | RISCVAttrs :: FPU_ABI_SOFTFP , RISCVAttrs :: RISCV_FPU_ABI | zm - split | RISCVAttrs :: FPU_ABI_SOFTFP ) ; +unsigned HardFPFlag ; +HardFPFlag = 0 ; +HardFPFlag = HardFPFlag | RISCVAttrs :: FPU_HARDFP_HALF ; +HardFPFlag = HardFPFlag | RISCVAttrs :: FPU_HARDFP_SINGLE ; +HardFPFlag = HardFPFlag | RISCVAttrs :: FPU_HARDFP_SINGLE ; +HardFPFlag = HardFPFlag | RISCVAttrs :: FPU_HARDFP_DOUBLE ; +HardFPFlag = HardFPFlag | RISCVAttrs :: FPU_HARDFP_DOUBLE ; +if ( HardFPFlag != 0 ) { +emitAttribute ( RISCVAttrs :: RISCV_FPU_DENORMAL | zm - split | RISCVAttrs :: NEEDED , RISCVAttrs :: RISCV_FPU_DENORMAL | zm - split | RISCVAttrs :: NEEDED ) ; +emitAttribute ( RISCVAttrs :: RISCV_FPU_EXCEPTION | zm - split | RISCVAttrs :: NEEDED , RISCVAttrs :: RISCV_FPU_EXCEPTION | zm - split | RISCVAttrs :: NEEDED ) ; +emitTextAttribute ( RISCVAttrs :: RISCV_FPU_NUMBER_MODULE | zm - split | "IEEE 754" , RISCVAttrs :: RISCV_FPU_NUMBER_MODULE | zm - split | "IEEE 754" ) ; +emitAttribute ( RISCVAttrs :: RISCV_FPU_HARDFP | zm - split | HardFPFlag , RISCVAttrs :: RISCV_FPU_HARDFP | zm - split | HardFPFlag ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitTextAttribute.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitTextAttribute.cpp new file mode 100644 index 0000000000000000000000000000000000000000..92ee004c97a4bf17694b0bb8a2c12c5dd5041e60 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitTextAttribute.cpp @@ -0,0 +1,3 @@ +void RISCVTargetAsmStreamer :: emitTextAttribute ( unsigned Attribute , StringRef String ) { +OS << "\t.attribute\t" << Attribute << ", \"" << String << "\"\n" ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitTextAttribute2.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitTextAttribute2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1ba4e0bd348672d887f8382b2578f1ea569ce4bb --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/emitTextAttribute2.cpp @@ -0,0 +1,2 @@ +void RISCVTargetStreamer :: emitTextAttribute ( unsigned Attribute , StringRef String ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/finish.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/finish.cpp new file mode 100644 index 0000000000000000000000000000000000000000..72cc490e9bbd94a905f8c68774a3cc65d447ef4b --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/finish.cpp @@ -0,0 +1,3 @@ +void RISCVTargetStreamer :: finish ( ) { +finishAttributeSection ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/finishAttributeSection.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/finishAttributeSection.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f4f715915b3d6c18c95ea010004be56e2e19741a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/finishAttributeSection.cpp @@ -0,0 +1,2 @@ +void RISCVTargetAsmStreamer :: finishAttributeSection ( ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/finishAttributeSection2.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/finishAttributeSection2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c90f26086748201705f11aa9c938ef1819e2c59b --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Emission/TargetStreamer/finishAttributeSection2.cpp @@ -0,0 +1,2 @@ +void RISCVTargetStreamer :: finishAttributeSection ( ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/CleanupVSETVLI/CleanupVSETVLI.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/CleanupVSETVLI/CleanupVSETVLI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b525c178c6f923232691e6d814fc580ef86432e5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/CleanupVSETVLI/CleanupVSETVLI.cpp @@ -0,0 +1,3 @@ +RISCVCleanupVSETVLI ( ) : MachineFunctionPass ( ID ) { +initializeRISCVCleanupVSETVLIPass ( * PassRegistry :: getPassRegistry ( ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/CleanupVSETVLI/createPass.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/CleanupVSETVLI/createPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..13fce8ddd07f8e0cd3ef428aaba85bdf35a7b622 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/CleanupVSETVLI/createPass.cpp @@ -0,0 +1,3 @@ +FunctionPass * llvm :: createRISCVCleanupVSETVLIPass ( ) { +return new RISCVCleanupVSETVLI ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/CleanupVSETVLI/getAnalysisUsage.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/CleanupVSETVLI/getAnalysisUsage.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ead5f1a786d8e94c38aaeccf54e965a7633f1381 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/CleanupVSETVLI/getAnalysisUsage.cpp @@ -0,0 +1,4 @@ +void getAnalysisUsage ( AnalysisUsage & AU ) const override { +AU . setPreservesCFG ( ) ; +MachineFunctionPass :: getAnalysisUsage ( AU ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/CleanupVSETVLI/getPassName.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/CleanupVSETVLI/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7e570a0bb69cec0e395a8a3d316efdccad3ed5c6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/CleanupVSETVLI/getPassName.cpp @@ -0,0 +1,3 @@ +StringRef getPassName ( ) const override { +return RISCV_CLEANUP_VSETVLI_NAME ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/CleanupVSETVLI/getRequiredProperties.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/CleanupVSETVLI/getRequiredProperties.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0adda88e88df06602241df5ea12b1b2b61a75d55 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/CleanupVSETVLI/getRequiredProperties.cpp @@ -0,0 +1,3 @@ +MachineFunctionProperties getRequiredProperties ( ) const override { +return MachineFunctionProperties ( ) . set ( MachineFunctionProperties :: Property :: IsSSA ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/CleanupVSETVLI/runOnMachineBasicBlock.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/CleanupVSETVLI/runOnMachineBasicBlock.cpp new file mode 100644 index 0000000000000000000000000000000000000000..703cafe35cf8053a680632338c92037730fb0e44 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/CleanupVSETVLI/runOnMachineBasicBlock.cpp @@ -0,0 +1,11 @@ +bool RISCVCleanupVSETVLI :: runOnMachineBasicBlock ( MachineBasicBlock & MBB ) { +bool Changed = false ; +for ( MachineBasicBlock :: iterator I = MBB . instr_begin ( ) ; I != MBB . instr_end ( ) ; ++ I ) { +Changed = true ; +Changed = true ; +continue ; +Changed = true ; +Changed = true ; +} +return Changed ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/CleanupVSETVLI/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/CleanupVSETVLI/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c30191497c6520cdefb552547858a6a8a11f01f3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/CleanupVSETVLI/runOnMachineFunction.cpp @@ -0,0 +1,14 @@ +bool RISCVCleanupVSETVLI :: runOnMachineFunction ( MachineFunction & MF ) { +if ( skipFunction ( MF . getFunction ( ) ) ) { +return false ; +} +bool Changed = false ; +const RISCVSubtarget & ST = MF . getSubtarget < RISCVSubtarget > ( ) ; +if ( ! ST . hasStdExtV ( ) ) { +return false ; +} +for ( MachineBasicBlock & MBB : MF ) { +Changed = Changed | runOnMachineBasicBlock ( MBB ) ; +} +return Changed ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/ExpandAtomicPseudoInsts/ExpandAtomicPseudo.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/ExpandAtomicPseudoInsts/ExpandAtomicPseudo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ccb2a3d2f20668a6992dfe3dc2a56cc3d8a5c610 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/ExpandAtomicPseudoInsts/ExpandAtomicPseudo.cpp @@ -0,0 +1,3 @@ +RISCVExpandAtomicPseudo ( ) : MachineFunctionPass ( ID ) { +initializeRISCVExpandAtomicPseudoPass ( * PassRegistry :: getPassRegistry ( ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/ExpandAtomicPseudoInsts/createPass.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/ExpandAtomicPseudoInsts/createPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c07969f15eea8992f254c7b271f732543960c352 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/ExpandAtomicPseudoInsts/createPass.cpp @@ -0,0 +1,3 @@ +FunctionPass * llvm :: createRISCVExpandAtomicPseudoPass ( ) { +return new RISCVExpandAtomicPseudo ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/ExpandAtomicPseudoInsts/expandMBB.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/ExpandAtomicPseudoInsts/expandMBB.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d1c19539b9d24e6a860f74c1effd36e178d46781 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/ExpandAtomicPseudoInsts/expandMBB.cpp @@ -0,0 +1,10 @@ +bool RISCVExpandAtomicPseudo :: expandMBB ( MachineBasicBlock & MBB ) { +bool Modified = false ; +MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , E = MBB . end ( ) ; +for ( ; MBBI != E ; ) { +MachineBasicBlock :: iterator NMBBI = std :: next ( MBBI ) ; +Modified = Modified | expandMI ( MBB , MBBI , NMBBI ) ; +MBBI = NMBBI ; +} +return Modified ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/ExpandAtomicPseudoInsts/expandMI.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/ExpandAtomicPseudoInsts/expandMI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2b873cd1c4b79d2018b95c38a0e6863dc8830f28 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/ExpandAtomicPseudoInsts/expandMI.cpp @@ -0,0 +1,42 @@ +bool RISCVExpandAtomicPseudo :: expandMI ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , MachineBasicBlock :: iterator & NextMBBI ) { +if ( MBBI -> getOpcode ( ) == RISCV :: PseudoAtomicLoadNand32 ) { +return expandAtomicCmpSwap ( MBB , MBBI , NMBB ) ; +} +if ( MBBI -> getOpcode ( ) == RISCV :: PseudoAtomicLoadNand64 ) { +return expandAtomicCmpSwap ( MBB , MBBI , NMBB ) ; +} +if ( MBBI -> getOpcode ( ) == RISCV :: PseudoMaskedAtomicSwap32 ) { +return expandAtomicCmpSwapSubword ( MBB , MBBI , NMBB ) ; +} +if ( MBBI -> getOpcode ( ) == RISCV :: PseudoMaskedAtomicLoadAdd32 ) { +return expandAtomicCmpSwapSubword ( MBB , MBBI , NMBB ) ; +} +if ( MBBI -> getOpcode ( ) == RISCV :: PseudoMaskedAtomicLoadSub32 ) { +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +} +if ( MBBI -> getOpcode ( ) == RISCV :: PseudoMaskedAtomicLoadNand32 ) { +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +} +if ( MBBI -> getOpcode ( ) == RISCV :: PseudoMaskedAtomicLoadMax32 ) { +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +} +if ( MBBI -> getOpcode ( ) == RISCV :: PseudoMaskedAtomicLoadMin32 ) { +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +} +if ( MBBI -> getOpcode ( ) == RISCV :: PseudoMaskedAtomicLoadUMax32 ) { +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +} +if ( MBBI -> getOpcode ( ) == RISCV :: PseudoMaskedAtomicLoadUMin32 ) { +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +} +if ( MBBI -> getOpcode ( ) == RISCV :: PseudoCmpXchg32 ) { +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +} +if ( MBBI -> getOpcode ( ) == RISCV :: PseudoCmpXchg64 ) { +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +} +if ( MBBI -> getOpcode ( ) == RISCV :: PseudoMaskedCmpXchg32 ) { +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/ExpandAtomicPseudoInsts/getPassName.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/ExpandAtomicPseudoInsts/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2413e2bc9448a25b28da3410dad9b03494900b3f --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/ExpandAtomicPseudoInsts/getPassName.cpp @@ -0,0 +1,3 @@ +StringRef getPassName ( ) const override { +return RISCV_EXPAND_ATOMIC_PSEUDO_NAME ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/ExpandAtomicPseudoInsts/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/ExpandAtomicPseudoInsts/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4cf4944bdf584b37dc6db94217ea1c35871dd5dc --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/ExpandAtomicPseudoInsts/runOnMachineFunction.cpp @@ -0,0 +1,8 @@ +bool RISCVExpandAtomicPseudo :: runOnMachineFunction ( MachineFunction & MF ) { +TII = static_cast < const RISCVInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; +bool Modified = false ; +for ( auto & MBB : MF ) { +Modified = Modified | expandMBB ( MBB ) ; +} +return Modified ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/ExpandPseudoInsts/ExpandPseudo.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/ExpandPseudoInsts/ExpandPseudo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0e43cd14a41cbb44f47d19556c517f698a73f8cc --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/ExpandPseudoInsts/ExpandPseudo.cpp @@ -0,0 +1,3 @@ +RISCVExpandPseudo ( ) : MachineFunctionPass ( ID ) { +initializeRISCVExpandPseudoPass ( * PassRegistry :: getPassRegistry ( ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/ExpandPseudoInsts/createPass.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/ExpandPseudoInsts/createPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7e56e1dfbefb3cebf300e0b1d10c62c98a900adc --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/ExpandPseudoInsts/createPass.cpp @@ -0,0 +1,3 @@ +FunctionPass * createRISCVExpandPseudoPass ( ) { +return new RISCVExpandPseudo ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/ExpandPseudoInsts/expandMBB.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/ExpandPseudoInsts/expandMBB.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ecaa4a746dfd38727c61ed5247656655279d2714 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/ExpandPseudoInsts/expandMBB.cpp @@ -0,0 +1,10 @@ +bool RISCVExpandPseudo :: expandMBB ( MachineBasicBlock & MBB ) { +bool Modified = false ; +MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , E = MBB . end ( ) ; +for ( ; MBBI != E ; ) { +MachineBasicBlock :: iterator NMBBI = std :: next ( MBBI ) ; +Modified = Modified | expandMI ( MBB , MBBI , NMBBI ) ; +MBBI = NMBBI ; +} +return Modified ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/ExpandPseudoInsts/expandMI.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/ExpandPseudoInsts/expandMI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..429e58a4dad9fa5d2168deb69d46d902c857572c --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/ExpandPseudoInsts/expandMI.cpp @@ -0,0 +1,63 @@ +bool RISCVExpandPseudo :: expandMI ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , MachineBasicBlock :: iterator & NextMBBI ) { +if ( MBBI -> getOpcode ( ) == RISCV :: PseudoLLA ) { +return expandAtomicCmpSwap ( MBB , MBBI , NMBB ) ; +} +if ( MBBI -> getOpcode ( ) == RISCV :: PseudoLA ) { +return expandAtomicCmpSwap ( MBB , MBBI , NMBB ) ; +} +if ( MBBI -> getOpcode ( ) == RISCV :: PseudoLA_TLS_IE ) { +return expandAtomicCmpSwapSubword ( MBB , MBBI , NMBB ) ; +} +if ( MBBI -> getOpcode ( ) == RISCV :: PseudoLA_TLS_GD ) { +return expandAtomicCmpSwapSubword ( MBB , MBBI , NMBB ) ; +} +if ( MBBI -> getOpcode ( ) == RISCV :: PseudoVSETVLI ) { +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +} +if ( MBBI -> getOpcode ( ) == RISCV :: PseudoVSETIVLI ) { +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +} +if ( MBBI -> getOpcode ( ) == RISCV :: PseudoVMCLR_M_B1 ) { +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +} +if ( MBBI -> getOpcode ( ) == RISCV :: PseudoVMCLR_M_B2 ) { +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +} +if ( MBBI -> getOpcode ( ) == RISCV :: PseudoVMCLR_M_B4 ) { +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +} +if ( MBBI -> getOpcode ( ) == RISCV :: PseudoVMCLR_M_B8 ) { +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +} +if ( MBBI -> getOpcode ( ) == RISCV :: PseudoVMCLR_M_B16 ) { +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +} +if ( MBBI -> getOpcode ( ) == RISCV :: PseudoVMCLR_M_B32 ) { +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +} +if ( MBBI -> getOpcode ( ) == RISCV :: PseudoVMCLR_M_B64 ) { +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +} +if ( MBBI -> getOpcode ( ) == RISCV :: PseudoVMSET_M_B1 ) { +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +} +if ( MBBI -> getOpcode ( ) == RISCV :: PseudoVMSET_M_B2 ) { +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +} +if ( MBBI -> getOpcode ( ) == RISCV :: PseudoVMSET_M_B4 ) { +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +} +if ( MBBI -> getOpcode ( ) == RISCV :: PseudoVMSET_M_B8 ) { +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +} +if ( MBBI -> getOpcode ( ) == RISCV :: PseudoVMSET_M_B16 ) { +return expandAtomicBinOpSubword ( MBB , MBBI , NMBB ) ; +} +if ( MBBI -> getOpcode ( ) == RISCV :: PseudoVMSET_M_B32 ) { +return expandAtomicBinOp ( MBB , MBBI , NMBB ) ; +} +if ( MBBI -> getOpcode ( ) == RISCV :: PseudoVMSET_M_B64 ) { +return expandAtomicBinOp ( MBB , MBBI , NMBB ) ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/ExpandPseudoInsts/getPassName.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/ExpandPseudoInsts/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3c671c393167571a385416e95d915917dae9816e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/ExpandPseudoInsts/getPassName.cpp @@ -0,0 +1,3 @@ +StringRef getPassName ( ) const override { +return RISCV_EXPAND_PSEUDO_NAME ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/ExpandPseudoInsts/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/ExpandPseudoInsts/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..34204fbabbd2c9931e0e54df2b0e3098d4540267 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/ExpandPseudoInsts/runOnMachineFunction.cpp @@ -0,0 +1,8 @@ +bool RISCVExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) { +TII = static_cast < const RISCVInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; +bool Modified = false ; +for ( auto & MBB : MF ) { +Modified = Modified | expandMBB ( MBB ) ; +} +return Modified ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/MergeBaseOffset/MergeBaseOffsetOpt.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/MergeBaseOffset/MergeBaseOffsetOpt.cpp new file mode 100644 index 0000000000000000000000000000000000000000..de8c6107b32968a9525c9d1fa2ec84a09f1cf018 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/MergeBaseOffset/MergeBaseOffsetOpt.cpp @@ -0,0 +1,2 @@ +RISCVMergeBaseOffsetOpt ( ) : MachineFunctionPass ( ID ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/MergeBaseOffset/createPass.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/MergeBaseOffset/createPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..77da6b9cb17ab8540023b8642f6f52dd8bd87967 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/MergeBaseOffset/createPass.cpp @@ -0,0 +1,3 @@ +FunctionPass * llvm :: createRISCVMergeBaseOffsetOptPass ( ) { +return new RISCVMergeBaseOffsetOpt ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/MergeBaseOffset/getPassName.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/MergeBaseOffset/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a17e0aa37b03c42edddac90a94a3646c1d4e2458 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/MergeBaseOffset/getPassName.cpp @@ -0,0 +1,3 @@ +StringRef getPassName ( ) const override { +return RISCV_MERGE_BASE_OFFSET_NAME ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/MergeBaseOffset/getRequiredProperties.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/MergeBaseOffset/getRequiredProperties.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0adda88e88df06602241df5ea12b1b2b61a75d55 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/MergeBaseOffset/getRequiredProperties.cpp @@ -0,0 +1,3 @@ +MachineFunctionProperties getRequiredProperties ( ) const override { +return MachineFunctionProperties ( ) . set ( MachineFunctionProperties :: Property :: IsSSA ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/MergeBaseOffset/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/MergeBaseOffset/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d4589212e731444dc028dfa66a42eb91fe547980 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Optimization/MergeBaseOffset/runOnMachineFunction.cpp @@ -0,0 +1,18 @@ +bool RISCVMergeBaseOffset :: runOnMachineFunction ( MachineFunction & MF ) { +if ( skipFunction ( * F . getFunction ( ) ) ) { +return false ; +} +bool Changed = false ; +const Subtarget & ST = MF . getSubtarget < Subtarget > ( ) ; +TII = ST . getInstrInfo ( ) ; +TRI = ST . getRegisterInfo ( ) ; +MRI = & MF . getRegInfo ( ) ; +ClobberedRegs . resize ( TRI -> getNumRegs ( ) ) ; +if ( ST . isV9 ( ) ) { +return false ; +} +for ( MachineBasicBlock & MBB : MF ) { +Changed = Changed | runOnMachineBasicBlock ( MBB ) ; +} +return Changed ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/InstrInfo.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/InstrInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..768f27c25f9b244976b0c9dec8e88b764b418225 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/InstrInfo.cpp @@ -0,0 +1,2 @@ +RISCVInstrInfo :: RISCVInstrInfo ( RISCVSubtarget & STI ) : RISCVGenInstrInfo ( RISCV :: ADJCALLSTACKDOWN , RISCV :: ADJCALLSTACKUP ) , STI ( STI ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/analyzeBranch.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/analyzeBranch.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f83f76a26a6c72bf841be133e3bb4afe2e42e887 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/analyzeBranch.cpp @@ -0,0 +1,60 @@ +bool RISCVInstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { +TBB = nullptr ; +FBB = nullptr ; +Cond . clear ( ) ; +MachineBasicBlock :: iterator I = MBB . getLastNonDebugInstr ( ) ; +if ( I == MBB . end ( ) ) { +return false ; +} +if ( ! isUnpredicatedTerminator ( * I ) ) { +return false ; +} +MachineBasicBlock :: iterator FirstUncondOrIndirectBr = MBB . end ( ) ; +int NumTerminators = 0 ; +for ( auto J = I . getReverse ( ) ; J != MBB . rend ( ) && isUnpredicatedTerminator ( * J ) ; J ++ ) { +NumTerminators = NumTerminators + 1 ; +if ( J -> getDesc ( ) . isUnconditionalBranch ( ) ) { +FirstUncondOrIndirectBr = J . getReverse ( ) ; +} +if ( J -> getDesc ( ) . isIndirectBranch ( ) ) { +FirstUncondOrIndirectBr = J . getReverse ( ) ; +} +} +if ( AllowModify ) { +if ( FirstUncondOrIndirectBr != MBB . end ( ) ) { +for ( ; std :: next ( FirstUncondOrIndirectBr ) != MBB . end ( ) ; ) { +std :: next ( FirstUncondOrIndirectBr ) -> eraseFromParent ( ) ; +NumTerminators = NumTerminators - 1 ; +} +I = FirstUncondOrIndirectBr ; +} +} +if ( I -> getDesc ( ) . isIndirectBranch ( ) ) { +return true ; +} +if ( NumTerminators > 2 ) { +return true ; +} +if ( NumTerminators == 1 ) { +if ( I -> getDesc ( ) . isUnconditionalBranch ( ) ) { +TBB = getBranchDestBlock ( * I ) ; +return false ; +} +} +if ( NumTerminators == 1 ) { +if ( I -> getDesc ( ) . isConditionalBranch ( ) ) { +parseCondBranch ( * I , TBB , Cond ) ; +return false ; +} +} +if ( NumTerminators == 2 ) { +if ( I -> getDesc ( ) . isUnconditionalBranch ( ) ) { +if ( std :: prev ( I ) -> getDesc ( ) . isConditionalBranch ( ) ) { +parseCondBranch ( * std :: prev ( I ) , TBB , Cond ) ; +FBB = getBranchDestBlock ( * I ) ; +return false ; +} +} +} +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/areMemAccessesTriviallyDisjoint.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/areMemAccessesTriviallyDisjoint.cpp new file mode 100644 index 0000000000000000000000000000000000000000..37c649e09a2117559073cce57410d67a1bfd02f9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/areMemAccessesTriviallyDisjoint.cpp @@ -0,0 +1,36 @@ +bool RISCVInstrInfo :: areMemAccessesTriviallyDisjoint ( const MachineInstr & MIa , const MachineInstr & MIb ) const { +assert ( MIa . mayLoadOrStore ( ) && "MIa must be a load or store." ) ; +assert ( MIb . mayLoadOrStore ( ) && "MIb must be a load or store." ) ; +if ( MIa . hasUnmodeledSideEffects ( ) ) { +return false ; +} +if ( MIb . hasUnmodeledSideEffects ( ) ) { +return false ; +} +if ( MIa . hasOrderedMemoryRef ( ) ) { +return false ; +} +if ( MIb . hasOrderedMemoryRef ( ) ) { +return false ; +} +const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ; +const MachineOperand * BaseOpA = nullptr ; +const MachineOperand * BaseOpB = nullptr ; +int64_t OffsetA = 0 ; +int64_t OffsetB = 0 ; +unsigned WidthA = 0 ; +unsigned WidthB = 0 ; +if ( getMemOperandWithOffsetWidth ( MIa , BaseOpA , OffsetA , WidthA , TRI ) ) { +if ( getMemOperandWithOffsetWidth ( MIb , BaseOpB , OffsetB , WidthB , TRI ) ) { +if ( BaseOpA -> isIdenticalTo ( * BaseOpB ) ) { +int LowOffset = std :: min ( OffsetA , OffsetB ) ; +int HighOffset = std :: max ( OffsetA , OffsetB ) ; +int LowWidth = ( LowOffset == OffsetA ) ? WidthA : WidthB ; +if ( LowOffset + LowWidth <= HighOffset ) { +return true ; +} +} +} +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/buildOutlinedFrame.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/buildOutlinedFrame.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fe3af7767cd950617fdf22b309054018bb5a752d --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/buildOutlinedFrame.cpp @@ -0,0 +1,45 @@ +void RISCVInstrInfo :: buildOutlinedFrame ( MachineBasicBlock & MBB , MachineFunction & MF , const outliner :: OutlinedFunction & OF ) const { +if ( OF . FrameConstructionID == MachineOutlinerThunk ) { +MachineInstr * Call = & * -- MBB . instr_end ( ) ; +bool isThumb = Subtarget . isThumb ( ) ; +unsigned FuncOp = isThumb ? 2 : 0 ; +unsigned Opc = Call -> getOperand ( FuncOp ) . isReg ( ) ? isThumb ? RISCV :: tTAILJMPr : RISCV :: TAILJMPr : isThumb ? Subtarget . isTargetMachO ( ) ? RISCV :: tTAILJMPd : RISCV :: tTAILJMPdND : RISCV :: TAILJMPd ; +MachineInstrBuilder MIB = BuildMI ( MBB , MBB . end ( ) , DebugLoc ( ) , get ( Opc ) ) . add ( Call -> getOperand ( FuncOp ) ) ; +if ( isThumb ) { +if ( ! Call -> getOperand ( FuncOp ) . isReg ( ) ) { +MIB . add ( predOps ( RISCVCC :: AL ) ) ; +} +} +Call -> eraseFromParent ( ) ; +} +if ( llvm :: any_of ( MBB . instrs ( ) , IsNonTailCall ) ) { +MachineBasicBlock :: iterator It = MBB . begin ( ) ; +MachineBasicBlock :: iterator Et = MBB . end ( ) ; +if ( OF . FrameConstructionID == MachineOutlinerTailCall ) { +Et = std :: prev ( MBB . end ( ) ) ; +} +if ( OF . FrameConstructionID == MachineOutlinerThunk ) { +Et = std :: prev ( MBB . end ( ) ) ; +} +if ( ! MBB . isLiveIn ( RISCV :: LR ) ) { +MBB . addLiveIn ( RISCV :: LR ) ; +} +saveLROnStack ( MBB , It ) ; +emitCFIForLRSaveOnStack ( MBB , It ) ; +fixupPostOutline ( MBB ) ; +restoreLRFromStack ( MBB , Et ) ; +emitCFIForLRRestoreFromStack ( MBB , Et ) ; +} +if ( OF . FrameConstructionID == MachineOutlinerTailCall ) { +return ; +} +return ; +if ( OF . FrameConstructionID != MachineOutlinerDefault ) { +if ( OF . Candidates [ 0 ] . CallConstructionID != MachineOutlinerDefault ) { +return ; +} +} +fixupPostOutline ( MBB ) ; +MachineInstr * retq = BuildMI ( MF , DebugLoc ( ) , get ( RISCV :: RET64 ) ) ; +MBB . insert ( MBB . end ( ) , retq ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/copyPhysReg.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/copyPhysReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ed05f46166492481d130ce758653a8c26c464b3a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/copyPhysReg.cpp @@ -0,0 +1,31 @@ +void RISCVInstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , MCRegister DstReg , MCRegister SrcReg , bool KillSrc ) const { +if ( RISCV :: GPRRegClass . contains ( DstReg , SrcReg ) ) { +BuildMI ( MBB , MBBI , DL , get ( RISCV::ADDI ) , DstReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addReg ( RISCV :: R0 ) ; +return ; +} +if ( RISCV :: FPR16RegClass . contains ( DestReg , SrcReg ) ) { +BuildMI ( MBB , MBBI , DL , get ( RISCV :: FSGNJ_H ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; +return ; +} +if ( RISCV :: FPR32RegClass . contains ( DestReg , SrcReg ) ) { +BuildMI ( MBB , MBBI , DL , get ( RISCV :: FSGNJ_S ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; +return ; +} +if ( RISCV :: FPR64RegClass . contains ( DestReg , SrcReg ) ) { +BuildMI ( MBB , MBBI , DL , get ( RISCV :: FSGNJ_D ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; +return ; +} +if ( RISCV :: VRRegClass . contains ( DestReg , SrcReg ) ) { +BuildMI ( MBB , MBBI , DL , get ( RISCV :: PseudoVMV1R_V ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; +return ; +} +if ( RISCV :: VRM2RegClass . contains ( DestReg , SrcReg ) ) { +BuildMI ( MBB , MBBI , DL , get ( RISCV :: PseudoVMV2R_V ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; +return ; +} +if ( RISCV :: VRM4RegClass . contains ( DestReg , SrcReg ) ) { +BuildMI ( MBB , MBBI , DL , get ( RISCV :: PseudoVMV4R_V ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; +return ; +} +llvm_unreachable ( "Impossible reg-to-reg copy" ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/decomposeMachineOperandsTargetFlags.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/decomposeMachineOperandsTargetFlags.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5a62b94b90c324c21e98f368bc88a22456ff95aa --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/decomposeMachineOperandsTargetFlags.cpp @@ -0,0 +1,4 @@ +std :: pair < unsigned , unsigned > RISCVInstrInfo :: decomposeMachineOperandsTargetFlags ( unsigned TF ) const { +const unsigned Mask = RISCVII :: MO_DIRECT_FLAG_MASK ; +return std :: make_pair ( TF & Mask , TF & ~ Mask ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/getBranchDestBlock.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/getBranchDestBlock.cpp new file mode 100644 index 0000000000000000000000000000000000000000..52fa4119c4ff21d2bf1dd37a46d5304c08485741 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/getBranchDestBlock.cpp @@ -0,0 +1,4 @@ +MachineBasicBlock * RISCVInstrInfo :: getBranchDestBlock ( const MachineInstr & MI ) const { +assert ( MI . getDesc ( ) . isBranch ( ) && "Unexpected opcode!" ) ; +return MI . getOperand ( MI . getNumExplicitOperands ( ) - 1 ) . getMBB ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/getInstSizeInBytes.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/getInstSizeInBytes.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4605e5bb04f011a86c3a2db5f58d2e2ba2960791 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/getInstSizeInBytes.cpp @@ -0,0 +1,35 @@ +unsigned RISCVInstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { +const MachineBasicBlock & MBB = * MI . getParent ( ) ; +const MachineFunction * MF = MBB . getParent ( ) ; +const MCAsmInfo * MAI = MF -> getTarget ( ) . getMCAsmInfo ( ) ; +unsigned Opcode = MI . getOpcode ( ) ; +if ( Opcode == TargetOpcode :: INLINEASM ) { +const MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ; +const char * AsmStr = MI -> getOperand ( 0 ) . getSymbolName ( ) ; +return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ; +return 0 ; +} +return MI -> getDesc ( ) . getSize ( ) ; +if ( Opcode == TargetOpcode :: EH_LABEL ) { +return 0 ; +} +if ( Opcode == TargetOpcode :: IMPLICIT_DEF ) { +return 0 ; +} +if ( Opcode == TargetOpcode :: KILL ) { +return 0 ; +} +if ( Opcode == RISCV :: PseudoCALLReg ) { +return 16 ; +} +if ( Opcode == TargetOpcode :: INLINEASM_BR ) { +return 12 ; +} +if ( Opcode == RISCV :: PseudoCALL ) { +return 12 ; +} +if ( Opcode == RISCV :: PseudoJump ) { +return 12 ; +} +return MI . getDesc ( ) . getSize ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/getMemOperandWithOffsetWidth.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/getMemOperandWithOffsetWidth.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ce7277eb921adf2cda96474ad413f110ae55bf33 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/getMemOperandWithOffsetWidth.cpp @@ -0,0 +1,21 @@ +bool RISCVInstrInfo :: getMemOperandWithOffsetWidth ( const MachineInstr & LdSt , const MachineOperand * & BaseReg , int64_t & Offset , unsigned & Width , const TargetRegisterInfo * TRI ) const { +if ( ! LdSt . mayLoadOrStore ( ) ) { +return false ; +} +if ( LdSt . getNumExplicitOperands ( ) != 3 ) { +return false ; +} +if ( ! LdSt . getOperand ( 2 ) . isImm ( ) ) { +return false ; +} +if ( ! LdSt . getOperand ( 1 ) . isReg ( ) ) { +return false ; +} +if ( ! LdSt . hasOneMemOperand ( ) ) { +return false ; +} +Width = ( * LdSt . memoperands_begin ( ) ) -> getSize ( ) ; +Offset = LdSt . getOperand ( 2 ) . getImm ( ) ; +BaseReg = & LdSt . getOperand ( 1 ) ; +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/getOutliningCandidateInfo.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/getOutliningCandidateInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..67de08b8c60bcc6cef6309c4457f8f40b20f5878 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/getOutliningCandidateInfo.cpp @@ -0,0 +1,23 @@ +outliner :: OutlinedFunction RISCVInstrInfo :: getOutliningCandidateInfo ( std :: vector < outliner :: Candidate > & RepeatedSequenceLocs ) const { +unsigned CFICount = 0 ; +MachineBasicBlock :: iterator MBBI = RepeatedSequenceLocs [ 0 ] . front ( ) ; +for ( unsigned Loc = RepeatedSequenceLocs [ 0 ] . getStartIdx ( ) ; Loc < RepeatedSequenceLocs [ 0 ] . getEndIdx ( ) + 1 ; Loc ++ ) { +if ( MBBI -> isCFIInstruction ( ) ) { +MBBI = MBBI + 1 ; +for ( outliner :: Candidate & C : RepeatedSequenceLocs ) { +std :: vector < MCCFIInstruction > CFIInstructions = C . getMF ( ) -> getFrameInstructions ( ) ; +if ( CFICount > 0 ) { +if ( CFICount != CFIInstructions . size ( ) ) { +return outliner :: OutlinedFunction ( ) ; +if ( RepeatedSequenceLocs [ 0 ] . back ( ) -> isTerminator ( ) ) { +for ( outliner :: Candidate & C : RepeatedSequenceLocs ) { +C . setCallInfo ( MachineOutlinerTailCall , 1 ) ; +} +return outliner :: OutlinedFunction ( RepeatedSequenceLocs , SequenceSize , 0 , MachineOutlinerTailCall ) ; +if ( CFICount > 0 ) { +return outliner :: OutlinedFunction ( ) ; +for ( outliner :: Candidate & C : RepeatedSequenceLocs ) { +C . setCallInfo ( MachineOutlinerDefault , 1 ) ; +} +return outliner :: OutlinedFunction ( RepeatedSequenceLocs , SequenceSize , 1 , MachineOutlinerDefault ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/getOutliningType.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/getOutliningType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fa3a813e2c39b0f4dfdc53db180b873adf8c8792 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/getOutliningType.cpp @@ -0,0 +1,68 @@ +outliner :: InstrType RISCVInstrInfo :: getOutliningType ( MachineBasicBlock :: iterator & MBBI , unsigned Flags ) const { +achineInstr & MI = * MBBI ; +MachineBasicBlock * MBB = MI . getParent ( ) ; +const TargetRegisterInfo * TRI = MBB -> getParent ( ) -> getSubtarget ( ) . getRegisterInfo ( ) ; +if ( MI . isDebugValue ( ) ) { +return MachineOutlinerInstrType :: Invisible ; +} +if ( MI . isIndirectDebugValue ( ) ) { +return MachineOutlinerInstrType :: Invisible ; +} +if ( isTailCall ( MI ) ) { +return MachineOutlinerInstrType :: Legal ; +} +if ( MI . isTerminator ( ) ) { +if ( MI . getParent ( ) -> succ_empty ( ) ) { +return MachineOutlinerInstrType :: Legal ; +} +return MachineOutlinerInstrType :: Illegal ; +} +if ( MI . isReturn ( ) ) { +if ( MI . getParent ( ) -> succ_empty ( ) ) { +return MachineOutlinerInstrType :: Legal ; +} +return MachineOutlinerInstrType :: Illegal ; +} +if ( MI . modifiesRegister ( OpcodeRSP , & RI ) ) { +return MachineOutlinerInstrType :: Illegal ; +} +if ( MI . readsRegister ( OpcodeRSP , & RI ) ) { +return MachineOutlinerInstrType :: Illegal ; +} +if ( MI . getDesc ( ) . hasImplicitUseOfPhysReg ( OpcodeRSP ) ) { +return MachineOutlinerInstrType :: Illegal ; +} +if ( MI . getDesc ( ) . hasImplicitDefOfPhysReg ( OpcodeRSP ) ) { +return MachineOutlinerInstrType :: Illegal ; +} +if ( MI . readsRegister ( OpcodeRIP , & RI ) ) { +return MachineOutlinerInstrType :: Illegal ; +} +if ( MI . getDesc ( ) . hasImplicitUseOfPhysReg ( OpcodeRIP ) ) { +return MachineOutlinerInstrType :: Illegal ; +} +if ( MI . getDesc ( ) . hasImplicitDefOfPhysReg ( OpcodeRIP ) ) { +return MachineOutlinerInstrType :: Illegal ; +} +if ( MI . isPosition ( ) ) { +return MachineOutlinerInstrType :: Illegal ; +} +for ( const MachineOperand & MOP : MI . operands ( ) ) { +if ( MOP . isCPI ( ) ) { +return MachineOutlinerInstrType :: Illegal ; +} +if ( MOP . isJTI ( ) ) { +return MachineOutlinerInstrType :: Illegal ; +} +if ( MOP . isCFIIndex ( ) ) { +return MachineOutlinerInstrType :: Illegal ; +} +if ( MOP . isFI ( ) ) { +return MachineOutlinerInstrType :: Illegal ; +} +if ( MOP . isTargetIndex ( ) ) { +return MachineOutlinerInstrType :: Illegal ; +} +} +return MachineOutlinerInstrType :: Legal ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/getSerializableDirectMachineOperandTargetFlags.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/getSerializableDirectMachineOperandTargetFlags.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7ffb62665814ba3b1e0b8a0bc598bfddf8c8efc6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/getSerializableDirectMachineOperandTargetFlags.cpp @@ -0,0 +1,5 @@ +ArrayRef < std :: pair < unsigned , const char * >> RISCVInstrInfo :: getSerializableDirectMachineOperandTargetFlags ( ) const { +using namespace RISCVII ; +static const std :: pair < unsigned , const char * > TargetFlags [ ] = { { MO_CALL , "riscv-call" } , { MO_PLT , "riscv-call" } , { MO_LP , "riscv-plt" } , { MO_LO , "riscv-lo" } , { MO_HI , "riscv-hi" } , { MO_PCREL_LO , "riscv-pcrel-lo" } , { MO_PCREL_HI , "riscv-pcrel-hi" } , { MO_GOT_HI , "riscv-got-hi" } , { MO_TPREL_LO , "riscv-tls-got-hi" } , { MO_TLS_GD_HI , "riscv-tls-gd-hi" } , { MO_TLS_GD_HI , "riscv-tls-gd-hi" } , { MO_TPREL_ADD , "riscv-tprel-add" } , { MO_TLS_GOT_HI , "riscv-tls-got-hi" } , { MO +return makeArrayRef ( TargetFlags ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/insertBranch.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/insertBranch.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f3f7b5e24f54f233372031ea20daf9bd6d72282f --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/insertBranch.cpp @@ -0,0 +1,27 @@ +unsigned RISCVInstrInfo :: insertBranch ( MachineBasicBlock & MBB , MachineBasicBlock * TBB , MachineBasicBlock * FBB , ArrayRef < MachineOperand > Cond , const DebugLoc & DL , int * BytesAdded ) const { +if ( BytesAdded ) { +* BytesAdded = 0 ; +} +assert ( TBB && "insertBranch must not be told to insert a fallthrough" ) ; +assert ( ( Cond . size ( ) == 3 || Cond . size ( ) == 0 ) && "RISCV branch conditions have two components!" ) ; +if ( Cond . empty ( ) ) { +MachineInstr & MI = * BuildMI ( & MBB , DL , get ( RISCV :: PseudoBR ) ) . addMBB ( TBB ) ; +if ( BytesAdded ) { +* BytesAdded = * BytesAdded + getInstSizeInBytes ( MI ) ; +} +return 1 ; +} +unsigned Opc = Cond [ 0 ] . getImm ( ) ; +MachineInstr & CondMI = * BuildMI ( & MBB , DL , get ( Opc ) ) . add ( Cond [ 1 ] ) . add ( Cond [ 2 ] ) . addMBB ( TBB ) ; +if ( BytesAdded ) { +* BytesAdded = * BytesAdded + getInstSizeInBytes ( CondMI ) ; +} +if ( ! FBB ) { +return 1 ; +} +MachineInstr & MI = * BuildMI ( & MBB , DL , get ( RISCV :: PseudoBR ) ) . addMBB ( FBB ) ; +if ( BytesAdded ) { +* BytesAdded = * BytesAdded + getInstSizeInBytes ( MI ) ; +} +return 2 ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/insertIndirectBranch.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/insertIndirectBranch.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e66a6d10bc6090a0cc7aaf16fd3070b3bc961a30 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/insertIndirectBranch.cpp @@ -0,0 +1,23 @@ +unsigned RISCVInstrInfo :: insertIndirectBranch ( MachineBasicBlock & MBB , MachineBasicBlock & DestBB , const DebugLoc & DL , int64_t BrOffset , RegScavenger * RS ) const { +assert ( RS && "RegScavenger required for long branching" ) ; +assert ( MBB . empty ( ) && "new block should be inserted for expanding unconditional branch" ) ; +assert ( MBB . pred_size ( ) == 1 ) ; +MachineFunction * MF = MBB . getParent ( ) ; +MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; +unsigned PCReg = MRI . createVirtualRegister ( & RISCV :: SReg_64RegClass ) ; +Register ScratchReg = MRI . createVirtualRegister ( & RISCV :: GPRRCRegClass ) ; +auto I = MBB . end ( ) ; +MachineInstr * GetPC = BuildMI ( MBB , I , DL , get ( RISCV :: S_GETPC_B64 ) , PCReg ) ; +if ( BrOffset >= 0 ) { +BuildMI ( MBB , I , DL , get ( RISCV :: PseudoJump ) ) . addReg ( PCReg , RegState :: Define , RISCV :: sub0 ) . addReg ( PCReg , 0 , RISCV :: sub0 ) . addMBB ( & DestBB , RISCV :: TF_LONG_BRANCH_BACKWARD ) ; +MachineInstr * MI = BuildMI ( MBB , I , DL , get ( RISCV :: JMP ) ) . addReg ( ScratchReg ) ; +RS -> enterBasicBlockEnd ( MBB ) ; +unsigned Scav = RS -> scavengeRegisterBackwards ( RISCV :: SReg_64RegClass , MachineBasicBlock :: iterator ( GetPC ) , false , 0 ) ; +MRI . replaceRegWith ( PCReg , Scav ) ; +unsigned Scav = RS -> scavengeRegisterBackwards ( RISCV :: GPRRCRegClass , MI -> getIterator ( ) , false , 0 ) ; +assert ( Scav != RISCV :: NoRegister && "No register is scavenged!" ) ; +MRI . replaceRegWith ( ScratchReg , Scav ) ; +MRI . clearVirtRegs ( ) ; +RS -> setRegUsed ( Scav ) ; +return 20 ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/insertOutlinedCall.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/insertOutlinedCall.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5a37b95ab1c5e6a9663338aa5d5609853b390c55 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/insertOutlinedCall.cpp @@ -0,0 +1,6 @@ +MachineBasicBlock :: iterator RISCVInstrInfo :: insertOutlinedCall ( Module & M , MachineBasicBlock & MBB , MachineBasicBlock :: iterator & It , MachineFunction & MF , outliner :: Candidate & C ) const { +It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( RISCV :: JMP_1 ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; +return It ; +It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( RISCV :: CALL64pcrel32 ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; +return It ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/isAsCheapAsAMove.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/isAsCheapAsAMove.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e933e02560d15a148e849a60ff0a666a7b34e09a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/isAsCheapAsAMove.cpp @@ -0,0 +1,19 @@ +bool RISCVInstrInfo :: isAsCheapAsAMove ( const MachineInstr & MI ) const { +const unsigned Opcode = MI . getOpcode ( ) ; +if ( Opcode == RISCV :: FSGNJ_D ) { +return ( MI . getOperand ( 1 ) . isReg ( ) && MI . getOperand ( 1 ) . getReg ( ) == RISCV :: ZERO ) ; +} +if ( Opcode == RISCV :: FSGNJ_S ) { +return ( MI . getOperand ( 1 ) . isReg ( ) && MI . getOperand ( 1 ) . getReg ( ) == RISCV :: ZERO ) ; +} +if ( Opcode == RISCV :: ADDI ) { +return ( MI . getOperand ( 1 ) . isReg ( ) && MI . getOperand ( 1 ) . getReg ( ) == RISCV :: ZERO ) ; +} +if ( Opcode == RISCV :: ORI ) { +return ( MI . getOperand ( 1 ) . isReg ( ) && MI . getOperand ( 1 ) . getReg ( ) == RISCV :: ZERO ) ; +} +if ( Opcode == RISCV :: XORI ) { +return ( MI . getOperand ( 1 ) . isReg ( ) && MI . getOperand ( 1 ) . getReg ( ) == RISCV :: ZERO ) ; +} +return MI . isAsCheapAsAMove ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/isBranchOffsetInRange.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/isBranchOffsetInRange.cpp new file mode 100644 index 0000000000000000000000000000000000000000..34e8ce3ca26c449684b6b2a2b7bf80cc3b944e21 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/isBranchOffsetInRange.cpp @@ -0,0 +1,30 @@ +bool RISCVInstrInfo :: isBranchOffsetInRange ( unsigned BranchOpc , int64_t BrOffset ) const { +if ( BranchOpc == RISCV :: BEQ ) { +return isIntN ( 13 , BrOffset ) ; +} +if ( BranchOpc == RISCV :: BNE ) { +return isIntN ( 13 , BrOffset ) ; +} +if ( BranchOpc == RISCV :: BLT ) { +return isIntN ( 13 , BrOffset ) ; +} +if ( BranchOpc == RISCV :: BGE ) { +return isIntN ( 13 , BrOffset ) ; +} +if ( BranchOpc == RISCV :: BLTU ) { +return isIntN ( 13 , BrOffset ) ; +} +if ( BranchOpc == RISCV :: BGEU ) { +return isIntN ( 13 , BrOffset ) ; +} +if ( BranchOpc == RISCV :: JAL ) { +return isIntN ( 21 , BrOffset ) ; +} +if ( BranchOpc == RISCV :: PseudoBR ) { +return isIntN ( 21 , BrOffset ) ; +} +if ( BranchOpc == RISCV :: PseudoJump ) { +return isIntN ( 32 , SignExtend64 ( BrOffset + 0x800 , STI . getZLen ( ) ) ) ; +} +llvm_unreachable ( "Unexpected opcode!" ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/isCopyInstrImpl.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/isCopyInstrImpl.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e1fbfa9c588b921f4012b1ef276bd484d2528f8a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/isCopyInstrImpl.cpp @@ -0,0 +1,25 @@ +Optional < DestSourcePair > RISCVInstrInfo :: isCopyInstrImpl ( const MachineInstr & MI ) const { +if ( MI . isMoveReg ( ) ) { +return DestSourcePair { MI . getOperand ( 0 ) , MI . getOperand ( 1 ) } ; +} +if ( MI . getOpcode ( ) == RISCV :: ADDI ) { +if ( MI . getOperand ( 2 ) . getImm ( ) == 0x0 ) { +return DestSourcePair { MI . getOperand ( 0 ) , MI . getOperand ( 1 ) } ; +} +} +if ( MI . getOpcode ( ) == RISCV::FSGNJ_D ) { +if ( MI . getOperand ( 1 ) . getReg ( ) == RISCV :: WZR ) { +if ( MI . getOperand ( 3 ) . getImm ( ) == 0x0 ) { +return DestSourcePair { MI . getOperand ( 0 ) , MI . getOperand ( 2 ) } ; +} +} +} +if ( MI . getOpcode ( ) == RISCV::FSGNJ_S ) { +if ( MI . getOperand ( 1 ) . getReg ( ) == RISCV :: XZR ) { +if ( MI . getOperand ( 3 ) . getImm ( ) == 0x0 ) { +return DestSourcePair { MI . getOperand ( 0 ) , MI . getOperand ( 2 ) } ; +} +} +} +return None ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/isFunctionSafeToOutlineFrom.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/isFunctionSafeToOutlineFrom.cpp new file mode 100644 index 0000000000000000000000000000000000000000..50780de21fe11cc2afb37299befcc62fbaaaebe3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/isFunctionSafeToOutlineFrom.cpp @@ -0,0 +1,12 @@ +bool RISCVInstrInfo :: isFunctionSafeToOutlineFrom ( MachineFunction & MF , bool OutlineFromLinkOnceODRs ) const { +const Function & F = MF . getFunction ( ) ; +if ( ! OutlineFromLinkOnceODRs ) { +if ( F . hasLinkOnceODRLinkage ( ) ) { +return false ; +} +} +if ( F . hasSection ( ) ) { +return false ; +} +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/isLoadFromStackSlot.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/isLoadFromStackSlot.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cbeb1ee9a6c9be525daa8f32ec64a9979d3d0e62 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/isLoadFromStackSlot.cpp @@ -0,0 +1,103 @@ +unsigned RISCVInstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { +if ( MI . getOpcode ( ) == RISCV::LB ) { +if ( MI . getOperand ( 1 ) . isFI ( ) ) { +if ( MI . getOperand ( 2 ) . isImm ( ) ) { +if ( MI . getOperand ( 2 ) . getImm ( ) == 0 ) { +FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; +return MI . getOperand ( 0 ) . getReg ( ) ; +} +} +} +} +if ( MI . getOpcode ( ) == RISCV :: LBU ) { +if ( MI . getOperand ( 1 ) . isFI ( ) ) { +if ( MI . getOperand ( 2 ) . isImm ( ) ) { +if ( MI . getOperand ( 2 ) . getImm ( ) == 0 ) { +FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; +return MI . getOperand ( 0 ) . getReg ( ) ; +} +} +} +} +if ( MI . getOpcode ( ) == RISCV :: LH ) { +if ( MI . getOperand ( 1 ) . isFI ( ) ) { +if ( MI . getOperand ( 2 ) . isImm ( ) ) { +if ( MI . getOperand ( 2 ) . getImm ( ) == 0 ) { +FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; +return MI . getOperand ( 0 ) . getReg ( ) ; +} +} +} +} +if ( MI . getOpcode ( ) == RISCV :: LHU ) { +if ( MI . getOperand ( 1 ) . isFI ( ) ) { +if ( MI . getOperand ( 2 ) . isImm ( ) ) { +if ( MI . getOperand ( 2 ) . getImm ( ) == 0 ) { +FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; +return MI . getOperand ( 0 ) . getReg ( ) ; +} +} +} +} +if ( MI . getOpcode ( ) == RISCV::FLH ) { +if ( MI . getOperand ( 1 ) . isFI ( ) ) { +if ( MI . getOperand ( 2 ) . isImm ( ) ) { +if ( MI . getOperand ( 2 ) . getImm ( ) == 0 ) { +FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; +return MI . getOperand ( 0 ) . getReg ( ) ; +} +} +} +} +if ( MI . getOpcode ( ) == RISCV :: LW ) { +if ( MI . getOperand ( 1 ) . isFI ( ) ) { +if ( MI . getOperand ( 2 ) . isImm ( ) ) { +if ( MI . getOperand ( 2 ) . getImm ( ) == 0 ) { +FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; +return MI . getOperand ( 0 ) . getReg ( ) ; +} +} +} +} +if ( MI . getOpcode ( ) == RISCV::FLW ) { +if ( MI . getOperand ( 1 ) . isFI ( ) ) { +if ( MI . getOperand ( 2 ) . isImm ( ) ) { +if ( MI . getOperand ( 2 ) . getImm ( ) == 0 ) { +FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; +return MI . getOperand ( 0 ) . getReg ( ) ; +} +} +} +} +if ( MI . getOpcode ( ) == RISCV :: LWU ) { +if ( MI . getOperand ( 1 ) . isFI ( ) ) { +if ( MI . getOperand ( 2 ) . isImm ( ) ) { +if ( MI . getOperand ( 2 ) . getImm ( ) == 0 ) { +FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; +return MI . getOperand ( 0 ) . getReg ( ) ; +} +} +} +} +if ( MI . getOpcode ( ) == RISCV :: LD ) { +if ( MI . getOperand ( 1 ) . isFI ( ) ) { +if ( MI . getOperand ( 2 ) . isImm ( ) ) { +if ( MI . getOperand ( 2 ) . getImm ( ) == 0 ) { +FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; +return MI . getOperand ( 0 ) . getReg ( ) ; +} +} +} +} +if ( MI . getOpcode ( ) == RISCV :: FLD ) { +if ( MI . getOperand ( 1 ) . isFI ( ) ) { +if ( MI . getOperand ( 2 ) . isImm ( ) ) { +if ( MI . getOperand ( 2 ) . getImm ( ) == 0 ) { +FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; +return MI . getOperand ( 0 ) . getReg ( ) ; +} +} +} +} +return 0 ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/isMBBSafeToOutlineFrom.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/isMBBSafeToOutlineFrom.cpp new file mode 100644 index 0000000000000000000000000000000000000000..aee339a3722b4eb2050feb4b0939229071c5ac5e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/isMBBSafeToOutlineFrom.cpp @@ -0,0 +1,3 @@ +bool RISCVInstrInfo :: isMBBSafeToOutlineFrom ( MachineBasicBlock & MBB , unsigned & Flags ) const { +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/isStoreToStackSlot.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/isStoreToStackSlot.cpp new file mode 100644 index 0000000000000000000000000000000000000000..700d97a2b4e59d8f5044a6e8f3f48863429bae75 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/isStoreToStackSlot.cpp @@ -0,0 +1,73 @@ +unsigned RISCVInstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { +if ( MI . getOpcode ( ) == RISCV :: SB ) { +if ( MI . getOperand ( 1 ) . isFI ( ) ) { +if ( MI . getOperand ( 2 ) . isImm ( ) ) { +if ( MI . getOperand ( 2 ) . getImm ( ) == 0 ) { +FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; +return MI . getOperand ( 0 ) . getReg ( ) ; +} +} +} +} +if ( MI . getOpcode ( ) == RISCV :: SH ) { +if ( MI . getOperand ( 1 ) . isFI ( ) ) { +if ( MI . getOperand ( 2 ) . isImm ( ) ) { +if ( MI . getOperand ( 2 ) . getImm ( ) == 0 ) { +FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; +return MI . getOperand ( 0 ) . getReg ( ) ; +} +} +} +} +if ( MI . getOpcode ( ) == RISCV :: SW ) { +if ( MI . getOperand ( 1 ) . isFI ( ) ) { +if ( MI . getOperand ( 2 ) . isImm ( ) ) { +if ( MI . getOperand ( 2 ) . getImm ( ) == 0 ) { +FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; +return MI . getOperand ( 0 ) . getReg ( ) ; +} +} +} +} +if ( MI . getOpcode ( ) == RISCV :: FSH ) { +if ( MI . getOperand ( 1 ) . isFI ( ) ) { +if ( MI . getOperand ( 2 ) . isImm ( ) ) { +if ( MI . getOperand ( 2 ) . getImm ( ) == 0 ) { +FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; +return MI . getOperand ( 0 ) . getReg ( ) ; +} +} +} +} +if ( MI . getOpcode ( ) == RISCV :: FSW ) { +if ( MI . getOperand ( 1 ) . isFI ( ) ) { +if ( MI . getOperand ( 2 ) . isImm ( ) ) { +if ( MI . getOperand ( 2 ) . getImm ( ) == 0 ) { +FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; +return MI . getOperand ( 0 ) . getReg ( ) ; +} +} +} +} +if ( MI . getOpcode ( ) == RISCV :: SD ) { +if ( MI . getOperand ( 1 ) . isFI ( ) ) { +if ( MI . getOperand ( 2 ) . isImm ( ) ) { +if ( MI . getOperand ( 2 ) . getImm ( ) == 0 ) { +FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; +return MI . getOperand ( 0 ) . getReg ( ) ; +} +} +} +} +if ( MI . getOpcode ( ) == RISCV :: FSD ) { +if ( MI . getOperand ( 1 ) . isFI ( ) ) { +if ( MI . getOperand ( 2 ) . isImm ( ) ) { +if ( MI . getOperand ( 2 ) . getImm ( ) == 0 ) { +FrameIndex = MI . getOperand ( 1 ) . getIndex ( ) ; +return MI . getOperand ( 0 ) . getReg ( ) ; +} +} +} +} +return 0 ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/loadRegFromStackSlot.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/loadRegFromStackSlot.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a5c1cda1a6a4d49914f65fafcd5b80f033045e6c --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/loadRegFromStackSlot.cpp @@ -0,0 +1,31 @@ +void RISCVInstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , Register DstReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { +DebugLoc DL ; +if ( I != MBB . end ( ) ) { +DL = I -> getDebugLoc ( ) ; +} +MachineFunction * MF = MBB . getParent ( ) ; +const MachineFrameInfo & MFI = MF -> getFrameInfo ( ) ; +MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlign ( FI ) ) ; +unsigned Opcode ; +if ( RISCV :: GPRRegClass . hasSubClassEq ( RC ) ) { +Opcode = TRI -> getRegSizeInBits ( RISCV :: GPRRegClass ) == 32 ? RISCV :: LW : RISCV :: LD ; +BuildMI ( MBB , I , DL , get ( Opcode ) , DstReg ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ; +return ; +} +if ( RISCV :: FPR16RegClass . hasSubClassEq ( RC ) ) { +Opcode = RISCV::FLH ; +BuildMI ( MBB , I , DL , get ( Opcode ) , DstReg ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ; +return ; +} +if ( RISCV :: FPR32RegClass . hasSubClassEq ( RC ) ) { +Opcode = RISCV::FLW ; +BuildMI ( MBB , I , DL , get ( Opcode ) , DstReg ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ; +return ; +} +if ( RISCV :: FPR64RegClass . hasSubClassEq ( RC ) ) { +Opcode = RISCV :: FLD ; +BuildMI ( MBB , I , DL , get ( Opcode ) , DstReg ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ; +return ; +} +llvm_unreachable ( "Can't load this register from stack slot" ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/movImm.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/movImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..591e98d833c054f89c0a93f005769c4670215455 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/movImm.cpp @@ -0,0 +1,21 @@ +void RISCVInstrInfo :: movImm ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , Register DstReg , uint64_t Val , MachineInstr :: MIFlag Flag ) const { +assert ( ( Seq . size ( ) > 0 ) ? "movImm" : "movImm" ) ) ; +MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; +DstReg = MRI . createVirtualRegister ( & RISCV :: GPRRegClass ) ; +BuildMI ( MBB , MBBI , DL , get ( RISCV :: MOVI32 ) , DstReg ) . addImm ( Val & 0xFFFF ) . setMIFlags ( Flag ) ; +BuildMI ( MBB , MBBI , DL , get ( RISCV :: MOVIH32 ) , DstReg ) . addImm ( ( Val >> 16 ) & 0xFFFF ) . setMIFlags ( Flag ) ; +if ( ! STI . hasE2 ( ) ) { +DstReg = MRI . createVirtualRegister ( & RISCV :: mGPRRegClass ) ; +BuildMI ( MBB , MBBI , DL , get ( RISCV :: MOVI16 ) , DstReg ) . addImm ( Val & 0xFF ) . setMIFlags ( Flag ) ; +return DstReg ; +BuildMI ( MBB , MBBI , DL , get ( RISCV :: MOVI16 ) , DstReg ) . addImm ( ( Val >> 8 ) & 0xFF ) . setMIFlags ( Flag ) ; +if ( ( Val & 0xFF ) != 0 ) { +return DstReg ; +BuildMI ( MBB , MBBI , DL , get ( RISCV :: MOVI16 ) , DstReg ) . addImm ( ( Val >> 16 ) & 0xFF ) . setMIFlags ( Flag ) ; +if ( ( Val & 0xFF ) != 0 ) { +return DstReg ; +BuildMI ( MBB , MBBI , DL , get ( RISCV :: MOVI16 ) , DstReg ) . addImm ( ( Val >> 24 ) & 0xFF ) . setMIFlags ( Flag ) ; +if ( ( Val & 0xFF ) != 0 ) { +return DstReg ; +return DstReg ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/parseCondBranch.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/parseCondBranch.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ee61a6f99c524feca29f0c4363a86c730ce1069a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/parseCondBranch.cpp @@ -0,0 +1,7 @@ +static void parseCondBranch ( MachineInstr & LastInst , MachineBasicBlock * & Target , SmallVectorImpl < MachineOperand > & Cond ) { +assert ( LastInst . getDesc ( ) . isConditionalBranch ( ) && "Unknown conditional branch" ) ; +Target = LastInst . getOperand ( 2 ) . getMBB ( ) ; +Cond . push_back ( MachineOperand :: CreateImm ( LastInst . getOpcode ( ) ) ) ; +Cond . push_back ( LastInst . getOperand ( 0 ) ) ; +Cond . push_back ( LastInst . getOperand ( 1 ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/removeBranch.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/removeBranch.cpp new file mode 100644 index 0000000000000000000000000000000000000000..18629294555cbcbcd233d7c6a91e2214736fd780 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/removeBranch.cpp @@ -0,0 +1,31 @@ +unsigned RISCVInstrInfo :: removeBranch ( MachineBasicBlock & MBB , int * BytesRemoved ) const { +if ( BytesRemoved ) { +* BytesRemoved = 0 ; +} +MachineBasicBlock :: iterator I = MBB . getLastNonDebugInstr ( ) ; +if ( I == MBB . end ( ) ) { +return 0 ; +} +if ( ! I -> getDesc ( ) . isUnconditionalBranch ( ) ) { +if ( ! I -> getDesc ( ) . isConditionalBranch ( ) ) { +return 0 ; +} +} +if ( BytesRemoved ) { +* BytesRemoved = * BytesRemoved + getInstSizeInBytes ( * I ) ; +} +I -> eraseFromParent ( ) ; +I = MBB . end ( ) ; +if ( I == MBB . begin ( ) ) { +return 1 ; +} +I -- ; +if ( ! I -> getDesc ( ) . isConditionalBranch ( ) ) { +return 1 ; +} +if ( BytesRemoved ) { +* BytesRemoved = * BytesRemoved + getInstSizeInBytes ( * I ) ; +} +I -> eraseFromParent ( ) ; +return 2 ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/reverseBranchCondition.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/reverseBranchCondition.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fb697f11f1b2898111a2dc7c49488a2e68c1bb0b --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/reverseBranchCondition.cpp @@ -0,0 +1,29 @@ +bool RISCVInstrInfo :: reverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const { +assert ( ( Cond . size ( ) == 3 ) && "Invalid branch condition!" ) ; +if ( Cond [ 0 ] . getImm ( ) == RISCV :: BEQ ) { +Cond [ 0 ] . setImm ( RISCV :: BNE ) ; +return false ; +} +if ( Cond [ 0 ] . getImm ( ) == RISCV :: BNE ) { +Cond [ 0 ] . setImm ( RISCV :: BEQ ) ; +return false ; +} +if ( Cond [ 0 ] . getImm ( ) == RISCV :: BLT ) { +Cond [ 0 ] . setImm ( RISCV :: BGE ) ; +return false ; +} +if ( Cond [ 0 ] . getImm ( ) == RISCV :: BGE ) { +Cond [ 0 ] . setImm ( RISCV :: BLT ) ; +return false ; +} +if ( Cond [ 0 ] . getImm ( ) == RISCV :: BLTU ) { +Cond [ 0 ] . setImm ( RISCV :: BGEU ) ; +return false ; +} +if ( Cond [ 0 ] . getImm ( ) == RISCV :: BGEU ) { +Cond [ 0 ] . setImm ( RISCV :: BLTU ) ; +return false ; +} +llvm_unreachable ( "Unrecognized conditional branch" ) ; +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/storeRegToStackSlot.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/storeRegToStackSlot.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f65952d8363ffb25778ce56c2fed9ffe82970d1c --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/storeRegToStackSlot.cpp @@ -0,0 +1,32 @@ +void RISCVInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , Register SrcReg , bool IsKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { +DebugLoc DL ; +if ( I != MBB . end ( ) ) { +DL = I -> getDebugLoc ( ) ; +} +MachineFunction & MF = * MBB . getParent ( ) ; +const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; +MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , MFI . getObjectAlign ( FI ) ) ; +MachineFunctionInfo * CFI = MF . getInfo < MachineFunctionInfo > ( ) ; +unsigned Opcode ; +if ( RISCV :: GPRRegClass . hasSubClassEq ( RC ) ) { +Opcode = TRI -> getRegSizeInBits ( RISCV :: GPRRegClass ) == 32 ? RISCV :: SW : RISCV :: SD ; +BuildMI ( MBB , I , DL , get ( Opcode ) ) . addReg ( SrcReg , getKillRegState ( IsKill ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ; +return ; +} +if ( RISCV :: FPR16RegClass . hasSubClassEq ( RC ) ) { +Opcode = RISCV :: FSH ; +BuildMI ( MBB , I , DL , get ( Opcode ) ) . addReg ( SrcReg , getKillRegState ( IsKill ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ; +return ; +} +if ( RISCV :: FPR32RegClass . hasSubClassEq ( RC ) ) { +Opcode = RISCV :: FSW ; +BuildMI ( MBB , I , DL , get ( Opcode ) ) . addReg ( SrcReg , getKillRegState ( IsKill ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ; +return ; +} +if ( RISCV :: FPR64RegClass . hasSubClassEq ( RC ) ) { +Opcode = RISCV :: FSD ; +BuildMI ( MBB , I , DL , get ( Opcode ) ) . addReg ( SrcReg , getKillRegState ( IsKill ) ) . addFrameIndex ( FI ) . addImm ( 0 ) . addMemOperand ( MMO ) ; +return ; +} +llvm_unreachable ( "Can't store this register to stack slot" ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/verifyInstruction.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/verifyInstruction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fcc10dbebee6a317646b16a7267e491c9f33c58c --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/InstrInfo/verifyInstruction.cpp @@ -0,0 +1,26 @@ +bool zmntarzmInstrInfo :: verifyInstruction ( const MachineInstr & MI , StringRef & ErrInfo ) const { +return false ; +return false ; +for ( const MachineOperand & MO : llvm :: drop_begin ( MI . operands ( ) , 2 ) ) { +continue ; +if ( ! MO . isReg ( ) ) { +continue ; +return false ; +return false ; +} +for ( const MachineOperand & MO : llvm :: drop_begin ( MI . operands ( ) , 2 ) ) { +continue ; +if ( ! MO . isReg ( ) ) { +continue ; +return false ; +return false ; +for ( const MachineOperand & MO : llvm :: drop_begin ( MI . operands ( ) , 2 ) ) { +continue ; +if ( ! MO . isReg ( ) ) { +continue ; +return false ; +return false ; +ErrInfo = "Incorrect array index for MVE_VMOV_q_rr" ; +return false ; +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/MachineFunctionInfo/MachineFunctionInfo.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/MachineFunctionInfo/MachineFunctionInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..70c39853ae6a9b6d82505b38a3ae4fe5234aa81f --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/MachineFunctionInfo/MachineFunctionInfo.cpp @@ -0,0 +1,2 @@ +RISCVMachineFunctionInfo ( const MachineFunction & MF ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/MachineFunctionInfo/getLibCallStackSize.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/MachineFunctionInfo/getLibCallStackSize.cpp new file mode 100644 index 0000000000000000000000000000000000000000..dd76ab5ba3323d65a4477bccc65534dc7962a22e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/MachineFunctionInfo/getLibCallStackSize.cpp @@ -0,0 +1,3 @@ +unsigned getLibCallStackSize ( ) const { +return LibCallStackSize ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/MachineFunctionInfo/getMoveF64FrameIndex.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/MachineFunctionInfo/getMoveF64FrameIndex.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1506385c39ba129264d05e3aeef80f525f072626 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/MachineFunctionInfo/getMoveF64FrameIndex.cpp @@ -0,0 +1,3 @@ +int getMoveF64FrameIndex ( MachineFunction & MF ) { +return VarArgsFrameIndex ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/MachineFunctionInfo/getVarArgsFrameIndex.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/MachineFunctionInfo/getVarArgsFrameIndex.cpp new file mode 100644 index 0000000000000000000000000000000000000000..dc86317bf4ffdb2157afe0cc9f496c3f8454b58d --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/MachineFunctionInfo/getVarArgsFrameIndex.cpp @@ -0,0 +1,3 @@ +int getVarArgsFrameIndex ( ) const { +return VarArgsFrameIndex ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/MachineFunctionInfo/getVarArgsSaveSize.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/MachineFunctionInfo/getVarArgsSaveSize.cpp new file mode 100644 index 0000000000000000000000000000000000000000..984c1825c54e81864add7c3ce18abcc8f75abfb1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/MachineFunctionInfo/getVarArgsSaveSize.cpp @@ -0,0 +1,3 @@ +unsigned getVarArgsSaveSize ( ) const { +return VarArgsSaveSize ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/MachineFunctionInfo/setLibCallStackSize.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/MachineFunctionInfo/setLibCallStackSize.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5abdcaac1a49937450075b01349b77aad5cba33e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/MachineFunctionInfo/setLibCallStackSize.cpp @@ -0,0 +1,3 @@ +void setLibCallStackSize ( unsigned Size ) { +LibCallStackSize = Size ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/MachineFunctionInfo/setVarArgsFrameIndex.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/MachineFunctionInfo/setVarArgsFrameIndex.cpp new file mode 100644 index 0000000000000000000000000000000000000000..66ec61362627179d015c191feff7e83b189ae468 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/MachineFunctionInfo/setVarArgsFrameIndex.cpp @@ -0,0 +1,3 @@ +void setVarArgsFrameIndex ( int Index ) { +VarArgsFrameIndex = Index ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/MachineFunctionInfo/setVarArgsSaveSize.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/MachineFunctionInfo/setVarArgsSaveSize.cpp new file mode 100644 index 0000000000000000000000000000000000000000..65028936eed662052285bdc438536ed2db9e126d --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/MachineFunctionInfo/setVarArgsSaveSize.cpp @@ -0,0 +1,3 @@ +void setVarArgsSaveSize ( int Size ) { +VarArgsSaveSize = Size ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/MachineFunctionInfo/useSaveRestoreLibCalls.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/MachineFunctionInfo/useSaveRestoreLibCalls.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7bf2af87f47f7fccd53a9869143ed96dbc2a7d2b --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/MachineFunctionInfo/useSaveRestoreLibCalls.cpp @@ -0,0 +1,4 @@ +bool useSaveRestoreLibCalls ( const MachineFunction & MF ) const { +return UseLongCalls ; +return UseRetpolineIndirectCalls ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/Subtarget.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/Subtarget.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1d1dc79fe0dc01959ea6ab571f4edab9a7abef5a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/Subtarget.cpp @@ -0,0 +1,7 @@ +RISCVSubtarget :: RISCVSubtarget ( const Triple & TT , StringRef CPU , StringRef TuneCPU , StringRef FS , StringRef ABIName , const TargetMachine & TM ) : RISCVGenSubtargetInfo ( TT , CPU , TuneCPU , FS ) , UserReservedRegister ( RISCV :: NUM_TARGET_REGS ) , FrameLowering ( initializeSubtargetDependencies ( TT , CPU , TuneCPU , FS , ABIName ) ) , InstrInfo ( * this ) , RegInfo ( getHwMode ( ) ) , TLInfo ( TM , * this ) { +CallLoweringInfo . reset ( new RISCVCallLowering ( * getTargetLowering ( ) ) ) ; +Legalizer . reset ( new RISCVLegalizerInfo ( * this ) ) ; +auto * RBI = new RISCVRegisterBankInfo ( * getRegisterInfo ( ) ) ; +RegBankInfo . reset ( RBI ) ; +InstSelector . reset ( createRISCVInstructionSelector ( * static_cast < const RISCVTargetMachine * > ( & TM ) , * this , * RBI ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/anchor.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/anchor.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ae9ce16457c37f0e5c1b75e7cc393283c26a9ae0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/anchor.cpp @@ -0,0 +1,2 @@ +void RISCVSubtarget :: anchor ( ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/enableLinkerRelax.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/enableLinkerRelax.cpp new file mode 100644 index 0000000000000000000000000000000000000000..70a8d18a0f4959c58f34faee220172dc3452205e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/enableLinkerRelax.cpp @@ -0,0 +1,3 @@ +bool enableLinkerRelax ( ) const { +return EnableLinkerRelax ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/enableMachineScheduler.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/enableMachineScheduler.cpp new file mode 100644 index 0000000000000000000000000000000000000000..51af53569dda58106126bb9616c9b0e228522932 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/enableMachineScheduler.cpp @@ -0,0 +1,3 @@ +bool enableMachineScheduler ( ) const override { +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/enableRVCHintInstrs.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/enableRVCHintInstrs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..88c4f2c9ef4b883b0ff22bc15363b377cf8c1e96 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/enableRVCHintInstrs.cpp @@ -0,0 +1,3 @@ +bool enableRVCHintInstrs ( ) const { +return EnableRVCHintInstrs ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/enableSaveRestore.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/enableSaveRestore.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5523878c63a3fec5d0d102911de8a2fb644c25da --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/enableSaveRestore.cpp @@ -0,0 +1,3 @@ +bool enableSaveRestore ( ) const { +return EnableSaveRestore ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/getCallLowering.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/getCallLowering.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5b724fe04d39457a9b6eaa0d79fc3d7f02691138 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/getCallLowering.cpp @@ -0,0 +1,3 @@ +const CallLowering * RISCVSubtarget :: getCallLowering ( ) const { +return CallLoweringInfo . get ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/getFrameLowering.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/getFrameLowering.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cab0e842d362aace40f7d61a1f90b345034c9dd6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/getFrameLowering.cpp @@ -0,0 +1,3 @@ +const RISCVFrameLowering * getFrameLowering ( ) const override { +return & FrameLowering ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/getInstrInfo.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/getInstrInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e91b785b00b51558d5668733ac8afefab832dd92 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/getInstrInfo.cpp @@ -0,0 +1,3 @@ +const RISCVInstrInfo * getInstrInfo ( ) const override { +return & InstrInfo ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/getInstructionSelector.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/getInstructionSelector.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f460305e71338c6528f589ba22d7eeb84cd2ee14 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/getInstructionSelector.cpp @@ -0,0 +1,3 @@ +InstructionSelector * RISCVSubtarget :: getInstructionSelector ( ) const { +return InstSelector . get ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/getLegalizerInfo.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/getLegalizerInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..66ce70fff116dbbaee5054316733b2a198e87e05 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/getLegalizerInfo.cpp @@ -0,0 +1,3 @@ +const LegalizerInfo * RISCVSubtarget :: getLegalizerInfo ( ) const { +return Legalizer . get ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/getRegBankInfo.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/getRegBankInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e8e02b3531d675c9106059eb4807c192cd7017f3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/getRegBankInfo.cpp @@ -0,0 +1,3 @@ +const RegisterBankInfo * RISCVSubtarget :: getRegBankInfo ( ) const { +return RegBankInfo . get ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/getRegisterInfo.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/getRegisterInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3e2c75dd6ddf98c738cd915f765c59fa13f026a7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/getRegisterInfo.cpp @@ -0,0 +1,3 @@ +const RISCVRegisterInfo * getRegisterInfo ( ) const override { +return & RegInfo ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/getSelectionDAGInfo.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/getSelectionDAGInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..83c31a22c7236b0e11e56881d95a0f360d309ab2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/getSelectionDAGInfo.cpp @@ -0,0 +1,3 @@ +const SelectionDAGTargetInfo * getSelectionDAGInfo ( ) const override { +return & TSInfo ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/getTargetABI.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/getTargetABI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..16ae15472632097d3075aff0875c283e8990edc2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/getTargetABI.cpp @@ -0,0 +1,3 @@ +RISCVABI :: ABI getTargetABI ( ) const { +return TargetABI ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/getTargetLowering.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/getTargetLowering.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6af3413c26e7aa716d9ba96ddcf154389b8210eb --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/getTargetLowering.cpp @@ -0,0 +1,3 @@ +const RISCVTargetLowering * getTargetLowering ( ) const override { +return & TLInfo ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/getXLen.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/getXLen.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a6e3bde5f9b6b485447a8bce8a0091f1a0340c94 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/getXLen.cpp @@ -0,0 +1,3 @@ +unsigned getXLen ( ) const { +return XLen ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/getXLenVT.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/getXLenVT.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6d4f4a2499c523fc8594ec194a1d030d0dad1e92 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/getXLenVT.cpp @@ -0,0 +1,3 @@ +MVT getXLenVT ( ) const { +return XLenVT ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtA.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtA.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f2e661f51d43203396d1e225cbc8278eace7b4df --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtA.cpp @@ -0,0 +1,3 @@ +bool hasStdExtA ( ) const { +return HasStdExtA ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtB.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtB.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ce5e9fb80677325f4d15acae0c205541ba3f0a86 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtB.cpp @@ -0,0 +1,3 @@ +bool hasStdExtB ( ) const { +return HasStdExtB ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtC.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6afa2dea62227c40e77b1d809e422cc828634c13 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtC.cpp @@ -0,0 +1,3 @@ +bool hasStdExtC ( ) const { +return HasStdExtC ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtD.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtD.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e777c791d438d140046213757adc02b4ad72943b --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtD.cpp @@ -0,0 +1,3 @@ +bool hasStdExtD ( ) const { +return HasStdExtD ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtF.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtF.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6604f1a6d0b9bd50209386800e4b95b032d791ad --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtF.cpp @@ -0,0 +1,3 @@ +bool hasStdExtF ( ) const { +return HasStdExtF ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtM.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtM.cpp new file mode 100644 index 0000000000000000000000000000000000000000..21ed588c30fce8b938d0734277487193cd84c592 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtM.cpp @@ -0,0 +1,3 @@ +bool hasStdExtM ( ) const { +return HasStdExtM ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtV.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtV.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a73c0d3f407b71b90ca2ba8539d287063ccf6f3e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtV.cpp @@ -0,0 +1,3 @@ +bool hasStdExtV ( ) const { +return HasStdExtV ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtZba.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtZba.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b5a9225770f654fcd514c1da5ab6e925fd96804a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtZba.cpp @@ -0,0 +1,3 @@ +bool hasStdExtZba ( ) const { +return HasStdExtZba ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtZbb.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtZbb.cpp new file mode 100644 index 0000000000000000000000000000000000000000..28a3678f936fee5641edcb5075f2abf9fdfe7335 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtZbb.cpp @@ -0,0 +1,3 @@ +bool hasStdExtZbb ( ) const { +return HasStdExtZbb ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtZbc.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtZbc.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5d024a63261d9fb21603c6b130f22b925d50b933 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtZbc.cpp @@ -0,0 +1,3 @@ +bool hasStdExtZbc ( ) const { +return HasStdExtZbc ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtZbe.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtZbe.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ebad6fe9769e6edcc5bc81d781126d04df82694e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtZbe.cpp @@ -0,0 +1,3 @@ +bool hasStdExtZbe ( ) const { +return HasStdExtZbe ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtZbf.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtZbf.cpp new file mode 100644 index 0000000000000000000000000000000000000000..dbc5d68d500b25105271947368d1a77de4d31b40 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtZbf.cpp @@ -0,0 +1,3 @@ +bool hasStdExtZbf ( ) const { +return HasStdExtZbf ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtZbm.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtZbm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..efaa1d7da6ca38abca75b0da6b48aced6cd1696d --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtZbm.cpp @@ -0,0 +1,3 @@ +bool hasStdExtZbm ( ) const { +return HasStdExtZbm ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtZbp.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtZbp.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b5396d1bb87eb10eee1d64fb4d8315b808898b02 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtZbp.cpp @@ -0,0 +1,3 @@ +bool hasStdExtZbp ( ) const { +return HasStdExtZbp ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtZbproposedc.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtZbproposedc.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7c12b3ad22e06eb29ebda5ab08e3dddda0e9f320 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtZbproposedc.cpp @@ -0,0 +1,3 @@ +bool hasStdExtZbproposedc ( ) const { +return HasStdExtZbproposedc ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtZbr.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtZbr.cpp new file mode 100644 index 0000000000000000000000000000000000000000..65e76b1debf4bcd1997f16adfa040bb88faf6617 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtZbr.cpp @@ -0,0 +1,3 @@ +bool hasStdExtZbr ( ) const { +return HasStdExtZbr ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtZbs.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtZbs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..98ab2c86bcc3ffd2a227696236b28d03e20fe466 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtZbs.cpp @@ -0,0 +1,3 @@ +bool hasStdExtZbs ( ) const { +return HasStdExtZbs ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtZbt.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtZbt.cpp new file mode 100644 index 0000000000000000000000000000000000000000..10ad75e226f3fc188a0b8134df8a8284a1ed10b3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtZbt.cpp @@ -0,0 +1,3 @@ +bool hasStdExtZbt ( ) const { +return HasStdExtZbt ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtZfh.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtZfh.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a754f5f42aa332191c6959d7b43fe6e6657d2d1a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtZfh.cpp @@ -0,0 +1,3 @@ +bool hasStdExtZfh ( ) const { +return HasStdExtZfh ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtZvamo.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtZvamo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fe9c8a54a357a1f5f9686c085c4f28943257ae0f --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtZvamo.cpp @@ -0,0 +1,3 @@ +bool hasStdExtZvamo ( ) const { +return HasStdExtZvamo ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtZvlsseg.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtZvlsseg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9740e1eb0dce59980aa951a67fca0ad5a27ad003 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/hasStdExtZvlsseg.cpp @@ -0,0 +1,3 @@ +bool hasStdExtZvlsseg ( ) const { +return HasStdExtZvlsseg ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/initializeSubtargetDependencies.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/initializeSubtargetDependencies.cpp new file mode 100644 index 0000000000000000000000000000000000000000..52096e26ec43e76faa0f8612d36d5b26cafd8b03 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/initializeSubtargetDependencies.cpp @@ -0,0 +1,17 @@ +RISCVSubtarget & RISCVSubtarget :: initializeSubtargetDependencies ( const Triple & TT , StringRef CPU , StringRef TuneCPU , StringRef FS , StringRef ABIName ) { +std :: string CPUName = CPU ; +bool Is64Bit = TT . isArch64Bit ( ) ; +if ( CPU . empty ( ) ) { +CPUName = Is64Bit ? "generic-la64" : "generic-la32" ; +} +if ( TuneCPU . empty ( ) ) { +TuneCPU = CPUName ; +} +ParseSubtargetFeatures ( CPUName , TuneCPU , FS ) ; +if ( Is64Bit ) { +GRLenVT = MVT :: i64 ; +GRLen = 64 ; +} +TargetABI = Is64Bit ? RISCVABI :: ABI_LP64D : RISCVABI :: ABI_ILP32D ; +return * this ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/is64Bit.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/is64Bit.cpp new file mode 100644 index 0000000000000000000000000000000000000000..44cd572e277dadcf0f1bd6ba82d9e10c25d718c0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/is64Bit.cpp @@ -0,0 +1,3 @@ +bool is64Bit ( ) const { +return HasRV64 ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/isRV32E.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/isRV32E.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d3e892bba6b18878664cc247c83bf009dbe49640 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/isRV32E.cpp @@ -0,0 +1,3 @@ +bool isRV32E ( ) const { +return IsRV32E ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/isRegisterReservedByUser.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/isRegisterReservedByUser.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ca947ceba26408c2cc34b668c9e12caf8e1257ec --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/Subtarget/isRegisterReservedByUser.cpp @@ -0,0 +1,4 @@ +bool isRegisterReservedByUser ( Register R ) const { +assert ( R < RISCV :: NUM_TARGET_REGS && "Register out of range" ) ; +return UserReservedRegister [ R ] ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetInfo/LLVMInitializeTargetInfo.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetInfo/LLVMInitializeTargetInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..618aa0427a33252d781d2a6b1906e7ce894b0983 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetInfo/LLVMInitializeTargetInfo.cpp @@ -0,0 +1,4 @@ +extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTargetInfo ( ) { +RegisterTarget < Triple :: RISCV32 > X ( getTheRISCV32Target ( ) , "RISCV32" , "32-bit RISCV" , "RISCV" ) ; +RegisterTarget < Triple :: RISCV64 > Y ( getTheRISCV64Target ( ) , "RISCV64" , "64-bit RISCV" , "RISCV" ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetInfo/getThe32Target.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetInfo/getThe32Target.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e0b143de30a76b7ff8951b7a8d8065917c6adfc1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetInfo/getThe32Target.cpp @@ -0,0 +1,4 @@ +Target & llvm :: getTheRISCV32Target ( ) { +static Target TheRISCV32Target ; +return TheRISCV32Target ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetInfo/getThe64Target.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetInfo/getThe64Target.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0856efac4c09662f6774e0e56866af6b8a844333 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetInfo/getThe64Target.cpp @@ -0,0 +1,4 @@ +Target & llvm :: getTheRISCV64Target ( ) { +static Target TheRISCV64Target ; +return TheRISCV64Target ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/LLVMInitializeTarget.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/LLVMInitializeTarget.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e95bb4c3064161277deab9f3e90e87296fa6ca9e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/LLVMInitializeTarget.cpp @@ -0,0 +1,9 @@ +extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget ( ) { +RegisterTargetMachine < RISCVTargetMachine > X ( getTheRISCV32Target ( ) ) ; +RegisterTargetMachine < RISCVTargetMachine > Y ( getTheRISCV64Target ( ) ) ; +auto * PR = PassRegistry :: getPassRegistry ( ) ; +initializeGlobalISel ( * PR ) ; +initializeRISCVMergeBaseOffsetOptPass ( * PR ) ; +initializeRISCVExpandPseudoPass ( * PR ) ; +initializeRISCVCleanupVSETVLIPass ( * PR ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/PassConfig.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/PassConfig.cpp new file mode 100644 index 0000000000000000000000000000000000000000..19f2c233a79154ad7f7b65f1256d72be0007a3d4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/PassConfig.cpp @@ -0,0 +1,2 @@ +RISCVPassConfig ( RISCVTargetMachine & TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/TargetMachine.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/TargetMachine.cpp new file mode 100644 index 0000000000000000000000000000000000000000..171e06f32aad02b237c050cd5847656b6f03797b --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/TargetMachine.cpp @@ -0,0 +1,3 @@ +RISCVTargetMachine :: RISCVTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( RM ) , CM , OL ) , TLOF ( make_unique < TargetObjectFile > ( ) ) , Subtarget ( TT , CPU , FS , * this ) { +initAsmInfo ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/addGlobalInstructionSelect.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/addGlobalInstructionSelect.cpp new file mode 100644 index 0000000000000000000000000000000000000000..353655a92f0f021ab072e54d72010f8302cc812d --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/addGlobalInstructionSelect.cpp @@ -0,0 +1,4 @@ +bool RISCVPassConfig :: addGlobalInstructionSelect ( ) { +addPass ( new InstructionSelect ( ) ) ; +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/addIRPasses.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/addIRPasses.cpp new file mode 100644 index 0000000000000000000000000000000000000000..19276599151c530e533e8cfa32b5d0f942b8cbb1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/addIRPasses.cpp @@ -0,0 +1,4 @@ +void RISCVPassConfig :: addIRPasses ( ) { +addPass ( createAtomicExpandPass ( ) ) ; +TargetPassConfig :: addIRPasses ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/addIRTranslator.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/addIRTranslator.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c1ac57ab76b0b7d5f39e287396a97ffee452cacf --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/addIRTranslator.cpp @@ -0,0 +1,4 @@ +bool RISCVPassConfig :: addIRTranslator ( ) { +addPass ( new IRTranslator ( getOptLevel ( ) ) ) ; +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/addInstSelector.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/addInstSelector.cpp new file mode 100644 index 0000000000000000000000000000000000000000..303887b02a296efd51b0577c992419d56c225955 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/addInstSelector.cpp @@ -0,0 +1,4 @@ +bool RISCVPassConfig :: addInstSelector ( ) { +addPass ( createRISCVISelDag ( getRISCVTargetMachine ( ) ) ) ; +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/addLegalizeMachineIR.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/addLegalizeMachineIR.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9a1e3283d2610ae06b80e64efe851634256d148e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/addLegalizeMachineIR.cpp @@ -0,0 +1,4 @@ +bool RISCVPassConfig :: addLegalizeMachineIR ( ) { +addPass ( new Legalizer ( ) ) ; +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/addPreEmitPass.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/addPreEmitPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..314a137ab7254cb9575f2b864fce780aa1a538d1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/addPreEmitPass.cpp @@ -0,0 +1,3 @@ +void RISCVPassConfig :: addPreEmitPass ( ) { +addPass ( & BranchRelaxationPassID ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/addPreEmitPass2.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/addPreEmitPass2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3c2ec9402966140278db397cc4f52eab3c301f7c --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/addPreEmitPass2.cpp @@ -0,0 +1,4 @@ +void RISCVPassConfig :: addPreEmitPass2 ( ) { +addPass ( createRISCVExpandPseudoPass ( ) ) ; +addPass ( createRISCVExpandAtomicPseudoPass ( ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/addPreRegAlloc.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/addPreRegAlloc.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5467de3e71a9fe2875ab8f3fb29e0fd19b7a1464 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/addPreRegAlloc.cpp @@ -0,0 +1,8 @@ +void RISCVPassConfig :: addPreRegAlloc ( ) { +if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { +if ( EnableAdvSIMDScalar ) { +addPass ( createRISCVAdvSIMDScalar ( ) ) ; +addPass ( & PeepholeOptimizerID ) ; +} +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/addPreSched2.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/addPreSched2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..df752bad6b2de30338c3f6677be99f56c5b15231 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/addPreSched2.cpp @@ -0,0 +1,2 @@ +void RISCVPassConfig :: addPreSched2 ( ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/addRegBankSelect.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/addRegBankSelect.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3bb266fa7802a19d61c2e84c0b1ac88f900f0885 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/addRegBankSelect.cpp @@ -0,0 +1,4 @@ +bool RISCVPassConfig :: addRegBankSelect ( ) { +addPass ( new RegBankSelect ( ) ) ; +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/computeDataLayout.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/computeDataLayout.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d0eefacff3c52b1d5790efd8b231f6d18aceb1da --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/computeDataLayout.cpp @@ -0,0 +1,7 @@ +static StringRef computeDataLayout ( const Triple & TT ) { +if ( TT . isArch64Bit ( ) ) { +return "e-m:e-p:64:64-i64:64-i128:128-n64-S128" ; +} +assert ( TT . isArch32Bit ( ) && "only RV32 and RV64 is currently supported" ) ; +return "e-m:e-p:32:32-i64:64-n32-S128" ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/createPassConfig.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/createPassConfig.cpp new file mode 100644 index 0000000000000000000000000000000000000000..08f40fcd409dc7dec9ab3c07ec1b291650a08662 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/createPassConfig.cpp @@ -0,0 +1,3 @@ +TargetPassConfig * TargetMachine :: createPassConfig ( PassManagerBase & PM ) { +return new RISCVPassConfig ( * this , PM ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/getEffectiveRelocModel.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/getEffectiveRelocModel.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9424f05ebb3cbbd3ce9eff02ee928b811b620b67 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/getEffectiveRelocModel.cpp @@ -0,0 +1,6 @@ +static Reloc :: Model getEffectiveRelocModel ( const Triple & TT , Optional < Reloc :: Model > RM ) { +if ( ! RM . hasValue ( ) ) { +return Reloc :: Static ; +} +return * RM ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/getObjFileLowering.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/getObjFileLowering.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6174dfa05f7cbe9092209bade1a1dee2435f5e04 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/getObjFileLowering.cpp @@ -0,0 +1,3 @@ +TargetLoweringObjectFile * getObjFileLowering ( ) const override { +return TLOF . get ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/getSubtargetImpl.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/getSubtargetImpl.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1f3f3513181cba683f5df3eed7740c8daa221d98 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/getSubtargetImpl.cpp @@ -0,0 +1,25 @@ +const RISCVSubtarget * RISCVTargetMachine :: getSubtargetImpl ( const Function & F ) const { +Attribute TuneAttr = F . getFnAttribute ( "tune-cpu" ) ; +Attribute CPUAttr = F . getFnAttribute ( "target-cpu" ) ; +Attribute FSAttr = F . getFnAttribute ( "target-features" ) ; +std :: string CPU = CPUAttr . isValid ( ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; +std :: string TuneCPU = TuneAttr . isValid ( ) ? TuneAttr . getValueAsString ( ) . str ( ) : CPU ; +std :: string FS = FSAttr . isValid ( ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; +std :: string Key = CPU + TuneCPU + FS ; +auto & I = SubtargetMap [ Key ] ; +if ( ! I ) { +resetTargetOptions ( F ) ; +auto ABIName = Options . MCOptions . getABIName ( ) ; +if ( const MDString * ModuleTargetABI = dyn_cast_or_null < MDString > ( F . getParent ( ) -> getModuleFlag ( "target-abi" ) ) ) { +auto TargetABI = RISCVABI :: getTargetABI ( ABIName ) ; +if ( TargetABI != RISCVABI :: ABI_Unknown ) { +if ( ModuleTargetABI -> getString ( ) != ABIName ) { +report_fatal_error ( "-target-abi option != target-abi module flag" ) ; +} +} +ABIName = ModuleTargetABI -> getString ( ) ; +} +I = std :: make_unique < RISCVSubtarget > ( TargetTriple , CPU , TuneCPU , FS , ABIName , * this ) ; +} +return I . get ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/getTargetMachine.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/getTargetMachine.cpp new file mode 100644 index 0000000000000000000000000000000000000000..70d47ae062510f217f897f9d94ef669b3d66c440 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/getTargetMachine.cpp @@ -0,0 +1,3 @@ +RISCVTargetMachine & getRISCVTargetMachine ( ) const { +return getTM < RISCVTargetMachine > ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/getTargetTransformInfo.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/getTargetTransformInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..97d5f53e2a0e4039c94c9a8224370ec4a252e7fb --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/getTargetTransformInfo.cpp @@ -0,0 +1,3 @@ +TargetTransformInfo RISCVTargetMachine :: getTargetTransformInfo ( const Function & F ) { +return TargetTransformInfo ( RISCVTTIImpl ( this , F ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/isNoopAddrSpaceCast.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/isNoopAddrSpaceCast.cpp new file mode 100644 index 0000000000000000000000000000000000000000..de0e5cb35e217bc4dee6d2413e0cf1cd9b95754b --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetMachine/isNoopAddrSpaceCast.cpp @@ -0,0 +1,3 @@ +bool RISCVTargetMachine :: isNoopAddrSpaceCast ( unsigned SrcAS , unsigned DestAS ) const { +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetObjectFile/Initialize.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetObjectFile/Initialize.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ff01f0f5399237b5479a240d7c884e27b577ffbc --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetObjectFile/Initialize.cpp @@ -0,0 +1,5 @@ +void RISCVELFTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { +TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; +SmallDataSection = getContext ( ) . getELFSection ( ".sdata" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; +SmallBSSSection = getContext ( ) . getELFSection ( ".sbss" , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetObjectFile/SelectSectionForGlobal.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetObjectFile/SelectSectionForGlobal.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b915b5a7d5155af85458fe1635c7196af72165b1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetObjectFile/SelectSectionForGlobal.cpp @@ -0,0 +1,13 @@ +MCSection * RISCVELFTargetObjectFile :: SelectSectionForGlobal ( const GlobalObject * GO , SectionKind Kind , const TargetMachine & TM ) const { +if ( Kind . isBSS ( ) ) { +if ( isGlobalInSmallSection ( GO , TM ) ) { +return SmallBSSSection ; +} +} +if ( Kind . isData ( ) ) { +if ( isGlobalInSmallSection ( GO , TM ) ) { +return SmallDataSection ; +} +} +return TargetLoweringObjectFileELF :: SelectSectionForGlobal ( GO , Kind , TM ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetObjectFile/getModuleMetadata.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetObjectFile/getModuleMetadata.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b930b868e176fea4894b9479d9af416ad84ef11d --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetObjectFile/getModuleMetadata.cpp @@ -0,0 +1,23 @@ +void RISCVELFTargetObjectFile :: getModuleMetadata ( Module & M ) { +constexpr StringLiteral DeadKeys [ ] = { ValVerKey } ; +StringSet < > DeadKeySet ; +for ( auto & Key : DeadKeys ) { +if ( M . getModuleFlag ( Key ) ) { +DeadKeySet . insert ( Key ) ; +} +} +if ( DeadKeySet . empty ( ) ) { +return ; +} +SmallVector < Module :: ModuleFlagEntry , 8 > ModuleFlags ; +M . getModuleFlagsMetadata ( ModuleFlags ) ; +NamedMDNode * MDFlags = M . getModuleFlagsMetadata ( ) ; +MDFlags -> eraseFromParent ( ) ; +for ( auto & Flag : ModuleFlags ) { +StringRef Key = Flag . Key -> getString ( ) ; +if ( DeadKeySet . contains ( Key ) ) { +continue ; +} +M . addModuleFlag ( Flag . Behavior , Key , Flag . Val ) ; +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetObjectFile/getSectionForConstant.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetObjectFile/getSectionForConstant.cpp new file mode 100644 index 0000000000000000000000000000000000000000..098d9633fc11fa0fb7a8fb317d96e0fffe91e49f --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetObjectFile/getSectionForConstant.cpp @@ -0,0 +1,6 @@ +MCSection * RISCVELFTargetObjectFile :: getSectionForConstant ( const DataLayout & DL , SectionKind Kind , const Constant * C , Align & Alignment ) const { +if ( isConstantInSmallSection ( DL , C ) ) { +return SmallDataSection ; +} +return TargetLoweringObjectFileELF :: getSectionForConstant ( DL , Kind , C , Alignment ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetObjectFile/isConstantInSmallSection.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetObjectFile/isConstantInSmallSection.cpp new file mode 100644 index 0000000000000000000000000000000000000000..616abcc31c793acd3e701de06d8760013e5bb39a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetObjectFile/isConstantInSmallSection.cpp @@ -0,0 +1,3 @@ +bool RISCVELFTargetObjectFile :: isConstantInSmallSection ( const DataLayout & DL , const Constant * CN ) const { +return isInSmallSection ( DL . getTypeAllocSize ( CN -> getType ( ) ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetObjectFile/isGlobalInSmallSection.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetObjectFile/isGlobalInSmallSection.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1fe9bad88652380aaf1cd8a4cfaee42af8aebe44 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetObjectFile/isGlobalInSmallSection.cpp @@ -0,0 +1,12 @@ +bool RISCVTargetObjectFile :: isGlobalInSmallSection ( const GlobalObject * GO , const TargetMachine & TM ) const { +if ( GO == nullptr ) { +return TM . getCodeModel ( ) == CodeModel :: Small ; +} +if ( GO -> isDeclaration ( ) ) { +return isGlobalInSmallSectionImpl ( GO , TM ) ; +} +if ( GO -> hasAvailableExternallyLinkage ( ) ) { +return isGlobalInSmallSectionImpl ( GO , TM ) ; +} +return isGlobalInSmallSection ( GO , TM , getKindForGlobal ( GO , TM ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetObjectFile/isInSmallSection.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetObjectFile/isInSmallSection.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8d00011ff590686113391d6a4b9441bd616af062 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetObjectFile/isInSmallSection.cpp @@ -0,0 +1,3 @@ +bool RISCVELFTargetObjectFile :: isInSmallSection ( uint64_t Size ) const { +return Size > 0 && Size <= SSThreshold ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetTransformInfo/TTIImpl.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetTransformInfo/TTIImpl.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a01c6a46240853e15d7ba703e55c35182bbbfb7d --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetTransformInfo/TTIImpl.cpp @@ -0,0 +1,2 @@ +explicit RISCVTTIImpl ( const RISCVTargetMachine * TM , const Function & F ) : BaseT ( TM , F . getParent ( ) -> getDataLayout ( ) ) , ST ( TM -> getSubtargetImpl ( F ) ) , TLI ( ST -> getTargetLowering ( ) ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetTransformInfo/getIntImmCost.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetTransformInfo/getIntImmCost.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e82db21c6ffaa82704311393c6eaa6fc14bfe3de --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetTransformInfo/getIntImmCost.cpp @@ -0,0 +1,6 @@ +int RISCVTTIImpl :: getIntImmCost ( const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind ) { +if ( Imm == 0 ) { +return TTI :: TCC_Free ; +} +return RISCVMatInt::getIntMatCost(Imm, DL.getTypeSizeInBits(Ty), getST()->is64Bit()) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetTransformInfo/getIntImmCostInst.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetTransformInfo/getIntImmCostInst.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5d182783270a71782eebbe782f7045852edfc68b --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetTransformInfo/getIntImmCostInst.cpp @@ -0,0 +1,71 @@ +int RISCVTTIImpl :: getIntImmCostInst ( unsigned Opcode , unsigned Idx , const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind , Instruction * Inst ) { +assert ( Ty -> isIntegerTy ( ) && "getIntImmCost can only estimate cost of materialising integers" ) ; +if ( Opcode == Instruction :: GetElementPtr ) { +return TTI :: TCC_Free ; +} +if ( Opcode == Instruction :: Add ) { +if ( Imm . getBitWidth ( ) <= 64 ) { +if ( Ty -> getPrimitiveSizeInBits ( ) == 8 ) { +return TTI :: TCC_Free ; +} +} +} +if ( Opcode == Instruction :: And ) { +if ( Imm . getBitWidth ( ) <= 64 ) { +if ( isInt < 32 > ( Imm . getSExtValue ( ) ) ) { +return TTI :: TCC_Free ; +} +} +return getIntImmCost ( Imm , Ty , CostKind ) ; +} +if ( Opcode == Instruction :: Or ) { +if ( Imm . getBitWidth ( ) <= 64 ) { +if ( isInt < 32 > ( Imm . getSExtValue ( ) ) ) { +return TTI :: TCC_Free ; +} +} +return getIntImmCost ( Imm , Ty , CostKind ) ; +} +if ( Opcode == Instruction :: Xor ) { +if ( Imm . getBitWidth ( ) <= 64 ) { +if ( isInt < 32 > ( Imm . getSExtValue ( ) ) ) { +return TTI :: TCC_Free ; +} +} +return getIntImmCost ( Imm , Ty , CostKind ) ; +} +if ( Opcode == Instruction :: Mul ) { +if ( Imm . getBitWidth ( ) <= 64 ) { +if ( isInt < 32 > ( Imm . getSExtValue ( ) ) ) { +return TTI :: TCC_Free ; +} +} +return getIntImmCost ( Imm , Ty , CostKind ) ; +} +if ( Opcode == Instruction :: Sub ) { +if ( Imm . getBitWidth ( ) <= 64 ) { +if ( isInt < 32 > ( Imm . getSExtValue ( ) ) ) { +return TTI :: TCC_Free ; +} +} +return getIntImmCost ( Imm , Ty , CostKind ) ; +} +if ( Opcode == Instruction :: Shl ) { +if ( Imm . getBitWidth ( ) <= 64 ) { +if ( isInt < 32 > ( Imm . getSExtValue ( ) ) ) { +return TTI :: TCC_Free ; +} +} +} +if ( Opcode == Instruction :: LShr ) { +if ( Imm . getBitWidth ( ) <= 64 ) { +if ( Ty -> getPrimitiveSizeInBits ( ) <= 32 ) { +return TTI :: TCC_Free ; +} +} +} +if ( Opcode == Instruction :: AShr ) { +return TTI :: TCC_Free ; +} +return TTI :: TCC_Free ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetTransformInfo/getIntImmCostIntrin.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetTransformInfo/getIntImmCostIntrin.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3cc4a65705a79d2d6eba01844b8feb1e9d4ad30b --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetTransformInfo/getIntImmCostIntrin.cpp @@ -0,0 +1,3 @@ +int RISCVTTIImpl :: getIntImmCostIntrin ( Intrinsic :: ID IID , unsigned Idx , const APInt & Imm , Type * Ty , TTI :: TargetCostKind CostKind ) { +return TTI :: TCC_Free ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetTransformInfo/getST.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetTransformInfo/getST.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6abade06b10f597112633f2279b6db54c0da03f8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetTransformInfo/getST.cpp @@ -0,0 +1,3 @@ +const RISCVSubtarget * getST ( ) const { +return ST ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetTransformInfo/getTLI.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetTransformInfo/getTLI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3ef0206d9b5838455261d7311790309659b7cd36 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Scheduling/TargetTransformInfo/getTLI.cpp @@ -0,0 +1,3 @@ +const RISCVTargetLowering * getTLI ( ) const { +return TLI ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/CallLowering/CallLowering.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/CallLowering/CallLowering.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f346e95ac7e28b68230370764822c23ee5369d48 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/CallLowering/CallLowering.cpp @@ -0,0 +1,2 @@ +RISCVCallLowering :: RISCVCallLowering ( const RISCVTargetLowering & TLI ) : CallLowering ( & TLI ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/CallLowering/lowerCall.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/CallLowering/lowerCall.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8ee07984b435dc293551c46a5f3448e78645163e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/CallLowering/lowerCall.cpp @@ -0,0 +1,3 @@ +bool RISCVCallLowering :: lowerCall ( MachineIRBuilder & MIRBuilder , CallLoweringInfo & Info ) const { +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/CallLowering/lowerFormalArguments.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/CallLowering/lowerFormalArguments.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e93f77dd2c38215720c6f67c52516f9f45ba3099 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/CallLowering/lowerFormalArguments.cpp @@ -0,0 +1,6 @@ +bool RISCVCallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < ArrayRef < Register >> VRegs , FunctionLoweringInfo & FLI ) const { +if ( F . arg_empty ( ) ) { +return true ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/CallLowering/lowerReturn.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/CallLowering/lowerReturn.cpp new file mode 100644 index 0000000000000000000000000000000000000000..facd562885bb227e1fc2539e22a0e6319329e9bf --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/CallLowering/lowerReturn.cpp @@ -0,0 +1,8 @@ +bool RISCVCallLowering :: lowerReturn ( MachineIRBuilder & MIRBuilder , const Value * Val , ArrayRef < Register > VRegs , FunctionLoweringInfo & FLI ) const { +MachineInstrBuilder Ret = MIRBuilder . buildInstrNoInsert ( RISCV :: PseudoRET ) ; +if ( Val != nullptr ) { +return false ; +} +MIRBuilder . insertInstr ( Ret ) ; +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/FrameLowering/FrameLowering.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/FrameLowering/FrameLowering.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3f7edfbd62872d1f6d4b68ed6eedfed75813d89d --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/FrameLowering/FrameLowering.cpp @@ -0,0 +1,2 @@ +explicit RISCVSubtarget & STI ) : TargetFrameLowering ( StackGrowsDown , 4 , 0 ) , STI ( STI ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/FrameLowering/adjustReg.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/FrameLowering/adjustReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d15b59b577104611e45820ce4efb2affa91c3e5f --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/FrameLowering/adjustReg.cpp @@ -0,0 +1,22 @@ +void RISCVFrameLowering :: adjustReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , Register DestReg , Register SrcReg , int64_t Val , MachineInstr :: MIFlag Flag ) const { +MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; +const RISCVInstrInfo * TII = STI . getInstrInfo ( ) ; +if ( DestReg == SrcReg ) { +if ( Val == 0 ) { +return ; +} +} +if ( DestReg != SrcReg ) { +if ( isInt < 12 > ( Val ) ) { +BuildMI ( MBB , MBBI , DL , TII -> get ( RISCV :: ADDI ) , DestReg ) . addReg ( SrcReg ) . addImm ( Val ) . setMIFlag ( Flag ) ; +} +if ( ! isInt < 12 > ( Val ) ) { +unsigned Opc = RISCV :: ADD ; +bool isSub = Val < 0 ; +if ( isSub ) { +Opc = RISCV :: SUB ; +} +Register ScratchReg = MRI . createVirtualRegister ( & RISCV :: GPRRegClass ) ; +BuildMI ( MBB , MBBI , DL , TII -> get ( Opc ) , DestReg ) . addReg ( SrcReg ) . addReg ( ScratchReg , RegState :: Kill ) . setMIFlag ( Flag ) ; +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/FrameLowering/canUseAsEpilogue.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/FrameLowering/canUseAsEpilogue.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c2553b9a48bb8d93fb83b9e84985f6116f59276c --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/FrameLowering/canUseAsEpilogue.cpp @@ -0,0 +1,4 @@ +bool RISCVFrameLowering :: canUseAsEpilogue ( const MachineBasicBlock & MBB ) const { +return false ; +return SuccMBB -> isReturnBlock ( ) && SuccMBB -> size ( ) == 1 ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/FrameLowering/canUseAsPrologue.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/FrameLowering/canUseAsPrologue.cpp new file mode 100644 index 0000000000000000000000000000000000000000..47608b1eac8249e713e57750860ff5e18c426a0e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/FrameLowering/canUseAsPrologue.cpp @@ -0,0 +1,4 @@ +bool RISCVFrameLowering :: canUseAsPrologue ( const MachineBasicBlock & MBB ) const { +const MachineFunction * MF = MBB . getParent ( ) ; +return !RS.isRegUsed(RISCV::X5) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/FrameLowering/determineCalleeSaves.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/FrameLowering/determineCalleeSaves.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f13e28a98a8f64fdcb3d455afd1a7d1c8ab749b0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/FrameLowering/determineCalleeSaves.cpp @@ -0,0 +1,66 @@ +void RISCVFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { +TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; +RISCVMachineFunctionInfo * CFI = MF . getInfo < RISCVMachineFunctionInfo > ( ) ; +MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; +if ( hasFP ( MF ) ) { +SavedRegs . set ( RISCV :: R8 ) ; +} +if ( hasBP ( MF ) ) { +SavedRegs . set ( RISCV :: R7 ) ; +} +if ( MF . getFunction ( ) . hasFnAttribute ( "interrupt" ) ) { +if ( MFI . hasCalls ( ) ) { +static const MCPhysReg CSRegs [ ] = { RISCV :: R0 , RISCV :: R1 , RISCV :: R2 , RISCV :: R3 , RISCV :: R12 , RISCV :: R13 , 0 } ; +for ( unsigned i = 0 ; CSRegs [ i ] ; ++ i ) { +SavedRegs . set ( CSRegs [ i ] ) ; +} +static const MCPhysReg CSHRegs [ ] = { RISCV :: R18 , RISCV :: R19 , RISCV :: R20 , RISCV :: R21 , RISCV :: R22 , RISCV :: R23 , RISCV :: R24 , RISCV :: R25 , 0 } ; +for ( unsigned i = 0 ; CSHRegs [ i ] ; ++ i ) { +SavedRegs . set ( CSHRegs [ i ] ) ; +} +static const MCPhysReg CSF32Regs [ ] = { RISCV :: F8_32 , RISCV :: F9_32 , RISCV :: F10_32 , RISCV :: F11_32 , RISCV :: F12_32 , RISCV :: F13_32 , RISCV :: F14_32 , RISCV :: F15_32 , 0 } ; +static const MCPhysReg CSF64Regs [ ] = { RISCV :: F8_64 , RISCV :: F9_64 , RISCV :: F10_64 , RISCV :: F11_64 , RISCV :: F12_64 , RISCV :: F13_64 , RISCV :: F14_64 , RISCV :: F15_64 , 0 } ; +const MCPhysReg * FRegs = NULL ; +FRegs = CSF64Regs ; +FRegs = CSF64Regs ; +FRegs = CSF32Regs ; +FRegs = CSF32Regs ; +if ( FRegs != NULL ) { +const MCPhysReg * Regs = MF . getRegInfo ( ) . getCalleeSavedRegs ( ) ; +for ( unsigned i = 0 ; Regs [ i ] ; ++ i ) { +unsigned x = 0 ; +for ( ; FRegs [ x ] ; ++ x ) { +if ( FRegs [ x ] == Regs [ i ] ) { +break ; +} +} +if ( FRegs [ x ] == 0 ) { +SavedRegs . set ( Regs [ i ] ) ; +unsigned x = 0 ; +for ( ; FRegs [ x ] ; ++ x ) { +if ( FRegs [ x ] == Regs [ i ] ) { +break ; +if ( FRegs [ x ] == 0 ) { +SavedRegs . set ( Regs [ i ] ) ; +} +} +CFI -> setLRIsSpilled ( SavedRegs . test ( RISCV :: R15 ) ) ; +unsigned CSStackSize = 0 ; +for ( unsigned Reg : SavedRegs . set_bits ( ) ) { +auto RegSize = TRI -> getRegSizeInBits ( Reg , MRI ) / 8 ; +CFI -> setCalleeSaveAreaSize ( CSStackSize ) ; +uint64_t Limit = estimateRSStackSizeLimit ( MF , STI ) ; +bool BigFrame = ( MFI . estimateStackSize ( MF ) + CSStackSize >= Limit ) ; +if ( BigFrame ) { +const TargetRegisterClass * RC = & RISCV :: GPRRegClass ; +unsigned size = TRI -> getSpillSize ( * RC ) ; +Align align = TRI -> getSpillAlign ( * RC ) ; +if ( CFI -> isCRSpilled ( ) ) { +const TargetRegisterClass * RC = & RISCV :: GPRRegClass ; +unsigned size = TRI -> getSpillSize ( * RC ) ; +Align align = TRI -> getSpillAlign ( * RC ) ; +if ( ! STI . hasE2 ( ) ) { +const TargetRegisterClass * RC = & RISCV :: GPRRegClass ; +unsigned size = TRI -> getSpillSize ( * RC ) ; +Align align = TRI -> getSpillAlign ( * RC ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/FrameLowering/eliminateCallFramePseudoInstr.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/FrameLowering/eliminateCallFramePseudoInstr.cpp new file mode 100644 index 0000000000000000000000000000000000000000..280fcc73f35e1a0a190f7e1185365ce8591e570e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/FrameLowering/eliminateCallFramePseudoInstr.cpp @@ -0,0 +1,15 @@ +MachineBasicBlock :: iterator RISCVFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const { +Register SPReg = RISCV :: X2 ; +DebugLoc DL = MI -> getDebugLoc ( ) ; +if ( ! hasReservedCallFrame ( MF ) ) { +int64_t Amount = MI -> getOperand ( 0 ) . getImm ( ) ; +if ( Amount != 0 ) { +Amount = alignSPAdjust ( Amount ) ; +if ( MI -> getOpcode ( ) == RISCV :: ADJCALLSTACKDOWN ) { +Amount = - Amount ; +} +adjustReg ( MBB , MI , DL , SPReg , SPReg , Amount , MachineInstr :: NoFlags ) ; +} +} +return MBB . erase ( MI ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/FrameLowering/emitEpilogue.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/FrameLowering/emitEpilogue.cpp new file mode 100644 index 0000000000000000000000000000000000000000..409e41620bb1646918f50aeaab3aa9c835245160 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/FrameLowering/emitEpilogue.cpp @@ -0,0 +1,33 @@ +void RISCVFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { +const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; +MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; +RISCVMachineFunctionInfo * CFI = MF . getInfo < RISCVMachineFunctionInfo > ( ) ; +Register FPReg = getFPReg ( STI ) ; +Register SPReg = getSPReg ( STI ) ; +MachineBasicBlock :: iterator MBBI = MBB . end ( ) ; +DebugLoc DL ; +DL = MBBI -> getDebugLoc ( ) ; +if ( ! MBB . empty ( ) ) { +MBBI = MBB . getFirstTerminator ( ) ; +if ( MBBI == MBB . end ( ) ) { +MBBI = MBB . getLastNonDebugInstr ( ) ; +} +if ( ! MBBI -> isTerminator ( ) ) { +MBBI = std :: next ( MBBI ) ; +} +} +const auto & CSI = MFI . getCalleeSavedInfo ( ) ; +auto LastFrameDestroy = MBBI ; +if ( ! CSI . empty ( ) ) { +LastFrameDestroy = std :: prev ( MBBI , CSI . size ( ) ) ; +} +uint64_t StackSize = MFI . getStackSize ( ) ; +uint64_t ActualSize = CFI -> getCalleeSaveAreaSize ( ) + CFI -> getVarArgsSaveSize ( ) ; +if ( hasFP ( MF ) ) { +BuildMI ( MBB , LastFrameDestroy , DL , TII -> get ( TargetOpcode :: COPY ) , SPReg ) . addReg ( FPReg ) . setMIFlag ( MachineInstr :: NoFlags ) ; +} +if ( ! hasFP ( MF ) ) { +adjustReg ( MBB , LastFrameDestroy , DL , SPReg , SPReg , ( StackSize - ActualSize ) , MachineInstr :: FrameDestroy ) ; +} +adjustReg ( MBB , MBBI , DL , SPReg , SPReg , ActualSize , MachineInstr :: FrameDestroy ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/FrameLowering/emitPrologue.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/FrameLowering/emitPrologue.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c1155cd6b4251084dd35d2aa681a718903d1be43 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/FrameLowering/emitPrologue.cpp @@ -0,0 +1,55 @@ +void RISCVFrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { +const RegisterInfo * RI = STI . getRegisterInfo ( ) ; +MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; +MachineFunctionInfo * CFI = MF . getInfo < MachineFunctionInfo > ( ) ; +Register SPReg = getSPReg ( STI ) ; +Register BPReg = getBPReg ( STI ) ; +const RISCVInstrInfo * TII = STI . getInstrInfo ( ) ; +MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; +const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; +const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; +DebugLoc DL ; +if ( MF . getFunction ( ) . hasFnAttribute ( "interrupt" ) ) { +determineFrameLayout ( MF ) ; +uint64_t StackSize = MFI . getStackSize ( ) ; +if ( StackSize == 0 ) { +if ( ! MFI . adjustsStack ( ) ) { +return ; +const auto & CSI = MFI . getCalleeSavedInfo ( ) ; +unsigned spillAreaSize = CFI -> getCalleeSaveAreaSize ( ) ; +uint64_t ActualSize = spillAreaSize + CFI -> getVarArgsSaveSize ( ) ; +adjustReg ( MBB , MBBI , DL , SPReg , SPReg , - ( static_cast < int64_t > ( ActualSize ) ) , MachineInstr :: NoFlags ) ; +unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfaOffset ( nullptr , ActualSize ) ) ; +std :: advance ( MBBI , CSI . size ( ) ) ; +for ( const auto & Entry : CSI ) { +int64_t Offset = MFI . getObjectOffset ( Entry . getFrameIdx ( ) ) ; +unsigned Num = TRI -> getRegSizeInBits ( Reg , MRI ) / 32 ; +for ( unsigned i = 0 ; i < Num ; i ++ ) { +unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , RI -> getDwarfRegNum ( Reg , true ) + i , Offset + i * 4 ) ) ; +BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; +} +if ( hasFP ( MF ) ) { +unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaRegister ( nullptr , RI -> getDwarfRegNum ( FPReg , true ) ) ) ; +adjustReg ( MBB , MBBI , DL , SPReg , SPReg , - ( static_cast < int64_t > ( StackSize - ActualSize ) ) , MachineInstr :: NoFlags ) ; +if ( RI -> hasStackRealignment ( MF ) ) { +Align MaxAlignment = MFI . getMaxAlign ( ) ; +if ( isUInt < 12 > ( ~ ( - ( int ) MaxAlignment . value ( ) ) ) ) { +BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) , SPReg ) . addReg ( SPReg ) . addImm ( ~ ( - ( int ) MaxAlignment . value ( ) ) ) ; +if ( ! STI . hasE2 ( ) ) { +if ( ! STI . hasE2 ( ) ) { +if ( ! isUInt < 12 > ( ~ ( - ( int ) MaxAlignment . value ( ) ) ) ) { +BuildMI ( MBB , MBBI , DL , TII -> get ( RISCV::ANDI ) , SPReg ) . addReg ( VR ) . addImm ( ShiftAmount ) ; +if ( ! STI . hasE2 ( ) ) { +Register VR = MF . getRegInfo ( ) . createVirtualRegister ( & RISCV :: mGPRRegClass ) ; +BuildMI ( MBB , MBBI , DL , TII -> get ( RISCV :: ANDI ) , VR ) . addReg ( SPReg ) ; +BuildMI ( MBB , MBBI , DL , TII -> get ( RISCV::SRLI ) , VR ) . addReg ( VR ) . addImm ( ShiftAmount ) ; +BuildMI ( MBB , MBBI , DL , TII -> get ( RISCV :: SLLI ) , SPReg ) . addReg ( VR ) ; +} +if ( hasBP ( MF ) ) { +BuildMI ( MBB , MBBI , DL , TII -> get ( RISCV::ADDI ) , BPReg ) . addReg ( SPReg ) ; +} +} +if ( ! hasFP ( MF ) ) { +adjustReg ( MBB , MBBI , DL , SPReg , SPReg , - ( static_cast < int64_t > ( StackSize - ActualSize ) ) , MachineInstr :: NoFlags ) ; +unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfaOffset ( nullptr , MFI . getStackSize ( ) ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/FrameLowering/getFrameIndexReference.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/FrameLowering/getFrameIndexReference.cpp new file mode 100644 index 0000000000000000000000000000000000000000..05ecd69cea281a3a52cd6addd92717e8970dfe69 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/FrameLowering/getFrameIndexReference.cpp @@ -0,0 +1,55 @@ +StackOffset RISCVFrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , Register & FrameReg ) const { +const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; +const TargetRegisterInfo * RI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; +const auto * CFI = MF . getInfo < MachineFunctionInfo > ( ) ; +const auto & CSI = MFI . getCalleeSavedInfo ( ) ; +int MinCSFI = 0 ; +int MaxCSFI = - 1 ; +int Offset = MFI . getObjectOffset ( FI ) + MFI . getOffsetAdjustment ( ) ; +if ( CSI . size ( ) ) { +MinCSFI = CSI [ 0 ] . getFrameIdx ( ) ; +MaxCSFI = CSI [ CSI . size ( ) - 1 ] . getFrameIdx ( ) ; +} +if ( FI >= MinCSFI ) { +if ( FI <= MaxCSFI ) { +FrameReg = RISCV :: X2 ; +Offset = Offset + CFI -> getVarArgsSaveSize ( ) + CFI -> getCalleeSaveAreaSize ( ) ; +} +} +if ( RI -> hasStackRealignment ( MF ) ) { +if ( ! MFI . isFixedObjectIndex ( FI ) ) { +FrameReg = RISCV :: X9 ; +Offset = Offset + MFI . getStackSize ( ) ; +} +if ( MFI . isFixedObjectIndex ( FI ) ) { +FrameReg = getFPReg ( STI ) ; +Offset = Offset + CFI -> getVarArgsSaveSize ( ) + CFI -> getCalleeSaveAreaSize ( ) ; +} +if ( FI > MaxCSFI ) { +if ( ! MFI . isFixedObjectIndex ( FI ) ) { +Offset = Offset + MFI . getStackSize ( ) ; +} +if ( MFI . isFixedObjectIndex ( FI ) ) { +FrameReg = getFPReg ( STI ) ; +Offset = Offset + CFI -> getVarArgsSaveSize ( ) + CFI -> getCalleeSaveAreaSize ( ) ; +} +} +} +int64_t FrameOffset = MF . getFrameInfo ( ) . getObjectOffset ( FI ) ; +if ( ! hasFP ( MF ) ) { +return StackOffset :: getFixed ( FrameOffset + MF . getFrameInfo ( ) . getStackSize ( ) ) ; +} +if ( RI -> needsStackRealignment ( MF ) ) { +if ( ! MFI . isFixedObjectIndex ( FI ) ) { +if ( hasBP ( MF ) ) { +FrameReg = RISCV :: X9 ; +} +if ( ! hasBP ( MF ) ) { +FrameReg = RISCV :: X2 ; +} +return StackOffset :: getFixed ( FrameOffset + MF . getFrameInfo ( ) . getStackSize ( ) ) ; +} +} +FrameReg = RI -> getFrameRegister ( MF ) ; +return StackOffset :: getFixed ( Offset ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/FrameLowering/hasBP.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/FrameLowering/hasBP.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8e1216bbbef2f2fac206e348fb534159d264106e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/FrameLowering/hasBP.cpp @@ -0,0 +1,5 @@ +bool RISCVFrameLowering :: hasBP ( const MachineFunction & MF ) const { +const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; +const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ; +return MFI . hasVarSizedObjects ( ) && TRI -> needsStackRealignment ( MF ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/FrameLowering/hasFP.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/FrameLowering/hasFP.cpp new file mode 100644 index 0000000000000000000000000000000000000000..41a9e7884235055e05f9b24a354925d41adafc0d --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/FrameLowering/hasFP.cpp @@ -0,0 +1,5 @@ +bool RISCVFrameLowering :: hasFP ( const MachineFunction & MF ) const { +const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; +const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; +return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || RegInfo -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/FrameLowering/hasReservedCallFrame.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/FrameLowering/hasReservedCallFrame.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6143029916b52f22491218fca66308335693b92a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/FrameLowering/hasReservedCallFrame.cpp @@ -0,0 +1,3 @@ +bool RISCVFrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { +return ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/FrameLowering/processFunctionBeforeFrameFinalized.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/FrameLowering/processFunctionBeforeFrameFinalized.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b2c98e8855fdc66af79a5ce8307c269391f43644 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/FrameLowering/processFunctionBeforeFrameFinalized.cpp @@ -0,0 +1,9 @@ +void RISCVFrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { +const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; +MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; +const TargetRegisterClass * RC = & RISCV :: GPRRegClass ; +if ( ! isInt < 11 > ( MFI . estimateStackSize ( MF ) ) ) { +int RegScavFI = MFI . CreateStackObject ( RegInfo -> getSpillSize ( * RC ) , RegInfo -> getSpillAlign ( * RC ) , false ) ; +RS -> addScavengingFrameIndex ( RegScavFI ) ; +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/FrameLowering/restoreCalleeSavedRegisters.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/FrameLowering/restoreCalleeSavedRegisters.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1fc82d4bdd161a43e98a38f285fdc639ec6983a3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/FrameLowering/restoreCalleeSavedRegisters.cpp @@ -0,0 +1,19 @@ +bool RISCVFrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , MutableArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { +if ( CSI . empty ( ) ) { +return true ; +} +MachineFunction * MF = MBB . getParent ( ) ; +const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ; +DebugLoc DL ; +if ( MI != MBB . end ( ) ) { +if ( ! MI -> isDebugInstr ( ) ) { +DL = MI -> getDebugLoc ( ) ; +} +} +for ( auto & CS : reverse ( CSI ) ) { +Register Reg = CS . getReg ( ) ; +TII . loadRegFromStackSlot ( MBB , MI , Reg , CS . getFrameIdx ( ) , RC , TRI ) ; +assert ( MI != MBB . begin ( ) && "loadRegFromStackSlot didn't insert any code!" ) ; +} +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/FrameLowering/spillCalleeSavedRegisters.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/FrameLowering/spillCalleeSavedRegisters.cpp new file mode 100644 index 0000000000000000000000000000000000000000..27e3c1e57015c82d42d1c8b0da0840f8289a5cb2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/FrameLowering/spillCalleeSavedRegisters.cpp @@ -0,0 +1,30 @@ +bool RISCVFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { +if ( CSI . empty ( ) ) { +return false ; +} +DebugLoc DL ; +unsigned CalleeFrameSize = 0 ; +DebugLoc DL = MBB . findDebugLoc ( MI ) ; +DebugLoc dl ; +if ( MI != MBB . end ( ) ) { +DL = MI -> getDebugLoc ( ) ; +} +MachineFunction * MF = MBB . getParent ( ) ; +const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ; +DebugLoc DL ; +if ( MI != MBB . end ( ) ) { +DL = MI -> getDebugLoc ( ) ; +if ( ! MI -> isDebugInstr ( ) ) { +DL = MI -> getDebugLoc ( ) ; +} +} +for ( unsigned i = CSI . size ( ) ; i != 0 ; -- i ) { +unsigned Reg = CS . getReg ( ) ; +MachineFunction * MF = MBB . getParent ( ) ; +BuildMI ( MBB , MI , DL , TII . get ( RISCV :: PseudoCALL ) ) . addReg ( Reg , getKillRegState ( IsNotLiveIn ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ; +Register Reg = CS . getReg ( ) ; +const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; +TII -> storeRegToStackSlot ( MBB , MBBI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ; +} +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelDAGToDAG/DAGToDAGISel.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelDAGToDAG/DAGToDAGISel.cpp new file mode 100644 index 0000000000000000000000000000000000000000..949472bcf4aeb01469b19d992e696f36ab2e04c7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelDAGToDAG/DAGToDAGISel.cpp @@ -0,0 +1,2 @@ +explicit RISCVDAGToDAGISel ( RISCVTargetMachine & TargetMachine ) : SelectionDAGISel ( TargetMachine ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelDAGToDAG/MatchSLLIUW.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelDAGToDAG/MatchSLLIUW.cpp new file mode 100644 index 0000000000000000000000000000000000000000..10f3f80f974371d3bfa629f5a8a37c4542d7736d --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelDAGToDAG/MatchSLLIUW.cpp @@ -0,0 +1,2 @@ +bool RISCVDAGToDAGISel :: MatchSLLIUW ( SDNode * N ) const { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelDAGToDAG/MatchSRLIUW.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelDAGToDAG/MatchSRLIUW.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7d8e4bb93a2851ed78020598b9f3d62e97ef7537 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelDAGToDAG/MatchSRLIUW.cpp @@ -0,0 +1,2 @@ +bool RISCVDAGToDAGISel :: MatchSRLIUW ( SDNode * N ) const { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelDAGToDAG/PostprocessISelDAG.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelDAGToDAG/PostprocessISelDAG.cpp new file mode 100644 index 0000000000000000000000000000000000000000..64ebc5e399566bfe6ffd6cfc0c8707c05b14be31 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelDAGToDAG/PostprocessISelDAG.cpp @@ -0,0 +1,106 @@ +void RISCVDAGToDAGISel :: PostprocessISelDAG ( ) { +bool IsModified = false ; +if ( TM . getOptLevel ( ) == CodeGenOpt :: None ) { +SelectionDAG :: allnodes_iterator Position ( CurDAG -> getRoot ( ) . getNode ( ) ) ; +Position = Position + 1 ; +for ( ; IsModified ; ) { +IsModified = false ; +SelectionDAG :: allnodes_iterator Position = CurDAG -> allnodes_begin ( ) ; +for ( ; Position != CurDAG -> allnodes_end ( ) ; ) { +SDNode * Node = & * Position ++ ; +MachineSDNode * MachineNode = dyn_cast < MachineSDNode > ( Node ) ; +if ( ! MachineNode ) { +continue ; +} +SDNode * ResNode = Lowering . PostISelFolding ( MachineNode , * CurDAG ) ; +if ( ResNode != Node ) { +if ( ResNode ) { +ReplaceUses ( Node , ResNode ) ; +} +IsModified = true ; +} +} +CurDAG -> RemoveDeadNodes ( ) ; +DNode * N = Position - 1 ; +Position = Posiiton - 1 +if ( N -> use_empty ( ) ) { +continue ; +} +if ( ! N -> isMachineOpcode ( ) ) { +continue ; +} +unsigned FirstOp ; +unsigned StorageOpcode = N -> getMachineOpcode ( ) ; +if ( StorageOpcode == RISCV::LB ) { +FirstOp = 0 ; +} +if ( StorageOpcode == RISCV :: LH ) { +FirstOp = 0 ; +} +if ( StorageOpcode == RISCV :: LW ) { +FirstOp = 0 ; +} +if ( StorageOpcode == RISCV :: LBU ) { +FirstOp = 0 ; +} +if ( StorageOpcode == RISCV :: LHU ) { +FirstOp = 0 ; +} +if ( StorageOpcode == RISCV :: LWU ) { +FirstOp = 0 ; +} +if ( StorageOpcode == RISCV :: LD ) { +FirstOp = 1 ; +} +if ( StorageOpcode == RISCV::FLH ) { +FirstOp = 1 ; +} +if ( StorageOpcode == RISCV::FLW ) { +FirstOp = 1 ; +} +if ( StorageOpcode == RISCV :: FLD ) { +FirstOp = 1 ; +} +if ( StorageOpcode == RISCV :: SB ) { +FirstOp = 1 ; +} +if ( ! isa < ConstantSDNode > ( N -> getOperand ( FirstOp ) ) ) { +continue ; +} +if ( N -> getConstantOperandVal ( FirstOp ) != 0 ) { +continue ; +} +SDValue Base = N -> getOperand ( FirstOp + 1 ) ; +if ( ! Base . isMachineOpcode ( ) ) { +continue ; +} +unsigned Flags = 0 ; +bool ReplaceFlags = true ; +ReplaceFlags = false ; +Flags = RISCVII :: MO_DTPREL_LO ; +Flags = RISCVII :: MO_TLSLD_LO ; +Flags = RISCVII :: MO_TOC_LO ; +DEBUG ( dbgs ( ) << "Folding add-immediate into mem-op:\nBase: " ) ; +SDValue ImmOpnd = Base . getOperand ( 1 ) ; +if ( ReplaceFlags ) { +if ( GlobalAddressSDNode * GA = dyn_cast < GlobalAddressSDNode > ( ImmOpnd ) ) { +SDLoc dl ( GA ) ; +const GlobalValue * GV = GA -> getGlobal ( ) ; +ImmOpnd = CurDAG -> getTargetGlobalAddress ( GV , dl , MVT :: i64 , 0 , Flags ) ; +} +if ( ConstantPoolSDNode * CP = dyn_cast < ConstantPoolSDNode > ( ImmOpnd ) ) { +const Constant * C = CP -> getConstVal ( ) ; +ImmOpnd = CurDAG -> getTargetConstantPool ( C , MVT :: i64 , CP -> getAlignment ( ) , 0 , Flags ) ; +} +} +if ( FirstOp == 1 ) { +( void ) CurDAG -> UpdateNodeOperands ( N , N -> getOperand ( 0 ) , ImmOpnd , Base . getOperand ( 0 ) , N -> getOperand ( 3 ) ) ; +} +if ( FirstOp != 1 ) { +( void ) CurDAG -> UpdateNodeOperands ( N , N -> getOperand ( 0 ) , ImmOpnd , Base . getOperand ( 0 ) , N -> getOperand ( 3 ) ) ; +} +if ( Base . getNode ( ) -> use_empty ( ) ) { +CurDAG -> RemoveDeadNode ( Base . getNode ( ) ) ; +} +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelDAGToDAG/Select.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelDAGToDAG/Select.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f60b6aabbbb9fec3f010758aca9c5863c0003430 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelDAGToDAG/Select.cpp @@ -0,0 +1,66 @@ +void RISCVDAGToDAGISel :: Select ( SDNode * Node ) { +unsigned Opcode = Node -> getOpcode ( ) ; +if ( Node -> isMachineOpcode ( ) ) { +LLVM_DEBUG ( dbgs ( ) << "== " ; Node -> dump ( CurDAG ) ; dbgs ( ) << "\n" ) ; +Node -> setNodeId ( - 1 ) ; +return ; +} +EVT NodeTy = Node -> getValueType ( 0 ) ; +unsigned MultOpc ; +SDLoc Dl ( Node ) ; +unsigned Opcode = Node -> getOpcode ( ) ; +bool IsSelected = false ; +if ( Opcode == ISD :: ADD ) { +SDValue Chain = Node -> getOperand ( 0 ) ; +SDValue Skb = Node -> getOperand ( 2 ) ; +SDValue N3 = Node -> getOperand ( 3 ) ; +SDValue R6Reg = CurDAG -> getRegister ( RISCV :: R6 , MVT :: i64 ) ; +Chain = CurDAG -> getCopyToReg ( Chain , DL , R6Reg , Skb , SDValue ( ) ) ; +Node = CurDAG -> UpdateNodeOperands ( Node , Chain , N1 , R6Reg , N3 ) ; +break ; +if ( IntNo == ISD :: Constant ) { +SDLoc DL ( Node ) ; +SDValue Chain = Node -> getOperand ( 0 ) ; +SDValue Skb = Node -> getOperand ( 2 ) ; +SDValue N3 = Node -> getOperand ( 3 ) ; +SDValue R6Reg = CurDAG -> getRegister ( RISCV :: R6 , MVT :: i64 ) ; +Chain = CurDAG -> getCopyToReg ( Chain , DL , R6Reg , Skb , SDValue ( ) ) ; +Node = CurDAG -> UpdateNodeOperands ( Node , Chain , N1 , R6Reg , N3 ) ; +break ; +} +if ( IntNo == ISD :: FrameIndex ) { +SDLoc DL ( Node ) ; +SDValue Chain = Node -> getOperand ( 0 ) ; +SDValue Skb = Node -> getOperand ( 2 ) ; +SDValue N3 = Node -> getOperand ( 3 ) ; +SDValue R6Reg = CurDAG -> getRegister ( RISCV :: R6 , MVT :: i64 ) ; +Chain = CurDAG -> getCopyToReg ( Chain , DL , R6Reg , Skb , SDValue ( ) ) ; +Node = CurDAG -> UpdateNodeOperands ( Node , Chain , N1 , R6Reg , N3 ) ; +break ; +} +} +if ( Opcode == ISD :: INTRINSIC_W_CHAIN ) { +int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ; +EVT VT = Node -> getValueType ( 0 ) ; +SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ; +unsigned Opc = RISCV :: MOV_rr ; +ReplaceNode ( Node , CurDAG -> getMachineNode ( Opc , SDLoc ( Node ) , VT , TFI ) ) ; +return ; +} +if ( Opcode == ISD :: INTRINSIC_VOID ) { +const ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Node ) ; +unsigned Size = CN -> getValueSizeInBits ( 0 ) ; +int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ; +ReplaceNode ( Node , CurDAG -> getMachineNode ( Subtarget -> hasE2 ( ) ? RISCV :: ADDI32 : RISCV :: ADDI16XZ , Dl , MVT :: i32 , TFI , Imm ) ) ; +IsSelected = true ; +selectFrameIndex ( Node ) ; +ReplaceNode ( Node , CurDAG -> getMachineNode ( RISCV :: ADDI , DL , VT , TFI , Imm ) ) ; +return ; +} +SDNode * ResNode = SelectCode ( Node ) ; +return ResNode ; +if ( IsSelected ) { +return ; +} +SelectCode ( Node ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelDAGToDAG/SelectAddrFI.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelDAGToDAG/SelectAddrFI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..557c693bf868b0fc0b9cffea5c4c83536f585dbe --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelDAGToDAG/SelectAddrFI.cpp @@ -0,0 +1,7 @@ +bool RISCVDAGToDAGISel :: SelectAddrFI ( SDValue Addr , SDValue & Base ) { +if ( auto FIN = dyn_cast < FrameIndexSDNode > ( Addr ) ) { +Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , Subtarget -> getXLenVT ( ) ) ; +return true ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelDAGToDAG/SelectInlineAsmMemoryOperand.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelDAGToDAG/SelectInlineAsmMemoryOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..03bbb2c4d1a46bb6b0b1744ebb3c0a7c64a9570f --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelDAGToDAG/SelectInlineAsmMemoryOperand.cpp @@ -0,0 +1,12 @@ +bool RISCVDAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , unsigned ConstraintID , std :: vector < SDValue > & OutOps ) { +if ( ConstraintID == InlineAsm :: Constraint_m ) { +OutOps . push_back ( Op ) ; +return false ; +} +if ( ConstraintID == InlineAsm :: Constraint_A ) { +OutOps . push_back ( Op ) ; +return false ; +} +llvm_unreachable ( "Unexpected asm memory constraint" ) ; +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelDAGToDAG/createISelDag.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelDAGToDAG/createISelDag.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cc4ca513b3d19fe740805ba02254115013b7adf9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelDAGToDAG/createISelDag.cpp @@ -0,0 +1,3 @@ +FunctionPass * llvm :: createRISCVISelDag ( RISCVTargetMachine & TM ) { +return new RISCVDAGToDAGISel ( TM ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelDAGToDAG/getPassName.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelDAGToDAG/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c6421d727e042af3e03db83a48934e1a6f832716 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelDAGToDAG/getPassName.cpp @@ -0,0 +1,3 @@ +StringRef getPassName ( ) const override { +return "RISCV DAG->DAG Pattern Instruction Selection" ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelDAGToDAG/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelDAGToDAG/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6ce1ac25c2747cc2284cee6d398826135b851714 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelDAGToDAG/runOnMachineFunction.cpp @@ -0,0 +1,4 @@ +bool runOnMachineFunction ( MachineFunction & MF ) override { +Subtarget = & MF . getSubtarget < RISCVSubtarget > ( ) ; +return SelectionDAGISel :: runOnMachineFunction ( MF ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelDAGToDAG/selectVLOp.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelDAGToDAG/selectVLOp.cpp new file mode 100644 index 0000000000000000000000000000000000000000..217fe60421fbc9c1c4d8fd4169bb9120dae9bfdd --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelDAGToDAG/selectVLOp.cpp @@ -0,0 +1,9 @@ +bool RISCVDAGToDAGISel :: selectVLOp ( SDValue N , SDValue & VL ) { +const ConstantFPSDNode * CN = dyn_cast < ConstantFPSDNode > ( N ) ; +Val = N ; +if ( v ) { +if ( ! ( v & ( v - 1 ) ) ) { +return true ; +} +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelDAGToDAG/selectVSplat.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelDAGToDAG/selectVSplat.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c270a24175b584ed7007ee605b399d579a10134b --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelDAGToDAG/selectVSplat.cpp @@ -0,0 +1,10 @@ +bool RISCVDAGToDAGISel :: selectVSplat ( SDValue N , SDValue & SplatVal ) { +const ConstantFPSDNode * CN = dyn_cast < ConstantFPSDNode > ( N ) ; +if ( ConstantSDNode * Imm = dyn_cast < ConstantSDNode > ( N . getNode ( ) ) ) { +} +if ( ! ( ConstantSDNode * Imm = dyn_cast < ConstantSDNode > ( N . getNode ( ) ) ) ) { +} +int bit = 0x1f - __builtin_clz ( v ) ; +imm = CurDAG -> getTargetConstant ( bit , MVT :: i32 ) ; +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelDAGToDAG/selectVSplatSimm5.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelDAGToDAG/selectVSplatSimm5.cpp new file mode 100644 index 0000000000000000000000000000000000000000..98e3da06d578a447193cc2d7237ab037a511018e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelDAGToDAG/selectVSplatSimm5.cpp @@ -0,0 +1,10 @@ +bool RISCVDAGToDAGISel :: selectVSplatSimm5 ( SDValue N , SDValue & SplatVal ) { +const ConstantFPSDNode * CN = dyn_cast < ConstantFPSDNode > ( N ) ; +if ( ConstantSDNode * Imm = dyn_cast < ConstantSDNode > ( N . getNode ( ) ) ) { +} +if ( ! ( ConstantSDNode * Imm = dyn_cast < ConstantSDNode > ( N . getNode ( ) ) ) ) { +} +int bit = 0x1f - __builtin_clz ( v ) ; +imm = CurDAG -> getTargetConstant ( bit , MVT :: i32 ) ; +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelDAGToDAG/selectVSplatUimm5.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelDAGToDAG/selectVSplatUimm5.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c08b4679a6b3a1ca334fc129ad5746a12a52c0a0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelDAGToDAG/selectVSplatUimm5.cpp @@ -0,0 +1,9 @@ +bool RISCVDAGToDAGISel :: selectVSplatUimm5 ( SDValue N , SDValue & SplatVal ) { +const ConstantFPSDNode * CN = dyn_cast < ConstantFPSDNode > ( N ) ; +if ( ConstantSDNode * Imm = dyn_cast < ConstantSDNode > ( N . getNode ( ) ) ) { +} +if ( ! ( ConstantSDNode * Imm = dyn_cast < ConstantSDNode > ( N . getNode ( ) ) ) ) { +} +imm = CurDAG -> getTargetConstant ( bit , MVT :: i32 ) ; +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/CanLowerReturn.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/CanLowerReturn.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e0bf63fd8da8636b8e53a4d9760da5dc0cc2782d --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/CanLowerReturn.cpp @@ -0,0 +1,14 @@ +bool RISCVTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool IsVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { +CCAssignFn * RetCC = CallConv == CallingConv :: WebKit_JS ? RetCC_RISCV_WebKit_JS : RetCC_RISCV_AAPCS ; +SmallVector < CCValAssign , 16 > RVLocs ; +CCState CCInfo ( CallConv , isVarArg , MF , RVLocs , Context ) ; +CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , Context ) ; +auto CCFunction = CCAssignFnForReturn ( CallConv ) ; +for ( unsigned i = 0 , e = Outs . size ( ) ; i != e ; ++ i ) { +MVT VT = Outs [ i ] . VT ; +if ( VT == MVT :: i128 ) { +return false ; +} +} +return CCInfo . CheckReturn ( Outs , RetCC ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/ComputeNumSignBitsForTargetNode.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/ComputeNumSignBitsForTargetNode.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e69d8f7a9d0dff85f54f6378e2364d9523facf16 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/ComputeNumSignBitsForTargetNode.cpp @@ -0,0 +1,39 @@ +unsigned RISCVTargetLowering :: ComputeNumSignBitsForTargetNode ( SDValue Op , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { +if ( Op . getOpcode ( ) == RISCVISD :: SLLW ) { +return Op . getScalarValueSizeInBits ( ) ; +} +if ( Op . getOpcode ( ) == RISCVISD :: SRAW ) { +return Op . getScalarValueSizeInBits ( ) ; +} +if ( Op . getOpcode ( ) == RISCVISD :: SRLW ) { +return 33 ; +} +if ( Op . getOpcode ( ) == RISCVISD :: DIVW ) { +return 33 ; +} +if ( Op . getOpcode ( ) == RISCVISD :: DIVUW ) { +return 33 ; +} +if ( Op . getOpcode ( ) == RISCVISD :: REMUW ) { +return 33 ; +} +if ( Op . getOpcode ( ) == RISCVISD::VMV_X_S ) { +ConstantSDNode * Width = dyn_cast < ConstantSDNode > ( Op . getOperand ( 2 ) ) ; +if ( ! Width ) { +return 1 ; +} +unsigned SignBits = 32 - Width -> getZExtValue ( ) + 1 ; +if ( ! isNullConstant ( Op . getOperand ( 1 ) ) ) { +return SignBits ; +} +unsigned Op0SignBits = DAG . ComputeNumSignBits ( Op . getOperand ( 0 ) , Depth + 1 ) ; +SDValue Src = Op . getOperand ( 0 ) ; +unsigned Tmp = DAG . ComputeNumSignBits ( Src , Depth + 1 ) ; +Tmp = Tmp + VTBits - Src . getScalarValueSizeInBits ( ) ; +} +if ( Op . getOpcode ( ) == RISCVISD :: ROLW ) { +unsigned Tmp = DAG . ComputeNumSignBits ( Src , Depth + 1 ) ; +return 33 ; +} +return 1 ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/EmitInstrWithCustomInserter.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/EmitInstrWithCustomInserter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..715360bc6eb5c00b66e95aa1e11fde7bf6edb523 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/EmitInstrWithCustomInserter.cpp @@ -0,0 +1,22 @@ +MachineBasicBlock * RISCVTargetLowering :: EmitInstrWithCustomInserter ( MachineInstr & MI , MachineBasicBlock * BB ) const { +if ( MI . getOpcode ( ) == RISCV :: Select_GPR_Using_CC_GPR ) { +return expandSelectCC ( MI , BB , RISCV :: BCOND ) ; +} +if ( MI . getOpcode ( ) == RISCV :: Select_FPR16_Using_CC_GPR ) { +return expandSelectCC ( MI , BB , RISCV :: BCOND ) ; +} +if ( MI . getOpcode ( ) == RISCV :: Select_FPR32_Using_CC_GPR ) { +return expandSelectCC ( MI , BB , RISCV :: BCOND ) ; +} +if ( MI . getOpcode ( ) == RISCV :: Select_FPR64_Using_CC_GPR ) { +return expandSelectCC ( MI , BB , RISCV :: BCOND ) ; +} +if ( MI . getOpcode ( ) == RISCV :: BuildPairF64Pseudo ) { +return expandSelectCC ( MI , BB , RISCV :: FBCOND ) ; +return EmitSelectInstr ( MI , MBB ) ; +} +if ( MI . getOpcode ( ) == RISCV :: SplitF64Pseudo ) { +return expandSelectCC ( MI , BB , RISCV :: FBCOND ) ; +} +llvm_unreachable ( "Unexpected instruction for custom inserter!" ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/LowerAsmOperandForConstraint.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/LowerAsmOperandForConstraint.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2fc031d6fb3b4e0ce9f685b75f9c10c138a2446b --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/LowerAsmOperandForConstraint.cpp @@ -0,0 +1,35 @@ +void RISCVTargetLowering :: LowerAsmOperandForConstraint ( SDValue Op , std :: string & Constraint , std :: vector < SDValue > & Ops , SelectionDAG & DAG ) const { +SDLoc DL ( Op ) ; +SDValue Result ; +MVT XLenVT = Subtarget . getXLenVT ( ) ; +if ( Constraint . length ( ) == 1 ) { +if ( Constraint [ 0 ] == 'I' ) { +if ( auto * C = dyn_cast < ConstantSDNode > ( Op ) ) { +uint64_t Val = C -> getSExtValue ( ) ; +if ( isInt < 12 > ( Val ) ) { +Ops . push_back ( DAG . getTargetConstant ( Val , DL , XLenVT ) ) ; +} +} +return ; +} +if ( Constraint [ 0 ] == 'J' ) { +if ( auto * C = dyn_cast < ConstantSDNode > ( Op ) ) { +uint64_t Val = C -> getSExtValue ( ) ; +if ( Val == 0 ) { +Ops . push_back ( DAG . getTargetConstant ( 0 , DL , XLenVT ) ) ; +} +} +return ; +} +if ( Constraint [ 0 ] == 'K' ) { +if ( auto * C = dyn_cast < ConstantSDNode > ( Op ) ) { +uint64_t Val = C -> getSExtValue ( ) ; +if ( isUInt < 5 > ( Val ) ) { +Ops . push_back ( DAG . getTargetConstant ( Val , DL , XLenVT ) ) ; +} +} +return ; +} +} +TargetLowering :: LowerAsmOperandForConstraint ( Op , Constraint , Ops , DAG ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/LowerBlockAddress.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/LowerBlockAddress.cpp new file mode 100644 index 0000000000000000000000000000000000000000..825802886cf829c000e7bd4ed1ead03355f7439a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/LowerBlockAddress.cpp @@ -0,0 +1,4 @@ +SDValue RISCVTargetLowering :: lowerBlockAddress ( SDValue Op , SelectionDAG & DAG ) const { +BlockAddressSDNode * N = cast < BlockAddressSDNode > ( Op ) ; +return getAddr ( N , DAG ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/LowerCall.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/LowerCall.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0850225aedf95232a51d2f5e5c4ed53f3e4f12ad --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/LowerCall.cpp @@ -0,0 +1,348 @@ +SDValue RISCVTargetLowering :: LowerCall ( CallLoweringInfo & CLI , SmallVectorImpl < SDValue > & InVals ) const { +SelectionDAG & DAG = CLI . DAG ; +SDLoc & DL = CLI . DL ; +SmallVectorImpl < ISD :: OutputArg > & Outs = CLI . Outs ; +SmallVectorImpl < SDValue > & OutVals = CLI . OutVals ; +SmallVectorImpl < ISD :: InputArg > & Ins = CLI . Ins ; +DebugLoc & dl = CLI . DL ; +SmallVector < ISD :: OutputArg , 32 > & Outs = CLI . Outs ; +SmallVector < SDValue , 32 > & OutVals = CLI . OutVals ; +SmallVector < ISD :: InputArg , 32 > & Ins = CLI . Ins ; +SDValue Chain = CLI . Chain ; +SDValue Callee = CLI . Callee ; +bool & isTailCall = CLI . IsTailCall ; +CallingConv :: ID CallConv = CLI . CallConv ; +bool isVarArg = CLI . IsVarArg ; +const char * RISCV16HelperFunction = 0 ; +bool needRISCV16Helper = false ; +if ( Subtarget -> inMips16Mode ( ) ) { +bool lookupHelper = true ; +if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { +if ( noHelperNeeded . find ( S -> getSymbol ( ) ) != noHelperNeeded . end ( ) ) { +lookupHelper = false ; +} +} +if ( lookupHelper ) { +RISCV16HelperFunction = getRISCV16HelperFunction ( CLI . RetTy , CLI . Args , needRISCV16Helper ) ; +} +} +MachineFunction & MF = DAG . getMachineFunction ( ) ; +isTailCall = false ; +MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; +const TargetFrameLowering * TFL = MF . getTarget ( ) . getFrameLowering ( ) ; +bool IsPIC = getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ; +SmallVector < CCValAssign , 16 > ArgLocs ; +CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; +const Function * F = nullptr ; +if ( const GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { +const GlobalValue * GV = G -> getGlobal ( ) ; +F = cast < Function > ( GV ) ; +Callee = DAG . getTargetGlobalAddress ( GV , DL , getPointerTy ( DAG . getDataLayout ( ) ) ) ; +} +if ( const ExternalSymbolSDNode * ES = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { +Callee = DAG . getTargetExternalSymbol ( ES -> getSymbol ( ) , getPointerTy ( DAG . getDataLayout ( ) ) ) ; +} +analyzeArguments ( & CLI , F , & DAG . getDataLayout ( ) , & Outs , 0 , CallConv , ArgLocs , CCInfo , true , isVarArg ) ; +unsigned NumBytes = CCInfo . getNextStackOffset ( ) ; +CCState CCInfo ( CallConv , isVarArg , DAG . getTarget ( ) , ArgLocs , * DAG . getContext ( ) ) ; +CCInfo . AnalyzeCallOperands ( Outs , CC_RISCV32 ) ; +unsigned ArgsSize = CCInfo . getNextStackOffset ( ) ; +ArgsSize = ( ArgsSize + 7 ) & ~ 7 ; +MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; +SmallVector < SDValue , 8 > ByValArgs ; +for ( unsigned i = 0 , e = Outs . size ( ) ; i != e ; ++ i ) { +ISD :: ArgFlagsTy Flags = Outs [ i ] . Flags ; +if ( ! Flags . isByVal ( ) ) { +continue ; +} +SDValue Arg = OutVals [ i ] ; +unsigned Size = Flags . getByValSize ( ) ; +unsigned Align = Flags . getByValAlign ( ) ; +int FI = MFI -> CreateStackObject ( Size , Align , false ) ; +SDValue FIPtr = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; +SDValue SizeNode = DAG . getConstant ( Size , MVT :: i32 ) ; +Chain = DAG . getMemcpy ( Chain , dl , FIPtr , Arg , SizeNode , Align , false , ( Size <= 32 ) , MachinePointerInfo ( ) , MachinePointerInfo ( ) ) ; +ByValArgs . push_back ( FIPtr ) ; +} +Chain = DAG . getCALLSEQ_START ( Chain , DAG . getIntPtrConstant ( NumBytes , DL , true ) , DL ) ; +SmallVector < std :: pair < unsigned , SDValue > , 8 > RegsToPass ; +unsigned AI ; +unsigned AE ; +bool HasStackArgs = false ; +CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , ArgLocs , * DAG . getContext ( ) ) ; +RISCVCC RISCVCCInfo ( CallConv , IsO32 , CCInfo ) ; +RISCVCCInfo . analyzeCallOperands ( Outs , isVarArg ) ; +unsigned NextStackOffset = CCInfo . getNextStackOffset ( ) ; +if ( isTailCall ) { +isTailCall = IsEligibleForTailCallOptimization ( RISCVCCInfo , NextStackOffset , * MF . getInfo < RISCVFunctionInfo > ( ) ) ; +} +if ( isTailCall ) { +NumTailCalls = NumTailCalls + 1 ; +} +unsigned StackAlignment = TFL -> getStackAlignment ( ) ; +NextStackOffset = RoundUpToAlignment ( NextStackOffset , StackAlignment ) ; +SDValue NextStackOffsetVal = DAG . getIntPtrConstant ( NextStackOffset , true ) ; +if ( ! isTailCall ) { +Chain = DAG . getCALLSEQ_START ( Chain , NextStackOffsetVal ) ; +} +SDValue StackPtr = DAG . getCopyFromReg ( Chain , dl , IsN64 ? RISCV :: SP_64 : RISCV :: SP , getPointerTy ( ) ) ; +std :: deque < std :: pair < unsigned , SDValue > > RegsToPass ; +SmallVector < SDValue , 8 > MemOpChains ; +RISCVCC :: byval_iterator ByValArg = RISCVCCInfo . byval_begin ( ) ; +const unsigned StackOffset = 92 ; +bool hasStructRetAttr = false ; +for ( AI = 0 , AE = ArgLocs . size ( ) ; AI != AE ; ++ AI ) { +CCValAssign & VA = ArgLocs [ AI ] ; +EVT RegVT = VA . getLocVT ( ) ; +SDValue Arg = OutVals [ AI ] ; +CCValAssign & VA = ArgLocs [ i ] ; +MVT ValVT = VA . getValVT ( ) , LocVT = VA . getLocVT ( ) ; +if ( Flags . isByVal ( ) ) { +assert ( ! isTailCall && "Do not tail-call optimize if there is a byval argument." ) ; +passByValArg ( Chain , dl , RegsToPass , MemOpChains , StackPtr , MFI , DAG , Arg , RISCVCCInfo , * ByValArg , Flags , Subtarget -> isLittle ( ) ) ; +ByValArg = ByValArg + 1 ; +continue ; +Arg = ByValArgs [ byvalArgIdx ++ ] ; +} +Arg = DAG . getNode ( ISD :: SIGN_EXTEND , DL , RegVT , Arg ) ; +if ( ValVT == MVT :: f32 ) { +if ( LocVT == MVT :: i32 ) { +Arg = DAG . getNode ( ISD :: BITCAST , dl , LocVT , Arg ) ; +} +} +if ( ValVT == MVT :: f64 ) { +if ( LocVT == MVT :: i64 ) { +Arg = DAG . getNode ( ISD :: BITCAST , dl , LocVT , Arg ) ; +} +} +if ( LocVT == MVT :: i32 ) { +if ( ValVT == MVT :: f64 ) { +SDValue Lo = DAG . getNode ( RISCVISD :: ExtractElementF64 , dl , MVT :: i32 , Arg , DAG . getConstant ( 0 , MVT :: i32 ) ) ; +SDValue Hi = DAG . getNode ( RISCVISD :: ExtractElementF64 , dl , MVT :: i32 , Arg , DAG . getConstant ( 1 , MVT :: i32 ) ) ; +std :: swap ( Lo , Hi ) ; +unsigned LocRegLo = VA . getLocReg ( ) ; +unsigned LocRegHigh = getNextIntArgReg ( LocRegLo ) ; +RegsToPass . push_back ( std :: make_pair ( LocRegLo , Lo ) ) ; +RegsToPass . push_back ( std :: make_pair ( LocRegHigh , Hi ) ) ; +continue ; +} +} +Arg = DAG . getNode ( ISD :: ZERO_EXTEND , DL , RegVT , Arg ) ; +Arg = DAG . getNode ( ISD :: ANY_EXTEND , DL , RegVT , Arg ) ; +Arg = DAG . getNode ( ISD :: BITCAST , DL , RegVT , Arg ) ; +if ( VA . isMemLoc ( ) ) { +HasStackArgs = true ; +break ; +} +RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; +if ( Flags . isSRet ( ) ) { +SDValue StackPtr = DAG . getRegister ( RISCV :: O6 , MVT :: i32 ) ; +SDValue PtrOff = DAG . getIntPtrConstant ( 64 ) ; +PtrOff = DAG . getNode ( ISD :: ADD , dl , MVT :: i32 , StackPtr , PtrOff ) ; +MemOpChains . push_back ( DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo ( ) , false , false , 0 ) ) ; +hasStructRetAttr = true ; +continue ; +} +if ( VA . needsCustom ( ) ) { +if ( VA . isMemLoc ( ) ) { +unsigned Offset = VA . getLocMemOffset ( ) + StackOffset ; +if ( Offset % 8 == 0 ) { +SDValue StackPtr = DAG . getRegister ( RISCV :: O6 , MVT :: i32 ) ; +SDValue PtrOff = DAG . getIntPtrConstant ( Offset ) ; +PtrOff = DAG . getNode ( ISD :: ADD , dl , MVT :: i32 , StackPtr , PtrOff ) ; +MemOpChains . push_back ( DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo ( ) , false , false , 0 ) ) ; +continue ; +} +} +SDValue StackPtr = DAG . CreateStackTemporary ( MVT :: f64 , MVT :: i32 ) ; +SDValue Store = DAG . getStore ( DAG . getEntryNode ( ) , dl , Arg , StackPtr , MachinePointerInfo ( ) , false , false , 0 ) ; +SDValue Hi = DAG . getLoad ( MVT :: i32 , dl , Store , StackPtr , MachinePointerInfo ( ) , false , false , 0 ) ; +StackPtr = DAG . getNode ( ISD :: ADD , dl , StackPtr . getValueType ( ) , StackPtr , DAG . getIntPtrConstant ( 4 ) ) ; +SDValue Lo = DAG . getLoad ( MVT :: i32 , dl , Store , StackPtr , MachinePointerInfo ( ) , false , false , 0 ) ; +if ( VA . isRegLoc ( ) ) { +RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Hi ) ) ; +CCValAssign & NextVA = ArgLocs [ ++ i ] ; +if ( NextVA . isRegLoc ( ) ) { +RegsToPass . push_back ( std :: make_pair ( NextVA . getLocReg ( ) , Lo ) ) ; +} +if ( ! NextVA . isRegLoc ( ) ) { +unsigned Offset = NextVA . getLocMemOffset ( ) + StackOffset ; +SDValue StackPtr = DAG . getRegister ( RISCV :: O6 , MVT :: i32 ) ; +SDValue PtrOff = DAG . getIntPtrConstant ( Offset ) ; +PtrOff = DAG . getNode ( ISD :: ADD , dl , MVT :: i32 , StackPtr , PtrOff ) ; +MemOpChains . push_back ( DAG . getStore ( Chain , dl , Lo , PtrOff , MachinePointerInfo ( ) , false , false , 0 ) ) ; +} +} +if ( ! VA . isRegLoc ( ) ) { +unsigned Offset = VA . getLocMemOffset ( ) + StackOffset ; +SDValue StackPtr = DAG . getRegister ( RISCV :: O6 , MVT :: i32 ) ; +SDValue PtrOff = DAG . getIntPtrConstant ( Offset ) ; +PtrOff = DAG . getNode ( ISD :: ADD , dl , MVT :: i32 , StackPtr , PtrOff ) ; +MemOpChains . push_back ( DAG . getStore ( Chain , dl , Hi , PtrOff , MachinePointerInfo ( ) , false , false , 0 ) ) ; +PtrOff = DAG . getIntPtrConstant ( Offset + 4 ) ; +PtrOff = DAG . getNode ( ISD :: ADD , dl , MVT :: i32 , StackPtr , PtrOff ) ; +MemOpChains . push_back ( DAG . getStore ( Chain , dl , Lo , PtrOff , MachinePointerInfo ( ) , false , false , 0 ) ) ; +} +continue ; +} +if ( VA . isRegLoc ( ) ) { +if ( VA . getLocVT ( ) != MVT :: f32 ) { +RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; +continue ; +} +Arg = DAG . getNode ( ISD :: BITCAST , dl , MVT :: i32 , Arg ) ; +RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; +continue ; +} +assert ( VA . isMemLoc ( ) ) ; +MemOpChains . push_back ( passArgOnStack ( StackPtr , VA . getLocMemOffset ( ) , Chain , Arg , dl , isTailCall , DAG ) ) ; +SDValue StackPtr = DAG . getRegister ( RISCV :: O6 , MVT :: i32 ) ; +SDValue PtrOff = DAG . getIntPtrConstant ( VA . getLocMemOffset ( ) + StackOffset ) ; +PtrOff = DAG . getNode ( ISD :: ADD , dl , MVT :: i32 , StackPtr , PtrOff ) ; +MemOpChains . push_back ( DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo ( ) , false , false , 0 ) ) ; +} +if ( HasStackArgs ) { +for ( AE = AI , AI = ArgLocs . size ( ) ; AI != AE ; -- AI ) { +unsigned Loc = AI - 1 ; +CCValAssign & VA = ArgLocs [ Loc ] ; +SDValue Arg = OutVals [ Loc ] ; +assert ( VA . isMemLoc ( ) ) ; +SDValue PtrOff = DAG . getNode ( ISD :: ADD , DL , getPointerTy ( DAG . getDataLayout ( ) ) , DAG . getRegister ( RISCV :: SP , getPointerTy ( DAG . getDataLayout ( ) ) ) , DAG . getIntPtrConstant ( VA . getLocMemOffset ( ) + 1 , DL ) ) ; +Chain = DAG . getStore ( Chain , DL , Arg , PtrOff , MachinePointerInfo :: getStack ( MF , VA . getLocMemOffset ( ) ) , 0 ) ; +} +} +if ( ! MemOpChains . empty ( ) ) { +Chain = DAG . getCopyToReg ( Chain , DL , Reg . first , Reg . second , InFlag ) ; +} +bool IsPICCall = ( IsN64 || IsPIC ) ; +bool GlobalOrExternal = false , InternalLinkage = false ; +SDValue CalleeLo ; +if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { +if ( IsPICCall ) { +InternalLinkage = G -> getGlobal ( ) -> hasInternalLinkage ( ) ; +if ( InternalLinkage ) { +Callee = getAddrLocal ( Callee , DAG , HasRISCV64 ) ; +} +if ( LargeGOT ) { +Callee = getAddrGlobalLargeGOT ( Callee , DAG , RISCVII :: MO_CALL_HI16 , RISCVII :: MO_CALL_LO16 ) ; +} +if ( ! InternalLinkage ) { +if ( ! LargeGOT ) { +Callee = getAddrGlobal ( Callee , DAG , RISCVII :: MO_GOT_CALL ) ; +} +} +} +if ( ! IsPICCall ) { +Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , dl , getPointerTy ( ) , 0 , RISCVII :: MO_NO_FLAG ) ; +} +GlobalOrExternal = true ; +} +if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { +if ( ! IsN64 ) { +if ( ! IsPIC ) { +Callee = DAG . getTargetExternalSymbol ( S -> getSymbol ( ) , getPointerTy ( ) , RISCVII :: MO_NO_FLAG ) ; +} +} +if ( LargeGOT ) { +Callee = getAddrGlobalLargeGOT ( Callee , DAG , RISCVII :: MO_CALL_HI16 , RISCVII :: MO_CALL_LO16 ) ; +} +if ( ! LargeGOT ) { +Callee = getAddrGlobal ( Callee , DAG , RISCVII :: MO_GOT_CALL ) ; +} +GlobalOrExternal = true ; +} +SDValue JumpTarget = Callee ; +if ( IsPICCall ) { +unsigned T9Reg = IsN64 ? RISCV :: T9_64 : RISCV :: T9 ; +unsigned V0Reg = RISCV :: V0 ; +if ( needRISCV16Helper ) { +RegsToPass . push_front ( std :: make_pair ( V0Reg , Callee ) ) ; +JumpTarget = DAG . getExternalSymbol ( RISCV16HelperFunction , getPointerTy ( ) ) ; +JumpTarget = getAddrGlobal ( JumpTarget , DAG , RISCVII :: MO_GOT ) ; +} +if ( ! needRISCV16Helper ) { +RegsToPass . push_front ( std :: make_pair ( T9Reg , Callee ) ) ; +JumpTarget = SDValue ( ) ; +} +} +if ( ! GlobalOrExternal ) { +unsigned T9Reg = IsN64 ? RISCV :: T9_64 : RISCV :: T9 ; +unsigned V0Reg = RISCV :: V0 ; +if ( needRISCV16Helper ) { +RegsToPass . push_front ( std :: make_pair ( V0Reg , Callee ) ) ; +JumpTarget = DAG . getExternalSymbol ( RISCV16HelperFunction , getPointerTy ( ) ) ; +JumpTarget = getAddrGlobal ( JumpTarget , DAG , RISCVII :: MO_GOT ) ; +} +if ( ! needRISCV16Helper ) { +RegsToPass . push_front ( std :: make_pair ( T9Reg , Callee ) ) ; +JumpTarget = SDValue ( ) ; +} +} +if ( IsPICCall ) { +if ( ! InternalLinkage ) { +unsigned GPReg = IsN64 ? RISCV :: GP_64 : RISCV :: GP ; +EVT Ty = IsN64 ? MVT :: i64 : MVT :: i32 ; +RegsToPass . push_back ( std :: make_pair ( GPReg , GetGlobalReg ( DAG , Ty ) ) ) ; +} +} +SDValue InFlag ; +for ( auto Reg : RegsToPass ) { +unsigned Reg = RegsToPass [ i ] . first ; +Reg = Reg - RISCV :: I0 + RISCV :: O0 ; +Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( NumBytes , DL , true ) , DAG . getIntPtrConstant ( 0 , DL , true ) , InFlag , DL ) ; +InFlag = Chain . getValue ( 1 ) ; +} +unsigned SRetArgSize = ( hasStructRetAttr ) ? getSRetArgSize ( DAG , Callee ) : 0 ; +if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { +Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , dl , MVT :: i32 ) ; +} +if ( ExternalSymbolSDNode * E = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { +Callee = DAG . getTargetExternalSymbol ( E -> getSymbol ( ) , MVT :: i32 ) ; +} +SDVTList NodeTys = DAG . getVTList ( MVT :: Other , MVT :: Glue ) ; +SmallVector < SDValue , 8 > Ops ; +Ops . push_back ( Chain ) ; +Ops . push_back ( Callee ) ; +SmallVector < SDValue , 8 > Ops ( 1 , Chain ) ; +if ( JumpTarget . getNode ( ) ) { +Ops . push_back ( JumpTarget ) ; +} +if ( hasStructRetAttr ) { +Ops . push_back ( DAG . getTargetConstant ( SRetArgSize , MVT :: i32 ) ) ; +} +for ( auto Reg : RegsToPass ) { +Ops . push_back ( DAG . getRegister ( Reg . first , Reg . second . getValueType ( ) ) ) ; +Ops . push_back ( DAG . getRegister ( RegsToPass [ i ] . first , RegsToPass [ i ] . second . getValueType ( ) ) ) ; +unsigned Reg = RegsToPass [ i ] . first ; +Reg = Reg - RISCV :: I0 + RISCV :: O0 ; +Ops . push_back ( DAG . getRegister ( Reg , RegsToPass [ i ] . second . getValueType ( ) ) ) ; +} +const RISCVTargetMachine & TM = ( const RISCVTargetMachine & ) getTargetMachine ( ) ; +const TargetRegisterInfo * TRI = TM . getSubtargetImpl ( ) -> getRegisterInfo ( ) ; +const uint32_t * Mask = TRI -> getCallPreservedMask ( DAG . getMachineFunction ( ) , CallConv ) ; +assert ( Mask && "Missing call preserved mask for calling convention" ) ; +Ops . push_back ( DAG . getRegisterMask ( Mask ) ) ; +if ( InFlag . getNode ( ) ) { +Ops . push_back ( InFlag ) ; +} +if ( isTailCall ) { +return DAG . getNode ( RISCVISD :: TailCall , dl , MVT :: Other , & Ops [ 0 ] , Ops . size ( ) ) ; +} +Chain = DAG . getNode ( RISCVISD :: CALL , DL , NodeTys , Ops ) ; +InFlag = Chain . getValue ( 1 ) ; +Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( NumBytes , DL , true ) , DAG . getIntPtrConstant ( 0 , DL , true ) , InFlag , DL ) ; +if ( ! Ins . empty ( ) ) { +InFlag = Chain . getValue ( 1 ) ; +} +InFlag = Chain . getValue ( 1 ) ; +SmallVector < CCValAssign , 16 > RVLocs ; +CCState RVInfo ( CallConv , isVarArg , DAG . getTarget ( ) , RVLocs , * DAG . getContext ( ) ) ; +RVInfo . AnalyzeCallResult ( Ins , RetCC_RISCV32 ) ; +for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { +unsigned Reg = RVLocs [ i ] . getLocReg ( ) ; +Reg = Reg - RISCV :: I0 + RISCV :: O0 ; +Chain = DAG . getCopyFromReg ( Chain , dl , Reg , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ; +InFlag = Chain . getValue ( 2 ) ; +InVals . push_back ( Chain . getValue ( 0 ) ) ; +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/LowerConstantPool.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/LowerConstantPool.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9277a30ce937d8286924e62eb523833933e23702 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/LowerConstantPool.cpp @@ -0,0 +1,4 @@ +SDValue RISCVTargetLowering :: lowerConstantPool ( SDValue Op , SelectionDAG & DAG ) const { +ConstantPoolSDNode * N = cast < ConstantPoolSDNode > ( Op ) ; +return getAddr ( N , DAG ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/LowerFRAMEADDR.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/LowerFRAMEADDR.cpp new file mode 100644 index 0000000000000000000000000000000000000000..245811c6be8cd3241f71f05fb9a9091b9382ec35 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/LowerFRAMEADDR.cpp @@ -0,0 +1,19 @@ +SDValue RISCVTargetLowering :: lowerFRAMEADDR ( SDValue Op , SelectionDAG & DAG ) const { +const RISCVRegisterInfo & RI = * Subtarget . getRegisterInfo ( ) ; +MachineFunction & MF = DAG . getMachineFunction ( ) ; +MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; +MFI . setFrameAddressIsTaken ( true ) ; +Register FrameReg = RI . getFrameRegister ( MF ) ; +int XLenInBytes = Subtarget . getZLen ( ) / 8 ; +EVT VT = Op . getValueType ( ) ; +SDLoc DL ( Op ) ; +SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , FrameReg , VT ) ; +unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( 0 ) ) -> getZExtValue ( ) ; +for ( ; Depth > 0 ; ) { +int Offset = - ( XLenInBytes * 2 ) ; +SDValue Ptr = DAG . getNode ( ISD :: ADD , DL , VT , FrameAddr , DAG . getIntPtrConstant ( Offset , DL ) ) ; +FrameAddr = DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , Ptr , MachinePointerInfo ( ) ) ; +Depth = Depth - 1 ; +} +return FrameAddr ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/LowerFormalArguments.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/LowerFormalArguments.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c505e477ee2df0209d53865ee3454d6784270656 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/LowerFormalArguments.cpp @@ -0,0 +1,149 @@ +SDValue RISCVTargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , const SDLoc & DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { +if ( CallCConv != CallingConv :: C ) { +if ( CallCConv != CallingConv :: Fast ) { +report_fatal_error ( "Unsupported calling convention" ) ; +} +} +LLVM_DEBUG ( dbgs ( ) << "ISelDAG: Lowering formal arguments\n" ) ; +if ( isVarArg ) { +LLVM_DEBUG ( dbgs ( ) << "ISelDAG: Can't lower variadic arguments\n" ) ; +return SDValue ( ) ; +} +MachineFunction & MF = DAG . getMachineFunction ( ) ; +std :: vector < SDValue > OutChains ; +unsigned ArgsBaseOffset = 176 ; +unsigned ArgsPreserved = 64 ; +RISCVMachineFunctionInfo * FuncInfo = MF . getInfo < RISCVMachineFunctionInfo > ( ) ; +MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; +MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; +SmallVector < CCValAssign , 16 > ArgLocs ; +CCState CCInfo ( CallConv , IsVarArg , MF , ArgLocs , * DAG . getContext ( ) ) ; +CCInfo . AnalyzeFormalArguments ( Ins , CCAssignFnForCall ( CallConv , IsVarArg ) ) ; +CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; +CCInfo . AllocateStack ( ArgsPreserved , Align ( 8 ) ) ; +CCInfo . AnalyzeFormalArguments ( Ins , CC_RISCV ) ; +CCState CCInfo ( CallConv , isVarArg , MF , ArgLocs , * DAG . getContext ( ) ) ; +CCInfo . AnalyzeFormalArguments ( Ins , CCAssignFnForCall ( CallConv , isVarArg ) ) ; +Chain = DAG . getNode ( RISCVISD :: ENTRY_FLAG , DL , MVT :: Other , { Chain , DAG . getRegister ( RISCV :: a1 , MVT :: i32 ) , DAG . getTargetConstant ( 4 , DL , MVT :: i32 ) } ) ; +CCInfo . AnalyzeFormalArguments ( Ins , getCCAssignFn ( CallConv ) ) ; +if ( MFI . hasVAStart ( ) ) { +FuncInfo -> setVarArgsFrameIndex ( MFI . CreateFixedObject ( 1 , CCInfo . getNextStackOffset ( ) , true ) ) ; +} +SDValue ArgValue ; +for ( unsigned i = 0 , e = ArgLocs . size ( ) ; i != e ; ++ i ) { +CCValAssign & VA = ArgLocs [ i ] ; +SDValue ArgValue ; +bool IsF64OnRISCV = VA . getLocVT ( ) == MVT :: i32 && VA . getValVT ( ) == MVT :: f64 ; +if ( IsF64OnRISCV ) { +ArgValue = unpack64 ( DAG , Chain , VA , DL ) ; +} +if ( ! IsF64OnRISCV ) { +if ( VA . isRegLoc ( ) ) { +ArgValue = unpackFromRegLoc ( Subtarget , DAG , Chain , VA , DL ) ; +} +} +if ( ! IsF64OnRISCV ) { +if ( ! VA . isRegLoc ( ) ) { +ArgValue = unpackFromMemLoc ( DAG , Chain , VA , DL ) ; +} +} +InVals . push_back ( ArgValue ) ; +if ( VA . isRegLoc ( ) ) { +unsigned VReg = MF . addLiveIn ( VA . getLocReg ( ) , getRegClassFor ( VA . getLocVT ( ) ) ) ; +SDValue Arg = DAG . getCopyFromReg ( Chain , DL , VReg , VA . getLocVT ( ) ) ; +if ( VA . getValVT ( ) == MVT :: i32 ) { +if ( VA . needsCustom ( ) ) { +Arg = DAG . getNode ( ISD :: SRL , DL , VA . getLocVT ( ) , Arg , DAG . getConstant ( 32 , DL , MVT :: i32 ) ) ; +} +} +if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) { +Arg = DAG . getNode ( ISD :: AssertSext , DL , VA . getLocVT ( ) , Arg , DAG . getValueType ( VA . getValVT ( ) ) ) ; +} +if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) { +Arg = DAG . getNode ( ISD :: AssertZext , DL , VA . getLocVT ( ) , Arg , DAG . getValueType ( VA . getValVT ( ) ) ) ; +} +if ( VA . isExtInLoc ( ) ) { +Arg = DAG . getNode ( ISD :: TRUNCATE , DL , VA . getValVT ( ) , Arg ) ; +} +InVals . push_back ( Arg ) ; +continue ; +} +unsigned Offset = VA . getLocMemOffset ( ) + ArgsBaseOffset ; +unsigned ValSize = VA . getValVT ( ) . getSizeInBits ( ) / 8 ; +int FI = MF . getFrameInfo ( ) . CreateFixedObject ( ValSize , Offset , true ) ; +InVals . push_back ( DAG . getLoad ( VA . getValVT ( ) , DL , Chain , DAG . getFrameIndex ( FI , getPointerTy ( MF . getDataLayout ( ) ) ) , MachinePointerInfo :: getFixedStack ( MF , FI ) ) ) ; +if ( VA . isRegLoc ( ) ) { +EVT RegVT = VA . getLocVT ( ) ; +const TargetRegisterClass * RC ; +if ( RegVT == MVT :: i32 ) { +RC = & RISCV :: GPRRegClass ; +} +if ( RegVT == MVT :: f32 ) { +RC = & RISCV :: FPRRegClass ; +} +unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ; +SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , RegVT ) ; +if ( VA . getLocInfo ( ) == CCValAssign :: Full ) { +InVals . push_back ( ArgValue ) ; +} +if ( VA . getLocInfo ( ) == CCValAssign :: BCvt ) { +ArgValue = DAG . getNode ( ISD :: BITCAST , DL , VA . getValVT ( ) , ArgValue ) ; +InVals . push_back ( ArgValue ) ; +} +} +SDValue Val = DAG . getLoad ( VA . getLocInfo ( ) == CCValAssign :: AExt ? VA . getValVT ( ) : VA . getLocVT ( ) , DL , Chain , DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) ) ; +if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) { +MFI . setObjectZExt ( FI , true ) ; +Val = DAG . getNode ( ISD :: AssertZext , DL , VA . getLocVT ( ) , Val , DAG . getValueType ( VA . getValVT ( ) ) ) ; +} +if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) { +MFI . setObjectSExt ( FI , true ) ; +Val = DAG . getNode ( ISD :: AssertSext , DL , VA . getLocVT ( ) , Val , DAG . getValueType ( VA . getValVT ( ) ) ) ; +} +InVals . push_back ( DAG . getNode ( ISD :: TRUNCATE , DL , VA . getValVT ( ) , Val ) ) ; +} +if ( IsVarArg ) { +const unsigned XLenInBytes = 4 ; +const MVT XLenVT = MVT :: i32 ; +ArrayRef < MCPhysReg > ArgRegs = makeArrayRef ( GPRArgRegs ) ; +unsigned Idx = CCInfo . getFirstUnallocated ( ArgRegs ) ; +const TargetRegisterClass * RC = & RISCV :: GPRRegClass ; +MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; +MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; +RISCVMachineFunctionInfo * RISCVFI = MF . getInfo < RISCVMachineFunctionInfo > ( ) ; +int VaArgOffset ; +int VarArgsSaveSize ; +if ( ArgRegs . size ( ) == Idx ) { +VaArgOffset = CCInfo . getNextStackOffset ( ) ; +VarArgsSaveSize = 0 ; +} +if ( ArgRegs . size ( ) != Idx ) { +VarArgsSaveSize = XLenInBytes * ( ArgRegs . size ( ) - Idx ) ; +VaArgOffset = - VarArgsSaveSize ; +} +int FI = MFI . CreateFixedObject ( XLenInBytes , VaArgOffset , true ) ; +RISCVFI -> setVarArgsFrameIndex ( FI ) ; +for ( unsigned i = Idx ; i < ArgRegs . size ( ) ; ++ i , VaArgOffset += XLenInBytes ) { +const Register Reg = RegInfo . createVirtualRegister ( RC ) ; +RegInfo . addLiveIn ( ArgRegs [ i ] , Reg ) ; +SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , XLenVT ) ; +FI = MFI . CreateFixedObject ( XLenInBytes , VaArgOffset , true ) ; +SDValue PtrOff = DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) ; +SDValue Store = DAG . getStore ( Chain , DL , ArgValue , PtrOff , MachinePointerInfo :: getFixedStack ( MF , FI ) ) ; +cast < StoreSDNode > ( Store . getNode ( ) ) -> getMemOperand ( ) -> setValue ( ( Value * ) nullptr ) ; +OutChains . push_back ( Store ) ; +} +RISCVFI -> setVarArgsSaveSize ( VarArgsSaveSize ) ; +} +if ( ! OutChains . empty ( ) ) { +OutChains . push_back ( Chain ) ; +Chain = DAG . getNode ( ISD :: TokenFactor , DL , MVT :: Other , OutChains ) ; +} +if ( ! IsVarArg ) { +return Chain ; +} +unsigned ArgOffset = ArgLocs . size ( ) * 8 ; +RISCVMachineFunctionInfo * FuncInfo = MF . getInfo < RISCVMachineFunctionInfo > ( ) ; +FuncInfo -> setVarArgsFrameOffset ( ArgOffset + ArgsBaseOffset ) ; +return Chain ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/LowerGlobalAddress.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/LowerGlobalAddress.cpp new file mode 100644 index 0000000000000000000000000000000000000000..099b20dc0e1d28870c2af0c72835bcad698b4604 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/LowerGlobalAddress.cpp @@ -0,0 +1,14 @@ +SDValue RISCVTargetLowering :: lowerGlobalAddress ( SDValue Op , SelectionDAG & DAG ) const { +SDLoc DL ( Op ) ; +EVT Ty = Op . getValueType ( ) ; +GlobalAddressSDNode * N = cast < GlobalAddressSDNode > ( Op ) ; +int64_t Offset = N -> getOffset ( ) ; +MVT XLenVT = Subtarget . getXLenVT ( ) ; +const GlobalValue * GV = N -> getGlobal ( ) ; +bool IsLocal = getTargetMachine ( ) . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ; +SDValue Addr = getAddr ( N , DAG , IsLocal ) ; +if ( Offset ) { +return DAG . getNode ( ISD :: ADD , DL , Ty , Addr , DAG . getConstant ( Offset , DL , XLenVT ) ) ; +} +return Addr ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/LowerGlobalTLSAddress.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/LowerGlobalTLSAddress.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3076140ae5cb9cc92ed12cb26acc0794cd2f8726 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/LowerGlobalTLSAddress.cpp @@ -0,0 +1,28 @@ +SDValue RISCVTargetLowering :: lowerGlobalTLSAddress ( SDValue Op , SelectionDAG & DAG ) const { +SDLoc DL ( Op ) ; +EVT Ty = Op . getValueType ( ) ; +GlobalAddressSDNode * N = cast < GlobalAddressSDNode > ( Op ) ; +int64_t Offset = N -> getOffset ( ) ; +MVT XLenVT = Subtarget . getXLenVT ( ) ; +TLSModel :: Model Model = getTargetMachine ( ) . getTLSModel ( N -> getGlobal ( ) ) ; +if ( DAG . getMachineFunction ( ) . getFunction ( ) . getCallingConv ( ) == CallingConv :: GHC ) { +report_fatal_error ( "In GHC calling convention TLS is not supported" ) ; +} +SDValue Addr ; +if ( Model == TLSModel :: LocalExec ) { +Addr = getStaticTLSAddr ( N , DAG , false ) ; +} +if ( Model == TLSModel :: InitialExec ) { +Addr = getStaticTLSAddr ( N , DAG , true ) ; +} +if ( Model == TLSModel :: LocalDynamic ) { +Addr = getDynamicTLSAddr ( N , DAG ) ; +} +if ( Model == TLSModel :: GeneralDynamic ) { +Addr = getDynamicTLSAddr ( N , DAG ) ; +} +if ( Offset != 0 ) { +return DAG . getNode ( ISD :: ADD , DL , Ty , Addr , DAG . getConstant ( Offset , DL , XLenVT ) ) ; +} +return Addr ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/LowerINTRINSIC_WO_CHAIN.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/LowerINTRINSIC_WO_CHAIN.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f46087a0fc61e5030738b72d66d21da8d9c596f6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/LowerINTRINSIC_WO_CHAIN.cpp @@ -0,0 +1,29 @@ +SDValue RISCVTargetLowering :: LowerINTRINSIC_WO_CHAIN ( SDValue Op , SelectionDAG & DAG ) const { +MVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; +unsigned IntNo = cast < ConstantSDNode > ( Op . getOperand ( 0 ) ) -> getZExtValue ( ) ; +DebugLoc DL = Op . getDebugLoc ( ) ; +SDLoc DL ( Op ) ; +SmallVector < SDValue , 16 > Ops ( std :: next ( Op -> op_begin ( ) ) , Op -> op_end ( ) ) ; +unsigned Size = Ops . size ( ) ; +bool SmallTuple = Size <= RISCVTargetMachine :: SmallTupleLimit ; +Ops . push_back ( DAG . getConstant ( Size , DL , MVT :: i257 , SmallTuple ) ) ; +unsigned Cmd = SmallTuple ? RISCVISD :: TUPLE : RISCVISD :: TUPLEVAR ; +MachineFunction & MF = DAG . getMachineFunction ( ) ; +MVT VT = Op . getSimpleValueType ( ) ; +const RISCVTargetMachine * TM = static_cast < const RISCVTargetMachine * > ( & DAG . getTarget ( ) ) ; +TM -> getStrList ( ) -> push_back ( std :: string ( ( Twine ( "GCC_except_table" ) + Twine ( MF . getFunctionNumber ( ) ) ) . str ( ) ) ) ; +SDValue Addr = DAG . getTargetExternalSymbol ( TM -> getStrList ( ) -> back ( ) . c_str ( ) , VT , 0 ) ; +if ( isPositionIndependent ( ) ) { +Addr = makeHiLoPair ( Addr , RISCVMCExpr :: VK_RISCV_GOTOFF_HI32 , RISCVMCExpr :: VK_RISCV_GOTOFF_LO32 , DAG ) ; +SDValue GlobalBase = DAG . getNode ( RISCVISD :: GLOBAL_BASE_REG , DL , VT ) ; +return DAG . getNode ( ISD :: ADD , DL , VT , GlobalBase , Addr ) ; +} +EVT VT = Op . getValueType ( ) ; +const RISCVTargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; +MVT PtrVT = TLI . getPointerTy ( DAG . getDataLayout ( ) ) ; +auto & Context = MF . getMMI ( ) . getContext ( ) ; +MCSymbol * S = Context . getOrCreateSymbol ( Twine ( "GCC_except_table" ) + Twine ( MF . getFunctionNumber ( ) ) ) ; +EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; +return DAG . getRegister ( RISCV :: G7 , PtrVT ) ; +return SDValue ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/LowerINTRINSIC_W_CHAIN.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/LowerINTRINSIC_W_CHAIN.cpp new file mode 100644 index 0000000000000000000000000000000000000000..37677d8bd163ef48e9e50077bb00dfee07e19686 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/LowerINTRINSIC_W_CHAIN.cpp @@ -0,0 +1,68 @@ +SDValue RISCVTargetLowering :: LowerINTRINSIC_W_CHAIN ( SDValue Op , SelectionDAG & DAG ) const { +unsigned IntNo = cast ( Op . getOperand ( 1 ) ) . getZExtValue ( ) ; +if ( IntNo == Intrinsic :: RISCV_vleff ) { +return lowerDSPIntr ( Op , DAG , RISCVISD :: EXTP ) ; +} +if ( IntNo == Intrinsic :: RISCV_vleff_mask ) { +return lowerDSPIntr ( Op , DAG , RISCVISD :: EXTPDP ) ; +} +if ( IntNo == Intrinsic :: RISCV_vlseg8ff ) { +return lowerDSPIntr ( Op , DAG , RISCVISD :: EXTR_W ) ; +} +if ( IntNo == Intrinsic :: RISCV_vlseg7ff ) { +return lowerDSPIntr ( Op , DAG , RISCVISD :: EXTR_R_W ) ; +} +if ( IntNo == Intrinsic :: RISCV_vlseg6ff ) { +return lowerDSPIntr ( Op , DAG , RISCVISD :: EXTR_RS_W ) ; +} +if ( IntNo == Intrinsic :: RISCV_vlseg5ff ) { +return lowerDSPIntr ( Op , DAG , RISCVISD :: EXTR_S_H ) ; +} +if ( IntNo == Intrinsic :: RISCV_vlseg4ff ) { +return lowerDSPIntr ( Op , DAG , RISCVISD :: MTHLIP ) ; +} +if ( IntNo == Intrinsic :: RISCV_vlseg2ff ) { +return lowerDSPIntr ( Op , DAG , RISCVISD :: MULSAQ_S_W_PH ) ; +} +if ( IntNo == Intrinsic :: RISCV_vlseg8ff_mask ) { +return lowerDSPIntr ( Op , DAG , RISCVISD :: MAQ_S_W_PHL ) ; +} +if ( IntNo == Intrinsic :: RISCV_vlseg7ff_mask ) { +return lowerDSPIntr ( Op , DAG , RISCVISD :: MAQ_S_W_PHR ) ; +} +if ( IntNo == Intrinsic :: RISCV_vlseg6ff_mask ) { +return lowerDSPIntr ( Op , DAG , RISCVISD :: MAQ_SA_W_PHL ) ; +} +if ( IntNo == Intrinsic :: RISCV_vlseg5ff_mask ) { +return lowerDSPIntr ( Op , DAG , RISCVISD :: MAQ_SA_W_PHR ) ; +} +if ( IntNo == Intrinsic :: RISCV_vlseg4ff_mask ) { +return lowerDSPIntr ( Op , DAG , RISCVISD :: DPAQ_S_W_PH ) ; +} +if ( IntNo == Intrinsic :: RISCV_vlseg3ff_mask ) { +return lowerDSPIntr ( Op , DAG , RISCVISD :: DPSQ_S_W_PH ) ; +} +if ( IntNo == Intrinsic :: RISCV_vlseg2ff_mask ) { +auto Node = cast < MemIntrinsicSDNode > ( Op . getNode ( ) ) ; +SDLoc DL ( Op ) ; +SDValue Chain = Node -> getChain ( ) ; +SDValue Dst = Op . getOperand ( 2 ) ; +SDValue Val = Op . getOperand ( 3 ) ; +Val = DAG . getAnyExtOrTrunc ( Val , DL , MVT :: i64 ) ; +SDValue Size = Op . getOperand ( 4 ) ; +auto Alignment = Node -> getMemOperand ( ) -> getAlign ( ) ; +bool IsVol = Node -> isVolatile ( ) ; +auto DstPtrInfo = Node -> getPointerInfo ( ) ; +const auto & SDI = static_cast < const RISCVSelectionDAGInfo & > ( DAG . getSelectionDAGInfo ( ) ) ; +SDValue MS = SDI . EmitMOPS ( RISCVISD :: MOPS_MEMSET_TAGGING , DAG , DL , Chain , Dst , Val , Size , Alignment , IsVol , DstPtrInfo , MachinePointerInfo { } ) ; +} +unsigned Opcode ; +unsigned CCValid ; +if ( isIntrinsicWithCCAndChain ( Op , Opcode , CCValid ) ) { +SDNode * Node = emitIntrinsicWithCCAndChain ( DAG , Op , Opcode ) ; +SDValue CC = getCCResult ( DAG , SDValue ( Node , 0 ) ) ; +DAG . ReplaceAllUsesOfValueWith ( SDValue ( Op . getNode ( ) , 0 ) , CC ) ; +return SDValue ( ) ; +} +return SDValue ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/LowerJumpTable.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/LowerJumpTable.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9ff4576b39126b5c55de9dc131764c29465ff28e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/LowerJumpTable.cpp @@ -0,0 +1,4 @@ +SDValue RISCVTargetLowering :: lowerJumpTable ( SDValue Op , SelectionDAG & DAG ) const { +JumpTableSDNode * N = cast < JumpTableSDNode > ( Op ) ; +return getAddr ( N , DAG ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/LowerOperation.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/LowerOperation.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fb418e19da755787e5af2f304c21590fbc497b9f --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/LowerOperation.cpp @@ -0,0 +1,60 @@ +SDValue RISCVTargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { +if ( Op . getOpcode ( ) == ISD :: FRAMEADDR ) { +return LowerFrameIndex ( Op , DAG ) ; +} +if ( Op . getOpcode ( ) == ISD :: GlobalAddress ) { +return LowerGlobalAddress ( Op , DAG ) ; +} +if ( Op . getOpcode ( ) == ISD :: JumpTable ) { +return LowerJumpTable ( Op , DAG ) ; +} +if ( Op . getOpcode ( ) == ISD :: BlockAddress ) { +return lowerBlockAddress ( Op , DAG ) ; +} +if ( Op . getOpcode ( ) == ISD :: ConstantPool ) { +return lowerConstantPool ( Op , DAG ) ; +} +if ( Op . getOpcode ( ) == ISD :: GlobalTLSAddress ) { +return lowerGlobalTLSAddress ( Op , DAG ) ; +} +if ( Op . getOpcode ( ) == ISD :: SELECT ) { +return lowerSELECT ( Op , DAG ) ; +} +if ( Op . getOpcode ( ) == ISD :: VASTART ) { +return lowerVASTART ( Op , DAG ) ; +} +if ( Op . getOpcode ( ) == ISD :: RETURNADDR ) { +return lowerRETURNADDR ( Op , DAG ) ; +} +if ( Op . getOpcode ( ) == ISD :: SHL_PARTS ) { +return lowerShiftLeftParts ( Op , DAG ) ; +} +if ( Op . getOpcode ( ) == ISD :: SRA_PARTS ) { +return lowerShiftRightParts ( Op , DAG , true ) ; +} +if ( Op . getOpcode ( ) == ISD :: SRL_PARTS ) { +return lowerShiftRightParts ( Op , DAG , false ) ; +} +if ( Op . getOpcode ( ) == ISD :: INTRINSIC_WO_CHAIN ) { +return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; +} +if ( Op . getOpcode ( ) == ISD :: INTRINSIC_W_CHAIN ) { +return LowerINTRINSIC_W_CHAIN ( Op , DAG ) ; +} +if ( Op . getOpcode ( ) == ISD :: ANY_EXTEND ) { +return lowerVectorMaskExt ( Op , DAG , 1 ) ; +} +if ( Op . getOpcode ( ) == ISD :: ZERO_EXTEND ) { +return lowerVectorMaskExt ( Op , DAG , 1 ) ; +} +if ( Op . getOpcode ( ) == ISD :: SIGN_EXTEND ) { +return lowerVectorMaskExt ( Op , DAG , - 1 ) ; +} +if ( Op . getOpcode ( ) == ISD :: SPLAT_VECTOR ) { +return lowerSPLATVECTOR ( Op , DAG ) ; +} +if ( Op . getOpcode ( ) == ISD :: INSERT_VECTOR_ELT ) { +return lowerINSERT_VECTOR_ELT ( Op , DAG ) ; +} +report_fatal_error ( "unimplemented operand" ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/LowerRETURNADDR.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/LowerRETURNADDR.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b3b5430543858f3f0f6180d7af18be861bf3d63b --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/LowerRETURNADDR.cpp @@ -0,0 +1,20 @@ +SDValue RISCVTargetLowering :: lowerRETURNADDR ( SDValue Op , SelectionDAG & DAG ) const { +const RISCVRegisterInfo & RI = * Subtarget . getRegisterInfo ( ) ; +MachineFunction & MF = DAG . getMachineFunction ( ) ; +MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; +MFI . setReturnAddressIsTaken ( true ) ; +int XLenInBytes = Subtarget . getZLen ( ) / 8 ; +if ( verifyReturnAddressArgumentIsConstant ( Op , DAG ) ) { +return SDValue ( ) ; +} +EVT VT = Op . getValueType ( ) ; +SDLoc DL ( Op ) ; +unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( 0 ) ) -> getZExtValue ( ) ; +if ( Depth ) { +int Off = - XLenInBytes ; +SDValue FrameAddr = lowerFRAMEADDR ( Op , DAG ) ; +SDValue Offset = DAG . getConstant ( Off , DL , VT ) ; +return DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , DAG . getNode ( ISD :: ADD , DL , VT , FrameAddr , Offset ) , MachinePointerInfo ( ) ) ; +} +return DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , Reg , XLenVT ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/LowerReturn.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/LowerReturn.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2683f04c5a9650f040810fc7a7c4b03b45b483c4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/LowerReturn.cpp @@ -0,0 +1,155 @@ +SDValue RISCVTargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SDLoc & DL , SelectionDAG & DAG ) const { +report_fatal_error ( "VarArg not supported" ) ; +} +MachineFunction & MF = DAG . getMachineFunction ( ) ; +SmallVector < CCValAssign , 16 > RVLocs ; +CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; +CCInfo . AnalyzeReturn ( Outs , RetCC_RISCV ) ; +if ( DAG . getMachineFunction ( ) . getRegInfo ( ) . liveout_empty ( ) ) { +for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) +if ( RVLocs [ i ] . isRegLoc ( ) ) { +DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ; +} +for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { +if ( RVLocs [ i ] . isRegLoc ( ) ) { +DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ; +} +} +} +if ( MF . getRegInfo ( ) . liveout_empty ( ) ) { +for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { +if ( RVLocs [ i ] . isRegLoc ( ) ) { +MF . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ; +} +} +} +SDValue Flag ; +analyzeOutputArgs ( CCInfo , Outs , CC_RISCV ) ; +analyzeOutputArgs ( DAG . getMachineFunction ( ) , CCInfo , Outs , true , nullptr ) ; +SDValue Glue ; +SmallVector < SDValue , 4 > RetOps ( 1 , Chain ) ; +RetOps . push_back ( SDValue ( ) ) ; +for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { +SDValue Val = OutVals [ i ] ; +CCValAssign & VA = RVLocs [ i ] ; +SDValue ResValue = Outs [ i ] . Val ; +assert ( VA . isRegLoc ( ) && "Can only return in registers!" ) ; +if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) { +ResValue = DAG . getNode ( ISD :: SIGN_EXTEND , dl , VA . getLocVT ( ) , ResValue ) ; +} +if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) { +ResValue = DAG . getNode ( ISD :: ZERO_EXTEND , dl , VA . getLocVT ( ) , ResValue ) ; +} +if ( VA . getLocInfo ( ) == CCValAssign :: AExt ) { +ResValue = DAG . getNode ( ISD :: ANY_EXTEND , dl , VA . getLocVT ( ) , ResValue ) ; +} +Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; +Flag = Chain . getValue ( 1 ) ; +Glue = Chain . getValue ( 1 ) ; +RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; +bool IsF64OnRISCV = VA . getLocVT ( ) == MVT :: i32 && VA . getValVT ( ) == MVT :: f64 ; +if ( IsF64OnRISCV ) { +SDValue Split64 = DAG . getNode ( RISCVISD :: BITCAST_TO_LOHI , DL , DAG . getVTList ( MVT :: i32 , MVT :: i32 ) , Val ) ; +SDValue Lo = Split64 . getValue ( 0 ) ; +SDValue Hi = Split64 . getValue ( 1 ) ; +Register RegLo = VA . getLocReg ( ) ; +assert ( RegLo < RISCV :: R31 && "Invalid register pair" ) ; +Register RegHi = RegLo + 1 ; +Chain = DAG . getCopyToReg ( Chain , DL , RegLo , Lo , Glue ) ; +Glue = Chain . getValue ( 1 ) ; +RetOps . push_back ( DAG . getRegister ( RegLo , MVT :: i32 ) ) ; +Chain = DAG . getCopyToReg ( Chain , DL , RegHi , Hi , Glue ) ; +Glue = Chain . getValue ( 1 ) ; +RetOps . push_back ( DAG . getRegister ( RegHi , MVT :: i32 ) ) ; +} +if ( ! IsF64OnRISCV ) { { +} +RetOps [ 0 ] = Chain ; +if ( Glue . getNode ( ) ) { +RetOps . push_back ( Glue ) ; +} +if ( DAG . getMachineFunction ( ) . getFunction ( ) . hasFnAttribute ( "interrupt" ) ) { +return DAG . getNode ( RISCVISD :: NIR , DL , MVT :: Other , RetOps ) ; +} +return DAG . getNode ( RISCVISD :: RET , DL , MVT :: Other , RetOps ) ; +if ( VA . getLocVT ( ) != MVT :: i32 ) { +Val = convertValVTToLocVT ( DAG , Val , VA , DL ) ; +Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Val , Glue ) ; +Glue = Chain . getValue ( 1 ) ; +RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; +} +if ( VA . getValVT ( ) != MVT :: f64 ) { +Val = convertValVTToLocVT ( DAG , Val , VA , DL ) ; +Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Val , Glue ) ; +Glue = Chain . getValue ( 1 ) ; +RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; +} +} +if ( DAG . getMachineFunction ( ) . getFunction ( ) . hasStructRetAttr ( ) ) { +MachineFunction & MF = DAG . getMachineFunction ( ) ; +RISCVMachineFunctionInfo * RISCVMFI = MF . getInfo < RISCVMachineFunctionInfo > ( ) ; +Register Reg = RISCVMFI -> getSRetReturnReg ( ) ; +Chain = DAG . getCopyToReg ( Chain , DL , RISCV :: RV , Val , Flag ) ; +Flag = Chain . getValue ( 1 ) ; +RetOps . push_back ( DAG . getRegister ( RISCV :: RV , getPointerTy ( DAG . getDataLayout ( ) ) ) ) ; +} +if ( MF . getFunction ( ) . hasStructRetAttr ( ) ) { +RISCVMachineFunctionInfo * FuncInfo = MF . getInfo < RISCVMachineFunctionInfo > ( ) ; +unsigned Reg = FuncInfo -> getSRetReturnReg ( ) ; +if ( ! Reg ) { +llvm_unreachable ( "sret virtual register not created in entry block" ) ; +} +SDValue Val = DAG . getCopyFromReg ( Chain , dl , Reg , getPointerTy ( DAG . getDataLayout ( ) ) ) ; +unsigned R12 = RISCV :: R12 ; +Chain = DAG . getCopyToReg ( Chain , dl , R12 , Val , Flag ) ; +Flag = Chain . getValue ( 1 ) ; +RetOps . push_back ( DAG . getRegister ( R12 , getPointerTy ( DAG . getDataLayout ( ) ) ) ) ; +} +unsigned Opc = ( CallConv == CallingConv :: RISCV_INTR ? RISCVISD :: RETI_FLAG : RISCVISD :: RET_FLAG ) ; +unsigned RetAddrOffset = 8 ; +if ( MF . getFunction ( ) -> hasStructRetAttr ( ) ) { +RISCVMachineFunctionInfo * SFI = MF . getInfo < RISCVMachineFunctionInfo > ( ) ; +RISCVMachineFunctionInfo * FI = MF . getInfo < RISCVMachineFunctionInfo > ( ) ; +if ( ! Reg ) { +llvm_unreachable ( "sret virtual register not created in the entry block" ) ; +} +Chain = DAG . getCopyToReg ( Chain , dl , RISCV :: I0 , Val , Flag ) ; +Chain = DAG . getCopyToReg ( Chain , DL , RISCV :: R0 , Val , Flag ) ; +Flag = Chain . getValue ( 1 ) ; +RetOps . push_back ( DAG . getRegister ( RISCV :: I0 , getPointerTy ( ) ) ) ; +RetAddrOffset = 12 ; +if ( MF . getRegInfo ( ) . liveout_empty ( ) ) { +MF . getRegInfo ( ) . addLiveOut ( RISCV :: R0 ) ; +} +} +RetOps [ 0 ] = Chain ; +unsigned Opc = RISCVISD :: RET_FLAG ; +if ( DAG . getMachineFunction ( ) . getFunction ( ) -> hasStructRetAttr ( ) ) { +MachineFunction & MF = DAG . getMachineFunction ( ) ; +RISCVFunctionInfo * RISCVFI = MF . getInfo < RISCVFunctionInfo > ( ) ; +unsigned Reg = RISCVFI -> getSRetReturnReg ( ) ; +if ( ! Reg ) { +llvm_unreachable ( "sret virtual register not created in the entry block" ) ; +} +SDValue Val = DAG . getCopyFromReg ( Chain , dl , Reg , getPointerTy ( ) ) ; +Chain = DAG . getCopyToReg ( Chain , dl , RISCV :: V0 , Val , Flag ) ; +Flag = Chain . getValue ( 1 ) ; +} +RetOps [ 1 ] = DAG . getConstant ( RetAddrOffset , MVT :: i32 ) ; +SDValue LinkReg = DAG . getRegister ( RISCV :: LinkRegister , getPointerTy ( ) ) ; +if ( Flag . getNode ( ) ) { +RetOps . push_back ( Flag ) ; +return DAG . getNode ( RISCVISD :: Ret , dl , MVT :: Other , Chain , DAG . getRegister ( RISCV :: RA , MVT :: i32 ) , Flag ) ; +} +if ( Glue . getNode ( ) ) { +RetOps . push_back ( Glue ) ; +} +const Function & Func = DAG . getMachineFunction ( ) . getFunction ( ) ; +if ( Func . hasFnAttribute ( "interrupt" ) ) { +llvm_unreachable ( "interrupts not supported" ) ; +} +if ( ! Flag . getNode ( ) ) { +return DAG . getNode ( RISCVISD :: Ret , dl , MVT :: Other , Chain , DAG . getRegister ( RISCV :: RA , MVT :: i32 ) ) ; +return DAG . getNode ( T64ISD :: JRP , DL , MVT :: Other , Chain , LinkReg ) ; +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/LowerVASTART.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/LowerVASTART.cpp new file mode 100644 index 0000000000000000000000000000000000000000..20003795fc4bdfdab7940187c54033e0ec4e23da --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/LowerVASTART.cpp @@ -0,0 +1,8 @@ +SDValue RISCVTargetLowering :: lowerVASTART ( SDValue Op , SelectionDAG & DAG ) const { +MachineFunction & MF = DAG . getMachineFunction ( ) ; +const RISCVMachineFunctionInfo * FuncInfo = MF . getInfo < RISCVMachineFunctionInfo > ( ) ; +SDLoc DL ( Op ) ; +SDValue FI = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , getPointerTy ( MF . getDataLayout ( ) ) ) ; +const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( 2 ) ) -> getValue ( ) ; +return DAG . getStore ( Op . getOperand ( 0 ) , DL , FI , Op . getOperand ( 1 ) , MachinePointerInfo ( SV ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/NodeType.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/NodeType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..16f1222fb7662f8a978a0205d7d36b3d76930d7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/NodeType.cpp @@ -0,0 +1,43 @@ +enum NodeType : unsigned { +FIRST_NUMBER = ISD :: BUILTIN_OP_END , +RET_FLAG , +URET_FLAG , +SRET_FLAG , +MRET_FLAG , +CALL , +SELECT_CC , +BuildPairF64 , +SplitF64 , +TAIL , +SLLW , +SRAW , +SRLW , +DIVW , +DIVUW , +REMUW , +ROLW , +RORW , +FSRW , +FSLW , +FMV_H_X , +FMV_X_ANYEXTH , +FMV_W_X_RV64 , +FMV_X_ANYEXTW_RV64 , +READ_CYCLE_WIDE , +GREVI , +GREVIW , +GORCI , +GORCIW , +VMV_X_S , +SPLAT_VECTOR_I64 , +READ_VLENB , +TRUNCATE_VECTOR , +VLEFF , +VLEFF_MASK , +VLSEGFF , +VLSEGFF_MASK , +READ_VL , +VSLIDEUP , +VSLIDEDOWN , +VID , +} ; \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/PerformDAGCombine.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/PerformDAGCombine.cpp new file mode 100644 index 0000000000000000000000000000000000000000..684c4ba88c4f46a2e998da28d478370720844eeb --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/PerformDAGCombine.cpp @@ -0,0 +1,42 @@ +SDValue RISCVTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { +if ( N -> getOpcode ( ) == RISCVISD :: SplitF64 ) { +} +if ( N -> getOpcode ( ) == RISCVISD :: SLLW ) { +} +if ( N -> getOpcode ( ) == RISCVISD :: SRAW ) { +} +if ( N -> getOpcode ( ) == RISCVISD :: SRLW ) { +} +if ( N -> getOpcode ( ) == RISCVISD :: ROLW ) { +} +SelectionDAG & DAG = DCI . DAG ; +SDValue Val ; +if ( N -> getOpcode ( ) == RISCVISD :: RORW ) { +} +if ( N -> getOpcode ( ) == RISCVISD :: FSLW ) { +} +if ( N -> getOpcode ( ) == RISCVISD :: FSRW ) { +} +if ( N -> getOpcode ( ) == RISCVISD::GREVIW ) { +} +if ( N -> getOpcode ( ) == RISCVISD :: GORCIW ) { +} +if ( N -> getOpcode ( ) == RISCVISD::FMV_X_ANYEXTW_RV64 ) { +} +if ( N -> getOpcode ( ) == RISCVISD::GREVI ) { +Val = performSETCCCombine ( N , DAG ) ; +} +if ( Val . getNode ( ) ) { +return Val ; +} +if ( N -> getOpcode ( ) == RISCVISD :: GORCI ) { +return combineBSWAP ( N , DCI ) ; +} +if ( N -> getOpcode ( ) == RISCVISD :: OR ) { +} +if ( N -> getOpcode ( ) == RISCVISD :: SELECT_CC ) { +} +if ( N -> getOpcode ( ) == RISCVISD :: SETCC ) { +} +return SDValue ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/ReplaceNodeResults.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/ReplaceNodeResults.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e2eb1735ae1a6b6f2f92ad84c2933ec7f689b94f --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/ReplaceNodeResults.cpp @@ -0,0 +1,211 @@ +void RISCVTargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { +SDValue Res ; +if ( N -> getOpcode ( ) == ISD :: STRICT_FP_TO_SINT ) { +ExpandREAD_REGISTER ( N , Results , DAG ) ; +if ( Res . getNode ( ) ) { +Results . push_back ( Res ) ; +} +return ; +} +if ( N -> getOpcode ( ) == ISD :: STRICT_FP_TO_UINT ) { +Res = ExpandBITCAST ( N , DAG , Subtarget ) ; +if ( Res . getNode ( ) ) { +Results . push_back ( Res ) ; +} +return ; +} +if ( N -> getOpcode ( ) == ISD :: FP_TO_SINT ) { +ReplaceBITCASTResults ( N , Results , DAG ) ; +if ( Res . getNode ( ) ) { +Results . push_back ( Res ) ; +} +return ; +} +if ( N -> getOpcode ( ) == ISD :: FP_TO_UINT ) { +Results . push_back ( LowerVECREDUCE ( SDValue ( N , 0 ) , DAG ) ) ; +if ( Res . getNode ( ) ) { +Results . push_back ( Res ) ; +} +return ; +} +if ( N -> getOpcode ( ) == ISD :: READCYCLECOUNTER ) { +Results . push_back ( LowerVECREDUCE ( SDValue ( N , 0 ) , DAG ) ) ; +if ( Res . getNode ( ) ) { +Results . push_back ( Res ) ; +} +return ; +} +if ( N -> getOpcode ( ) == ISD :: ADD ) { +Results . push_back ( LowerVECREDUCE ( SDValue ( N , 0 ) , DAG ) ) ; +Res = LowerREM ( N , DAG ) ; +if ( Res . getNode ( ) ) { +Results . push_back ( Res ) ; +} +return ; +} +if ( N -> getOpcode ( ) == ISD :: SUB ) { +Results . push_back ( LowerVECREDUCE ( SDValue ( N , 0 ) , DAG ) ) ; +Res = LowerREM ( N , DAG ) ; +if ( Res . getNode ( ) ) { +Results . push_back ( Res ) ; +} +return ; +} +if ( N -> getOpcode ( ) == ISD :: FSHL ) { +Results . push_back ( LowerVECREDUCE ( SDValue ( N , 0 ) , DAG ) ) ; +Res = LowerDivRem ( SDValue ( N , 0 ) , DAG ) ; +Results . push_back ( Res . getValue ( 0 ) ) ; +Results . push_back ( Res . getValue ( 1 ) ) ; +return ; +} +if ( N -> getOpcode ( ) == ISD :: MUL ) { +Results . push_back ( LowerCTPOP ( SDValue ( N , 0 ) , DAG ) ) ; +Res = LowerDivRem ( SDValue ( N , 0 ) , DAG ) ; +Results . push_back ( Res . getValue ( 0 ) ) ; +Results . push_back ( Res . getValue ( 1 ) ) ; +return ; +} +if ( N -> getOpcode ( ) == ISD :: SHL ) { +ReplaceReductionResults ( N , Results , DAG , ISD :: ADD , RISCVISD :: SADDV ) ; +Res = LowerSADDSUBSAT ( SDValue ( N , 0 ) , DAG , Subtarget ) ; +Results . push_back ( Res ) ; +return ; +} +if ( N -> getOpcode ( ) == ISD :: SRA ) { +ReplaceReductionResults ( N , Results , DAG , ISD :: ADD , RISCVISD :: UADDV ) ; +Res = LowerSADDSUBSAT ( SDValue ( N , 0 ) , DAG , Subtarget ) ; +Results . push_back ( Res ) ; +return ; +} +if ( N -> getOpcode ( ) == ISD :: SRL ) { +ReplaceReductionResults ( N , Results , DAG , ISD :: SMIN , RISCVISD :: SMINVV ) ; +ReplaceREADCYCLECOUNTER ( N , Results , DAG , Subtarget ) ; +Results . push_back ( Res ) ; +return ; +} +if ( N -> getOpcode ( ) == ISD :: ROTL ) { +ReplaceReductionResults ( N , Results , DAG , ISD :: UMINV , RISCVISD :: UMINV ) ; +return ; +return ExpandDIV_Windows ( SDValue ( N , 0 ) , DAG , N -> getOpcode ( ) == ISD :: SDIV , Results ) ; +} +if ( N -> getOpcode ( ) == ISD :: ROTR ) { +return ; +} +if ( N -> getOpcode ( ) == ISD :: SDIV ) { +ReplaceReductionResults ( N , Results , DAG , ISD :: UMAX , RISCVISD :: UMAXVV ) ; +return ; +} +if ( N -> getOpcode ( ) == ISD :: UDIV ) { +if ( N -> getOperand ( 0 ) . getValueType ( ) != MVT :: f128 ) { +return ; +} +if ( N -> getValueType ( 0 ) != MVT :: i64 ) { +return ; +} +libCall = RTLIB :: FPTOSINT_F128_I64 ; +Results . push_back ( LowerF128Op ( SDValue ( N , 0 ) , DAG , getLibcallName ( libCall ) , 1 ) ) ; +return ; +} +if ( N -> getOpcode ( ) == ISD :: UREM ) { +if ( ! LoadNode -> isVolatile ( ) ) { +return ; +} +if ( LoadNode -> getMemoryVT ( ) != MVT :: i128 ) { +return ; +} +SDValue Result = DAG . getMemIntrinsicNode ( RISCVISD :: LDP , SDLoc ( N ) , DAG . getVTList ( { MVT :: i64 , MVT :: i64 , MVT :: Other } ) , { LoadNode -> getChain ( ) , LoadNode -> getBasePtr ( ) } , LoadNode -> getMemoryVT ( ) , LoadNode -> getMemOperand ( ) ) ; +SDValue Pair = DAG . getNode ( ISD :: BUILD_PAIR , SDLoc ( N ) , MVT :: i128 , Result . getValue ( 0 ) , Result . getValue ( 1 ) ) ; +Results . append ( { Pair , Result . getValue ( 2 ) } ) ; +if ( N -> getOperand ( 0 ) . getValueType ( ) != MVT :: f128 ) { +return ; +} +if ( N -> getValueType ( 0 ) != MVT :: i64 ) { +return ; +} +libCall = RTLIB :: FPTOUINT_F128_I64 ; +Results . push_back ( LowerF128Op ( SDValue ( N , 0 ) , DAG , getLibcallName ( libCall ) , 1 ) ) ; +return ; +} +if ( N -> getOpcode ( ) == ISD :: BITCAST ) { +ReplaceCMP_SWAP_128Results ( N , Results , DAG , Subtarget ) ; +ReplaceExtractSubVectorResults ( N , Results , DAG ) ; +SDValue Lo = DAG . getCopyFromReg ( N -> getOperand ( 0 ) , DL , RISCV :: ASR23 , MVT :: i32 ) ; +SDValue Hi = DAG . getCopyFromReg ( Lo , DL , RISCV :: G0 , MVT :: i32 ) ; +SDValue Ops [ ] = { Lo , Hi } ; +SDValue Pair = DAG . getNode ( ISD :: BUILD_PAIR , DL , MVT :: i64 , Ops ) ; +Results . push_back ( Pair ) ; +return ; +} +if ( N -> getOpcode ( ) == RISCVISD::GREVI ) { +LoadSDNode * LoadNode = cast < LoadSDNode > ( N ) ; +if ( ! LoadNode -> isVolatile ( ) ) { +return ; +} +if ( LoadNode -> getMemoryVT ( ) != MVT :: i128 ) { +return ; +} +SDValue Result = DAG . getMemIntrinsicNode ( RISCVISD :: LDP , SDLoc ( N ) , DAG . getVTList ( { MVT :: i64 , MVT :: i64 , MVT :: Other } ) , { LoadNode -> getChain ( ) , LoadNode -> getBasePtr ( ) } , LoadNode -> getMemoryVT ( ) , LoadNode -> getMemOperand ( ) ) ; +SDValue Pair = DAG . getNode ( ISD :: BUILD_PAIR , SDLoc ( N ) , MVT :: i128 , Result . getValue ( 0 ) , Result . getValue ( 1 ) ) ; +Results . append ( { Pair , Result . getValue ( 2 ) } ) ; +if ( N -> getValueType ( 0 ) != MVT :: f128 ) { +return ; +} +if ( N -> getOperand ( 0 ) . getValueType ( ) != MVT :: i64 ) { +return ; +} +libCall = RTLIB :: SINTTOFP_I64_F128 ; +Results . push_back ( LowerF128Op ( SDValue ( N , 0 ) , DAG , getLibcallName ( libCall ) , 1 ) ) ; +return ; +return ReplaceLongIntrinsic ( N , Results , DAG ) ; +} +if ( N -> getOpcode ( ) == RISCVISD :: GORCI ) { +ReplaceExtractSubVectorResults ( N , Results , DAG ) ; +ReplaceLongIntrinsic ( N , Results , DAG ) ; +if ( N -> getValueType ( 0 ) != MVT :: f128 ) { +return ; +} +if ( N -> getOperand ( 0 ) . getValueType ( ) != MVT :: i64 ) { +return ; +} +libCall = RTLIB :: UINTTOFP_I64_F128 ; +Results . push_back ( LowerF128Op ( SDValue ( N , 0 ) , DAG , getLibcallName ( libCall ) , 1 ) ) ; +return ; +} +if ( N -> getOpcode ( ) == ISD :: BSWAP ) { +EVT VT = N -> getValueType ( 0 ) ; +ConstantSDNode * CN = cast < ConstantSDNode > ( N -> getOperand ( 0 ) ) ; +Intrinsic :: ID IntID = static_cast < Intrinsic :: ID > ( CN -> getZExtValue ( ) ) ; +if ( IntID == Intrinsic :: aarch64_sve_clasta_n ) { +SDLoc DL ( N ) ; +auto Op2 = DAG . getNode ( ISD :: ANY_EXTEND , DL , MVT :: i32 , N -> getOperand ( 2 ) ) ; +auto V = DAG . getNode ( RISCVISD :: CLASTA_N , DL , MVT :: i32 , N -> getOperand ( 1 ) , Op2 , N -> getOperand ( 3 ) ) ; +Results . push_back ( DAG . getNode ( ISD :: TRUNCATE , DL , VT , V ) ) ; +return ; +} +SDLoc DL ( N ) ; +auto V = DAG . getNode ( RISCVISD :: LASTA , DL , MVT :: i32 , N -> getOperand ( 1 ) , N -> getOperand ( 2 ) ) ; +Results . push_back ( DAG . getNode ( ISD :: TRUNCATE , DL , VT , V ) ) ; +return ; +SDLoc DL ( N ) ; +auto V = DAG . getNode ( RISCVISD :: LASTB , DL , MVT :: i32 , N -> getOperand ( 1 ) , N -> getOperand ( 2 ) ) ; +Results . push_back ( DAG . getNode ( ISD :: TRUNCATE , DL , VT , V ) ) ; +return ; +LowerLOAD ( N , Results , DAG ) ; +if ( Res . getNode ( ) ) { +Results . push_back ( Res ) ; +} +LoadSDNode * Ld = cast < LoadSDNode > ( N ) ; +if ( Ld -> getValueType ( 0 ) != MVT :: i64 ) { +return ; +} +if ( Ld -> getMemoryVT ( ) != MVT :: i64 ) { +return ; +} +SDLoc DL ( N ) ; +SDValue LoadRes = DAG . getExtLoad ( Ld -> getExtensionType ( ) , DL , MVT :: v2i32 , Ld -> getChain ( ) , Ld -> getBasePtr ( ) , Ld -> getPointerInfo ( ) , MVT :: v2i32 , Ld -> getAlignment ( ) , Ld -> getMemOperand ( ) -> getFlags ( ) , Ld -> getAAInfo ( ) ) ; +SDValue Res = DAG . getNode ( ISD :: BITCAST , DL , MVT :: i64 , LoadRes ) ; +Results . push_back ( Res ) ; +Results . push_back ( LoadRes . getValue ( 1 ) ) ; +return ; +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/TargetLowering.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/TargetLowering.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3d2fb2af0c056b9c2f3568520a755dff2f0232db --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/TargetLowering.cpp @@ -0,0 +1,42 @@ +RISCVTargetLowering :: RISCVTargetLowering ( const TargetMachine & TM , const RISCVSubtarget & STI ) : TargetLowering ( TM ) , Subtarget ( STI ) { +computeRegisterProperties ( STI . getRegisterInfo ( ) ) ; +setStackPointerRegisterToSaveRestore ( RISCV :: X1 ) ; +for ( auto N : { ISD :: EXTLOAD , ISD :: SEXTLOAD , ISD :: ZEXTLOAD } ) { +} +setBooleanContents ( ZeroOrOneBooleanContent ) ; +addRegisterClass ( MVT :: i32 , & RISCV :: GPRRegClass ) ; +TRI = STI . getRegisterInfo ( ) ; +computeRegisterProperties ( TRI ) ; +auto * RegInfo = Subtarget . getRegisterInfo ( ) ; +setBooleanVectorContents ( ZeroOrNegativeOneBooleanContent ) ; +setBooleanContents ( ZeroOrOneBooleanContent , ZeroOrNegativeOneBooleanContent ) ; +} +} +for ( auto CC : FPCCToExtend ) { +setLoadExtAction ( ISD :: SEXTLOAD , VT , MVT :: i1 , Promote ) ; +setLoadExtAction ( ISD :: ZEXTLOAD , VT , MVT :: i1 , Promote ) ; +if ( F16VT . isValid ( ) ) { +} +} +if ( Subtarget . atLeastM68020 ( ) ) { +} +setBooleanContents ( ZeroOrOneBooleanContent ) ; +setMinimumJumpTableEntries ( INT_MAX ) ; +setCondCodeAction ( CC , VT , Expand ) ; +computeRegisterProperties ( STI . getRegisterInfo ( ) ) ; +setBooleanContents ( UndefinedBooleanContent ) ; +setBooleanVectorContents ( ZeroOrNegativeOneBooleanContent ) ; +setMaxAtomicSizeInBitsSupported ( 0 ) ; +setStackPointerRegisterToSaveRestore ( RISCV :: R14 ) ; +const Align FunctionAlignment ( 2 ) ; +setStackPointerRegisterToSaveRestore ( RISCV :: R3 ) ; +setMinFunctionAlignment ( FunctionAlignment ) ; +setSchedulingPreference ( Sched :: Source ) ; +setJumpIsExpensive ( true ) ; +setLibcallCallingConv ( static_cast < RTLIB :: Libcall > ( I ) , CallingConv :: Fast ) ; +setBooleanContents ( ZeroOrOneBooleanContent ) ; +computeRegisterProperties ( ) ; +computeRegisterProperties ( STI . getRegisterInfo ( ) ) ; +setMinFunctionAlignment ( Align :: Constant < 2 > ( ) ) ; +setStackPointerRegisterToSaveRestore ( ABI . IsN64 ( ) ? RISCV :: SP_64 : RISCV :: SP ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/analyzeInputArgs.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/analyzeInputArgs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e382eff4824d447aead39f6e4241c5dfc5dc7071 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/analyzeInputArgs.cpp @@ -0,0 +1,16 @@ +void RISCVTargetLowering :: analyzeInputArgs ( MachineFunction & MF , CCState & CCInfo , const SmallVectorImpl < ISD :: InputArg > & Ins , bool IsRet ) const { +unsigned NumArgs = Ins . size ( ) ; +FunctionType * FType = MF . getFunction ( ) . getFunctionType ( ) ; +for ( unsigned i = 0 ; i != NumArgs ; ++ i ) { +MVT ArgVT = Ins [ i ] . VT ; +ISD :: ArgFlagsTy ArgFlags = Ins [ i ] . Flags ; +if ( IsRet ) { +} +if ( ! IsRet ) { +if ( CC_ ( i , ArgVT , ArgVT , CCValAssign :: Full , ArgFlags , CCInfo ) ) { +} +} +if ( Fn ( i , ArgVT , CCValAssign :: Full , CCInfo ) ) { +} +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/analyzeOutputArgs.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/analyzeOutputArgs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6450f3bbfe25541641cce7faf82031a29bf671e5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/analyzeOutputArgs.cpp @@ -0,0 +1,15 @@ +void RISCVTargetLowering :: analyzeOutputArgs ( MachineFunction & MF , CCState & CCInfo , const SmallVectorImpl < ISD :: OutputArg > & Outs , bool IsRet , CallLoweringInfo * CLI ) const { +unsigned NumArgs = Outs . size ( ) ; +for ( unsigned i = 0 ; i != NumArgs ; i ++ ) { +MVT ArgVT = Outs [ i ] . VT ; +ISD :: ArgFlagsTy ArgFlags = Outs [ i ] . Flags ; +if ( IsRet ) { +if ( RetCC_ ( i , ArgVT , ArgVT , CCValAssign :: Full , ArgFlags , CCInfo ) ) { +} +} +if ( ! IsRet ) { +if ( CC_ ( i , ArgVT , ArgVT , CCValAssign :: Full , ArgFlags , CCInfo ) ) { +} +} +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/computeKnownBitsForTargetNode.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/computeKnownBitsForTargetNode.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7702402e9ea546afa1514a1529b053e51ac9686b --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/computeKnownBitsForTargetNode.cpp @@ -0,0 +1,26 @@ +void RISCVTargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , KnownBits & Known , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { +KnownZero = KnownOne = APInt ( KnownOne . getBitWidth ( ) , 0 ) ; +APInt KnownZero2 ; +APInt KnownOne2 ; +unsigned BitWidth = Known . getBitWidth ( ) ; +unsigned Opc = Op . getOpcode ( ) ; +EVT VT = Op . getValueType ( ) ; +Known . resetAll ( ) ; +if ( Op . getOpcode ( ) == RISCVISD :: REMUW ) { +Known . Zero . setBitsFrom ( 1 ) ; +} +if ( Op . getOpcode ( ) == RISCVISD :: DIVUW ) { +KnownBits Known2 ; +DAG . computeKnownBits ( Op . getOperand ( 0 ) , Known , Depth + 1 ) ; +DAG . computeKnownBits ( Op . getOperand ( 1 ) , Known2 , Depth + 1 ) ; +Known . Zero = Known . Zero & Known2 . Zero ; +Known . One = Known . One & Known2 . One ; +Known . Zero . setBitsFrom ( 1 ) ; +} +if ( Op . getOpcode ( ) == RISCVISD :: READ_VLENB ) { +if ( Op . getResNo ( ) == 0 ) { +return ; +} +Known . Zero . setBitsFrom ( 1 ) ; +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/convertSelectOfConstantsToMath.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/convertSelectOfConstantsToMath.cpp new file mode 100644 index 0000000000000000000000000000000000000000..51269f50ce2e5fc7c824cfa4100384d706db162c --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/convertSelectOfConstantsToMath.cpp @@ -0,0 +1,3 @@ +bool convertSelectOfConstantsToMath ( EVT VT ) const override { +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/convertSetCCLogicToBitwiseLogic.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/convertSetCCLogicToBitwiseLogic.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3178e743bf8e6612f2326e0390c95e0ed53bbb73 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/convertSetCCLogicToBitwiseLogic.cpp @@ -0,0 +1,3 @@ +bool convertSetCCLogicToBitwiseLogic ( EVT VT ) const override { +return VT . isScalarInteger ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/decomposeMulByConstant.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/decomposeMulByConstant.cpp new file mode 100644 index 0000000000000000000000000000000000000000..62df45e0d1324398407de1489c1207801bab9658 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/decomposeMulByConstant.cpp @@ -0,0 +1,18 @@ +bool RISCVTargetLowering :: decomposeMulByConstant ( LLVMContext & Context , EVT VT , SDValue C ) const { +if ( ! VT . isScalarInteger ( ) ) { +return false ; +} +if ( auto * ConstNode = dyn_cast < ConstantSDNode > ( C . getNode ( ) ) ) { +if ( ! ConstNode -> getAPIntValue ( ) . isSignedIntN ( 64 ) ) { +return false ; +} +int64_t Imm = ConstNode -> getSExtValue ( ) ; +unsigned Shift = countTrailingZeros < uint64_t > ( Imm ) ; +Imm = Imm >> Shift ; +if ( isInt < 16 > ( Imm ) ) { +return false ; +} +uint64_t UImm = static_cast < uint64_t > ( Imm ) ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/emitLeadingFence.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/emitLeadingFence.cpp new file mode 100644 index 0000000000000000000000000000000000000000..aaf0462eacccf2161cf029182c909d9d244bb0fc --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/emitLeadingFence.cpp @@ -0,0 +1,20 @@ +Instruction * RISCVTargetLowering :: emitLeadingFence ( IRBuilder < > & Builder , Instruction * Inst , AtomicOrdering Ord ) const { +return nullptr ; +return nullptr ; +if ( Ord == AtomicOrdering :: SequentiallyConsistent ) { +if ( ! Inst -> hasAtomicStore ( ) ) { +return nullptr ; +} +} +if ( Ord == AtomicOrdering :: Release ) { +return makeDMB ( Builder , RISCV_MB :: ISHST ) ; +return makeDMB ( Builder , RISCV_MB :: ISH ) ; +} +return makeDMB ( Builder , RISCV_MB :: ISHST ) ; +return makeDMB ( Builder , RISCV_MB :: ISH ) ; +return callIntrinsic ( Builder , Intrinsic :: ppc_sync ) ; +if ( isAtLeastRelease ( Ord ) ) { +return callIntrinsic ( Builder , Intrinsic :: ppc_lwsync ) ; +} +return nullptr ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/emitMaskedAtomicCmpXchgIntrinsic.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/emitMaskedAtomicCmpXchgIntrinsic.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cfcf09034d257e0e65527385fed17f36a5976f5a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/emitMaskedAtomicCmpXchgIntrinsic.cpp @@ -0,0 +1,19 @@ +Value * RISCVTargetLowering :: emitMaskedAtomicCmpXchgIntrinsic ( IRBuilder < > & Builder , AtomicCmpXchgInst * CI , Value * AlignedAddr , Value * CmpVal , Value * NewVal , Value * Mask , AtomicOrdering Ord ) const { +Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; +Type * ValTy = CmpVal -> getType ( ) ; +Function * IntCmpXchg = Intrinsic :: getDeclaration ( M , Intrinsic :: ppc_cmpxchg_i128 ) ; +Type * Int64Ty = Type :: getInt64Ty ( M -> getContext ( ) ) ; +Value * CmpLo = Builder . CreateTrunc ( CmpVal , Int64Ty , "cmp_lo" ) ; +Value * CmpHi = Builder . CreateTrunc ( Builder . CreateLShr ( CmpVal , 64 ) , Int64Ty , "cmp_hi" ) ; +Value * NewLo = Builder . CreateTrunc ( NewVal , Int64Ty , "new_lo" ) ; +Value * NewHi = Builder . CreateTrunc ( Builder . CreateLShr ( NewVal , 64 ) , Int64Ty , "new_hi" ) ; +Value * Addr = Builder . CreateBitCast ( AlignedAddr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; +emitLeadingFence ( Builder , CI , Ord ) ; +Value * LoHi = Builder . CreateCall ( IntCmpXchg , { Addr , CmpLo , CmpHi , NewLo , NewHi } ) ; +emitTrailingFence ( Builder , CI , Ord ) ; +Value * Lo = Builder . CreateExtractValue ( LoHi , 0 , "lo" ) ; +Value * Hi = Builder . CreateExtractValue ( LoHi , 1 , "hi" ) ; +Lo = Builder . CreateZExt ( Lo , ValTy , "lo64" ) ; +Hi = Builder . CreateZExt ( Hi , ValTy , "hi64" ) ; +return Builder . CreateOr ( Lo , Builder . CreateShl ( Hi , ConstantInt :: get ( ValTy , 64 ) ) , "val64" ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/emitMaskedAtomicRMWIntrinsic.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/emitMaskedAtomicRMWIntrinsic.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e7388d9db713699e2d25209b8cee4409b798407e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/emitMaskedAtomicRMWIntrinsic.cpp @@ -0,0 +1,15 @@ +Value * RISCVTargetLowering :: emitMaskedAtomicRMWIntrinsic ( IRBuilder < > & Builder , AtomicRMWInst * AI , Value * AlignedAddr , Value * Incr , Value * Mask , Value * ShiftAmt , AtomicOrdering Ord ) const { +Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; +Type * ValTy = AlignedAddr -> getType ( ) -> getPointerElementType ( ) ; +Function * RMW = Intrinsic :: getDeclaration ( M , getIntrinsicForAtomicRMWBinOp128 ( AI -> getOperation ( ) ) ) ; +Type * Int64Ty = Type :: getInt64Ty ( M -> getContext ( ) ) ; +Value * IncrLo = Builder . CreateTrunc ( Incr , Int64Ty , "incr_lo" ) ; +Value * IncrHi = Builder . CreateTrunc ( Builder . CreateLShr ( Incr , 64 ) , Int64Ty , "incr_hi" ) ; +Value * Addr = Builder . CreateBitCast ( AlignedAddr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; +Value * LoHi = Builder . CreateCall ( RMW , { Addr , IncrLo , IncrHi } ) ; +Value * Lo = Builder . CreateExtractValue ( LoHi , 0 , "lo" ) ; +Value * Hi = Builder . CreateExtractValue ( LoHi , 1 , "hi" ) ; +Lo = Builder . CreateZExt ( Lo , ValTy , "lo64" ) ; +Hi = Builder . CreateZExt ( Hi , ValTy , "hi64" ) ; +return Builder . CreateOr ( Lo , Builder . CreateShl ( Hi , ConstantInt :: get ( ValTy , 64 ) ) , "val64" ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/emitTrailingFence.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/emitTrailingFence.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0095027c763a78157c0d3d7cd2da0936f0694646 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/emitTrailingFence.cpp @@ -0,0 +1,14 @@ +Instruction * RISCVTargetLowering :: emitTrailingFence ( IRBuilder < > & Builder , Instruction * Inst , AtomicOrdering Ord ) const { +if ( Ord == AtomicOrdering :: AcquireRelease ) { +if ( Ord == AtomicOrdering :: SequentiallyConsistent ) { +if ( Ord == AtomicOrdering :: Monotonic ) { +return nullptr ; +return nullptr ; +if ( isAcquireOrStronger ( Ord ) ) { +if ( isa < LoadInst > ( Inst ) ) { +return Builder . CreateCall ( Intrinsic :: getDeclaration ( Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) , Intrinsic :: ppc_cfence , { Inst -> getType ( ) } ) , { Inst } ) ; +} +} +return callIntrinsic ( Builder , Intrinsic :: ppc_lwsync ) ; +return nullptr ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/getAddr.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/getAddr.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e428bc4d3c41e5a5a31ba055bda636e73f368133 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/getAddr.cpp @@ -0,0 +1,20 @@ +template < class NodeTy > SDValue RISCVTargetLowering :: getAddr ( NodeTy * N , SelectionDAG & DAG , bool IsLocal ) const { +SDLoc DL ( N ) ; +EVT Ty = getPointerTy ( DAG . getDataLayout ( ) ) ; +unsigned Flag = RISCVII :: MO_None ; +if ( isPositionIndependent ( ) ) { +SDValue GPReg = DAG . getRegister ( RISCV :: GP_REG , MVT :: i32 ) ; +SDValue Wrapper = DAG . getNode ( RISCVISD :: GOT_ADDR , DL , Ty , GPReg , getTargetNode ( N , Ty , DAG , RISCV :: MO_GOT ) ) ; +return DAG . getLoad ( Ty , DL , DAG . getEntryNode ( ) , Wrapper , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) ) ; +} +SDValue TV = getTargetNode ( N , DL , Ty , DAG , Flag ) ; +if ( ! isPositionIndependent ( ) ) { +SDValue Hi = getTargetNode ( N , Ty , DAG , RISCV :: MO_ABS_HI ) ; +SDValue Lo = getTargetNode ( N , Ty , DAG , RISCV :: MO_ABS_LO ) ; +SDValue MoveHi = DAG . getNode ( RISCVISD :: MOVEHI , DL , MVT :: i32 , Hi ) ; +} +if ( IsLocal ) { +DAG . getNode ( ISD :: ADD , DL , Ty , { DAG . getGLOBAL_OFFSET_TABLE ( Ty ) , Addr } ) ; +} +return DAG . getLoad ( Ty , DL , DAG . getEntryNode ( ) , Result , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/getConstraintType.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/getConstraintType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3cd3a4682a77efc696a92a3141f7ac6330c1e4c5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/getConstraintType.cpp @@ -0,0 +1,20 @@ +RISCVTargetLowering :: ConstraintType RISCVTargetLowering :: getConstraintType ( StringRef Constraint ) const { +if ( Constraint . size ( ) == 1 ) { +if ( Constraint [ 0 ] == 'f' ) { +return C_RegisterClass ; +} +if ( Constraint [ 0 ] == 'I' ) { +return C_Immediate ; +} +if ( Constraint [ 0 ] == 'J' ) { +return C_Immediate ; +} +if ( Constraint [ 0 ] == 'K' ) { +return C_Immediate ; +} +if ( Constraint [ 0 ] == 'A' ) { +return C_Memory ; +} +} +return TargetLowering :: getConstraintType ( Constraint ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/getDynamicTLSAddr.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/getDynamicTLSAddr.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a595cc74e020497c74d7dfac4079f445cf314273 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/getDynamicTLSAddr.cpp @@ -0,0 +1,19 @@ +SDValue RISCVTargetLowering :: getDynamicTLSAddr ( GlobalAddressSDNode * N , SelectionDAG & DAG ) const { +MachineFunction & MF = DAG . getMachineFunction ( ) ; +RISCVMachineFunctionInfo * CFI = MF . getInfo < RISCVMachineFunctionInfo > ( ) ; +unsigned RISCVPCLabelIndex = CFI -> createPICLabelUId ( ) ; +SDLoc DL ( N ) ; +EVT Ty = getPointerTy ( DAG . getDataLayout ( ) ) ; +IntegerType * CallTy = Type :: getIntNTy ( * DAG . getContext ( ) , Ty . getSizeInBits ( ) ) ; +SDValue PICLabel = DAG . getTargetConstant ( RISCVPCLabelIndex , DL , MVT :: i32 ) ; +SDValue Addr = DAG . getTargetGlobalAddress ( GV , DL , Ty , 0 , 0 ) ; +SDValue Load = SDValue ( DAG . getMachineNode ( RISCV :: PseudoLA_TLS_GD , DL , Ty , Addr ) , 0 ) ; +ArgListTy Args ; +ArgListEntry Entry ; +Entry . Node = Load ; +Entry . Ty = CallTy ; +Args . push_back ( Entry ) ; +TargetLowering :: CallLoweringInfo CLI ( DAG ) ; +CLI . setDebugLoc ( DL ) . setChain ( DAG . getEntryNode ( ) ) . setLibCallee ( CallingConv :: C , CallTy , DAG . getExternalSymbol ( "__tls_get_addr" , Ty ) , std :: move ( Args ) ) ; +return LowerCallTo ( CLI ) . first ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/getExceptionPointerRegister.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/getExceptionPointerRegister.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fc02741aaf5a8cbf9dd1c422325f1b9264cfe403 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/getExceptionPointerRegister.cpp @@ -0,0 +1,3 @@ +Register RISCVTargetLowering :: getExceptionPointerRegister ( const Constant * PersonalityFn ) const { +return RISCV :: X10 ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/getExceptionSelectorRegister.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/getExceptionSelectorRegister.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b009628facdcf7986bcf0d4fc93fae496f151f60 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/getExceptionSelectorRegister.cpp @@ -0,0 +1,3 @@ +Register RISCVTargetLowering :: getExceptionSelectorRegister ( const Constant * PersonalityFn ) const { +return RISCV :: X11 ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/getExtendForAtomicCmpSwapArg.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/getExtendForAtomicCmpSwapArg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..38de26de656308f961676867af71fc387570f00a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/getExtendForAtomicCmpSwapArg.cpp @@ -0,0 +1,3 @@ +ISD :: NodeType getExtendForAtomicCmpSwapArg ( ) const override { +return ISD :: SIGN_EXTEND ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/getExtendForAtomicOps.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/getExtendForAtomicOps.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b9c2d6c3acd41ab5253583248f7de9c051d4481b --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/getExtendForAtomicOps.cpp @@ -0,0 +1,3 @@ +ISD :: NodeType getExtendForAtomicOps ( ) const override { +return ISD :: SIGN_EXTEND ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/getInlineAsmMemConstraint.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/getInlineAsmMemConstraint.cpp new file mode 100644 index 0000000000000000000000000000000000000000..253b96d8be6ebabc2aa0d331feb3b67fb0ddfdff --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/getInlineAsmMemConstraint.cpp @@ -0,0 +1,8 @@ +unsigned RISCVTargetLowering :: getInlineAsmMemConstraint ( StringRef ConstraintCode ) const { +if ( ConstraintCode . size ( ) == 1 ) { +if ( ConstraintCode [ 0 ] == 'A' ) { +return InlineAsm :: Constraint_A ; +} +} +return TargetLowering :: getInlineAsmMemConstraint ( ConstraintCode ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/getRegForInlineAsmConstraint.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/getRegForInlineAsmConstraint.cpp new file mode 100644 index 0000000000000000000000000000000000000000..40ad815c07e1409e745187e8ddbc2ea6bb676f97 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/getRegForInlineAsmConstraint.cpp @@ -0,0 +1,326 @@ +std :: pair < unsigned , const TargetRegisterClass * > RISCVTargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { +if ( Constraint . size ( ) == 1 ) { +if ( Constraint [ 0 ] == 'r' ) { +return std :: make_pair ( 0U , & RISCV :: GPRRegClass ) ; +} +if ( Constraint [ 0 ] == 'f' ) { +if ( Subtarget . hasStdExtF ( ) ) { +if ( VT == MVT :: f32 ) { +return std :: make_pair ( 0U , & RISCV :: FPR32RegClass ) ; +} +} +if ( Subtarget . hasStdExtD ( ) ) { +if ( VT == MVT :: f64 ) { +return std :: make_pair ( 0U , & RISCV :: FPR64RegClass ) ; +} +} +} +} +return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; +unsigned XRegFromAlias = RISCV :: NoRegister ; +if ( Constraint . lower ( ) == "{zero}" ) { +XRegFromAlias = RISCV :: X0 ; +} +if ( Constraint . lower ( ) == "{ra}" ) { +XRegFromAlias = RISCV :: X1 ; +} +if ( Constraint . lower ( ) == "{sp}" ) { +XRegFromAlias = RISCV :: X2 ; +} +if ( Constraint . lower ( ) == "{gp}" ) { +XRegFromAlias = RISCV :: X3 ; +} +if ( Constraint . lower ( ) == "{tp}" ) { +XRegFromAlias = RISCV :: X4 ; +} +if ( Constraint . lower ( ) == "{t0}" ) { +XRegFromAlias = RISCV :: X5 ; +} +if ( Constraint . lower ( ) == "{t1}" ) { +XRegFromAlias = RISCV :: X6 ; +} +if ( Constraint . lower ( ) == "{t2}" ) { +XRegFromAlias = RISCV :: X7 ; +} +if ( Constraint . lower ( ) == "{s0}" ) { +XRegFromAlias = RISCV :: X8 ; +} +if ( Constraint . lower ( ) == "{fp}" ) { +XRegFromAlias = RISCV :: X8 ; +} +if ( Constraint . lower ( ) == "{s1}" ) { +XRegFromAlias = RISCV :: X9 ; +} +if ( Constraint . lower ( ) == "{a0}" ) { +XRegFromAlias = RISCV :: X10 ; +} +if ( Constraint . lower ( ) == "{a1}" ) { +XRegFromAlias = RISCV :: X11 ; +} +if ( Constraint . lower ( ) == "{a2}" ) { +XRegFromAlias = RISCV :: X12 ; +} +if ( Constraint . lower ( ) == "{a3}" ) { +XRegFromAlias = RISCV :: X13 ; +} +if ( Constraint . lower ( ) == "{a4}" ) { +XRegFromAlias = RISCV :: X14 ; +} +if ( Constraint . lower ( ) == "{a5}" ) { +XRegFromAlias = RISCV :: X15 ; +} +if ( Constraint . lower ( ) == "{a6}" ) { +XRegFromAlias = RISCV :: X16 ; +} +if ( Constraint . lower ( ) == "{a7}" ) { +XRegFromAlias = RISCV :: X17 ; +} +if ( Constraint . lower ( ) == "{s2}" ) { +XRegFromAlias = RISCV :: X18 ; +} +if ( Constraint . lower ( ) == "{s3}" ) { +XRegFromAlias = RISCV :: X19 ; +} +if ( Constraint . lower ( ) == "{s4}" ) { +XRegFromAlias = RISCV :: X20 ; +} +if ( Constraint . lower ( ) == "{s5}" ) { +XRegFromAlias = RISCV :: X21 ; +} +if ( Constraint . lower ( ) == "{s6}" ) { +XRegFromAlias = RISCV :: X22 ; +} +if ( Constraint . lower ( ) == "{s7}" ) { +XRegFromAlias = RISCV :: X23 ; +} +if ( Constraint . lower ( ) == "{s8}" ) { +XRegFromAlias = RISCV :: X24 ; +} +if ( Constraint . lower ( ) == "{s9}" ) { +XRegFromAlias = RISCV :: X25 ; +} +if ( Constraint . lower ( ) == "{s10}" ) { +XRegFromAlias = RISCV :: X26 ; +} +if ( Constraint . lower ( ) == "{s11}" ) { +XRegFromAlias = RISCV :: X27 ; +} +if ( Constraint . lower ( ) == "{t3}" ) { +XRegFromAlias = RISCV :: X28 ; +} +if ( Constraint . lower ( ) == "{t4}" ) { +XRegFromAlias = RISCV :: X29 ; +} +if ( Constraint . lower ( ) == "{t5}" ) { +XRegFromAlias = RISCV :: X30 ; +} +if ( Constraint . lower ( ) == "{t6}" ) { +XRegFromAlias = RISCV :: X31 ; +} +if ( XRegFromAlias != RISCV :: NoRegister ) { +return std :: make_pair ( XRegFromAlias , & RISCV :: GPRRegClass ) ; +} +if ( Subtarget . hasStdExtF ( ) ) { +unsigned FReg = RISCV :: NoRegister ; +if ( Constraint . lower ( ) == "{f0}" ) { +FReg = RISCV :: F0_F ; +} +if ( Constraint . lower ( ) == "{ft0}" ) { +FReg = RISCV :: F0_F ; +} +if ( Constraint . lower ( ) == "{f1}" ) { +FReg = RISCV :: F1_F ; +} +if ( Constraint . lower ( ) == "{ft1}" ) { +FReg = RISCV :: F1_F ; +} +if ( Constraint . lower ( ) == "{f2}" ) { +FReg = RISCV :: F2_F ; +} +if ( Constraint . lower ( ) == "{ft2}" ) { +FReg = RISCV :: F2_F ; +} +if ( Constraint . lower ( ) == "{f3}" ) { +FReg = RISCV :: F3_F ; +} +if ( Constraint . lower ( ) == "{ft3}" ) { +FReg = RISCV :: F3_F ; +} +if ( Constraint . lower ( ) == "{f4}" ) { +FReg = RISCV :: F4_F ; +} +if ( Constraint . lower ( ) == "{ft4}" ) { +FReg = RISCV :: F4_F ; +} +if ( Constraint . lower ( ) == "{f5}" ) { +FReg = RISCV :: F5_F ; +} +if ( Constraint . lower ( ) == "{ft5}" ) { +FReg = RISCV :: F5_F ; +} +if ( Constraint . lower ( ) == "{f6}" ) { +FReg = RISCV :: F6_F ; +} +if ( Constraint . lower ( ) == "{ft6}" ) { +FReg = RISCV :: F6_F ; +} +if ( Constraint . lower ( ) == "{f7}" ) { +FReg = RISCV :: F7_F ; +} +if ( Constraint . lower ( ) == "{ft7}" ) { +FReg = RISCV :: F7_F ; +} +if ( Constraint . lower ( ) == "{f8}" ) { +FReg = RISCV :: F8_F ; +} +if ( Constraint . lower ( ) == "{ft8}" ) { +FReg = RISCV :: F8_F ; +} +if ( Constraint . lower ( ) == "{f9}" ) { +FReg = RISCV :: F9_F ; +} +if ( Constraint . lower ( ) == "{ft9}" ) { +FReg = RISCV :: F9_F ; +} +if ( Constraint . lower ( ) == "{f10}" ) { +FReg = RISCV :: F10_F ; +} +if ( Constraint . lower ( ) == "{ft10}" ) { +FReg = RISCV :: F10_F ; +} +if ( Constraint . lower ( ) == "{f11}" ) { +FReg = RISCV :: F11_F ; +} +if ( Constraint . lower ( ) == "{ft11}" ) { +FReg = RISCV :: F11_F ; +} +if ( Constraint . lower ( ) == "{f12}" ) { +FReg = RISCV :: F12_F ; +} +if ( Constraint . lower ( ) == "{ft12}" ) { +FReg = RISCV :: F12_F ; +} +if ( Constraint . lower ( ) == "{f13}" ) { +FReg = RISCV :: F13_F ; +} +if ( Constraint . lower ( ) == "{ft13}" ) { +FReg = RISCV :: F13_F ; +} +if ( Constraint . lower ( ) == "{f14}" ) { +FReg = RISCV :: F14_F ; +} +if ( Constraint . lower ( ) == "{ft14}" ) { +FReg = RISCV :: F14_F ; +} +if ( Constraint . lower ( ) == "{f15}" ) { +FReg = RISCV :: F15_F ; +} +if ( Constraint . lower ( ) == "{ft15}" ) { +FReg = RISCV :: F15_F ; +} +if ( Constraint . lower ( ) == "{f16}" ) { +FReg = RISCV :: F16_F ; +} +if ( Constraint . lower ( ) == "{ft16}" ) { +FReg = RISCV :: F16_F ; +} +if ( Constraint . lower ( ) == "{f17}" ) { +FReg = RISCV :: F17_F ; +} +if ( Constraint . lower ( ) == "{ft17}" ) { +FReg = RISCV :: F17_F ; +} +if ( Constraint . lower ( ) == "{f18}" ) { +FReg = RISCV :: F18_F ; +} +if ( Constraint . lower ( ) == "{ft18}" ) { +FReg = RISCV :: F18_F ; +} +if ( Constraint . lower ( ) == "{f19}" ) { +FReg = RISCV :: F19_F ; +} +if ( Constraint . lower ( ) == "{ft19}" ) { +FReg = RISCV :: F19_F ; +} +if ( Constraint . lower ( ) == "{f20}" ) { +FReg = RISCV :: F20_F ; +} +if ( Constraint . lower ( ) == "{ft20}" ) { +FReg = RISCV :: F20_F ; +} +if ( Constraint . lower ( ) == "{f21}" ) { +FReg = RISCV :: F21_F ; +} +if ( Constraint . lower ( ) == "{ft21}" ) { +FReg = RISCV :: F21_F ; +} +if ( Constraint . lower ( ) == "{f22}" ) { +FReg = RISCV :: F22_F ; +} +if ( Constraint . lower ( ) == "{ft22}" ) { +FReg = RISCV :: F22_F ; +} +if ( Constraint . lower ( ) == "{f23}" ) { +FReg = RISCV :: F23_F ; +} +if ( Constraint . lower ( ) == "{ft23}" ) { +FReg = RISCV :: F23_F ; +} +if ( Constraint . lower ( ) == "{f24}" ) { +FReg = RISCV :: F24_F ; +} +if ( Constraint . lower ( ) == "{ft24}" ) { +FReg = RISCV :: F24_F ; +} +if ( Constraint . lower ( ) == "{f25}" ) { +FReg = RISCV :: F25_F ; +} +if ( Constraint . lower ( ) == "{ft25}" ) { +FReg = RISCV :: F25_F ; +} +if ( Constraint . lower ( ) == "{f26}" ) { +FReg = RISCV :: F26_F ; +} +if ( Constraint . lower ( ) == "{ft26}" ) { +FReg = RISCV :: F26_F ; +} +if ( Constraint . lower ( ) == "{f27}" ) { +FReg = RISCV :: F27_F ; +} +if ( Constraint . lower ( ) == "{ft27}" ) { +FReg = RISCV :: F27_F ; +} +if ( Constraint . lower ( ) == "{f28}" ) { +FReg = RISCV :: F28_F ; +} +if ( Constraint . lower ( ) == "{ft28}" ) { +FReg = RISCV :: F28_F ; +} +if ( Constraint . lower ( ) == "{f29}" ) { +FReg = RISCV :: F29_F ; +} +if ( Constraint . lower ( ) == "{ft29}" ) { +FReg = RISCV :: F29_F ; +} +if ( Constraint . lower ( ) == "{f30}" ) { +FReg = RISCV :: F30_F ; +} +if ( Constraint . lower ( ) == "{ft30}" ) { +FReg = RISCV :: F30_F ; +} +if ( Constraint . lower ( ) == "{f31}" ) { +FReg = RISCV :: F31_F ; +} +if ( Constraint . lower ( ) == "{ft31}" ) { +FReg = RISCV :: F31_F ; +} +if ( FReg != RISCV :: NoRegister ) { +assert ( RISCV :: F0_32 <= FReg && FReg <= RISCV :: F31_32 && "Unknown fp-reg" ) ; +if ( Subtarget . hasStdExtD ( ) ) { +unsigned RegNo = FReg - RISCV :: F0_32 ; +unsigned DReg = RISCV :: F0_64 + RegNo ; +} +} +} +return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/getRegisterByName.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/getRegisterByName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c16b4703c68fed7aab4e8cde232d9094b9ccd8ca --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/getRegisterByName.cpp @@ -0,0 +1,6 @@ +Register RISCVTargetLowering :: getRegisterByName ( const char * RegName , LLT VT , const MachineFunction & MF ) const { +Register Reg = MatchRegisterAltName ( RegName ) ; +if ( Reg ) { +return Reg ; +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/getSetCCResultType.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/getSetCCResultType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..77bb51ed2c7075e9575dfc327e58c36fb28e43c2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/getSetCCResultType.cpp @@ -0,0 +1,8 @@ +EVT RISCVTargetLowering :: getSetCCResultType ( const DataLayout & DL , LLVMContext & , EVT VT ) const { +if ( ! VT . isVector ( ) ) { +return getPointerTy ( DL ) ; +} +if ( Subtarget . hasStdExtV ( ) ) { +return MVT :: getVectorVT ( MVT :: i1 , VT . getVectorElementCount ( ) ) ; +return VT . changeVectorElementTypeToInteger ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/getStaticTLSAddr.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/getStaticTLSAddr.cpp new file mode 100644 index 0000000000000000000000000000000000000000..442db86c6e45445e2d7c6b517d23cf2a715ea20a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/getStaticTLSAddr.cpp @@ -0,0 +1,24 @@ +SDValue RISCVTargetLowering :: getStaticTLSAddr ( GlobalAddressSDNode * N , SelectionDAG & DAG , bool UseGOT ) const { +MachineFunction & MF = DAG . getMachineFunction ( ) ; +RISCVMachineFunctionInfo * CFI = MF . getInfo < RISCVMachineFunctionInfo > ( ) ; +unsigned RISCVPCLabelIndex = CFI -> createPICLabelUId ( ) ; +SDLoc DL ( N ) ; +EVT Ty = getPointerTy ( DAG . getDataLayout ( ) ) ; +RISCVCP :: RISCVCPModifier Flag = UseGOT ? RISCVCP :: TLSIE : RISCVCP :: TLSLE ; +bool AddCurrentAddr = UseGOT ? true : false ; +unsigned char PCAjust = UseGOT ? 4 : 0 ; +RISCVConstantPoolValue * CPV = RISCVConstantPoolConstant :: Create ( N -> getGlobal ( ) , RISCVCP :: CPValue , PCAjust , Flag , AddCurrentAddr , RISCVPCLabelIndex ) ; +SDValue CAddr = DAG . getTargetConstantPool ( CPV , Ty ) ; +SDValue Load ; +if ( UseGOT ) { +SDValue PICLabel = DAG . getTargetConstant ( RISCVPCLabelIndex , DL , MVT :: i32 ) ; +auto * LRWGRS = DAG . getMachineNode ( RISCV :: PseudoTLSLA32 , DL , { Ty , Ty } , { CAddr , PICLabel } ) ; +auto LRWADDGRS = DAG . getNode ( ISD :: ADD , DL , Ty , SDValue ( LRWGRS , 0 ) , SDValue ( LRWGRS , 1 ) ) ; +Load = DAG . getLoad ( Ty , DL , DAG . getEntryNode ( ) , LRWADDGRS , MachinePointerInfo ( N -> getGlobal ( ) ) ) ; +} +if ( ! UseGOT ) { +Load = SDValue ( DAG . getMachineNode ( RISCV :: LRW32 , DL , Ty , CAddr ) , 0 ) ; +} +SDValue TPReg = DAG . getRegister ( RISCV :: R31 , MVT :: i32 ) ; +return DAG . getNode ( ISD :: ADD , DL , Ty , Load , TPReg ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/getSubtarget.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/getSubtarget.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a040c2636476d164c22e0a10b28a246c3520a00b --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/getSubtarget.cpp @@ -0,0 +1,3 @@ +const RISCVSubtarget & getSubtarget ( ) const { +return Subtarget ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/getTargetNodeName.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/getTargetNodeName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a2d1131fb5f1f81109040e25546a593d6c76b834 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/getTargetNodeName.cpp @@ -0,0 +1,123 @@ +const char * RISCVTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { +if ( ( RISCVISD :: NodeType ) Opcode == RISCVISD :: RET_FLAG ) { +return "RISCVISD::RET_FLAG" ; +} +if ( ( RISCVISD :: NodeType ) Opcode == RISCVISD::URET_FLAG ) { +return "RISCVISD::URET_FLAG" ; +} +if ( ( RISCVISD :: NodeType ) Opcode == RISCVISD :: SRET_FLAG ) { +return "RISCVISD::SRET_FLAG" ; +} +if ( ( RISCVISD :: NodeType ) Opcode == RISCVISD :: MRET_FLAG ) { +return "RISCVISD::MRET_FLAG" ; +} +if ( ( RISCVISD :: NodeType ) Opcode == RISCVISD :: CALL ) { +return "RISCVISD::CALL" ; +} +if ( ( RISCVISD :: NodeType ) Opcode == RISCVISD :: SELECT_CC ) { +return "RISCVISD::SELECT_CC" ; +} +if ( ( RISCVISD :: NodeType ) Opcode == RISCVISD :: BuildPairF64 ) { +return "RISCVISD::BuildPairF64" ; +} +if ( ( RISCVISD :: NodeType ) Opcode == RISCVISD :: SplitF64 ) { +return "RISCVISD::SplitF64" ; +} +if ( ( RISCVISD :: NodeType ) Opcode == RISCVISD ::TAIL ) { +return "RISCVISD::TAIL" ; +} +if ( ( RISCVISD :: NodeType ) Opcode == RISCVISD :: FMV_X_ANYEXTH ) { +return "RISCVISD::FMV_X_ANYEXTH" ; +} +if ( ( RISCVISD :: NodeType ) Opcode == RISCVISD :: FMV_W_X_RV64 ) { +return "RISCVISD::FMV_W_X_RV64" ; +} +if ( ( RISCVISD :: NodeType ) Opcode == RISCVISD :: FMV_X_ANYEXTW_RV64 ) { +return "RISCVISD::FMV_X_ANYEXTW_RV64" ; +} +if ( ( RISCVISD :: NodeType ) Opcode == RISCVISD :: READ_CYCLE_WIDE ) { +return "RISCVISD::READ_CYCLE_WIDE" ; +} +if ( ( RISCVISD :: NodeType ) Opcode == RISCVISD::GREVI ) { +return "RISCVISD::GREVI" ; +} +if ( ( RISCVISD :: NodeType ) Opcode == RISCVISD::GREVIW ) { +return "RISCVISD::GREVIW" ; +} +if ( ( RISCVISD :: NodeType ) Opcode == RISCVISD :: GORCI ) { +return "RISCVISD::GORCI" ; +} +if ( ( RISCVISD :: NodeType ) Opcode == RISCVISD :: GORCIW ) { +return "RISCVISD::GORCIW" ; +} +if ( ( RISCVISD :: NodeType ) Opcode == RISCVISD::VMV_X_S ) { +return "RISCVISD::VMV_X_S" ; +} +if ( ( RISCVISD :: NodeType ) Opcode == RISCVISD :: SPLAT_VECTOR_I64 ) { +return "RISCVISD::SPLAT_VECTOR_I64" ; +} +if ( ( RISCVISD :: NodeType ) Opcode == RISCVISD :: READ_VLENB ) { +return "RISCVISD::READ_VLENB" ; +} +if ( ( RISCVISD :: NodeType ) Opcode == RISCVISD :: TRUNCATE_VECTOR ) { +return "RISCVISD::TRUNCATE_VECTOR" ; +} +if ( ( RISCVISD :: NodeType ) Opcode == RISCVISD :: VLEFF ) { +return "RISCVISD::VLEFF" ; +} +if ( ( RISCVISD :: NodeType ) Opcode == RISCVISD :: VLEFF_MASK ) { +return "RISCVISD::VLEFF_MASK" ; +} +if ( ( RISCVISD :: NodeType ) Opcode == RISCVISD::VLSEGFF ) { +return "RISCVISD::VLSEGFF" ; +} +if ( ( RISCVISD :: NodeType ) Opcode == RISCVISD :: VLSEGFF_MASK ) { +return "RISCVISD::VLSEGFF_MASK" ; +} +if ( ( RISCVISD :: NodeType ) Opcode == RISCVISD :: READ_VL ) { +return "RISCVISD::READ_VL" ; +} +if ( ( RISCVISD :: NodeType ) Opcode == RISCVISD :: VSLIDEUP ) { +return "RISCVISD::VSLIDEUP" ; +} +if ( ( RISCVISD :: NodeType ) Opcode == RISCVISD :: VSLIDEDOWN ) { +return "RISCVISD::VSLIDEDOWN" ; +} +if ( ( RISCVISD :: NodeType ) Opcode == RISCVISD :: VID ) { +return "RISCVISD::VID" ; +} +if ( ( RISCVISD :: NodeType ) Opcode == RISCVISD :: FMV_H_X ) { +return "RISCVISD::FMV_H_X" ; +} +if ( ( RISCVISD :: NodeType ) Opcode == RISCVISD :: FSRW ) { +return "RISCVISD::FSRW" ; +} +if ( ( RISCVISD :: NodeType ) Opcode == RISCVISD :: FSLW ) { +return "RISCVISD::FSLW" ; +} +if ( ( RISCVISD :: NodeType ) Opcode == RISCVISD :: RORW ) { +return "RISCVISD::RORW" ; +} +if ( ( RISCVISD :: NodeType ) Opcode == RISCVISD :: ROLW ) { +return "RISCVISD::ROLW" ; +} +if ( ( RISCVISD :: NodeType ) Opcode == RISCVISD :: REMUW ) { +return "RISCVISD::REMUW" ; +} +if ( ( RISCVISD :: NodeType ) Opcode == RISCVISD :: DIVUW ) { +return "RISCVISD::DIVUW" ; +} +if ( ( RISCVISD :: NodeType ) Opcode == RISCVISD :: DIVW ) { +return "RISCVISD::DIVW" ; +} +if ( ( RISCVISD :: NodeType ) Opcode == RISCVISD :: SRLW ) { +return "RISCVISD::SRLW" ; +} +if ( ( RISCVISD :: NodeType ) Opcode == RISCVISD :: SRAW ) { +return "RISCVISD::SRAW" ; +} +if ( ( RISCVISD :: NodeType ) Opcode == RISCVISD :: SLLW ) { +return "RISCVISD::SLLW" ; +} +return nullptr ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/getTgtMemIntrinsic.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/getTgtMemIntrinsic.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3579f0736c29acc14ca6ad1b4c7b396a980277f5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/getTgtMemIntrinsic.cpp @@ -0,0 +1,111 @@ +bool RISCVTargetLowering :: getTgtMemIntrinsic ( IntrinsicInfo & Info , const CallInst & I , MachineFunction & MF , unsigned Intrinsic ) const { +if ( Intrinsic == Intrinsic :: RISCV_masked_atomicrmw_xchg_i32 ) { +PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( 0 ) -> getType ( ) ) ; +Info . opc = ISD :: INTRINSIC_W_CHAIN ; +Info . memVT = MVT :: getVT ( PtrTy -> getElementType ( ) ) ; +Info . ptrVal = I . getArgOperand ( 0 ) ; +Info . offset = 0 ; +Info . align = I . getModule ( ) -> getDataLayout ( ) . getABITypeAlignment ( PtrTy -> getElementType ( ) ) ; +Info . vol = true ; +Info . readMem = true ; +Info . writeMem = false ; +return true ; +} +if ( Intrinsic == Intrinsic :: RISCV_masked_atomicrmw_add_i32 ) { +PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( 0 ) -> getType ( ) ) ; +Info . opc = ISD :: INTRINSIC_W_CHAIN ; +Info . memVT = MVT :: getVT ( PtrTy -> getElementType ( ) ) ; +Info . ptrVal = I . getArgOperand ( 0 ) ; +Info . offset = 0 ; +Info . align = I . getModule ( ) -> getDataLayout ( ) . getABITypeAlignment ( PtrTy -> getElementType ( ) ) ; +Info . vol = true ; +Info . readMem = true ; +Info . writeMem = false ; +return true ; +} +if ( Intrinsic == Intrinsic :: RISCV_masked_atomicrmw_sub_i32 ) { +PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( 0 ) -> getType ( ) ) ; +Info . opc = ISD :: INTRINSIC_W_CHAIN ; +Info . memVT = MVT :: getVT ( PtrTy -> getElementType ( ) ) ; +Info . ptrVal = I . getArgOperand ( 0 ) ; +Info . offset = 0 ; +Info . align = I . getModule ( ) -> getDataLayout ( ) . getABITypeAlignment ( PtrTy -> getElementType ( ) ) ; +Info . vol = true ; +Info . readMem = true ; +Info . writeMem = false ; +return true ; +} +if ( Intrinsic == Intrinsic :: RISCV_masked_atomicrmw_nand_i32 ) { +PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( 0 ) -> getType ( ) ) ; +Info . opc = ISD :: INTRINSIC_W_CHAIN ; +Info . memVT = MVT :: getVT ( PtrTy -> getElementType ( ) ) ; +Info . ptrVal = I . getArgOperand ( 0 ) ; +Info . offset = 0 ; +Info . align = I . getModule ( ) -> getDataLayout ( ) . getABITypeAlignment ( PtrTy -> getElementType ( ) ) ; +Info . vol = true ; +Info . readMem = true ; +Info . writeMem = false ; +return true ; +} +if ( Intrinsic == Intrinsic :: RISCV_masked_atomicrmw_max_i32 ) { +PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( 1 ) -> getType ( ) ) ; +Info . opc = ISD :: INTRINSIC_W_CHAIN ; +Info . memVT = MVT :: getVT ( PtrTy -> getElementType ( ) ) ; +Info . ptrVal = I . getArgOperand ( 1 ) ; +Info . offset = 0 ; +Info . align = I . getModule ( ) -> getDataLayout ( ) . getABITypeAlignment ( PtrTy -> getElementType ( ) ) ; +Info . vol = true ; +Info . readMem = false ; +Info . writeMem = true ; +return true ; +} +if ( Intrinsic == Intrinsic :: RISCV_masked_atomicrmw_min_i32 ) { +PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( 1 ) -> getType ( ) ) ; +Info . opc = ISD :: INTRINSIC_W_CHAIN ; +Info . memVT = MVT :: getVT ( PtrTy -> getElementType ( ) ) ; +Info . ptrVal = I . getArgOperand ( 1 ) ; +Info . offset = 0 ; +Info . align = I . getModule ( ) -> getDataLayout ( ) . getABITypeAlignment ( PtrTy -> getElementType ( ) ) ; +Info . vol = true ; +Info . readMem = false ; +Info . writeMem = true ; +return true ; +} +if ( Intrinsic == Intrinsic :: RISCV_masked_atomicrmw_umax_i32 ) { +PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( 0 ) -> getType ( ) ) ; +Info . opc = ISD :: INTRINSIC_W_CHAIN ; +Info . memVT = MVT :: getVT ( PtrTy -> getElementType ( ) ) ; +Info . ptrVal = I . getArgOperand ( 0 ) ; +Info . offset = 0 ; +Info . align = I . getModule ( ) -> getDataLayout ( ) . getABITypeAlignment ( PtrTy -> getElementType ( ) ) ; +Info . vol = true ; +Info . readMem = true ; +Info . writeMem = false ; +return true ; +} +if ( Intrinsic == Intrinsic :: RISCV_masked_atomicrmw_umin_i32 ) { +PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( 0 ) -> getType ( ) ) ; +Info . opc = ISD :: INTRINSIC_W_CHAIN ; +Info . memVT = MVT :: getVT ( PtrTy -> getElementType ( ) ) ; +Info . ptrVal = I . getArgOperand ( 0 ) ; +Info . offset = 0 ; +Info . align = I . getModule ( ) -> getDataLayout ( ) . getABITypeAlignment ( PtrTy -> getElementType ( ) ) ; +Info . vol = true ; +Info . readMem = true ; +Info . writeMem = false ; +return true ; +} +if ( Intrinsic == Intrinsic :: RISCV_masked_cmpxchg_i32 ) { +PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( 0 ) -> getType ( ) ) ; +Info . opc = ISD :: INTRINSIC_W_CHAIN ; +Info . memVT = MVT :: getVT ( PtrTy -> getElementType ( ) ) ; +Info . ptrVal = I . getArgOperand ( 0 ) ; +Info . offset = 0 ; +Info . align = I . getModule ( ) -> getDataLayout ( ) . getABITypeAlignment ( PtrTy -> getElementType ( ) ) ; +Info . vol = true ; +Info . readMem = true ; +Info . writeMem = false ; +return true ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/hasBitPreservingFPLogic.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/hasBitPreservingFPLogic.cpp new file mode 100644 index 0000000000000000000000000000000000000000..558a2f60006bf8e5482ed81b7857f92e9cb02c54 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/hasBitPreservingFPLogic.cpp @@ -0,0 +1,3 @@ +bool RISCVTargetLowering :: hasBitPreservingFPLogic ( EVT VT ) const { +return ( VT == MVT :: f16 && Subtarget . hasStdExtZfh ( ) ) || ( VT == MVT :: f32 && Subtarget . hasStdExtF ( ) ) || ( VT == MVT :: f64 && Subtarget . hasStdExtD ( ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/isCheapToSpeculateCtlz.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/isCheapToSpeculateCtlz.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4427dc250a9b14b0605fc29f282b714b447e3b48 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/isCheapToSpeculateCtlz.cpp @@ -0,0 +1,3 @@ +bool RISCVTargetLowering :: isCheapToSpeculateCtlz ( ) const { +return Subtarget . hasStdExtZbb ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/isCheapToSpeculateCttz.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/isCheapToSpeculateCttz.cpp new file mode 100644 index 0000000000000000000000000000000000000000..41b20d8233d4b501a3330b31305ac754f057073c --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/isCheapToSpeculateCttz.cpp @@ -0,0 +1,3 @@ +bool RISCVTargetLowering :: isCheapToSpeculateCttz ( ) const { +return Subtarget . hasStdExtZbb ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/isDesirableToCommuteWithShift.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/isDesirableToCommuteWithShift.cpp new file mode 100644 index 0000000000000000000000000000000000000000..eaa72c8ecfe7d984d0c39a275176b30dc93cdcdd --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/isDesirableToCommuteWithShift.cpp @@ -0,0 +1,8 @@ +bool RISCVTargetLowering :: isDesirableToCommuteWithShift ( const SDNode * N , CombineLevel Level ) const { +if ( Level == BeforeLegalizeTypes ) { +return true ; +return true ; +if ( N -> getOpcode ( ) != ISD :: SHL ) { +return true ; +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/isEligibleForTailCallOptimization.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/isEligibleForTailCallOptimization.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9663f6712e4cedfd95144b31ae165430cc5d719b --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/isEligibleForTailCallOptimization.cpp @@ -0,0 +1,23 @@ +bool RISCVTargetLowering :: isEligibleForTailCallOptimization ( CCState & CCInfo , CallLoweringInfo & CLI , MachineFunction & MF , const SmallVector < CCValAssign , 16 > & ArgLocs ) const { +MachineFunction & MF = DAG . getMachineFunction ( ) ; +const Function & CallerF = MF . getFunction ( ) ; +CallingConv :: ID CallerCC = CallerF . getCallingConv ( ) ; +bool CCMatch = CallerCC == CalleeCC ; +for ( Function :: const_arg_iterator i = CallerF . arg_begin ( ) , e = CallerF . arg_end ( ) ; i != e ; ++ i ) { +if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { +const GlobalValue * GV = G -> getGlobal ( ) ; +if ( GV -> hasExternalWeakLinkage ( ) ) { +return false ; +} +if ( GV -> hasExternalWeakLinkage ( ) ) { +if ( TT . isOSBinFormatELF ( ) ) { +return false ; +} +if ( GV -> hasExternalWeakLinkage ( ) ) { +return false ; +} +} +assert ( ( ! isVarArg || CalleeCC == CallingConv :: C ) && "Unexpected variadic calling convention" ) ; +for ( const CCValAssign & ArgLoc : ArgLocs ) { +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/isFMAFasterThanFMulAndFAdd.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/isFMAFasterThanFMulAndFAdd.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ba3288894950b3d49166d803f88732c98e0db5d3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/isFMAFasterThanFMulAndFAdd.cpp @@ -0,0 +1,16 @@ +bool RISCVTargetLowering :: isFMAFasterThanFMulAndFAdd ( const MachineFunction & MF , EVT VT ) const { +VT = VT . getScalarType ( ) ; +if ( ! VT . isSimple ( ) ) { +return false ; +} +if ( VT . getSimpleVT ( ) . SimpleTy == MVT :: f16 ) { +return Subtarget . hasStdExtZfh ( ) ; +} +if ( VT . getSimpleVT ( ) . SimpleTy == MVT :: f32 ) { +return Subtarget . hasStdExtF ( ) ; +} +if ( VT . getSimpleVT ( ) . SimpleTy == MVT :: f64 ) { +return Subtarget . hasStdExtD ( ) ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/isFPImmLegal.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/isFPImmLegal.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1e059ba3b083f586ba645b41d656c18f0eb2ff5c --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/isFPImmLegal.cpp @@ -0,0 +1,24 @@ +bool RISCVTargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT , bool ForCodeSize ) const { +if ( VT == MVT :: f16 ) { +if ( Subtarget . hasFullFP16 ( ) ) { +return RISCV_AM :: getFP16Imm ( Imm ) != - 1 ; +} +} +if ( VT == MVT :: f32 ) { +return RISCV_AM :: getFP32Imm ( Imm ) != - 1 ; +} +if ( VT == MVT :: f64 ) { +if ( Subtarget . isFPOnlySP ( ) ) { +return RISCV_AM :: getFP64Imm ( Imm ) != - 1 ; +} +} +if ( VT != MVT :: f32 ) { +if ( VT != MVT :: f64 ) { +return false ; +} +} +if ( Imm . isNegZero ( ) ) { +return false ; +} +return Imm . isZero ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/isLegalAddImmediate.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/isLegalAddImmediate.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7d5834d6144049eae3dbf3fe6dd9e28a4b8c13a2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/isLegalAddImmediate.cpp @@ -0,0 +1,3 @@ +bool RISCVTargetLowering :: isLegalAddImmediate ( int64_t Imm ) const { +return isInt < 12 > ( Imm ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/isLegalAddressingMode.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/isLegalAddressingMode.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4d12ec1c1b567ebfad0025a54909a62c21f78173 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/isLegalAddressingMode.cpp @@ -0,0 +1,17 @@ +bool RISCVTargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS , Instruction * I ) const { +if ( AM . BaseGV ) { +return false ; +} +if ( ! isInt < 12 > ( AM . BaseOffs ) ) { +return false ; +} +if ( AM . Scale == 0 ) { +return true ; +} +if ( AM . Scale == 1 ) { +if ( ! AM . HasBaseReg ) { +return true ; +} +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/isLegalICmpImmediate.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/isLegalICmpImmediate.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cbde0e488134a5c31dc0832326826d473fc641a9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/isLegalICmpImmediate.cpp @@ -0,0 +1,3 @@ +bool RISCVTargetLowering :: isLegalICmpImmediate ( int64_t Imm ) const { +return isInt < 12 > ( Imm ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/isSExtCheaperThanZExt.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/isSExtCheaperThanZExt.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d72959088a6b5a01d516575ba586b3c4e1e98549 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/isSExtCheaperThanZExt.cpp @@ -0,0 +1,3 @@ +bool RISCVTargetLowering :: isSExtCheaperThanZExt ( EVT VT1 , EVT VT2 ) const { +return Subtarget . is64Bit ( ) && VT1 == MVT :: i32 && VT2 == MVT :: i64 ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/isTruncateFree.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/isTruncateFree.cpp new file mode 100644 index 0000000000000000000000000000000000000000..99032499ffe75c5f3f92460c5e05943f6952eb16 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/isTruncateFree.cpp @@ -0,0 +1,14 @@ +bool RISCVTargetLowering :: isTruncateFree ( Type * SrcTy , Type * DstTy ) const { +if ( Subtarget . is64Bit ( ) ) { +return false ; +} +if ( ! SrcTy -> isIntegerTy ( ) ) { +return false ; +} +if ( ! DstTy -> isIntegerTy ( ) ) { +return false ; +} +unsigned NumBits1 = SrcTy -> getPrimitiveSizeInBits ( ) ; +unsigned NumBits2 = DstTy -> getPrimitiveSizeInBits ( ) ; +return NumBits1 == 64 && NumBits2 == 32 ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/isTruncateFree2.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/isTruncateFree2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..76397e4a0806301acd38defcccf149b328bc5615 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/isTruncateFree2.cpp @@ -0,0 +1,20 @@ +bool RISCVTargetLowering :: isTruncateFree ( EVT SrcVT , EVT DstVT ) const { +if ( Subtarget . is64Bit ( ) ) { +return false ; +} +if ( SrcVT . isVector ( ) ) { +return false ; +} +if ( DstVT . isVector ( ) ) { +return false ; +} +if ( ! SrcVT . isInteger ( ) ) { +return false ; +} +if ( ! DstVT . isInteger ( ) ) { +return false ; +} +unsigned SrcBits = SrcVT . getSizeInBits ( ) ; +unsigned DestBits = DstVT . getSizeInBits ( ) ; +return ( SrcBits == 64 && DestBits == 32 ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/isZExtFree.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/isZExtFree.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fcbba94cbf602366fad80d1244d09825914acb64 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/isZExtFree.cpp @@ -0,0 +1,37 @@ +bool RISCVTargetLowering :: isZExtFree ( SDValue Val , EVT VT2 ) const { +if ( auto * LD = dyn_cast < LoadSDNode > ( Val ) ) { +EVT MemVT = LD -> getMemoryVT ( ) ; +if ( MemVT == MVT :: i1 ) { +if ( LD -> getExtensionType ( ) == ISD :: NON_EXTLOAD ) { +return true ; +if ( LD -> getExtensionType ( ) == ISD :: ZEXTLOAD ) { +return true ; +if ( MemVT == MVT :: i8 ) { +if ( LD -> getExtensionType ( ) == ISD :: NON_EXTLOAD ) { +return true ; +} +if ( LD -> getExtensionType ( ) == ISD :: ZEXTLOAD ) { +return true ; +} +} +if ( MemVT == MVT :: i16 ) { +if ( LD -> getExtensionType ( ) == ISD :: NON_EXTLOAD ) { +return true ; +} +if ( LD -> getExtensionType ( ) == ISD :: ZEXTLOAD ) { +return true ; +} +} +if ( MemVT == MVT :: i32 ) { +if ( Subtarget . is64Bit ( ) ) { +if ( LD -> getExtensionType ( ) == ISD :: NON_EXTLOAD ) { +return true ; +} +if ( LD -> getExtensionType ( ) == ISD :: ZEXTLOAD ) { +return true ; +} +} +} +} +return TargetLowering :: isZExtFree ( Val , VT2 ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/lowerEXTRACT_VECTOR_ELT.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/lowerEXTRACT_VECTOR_ELT.cpp new file mode 100644 index 0000000000000000000000000000000000000000..80a380dfc2b84af4c8b934700e6392727ea8c615 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/lowerEXTRACT_VECTOR_ELT.cpp @@ -0,0 +1,15 @@ +SDValue RISCVTargetLowering :: lowerEXTRACT_VECTOR_ELT ( SDValue Op , SelectionDAG & DAG ) const { +return Op ; +return Op ; +return Op ; +return Op ; +return Op ; +return Op ; +SDLoc DL ( Op ) ; +SDValue Idx = Op . getOperand ( 1 ) ; +Result = DAG . getNode ( ISD :: TRUNCATE , SL , MVT :: i16 , Result ) ; +MVT VecTy = ty ( Vec ) ; +return Op ; +return Op ; +SDValue Res = DAG . getNode ( ISD :: EXTRACT_VECTOR_ELT , DL , IntVT , DAG . getNode ( ISD :: BITCAST , DL , IntVecVT , Op0 ) , Op1 ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/lowerINSERT_VECTOR_ELT.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/lowerINSERT_VECTOR_ELT.cpp new file mode 100644 index 0000000000000000000000000000000000000000..39244c32b1a8f2f48d211bcfd180c40890ec7729 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/lowerINSERT_VECTOR_ELT.cpp @@ -0,0 +1,10 @@ +SDValue RISCVTargetLowering :: lowerINSERT_VECTOR_ELT ( SDValue Op , SelectionDAG & DAG ) const { +SDLoc dl ( Op ) ; +SDValue V1 = Op . getOperand ( 0 ) ; +SDValue V2 = Op . getOperand ( 1 ) ; +SDLoc SL ( Op ) ; +SDValue Vec = Op . getOperand ( 0 ) ; +SDValue Val = DAG . getNode ( ISD :: BITCAST , SL , MVT :: i16 , Op . getOperand ( 1 ) ) ; +SDValue BCVec = DAG . getNode ( ISD :: BITCAST , SL , MVT :: i32 , Vec ) ; +SDValue Res = DAG . getNode ( ISD :: INSERT_VECTOR_ELT , DL , IntVecVT , DAG . getNode ( ISD :: BITCAST , DL , IntVecVT , Op0 ) , DAG . getNode ( ISD :: BITCAST , DL , IntVT , Op1 ) , Op2 ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/lowerSELECT.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/lowerSELECT.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d4cee3b7c82e61d3c23a706ad7971bd0b7bc7ef6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/lowerSELECT.cpp @@ -0,0 +1,27 @@ +SDValue RISCVTargetLowering :: lowerSELECT ( SDValue Op , SelectionDAG & DAG ) const { +SDValue CondV = Op . getOperand ( 0 ) ; +SDValue TrueV = Op . getOperand ( 1 ) ; +SDValue FalseV = Op . getOperand ( 2 ) ; +SDLoc DL ( Op ) ; +MVT XLenVT = Subtarget . getXLenVT ( ) ; +if ( Op . getSimpleValueType ( ) == XLenVT ) { +if ( CondV . getOperand ( 0 ) . getSimpleValueType ( ) == XLenVT ) { +if ( CondV . getOpcode ( ) == ISD :: SETCC ) { +SDValue LHS = CondV . getOperand ( 0 ) ; +SDValue RHS = CondV . getOperand ( 1 ) ; +auto CC = cast < CondCodeSDNode > ( CondV . getOperand ( 2 ) ) ; +ISD :: CondCode CCVal = CC -> get ( ) ; +normaliseSetCC ( LHS , RHS , CCVal ) ; +SDValue TargetCC = DAG . getConstant ( CCVal , DL , XLenVT ) ; +auto VTs = Op . getValueType ( ) ; +SDValue Ops [ ] = { LHS , RHS , TargetCC , TrueV , FalseV } ; +return DAG . getNode ( RISCVISD :: SELECT_CC , DL , VTs , Ops ) ; +} +} +} +SDValue Zero = DAG . getConstant ( 0 , DL , XLenVT ) ; +SDValue SetNE = DAG . getConstant ( ISD :: SETNE , DL , XLenVT ) ; +auto VTs = Op . getValueType ( ) ; +SDValue Ops [ ] = { CondV , Zero , SetNE , TrueV , FalseV } ; +return DAG . getNode ( RISCVISD :: SELECT_CC , DL , VTs , Ops ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/lowerSPLATVECTOR.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/lowerSPLATVECTOR.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7022898f76521dad4874a7e3cc1905b9a1017dd4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/lowerSPLATVECTOR.cpp @@ -0,0 +1,19 @@ +SDValue RISCVTargetLowering :: lowerSPLATVECTOR ( SDValue Op , SelectionDAG & DAG ) const { +assert ( ! Subtarget . is64Bit ( ) && VecVT . getVectorElementType ( ) == MVT :: i64 && "Unexpected SPLAT_VECTOR lowering" ) ; +SDLoc DL ( Op ) ; +SDValue N1 = Op . getOperand ( 0 ) ; +unsigned SrcSize = N1 . getValueType ( ) . getSizeInBits ( ) ; +SDValue WideSrc = SrcSize == 128 ? N1 : widenVec ( DAG , N1 , DL ) ; +unsigned TrgNumElts = TrgVT . getVectorNumElements ( ) ; +SmallVector < int , 16 > ShuffV ; +if ( Subtarget . isLittleEndian ( ) ) { +for ( unsigned i = 0 ; i < TrgNumElts ; ++ i ) { +ShuffV . push_back ( i * SizeMult ) ; +if ( Subtarget . isBigEndian ( ) ) { +for ( unsigned i = 1 ; i < TrgNumElts ; ++ i ) { +ShuffV . push_back ( i * SizeMult - 1 ) ; +for ( unsigned i = TrgNumElts ; i < WideNumElts ; ++ i ) { +ShuffV . push_back ( WideNumElts + 1 ) ; +SDValue Conv = DAG . getNode ( ISD :: BITCAST , DL , WideVT , WideSrc ) ; +return DAG . getVectorShuffle ( WideVT , DL , Conv , DAG . getUNDEF ( WideVT ) , ShuffV ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/lowerShiftLeftParts.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/lowerShiftLeftParts.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1e7868e4bb56096f70d5c71d642f5a39eea21ec5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/lowerShiftLeftParts.cpp @@ -0,0 +1,40 @@ +SDValue RISCVTargetLowering :: lowerShiftLeftParts ( SDValue Op , SelectionDAG & DAG ) const { +EVT VT = Op . getValueType ( ) ; +unsigned VTBits = VT . getSizeInBits ( ) ; +SDLoc DL ( Op ) ; +MVT VT = Subtarget . isGP64bit ( ) ? MVT :: i64 : MVT :: i32 ; +SDValue Lo = Op . getOperand ( 0 ) ; +SDValue Hi = Op . getOperand ( 1 ) ; +SDValue Shamt = Op . getOperand ( 2 ) ; +SDValue RevShAmt = DAG . getNode ( ISD :: SUB , DL , MVT :: i64 , DAG . getConstant ( VTBits , MVT :: i64 ) , Shamt ) ; +SDValue Tmp1 = DAG . getNode ( ISD :: SRL , DL , VT , Lo , RevShAmt ) ; +SDValue ExtraShAmt = DAG . getNode ( ISD :: SUB , DL , MVT :: i64 , Shamt , DAG . getConstant ( VTBits , MVT :: i64 ) ) ; +SDValue Tmp2 = DAG . getNode ( ISD :: SHL , DL , VT , Hi , Shamt ) ; +SDValue Tmp3 = DAG . getNode ( ISD :: SHL , DL , VT , Lo , ExtraShAmt ) ; +SDValue FalseVal = DAG . getNode ( ISD :: OR , DL , VT , Tmp1 , Tmp2 ) ; +SDValue Tmp4 = DAG . getNode ( ISD :: SHL , DL , VT , Lo , Shamt ) ; +SDValue CmpOp = getSelectableIntSetCC ( ExtraShAmt , DAG . getConstant ( 0 , MVT :: i64 ) , ISD :: SETGE , A64cc , DAG , DL ) ; +SDValue CCR = DAG . getRegister ( RISCV :: CPSR , MVT :: i32 ) ; +SDValue Cmp = getRISCVCmp ( ExtraShAmt , DAG . getConstant ( 0 , MVT :: i32 ) , ISD :: SETGE , RISCVcc , DAG , DL ) ; +SDValue Ops [ 2 ] = { Lo , Hi } ; +EVT VT = Lo . getValueType ( ) ; +SDValue Zero = DAG . getConstant ( 0 , DL , VT ) ; +SDValue One = DAG . getConstant ( 1 , DL , VT ) ; +SDValue MinusRegisterSize = DAG . getConstant ( - 32 , DL , VT ) ; +SDValue RegisterSizeMinus1 = DAG . getConstant ( 32 - 1 , DL , VT ) ; +SDValue ShamtMinusRegisterSize = DAG . getNode ( ISD :: ADD , DL , VT , Shamt , MinusRegisterSize ) ; +SDValue RegisterSizeMinus1Shamt = DAG . getNode ( ISD :: XOR , DL , VT , RegisterSizeMinus1 , Shamt ) ; +SDValue LoTrue = DAG . getNode ( ISD :: SHL , DL , VT , Lo , Shamt ) ; +SDValue Not = DAG . getNode ( ISD :: XOR , DL , MVT :: i32 , Shamt , DAG . getConstant ( - 1 , MVT :: i32 ) ) ; +SDValue ShiftLeftHi = DAG . getNode ( ISD :: SHL , DL , VT , Hi , Shamt ) ; +SDValue HiTrue = DAG . getNode ( ISD :: OR , DL , VT , ShiftLeftHi , ShiftRightLo ) ; +SDValue HiFalse = DAG . getNode ( ISD :: SHL , DL , VT , Lo , ShamtMinusRegisterSize ) ; +SDValue CC = DAG . getSetCC ( DL , MVT :: i8 , ShamtMinusRegisterSize , Zero , ISD :: SETLT ) ; +SDValue Or = DAG . getNode ( ISD :: OR , DL , VT , ShiftLeftHi , ShiftRightLo ) ; +SDValue ShiftLeftLo = DAG . getNode ( ISD :: SHL , DL , VT , Lo , Shamt ) ; +SDValue Cond = DAG . getNode ( ISD :: AND , DL , MVT :: i32 , Shamt , DAG . getConstant ( VT . getSizeInBits ( ) , MVT :: i32 ) ) ; +Lo = DAG . getNode ( ISD :: SELECT , DL , VT , CC , LoTrue , Zero ) ; +Hi = DAG . getNode ( ISD :: SELECT , DL , VT , CC , HiTrue , HiFalse ) ; +SDValue Ops [ 2 ] = { Lo , Hi } ; +return DAG . getMergeValues (Parts , DL ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/lowerShiftRightParts.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/lowerShiftRightParts.cpp new file mode 100644 index 0000000000000000000000000000000000000000..030cb3ec045fd289c527d89453b2f9dbd9184904 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/lowerShiftRightParts.cpp @@ -0,0 +1,56 @@ +SDValue RISCVTargetLowering :: lowerShiftRightParts ( SDValue Op , SelectionDAG & DAG , bool IsSRA ) const { +EVT VT = Op . getValueType ( ) ; +unsigned VTBits = VT . getSizeInBits ( ) ; +SDLoc DL ( Op ) ; +SDValue ShOpLo = Op . getOperand ( 0 ) ; +SDValue ShOpHi = Op . getOperand ( 1 ) ; +SDValue ShAmt = Op . getOperand ( 2 ) ; +unsigned Opc = ( Op . getOpcode ( ) == ISD :: SRA_PARTS ) ? ISD :: SRA : ISD :: SRL ; +SDValue RevShAmt = DAG . getNode ( ISD :: SUB , DL , MVT :: i64 , DAG . getConstant ( VTBits , DL , MVT :: i64 ) , ShAmt ) ; +SDValue Tmp1 = DAG . getNode ( ISD :: SRL , DL , VT , ShOpLo , ShAmt ) ; +SDValue ExtraShAmt = DAG . getNode ( ISD :: SUB , DL , MVT :: i64 , ShAmt , DAG . getConstant ( VTBits , DL , MVT :: i64 ) ) ; +SDValue Tmp2 = DAG . getNode ( ISD :: SHL , DL , VT , ShOpHi , RevShAmt ) ; +SDValue FalseVal = DAG . getNode ( ISD :: OR , DL , VT , Tmp1 , Tmp2 ) ; +SDValue TrueVal = DAG . getNode ( Opc , DL , VT , ShOpHi , ExtraShAmt ) ; +SDValue CCR = DAG . getRegister ( RISCV :: CPSR , MVT :: i32 ) ; +SDValue Cmp = emitComparison ( ExtraShAmt , DAG . getConstant ( 0 , DL , MVT :: i64 ) , ISD :: SETGE , DL , DAG ) ; +SDValue CCVal = DAG . getConstant ( RISCVCC :: GE , DL , MVT :: i32 ) ; +SDValue FalseValLo = DAG . getNode ( ISD :: OR , DL , VT , Tmp1 , Tmp2 ) ; +SDValue TrueValLo = DAG . getNode ( Opc , DL , VT , ShOpHi , ExtraShAmt ) ; +SDValue Lo = Op . getOperand ( 0 ) ; +SDValue FalseValHi = DAG . getNode ( Opc , DL , VT , ShOpHi , ShAmt ) ; +SDValue TrueValHi = Opc == ISD :: SRA ? DAG . getNode ( Opc , DL , VT , ShOpHi , DAG . getConstant ( VTBits - 1 , DL , MVT :: i64 ) ) : DAG . getConstant ( 0 , DL , VT ) ; +SDValue Hi = Op . getOperand ( 1 ) ; +SDValue Lo = DAG . getNode ( RISCVISD :: CMOV , DL , VT , FalseVal , TrueVal , RISCVcc , CCR , Cmp ) ; +SDValue Ops [ 2 ] = { Lo , Hi } ; +SDValue Lo = Op . getOperand ( 0 ) , Hi = Op . getOperand ( 1 ) ; +SDValue Shamt = Op . getOperand ( 2 ) ; +EVT VT = Lo . getValueType ( ) ; +unsigned ShiftRightOp = IsSRA ? ISD :: SRA : ISD :: SRL ; +SDValue Zero = DAG . getConstant ( 0 , DL , VT ) ; +SDValue One = DAG . getConstant ( 1 , DL , VT ) ; +SDValue MinusRegisterSize = DAG . getConstant ( - 32 , DL , VT ) ; +SDValue RegisterSizeMinus1 = DAG . getConstant ( 32 - 1 , DL , VT ) ; +SDValue ShamtMinusRegisterSize = DAG . getNode ( ISD :: ADD , DL , VT , Shamt , MinusRegisterSize ) ; +SDValue RegisterSizeMinus1Shamt = DAG . getNode ( ISD :: XOR , DL , VT , RegisterSizeMinus1 , Shamt ) ; +SDValue ShiftRightLo = DAG . getNode ( ISD :: SRL , DL , VT , Lo , Shamt ) ; +SDValue ShiftLeftHi1 = DAG . getNode ( ISD :: SHL , DL , VT , Hi , One ) ; +MVT VT = Subtarget . isGP64bit ( ) ? MVT :: i64 : MVT :: i32 ; +SDValue Not = DAG . getNode ( ISD :: XOR , DL , MVT :: i32 , Shamt , DAG . getConstant ( - 1 , MVT :: i32 ) ) ; +SDValue ShiftLeft1Hi = DAG . getNode ( ISD :: SHL , DL , VT , Hi , DAG . getConstant ( 1 , VT ) ) ; +SDValue ShiftLeftHi = DAG . getNode ( ISD :: SHL , DL , VT , ShiftLeftHi1 , RegisterSizeMinus1Shamt ) ; +SDValue LoTrue = DAG . getNode ( ISD :: OR , DL , VT , ShiftRightLo , ShiftLeftHi ) ; +SDValue HiTrue = DAG . getNode ( ShiftRightOp , DL , VT , Hi , Shamt ) ; +SDValue LoFalse = DAG . getNode ( ShiftRightOp , DL , VT , Hi , ShamtMinusRegisterSize ) ; +SDValue HiFalse = IsSRA ? DAG . getNode ( ISD :: SRA , DL , VT , Hi , RegisterSizeMinus1 ) : Zero ; +SDValue CC = DAG . getSetCC ( DL , MVT :: i8 , ShamtMinusRegisterSize , Zero , ISD :: SETLT ) ; +SDValue ShiftRightLo = DAG . getNode ( ISD :: SRL , DL , VT , Lo , Shamt ) ; +SDValue Or = DAG . getNode ( ISD :: OR , DL , VT , ShiftLeftHi , ShiftRightLo ) ; +SDValue ShiftRightHi = DAG . getNode ( IsSRA ? ISD :: SRA : ISD :: SRL , DL , VT , Hi , Shamt ) ; +SDValue Cond = DAG . getNode ( ISD :: AND , DL , MVT :: i32 , Shamt , DAG . getConstant ( VT . getSizeInBits ( ) , MVT :: i32 ) ) ; +SDValue Ext = DAG . getNode ( ISD :: SRA , DL , VT , Hi , DAG . getConstant ( VT . getSizeInBits ( ) - 1 , VT ) ) ; +Lo = DAG . getNode ( ISD :: SELECT , DL , VT , CC , LoTrue , LoFalse ) ; +Hi = DAG . getNode ( ISD :: SELECT , DL , VT , CC , HiTrue , HiFalse ) ; +SDValue Ops [ 2 ] = { Lo , Hi } ; +return DAG . getMergeValues (Parts , DL ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/lowerVectorMaskExt.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/lowerVectorMaskExt.cpp new file mode 100644 index 0000000000000000000000000000000000000000..230cf468a4445c364d402e6551db9fbfd5cc3121 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/lowerVectorMaskExt.cpp @@ -0,0 +1,15 @@ +static SDValue RISCVTargetLowering :: lowerVectorMaskExt ( SDValue Op , SelectionDAG & DAG , int64_t ExtTrueVal ) const { +SDLoc DL ( N ) ; +EVT VT = N -> getValueType ( 0 ) ; +if ( VT . getSizeInBits ( ) . getKnownMinSize ( ) != RISCV :: SVEBitsPerBlock ) { +return SDValue ( ) ; +} +unsigned ElemSize = VT . getVectorElementType ( ) . getSizeInBits ( ) / 8 ; +unsigned ByteSize = VT . getSizeInBits ( ) . getKnownMinSize ( ) / 8 ; +EVT ByteVT = EVT :: getVectorVT ( Ctx , MVT :: i8 , { ByteSize , true } ) ; +if ( ! ST -> hasMVEFloatOps ( ) ) { +return SDValue ( ) ; +} +SDLoc DL ( BV ) ; +EVT VT = BV . getValueType ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/lowerVectorMaskTrunc.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/lowerVectorMaskTrunc.cpp new file mode 100644 index 0000000000000000000000000000000000000000..dc8a3001fca52c0616d830e6b54b93fdc98dd831 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/lowerVectorMaskTrunc.cpp @@ -0,0 +1,33 @@ +SDValue RISCVTargetLowering :: lowerVectorMaskTrunc ( SDValue Op , SelectionDAG & DAG ) const { +assert ( MaskVT . isVector ( ) && MaskVT . getVectorElementType ( ) == MVT :: i1 ) && "Unexpected type for vector mask lowering" ) ; +if ( ! ST -> hasMVEFloatOps ( ) ) { +return SDValue ( ) ; +SDLoc dl ( BV ) ; +if ( VT != MVT :: v8f16 ) { +return SDValue ( ) ; +if ( BV . getOperand ( 0 ) . getOpcode ( ) != ISD :: FP_ROUND ) { +return SDValue ( ) ; +if ( BV . getOperand ( 0 ) . getOperand ( 0 ) . getOpcode ( ) != ISD :: EXTRACT_VECTOR_ELT ) { +return SDValue ( ) ; +if ( BV . getOperand ( 0 ) . getOperand ( 0 ) . getConstantOperandVal ( 1 ) != 0 ) { +return SDValue ( ) ; +if ( BV . getOperand ( 1 ) . getOpcode ( ) != ISD :: FP_ROUND ) { +return SDValue ( ) ; +if ( BV . getOperand ( 1 ) . getOperand ( 0 ) . getOpcode ( ) != ISD :: EXTRACT_VECTOR_ELT ) { +return SDValue ( ) ; +if ( BV . getOperand ( 1 ) . getOperand ( 0 ) . getConstantOperandVal ( 1 ) != 0 ) { +return SDValue ( ) ; +SDValue Op0 = BV . getOperand ( 0 ) . getOperand ( 0 ) . getOperand ( 0 ) ; +SDValue Op1 = BV . getOperand ( 1 ) . getOperand ( 0 ) . getOperand ( 0 ) ; +if ( Op0 . getValueType ( ) != MVT :: v4f32 ) { +return SDValue ( ) ; +if ( Op1 . getValueType ( ) != MVT :: v4f32 ) { +return SDValue ( ) ; +for ( unsigned i = 1 ; i < 4 ; i ++ ) { +if ( ! Check ( BV . getOperand ( i * 2 + 0 ) , Op0 , i ) ) { +return SDValue ( ) ; +if ( ! Check ( BV . getOperand ( i * 2 + 1 ) , Op1 , i ) ) { +return SDValue ( ) ; +SDValue N1 = DAG . getNode ( RISCVISD :: VCVTN , dl , VT , DAG . getUNDEF ( VT ) , Op0 , DAG . getConstant ( 0 , dl , MVT :: i32 ) ) ; +return DAG . getNode ( RISCVISD :: VCVTN , dl , VT , N1 , Op1 , DAG . getConstant ( 1 , dl , MVT :: i32 ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/mayBeEmittedAsTailCall.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/mayBeEmittedAsTailCall.cpp new file mode 100644 index 0000000000000000000000000000000000000000..56c56592ac7a191998c82a0bc8dd7a27e2218fa9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/mayBeEmittedAsTailCall.cpp @@ -0,0 +1,6 @@ +bool RISCVTargetLowering :: mayBeEmittedAsTailCall ( const CallInst * CI ) const { +if ( CI -> isTailCall ( ) ) { +return true ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/normaliseSetCC.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/normaliseSetCC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5e8ca14d17c2c96e01f50cf003b660fd552090a8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/normaliseSetCC.cpp @@ -0,0 +1,22 @@ +static void normaliseSetCC ( SDValue & LHS , SDValue & RHS , ISD :: CondCode & CC ) { +if ( CC == ISD :: SETGT ) { +CC = ISD :: getSetCCSwappedOperands ( CC ) ; +std :: swap ( LHS , RHS ) ; +return ; +} +if ( CC == ISD :: SETLE ) { +CC = ISD :: getSetCCSwappedOperands ( CC ) ; +std :: swap ( LHS , RHS ) ; +return ; +} +if ( CC == ISD :: SETUGT ) { +CC = ISD :: getSetCCSwappedOperands ( CC ) ; +std :: swap ( LHS , RHS ) ; +return ; +} +if ( CC == ISD :: SETULE ) { +CC = ISD :: getSetCCSwappedOperands ( CC ) ; +std :: swap ( LHS , RHS ) ; +return ; +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/normalizeSetCC.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/normalizeSetCC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f68f25a787d6d9d179404a12f57ee6bc55abf05a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/normalizeSetCC.cpp @@ -0,0 +1,2 @@ +static void normaliseSetCC(SDValue &LHS, SDValue &RHS, ISD::CondCode &CC) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/shouldConsiderGEPOffsetSplit.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/shouldConsiderGEPOffsetSplit.cpp new file mode 100644 index 0000000000000000000000000000000000000000..aea7b13466bda38ef605e932c0424e464e006d3c --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/shouldConsiderGEPOffsetSplit.cpp @@ -0,0 +1,3 @@ +bool shouldConsiderGEPOffsetSplit ( ) const override { +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/shouldConvertConstantLoadToIntImm.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/shouldConvertConstantLoadToIntImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c6c4f52e649ae4b4b1a72eabf7992953c6c65f9e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/shouldConvertConstantLoadToIntImm.cpp @@ -0,0 +1,3 @@ +bool shouldConvertConstantLoadToIntImm ( const APInt & Imm , Type * Ty ) const override { +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/shouldExpandAtomicCmpXchgInIR.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/shouldExpandAtomicCmpXchgInIR.cpp new file mode 100644 index 0000000000000000000000000000000000000000..03f57c86bfe6399a80de39551a813c90cd79abcd --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/shouldExpandAtomicCmpXchgInIR.cpp @@ -0,0 +1,10 @@ +TargetLowering :: AtomicExpansionKind RISCVTargetLowering :: shouldExpandAtomicCmpXchgInIR ( AtomicCmpXchgInst * AI ) const { +unsigned Size = AI -> getCompareOperand ( ) -> getType ( ) -> getPrimitiveSizeInBits ( ) ; +if ( Size == 8 ) { +return AtomicExpansionKind :: MaskedIntrinsic ; +} +if ( Size == 16 ) { +return AtomicExpansionKind :: MaskedIntrinsic ; +} +return AtomicExpansionKind :: None ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/shouldExpandAtomicRMWInIR.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/shouldExpandAtomicRMWInIR.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7e947ccb45d4f2d7405aacabf6dfdab7a87049b3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/shouldExpandAtomicRMWInIR.cpp @@ -0,0 +1,13 @@ +TargetLowering :: AtomicExpansionKind RISCVTargetLowering :: shouldExpandAtomicRMWInIR ( AtomicRMWInst * AI ) const { +if ( AI -> isFloatingPointOperation ( ) ) { +return AtomicExpansionKind :: CmpXChg ; +} +unsigned Size = AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; +if ( Size == 8 ) { +return AtomicExpansionKind :: MaskedIntrinsic ; +} +if ( Size == 16 ) { +return AtomicExpansionKind :: MaskedIntrinsic ; +} +return AtomicExpansionKind :: None ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/shouldExpandShift.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/shouldExpandShift.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c810809a86725d91ae1c0fa0178381f6acebb69a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/shouldExpandShift.cpp @@ -0,0 +1,7 @@ +bool shouldExpandShift ( SelectionDAG & DAG , SDNode * N ) const override { +if ( DAG . getMachineFunction ( ) . getFunction ( ) . hasMinSize ( ) ) { +return false ; +return false ; +} +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/shouldExtendTypeInLibCall.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/shouldExtendTypeInLibCall.cpp new file mode 100644 index 0000000000000000000000000000000000000000..73655d0cb35912f63fadd5eef2ac7ccf71c9de52 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/shouldExtendTypeInLibCall.cpp @@ -0,0 +1,8 @@ +bool RISCVTargetLowering :: shouldExtendTypeInLibCall ( EVT Type ) const { +if ( Subtarget . abiUsesSoftFloat ( ) ) { +if ( Type == MVT :: i32 ) { +return true ; +} +} +return IsSigned ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/shouldInsertFencesForAtomic.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/shouldInsertFencesForAtomic.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1428347bf80aab4226352f9fbf46158c4494c134 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/shouldInsertFencesForAtomic.cpp @@ -0,0 +1,3 @@ +bool shouldInsertFencesForAtomic ( const Instruction * I ) const override { +return isa < LoadInst > ( I ) || isa < StoreInst > ( I ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/shouldSignExtendTypeInLibCall.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/shouldSignExtendTypeInLibCall.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a8f36cd9532f14f0a552656209ace736862ffdb5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/shouldSignExtendTypeInLibCall.cpp @@ -0,0 +1,8 @@ +bool RISCVTargetLowering :: shouldSignExtendTypeInLibCall ( EVT Type , bool IsSigned ) const { +if ( Subtarget . is64Bit ( ) ) { +if ( Type == MVT :: i32 ) { +return true ; +} +} +return IsSigned ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/targetShrinkDemandedConstant.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/targetShrinkDemandedConstant.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d63d128be2aa4f51d4d1721fc38b40a134711b00 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/targetShrinkDemandedConstant.cpp @@ -0,0 +1,33 @@ +bool RISCVTargetLowering :: targetShrinkDemandedConstant ( SDValue Op , const APInt & DemandedBits , const APInt & DemandedElts , TargetLoweringOpt & TLO ) const { +if ( ! TLO . LegalOps ) { +return false ; +} +EVT VT = Op . getValueType ( ) ; +if ( VT . isVector ( ) ) { +return false ; +} +if ( Op . getOpcode ( ) != ISD :: AND ) { +return false ; +} +unsigned Size = VT . getSizeInBits ( ) ; +ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op . getOperand ( 1 ) ) ; +if ( ! C ) { +return false ; +} +const APInt & Mask = C -> getAPIntValue ( ) ; +APInt ExpandedMask = Mask | ~ Demanded ; +if ( ShrunkMask == 0 ) { +return false ; +} +if ( ExpandedMask == ~ 0U ) { +return TLO . CombineTo ( Op , Op . getOperand ( 0 ) ) ; +} +if ( NewMask == Mask ) { +return true ; +} +return false ; +return false ; +SDLoc DL ( Op ) ; +SDValue NewOp = TLO . DAG . getNode ( ISD :: AND , DL , VT , Op . getOperand ( 0 ) , NewC ) ; +return TLO . CombineTo ( Op , NewOp ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/validateCCReservedRegs.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/validateCCReservedRegs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..08d730ae9daf2b7e0ae7effd7041b01d4dfd6935 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/ISelLowering/validateCCReservedRegs.cpp @@ -0,0 +1,11 @@ +void RISCVTargetLowering :: validateCCReservedRegs ( const SmallVectorImpl < std :: pair < llvm :: Register , llvm :: SDValue >> & Regs , MachineFunction & MF ) const { +auto * CA = dyn_cast < ConstantSDNode > ( Ptr ) ; +if ( ! CA ) { +return true ; +unsigned Addr = CA -> getZExtValue ( ) ; +return true ; +std :: string ErrMsg ; +raw_string_ostream O ( ErrMsg ) ; +if ( DebugLoc DL = dl . getDebugLoc ( ) ) { +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/InstructionSelector/InstructionSelector.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/InstructionSelector/InstructionSelector.cpp new file mode 100644 index 0000000000000000000000000000000000000000..53cc2835a41ac58f713da3322777b6baeda2bb12 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/InstructionSelector/InstructionSelector.cpp @@ -0,0 +1,9 @@ +RISCVInstructionSelector::RISCVInstructionSelector(const RISCVTargetMachine &TM, const RISCVSubtarget &STI,const RISCVRegisterBankInfo &RBI) : InstructionSelector(), STI(STI), TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()), RBI(RBI), +#define GET_GLOBALISEL_PREDICATES_INIT +#include "RISCVGenGlobalISel.inc" +#undef GET_GLOBALISEL_PREDICATES_INIT +#define GET_GLOBALISEL_TEMPORARIES_INIT +#include "RISCVGenGlobalISel.inc" +#undef GET_GLOBALISEL_TEMPORARIES_INIT +{ +} diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/InstructionSelector/createInstructionSelector.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/InstructionSelector/createInstructionSelector.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6ede3ab8f53f444fa23593c2acad51ad21bc8f27 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/InstructionSelector/createInstructionSelector.cpp @@ -0,0 +1,3 @@ +InstructionSelector * createRISCVInstructionSelector ( const RISCVTargetMachine & TM , RISCVSubtarget & Subtarget , RISCVRegisterBankInfo & RBI ) { +return new RISCVInstructionSelector ( TM , Subtarget , RBI ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/InstructionSelector/getName.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/InstructionSelector/getName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..740b6f1fbb4a3afc4ded45f1aa79d0fb35ce8a43 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/InstructionSelector/getName.cpp @@ -0,0 +1,3 @@ +static const char * getName ( ) { +return DEBUG_TYPE ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/InstructionSelector/select.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/InstructionSelector/select.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ce42c15be2bbe5d8c30dbf51033ebd0ae9508f5b --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/InstructionSelector/select.cpp @@ -0,0 +1,9 @@ +bool RISCVInstructionSelector :: select ( MachineInstr & I ) { +if ( ! isPreISelGenericOpcode ( I . getOpcode ( ) ) ) { +return true ; +} +if ( selectImpl ( I , * CoverageInfo ) ) { +return true ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/LegalizeInfo/LegalizerInfo.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/LegalizeInfo/LegalizerInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e79f38b38db881cf83b95d2eded06d891975f42d --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/LegalizeInfo/LegalizerInfo.cpp @@ -0,0 +1,3 @@ +RISCVLegalizerInfo :: RISCVLegalizerInfo ( const RISCVSubtarget & ST ) { +computeTables ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/MCInstLower/lowerMachineInstrToMCInst.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/MCInstLower/lowerMachineInstrToMCInst.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e7c5990a18b07e178c2bbb5817ccee060a72bfb7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/MCInstLower/lowerMachineInstrToMCInst.cpp @@ -0,0 +1,13 @@ +void llvm :: LowerMachineInstrToMCInst ( const MachineInstr * MI , MCInst & OutMI , const AsmPrinter & AP ) { +OutMI . setOpcode ( MI -> getOpcode ( ) ) ; +for ( const MachineOperand & MO : MI -> operands ( ) ) { +MCOperand MCOp ; +if ( MCOp . isValid ( ) ) { +OutMI . addOperand ( LowerOperand ( MI , MO , AP ) ) ; +} +LowerMachineOperandToMCOperand ( MO , MCOp , AP ) ; +if ( LowerMachineOperandToMCOperand ( MO , MCOp , AP ) ) { +OutMI . addOperand ( MCOp ) ; +} +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/MCInstLower/lowerMachineOperandToMCOperand.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/MCInstLower/lowerMachineOperandToMCOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..13385ff94e4c86b6a86a73070083bfcdc93e6b0a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/MCInstLower/lowerMachineOperandToMCOperand.cpp @@ -0,0 +1,41 @@ +bool llvm :: LowerRISCVMachineOperandToMCOperand ( const MachineOperand & MO , MCOperand & MCOp , const AsmPrinter & AP ) { +if ( MO . getType ( ) == MachineOperand :: MO_ConstantPoolIndex ) { +MCOp = lowerSymbolOperand ( MO , AP . GetCPISymbol ( MO . getIndex ( ) ) , AP ) ; +return true ; +} +if ( MO . getType ( ) == MachineOperand :: MO_JumpTableIndex ) { +MCOp = lowerSymbolOperand ( MO , AP . GetJTISymbol ( MO . getIndex ( ) ) , AP ) ; +return true ; +} +if ( MO . getType ( ) == MachineOperand :: MO_Register ) { +if ( MO . isImplicit ( ) ) { +return false ; +} +MCOp = MCOperand :: createReg ( MO . getReg ( ) ) ; +return true ; +} +if ( MO . getType ( ) == MachineOperand :: MO_Immediate ) { +MCOp = MCOperand :: createImm ( MO . getImm ( ) ) ; +return true ; +} +if ( MO . getType ( ) == MachineOperand :: MO_RegisterMask ) { +return false ; +} +if ( MO . getType ( ) == MachineOperand :: MO_MachineBasicBlock ) { +MCOp = lowerSymbolOperand ( MO , MO . getMBB ( ) -> getSymbol ( ) , AP ) ; +return true ; +} +if ( MO . getType ( ) == MachineOperand :: MO_GlobalAddress ) { +MCOp = lowerSymbolOperand ( MO , AP . getSymbol ( MO . getGlobal ( ) ) , AP ) ; +return true ; +} +if ( MO . getType ( ) == MachineOperand :: MO_BlockAddress ) { +MCOp = lowerSymbolOperand ( MO , AP . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) , AP ) ; +return true ; +} +if ( MO . getType ( ) == MachineOperand :: MO_ExternalSymbol ) { +MCOp = lowerSymbolOperand ( MO , AP . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) , AP ) ; +return true ; +} +report_fatal_error ( "LowerRISCVMachineInstrToMCInst: unknown operand type" ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/MCInstLower/lowerSymbolOperand.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/MCInstLower/lowerSymbolOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..91628062dcaa99768620b4effc89b2a9e86f7c71 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/RISCV/Selection/MCInstLower/lowerSymbolOperand.cpp @@ -0,0 +1,65 @@ +static MCOperand lowerSymbolOperand ( const MachineOperand & MO , MCSymbol * Sym , const AsmPrinter & AP ) { +MCContext & Ctx = AP . OutContext ; +const MCExpr * Expr = nullptr ; +Expr = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_RISCV_None , Ctx ) ; +if ( ! MO . isJTI ( ) ) { +if ( ! MO . isMBB ( ) ) { +if ( MO . getOffset ( ) ) { +Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( MO . getOffset ( ) , Ctx ) , Ctx ) ; +} +} +} +if ( MO . getTargetFlags ( ) == RISCVII :: MO_CALL ) { +Expr = RISCVMCExpr :: create ( Expr , RISCVMCExpr :: VK_CALL , Ctx ) ; +return MCOperand :: createExpr ( Expr ) ; +} +if ( MO . getTargetFlags ( ) == RISCVII :: MO_PLT ) { +Expr = RISCVMCExpr :: create ( Expr , RISCVMCExpr :: VK_CALL_PLT , Ctx ) ; +return MCOperand :: createExpr ( Expr ) ; +} +if ( MO . getTargetFlags ( ) == RISCVII :: MO_LO ) { +Expr = RISCVMCExpr :: create ( Expr , RISCVMCExpr :: VK_RISCV_LO , Ctx ) ; +return MCOperand :: createExpr ( Expr ) ; +} +if ( MO . getTargetFlags ( ) == RISCVII :: MO_HI ) { +Expr = RISCVMCExpr :: create ( Expr , RISCVMCExpr :: VK_HI , Ctx ) ; +return MCOperand :: createExpr ( Expr ) ; +} +if ( MO . getTargetFlags ( ) == RISCVII :: MO_PCREL_LO ) { +Expr = RISCVMCExpr :: create ( Expr , RISCVMCExpr :: VK_PCREL_LO , Ctx ) ; +return MCOperand :: createExpr ( Expr ) ; +} +if ( MO . getTargetFlags ( ) == RISCVII :: MO_PCREL_HI ) { +Expr = RISCVMCExpr :: create ( Expr , RISCVMCExpr :: VK_PCREL_HI , Ctx ) ; +return MCOperand :: createExpr ( Expr ) ; +} +if ( MO . getTargetFlags ( ) == RISCVII :: MO_GOT_HI ) { +Expr = RISCVMCExpr :: create ( Expr , RISCVMCExpr :: VK_GOT_HI , Ctx ) ; +return MCOperand :: createExpr ( Expr ) ; +} +if ( MO . getTargetFlags ( ) == RISCVII :: MO_TPREL_LO ) { +Expr = RISCVMCExpr :: create ( Expr , RISCVMCExpr :: VK_TPREL_LO , Ctx ) ; +return MCOperand :: createExpr ( Expr ) ; +} +if ( MO . getTargetFlags ( ) == RISCVII :: MO_TPREL_HI ) { +Expr = RISCVMCExpr :: create ( Expr , RISCVMCExpr :: VK_TPREL_HI , Ctx ) ; +return MCOperand :: createExpr ( Expr ) ; +} +if ( MO . getTargetFlags ( ) == RISCVII :: MO_TPREL_ADD ) { +Expr = RISCVMCExpr :: create ( Expr , RISCVMCExpr :: VK_TPREL_ADD , Ctx ) ; +return MCOperand :: createExpr ( Expr ) ; +} +if ( MO . getTargetFlags ( ) == RISCVII :: MO_TLS_GOT_HI ) { +Expr = RISCVMCExpr :: create ( Expr , RISCVMCExpr :: VK_TLS_GOT_HI , Ctx ) ; +return MCOperand :: createExpr ( Expr ) ; +} +if ( MO . getTargetFlags ( ) == RISCVII :: MO_TLS_GD_HI ) { +Expr = RISCVMCExpr :: create ( Expr , RISCVMCExpr :: VK_TLS_GD_HI , Ctx ) ; +return MCOperand :: createExpr ( Expr ) ; +} +if ( MO . getTargetFlags ( ) == RISCVII :: MO_None ) { +return MCOperand :: createExpr ( Expr ) ; +} +llvm_unreachable ( "Unknown target flag on GV operand" ) ; +return MCOperand :: createExpr ( Expr ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Allocation/RegisterInfo/RegisterInfo.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Allocation/RegisterInfo/RegisterInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d88da16534f44c4bf8a6f6486a0a281cc7de0ede --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Allocation/RegisterInfo/RegisterInfo.cpp @@ -0,0 +1,2 @@ +XCoreRegisterInfo :: XCoreRegisterInfo ( const TargetInstrInfo & tii ) : XCoreGenRegisterInfo ( XCore :: LR ) , TII ( tii ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Allocation/RegisterInfo/eliminateCallFramePseudoInstr.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Allocation/RegisterInfo/eliminateCallFramePseudoInstr.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c7ec4d140c0eeb48637efaac184d0ec9be3b26c2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Allocation/RegisterInfo/eliminateCallFramePseudoInstr.cpp @@ -0,0 +1,20 @@ +void XCoreRegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { +if ( ! TFI -> hasReservedCallFrame ( MF ) ) { +MachineInstr * Old = I ; +uint64_t Amount = Old -> getOperand ( 0 ) . getImm ( ) ; +if ( Amount != 0 ) { +unsigned Align = MF . getTarget ( ) . getFrameInfo ( ) -> getStackAlignment ( ) ; +Amount = ( Amount + Align - 1 ) / Align * Align ; +MachineInstr * New ; +if ( Old -> getOpcode ( ) == XCore :: ADJUSTSTACKDOWN ) { +New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( XCore :: LDA ) , XCore :: R30 ) . addImm ( - Amount ) . addReg ( XCore :: R30 ) ; +} +else { +assert ( Old -> getOpcode ( ) == XCore :: ADJUSTSTACKUP ) ; +New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( XCore :: LDA ) , XCore :: R30 ) . addImm ( Amount ) . addReg ( XCore :: R30 ) ; +} +MBB . insert ( I , New ) ; +} +} +MBB . erase ( I ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Allocation/RegisterInfo/eliminateFrameIndex.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Allocation/RegisterInfo/eliminateFrameIndex.cpp new file mode 100644 index 0000000000000000000000000000000000000000..73e769959121e6beb82a56e3ee5546877073e2e6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Allocation/RegisterInfo/eliminateFrameIndex.cpp @@ -0,0 +1,59 @@ +void XCoreRegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { +assert ( SPAdj == 0 && "Unexpected non-zero SPAdj value" ) ; +MachineInstr & MI = * II ; +MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; +MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; +DebugLoc DL = MI . getDebugLoc ( ) ; +const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; +DebugLoc dl = MI . getDebugLoc ( ) ; +int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; +Register FrameReg ; +MI . getOperand ( FIOperandNum ) . ChangeToRegister ( XCore :: SP , false ) ; +int OffsetOperandNo = FIOperandNum + 1 ; +int Offset = getFrameLowering ( MF ) -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) + MI . getOperand ( FIOperandNum + 1 ) . getImm ( ) ; +if ( ! isInt < 16 > ( Offset ) ) { +report_fatal_error ( "Frame offsets outside of the signed 16-bit range not supported" ) ; +} +MachineBasicBlock & MBB = * MI . getParent ( ) ; +const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; +const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; +MachineOperand & FIOp = MI . getOperand ( FIOperandNum ) ; +int FI = FIOp . getIndex ( ) ; +unsigned ImmOpIdx = 0 ; +const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; +unsigned DstReg = MI . getOperand ( 0 ) . getReg ( ) ; +if ( Offset == 0 ) { +MI . setDesc ( TII . get ( XCore :: MOV ) ) ; +MI . getOperand ( 1 ) . ChangeToRegister ( FrameReg , false ) ; +MI . RemoveOperand ( 2 ) ; +return ; +} +MI . setDesc ( TII . get ( XCore :: LI ) ) ; +MI . getOperand ( 1 ) . ChangeToImmediate ( Offset ) ; +MI . RemoveOperand ( 2 ) ; +II = II + 1 ; +MachineInstr * New = BuildMI ( MBB , II , DL , TII . get ( XCore :: ADD ) , DstReg ) . addReg ( DstReg , RegState :: Kill ) . addReg ( FrameReg ) ; +New -> getOperand ( 3 ) . setIsDead ( ) ; +return ; +ImmOpIdx = FIOperandNum + 1 ; +MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ; +MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ; +const XCoreTargetMachine & TM = ( const XCoreTargetMachine & ) MF . getTarget ( ) ; +const TargetFrameLowering * TFI = TM . getSubtargetImpl ( ) -> getFrameLowering ( ) ; +Offset = Offset + MFI . getStackSize ( ) - TFI -> getOffsetOfLocalArea ( ) + 1 ; +Offset = Offset + MI . getOperand ( OffsetOperandNo ) . getImm ( ) ; +MI . getOperand ( FIOperandNum ) . ChangeToRegister ( XCore :: A , false ) ; +uint64_t stackSize = MF . getFrameInfo ( ) -> getStackSize ( ) ; +int64_t spOffset = MF . getFrameInfo ( ) -> getObjectOffset ( frameIndex ) ; +Register FrameReg = getFrameRegister ( MF ) ; +bool FrameRegIsKill = true ; +int64_t Offset = spOffset + ( int64_t ) stackSize ; +MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false , false , FrameRegIsKill ) ; +MI . getOperand ( FIOperandNum + 1 ) . ChangeToImmediate ( Offset ) ; +ImmOpIdx = FIOperandNum + 1 ; +MachineOperand & ImmOp = MI . getOperand ( ImmOpIdx ) ; +int Offset = MFI . getObjectOffset ( FI ) + MFI . getStackSize ( ) + ImmOp . getImm ( ) ; +FIOp . ChangeToRegister ( XCore :: SP , false ) ; +ImmOp . ChangeToImmediate ( Offset ) ; +MI . getOperand ( OffsetOperandNo ) . ChangeToImmediate ( Offset ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Allocation/RegisterInfo/getArgRegs.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Allocation/RegisterInfo/getArgRegs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9f445c17971760c9d19a9a39b66ef27b58d0cae0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Allocation/RegisterInfo/getArgRegs.cpp @@ -0,0 +1,3 @@ +const unsigned * XCoreRegisterInfo :: getArgRegs ( const MachineFunction * MF ) { +return XCore_ArgRegs ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Allocation/RegisterInfo/getCalleeSavedRegs.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Allocation/RegisterInfo/getCalleeSavedRegs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..acea69b5fcb341bd8b384e3e2a11f27d92b75f28 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Allocation/RegisterInfo/getCalleeSavedRegs.cpp @@ -0,0 +1,11 @@ +const MCPhysReg * XCoreRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { +static const MCPhysReg CalleeSavedRegs [ ] = { XCore :: S0 , XCore :: SRB , XCore :: SRO , XCore :: R21 , XCore :: R22 , XCore :: R23 , XCore :: R24 , XCore :: R25 , XCore :: R26 , XCore :: R27 , XCore :: R28 , XCore :: P1 , XCore :: P2 , XCore :: P3 , XCore :: P4 , XCore :: P5 , XCore :: P6 , XCore :: P7 , 0 +} +static const MCPhysReg CalleeSavedRegsFP [ ] = { +XCore :: S0 , XCore :: SRB , XCore :: SRO , XCore :: R21 , XCore :: R22 , XCore :: R23 , XCore :: R24 , XCore :: R25 , XCore :: R26 , XCore :: R27 , XCore :: R28 , XCore :: RFP , XCore :: P1 , XCore :: P2 , XCore :: P3 , XCore :: P4 , XCore :: P5 , XCore :: P6 , XCore :: P7 , 0 +} +if ( TFI -> hasFP ( * MF ) ) { +return CalleeSavedRegsFP ; +} +return CalleeSavedRegs ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Allocation/RegisterInfo/getFrameRegister.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Allocation/RegisterInfo/getFrameRegister.cpp new file mode 100644 index 0000000000000000000000000000000000000000..eca2779042f9c273a3f2b2fd836b8b2bc58af2ed --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Allocation/RegisterInfo/getFrameRegister.cpp @@ -0,0 +1,4 @@ +unsigned XCoreRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { +const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; +return TFI -> hasFP ( MF ) ? XCore :: R10 : XCore :: SP ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Allocation/RegisterInfo/getNumArgRegs.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Allocation/RegisterInfo/getNumArgRegs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2810ef11097de7bb546a5fb0f494b93edbdd09ee --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Allocation/RegisterInfo/getNumArgRegs.cpp @@ -0,0 +1,3 @@ +unsigned XCoreRegisterInfo :: getNumArgRegs ( const MachineFunction * MF ) { +return array_lengthof ( XCore_ArgRegs ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Allocation/RegisterInfo/getReservedRegs.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Allocation/RegisterInfo/getReservedRegs.cpp new file mode 100644 index 0000000000000000000000000000000000000000..463f1f6ffdcd722bc3738bf7e98ea53f16a7ba56 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Allocation/RegisterInfo/getReservedRegs.cpp @@ -0,0 +1,12 @@ +BitVector XCoreRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { +BitVector Reserved ( getNumRegs ( ) ) ; +const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; +Reserved . set ( XCore :: CP ) ; +Reserved . set ( XCore :: DP ) ; +Reserved . set ( XCore :: SP ) ; +Reserved . set ( XCore :: LR ) ; +if ( TFI -> hasFP ( MF ) ) { +Reserved . set ( XCore :: R10 ) ; +} +return Reserved ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Allocation/RegisterInfo/needsFrameMoves.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Allocation/RegisterInfo/needsFrameMoves.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4eb16cbde8c952e03e125a180394630277a1573e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Allocation/RegisterInfo/needsFrameMoves.cpp @@ -0,0 +1,3 @@ +bool XCoreRegisterInfo :: needsFrameMoves ( const MachineFunction & MF ) { +return MF . getMMI ( ) . hasDebugInfo ( ) || ! MF . getFunction ( ) -> doesNotThrow ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Allocation/RegisterInfo/processFunctionBeforeFrameFinalized.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Allocation/RegisterInfo/processFunctionBeforeFrameFinalized.cpp new file mode 100644 index 0000000000000000000000000000000000000000..954f2cf29e5e9da842ef31dabff9a23c3b2dc7f5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Allocation/RegisterInfo/processFunctionBeforeFrameFinalized.cpp @@ -0,0 +1,2 @@ +void XCoreRegisterInfo :: processFunctionBeforeFrameFinalized ( MachineFunction & MF ) const { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Allocation/RegisterInfo/requiresRegisterScavenging.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Allocation/RegisterInfo/requiresRegisterScavenging.cpp new file mode 100644 index 0000000000000000000000000000000000000000..335562ff4af74639356e7aa489d79f87f2c98486 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Allocation/RegisterInfo/requiresRegisterScavenging.cpp @@ -0,0 +1,4 @@ +bool XCoreRegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF ) const { +const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; +return TFI -> hasFP ( MF ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Allocation/RegisterInfo/useFPForScavengingIndex.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Allocation/RegisterInfo/useFPForScavengingIndex.cpp new file mode 100644 index 0000000000000000000000000000000000000000..71cfffecad0614ba3682b00a650ed2f000c79c52 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Allocation/RegisterInfo/useFPForScavengingIndex.cpp @@ -0,0 +1,3 @@ +bool XCoreRegisterInfo :: useFPForScavengingIndex ( const MachineFunction & MF ) const { +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/AsmPrinter.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/AsmPrinter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..dd93da5bd92577904a0dd3597fee7e4610c2afda --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/AsmPrinter.cpp @@ -0,0 +1,2 @@ +explicit XCoreAsmPrinter ( TargetMachine & TM , std :: unique_ptr < MCStreamer > Streamer ) : AsmPrinter ( TM , std :: move ( Streamer ) ) , STI ( TM . getMCSubtargetInfo ( ) ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/EmitBasicBlockStart.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/EmitBasicBlockStart.cpp new file mode 100644 index 0000000000000000000000000000000000000000..646537c7ba0ebabd183f3e3882640114082c15b1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/EmitBasicBlockStart.cpp @@ -0,0 +1,6 @@ +void XCoreAsmPrinter :: EmitBasicBlockStart ( const MachineBasicBlock * MBB ) { +AsmPrinter :: EmitBasicBlockStart ( MBB ) ; +if ( isLoopHeaderOfNoUnroll ( MBB ) ) { +OutStreamer -> EmitRawText ( StringRef ( "\t.pragma \"nounroll\";\n" ) ) ; +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/EmitConstantPool.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/EmitConstantPool.cpp new file mode 100644 index 0000000000000000000000000000000000000000..139244fe5d514fca3880519b95f099ce3fdb9536 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/EmitConstantPool.cpp @@ -0,0 +1,39 @@ +void XCoreAsmPrinter :: EmitConstantPool ( ) { +const MachineConstantPool * MCP = MF -> getConstantPool ( ) ; +const std :: vector < MachineConstantPoolEntry > & CP = MCP -> getConstants ( ) ; +XCoreTargetMachine & TTM = static_cast < XCoreTargetMachine & > ( TM ) ; +const std :: vector < MachineConstantPoolEntry > & CP = TTM . MCP . getConstants ( ) ; +if ( CP . empty ( ) ) { +return ; +} +const MCSection * S = TM . getTargetLowering ( ) -> getObjFileLowering ( ) . getDataSection ( ) ; +OutStreamer . SwitchSection ( S ) ; +unsigned Offset = 0 ; +for ( unsigned i = 0 , e = CP . size ( ) ; i != e ; ++ i ) { +const MachineConstantPoolEntry & CPE = CP [ i ] ; +unsigned Align = CPE . getAlignment ( ) ; +unsigned AlignMask = CPE . getAlignment ( ) - 1 ; +unsigned NewOffset = ( Offset + AlignMask ) & ~ AlignMask ; +SmallString < 128 > Str ; +raw_svector_ostream OS ( Str ) ; +if ( NewOffset - Offset ) { +OS << "\tstring\tbyte[" << ( NewOffset - Offset ) << "] 0\n" ; +} +Type * Ty = CPE . getType ( ) ; +Offset = NewOffset + TM . getDataLayout ( ) -> getTypeAllocSize ( Ty ) ; +MCSymbol * Symbol = GetCPISymbol ( i ) ; +OS << "\t" << * Symbol ; +HackStreamer ( OutStreamer ) << OS . str ( ) ; +if ( CPE . isMachineConstantPoolEntry ( ) ) { +EmitMachineConstantPoolValue ( CPE . Val . MachineCPVal ) ; +} +else { +EmitGlobalConstant ( CPE . Val . ConstVal ) ; +} +} +MCTargetStreamer & TS = * OutStreamer -> getTargetStreamer ( ) ; +XCoreTargetStreamer & TTS = static_cast < XCoreTargetStreamer & > ( TS ) ; +while ( cpi < CP . size ( ) ) { +TTS . EmitConstantPoolEntry ( CP [ cpi ++ ] ) ; +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/EmitFunctionEntryLabel.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/EmitFunctionEntryLabel.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ae94aa84a66f6aa550d808610ca711ed5a5ea19f --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/EmitFunctionEntryLabel.cpp @@ -0,0 +1,4 @@ +void XCoreAsmPrinter :: EmitFunctionEntryLabel ( ) { +getTargetStreamer ( ) . emitCCTopFunction ( CurrentFnSym -> getName ( ) ) ; +OutStreamer . EmitLabel ( CurrentFnSym ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/EmitGlobalVariable.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/EmitGlobalVariable.cpp new file mode 100644 index 0000000000000000000000000000000000000000..55f99c669192b0d39dd552740110c1f2ee28c855 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/EmitGlobalVariable.cpp @@ -0,0 +1,59 @@ +void XCoreAsmPrinter :: EmitGlobalVariable ( const GlobalVariable * GV ) { +XCoreoldTargetStreamer * TS = static_cast < XCoreoldTargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) ; +if ( GV -> hasInitializer ( ) ) { +if ( EmitSpecialLLVMGlobal ( GV ) ) { +return ; +} +} +MCSymbol * GVSym = getSymbol ( GV ) ; +ValidateGV ( GV ) ; +if ( ! GV -> hasInitializer ( ) ) { +return ; +} +GVSym -> redefineIfPossible ( ) ; +if ( GVSym -> isDefined ( ) || GVSym -> isVariable ( ) ) { +report_fatal_error ( "symbol '" + Twine ( GVSym -> getName ( ) ) + "' is already defined" ) ; +} +SectionKind GVKind = TargetLoweringObjectFile :: getKindForGlobal ( GV , TM ) ; +MCSymbolXCOFF * GVSym = cast < MCSymbolXCOFF > ( getSymbol ( GV ) ) ; +GVSym -> setStorageClass ( TargetLoweringObjectFileXCOFF :: getStorageClassForGlobal ( GV ) ) ; +SectionKind GVKind = getObjFileLowering ( ) . getKindForGlobal ( GV , TM ) ; +if ( ( ! GVKind . isCommon ( ) && ! GVKind . isBSS ( ) && ! GVKind . isData ( ) && ! GVKind . isReadOnly ( ) ) || GVKind . isMergeable2ByteCString ( ) || GVKind . isMergeable4ByteCString ( ) ) { +report_fatal_error ( "Encountered a global variable kind that is not supported yet." ) ; +} +MCSectionXCOFF * Csect = cast < MCSectionXCOFF > ( getObjFileLowering ( ) . SectionForGlobal ( GV , GVKind , TM ) ) ; +OutStreamer -> SwitchSection ( Csect ) ; +GVSym -> setContainingCsect ( Csect ) ; +uint64_t Size = DL . getTypeAllocSize ( GV -> getType ( ) -> getElementType ( ) ) ; +unsigned Align = DL . getPreferredAlignment ( GV ) ; +MCSection * TheSection = getObjFileLowering ( ) . SectionForGlobal ( GV , GVKind , TM ) ; +OutStreamer -> SwitchSection ( TheSection ) ; +TS -> emitAlign ( Align ) ; +if ( ! GV -> hasLocalLinkage ( ) ) { +TS -> emitGlobal ( GVSym ) ; +} +OutStreamer -> EmitLabel ( GVSym ) ; +if ( GVKind . isBSS ( ) ) { +TS -> emitBlock ( Size ) ; +} +else { +EmitGlobalConstant ( DL , GV -> getInitializer ( ) ) ; +} +OutStreamer -> AddBlankLine ( ) ; +if ( GVKind . isCommon ( ) || GVKind . isBSSLocal ( ) ) { +unsigned Align = GV -> getAlignment ( ) ? GV -> getAlignment ( ) : DL . getPreferredAlignment ( GV ) ; +uint64_t Size = DL . getTypeAllocSize ( GV -> getType ( ) -> getElementType ( ) ) ; +if ( GVKind . isBSSLocal ( ) ) { +OutStreamer -> EmitXCOFFLocalCommonSymbol ( GVSym , Size , Csect -> getQualNameSymbol ( ) , Align ) ; +} +else { +OutStreamer -> EmitCommonSymbol ( Csect -> getQualNameSymbol ( ) , Size , Align ) ; +} +return ; +} +MCSymbol * EmittedInitSym = GVSym ; +EmitLinkage ( GV , EmittedInitSym ) ; +EmitAlignment ( getGVAlignment ( GV , DL ) , GV ) ; +OutStreamer -> EmitLabel ( EmittedInitSym ) ; +EmitGlobalConstant ( GV -> getParent ( ) -> getDataLayout ( ) , GV -> getInitializer ( ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/EmitInstruction.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/EmitInstruction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..004518d3a34b37dc936a06180b807467d95ac1ba --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/EmitInstruction.cpp @@ -0,0 +1,8 @@ +void XCoreAsmPrinter :: EmitInstruction ( const MachineInstr * MI ) { +if ( emitPseudoExpansionLowering ( * OutStreamer , MI ) ) { +return ; +} +MCInst TmpInst ; +LowerXCoreMachineInstrToMCInst ( MI , TmpInst , * this ) ; +EmitToStreamer ( * OutStreamer , TmpInst ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/LLVMInitializeAsmPrinter.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/LLVMInitializeAsmPrinter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..03682e4d98193184051e9da282205d3a5b88bccb --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/LLVMInitializeAsmPrinter.cpp @@ -0,0 +1,3 @@ +extern "C" void LLVMInitializeXCoreAsmPrinter ( ) { +RegisterAsmPrinter < XCoreAsmPrinter > X ( TheXCoreTarget ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/PrintAsmMemoryOperand.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/PrintAsmMemoryOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..84bc0aa01286f2894d901814c9a2e97ba1082a11 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/PrintAsmMemoryOperand.cpp @@ -0,0 +1,10 @@ +bool XCoreAsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { +if ( ExtraCode && ExtraCode [ 0 ] ) { +return true ; +} +printOperand ( MI , OpNo , O ) ; +O << "[" ; +printMemOperand ( MI , OpNo + 1 , O ) ; +O << "]" ; +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/PrintAsmOperand.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/PrintAsmOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e191b5b9bb8540b7cd27df8b9014274632cdc090 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/PrintAsmOperand.cpp @@ -0,0 +1,4 @@ +bool XCoreAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { +printOperand ( MI , OpNo , O ) ; +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/PrintSpecial.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/PrintSpecial.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e798c77bd033d1bd212b5e2f19537b10c5004d25 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/PrintSpecial.cpp @@ -0,0 +1,9 @@ +void XCoreAsmPrinter :: PrintSpecial ( const MCInst * MI , raw_ostream & O , const char * Code ) const { +assert ( strcmp ( Code , "arguments" ) == 0 ) ; +for ( unsigned i = 0 ; i < MI -> getNumOperands ( ) - 1 ; i ++ ) { +if ( i != 0 ) { +O << ", " ; +} +O << "$r" << i << "|0" ; +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/emitEndOfAsmFile.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/emitEndOfAsmFile.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3385972429238a323a320cdb856d0704d230df97 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/emitEndOfAsmFile.cpp @@ -0,0 +1,9 @@ +void XCoreAsmPrinter :: EmitEndOfAsmFile ( Module & M ) { +if ( TM . getTargetTriple ( ) . isOSBinFormatELF ( ) ) { +CTS . finishAttributeSection ( ) ; +} +const TargetLoweringObjectFile & TLOF = getObjFileLowering ( ) ; +OutStreamer . SwitchSection ( TLOF . getTextSection ( ) ) ; +MCSymbol * EndOfTextLabel = OutContext . GetOrCreateSymbol ( StringRef ( END_OF_TEXT_LABEL_NAME ) ) ; +OutStreamer . EmitLabel ( EndOfTextLabel ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/emitStartOfAsmFile.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/emitStartOfAsmFile.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ecf63e6d4eb303d919b132a9dbe9a1d178c67ae6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/emitStartOfAsmFile.cpp @@ -0,0 +1,11 @@ +void XCoreAsmPrinter :: emitStartOfAsmFile ( Module & M ) { +OutStreamer -> emitAssemblerFlag ( MCAF_SyntaxUnified ) ; +if ( TM . getTargetTriple ( ) . isOSBinFormatELF ( ) ) { +emitAttributes ( ) ; +} +if ( ! M . getModuleInlineAsm ( ) . empty ( ) ) { +if ( TM . getTargetTriple ( ) . isThumb ( ) ) { +OutStreamer -> emitAssemblerFlag ( MCAF_Code16 ) ; +} +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/getAnalysisUsage.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/getAnalysisUsage.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a36959e91a44efe2736ac596ef85e6434ec0ebb2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/getAnalysisUsage.cpp @@ -0,0 +1,5 @@ +void getAnalysisUsage ( AnalysisUsage & AU ) const { +AsmPrinter :: getAnalysisUsage ( AU ) ; +AU . setPreservesAll ( ) ; +AU . addRequired < XCoreMetadata > ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/getDebugValueLocation.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/getDebugValueLocation.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e42f1915bc314f1e46b9e3f922bb6641cff1e576 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/getDebugValueLocation.cpp @@ -0,0 +1,5 @@ +MachineLocation XCoreAsmPrinter :: getDebugValueLocation ( const MachineInstr * MI ) const { +assert ( MI -> getNumOperands ( ) == 4 && "Invalid no. of machine operands!" ) ; +assert ( MI -> getOperand ( 0 ) . isReg ( ) && MI -> getOperand ( 1 ) . isImm ( ) && "Unexpected MachineOperand types" ) ; +return MachineLocation ( MI -> getOperand ( 0 ) . getReg ( ) , MI -> getOperand ( 1 ) . getImm ( ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/getPassName.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c490a54e1033bf81ca115ff9b2c92baaab5c27eb --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/getPassName.cpp @@ -0,0 +1,3 @@ +virtual const char * getPassName ( ) const { +return "XCore Assembly Printer" ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/printInlineJT.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/printInlineJT.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bb986ae09b05db3f8831a28c30479259a8e98bd9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/printInlineJT.cpp @@ -0,0 +1,3 @@ +void XCoreInstPrinter :: printInlineJT ( const MCInst * MI , int opNum , raw_ostream & O ) { +report_fatal_error ( "can't handle InlineJT" ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/printInlineJT32.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/printInlineJT32.cpp new file mode 100644 index 0000000000000000000000000000000000000000..49746db2084d79f13571e6e08a87aef93ef16900 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/printInlineJT32.cpp @@ -0,0 +1,3 @@ +void XCoreInstPrinter :: printInlineJT32 ( const MCInst * MI , int opNum , raw_ostream & O ) { +report_fatal_error ( "can't handle InlineJT32" ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/printMemOperand.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/printMemOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9c9961adae27fc891e610d6d5dc25f3c69e06618 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/printMemOperand.cpp @@ -0,0 +1,8 @@ +void XCoreAsmPrinter :: printMemOperand ( const MachineInstr * MI , int opNum , raw_ostream & O ) { +printOperand ( MI , opNum , O ) ; +if ( MI -> getOperand ( opNum + 1 ) . isImm ( ) && MI -> getOperand ( opNum + 1 ) . getImm ( ) == 0 ) { +return ; +} +O << "+" ; +printOperand ( MI , opNum + 1 , O ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/printOperand.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/printOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..48732184388ab36467b63ab680a5035085b996e1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/printOperand.cpp @@ -0,0 +1,36 @@ +void XCoreAsmPrinter :: printOperand ( const MachineInstr * MI , int OpNo , raw_ostream & O ) { +const MachineOperand & MO = MI -> getOperand ( OpNo ) ; +if ( MO . getType ( ) == MachineOperand :: MO_Register ) { +O << getRegisterName ( MO . getReg ( ) ) ; +return ; +} +if ( MO . getType ( ) == MachineOperand :: MO_Immediate ) { +O << MO . getImm ( ) ; +return ; +} +if ( MO . getType ( ) == MachineOperand :: MO_MachineBasicBlock ) { +O << * MO . getMBB ( ) -> getSymbol ( ) ; +return ; +} +if ( MO . getType ( ) == MachineOperand :: MO_GlobalAddress ) { +O << * Mang -> getSymbol ( MO . getGlobal ( ) ) ; +return ; +} +if ( MO . getType ( ) == MachineOperand :: MO_ConstantPoolIndex ) { +O << MAI -> getPrivateGlobalPrefix ( ) << "CPI" << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ; +return ; +} +if ( MO . getType ( ) == MachineOperand :: MO_BlockAddress ) { +O << * GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ; +return ; +} +if ( MO . getType ( ) == MachineOperand :: MO_ExternalSymbol ) { +O << MO . getSymbolName ( ) ; +return ; +} +if ( MO . getType ( ) == MachineOperand :: MO_JumpTableIndex ) { +O << MAI -> getPrivateGlobalPrefix ( ) << "JTI" << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ; +return ; +} +llvm_unreachable ( "not implemented" ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..64a11fc15b9f52e7d1a279d4e95b2835c0be318f --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/runOnMachineFunction.cpp @@ -0,0 +1,9 @@ +bool XCoreAsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { +NewSTI . setFeatureBits ( MF . getSubtarget ( ) . getFeatureBits ( ) ) ; +if ( MF . getFunction ( ) . hasFnAttribute ( "interrupt" ) ) { +EmitInterruptVectorSection ( MF ) ; +} +SetupMachineFunction ( MF ) ; +emitFunctionBody ( ) ; +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/~AsmPrinter.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/~AsmPrinter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a4bf49ae92475fdf2da730d2fc6fbb1ea9cb22ed --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Assembler/AsmPrinter/~AsmPrinter.cpp @@ -0,0 +1,2 @@ +virtual ~ XCoreAsmPrinter ( ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Emission/AsmInfo/MCAsmInfo.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Emission/AsmInfo/MCAsmInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..47b0f74da6093d80f1bbdafd1655b350c859be60 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Emission/AsmInfo/MCAsmInfo.cpp @@ -0,0 +1,13 @@ +XCoreMCAsmInfo :: XCoreMCAsmInfo ( const Target & T , StringRef TT ) { +SupportsDebugInformation = true ; +Data16bitsDirective = "\t.short\t" ; +Data32bitsDirective = "\t.long\t" ; +Data64bitsDirective = 0 ; +ZeroDirective = "\t.space\t" ; +CommentString = "#" ; +PrivateGlobalPrefix = ".L" ; +AscizDirective = ".asciiz" ; +WeakRefDirective = "\t.weak\t" ; +HasLEB128 = true ; +ExceptionsType = DwarfCFI ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Emission/MCTargetDesc/LLVMInitializeTargetMC.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Emission/MCTargetDesc/LLVMInitializeTargetMC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ad4572016a583d0f24654bf95af0ecf9e8b0d648 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Emission/MCTargetDesc/LLVMInitializeTargetMC.cpp @@ -0,0 +1,7 @@ +extern "C" void LLVMInitializeXCoreTargetMC ( ) { +RegisterMCAsmInfoFn X ( TheXCoreTarget , createXCoreMCAsmInfo ) ; +TargetRegistry :: RegisterMCCodeGenInfo ( TheXCoreTarget , createXCoreMCCodeGenInfo ) ; +TargetRegistry :: RegisterMCInstrInfo ( TheXCoreTarget , createXCoreMCInstrInfo ) ; +TargetRegistry :: RegisterMCRegInfo ( TheXCoreTarget , createXCoreMCRegisterInfo ) ; +TargetRegistry :: RegisterMCSubtargetInfo ( TheXCoreTarget , createXCoreMCSubtargetInfo ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Emission/MCTargetDesc/createMCAsmInfo.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Emission/MCTargetDesc/createMCAsmInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..388448d5287007b849d2c7a23ea67c715351fbb0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Emission/MCTargetDesc/createMCAsmInfo.cpp @@ -0,0 +1,7 @@ +static MCAsmInfo * createXCoreMCAsmInfo ( const Target & T , StringRef TT ) { +MCAsmInfo * MAI = new XCoreMCAsmInfo ( T , TT ) ; +MachineLocation Dst ( MachineLocation :: VirtualFP ) ; +MachineLocation Src ( XCore :: SP , 0 ) ; +MAI -> addInitialFrameState ( 0 , Dst , Src ) ; +return MAI ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Emission/MCTargetDesc/createMCCodeGenInfo.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Emission/MCTargetDesc/createMCCodeGenInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0985d539f262eb70ca3380939802b7702529fefa --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Emission/MCTargetDesc/createMCCodeGenInfo.cpp @@ -0,0 +1,5 @@ +static MCCodeGenInfo * createXCoreMCCodeGenInfo ( StringRef TT , Reloc :: Model RM , CodeModel :: Model CM ) { +MCCodeGenInfo * X = new MCCodeGenInfo ( ) ; +X -> InitMCCodeGenInfo ( RM , CM ) ; +return X ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Emission/MCTargetDesc/createMCInstrInfo.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Emission/MCTargetDesc/createMCInstrInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..30f512b8abfda27774b209bd765850933fe57777 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Emission/MCTargetDesc/createMCInstrInfo.cpp @@ -0,0 +1,6 @@ +static MCInstrInfo * createXCoreMCInstrInfo ( ) { +MCInstrInfo * X ; +X = new MCInstrInfo ( ) ; +InitXCoreMCInstrInfo ( X ) ; +return X ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Emission/MCTargetDesc/createMCRegisterInfo.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Emission/MCTargetDesc/createMCRegisterInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d4605684aeb841213588d65e8c49b7ad2705ab35 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Emission/MCTargetDesc/createMCRegisterInfo.cpp @@ -0,0 +1,6 @@ +static MCRegisterInfo * createXCoreMCRegisterInfo ( StringRef TT ) { +MCRegisterInfo * X ; +X = new MCRegisterInfo ( ) ; +InitXCoreMCRegisterInfo ( X , XCore :: LR ) ; +return X ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Emission/MCTargetDesc/createMCSubtargetInfo.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Emission/MCTargetDesc/createMCSubtargetInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d5c7b7b1c5b2f674b0401f93d5b65270a156864a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Emission/MCTargetDesc/createMCSubtargetInfo.cpp @@ -0,0 +1,5 @@ +static MCSubtargetInfo * createXCoreMCSubtargetInfo ( StringRef TT , StringRef CPU , StringRef FS ) { +MCSubtargetInfo * X = new MCSubtargetInfo ( ) ; +InitXCoreMCSubtargetInfo ( X , TT , CPU , FS ) ; +return X ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/FrameToArgsOffsetElim/FTAOElim.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/FrameToArgsOffsetElim/FTAOElim.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fd1aec54bc0a12717d7bc9255f0e37890b35c0d5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/FrameToArgsOffsetElim/FTAOElim.cpp @@ -0,0 +1,2 @@ +XCoreFTAOElim ( ) : MachineFunctionPass ( ID ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/FrameToArgsOffsetElim/XCoreFTAOElim.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/FrameToArgsOffsetElim/XCoreFTAOElim.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f7a1a1415db832540fb6c850d4cf6ede91113354 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/FrameToArgsOffsetElim/XCoreFTAOElim.cpp @@ -0,0 +1,2 @@ +XCoreFTAOElim() : MachineFunctionPass(ID) { +} diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/FrameToArgsOffsetElim/createPass.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/FrameToArgsOffsetElim/createPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e674677a492ef74b6ecc159279c6380d10670764 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/FrameToArgsOffsetElim/createPass.cpp @@ -0,0 +1,3 @@ +FunctionPass * llvm :: createXCoreFrameToArgsOffsetEliminationPass ( ) { +return new XCoreFTAOElim ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/FrameToArgsOffsetElim/getPassName.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/FrameToArgsOffsetElim/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..674a4a0c4f862aed107d0cc5af311e52cde84d2d --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/FrameToArgsOffsetElim/getPassName.cpp @@ -0,0 +1,3 @@ +virtual const char * getPassName ( ) const { +return "XCore FRAME_TO_ARGS_OFFSET Elimination" ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/FrameToArgsOffsetElim/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/FrameToArgsOffsetElim/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b844f69d52c1bd25558a02de518e585c45b3a909 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/FrameToArgsOffsetElim/runOnMachineFunction.cpp @@ -0,0 +1,11 @@ +bool XCoreFTAOElim :: runOnMachineFunction ( MachineFunction & MF ) { +if ( skipFunction ( MF . getFunction ( ) ) ) { +} +bool Changed = false ; +TII = ST . getInstrInfo ( ) ; +TRI = ST . getRegisterInfo ( ) ; +for ( MachineBasicBlock & MBB : MF ) { +Changed = Changed | runOnMachineBasicBlock ( MBB ) ; +} +return Changed ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/LoopMetadataLowering/LoopMetadataLowering.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/LoopMetadataLowering/LoopMetadataLowering.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a7421d0e8d323058a7484b27aac82ca54ff0ae98 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/LoopMetadataLowering/LoopMetadataLowering.cpp @@ -0,0 +1,3 @@ +XCoreLoopMetadataLowering ( ) : FunctionPass ( ID ) { +initializeXCoreLoopMetadataLowering ( * PassRegistry :: getPassRegistry ( ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/LoopMetadataLowering/createPass.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/LoopMetadataLowering/createPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d4818b614f669dce7b448540635b53b27e91f287 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/LoopMetadataLowering/createPass.cpp @@ -0,0 +1,3 @@ +FunctionPass * llvm :: createXCoreLoopMetadataLowering ( ) { +return new XCoreLoopMetadataLowering ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/LoopMetadataLowering/getAnalysisUsage.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/LoopMetadataLowering/getAnalysisUsage.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b17340c848fe3a53f69c28a88af8297dfa812c69 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/LoopMetadataLowering/getAnalysisUsage.cpp @@ -0,0 +1,3 @@ +virtual void getAnalysisUsage ( AnalysisUsage & AU ) const override { +AU . setPreservesAll ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/LoopMetadataLowering/runOnFunction.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/LoopMetadataLowering/runOnFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6809fc1d47f6a5f1b6fcb81fca52f1f0286c64ba --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/LoopMetadataLowering/runOnFunction.cpp @@ -0,0 +1,54 @@ +bool XCoreLoopMetadataLowering :: runOnFunction ( Function & F ) { +LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; +SE = & getAnalysis < ScalarEvolution > ( ) ; +DT = & getAnalysis < DominatorTreeWrapperPass > ( ) . getDomTree ( ) ; +DL = & F . getParent ( ) -> getDataLayout ( ) ; +auto * TLIP = getAnalysisIfAvailable < TargetLibraryInfoWrapperPass > ( ) ; +LibInfo = TLIP ? & TLIP -> getTLI ( ) : nullptr ; +bool MadeChange = false ; +for ( LoopInfo :: iterator I = LI -> begin ( ) , E = LI -> end ( ) ; I != E ; ++ I ) { +Loop * L = * I ; +if ( ! L -> getParentLoop ( ) ) { +MadeChange |= convertToCTRLoop ( L ) ; +} +} +return MadeChange ; +if ( Func . isDeclaration ( ) ) { +} +F = & Func ; +IRB = new IRBuilder < > ( Func . getContext ( ) ) ; +AggrConsts . clear ( ) ; +AggrStores . clear ( ) ; +IRB -> SetInsertPoint ( & Func . getEntryBlock ( ) . front ( ) ) ; +for ( auto & GV : Func . getParent ( ) -> globals ( ) ) { +processGlobalValue ( GV ) ; +} +SmallVector < Instruction * > Worklist ; +for ( auto & I : instructions ( Func ) ) { +Worklist . push_back ( & I ) ; +} +for ( auto & I : Worklist ) { +insertAssignTypeIntrs ( I ) ; +} +for ( auto * I : Worklist ) { +TrackConstants = true ; +if ( ! I -> getType ( ) -> isVoidTy ( ) || isa < StoreInst > ( I ) ) { +IRB -> SetInsertPoint ( I -> getNextNode ( ) ) ; +} +I = visit ( * I ) ; +processInstrAfterVisit ( I ) ; +} +bool functionModified = false ; +Function :: iterator I = function . begin ( ) ; +TerminatorInst * firstTerminatorInst = ( I ++ ) -> getTerminator ( ) ; +for ( Function :: iterator E = function . end ( ) ; I != E ; ++ I ) { +for ( BasicBlock :: iterator BI = I -> begin ( ) , BE = I -> end ( ) ; BI != BE ; ) { +AllocaInst * allocaInst = dyn_cast < AllocaInst > ( BI ++ ) ; +if ( allocaInst && isa < ConstantInt > ( allocaInst -> getArraySize ( ) ) ) { +allocaInst -> moveBefore ( firstTerminatorInst ) ; +functionModified = true ; +} +} +} +return functionModified ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/LoopMetadataLowering/~LoopMetadataLowering.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/LoopMetadataLowering/~LoopMetadataLowering.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f46339f5ca9ecc44f0d7eb2d23ef8b7a88dbc7b4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/LoopMetadataLowering/~LoopMetadataLowering.cpp @@ -0,0 +1,2 @@ +~ XCoreLoopMetadataLowering ( ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/SimpleBranchOpt/SimpleBranchOpt.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/SimpleBranchOpt/SimpleBranchOpt.cpp new file mode 100644 index 0000000000000000000000000000000000000000..efe6f5308673e7ed46d8a73f05c50339143ac667 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/SimpleBranchOpt/SimpleBranchOpt.cpp @@ -0,0 +1,2 @@ +XCoreSimpleBranchOpt ( ) : MachineFunctionPass ( ID ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/SimpleBranchOpt/createPass.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/SimpleBranchOpt/createPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..83ca9d40821520b3692953036fb1e7f765668297 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/SimpleBranchOpt/createPass.cpp @@ -0,0 +1,3 @@ +FunctionPass * llvm :: createXCoreSimpleBranchOptPass ( ) { +return new XCoreSimpleBranchOpt ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/SimpleBranchOpt/getPassName.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/SimpleBranchOpt/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fcb4a6ee09d8ff4258f1addd18dc8db54dbfed69 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/SimpleBranchOpt/getPassName.cpp @@ -0,0 +1,3 @@ +virtual const char * getPassName ( ) const { +return "XCore branch to trap optimization" ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/SimpleBranchOpt/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/SimpleBranchOpt/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8c551026b23954b356f067b683b6bdf35ed69989 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/SimpleBranchOpt/runOnMachineFunction.cpp @@ -0,0 +1,11 @@ +bool XCoreSimpleBranchOpt :: runOnMachineFunction ( MachineFunction & MF ) { +if ( skipFunction ( MF . getFunction ( ) ) ) { +} +bool Changed = false ; +TII = ST . getInstrInfo ( ) ; +TRI = ST . getRegisterInfo ( ) ; +for ( MachineBasicBlock & MBB : MF ) { +Changed = Changed | runOnMachineBasicBlock ( MBB ) ; +} +return Changed ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/StackAnalysisPrepare/StackAnalysisPrepare.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/StackAnalysisPrepare/StackAnalysisPrepare.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7ab4f4a003cb411608071e8e6b27c088992d296a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/StackAnalysisPrepare/StackAnalysisPrepare.cpp @@ -0,0 +1,3 @@ +XCoreStackAnalysisPrepare ( ) : FunctionPass ( ID ) { +initializeXCoreStackAnalysisPrepare ( * PassRegistry :: getPassRegistry ( ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/StackAnalysisPrepare/createPass.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/StackAnalysisPrepare/createPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..aef589bbad9818c07b357e30fdd1d1d886cf9b44 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/StackAnalysisPrepare/createPass.cpp @@ -0,0 +1,3 @@ +FunctionPass * llvm :: createXCoreStackAnalysisPrepare ( ) { +return new XCoreStackAnalysisPrepare ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/StackAnalysisPrepare/getAnalysisUsage.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/StackAnalysisPrepare/getAnalysisUsage.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b17340c848fe3a53f69c28a88af8297dfa812c69 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/StackAnalysisPrepare/getAnalysisUsage.cpp @@ -0,0 +1,3 @@ +virtual void getAnalysisUsage ( AnalysisUsage & AU ) const override { +AU . setPreservesAll ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/StackAnalysisPrepare/runOnFunction.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/StackAnalysisPrepare/runOnFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3e4adbf95e2c73ac447e1a3e9bac84b8573bd203 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/StackAnalysisPrepare/runOnFunction.cpp @@ -0,0 +1,55 @@ +bool XCoreStackAnalysisPrepare :: runOnFunction ( Function & F ) { +LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; +SE = & getAnalysis < ScalarEvolution > ( ) ; +DT = & getAnalysis < DominatorTreeWrapperPass > ( ) . getDomTree ( ) ; +DL = & F . getParent ( ) -> getDataLayout ( ) ; +auto * TLIP = getAnalysisIfAvailable < TargetLibraryInfoWrapperPass > ( ) ; +LibInfo = TLIP ? & TLIP -> getTLI ( ) : nullptr ; +bool MadeChange = false ; +for ( LoopInfo :: iterator I = LI -> begin ( ) , E = LI -> end ( ) ; I != E ; ++ I ) { +Loop * L = * I ; +if ( ! L -> getParentLoop ( ) ) { +MadeChange |= convertToCTRLoop ( L ) ; +} +} +return MadeChange ; +if ( Func . isDeclaration ( ) ) { +} +F = & Func ; +IRB = new IRBuilder < > ( Func . getContext ( ) ) ; +AggrConsts . clear ( ) ; +AggrStores . clear ( ) ; +IRB -> SetInsertPoint ( & Func . getEntryBlock ( ) . front ( ) ) ; +for ( auto & GV : Func . getParent ( ) -> globals ( ) ) { +processGlobalValue ( GV ) ; +} +preprocessCompositeConstants ( ) ; +SmallVector < Instruction * > Worklist ; +for ( auto & I : instructions ( Func ) ) { +Worklist . push_back ( & I ) ; +} +for ( auto & I : Worklist ) { +insertAssignTypeIntrs ( I ) ; +} +for ( auto * I : Worklist ) { +TrackConstants = true ; +if ( ! I -> getType ( ) -> isVoidTy ( ) || isa < StoreInst > ( I ) ) { +IRB -> SetInsertPoint ( I -> getNextNode ( ) ) ; +} +I = visit ( * I ) ; +processInstrAfterVisit ( I ) ; +} +bool functionModified = false ; +Function :: iterator I = function . begin ( ) ; +TerminatorInst * firstTerminatorInst = ( I ++ ) -> getTerminator ( ) ; +for ( Function :: iterator E = function . end ( ) ; I != E ; ++ I ) { +for ( BasicBlock :: iterator BI = I -> begin ( ) , BE = I -> end ( ) ; BI != BE ; ) { +AllocaInst * allocaInst = dyn_cast < AllocaInst > ( BI ++ ) ; +if ( allocaInst && isa < ConstantInt > ( allocaInst -> getArraySize ( ) ) ) { +allocaInst -> moveBefore ( firstTerminatorInst ) ; +functionModified = true ; +} +} +} +return functionModified ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/StackAnalysisPrepare/~StackAnalysisPrepare.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/StackAnalysisPrepare/~StackAnalysisPrepare.cpp new file mode 100644 index 0000000000000000000000000000000000000000..760d3e9778423dcf52e0307e76681f7eccc494e4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/StackAnalysisPrepare/~StackAnalysisPrepare.cpp @@ -0,0 +1,2 @@ +~ XCoreStackAnalysisPrepare ( ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/StackUsage/StackUsage.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/StackUsage/StackUsage.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c8653ae1ae6795005bbb51141811abd840e6e7ea --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/StackUsage/StackUsage.cpp @@ -0,0 +1,2 @@ +XCoreStackUsage ( ) : MachineFunctionPass ( ID ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/StackUsage/createPass.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/StackUsage/createPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..994c88fdbac2d9819220ab927ec224ae653a06b2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/StackUsage/createPass.cpp @@ -0,0 +1,3 @@ +FunctionPass * llvm :: createXCoreStackUsage ( ) { +return new XCoreStackUsage ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/StackUsage/getAnalysisUsage.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/StackUsage/getAnalysisUsage.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a7fc06dcdd4aa3d2e82b8eab2047bac7ec6bdcac --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/StackUsage/getAnalysisUsage.cpp @@ -0,0 +1,4 @@ +virtual void getAnalysisUsage ( AnalysisUsage & AU ) const override { +AU . setPreservesAll ( ) ; +MachineFunctionPass :: getAnalysisUsage ( AU ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/StackUsage/getPassName.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/StackUsage/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..554e6cf89e2baad3ba8ec8222a3bb84d1c5414fc --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/StackUsage/getPassName.cpp @@ -0,0 +1,3 @@ +const char * getPassName ( ) const { +return "Calculates XCore stack usage" ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/StackUsage/runOnMachineFunction.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/StackUsage/runOnMachineFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..17f0210a26f39d43e78d24a0056e8c135e48ca89 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Optimization/StackUsage/runOnMachineFunction.cpp @@ -0,0 +1,11 @@ +bool XCoreStackUsage :: runOnMachineFunction ( MachineFunction & MF ) { +if ( skipFunction ( MF . getFunction ( ) ) ) { +} +bool Changed = false ; +TII = ST . getInstrInfo ( ) ; +TRI = ST . getRegisterInfo ( ) ; +for ( MachineBasicBlock & MBB : MF ) { +Changed = Changed | runOnMachineBasicBlock ( MBB ) ; +} +return Changed ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/GetCondBranchFromCond.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/GetCondBranchFromCond.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bf29225b942b976fb4867a778ab2c40dba66b9bd --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/GetCondBranchFromCond.cpp @@ -0,0 +1,9 @@ +static inline unsigned GetCondBranchFromCond ( XCore :: CondCode BrOpc ) { +if ( BrOpc == XCore :: COND_TRUE ) { +return XCore :: BRFT_lru6 ; +} +if ( BrOpc == XCore :: COND_FALSE ) { +return XCore :: BRFF_lru6 ; +} +llvm_unreachable ( "Illegal condition code!" ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/GetCondFromBranchOpc.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/GetCondFromBranchOpc.cpp new file mode 100644 index 0000000000000000000000000000000000000000..164a9e54b9be1b9e098d4723c25438ad3cd1f0a0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/GetCondFromBranchOpc.cpp @@ -0,0 +1,27 @@ +static XCore :: CondCode GetCondFromBranchOpc ( unsigned CC ) { +if ( CC == XCore :: BRFT_ru6 ) { +return XCore :: COND_TRUE ; +} +if ( CC == XCore :: BRFT_lru6 ) { +return XCore :: COND_TRUE ; +} +if ( CC == XCore :: BRBT_ru6 ) { +return XCore :: COND_TRUE ; +} +if ( CC == XCore :: BRBT_lru6 ) { +return XCore :: COND_TRUE ; +} +if ( CC == XCore :: BRFF_ru6 ) { +return XCore :: COND_FALSE ; +} +if ( CC == XCore :: BRFF_lru6 ) { +return XCore :: COND_FALSE ; +} +if ( CC == XCore :: BRBF_ru6 ) { +return XCore :: COND_FALSE ; +} +if ( CC == XCore :: BRBF_lru6 ) { +return XCore :: COND_FALSE ; +} +return XCore :: COND_INVALID ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/GetInstSizeInBytes.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/GetInstSizeInBytes.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7395edfcc9e1b46a1a432ba5f204fe0d4a6b849e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/GetInstSizeInBytes.cpp @@ -0,0 +1,19 @@ +unsigned XCoreInstrInfo :: GetInstSizeInBytes ( const MachineInstr * MI ) const { +if ( MI -> getOpcode ( ) == XCore :: INLINEASM ) { +} +if ( Desc . getOpcode ( ) == XCore :: INLINEASM ) { +return 4 ; +} +if ( Desc . getOpcode ( ) == XCore :: BR_JT ) { +} +if ( Desc . getOpcode ( ) == XCore :: BR_JT32 ) { +return 0 ; +} +const MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ; +const XCoreTargetMachine & TM = static_cast < const XCoreTargetMachine & > ( MF -> getTarget ( ) ) ; +const TargetInstrInfo & TII = * TM . getSubtargetImpl ( ) -> getInstrInfo ( ) ; +return TII . getInlineAsmLength ( MI -> getOperand ( 0 ) . getSymbolName ( ) , * TM . getMCAsmInfo ( ) ) ; +const char * AsmStr = MI -> getOperand ( 0 ) . getSymbolName ( ) ; +return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ; +llvm_unreachable ( "GetInstSizeInBytes()- Unable to determin insn size" ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/GetOppositeBranchCondition.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/GetOppositeBranchCondition.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6279a2b94e29fcd32180d5713b862d3864ee6076 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/GetOppositeBranchCondition.cpp @@ -0,0 +1,9 @@ +static inline XCore :: CondCode GetOppositeBranchCondition ( XCore :: CondCode CC ) { +if ( CC == XCore :: COND_TRUE ) { +return XCore :: COND_FALSE ; +} +if ( CC == XCore :: COND_FALSE ) { +return XCore :: COND_TRUE ; +} +llvm_unreachable ( "Illegal condition code!" ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/InstrInfo.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/InstrInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b262e5e2a3ac07071cc2b5b2928e8d79aed25a58 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/InstrInfo.cpp @@ -0,0 +1,2 @@ +XCoreInstrInfo :: XCoreInstrInfo ( ) : XCoreGenInstrInfo ( XCore :: ADJCALLSTACKDOWN , XCore :: ADJCALLSTACKUP ) , RI ( * this ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/IsBRF.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/IsBRF.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2f9c9d24a4f4eb4c122e24f977599703c33a1ae7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/IsBRF.cpp @@ -0,0 +1,15 @@ +static inline bool IsBRF ( unsigned BrOpc ) { +if ( BrOpc == XCore :: BRFF_ru6 ) { +return true ; +} +if ( BrOpc == XCore :: BRFF_lru6 ) { +return true ; +} +if ( BrOpc == XCore :: BRBF_ru6 ) { +return true ; +} +if ( BrOpc == XCore :: BRBF_lru6 ) { +return true ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/IsBRT.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/IsBRT.cpp new file mode 100644 index 0000000000000000000000000000000000000000..077f623f95c359ce8cfd63c09083633a9996666d --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/IsBRT.cpp @@ -0,0 +1,15 @@ +static inline bool IsBRT ( unsigned BrOpc ) { +if ( BrOpc == XCore :: BRFT_ru6 ) { +return true ; +} +if ( BrOpc == XCore :: BRFT_lru6 ) { +return true ; +} +if ( BrOpc == XCore :: BRBT_ru6 ) { +return true ; +} +if ( BrOpc == XCore :: BRBT_lru6 ) { +return true ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/IsBRU.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/IsBRU.cpp new file mode 100644 index 0000000000000000000000000000000000000000..014b3c19d6a4c3fa55c1ac412150e3cf11d36e7c --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/IsBRU.cpp @@ -0,0 +1,15 @@ +static inline bool IsBRU ( unsigned BrOpc ) { +if ( BrOpc == XCore :: BRFU_u6 ) { +return true ; +} +if ( BrOpc == XCore :: BRFU_lu6 ) { +return true ; +} +if ( BrOpc == XCore :: BRBU_u6 ) { +return true ; +} +if ( BrOpc == XCore :: BRBU_lu6 ) { +return true ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/IsBR_JT.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/IsBR_JT.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e83480f67fa0232eeb79b7dabc31fdf31d0e9788 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/IsBR_JT.cpp @@ -0,0 +1,9 @@ +static inline bool IsBR_JT ( unsigned BrOpc ) { +if ( BrOpc == XCore :: BR_JT ) { +return true ; +} +if ( BrOpc == XCore :: BR_JT32 ) { +return true ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/IsCondBranch.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/IsCondBranch.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b19ce91e2acd70a67d5f778c9465a42479044990 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/IsCondBranch.cpp @@ -0,0 +1,27 @@ +static inline bool IsCondBranch ( unsigned BrOpc ) { +if ( BrOpc == XCore :: BRFF_ru6 ) { +return true ; +} +if ( BrOpc == XCore :: BRFF_lru6 ) { +return true ; +} +if ( BrOpc == XCore :: BRBF_ru6 ) { +return true ; +} +if ( BrOpc == XCore :: BRBF_lru6 ) { +return true ; +} +if ( BrOpc == XCore :: BRFT_ru6 ) { +return true ; +} +if ( BrOpc == XCore :: BRFT_lru6 ) { +return true ; +} +if ( BrOpc == XCore :: BRBT_ru6 ) { +return true ; +} +if ( BrOpc == XCore :: BRBT_lru6 ) { +return true ; +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/analyzeBranch.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/analyzeBranch.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c3c5f86e6abc6a303ebb2cbec8a22f275806c439 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/analyzeBranch.cpp @@ -0,0 +1,60 @@ +bool XCoreInstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { +TBB = nullptr ; +FBB = nullptr ; +Cond . clear ( ) ; +MachineBasicBlock :: iterator I = MBB . getLastNonDebugInstr ( ) ; +if ( I == MBB . end ( ) ) { +return false ; +} +if ( ! isUnpredicatedTerminator ( * I ) ) { +return false ; +} +MachineBasicBlock :: iterator FirstUncondOrIndirectBr = MBB . end ( ) ; +int NumTerminators = 0 ; +for ( auto J = I . getReverse ( ) ; J != MBB . rend ( ) && isUnpredicatedTerminator ( * J ) ; J ++ ) { +NumTerminators = NumTerminators + 1 ; +if ( J -> getDesc ( ) . isUnconditionalBranch ( ) ) { +FirstUncondOrIndirectBr = J . getReverse ( ) ; +} +if ( J -> getDesc ( ) . isIndirectBranch ( ) ) { +FirstUncondOrIndirectBr = J . getReverse ( ) ; +} +} +if ( AllowModify ) { +if ( FirstUncondOrIndirectBr != MBB . end ( ) ) { +for ( ; std :: next ( FirstUncondOrIndirectBr ) != MBB . end ( ) ; ) { +std :: next ( FirstUncondOrIndirectBr ) -> eraseFromParent ( ) ; +NumTerminators = NumTerminators - 1 ; +} +I = FirstUncondOrIndirectBr ; +} +} +if ( I -> getDesc ( ) . isIndirectBranch ( ) ) { +return true ; +} +if ( NumTerminators > 2 ) { +return true ; +} +if ( NumTerminators == 1 ) { +if ( I -> getDesc ( ) . isUnconditionalBranch ( ) ) { +TBB = getBranchDestBlock ( * I ) ; +return false ; +} +} +if ( NumTerminators == 1 ) { +if ( I -> getDesc ( ) . isConditionalBranch ( ) ) { +parseCondBranch ( * I , TBB , Cond ) ; +return false ; +} +} +if ( NumTerminators == 2 ) { +if ( I -> getDesc ( ) . isUnconditionalBranch ( ) ) { +if ( std :: prev ( I ) -> getDesc ( ) . isConditionalBranch ( ) ) { +parseCondBranch ( * std :: prev ( I ) , TBB , Cond ) ; +FBB = getBranchDestBlock ( * I ) ; +return false ; +} +} +} +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/copyPhysReg.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/copyPhysReg.cpp new file mode 100644 index 0000000000000000000000000000000000000000..70a993e7825d4f2005107da609d2e3875a356796 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/copyPhysReg.cpp @@ -0,0 +1,10 @@ +void XCoreInstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , MCRegister DstReg , MCRegister SrcReg , bool KillSrc ) const { +return ; +return ; +return ; +return ; +return ; +return ; +return ; +llvm_unreachable ( "Impossible reg-to-reg copy" ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/emitFrameIndexDebugValue.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/emitFrameIndexDebugValue.cpp new file mode 100644 index 0000000000000000000000000000000000000000..dc2b3766c4a5f82c66bcb0d347e633c09201a4fe --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/emitFrameIndexDebugValue.cpp @@ -0,0 +1,4 @@ +MachineInstr * XCoreInstrInfo :: emitFrameIndexDebugValue ( MachineFunction & MF , int FrameIx , uint64_t Offset , const MDNode * MDPtr , DebugLoc DL ) const { +MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( XCore :: DBG_VALUE ) ) . addFrameIndex ( FrameIx ) . addImm ( 0 ) . addImm ( Offset ) . addMetadata ( MDPtr ) ; +return & * MIB ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/enum CondCode.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/enum CondCode.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5dd97f1459e046e69c38462cd9a2b7b4ae8857c5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/enum CondCode.cpp @@ -0,0 +1,5 @@ +enum CondCode { +COND_TRUE , +COND_FALSE , +COND_INVALID +} ; \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/getRegisterInfo.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/getRegisterInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..273524c4ea3d3a5e3ac4fcff3c6c0becdbbf6473 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/getRegisterInfo.cpp @@ -0,0 +1,3 @@ +virtual const TargetRegisterInfo & getRegisterInfo ( ) const { +return RI ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/insertBranch.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/insertBranch.cpp new file mode 100644 index 0000000000000000000000000000000000000000..89ea654f9829f392c8edd731834b85f1c7d3597f --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/insertBranch.cpp @@ -0,0 +1,24 @@ +unsigned XCoreInstrInfo :: insertBranch ( MachineBasicBlock & MBB , MachineBasicBlock * TBB , MachineBasicBlock * FBB , ArrayRef < MachineOperand > Cond , const DebugLoc & DL , int * BytesAdded ) const { +if ( BytesAdded ) { +* BytesAdded = 0 ; +} +assert ( TBB && "insertBranch must not be told to insert a fallthrough" ) ; +if ( Cond . empty ( ) ) { +if ( BytesAdded ) { +* BytesAdded = * BytesAdded + getInstSizeInBytes ( MI ) ; +} +return 1 ; +} +unsigned Opc = Cond [ 0 ] . getImm ( ) ; +MachineInstr & CondMI = * BuildMI ( & MBB , DL , get ( Opc ) ) . add ( Cond [ 1 ] ) . add ( Cond [ 2 ] ) . addMBB ( TBB ) ; +if ( BytesAdded ) { +* BytesAdded = * BytesAdded + getInstSizeInBytes ( CondMI ) ; +} +if ( ! FBB ) { +return 1 ; +} +if ( BytesAdded ) { +* BytesAdded = * BytesAdded + getInstSizeInBytes ( MI ) ; +} +return 2 ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/isLoadFromStackSlot.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/isLoadFromStackSlot.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9ce625cf9e19368b8eb4abe097e5052016342b0c --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/isLoadFromStackSlot.cpp @@ -0,0 +1,10 @@ +unsigned XCoreInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { +int Opcode = MI -> getOpcode ( ) ; +if ( Opcode == XCore :: LDWFI ) { +if ( ( MI -> getOperand ( 1 ) . isFI ( ) ) && ( MI -> getOperand ( 2 ) . isImm ( ) ) && ( isZeroImm ( MI -> getOperand ( 2 ) ) ) ) { +FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; +return MI -> getOperand ( 0 ) . getReg ( ) ; +} +} +return 0 ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/isStoreToStackSlot.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/isStoreToStackSlot.cpp new file mode 100644 index 0000000000000000000000000000000000000000..88ce456dd52273ea10fbdb82850e5b850a09da01 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/isStoreToStackSlot.cpp @@ -0,0 +1,10 @@ +unsigned XCoreInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { +int Opcode = MI -> getOpcode ( ) ; +if ( Opcode == XCore :: STWFI ) { +if ( ( MI -> getOperand ( 1 ) . isFI ( ) ) && ( MI -> getOperand ( 2 ) . isImm ( ) ) && ( isZeroImm ( MI -> getOperand ( 2 ) ) ) ) { +FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; +return MI -> getOperand ( 0 ) . getReg ( ) ; +} +} +return 0 ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/isZeroImm.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/isZeroImm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..557cd477a3d53d5b8819e3be72a2517f713d37b5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/isZeroImm.cpp @@ -0,0 +1,8 @@ +static bool isZeroImm ( const MachineOperand & Op ) { +if ( Op . isImm ( ) ) { +if ( Op . getImm ( ) == 0 ) { +return true ; +} +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/loadRegFromStackSlot.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/loadRegFromStackSlot.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d8ff9f844d9918f72707c955d7d41f6a5dcf2588 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/loadRegFromStackSlot.cpp @@ -0,0 +1,7 @@ +void XCoreInstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned DestReg , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { +DebugLoc DL ; +if ( MI != MBB . end ( ) ) { +DL = MI -> getDebugLoc ( ) ; +} +BuildMI ( MBB , MI , DL , get ( XCore :: LDWFI ) , DestReg ) . addFrameIndex ( FrameIndex ) . addImm ( 0 ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/removeBranch.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/removeBranch.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fff550bd86d9aaf2e448b6d2fc4f24734b09ad15 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/removeBranch.cpp @@ -0,0 +1,27 @@ +unsigned XCoreInstrInfo :: RemoveBranch ( MachineBasicBlock & MBB ) const { +MachineBasicBlock :: iterator I = MBB . end ( ) ; +if ( I == MBB . begin ( ) ) { +return 0 ; +} +-- I ; +while ( I -> isDebugValue ( ) ) { +if ( I == MBB . begin ( ) ) { +return 0 ; +} +-- I ; +} +if ( ! IsBRU ( I -> getOpcode ( ) ) && ! IsCondBranch ( I -> getOpcode ( ) ) ) { +return 0 ; +} +I -> eraseFromParent ( ) ; +I = MBB . end ( ) ; +if ( I == MBB . begin ( ) ) { +return 1 ; +} +-- I ; +if ( ! IsCondBranch ( I -> getOpcode ( ) ) ) { +return 1 ; +} +I -> eraseFromParent ( ) ; +return 2 ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/reverseBranchCondition.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/reverseBranchCondition.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ef875ff424ec1b641d4b544513a3c44665ca45c9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/reverseBranchCondition.cpp @@ -0,0 +1,5 @@ +bool XCoreInstrInfo :: ReverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const { +assert ( ( Cond . size ( ) == 2 ) && "Invalid XCore branch condition!" ) ; +Cond [ 0 ] . setImm ( GetOppositeBranchCondition ( ( XCore :: CondCode ) Cond [ 0 ] . getImm ( ) ) ) ; +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/storeRegToStackSlot.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/storeRegToStackSlot.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ab9903b7a8d239021fa9563f912d45ccfae18af6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/InstrInfo/storeRegToStackSlot.cpp @@ -0,0 +1,9 @@ +void XCoreInstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { +DebugLoc DL ; +if ( I != MBB . end ( ) ) { +DL = I -> getDebugLoc ( ) ; +} +MachineFrameInfo * MFI = MBB . getParent ( ) -> getFrameInfo ( ) ; +MachineMemOperand * MMO = MBB . getParent ( ) -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FrameIndex ) , MachineMemOperand :: MOStore , MFI -> getObjectSize ( FrameIndex ) , MFI -> getObjectAlignment ( FrameIndex ) ) ; +BuildMI ( MBB , I , DL , get ( XCore :: STWFI ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addMemOperand ( MMO ) . addImm ( 0 ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/MachineFunctionInfo/Call.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/MachineFunctionInfo/Call.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6c8d75766004503c989d721a5da392f3d194ae7b --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/MachineFunctionInfo/Call.cpp @@ -0,0 +1,2 @@ +XCoreCall ( unsigned T ) : UsesLR ( false ) , LRSpillSlot ( 0 ) , FPSpillSlot ( 0 ) , VarArgsFrameIndex ( 0 ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/MachineFunctionInfo/ExternalSymbolCall.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/MachineFunctionInfo/ExternalSymbolCall.cpp new file mode 100644 index 0000000000000000000000000000000000000000..905bae2205f2d908b450455503422f584822a5f9 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/MachineFunctionInfo/ExternalSymbolCall.cpp @@ -0,0 +1,2 @@ +XCoreExternalSymbolCall ( const char * S ) : UsesLR ( false ) , LRSpillSlot ( 0 ) , FPSpillSlot ( 0 ) , VarArgsFrameIndex ( 0 ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/MachineFunctionInfo/FunctionCall.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/MachineFunctionInfo/FunctionCall.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d7ba722a059a85b677701346c0c7b66de1a9bf3a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/MachineFunctionInfo/FunctionCall.cpp @@ -0,0 +1,2 @@ +XCoreFunctionCall ( const Function * F ) : UsesLR ( false ) , LRSpillSlot ( 0 ) , FPSpillSlot ( 0 ) , VarArgsFrameIndex ( 0 ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/MachineFunctionInfo/FunctionInfo.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/MachineFunctionInfo/FunctionInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6164e57f433049649c56c56da6db72922fe8309c --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/MachineFunctionInfo/FunctionInfo.cpp @@ -0,0 +1,2 @@ +XCoreFunctionInfo ( ) : UsesLR ( false ) , LRSpillSlot ( 0 ) , FPSpillSlot ( 0 ) , VarArgsFrameIndex ( 0 ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/MachineFunctionInfo/FunctionInfo2.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/MachineFunctionInfo/FunctionInfo2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6e4ad3071bfb649c4034f9295593e4e7b66b806d --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/MachineFunctionInfo/FunctionInfo2.cpp @@ -0,0 +1,2 @@ +explicit XCoreFunctionInfo ( MachineFunction & MF ) : : UsesLR ( false ) , LRSpillSlot ( 0 ) , FPSpillSlot ( 0 ) , VarArgsFrameIndex ( 0 ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/MachineFunctionInfo/classof1.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/MachineFunctionInfo/classof1.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7fe0f84bf161a4321ef596a87d0021c3142e769e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/MachineFunctionInfo/classof1.cpp @@ -0,0 +1,3 @@ +static inline bool classof ( const XCoreCall * C ) { +return C -> getType ( ) == XCoreCall :: FunctionType ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/MachineFunctionInfo/classof2.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/MachineFunctionInfo/classof2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9d44a18c07869ec317b993601a7c580fe0e9c36a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/MachineFunctionInfo/classof2.cpp @@ -0,0 +1,3 @@ +static inline bool classof ( const XCoreFunctionCall * ) { +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/MachineFunctionInfo/classof3.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/MachineFunctionInfo/classof3.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f29f95c285d2c9398b5102aeb9f84f872793569f --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/MachineFunctionInfo/classof3.cpp @@ -0,0 +1,3 @@ +static inline bool classof ( const XCoreCall * ) { +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/MachineFunctionInfo/classof4.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/MachineFunctionInfo/classof4.cpp new file mode 100644 index 0000000000000000000000000000000000000000..df6befaf4902d48c44d19f377b1645844cbc7c1d --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/MachineFunctionInfo/classof4.cpp @@ -0,0 +1,3 @@ +static inline bool classof ( const XCoreExternalSymbolCall * ) { +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/MachineFunctionInfo/classof5.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/MachineFunctionInfo/classof5.cpp new file mode 100644 index 0000000000000000000000000000000000000000..02b859bbdd6ee6a1f11e31379e9590aa2eb37a01 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/MachineFunctionInfo/classof5.cpp @@ -0,0 +1,3 @@ +static inline bool classof ( const XCoreCall * C ) { +return C -> getType ( ) == XCoreCall :: ExternalSymbolType ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/MachineFunctionInfo/getCalls.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/MachineFunctionInfo/getCalls.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5adc8a97966212709ea643014afbdcae89ac93e4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/MachineFunctionInfo/getCalls.cpp @@ -0,0 +1,3 @@ +const std :: vector < XCoreCall * > & getCalls ( ) const { +return Calls ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/MachineFunctionInfo/getFunction.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/MachineFunctionInfo/getFunction.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0b2175ffa55a4f94e02bb3d6b4e36a9e825275af --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/MachineFunctionInfo/getFunction.cpp @@ -0,0 +1,3 @@ +const Function * getFunction ( ) { +return Fn ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/MachineFunctionInfo/getHasIndirectCalls.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/MachineFunctionInfo/getHasIndirectCalls.cpp new file mode 100644 index 0000000000000000000000000000000000000000..10040359dcb8151760f1be80b1e42d610f95320f --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/MachineFunctionInfo/getHasIndirectCalls.cpp @@ -0,0 +1,3 @@ +bool getHasIndirectCalls ( ) const { +return HasIndirectCalls ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/MachineFunctionInfo/getSymbol.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/MachineFunctionInfo/getSymbol.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bc191945e861f35a42eeb1ee9ffb096452844787 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/MachineFunctionInfo/getSymbol.cpp @@ -0,0 +1,3 @@ +const char * getSymbol ( ) { +return Sym ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/MachineFunctionInfo/getType.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/MachineFunctionInfo/getType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..cfac2032277ab3b21123ab953fee67f2f0611c89 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/MachineFunctionInfo/getType.cpp @@ -0,0 +1,3 @@ +unsigned getType ( ) const { +return Type ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/MachineFunctionInfo/getVarArgsFrameIndex.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/MachineFunctionInfo/getVarArgsFrameIndex.cpp new file mode 100644 index 0000000000000000000000000000000000000000..dc86317bf4ffdb2157afe0cc9f496c3f8454b58d --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/MachineFunctionInfo/getVarArgsFrameIndex.cpp @@ -0,0 +1,3 @@ +int getVarArgsFrameIndex ( ) const { +return VarArgsFrameIndex ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/MachineFunctionInfo/setHasIndirectCalls.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/MachineFunctionInfo/setHasIndirectCalls.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2404ad862713ec9f74e6b7a7aff202f4fa9a12cd --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/MachineFunctionInfo/setHasIndirectCalls.cpp @@ -0,0 +1,3 @@ +void setHasIndirectCalls ( bool val ) { +HasIndirectCalls = val ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/MachineFunctionInfo/setVarArgsFrameIndex.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/MachineFunctionInfo/setVarArgsFrameIndex.cpp new file mode 100644 index 0000000000000000000000000000000000000000..66ec61362627179d015c191feff7e83b189ae468 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/MachineFunctionInfo/setVarArgsFrameIndex.cpp @@ -0,0 +1,3 @@ +void setVarArgsFrameIndex ( int Index ) { +VarArgsFrameIndex = Index ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/MachineFunctionInfo/~FunctionInfo.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/MachineFunctionInfo/~FunctionInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..20b5ff310ae8e78377049130cf4afb646943c5a3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/MachineFunctionInfo/~FunctionInfo.cpp @@ -0,0 +1,2 @@ +XCoreFunctionInfo :: ~ XCoreFunctionInfo ( ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/Subtarget/Subtarget.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/Subtarget/Subtarget.cpp new file mode 100644 index 0000000000000000000000000000000000000000..41d360e211aec39795fc6180c6bc08e5b2da087e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/Subtarget/Subtarget.cpp @@ -0,0 +1,2 @@ +XCoreSubtarget :: XCoreSubtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS ) : XCoreGenSubtargetInfo ( TT , CPU , FS ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/TargetInfo/LLVMInitializeTargetInfo.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/TargetInfo/LLVMInitializeTargetInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..795ccd137b02f392ebe86e79fdb3188d1b58e076 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/TargetInfo/LLVMInitializeTargetInfo.cpp @@ -0,0 +1,3 @@ +extern "C" void LLVMInitializeXCoreTargetInfo ( ) { +RegisterTarget < Triple :: XCore > X ( TheXCoreTarget , "XCore" , "XCore" ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/TargetMachine/LLVMInitializeTarget.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/TargetMachine/LLVMInitializeTarget.cpp new file mode 100644 index 0000000000000000000000000000000000000000..82a072fb5c0fab266b2dd250c7853d1d5ca0abcb --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/TargetMachine/LLVMInitializeTarget.cpp @@ -0,0 +1,3 @@ +extern "C" void LLVMInitializeXCoreTarget ( ) { +RegisterTargetMachine < XCoreTargetMachine > X ( TheXCoreTarget ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/TargetMachine/TargetMachine.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/TargetMachine/TargetMachine.cpp new file mode 100644 index 0000000000000000000000000000000000000000..623379f36af0910719bb487f320de7475c9de555 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/TargetMachine/TargetMachine.cpp @@ -0,0 +1,2 @@ +XCoreTargetMachine :: XCoreTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , Reloc :: Model RM , CodeModel :: Model CM ) : LLVMTargetMachine ( T , TT , CPU , FS , RM , CM ) , Subtarget ( TT , CPU , FS ) , DataLayout ( "e-p:32:32:32-a0:0:32-f32:32:32-f64:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-v64:32:32-v128:32:32-n32" ) , InstrInfo ( ) , FrameLowering ( Subtarget ) , TLInfo ( * this ) , TSInfo ( * this ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/TargetMachine/addInstSelector.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/TargetMachine/addInstSelector.cpp new file mode 100644 index 0000000000000000000000000000000000000000..72c9d3f1aef44ff8567c25a81bde6577c599740e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/TargetMachine/addInstSelector.cpp @@ -0,0 +1,4 @@ +bool XCoreTargetMachine :: addInstSelector ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { +PM . add ( createXCoreISelDag ( * this , OptLevel ) ) ; +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/TargetMachine/addPreEmitPass.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/TargetMachine/addPreEmitPass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f9db25d5b9de30dfb6e05e466bd1cccd07c86f11 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/TargetMachine/addPreEmitPass.cpp @@ -0,0 +1,8 @@ +bool XCoreTargetMachine :: addPreEmitPass ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { +PM . add ( createXCoreFrameToArgsOffsetEliminationPass ( ) ) ; +if ( OptLevel == 0 ) { +PM . add ( createXCoreSimpleBranchOptPass ( ) ) ; +} +PM . add ( createXCoreStackUsage ( ) ) ; +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/TargetMachine/addPreISel.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/TargetMachine/addPreISel.cpp new file mode 100644 index 0000000000000000000000000000000000000000..30cc704dc2c1fe9f5cc40948c3cfb1916bd23627 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/TargetMachine/addPreISel.cpp @@ -0,0 +1,6 @@ +bool XCoreTargetMachine :: addPreISel ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { +PM . add ( createXCoreStackAnalysisPrepare ( ) ) ; +PM . add ( createXCoreLoopMetadataLowering ( ) ) ; +PM . add ( createXCoreLowerTwoStageResourceAllocPass ( ) ) ; +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/TargetMachine/getFrameLowering.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/TargetMachine/getFrameLowering.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1962f6fff4c722bb9a651c077e138d832639500d --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/TargetMachine/getFrameLowering.cpp @@ -0,0 +1,3 @@ +virtual const XCoreFrameLowering * getFrameLowering ( ) const { +return & FrameLowering ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/TargetMachine/getInstrInfo.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/TargetMachine/getInstrInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f82f9e350ed2843eb19a77d3415a863bbc4e24ad --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/TargetMachine/getInstrInfo.cpp @@ -0,0 +1,3 @@ +virtual const XCoreInstrInfo * getInstrInfo ( ) const { +return & InstrInfo ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/TargetMachine/getRegisterInfo.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/TargetMachine/getRegisterInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1896ceaecf72edecf383979445871297f1b9385e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/TargetMachine/getRegisterInfo.cpp @@ -0,0 +1,3 @@ +virtual const TargetRegisterInfo * getRegisterInfo ( ) const { +return & InstrInfo . getRegisterInfo ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/TargetMachine/getSelectionDAGInfo.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/TargetMachine/getSelectionDAGInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0c37ade2906db50eb7e2f2122b7dbb74aa22ffce --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/TargetMachine/getSelectionDAGInfo.cpp @@ -0,0 +1,3 @@ +virtual const XCoreSelectionDAGInfo * getSelectionDAGInfo ( ) const { +return & TSInfo ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/TargetMachine/getSubtargetImpl.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/TargetMachine/getSubtargetImpl.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fe4e169d02e3ac16876b8051a5ea87f31d2e95c7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/TargetMachine/getSubtargetImpl.cpp @@ -0,0 +1,3 @@ +virtual const XCoreSubtarget * getSubtargetImpl ( ) const { +return & Subtarget ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/TargetMachine/getTargetData.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/TargetMachine/getTargetData.cpp new file mode 100644 index 0000000000000000000000000000000000000000..695e32f1c08703020137c8d64952af28ebe0ce5b --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/TargetMachine/getTargetData.cpp @@ -0,0 +1,3 @@ +virtual const TargetData * getTargetData ( ) const { +return & DataLayout ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/TargetMachine/getTargetLowering.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/TargetMachine/getTargetLowering.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a4ff8036f06a6abca5675222a754c0a1ec54aed7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/TargetMachine/getTargetLowering.cpp @@ -0,0 +1,3 @@ +virtual const XCoreTargetLowering * getTargetLowering ( ) const { +return & TLInfo ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/TargetObjectFile/Initialize.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/TargetObjectFile/Initialize.cpp new file mode 100644 index 0000000000000000000000000000000000000000..57f9fcb8331119ee4f9b711d1dd6182f7b3f51b1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/TargetObjectFile/Initialize.cpp @@ -0,0 +1,7 @@ +void XCoreELFTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { +TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; +InitializeELF ( TM . Options . UseInitArray ) ; +SmallDataSection = getContext ( ) . getELFSection ( ".sdata" , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; +SmallBSSSection = getContext ( ) . getELFSection ( ".sbss" , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; +this -> TM = & static_cast < const XCoreTargetMachine & > ( TM ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/TargetObjectFile/SelectSectionForGlobal.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/TargetObjectFile/SelectSectionForGlobal.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b8a627cfc36fb8c0704138aba79d78b48de1b59d --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/TargetObjectFile/SelectSectionForGlobal.cpp @@ -0,0 +1,13 @@ +MCSection * XCoreELFTargetObjectFile :: SelectSectionForGlobal ( const GlobalObject * GO , SectionKind Kind , const TargetMachine & TM ) const { +if ( Kind . isBSS ( ) ) { +if ( isGlobalInSmallSection ( GO , TM ) ) { +return SmallBSSSection ; +} +} +if ( Kind . isData ( ) ) { +if ( isGlobalInSmallSection ( GO , TM ) ) { +return SmallDataSection ; +} +} +return TargetLoweringObjectFileELF :: SelectSectionForGlobal ( GO , Kind , TM ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/TargetObjectFile/getExplicitSectionGlobal.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/TargetObjectFile/getExplicitSectionGlobal.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3c1c2e504220d8bf69764050547cd07a02417df3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/TargetObjectFile/getExplicitSectionGlobal.cpp @@ -0,0 +1,10 @@ +MCSection * XCoreTargetObjectFile :: getExplicitSectionGlobal ( const GlobalObject * GO , SectionKind Kind , const TargetMachine & TM ) const { +StringRef SectionName = GO -> getSection ( ) ; +if ( SectionName . startswith ( ".XCore.comment." ) ) { +SK = SectionKind :: getMetadata ( ) ; +} +if ( isExecuteOnlyFunction ( GO , SK , TM ) ) { +SK = SectionKind :: getExecuteOnly ( ) ; +} +return TargetLoweringObjectFileELF :: getExplicitSectionGlobal ( GO , SK , TM ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/TargetObjectFile/getSectionForConstant.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/TargetObjectFile/getSectionForConstant.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2e0bf2601aabd729389669a020cea7bb96fe25ae --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Scheduling/TargetObjectFile/getSectionForConstant.cpp @@ -0,0 +1,6 @@ +MCSection * XCoreELFTargetObjectFile :: getSectionForConstant ( const DataLayout & DL , SectionKind Kind , const Constant * C , Align & Alignment ) const { +if ( isConstantInSmallSection ( DL , C ) ) { +return SmallDataSection ; +} +return TargetLoweringObjectFileELF :: getSectionForConstant ( DL , Kind , C , Alignment ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/FrameLowering/FrameLowering.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/FrameLowering/FrameLowering.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ce843baf5e1b318d6b63e010ccfee99c4841a3fc --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/FrameLowering/FrameLowering.cpp @@ -0,0 +1,2 @@ +XCoreFrameLowering :: XCoreFrameLowering ( const XCoreSubtarget & STI ) : TargetFrameLowering ( TargetFrameLowering :: StackGrowsDown , 4 , 0 ) , STI ( STI ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/FrameLowering/emitEpilogue.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/FrameLowering/emitEpilogue.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7bc32399cf47254a9d60e414ed4f48f8c305c25c --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/FrameLowering/emitEpilogue.cpp @@ -0,0 +1,42 @@ +void XCoreFrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { +const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; +MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; +XCoreMachineFunctionInfo * CFI = MF . getInfo < XCoreMachineFunctionInfo > ( ) ; +Register FPReg = getFPReg ( STI ) ; +Register SPReg = getSPReg ( STI ) ; +MachineBasicBlock :: iterator MBBI = MBB . end ( ) ; +DebugLoc DL ; +DL = MBBI -> getDebugLoc ( ) ; +if ( ! MBB . empty ( ) ) { +MBBI = MBB . getFirstTerminator ( ) ; +if ( MBBI == MBB . end ( ) ) { +MBBI = MBB . getLastNonDebugInstr ( ) ; +} +if ( ! MBBI -> isTerminator ( ) ) { +MBBI = std :: next ( MBBI ) ; +} +} +const auto & CSI = MFI . getCalleeSavedInfo ( ) ; +auto LastFrameDestroy = MBBI ; +if ( ! CSI . empty ( ) ) { +LastFrameDestroy = std :: prev ( MBBI , CSI . size ( ) ) ; +} +uint64_t StackSize = MFI . getStackSize ( ) ; +uint64_t ActualSize = CFI -> getCalleeSaveAreaSize ( ) + CFI -> getVarArgsSaveSize ( ) ; +if ( hasFP ( MF ) ) { +BuildMI ( MBB , LastFrameDestroy , DL , TII -> get ( TargetOpcode :: COPY ) , SPReg ) . addReg ( FPReg ) . setMIFlag ( MachineInstr :: NoFlags ) ; +} +if ( ! hasFP ( MF ) ) { +adjustReg ( MBB , LastFrameDestroy , DL , SPReg , SPReg , ( StackSize - ActualSize ) , MachineInstr :: FrameDestroy ) ; +} +adjustReg ( MBB , MBBI , DL , SPReg , SPReg , ActualSize , MachineInstr :: FrameDestroy ) ; +if ( ! StackSize ) { +return ; +} +if ( materializeOffset ( MF , MBB , MBBI , ( unsigned ) StackSize ) ) { +BuildMI ( MBB , MBBI , DL , TII . get ( XCore :: ADDrr ) , XCore :: SP ) . addReg ( StackReg ) . addReg ( OffsetReg ) . setMIFlag ( MachineInstr :: FrameSetup ) ; +} +if ( ! materializeOffset ( MF , MBB , MBBI , ( unsigned ) StackSize ) ) { +BuildMI ( MBB , MBBI , DL , TII . get ( XCore :: ADDri ) , XCore :: SP ) . addReg ( StackReg ) . addImm ( StackSize ) . setMIFlag ( MachineInstr :: FrameSetup ) ; +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/FrameLowering/emitPrologue.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/FrameLowering/emitPrologue.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fbc884f66e605faabddee76c48f0dd67d2d3e9ab --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/FrameLowering/emitPrologue.cpp @@ -0,0 +1,72 @@ +void XCoreFrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { +const RegisterInfo * RI = STI . getRegisterInfo ( ) ; +MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; +MachineFunctionInfo * CFI = MF . getInfo < MachineFunctionInfo > ( ) ; +Register SPReg = getSPReg ( STI ) ; +Register BPReg = getBPReg ( STI ) ; +const XCoreInstrInfo * TII = STI . getInstrInfo ( ) ; +MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; +const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; +const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; +DebugLoc DL ; +if ( MF . getFunction ( ) . hasFnAttribute ( "interrupt" ) ) { +} +determineFrameLayout ( MF ) ; +uint64_t StackSize = MFI . getStackSize ( ) ; +if ( StackSize == 0 ) { +if ( ! MFI . adjustsStack ( ) ) { +return ; +} +} +const auto & CSI = MFI . getCalleeSavedInfo ( ) ; +unsigned spillAreaSize = CFI -> getCalleeSaveAreaSize ( ) ; +uint64_t ActualSize = spillAreaSize + CFI -> getVarArgsSaveSize ( ) ; +adjustReg ( MBB , MBBI , DL , SPReg , SPReg , - ( static_cast < int64_t > ( ActualSize ) ) , MachineInstr :: NoFlags ) ; +unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfaOffset ( nullptr , ActualSize ) ) ; +std :: advance ( MBBI , CSI . size ( ) ) ; +for ( const auto & Entry : CSI ) { +int64_t Offset = MFI . getObjectOffset ( Entry . getFrameIdx ( ) ) ; +unsigned Num = TRI -> getRegSizeInBits ( Reg , MRI ) / 32 ; +for ( unsigned i = 0 ; i < Num ; i ++ ) { +unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , RI -> getDwarfRegNum ( Reg , true ) + i , Offset + i * 4 ) ) ; +BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; +} +} +if ( hasFP ( MF ) ) { +unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaRegister ( nullptr , RI -> getDwarfRegNum ( FPReg , true ) ) ) ; +adjustReg ( MBB , MBBI , DL , SPReg , SPReg , - ( static_cast < int64_t > ( StackSize - ActualSize ) ) , MachineInstr :: NoFlags ) ; +const XCoreRegisterInfo * RI = STI . getRegisterInfo ( ) ; +if ( RI -> hasStackRealignment ( MF ) ) { +Align MaxAlignment = MFI . getMaxAlign ( ) ; +const XCoreInstrInfo * TII = STI . getInstrInfo ( ) ; +if ( isUInt < 12 > ( ~ ( - ( int ) MaxAlignment . value ( ) ) ) ) { +BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) , SPReg ) . addReg ( SPReg ) . addImm ( ~ ( - ( int ) MaxAlignment . value ( ) ) ) ; +} +if ( ! STI . hasE2 ( ) ) { +unsigned ShiftAmount = Log2 ( MaxAlignment ) ; +Register VR = MF . getRegInfo ( ) . createVirtualRegister ( & XCore :: GPRRegClass ) ; +if ( ! STI . hasE2 ( ) ) { +Register VR = MF . getRegInfo ( ) . createVirtualRegister ( & XCore :: mGPRRegClass ) ; +} +} +if ( ! isUInt < 12 > ( ~ ( - ( int ) MaxAlignment . value ( ) ) ) ) { +unsigned ShiftAmount = Log2 ( MaxAlignment ) ; +Register VR = MF . getRegInfo ( ) . createVirtualRegister ( & XCore :: GPRRegClass ) ; +BuildMI ( MBB , MBBI , DL , TII -> get ( XCore::ANDI ) , SPReg ) . addReg ( VR ) . addImm ( ShiftAmount ) ; +if ( ! STI . hasE2 ( ) ) { +Register VR = MF . getRegInfo ( ) . createVirtualRegister ( & XCore :: mGPRRegClass ) ; +BuildMI ( MBB , MBBI , DL , TII -> get ( XCore :: ANDI ) , VR ) . addReg ( SPReg ) ; +BuildMI ( MBB , MBBI , DL , TII -> get ( XCore::SRLI ) , VR ) . addReg ( VR ) . addImm ( ShiftAmount ) ; +BuildMI ( MBB , MBBI , DL , TII -> get ( XCore :: SLLI ) , SPReg ) . addReg ( VR ) ; +} +} +} +if ( hasBP ( MF ) ) { +BuildMI ( MBB , MBBI , DL , TII -> get ( XCore::ADDI ) , BPReg ) . addReg ( SPReg ) ; +} +} +if ( ! hasFP ( MF ) ) { +adjustReg ( MBB , MBBI , DL , SPReg , SPReg , - ( static_cast < int64_t > ( StackSize - ActualSize ) ) , MachineInstr :: NoFlags ) ; +unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfaOffset ( nullptr , MFI . getStackSize ( ) ) ) ; +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/FrameLowering/hasFP.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/FrameLowering/hasFP.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5614fb4b4b63e1357e33a1dbc086c7c68b8e52cf --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/FrameLowering/hasFP.cpp @@ -0,0 +1,3 @@ +bool XCoreFrameLowering :: hasFP ( const MachineFunction & MF ) const { +return DisableFramePointerElim ( MF ) || MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/FrameLowering/isShrinkWrappingProfitable.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/FrameLowering/isShrinkWrappingProfitable.cpp new file mode 100644 index 0000000000000000000000000000000000000000..dc93b19f6dad24a71e00a98f45eebdfa0156155b --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/FrameLowering/isShrinkWrappingProfitable.cpp @@ -0,0 +1,3 @@ +bool XCoreFrameLowering :: isShrinkWrappingProfitable ( ) const { +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/FrameLowering/processFunctionBeforeCalleeSavedScan.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/FrameLowering/processFunctionBeforeCalleeSavedScan.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c0ec1fc615a4426f96098f20838b986f54627d97 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/FrameLowering/processFunctionBeforeCalleeSavedScan.cpp @@ -0,0 +1,19 @@ +void XCoreFrameLowering :: processFunctionBeforeCalleeSavedScan ( MachineFunction & MF , RegScavenger * RS ) const { +MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; +MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; +const TargetRegisterClass * RC = & XCore :: R32CRegClass ; +RS -> setScavengingFrameIndex ( MFI -> CreateStackObject ( RC -> getSize ( ) , RC -> getAlignment ( ) , false ) ) ; +XCoreFunctionInfo * FI = MF . getInfo < XCoreFunctionInfo > ( ) ; +CallingConv :: ID CallConv = MF . getFunction ( ) -> getCallingConv ( ) ; +bool requiresRA = CallConv == CallingConv :: MBLAZE_INTR ; +if ( MFI -> adjustsStack ( ) || requiresRA ) { +MBlazeFI -> setRAStackOffset ( 0 ) ; +MFI -> CreateFixedObject ( 4 , 0 , true ) ; +} +if ( hasFP ( MF ) ) { +MBlazeFI -> setFPStackOffset ( 4 ) ; +MFI -> CreateFixedObject ( 4 , 4 , true ) ; +} +interruptFrameLayout ( MF ) ; +analyzeFrameIndexes ( MF ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/FrameLowering/processFunctionBeforeFrameFinalized.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/FrameLowering/processFunctionBeforeFrameFinalized.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8b12f196b62ec88d75099afd4f550eb656f8f683 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/FrameLowering/processFunctionBeforeFrameFinalized.cpp @@ -0,0 +1,2 @@ +void XCoreFrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF ) const { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/FrameLowering/restoreCalleeSavedRegisters.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/FrameLowering/restoreCalleeSavedRegisters.cpp new file mode 100644 index 0000000000000000000000000000000000000000..10d7ffbeb9e337a5f782dcf7c42f619b91d5b559 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/FrameLowering/restoreCalleeSavedRegisters.cpp @@ -0,0 +1,19 @@ +bool XCoreFrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , MutableArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { +if ( CSI . empty ( ) ) { +return true ; +} +MachineFunction * MF = MBB . getParent ( ) ; +const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ; +DebugLoc DL ; +if ( MI != MBB . end ( ) ) { +if ( ! MI -> isDebugInstr ( ) ) { +DL = MI -> getDebugLoc ( ) ; +} +} +for ( auto & CS : CSI ) { +Register Reg = CS . getReg ( ) ; +const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ; +TII . loadRegFromStackSlot ( MBB , MI , Reg , CS . getFrameIdx ( ) , RC , TRI ) ; +} +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/FrameLowering/spillCalleeSavedRegisters.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/FrameLowering/spillCalleeSavedRegisters.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0943e166c7a184db8ed35147d9763849caa8149b --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/FrameLowering/spillCalleeSavedRegisters.cpp @@ -0,0 +1,73 @@ +bool XCoreFrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { +if ( CSI . empty ( ) ) { +return false ; +} +DebugLoc DL ; +unsigned CalleeFrameSize = 0 ; +DebugLoc DL = MBB . findDebugLoc ( MI ) ; +DebugLoc dl ; +if ( MI != MBB . end ( ) ) { +DL = MI -> getDebugLoc ( ) ; +} +MachineFunction * MF = MBB . getParent ( ) ; +const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ; +DebugLoc DL ; +if ( MI != MBB . end ( ) ) { +DL = MI -> getDebugLoc ( ) ; +if ( ! MI -> isDebugInstr ( ) ) { +} +} +MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( XCore :: tPUSH ) ) ; +AddDefaultPred ( MIB ) ; +MachineFunctionInfo * XCoreFI = MF . getInfo < MachineFunctionInfo > ( ) ; +MachineFunctionInfo * MFI = MF . getInfo < MachineFunctionInfo > ( ) ; +XCoreMachineFunctionInfo * MFI = MF . getInfo < XCoreMachineFunctionInfo > ( ) ; +MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * 2 ) ; +MachineBasicBlock * EntryBlock = MF -> begin ( ) ; +for ( const CalleeSavedInfo & CS : CSI ) { +unsigned Reg = CS . getReg ( ) ; +if ( CS . isSpilledToReg ( ) ) { +BuildMI ( MBB , MBBI , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , CS . getDstReg ( ) ) . addReg ( Reg , getKillRegState ( true ) ) ; +} +if ( ! CS . isSpilledToReg ( ) ) { +const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; +const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; +TII -> storeRegToStackSlotCFI ( MBB , MBBI , Reg , ! IsLiveIn , CS . getFrameIdx ( ) , RC , TRI ) ; +} +MachineFunction * MF = MBB . getParent ( ) ; +if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) ) { +if ( MF . getRegInfo ( ) . isLiveIn ( Reg ) ) { +} +} +if ( isKill ) { +MBB . addLiveIn ( Reg ) ; +} +MIB . addReg ( Reg , getKillRegState ( isKill ) ) ; +bool IsNotLiveIn = ! MBB . isLiveIn ( Reg ) ; +if ( IsNotLiveIn ) { +MBB . addLiveIn ( Reg ) ; +} +CalleeFrameSize = CalleeFrameSize + 1 ; +MBB . addLiveIn ( Reg ) ; +bool IsRAAndRetAddrIsTaken = ( Reg == XCore :: LR ) && MF -> getFrameInfo ( ) . isReturnAddressTaken ( ) ; +bool IsRAAndRetAddrIsTaken = ( Reg == XCore :: RA || Reg == XCore :: RA_64 ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ; +bool IsRAAndRetAddrIsTaken = ( Reg == XCore :: L ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ; +if ( ! IsRAAndRetAddrIsTaken ) { +EntryBlock -> addLiveIn ( Reg ) ; +} +bool IsKill = ! IsRAAndRetAddrIsTaken ; +Register Reg = CS . getReg ( ) ; +const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; +TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; +TII . storeRegToStackSlot ( MBB , MI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ; +BuildMI ( MBB , MI , dl , TII . get ( XCore :: PUSH16r ) ) . addReg ( Reg , RegState :: Kill ) ; +if ( ! MBB . isLiveIn ( Reg ) ) { +MBB . addLiveIn ( Reg ) ; +} +TII -> storeRegToStackSlot ( MBB , MBBI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ; +} +MIB . setMIFlags ( MachineInstr :: FrameSetup ) ; +XCoreFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ; +MFI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ; +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/FrameLowering/stackSlotSize.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/FrameLowering/stackSlotSize.cpp new file mode 100644 index 0000000000000000000000000000000000000000..54770bc352d2a56951a1340591d6fec7fa919cc5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/FrameLowering/stackSlotSize.cpp @@ -0,0 +1,3 @@ +static int stackSlotSize ( ) { +return 4 ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelDAGToDAG/DAGToDAGISel.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelDAGToDAG/DAGToDAGISel.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c5090eff583501f0c50b3201a43af65d2517b874 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelDAGToDAG/DAGToDAGISel.cpp @@ -0,0 +1,2 @@ +XCoreDAGToDAGISel ( XCoreTargetMachine & TM , CodeGenOpt :: Level OptLevel ) : SelectionDAGISel ( TM , OptLevel ) , Lowering ( * TM . getTargetLowering ( ) ) , Subtarget ( * TM . getSubtargetImpl ( ) ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelDAGToDAG/Select.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelDAGToDAG/Select.cpp new file mode 100644 index 0000000000000000000000000000000000000000..459ce799c25ea386f4fa4e80d94ae074012ce619 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelDAGToDAG/Select.cpp @@ -0,0 +1,134 @@ +void XCoreDAGToDAGISel :: Select ( SDNode * Node ) { +unsigned Opcode = Node -> getOpcode ( ) ; +DEBUG ( dbgs ( ) << "Selecting: " ; Node -> dump ( CurDAG ) ; dbgs ( ) << '\n' ) ; +DebugLoc dl = Node -> getDebugLoc ( ) ; +DEBUG ( errs ( ) << "Selecting: " ; Node -> dump ( CurDAG ) ; errs ( ) << "\n" ) ; +if ( Node -> isMachineOpcode ( ) ) { +DEBUG ( dbgs ( ) << "== " ; Node -> dump ( CurDAG ) ; dbgs ( ) << '\n' ) ; +DEBUG ( errs ( ) << "== " ; Node -> dump ( CurDAG ) ; errs ( ) << "\n" ) ; +LLVM_DEBUG ( dbgs ( ) << "== " ; Node -> dump ( CurDAG ) ; dbgs ( ) << "\n" ) ; +Node -> setNodeId ( - 1 ) ; +LLVM_DEBUG ( errs ( ) << "== " ; Node -> dump ( CurDAG ) ; errs ( ) << "\n" ) ; +return ; +return NULL ; +} +EVT NodeTy = Node -> getValueType ( 0 ) ; +unsigned MultOpc ; +SDLoc Dl ( Node ) ; +unsigned Opcode = Node -> getOpcode ( ) ; +bool IsSelected = false ; +DebugLoc Empty ; +const DebugLoc & DL = Node -> getDebugLoc ( ) ; +if ( DL != Empty ) { +} +if ( DL == Empty ) { +} +errs ( ) << "Unsupport signed division for DAG: " ; +Node -> print ( errs ( ) , CurDAG ) ; +errs ( ) << "Please convert to unsigned div/mod.\n" ; +break ; +MultOpc = ( Opcode == ISD :: MULHU ? XCore :: MULTu : XCore :: MULT ) ; +return SelectMULT ( Node , MultOpc , dl , NodeTy , false , true ) . second ; +IsSelected = selectAddCarry ( Node ) ; +if ( Opcode == ISD :: ADD ) { +unsigned IntNo = cast < ConstantSDNode > ( Node -> getOperand ( 1 ) ) -> getZExtValue ( ) ; +SDLoc DL ( Node ) ; +SDValue Chain = Node -> getOperand ( 0 ) ; +SDValue Skb = Node -> getOperand ( 2 ) ; +SDValue N3 = Node -> getOperand ( 3 ) ; +SDValue R6Reg = CurDAG -> getRegister ( XCore :: R6 , MVT :: i64 ) ; +Chain = CurDAG -> getCopyToReg ( Chain , DL , R6Reg , Skb , SDValue ( ) ) ; +Node = CurDAG -> UpdateNodeOperands ( Node , Chain , N1 , R6Reg , N3 ) ; +break ; +if ( IntNo == ISD :: Constant ) { +SDLoc DL ( Node ) ; +SDValue Chain = Node -> getOperand ( 0 ) ; +SDValue Skb = Node -> getOperand ( 2 ) ; +SDValue N3 = Node -> getOperand ( 3 ) ; +SDValue R6Reg = CurDAG -> getRegister ( XCore :: R6 , MVT :: i64 ) ; +Chain = CurDAG -> getCopyToReg ( Chain , DL , R6Reg , Skb , SDValue ( ) ) ; +Node = CurDAG -> UpdateNodeOperands ( Node , Chain , N1 , R6Reg , N3 ) ; +break ; +} +if ( IntNo == ISD :: FrameIndex ) { +SDLoc DL ( Node ) ; +SDValue Chain = Node -> getOperand ( 0 ) ; +SDValue Skb = Node -> getOperand ( 2 ) ; +SDValue N3 = Node -> getOperand ( 3 ) ; +SDValue R6Reg = CurDAG -> getRegister ( XCore :: R6 , MVT :: i64 ) ; +Chain = CurDAG -> getCopyToReg ( Chain , DL , R6Reg , Skb , SDValue ( ) ) ; +Node = CurDAG -> UpdateNodeOperands ( Node , Chain , N1 , R6Reg , N3 ) ; +break ; +} +MultOpc = ( Opcode == ISD :: MULHU ? XCore :: MULTu : XCore :: MULT ) ; +return SelectMULT ( Node , MultOpc , dl , NodeTy , false , true ) . second ; +IsSelected = selectSubCarry ( Node ) ; +} +MVT XLenVT = MVT :: i32 ; +SDLoc DL ( Node ) ; +EVT VT = Node -> getValueType ( 0 ) ; +if ( Opcode == ISD :: INTRINSIC_W_CHAIN ) { +int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ; +EVT VT = Node -> getValueType ( 0 ) ; +SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ; +unsigned Opc = XCore :: MOV_rr ; +if ( Node -> hasOneUse ( ) ) { +CurDAG -> SelectNodeTo ( Node , Opc , VT , TFI ) ; +return ; +} +ReplaceNode ( Node , CurDAG -> getMachineNode ( Opc , SDLoc ( Node ) , VT , TFI ) ) ; +return ; +return getGlobalBaseReg ( ) ; +Register GP = Subtarget -> getInstrInfo ( ) -> getGlobalBaseReg ( * MF ) ; +ReplaceNode ( Node , CurDAG -> getRegister ( GP , Node -> getValueType ( 0 ) ) . getNode ( ) ) ; +IsSelected = true ; +auto ConstNode = cast < ConstantSDNode > ( Node ) ; +ConstantSDNode * ConstNode = cast < ConstantSDNode > ( Node ) ; +if ( ConstNode -> isNullValue ( ) ) { +SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , XCore :: R0 , MVT :: i32 ) ; +return ReplaceNode ( Node , New . getNode ( ) ) ; +SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , XCore :: ZERO , XLenVT ) ; +ReplaceNode ( Node , New . getNode ( ) ) ; +return ; +} +if ( ConstNode -> isAllOnesValue ( ) ) { +SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , XCore :: R1 , MVT :: i32 ) ; +return ReplaceNode ( Node , New . getNode ( ) ) ; +} +int64_t Imm = ConstNode -> getSExtValue ( ) ; +if ( XLenVT == MVT :: i32 ) { +ReplaceNode ( Node , selectImm ( CurDAG , SDLoc ( Node ) , Imm , XLenVT ) ) ; +return ; +} +break ; +} +SDLoc dl ( Node ) ; +int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ; +SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , MVT :: i32 ) ; +if ( Node -> hasOneUse ( ) ) { +CurDAG -> SelectNodeTo ( Node , XCore :: ADDri , MVT :: i32 , TFI , CurDAG -> getTargetConstant ( 0 , dl , MVT :: i32 ) ) ; +return ; +} +ReplaceNode ( Node , CurDAG -> getMachineNode ( XCore :: ADDri , dl , MVT :: i32 , TFI , CurDAG -> getTargetConstant ( 0 , dl , MVT :: i32 ) ) ) ; +return ; +SelectCode ( Node ) ; +if ( Opcode == ISD :: INTRINSIC_VOID ) { +const ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Node ) ; +unsigned Size = CN -> getValueSizeInBits ( 0 ) ; +if ( Size == 32 ) { +break ; +} +int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ; +ReplaceNode ( Node , CurDAG -> getMachineNode ( Subtarget -> hasE2 ( ) ? XCore :: ADDI32 : XCore :: ADDI16XZ , Dl , MVT :: i32 , TFI , Imm ) ) ; +IsSelected = true ; +selectFrameIndex ( Node ) ; +ReplaceNode ( Node , CurDAG -> getMachineNode ( XCore :: ADDI , DL , VT , TFI , Imm ) ) ; +return ; +} +SDNode * ResNode = SelectCode ( Node ) ; +return ResNode ; +if ( IsSelected ) { +return ; +} +SelectCode ( Node ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelDAGToDAG/SelectADDRcpii.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelDAGToDAG/SelectADDRcpii.cpp new file mode 100644 index 0000000000000000000000000000000000000000..afcac9b3f35d705e7831a56e71d84e7622b02c76 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelDAGToDAG/SelectADDRcpii.cpp @@ -0,0 +1,16 @@ +bool XCoreDAGToDAGISel :: SelectADDRcpii ( SDValue Addr , SDValue & Base , SDValue & Offset ) { +if ( Addr . getOpcode ( ) == XCoreISD :: CPRelativeWrapper ) { +Base = Addr . getOperand ( 0 ) ; +Offset = CurDAG -> getTargetConstant ( 0 , MVT :: i32 ) ; +return true ; +} +if ( Addr . getOpcode ( ) == ISD :: ADD ) { +ConstantSDNode * CN = 0 ; +if ( ( Addr . getOperand ( 0 ) . getOpcode ( ) == XCoreISD :: CPRelativeWrapper ) && ( CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( 1 ) ) ) && ( CN -> getSExtValue ( ) % 4 == 0 && CN -> getSExtValue ( ) >= 0 ) ) { +Base = Addr . getOperand ( 0 ) . getOperand ( 0 ) ; +Offset = CurDAG -> getTargetConstant ( CN -> getSExtValue ( ) , MVT :: i32 ) ; +return true ; +} +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelDAGToDAG/SelectADDRdpii.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelDAGToDAG/SelectADDRdpii.cpp new file mode 100644 index 0000000000000000000000000000000000000000..be39c1d301621ed75b3043f7217c4d1557b935c8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelDAGToDAG/SelectADDRdpii.cpp @@ -0,0 +1,16 @@ +bool XCoreDAGToDAGISel :: SelectADDRdpii ( SDValue Addr , SDValue & Base , SDValue & Offset ) { +if ( Addr . getOpcode ( ) == XCoreISD :: DPRelativeWrapper ) { +Base = Addr . getOperand ( 0 ) ; +Offset = CurDAG -> getTargetConstant ( 0 , MVT :: i32 ) ; +return true ; +} +if ( Addr . getOpcode ( ) == ISD :: ADD ) { +ConstantSDNode * CN = 0 ; +if ( ( Addr . getOperand ( 0 ) . getOpcode ( ) == XCoreISD :: DPRelativeWrapper ) && ( CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( 1 ) ) ) && ( CN -> getSExtValue ( ) % 4 == 0 && CN -> getSExtValue ( ) >= 0 ) ) { +Base = Addr . getOperand ( 0 ) . getOperand ( 0 ) ; +Offset = CurDAG -> getTargetConstant ( CN -> getSExtValue ( ) , MVT :: i32 ) ; +return true ; +} +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelDAGToDAG/SelectADDRspii.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelDAGToDAG/SelectADDRspii.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5b48277fc9524b0c8cb90b3c06c1238bf196f8df --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelDAGToDAG/SelectADDRspii.cpp @@ -0,0 +1,17 @@ +bool XCoreDAGToDAGISel :: SelectADDRspii ( SDValue Addr , SDValue & Base , SDValue & Offset ) { +FrameIndexSDNode * FIN = 0 ; +if ( ( FIN = dyn_cast < FrameIndexSDNode > ( Addr ) ) ) { +Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , MVT :: i32 ) ; +Offset = CurDAG -> getTargetConstant ( 0 , MVT :: i32 ) ; +return true ; +} +if ( Addr . getOpcode ( ) == ISD :: ADD ) { +ConstantSDNode * CN = 0 ; +if ( ( FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( 0 ) ) ) && ( CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( 1 ) ) ) && ( CN -> getSExtValue ( ) % 4 == 0 && CN -> getSExtValue ( ) >= 0 ) ) { +Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , MVT :: i32 ) ; +Offset = CurDAG -> getTargetConstant ( CN -> getSExtValue ( ) , MVT :: i32 ) ; +return true ; +} +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelDAGToDAG/SelectInlineAsmMemoryOperand.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelDAGToDAG/SelectInlineAsmMemoryOperand.cpp new file mode 100644 index 0000000000000000000000000000000000000000..255a2293fa271fdaa539e7bd3a7d0468d31e2559 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelDAGToDAG/SelectInlineAsmMemoryOperand.cpp @@ -0,0 +1,8 @@ +bool XCoreDAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , unsigned ConstraintID , std :: vector < SDValue > & OutOps ) { +OutOps . push_back ( Op ) ; +OutOps . push_back ( Op ) ; +return false ; +OutOps . push_back ( Op ) ; +return false ; +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelDAGToDAG/createISelDag.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelDAGToDAG/createISelDag.cpp new file mode 100644 index 0000000000000000000000000000000000000000..039e4aeeb2b838fa97154902c09cfacb254098ac --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelDAGToDAG/createISelDag.cpp @@ -0,0 +1,3 @@ +FunctionPass * llvm :: createXCoreISelDag ( XCoreTargetMachine & TM , CodeGenOpt :: Level OptLevel ) { +return new XCoreDAGToDAGISel ( TM , OptLevel ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelDAGToDAG/getI32Imm.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelDAGToDAG/getI32Imm.cpp new file mode 100644 index 0000000000000000000000000000000000000000..29e43cde1da4a67936e90f1283dd0dc5ce79b865 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelDAGToDAG/getI32Imm.cpp @@ -0,0 +1,3 @@ +inline SDValue getI32Imm ( unsigned Imm ) { +return CurDAG -> getTargetConstant ( Imm , MVT :: i32 ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelDAGToDAG/getPassName.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelDAGToDAG/getPassName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fcbdce0cff47e27816c1db6da52831c5eecd1483 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelDAGToDAG/getPassName.cpp @@ -0,0 +1,3 @@ +virtual const char * getPassName ( ) const { +return "XCore DAG->DAG Pattern Instruction Selection" ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelDAGToDAG/immBitp.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelDAGToDAG/immBitp.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a7701596e14fadf5b7483924b3a14459634d08ee --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelDAGToDAG/immBitp.cpp @@ -0,0 +1,42 @@ +inline bool immBitp ( SDNode * inN ) const { +const ConstantFPSDNode * CN = dyn_cast < ConstantFPSDNode > ( N ) ; +if ( ! CN ) { +return false ; +} +bool IsExact ; +APSInt IntVal ( 65 , true ) ; +CN -> getValueAPF ( ) . convertToInteger ( IntVal , APFloat :: rmTowardZero , & IsExact ) ; +if ( ! IsExact ) { +return false ; +} +if ( ! IntVal . isPowerOf2 ( ) ) { +return false ; +} +unsigned FBits = IntVal . logBase2 ( ) ; +return false ; +if ( FBits > RegWidth ) { +return false ; +} +FixedPos = CurDAG -> getTargetConstant ( 64 - FBits , MVT :: i32 ) ; +return true ; +SDLoc dl ( N ) ; +if ( ConstantSDNode * Imm = dyn_cast < ConstantSDNode > ( N . getNode ( ) ) ) { +Reg = CurDAG -> getRegister ( XCore :: NoRegister , MVT :: i1 ) ; +Inv = CurDAG -> getTargetConstant ( ( Imm -> getConstantIntValue ( ) -> isZero ( ) ) ? 1 : 0 , dl , MVT :: i1 ) ; +} +if ( ! ( ConstantSDNode * Imm = dyn_cast < ConstantSDNode > ( N . getNode ( ) ) ) ) { +Reg = N ; +Inv = CurDAG -> getTargetConstant ( 0 , dl , MVT :: i1 ) ; +} +if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( N ) ) { +R1 = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , MVT :: i32 ) ; +return true ; +} +if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( N ) ) { +if ( v ) { +if ( ! ( v & ( v - 1 ) ) ) { +} +} +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelDAGToDAG/immMskBitp.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelDAGToDAG/immMskBitp.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8d87916eb96d39e97815ce7bcb172f627fc08d0a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelDAGToDAG/immMskBitp.cpp @@ -0,0 +1,42 @@ +inline bool immMskBitp ( SDNode * inN ) const { +const ConstantFPSDNode * CN = dyn_cast < ConstantFPSDNode > ( N ) ; +if ( ! CN ) { +return false ; +} +bool IsExact ; +APSInt IntVal ( 65 , true ) ; +CN -> getValueAPF ( ) . convertToInteger ( IntVal , APFloat :: rmTowardZero , & IsExact ) ; +if ( ! IsExact ) { +return false ; +} +if ( ! IntVal . isPowerOf2 ( ) ) { +return false ; +} +unsigned FBits = IntVal . logBase2 ( ) ; +return false ; +if ( FBits > RegWidth ) { +return false ; +} +FixedPos = CurDAG -> getTargetConstant ( 64 - FBits , MVT :: i32 ) ; +return true ; +SDLoc dl ( N ) ; +if ( ConstantSDNode * Imm = dyn_cast < ConstantSDNode > ( N . getNode ( ) ) ) { +Reg = CurDAG -> getRegister ( XCore :: NoRegister , MVT :: i1 ) ; +Inv = CurDAG -> getTargetConstant ( ( Imm -> getConstantIntValue ( ) -> isZero ( ) ) ? 1 : 0 , dl , MVT :: i1 ) ; +} +if ( ! ( ConstantSDNode * Imm = dyn_cast < ConstantSDNode > ( N . getNode ( ) ) ) ) { +Reg = N ; +Inv = CurDAG -> getTargetConstant ( 0 , dl , MVT :: i1 ) ; +} +if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( N ) ) { +R1 = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , MVT :: i32 ) ; +return true ; +} +if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( N ) ) { +if ( v ) { +if ( ! ( v & ( v - 1 ) ) ) { +} +} +} +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/CanLowerReturn.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/CanLowerReturn.cpp new file mode 100644 index 0000000000000000000000000000000000000000..bf58df0f1deca09a1617bd8c642e6d94c43246b5 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/CanLowerReturn.cpp @@ -0,0 +1,11 @@ +bool XCoreTargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , LLVMContext & Context ) const { +SmallVector < CCValAssign , 16 > RVLocs ; +CCState CCInfo ( CallConv , isVarArg , MF , getTargetMachine ( ) , RVLocs , Context ) ; +if ( ! CCInfo . CheckReturn ( Outs , RetCC_XCore ) ) { +return false ; +} +if ( CCInfo . getNextStackOffset ( ) != 0 && isVarArg ) { +return false ; +} +return true ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/EmitInstrWithCustomInserter.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/EmitInstrWithCustomInserter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9452fa0fc125f5e7646b881b443594613faba537 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/EmitInstrWithCustomInserter.cpp @@ -0,0 +1,25 @@ +MachineBasicBlock * XCoreTargetLowering :: EmitInstrWithCustomInserter ( MachineInstr * MI , MachineBasicBlock * BB ) const { +const TargetInstrInfo & TII = * getTargetMachine ( ) . getInstrInfo ( ) ; +DebugLoc dl = MI -> getDebugLoc ( ) ; +assert ( ( MI -> getOpcode ( ) == XCore :: SELECT_CC ) && "Unexpected instr type to insert" ) ; +const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; +MachineFunction :: iterator I = BB ; +++ I ; +MachineBasicBlock * thisMBB = BB ; +MachineFunction * F = BB -> getParent ( ) ; +MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; +MachineBasicBlock * copy1MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; +F -> insert ( I , copy0MBB ) ; +F -> insert ( I , copy1MBB ) ; +copy1MBB -> splice ( copy1MBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; +copy1MBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; +BB -> addSuccessor ( copy0MBB ) ; +BB -> addSuccessor ( copy1MBB ) ; +BuildMI ( BB , dl , TII . get ( XCore :: BRFT_lru6 ) ) . addReg ( MI -> getOperand ( 1 ) . getReg ( ) ) . addMBB ( copy1MBB ) ; +BB = copy0MBB ; +BB -> addSuccessor ( copy1MBB ) ; +BB = copy1MBB ; +BuildMI ( * BB , BB -> begin ( ) , dl , TII . get ( XCore :: PHI ) , MI -> getOperand ( 0 ) . getReg ( ) ) . addReg ( MI -> getOperand ( 3 ) . getReg ( ) ) . addMBB ( copy0MBB ) . addReg ( MI -> getOperand ( 2 ) . getReg ( ) ) . addMBB ( thisMBB ) ; +MI -> eraseFromParent ( ) ; +return BB ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/ExpandADDSUB.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/ExpandADDSUB.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ca3dbf417574f79cf172ac534810daad76c105e1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/ExpandADDSUB.cpp @@ -0,0 +1,44 @@ +SDValue XCoreTargetLowering :: ExpandADDSUB ( SDNode * N , SelectionDAG & DAG ) const { +EVT VT = N -> getValueType ( 0 ) ; +SDLoc dl ( N ) ; +if ( VT != MVT :: i64 ) { +} +assert ( ( N -> getOpcode ( ) == ISD :: SRL || N -> getOpcode ( ) == ISD :: SRA ) && "Unknown shift to lower!" ) ; +if ( ! isa < ConstantSDNode > ( N -> getOperand ( 1 ) ) || cast < ConstantSDNode > ( N -> getOperand ( 1 ) ) -> getZExtValue ( ) != 1 ) { +} +if ( ST -> isThumb1Only ( ) ) { +} +SDValue Lo = DAG . getNode ( ISD :: EXTRACT_ELEMENT , dl , MVT :: i32 , N -> getOperand ( 0 ) , DAG . getConstant ( 0 , MVT :: i32 ) ) ; +SDValue Hi = DAG . getNode ( ISD :: EXTRACT_ELEMENT , dl , MVT :: i32 , N -> getOperand ( 0 ) , DAG . getConstant ( 1 , MVT :: i32 ) ) ; +unsigned Opc = N -> getOpcode ( ) == ISD :: SRL ? XCoreISD :: SRL_FLAG : XCoreISD :: SRA_FLAG ; +Hi = DAG . getNode ( Opc , dl , DAG . getVTList ( MVT :: i32 , MVT :: Glue ) , Hi ) ; +Lo = DAG . getNode ( XCoreISD :: RRX , dl , MVT :: i32 , Lo , Hi . getValue ( 1 ) ) ; +return DAG . getNode ( ISD :: BUILD_PAIR , dl , MVT :: i64 , Lo , Hi ) ; +EVT VT = V0 . getValueType ( ) ; +assert ( VT . is256BitVector ( ) && VT == V1 . getValueType ( ) && "Invalid nodes in input!" ) ; +unsigned NumElts = VT . getVectorNumElements ( ) ; +SDValue V0_LO = Extract128BitVector ( V0 , 0 , DAG , DL ) ; +SDValue V0_HI = Extract128BitVector ( V0 , NumElts / 2 , DAG , DL ) ; +SDValue V1_LO = Extract128BitVector ( V1 , 0 , DAG , DL ) ; +SDValue V1_HI = Extract128BitVector ( V1 , NumElts / 2 , DAG , DL ) ; +EVT NewVT = V0_LO . getValueType ( ) ; +SDValue LO = DAG . getUNDEF ( NewVT ) ; +SDValue HI = DAG . getUNDEF ( NewVT ) ; +if ( Mode ) { +if ( ! isUndefLO && V0 -> getOpcode ( ) != ISD :: UNDEF ) { +LO = DAG . getNode ( XCoreOpcode , DL , NewVT , V0_LO , V0_HI ) ; +} +if ( ! isUndefHI && V1 -> getOpcode ( ) != ISD :: UNDEF ) { +HI = DAG . getNode ( XCoreOpcode , DL , NewVT , V1_LO , V1_HI ) ; +} +} +else { +if ( ! isUndefLO && ( V0_LO -> getOpcode ( ) != ISD :: UNDEF || V1_LO -> getOpcode ( ) != ISD :: UNDEF ) ) { +LO = DAG . getNode ( XCoreOpcode , DL , NewVT , V0_LO , V1_LO ) ; +} +if ( ! isUndefHI && ( V0_HI -> getOpcode ( ) != ISD :: UNDEF || V1_HI -> getOpcode ( ) != ISD :: UNDEF ) ) { +HI = DAG . getNode ( XCoreOpcode , DL , NewVT , V0_HI , V1_HI ) ; +} +} +return DAG . getNode ( ISD :: CONCAT_VECTORS , DL , VT , LO , HI ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerADJUST_TRAMPOLINE.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerADJUST_TRAMPOLINE.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6fc092d73128d2ee4a2d380f97031a20a4dd93d0 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerADJUST_TRAMPOLINE.cpp @@ -0,0 +1,3 @@ +SDValue XCoreTargetLowering :: LowerADJUST_TRAMPOLINE ( SDValue Op , SelectionDAG & DAG ) const { +return Op . getOperand ( 0 ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerATOMIC_FENCE.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerATOMIC_FENCE.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2a982d70b213c77b6e9c1c5b5bcbfb502ea43ba7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerATOMIC_FENCE.cpp @@ -0,0 +1,4 @@ +SDValue XCoreTargetLowering :: LowerATOMIC_FENCE ( SDValue Op , SelectionDAG & DAG ) const { +DebugLoc dl = Op . getDebugLoc ( ) ; +return DAG . getNode ( XCoreISD::MEMBARRIER , dl , MVT :: Other , Op . getOperand ( 0 ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerBR_JT.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerBR_JT.cpp new file mode 100644 index 0000000000000000000000000000000000000000..40a11377268e0e1381f4c20a0d2940a471643f87 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerBR_JT.cpp @@ -0,0 +1,36 @@ +SDValue XCoreTargetLowering :: LowerBR_JT ( SDValue Op , SelectionDAG & DAG ) const { +SDLoc DL ( Op ) ; +SDValue Chain = Op . getOperand ( 0 ) ; +const auto * JT = cast < JumpTableSDNode > ( Op . getOperand ( 1 ) ) ; +SDValue Table = Op . getOperand ( 1 ) ; +SDValue Index = Op . getOperand ( 2 ) ; +assert ( JT -> getTargetFlags ( ) == 0 && "XCore doesn't set target flags" ) ; +SmallVector < SDValue , 8 > Ops ; +Ops . push_back ( Chain ) ; +Ops . push_back ( Index ) ; +MachineJumpTableInfo * MJTI = DAG . getMachineFunction ( ) . getJumpTableInfo ( ) ; +const auto & MBBs = MJTI -> getJumpTables ( ) [ JT -> getIndex ( ) ] . MBBs ; +for ( auto MBB : MBBs ) { +Ops . push_back ( DAG . getBasicBlock ( MBB ) ) ; +} +Ops . push_back ( DAG . getBasicBlock ( MBBs [ 0 ] ) ) ; +return DAG . getNode ( XCoreISD :: BR_TABLE , DL , MVT :: Other , Ops ) ; +DebugLoc dl = Op . getDebugLoc ( ) ; +JumpTableSDNode * JT = cast < JumpTableSDNode > ( Table ) ; +unsigned JTI = JT -> getIndex ( ) ; +MachineFunction & MF = DAG . getMachineFunction ( ) ; +const MachineJumpTableInfo * MJTI = MF . getJumpTableInfo ( ) ; +SDValue TargetJT = DAG . getTargetJumpTable ( JT -> getIndex ( ) , MVT :: i32 ) ; +const std :: vector < MachineJumpTableEntry > & JTE = MJTI -> getJumpTables ( ) ; +const std :: vector < MachineBasicBlock * > & JTBBs = JTE [ JTI ] . MBBs ; +for ( unsigned i = 0 , e = JTBBs . size ( ) ; i != e ; ++ i ) { +MachineBasicBlock * MBB = JTBBs [ i ] ; +MBB -> setHasAddressTaken ( ) ; +BlockAddress :: get ( const_cast < BasicBlock * > ( MBB -> getBasicBlock ( ) ) ) ; +} +SDValue JumpTableBase = DAG . getNode ( XCoreISD :: WrapperJT , dl , getPointerTy ( ) , TargetJT ) ; +SDValue ShiftIndex = DAG . getNode ( ISD :: SHL , dl , MVT :: i32 , Index , DAG . getConstant ( 2 , MVT :: i32 ) ) ; +SDValue JTAddress = DAG . getNode ( ISD :: ADD , dl , MVT :: i32 , JumpTableBase , ShiftIndex ) ; +SDValue LoadTarget = DAG . getLoad ( MVT :: i32 , dl , Chain , JTAddress , MachinePointerInfo ( ) , false , false , false , 0 ) ; +return DAG . getNode ( XCoreISD :: BR_JT , dl , MVT :: Other , Chain , LoadTarget ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerBlockAddress.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerBlockAddress.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a8439703fe3d368e64028ecebd061434985c1435 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerBlockAddress.cpp @@ -0,0 +1,6 @@ +SDValue XCoreTargetLowering :: LowerBlockAddress ( SDValue Op , SelectionDAG & DAG ) const { +DebugLoc DL = Op . getDebugLoc ( ) ; +const BlockAddress * BA = cast < BlockAddressSDNode > ( Op ) -> getBlockAddress ( ) ; +SDValue Result = DAG . getBlockAddress ( BA , getPointerTy ( ) , true ) ; +return DAG . getNode ( XCoreISD :: PCRelativeWrapper , DL , getPointerTy ( ) , Result ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerCall.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerCall.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c1fa816f21cb4538d222d0dd464f13bcb111b5c7 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerCall.cpp @@ -0,0 +1,348 @@ +SDValue XCoreTargetLowering :: LowerCall ( CallLoweringInfo & CLI , SmallVectorImpl < SDValue > & InVals ) const { +SelectionDAG & DAG = CLI . DAG ; +SDLoc & DL = CLI . DL ; +SmallVectorImpl < ISD :: OutputArg > & Outs = CLI . Outs ; +SmallVectorImpl < SDValue > & OutVals = CLI . OutVals ; +SmallVectorImpl < ISD :: InputArg > & Ins = CLI . Ins ; +DebugLoc & dl = CLI . DL ; +SmallVector < ISD :: OutputArg , 32 > & Outs = CLI . Outs ; +SmallVector < SDValue , 32 > & OutVals = CLI . OutVals ; +SmallVector < ISD :: InputArg , 32 > & Ins = CLI . Ins ; +SDValue Chain = CLI . Chain ; +SDValue Callee = CLI . Callee ; +bool & isTailCall = CLI . IsTailCall ; +CallingConv :: ID CallConv = CLI . CallConv ; +bool isVarArg = CLI . IsVarArg ; +const char * XCore16HelperFunction = 0 ; +bool needXCore16Helper = false ; +if ( Subtarget -> inMips16Mode ( ) ) { +bool lookupHelper = true ; +if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { +if ( noHelperNeeded . find ( S -> getSymbol ( ) ) != noHelperNeeded . end ( ) ) { +lookupHelper = false ; +} +} +if ( lookupHelper ) { +XCore16HelperFunction = getXCore16HelperFunction ( CLI . RetTy , CLI . Args , needXCore16Helper ) ; +} +} +MachineFunction & MF = DAG . getMachineFunction ( ) ; +isTailCall = false ; +MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; +const TargetFrameLowering * TFL = MF . getTarget ( ) . getFrameLowering ( ) ; +bool IsPIC = getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ; +SmallVector < CCValAssign , 16 > ArgLocs ; +CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; +const Function * F = nullptr ; +if ( const GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { +const GlobalValue * GV = G -> getGlobal ( ) ; +F = cast < Function > ( GV ) ; +Callee = DAG . getTargetGlobalAddress ( GV , DL , getPointerTy ( DAG . getDataLayout ( ) ) ) ; +} +if ( const ExternalSymbolSDNode * ES = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { +Callee = DAG . getTargetExternalSymbol ( ES -> getSymbol ( ) , getPointerTy ( DAG . getDataLayout ( ) ) ) ; +} +analyzeArguments ( & CLI , F , & DAG . getDataLayout ( ) , & Outs , 0 , CallConv , ArgLocs , CCInfo , true , isVarArg ) ; +unsigned NumBytes = CCInfo . getNextStackOffset ( ) ; +CCState CCInfo ( CallConv , isVarArg , DAG . getTarget ( ) , ArgLocs , * DAG . getContext ( ) ) ; +CCInfo . AnalyzeCallOperands ( Outs , CC_XCore32 ) ; +unsigned ArgsSize = CCInfo . getNextStackOffset ( ) ; +ArgsSize = ( ArgsSize + 7 ) & ~ 7 ; +MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; +SmallVector < SDValue , 8 > ByValArgs ; +for ( unsigned i = 0 , e = Outs . size ( ) ; i != e ; ++ i ) { +ISD :: ArgFlagsTy Flags = Outs [ i ] . Flags ; +if ( ! Flags . isByVal ( ) ) { +continue ; +} +SDValue Arg = OutVals [ i ] ; +unsigned Size = Flags . getByValSize ( ) ; +unsigned Align = Flags . getByValAlign ( ) ; +int FI = MFI -> CreateStackObject ( Size , Align , false ) ; +SDValue FIPtr = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; +SDValue SizeNode = DAG . getConstant ( Size , MVT :: i32 ) ; +Chain = DAG . getMemcpy ( Chain , dl , FIPtr , Arg , SizeNode , Align , false , ( Size <= 32 ) , MachinePointerInfo ( ) , MachinePointerInfo ( ) ) ; +ByValArgs . push_back ( FIPtr ) ; +} +Chain = DAG . getCALLSEQ_START ( Chain , DAG . getIntPtrConstant ( NumBytes , DL , true ) , DL ) ; +SmallVector < std :: pair < unsigned , SDValue > , 8 > RegsToPass ; +unsigned AI ; +unsigned AE ; +bool HasStackArgs = false ; +CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , ArgLocs , * DAG . getContext ( ) ) ; +XCoreCC XCoreCCInfo ( CallConv , IsO32 , CCInfo ) ; +XCoreCCInfo . analyzeCallOperands ( Outs , isVarArg ) ; +unsigned NextStackOffset = CCInfo . getNextStackOffset ( ) ; +if ( isTailCall ) { +isTailCall = IsEligibleForTailCallOptimization ( XCoreCCInfo , NextStackOffset , * MF . getInfo < XCoreFunctionInfo > ( ) ) ; +} +if ( isTailCall ) { +NumTailCalls = NumTailCalls + 1 ; +} +unsigned StackAlignment = TFL -> getStackAlignment ( ) ; +NextStackOffset = RoundUpToAlignment ( NextStackOffset , StackAlignment ) ; +SDValue NextStackOffsetVal = DAG . getIntPtrConstant ( NextStackOffset , true ) ; +if ( ! isTailCall ) { +Chain = DAG . getCALLSEQ_START ( Chain , NextStackOffsetVal ) ; +} +SDValue StackPtr = DAG . getCopyFromReg ( Chain , dl , IsN64 ? XCore :: SP_64 : XCore :: SP , getPointerTy ( ) ) ; +std :: deque < std :: pair < unsigned , SDValue > > RegsToPass ; +SmallVector < SDValue , 8 > MemOpChains ; +XCoreCC :: byval_iterator ByValArg = XCoreCCInfo . byval_begin ( ) ; +const unsigned StackOffset = 92 ; +bool hasStructRetAttr = false ; +for ( AI = 0 , AE = ArgLocs . size ( ) ; AI != AE ; ++ AI ) { +CCValAssign & VA = ArgLocs [ AI ] ; +EVT RegVT = VA . getLocVT ( ) ; +SDValue Arg = OutVals [ AI ] ; +CCValAssign & VA = ArgLocs [ i ] ; +MVT ValVT = VA . getValVT ( ) , LocVT = VA . getLocVT ( ) ; +if ( Flags . isByVal ( ) ) { +assert ( ! isTailCall && "Do not tail-call optimize if there is a byval argument." ) ; +passByValArg ( Chain , dl , RegsToPass , MemOpChains , StackPtr , MFI , DAG , Arg , XCoreCCInfo , * ByValArg , Flags , Subtarget -> isLittle ( ) ) ; +ByValArg = ByValArg + 1 ; +continue ; +Arg = ByValArgs [ byvalArgIdx ++ ] ; +} +Arg = DAG . getNode ( ISD :: SIGN_EXTEND , DL , RegVT , Arg ) ; +if ( ValVT == MVT :: f32 ) { +if ( LocVT == MVT :: i32 ) { +Arg = DAG . getNode ( ISD :: BITCAST , dl , LocVT , Arg ) ; +} +} +if ( ValVT == MVT :: f64 ) { +if ( LocVT == MVT :: i64 ) { +Arg = DAG . getNode ( ISD :: BITCAST , dl , LocVT , Arg ) ; +} +} +if ( LocVT == MVT :: i32 ) { +if ( ValVT == MVT :: f64 ) { +SDValue Lo = DAG . getNode ( XCoreISD :: ExtractElementF64 , dl , MVT :: i32 , Arg , DAG . getConstant ( 0 , MVT :: i32 ) ) ; +SDValue Hi = DAG . getNode ( XCoreISD :: ExtractElementF64 , dl , MVT :: i32 , Arg , DAG . getConstant ( 1 , MVT :: i32 ) ) ; +std :: swap ( Lo , Hi ) ; +unsigned LocRegLo = VA . getLocReg ( ) ; +unsigned LocRegHigh = getNextIntArgReg ( LocRegLo ) ; +RegsToPass . push_back ( std :: make_pair ( LocRegLo , Lo ) ) ; +RegsToPass . push_back ( std :: make_pair ( LocRegHigh , Hi ) ) ; +continue ; +} +} +Arg = DAG . getNode ( ISD :: ZERO_EXTEND , DL , RegVT , Arg ) ; +Arg = DAG . getNode ( ISD :: ANY_EXTEND , DL , RegVT , Arg ) ; +Arg = DAG . getNode ( ISD :: BITCAST , DL , RegVT , Arg ) ; +if ( VA . isMemLoc ( ) ) { +HasStackArgs = true ; +break ; +} +RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; +if ( Flags . isSRet ( ) ) { +SDValue StackPtr = DAG . getRegister ( XCore :: O6 , MVT :: i32 ) ; +SDValue PtrOff = DAG . getIntPtrConstant ( 64 ) ; +PtrOff = DAG . getNode ( ISD :: ADD , dl , MVT :: i32 , StackPtr , PtrOff ) ; +MemOpChains . push_back ( DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo ( ) , false , false , 0 ) ) ; +hasStructRetAttr = true ; +continue ; +} +if ( VA . needsCustom ( ) ) { +if ( VA . isMemLoc ( ) ) { +unsigned Offset = VA . getLocMemOffset ( ) + StackOffset ; +if ( Offset % 8 == 0 ) { +SDValue StackPtr = DAG . getRegister ( XCore :: O6 , MVT :: i32 ) ; +SDValue PtrOff = DAG . getIntPtrConstant ( Offset ) ; +PtrOff = DAG . getNode ( ISD :: ADD , dl , MVT :: i32 , StackPtr , PtrOff ) ; +MemOpChains . push_back ( DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo ( ) , false , false , 0 ) ) ; +continue ; +} +} +SDValue StackPtr = DAG . CreateStackTemporary ( MVT :: f64 , MVT :: i32 ) ; +SDValue Store = DAG . getStore ( DAG . getEntryNode ( ) , dl , Arg , StackPtr , MachinePointerInfo ( ) , false , false , 0 ) ; +SDValue Hi = DAG . getLoad ( MVT :: i32 , dl , Store , StackPtr , MachinePointerInfo ( ) , false , false , 0 ) ; +StackPtr = DAG . getNode ( ISD :: ADD , dl , StackPtr . getValueType ( ) , StackPtr , DAG . getIntPtrConstant ( 4 ) ) ; +SDValue Lo = DAG . getLoad ( MVT :: i32 , dl , Store , StackPtr , MachinePointerInfo ( ) , false , false , 0 ) ; +if ( VA . isRegLoc ( ) ) { +RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Hi ) ) ; +CCValAssign & NextVA = ArgLocs [ ++ i ] ; +if ( NextVA . isRegLoc ( ) ) { +RegsToPass . push_back ( std :: make_pair ( NextVA . getLocReg ( ) , Lo ) ) ; +} +if ( ! NextVA . isRegLoc ( ) ) { +unsigned Offset = NextVA . getLocMemOffset ( ) + StackOffset ; +SDValue StackPtr = DAG . getRegister ( XCore :: O6 , MVT :: i32 ) ; +SDValue PtrOff = DAG . getIntPtrConstant ( Offset ) ; +PtrOff = DAG . getNode ( ISD :: ADD , dl , MVT :: i32 , StackPtr , PtrOff ) ; +MemOpChains . push_back ( DAG . getStore ( Chain , dl , Lo , PtrOff , MachinePointerInfo ( ) , false , false , 0 ) ) ; +} +} +if ( ! VA . isRegLoc ( ) ) { +unsigned Offset = VA . getLocMemOffset ( ) + StackOffset ; +SDValue StackPtr = DAG . getRegister ( XCore :: O6 , MVT :: i32 ) ; +SDValue PtrOff = DAG . getIntPtrConstant ( Offset ) ; +PtrOff = DAG . getNode ( ISD :: ADD , dl , MVT :: i32 , StackPtr , PtrOff ) ; +MemOpChains . push_back ( DAG . getStore ( Chain , dl , Hi , PtrOff , MachinePointerInfo ( ) , false , false , 0 ) ) ; +PtrOff = DAG . getIntPtrConstant ( Offset + 4 ) ; +PtrOff = DAG . getNode ( ISD :: ADD , dl , MVT :: i32 , StackPtr , PtrOff ) ; +MemOpChains . push_back ( DAG . getStore ( Chain , dl , Lo , PtrOff , MachinePointerInfo ( ) , false , false , 0 ) ) ; +} +continue ; +} +if ( VA . isRegLoc ( ) ) { +if ( VA . getLocVT ( ) != MVT :: f32 ) { +RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; +continue ; +} +Arg = DAG . getNode ( ISD :: BITCAST , dl , MVT :: i32 , Arg ) ; +RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; +continue ; +} +assert ( VA . isMemLoc ( ) ) ; +MemOpChains . push_back ( passArgOnStack ( StackPtr , VA . getLocMemOffset ( ) , Chain , Arg , dl , isTailCall , DAG ) ) ; +SDValue StackPtr = DAG . getRegister ( XCore :: O6 , MVT :: i32 ) ; +SDValue PtrOff = DAG . getIntPtrConstant ( VA . getLocMemOffset ( ) + StackOffset ) ; +PtrOff = DAG . getNode ( ISD :: ADD , dl , MVT :: i32 , StackPtr , PtrOff ) ; +MemOpChains . push_back ( DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo ( ) , false , false , 0 ) ) ; +} +if ( HasStackArgs ) { +for ( AE = AI , AI = ArgLocs . size ( ) ; AI != AE ; -- AI ) { +unsigned Loc = AI - 1 ; +CCValAssign & VA = ArgLocs [ Loc ] ; +SDValue Arg = OutVals [ Loc ] ; +assert ( VA . isMemLoc ( ) ) ; +SDValue PtrOff = DAG . getNode ( ISD :: ADD , DL , getPointerTy ( DAG . getDataLayout ( ) ) , DAG . getRegister ( XCore :: SP , getPointerTy ( DAG . getDataLayout ( ) ) ) , DAG . getIntPtrConstant ( VA . getLocMemOffset ( ) + 1 , DL ) ) ; +Chain = DAG . getStore ( Chain , DL , Arg , PtrOff , MachinePointerInfo :: getStack ( MF , VA . getLocMemOffset ( ) ) , 0 ) ; +} +} +if ( ! MemOpChains . empty ( ) ) { +Chain = DAG . getCopyToReg ( Chain , DL , Reg . first , Reg . second , InFlag ) ; +} +bool IsPICCall = ( IsN64 || IsPIC ) ; +bool GlobalOrExternal = false , InternalLinkage = false ; +SDValue CalleeLo ; +if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { +if ( IsPICCall ) { +InternalLinkage = G -> getGlobal ( ) -> hasInternalLinkage ( ) ; +if ( InternalLinkage ) { +Callee = getAddrLocal ( Callee , DAG , HasXCore64 ) ; +} +if ( LargeGOT ) { +Callee = getAddrGlobalLargeGOT ( Callee , DAG , XCoreII :: MO_CALL_HI16 , XCoreII :: MO_CALL_LO16 ) ; +} +if ( ! InternalLinkage ) { +if ( ! LargeGOT ) { +Callee = getAddrGlobal ( Callee , DAG , XCoreII :: MO_GOT_CALL ) ; +} +} +} +if ( ! IsPICCall ) { +Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , dl , getPointerTy ( ) , 0 , XCoreII :: MO_NO_FLAG ) ; +} +GlobalOrExternal = true ; +} +if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { +if ( ! IsN64 ) { +if ( ! IsPIC ) { +Callee = DAG . getTargetExternalSymbol ( S -> getSymbol ( ) , getPointerTy ( ) , XCoreII :: MO_NO_FLAG ) ; +} +} +if ( LargeGOT ) { +Callee = getAddrGlobalLargeGOT ( Callee , DAG , XCoreII :: MO_CALL_HI16 , XCoreII :: MO_CALL_LO16 ) ; +} +if ( ! LargeGOT ) { +Callee = getAddrGlobal ( Callee , DAG , XCoreII :: MO_GOT_CALL ) ; +} +GlobalOrExternal = true ; +} +SDValue JumpTarget = Callee ; +if ( IsPICCall ) { +unsigned T9Reg = IsN64 ? XCore :: T9_64 : XCore :: T9 ; +unsigned V0Reg = XCore :: V0 ; +if ( needXCore16Helper ) { +RegsToPass . push_front ( std :: make_pair ( V0Reg , Callee ) ) ; +JumpTarget = DAG . getExternalSymbol ( XCore16HelperFunction , getPointerTy ( ) ) ; +JumpTarget = getAddrGlobal ( JumpTarget , DAG , XCoreII :: MO_GOT ) ; +} +if ( ! needXCore16Helper ) { +RegsToPass . push_front ( std :: make_pair ( T9Reg , Callee ) ) ; +JumpTarget = SDValue ( ) ; +} +} +if ( ! GlobalOrExternal ) { +unsigned T9Reg = IsN64 ? XCore :: T9_64 : XCore :: T9 ; +unsigned V0Reg = XCore :: V0 ; +if ( needXCore16Helper ) { +RegsToPass . push_front ( std :: make_pair ( V0Reg , Callee ) ) ; +JumpTarget = DAG . getExternalSymbol ( XCore16HelperFunction , getPointerTy ( ) ) ; +JumpTarget = getAddrGlobal ( JumpTarget , DAG , XCoreII :: MO_GOT ) ; +} +if ( ! needXCore16Helper ) { +RegsToPass . push_front ( std :: make_pair ( T9Reg , Callee ) ) ; +JumpTarget = SDValue ( ) ; +} +} +if ( IsPICCall ) { +if ( ! InternalLinkage ) { +unsigned GPReg = IsN64 ? XCore :: GP_64 : XCore :: GP ; +EVT Ty = IsN64 ? MVT :: i64 : MVT :: i32 ; +RegsToPass . push_back ( std :: make_pair ( GPReg , GetGlobalReg ( DAG , Ty ) ) ) ; +} +} +SDValue InFlag ; +for ( auto Reg : RegsToPass ) { +unsigned Reg = RegsToPass [ i ] . first ; +Reg = Reg - XCore :: I0 + XCore :: O0 ; +Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( NumBytes , DL , true ) , DAG . getIntPtrConstant ( 0 , DL , true ) , InFlag , DL ) ; +InFlag = Chain . getValue ( 1 ) ; +} +unsigned SRetArgSize = ( hasStructRetAttr ) ? getSRetArgSize ( DAG , Callee ) : 0 ; +if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { +Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , dl , MVT :: i32 ) ; +} +if ( ExternalSymbolSDNode * E = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { +Callee = DAG . getTargetExternalSymbol ( E -> getSymbol ( ) , MVT :: i32 ) ; +} +SDVTList NodeTys = DAG . getVTList ( MVT :: Other , MVT :: Glue ) ; +SmallVector < SDValue , 8 > Ops ; +Ops . push_back ( Chain ) ; +Ops . push_back ( Callee ) ; +SmallVector < SDValue , 8 > Ops ( 1 , Chain ) ; +if ( JumpTarget . getNode ( ) ) { +Ops . push_back ( JumpTarget ) ; +} +if ( hasStructRetAttr ) { +Ops . push_back ( DAG . getTargetConstant ( SRetArgSize , MVT :: i32 ) ) ; +} +for ( auto Reg : RegsToPass ) { +Ops . push_back ( DAG . getRegister ( Reg . first , Reg . second . getValueType ( ) ) ) ; +Ops . push_back ( DAG . getRegister ( RegsToPass [ i ] . first , RegsToPass [ i ] . second . getValueType ( ) ) ) ; +unsigned Reg = RegsToPass [ i ] . first ; +Reg = Reg - XCore :: I0 + XCore :: O0 ; +Ops . push_back ( DAG . getRegister ( Reg , RegsToPass [ i ] . second . getValueType ( ) ) ) ; +} +const XCoreTargetMachine & TM = ( const XCoreTargetMachine & ) getTargetMachine ( ) ; +const TargetRegisterInfo * TRI = TM . getSubtargetImpl ( ) -> getRegisterInfo ( ) ; +const uint32_t * Mask = TRI -> getCallPreservedMask ( DAG . getMachineFunction ( ) , CallConv ) ; +assert ( Mask && "Missing call preserved mask for calling convention" ) ; +Ops . push_back ( DAG . getRegisterMask ( Mask ) ) ; +if ( InFlag . getNode ( ) ) { +Ops . push_back ( InFlag ) ; +} +if ( isTailCall ) { +return DAG . getNode ( XCoreISD :: TailCall , dl , MVT :: Other , & Ops [ 0 ] , Ops . size ( ) ) ; +} +Chain = DAG . getNode ( XCoreISD :: CALL , DL , NodeTys , Ops ) ; +InFlag = Chain . getValue ( 1 ) ; +Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( NumBytes , DL , true ) , DAG . getIntPtrConstant ( 0 , DL , true ) , InFlag , DL ) ; +if ( ! Ins . empty ( ) ) { +InFlag = Chain . getValue ( 1 ) ; +} +InFlag = Chain . getValue ( 1 ) ; +SmallVector < CCValAssign , 16 > RVLocs ; +CCState RVInfo ( CallConv , isVarArg , DAG . getTarget ( ) , RVLocs , * DAG . getContext ( ) ) ; +RVInfo . AnalyzeCallResult ( Ins , RetCC_XCore32 ) ; +for ( unsigned i = 0 ; i != RVLocs . size ( ) ; ++ i ) { +unsigned Reg = RVLocs [ i ] . getLocReg ( ) ; +Reg = Reg - XCore :: I0 + XCore :: O0 ; +Chain = DAG . getCopyFromReg ( Chain , dl , Reg , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( 1 ) ; +InFlag = Chain . getValue ( 2 ) ; +InVals . push_back ( Chain . getValue ( 0 ) ) ; +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerConstantPool.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerConstantPool.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a7719f0a042d151083067f45d0e1bd46e77dcf84 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerConstantPool.cpp @@ -0,0 +1,13 @@ +SDValue XCoreTargetLowering :: LowerConstantPool ( SDValue Op , SelectionDAG & DAG ) const { +ConstantPoolSDNode * CP = cast < ConstantPoolSDNode > ( Op ) ; +DebugLoc dl = CP -> getDebugLoc ( ) ; +EVT PtrVT = Op . getValueType ( ) ; +SDValue Res ; +if ( CP -> isMachineConstantPoolEntry ( ) ) { +Res = DAG . getTargetConstantPool ( CP -> getMachineCPVal ( ) , PtrVT , CP -> getAlignment ( ) ) ; +} +else { +Res = DAG . getTargetConstantPool ( CP -> getConstVal ( ) , PtrVT , CP -> getAlignment ( ) ) ; +} +return DAG . getNode ( XCoreISD :: CPRelativeWrapper , dl , MVT :: i32 , Res ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerDYNAMIC_STACKALLOC.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerDYNAMIC_STACKALLOC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..390aa0a658c093b7e00a2b6427fca192b1f5855e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerDYNAMIC_STACKALLOC.cpp @@ -0,0 +1,35 @@ +SDValue XCoreTargetLowering :: LowerDYNAMIC_STACKALLOC ( SDValue Op , SelectionDAG & DAG ) const { +assert ( Subtarget -> isTargetWindows ( ) && "unsupported target platform" ) ; +SDLoc DL ( Op ) ; +SDValue Chain = Op . getOperand ( 0 ) ; +SDValue Size = Op . getOperand ( 1 ) ; +if ( isa < ConstantSDNode > ( Size ) ) { +return lowerDYNAMIC_STACKALLOCImpl ( Op , DAG ) ; +} +return XCoreTargetLowering :: LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; +if ( DAG . getMachineFunction ( ) . getFunction ( ) . hasFnAttribute ( "no-stack-arg-probe" ) ) { +MaybeAlign Align = cast < ConstantSDNode > ( Op . getOperand ( 2 ) ) -> getMaybeAlignValue ( ) ; +SDValue SP = DAG . getCopyFromReg ( Chain , DL , XCore :: SP , MVT :: i32 ) ; +Chain = SP . getValue ( 1 ) ; +SP = DAG . getNode ( ISD :: SUB , DL , MVT :: i32 , SP , Size ) ; +if ( Align ) { +SP = DAG . getNode ( ISD :: AND , DL , MVT :: i32 , SP . getValue ( 0 ) , DAG . getConstant ( - ( uint64_t ) Align -> value ( ) , DL , MVT :: i32 ) ) ; +} +Chain = DAG . getCopyToReg ( Chain , DL , XCore :: SP , SP ) ; +SDValue Ops [ 2 ] = { SP , Chain } ; +} +SDValue Words = DAG . getNode ( ISD :: SRL , DL , MVT :: i32 , Size , DAG . getConstant ( 2 , DL , MVT :: i32 ) ) ; +SDValue Flag ; +Chain = DAG . getCopyToReg ( Chain , DL , XCore :: R4 , Words , Flag ) ; +Flag = Chain . getValue ( 1 ) ; +SDVTList NodeTys = DAG . getVTList ( MVT :: Other , MVT :: Glue ) ; +Chain = DAG . getNode ( XCoreISD :: WIN__CHKSTK , DL , NodeTys , Chain , Flag ) ; +SDValue NewSP = DAG . getCopyFromReg ( Chain , DL , XCore :: SP , MVT :: i32 ) ; +Chain = NewSP . getValue ( 1 ) ; +SDValue Ops [ 2 ] = { NewSP , Chain } ; +SDValue NegSize = DAG . getNode ( ISD :: SUB , dl , PtrVT , DAG . getConstant ( 0 , dl , PtrVT ) , Size ) ; +SDValue FPSIdx = getFramePointerFrameIndex ( DAG ) ; +SDValue Ops [ 3 ] = { Chain , NegSize , FPSIdx } ; +SDVTList VTs = DAG . getVTList ( PtrVT , MVT :: Other ) ; +return DAG . getNode ( XCoreISD :: DYNALLOC , dl , VTs , Ops ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerEH_RETURN.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerEH_RETURN.cpp new file mode 100644 index 0000000000000000000000000000000000000000..5e08d2a8b9d51a96cf7eed551eb62cb6f46a5309 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerEH_RETURN.cpp @@ -0,0 +1,32 @@ +SDValue XCoreTargetLowering :: LowerEH_RETURN ( SDValue Op , SelectionDAG & DAG ) const { +MachineFunction & MF = DAG . getMachineFunction ( ) ; +XCoreMachineFunctionInfo * XCoreFI = MF . getInfo < XCoreMachineFunctionInfo > ( ) ; +XCoreFunctionInfo * XCoreFI = MF . getInfo < XCoreFunctionInfo > ( ) ; +XCoreFI -> setCallsEhReturn ( ) ; +SDValue Chain = Op . getOperand ( 0 ) ; +SDValue Offset = Op . getOperand ( 1 ) ; +SDValue Handler = Op . getOperand ( 2 ) ; +SDLoc dl ( Op ) ; +unsigned OffsetReg = XCore :: R2 ; +unsigned AddrReg = XCore :: R3 ; +unsigned ReturnReg = XCore :: R0 ; +auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; +FuncInfo -> setHasEHReturn ( ) ; +unsigned OffsetReg = XCore :: R28 ; +SDValue StoreAddr = DAG . getNode ( ISD :: ADD , dl , PtrVT , DAG . getRegister ( XCore :: R30 , PtrVT ) , DAG . getIntPtrConstant ( 4 , dl ) ) ; +Chain = DAG . getStore ( Chain , dl , Handler , StoreAddr , MachinePointerInfo ( ) , false , false , 0 ) ; +Chain = DAG . getCopyToReg ( Chain , dl , OffsetReg , Offset ) ; +Chain = DAG . getCopyToReg ( Chain , dl , AddrReg , Handler ) ; +Chain = DAG . getCopyToReg ( Chain , dl , ReturnReg , DAG . getIntPtrConstant ( 0 ) ) ; +return DAG . getNode ( XCoreISD :: EH_RETURN , dl , MVT :: Other , Chain , DAG . getRegister ( OffsetReg , MVT :: i32 ) , DAG . getRegister ( AddrReg , getPointerTy ( ) ) ) ; +unsigned OffsetReg = XCore :: V1 ; +unsigned AddrReg = XCore :: V0 ; +EVT Ty = ABI . IsN64 ( ) ? MVT :: i64 : MVT :: i32 ; +unsigned OffsetReg = ABI . IsN64 ( ) ? XCore :: V1_64 : XCore :: V1 ; +unsigned AddrReg = ABI . IsN64 ( ) ? XCore :: V0_64 : XCore :: V0 ; +Chain = DAG . getCopyToReg ( Chain , dl , OffsetReg , Offset , SDValue ( ) ) ; +Chain = DAG . getCopyToReg ( Chain , dl , AddrReg , Handler , Chain . getValue ( 1 ) ) ; +return DAG . getNode ( XCoreISD :: EH_RETURN , dl , MVT :: Other , Chain , DAG . getRegister ( OffsetReg , MVT :: i32 ) , DAG . getRegister ( AddrReg , getPointerTy ( MF . getDataLayout ( ) ) ) , Chain . getValue ( 1 ) ) ; +return DAG . getNode ( XCoreISD :: EH_RETURN , dl , MVT :: Other , Chain ) ; +return DAG . getNode ( XCoreISD :: EH_RETURN , dl , MVT :: Other , Chain , DAG . getRegister ( OffsetReg , Ty ) , DAG . getRegister ( AddrReg , getPointerTy ( MF . getDataLayout ( ) ) ) , Chain . getValue ( 1 ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerFRAMEADDR.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerFRAMEADDR.cpp new file mode 100644 index 0000000000000000000000000000000000000000..32c2965c0c4e85d429cc949633cc1b851dcaab32 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerFRAMEADDR.cpp @@ -0,0 +1,18 @@ +SDValue XCoreTargetLowering :: lowerFRAMEADDR ( SDValue Op , SelectionDAG & DAG ) const { +const XCoreRegisterInfo & RI = * Subtarget . getRegisterInfo ( ) ; +MachineFunction & MF = DAG . getMachineFunction ( ) ; +MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; +MFI . setFrameAddressIsTaken ( true ) ; +Register FrameReg = RI . getFrameRegister ( MF ) ; +EVT VT = Op . getValueType ( ) ; +SDLoc DL ( Op ) ; +SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , FrameReg , VT ) ; +unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( 0 ) ) -> getZExtValue ( ) ; +for ( ; Depth > 0 ; ) { +int Offset = - ( XLenInBytes * 2 ) ; +SDValue Ptr = DAG . getNode ( ISD :: ADD , DL , VT , FrameAddr , DAG . getIntPtrConstant ( Offset , DL ) ) ; +FrameAddr = DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , Ptr , MachinePointerInfo ( ) ) ; +Depth = Depth - 1 ; +} +return FrameAddr ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerFRAME_TO_ARGS_OFFSET.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerFRAME_TO_ARGS_OFFSET.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fef2f3c7990fd41401982666e55607b73a15cb2f --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerFRAME_TO_ARGS_OFFSET.cpp @@ -0,0 +1,3 @@ +SDValue XCoreTargetLowering :: LowerFRAME_TO_ARGS_OFFSET ( SDValue Op , SelectionDAG & DAG ) const { +return DAG . getIntPtrConstant ( 2 * RegInfo -> getSlotSize ( ) , SDLoc ( Op ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerFormalArguments.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerFormalArguments.cpp new file mode 100644 index 0000000000000000000000000000000000000000..740a359cc7cafd2d4239b277f0167e978b05e110 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerFormalArguments.cpp @@ -0,0 +1,149 @@ +SDValue XCoreTargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < ISD :: InputArg > & Ins , const SDLoc & DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { +if ( CallCConv != CallingConv :: C ) { +if ( CallCConv != CallingConv :: Fast ) { +report_fatal_error ( "Unsupported calling convention" ) ; +} +} +LLVM_DEBUG ( dbgs ( ) << "ISelDAG: Lowering formal arguments\n" ) ; +if ( isVarArg ) { +LLVM_DEBUG ( dbgs ( ) << "ISelDAG: Can't lower variadic arguments\n" ) ; +return SDValue ( ) ; +} +MachineFunction & MF = DAG . getMachineFunction ( ) ; +std :: vector < SDValue > OutChains ; +unsigned ArgsBaseOffset = 176 ; +unsigned ArgsPreserved = 64 ; +XCoreMachineFunctionInfo * FuncInfo = MF . getInfo < XCoreMachineFunctionInfo > ( ) ; +MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; +MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; +SmallVector < CCValAssign , 16 > ArgLocs ; +CCState CCInfo ( CallConv , IsVarArg , MF , ArgLocs , * DAG . getContext ( ) ) ; +CCInfo . AnalyzeFormalArguments ( Ins , CCAssignFnForCall ( CallConv , IsVarArg ) ) ; +CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; +CCInfo . AllocateStack ( ArgsPreserved , Align ( 8 ) ) ; +CCInfo . AnalyzeFormalArguments ( Ins , CC_XCore ) ; +CCState CCInfo ( CallConv , isVarArg , MF , ArgLocs , * DAG . getContext ( ) ) ; +CCInfo . AnalyzeFormalArguments ( Ins , CCAssignFnForCall ( CallConv , isVarArg ) ) ; +Chain = DAG . getNode ( XCoreISD :: ENTRY_FLAG , DL , MVT :: Other , { Chain , DAG . getRegister ( XCore :: a1 , MVT :: i32 ) , DAG . getTargetConstant ( 4 , DL , MVT :: i32 ) } ) ; +CCInfo . AnalyzeFormalArguments ( Ins , getCCAssignFn ( CallConv ) ) ; +if ( MFI . hasVAStart ( ) ) { +FuncInfo -> setVarArgsFrameIndex ( MFI . CreateFixedObject ( 1 , CCInfo . getNextStackOffset ( ) , true ) ) ; +} +SDValue ArgValue ; +for ( unsigned i = 0 , e = ArgLocs . size ( ) ; i != e ; ++ i ) { +CCValAssign & VA = ArgLocs [ i ] ; +SDValue ArgValue ; +bool IsF64OnXCore = VA . getLocVT ( ) == MVT :: i32 && VA . getValVT ( ) == MVT :: f64 ; +if ( IsF64OnXCore ) { +ArgValue = unpack64 ( DAG , Chain , VA , DL ) ; +} +if ( ! IsF64OnXCore ) { +if ( VA . isRegLoc ( ) ) { +ArgValue = unpackFromRegLoc ( Subtarget , DAG , Chain , VA , DL ) ; +} +} +if ( ! IsF64OnXCore ) { +if ( ! VA . isRegLoc ( ) ) { +ArgValue = unpackFromMemLoc ( DAG , Chain , VA , DL ) ; +} +} +InVals . push_back ( ArgValue ) ; +if ( VA . isRegLoc ( ) ) { +unsigned VReg = MF . addLiveIn ( VA . getLocReg ( ) , getRegClassFor ( VA . getLocVT ( ) ) ) ; +SDValue Arg = DAG . getCopyFromReg ( Chain , DL , VReg , VA . getLocVT ( ) ) ; +if ( VA . getValVT ( ) == MVT :: i32 ) { +if ( VA . needsCustom ( ) ) { +Arg = DAG . getNode ( ISD :: SRL , DL , VA . getLocVT ( ) , Arg , DAG . getConstant ( 32 , DL , MVT :: i32 ) ) ; +} +} +if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) { +Arg = DAG . getNode ( ISD :: AssertSext , DL , VA . getLocVT ( ) , Arg , DAG . getValueType ( VA . getValVT ( ) ) ) ; +} +if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) { +Arg = DAG . getNode ( ISD :: AssertZext , DL , VA . getLocVT ( ) , Arg , DAG . getValueType ( VA . getValVT ( ) ) ) ; +} +if ( VA . isExtInLoc ( ) ) { +Arg = DAG . getNode ( ISD :: TRUNCATE , DL , VA . getValVT ( ) , Arg ) ; +} +InVals . push_back ( Arg ) ; +continue ; +} +unsigned Offset = VA . getLocMemOffset ( ) + ArgsBaseOffset ; +unsigned ValSize = VA . getValVT ( ) . getSizeInBits ( ) / 8 ; +int FI = MF . getFrameInfo ( ) . CreateFixedObject ( ValSize , Offset , true ) ; +InVals . push_back ( DAG . getLoad ( VA . getValVT ( ) , DL , Chain , DAG . getFrameIndex ( FI , getPointerTy ( MF . getDataLayout ( ) ) ) , MachinePointerInfo :: getFixedStack ( MF , FI ) ) ) ; +if ( VA . isRegLoc ( ) ) { +EVT RegVT = VA . getLocVT ( ) ; +const TargetRegisterClass * RC ; +if ( RegVT == MVT :: i32 ) { +RC = & XCore :: GPRRegClass ; +} +if ( RegVT == MVT :: f32 ) { +RC = & XCore :: FPRRegClass ; +} +unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ; +SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , RegVT ) ; +if ( VA . getLocInfo ( ) == CCValAssign :: Full ) { +InVals . push_back ( ArgValue ) ; +} +if ( VA . getLocInfo ( ) == CCValAssign :: BCvt ) { +ArgValue = DAG . getNode ( ISD :: BITCAST , DL , VA . getValVT ( ) , ArgValue ) ; +InVals . push_back ( ArgValue ) ; +} +} +SDValue Val = DAG . getLoad ( VA . getLocInfo ( ) == CCValAssign :: AExt ? VA . getValVT ( ) : VA . getLocVT ( ) , DL , Chain , DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) ) ; +if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) { +MFI . setObjectZExt ( FI , true ) ; +Val = DAG . getNode ( ISD :: AssertZext , DL , VA . getLocVT ( ) , Val , DAG . getValueType ( VA . getValVT ( ) ) ) ; +} +if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) { +MFI . setObjectSExt ( FI , true ) ; +Val = DAG . getNode ( ISD :: AssertSext , DL , VA . getLocVT ( ) , Val , DAG . getValueType ( VA . getValVT ( ) ) ) ; +} +InVals . push_back ( DAG . getNode ( ISD :: TRUNCATE , DL , VA . getValVT ( ) , Val ) ) ; +} +if ( IsVarArg ) { +const unsigned XLenInBytes = 4 ; +const MVT XLenVT = MVT :: i32 ; +ArrayRef < MCPhysReg > ArgRegs = makeArrayRef ( GPRArgRegs ) ; +unsigned Idx = CCInfo . getFirstUnallocated ( ArgRegs ) ; +const TargetRegisterClass * RC = & XCore :: GPRRegClass ; +MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; +MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; +XCoreMachineFunctionInfo * XCoreFI = MF . getInfo < XCoreMachineFunctionInfo > ( ) ; +int VaArgOffset ; +int VarArgsSaveSize ; +if ( ArgRegs . size ( ) == Idx ) { +VaArgOffset = CCInfo . getNextStackOffset ( ) ; +VarArgsSaveSize = 0 ; +} +if ( ArgRegs . size ( ) != Idx ) { +VarArgsSaveSize = XLenInBytes * ( ArgRegs . size ( ) - Idx ) ; +VaArgOffset = - VarArgsSaveSize ; +} +int FI = MFI . CreateFixedObject ( XLenInBytes , VaArgOffset , true ) ; +XCoreFI -> setVarArgsFrameIndex ( FI ) ; +for ( unsigned i = Idx ; i < ArgRegs . size ( ) ; ++ i , VaArgOffset += XLenInBytes ) { +const Register Reg = RegInfo . createVirtualRegister ( RC ) ; +RegInfo . addLiveIn ( ArgRegs [ i ] , Reg ) ; +SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , XLenVT ) ; +FI = MFI . CreateFixedObject ( XLenInBytes , VaArgOffset , true ) ; +SDValue PtrOff = DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) ; +SDValue Store = DAG . getStore ( Chain , DL , ArgValue , PtrOff , MachinePointerInfo :: getFixedStack ( MF , FI ) ) ; +cast < StoreSDNode > ( Store . getNode ( ) ) -> getMemOperand ( ) -> setValue ( ( Value * ) nullptr ) ; +OutChains . push_back ( Store ) ; +} +XCoreFI -> setVarArgsSaveSize ( VarArgsSaveSize ) ; +} +if ( ! OutChains . empty ( ) ) { +OutChains . push_back ( Chain ) ; +Chain = DAG . getNode ( ISD :: TokenFactor , DL , MVT :: Other , OutChains ) ; +} +if ( ! IsVarArg ) { +return Chain ; +} +unsigned ArgOffset = ArgLocs . size ( ) * 8 ; +XCoreMachineFunctionInfo * FuncInfo = MF . getInfo < XCoreMachineFunctionInfo > ( ) ; +FuncInfo -> setVarArgsFrameOffset ( ArgOffset + ArgsBaseOffset ) ; +return Chain ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerGlobalAddress.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerGlobalAddress.cpp new file mode 100644 index 0000000000000000000000000000000000000000..852118b282f4e0062a03221a3bb226d0633b1db8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerGlobalAddress.cpp @@ -0,0 +1,13 @@ +SDValue XCoreTargetLowering :: lowerGlobalAddress ( SDValue Op , SelectionDAG & DAG ) const { +SDLoc DL ( Op ) ; +EVT Ty = Op . getValueType ( ) ; +GlobalAddressSDNode * N = cast < GlobalAddressSDNode > ( Op ) ; +int64_t Offset = N -> getOffset ( ) ; +const GlobalValue * GV = N -> getGlobal ( ) ; +bool IsLocal = getTargetMachine ( ) . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ; +SDValue Addr = getAddr ( N , DAG , IsLocal ) ; +if ( Offset ) { +return DAG . getNode ( ISD :: ADD , DL , Ty , Addr , DAG . getConstant ( Offset , DL , XLenVT ) ) ; +} +return Addr ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerGlobalTLSAddress.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerGlobalTLSAddress.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c53fb82fee7a461966462b332d010f3341876191 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerGlobalTLSAddress.cpp @@ -0,0 +1,9 @@ +SDValue XCoreTargetLowering :: lowerGlobalTLSAddress ( SDValue Op , SelectionDAG & DAG ) const { +if ( DAG . getTarget ( ) . useEmulatedTLS ( ) ) { +} +SDLoc DL ( Op ) ; +SDValue Offset ; +SDValue Addr ; +MFI -> incNumLocalDynamicTLSAccesses ( ) ; +return Addr ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerINIT_TRAMPOLINE.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerINIT_TRAMPOLINE.cpp new file mode 100644 index 0000000000000000000000000000000000000000..74a89b469327a0f8a3fd5cf8488a08f0efdf3b2c --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerINIT_TRAMPOLINE.cpp @@ -0,0 +1,22 @@ +SDValue XCoreTargetLowering :: LowerINIT_TRAMPOLINE ( SDValue Op , SelectionDAG & DAG ) const { +SDValue Chain = Op . getOperand ( 0 ) ; +SDValue Trmp = Op . getOperand ( 1 ) ; +SDValue FPtr = Op . getOperand ( 2 ) ; +SDValue Nest = Op . getOperand ( 3 ) ; +SDLoc dl ( Op ) ; +bool isPPC64 = ( PtrVT == MVT :: i64 ) ; +Type * IntPtrTy = DAG . getTargetLoweringInfo ( ) . getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; +TargetLowering :: ArgListTy Args ; +TargetLowering :: ArgListEntry Entry ; +Entry . Ty = IntPtrTy ; +Entry . Node = Trmp ; +Args . push_back ( Entry ) ; +Entry . Node = DAG . getConstant ( isPPC64 ? 48 : 40 , isPPC64 ? MVT :: i64 : MVT :: i32 ) ; +Args . push_back ( Entry ) ; +Entry . Node = FPtr ; +Args . push_back ( Entry ) ; +Entry . Node = Nest ; +Args . push_back ( Entry ) ; +std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( CLI ) ; +return CallResult . second ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerINTRINSIC_WO_CHAIN.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerINTRINSIC_WO_CHAIN.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8c114af20b5a36676b410b348c9c0e1befcf4b65 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerINTRINSIC_WO_CHAIN.cpp @@ -0,0 +1,27 @@ +SDValue XCoreTargetLowering :: LowerINTRINSIC_WO_CHAIN ( SDValue Op , SelectionDAG & DAG ) const { +MVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; +unsigned IntNo = cast < ConstantSDNode > ( Op . getOperand ( 0 ) ) -> getZExtValue ( ) ; +DebugLoc DL = Op . getDebugLoc ( ) ; +return DAG . getNode ( XCoreISD :: THREAD_POINTER , DL , PtrVT ) ; +SDLoc DL ( Op ) ; +return DAG . getNode ( XCoreISD :: EH_SJLJ_SETJMP , DL , MVT :: i32 , Op . getOperand ( 1 ) ) ; +return DAG . getRegister ( XCore :: G7 , PtrVT ) ; +SmallVector < SDValue , 16 > Ops ( std :: next ( Op -> op_begin ( ) ) , Op -> op_end ( ) ) ; +Ops . push_back ( DAG . getConstant ( Size , DL , MVT :: i257 , SmallTuple ) ) ; +MachineFunction & MF = DAG . getMachineFunction ( ) ; +MVT VT = Op . getSimpleValueType ( ) ; +const XCoreTargetMachine * TM = static_cast < const XCoreTargetMachine * > ( & DAG . getTarget ( ) ) ; +TM -> getStrList ( ) -> push_back ( std :: string ( ( Twine ( "GCC_except_table" ) + Twine ( MF . getFunctionNumber ( ) ) ) . str ( ) ) ) ; +SDValue Addr = DAG . getTargetExternalSymbol ( TM -> getStrList ( ) -> back ( ) . c_str ( ) , VT , 0 ) ; +if ( isPositionIndependent ( ) ) { +Addr = makeHiLoPair ( Addr , XCoreMCExpr :: VK_XCore_GOTOFF_HI32 , XCoreMCExpr :: VK_XCore_GOTOFF_LO32 , DAG ) ; +SDValue GlobalBase = DAG . getNode ( XCoreISD :: GLOBAL_BASE_REG , DL , VT ) ; +} +EVT VT = Op . getValueType ( ) ; +const XCoreTargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; +MVT PtrVT = TLI . getPointerTy ( DAG . getDataLayout ( ) ) ; +auto & Context = MF . getMMI ( ) . getContext ( ) ; +MCSymbol * S = Context . getOrCreateSymbol ( Twine ( "GCC_except_table" ) + Twine ( MF . getFunctionNumber ( ) ) ) ; +return DAG . getNode ( XCoreISD :: Wrapper , DL , VT , DAG . getMCSymbol ( S , PtrVT ) ) ; +return SDValue ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerLOAD.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerLOAD.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7b890e1021e91b8f2db6f900bf971b94653bb82a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerLOAD.cpp @@ -0,0 +1,35 @@ +SDValue XCoreTargetLowering :: LowerLOAD ( SDValue Op , SelectionDAG & DAG ) const { +SDLoc dl ( Op ) ; +StoreSDNode * StoreNode = cast < StoreSDNode > ( Op ) ; +assert ( StoreNode && "Can only custom lower store nodes" ) ; +SDValue Value = StoreNode -> getValue ( ) ; +EVT VT = Value . getValueType ( ) ; +EVT MemVT = StoreNode -> getMemoryVT ( ) ; +assert ( VT . isVector ( ) && "Can only custom lower vector store types" ) ; +unsigned AS = StoreNode -> getAddressSpace ( ) ; +unsigned Align = StoreNode -> getAlignment ( ) ; +if ( Align < MemVT . getStoreSize ( ) && ! allowsMisalignedMemoryAccesses ( MemVT , AS , Align , StoreNode -> getMemOperand ( ) -> getFlags ( ) , nullptr ) ) { +return scalarizeVectorStore ( StoreNode , DAG ) ; +} +if ( StoreNode -> isTruncatingStore ( ) ) { +return LowerTruncateVectorStore ( Dl , StoreNode , VT , MemVT , DAG ) ; +} +EVT VT = StoreNode -> getMemoryVT ( ) ; +if ( VT == MVT :: i1 ) { +return LowerSTOREi1 ( Op , DAG ) ; +} +if ( VT == MVT :: v2f16 && ! allowsMemoryAccess ( * DAG . getContext ( ) , DAG . getDataLayout ( ) , VT , StoreNode -> getAddressSpace ( ) , StoreNode -> getAlignment ( ) ) ) { +return expandUnalignedStore ( Store , DAG ) ; +} +if ( VT . isVector ( ) ) { +return LowerSTOREVector ( Op , DAG ) ; +} +if ( MemVT == MVT :: f128 ) { +return LowerF128Store ( Op , DAG ) ; +} +if ( MemVT == MVT :: i64 ) { +SDValue Val = DAG . getNode ( ISD :: BITCAST , dl , MVT :: v2i32 , StoreNode -> getValue ( ) ) ; +SDValue Chain = DAG . getStore ( StoreNode -> getChain ( ) , dl , Val , StoreNode -> getBasePtr ( ) , StoreNode -> getPointerInfo ( ) , StoreNode -> getAlignment ( ) , StoreNode -> getMemOperand ( ) -> getFlags ( ) , StoreNode -> getAAInfo ( ) ) ; +} +return SDValue ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerOperation.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerOperation.cpp new file mode 100644 index 0000000000000000000000000000000000000000..100cc6d313c3987ad9541075e5ac18a1a2eb5258 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerOperation.cpp @@ -0,0 +1,3 @@ +SDValue XCoreTargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { +report_fatal_error ( "unimplemented operand" ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerRETURNADDR.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerRETURNADDR.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6cc5fd48ab4e865959bd051d75abd8b25801c605 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerRETURNADDR.cpp @@ -0,0 +1,19 @@ +SDValue XCoreTargetLowering :: lowerRETURNADDR ( SDValue Op , SelectionDAG & DAG ) const { +const XCoreRegisterInfo & RI = * Subtarget . getRegisterInfo ( ) ; +MachineFunction & MF = DAG . getMachineFunction ( ) ; +MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; +MFI . setReturnAddressIsTaken ( true ) ; +if ( verifyReturnAddressArgumentIsConstant ( Op , DAG ) ) { +return SDValue ( ) ; +} +EVT VT = Op . getValueType ( ) ; +SDLoc DL ( Op ) ; +unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( 0 ) ) -> getZExtValue ( ) ; +if ( Depth ) { +int Off = - XLenInBytes ; +SDValue FrameAddr = lowerFRAMEADDR ( Op , DAG ) ; +SDValue Offset = DAG . getConstant ( Off , DL , VT ) ; +return DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , DAG . getNode ( ISD :: ADD , DL , VT , FrameAddr , Offset ) , MachinePointerInfo ( ) ) ; +} +return DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , Reg , XLenVT ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerReturn.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerReturn.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b46e7f2904872beff028810a63f56cf215e9d6ea --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerReturn.cpp @@ -0,0 +1,40 @@ +SDValue XCoreTargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < ISD :: OutputArg > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SDLoc & dl , SelectionDAG & DAG ) const { +auto * AFI = DAG . getMachineFunction ( ) . getInfo < XCoreFunctionInfo > ( ) ; +MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; +SmallVector < CCValAssign , 16 > RVLocs ; +CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; +if ( ! IsVarArg ) { +CCInfo . AllocateStack ( AFI -> getReturnStackOffset ( ) , 4 ) ; +} +CCInfo . AnalyzeReturn ( Outs , RetCC_XCore ) ; +SDValue Flag ; +SmallVector < SDValue , 12 > MemOpChains ; +for ( unsigned i = 0 , e = RVLocs . size ( ) ; i != e ; ++ i ) { +CCValAssign & VA = RVLocs [ i ] ; +if ( VA . isRegLoc ( ) ) { +continue ; +} +assert ( VA . isMemLoc ( ) ) ; +report_fatal_error ( "Can't return value from vararg function in memory" ) ; +} +int Offset = VA . getLocMemOffset ( ) ; +unsigned ObjSize = VA . getLocVT ( ) . getStoreSize ( ) / 8 ; +int FI = MFI -> CreateFixedObject ( ObjSize , Offset , false ) ; +SDValue FIN = DAG . getFrameIndex ( FI , MVT :: i32 ) ; +MemOpChains . push_back ( DAG . getStore ( Chain , dl , OutVals [ i ] , FIN , MachinePointerInfo :: getFixedStack ( FI ) , false , false , 0 ) ) ; +} +if ( ! MemOpChains . empty ( ) ) { +Chain = DAG . getNode ( ISD :: TokenFactor , dl , MVT :: Other , & MemOpChains [ 0 ] , MemOpChains . size ( ) ) ; +} +for ( unsigned i = 0 , e = RVLocs . size ( ) ; i != e ; ++ i ) { +CCValAssign & VA = RVLocs [ i ] ; +if ( ! VA . isRegLoc ( ) ) { +continue ; +} +Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; +Flag = Chain . getValue ( 1 ) ; +} +RetOps [ 0 ] = Chain ; +if ( Flag . getNode ( ) ) { +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerSELECT_CC.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerSELECT_CC.cpp new file mode 100644 index 0000000000000000000000000000000000000000..56326d00cd66b0f0e976f95bc11c011c6bf8b665 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerSELECT_CC.cpp @@ -0,0 +1,5 @@ +SDValue XCoreTargetLowering :: LowerSELECT_CC ( SDValue Op , SelectionDAG & DAG ) const { +DebugLoc dl = Op . getDebugLoc ( ) ; +SDValue Cond = DAG . getNode ( ISD :: SETCC , dl , MVT :: i32 , Op . getOperand ( 2 ) , Op . getOperand ( 3 ) , Op . getOperand ( 4 ) ) ; +return DAG . getNode ( ISD :: SELECT , dl , MVT :: i32 , Cond , Op . getOperand ( 0 ) , Op . getOperand ( 1 ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerSMUL_LOHI.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerSMUL_LOHI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..60807f16b06e0880ac28159e4c517095e8255fb4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerSMUL_LOHI.cpp @@ -0,0 +1,24 @@ +SDValue XCoreTargetLowering :: LowerSMUL_LOHI ( SDValue Op , SelectionDAG & DAG ) const { +EVT VT = Op . getValueType ( ) ; +SDLoc DL ( Op ) ; +SDValue Ops [ 2 ] ; +if ( is32Bit ( VT ) ) { +lowerMUL_LOHI32 ( DAG , DL , ISD :: SIGN_EXTEND , Op . getOperand ( 0 ) , Op . getOperand ( 1 ) , Ops [ 1 ] , Ops [ 0 ] ) ; +} +else if ( Subtarget . hasMiscellaneousExtensions2 ( ) ) { +lowerGR128Binary ( DAG , DL , VT , XCoreISD :: SMUL_LOHI , Op . getOperand ( 0 ) , Op . getOperand ( 1 ) , Ops [ 1 ] , Ops [ 0 ] ) ; +} +else { +SDValue C63 = DAG . getConstant ( 63 , DL , MVT :: i64 ) ; +SDValue LL = Op . getOperand ( 0 ) ; +SDValue RL = Op . getOperand ( 1 ) ; +SDValue LH = DAG . getNode ( ISD :: SRA , DL , VT , LL , C63 ) ; +SDValue RH = DAG . getNode ( ISD :: SRA , DL , VT , RL , C63 ) ; +lowerGR128Binary ( DAG , DL , VT , XCoreISD :: UMUL_LOHI , LL , RL , Ops [ 1 ] , Ops [ 0 ] ) ; +SDValue NegLLTimesRH = DAG . getNode ( ISD :: AND , DL , VT , LL , RH ) ; +SDValue NegLHTimesRL = DAG . getNode ( ISD :: AND , DL , VT , LH , RL ) ; +SDValue NegSum = DAG . getNode ( ISD :: ADD , DL , VT , NegLLTimesRH , NegLHTimesRL ) ; +Ops [ 1 ] = DAG . getNode ( ISD :: SUB , DL , VT , Ops [ 1 ] , NegSum ) ; +} +return DAG . getMergeValues ( Ops , DL ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerSTACKSAVE.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerSTACKSAVE.cpp new file mode 100644 index 0000000000000000000000000000000000000000..f5cb74c17dcdb18da089f3efe9371c427ee72385 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerSTACKSAVE.cpp @@ -0,0 +1,5 @@ +SDValue XCoreTargetLowering :: LowerSTACKSAVE ( SDValue Op , SelectionDAG & DAG ) const { +MachineFunction & MF = DAG . getMachineFunction ( ) ; +MF . getInfo < XCoreMachineFunctionInfo > ( ) -> setManipulatesSP ( true ) ; +return DAG . getCopyFromReg ( Op . getOperand ( 0 ) , SDLoc ( Op ) , XCore :: R15D , Op . getValueType ( ) ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerSTORE.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerSTORE.cpp new file mode 100644 index 0000000000000000000000000000000000000000..39e961cb5b3c120f02cfea8c58fca537f5300fbd --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerSTORE.cpp @@ -0,0 +1,35 @@ +SDValue XCoreTargetLowering :: LowerSTORE ( SDValue Op , SelectionDAG & DAG ) const { +SDLoc dl ( Op ) ; +StoreSDNode * StoreNode = cast < StoreSDNode > ( Op ) ; +assert ( StoreNode && "Can only custom lower store nodes" ) ; +SDValue Value = StoreNode -> getValue ( ) ; +EVT VT = Value . getValueType ( ) ; +EVT MemVT = StoreNode -> getMemoryVT ( ) ; +assert ( VT . isVector ( ) && "Can only custom lower vector store types" ) ; +unsigned AS = StoreNode -> getAddressSpace ( ) ; +unsigned Align = StoreNode -> getAlignment ( ) ; +if ( Align < MemVT . getStoreSize ( ) && ! allowsMisalignedMemoryAccesses ( MemVT , AS , Align , StoreNode -> getMemOperand ( ) -> getFlags ( ) , nullptr ) ) { +return scalarizeVectorStore ( StoreNode , DAG ) ; +} +if ( StoreNode -> isTruncatingStore ( ) ) { +return LowerTruncateVectorStore ( Dl , StoreNode , VT , MemVT , DAG ) ; +} +EVT VT = StoreNode -> getMemoryVT ( ) ; +if ( VT == MVT :: i1 ) { +return LowerSTOREi1 ( Op , DAG ) ; +} +if ( VT == MVT :: v2f16 && ! allowsMemoryAccess ( * DAG . getContext ( ) , DAG . getDataLayout ( ) , VT , StoreNode -> getAddressSpace ( ) , StoreNode -> getAlignment ( ) ) ) { +return expandUnalignedStore ( Store , DAG ) ; +} +if ( VT . isVector ( ) ) { +return LowerSTOREVector ( Op , DAG ) ; +} +if ( MemVT == MVT :: f128 ) { +return LowerF128Store ( Op , DAG ) ; +} +if ( MemVT == MVT :: i64 ) { +SDValue Val = DAG . getNode ( ISD :: BITCAST , dl , MVT :: v2i32 , StoreNode -> getValue ( ) ) ; +SDValue Chain = DAG . getStore ( StoreNode -> getChain ( ) , dl , Val , StoreNode -> getBasePtr ( ) , StoreNode -> getPointerInfo ( ) , StoreNode -> getAlignment ( ) , StoreNode -> getMemOperand ( ) -> getFlags ( ) , StoreNode -> getAAInfo ( ) ) ; +} +return SDValue ( ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerUMUL_LOHI.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerUMUL_LOHI.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9da77e1c2a6ead9df613a6f9d92d8b6be5007aa2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerUMUL_LOHI.cpp @@ -0,0 +1,12 @@ +SDValue XCoreTargetLowering :: LowerUMUL_LOHI ( SDValue Op , SelectionDAG & DAG ) const { +EVT VT = Op . getValueType ( ) ; +SDLoc DL ( Op ) ; +SDValue Ops [ 2 ] ; +if ( is32Bit ( VT ) ) { +lowerMUL_LOHI32 ( DAG , DL , ISD :: ZERO_EXTEND , Op . getOperand ( 0 ) , Op . getOperand ( 1 ) , Ops [ 1 ] , Ops [ 0 ] ) ; +} +else { +lowerGR128Binary ( DAG , DL , VT , XCoreISD :: UMUL_LOHI , Op . getOperand ( 0 ) , Op . getOperand ( 1 ) , Ops [ 1 ] , Ops [ 0 ] ) ; +} +return DAG . getMergeValues ( Ops , DL ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerVAARG.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerVAARG.cpp new file mode 100644 index 0000000000000000000000000000000000000000..391509a77236693cf5d4f3418832b72c4c5686ab --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerVAARG.cpp @@ -0,0 +1,13 @@ +SDValue XCoreTargetLowering :: LowerVAARG ( SDValue Op , SelectionDAG & DAG ) const { +llvm_unreachable ( "unimplemented" ) ; +SDNode * Node = Op . getNode ( ) ; +EVT VT = Node -> getValueType ( 0 ) ; +SDValue InChain = Node -> getOperand ( 0 ) ; +SDValue VAListPtr = Node -> getOperand ( 1 ) ; +const Value * SV = cast < SrcValueSDNode > ( Node -> getOperand ( 2 ) ) -> getValue ( ) ; +DebugLoc DL = Node -> getDebugLoc ( ) ; +SDValue VAList = DAG . getLoad ( getPointerTy ( ) , DL , InChain , VAListPtr , MachinePointerInfo ( SV ) , false , false , 0 ) ; +SDValue NextPtr = DAG . getNode ( ISD :: ADD , DL , getPointerTy ( ) , VAList , DAG . getIntPtrConstant ( VT . getSizeInBits ( ) , getPointerTy ( ) ) ) ; +NextPtr = DAG . getStore ( VAList . getValue ( 1 ) , DL , NextPtr , VAListPtr , MachinePointerInfo ( SV ) , false , false , 0 ) ; +return DAG . getLoad ( VT , DL , InChain , VAList , MachinePointerInfo ( ) , false , false , 0 ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerVASTART.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerVASTART.cpp new file mode 100644 index 0000000000000000000000000000000000000000..25175128ece3327adc4cccc4c533f58b679e79e1 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/LowerVASTART.cpp @@ -0,0 +1,7 @@ +SDValue XCoreTargetLowering :: LowerVASTART ( SDValue Op , SelectionDAG & DAG ) const { +MachineFunction & MF = DAG . getMachineFunction ( ) ; +XCoreFunctionInfo * FuncInfo = MF . getInfo < XCoreFunctionInfo > ( ) ; +DebugLoc dl = Op . getDebugLoc ( ) ; +SDValue FR = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , MVT :: i32 ) ; +return DAG . getStore ( Op . getOperand ( 0 ) , dl , FR , Op . getOperand ( 1 ) , MachinePointerInfo ( ) , false , false , 0 ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/NodeType.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/NodeType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9a1ee15c8b3b2429e290055b06727738ecfdd0e4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/NodeType.cpp @@ -0,0 +1,30 @@ +enum NodeType { + FIRST_NUMBER = ISD::BUILTIN_OP_END, + BL, + PCRelativeWrapper, + DPRelativeWrapper, + CPRelativeWrapper, + ABS16Wrapper, + LDWSP, + STWSP, + RETSP, + OUTPW, + INPW, + LADD, + LSUB, + LMUL, + MACCU, + MACCS, + BR_JT, + BR_JT32, + FRAME_TO_ARGS_OFFSET, + EH_RETURN, + MEMBARRIER, + RETURN_REG_HOLDER, + STACKSAVE, + STACKRESTORE, + STACKUP, + STACKDOWN, + ALLOCA, + LOOPMARKER +}; diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/PerformDAGCombine.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/PerformDAGCombine.cpp new file mode 100644 index 0000000000000000000000000000000000000000..597c1ae775c31e9f33af30658fb40cb161b1c55e --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/PerformDAGCombine.cpp @@ -0,0 +1,5 @@ +SDValue XCoreTargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { +SDValue Val ; +if ( Val . getNode ( ) ) { +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/ReplaceNodeResults.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/ReplaceNodeResults.cpp new file mode 100644 index 0000000000000000000000000000000000000000..56b3b1e6b9b0fe74f417152018ceede1d8d3fdf6 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/ReplaceNodeResults.cpp @@ -0,0 +1,225 @@ +void XCoreTargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { +SDValue Res ; +if ( N -> getOpcode ( ) == ISD :: STRICT_FP_TO_SINT ) { +ExpandREAD_REGISTER ( N , Results , DAG ) ; +if ( Res . getNode ( ) ) { +Results . push_back ( Res ) ; +} +return ; +} +if ( N -> getOpcode ( ) == ISD :: STRICT_FP_TO_UINT ) { +Res = ExpandBITCAST ( N , DAG , Subtarget ) ; +if ( Res . getNode ( ) ) { +Results . push_back ( Res ) ; +} +return ; +} +if ( N -> getOpcode ( ) == ISD :: FP_TO_SINT ) { +ReplaceBITCASTResults ( N , Results , DAG ) ; +if ( Res . getNode ( ) ) { +Results . push_back ( Res ) ; +} +return ; +} +if ( N -> getOpcode ( ) == ISD :: FP_TO_UINT ) { +Results . push_back ( LowerVECREDUCE ( SDValue ( N , 0 ) , DAG ) ) ; +if ( Res . getNode ( ) ) { +Results . push_back ( Res ) ; +} +return ; +} +if ( N -> getOpcode ( ) == ISD :: READCYCLECOUNTER ) { +Results . push_back ( LowerVECREDUCE ( SDValue ( N , 0 ) , DAG ) ) ; +if ( Res . getNode ( ) ) { +Results . push_back ( Res ) ; +} +return ; +} +if ( N -> getOpcode ( ) == ISD :: ADD ) { +Results . push_back ( LowerVECREDUCE ( SDValue ( N , 0 ) , DAG ) ) ; +Res = LowerREM ( N , DAG ) ; +if ( Res . getNode ( ) ) { +Results . push_back ( Res ) ; +} +return ; +} +if ( N -> getOpcode ( ) == ISD :: SUB ) { +Results . push_back ( LowerVECREDUCE ( SDValue ( N , 0 ) , DAG ) ) ; +Res = LowerREM ( N , DAG ) ; +if ( Res . getNode ( ) ) { +Results . push_back ( Res ) ; +} +return ; +} +if ( N -> getOpcode ( ) == ISD :: FSHL ) { +Results . push_back ( LowerVECREDUCE ( SDValue ( N , 0 ) , DAG ) ) ; +Res = LowerDivRem ( SDValue ( N , 0 ) , DAG ) ; +Results . push_back ( Res . getValue ( 0 ) ) ; +Results . push_back ( Res . getValue ( 1 ) ) ; +return ; +} +if ( N -> getOpcode ( ) == ISD :: MUL ) { +Results . push_back ( LowerCTPOP ( SDValue ( N , 0 ) , DAG ) ) ; +Res = LowerDivRem ( SDValue ( N , 0 ) , DAG ) ; +Results . push_back ( Res . getValue ( 0 ) ) ; +Results . push_back ( Res . getValue ( 1 ) ) ; +return ; +} +if ( N -> getOpcode ( ) == ISD :: SHL ) { +ReplaceReductionResults ( N , Results , DAG , ISD :: ADD , XCoreISD :: SADDV ) ; +Res = LowerSADDSUBSAT ( SDValue ( N , 0 ) , DAG , Subtarget ) ; +if ( Res . getNode ( ) ) { +Results . push_back ( Res ) ; +} +return ; +} +if ( N -> getOpcode ( ) == ISD :: SRA ) { +ReplaceReductionResults ( N , Results , DAG , ISD :: ADD , XCoreISD :: UADDV ) ; +Res = LowerSADDSUBSAT ( SDValue ( N , 0 ) , DAG , Subtarget ) ; +if ( Res . getNode ( ) ) { +Results . push_back ( Res ) ; +} +return ; +} +if ( N -> getOpcode ( ) == ISD :: SRL ) { +ReplaceReductionResults ( N , Results , DAG , ISD :: SMIN , XCoreISD :: SMINVV ) ; +ReplaceREADCYCLECOUNTER ( N , Results , DAG , Subtarget ) ; +if ( Res . getNode ( ) ) { +Results . push_back ( Res ) ; +} +return ; +} +if ( N -> getOpcode ( ) == ISD :: ROTL ) { +ReplaceReductionResults ( N , Results , DAG , ISD :: UMINV , XCoreISD :: UMINV ) ; +return ; +return ExpandDIV_Windows ( SDValue ( N , 0 ) , DAG , N -> getOpcode ( ) == ISD :: SDIV , Results ) ; +} +if ( N -> getOpcode ( ) == ISD :: ROTR ) { +return ; +} +if ( N -> getOpcode ( ) == ISD :: SDIV ) { +ReplaceReductionResults ( N , Results , DAG , ISD :: UMAX , XCoreISD :: UMAXVV ) ; +return ; +} +SDLoc DL ( N ) ; +RTLIB :: Libcall libCall = RTLIB :: UNKNOWN_LIBCALL ; +if ( N -> getOpcode ( ) == ISD :: UDIV ) { +ReplaceCMP_SWAP_128Results ( N , Results , DAG , Subtarget ) ; +if ( N -> getOperand ( 0 ) . getValueType ( ) != MVT :: f128 ) { +return ; +} +if ( N -> getValueType ( 0 ) != MVT :: i64 ) { +return ; +} +libCall = RTLIB :: FPTOSINT_F128_I64 ; +Results . push_back ( LowerF128Op ( SDValue ( N , 0 ) , DAG , getLibcallName ( libCall ) , 1 ) ) ; +return ; +} +if ( N -> getOpcode ( ) == ISD :: UREM ) { +LoadSDNode * LoadNode = cast < LoadSDNode > ( N ) ; +if ( ! LoadNode -> isVolatile ( ) ) { +return ; +} +if ( LoadNode -> getMemoryVT ( ) != MVT :: i128 ) { +return ; +} +SDValue Result = DAG . getMemIntrinsicNode ( XCoreISD :: LDP , SDLoc ( N ) , DAG . getVTList ( { MVT :: i64 , MVT :: i64 , MVT :: Other } ) , { LoadNode -> getChain ( ) , LoadNode -> getBasePtr ( ) } , LoadNode -> getMemoryVT ( ) , LoadNode -> getMemOperand ( ) ) ; +SDValue Pair = DAG . getNode ( ISD :: BUILD_PAIR , SDLoc ( N ) , MVT :: i128 , Result . getValue ( 0 ) , Result . getValue ( 1 ) ) ; +Results . append ( { Pair , Result . getValue ( 2 ) } ) ; +if ( N -> getOperand ( 0 ) . getValueType ( ) != MVT :: f128 ) { +return ; +} +if ( N -> getValueType ( 0 ) != MVT :: i64 ) { +return ; +} +libCall = RTLIB :: FPTOUINT_F128_I64 ; +Results . push_back ( LowerF128Op ( SDValue ( N , 0 ) , DAG , getLibcallName ( libCall ) , 1 ) ) ; +return ; +} +if ( N -> getOpcode ( ) == ISD :: BITCAST ) { +ReplaceCMP_SWAP_128Results ( N , Results , DAG , Subtarget ) ; +ReplaceExtractSubVectorResults ( N , Results , DAG ) ; +SDValue Lo = DAG . getCopyFromReg ( N -> getOperand ( 0 ) , DL , XCore :: ASR23 , MVT :: i32 ) ; +SDValue Hi = DAG . getCopyFromReg ( Lo , DL , XCore :: G0 , MVT :: i32 ) ; +SDValue Ops [ ] = { Lo , Hi } ; +SDValue Pair = DAG . getNode ( ISD :: BUILD_PAIR , DL , MVT :: i64 , Ops ) ; +Results . push_back ( Pair ) ; +return ; +} +if ( N -> getOpcode ( ) == XCoreISD::GREVI ) { +LoadSDNode * LoadNode = cast < LoadSDNode > ( N ) ; +if ( ! LoadNode -> isVolatile ( ) ) { +return ; +} +if ( LoadNode -> getMemoryVT ( ) != MVT :: i128 ) { +return ; +} +SDValue Result = DAG . getMemIntrinsicNode ( XCoreISD :: LDP , SDLoc ( N ) , DAG . getVTList ( { MVT :: i64 , MVT :: i64 , MVT :: Other } ) , { LoadNode -> getChain ( ) , LoadNode -> getBasePtr ( ) } , LoadNode -> getMemoryVT ( ) , LoadNode -> getMemOperand ( ) ) ; +SDValue Pair = DAG . getNode ( ISD :: BUILD_PAIR , SDLoc ( N ) , MVT :: i128 , Result . getValue ( 0 ) , Result . getValue ( 1 ) ) ; +Results . append ( { Pair , Result . getValue ( 2 ) } ) ; +if ( N -> getValueType ( 0 ) != MVT :: f128 ) { +return ; +} +if ( N -> getOperand ( 0 ) . getValueType ( ) != MVT :: i64 ) { +return ; +} +libCall = RTLIB :: SINTTOFP_I64_F128 ; +Results . push_back ( LowerF128Op ( SDValue ( N , 0 ) , DAG , getLibcallName ( libCall ) , 1 ) ) ; +return ; +return ReplaceLongIntrinsic ( N , Results , DAG ) ; +} +if ( N -> getOpcode ( ) == XCoreISD :: GORCI ) { +ReplaceExtractSubVectorResults ( N , Results , DAG ) ; +ReplaceLongIntrinsic ( N , Results , DAG ) ; +if ( N -> getValueType ( 0 ) != MVT :: f128 ) { +return ; +} +if ( N -> getOperand ( 0 ) . getValueType ( ) != MVT :: i64 ) { +return ; +} +libCall = RTLIB :: UINTTOFP_I64_F128 ; +Results . push_back ( LowerF128Op ( SDValue ( N , 0 ) , DAG , getLibcallName ( libCall ) , 1 ) ) ; +return ; +} +if ( N -> getOpcode ( ) == ISD :: BSWAP ) { +EVT VT = N -> getValueType ( 0 ) ; +ConstantSDNode * CN = cast < ConstantSDNode > ( N -> getOperand ( 0 ) ) ; +Intrinsic :: ID IntID = static_cast < Intrinsic :: ID > ( CN -> getZExtValue ( ) ) ; +if ( IntID == Intrinsic :: aarch64_sve_clasta_n ) { +SDLoc DL ( N ) ; +auto Op2 = DAG . getNode ( ISD :: ANY_EXTEND , DL , MVT :: i32 , N -> getOperand ( 2 ) ) ; +auto V = DAG . getNode ( XCoreISD :: CLASTA_N , DL , MVT :: i32 , N -> getOperand ( 1 ) , Op2 , N -> getOperand ( 3 ) ) ; +Results . push_back ( DAG . getNode ( ISD :: TRUNCATE , DL , VT , V ) ) ; +return ; +} +if ( IntID == Intrinsic :: aarch64_sve_lasta ) { +SDLoc DL ( N ) ; +auto V = DAG . getNode ( XCoreISD :: LASTA , DL , MVT :: i32 , N -> getOperand ( 1 ) , N -> getOperand ( 2 ) ) ; +Results . push_back ( DAG . getNode ( ISD :: TRUNCATE , DL , VT , V ) ) ; +return ; +} +if ( IntID == Intrinsic :: aarch64_sve_lastb ) { +SDLoc DL ( N ) ; +auto V = DAG . getNode ( XCoreISD :: LASTB , DL , MVT :: i32 , N -> getOperand ( 1 ) , N -> getOperand ( 2 ) ) ; +Results . push_back ( DAG . getNode ( ISD :: TRUNCATE , DL , VT , V ) ) ; +return ; +} +LowerLOAD ( N , Results , DAG ) ; +if ( Res . getNode ( ) ) { +Results . push_back ( Res ) ; +} +LoadSDNode * Ld = cast < LoadSDNode > ( N ) ; +if ( Ld -> getValueType ( 0 ) != MVT :: i64 ) { +return ; +} +if ( Ld -> getMemoryVT ( ) != MVT :: i64 ) { +return ; +} +SDLoc DL ( N ) ; +SDValue LoadRes = DAG . getExtLoad ( Ld -> getExtensionType ( ) , DL , MVT :: v2i32 , Ld -> getChain ( ) , Ld -> getBasePtr ( ) , Ld -> getPointerInfo ( ) , MVT :: v2i32 , Ld -> getAlignment ( ) , Ld -> getMemOperand ( ) -> getFlags ( ) , Ld -> getAAInfo ( ) ) ; +SDValue Res = DAG . getNode ( ISD :: BITCAST , DL , MVT :: i64 , LoadRes ) ; +Results . push_back ( Res ) ; +Results . push_back ( LoadRes . getValue ( 1 ) ) ; +return ; +} +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/TargetLowering.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/TargetLowering.cpp new file mode 100644 index 0000000000000000000000000000000000000000..528e265e6742dd15a1c14b5f6494a0bcc27a8e7a --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/TargetLowering.cpp @@ -0,0 +1,42 @@ +XCoreTargetLowering :: XCoreTargetLowering ( const TargetMachine & TM , const XCoreSubtarget & STI ) : TargetLowering ( TM ) , Subtarget ( STI ) { +computeRegisterProperties ( STI . getRegisterInfo ( ) ) ; +setStackPointerRegisterToSaveRestore ( XCore :: X1 ) ; +for ( auto N : { ISD :: EXTLOAD , ISD :: SEXTLOAD , ISD :: ZEXTLOAD } ) { +} +setBooleanContents ( ZeroOrOneBooleanContent ) ; +addRegisterClass ( MVT :: i32 , & XCore :: GPRRegClass ) ; +TRI = STI . getRegisterInfo ( ) ; +computeRegisterProperties ( TRI ) ; +auto * RegInfo = Subtarget . getRegisterInfo ( ) ; +setBooleanVectorContents ( ZeroOrNegativeOneBooleanContent ) ; +setBooleanContents ( ZeroOrOneBooleanContent , ZeroOrNegativeOneBooleanContent ) ; +} +} +for ( auto CC : FPCCToExtend ) { +setLoadExtAction ( ISD :: SEXTLOAD , VT , MVT :: i1 , Promote ) ; +setLoadExtAction ( ISD :: ZEXTLOAD , VT , MVT :: i1 , Promote ) ; +if ( F16VT . isValid ( ) ) { +} +} +if ( Subtarget . atLeastM68020 ( ) ) { +} +setBooleanContents ( ZeroOrOneBooleanContent ) ; +setMinimumJumpTableEntries ( INT_MAX ) ; +setCondCodeAction ( CC , VT , Expand ) ; +computeRegisterProperties ( STI . getRegisterInfo ( ) ) ; +setBooleanContents ( UndefinedBooleanContent ) ; +setBooleanVectorContents ( ZeroOrNegativeOneBooleanContent ) ; +setMaxAtomicSizeInBitsSupported ( 0 ) ; +setStackPointerRegisterToSaveRestore ( XCore :: R14 ) ; +const Align FunctionAlignment ( 2 ) ; +setStackPointerRegisterToSaveRestore ( XCore :: R3 ) ; +setMinFunctionAlignment ( FunctionAlignment ) ; +setSchedulingPreference ( Sched :: Source ) ; +setJumpIsExpensive ( true ) ; +setLibcallCallingConv ( static_cast < RTLIB :: Libcall > ( I ) , CallingConv :: Fast ) ; +setBooleanContents ( ZeroOrOneBooleanContent ) ; +computeRegisterProperties ( ) ; +computeRegisterProperties ( STI . getRegisterInfo ( ) ) ; +setMinFunctionAlignment ( Align :: Constant < 2 > ( ) ) ; +setStackPointerRegisterToSaveRestore ( ABI . IsN64 ( ) ? XCore :: SP_64 : XCore :: SP ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/computeMaskedBitsForTargetNode.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/computeMaskedBitsForTargetNode.cpp new file mode 100644 index 0000000000000000000000000000000000000000..719f4f494556e7e5180fa3a3976a87840dc69030 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/computeMaskedBitsForTargetNode.cpp @@ -0,0 +1,170 @@ +void XCoreTargetLowering :: computeKnownBitsForTargetNode ( const SDValue Op , KnownBits & Known , const APInt & DemandedElts , const SelectionDAG & DAG , unsigned Depth ) const { +KnownZero = KnownOne = APInt ( KnownOne . getBitWidth ( ) , 0 ) ; +APInt KnownZero2 ; +APInt KnownOne2 ; +unsigned BitWidth = Known . getBitWidth ( ) ; +unsigned Opc = Op . getOpcode ( ) ; +EVT VT = Op . getValueType ( ) ; +Known . resetAll ( ) ; +if ( Op . getOpcode ( ) == XCoreISD :: REMUW ) { +KnownZero = APInt :: getHighBitsSet ( 32 , 31 ) ; +if ( Op . getResNo ( ) == 0 ) { +return ; +} +Known . Zero . setBitsFrom ( 1 ) ; +} +if ( Op . getOpcode ( ) == XCoreISD :: DIVUW ) { +KnownBits Known2 ; +DAG . computeKnownBits ( Op . getOperand ( 0 ) , Known , Depth + 1 ) ; +DAG . computeKnownBits ( Op . getOperand ( 1 ) , Known2 , Depth + 1 ) ; +Known . Zero = Known . Zero & Known2 . Zero ; +Known . One = Known . One & Known2 . One ; +KnownZero = APInt :: getHighBitsSet ( 32 , 31 ) ; +if ( Op . getResNo ( ) == 0 ) { +return ; +} +Known . Zero . setBitsFrom ( 1 ) ; +} +unsigned BitWidth = Known . getBitWidth ( ) ; +if ( Op . getResNo ( ) == 0 ) { +return ; +} +Known . Zero . setBitsFrom ( 1 ) ; +if ( Op . getOpcode ( ) == XCoreISD :: READ_VLENB ) { +if ( Op . getResNo ( ) == 0 ) { +return ; +} +Known . Zero . setBitsFrom ( 1 ) ; +} +if ( Op . getResNo ( ) == 0 ) { +return ; +} +Known . Zero . setBitsFrom ( 1 ) ; +if ( Op . getResNo ( ) == 0 ) { +return ; +} +Known . Zero . setBitsFrom ( 1 ) ; +if ( Op . getResNo ( ) == 0 ) { +return ; +} +Known . Zero . setBitsFrom ( 1 ) ; +if ( Op . getResNo ( ) == 0 ) { +return ; +} +Known . Zero . setBitsFrom ( 1 ) ; +if ( Op . getResNo ( ) == 0 ) { +return ; +} +Known . Zero . setBitsFrom ( 1 ) ; +if ( Op . getResNo ( ) == 0 ) { +return ; +} +Known . Zero . setBitsFrom ( 1 ) ; +if ( Op . getResNo ( ) == 0 ) { +return ; +} +Known . Zero . setBitsFrom ( 1 ) ; +if ( Op . getResNo ( ) == 0 ) { +return ; +} +Known . Zero . setBitsFrom ( 1 ) ; +unsigned NumLoBits = Op . getOperand ( 0 ) . getValueType ( ) . getVectorNumElements ( ) ; +Known . Zero . setBitsFrom ( NumLoBits ) ; +if ( auto * ShiftImm = dyn_cast < ConstantSDNode > ( Op . getOperand ( 1 ) ) ) { +if ( ShiftImm -> getAPIntValue ( ) . uge ( VT . getScalarSizeInBits ( ) ) ) { +Known . setAllZero ( ) ; +break ; +} +DAG . computeKnownBits ( Op . getOperand ( 0 ) , Known , Depth + 1 ) ; +unsigned ShAmt = ShiftImm -> getZExtValue ( ) ; +Known . Zero . lshrInPlace ( ShAmt ) ; +Known . One . lshrInPlace ( ShAmt ) ; +Known . Zero . setHighBits ( ShAmt ) ; +} +ConstantSDNode * CN = cast < ConstantSDNode > ( Op -> getOperand ( 1 ) ) ; +Intrinsic :: ID IntID = static_cast < Intrinsic :: ID > ( CN -> getZExtValue ( ) ) ; +unsigned BitWidth = Known . getBitWidth ( ) ; +EVT VT = cast < MemIntrinsicSDNode > ( Op ) -> getMemoryVT ( ) ; +unsigned MemBits = VT . getScalarSizeInBits ( ) ; +Known . Zero = Known . Zero | APInt :: getHighBitsSet ( BitWidth , BitWidth - MemBits ) ; +return ; +unsigned BitWidth = Known . getBitWidth ( ) ; +EVT VT = cast < MemIntrinsicSDNode > ( Op ) -> getMemoryVT ( ) ; +unsigned MemBits = VT . getScalarSizeInBits ( ) ; +Known . Zero = Known . Zero | APInt :: getHighBitsSet ( BitWidth , BitWidth - MemBits ) ; +return ; +ConstantSDNode * CWidth = dyn_cast < ConstantSDNode > ( Op . getOperand ( 2 ) ) ; +if ( ! CWidth ) { +return ; +} +unsigned BitWidth = 32 ; +uint32_t Width = CWidth -> getZExtValue ( ) & 0x1f ; +Known = KnownBits ( BitWidth ) ; +Known . Zero . setBits ( 1 , BitWidth ) ; +if ( auto * ShiftImm = dyn_cast < ConstantSDNode > ( Op . getOperand ( 1 ) ) ) { +if ( ShiftImm -> getAPIntValue ( ) . uge ( VT . getScalarSizeInBits ( ) ) ) { +Known . setAllZero ( ) ; +break ; +} +DAG . computeKnownBits ( Op . getOperand ( 0 ) , Known , Depth + 1 ) ; +unsigned ShAmt = ShiftImm -> getZExtValue ( ) ; +Known . Zero = Known . Zero << ShAmt ; +Known . One = Known . One << ShAmt ; +Known . Zero . setLowBits ( ShAmt ) ; +} +Intrinsic :: ID IntID = static_cast < Intrinsic :: ID > ( Op . getOperand ( 0 ) -> getZExtValue ( ) ) ; +unsigned BitWidth = Known . getBitWidth ( ) ; +if ( VT == MVT :: v16i8 ) { +APInt Mask = APInt :: getHighBitsSet ( BitWidth , BitWidth - 8 ) ; +Known . Zero = Known . Zero | Mask ; +} +if ( VT == MVT :: v8i8 ) { +APInt Mask = APInt :: getHighBitsSet ( BitWidth , BitWidth - 8 ) ; +Known . Zero = Known . Zero | Mask ; +} +if ( VT == MVT :: v4i16 ) { +APInt Mask = APInt :: getHighBitsSet ( BitWidth , BitWidth - 16 ) ; +Known . Zero = Known . Zero | Mask ; +} +if ( VT == MVT :: v8i16 ) { +APInt Mask = APInt :: getHighBitsSet ( BitWidth , BitWidth - 16 ) ; +Known . Zero = Known . Zero | Mask ; +} +unsigned BitWidth = Known . getBitWidth ( ) ; +if ( VT == MVT :: v8i8 ) { +APInt Mask = APInt :: getHighBitsSet ( BitWidth , BitWidth - 8 ) ; +Known . Zero = Known . Zero | Mask ; +} +if ( VT == MVT :: v16i8 ) { +APInt Mask = APInt :: getHighBitsSet ( BitWidth , BitWidth - 8 ) ; +Known . Zero = Known . Zero | Mask ; +} +if ( VT == MVT :: v4i16 ) { +APInt Mask = APInt :: getHighBitsSet ( BitWidth , BitWidth - 16 ) ; +Known . Zero = Known . Zero | Mask ; +} +if ( VT == MVT :: v8i16 ) { +APInt Mask = APInt :: getHighBitsSet ( BitWidth , BitWidth - 16 ) ; +Known . Zero = Known . Zero | Mask ; +} +ConstantSDNode * CWidth = dyn_cast < ConstantSDNode > ( Op . getOperand ( 2 ) ) ; +if ( ! CWidth ) { +return ; +} +unsigned BitWidth = 32 ; +uint32_t Width = CWidth -> getZExtValue ( ) & 0x1f ; +KnownZero = APInt :: getHighBitsSet ( BitWidth , BitWidth - Width ) ; +KnownBits Known2 ; +SDValue N0 = Op . getOperand ( 0 ) ; +unsigned NumElts = VT . getVectorNumElements ( ) ; +EVT SrcVT = N0 . getValueType ( ) ; +unsigned InNumElts = SrcVT . getVectorNumElements ( ) ; +unsigned InBitWidth = SrcVT . getScalarSizeInBits ( ) ; +Known2 = DAG . computeKnownBits ( Op -> getOperand ( 1 ) , Depth + 1 ) ; +Known . Zero = Known . Zero & Known2 . Zero ; +Known . One = Known . One & Known2 . One ; +APInt DemandedSrcElts = APInt :: getLowBitsSet ( InNumElts , NumElts ) ; +DAG . computeKnownBits ( N0 , Known , DemandedSrcElts , Depth + 1 ) ; +Known = Known . zext ( BitWidth ) ; +Known . Zero . setBitsFrom ( InBitWidth ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/enum NodeType.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/enum NodeType.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b6a459394d7eea05a2ffde5ec5985951b1c56d39 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/enum NodeType.cpp @@ -0,0 +1,30 @@ +enum NodeType { +FIRST_NUMBER = ISD :: BUILTIN_OP_END , +BL , +PCRelativeWrapper , +DPRelativeWrapper , +CPRelativeWrapper , +ABS16Wrapper , +LDWSP , +STWSP , +RETSP , +OUTPW , +INPW , +LADD , +LSUB , +LMUL , +MACCU , +MACCS , +BR_JT , +BR_JT32 , +FRAME_TO_ARGS_OFFSET , +EH_RETURN , +MEMBARRIER , +RETURN_REG_HOLDER , +STACKSAVE , +STACKRESTORE , +STACKUP , +STACKDOWN , +ALLOCA , +LOOPMARKER +} ; \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/getJumpTableEncoding.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/getJumpTableEncoding.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1eb25c3c5251d071444e8e8d4613e46e22e17c58 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/getJumpTableEncoding.cpp @@ -0,0 +1,3 @@ +unsigned XCoreTargetLowering :: getJumpTableEncoding ( ) const { +return MachineJumpTableInfo :: EK_Inline ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/getRegForInlineAsmConstraint.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/getRegForInlineAsmConstraint.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fbb4b0f13c9c138b4feb398075a20011ab488f43 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/getRegForInlineAsmConstraint.cpp @@ -0,0 +1,10 @@ +std :: pair < unsigned , const TargetRegisterClass * > XCoreTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , EVT VT ) const { +if ( Constraint . size ( ) == 1 ) { +if ( Constraint [ 0 ] == 'r' ) { +if ( VT . getSizeInBits ( ) <= 32 ) { +return std :: make_pair ( 0U , XCore :: GRRegsRegisterClass ) ; +} +} +} +return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/getShiftAmountTy.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/getShiftAmountTy.cpp new file mode 100644 index 0000000000000000000000000000000000000000..35ca7a530662765a419db2d7e551075b87b88ea4 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/getShiftAmountTy.cpp @@ -0,0 +1,3 @@ +virtual MVT getShiftAmountTy ( EVT LHSTy ) const { +return MVT :: i32 ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/getTargetNodeName.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/getTargetNodeName.cpp new file mode 100644 index 0000000000000000000000000000000000000000..47021ab56cd424d11745f79e585d63418a9b70f8 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/getTargetNodeName.cpp @@ -0,0 +1,63 @@ +const char * XCoreTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { +if ( ( XCoreISD :: NodeType ) Opcode == XCoreISD :: BL ) { +return "XCoreISD::BL" ; +} +if ( ( XCoreISD :: NodeType ) Opcode == XCoreISD :: PCRelativeWrapper ) { +return "XCoreISD::PCRelativeWrapper" ; +} +if ( ( XCoreISD :: NodeType ) Opcode == XCoreISD :: DPRelativeWrapper ) { +return "XCoreISD::DPRelativeWrapper" ; +} +if ( ( XCoreISD :: NodeType ) Opcode == XCoreISD :: CPRelativeWrapper ) { +return "XCoreISD::CPRelativeWrapper" ; +} +if ( ( XCoreISD :: NodeType ) Opcode == XCoreISD :: ABS16Wrapper ) { +return "XCoreISD::ABS16Wrapper" ; +} +if ( ( XCoreISD :: NodeType ) Opcode == XCoreISD :: LDWSP ) { +return "XCoreISD::LDWSP" ; +} +if ( ( XCoreISD :: NodeType ) Opcode == XCoreISD :: STWSP ) { +return "XCoreISD::STWSP" ; +} +if ( ( XCoreISD :: NodeType ) Opcode == XCoreISD :: RETSP ) { +return "XCoreISD::RETSP" ; +} +if ( ( XCoreISD :: NodeType ) Opcode == XCoreISD :: LADD ) { +return "XCoreISD::LADD" ; +} +if ( ( XCoreISD :: NodeType ) Opcode == XCoreISD :: OUTPW ) { +return "XCoreISD::OUTPW" ; +} +if ( ( XCoreISD :: NodeType ) Opcode == XCoreISD :: INPW ) { +return "XCoreISD::INPW" ; +} +if ( ( XCoreISD :: NodeType ) Opcode == XCoreISD :: LSUB ) { +return "XCoreISD::LSUB" ; +} +if ( ( XCoreISD :: NodeType ) Opcode == XCoreISD :: LMUL ) { +return "XCoreISD::LMUL" ; +} +if ( ( XCoreISD :: NodeType ) Opcode == XCoreISD::MACCU ) { +return "XCoreISD::MACCU" ; +} +if ( ( XCoreISD :: NodeType ) Opcode == XCoreISD::MACCS ) { +return "XCoreISD::MACCS" ; +} +if ( ( XCoreISD :: NodeType ) Opcode == XCoreISD :: BR_JT ) { +return "XCoreISD::BR_JT" ; +} +if ( ( XCoreISD :: NodeType ) Opcode == XCoreISD :: BR_JT32 ) { +return "XCoreISD::BR_JT32" ; +} +if ( ( XCoreISD :: NodeType ) Opcode == XCoreISD :: FRAME_TO_ARGS_OFFSET ) { +return "XCoreISD::FRAME_TO_ARGS_OFFSET" ; +} +if ( ( XCoreISD :: NodeType ) Opcode == XCoreISD :: EH_RETURN ) { +return "XCoreISD::EH_RETURN" ; +} +if ( ( XCoreISD :: NodeType ) Opcode == XCoreISD::MEMBARRIER ) { +return "XCoreISD::MEMBARRIER" ; +} +return NULL ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/isLegalAddImmediate.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/isLegalAddImmediate.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b1a53807ab7da8c662a375e13e2c469aba8202fa --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/isLegalAddImmediate.cpp @@ -0,0 +1,3 @@ +bool XCoreTargetLowering :: isLegalAddImmediate ( int64_t Imm ) const { +return isUInt < 32 > ( Imm ) || isUInt < 32 > ( - Imm ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/isLegalAddressingMode.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/isLegalAddressingMode.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9be697f819be3cc7ce7458aa6f2dcf430909212b --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/isLegalAddressingMode.cpp @@ -0,0 +1,16 @@ +bool XCoreTargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS , Instruction * I ) const { +if ( AM . BaseGV ) { +return false ; +} +if ( ! AM . HasBaseReg ) { +} +if ( ! AM . BaseOffs ) { +} +if ( ! AM . HasBaseReg ) { +return true ; +if ( ! AM . BaseOffs ) { +} +} +return false ; +return false ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/isLegalICmpImmediate.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/isLegalICmpImmediate.cpp new file mode 100644 index 0000000000000000000000000000000000000000..71be4c9132d277735ca37fdefc0c01134fa758ac --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/ISelLowering/isLegalICmpImmediate.cpp @@ -0,0 +1,3 @@ +bool XCoreTargetLowering :: isLegalICmpImmediate ( int64_t Imm ) const { +return Imm >= 0 && Imm <= 11 ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/SelectionDAGInfo/EmitTargetCodeForMemcpy.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/SelectionDAGInfo/EmitTargetCodeForMemcpy.cpp new file mode 100644 index 0000000000000000000000000000000000000000..54e37df98de8dfe47e478c494faf5c39926b96c3 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/SelectionDAGInfo/EmitTargetCodeForMemcpy.cpp @@ -0,0 +1,17 @@ +SDValue XCoreSelectionDAGInfo :: EmitTargetCodeForMemcpy ( SelectionDAG & DAG , const SDLoc & dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , bool AlwaysInline , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { +const XCoreSubtarget & STI = DAG . getMachineFunction ( ) . getSubtarget < XCoreSubtarget > ( ) ; +if ( STI . hasMOPS ( ) ) { +return EmitMOPS ( XCoreISD :: MOPS_MEMCOPY , DAG , DL , Chain , Dst , Src , Size , Alignment , isVolatile , DstPtrInfo , SrcPtrInfo ) ; +} +if ( IsVolatile ) { +} +if ( auto * CSize = dyn_cast < ConstantSDNode > ( Size ) ) { +return emitMemMem ( DAG , DL , XCoreISD :: MVC , XCoreISD :: MVC_LOOP , Chain , Dst , Src , CSize -> getZExtValue ( ) ) ; +} +return SDValue ( ) ; +return EmitTargetCodeForMemOp ( DAG , dl , Chain , Dst , Src , Size , Alignment , isVolatile , AlwaysInline , MustPreserveCheriCapabilities , DstPtrInfo , SrcPtrInfo , true ) ; +if ( ! DAG . getMachineFunction ( ) . getSubtarget < XCoreSubtarget > ( ) . hasBulkMemory ( ) ) { +} +SDValue MemIdx = DAG . getConstant ( 0 , DL , MVT :: i32 ) ; +return DAG . getNode ( XCoreISD :: MEMORY_COPY , DL , MVT :: Other , { Chain , MemIdx , MemIdx , Dst , Src , DAG . getZExtOrTrunc ( Size , DL , MVT :: i32 ) } ) ; +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/SelectionDAGInfo/SelectionDAGInfo.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/SelectionDAGInfo/SelectionDAGInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0587bd3c5a6e1d08a2d4f0b49b12bf7e44b72955 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/SelectionDAGInfo/SelectionDAGInfo.cpp @@ -0,0 +1,2 @@ +XCoreSelectionDAGInfo :: XCoreSelectionDAGInfo ( const XCoreTargetMachine & TM ) : TargetSelectionDAGInfo ( TM ) , TLI ( * TM . getTargetLowering ( ) ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/SelectionDAGInfo/~SelectionDAGInfo.cpp b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/SelectionDAGInfo/~SelectionDAGInfo.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8f65393a6efa56a632ef84b54667a2fb848424b2 --- /dev/null +++ b/Scripts/Exp/ForkFlow/VEGA_Code/XCore/Selection/SelectionDAGInfo/~SelectionDAGInfo.cpp @@ -0,0 +1,2 @@ +XCoreSelectionDAGInfo :: ~ XCoreSelectionDAGInfo ( ) { +} \ No newline at end of file diff --git a/Scripts/Exp/ForkFlow/__pycache__/My_Difflib.cpython-39.pyc b/Scripts/Exp/ForkFlow/__pycache__/My_Difflib.cpython-39.pyc new file mode 100644 index 0000000000000000000000000000000000000000..5741dfd0f8efed66c07859c7e83def1e2bf4b762 Binary files /dev/null and b/Scripts/Exp/ForkFlow/__pycache__/My_Difflib.cpython-39.pyc differ diff --git a/Scripts/Exp/ForkFlow/calculate_forkflow.py b/Scripts/Exp/ForkFlow/calculate_forkflow.py new file mode 100644 index 0000000000000000000000000000000000000000..d354205c794f4edb57f540e3d71acaeef0121efd --- /dev/null +++ b/Scripts/Exp/ForkFlow/calculate_forkflow.py @@ -0,0 +1,203 @@ +# -*- encoding: utf-8 -*- + + +from asyncore import write +import My_Difflib +from distutils.command.config import config +import os, sys,string,re,glob +import html +import csv +import copy +from tqdm import tqdm +import pathlib + +folder = str(pathlib.Path(__file__).parent.resolve()) + +Wrong_Dir = folder +Mips_Dir = folder + "/Mips_Code" +VEGA_Dir = folder + "/VEGA_Code" +Ans_Dir = folder + "/Std_Code" +count_wrong = 0 + +Mod_File_Func = {} +Mod_Result = {} + + + +def deal_dir(src_dir): + global Mod_File_Func + global Mod_Result + if not os.path.exists(src_dir): + return False + filelists = os.listdir(src_dir) + for eachfile in filelists: + tem =eachfile + eachfile = src_dir + '/' +eachfile + if os.path.isdir(eachfile): + deal_dir(eachfile) + elif os.path.isfile(eachfile) and ".cpp" in eachfile: + module = eachfile.split("/")[-3] + if module not in Mod_Result.keys(): + Mod_Result[module] = [0,0,0] + file = eachfile.split("/")[-2] + func = eachfile.split("/")[-1].replace(".cpp", "") + if (" ").join([module, file, func]) not in Mod_File_Func.keys(): + Mod_File_Func[(" ").join([module, file, func])] = [] + codes = "" + f2 = open(eachfile, encoding = "utf-8") + lines = f2.readlines() + + for idx, l in enumerate(lines): + if idx == len(lines) - 1: + codes += l.replace(" ", "").replace("\n", "").lower().replace("mips","").replace("xcore", "").replace("pulp", "").replace("riscv", "") + else: + codes += l.replace(" ", "").lower().replace("mips","").replace("xcore", "").replace("pulp", "").replace("riscv", "") + f2.close() + + if "/Mips" in eachfile: + Mod_File_Func[(" ").join([module, file, func])].append(["Mips", codes]) + elif "/Std_Code/" in eachfile: + Mod_File_Func[(" ").join([module, file, func])].append(["Ans", codes]) + elif "/VEGA" in eachfile: + Mod_File_Func[(" ").join([module, file, func])].append(["VEGA", codes]) + return True + +wrong_stmt = [] +def get_wrong_list(): + global wrong_stmt + with open(Wrong_Dir+"/wrong_list_all.csv", 'r', encoding='utf-8') as fcsv: + reader = csv.reader(fcsv) + for row in reader: + if row[0] == "idx": + continue + wrong_stmt.append(row[0].strip().lower() + " " + row[1].strip().lower() + " " + row[2].strip().lower()) + + + + +def duplicate_data(tar): + global wrong_stmt + global Mod_File_Func + global Mod_Result + + for kv in Mod_File_Func.items(): + module = kv[0].split(" ")[0] + if len(kv[1]) != 3: + print(tar + " " + kv[0]) + Ans = "" + Vega = "" + Mips = "" + + for codes in kv[1]: + if codes[0] == "Mips": + Mips = codes[1] + #print(codes[1]) + if codes[0] == "Ans": + Ans = codes[1] + if codes[0] == "VEGA": + Vega = codes[1] + + total = len(Ans.split("\n")) + #print(Mod_Result) + Mod_Result[module][0] += total + + vega_same = 0 + vega_modi = 0 + vega_add = 0 + Mips_same = 0 + Mips_modi = 0 + Mips_add = 0 + diff_vega = list(My_Difflib.Differ().compare(Ans.splitlines(), Vega.splitlines())) + + for idx, dv in enumerate(diff_vega): + if dv[0] == '-': + if idx < len(diff_vega) - 1 and diff_vega[idx+1][0] == '?': + vega_modi += 1 + else: + vega_add += 1 + elif dv[0] == '+': + continue + elif dv[0] == '?': + continue + #vega_add -= 1 + elif dv.strip().replace("\n", "") == '': + continue + else: + vega_same += 1 + #assert vega_same + vega_modi + vega_add == total + # if file_path.split("/")[-1].replace(".cpp", "").replace("_Wrong", "").lower() == "eliminateframeindex": + # for dv in diff_vega: + # print(dv) + if kv[0].split(" ")[-2].strip().lower() + " " + kv[0].split(" ")[-1].strip().lower() + " " + tar.lower() not in wrong_stmt: + #print(kv[0].split(" ")[-2].lower() + " " + kv[0].split(" ")[-1].lower().strip()) + vega_same = total + vega_modi = 0 + vega_add = 0 + Mod_Result[module][2] += vega_same + if Mips.replace("\n", "") != "None": + diff_mips = list(My_Difflib.Differ().compare(Ans.splitlines(), Mips.splitlines())) + for dm in diff_mips: + #print(dm) + if dm[0] == '-': + if idx < len(diff_mips) - 1 and diff_mips[idx+1][0] == '?': + Mips_modi += 1 + else: + Mips_add += 1 + elif dm[0] == '+': + continue + elif dm[0] == '?': + continue + #vega_add -= 1 + elif dm.strip().replace("\n", "") == '': + continue + else: + Mips_same += 1 + else: + Mips_add = total + + Mod_Result[module][1] += Mips_same + # if Mips_same == total: + # print(kv[0]) + # exit() + # print(Mod_Result[module][1]) + + with open(folder+"/forkflow_result.csv", 'a', encoding='utf-8', newline="") as f: + f_csv = csv.writer(f) + avg_vega = 0.0 + avg_mips = 0.0 + for kv in Mod_Result.items(): + f_csv.writerow([tar.replace("PULP", "RI5CY"), kv[0], round(kv[1][1]*1.0 / kv[1][0], 3), round(kv[1][2]*1.0 / kv[1][0], 3)]) + avg_vega += float(round(kv[1][2]*1.0 / kv[1][0], 3)) + avg_mips += float(round(kv[1][1]*1.0 / kv[1][0], 3)) + f_csv.writerow([tar.replace("PULP", "RI5CY"), "Avg", round(avg_mips / len(Mod_Result), 3), round(avg_vega / len(Mod_Result), 3)]) + + with open(folder+"/mod_lines.csv", 'a', encoding='utf-8', newline="") as f: + f_csv = csv.writer(f) + all_vega = 0 + all_mips = 0 + all_stmt = 0 + for kv in Mod_Result.items(): + f_csv.writerow([tar.replace("PULP", "RI5CY"), kv[0], kv[1][2], kv[1][0]-kv[1][2]]) + all_vega += kv[1][2] + all_mips += kv[1][1] + all_stmt += kv[1][0] + f_csv.writerow([tar.replace("PULP", "RI5CY"), "All", all_vega, all_stmt - all_vega]) + +if __name__ == '__main__': + get_wrong_list() + with open(folder+"/forkflow_result.csv", 'w', encoding='utf-8', newline="") as f: + f_csv = csv.writer(f) + f_csv.writerow(["Target", "Module", "Fork_Acc", "VEGA_Acc"]) + + with open(folder+"/mod_lines.csv", 'w', encoding='utf-8', newline="") as f: + f_csv = csv.writer(f) + f_csv.writerow(["Target", "Module", "VEGA_Accurate_Lines", "VEGA_Manual_Lines"]) + + for tar in ["XCore", "PULP", "RISCV"]: + Mod_File_Func = {} + Mod_Result = {} + deal_dir(Mips_Dir+"/"+tar) + deal_dir(VEGA_Dir+"/"+tar) + deal_dir(Ans_Dir+"/"+tar) + + duplicate_data(tar) diff --git a/Scripts/Exp/Performance/BenchMark.xlsx b/Scripts/Exp/Performance/BenchMark.xlsx new file mode 100644 index 0000000000000000000000000000000000000000..1be71b79bfc5b77a61f7023b72bdd3e320c991c9 Binary files /dev/null and b/Scripts/Exp/Performance/BenchMark.xlsx differ diff --git a/Scripts/Exp/Time/calculate_time.py b/Scripts/Exp/Time/calculate_time.py new file mode 100644 index 0000000000000000000000000000000000000000..2e6dc8996534d2b2db011203f3a6d58dc288ad8b --- /dev/null +++ b/Scripts/Exp/Time/calculate_time.py @@ -0,0 +1,36 @@ +# -*- encoding: utf-8 -*- + + +from asyncore import write +import difflib +import os, sys,string,re,glob +import shutil +import csv +import copy +import math +import json +import time +from tqdm import tqdm +import pathlib + +folder = str(pathlib.Path(__file__).parent.resolve()) + + + +def calculate_time(): + Target_Module = {} + Func_Lis = [] + for line in open(folder+"/../../../dataset/test.jsonl", 'r', encoding="utf-8"): + dic = json.loads(line) + if dic["Target"]+" "+dic["Module"] not in Target_Module.keys(): + Target_Module[dic["Target"]+" "+dic["Module"]] = 1 + else: + Target_Module[dic["Target"]+" "+dic["Module"]] += 1 + Func_Lis.append(dic["File"]+" "+dic["Func"]) + with open(folder+"/time_overhead.csv", "w",encoding="utf-8", newline = "") as f: + writer = csv.writer(f) + for kv in Target_Module.items(): + writer.writerow(kv[0].replace("PULP", "RI5CY").split(" ") + [kv[1], math.ceil(kv[1] * 25.0 / 256)]) + +if __name__ == '__main__': + calculate_time() \ No newline at end of file diff --git a/Scripts/UnixCoder/model_gen.py b/Scripts/UnixCoder/model_gen.py new file mode 100644 index 0000000000000000000000000000000000000000..ebdc913d9a49641ff037c36765a90bb246068243 --- /dev/null +++ b/Scripts/UnixCoder/model_gen.py @@ -0,0 +1,279 @@ +# Copyright (c) Microsoft Corporation. +# Licensed under the MIT license. + +import torch +import torch.nn as nn +import torch +from torch.autograd import Variable +import copy +import numpy as np + +class Seq2Seq(nn.Module): + """ + Build Seqence-to-Sequence. + + Parameters: + + * `encoder`- encoder of seq2seq model. e.g. roberta + * `decoder`- decoder of seq2seq model. e.g. transformer + * `config`- configuration of encoder model. + * `beam_size`- beam size for beam search. + * `max_length`- max length of target for beam search. + * `sos_id`- start of symbol ids in target for beam search. + * `eos_id`- end of symbol ids in target for beam search. + """ + + def __init__(self, encoder, decoder, config, mse_loss_weight=0.95, ce_loss_weight=0.05, beam_size=None, max_length=None, sos_id=None, eos_id=None, ): + super(Seq2Seq, self).__init__() + self.encoder = encoder + self.decoder = decoder + self.config = config + self.register_buffer( + "bias", torch.tril(torch.ones( + (1024, 1024), dtype=torch.uint8)).view(1, 1024, 1024) + ) + self.dense = nn.Linear(config.hidden_size, config.hidden_size) + self.lm_head = nn.Linear( + config.hidden_size, config.vocab_size, bias=False) + self.lm_head.weight = self.encoder.embeddings.word_embeddings.weight + self.lsm = nn.LogSoftmax(dim=-1) + + self.pred_dense = nn.Linear(config.hidden_size, 1, bias=True) + self.sigmoid = nn.Sigmoid() + + self.mse_loss_weight = mse_loss_weight + self.ce_loss_weight = ce_loss_weight + + self.beam_size = beam_size + self.max_length = max_length + self.sos_id = sos_id + self.eos_id = eos_id + + def forward(self, source_ids, exist=None, target_ids=None): + if target_ids is None or exist is None: + return self.generate(source_ids) + + mask = source_ids.ne(1)[:, None, :]*source_ids.ne(1)[:, :, None] + encoder_output = self.encoder( + source_ids, attention_mask=mask, use_cache=True) + # print("source_ids:", source_ids.size()) # torch.Size([56, 510]) + # print("exist:", exist.size()) # torch.Size([56, 1]) + # print("target_ids:", target_ids.size()) # torch.Size([56, 240]) + ids = torch.cat((source_ids, target_ids), -1) + + mask = self.bias[:, + source_ids.size(-1):ids.size(-1), :ids.size(-1)].bool() + mask = mask & ids[:, None, :].ne(1) + + out = self.decoder(target_ids, attention_mask=mask, + past_key_values=encoder_output.past_key_values).last_hidden_state + + # 先concat 再池化 + # print("out:", out.size()) # torch.Size([56, 240, 768]) + + lm_logits = self.lm_head(out[..., 1:, :]) + # print("lm_logits:", lm_logits.size()) # torch.Size([56, 239, 51416]) + + # Shift so that tokens < n predict n + active_loss = target_ids[..., 2:].ne(1).view(-1) + # print("active_loss:", active_loss.size()) # torch.Size([13328]) + shift_logits = lm_logits[..., :-1, :].contiguous() + # print("shift_logits:", shift_logits.size()) # torch.Size([56, 238, 51416]) + + shift_labels = target_ids[..., 2:].contiguous() + # print("shift_labels:", shift_labels.size()) # torch.Size([56, 238]) + + exist_labels = exist.contiguous() + # print("exist_labels:", exist_labels.size()) # torch.Size([56, 1]) + + # print("shift_logits.size:", shift_logits.size(-1)) # 51416 + # print("shift_logits.view(-1, shift_logits.size(-1)):", shift_logits.view(-1, shift_logits.size(-1))[active_loss].size()) # torch.Size([614, 51416]) + # print("shift_labels.view(-1):", shift_labels.view(-1)[active_loss].size()) # torch.Size([614]) + + pred_out = out[..., 0, :] + # print("pred_out:", pred_out.size()) # torch.Size([56, 768]) + pred_sigmoid = self.sigmoid(self.pred_dense(pred_out)) + # print("pred_sigmoid:", pred_sigmoid.size()) # torch.Size([56, 1]) + + # Flatten the tokens + loss_fct_code = nn.CrossEntropyLoss(ignore_index=-1) + loss_fct_pred = nn.MSELoss(reduction="mean") + loss_code = loss_fct_code(shift_logits.view(-1, shift_logits.size(-1))[active_loss], + shift_labels.view(-1)[active_loss]) + + loss_pred = loss_fct_pred(pred_sigmoid, exist_labels) + loss = loss_pred * self.mse_loss_weight + loss_code * self.ce_loss_weight + # loss = loss.to(torch.float32) + # loss = loss_pred + + outputs = loss, loss*active_loss.sum(), active_loss.sum(), loss_pred, loss_code + return outputs + + def generate(self, source_ids): + mask = source_ids.ne(1)[:, None, :] * source_ids.ne(1)[:, :, None] + encoder_output = self.encoder( + source_ids, attention_mask=mask, use_cache=True) + preds = [] + predicates = [] + zero = torch.cuda.LongTensor(1).fill_(0) + source_len = list(source_ids.ne(1).sum(-1).cpu().numpy()) + for i in range(source_ids.shape[0]): + context = [[x[i:i+1, :, :source_len[i]].repeat(self.beam_size, 1, 1, 1) for x in y] + for y in encoder_output.past_key_values] + beam = Beam(self.beam_size, self.sos_id, self.eos_id) + input_ids = beam.getCurrentState() + context_ids = source_ids[i:i+1, + :source_len[i]].repeat(self.beam_size, 1) + predicate = [] + for _ in range(self.max_length): + if beam.done(): + break + + ids = torch.cat((context_ids, input_ids), -1) + mask = self.bias[:, + context_ids.size(-1):ids.size(-1), :ids.size(-1)].bool() + mask = mask & ids[:, None, :].ne(1) + out = self.decoder(input_ids, attention_mask=mask, + past_key_values=context).last_hidden_state + # print("out:", out.size()) + # concat 池化 out + hidden_states = out[:, -1, :] + # print("hidden_states:", hidden_states.size()) + if out.size(1) == 1: + pred_sigmoid = self.sigmoid(self.pred_dense( + hidden_states.view(-1, 1, hidden_states.size(-1)))) + predicate.append( + pred_sigmoid.view(-1, pred_sigmoid.size(-1))) + #predicate.append(pred_sigmoid.view(-1, pred_sigmoid.size(-1)).cpu().numpy())# ZM modified + out = self.lsm(self.lm_head(hidden_states)).data + beam.advance(out) + input_ids.data.copy_(input_ids.data.index_select( + 0, beam.getCurrentOrigin())) + input_ids = torch.cat((input_ids, beam.getCurrentState()), -1) + hyp = beam.getHyp(beam.getFinal()) + pred = beam.buildTargetTokens(hyp)[:self.beam_size] + pred = [torch.cat([x.view(-1) for x in p] + [zero] * + (self.max_length-len(p))).view(1, -1) for p in pred] + predicates.append(predicate[0][0])# ZM modified + #print("ZM-Model_Debug_P_Each_Itr: %d, %d, %d" % (len(predicate), len(predicate[0]), len(predicate[0][0]))) + preds.append(torch.cat(pred, 0).unsqueeze(0)) + #print("ZM-Model_Debug_Predicate_Shape: %d" % (len(predicates))) + #print("ZM-Model_Debug_Codes_BeforeCat: %d, %d, %d, %d" % (len(preds), len(preds[0]), len(preds[0][0]), len(preds[0][0][0]))) + preds = torch.cat(preds, 0) + predicates = torch.tensor(predicates, device="cuda")# ZM modified + # predicates = torch.cat(predicates, 0).unsqueeze(0) + #print("ZM-Model_Debug_Codes_AfterCat: %d, %d, %d" % (len(preds), len(preds[0]), len(preds[0][0]))) + return preds, predicates + + +class Beam(object): + def __init__(self, size, sos, eos): + self.size = size + self.tt = torch.cuda + # The score for each translation on the beam. + self.scores = self.tt.FloatTensor(size).zero_() + # The backpointers at each time-step. + self.prevKs = [] + # The outputs at each time-step. + self.nextYs = [self.tt.LongTensor(size) + .fill_(0)] + self.nextYs[0][0] = sos + # Has EOS topped the beam yet. + self._eos = eos + self.eosTop = False + # Time and k pair for finished. + self.finished = [] + + def getCurrentState(self): + "Get the outputs for the current timestep." + batch = self.tt.LongTensor(self.nextYs[-1]).view(-1, 1) + return batch + + def getCurrentOrigin(self): + "Get the backpointers for the current timestep." + return self.prevKs[-1] + + def advance(self, wordLk): + """ + Given prob over words for every last beam `wordLk` and attention + `attnOut`: Compute and update the beam search. + + Parameters: + + * `wordLk`- probs of advancing from the last step (K x words) + * `attnOut`- attention at the last step + + Returns: True if beam search is complete. + """ + numWords = wordLk.size(1) + + # Sum the previous scores. + if len(self.prevKs) > 0: + beamLk = wordLk + self.scores.unsqueeze(1).expand_as(wordLk) + + # Don't let EOS have children. + for i in range(self.nextYs[-1].size(0)): + if self.nextYs[-1][i] == self._eos: + beamLk[i] = -1e20 + else: + beamLk = wordLk[0] + flatBeamLk = beamLk.view(-1) + bestScores, bestScoresId = flatBeamLk.topk(self.size, 0, True, True) + + self.scores = bestScores + + # bestScoresId is flattened beam x word array, so calculate which + # word and beam each score came from + prevK = bestScoresId // numWords + self.prevKs.append(prevK) + self.nextYs.append((bestScoresId - prevK * numWords)) + + for i in range(self.nextYs[-1].size(0)): + if self.nextYs[-1][i] == self._eos: + s = self.scores[i] + self.finished.append((s, len(self.nextYs) - 1, i)) + + # End condition is when top-of-beam is EOS and no global score. + if self.nextYs[-1][0] == self._eos: + self.eosTop = True + + def done(self): + return self.eosTop and len(self.finished) >= self.size + + def getFinal(self): + if len(self.finished) == 0: + self.finished.append((self.scores[0], len(self.nextYs) - 1, 0)) + self.finished.sort(key=lambda a: -a[0]) + if len(self.finished) != self.size: + unfinished = [] + for i in range(self.nextYs[-1].size(0)): + if self.nextYs[-1][i] != self._eos: + s = self.scores[i] + unfinished.append((s, len(self.nextYs) - 1, i)) + unfinished.sort(key=lambda a: -a[0]) + self.finished += unfinished[:self.size-len(self.finished)] + return self.finished[:self.size] + + def getHyp(self, beam_res): + """ + Walk back to construct the full hypothesis. + """ + hyps = [] + for _, timestep, k in beam_res: + hyp = [] + for j in range(len(self.prevKs[:timestep]) - 1, -1, -1): + hyp.append(self.nextYs[j+1][k]) + k = self.prevKs[j][k] + hyps.append(hyp[::-1]) + return hyps + + def buildTargetTokens(self, preds): + sentence = [] + for pred in preds: + tokens = [] + for tok in pred: + if tok == self._eos: + break + tokens.append(tok) + sentence.append(tokens) + return sentence diff --git a/Scripts/UnixCoder/run_one_model.py b/Scripts/UnixCoder/run_one_model.py new file mode 100644 index 0000000000000000000000000000000000000000..f203812dc7cd5c0440c1200cfe3bc473e886bd78 --- /dev/null +++ b/Scripts/UnixCoder/run_one_model.py @@ -0,0 +1,912 @@ +from __future__ import absolute_import +import os +from statistics import mean +import sys +from xml.sax.handler import feature_external_ges +#import bleu +import pickle +import torch +import csv +import json +import random +import time +import logging +import argparse +#from fuzzywuzzy import fuzz +import numpy as np +from io import open +from itertools import cycle +import torch.nn as nn +from model_gen import Seq2Seq +from tqdm import tqdm, trange +from torch.utils.data import DataLoader, Dataset, SequentialSampler, RandomSampler, TensorDataset +from torch.utils.data.distributed import DistributedSampler +#from sklearn.metrics import mean_squared_error +from transformers import (WEIGHTS_NAME, AdamW, get_linear_schedule_with_warmup, + RobertaConfig, RobertaModel, RobertaTokenizer) + +import pathlib + +folder = str(pathlib.Path(__file__).parent.resolve()) + +#from sklearn.metrics import mean_absolute_error, mean_squared_error +logging.basicConfig(format='%(asctime)s - %(levelname)s - %(name)s - %(message)s', + datefmt='%m/%d/%Y %H:%M:%S', + level=logging.INFO) +logger = logging.getLogger(__name__) + + +divide_number = 6 +os.environ["CUDA_VISIBLE_DEVICES"] = "0,1,2,3,4,5,6,7" + +class Example(object): + """A single training/test example.""" + + def __init__(self, + idx, + source, + target, + cpuname, + funcname, + filename, + property, + vec, + exist, + module + # propertyposition, + ): + self.idx = idx + self.source = source + self.target = target + self.cpuname = cpuname + self.funcname = funcname + self.filename = filename + self.property = property + self.vec = vec + self.exist = exist + self.module = module + + +def read_examples_no_bracket(filename, is_function_test): + """Read examples from filename.""" + examples = [] + with open(filename, encoding="utf-8") as f: + for idx, line in enumerate(f): + if is_function_test: + if idx > 212: + break + line = line.strip() + js = json.loads(line) + # if len(js['Stmt_token']) > 300: + # continue + if js["Stmt"].strip()[0] == "}": + continue + if js["Value"].strip().lower() == "nothing" and '#' in js['FIR']: + continue + if '1' in js['Vector'][-97:] and '#' not in js['FIR']: + continue + if 'idx' not in js: + js['idx'] = idx + code = ' '.join(js['FIR_token']).replace('\n', ' ') + code = ' '.join(code.strip().split()) + nl = ' '.join(js['Stmt_token']).replace('\n', ' ') + nl = ' '.join(nl.strip().split()) + if str(js['Exist']).lower() != "true" and str(js['Exist']).lower() != "false": + if int(round(float(js['Exist']))) == 1: + exist = 1 + elif js["Value"].strip().lower() != "nothing": + exist = 1 + else: + exist = 0 + else: + if js['Exist'].lower() == "true": + exist = 1 + else: + exist = 0 + tem = list(js['Vector'].replace("|zm|","")) + vec = [] + for t in tem: + if int(t) == 1: + vec.append(1) + else: + vec.append(0) + pro = ' '.join(js['Value_token']).replace('\n', ' ') + pro = ' '.join(pro.strip().split()) + + cpu = js['Target'] + func = js['Func'] + file = js['File'] + mod = "" + if "Module" in js.keys(): + mod = js["Module"] + # propos = ' '.join(js['pp']) + # propos = ' '.join(propos.strip().split(',')) + # print(code) + # print(nl) + # print(pro) + examples.append( + Example( + idx=idx, + source=code, + target=nl, + cpuname=cpu, + funcname=func, + filename=file, + property=pro, + vec=vec, + exist=exist, + module = mod + # propertyposition = propos, + ) + ) + return examples + + +def read_examples(filename, is_function_test): + """Read examples from filename.""" + examples = [] + with open(filename, encoding="utf-8") as f: + for idx, line in enumerate(f): + if is_function_test: + if idx > 212: + break + line = line.strip() + js = json.loads(line) + # if len(js['Stmt_token']) > 300: + # continue + if 'idx' not in js: + js['idx'] = idx + code = ' '.join(js['FIR_token']).replace('\n', ' ') + code = ' '.join(code.strip().split()) + nl = ' '.join(js['Stmt_token']).replace('\n', ' ') + nl = ' '.join(nl.strip().split()) + if str(js['Exist']).lower() != "true" and str(js['Exist']).lower() != "false": + if int(round(float(js['Exist']))) == 1: + exist = 1 + elif js["Value"].strip().lower() != "nothing": + exist = 1 + else: + exist = 0 + else: + if js['Exist'].lower() == "true": + exist = 1 + else: + exist = 0 + tem = list(js['Vector'].replace("|zm|","")) + vec = [] + for t in tem: + if int(t) == 1: + vec.append(1) + else: + vec.append(0) + pro = ' '.join(js['Value_token']).replace('\n', ' ') + pro = ' '.join(pro.strip().split()) + + cpu = js['Target'] + func = js['Func'] + file = js['File'] + mod = "" + if "Module" in js.keys(): + mod = js["Module"] + # propos = ' '.join(js['pp']) + # propos = ' '.join(propos.strip().split(',')) + # print(code) + # print(nl) + # print(pro) + examples.append( + Example( + idx=idx, + source=code, + target=nl, + cpuname=cpu, + funcname=func, + filename=file, + property=pro, + vec=vec, + exist=exist, + module = mod + # propertyposition = propos, + ) + ) + return examples + + +class InputFeatures(object): + """A single training/test features for a example.""" + + def __init__(self, + example_id, + source_ids, + exist, + target_ids, + ): + self.example_id = example_id + self.source_ids = source_ids + self.exist = exist + self.target_ids = target_ids + + +def convert_examples_to_features(examples, tokenizer, args, stage=None): + """convert examples to token ids""" + features = [] + for example_index, example in enumerate(examples): + # source + func_tokens = tokenizer.tokenize(example.funcname) + source_tokens = tokenizer.tokenize( + example.source) # [:args.max_source_length-5] + pro_tokens = tokenizer.tokenize(example.property) + vec_tokens = example.vec + source_tokens = [tokenizer.cls_token, "", tokenizer.sep_token, ""] + func_tokens + [tokenizer.cls_token] + \ + source_tokens + [tokenizer.cls_token] + pro_tokens + \ + [tokenizer.cls_token] + vec_tokens + [tokenizer.sep_token] + source_ids = tokenizer.convert_tokens_to_ids(source_tokens) + padding_length = args.max_source_length - len(source_ids) + source_ids += [tokenizer.pad_token_id] * padding_length + + # target + # if stage=="test": + target_tokens = tokenizer.tokenize(example.target) + exist = [example.exist] + target_tokens = [tokenizer.cls_token, ""] + \ + target_tokens + [tokenizer.sep_token] + target_ids = tokenizer.convert_tokens_to_ids(target_tokens) + padding_length = args.max_target_length - len(target_ids) + target_ids += [tokenizer.pad_token_id] * padding_length + # else: + # target_tokens = tokenizer.tokenize(example.target) + # exist_tokens = tokenizer.tokenize(example.exist) + # target_tokens = [""] + exist_tokens + [tokenizer.cls_token] + target_tokens + [tokenizer.sep_token] + # target_ids = tokenizer.convert_tokens_to_ids(target_tokens) + # padding_length = args.max_target_length - len(target_ids) + # target_ids += [tokenizer.pad_token_id] * padding_length + + features.append( + InputFeatures( + example_index, + source_ids, + exist, + target_ids, + ) + ) + return features + + +def set_seed(seed=991105): + random.seed(seed) + os.environ['PYHTONHASHSEED'] = str(seed) + np.random.seed(seed) + torch.manual_seed(seed) + torch.cuda.manual_seed(seed) + torch.backends.cudnn.deterministic = True + +def is_valid_parentheses(s): + cnt_bracket_small = 0 + cnt_bracket_mid = 0 + cnt_bracket_large = 0 + new_s = "" + for p in s: + new_s += p + if p == "(": + cnt_bracket_small += 1 + if p == ")": + cnt_bracket_small -= 1 + if p == "[": + cnt_bracket_mid += 1 + if p == "]": + cnt_bracket_mid -= 1 + if p == "{": + cnt_bracket_large += 1 + if p == "}": + cnt_bracket_large -= 1 + if cnt_bracket_small < 0: + cnt_bracket_small = 0 + new_s = new_s[:-1] + #print(new_s) + if cnt_bracket_mid < 0: + cnt_bracket_mid = 0 + new_s = new_s[:-1] + #print(new_s) + if cnt_bracket_large < 0: + cnt_bracket_large = 0 + new_s = new_s[:-1] + #print(new_s) + return new_s + + +def rewrite_pred(pred, gt_pred, gt_source, gt_value): + re_pred = pred + if is_valid_parentheses(pred).replace(" ", "") == gt_pred.replace(" ", ""): + return True, is_valid_parentheses(re_pred) + if "zmtarzm" in gt_value and gt_source.replace("#", gt_value).replace(" ", "") == gt_pred.replace(" ", ""): + return True, gt_source.replace("#", gt_value) + return False, re_pred + + +def vega_train_main(): + parser = argparse.ArgumentParser() + + # Required parameters + parser.add_argument("--model_name_or_path", default=None, type=str, required=True, + help="Path to pre-trained model: e.g. roberta-base") + parser.add_argument("--output_dir", default=None, type=str, required=True, + help="The output directory where the model predictions and checkpoints will be written.") + + # # Other parameters + parser.add_argument("--train_filename", default=None, type=str, + help="The train filename. Should contain the .jsonl files for this task.") + parser.add_argument("--dev_filename", default=None, type=str, + help="The dev filename. Should contain the .jsonl files for this task.") + parser.add_argument("--test_filename", default=None, type=str, + help="The test filename. Should contain the .jsonl files for this task.") + parser.add_argument("--max_source_length", default=590, type=int, # 400 + help="The maximum total source sequence length after tokenization. Sequences longer " + "than this will be truncated, sequences shorter will be padded.") + parser.add_argument("--max_target_length", default=240, type=int, # 350 + help="The maximum total target sequence length after tokenization. Sequences longer " + "than this will be truncated, sequences shorter will be padded.") + parser.add_argument("--do_train", action='store_true', + help="Whether to run training.") + parser.add_argument("--do_eval", action='store_true', + help="Whether to run eval on the dev set.") + parser.add_argument("--do_test", action='store_true', + help="Whether to run eval on the dev set.") + parser.add_argument("--do_function_test", action='store_true', + help="Whether to run eval on the subset of the dev set.") + parser.add_argument("--no_cuda", action='store_true', + help="Avoid using CUDA when available") + + parser.add_argument("--train_batch_size", default=8, type=int, + help="Batch size per GPU/CPU for training.") + parser.add_argument("--eval_batch_size", default=8, type=int, + help="Batch size per GPU/CPU for evaluation.") + parser.add_argument('--gradient_accumulation_steps', type=int, default=1, + help="Number of updates steps to accumulate before performing a backward/update pass.") + parser.add_argument("--learning_rate", default=6e-5, type=float, + help="The initial learning rate for Adam.") + parser.add_argument("--beam_size", default=1, type=int, + help="beam size for beam search") + parser.add_argument("--weight_decay", default=0.0, type=float, + help="Weight deay if we apply some.") + parser.add_argument("--adam_epsilon", default=1e-8, type=float, + help="Epsilon for Adam optimizer.") + parser.add_argument("--max_grad_norm", default=1.0, type=float, + help="Max gradient norm.") + parser.add_argument("--num_train_epochs", default=30, type=int, + help="Total number of training epochs to perform.") + parser.add_argument('--seed', type=int, default=20230420, + help="random seed for initialization") + + parser.add_argument("--mse_loss_weight", default=0.9, type=float, + help="Weight of Mean Square Error Loss.") + parser.add_argument("--ce_loss_weight", default=0.1, type=float, + help="Weight of Cross Entropy Loss.") + + # print arguments + args = parser.parse_args() + # set log + logging.basicConfig(format='%(asctime)s - %(levelname)s - %(name)s - %(message)s', + datefmt='%m/%d/%Y %H:%M:%S', level=logging.INFO) + # set device + device = torch.device("cuda" if torch.cuda.is_available() else "cpu") + args.n_gpu = torch.cuda.device_count() + args.device = device + logger.info("device: %s, n_gpu: %s", device, args.n_gpu) + + # Set seed + set_seed(args.seed) + + # make dir if output_dir not exist + if os.path.exists(args.output_dir) is False: + os.makedirs(args.output_dir) + args.model_name_or_path = folder + "/" + args.model_name_or_path + if args.train_filename: + args.train_filename = folder + "/" + args.train_filename + if args.dev_filename: + args.dev_filename = folder + "/" + args.dev_filename + if args.test_filename: + args.test_filename = folder + "/" + args.test_filename + args.output_dir = folder + "/" + args.output_dir + # build model + tokenizer = RobertaTokenizer.from_pretrained(args.model_name_or_path) + config = RobertaConfig.from_pretrained(args.model_name_or_path) + # import！！！you must set is_decoder as True for generation + config.is_decoder = True + encoder = RobertaModel.from_pretrained( + args.model_name_or_path, config=config) + + model = Seq2Seq(encoder=encoder, decoder=encoder, config=config, + mse_loss_weight=args.mse_loss_weight, ce_loss_weight=args.ce_loss_weight, + beam_size=args.beam_size, max_length=args.max_target_length, + sos_id=tokenizer.convert_tokens_to_ids([""])[0], eos_id=tokenizer.sep_token_id) + + logger.info("Training/evaluation parameters %s", args) + model.to(args.device) + + if args.n_gpu > 1: + # multi-gpu training + model = torch.nn.DataParallel(model) + + if args.do_train: + # Prepare training data loader + all_examples = read_examples(folder+"/"+args.train_filename, False) + train_examples = read_examples_no_bracket(folder+"/"+args.train_filename, False) + train_features = convert_examples_to_features( + train_examples, tokenizer, args, stage='train') + all_source_ids = torch.tensor( + [f.source_ids for f in train_features], dtype=torch.long) + all_exists = torch.tensor( + [f.exist for f in train_features], dtype=torch.float32) + all_target_ids = torch.tensor( + [f.target_ids for f in train_features], dtype=torch.long) + train_data = TensorDataset(all_source_ids, all_exists, all_target_ids) + train_sampler = RandomSampler(train_data) + train_dataloader = DataLoader(train_data, sampler=train_sampler, + batch_size=args.train_batch_size // args.gradient_accumulation_steps) + + # Prepare optimizer and schedule (linear warmup and decay) + no_decay = ['bias', 'LayerNorm.weight'] + optimizer_grouped_parameters = [ + {'params': [p for n, p in model.named_parameters() if not any(nd in n for nd in no_decay)], + 'weight_decay': args.weight_decay}, + {'params': [p for n, p in model.named_parameters() if any( + nd in n for nd in no_decay)], 'weight_decay': 0.0} + ] + optimizer = AdamW(optimizer_grouped_parameters, + lr=args.learning_rate, eps=args.adam_epsilon) + scheduler = get_linear_schedule_with_warmup(optimizer, + num_warmup_steps=int( + len(train_dataloader)*args.num_train_epochs*0.1), + num_training_steps=len(train_dataloader)*args.num_train_epochs) + + # Start training + logger.info("***** Running training *****") + logger.info(" Num examples = %d", len(all_examples)) + logger.info(" Batch size = %d", args.train_batch_size * + args.gradient_accumulation_steps) + logger.info(" Num epoch = %d", args.num_train_epochs) + + model.train() + eval_examples_all = read_examples(folder+"/"+args.dev_filename, False) + total_eval_all = len(eval_examples_all) + patience, best_acc, losses, dev_dataset = 0, 0, [], {} + for epoch in tqdm(range(args.num_train_epochs)): + # print(args.num_train_epochs) + + for idx, batch in enumerate(train_dataloader): + # print("##########Debug################") + # print(idx) + # print("###############Debug###########") + # if idx > 100: + # break + batch = tuple(t.to(device) for t in batch) + source_ids, exist, target_ids = batch + loss, _, _, mse_loss, ce_loss = model( + source_ids=source_ids, exist=exist, target_ids=target_ids) + + if args.n_gpu > 1: + loss = loss.mean() # mean() to average on multi-gpu. + if args.gradient_accumulation_steps > 1: + loss = loss / args.gradient_accumulation_steps + + losses.append(loss.item()) + loss.backward() + if len(losses) % args.gradient_accumulation_steps == 0: + # Update parameters + optimizer.step() + optimizer.zero_grad() + scheduler.step() + if len(losses) // args.gradient_accumulation_steps % 100 == 0: + logger.info("epoch {} step {} loss {}".format(epoch, + len( + losses)//args.gradient_accumulation_steps, + round(np.mean(losses[-100*args.gradient_accumulation_steps:]), 4))) + if args.do_eval: + # Eval model with dev dataset + if 'dev_loss' in dev_dataset: + eval_examples, eval_data = dev_dataset['dev_loss'] + else: + eval_examples = read_examples_no_bracket(folder+"/"+args.dev_filename) + eval_features = convert_examples_to_features( + eval_examples, tokenizer, args, stage='dev') + all_source_ids = torch.tensor( + [f.source_ids for f in eval_features], dtype=torch.long) + all_exists = torch.tensor( + [f.exist for f in eval_features], dtype=torch.float32) + all_target_ids = torch.tensor( + [f.target_ids for f in eval_features], dtype=torch.long) + eval_data = TensorDataset( + all_source_ids, all_exists, all_target_ids) + dev_dataset['dev_loss'] = eval_examples, eval_data + eval_sampler = SequentialSampler(eval_data) + eval_dataloader = DataLoader( + eval_data, sampler=eval_sampler, batch_size=args.eval_batch_size) + + logger.info("***** Running evaluation *****") + logger.info(" Num examples = %d", total_eval_all) + logger.info(" Batch size = %d", args.eval_batch_size) + + # Start Evaling model + model.eval() + eval_loss, tokens_num = 0, 0 + for batch in eval_dataloader: + batch = tuple(t.to(device) for t in batch) + source_ids, exist, target_ids = batch + + with torch.no_grad(): + _, loss, num, _, _ = model( + source_ids=source_ids, exist=exist, target_ids=target_ids) + eval_loss += loss.sum().item() + tokens_num += num.sum().item() + # Pring loss of dev dataset + model.train() + eval_loss = eval_loss / tokens_num + result = {'eval_ppl': round(np.exp(eval_loss), 5)} + for key in sorted(result.keys()): + logger.info(" %s = %s", key, str(result[key])) + logger.info(" " + "*" * 20) + + # Calculate mse + if 'dev_acc' in dev_dataset: + eval_examples, eval_data = dev_dataset['dev_acc'] + else: + eval_examples = read_examples_no_bracket(folder+"/"+args.dev_filename) + eval_examples = random.sample(eval_examples, int(len(eval_examples) / divide_number)) + eval_features = convert_examples_to_features( + eval_examples, tokenizer, args, stage='test') + all_source_ids = torch.tensor( + [f.source_ids for f in eval_features], dtype=torch.long) + eval_data = TensorDataset(all_source_ids) + dev_dataset['dev_acc'] = eval_examples, eval_data + + eval_sampler = SequentialSampler(eval_data) + eval_dataloader = DataLoader( + eval_data, sampler=eval_sampler, batch_size=args.eval_batch_size) + model.eval() + pp = [] + pr = [] + for batch in eval_dataloader: + batch = tuple(t.to(device) for t in batch) + source_ids = batch[0] + with torch.no_grad(): + preds, predicates = model(source_ids) + # convert ids to text + for pred, predicate in zip(preds, predicates): + t = pred[0].cpu().numpy() + #p = predicate[0].cpu().numpy() + p = predicate.float().item() + #print("ZM_Debug -- ppp: " + str(p)) + t = list(t) + #p = list(p) + tem_i = 0 + if 0 in t: + for my_i in range(len(t) - 1, 0, -1): + if t[my_i] != 0: + break + tem_i -= 1 + if tem_i < 0: + t = t[:tem_i] + text = tokenizer.decode( + t, clean_up_tokenization_spaces=False) + pp.append(text) + pr.append(p) + model.train() + + p_wrong_list = [] + v_wrong_list = [] + model_predicate = [] + groundtruth_predicate = [] + #edit_sim = 0.0 + total = int(total_eval_all / divide_number) + base_num = total - len(eval_examples) + EM = float(base_num) + EM_V = float(base_num) + EM_P = float(base_num) + cnt_v = 0 + cnt_p = 0 + cnt_iteration = 0 + for ref, gold in zip(zip(pp, pr), eval_examples): + cnt_iteration += 1 + pred = ref[0].strip() + predicate = ref[1] + #print("ZM_Debug -- predicate: " + str(predicate)) + if gold.property.strip().lower() != "nothing": + predicate = 1.0 + else: + pred = gold.source.strip() + if 1 not in gold.vec: + predicate = 0.0 + if 1 in gold.vec and gold.source.strip()[0] == '}': + predicate = 1.0 + if '#' in gold.source: + predicate = 0.0 + if 1 in gold.vec[-97:]: + predicate = 1.0 + gt_pred = gold.target.strip() + gt_predicate = gold.exist + + + if pred == gt_pred and int(round(predicate)) == int(round(gt_predicate)): + #print("Total correct, Inside this place") + EM = EM + 1.0 + EM_V = EM_V + 1.0 + EM_P = EM_P + 1.0 + else: + if pred == gt_pred: + EM_V = EM_V + 1.0 + else: + v_wrong_list.append([gold.filename, gold.funcname, gold.cpuname,\ + round(predicate), gt_predicate, pred, gt_pred]) + cnt_v += 1 + if int(round(predicate)) == int(round(gt_predicate)): + EM_P = EM_P + 1.0 + else: + cnt_p += 1 + p_wrong_list.append([gold.filename, gold.funcname, gold.cpuname,\ + round(predicate), gt_predicate, pred, gt_pred]) + + model_predicate.append(predicate) + groundtruth_predicate.append(gt_predicate) + # if len(pred.split(tokenizer.cls_token)) >= 2: + # if pred.split(tokenizer.cls_token)[0].strip() == gt_pred.split(tokenizer.cls_token)[0].strip(): + # EM_P += 1 + # if pred.split(tokenizer.cls_token)[1].strip() == gt_pred.split(tokenizer.cls_token)[1].strip(): + # EM_V += 1 + # MAE_P = mean_absolute_error( + # np.array(model_predicate), np.array(groundtruth_predicate)) + # MSE_P = mean_squared_error( + # np.array(model_predicate), np.array(groundtruth_predicate)) + # RMSE_P = np.sqrt(MSE_P) + dev_acc = round((100*EM/total), 2) + dev_acc_v = round((100*EM_V/total), 2) + dev_acc_p = round((100*EM_P/total), 2) + logger.info(" %s = %s " % ("Current Acc", str(dev_acc))) + #logger.info(" %s = %s "%("Current Edit sim",str(round(edit_sim/total, 2)))) + logger.info(" "+"*"*20) + logger.info(" %s = %s " % ("Current Acc V", str(dev_acc_v))) + #logger.info(" %s = %s "%("Current Edit sim",str(round(edit_sim/total, 2)))) + logger.info(" "+"*"*20) + logger.info(" %s = %s " % ("Current Acc P", str(dev_acc_p))) + #logger.info(" %s = %s "%("Current Edit sim",str(round(edit_sim/total, 2)))) + logger.info(" "+"*"*20) + # logger.info(" %s = %s " % + # ("Current MAE P", str(round(MAE_P, 2)))) + # #logger.info(" %s = %s "%("Current Edit sim",str(round(edit_sim/total, 2)))) + # logger.info(" "+"*"*20) + # logger.info(" %s = %s " % + # ("Current MSE P", str(round(MSE_P, 2)))) + # #logger.info(" %s = %s "%("Current Edit sim",str(round(edit_sim/total, 2)))) + # logger.info(" "+"*"*20) + # logger.info(" %s = %s " % + # ("Current RMSE P", str(round(RMSE_P, 2)))) + # #logger.info(" %s = %s "%("Current Edit sim",str(round(edit_sim/total, 2)))) + # logger.info(" "+"*"*20) + if dev_acc > best_acc: + #logger.info(" Best acc:%s",dev_acc) + #logger.info(" "+"*"*20) + best_acc = dev_acc + # Save best checkpoint for best bleu + output_dir = os.path.join( + args.output_dir, 'checkpoint-best-acc') + if not os.path.exists(output_dir): + os.makedirs(output_dir) + model_to_save = model.module if hasattr( + model, 'module') else model # Only save the model it-self + output_model_file = os.path.join( + output_dir, "pytorch_model.bin") + torch.save(model_to_save.state_dict(), output_model_file) + # with open(args.output_dir+"/p_valid_wrong.csv", 'w', encoding='utf-8', newline="") as fcsv2: + # writer = csv.writer(fcsv2) + # for wl in p_wrong_list: + # writer.writerow(wl) + # with open(args.output_dir+"/v_valid_wrong.csv", 'w', encoding='utf-8', newline="") as fcsv2: + # writer = csv.writer(fcsv2) + # for wl in v_wrong_list: + # writer.writerow(wl) + #print("ZM Debug--cnt_err_v: " + str(cnt_v)) + logger.info(" Best acc:%s", best_acc) + logger.info(" " + "*" * 20) + + + if args.do_test or args.do_function_test: + if os.path.exists(args.output_dir+"/result.jsonl"): + os.unlink(args.output_dir+"/result.jsonl") + checkpoint_prefix = 'checkpoint-best-acc/pytorch_model.bin' + output_dir = os.path.join(args.output_dir, checkpoint_prefix) + model_to_load = model.module if hasattr(model, 'module') else model + model_to_load.load_state_dict(torch.load(output_dir)) + + eval_examples_all = read_examples(args.test_filename, args.do_function_test) + eval_examples = read_examples_no_bracket(args.test_filename, args.do_function_test) + + + total_all = len(eval_examples_all) + base_test = total_all - len(eval_examples) + + + eval_features = convert_examples_to_features( + eval_examples, tokenizer, args, stage='test') + all_source_ids = torch.tensor( + [f.source_ids for f in eval_features], dtype=torch.long) + eval_data = TensorDataset(all_source_ids) + + eval_examples_idx_lis = [] + for ee in eval_examples: + eval_examples_idx_lis.append(ee.idx) + # Calculate mse + eval_sampler = SequentialSampler(eval_data) + eval_dataloader = DataLoader( + eval_data, sampler=eval_sampler, batch_size=args.eval_batch_size) + + model.eval() + pp = [] + pr = [] + start = time.time() + if not args.do_function_test: + print("Start Inferencing!") + else: + print("Start Function Test Inferencing!") + for batch in eval_dataloader: + batch = tuple(t.to(device) for t in batch) + source_ids = batch[0] + with torch.no_grad(): + preds, predicates = model(source_ids) + # convert ids to text + for pred, predicate in zip(preds, predicates): + t = pred[0].cpu().numpy() + #p = predicate[0].cpu().numpy() + p = predicate.float().item() + #print("ZM_Debug -- ppp: " + str(p)) + t = list(t) + tem_i = 0 + if 0 in t: + for my_i in range(len(t)-1, 0, -1): + if t[my_i] != 0: + break + tem_i -= 1 + if tem_i < 0: + t = t[:tem_i] + text = tokenizer.decode( + t, clean_up_tokenization_spaces=False) + pp.append(text) + pr.append(p) + end = time.time() + if not args.do_function_test: + print("Finished Inferencing: ", end - start, ' secs') + else: + print("Finished Function Test Inferencing: ", end - start, ' secs') + model.train() + EM = float(base_test) + EM_P = float(base_test) + EM_V = float(base_test) + p_wrong_list = [] + v_wrong_list = [] + edit_sim = 0.0 + total = total_all + res_dic = {} + + model_predicate = [] + groundtruth_predicate = [] + + for ref, gold in zip(zip(pp, pr), eval_examples): + pred = ref[0].strip() + predicate = ref[1] + if gold.property.strip().lower() != "nothing": + predicate = 1.0 + else: + pred = gold.source.strip() + if 1 not in gold.vec: + predicate = 0.0 + if 1 in gold.vec and gold.source.strip()[0] == '}': + predicate = 1.0 + if '#' in gold.source: + predicate = 0.0 + if 1 in gold.vec[-97:]: + predicate = 1.0 + #my_cls = tokenizer.decode([tokenizer.cls_token_id],clean_up_tokenization_spaces=False) + gt_pred = gold.target.strip() + gt_predicate = gold.exist + is_re = False + gt_value = gold.property + gt_source = gold.source + if pred == gt_pred and round(predicate) == gt_predicate: + EM += 1 + if pred == gt_pred and round(predicate) != gt_predicate: + p_wrong_list.append([gold.filename, gold.funcname, gold.cpuname, gold.idx, + round(predicate), gt_predicate, pred, gt_pred]) + if pred != gt_pred and round(predicate) == gt_predicate: + is_re, re_pred = rewrite_pred(pred, gt_pred, gt_source, gt_value) + if not is_re: + v_wrong_list.append([gold.filename, gold.funcname, gold.cpuname, gold.idx, + round(predicate), gt_predicate, pred, gt_pred]) + else: + pred = re_pred + EM += 1 + if pred != gt_pred and round(predicate) != gt_predicate: + v_wrong_list.append([gold.filename, gold.funcname, gold.cpuname, gold.idx, + round(predicate), gt_predicate, pred, gt_pred]) + p_wrong_list.append([gold.filename, gold.funcname, gold.cpuname, gold.idx, + round(predicate), gt_predicate, pred, gt_pred]) + tem_dic = {} + tem_dic["idx"] = gold.idx + tem_dic["vega_code"] = pred + tem_dic["ans_code"] = gt_pred + tem_dic["vega_pre"] = round(predicate) + tem_dic["ans_pre"] = gt_predicate + tem_dic["File"] = gold.filename + tem_dic["Func"] = gold.funcname + tem_dic["Module"] = gold.module + tem_dic["Target"] = gold.cpuname + res_dic[gold.idx] = tem_dic + + if pred == gt_pred: + EM_V += 1 + # else: + # print("TEST Wrong pred:", pred, " gt_pred:", gt_pred) + if round(predicate) == gt_predicate: + EM_P += 1 + model_predicate.append(predicate) + groundtruth_predicate.append(gt_predicate) + + # MAE_P = mean_absolute_error( + # np.array(model_predicate), np.array(groundtruth_predicate)) + # MSE_P = mean_squared_error( + # np.array(model_predicate), np.array(groundtruth_predicate)) + # RMSE_P = np.sqrt(MSE_P) + + dev_acc = round((100 * EM / total), 2) + dev_acc_v = round((100 * EM_V / total), 2) + dev_acc_p = round((100 * EM_P / total), 2) + # logger.info(" %s = %s " % ("Test Acc", str(dev_acc))) + # logger.info(" %s = %s " % ("Test Acc V", str(dev_acc_v))) + # logger.info(" %s = %s " % ("Test Acc P", str(dev_acc_p))) + # logger.info(" %s = %s "%("Test Edit sim",str(round(edit_sim/total, 2)))) + # logger.info(" %s = %s " % ("Test MAE P", str(round(MAE_P, 2)))) + # logger.info(" %s = %s " % ("Test MSE P", str(round(MSE_P, 2)))) + # logger.info(" %s = %s " % ("Test RMSE P", str(round(RMSE_P, 2)))) + # logger.info(" " + "*" * 20) + predictions = [] + + + with open(args.output_dir+"/result.jsonl", 'a') as f2: + for ee in eval_examples_all: + if ee.idx not in eval_examples_idx_lis: + dic = {} + dic["idx"] = ee.idx + dic["vega_code"] = ee.source.replace("zmtarzm", ee.cpuname) + dic["ans_code"] = ee.source.replace("zmtarzm", ee.cpuname) + dic["vega_pre"] = ee.exist + dic["ans_pre"] = ee.exist + dic["File"] = ee.filename + dic["Func"] = ee.funcname + dic["Module"] = ee.module + dic["Target"] = ee.cpuname + dic["Stable"] = "True" + else: + dic = {} + dic["idx"] = res_dic[ee.idx]["idx"] + dic["vega_code"] = res_dic[ee.idx]["vega_code"].replace("zmtarzm", ee.cpuname) + dic["ans_code"] = res_dic[ee.idx]["ans_code"].replace("zmtarzm", ee.cpuname) + dic["vega_pre"] = res_dic[ee.idx]["vega_pre"] + dic["ans_pre"] = res_dic[ee.idx]["ans_pre"] + dic["File"] = res_dic[ee.idx]["File"] + dic["Func"] = res_dic[ee.idx]["Func"] + dic["Module"] = res_dic[ee.idx]["Module"] + dic["Target"] = res_dic[ee.idx]["Target"] + dic["Stable"] = "False" + + json.dump(dic, f2) + f2.write('\n') + + + # with open(args.output_dir+"/p_wrong.csv", 'w', encoding='utf-8', newline="") as fcsv2: + # writer = csv.writer(fcsv2) + # for wl in p_wrong_list: + # writer.writerow(wl) + # with open(args.output_dir+"/v_wrong.csv", 'w', encoding='utf-8', newline="") as fcsv2: + # writer = csv.writer(fcsv2) + # for wl in v_wrong_list: + # writer.writerow(wl) + + +if __name__ == "__main__": + vega_train_main() \ No newline at end of file diff --git a/dataset/test.jsonl b/dataset/test.jsonl new file mode 100644 index 0000000000000000000000000000000000000000..041d3bfa699feb064d769c0e6499d5436c6901d3 --- /dev/null +++ b/dataset/test.jsonl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:7a4340dee03184ebefe8fe632a9395be6c267aef8eb744ee906806bc5b904492 +size 27576775 diff --git a/dataset/train.jsonl b/dataset/train.jsonl new file mode 100644 index 0000000000000000000000000000000000000000..2bcc80e7a57bb8179f6bc6af0de8925d3ce29d58 --- /dev/null +++ b/dataset/train.jsonl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:5b56b7cd69c8119cb41ef7eab286ca0f03b543621d32d62e15957d82cfce93f1 +size 84425254 diff --git a/dataset/valid.jsonl b/dataset/valid.jsonl new file mode 100644 index 0000000000000000000000000000000000000000..7729370681170c0d444598cbcd32abe868ebf46b --- /dev/null +++ b/dataset/valid.jsonl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:fd9a4240629a6b53e168a735c93207560b90c92aa54ac4f79ad290d0830e2ee1 +size 41300618 diff --git a/requirements.txt b/requirements.txt new file mode 100644 index 0000000000000000000000000000000000000000..ddf51dfd7f73b794a9f23341374fd512baf2369f --- /dev/null +++ b/requirements.txt @@ -0,0 +1,7 @@ +pathlib == 1.0.1 +tokenizers == 0.13.3 +transformers == 4.28.0 +torch == 2.0.1 +fuzzywuzzy == 0.18.0 +tqdm == 4.66.2 +python-Levenshtein == 0.25.1 diff --git a/run_fine_tuning.sh b/run_fine_tuning.sh new file mode 100644 index 0000000000000000000000000000000000000000..8c147b8bc7fb140f686123ee0c2ccc89e907bb21 --- /dev/null +++ b/run_fine_tuning.sh @@ -0,0 +1,16 @@ +# do train +python ./Scripts/UnixCoder/run_one_model.py \ + --do_train \ + --do_eval \ + --model_name_or_path ../../saved_models/UnixCoder \ + --train_filename ../../dataset/train.jsonl \ + --dev_filename ../../dataset/valid.jsonl \ + --output_dir ../../saved_models/New_Fine_Tuned_Model \ + --beam_size 4 \ + --train_batch_size 96 \ + --eval_batch_size 80 \ + --learning_rate 6e-5 \ + --num_train_epochs 50 \ + --mse_loss_weight 0.9 \ + --ce_loss_weight 0.1 +~ diff --git a/run_function_test.sh b/run_function_test.sh new file mode 100644 index 0000000000000000000000000000000000000000..30be3be2a91c58ba57f2e48259325b87507c0c23 --- /dev/null +++ b/run_function_test.sh @@ -0,0 +1,15 @@ + +# do test +python ./Scripts/UnixCoder/run_one_model.py \ + --do_function_test \ + --model_name_or_path ../../saved_models/UnixCoder \ + --test_filename ../../dataset/test.jsonl \ + --output_dir ../../saved_models/Fine_Tuned_Model \ + --beam_size 4 \ + --train_batch_size 256 \ + --eval_batch_size 256 \ + --learning_rate 6e-5 \ + --gradient_accumulation_steps 2 \ + --num_train_epochs 10 \ + --mse_loss_weight 0.9 \ + --ce_loss_weight 0.1 diff --git a/run_test.sh b/run_test.sh new file mode 100644 index 0000000000000000000000000000000000000000..cbb953b836fbcad9cac506bcf7fa2fab08242d42 --- /dev/null +++ b/run_test.sh @@ -0,0 +1,15 @@ + +# do test +python ./Scripts/UnixCoder/run_one_model.py \ + --do_test \ + --model_name_or_path ../../saved_models/UnixCoder \ + --test_filename ../../dataset/test.jsonl \ + --output_dir ../../saved_models/Fine_Tuned_Model \ + --beam_size 4 \ + --train_batch_size 256 \ + --eval_batch_size 256 \ + --learning_rate 6e-5 \ + --gradient_accumulation_steps 2 \ + --num_train_epochs 10 \ + --mse_loss_weight 0.9 \ + --ce_loss_weight 0.1 diff --git a/saved_models/Fine_Tuned_Model/checkpoint-best-acc/pytorch_model.bin b/saved_models/Fine_Tuned_Model/checkpoint-best-acc/pytorch_model.bin new file mode 100644 index 0000000000000000000000000000000000000000..d5b5997a6ddc5126eb0d3dec0e76b1ff62e49459 --- /dev/null +++ b/saved_models/Fine_Tuned_Model/checkpoint-best-acc/pytorch_model.bin @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:814d33f0ccb0c8336a4a82c03cd99ac1aa0d92187d7f5d21a9059b6a447b7bc7 +size 507267303 diff --git a/saved_models/New_Fine_Tuned_Model/.gitkeep b/saved_models/New_Fine_Tuned_Model/.gitkeep new file mode 100644 index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 diff --git a/saved_models/UnixCoder/README.md b/saved_models/UnixCoder/README.md new file mode 100644 index 0000000000000000000000000000000000000000..154df8298fab5ecf322016157858e08cd1bccbe1 --- /dev/null +++ b/saved_models/UnixCoder/README.md @@ -0,0 +1,3 @@ +--- +license: apache-2.0 +--- diff --git a/saved_models/UnixCoder/config.json b/saved_models/UnixCoder/config.json new file mode 100644 index 0000000000000000000000000000000000000000..e65703ddf947d05150f3ba637d8592d669caceaf --- /dev/null +++ b/saved_models/UnixCoder/config.json @@ -0,0 +1,28 @@ +{ + "architectures": [ + "RobertaModel" + ], + "attention_probs_dropout_prob": 0.1, + "bos_token_id": 0, + "classifier_dropout": null, + "eos_token_id": 2, + "gradient_checkpointing": false, + "hidden_act": "gelu", + "hidden_dropout_prob": 0.1, + "hidden_size": 768, + "initializer_range": 0.02, + "intermediate_size": 3072, + "layer_norm_eps": 1e-05, + "max_position_embeddings": 1026, + "model_type": "roberta", + "num_attention_heads": 12, + "num_hidden_layers": 12, + "output_past": true, + "pad_token_id": 1, + "position_embedding_type": "absolute", + "torch_dtype": "float32", + "transformers_version": "4.11.3", + "type_vocab_size": 10, + "use_cache": true, + "vocab_size": 51416 +} diff --git a/saved_models/UnixCoder/gitattributes.txt b/saved_models/UnixCoder/gitattributes.txt new file mode 100644 index 0000000000000000000000000000000000000000..64f23e0770da589d2949e1c24149405f5eda3d68 --- /dev/null +++ b/saved_models/UnixCoder/gitattributes.txt @@ -0,0 +1,28 @@ +*.7z filter=lfs diff=lfs merge=lfs -text +*.arrow filter=lfs diff=lfs merge=lfs -text +*.bin filter=lfs diff=lfs merge=lfs -text +*.bin.* filter=lfs diff=lfs merge=lfs -text +*.bz2 filter=lfs diff=lfs merge=lfs -text +*.ftz filter=lfs diff=lfs merge=lfs -text +*.gz filter=lfs diff=lfs merge=lfs -text +*.h5 filter=lfs diff=lfs merge=lfs -text +*.joblib filter=lfs diff=lfs merge=lfs -text +*.lfs.* filter=lfs diff=lfs merge=lfs -text +*.model filter=lfs diff=lfs merge=lfs -text +*.msgpack filter=lfs diff=lfs merge=lfs -text +*.onnx filter=lfs diff=lfs merge=lfs -text +*.ot filter=lfs diff=lfs merge=lfs -text +*.parquet filter=lfs diff=lfs merge=lfs -text +*.pb filter=lfs diff=lfs merge=lfs -text +*.pt filter=lfs diff=lfs merge=lfs -text +*.pth filter=lfs diff=lfs merge=lfs -text +*.rar filter=lfs diff=lfs merge=lfs -text +saved_model/**/* filter=lfs diff=lfs merge=lfs -text +*.tar.* filter=lfs diff=lfs merge=lfs -text +*.tflite filter=lfs diff=lfs merge=lfs -text +*.tgz filter=lfs diff=lfs merge=lfs -text +*.wasm filter=lfs diff=lfs merge=lfs -text +*.xz filter=lfs diff=lfs merge=lfs -text +*.zip filter=lfs diff=lfs merge=lfs -text +*.zstandard filter=lfs diff=lfs merge=lfs -text +*tfevents* filter=lfs diff=lfs merge=lfs -text diff --git a/saved_models/UnixCoder/merges.txt b/saved_models/UnixCoder/merges.txt new file mode 100644 index 0000000000000000000000000000000000000000..3f858fa9616e055207ec6c7dd516603eb4bc1b0c --- /dev/null +++ b/saved_models/UnixCoder/merges.txt @@ -0,0 +1,49626 @@ +#version: 0.2 +Ġ Ġ +ĠĠ ĠĠ +ĠĠ Ġ +ĠĠĠĠ ĠĠĠĠ +r e +i n +e r +o n +s t +a t +Ġ = +e n +t h +) ; +ĉ ĉ +o r +a r +a l +s e +ĠĠĠĠ ĠĠĠ +l e +c t +i on +d e +Ġ { +Ġ ( +u r +i s +a n +Ġ c +e t +i f +t e +- > +a m +u n +ĠĠĠĠĠĠĠĠ ĠĠĠ +Ġ f +Ġ th +/ / +- - +Ġ n +r o +c e +in g +re t +i t +Ġ t +ur n +en t +Ġ } +Ġ * +ret urn +Ġ p +( ) +in t +Ġ s +u e +s s +Ġ a +i d +l o +Ġ " +e d +i c +Ġ $ +p e +Ġ b +d d +c h +u l +Ġ m +at e +Ġth e +t r +u t +Ġ o +b b +ct ion +am e +st r +i l +e l +a g +g et +Ġ v +Ġ 0 +Ġ if +c k +Ġ ' +0 0 +ĠĠĠĠĠĠĠĠ ĠĠĠĠĠĠĠ +p t +* * +c o +e x +a d +i g +ĠĠĠĠ Ġ +u m +" , +i m +Ġ w +-- -- +Ġ re +Ġ d +I n +e s +Ġ return +er r +o l +y pe +l a +Ġ in +e w +th is +se t +un ction +r i +ĠĠĠĠĠĠĠĠ ĠĠĠĠĠĠĠĠ +o de +r a +u b +at a += = +: : +an d +o t +( " +i z +o m +Ġ S +i st +Ġt o +) ) +al ue +ĉĉ ĉ +R e +Ġ + +a b +Ġ T +u s +Ġ < +Ġ // +Ġ & +i le +at ion +a s +( ); +Ġ 1 +c on +h e +er t +a se +en d +v e +a p +Ġ C +bb bb +' , +ag e +e ct +iz e +u p +Ġ l +pt ion +ar am +ul t +e m +f f +Ġ : +o d +Ġth is +Ġ i +Ġc on +Ġ= = +l ic +Ġ ! +Ġ A +Ġ int +Ġ is +) , +ab le +Ġ st +C on +er s +al l +( ' +Ġf or +m ent +b j +Ġ h +S t +** ** +( $ +k e +str ing +Ġ e +Ġ err +E x +q u +o w +Ġ de +i r +Ġn ew +---- ---- +Ġ - +re n +f o +ul l +b u +ĉĉ ĉĉ +re s +t er +t o +te x +Ġ N +o id +ĠĠĠĠĠĠĠĠ ĠĠĠĠĠĠĠĠĠĠĠ +E R +Ġo f +ub lic +u ct +a ck +at h +v i +p aram +or t +Ġf unction +ra y +ar t +m p +Ġ I +in e +dd dd +N ame +Ġ g +tr ing +el se +Ġ D +Ġ P +n ame +l i +f unction +o p +Ġ! = +bj ect +f or +Ġ _ +f a +tex t +Ġ [ +str uct +im e +Ġ r +ex t +Ġt r +Ġ u +p ut +Ġ* / +Ġ M +d ata +00 00 +h t +q ue +in d +T ype +/ * +un t +p ro +an g +v er +Ġ ar +) ); +Ġ | +s c +I N +Ġ F +p ublic +o s +p a +lo ck +o ut +G et +" ); +Ġv ar +Ġb e +al se +o c +ss ert +E n +a in +de x +bbbb bbbb +Ġ else +a ch +ke y +ig n +) . +a dd +D e +i th +ren t +o ur +Ġ ex +r r +R E +i p +t ype +S tring +or d +un c +T o +Ġ 2 +at ch +ro m +te st +l en +v ent +3 2 +la ss +de v +V alue +Ġ& & +== == +Ġn ull +v ar +E rr +v al +P ro +Ġre s +Ġ and +' ] +que st +Ġ se +te m +Ġ > +O N +le ment +at ic +ro w +Ġ: = +S T +u re +Ġ B +s h +A T +vi ce +Ġv oid +Ġ string +e ss +Ġ % +our ce +on e +de f +y te +g th +l y +Ġc h +it y +o int +a k +[ ' +R es +a ct +p er +an ce +i re +Ġ ) +Ġ get +I d +Ġ . +Ġ L +E N +il d +a x +s er +e st +p ort +ig ht +f ig +i al +o f +m o +] , +L L +p on +v alue +f unc +el d +an s +Ġf alse +Ġv alue +**** **** +Ġtr ue +ce ption +Ġ= > +ri te +a y +o re +i ve +Ġp ro +re ate +p r +< / +co de +i eld +g s +for m +' ) +// / +ĠĠĠĠĠĠĠĠ Ġ +Ġn ame +lo c +l l +Ġ O +e th +ce ss +Err or +un d +i x +ar y +s ize +b o +u le +Ġn ot +fa ult +Ġ( ! += " +o st +I D +re ak +" ) +it ion +k en +ĠĠĠĠĠĠĠĠ ĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠ +D ata +ption s +" : +re ad +S et +re ss +Ġ an ++ + +ct ed +-------- -------- +Ġ R +i v +] ; +f ile +or y +L E +Ġ set +p p +A r +Ġ # +dddd dddd +at or +ess age +Ġ U +Ġ it +eth od +um ent +C om +O R +qu al +L ist +C h +Ġerr or +ad er +Ġn il +b er +f e +6 4 +A L +te d +Ġ un +la y +Ġ| | +Ġ on +Ġ G +Ex ception +Ġ ); +re g +] . +Ġ E +u st +( & +a il +} , +o g +Ġar ray +c l +Ġ x +Ġd ata +ri v +i de +Ġ or +p l +at us +l ag +_ _ +p h +Ġb o +S E +Ġa s +Ġw h +re d +Ġc ase +Ġc om +p le +ang e +S e +Ġ W +Ġt ype +Ġ @ +// // +I T +() , +n ew +v oid +lo g +ff er +D E +se d +r y +p tr +p ath +re f +() . +O bject +ur rent +K e +ap p +M A +U LL +tr i +ff set +Ġ j +o unt +d ate +@ @ +as k +Ġw ith +or m +pon se +a c +Ġth at +p ert +lo w +Ġcon st +. . +Ke y +il l +Con t +() ); +c ase +st atic +re am +li ent +co l +ar get +Ġw e +re e +S ize +y n +Ġu int +b ack +st ance +m l +ro up +at ed +i es +) { +Ġo ut +an t +Ġs h +bbbbbbbb bbbbbbbb +) : +co m +en er +F ile +er y +A t +con t +s ign +t p +a st +in fo +Ġ test +U n +Ġ H +Ġ y +he ck +ĠĠĠĠ ĠĠ +' ); +Ġ< < +A dd +A R +i b +B u +o k +len gth +o ck +() ) +0000 0000 +in k +l ist +r c +us er +o le +In fo +on g +Ġa ssert +C ol +Ġcon t +i o +ar d +Ġ al +bu te +Ġ 3 +p riv +" ; +ode l +Ġ ? +Ġd o +pe c +or k +tri bute +um ber +p ar +C T +le ct +ĠN ULL +a ve +Ġ V +T r +Ġf ile +Ġ end +Ġs ize +Ġl en +ow n +Ġ / +S er +e c +ers ion +l f +Ġ Ċ +Ġ In +T ime +s g +ar g +1 6 +==== ==== +Ġf rom +lo ad +u se +ĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠ ĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠ +Ġb u +O M +Ġ at +s um +N ode +\ \ +[ ] +pr int +ul d +if i +d er +ĠT he +Ġ Re +Ġres ult +g er +co unt +T est +en s +m ap +In dex +lag s +Ġ+ = +o uld +y st +l ine +S S +r ame +p os +H E +de d +id th +od ule +m d +I C +Ġ /* +: " +ĉĉ ĉĉĉ +a v +lo at +T ext +. _ +Ġ( $ +e p +in dex +yst em +s p +H e +Ġ 4 +it er +err or +1 0 +n e +Ġ k +St ate +pert y +A n +E vent +b e +bu f +mo ve +1 2 +st art +u te +E qual +P oint +M E +Ġ en +n ode +sign ed +in al +Ġa dd +I tem +ir st +b yte +] ) +Ġch ar +ind ow +con st +Ġ im +w rite +Ġ str +as h +an n +ri pt +S h +b ase +P ath +m and +a ke +A A +n o +pt y +res ult +st ate +Ġb reak +C lass +Ġ key +i ew +and le +th er +Con text +A N +co mp +pe cted +Ġo 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+at tr +n ull +ole an +Ġs er +ch e +U E +At tribute +P R +tr ans +Ġs pec +it le +L og +' s +int er +e b +i a +s pace +Ġ ro +f d +le d +P os +t ot +Ġc urrent +yte s +ann el +Ġst art +\ " +et er +d o +} ; +Ġin dex +lab el +d r +t x +u int +t tp +C E +anag er +i ct +Ġ> = +C K +Ġa pp +Ġm ethod +L e +Ġ us +Tr ans +p en +F or +pe ct +m atch +fo re +Len gth +(? : +m s +Ġo ptions +v ert +ut o +ag es +in s +che ck +Ġn e +W ith +p y +U S +Pro perty +n et +form at +re q +] [ +print f +Ġ} ; +Ġ 8 +ot o +N ot +g roup +ain er +Ġe vent +0 4 +ation s +at ure +Point er +M odel +ĠC on +en ame +b s +ting s +O n +con text +& & +b lock +C H +Ġc lass +ifi ed +> < +2 5 +at ive +I m +P tr +o bj +A pp +n d +St ream +Ġ z +a pt +Ġs ub +ic k +t ag +if ic +lob al +m ethod +ĠT HE +00 0 +c urrent +Ġst d +m at +ild er +un signed +M ethod +Ġ< / +ne ction +Ġ( ) +A l +Ġl ong +N ew +St atus +Ġ> > +Qu ery +Ġp re +l ate +B y +p o +)) , +c le +ic h +C lient +a ce +t arget +i able +f lags +Ġde f +Ġcon text +> ( +N D +tr y +i e +Ġre ad +m sg +Ġh as +ht tp +ile d +In stance +ens ion +S tr +ĠĠĠĠĠĠĠĠ ĠĠĠĠ +ri ption +pa rent +Ġtr y +able d +Ġsh ould +B e +ĠS et +Ġi tem +de sc +ust om +" ), +Ġh ave +al e +Bu ffer +Ġf ield +et ers +B lock +Ġl ine +() { +T he +Ġin put += ' +T able +app end +c lient +L A +Ġ log +tr ue +[ $ +W rite +sa fe +D ate +Ġin stance +( _ +ĠTh is +bu ffer +p ush +e qual +it or +is s +M L +m odule +m on +m essage +In ter +C reate +T Y +Equal s +Ġc all +j o +Re ad +que ue +D esc +co pe +IN T +Ġm ax +r iter +' ), +param s +G roup +ig h +m ode +St art +lay er +A g +Ġ" \ +c y +i ce +n ot +Ġn umber +c s +press ion +Ġ" "" +ref ix +en u +Ġ Ex +n er +O D +Ġp rint +et a +Cont ent +V AL +t il +M ode +Ġn um +M P +B U +O per +f ree +Ġm atch +S C +p age +ĠA r +te cted +Form at +l s +I G +Ġ lo +pon ent +======== ======== +in ue +P ar +ĠD e +h as +IN G +isp lay +Ġwh en +Ġ text +AT E +R eturn +E m +c md +Ġint er +Ġcon fig +U ser +il ename +S ub +bo ol +ad ers +W indow +id er +I O +Ġtr ans +I P +. +Ġp oint +c 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"rel": 2526, "40": 2527, ")->": 2528, "STAT": 2529, "Ġ(\"": 2530, "Types": 2531, "br": 2532, "Values": 2533, "Invalid": 2534, "Menu": 2535, "ĠFile": 2536, "ĠReturns": 2537, "','": 2538, "unlock": 2539, "Factory": 2540, "ĠCheck": 2541, "Option": 2542, "main": 2543, "ĠID": 2544, "assertEquals": 2545, "otal": 2546, "Vis": 2547, "exp": 2548, "Role": 2549, "Ġthere": 2550, "STR": 2551, "ĠType": 2552, "END": 2553, "oft": 2554, "Settings": 2555, "EE": 2556, "à¤": 2557, "Ac": 2558, "86": 2559, "fer": 2560, "FB": 2561, "Ġrow": 2562, "Ver": 2563, "session": 2564, "Cur": 2565, "ĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠ": 2566, "sb": 2567, "Ġframe": 2568, "CC": 2569, "Ġchild": 2570, "Obj": 2571, "ugh": 2572, "Ġport": 2573, "position": 2574, "ensor": 2575, "ground": 2576, "Task": 2577, "Writer": 2578, "cul": 2579, "Body": 2580, "Link": 2581, "card": 2582, "ĠK": 2583, "Ġmay": 2584, "erge": 2585, "False": 2586, "Ġdest": 2587, "ĠCh": 2588, "ification": 2589, "sn": 2590, "Ġcolumn": 2591, "Callback": 2592, "Ġdev": 2593, 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"Comp": 2661, "pop": 2662, "ixel": 2663, "WR": 2664, "ĠArray": 2665, "Ġfunc": 2666, "SA": 2667, "23": 2668, "ym": 2669, "Ġempty": 2670, "Names": 2671, "\"],": 2672, "ottom": 2673, "dddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddd": 2674, "any": 2675, "udio": 2676, "mutex": 2677, "Ġop": 2678, "ogle": 2679, "Ġmo": 2680, "Ġover": 2681, "mission": 2682, "Ġmod": 2683, "cket": 2684, "Ġgo": 2685, "cor": 2686, "SSERT": 2687, "03": 2688, "Top": 2689, "Document": 2690, "begin": 2691, "Reader": 2692, "address": 2693, "Ġnp": 2694, "ACE": 2695, "sec": 2696, "ä¸": 2697, ">>": 2764, "Tool": 2765, "button": 2766, "Store": 2767, "nil": 2768, "aster": 2769, "domain": 2770, "Ġfmt": 2771, "08": 2772, "script": 2773, "FS": 2774, "Ġ'/": 2775, "VM": 2776, "Decl": 2777, "ctl": 2778, "rate": 2779, "Local": 2780, "Ġcolor": 2781, "Ġreq": 2782, "Operation": 2783, "Kind": 2784, ")]": 2785, "headers": 2786, "while": 2787, "Ġ\"\"": 2788, "Connection": 2789, "Sign": 2790, "Parse": 2791, "ĠEn": 2792, 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12214, "XR": 12215, "ĠFoo": 12216, "Ġperformance": 12217, "Ġpv": 12218, "cular": 12219, "ç¬": 12220, "oned": 12221, "Aggregate": 12222, "Ġblack": 12223, "pectrum": 12224, "versions": 12225, "letter": 12226, "Ġepoch": 12227, "Ġquoted": 12228, "Ġxmlns": 12229, "Ġ10000": 12230, "IOS": 12231, "Conditional": 12232, "Ġinserted": 12233, "CodeMirror": 12234, "rollers": 12235, "CMP": 12236, "ĠONE": 12237, "ä¿¡": 12238, "ibr": 12239, "DOUBLE": 12240, "DisplayName": 12241, "Ġrpc": 12242, "204": 12243, "izations": 12244, "ĠDatabase": 12245, "Ġannotation": 12246, "MetaData": 12247, "ĠAudio": 12248, "Ġ$\"": 12249, "Implementation": 12250, "Balancer": 12251, "Ġpx": 12252, "outil": 12253, "Palette": 12254, "Ġcam": 12255, "ĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠ": 12256, "ality": 12257, "PubKey": 12258, "Ġcapacity": 12259, "ĠUs": 12260, "Indexes": 12261, "WINDOW": 12262, "INTERFACE": 12263, "Ġreduce": 12264, "DAT": 12265, "ĠCloud": 12266, "Unsigned": 12267, "Ġlisten": 12268, "设": 12269, "PropertyName": 12270, "Ġsegments": 12271, "ε": 12272, "around": 12273, "Ġnormalized": 12274, "fld": 12275, "UGIN": 12276, "Ġnn": 12277, "SPEED": 12278, "ĉĠĠĠĠĠĠĠĠĠĠĠ": 12279, "recursive": 12280, "ĠRoute": 12281, "DRM": 12282, "valueObject": 12283, "phrase": 12284, "Ill": 12285, "fatal": 12286, "æŃ": 12287, ",.": 12288, "includes": 12289, "OWN": 12290, "boundary": 12291, "ftp": 12292, "WEEK": 12293, "glob": 12294, "sas": 12295, "};\\": 12296, "Encoded": 12297, "offsetWidth": 12298, "unity": 12299, "Ġexceptions": 12300, "Needed": 12301, "Rank": 12302, "Ġcred": 12303, "GetName": 12304, "([^": 12305, "Ġdigit": 12306, "getOpcode": 12307, "Repo": 12308, "strcpy": 12309, "(&$": 12310, "EK": 12311, "syn": 12312, "vity": 12313, "Ġrendered": 12314, "vk": 12315, "Ġder": 12316, "Ġbank": 12317, "Apr": 12318, "Cipher": 12319, "]):": 12320, "0440": 12321, "åIJ¦": 12322, "IPv": 12323, "audit": 12324, "tfm": 12325, "')));": 12326, "ĠRaises": 12327, "packets": 12328, "Logs": 12329, "MessageBox": 12330, "icons": 12331, "cursively": 12332, "tour": 12333, "toEqual": 12334, "iggers": 12335, "Inputs": 12336, "izard": 12337, "ĠNAME": 12338, "Ġshouldn": 12339, "ĠProtoMessage": 12340, "Hard": 12341, "Ġincorrect": 12342, "//----------------------------------------------------------------": 12343, "ĠMOZ": 12344, "Finder": 12345, "BIG": 12346, "à¹": 12347, "ĠSys": 12348, "Mismatch": 12349, "ĠDomain": 12350, "algorithm": 12351, "anger": 12352, "ĠCPL": 12353, "Spe": 12354, ");}": 12355, "Ġfloor": 12356, "amps": 12357, "=\\": 12358, "orthand": 12359, "ĠLength": 12360, "Ġchunks": 12361, "atory": 12362, "ĠEquals": 12363, "Frequency": 12364, "While": 12365, "Ġgetattr": 12366, "α": 12367, "Nz": 12368, "inite": 12369, "Ġsmaller": 12370, "MY": 12371, "Ġincoming": 12372, "Scheduler": 12373, "ĠFS": 12374, "\"][\"": 12375, "Boundary": 12376, "Ġterms": 12377, "always": 12378, "ĠAss": 12379, "Delim": 12380, "ĠCalled": 12381, "Ġfew": 12382, "264": 12383, "CAN": 12384, "esting": 12385, "Ġaff": 12386, "Repeat": 12387, "joint": 12388, "Ġdash": 12389, "Ġaddition": 12390, "ĠÃ": 12391, "itable": 12392, "sched": 12393, "ĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠ": 12394, "Ġrem": 12395, "Ġ\\\"%": 12396, "bracket": 12397, "DELAY": 12398, "ĠSmallVector": 12399, "Ġmoment": 12400, "ups": 12401, "GetInstance": 12402, "REEN": 12403, "finished": 12404, "Ġ36": 12405, "minimum": 12406, "س": 12407, "ArrayList": 12408, "ĠGot": 12409, "ocab": 12410, "bbox": 12411, "aven": 12412, "misc": 12413, "NoError": 12414, "Router": 12415, "ĠTx": 12416, "JJ": 12417, "Ġfollowed": 12418, "ĠAnal": 12419, "COR": 12420, "EH": 12421, "Sources": 12422, "yB": 12423, "Ġcounts": 12424, "ĠGeneric": 12425, "OPCODE": 12426, "Ġboxes": 12427, "could": 12428, "ĠPosition": 12429, "ĠRow": 12430, "Timeval": 12431, "follow": 12432, "ining": 12433, "docker": 12434, "translation": 12435, "[][]": 12436, "PB": 12437, "Ġminor": 12438, "ĠCodeMirror": 12439, "DATETIME": 12440, "vq": 12441, "Ġgradient": 12442, "ĠassertFalse": 12443, "Ġminutes": 12444, "xi": 12445, "Ġcalc": 12446, "è¦ģ": 12447, "ĠMay": 12448, "aliases": 12449, "TextString": 12450, "Flash": 12451, "proj": 12452, "Ġdeferred": 12453, "ĠNdb": 12454, "ĠCV": 12455, "Ġassembly": 12456, "ĠWIN": 12457, "opaque": 12458, "dividual": 12459, "inside": 12460, "!--": 12461, "IQ": 12462, "isFunction": 12463, "dark": 12464, "Views": 12465, "ticks": 12466, "RESH": 12467, "ĠSDK": 12468, "thisfile": 12469, "?>": 12470, "large": 12471, "ANG": 12472, "dependencies": 12473, "ĠGuid": 12474, "CEPTION": 12475, "Solver": 12476, "udelay": 12477, "Hy": 12478, "Connector": 12479, "Ġlocked": 12480, "Ġ++$": 12481, "Ġsimilar": 12482, "Additional": 12483, "separ": 12484, "epi": 12485, "controls": 12486, "564": 12487, "INTERNAL": 12488, "uer": 12489, "1010": 12490, "beat": 12491, "Wx": 12492, "Ġoverwrite": 12493, "ĉĉĉĉĉĊ": 12494, "ĠOrder": 12495, "_*": 12496, "ĠCWE": 12497, "Ġask": 12498, "enerated": 12499, "Confirm": 12500, "INSTANCE": 12501, "Wa": 12502, "ghi": 12503, "SAMPLE": 12504, "WithError": 12505, "ADC": 12506, "Ġscratch": 12507, "Ġhappens": 12508, "ATOMIC": 12509, "Ġslash": 12510, "ternative": 12511, "ĠDefaults": 12512, "Ub": 12513, "AJ": 12514, "ĠVal": 12515, "ĠPerform": 12516, "Ġ**/": 12517, "STORE": 12518, "Boot": 12519, "prise": 12520, "aat": 12521, "Ġ])": 12522, "mkdir": 12523, "lations": 12524, "------------------------------------------------": 12525, "nfs": 12526, "DROP": 12527, "Pressed": 12528, "Tabs": 12529, "Glvb": 12530, "ĠInvoke": 12531, "Initialized": 12532, "queues": 12533, "POLL": 12534, "keywords": 12535, "chunks": 12536, "Ġbi": 12537, "$/,": 12538, "Dependencies": 12539, "FIN": 12540, "ingerprint": 12541, "EXPECT": 12542, "Review": 12543, "NAMESPACE": 12544, "palette": 12545, "(!(": 12546, "Ġstyles": 12547, "Ġconsider": 12548, "(?:[": 12549, "Ġgeneral": 12550, "Ġevaluate": 12551, "Aq": 12552, "DiscardUnknown": 12553, "ALPH": 12554, "Typed": 12555, ")==": 12556, "ÃŃ": 12557, "FEATURE": 12558, "CURRENT": 12559, "KB": 12560, "Ġiv": 12561, "Ġti": 12562, "OID": 12563, "square": 12564, "Ġgetter": 12565, "ĠPlayer": 12566, "æŀľ": 12567, "Na": 12568, "wall": 12569, "nth": 12570, "Ranges": 12571, "jit": 12572, "DAC": 12573, "sat": 12574, "125": 12575, "Ġkvm": 12576, "Slide": 12577, "air": 12578, "Union": 12579, "ETH": 12580, "Creature": 12581, "fallback": 12582, "çī": 12583, "ĠVec": 12584, "Ġhasattr": 12585, "ĠTemp": 12586, "rn": 12587, "elding": 12588, "122": 12589, "asList": 12590, "Ġsvc": 12591, "Ġ%(": 12592, "ERIC": 12593, "ĠMB": 12594, "Projection": 12595, "SUPPORTED": 12596, "Norm": 12597, "Accessible": 12598, "Ġ%%": 12599, "Ġreached": 12600, "pick": 12601, "ĠGoString": 12602, "RING": 12603, "<>(": 12604, "Ġmicro": 12605, "Ġimpl": 12606, "groupBox": 12607, "Ġhigher": 12608, "TING": 12609, "ĠMM": 12610, "cells": 12611, "ĉĉĉĉĉĉĉĉĉĉĉ": 12612, "ĠSocket": 12613, "Ġstrtolower": 12614, "************************": 12615, "Utf": 12616, "Minus": 12617, "Ġconcat": 12618, "constants": 12619, "jiffies": 12620, "pal": 12621, "alignment": 12622, "lparen": 12623, "Ġprovides": 12624, "startsWith": 12625, "did": 12626, "NCY": 12627, "SOR": 12628, "URIComponent": 12629, "^^": 12630, "credentials": 12631, "Ġtxt": 12632, "Ġdentry": 12633, "KG": 12634, "Ġdr": 12635, "Ġdirty": 12636, "Ġfurther": 12637, "osen": 12638, "Ġali": 12639, "ango": 12640, "Ġformatter": 12641, "Ġ%.": 12642, "ards": 12643, "autorest": 12644, ",\\\"": 12645, "Ġans": 12646, "compar": 12647, "rtw": 12648, "pairs": 12649, "Terminal": 12650, "CEE": 12651, "general": 12652, "inical": 12653, "ĠCore": 12654, "ĠNPT": 12655, ">());": 12656, "ker": 12657, "mw": 12658, "Ġaligned": 12659, "Fy": 12660, "å¼ı": 12661, "ele": 12662, "paused": 12663, "Upgrade": 12664, "('./": 12665, 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"rates": 12696, "ĠDel": 12697, "verts": 12698, "ĠFound": 12699, "Ġchecker": 12700, "Blank": 12701, "Ġvi": 12702, "Cells": 12703, "BackColor": 12704, "Lun": 12705, "Immediate": 12706, "ĠPur": 12707, "ĠBLOCK": 12708, "about": 12709, "vey": 12710, "ACL": 12711, "descr": 12712, "Ġcontained": 12713, "DQ": 12714, "fan": 12715, "urst": 12716, "Ġcomedi": 12717, "printStackTrace": 12718, "TREE": 12719, "emulate": 12720, "VERT": 12721, "Ġrev": 12722, "assertInstanceOf": 12723, "Locations": 12724, "Viewport": 12725, "indio": 12726, "Reserved": 12727, "åij": 12728, "Ġsnprintf": 12729, "ieve": 12730, "gfx": 12731, "ĠFont": 12732, "Ġdisplayed": 12733, "Ġvolatile": 12734, "specified": 12735, "Ġack": 12736, "Dao": 12737, "thenReturn": 12738, "ĠMulti": 12739, "Infinity": 12740, "ellow": 12741, "lavor": 12742, "Ġcompression": 12743, "Ġleaf": 12744, "Ġlatest": 12745, "StartTime": 12746, "Bg": 12747, "locations": 12748, "Listen": 12749, "Positions": 12750, "Arn": 12751, "\"/": 12752, "exceptions": 12753, "sidered": 12754, "StateException": 12755, ".*?": 12756, "removeChild": 12757, "ĠMBB": 12758, "ĠLib": 12759, "adget": 12760, "versal": 12761, "Ġvc": 12762, "POINTER": 12763, "Calculate": 12764, "Ġfamily": 12765, "ĠDT": 12766, "Capabilities": 12767, "xmit": 12768, "Ġsrv": 12769, "getFile": 12770, "ĠPrepare": 12771, "erce": 12772, "vY": 12773, ")],": 12774, "ĠBE": 12775, "Ġdifference": 12776, "bss": 12777, "cov": 12778, "writable": 12779, "DURATION": 12780, "ĠConfigure": 12781, "Ġfr": 12782, "childNodes": 12783, "016": 12784, "åĪ°": 12785, "ä": 12786, "Ġevalu": 12787, "mmetric": 12788, "gree": 12789, "Aug": 12790, "Ġ'&#": 12791, "_]+": 12792, "Ġels": 12793, "lencode": 12794, "ĠBody": 12795, "operations": 12796, "Ġ<<=": 12797, "./": 12798, "Ġjiffies": 12799, "ĠCOL": 12800, "Ġintent": 12801, "Ġapr": 12802, "DOC": 12803, "person": 12804, "nodeType": 12805, "Roles": 12806, "à¥į": 12807, "Bindings": 12808, "arity": 12809, "ObjC": 12810, "qb": 12811, "ĠTimeSpan": 12812, "ĠSQLException": 12813, "wrong": 12814, "gf": 12815, "Ġcertain": 12816, "Ġtid": 12817, "Ġretrieved": 12818, "inspect": 12819, "SuppressWarnings": 12820, "getRequest": 12821, "ĠPO": 12822, "Steps": 12823, "numpy": 12824, "Ġuuid": 12825, "Ġuc": 12826, "ENSION": 12827, "Ġmarked": 12828, "jpeg": 12829, "LAST": 12830, "levant": 12831, "âĢĶâĢĶâĢĶâĢĶ": 12832, "Hour": 12833, "Assertion": 12834, "ools": 12835, "xpath": 12836, "getM": 12837, "Jax": 12838, "initializer": 12839, "Geom": 12840, "directive": 12841, "Cols": 12842, "ï¼ļ": 12843, "Parallel": 12844, "Ġautog": 12845, "lcd": 12846, "upported": 12847, "EXIST": 12848, "getTarget": 12849, "Ġ(++": 12850, "STATS": 12851, "Ġaddrlen": 12852, "ĠEmpty": 12853, "WithContext": 12854, "Rune": 12855, "xor": 12856, "Ġprobe": 12857, "Arrow": 12858, ")&&(": 12859, "SID": 12860, "icates": 12861, "tras": 12862, "lements": 12863, "CAL": 12864, "LCB": 12865, "LR": 12866, "ĠDetermine": 12867, "inet": 12868, "ceeded": 12869, "->$": 12870, "TypeOf": 12871, "å·": 12872, "offs": 12873, "Ġ'=": 12874, "fence": 12875, "udev": 12876, "Ġexc": 12877, "setEnabled": 12878, "supports": 12879, "wdt": 12880, "Android": 12881, "ĠReport": 12882, "Ġ*>": 12883, "BUILD": 12884, "Damage": 12885, "Cb": 12886, "Pie": 12887, "COLUMN": 12888, "ĠATA": 12889, "Illum": 12890, "Spacing": 12891, "Threads": 12892, "ently": 12893, "IsEmpty": 12894, "inity": 12895, "Ġmanaged": 12896, "escaped": 12897, "oe": 12898, "Ġtrunc": 12899, "wiki": 12900, "Lexer": 12901, "\")){": 12902, "Ġthough": 12903, "Ġrecent": 12904, "delayed": 12905, "Ġgeometry": 12906, "éĶ": 12907, "COPY": 12908, "Ġdirective": 12909, "rans": 12910, "ircular": 12911, "Ġcrc": 12912, "Tail": 12913, "thumb": 12914, "Ġpositions": 12915, "ĠParser": 12916, "Canonical": 12917, "GetCurrent": 12918, "PrivateKey": 12919, "Ġhaving": 12920, "ki": 12921, "ĠpostIndex": 12922, ",!": 12923, "Ġsolid": 12924, "srv": 12925, "Ġconflict": 12926, "getChild": 12927, "ĠPRO": 12928, "bra": 12929, "Ġtv": 12930, "cod": 12931, "manifest": 12932, "Bra": 12933, "xffffffff": 12934, "Cred": 12935, "éĿ": 12936, "Ġletter": 12937, "needs": 12938, "allocated": 12939, "ĠEOF": 12940, "PageToken": 12941, "mii": 12942, "+)": 12943, "Cleanup": 12944, "Ġ\"__": 12945, "StringRef": 12946, "Uses": 12947, "EXPORT": 12948, "die": 12949, "but": 12950, "Ġnewline": 12951, "*/,": 12952, "VG": 12953, "Reverse": 12954, "xhr": 12955, "Ġwi": 12956, "nor": 12957, "å±": 12958, "ALLOW": 12959, "Linux": 12960, "qd": 12961, "training": 12962, "Coords": 12963, "ĠASN": 12964, "ĠHtml": 12965, "kobj": 12966, "Ġlooking": 12967, "Highlighter": 12968, "nid": 12969, "ĠPORT": 12970, "callable": 12971, "isor": 12972, "ĠArgumentException": 12973, "ĠErrInvalid": 12974, "eh": 12975, "notifier": 12976, "METHODIMP": 12977, "Physics": 12978, "ROUND": 12979, "MaxLength": 12980, "stitution": 12981, "ZT": 12982, "clusion": 12983, "currence": 12984, "OCOL": 12985, "Ġtun": 12986, "NodeType": 12987, "Ġoperands": 12988, "choice": 12989, "Git": 12990, "ĠJust": 12991, "Curr": 12992, "received": 12993, "åıĤ": 12994, "()];": 12995, "Ġrsa": 12996, "gap": 12997, "GX": 12998, "Ġ'('": 12999, "pio": 13000, "}],": 13001, "ĠCor": 13002, "ĠNaN": 13003, "Ġjump": 13004, "Strict": 13005, "ãĥ¼": 13006, "Ack": 13007, "Ġ{})": 13008, "IMPORT": 13009, "Dummy": 13010, "Ġprototype": 13011, "ddr": 13012, "lsl": 13013, "Please": 13014, "Ġfour": 13015, "\"]',": 13016, "ADE": 13017, ":\"[": 13018, "shown": 13019, "Ġinc": 13020, "Like": 13021, "tracker": 13022, "ecause": 13023, "tgt": 13024, "urlencode": 13025, ".\";": 13026, "еÑĢ": 13027, "ĠIX": 13028, "Ġaway": 13029, "ĠUnsupported": 13030, "currentTime": 13031, "Ġgit": 13032, "è¿Ķ": 13033, "Ġata": 13034, "Pause": 13035, "Numbers": 13036, "ĠArrays": 13037, "shost": 13038, "ĠOb": 13039, "Unary": 13040, "BIND": 13041, "Ġends": 13042, "Given": 13043, "radeon": 13044, "Ġcond": 13045, "ĠNVPTX": 13046, "Px": 13047, "charCodeAt": 13048, "getColumn": 13049, "fcp": 13050, "pwm": 13051, "TASK": 13052, "Ġsubprocess": 13053, "CRYPT": 13054, "')))": 13055, "GI": 13056, "icky": 13057, "æłĩ": 13058, "ored": 13059, "horizontal": 13060, "alformed": 13061, "trap": 13062, "getX": 13063, "ĠMember": 13064, "micro": 13065, "DiskConfiguration": 13066, "PID": 13067, "els": 13068, "Ġsep": 13069, "ĠTrack": 13070, "udent": 13071, "issues": 13072, "Ġopened": 13073, "ĠAfter": 13074, "Ġdepending": 13075, "Correct": 13076, "Critical": 13077, "getElementsByTagName": 13078, "Ġsubmit": 13079, "gateway": 13080, "ĠTransaction": 13081, "Shortcut": 13082, "Elt": 13083, "tics": 13084, "Thumb": 13085, "txq": 13086, "Ġprocessor": 13087, "Deleter": 13088, "Allocator": 13089, "rivers": 13090, "Ġfilled": 13091, "GetHashCode": 13092, "ĠTransform": 13093, "Edges": 13094, "maybe": 13095, "Clicked": 13096, "Ġmanifest": 13097, "FJ": 13098, "thers": 13099, "MLElement": 13100, "hu": 13101, "RAW": 13102, "Cli": 13103, "completed": 13104, "Else": 13105, "ĠOver": 13106, "Ġvertical": 13107, "Pull": 13108, "VU": 13109, "Bounding": 13110, "Ġpipeline": 13111, "ĠIDC": 13112, "Sid": 13113, "tar": 13114, "Ġrespect": 13115, "compat": 13116, "++];": 13117, "Ġlogical": 13118, "ĠIterator": 13119, "XXXXXXXX": 13120, "çĤ": 13121, ":\"+": 13122, "2015": 13123, "mlme": 13124, "extends": 13125, "apis": 13126, "ĠOPT": 13127, "Ġslow": 13128, "ĠHashSet": 13129, "Receiver": 13130, "ĠStruct": 13131, "alog": 13132, "Datum": 13133, "IsNil": 13134, "'=>$": 13135, "PPC": 13136, "Templates": 13137, "Did": 13138, "roles": 13139, "dispatcher": 13140, "Invocation": 13141, "0002": 13142, "ο": 13143, "RTL": 13144, "Ġcd": 13145, "ĠXFS": 13146, "UART": 13147, "QUOT": 13148, "Mk": 13149, "appendTo": 13150, "riendly": 13151, "PUSH": 13152, "Ġprediction": 13153, "Ġsatis": 13154, "Devices": 13155, "Dto": 13156, "Ġlittle": 13157, "Ġwho": 13158, "Fx": 13159, "pended": 13160, "SLOT": 13161, "\"&&": 13162, "请": 13163, "ĠMac": 13164, "Ġioutil": 13165, "ĠIntrinsic": 13166, "Accounts": 13167, "Ġwl": 13168, "pology": 13169, "ãĤĴ": 13170, "started": 13171, "Fallback": 13172, "è´": 13173, "Ġconsidered": 13174, "forum": 13175, "dword": 13176, "ĠRegion": 13177, "ioaddr": 13178, "Inc": 13179, "ĠStorage": 13180, "Ġperformed": 13181, "ranges": 13182, "orientation": 13183, "ãĤĭ": 13184, "Ġ------------------------------------------------------------------------": 13185, "Ġ):": 13186, "ов": 13187, "ĠUSE": 13188, "cipe": 13189, "TypeError": 13190, "Ġgithub": 13191, "scaled": 13192, "unix": 13193, "Ġsqrt": 13194, "Ġls": 13195, "Ring": 13196, "rozen": 13197, "gog": 13198, "ĠHttpResponse": 13199, "Workspace": 13200, "Dash": 13201, "ĠStyle": 13202, "exact": 13203, "itecture": 13204, "removed": 13205, "hm": 13206, "nat": 13207, "meth": 13208, "VI": 13209, "003": 13210, "bG": 13211, "arily": 13212, "ĠJob": 13213, "Hw": 13214, "MK": 13215, "ĉĉĉĉĉĠĠĠĠĠĠ": 13216, "ĠEncoding": 13217, "combo": 13218, "etermin": 13219, "MAGIC": 13220, "umask": 13221, "permissions": 13222, "Vs": 13223, "ology": 13224, "graphics": 13225, "enqueue": 13226, "Ġha": 13227, "tg": 13228, "aged": 13229, "ĠATTR": 13230, "regional": 13231, ")])": 13232, "rror": 13233, "Ġkill": 13234, "ĠSW": 13235, "rtype": 13236, "mvm": 13237, "optim": 13238, ";\"": 13239, "/);": 13240, "YPTO": 13241, "SING": 13242, "å¸": 13243, ")*(": 13244, "ZZ": 13245, "tif": 13246, "Declar": 13247, "*.": 13248, "Ġ29": 13249, "streams": 13250, "getSub": 13251, "ĠPublic": 13252, "pValue": 13253, "BQU": 13254, "jump": 13255, "Ġpull": 13256, "rew": 13257, "IsNot": 13258, "Tokenizer": 13259, "###": 13260, "authorized": 13261, "Physical": 13262, "Ġcurrency": 13263, "Ġcompiled": 13264, "RQ": 13265, "Encryption": 13266, "erral": 13267, "ailability": 13268, "Rotate": 13269, "*\\\\": 13270, "ĠCar": 13271, "Alive": 13272, "guard": 13273, "Article": 13274, "Bank": 13275, "pmu": 13276, "&&\"": 13277, "Ġperson": 13278, ";\",": 13279, "STY": 13280, "Evalu": 13281, "Connections": 13282, "/\\\\": 13283, "ComponentModel": 13284, "expire": 13285, "Ġautogenerated": 13286, "----------------------------------------------------------------------": 13287, "Ġconsumer": 13288, "Lite": 13289, "ĠProgram": 13290, "ĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠ": 13291, "Ġkv": 13292, "VX": 13293, "picture": 13294, "modes": 13295, "ffffffff": 13296, "Black": 13297, "ĠHelper": 13298, "Ġaverage": 13299, "Ġordered": 13300, "foreign": 13301, "PCL": 13302, "nsI": 13303, "Illuminate": 13304, "isEqualTo": 13305, "ĠJOIN": 13306, "NM": 13307, "å¦": 13308, "0435": 13309, "Ġphysical": 13310, "Leave": 13311, "Supp": 13312, "ĠBr": 13313, "ctrine": 13314, "ĉĉĉĉĉĉĠ": 13315, "STA": 13316, "ilon": 13317, "ĠIF": 13318, "VARI": 13319, "uD": 13320, "demo": 13321, "ĠPass": 13322, "ĠScan": 13323, "Ġrectangle": 13324, "Ġvirt": 13325, "Ġ>',": 13326, "truncate": 13327, "ETCH": 13328, "inp": 13329, "uplex": 13330, "Distribution": 13331, "Ġdefines": 13332, "RELEASE": 13333, "Ġmime": 13334, "Ġbuttons": 13335, "Ġbas": 13336, "ĠALL": 13337, "Ġ---": 13338, "Configs": 13339, "helpers": 13340, "=-=-": 13341, "Picture": 13342, "Ġreferenced": 13343, "mh": 13344, "设置": 13345, "Uid": 13346, "Ġzoom": 13347, "Ġbackup": 13348, "firmware": 13349, "pmd": 13350, "Ġtip": 13351, "broadcast": 13352, "HRESULT": 13353, "Ġcols": 13354, "relax": 13355, "Freq": 13356, "See": 13357, "Circle": 13358, "midi": 13359, "390": 13360, "ĠCALL": 13361, "Seed": 13362, "nowled": 13363, "ĠValues": 13364, "Leaf": 13365, "icmp": 13366, "energy": 13367, "Eula": 13368, "Outer": 13369, "Ġcells": 13370, "Ñĸ": 13371, "ĠDown": 13372, "xuIC": 13373, "BLIC": 13374, "Ġglobals": 13375, "Ġphp": 13376, "Ġinsn": 13377, "ĠAArch": 13378, "Ass": 13379, "pq": 13380, "Wl": 13381, "deps": 13382, "ĠFF": 13383, "REV": 13384, "weep": 13385, "Scaling": 13386, "Skin": 13387, "Throwable": 13388, "Categories": 13389, "еÑĤ": 13390, "('',": 13391, "DataSet": 13392, "Ġdeepcopy": 13393, "Major": 13394, "Ġ2000": 13395, "notes": 13396, "ĠCancellationToken": 13397, "EEEE": 13398, "ä¸ĭ": 13399, "compression": 13400, "Ġsyn": 13401, "AES": 13402, "UPT": 13403, "CURRENCY": 13404, "minute": 13405, "slider": 13406, "Ġngx": 13407, "002": 13408, "AO": 13409, "unted": 13410, "TAIL": 13411, "BOOST": 13412, "rhs": 13413, "OPERAT": 13414, "sessment": 13415, "ĠHE": 13416, "ViewById": 13417, "Tester": 13418, "pipeline": 13419, "Hd": 13420, "bv": 13421, "Ġlevels": 13422, "ĠValidation": 13423, "ĠÑģ": 13424, "efx": 13425, "ract": 13426, "ĠQual": 13427, "æĺ¯åIJ¦": 13428, "ĠImmutable": 13429, "IVER": 13430, "ĠRTC": 13431, "Ġ$(\"#": 13432, "Ġcompressed": 13433, "symbols": 13434, "ĠvalueObject": 13435, "SOCKET": 13436, "Decimals": 13437, "inym": 13438, "getLength": 13439, "ĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĊ": 13440, "inymce": 13441, "qh": 13442, "shop": 13443, "listeners": 13444, "tell": 13445, "Generation": 13446, "ĠBut": 13447, "circle": 13448, "ĠLock": 13449, "æĸ¹": 13450, "/////": 13451, "bfd": 13452, "bk": 13453, "\":{": 13454, "semble": 13455, "imap": 13456, "dylib": 13457, "InvariantCulture": 13458, "ERS": 13459, "compiled": 13460, "notice": 13461, "Ġmatcher": 13462, "htable": 13463, "Ġcontrols": 13464, "REPL": 13465, "Jobs": 13466, "Half": 13467, "Stride": 13468, "Qualified": 13469, "Ax": 13470, "PSB": 13471, "=\"#": 13472, "covered": 13473, "ROLL": 13474, "sidebar": 13475, "Ġinterest": 13476, "Square": 13477, "Ġ\"@": 13478, "elt": 13479, "Digit": 13480, "DEN": 13481, "SCALE": 13482, "ike": 13483, "ĠVAR": 13484, "ior": 13485, "ergy": 13486, "icol": 13487, "ĠMat": 13488, "fsm": 13489, "Ġgeneration": 13490, "ĠLookup": 13491, "references": 13492, "TZ": 13493, "PROCESS": 13494, "Undo": 13495, "ĠCollections": 13496, "Ġfname": 13497, "mib": 13498, "erp": 13499, "SDK": 13500, "ĠSwift": 13501, "Ġshutdown": 13502, "Ġhours": 13503, "pcs": 13504, "Ġapplies": 13505, "JNI": 13506, "sts": 13507, "CLU": 13508, "dependency": 13509, "Ġterminal": 13510, "ifec": 13511, "Ġquestion": 13512, "istence": 13513, "Sector": 13514, "beans": 13515, "describe": 13516, "ablish": 13517, "legend": 13518, "Purifier": 13519, "DEC": 13520, "æĸ°": 13521, "éĻ¤": 13522, "AUDIO": 13523, "CompactTextString": 13524, "Roll": 13525, "ĠDoc": 13526, "å¹": 13527, "[@": 13528, "Ġaux": 13529, "Recommended": 13530, "abcdefghi": 13531, "ĠConnect": 13532, "ticket": 13533, "Ġinspect": 13534, "ĠJump": 13535, "gradient": 13536, "Ġsink": 13537, "``.": 13538, "terminate": 13539, "correlation": 13540, "Ġvectors": 13541, "Pairs": 13542, "âµ": 13543, "pel": 13544, "Since": 13545, "ĠProduct": 13546, "Ġ\":\"": 13547, "Ġ180": 13548, "Will": 13549, "coverage": 13550, "implify": 13551, "MAT": 13552, "Ġdvb": 13553, "pathname": 13554, "AAC": 13555, "Ġguid": 13556, "endswith": 13557, "pring": 13558, "rgba": 13559, "{}{": 13560, "Jump": 13561, "Ġ\",\",": 13562, "istributed": 13563, "getConfig": 13564, "Ġunix": 13565, "224": 13566, "Creator": 13567, "ĠHD": 13568, "Ġactivation": 13569, "Ġvalidator": 13570, "Balance": 13571, "Ġ123": 13572, "çĤ¹": 13573, "è¿ĶåĽŀ": 13574, "matching": 13575, "ĠTRACE": 13576, "rection": 13577, "pline": 13578, "parm": 13579, "Streamer": 13580, "addChild": 13581, "editable": 13582, "avor": 13583, "åĩº": 13584, "ifecycle": 13585, "dz": 13586, "lastic": 13587, "Ġblue": 13588, "ĠTab": 13589, "Tech": 13590, "Ray": 13591, "ÛĮ": 13592, "Ġв": 13593, "æĪ·": 13594, "reet": 13595, "ĠEnter": 13596, "(\\\"": 13597, "][\"": 13598, "Ġ33": 13599, "ĠCLASS": 13600, "getAs": 13601, "Ġcompatible": 13602, "Ġcanonical": 13603, "getCurrentToken": 13604, "Ġbbox": 13605, "ĠEE": 13606, "Starting": 13607, "snap": 13608, "mnt": 13609, "CRC": 13610, "sink": 13611, "strtolower": 13612, "Ġwallet": 13613, "lipse": 13614, "ĠBegin": 13615, "AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA": 13616, "Best": 13617, "longDate": 13618, "ecc": 13619, "Ġ(),": 13620, "Locator": 13621, "Attack": 13622, "_{": 13623, "ĠdefaultValue": 13624, "Hero": 13625, "erv": 13626, "ĠTWO": 13627, "åĽ¾": 13628, "Ġ__('": 13629, "Ġmoved": 13630, "Catch": 13631, "GetObject": 13632, "Fee": 13633, "Backward": 13634, "wave": 13635, "Ġ127": 13636, "reqHeaders": 13637, "Ġexecutable": 13638, "ĠCA": 13639, "ferred": 13640, "Mass": 13641, "Defs": 13642, "monthNames": 13643, "FQ": 13644, "Ġaxes": 13645, "mad": 13646, "quad": 13647, "ircu": 13648, "TRANSITION": 13649, "Gra": 13650, "isNaN": 13651, "toInt": 13652, "NewLine": 13653, "ĠGiven": 13654, "899": 13655, "Counts": 13656, "Ġlogs": 13657, "Ġpytest": 13658, "ĠBN": 13659, "ĠretVal": 13660, "IEEE": 13661, "WhiteSpace": 13662, "markup": 13663, "WK": 13664, "Incoming": 13665, "Suspend": 13666, "ĠSIG": 13667, "smtp": 13668, "Ġgt": 13669, "IDLE": 13670, "skin": 13671, "Duplicate": 13672, "dic": 13673, "llx": 13674, "ç¤": 13675, "outdent": 13676, "ĠSER": 13677, "ENOENT": 13678, "ĠASCII": 13679, "Ġearly": 13680, "kele": 13681, "LayoutPanel": 13682, "Ġft": 13683, "Dirs": 13684, "Nj": 13685, "MARY": 13686, "NP": 13687, "udp": 13688, "Magic": 13689, "redis": 13690, "Poll": 13691, "RefCount": 13692, "ĠMEM": 13693, ":\"#": 13694, "Servlet": 13695, "Ġdie": 13696, "EXCEPTION": 13697, "Ġheld": 13698, "Ġopening": 13699, "ializable": 13700, "ĠCallingConvention": 13701, "Ġmag": 13702, "DoesNot": 13703, "errorCode": 13704, "Outcome": 13705, "Ġprompt": 13706, "cases": 13707, "Ġacross": 13708, "Ġbean": 13709, "%=": 13710, "armon": 13711, "Ġcomma": 13712, "iommu": 13713, "Vi": 13714, "cms": 13715, "keyboard": 13716, "allocator": 13717, "ĠlocalVar": 13718, "mmap": 13719, "']]": 13720, "IntOverflow": 13721, "UNLOCK": 13722, "getLast": 13723, "ĠArr": 13724, "Sorted": 13725, "Ġdocs": 13726, "Sensor": 13727, "ĠSplit": 13728, "Scanner": 13729, "Ticks": 13730, "OLEAN": 13731, "few": 13732, "ShowIn": 13733, "BOT": 13734, "ĠTEXT": 13735, "Caller": 13736, "Deprecated": 13737, "1234567890": 13738, "ĠPC": 13739, "ĠMPI": 13740, "HEIGHT": 13741, "normalized": 13742, "Ġplaceholder": 13743, "TAB": 13744, "ĠErrIntOverflow": 13745, "errain": 13746, "ĠMerge": 13747, "=\",": 13748, "аÑĤ": 13749, "Frag": 13750, "decrypt": 13751, "RGBA": 13752, "Implicit": 13753, "ĠACT": 13754, "Setter": 13755, "dg": 13756, "Python": 13757, "Been": 13758, "prio": 13759, "HL": 13760, "dbc": 13761, "Animator": 13762, "Tooltip": 13763, "Principal": 13764, ")(),": 13795, "dj": 13796, "åŀ": 13797, "Ġhorizontal": 13798, "à¯": 13799, "RP": 13800, "routes": 13801, "There": 13802, "ĠMe": 13803, "210": 13804, "Ġ45": 13805, "Charset": 13806, "GG": 13807, "Wrong": 13808, "cI": 13809, "ĠUnit": 13810, "æĹ¥": 13811, "Ġtooltip": 13812, "Deferred": 13813, "ĠToString": 13814, "Ġign": 13815, "ĠRO": 13816, "LOOP": 13817, "CBC": 13818, "Ġslide": 13819, "ĠREAD": 13820, "Ġsctp": 13821, "(@\"": 13822, "Ġarm": 13823, "GetData": 13824, "اÙĦ": 13825, "BK": 13826, "å¦Ĥ": 13827, "DES": 13828, "abling": 13829, "sliding": 13830, "yo": 13831, "Ġlaunch": 13832, "ĠLI": 13833, "Episode": 13834, "pixels": 13835, "versed": 13836, "Optim": 13837, "OfType": 13838, "ĠIDs": 13839, "Ġfraction": 13840, "Closure": 13841, "lz": 13842, "thr": 13843, "Aw": 13844, "Assembler": 13845, "})\\": 13846, "ĠApi": 13847, "respond": 13848, "subscriptions": 13849, ".+": 13850, "Checksum": 13851, "HostCaching": 13852, "Vm": 13853, "undo": 13854, "integr": 13855, "DEPTH": 13856, "sense": 13857, "Question": 13858, "hist": 13859, "ãĢģ": 13860, "åıĤæķ°": 13861, "illisecond": 13862, "avigate": 13863, "Triangle": 13864, "ancestor": 13865, "()\",": 13866, "ConfigureAwait": 13867, "Ġstores": 13868, "indexes": 13869, "Ġ63": 13870, "eof": 13871, "BigEndian": 13872, "marshaller": 13873, "Ġplease": 13874, "otor": 13875, "Ïģ": 13876, "ĠTC": 13877, "Ġaccepts": 13878, "________________": 13879, ";&": 13880, "idence": 13881, "ĠSync": 13882, "å½ķ": 13883, "TryGetValue": 13884, "Parsed": 13885, "Persoon": 13886, "PACKET": 13887, "nu": 13888, "also": 13889, "@@@@@@@": 13890, "ection": 13891, "Ġrp": 13892, "DESCRIPT": 13893, "getWidth": 13894, "ĠUUID": 13895, "Ġroll": 13896, "alive": 13897, "COMMENT": 13898, "Ym": 13899, "Ġpf": 13900, "Ġ//$": 13901, "ä¿¡æģ¯": 13902, "jan": 13903, "çŃ": 13904, "ĠProtocol": 13905, "Ġrendering": 13906, "Managed": 13907, "Ġexponent": 13908, "Ġpassing": 13909, "æŁ¥": 13910, "Ġiterate": 13911, "packages": 13912, "Ġhelpers": 13913, "SEN": 13914, "ĠZero": 13915, "upt": 13916, "mixer": 13917, "ny": 13918, "ед": 13919, "SENT": 13920, "ĠRF": 13921, "ToolTip": 13922, "LU": 13923, "Motion": 13924, "ĠLD": 13925, "Ship": 13926, "future": 13927, "Ġquick": 13928, "leting": 13929, "Ġfun": 13930, "OutOfRange": 13931, "ATTRIBUTE": 13932, "Saved": 13933, "Ġbn": 13934, "ĠLayout": 13935, "ĠFull": 13936, "StringValue": 13937, "IDI": 13938, "ĠSK": 13939, "NER": 13940, "Ġsections": 13941, "Ġ99": 13942, "ĠSerialize": 13943, "SHARED": 13944, "Between": 13945, "PART": 13946, "extended": 13947, "Ġqp": 13948, "Ġexpressions": 13949, "candidate": 13950, "ĠMips": 13951, "CNTL": 13952, "Ġnc": 13953, "ĠFields": 13954, "STAND": 13955, "gable": 13956, "toolbar": 13957, "nand": 13958, "unable": 13959, "eE": 13960, "Orig": 13961, "AppendLine": 13962, "è·": 13963, "cgo": 13964, "Ġarbit": 13965, "UserName": 13966, "JE": 13967, "hand": 13968, "('');": 13969, "mpeg": 13970, "Ġrf": 13971, "Ġvb": 13972, "Ġencrypted": 13973, "Ġmacro": 13974, "xuICB": 13975, "Ġraised": 13976, "ALPHA": 13977, "undef": 13978, "ĠHelp": 13979, "Ġkmalloc": 13980, "åı¯": 13981, "Ġpanic": 13982, "ĠReal": 13983, "Ġ35": 13984, "velop": 13985, "CONN": 13986, "userAgent": 13987, "utc": 13988, ":/\\": 13989, "700": 13990, "Ġhd": 13991, "Ġcancellation": 13992, "lazy": 13993, "Ġdep": 13994, "ĠPIX": 13995, "workspace": 13996, "Pres": 13997, "declare": 13998, "rating": 13999, "Ġcle": 14000, "deli": 14001, "ĠerrorResponse": 14002, "Ġstrcmp": 14003, "ĠOpt": 14004, "Raster": 14005, "ĠGu": 14006, "014": 14007, "apps": 14008, "Whitespace": 14009, "ĠDiag": 14010, "ĠCondition": 14011, "mesa": 14012, "Ġdojo": 14013, "ĠScal": 14014, "Handles": 14015, "dispose": 14016, "rng": 14017, "coeff": 14018, "izable": 14019, "¨¡": 14020, "Ġqueries": 14021, "Ġassignment": 14022, "setopt": 14023, "Rendering": 14024, "Ġhton": 14025, "lope": 14026, "scanf": 14027, "ĠNL": 14028, "Ajax": 14029, "}`": 14030, "Quad": 14031, "linkname": 14032, "ĠErrInvalidLength": 14033, "GED": 14034, "gh": 14035, "MaxValue": 14036, "234": 14037, "dbgs": 14038, "Ġvisual": 14039, ";/": 14131, "Ġdet": 14132, "charge": 14133, "getter": 14134, "Servers": 14135, "ĠScroll": 14136, "sdev": 14137, "runner": 14138, "Levels": 14139, "RequestId": 14140, "æİ¥": 14141, "\"}]": 14142, "ceil": 14143, "readyState": 14144, "ey": 14145, "nitude": 14146, "Ġsv": 14147, "ilege": 14148, "ODING": 14149, "ĠQTest": 14150, "åĬ¨": 14151, "posable": 14152, "(**": 14153, "+=\"": 14154, "irected": 14155, "ĠOPEN": 14156, "msgs": 14157, "volatile": 14158, "Ġmut": 14159, "Ġ(--": 14160, "prepend": 14161, "configs": 14162, "èĩ": 14163, "Ġidle": 14164, "RAD": 14165, "multiply": 14166, "Ġlinked": 14167, "hf": 14168, "Aff": 14169, "PCLZIP": 14170, "AH": 14171, "egid": 14172, "PARSE": 14173, "456": 14174, "VID": 14175, "OFT": 14176, "Ġonto": 14177, "Reject": 14178, "addrlen": 14179, "Ġclazz": 14180, "ccb": 14181, "sysfs": 14182, "TreeNode": 14183, "Ġna": 14184, "gogo": 14185, "postIndex": 14186, "resentation": 14187, "Ġderived": 14188, ":\"\",": 14189, "pkey": 14190, "spell": 14191, "GID": 14192, "Ġaren": 14193, "operands": 14194, "transitioning": 14195, "Segments": 14196, "elist": 14197, "Then": 14198, "Vd": 14199, "PrivacyUri": 14200, "Prefs": 14201, ">>>": 14202, "obs": 14203, "ORITY": 14204, "ĠRHS": 14205, "ListItem": 14206, "Ġfilesystem": 14207, "apr": 14208, "IBLE": 14209, "ĠSHA": 14210, "hore": 14211, "wqe": 14212, "Ġiio": 14213, "ĠBenchmark": 14214, "moveTo": 14215, "ĠModal": 14216, "arded": 14217, "ĠRoot": 14218, "ming": 14219, "pat": 14220, "Mn": 14221, "needed": 14222, "()};": 14223, "shortDate": 14224, "Ġnf": 14225, "emulateTransitionEnd": 14226, "NPC": 14227, "Utc": 14228, "ĠFLAGS": 14229, "kvm": 14230, "chmod": 14231, "Arc": 14232, "ĠUP": 14233, "Ġcalendar": 14234, "134": 14235, "vest": 14236, "Ġiwl": 14237, "ENA": 14238, "('$": 14239, "Ġbeta": 14240, "ager": 14241, "Ġfloating": 14242, "'/": 14243, "Allocate": 14244, "Ho": 14245, "Ġseek": 14246, "Ġln": 14247, "Ġmajor": 14248, "shortTime": 14249, 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"APTER": 15990, "ĠYii": 15991, "Ġ*\\": 15992, "ĠMUST": 15993, "noop": 15994, "Ġsquare": 15995, "ofday": 15996, "Ġstrategy": 15997, "important": 15998, "ĠSetChr": 15999, "bre": 16000, "ente": 16001, "Drv": 16002, "Ġscheduler": 16003, "Ġbw": 16004, "à¤ķ": 16005, "YU": 16006, "Busy": 16007, "HU": 16008, "Suggest": 16009, "Compilation": 16010, "eX": 16011, "PX": 16012, "Ġrepeated": 16013, "Ġflatten": 16014, "unrecognized": 16015, "thumbnail": 16016, "Ports": 16017, "ĠLocale": 16018, "è±": 16019, "addresses": 16020, "ĠBound": 16021, "'\");": 16022, ">>(": 16023, "lvl": 16024, "Protection": 16025, "ĠExpand": 16026, "strdup": 16027, "/***/": 16028, "Ġauthorization": 16029, "Ij": 16030, "ĠRestore": 16031, "Ġnavigation": 16032, "Ġ','": 16033, "Migration": 16034, "Packages": 16035, "etag": 16036, "ZC": 16037, "ĠAuthor": 16038, "MENU": 16039, "ECD": 16040, "SINGLE": 16041, "Ġmis": 16042, "Ġwc": 16043, "imagick": 16044, "+\".": 16045, ";\");": 16046, "Ġ{!": 16047, "SYMBOL": 16048, "ĠLOCK": 16049, "Ġandroid": 16050, "ĠORD": 16051, "Ġupdating": 16052, "Mixed": 16053, "Enumeration": 16054, "Recent": 16055, "tunnel": 16056, "eql": 16057, "Ġxx": 16058, "ICS": 16059, "Ġscaled": 16060, "ufacture": 16061, "adoc": 16062, "اØ": 16063, "eng": 16064, "Quoted": 16065, "Ġprec": 16066, "('_'),": 16067, "ĠAM": 16068, "tap": 16069, "Ġexpires": 16070, "decess": 16071, "ulative": 16072, "Ġgui": 16073, "ĠMeta": 16074, "HOO": 16075, "jul": 16076, "Ġ01": 16077, "Ġtries": 16078, "PKEY": 16079, "placement": 16080, "annotations": 16081, "PKT": 16082, "ĠSELECT": 16083, "Caption": 16084, "/_": 16085, "ĠCmd": 16086, "Ġsid": 16087, "ç®": 16088, "IsEnabled": 16089, "vmx": 16090, "Documents": 16091, "ĠOld": 16092, "Callable": 16093, "IZED": 16094, "Ġled": 16095, "VERBOSE": 16096, "gorithms": 16097, "Micro": 16098, "getQuery": 16099, "mos": 16100, "Ġbm": 16101, "ĠencodeVarint": 16102, "Green": 16103, "rett": 16104, "CallbackImpl": 16105, "getEnd": 16106, "effects": 16107, "scanner": 16108, "..)": 16109, "*******": 16110, "Ġaggregate": 16111, "801": 16112, "cancellationToken": 16113, "easy": 16114, "Ġexpired": 16115, "è°": 16116, "Ġproblems": 16117, "ĠSIZE": 16118, "Ġminute": 16119, "Stopped": 16120, "Ġdepends": 16121, "isObject": 16122, "IsIn": 16123, "Ġgoes": 16124, "translator": 16125, "REMOVE": 16126, "ĠAccept": 16127, "ĠFetch": 16128, "blocking": 16129, "Ġconnector": 16130, "gadget": 16131, "Ġflex": 16132, "Legacy": 16133, "textContent": 16134, "GRAM": 16135, "Gain": 16136, "105": 16137, "Ġscaling": 16138, "ĠOB": 16139, "ArgumentNullException": 16140, "Oi": 16141, "SUS": 16142, "bian": 16143, "Turn": 16144, "attribs": 16145, "theta": 16146, "getResult": 16147, "Ġdetermined": 16148, "Ġreload": 16149, "ndarray": 16150, "Ġguard": 16151, "Ġxy": 16152, "Effects": 16153, "alter": 16154, "ĠChain": 16155, "ographic": 16156, "Ġdocker": 16157, "('/^": 16158, "231": 16159, "åĻ¨": 16160, "timeofday": 16161, "waiting": 16162, "Informer": 16163, "Registers": 16164, "ICT": 16165, "Widgets": 16166, "vfs": 16167, "assertNotNull": 16168, "lfw": 16169, "Detector": 16170, "Ġradio": 16171, "Ġspawn": 16172, "Working": 16173, "parallel": 16174, "ĉĉĉĉĉĉĠĠĠ": 16175, "SKIP": 16176, "*$": 16177, "ĠTRAN": 16178, "Ġwr": 16179, "vember": 16180, "|$": 16181, "Ġaffect": 16182, "Ġhid": 16183, "(?!": 16184, "Policies": 16185, "appro": 16186, "gsub": 16187, "defaultValue": 16188, "Iteration": 16189, "ĠGR": 16190, "ĠBasicBlock": 16191, "PROFILE": 16192, "HANDLER": 16193, "Ġsx": 16194, "addReg": 16195, "ĠAsm": 16196, "WorkItem": 16197, "ãģĻ": 16198, "360": 16199, "Ġmr": 16200, "intersect": 16201, "Preferred": 16202, "ĠAdjust": 16203, "Ġig": 16204, "getUrl": 16205, "ĠPri": 16206, "lit": 16207, "Ġconverter": 16208, "777": 16209, "SOL": 16210, "Ġfault": 16211, "ReadInt": 16212, "ĠSOCK": 16213, "ãģ«": 16214, "Populated": 16215, "USTOM": 16216, "Ġgd": 16217, "ZXR": 16218, "ĠIllegalStateException": 16219, "IFIER": 16220, "LittleEndian": 16221, "ĠMachineInstr": 16222, "Adres": 16223, "AZ": 16224, "minutes": 16225, "Ġnonce": 16226, "éĿ¢": 16227, "Ġì": 16228, "vic": 16229, "icolon": 16230, "cerr": 16231, "calloc": 16232, "writeAttribute": 16233, "Ġviewport": 16234, "Ġfaster": 16235, "stp": 16236, "ulary": 16237, "aco": 16238, "collapsed": 16239, "stable": 16240, "wide": 16241, "orient": 16242, "SAVE": 16243, "review": 16244, "holders": 16245, "riterion": 16246, "cG": 16247, "LRS": 16248, "Ġlocations": 16249, "COUN": 16250, "=['": 16251, "ELE": 16252, "uu": 16253, "ADMIN": 16254, "DOMAIN": 16255, "stone": 16256, "erical": 16257, "Ġtbl": 16258, "ATFORM": 16259, "ĠBindingFlags": 16260, "Cut": 16261, "zi": 16262, "Ġsay": 16263, "Ġquotes": 16264, "too": 16265, "\"(": 16266, "Cop": 16267, "cps": 16268, "Wk": 16269, "оÑĢ": 16270, "Td": 16271, "REPORT": 16272, "Routes": 16273, "Ġ[(": 16274, "ĠMathf": 16275, "pmc": 16276, "NPT": 16277, "Water": 16278, "scl": 16279, "PENDING": 16280, "ĠIdentifier": 16281, "bond": 16282, "qla": 16283, "tember": 16284, "MII": 16285, "Ġrecipient": 16286, "HANDLED": 16287, "DUP": 16288, "yyy": 16289, "Ġpause": 16290, "Pose": 16291, "ĠINVALID": 16292, "Preparer": 16293, "ĠBM": 16294, "ä¸Ģ个": 16295, "Ġpieces": 16296, "Ġ{|": 16297, "igrations": 16298, "99999999": 16299, "ATER": 16300, "ensit": 16301, "aid": 16302, "licas": 16303, "decay": 16304, "Qy": 16305, "VH": 16306, "getBlock": 16307, "Ġnbytes": 16308, "Ev": 16309, "Ġbulk": 16310, "positor": 16311, "StringBuilder": 16312, "AVAIL": 16313, ":\\": 16452, "management": 16453, "SERIAL": 16454, "Ġawserr": 16455, "MIC": 16456, "pV": 16457, "<-": 16458, "Positive": 16459, "duplicate": 16460, "Ġclamp": 16461, "Ġpen": 16462, "Ġcounters": 16463, "Ġpacked": 16464, "FullPath": 16465, "Placeholder": 16466, "Succe": 16467, "ars": 16468, "PointerException": 16469, "zu": 16470, "Ġdocuments": 16471, "190": 16472, "selves": 16473, "REAL": 16474, "ifold": 16475, "atever": 16476, "Ġrelevant": 16477, "astype": 16478, "Ġregulator": 16479, "BOOLEAN": 16480, "ĠCookie": 16481, "Ġpll": 16482, "OnError": 16483, "Embedded": 16484, "LEEP": 16485, "setHeader": 16486, "rssi": 16487, "InProgress": 16488, "weet": 16489, "ĠSn": 16490, "ĠScope": 16491, "acquire": 16492, "Ġprimitive": 16493, "CHIP": 16494, "solution": 16495, "ĠStringUtils": 16496, "xen": 16497, "Procedure": 16498, "Ġqueued": 16499, "Ġcauses": 16500, "ForeignKey": 16501, "manage": 16502, "(\"\")": 16503, "Sparse": 16504, "æĭ": 16505, "deploy": 16506, "Always": 16507, "ingular": 16508, "Ġdecoding": 16509, "QX": 16510, "||!": 16511, "faces": 16512, "MathJax": 16513, "Ġcod": 16514, "IHRo": 16515, "BX": 16516, "Ġ>::": 16517, "Ġcheckpoint": 16518, "Runs": 16519, "scores": 16520, "positions": 16521, "anizations": 16522, "0442": 16523, "SSID": 16524, "MethodImpl": 16525, "masked": 16526, "Ġdetach": 16527, "ĠMAP": 16528, "Providers": 16529, "Ġsun": 16530, "sampler": 16531, "DISABLED": 16532, "IMPORTED": 16533, "ĠUnsupportedOperationException": 16534, "Ġdescrib": 16535, "ulus": 16536, "ĠORDER": 16537, "ä¾": 16538, "()\\": 16539, "moused": 16540, "MEMB": 16541, "Ġstrcpy": 16542, "Ġqemu": 16543, "Ġdeploy": 16544, "DOT": 16545, "Ġdirs": 16546, "Ma": 16547, "ĠCould": 16548, "cedence": 16549, "merged": 16550, "endant": 16551, "shipping": 16552, "Cookies": 16553, "Ġfailures": 16554, "Plug": 16555, "Coordinates": 16556, "wlan": 16557, "stype": 16558, "Ġ#=>": 16559, "prediction": 16560, "ASC": 16561, "NDER": 16562, "published": 16563, "GPR": 16564, "TUN": 16565, "avax": 16566, "Blk": 16567, "ĠRetrieve": 16568, "ODY": 16569, "authentication": 16570, "Ġoptionally": 16571, "Ġwiret": 16572, "itation": 16573, "getStatus": 16574, "ĠTile": 16575, "Ġtested": 16576, "Ġopacity": 16577, "ĠSoft": 16578, "使": 16579, "hind": 16580, "avctx": 16581, "pure": 16582, "ysqli": 16583, "401": 16584, "DJ": 16585, "ÐŁ": 16586, "olang": 16587, "DIST": 16588, "brace": 16589, "vaddr": 16590, "Observable": 16591, "already": 16592, "Ġlpfc": 16593, "Guard": 16594, "Ġsubset": 16595, "Problem": 16596, "Ġcourse": 16597, "ĠMODE": 16598, "SUCCEEDED": 16599, "ö": 16600, "ToObject": 16601, "Ġrespond": 16602, "'''": 16603, "é»": 16604, "avadoc": 16605, "Outline": 16606, "transpose": 16607, "odb": 16608, "RH": 16609, "Rk": 16610, "Ġever": 16611, "ĠNT": 16612, "2008": 16613, "Ġhp": 16614, "Ġbecome": 16615, "RequestMarshaller": 16616, "Album": 16617, "uve": 16618, "chrom": 16619, "Ġrouter": 16620, "Ġcleared": 16621, "Ġcover": 16622, "getSession": 16623, "mailbox": 16624, "ĠSTRING": 16625, "mce": 16626, "namespaces": 16627, "FONT": 16628, "NodeId": 16629, "asp": 16630, "BAA": 16631, "DG": 16632, "isNot": 16633, "arer": 16634, "MediaType": 16635, "antics": 16636, "Ġattempts": 16637, "Mean": 16638, "BLE": 16639, "Interceptor": 16640, "Patterns": 16641, "ĠTmp": 16642, "FLASH": 16643, "Take": 16644, "eventObject": 16645, "news": 16646, "Ġ<<<": 16647, "offsetHeight": 16648, "ĠOpcode": 16649, "CRL": 16650, "ĠPacket": 16651, "nsec": 16652, "Ġlimits": 16653, "Nk": 16654, "Ġrtw": 16655, "ĠRole": 16656, "BOARD": 16657, "//#": 16658, "Ġnav": 16659, "refcount": 16660, "Ġdeal": 16661, "filp": 16662, "èĩª": 16663, "pres": 16664, "Ġcalculation": 16665, "Filtered": 16666, "Ġpotential": 16667, "Ġcsv": 16668, "ALI": 16669, "+)?": 16670, "GFP": 16671, "Ġpreserve": 16672, "ĠCRC": 16673, "quit": 16674, "getIndex": 16675, "Ġseveral": 16676, "Ġphone": 16677, "wra": 16678, "lookups": 16679, "Lifetime": 16680, "Ġmapper": 16681, "ĠTotal": 16682, "Ġprot": 16683, "EDGE": 16684, "AWS": 16685, "á»": 16686, "ĠgetDefault": 16687, "Ġmanagement": 16688, "ĠBuffered": 16689, "benchmark": 16690, "arange": 16691, "ResponseUnmarshaller": 16692, "tpg": 16693, "scopes": 16694, "Ġseparated": 16695, "ĠEditorGUILayout": 16696, "ĠOps": 16697, "Ġencryption": 16698, "Way": 16699, "Ġ\"),": 16700, "6708": 16701, "symlink": 16702, "Ġcompilation": 16703, "fuse": 16704, "æµ": 16705, "patterns": 16706, ".'.": 16707, "Ġinherit": 16708, "Ġ1000000": 16709, "âĶĢâĶĢ": 16710, "zier": 16711, "emo": 16712, "por": 16713, "Elapsed": 16714, "ĠCursor": 16715, "Sun": 16716, "Ġappended": 16717, "COMM": 16718, "mdb": 16719, "WebKit": 16720, "ĠCHAR": 16721, "ĠstructPointer": 16722, "Translator": 16723, "bitrate": 16724, "jp": 16725, "interp": 16726, "Demo": 16727, "ĠReflection": 16728, "}\".": 16729, "attached": 16730, "JSContext": 16731, "indexed": 16732, "capabilities": 16733, "allest": 16734, "LCD": 16735, "ease": 16736, "locks": 16737, "012": 16738, "isString": 16739, "gICAgICAg": 16740, "ACCE": 16741, "preted": 16742, "Loss": 16743, "Ga": 16744, "fopen": 16745, "2001": 16746, "Stencil": 16747, "Ġ37": 16748, "=\"\",": 16749, "SEQUENCE": 16750, "dro": 16751, "WHITE": 16752, "]\\\\": 16753, "imated": 16754, "prim": 16755, "([],": 16756, "cycl": 16757, "mass": 16758, "ĠRep": 16759, "Bulk": 16760, "intent": 16761, "calcul": 16762, "Activation": 16763, "xm": 16764, "getIn": 16765, "220": 16766, "Deploy": 16767, "PED": 16768, "Terms": 16769, "ships": 16770, "Ġenumerable": 16771, "Ġcircle": 16772, "hljs": 16773, "ĠCultureInfo": 16774, "RFC": 16775, "zt": 16776, "FILEN": 16777, "Ġartifact": 16778, "Ġflip": 16779, "andatory": 16780, "Ġconsistent": 16781, "lZ": 16782, "ĠAX": 16783, "explicit": 16784, "Compat": 16785, "DataProvider": 16786, "ĠRight": 16787, "Movie": 16788, "FRAG": 16789, "tlv": 16790, "```": 16791, "ĠBlockly": 16792, "Ġrace": 16793, "lh": 16794, "station": 16795, "thesis": 16796, "FFF": 16797, "Ġconditional": 16798, "度": 16799, "attempt": 16800, "ĠDIRECT": 16801, "ĠAlert": 16802, "DRV": 16803, "6659": 16804, "slow": 16805, "ĠUnix": 16806, "768": 16807, "fee": 16808, "Oid": 16809, "TRACK": 16810, "Wxl": 16811, "traction": 16812, "LG": 16813, "åıij": 16814, "Ġprece": 16815, "Ġeg": 16816, "Declared": 16817, "REMOTE": 16818, "-*": 16819, "Crypt": 16820, "MIX": 16821, "================================================": 16822, "Ġassumes": 16823, "ĠFUNCTION": 16824, "ĠGPU": 16825, "repeated": 16826, "Ġevaluation": 16827, "firm": 16828, "assembler": 16829, "Formula": 16830, "greater": 16831, "agram": 16832, "tery": 16833, "encrypted": 16834, "dlm": 16835, "IllegalArgumentException": 16836, "Ġwritable": 16837, "Ġspin": 16838, ":(": 16839, "subs": 16840, "utoff": 16841, "Compressed": 16842, "Serialized": 16843, "Ġannotations": 16844, "colour": 16845, "FREQ": 16846, "Ġholding": 16847, "arrays": 16848, "OSS": 16849, "pM": 16850, "ĠBar": 16851, "ĠHigh": 16852, "Threading": 16853, "Ġ(~": 16854, "setUp": 16855, "CALLBACK": 16856, "åĮĸ": 16857, "Ġ×": 16858, "oral": 16859, "æīĢ": 16860, "Quotes": 16861, "ĠFC": 16862, "Ġ39": 16863, "Ġnor": 16864, "%%%%": 16865, "304": 16866, "ĠSEEK": 16867, "CKEDITOR": 16868, "AssignableFrom": 16869, "Tol": 16870, "something": 16871, "infos": 16872, "tepret": 16873, "elemetry": 16874, "repr": 16875, "Ġmov": 16876, "SelectedIndex": 16877, "Replica": 16878, "\"]:": 16879, "Related": 16880, "GetComponent": 16881, "Ġpasses": 16882, "ĠQVariant": 16883, "Ġ{:": 16884, "Clipboard": 16885, "Checkbox": 16886, "CTYPE": 16887, "Coins": 16888, "Pixmap": 16889, "contexts": 16890, "म": 16891, "Dw": 16892, "Ġiso": 16893, "Ġgives": 16894, "ĠSite": 16895, "TITLE": 16896, "dates": 16897, "\"}},": 16898, "Ġ--------------------------------------------------------------------": 16899, "Ġ4096": 16900, "Rz": 16901, "retrieve": 16902, "chg": 16903, "Voice": 16904, "èĥ½": 16905, "SDNode": 16906, "对象": 16907, "Trunc": 16908, "ordering": 16909, "Ġmodifiers": 16910, "txn": 16911, "reporter": 16912, "ĠCAI": 16913, "æľ¬": 16914, "ĠCLI": 16915, "स": 16916, "ĠExport": 16917, "FLUSH": 16918, "quotes": 16919, "Land": 16920, "XIO": 16921, "Ġsalt": 16922, "ky": 16923, "Ġ...)": 16924, "Ġtolerance": 16925, "Snippet": 16926, "Ġdrv": 16927, "startup": 16928, "UserData": 16929, "FILES": 16930, "112": 16931, "ĠgetValue": 16932, "Ġregard": 16933, "(\"(": 16934, "',\\": 16935, "'),('": 16936, "ĠNoMethod": 16937, "å»": 16938, "Ġcolour": 16939, "WB": 16940, "Ġbnx": 16941, "computed": 16942, "tlb": 16943, "8192": 16944, "SOFT": 16945, "finalize": 16946, "clazz": 16947, "REGION": 16948, "WebAPI": 16949, "datum": 16950, "DeepEqual": 16951, "ĠLIB": 16952, "\"/>.": 16953, "ĠstartIndex": 16954, "Ġintern": 16955, "Closer": 16956, "production": 16957, "BraceOutdent": 16958, "xz": 16959, "Ġnvkm": 16960, "Ġ'!": 16961, "Ġrid": 16962, "nB": 16963, "ĠTII": 16964, "STE": 16965, "Ġ`,": 16966, "interruptible": 16967, "Ġvx": 16968, "rst": 16969, "Ġpivot": 16970, "Gap": 16971, "angent": 16972, "ĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠ": 16973, "Collect": 16974, "Ġundo": 16975, "Middleware": 16976, "Ġ'->": 16977, "CENTER": 16978, "Ġdescribed": 16979, "ĠByteBuffer": 16980, "PATTERN": 16981, "æ±": 16982, "newRow": 16983, "ChangeListener": 16984, "æĮĩ": 16985, "uveau": 16986, "comparison": 16987, ":\")": 16988, "ĠMockito": 16989, "Ġlargest": 16990, "specialchars": 16991, "Designer": 16992, "Pk": 16993, "Ġ((!": 16994, "}\\\"": 16995, "aaa": 16996, "ĠPIXEL": 16997, "ians": 16998, "exponent": 16999, "ĠEXIT": 17000, "btrfs": 17001, "ĠisValid": 17002, "xel": 17003, "stock": 17004, "Ġpreferred": 17005, "bpp": 17006, "|^": 17007, "bssid": 17008, "Completions": 17009, "strictions": 17010, "Ġarrow": 17011, "alarm": 17012, "GetProperty": 17013, "Bug": 17014, "oken": 17015, "scheduler": 17016, "ldap": 17017, "IK": 17018, "Reads": 17019, "Hooks": 17020, "Glob": 17021, "{{.*": 17022, "Responder": 17023, "debugger": 17024, "Ġqualified": 17025, "Ts": 17026, "ALEN": 17027, "Ġhowever": 17028, "persist": 17029, "ĠTerm": 17030, "VED": 17031, "Ġmmc": 17032, "ĠCX": 17033, "ByIndex": 17034, "108": 17035, "Ġpress": 17036, "ĠLHS": 17037, "Ġencountered": 17038, "Ġ'_'": 17039, "AbsolutePath": 17040, "pO": 17041, "Ġaspect": 17042, "olete": 17043, "ĠArch": 17044, "enet": 17045, "Ġ250": 17046, "ENDOR": 17047, "tepreter": 17048, "ĠPLUGIN": 17049, "Ġregmap": 17050, "'][]": 17051, "?,": 17052, "indicator": 17053, "DropDown": 17054, "Deleg": 17055, "octet": 17056, "vin": 17057, "variance": 17058, "Pager": 17059, "ENTITY": 17060, "uber": 17061, "addColumn": 17062, "Ġsystems": 17063, "Cause": 17064, "Pseudo": 17065, "Ġthink": 17066, "getArg": 17067, "CANCE": 17068, "Ġqs": 17069, "ServiceName": 17070, "zil": 17071, "delim": 17072, "Ġdup": 17073, "ĠShared": 17074, "nN": 17075, "Ġ][": 17076, "ĠShape": 17077, "ĠExecution": 17078, "grunt": 17079, "Ġtransformation": 17080, "eder": 17081, "Ġgamma": 17082, "Ġearlier": 17083, "stringstream": 17084, "Ġencrypt": 17085, "standing": 17086, "Ġrespons": 17087, "PIXEL": 17088, "rnd": 17089, "ICMP": 17090, "EAGAIN": 17091, "irs": 17092, "Ang": 17093, "*?": 17094, "Sz": 17095, "PROB": 17096, "Ġ)(": 17097, "Ġ($_": 17098, "tmpl": 17099, "enance": 17100, "Ġxrange": 17101, "TimeZone": 17102, "sdk": 17103, "Ġceph": 17104, "+-+-+-+-": 17105, "ĠPP": 17106, "IPHER": 17107, "|\"+": 17108, "getMonth": 17109, "ĠAttach": 17110, "Ġbackwards": 17111, "bindings": 17112, "Orders": 17113, "aug": 17114, "TRACT": 17115, "$('#": 17116, "FV": 17117, "logic": 17118, "neigh": 17119, "Monster": 17120, "guide": 17121, "erc": 17122, "ĠQByteArray": 17123, "Ġgs": 17124, "mdio": 17125, "Expiration": 17126, "ubuntu": 17127, "iles": 17128, "trunc": 17129, "FlagSet": 17130, "=>$": 17131, "Facet": 17132, "Tod": 17133, "APPL": 17134, "composition": 17135, "invocation": 17136, "TextHighlightRules": 17137, "CAM": 17138, "Ġmodal": 17139, "getCursor": 17140, "Intepreter": 17141, "accel": 17142, "ASH": 17143, "Lin": 17144, "Ġfabric": 17145, "ĠAlways": 17146, "cgi": 17147, "olar": 17148, "ĠCancel": 17149, "ĠEdit": 17150, "Qj": 17151, "Ġ70": 17152, "Folders": 17153, "PrimaryKey": 17154, "IGNORE": 17155, "Ġdns": 17156, "backtrace": 17157, "ĠJc": 17158, "HasPrefix": 17159, "ĠAtomic": 17160, "Cx": 17161, "Grammar": 17162, "ipheral": 17163, "coexist": 17164, "Ġtodo": 17165, "Reload": 17166, "Ġdecorator": 17167, "àµ": 17168, "Ġaliases": 17169, "__('": 17170, "FileSync": 17171, "TextNode": 17172, "ĠBox": 17173, "FER": 17174, "Ñİ": 17175, "Ġpch": 17176, "Swift": 17177, "Dark": 17178, "setContent": 17179, "quota": 17180, "getEntity": 17181, "clZip": 17182, "ĠgetInstance": 17183, "ĠRot": 17184, "åĬŁ": 17185, ">')": 17186, "getHours": 17187, "WebSocket": 17188, "acle": 17189, "ZWF": 17190, "bid": 17191, "од": 17192, "Corner": 17193, ")),\"": 17194, "=[\"": 17195, "three": 17196, "Ġrte": 17197, "ĠOAuth": 17198, "pars": 17199, "Ġreleased": 17200, "JNIEnv": 17201, "ĠDst": 17202, "Ġmarkup": 17203, "Referral": 17204, "Ġlocals": 17205, "privacy": 17206, "ĠContract": 17207, "DEFINED": 17208, "Jun": 17209, "(\"(()": 17241, "Ġdrawing": 17242, "Ġdwarf": 17243, "ĠProfile": 17244, "charg": 17245, "ĠTe": 17246, "Ġtranslated": 17247, "Lj": 17248, "xsd": 17249, "stuff": 17250, "esModule": 17251, "ĠWITH": 17252, "iagnostics": 17253, "LANG": 17254, "MarshalTo": 17255, ")%": 17256, "eras": 17257, "Ġroutes": 17258, "Scheduled": 17259, "106": 17260, "Painter": 17261, "Waiting": 17262, "æ®": 17263, "ReadWrite": 17264, "Ġк": 17265, "ĠCUR": 17266, "_$": 17267, "Ġmf": 17268, "ĠREQ": 17269, "gtk": 17270, "Descriptors": 17271, "ĠGeneral": 17272, "intp": 17273, "Advanced": 17274, "ĠresourceGroupName": 17275, "ĠpropertyName": 17276, "Sphere": 17277, "Train": 17278, "ByteBuffer": 17279, "mousedown": 17280, "ĠII": 17281, "Nov": 17282, ")});": 17283, "dumps": 17284, "getPointer": 17285, "ãĥ³": 17286, "Angles": 17287, "NewError": 17288, "BSD": 17289, "Ġcompletely": 17290, "lus": 17291, ";//": 17292, "Qz": 17293, "inally": 17294, "ĠAE": 17295, "declaration": 17296, "bounce": 17297, "DateFormat": 17298, "onload": 17299, "ancy": 17300, "ем": 17301, "musb": 17302, "Ġoverridden": 17303, "currentTimeMillis": 17304, "indicators": 17305, ":\\\\": 17306, "HK": 17307, "Zz": 17308, "Ġsimd": 17309, "Portal": 17310, "fol": 17311, "arations": 17312, "Ġnat": 17313, "parms": 17314, ")}),": 17315, "Histogram": 17316, "vue": 17317, "ORAGE": 17318, ")+\"": 17319, "hx": 17320, "å¼Ģ": 17321, "âķ": 17322, "èµ": 17323, "subtract": 17324, "Parm": 17325, "Executable": 17326, "PHPUnit": 17327, "dashboard": 17328, "ĠCategory": 17329, "ĠDefine": 17330, "setCurrent": 17331, "MW": 17332, "dbl": 17333, "phydev": 17334, "Aggregation": 17335, "831": 17336, "daemon": 17337, "Detection": 17338, "ISR": 17339, "ĠFactory": 17340, "Ce": 17341, "Ġtot": 17342, "Subtarget": 17343, "320": 17344, "Subscribe": 17345, "\".$": 17346, "EVT": 17347, "Ġvt": 17348, "ĠMaterial": 17349, "enumerable": 17350, "LIC": 17351, "LOCATION": 17352, "\"\":": 17353, "SIMPLE": 17354, "omp": 17355, "Ġcatalog": 17356, "aspect": 17357, "mdp": 17358, "SmallIconUri": 17359, "GroupId": 17360, "separated": 17361, "Cart": 17362, "DTO": 17363, "StringLen": 17364, "invoice": 17365, "shm": 17366, "ĠFiles": 17367, "Ascii": 17368, "Within": 17369, "ĠChecks": 17370, "094": 17371, "Ġposts": 17372, "pearance": 17373, "è°ĥ": 17374, "erator": 17375, "INLINE": 17376, "Queries": 17377, "extern": 17378, "CodeAttribute": 17379, "ĠCFG": 17380, "poser": 17381, "Sizer": 17382, "Ġloff": 17383, "Ġeffects": 17384, "FORCE": 17385, "Ġtimed": 17386, "ĠEl": 17387, "Ġpayment": 17388, ")(((": 17389, "Ġlicense": 17390, "Recorder": 17391, "invert": 17392, "Ġnamespaces": 17393, "ãĢĤ\\": 17394, "å½ĵåīį": 17395, "Profiles": 17396, "TextView": 17397, "OPER": 17398, "don": 17399, "ĠCODE": 17400, "Buffered": 17401, "Fm": 17402, "xFFFFFFFF": 17403, "nowledge": 17404, "Insn": 17405, "Ġvendor": 17406, "ĠTimes": 17407, "Nt": 17408, "vial": 17409, "shint": 17410, "Converts": 17411, "Âł": 17412, "ú": 17413, "Ġinterceptor": 17414, "ĠWill": 17415, "connections": 17416, "TRUN": 17417, "Ġbackward": 17418, "Ġoverrides": 17419, "Mutation": 17420, "\")?": 17421, "DRAW": 17422, "Jq": 17423, "ĠfilePath": 17424, "()==": 17425, "creation": 17426, "vict": 17427, "Ġgdb": 17428, "AILED": 17429, "smbus": 17430, "Ġrecover": 17431, "IOD": 17432, "Ġbitcast": 17433, "Ġtools": 17434, "PATCH": 17435, "Editable": 17436, "ĠRUN": 17437, "jdGlvb": 17438, "inja": 17439, "JIT": 17440, "modifiers": 17441, "desired": 17442, "MMMM": 17443, "ĠTimestamp": 17444, "Ctor": 17445, "áĥĺ": 17446, "pem": 17447, "hsotg": 17448, "Ġcollections": 17449, "大": 17450, "åĪłéĻ¤": 17451, "ÑĦ": 17452, "ĠIND": 17453, "Ġslider": 17454, "rewrite": 17455, "addListener": 17456, "bW": 17457, "ĠRS": 17458, "çİ": 17459, "About": 17460, "PageSize": 17461, "sigma": 17462, "Ġ360": 17463, "ав": 17464, "average": 17465, "Injection": 17466, "ĠNamed": 17467, "Relationship": 17468, "Spaces": 17469, "NOTICE": 17470, "ĠAsset": 17471, "Cube": 17472, "cern": 17473, "masks": 17474, "ĠCluster": 17475, "nfunction": 17476, "ĠBl": 17477, "ĠLED": 17478, "ucene": 17479, "Ġdeps": 17480, "devs": 17481, "Ġintended": 17482, "Sales": 17483, "Ġindirect": 17484, "Ġcomes": 17485, "INTERVAL": 17486, "Ġpts": 17487, "ĠFunctions": 17488, "Pkg": 17489, "SAS": 17490, "Spot": 17491, "csum": 17492, "ĠAN": 17493, "ĠBrowser": 17494, "PKCS": 17495, "Ġoptimization": 17496, "Ġepsilon": 17497, "Caret": 17498, "spot": 17499, "ĠArt": 17500, "à¤Ĥ": 17501, "Regions": 17502, "Selfer": 17503, "NAM": 17504, "(\"&": 17505, "Millisecond": 17506, "]},": 17507, "nbytes": 17508, "ĠPH": 17509, "printer": 17510, "choices": 17511, "Capability": 17512, "ĠWC": 17513, "gameObject": 17514, "Ġrq": 17515, "Couldn": 17516, "pipes": 17517, "tomorrow": 17518, "dss": 17519, "Ġ&_": 17520, "Evaluation": 17521, "HOME": 17522, "NW": 17523, "unload": 17524, "Ġ>(": 17525, "ĠRunnable": 17526, "Iam": 17527, "Ġnormally": 17528, "Minute": 17529, "Ġgrow": 17530, "implicit": 17531, "Menus": 17532, "ouch": 17533, "8859": 17534, "Ġformula": 17535, "ĠSourceLocation": 17536, "ĠComplex": 17537, "Ġbh": 17538, "feat": 17539, "Ance": 17540, "Passed": 17541, "Ġerase": 17542, "KX": 17543, "г": 17544, "ĠVideo": 17545, "Transactions": 17546, "Ġ}}": 17547, "ĠstartTime": 17548, "chn": 17549, "INTERRUPT": 17550, "Ġgeo": 17551, "httpResponse": 17552, "çĶŁ": 17553, "Ġ96": 17554, "claim": 17555, "Multiply": 17556, "Envelope": 17557, "äºİ": 17558, "Ġbeg": 17559, "implemented": 17560, "OneOf": 17561, "Ġini": 17562, "Dependent": 17563, "phabet": 17564, "WARF": 17565, "assigned": 17566, "icipant": 17567, "SourceMap": 17568, "ĠIW": 17569, "Ġdg": 17570, "ominator": 17571, "ĠPopover": 17572, "Ġdropped": 17573, "ĠCBase": 17574, "NZ": 17575, "Ġ`$": 17576, "Histor": 17577, "jklm": 17578, "Ġ'(": 17579, "Ġloads": 17580, "venience": 17581, "使çĶ¨": 17582, "Ġrecursively": 17583, "prof": 17584, "addWidget": 17585, "BOOT": 17586, "removeAll": 17587, "109": 17588, "finder": 17589, "ToFile": 17590, "Determine": 17591, "pmlme": 17592, "Ġefx": 17593, "checkOutdent": 17594, "Ġexecuting": 17595, "YYYY": 17596, "ĠErrInvalidLengthGenerated": 17597, "Ut": 17598, "Ġtst": 17599, "AsyncResult": 17600, "ĠVisual": 17601, "Ġfo": 17602, "/****************************************************************": 17603, "developer": 17604, "questions": 17605, "stors": 17606, "EEPROM": 17607, "Ġvisited": 17608, "Ġtegra": 17609, "bcd": 17610, "rus": 17611, "idr": 17612, "Ġrw": 17613, "LogLevel": 17614, "ĠDESC": 17615, "CEV": 17616, "Fw": 17617, "PROJECT": 17618, "xk": 17619, "ĠbeforeEach": 17620, "Ġinvalidate": 17621, "Preset": 17622, ">*": 17623, "workflow": 17624, "Echo": 17625, "YXRl": 17626, "GTK": 17627, "?\");": 17628, "Ġsubclass": 17629, "getDocument": 17630, "Rev": 17631, "Ġimported": 17632, "ĠLOGGER": 17633, "ifiable": 17634, "definitions": 17635, "getRoot": 17636, "projection": 17637, "ĠEEPROM": 17638, "ãģĦ": 17639, "('/',": 17640, "Ġdeclare": 17641, "olr": 17642, "Ġtuples": 17643, "Errno": 17644, "SCREEN": 17645, "mis": 17646, "lapping": 17647, "Ġrval": 17648, "Ġprocedure": 17649, "NOTE": 17650, "Ġtk": 17651, "blocksize": 17652, "prefs": 17653, "Rating": 17654, "ĠIss": 17655, "Attached": 17656, "ĠNDB": 17657, "SECTION": 17658, "Cpu": 17659, "Ġ02": 17660, "Ġparses": 17661, "LayoutParams": 17662, "LoadBalancer": 17663, "Ġunmarshaller": 17664, "erscore": 17665, "Ġloops": 17666, "ĠrelatedTarget": 17667, "dapm": 17668, "VZ": 17669, "ilio": 17670, "ĠCB": 17671, "ĠSQLITE": 17672, "parseFloat": 17673, "Jz": 17674, "åĴ": 17675, "FIXED": 17676, "Ġquality": 17677, "-\"": 17678, "CreateInstance": 17679, "è¿Ļ": 17680, "hood": 17681, "Mz": 17682, "ç´": 17683, "ĠHeaders": 17684, "iated": 17685, "ĠIT": 17686, "typeName": 17687, "Ġpathname": 17688, "loit": 17689, "Ġhl": 17690, "tableLayoutPanel": 17691, "ĠAPInt": 17692, "iscsi": 17693, "ĉĉĉĉĉĉĉĉĉĉĉĉ": 17694, "TypeInfo": 17695, "UW": 17696, "Raise": 17697, "uA": 17698, "ColumnName": 17699, "Ġlr": 17700, "exchange": 17701, "aily": 17702, "compareTo": 17703, ">%": 17704, "cmap": 17705, "Weights": 17706, "gx": 17707, "yond": 17708, "ago": 17709, "ĠSA": 17710, "ĠPIPE": 17711, "problem": 17712, "TRIES": 17713, "PDO": 17714, "ĠfieldNum": 17715, "ĠRegex": 17716, ":\"%": 17717, "coherent": 17718, "Desktop": 17719, "subtype": 17720, "åı·": 17721, "))*": 17722, "ç±»åŀĭ": 17723, "navigation": 17724, "й": 17725, "Inverse": 17726, "velopers": 17727, ")')": 17728, "Ġpolynomial": 17729, "ĠPtr": 17730, "EVP": 17731, "cuda": 17732, "rettify": 17733, "Ps": 17734, "121": 17735, "ĠIdx": 17736, "ĠULONG": 17737, "OE": 17738, "BIO": 17739, "IMETHODIMP": 17740, "rport": 17741, "MISC": 17742, "IFS": 17743, "('../": 17744, "ĠBIO": 17745, "Ġsetter": 17746, "kbd": 17747, "CPP": 17748, "FontSize": 17749, "napi": 17750, "ĠfieldName": 17751, "Ġparents": 17752, "Ġ75": 17753, "Ġenviron": 17754, "umented": 17755, "Collapsed": 17756, "ResumeLayout": 17757, "Ġwave": 17758, "tmpdir": 17759, "RUNNING": 17760, "addElement": 17761, "DIAN": 17762, "qrst": 17763, "tolua": 17764, "Ġfunctionality": 17765, "Ġgateway": 17766, "ĠConst": 17767, "Ġgraphics": 17768, "SuspendLayout": 17769, "ĠTM": 17770, "ĠExpect": 17771, "GetNext": 17772, "==============": 17773, "Ġbone": 17774, "Inject": 17775, "readcr": 17776, "Ġscores": 17777, "DBB": 17778, "physical": 17779, "Ġordinal": 17780, "Cs": 17781, "Ġfg": 17782, "checkPosition": 17783, "ĠFAILED": 17784, "Ġhal": 17785, "Ġ```": 17786, "2018": 17787, "=\\\"\"": 17788, "FY": 17789, "getConnection": 17790, "(;": 17791, "ership": 17792, "Ġcombine": 17793, "2019": 17794, "ragma": 17795, "|%": 17796, "AttributeChecker": 17797, "vLy": 17798, "Ġpeek": 17799, "Ġ\"//": 17800, "ĠWLAN": 17801, "Ġstrn": 17802, "rust": 17803, "onus": 17804, "ora": 17805, "ĠFR": 17806, "reqs": 17807, "NewReader": 17808, "VERTEX": 17809, "Tm": 17810, "drupal": 17811, "Ġpersoon": 17812, "InstancePtr": 17813, "PluralRule": 17814, "ACTIVITY": 17815, "Ġexpects": 17816, "Fo": 17817, "Es": 17818, "æ¬": 17819, "Builtin": 17820, "Gtk": 17821, "Ġscanner": 17822, "Synchron": 17823, "bag": 17824, "iounmap": 17825, "DIM": 17826, "equalsIgnoreCase": 17827, "ALTER": 17828, "callee": 17829, "ĠPSU": 17830, "early": 17831, "Ji": 17832, "prime": 17833, "CDATA": 17834, "argins": 17835, "domains": 17836, "Ġinsertion": 17837, "Mapped": 17838, "thresh": 17839, "Ġqueues": 17840, "ĠAff": 17841, "dB": 17842, "xmm": 17843, "ĠBool": 17844, "*$/": 17845, "nam": 17846, "Trailing": 17847, "BREAK": 17848, "Ġfiltering": 17849, "Timing": 17850, "cycler": 17851, "kk": 17852, "ISH": 17853, "seealso": 17854, "goods": 17855, "BINARY": 17856, "ĠNamespace": 17857, "Ġhierarchy": 17858, "ills": 17859, "Ġrewrite": 17860, "ĠMCS": 17861, "Brazil": 17862, "ĠlastNode": 17863, "utr": 17864, "ĠINIT": 17865, "Ġexecutor": 17866, "NonUser": 17867, "(($": 17868, "Aws": 17869, "ĠINDEX": 17870, "Availability": 17871, "Ġdependent": 17872, "Ġarticle": 17873, "ipy": 17874, "Ġexchange": 17875, "MinValue": 17876, "Stderr": 17877, "strncpy": 17878, "clamp": 17879, "Ġsecure": 17880, "Che": 17881, "SIX": 17882, "Publisher": 17883, "Ġindentation": 17884, "primitive": 17885, "Ġassociation": 17886, "(*(": 17887, "VENDOR": 17888, "ç©": 17889, "coef": 17890, "MEMBER": 17891, "gdG": 17892, "xn": 17893, "QObject": 17894, "ĠtableName": 17895, "writing": 17896, "Southeast": 17897, "Ġdial": 17898, ":$": 17899, "èĢ": 17900, "reamble": 17901, "Syn": 17902, "atin": 17903, "Gdata": 17904, "åĵ": 17905, "FILL": 17906, "Ġbf": 17907, "getSelection": 17908, "Icons": 17909, "à¥ĩ": 17910, "=',": 17911, "APH": 17912, "ĠCamera": 17913, "compose": 17914, "scaler": 17915, "ĠTIME": 17916, "Ġtracking": 17917, "bench": 17918, "ĠstatusCode": 17919, "ĠSelector": 17920, "elcome": 17921, "Replication": 17922, "Comma": 17923, "ï¼ī": 17924, ">:": 17925, "EOP": 17926, "Ñħ": 17927, "mpdf": 17928, "Profiler": 17929, "Ġbusy": 17930, "ĠSignature": 17931, "ĠInputStream": 17932, "reinterpret": 17933, "----------------------------------------": 17934, "creator": 17935, "UserAgent": 17936, "abi": 17937, "ĠTimeout": 17938, "ĠuserId": 17939, "ĠblockSize": 17940, "ConnectionString": 17941, "ddy": 17942, "ĠSF": 17943, "ï¼Ī": 17944, "VISIBLE": 17945, "collections": 17946, "dial": 17947, "Ġcpp": 17948, "setOn": 17949, "ensus": 17950, "5555": 17951, "ĠACL": 17952, "pwd": 17953, "Ġscenario": 17954, "dispatchEvent": 17955, "ĠWatch": 17956, "FAST": 17957, ")');": 17958, "dW": 17959, "Photo": 17960, "ĠOPTION": 17961, "ĠCarousel": 17962, "Ġforms": 17963, "Ġlost": 17964, "ĠAnnot": 17965, "Mb": 17966, "Fp": 17967, "fall": 17968, "ĠCannot": 17969, "brightness": 17970, "Selects": 17971, "Ġactivate": 17972, "Ġvan": 17973, "Ġ{}\",": 17974, "EXTENSION": 17975, "ĠmethodName": 17976, "outed": 17977, "aussian": 17978, "wav": 17979, "xo": 17980, "ä¼ł": 17981, "lon": 17982, "tsk": 17983, "}_": 17984, "Ġsnippet": 17985, "Ġscheduled": 17986, "starting": 17987, "Skipped": 17988, "ĠBC": 17989, "mtab": 17990, "THE": 17991, "Ġwor": 17992, "setType": 17993, "Febru": 17994, "SUR": 17995, "ĠYAML": 17996, "ĠVP": 17997, "Ġks": 17998, "vga": 17999, "Ġfine": 18000, "Chip": 18001, "aggregate": 18002, "容": 18003, "Ġembedding": 18004, ">\")": 18005, "Ġrl": 18006, "Ġpurpose": 18007, "InstanceId": 18008, "~/": 18009, "ĠObjC": 18010, "Ġur": 18011, "eps": 18012, "converter": 18013, "tester": 18014, "=============": 18015, "Ġ\"=": 18016, "Ġи": 18017, "inventory": 18018, "VLAN": 18019, "Ġsymlink": 18020, "stringValue": 18021, "atalen": 18022, "Party": 18023, "Playing": 18024, "lq": 18025, "à¥Ģ": 18026, "Ġmkdir": 18027, "ĠCast": 18028, "playback": 18029, "ĠgetId": 18030, "KeyDown": 18031, "FU": 18032, "Ġgfs": 18033, "ufacturer": 18034, "getActive": 18035, "otos": 18036, "Lowering": 18037, "Ġsuspend": 18038, "ico": 18039, "Canada": 18040, "\"\",": 18041, "302": 18042, "jklmnop": 18043, "ban": 18044, "ĉĉĠĠĠĠĠĠĠ": 18045, "freeze": 18046, "removeListener": 18047, "utive": 18048, "addon": 18049, "ĠPersoon": 18050, "Ġhasn": 18051, "bmN": 18052, "Ġmeaning": 18053, "Ġck": 18054, "Ġsorting": 18055, "{'": 18056, "readInt": 18057, "sky": 18058, "JZ": 18059, "VIR": 18060, "Ġbrowsers": 18061, "Inet": 18062, "ĠTS": 18063, "655": 18064, "FieldValue": 18065, "ĠActiv": 18066, "stopped": 18067, "Ġcompact": 18068, "PIE": 18069, "Containers": 18070, "Movement": 18071, "wnd": 18072, "Ġstartup": 18073, "TYPES": 18074, "Recording": 18075, "activation": 18076, "Ġ-(": 18077, "OrUpdate": 18078, "PROGRESS": 18079, "wers": 18080, "Ġmasked": 18081, "INITY": 18082, "omb": 18083, "ĠCXX": 18084, "ĠNotification": 18085, "spa": 18086, "hat": 18087, "ĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠ": 18088, "isF": 18089, "()*": 18090, "å®ŀ": 18091, "GOT": 18092, "TestData": 18093, "COVER": 18094, "ек": 18095, "Anonymous": 18096, "Cms": 18097, "|_": 18098, "mdc": 18099, "ĠQT": 18100, "ĠcontentType": 18101, "åºĶ": 18102, "ĠErrIntOverflowGenerated": 18103, "ConvertTo": 18104, "ĠPair": 18105, "Ġclang": 18106, "Removes": 18107, "Pi": 18108, "ĠES": 18109, "ĠScreen": 18110, "Ġ\"=\"": 18111, "movie": 18112, "DAO": 18113, "gmt": 18114, "Ġunre": 18115, "cyc": 18116, "izzle": 18117, "ĠAnaly": 18118, "Ast": 18119, "mci": 18120, "pename": 18121, "OAuth": 18122, "Vote": 18123, "Ġbenchmark": 18124, "Ġbalance": 18125, "weekday": 18126, "Ġtyped": 18127, "Ġopaque": 18128, "FFIX": 18129, "Ġ},\\": 18130, "(\"*": 18131, "Unmarshall": 18132, "igure": 18133, "Ġ\")\");": 18134, "MPI": 18135, "UME": 18136, "ĠSCR": 18137, "ĠProgress": 18138, "Ġappears": 18139, "().(*": 18140, "ĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠ": 18141, "Hostname": 18142, "Ġjournal": 18143, "vout": 18144, "Ġtruncate": 18145, "Ġstdin": 18146, "Vectors": 18147, "åŃĹ符": 18148, "ĠĠĠĠĠĊ": 18149, "enticator": 18150, "dataType": 18151, "Ġ47": 18152, "fk": 18153, "ĠKER": 18154, "Hold": 18155, "ĠDat": 18156, "ĠSeek": 18157, "ĠLeft": 18158, "ĠPatch": 18159, "tracking": 18160, "routing": 18161, "Ġsatisfy": 18162, "asi": 18163, "ynos": 18164, "SETUP": 18165, "conflict": 18166, "assertNot": 18167, "COMPRE": 18168, "CSharp": 18169, "enses": 18170, "indirect": 18171, "0441": 18172, "Ġterminate": 18173, "Peek": 18174, "Ġcontinuation": 18175, "ĠMII": 18176, "ĠFace": 18177, "Ġdecide": 18178, "Ġrestrict": 18179, "vectors": 18180, "xdr": 18181, "camel": 18182, "ĠØ": 18183, "ĠVertex": 18184, "**/": 18185, "Ġdegrees": 18186, "ĠNE": 18187, "Ġprinted": 18188, "gpi": 18189, "SIM": 18190, "executor": 18191, "Ġ160": 18192, "ĠSwap": 18193, "smb": 18194, "Edm": 18195, "Ġaborted": 18196, "Bh": 18197, "======": 18198, "VarP": 18199, "CSSPrefix": 18200, "8080": 18201, "Dns": 18202, "ĠManager": 18203, "SSED": 18204, "adb": 18205, "=========": 18206, "Authority": 18207, "GRE": 18208, "pSrc": 18209, "rack": 18210, "Ġmul": 18211, "implode": 18212, "MULTI": 18213, "è·¯": 18214, "Ġfifo": 18215, "365": 18216, "ĠQStringList": 18217, "uar": 18218, "etrokken": 18219, "intval": 18220, "Ġ[['": 18221, "past": 18222, "%(": 18223, "386": 18224, "inel": 18225, "MISS": 18226, "dense": 18227, "ĠQLatin": 18228, "Ġjobs": 18229, "dateFormat": 18230, "createMock": 18231, "StdString": 18232, "ĠTrigger": 18233, "Ġ1234": 18234, "}))": 18235, "Ġintro": 18236, "VQ": 18237, "unpin": 18238, "Requirement": 18239, "sap": 18240, "áĥIJ": 18241, "οÏ": 18242, "ĠMs": 18243, "ASM": 18244, "ĠUsage": 18245, "114": 18246, "BasePath": 18247, "NOTSUPP": 18248, "ĠEdge": 18249, "Desired": 18250, "Solid": 18251, "TypeDef": 18252, "Ġlead": 18253, "firstDay": 18254, "LICT": 18255, "Ġworkflow": 18256, "Ġlowest": 18257, "baseCSSPrefix": 18258, "Prettify": 18259, "trast": 18260, "Ġping": 18261, "keyup": 18262, "ENDIAN": 18263, "ĠQU": 18264, "CallOption": 18265, "SMALL": 18266, "Ġharmony": 18267, "ĠPF": 18268, "unittest": 18269, "ĠCollapse": 18270, "ARGUMENT": 18271, "Ġlengths": 18272, "Ġ&,": 18273, "msghdr": 18274, "umulative": 18275, "slid": 18276, "getMax": 18277, "ALAR": 18278, "userdata": 18279, "battery": 18280, "Ġ404": 18281, "quantity": 18282, "ĠAddr": 18283, "Ġterminated": 18284, "Rob": 18285, "ĠProxy": 18286, "Ġuniform": 18287, "(_(\"": 18288, "LCJ": 18289, "cbl": 18290, "/},{": 18291, "grow": 18292, "Ġist": 18293, "ializers": 18294, "ParseError": 18295, "endsWith": 18296, "询": 18297, "BANK": 18298, "GJ": 18299, "Ġ(@": 18300, "ĠBR": 18301, "Ġimpro": 18302, "DIFF": 18303, "ENDED": 18304, "Broker": 18305, "ĠDP": 18306, "Imports": 18307, "Ġbelongs": 18308, "ensitivity": 18309, "Ġlc": 18310, "Invalidate": 18311, "Domains": 18312, "Latest": 18313, "Ur": 18314, "CAA": 18315, "ĠCGF": 18316, "Gate": 18317, "unsupported": 18318, "Products": 18319, "Gro": 18320, "TOM": 18321, "PUBLIC": 18322, "SimpleRefCount": 18323, "Directories": 18324, "gZ": 18325, "|[^": 18326, "unref": 18327, "COLL": 18328, "directories": 18329, "bcs": 18330, "eting": 18331, "voked": 18332, "ubernet": 18333, "SetString": 18334, "<<\"": 18335, "riptions": 18336, "ValuePair": 18337, "transparent": 18338, "146": 18339, "ĠWS": 18340, "equalTo": 18341, "MAPPING": 18342, "hed": 18343, "ĠInclude": 18344, "between": 18345, "nJ": 18346, "Ġcanceled": 18347, "ĠTT": 18348, "Least": 18349, "Ġql": 18350, "Ġ\"-\"": 18351, "BLK": 18352, "Limits": 18353, "Ġstand": 18354, "SIGNAL": 18355, "checks": 18356, "Ġawsutil": 18357, "vise": 18358, "into": 18359, "Ġdistribute": 18360, "Assessment": 18361, "Ki": 18362, "ubernetes": 18363, "ĠPipe": 18364, "ĠAssembly": 18365, "/$": 18366, "topology": 18367, "InputService": 18368, "154": 18369, "CW": 18370, "ĠDA": 18371, "Md": 18372, "CREF": 18373, "CAPTURE": 18374, "ubi": 18375, "handles": 18376, "rolled": 18377, "Txt": 18378, "ĠCard": 18379, "Ġgrab": 18380, "Ġbuiltin": 18381, "Ġ[]);": 18382, "ĠPerson": 18383, "Ġcwd": 18384, "ergency": 18385, "rendered": 18386, "ĠWidth": 18387, "Leader": 18388, "Ġpersistent": 18389, "(++": 18390, "Ġ:'": 18391, "}/{": 18392, "Ġyes": 18393, "ICY": 18394, "MultiLine": 18395, "Sampler": 18396, "Ġ?>;": 18542, "anc": 18543, "004": 18544, "addItem": 18545, "ENXIO": 18546, "rawler": 18547, "762": 18548, "Exclusive": 18549, "113": 18550, "Writes": 18551, "ReadAll": 18552, ")))|": 18553, "Ġgst": 18554, "Ġportion": 18555, "XYZ": 18556, "SECOND": 18557, "Advance": 18558, "Faces": 18559, "CONNECTED": 18560, "Reduce": 18561, "Canceled": 18562, "ListBox": 18563, "ĠHZ": 18564, "SYN": 18565, "preferred": 18566, "hmac": 18567, "mlog": 18568, "POOL": 18569, "é»ĺ认": 18570, ",,": 18571, "Tue": 18572, "Ġhints": 18573, "Stock": 18574, "Ġdestroyed": 18575, "Ġanimate": 18576, "COMMON": 18577, "ployee": 18578, "SWAP": 18579, "232": 18580, "MACH": 18581, "Bootstrap": 18582, "Die": 18583, "Ġ/^\\": 18584, "drain": 18585, "MessageType": 18586, "Ġ192": 18587, "Ġweekdays": 18588, "IOCTL": 18589, "pagination": 18590, "fabric": 18591, "æł¼": 18592, "patient": 18593, "viation": 18594, "Ġexcluded": 18595, "sentence": 18596, "ĠIo": 18597, "MET": 18598, "Ġrecovery": 18599, "COOKIE": 18600, "Redis": 18601, "Ġolder": 18602, "Ġ())": 18603, "ĠFLASH": 18604, "],\"": 18605, "Ġtransitions": 18606, "Ġgeom": 18607, "celeration": 18608, "ENGINE": 18609, "ĠnsI": 18610, "ल": 18611, "wifiex": 18612, "npos": 18613, "Ġtheta": 18614, "443": 18615, "ĠSafe": 18616, "è¯ģ": 18617, "TEMPLATE": 18618, "thca": 18619, "ĠCase": 18620, "ocfs": 18621, "ToEnd": 18622, "Ġ/**\\": 18623, ")}},": 18624, "ĠMemoryStream": 18625, "Hl": 18626, "ĠAssume": 18627, "éª": 18628, "jklmnopqrst": 18629, "Ġoid": 18630, "ileges": 18631, "оÑĤ": 18632, "Verts": 18633, "Care": 18634, "strm": 18635, "Ġrepr": 18636, "0930": 18637, "Ġobtained": 18638, "pins": 18639, "Unused": 18640, "Floor": 18641, "Ġunlink": 18642, "Performance": 18643, "triple": 18644, "Ġ$('<": 18645, "ĠSecure": 18646, "readed": 18647, "Ġtrust": 18648, "ĠEP": 18649, "cma": 18650, "ĠHAVE": 18651, ":\"^": 18652, "RemoveAll": 18653, "PrototypeOf": 18654, "Ġnearest": 18655, "æ¯": 18656, "recent": 18657, "ĠNewPopulated": 18658, "ĠShift": 18659, "Ġwide": 18660, "formula": 18661, "newValue": 18662, "hance": 18663, "Ġmetav": 18664, "nock": 18665, "Ġinfinite": 18666, "Ds": 18667, "Ġgenerating": 18668, "apic": 18669, "Linkage": 18670, "ĠSoutheast": 18671, "Ġot": 18672, "007": 18673, "SingleValue": 18674, "ĠDIRECTORY": 18675, "Ġdro": 18676, "barrier": 18677, "ĠIORESOURCE": 18678, "Ġ?:": 18679, "Ġspecs": 18680, "rte": 18681, "Expired": 18682, "ipc": 18683, "nextSibling": 18684, "Disposition": 18685, "Ġbreakpoint": 18686, "zs": 18687, "cssText": 18688, "Ġrefers": 18689, "\"+\"": 18690, "/*------------------------------------------------------------------------": 18691, "(_.": 18692, "ResultSet": 18693, "Handled": 18694, "CUSTOM": 18695, "Unpack": 18696, "Ġtherefore": 18697, "Ġinvariant": 18698, "Inspect": 18699, "PLAYER": 18700, "éĢī": 18701, "City": 18702, "Ġshall": 18703, "dwc": 18704, "Ġ(/": 18705, "realm": 18706, "Ġsubtract": 18707, "ĠLinear": 18708, "odd": 18709, "tector": 18710, "ĠluaL": 18711, "gzip": 18712, "ĠDispatch": 18713, "getPosition": 18714, "ĠOFF": 18715, "Stored": 18716, "ALOG": 18717, "Ġ::=": 18718, "])))": 18719, "Counters": 18720, "6000": 18721, "analysis": 18722, "Ġunregister": 18723, "Instructions": 18724, "ORS": 18725, "ferer": 18726, "Exponent": 18727, "ĠUSER": 18728, "Comput": 18729, "listed": 18730, "Ġsysfs": 18731, "Pal": 18732, "swig": 18733, "ĠDestroy": 18734, ".\"),": 18735, "TSource": 18736, "ĠLIMIT": 18737, "Ġconsumed": 18738, "ivative": 18739, "solid": 18740, "thernet": 18741, "ĠLeg": 18742, ">}": 18743, "SFER": 18744, "tel": 18745, "ENSE": 18746, "Ġyyyy": 18747, "ν": 18748, "shapes": 18749, "Ġrecogn": 18750, "Ġtimezone": 18751, "Routines": 18752, "空": 18753, "Flex": 18754, "Ġ$$": 18755, "sal": 18756, "Creating": 18757, "à¨": 18758, "NewErrParam": 18759, "leading": 18760, "ccw": 18761, "never": 18762, "NOTIFY": 18763, "googleapis": 18764, "ately": 18765, "Ġomitted": 18766, "restrict": 18767, "Ġdv": 18768, "ĠgetData": 18769, "orderby": 18770, "JR": 18771, "mpt": 18772, "loom": 18773, "Localized": 18774, "Underlying": 18775, "Ġcycles": 18776, "]&&": 18777, "Å¡": 18778, "gines": 18779, "Scopes": 18780, "Ġpiece": 18781, "OWER": 18782, "pubkey": 18783, "ctime": 18784, "è¿Ľ": 18785, "ĠGameObject": 18786, "EntityType": 18787, "Ġclosure": 18788, "CONNECTION": 18789, "Ġ(`": 18790, "Ġsynchronous": 18791, "Ġ\\$": 18792, "DebuggerNonUser": 18793, "inated": 18794, "ONCE": 18795, "Eye": 18796, "sibling": 18797, "ĠAgg": 18798, "Ġinterpreter": 18799, "HttpResponse": 18800, "Nonce": 18801, "Ġcomputation": 18802, "baseline": 18803, "ccc": 18804, "datatype": 18805, "DefaultValue": 18806, "ĠNothing": 18807, "sth": 18808, "Ġoperators": 18809, "ãģĹãģ": 18810, "Vel": 18811, "Ġmed": 18812, "getOptions": 18813, "ĠEvaluate": 18814, "fX": 18815, "little": 18816, "UTDOWN": 18817, "ucontrol": 18818, "/*.": 18819, "rds": 18820, "ĠMesh": 18821, "Ġancestor": 18822, "tasklet": 18823, "ĠOff": 18824, "æĬ": 18825, "Transparent": 18826, "clearTimeout": 18827, "Verification": 18828, "LogicException": 18829, "flater": 18830, "bookmark": 18831, "ç«": 18832, "Enemy": 18833, "OTAL": 18834, "Clients": 18835, "ToBe": 18836, "ClassLoader": 18837, "ĠNFS": 18838, "ooth": 18839, "dto": 18840, "ĠObservable": 18841, "divider": 18842, "754": 18843, "Ġ=&": 18844, "Ġisa": 18845, "ĠQModelIndex": 18846, "bby": 18847, "hom": 18848, "ĠKeyError": 18849, "omation": 18850, "Ġwasn": 18851, "SUBTEST": 18852, "Accum": 18853, "MN": 18854, "replacement": 18855, "ACTER": 18856, "|-": 18857, "cember": 18858, "Avg": 18859, "eatWhile": 18860, ",[": 18861, "MSK": 18862, "Ġunc": 18863, "*)?": 18864, "Deadline": 18865, "ĠEVENT": 18866, "Ġensures": 18867, "USR": 18868, "ĠErrno": 18869, "Guide": 18870, "retries": 18871, "declared": 18872, "Qo": 18873, "ĠBecause": 18874, "swing": 18875, "/********************************": 18876, "Il": 18877, "lipsis": 18878, "ĠBus": 18879, "ivery": 18880, "];\\": 18881, "ARGE": 18882, "Ġending": 18883, "ĠZSTD": 18884, "corner": 18885, "转": 18886, "Ġhuman": 18887, "subprocess": 18888, "Ql": 18889, "Yy": 18890, "Percentage": 18891, "Ġaffected": 18892, "unday": 18893, "216": 18894, ";}.": 18895, "Ġgetid": 18896, "typed": 18897, "unless": 18898, "RECTION": 18899, "Lz": 18900, "TN": 18901, "subset": 18902, "Zy": 18903, "chi": 18904, "ĠCurrently": 18905, "replay": 18906, "fib": 18907, "Ġdlg": 18908, "AddTo": 18909, "SEEK": 18910, "pbm": 18911, "Ġaa": 18912, "ĠOPENSSL": 18913, "motion": 18914, "MISSION": 18915, "Ġdbg": 18916, "vio": 18917, "Ġ`,`,": 18918, "TextField": 18919, "ĠwxT": 18920, "Ġoptimizer": 18921, "aping": 18922, "[]>": 18923, "mmu": 18924, "ĠWriter": 18925, "Iterations": 18926, "Ġteams": 18927, "ĠPKIX": 18928, "Ġsaving": 18929, "Defn": 18930, "={}": 18931, "getView": 18932, "Ġ101": 18933, "段": 18934, "QueryString": 18935, "Ġcrtc": 18936, "ScriptEngine": 18937, "OU": 18938, "mozilla": 18939, "æĪIJåĬŁ": 18940, "CRYPTO": 18941, "ignored": 18942, "Ġignoring": 18943, "zones": 18944, "ĠADC": 18945, "Ticket": 18946, "ج": 18947, "strain": 18948, "navigator": 18949, "Installed": 18950, "abcdefghijklmnopqrst": 18951, "moo": 18952, "Ġcomparator": 18953, "iterable": 18954, "DbType": 18955, "DEFINE": 18956, "TopLevel": 18957, "Convex": 18958, "latin": 18959, "ĠConverts": 18960, "trig": 18961, "ĠRADE": 18962, "ĠSUB": 18963, "displayName": 18964, "Ġcouldn": 18965, "VARIABLE": 18966, "kref": 18967, "EndPoint": 18968, "ĠRADEON": 18969, "dcb": 18970, "deployment": 18971, "))?": 18972, "Ġscatter": 18973, "ĠCD": 18974, "nob": 18975, "ulo": 18976, "outs": 18977, "ĠBFA": 18978, "Ġendif": 18979, "IGF": 18980, "}[": 18981, "åĬ¡": 18982, "iam": 18983, "nativeObj": 18984, "Rand": 18985, "Ġshuffle": 18986, "cycles": 18987, "Ġdrbd": 18988, "Ġnotifications": 18989, "PAY": 18990, "zilla": 18991, "Notifications": 18992, "rxq": 18993, "Yz": 18994, "ĠPolicy": 18995, "Ġ{}\".": 18996, "Ġints": 18997, "496": 18998, "Zv": 18999, "getVersion": 19000, "COMPONENT": 19001, "Mage": 19002, "Ġ#%": 19003, "iterations": 19004, "Dbg": 19005, "Normalized": 19006, "jack": 19007, "lood": 19008, "colon": 19009, "Ġweak": 19010, "ĠPhys": 19011, "Instrument": 19012, "ени": 19013, "ĠUni": 19014, "Ġplural": 19015, "PFN": 19016, "Ġinp": 19017, "Ġstm": 19018, "sci": 19019, "ĠCPPUNIT": 19020, "addTo": 19021, "Ġcombo": 19022, "0100": 19023, "sdio": 19024, "Alarm": 19025, "ĠRedirect": 19026, "2400": 19027, "Ġdeletes": 19028, "needle": 19029, "pB": 19030, "(\"//": 19031, "Ġ});\\": 19032, "organization": 19033, "MUX": 19034, "YEAR": 19035, "Ġâ": 19036, "startElement": 19037, "getTotal": 19038, "Ġnotes": 19039, "mip": 19040, "ĠSym": 19041, "ĠFake": 19042, "Ġbuffered": 19043, "pnt": 19044, "yellow": 19045, "Backdrop": 19046, "Ġprobability": 19047, "Opaque": 19048, "eli": 19049, "KeyValuePair": 19050, "NoneMatch": 19051, "ĠPx": 19052, "iteration": 19053, "Ġperforms": 19054, "ĠQuick": 19055, "Um": 19056, "umbs": 19057, "JD": 19058, "lyr": 19059, "è¾ĵ": 19060, "ĠQList": 19061, "%;": 19062, "Ġfired": 19063, "spinlock": 19064, "pyx": 19065, "Led": 19066, "isDirectory": 19067, "comma": 19068, "Callee": 19069, "gent": 19070, "Ġ}]": 19071, "Severity": 19072, "Fb": 19073, "ku": 19074, "etooth": 19075, "Cover": 19076, "Ġexecutes": 19077, "PAN": 19078, "ĠModify": 19079, "rlimit": 19080, "yer": 19081, "rip": 19082, "pivot": 19083, "UseVisualStyle": 19084, "stm": 19085, "Ġrefs": 19086, "phpcs": 19087, "Benchmark": 19088, "aq": 19089, "ĠtypeName": 19090, "CHK": 19091, "CONTA": 19092, "ĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠĠ": 19093, "Exclude": 19094, "ĠHAND": 19095, "ĠRest": 19096, "affixed": 19097, "WireType": 19098, "ел": 19099, "UseVisualStyleBackColor": 19100, "}(": 19101, "endElement": 19102, "0254": 19103, "AutoScale": 19104, "Smart": 19105, "ervation": 19106, "getClient": 19107, "ĠtearDown": 19108, "*=": 19109, "Ġba": 19110, "central": 19111, "ĠTranslate": 19112, "MarshalJSON": 19113, "æŶéĹ´": 19114, "Editing": 19115, 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