module_name
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cu_driver |
#if MIXED_SIM
sc_out<sc_logic> rst;
sc_out<sc_logic> RD; // DRAM read command
sc_out<sc_logic> WR; // DRAM write command
sc_out<sc_logic> ACT; // DRAM activate command
// sc_out<sc_logic> RSTB; //
sc_out<sc_logic> AB_mode; // Signals if the All-Banks mode is enabled
sc_out<sc_logic> pim_mode; // Signals if the PIM mode is enabled
sc_out<sc_lv<BANK_BITS> > bank_addr; // Address of the bank
sc_out<sc_lv<ROW_BITS> > row_addr; // Address of the bank row
sc_out<sc_lv<COL_BITS> > col_addr; // Address of the bank column
sc_out<sc_lv<64> > DQ; // Data input from DRAM controller (output makes no sense
sc_out<sc_lv<32> > instr; // Instruction input from CRF
#else
sc_out<bool> rst;
sc_out<bool> RD; // DRAM read command
sc_out<bool> WR; // DRAM write command
sc_out<bool> ACT; // DRAM activate command
// sc_out<bool> RSTB; //
sc_out<bool> AB_mode; // Signals if the All-Banks mode is enabled
sc_out<bool> pim_mode; // Signals if the PIM mode is enabled
sc_out<sc_uint<BANK_BITS> > bank_addr; // Address of the bank
sc_out<sc_uint<ROW_BITS> > row_addr; // Address of the bank row
sc_out<sc_uint<COL_BITS> > col_addr; // Address of the bank column
sc_out<uint64_t> DQ; // Data input from DRAM controller (output makes no sense
sc_out<uint32_t> instr; // Instruction input from CRF
#endif
SC_CTOR(cu_driver) {
SC_THREAD(driver_thread);
}
void driver_thread();
|
rocket_wrapper |
//== Ports
sc_in<bool> clock;
sc_in<bool> reset;
sc_out<sc_lv<44>> periph_aw_msg;
sc_out<bool> periph_aw_valid;
sc_in<bool> periph_aw_ready;
sc_out<sc_lv<37>> periph_w_msg;
sc_out<bool> periph_w_valid;
sc_in<bool> periph_w_ready;
sc_in<sc_lv<6>> periph_b_msg;
sc_in<bool> periph_b_valid;
sc_out<bool> periph_b_ready;
sc_out<sc_lv<44>> periph_ar_msg;
sc_out<bool> periph_ar_valid;
sc_in<bool> periph_ar_ready;
sc_in<sc_lv<39>> periph_r_msg;
sc_in<bool> periph_r_valid;
sc_out<bool> periph_r_ready;
//== Signals
sc_signal<sc_logic> my_sc_clock;
sc_signal<sc_logic> my_sc_reset;
sc_signal<sc_lv<44>> sc_periph_aw_msg;
sc_signal<sc_logic> sc_periph_aw_valid;
sc_signal<sc_logic> sc_periph_aw_ready;
sc_signal<sc_lv<37>> sc_periph_w_msg;
sc_signal<sc_logic> sc_periph_w_valid;
sc_signal<sc_logic> sc_periph_w_ready;
sc_signal<sc_lv<6>> sc_periph_b_msg;
sc_signal<sc_logic> sc_periph_b_valid;
sc_signal<sc_logic> sc_periph_b_ready;
sc_signal<sc_lv<44>> sc_periph_ar_msg;
sc_signal<sc_logic> sc_periph_ar_valid;
sc_signal<sc_logic> sc_periph_ar_ready;
sc_signal<sc_lv<39>> sc_periph_r_msg;
sc_signal<sc_logic> sc_periph_r_valid;
sc_signal<sc_logic> sc_periph_r_ready;
//sc_logic sc_periph_r_ready;
//== Instances
sc_module_name rocket_sc_module_name{"rocket" |
sc_shifter_TB |
sc_clock clk;
sc_signal<bool> rst,
sc_signal<sc_bv<7> > rst, din, qout;
Vshifter* u_Vshifter;
sc_trace_file* fp; // SystemC VCD file
SC_CTOR(sc_shifter_TB): // constructor
clk("clk", 100, SC_NS, 0.5, 0.0, SC_NS, false)
{
// instantiate DUT
u_Vshifter = new Vshifter("u_Vshifter");
// Binding
u_Vshifter->clk(clk);
u_Vshifter->rst(rst);
u_Vshifter->din(din);
u_Vshifter->qout(qout);
SC_THREAD(test_generator);
sensitive << clk;
// VCD Trace
fp = sc_create_vcd_trace_file("sc_shifter_TB");
sc_trace(fp, clk, "clk");
sc_trace(fp, rst, "rst");
sc_trace(fp, din, "din");
sc_trace(fp, qout, "qout");
}
void test_generator()
{
int test_count =0;
din.write(0);
rst.write(0);
wait(clk.posedge_event());
wait(clk.posedge_event());
rst.write(1);
wait(clk.posedge_event());
while(true)
{
din.write(1);
wait(clk.posedge_event());
if (test_count>6)
{
sc_close_vcd_trace_file(fp);
sc_stop();
}
else
test_count++;
}
}
|
communicationInterfaceTB |
sc_signal<sc_uint<12> > inData;
sc_signal<bool> clock , reset , clear;
sc_signal<sc_uint<4> > payloadOut;
sc_signal<sc_uint<8> > countOut , errorOut;
void clockSignal();
void clearSignal();
void resetSignal();
void inDataSignal();
communicationInterface* cI;
SC_CTOR(communicationInterfaceTB) {
cI = new communicationInterface ("CI");
cI->clock(clock);
cI->inData(inData);
cI->reset(reset);
cI->clear(clear);
cI->payloadOut(payloadOut);
cI->countOut(countOut);
cI->errorOut(errorOut);
SC_THREAD(clockSignal);
SC_THREAD(clearSignal);
SC_THREAD(resetSignal);
SC_THREAD(inDataSignal);
}
|
fir_top |
sc_in<bool> CLK;
sc_in<bool> RESET;
sc_in<bool> IN_VALID;
sc_in<int> SAMPLE;
sc_out<bool> OUTPUT_DATA_READY;
sc_out<int> RESULT;
sc_signal<unsigned> state_out;
fir_fsm *fir_fsm1;
fir_data *fir_data1;
SC_CTOR(fir_top) {
fir_fsm1 = new fir_fsm("FirFSM");
fir_fsm1->clock(CLK);
fir_fsm1->reset(RESET);
fir_fsm1->in_valid(IN_VALID);
fir_fsm1->state_out(state_out);
fir_data1 = new fir_data("FirData");
fir_data1 -> reset(RESET);
fir_data1 -> state_out(state_out);
fir_data1 -> sample(SAMPLE);
fir_data1 -> result(RESULT);
fir_data1 -> output_data_ready(OUTPUT_DATA_READY);
}
|
top |
HMAC hmc;
SHA512_masked sha384_1;
SHA512_masked sha384_2;
hmac_sha hmacsha;
blocking_in<block> top_hmac;
blocking_out<sc_biguint<KEY_WIDTH>> top_tag;
Blocking<block> hmac_msg;
Blocking<sc_biguint<KEY_WIDTH>> tag;
Blocking<sha_splitter> sha_msg_split_1, sha_msg_split_2;
Blocking<sc_biguint<DIGEST_WIDTH>> H1_setup_digest, hmac_1_digest, hmac_2_digest;
Blocking<sha_block> h_sha_msg_1, h_sha_msg_2;
Blocking<sc_biguint<DIGEST_WIDTH>> sha_1_digest, sha_2_digest;
SC_CTOR(top) : hmc("hmc"),
sha384_1("sha384_1"),
sha384_2("sha384_2"),
hmacsha("hmacsha"),
top_hmac("top_in"),
top_tag("top_out"),
hmac_msg("hmac_msg"),
tag("tag"),
sha_msg_split_1("sha_msg_split_1"),
sha_msg_split_2("sha_msg_split_2"),
//sha_msg_split_2("sha_msg_split_2"),
H1_setup_digest("H1_setup_digest"),
hmac_1_digest("hmac_1_digest"),
hmac_2_digest("hmac_2_digest"),
h_sha_msg_1("h_sha_msg_1"),
h_sha_msg_2("h_sha_msg_2"),
sha_1_digest("sha_1_digest"),
sha_2_digest("sha_2_digest")
{
hmc.hmac_msg(top_hmac);
hmc.sha_msg_1(sha_msg_split_1);
hmacsha.sha_msg_split_1(sha_msg_split_1);
hmacsha.h_sha_msg_1(h_sha_msg_1);
sha384_1.SHA_Input(h_sha_msg_1);
sha384_1.out(sha_1_digest);
hmacsha.hmac_setup_digest(H1_setup_digest);
hmc.H1_setup_digest(H1_setup_digest);
// hmc.sha_msg_2(sha_msg_split_2);
// hmacsha.sha_msg_split_2(sha_msg_split_2);
hmacsha.sha_1_digest(sha_1_digest);
hmacsha.hmac_1_digest(hmac_1_digest);
hmc.H1_digest(hmac_1_digest);
hmc.sha_msg_2(sha_msg_split_2);
hmacsha.sha_msg_split_2(sha_msg_split_2);
hmacsha.h_sha_msg_2(h_sha_msg_2);
sha384_2.SHA_Input(h_sha_msg_2);
sha384_2.out(sha_2_digest);
hmacsha.sha_2_digest(sha_2_digest);
hmacsha.hmac_2_digest(hmac_2_digest);
hmc.H2_digest(hmac_2_digest);
hmc.tag(top_tag);
}
|
transmitter)
//class transmitter : public sc_module
{
/// Input port for datas from the switch
sc_in<Packet> datain;
/// reset port
sc_in<bool> rst_n;
/// clk port
sc_in<bool> clk;
/// full port. If it's set it indicates that the fifo of the transmitter is to small to contain all datas
sc_out<sc_bit> full;
/// strobe output port.It changes with datac
sc_out<sc_bit> strobe;
/// data to the receiver sub-block of the wrapper
sc_out<Packet> datac;
/// main process of the transmitter module
void evaluate();
//Packet FIFO[FIFO_TX_DIM];
/// fifo used to manage case of fast transmitter
Packet* FIFO;
int i,last_pos,c;
ofstream tx_file;
//SC_CTOR(transmitter)
/// constructor of the transmitter
SC_HAS_PROCESS(transmitter);
transmitter(sc_module_name name_ , int N_R , int N_T, int fifo_tx_dim) : sc_module(name_), m_N_R(N_R), m_N_T(N_T),m_fifo_tx_dim(fifo_tx_dim |
SC_METHOD(evaluate);
sensitive<<clk.pos()<<rst_n.neg();
FIFO= new Packet[m_fifo_tx_dim];
for (i=0;i<m_fifo_tx_dim;i++)
FIFO[i]=empty_NL_PDU;
last_pos=0;
if(m_N_R > m_N_T)
c=m_N_R;
tx_file.open ("tx_file.txt",ios::trunc);
tx_file << "SIMULATION STARTS NOW: "<<endl<<endl;
tx_file.close();
}
private:
int m_N_R,m_N_T,m_fifo_tx_dim;
|
sc_fir8 |
sc_in<bool> clk;
sc_in<sc_uint<8> > Xin;
sc_out<sc_uint<8> > Xout;
sc_in<sc_uint<16> > Yin;
sc_out<sc_uint<16> > Yout;
sc_signal<sc_uint<8> > X[FILTER_TAP_NUM]; // Shift Register X
void fir8_thread(void)
{
uint8_t x;
uint8_t yL, yH;
uint16_t y;
while(true)
{
wait(clk.posedge_event());
x = (uint8_t)Xin.read();
while(write(fd, &x, 1)<=0) // Send Byte
usleep(100);
for (int i=0; i<FILTER_TAP_NUM; i++)
{
while(read(fd, &x, 1)<=0) // Receive Byte: Shift Register of X
usleep(100);
X[i].write(sc_uint<8>(x));
}
while(read(fd, &yL, 1)<=0) // Receive Byte:LSB of y
usleep(100);
while(read(fd, &yH, 1)<=0) // Receive Byte:MSB of y
usleep(100);
y = (uint16_t)(yH<<8) | (uint16_t)(yL);
Yout.write(y);
}
}
// Arduino Serial IF
int fd; // Serial port file descriptor
struct termios options; // Serial port setting
#ifdef VCD_TRACE_FIR8
sc_trace_file* fp; // VCD file
#endif
SC_CTOR(sc_fir8):
clk("clk"),
Xin("Xin"),
Xout("Xout"),
Yin("Yin"),
Yout("Yout")
{
SC_THREAD(fir8_thread);
sensitive << clk;
// Arduino DUT
//fd = open("/dev/ttyACM0", O_RDWR | O_NDELAY | O_NOCTTY);
fd = open("/dev/ttyACM0", O_RDWR | O_NOCTTY);
if (fd < 0)
{
perror("Error opening serial port");
//return -1;
}
// Set up serial port
options.c_cflag = B9600 | CS8 | CLOCAL | CREAD;
options.c_iflag = IGNPAR;
options.c_oflag = 0;
options.c_lflag = 0;
// Apply the settings
tcflush(fd, TCIFLUSH);
tcsetattr(fd, TCSANOW, &options);
// Establish Contact
int len = 0;
char rx;
while(!len)
len = read(fd, &rx, 1);
if (rx=='A')
write(fd, &rx, 1);
printf("Connection established...\n");
#ifdef VCD_TRACE_FIR8
// WAVE
fp = sc_create_vcd_trace_file("sc_fir8");
fp->set_time_unit(100, SC_PS); // resolution (trace) ps
sc_trace(fp, clk, "clk");
sc_trace(fp, Xin, "Xin");
sc_trace(fp, Xout, "Xout");
sc_trace(fp, Yin, "Yin");
sc_trace(fp, Yout, "Yout");
char szTrace[8];
for (int i=0; i<FILTER_TAP_NUM; i++)
{
sprintf(szTrace, "X_%d", i);
sc_trace(fp, X[i], szTrace);
}
#endif
}
~sc_fir8(void)
{
close(fd);
}
|
fir |
sc_in<bool> clk;
sc_in<bool> rst;
sc_in<sc_int<16>> inp;
sc_out<sc_int<16>> out;
// Handshake signals
sc_in<bool> inp_vld;
sc_out<bool> inp_rdy;
sc_out<bool> out_vld;
sc_in<bool> out_rdy;
void fir_main();
SC_CTOR( fir ) {
SC_CTHREAD(fir_main, clk.pos());
reset_signal_is(rst, true);
}
|
CounterModule |
// Inputs
sc_in<bool> clk;
sc_in<bool> reset;
sc_in<bool> up_down_ctrl;
sc_in<bool> count_enable;
//Outputs
sc_out<sc_uint<N> > count_out;
sc_out<bool> overflow_intr;
sc_out<bool> underflow_intr;
// Variables
sc_uint<N> count;
// Main function of the module
void do_count();
SC_CTOR(CounterModule){
SC_METHOD(do_count);
sensitive << clk.pos();
}
|
i2c_controller_tb |
sc_clock *clk;
sc_signal<bool> rst;
sc_signal<sc_uint<7>> addr;
sc_signal<sc_uint<8>> data_in;
sc_signal<bool> enable;
sc_signal<bool> rw;
sc_signal<sc_lv<8>> data_out;
sc_signal<bool> ready;
sc_signal<sc_logic, SC_MANY_WRITERS> i2c_sda;
sc_signal<sc_logic> i2c_scl;
i2c_controller *master;
i2c_slave_controller *slave;
SC_CTOR(i2c_controller_tb)
{
clk = new sc_clock("clk",2,SC_NS);
master = new i2c_controller("i2c_controller");
master->clk(*clk);
master->rst(rst);
master->addr(addr);
master->data_in(data_in);
master->enable(enable);
master->rw(rw);
master->data_out(data_out);
master->ready(ready);
master->i2c_sda(i2c_sda);
master->i2c_scl(i2c_scl);
slave = new i2c_slave_controller("i2c_slave_controller");
slave->sda(i2c_sda);
slave->scl(i2c_scl);
SC_THREAD(stimuli);
sensitive << *clk << rst;
}
~i2c_controller_tb()
{
delete master;
delete slave;
}
void stimuli();
|
sc_DUT_TB |
sc_clock CLK;
sc_signal<bool> nCLR;
sc_signal<bool> nLOAD;
sc_signal<bool> ENP;
sc_signal<bool> ENT;
sc_signal<bool> RCO;
// Verilator treats all Verilog's vector as <uint32_t>
sc_signal<uint32_t> Digit;
sc_signal<uint32_t> Din;
sc_signal<uint32_t> Dout;
// Exact DUT ports' vector width
sc_signal<sc_uint<2> > Digit_n2;
sc_signal<sc_uint<4> > Din_n4;
sc_signal<sc_uint<16> > Dout_n16;
// Verilated DUT or Foreign Verilog
VDUT* u_VDUT;
#ifdef CO_EMULATION
// Emulator DUT
DUT* u_DUT;
sc_signal<sc_uint<16> > Dout_emu;
sc_signal<bool> RCO_emu;
#endif
// Convert Verilator's ports to DUT's ports
void conv_method()
{
Digit_n2.write((sc_uint<2>)Digit);
Din_n4.write((sc_uint<4>)Din);
Dout_n16.write((sc_uint<16>)Dout);
}
void test_generator();
void monitor();
sc_trace_file* fp; // VCD file
SC_CTOR(sc_DUT_TB) : // Constructor
CLK("CLK", 100, SC_NS, 0.5, 0.0, SC_NS, false)
{
SC_THREAD(test_generator);
sensitive << CLK;
SC_THREAD(monitor);
sensitive << CLK;
SC_METHOD(conv_method);
sensitive << Din << Dout << Digit;
// DUT Instantiation
u_VDUT = new VDUT("u_VDUT");
// Binding
u_VDUT->CLK(CLK);
u_VDUT->nCLR(nCLR);
u_VDUT->nLOAD(nLOAD);
u_VDUT->Digit(Digit);
u_VDUT->ENP(ENP);
u_VDUT->ENT(ENT);
u_VDUT->Din(Din);
u_VDUT->Dout(Dout);
u_VDUT->RCO(RCO);
#ifdef CO_EMULATION
u_DUT = new DUT("u_DUT");
// Binding
u_DUT->CLK(CLK);
u_DUT->nCLR(nCLR);
u_DUT->nLOAD(nLOAD);
u_DUT->Digit(Digit_n2);
u_DUT->Din(Din_n4);
u_DUT->Dout(Dout_emu);
u_DUT->RCO(RCO_emu);
#endif
// VCD Trace
fp = sc_create_vcd_trace_file("sc_DUT_TB");
fp->set_time_unit(100, SC_PS);
sc_trace(fp, CLK, "CLK");
sc_trace(fp, nCLR, "nCLR");
sc_trace(fp, nLOAD, "nLOAD");
sc_trace(fp, Digit_n2, "Digit");
sc_trace(fp, ENP, "ENP");
sc_trace(fp, ENT, "ENT");
sc_trace(fp, Din_n4, "Din");
sc_trace(fp, Dout_n16, "Dout");
sc_trace(fp, RCO, "RCO");
#ifdef CO_EMULATION
sc_trace(fp, Dout_emu, "Dout_emu");
sc_trace(fp, RCO_emu, "RCO_emu");
#endif
}
// Destructor
~sc_DUT_TB()
{}
|
dut_cycsim |
// Port declarations.
sc_in< bool > clk;
sc_in< bool > rst;
sc_out< bool > din_busy;
sc_in< bool > din_vld;
sc_in< sc_uint< 8 > > din_data_a;
sc_in< sc_uint< 8 > > din_data_b;
sc_in< sc_uint< 8 > > din_data_c;
sc_in< sc_uint< 8 > > din_data_d;
sc_in< sc_uint< 8 > > din_data_e;
sc_in< sc_uint< 8 > > din_data_f;
sc_in< sc_uint< 8 > > din_data_g;
sc_in< sc_uint< 8 > > din_data_h;
sc_in< bool > dout_busy;
sc_out< bool > dout_vld;
sc_out< sc_uint< 32 > > dout_data;
dut_cycsim( sc_module_name in_name=sc_module_name(sc_gen_unique_name(" dut") ) )
: sc_module(in_name)
,clk("clk")
,rst("rst")
,din_busy("din_busy")
,din_vld("din_vld")
,din_data_a("din_data_a"),
din_data_b("din_data_b"),
din_data_c("din_data_c"),
din_data_d("din_data_d"),
din_data_e("din_data_e"),
din_data_f("din_data_f"),
din_data_g("din_data_g"),
din_data_h("din_data_h")
,dout_busy("dout_busy")
,dout_vld("dout_vld")
,dout_data("dout_data")
{
|
dut |
sc_in_clk clk;
sc_in< bool > rst;
cynw_p2p< input_data, ioConfig >::in in;
cynw_p2p< output_data, ioConfig >::out out;
stream_16X8::in<ioConfig> streamin;
stream_16X8::out<ioConfig> streamout;
SC_CTOR( dut )
: clk( "clk" )
, rst( "rst" )
, in( "in" )
, out( "out" )
, streamin( "streamin" )
, streamout( "streamout" )
{
SC_CTHREAD( thread1, clk.pos() );
reset_signal_is( rst, false );
in.clk_rst( clk, rst );
out.clk_rst( clk, rst );
streamin.clk_rst( clk, rst );
streamout.clk_rst( clk, rst );
}
sc_uint<8> x[8];
sc_uint<8> y[4];
sc_uint<8> data[16];
void thread1();
|
tb |
sc_in<bool> clk;
sc_out<bool> rst;
sc_out< sc_int<16> > inp;
sc_out<bool> inp_vld;
sc_in<bool> inp_rdy;
sc_in< sc_int<16> > outp;
sc_in<bool> outp_vld;
sc_out<bool> outp_rdy;
void source();
void sink();
FILE *outfp;
sc_time start_time[64], end_time[64], clock_period;
SC_CTOR( tb ){
SC_CTHREAD( source, clk.pos() );
SC_CTHREAD( sink, clk.pos() );
}
|
s3 |
sc_in<sc_uint<6> > stage1_input;
sc_out<sc_uint<4> > stage1_output;
void s3_box();
SC_CTOR(s3)
{
SC_METHOD(s3_box);
sensitive << stage1_input;
}
|
display |
// Port for input by channel
sc_port< sc_csp_channel_in_if< sc_uint<8> > > result_channel_port;
SC_CTOR(display)
{
SC_THREAD(output);
}
// Main method
void output();
|
dut_cycsim |
// Port declarations.
sc_in< bool > clk;
sc_in< bool > rst;
sc_out< bool > din_1_busy;
sc_in< bool > din_1_vld;
sc_in< sc_uint< 8 > > din_1_data;
sc_out< bool > din_2_busy;
sc_in< bool > din_2_vld;
sc_in< sc_uint< 8 > > din_2_data;
sc_in< bool > dout_busy;
sc_out< bool > dout_vld;
sc_out< sc_uint< 9 > > dout_data;
dut_cycsim( sc_module_name in_name=sc_module_name(sc_gen_unique_name(" dut") ) )
: sc_module(in_name)
,clk("clk")
,rst("rst")
,din_1_busy("din_1_busy")
,din_1_vld("din_1_vld")
,din_1_data("din_1_data")
,din_2_busy("din_2_busy")
,din_2_vld("din_2_vld")
,din_2_data("din_2_data")
,dout_busy("dout_busy")
,dout_vld("dout_vld")
,dout_data("dout_data")
{
|
sc_top |
sc_clock clk;
sc_signal<bool> reset;
sc_signal<bool> cs;
sc_signal<bool> rw;
sc_signal<bool> ready;
#ifdef VERILATOR
sc_signal<uint32_t> addr;
sc_signal<uint32_t> data_in;
sc_signal<uint32_t> data_out;
#else
sc_signal<sc_uint<16>> addr;
sc_signal<sc_uint<32>> data_in;
sc_signal<sc_uint<32>> data_out;
#endif
Vtop *u_top;
bfm *u_bfm;
SC_CTOR(sc_top) :
clk("clk", 10, SC_NS, 0.5, 5, SC_NS, true),
reset("reset"), cs("cs"), rw("rw"), addr("addr"), ready("ready"), data_in("data_in"), data_out("data_out") {
#ifdef VERILATOR
u_top = new Vtop{"top" |
V_fir_pe |
sc_in<bool> clk;
sc_in<bool> Rdy;
sc_out<bool> Vld;
sc_in<sc_uint<6> > Cin;
sc_in<sc_uint<4> > Xin;
sc_out<sc_uint<4> > Xout;
sc_in<sc_uint<4> > Yin;
sc_out<sc_uint<4> > Yout;
Vfir_pe* u_Vfir_pe;
sc_signal<uint32_t> _Cin;
sc_signal<uint32_t> _Xin;
sc_signal<uint32_t> _Xout;
sc_signal<uint32_t> _Yin;
sc_signal<uint32_t> _Yout;
sc_signal<bool> _Rdy;
sc_signal<bool> _Vld;
void pe_method(void)
{
_Cin = (uint32_t)Cin.read();
_Xin = (uint32_t)Xin.read();
_Yin = (uint32_t)Yin.read();
_Rdy = Rdy.read();
Xout.write(sc_uint<4>(_Xout));
Yout.write(sc_uint<4>(_Yout));
Vld.write(_Vld);
}
SC_CTOR(V_fir_pe):
clk("clk"),
Rdy("Rdy"), _Rdy("_Rdy"),
Vld("Vld"), _Vld("_Vld"),
Cin("Cin"), _Cin("_Cin"),
Xin("Xin"), _Xin("_Xin"),
Xout("Xout"), _Xout("_Xout"),
Yin("Yin"), _Yin("_Yin"),
Yout("Yout"), _Yout("_Yout")
{
SC_METHOD(pe_method);
sensitive << clk << Cin << Xin << Yin << Rdy;
// Instantiate Verilated PE
u_Vfir_pe = new Vfir_pe("u_Vfir_pe");
u_Vfir_pe->clk(clk);
u_Vfir_pe->Cin(_Cin);
u_Vfir_pe->Xin(_Xin);
u_Vfir_pe->Xout(_Xout);
u_Vfir_pe->Yin(_Yin);
u_Vfir_pe->Yout(_Yout);
u_Vfir_pe->Rdy(_Rdy);
u_Vfir_pe->Vld(_Vld);
}
~V_fir_pe(void)
{
}
|
Neuron |
sc_in<float> input1, input2;
sc_out<float> output;
float w1, w2, b, y;
float output_temp;
void neuron();
SC_CTOR(Neuron) {
SC_METHOD(neuron);
sensitive << input1 << input2;
}
|
ACCNAME |
//debug vars
bool print_po = false;
bool print_wo = false;
int simplecounter=0;
ACC_DTYPE<14> depth;
sc_in<bool> clock;
sc_in <bool> reset;
sc_fifo_in<DATA> din1;
sc_fifo_in<DATA> din2;
sc_fifo_in<DATA> din3;
sc_fifo_in<DATA> din4;
sc_fifo_out<DATA> dout1;
sc_fifo_out<DATA> dout2;
sc_fifo_out<DATA> dout3;
sc_fifo_out<DATA> dout4;
sc_signal<bool> read_inputs;
sc_signal<bool> rtake;
sc_signal<bool> ltake;
sc_signal<int> llen;
sc_signal<int> rlen;
sc_signal<int> lhs_block_max;
sc_signal<int> rhs_block_max;
#ifndef __SYNTHESIS__
sc_signal<bool,SC_MANY_WRITERS> d_in1;
sc_signal<bool,SC_MANY_WRITERS> d_in2;
sc_signal<bool,SC_MANY_WRITERS> d_in3;
sc_signal<bool,SC_MANY_WRITERS> d_in4;
sc_signal<bool,SC_MANY_WRITERS> schedule;
sc_signal<bool,SC_MANY_WRITERS> out_check;
sc_signal<bool,SC_MANY_WRITERS> gemm_unit_1_ready;
sc_signal<bool,SC_MANY_WRITERS> write1;
sc_signal<bool,SC_MANY_WRITERS> arrange1;
#else
sc_signal<bool> d_in1;
sc_signal<bool> d_in2;
sc_signal<bool> d_in3;
sc_signal<bool> d_in4;
sc_signal<bool> schedule;
sc_signal<bool> out_check;
sc_signal<bool> gemm_unit_1_ready;
sc_signal<bool> write1;
sc_signal<bool> arrange1;
#endif
sc_signal<int> gemm_unit_1_l_pointer;
sc_signal<bool> gemm_unit_1_iwuse;
ACC_DTYPE<32> g1 [256];
ACC_DTYPE<8> r1 [256];
//GEMM 1 Inputs
ACC_DTYPE<32> lhsdata1a[4096];
ACC_DTYPE<32> lhsdata2a[4096];
ACC_DTYPE<32> lhsdata3a[4096];
ACC_DTYPE<32> lhsdata4a[4096];
//Global Weights
ACC_DTYPE<32> rhsdata1[8192];
ACC_DTYPE<32> rhsdata2[8192];
ACC_DTYPE<32> rhsdata3[8192];
ACC_DTYPE<32> rhsdata4[8192];
// //new sums bram
// ACC_DTYPE<32> lhs_sum1[512];
// ACC_DTYPE<32> lhs_sum2[512];
// ACC_DTYPE<32> lhs_sum3[512];
// ACC_DTYPE<32> lhs_sum4[512];
//
// ACC_DTYPE<32> rhs_sum1[512];
// ACC_DTYPE<32> rhs_sum2[512];
// ACC_DTYPE<32> rhs_sum3[512];
// ACC_DTYPE<32> rhs_sum4[512];
//
// //crf & crx
// ACC_DTYPE<32> crf1[512];
// ACC_DTYPE<32> crf2[512];
// ACC_DTYPE<32> crf3[512];
// ACC_DTYPE<32> crf4[512];
// ACC_DTYPE<32> crx[512];
//new sums bram
ACC_DTYPE<32> lhs_sum1[1024];
ACC_DTYPE<32> lhs_sum2[1024];
ACC_DTYPE<32> lhs_sum3[1024];
ACC_DTYPE<32> lhs_sum4[1024];
ACC_DTYPE<32> rhs_sum1[1024];
ACC_DTYPE<32> rhs_sum2[1024];
ACC_DTYPE<32> rhs_sum3[1024];
ACC_DTYPE<32> rhs_sum4[1024];
//crf & crx
ACC_DTYPE<32> crf1[1024];
ACC_DTYPE<32> crf2[1024];
ACC_DTYPE<32> crf3[1024];
ACC_DTYPE<32> crf4[1024];
ACC_DTYPE<32> crx[1024];
int ra=0;
sc_fifo<int> WRQ1;
sc_fifo<int> WRQ2;
sc_fifo<int> WRQ3;
sc_fifo<char> sIs1;
sc_fifo<char> sIs2;
sc_fifo<char> sIs3;
sc_fifo<char> sIs4;
sc_fifo<char> sIs5;
sc_fifo<char> sIs6;
sc_fifo<char> sIs7;
sc_fifo<char> sIs8;
sc_fifo<char> sIs9;
sc_fifo<char> sIs10;
sc_fifo<char> sIs11;
sc_fifo<char> sIs12;
sc_fifo<char> sIs13;
sc_fifo<char> sIs14;
sc_fifo<char> sIs15;
sc_fifo<char> sIs16;
sc_fifo<char> sWs1;
sc_fifo<char> sWs2;
sc_fifo<char> sWs3;
sc_fifo<char> sWs4;
sc_fifo<char> sWs5;
sc_fifo<char> sWs6;
sc_fifo<char> sWs7;
sc_fifo<char> sWs8;
sc_fifo<char> sWs9;
sc_fifo<char> sWs10;
sc_fifo<char> sWs11;
sc_fifo<char> sWs12;
sc_fifo<char> sWs13;
sc_fifo<char> sWs14;
sc_fifo<char> sWs15;
sc_fifo<char> sWs16;
sc_signal<int> w1S;
sc_signal<int> w2S;
sc_signal<int> w3S;
sc_signal<int> w4S;
#ifndef __SYNTHESIS__
int weight_max_index=0;
int input_max_index=0;
int local_weight_max_index=0;
int g1_macs=0;
int g2_macs=0;
int g3_macs=0;
int g4_macs=0;
int g1_out_count=0;
int g2_out_count=0;
int g3_out_count=0;
int g4_out_count=0;
#endif
sc_out<int> inS;
sc_out<int> read_cycle_count;
sc_out<int> process_cycle_count;
sc_out<int> gemm_1_idle;
sc_out<int> gemm_2_idle;
sc_out<int> gemm_3_idle;
sc_out<int> gemm_4_idle;
sc_out<int> gemm_1_write;
sc_out<int> gemm_2_write;
sc_out<int> gemm_3_write;
sc_out<int> gemm_4_write;
sc_out<int> gemm_1;
sc_out<int> gemm_2;
sc_out<int> gemm_3;
sc_out<int> gemm_4;
sc_out<int> wstall_1;
sc_out<int> wstall_2;
sc_out<int> wstall_3;
sc_out<int> wstall_4;
sc_out<int> rmax;
sc_out<int> lmax;
sc_out<int> outS;
sc_out<int> w1SS;
sc_out<int> w2SS;
sc_out<int> w3SS;
sc_out<int> w4SS;
sc_out<int> schS;
sc_out<int> p1S;
void Input_Handler();
void Output_Handler();
void Worker1();
void Data_In1();
void Data_In2();
void Data_In3();
void Data_In4();
void Tracker();
void Scheduler();
void Post1();
void schedule_gemm_unit(int, int, int, int, int,int,int);
int SHR(int,int);
void Read_Cycle_Counter();
void Process_Cycle_Counter();
void Writer_Cycle_Counter();
SC_HAS_PROCESS(ACCNAME);
// Parameters for the DUT
ACCNAME(sc_module_name name_) :sc_module(name_),WRQ1(512),sIs1(2048),sIs2(2048),sIs3(2048),sIs4(2048),sIs5(2048),sIs6(2048),sIs7(2048),sIs8(2048),
sIs9(2048),sIs10(2048),sIs11(2048),sIs12(2048),sIs13(2048),sIs14(2048),sIs15(2048),sIs16(2048),
WRQ2(512),sWs1(2048),sWs2(2048),sWs3(2048),sWs4(2048),sWs5(2048),sWs6(2048),sWs7(2048),sWs8(2048),
sWs9(2048),sWs10(2048),sWs11(2048),sWs12(2048),sWs13(2048),sWs14(2048),sWs15(2048),sWs16(2048),WRQ3(512){
SC_CTHREAD(Input_Handler,clock.pos());
reset_signal_is(reset,true);
SC_CTHREAD(Worker1,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Output_Handler,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Data_In1,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Data_In2,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Data_In3,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Data_In4,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Scheduler,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Post1,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Read_Cycle_Counter,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Process_Cycle_Counter,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Writer_Cycle_Counter,clock);
reset_signal_is(reset,true);
#pragma HLS RESOURCE variable=din1 core=AXI4Stream metadata="-bus_bundle S_AXIS_DATA1" port_map={{din1_0 TDATA} {din1_1 TLAST}}
#pragma HLS RESOURCE variable=din2 core=AXI4Stream metadata="-bus_bundle S_AXIS_DATA2" port_map={{din2_0 TDATA} {din2_1 TLAST}}
#pragma HLS RESOURCE variable=din3 core=AXI4Stream metadata="-bus_bundle S_AXIS_DATA3" port_map={{din3_0 TDATA} {din3_1 TLAST}}
#pragma HLS RESOURCE variable=din4 core=AXI4Stream metadata="-bus_bundle S_AXIS_DATA4" port_map={{din4_0 TDATA} {din4_1 TLAST}}
#pragma HLS RESOURCE variable=dout1 core=AXI4Stream metadata="-bus_bundle M_AXIS_DATA1" port_map={{dout1_0 TDATA} {dout1_1 TLAST}}
#pragma HLS RESOURCE variable=dout2 core=AXI4Stream metadata="-bus_bundle M_AXIS_DATA2" port_map={{dout2_0 TDATA} {dout2_1 TLAST}}
#pragma HLS RESOURCE variable=dout3 core=AXI4Stream metadata="-bus_bundle M_AXIS_DATA3" port_map={{dout3_0 TDATA} {dout3_1 TLAST}}
#pragma HLS RESOURCE variable=dout4 core=AXI4Stream metadata="-bus_bundle M_AXIS_DATA4" port_map={{dout4_0 TDATA} {dout4_1 TLAST}}
#pragma HLS array_partition variable=g1 complete dim=0
#pragma HLS RESET variable=reset
}
|
s6 |
sc_in<sc_uint<6> > stage1_input;
sc_out<sc_uint<4> > stage1_output;
void s6_box();
SC_CTOR(s6)
{
SC_METHOD(s6_box);
sensitive << stage1_input;
}
|
sc_fir8_tb |
sc_clock clk;
sc_signal<sc_uint<8> > Xin;
sc_signal<sc_uint<8> > Xout;
sc_signal<sc_uint<16> > Yin;
sc_signal<sc_uint<16> > Yout;
#ifdef EMULATED
sc_signal<sc_uint<8> > E_Xout;
sc_signal<sc_uint<16> > E_Yout;
#endif
sc_fir8* u_sc_fir8;
// Test utilities
void Test_Gen();
void Test_Mon();
sc_uint<8> x[F_SAMPLE]; // Time seq. input
sc_uint<16> y[F_SAMPLE]; // Filter output
#ifdef VCD_TRACE_FIR8_TB
sc_trace_file* fp; // VCD file
#endif
SC_CTOR(sc_fir8_tb):
clk("clk", 100, SC_NS, 0.5, 0.0, SC_NS, false),
Xin("Xin"),
Xout("Xout"),
Yin("Yin"),
Yout("Yout")
{
SC_THREAD(Test_Gen);
sensitive << clk;
SC_THREAD(Test_Mon);
sensitive << clk;
// Instaltiate FIR8
u_sc_fir8 = new sc_fir8("u_sc_fir8");
u_sc_fir8->clk(clk);
u_sc_fir8->Xin(Xin);
u_sc_fir8->Xout(Xout);
u_sc_fir8->Yin(Yin);
u_sc_fir8->Yout(Yout);
#ifdef EMULATED
u_sc_fir8->E_Xout(E_Xout);
u_sc_fir8->E_Yout(E_Yout);
#endif
#ifdef VCD_TRACE_FIR8_TB
// WAVE
fp = sc_create_vcd_trace_file("sc_fir8_tb");
fp->set_time_unit(100, SC_PS); // resolution (trace) ps
sc_trace(fp, clk, "clk");
sc_trace(fp, Xin, "Xin");
sc_trace(fp, Xout, "Xout");
sc_trace(fp, Yin, "Yin");
sc_trace(fp, Yout, "Yout");
#endif
}
~sc_fir8_tb(void)
{
}
|
Neural_Network |
sc_in<float> input1, input2;
sc_out<float> output;
sc_signal<float> c1, c2;
Neuron* N1;
Neuron* N2;
Neuron* N3;
SC_CTOR(Neural_Network) {
// vvvvv put your code here vvvvv
N1 = new Neuron("N1");
N2 = new Neuron("N2");
N3 = new Neuron("N3");
N1->input1(input1);
N1->input2(input2);
N1->output(c1);
N2->input1(input1);
N2->input2(input2);
N2->output(c2);
N3->input1(c1);
N3->input2(c2);
N3->output(output);
// ^^^^^ put your code here ^^^^^
N1->w1 = 10;
N1->w2 = -10;
N1->b = -5;
N2->w1 = -10;
N2->w2 = 10;
N2->b = -5;
N3->w1 = 10;
N3->w2 = 10;
N3->b = -5;
}
|
tb |
sc_out < sc_uint<4> > OPa,OPb;
sc_out < sc_uint<4> > OP;
sc_in<bool> Clk;
void tbGen() {
OPa.write(0111);
OPb.write(0001);
OP.write(0);
wait(10,SC_NS);
OPa.write(0111);
OPb.write(0001);
OP.write(1);
wait(10,SC_NS);
OPa.write(0111);
OPb.write(0001);
OP.write(2);
wait(10,SC_NS);
OPa.write(0111);
OPb.write(0001);
OP.write(3);
wait(10,SC_NS);
OPa.write(0111);
OPb.write(0001);
OP.write(4);
wait(10,SC_NS);
OPa.write(0111);
OPb.write(0001);
OP.write(5);
wait(10,SC_NS);
sc_stop();
}
SC_CTOR(tb) {
SC_THREAD(tbGen);
}
|
dut_cycsim |
// Port declarations.
sc_in< bool > clk;
sc_in< bool > rst;
sc_out< bool > din_busy;
sc_in< bool > din_vld;
sc_in< sc_uint< 8 > > din_data_a;
sc_in< sc_uint< 8 > > din_data_b;
sc_in< sc_uint< 8 > > din_data_c;
sc_in< sc_uint< 8 > > din_data_d;
sc_in< sc_uint< 8 > > din_data_e;
sc_in< sc_uint< 8 > > din_data_f;
sc_in< sc_uint< 8 > > din_data_g;
sc_in< sc_uint< 8 > > din_data_h;
sc_in< bool > dout_busy;
sc_out< bool > dout_vld;
sc_out< sc_uint< 32 > > dout_data;
dut_cycsim( sc_module_name in_name=sc_module_name(sc_gen_unique_name(" dut") ) )
: sc_module(in_name)
,clk("clk")
,rst("rst")
,din_busy("din_busy")
,din_vld("din_vld")
,din_data_a("din_data_a"),
din_data_b("din_data_b"),
din_data_c("din_data_c"),
din_data_d("din_data_d"),
din_data_e("din_data_e"),
din_data_f("din_data_f"),
din_data_g("din_data_g"),
din_data_h("din_data_h")
,dout_busy("dout_busy")
,dout_vld("dout_vld")
,dout_data("dout_data")
{
|
sc_top |
sc_clock clk;
sc_signal<bool> reset;
sc_signal<bool> cs;
sc_signal<bool> rw;
sc_signal<bool> ready;
#ifdef VERILATOR
sc_signal<uint32_t> addr;
sc_signal<uint32_t> data_in;
sc_signal<uint32_t> data_out;
#else
sc_signal<sc_uint<16>> addr;
sc_signal<sc_uint<32>> data_in;
sc_signal<sc_uint<32>> data_out;
#endif
Vtop *u_top;
bfm *u_bfm;
SC_CTOR(sc_top) :
clk("clk", 10, SC_NS, 0.5, 5, SC_NS, true),
reset("reset"), cs("cs"), rw("rw"), addr("addr"), ready("ready"), data_in("data_in"), data_out("data_out") {
#ifdef VERILATOR
u_top = new Vtop{"top" |
V_fir_pe |
sc_in<bool> clk;
sc_in<bool> Rdy;
sc_out<bool> Vld;
sc_in<sc_uint<6> > Cin;
sc_in<sc_uint<4> > Xin;
sc_out<sc_uint<4> > Xout;
sc_in<sc_uint<4> > Yin;
sc_out<sc_uint<4> > Yout;
Vfir_pe* u_Vfir_pe;
sc_signal<uint32_t> _Cin;
sc_signal<uint32_t> _Xin;
sc_signal<uint32_t> _Xout;
sc_signal<uint32_t> _Yin;
sc_signal<uint32_t> _Yout;
sc_signal<bool> _Rdy;
sc_signal<bool> _Vld;
void pe_method(void)
{
_Cin = (uint32_t)Cin.read();
_Xin = (uint32_t)Xin.read();
_Yin = (uint32_t)Yin.read();
_Rdy = Rdy.read();
Xout.write(sc_uint<4>(_Xout));
Yout.write(sc_uint<4>(_Yout));
Vld.write(_Vld);
}
SC_CTOR(V_fir_pe):
clk("clk"),
Rdy("Rdy"), _Rdy("_Rdy"),
Vld("Vld"), _Vld("_Vld"),
Cin("Cin"), _Cin("_Cin"),
Xin("Xin"), _Xin("_Xin"),
Xout("Xout"), _Xout("_Xout"),
Yin("Yin"), _Yin("_Yin"),
Yout("Yout"), _Yout("_Yout")
{
SC_METHOD(pe_method);
sensitive << clk << Cin << Xin << Yin << Rdy;
// Instantiate Verilated PE
u_Vfir_pe = new Vfir_pe("u_Vfir_pe");
u_Vfir_pe->clk(clk);
u_Vfir_pe->Cin(_Cin);
u_Vfir_pe->Xin(_Xin);
u_Vfir_pe->Xout(_Xout);
u_Vfir_pe->Yin(_Yin);
u_Vfir_pe->Yout(_Yout);
u_Vfir_pe->Rdy(_Rdy);
u_Vfir_pe->Vld(_Vld);
}
~V_fir_pe(void)
{
}
|
cnn |
// typedef
typedef hwcore::cnn::top_cnn<P_data_W, P_data_P, P_input_BW_N, P_output_BW_N, P_pe_n, P_pe_bw_n, P_wbuf_size,
P_data_buf_clb_size, P_data_buf_clb_n, P_data_buf_shift_size, P_data_out_n,
P_pool_size, P_PE_pipeline_II, P_pe_pre_fifo_deep>
top_cnn_t;
// interface
SC_MODULE_CLK_RESET_SIGNAL;
sc_fifo_in<hwcore::pipes::SC_DATA_T(P_input_width)> data_sink;
sc_fifo_in<hwcore::pipes::SC_DATA_T(P_input_width)> data_buf_sink;
sc_fifo_in<hwcore::pipes::SC_DATA_T(P_input_width)> w_sink;
sc_fifo_in<hwcore::pipes::SC_DATA_T(64)> ctrl_sink;
sc_fifo_out<hwcore::pipes::SC_DATA_T(P_output_width)> data_source;
#if __RTL_SIMULATION__
sc_status_module_create_interface_only(reg1);
ap_rtl::cnn rtl_wrapper_cnn;
SC_FIFO_IN_TRANS<P_input_width> data_sink_trans;
SC_FIFO_IN_TRANS<P_input_width> data_buf_sink_trans;
SC_FIFO_IN_TRANS<P_input_width> w_sink_trans;
SC_FIFO_IN_TRANS<64> ctrl_sink_trans;
SC_FIFO_OUT_TRANS<P_output_width> data_source_trans;
sc_signal<sc_logic> reset_s;
sc_signal<sc_lv<32> > status_add_s;
sc_signal<sc_lv<32> > status_val_s;
void signal_connection() {
sc_dt::sc_logic reset_tmp = (sc_dt::sc_logic)reset.read();
reset_s.write(reset_tmp);
status_add_s.write(status_add.read());
status_val.write(status_val_s.read().to_int());
}
SC_CTOR(cnn)
: rtl_wrapper_cnn("rtl_wrapper_cnn"), data_sink_trans("data_sink_trans"),
data_buf_sink_trans("data_buf_sink_trans"), data_source_trans("data_source_trans"),
w_sink_trans("w_sink_trans"), ctrl_sink_trans("ctrl_sink_trans") {
// SC_MODULE_LINK(rtl_wrapper_cnn);
SC_FIFO_IN_TRANS_CONNECT(rtl_wrapper_cnn, data_sink_trans, data_sink);
SC_FIFO_IN_TRANS_CONNECT(rtl_wrapper_cnn, data_buf_sink_trans, data_buf_sink);
SC_FIFO_IN_TRANS_CONNECT(rtl_wrapper_cnn, w_sink_trans, w_sink);
SC_FIFO_IN_TRANS_CONNECT(rtl_wrapper_cnn, ctrl_sink_trans, ctrl_sink);
SC_FIFO_OUT_TRANS_CONNECT(rtl_wrapper_cnn, data_source_trans, data_source);
rtl_wrapper_cnn.clk(clk);
rtl_wrapper_cnn.reset(reset_s);
rtl_wrapper_cnn.status_add(status_add_s);
rtl_wrapper_cnn.status_val(status_val_s);
SC_METHOD(signal_connection);
sensitive << status_add << status_val_s << reset;
}
#else
sc_status_module_create(reg1);
sc_status_reg_create(r0_dma_ingress);
sc_status_reg_create(r1_dma_egress);
sc_status_reg_create(r2_data_W);
sc_status_reg_create(r3_data_P);
sc_status_reg_create(r4_input_BW_N);
sc_status_reg_create(r5_output_BW_N);
sc_status_reg_create(r6_pe_n);
sc_status_reg_create(r7_pe_bw_n);
sc_status_reg_create(r8_wbuf_size);
sc_status_reg_create(r9_data_buf_clb_size);
sc_status_reg_create(r10_data_buf_clb_n);
sc_status_reg_create(r11_data_buf_shift_size);
sc_status_reg_create(r12_data_out_n);
sc_status_end_create(regend);
void status_reg_param_link() {
r2_data_W_status.write(P_data_W);
r3_data_P_status.write(P_data_P);
r4_input_BW_N_status.write(P_input_BW_N);
r5_output_BW_N_status.write(P_pool_size);
r6_pe_n_status.write(P_pe_n);
r7_pe_bw_n_status.write(P_pe_bw_n);
r8_wbuf_size_status.write(P_wbuf_size);
r9_data_buf_clb_size_status.write(P_data_buf_clb_size);
r10_data_buf_clb_n_status.write(P_data_buf_clb_n);
r11_data_buf_shift_size_status.write(P_data_buf_shift_size);
r12_data_out_n_status.write(P_data_out_n);
}
sc_fifo<hwcore::pipes::SC_DATA_T(P_input_width)> data_sink_forward;
sc_fifo<hwcore::pipes::SC_DATA_T(P_input_width)> data_buf_sink_forward;
sc_fifo<hwcore::pipes::SC_DATA_T(P_input_width)> w_sink_forward;
sc_fifo<hwcore::pipes::SC_DATA_T(P_output_width)> data_source_forward;
sc_fifo<sc_uint<31> > weight_ctrls_fifo;
sc_fifo<sc_uint<32> > ctrl_image_size_fifo;
sc_fifo<sc_uint<16> > ctrl_row_size_pkg_fifo;
sc_fifo<sc_uint<16> > ctrl_window_size_fifo;
sc_fifo<sc_uint<16> > ctrl_depth_fifo;
sc_fifo<sc_uint<16> > ctrl_stride_fifo;
sc_fifo<sc_uint<16> > ctrl_replay_fifo;
sc_fifo<sc_uint<16> > ctrl_zeropad_fifo;
sc_fifo<sc_uint<1> > ctrl_output_channel_fifo;
sc_fifo<sc_uint<16> > ctrl_stitch_depth_fifo;
sc_fifo<sc_uint<16> > ctrl_stitch_buf_depth_fifo;
sc_fifo<sc_uint<1> > ctrl_db_output_fifo;
sc_fifo<sc_uint<1> > ctrl_image_data_fifo;
sc_fifo<sc_uint<16> > ctrl_pool_depth_fifo;
sc_fifo<sc_uint<16> > ctrl_pool_type_fifo;
sc_fifo<sc_uint<16> > ctrl_pool_N_fifo;
sc_fifo<sc_uint<16> > ctrl_pool_size_fifo;
sc_fifo<sc_uint<16> > ctrl_row_N_fifo;
sc_fifo<sc_uint<16> > ctrl_acf_fifo;
// modules
hwcore::cnn::top_cnn<P_data_W, P_data_P, P_input_BW_N, P_output_BW_N, P_pe_n, P_pe_bw_n, P_wbuf_size,
P_data_buf_clb_size, P_data_buf_clb_n, P_data_buf_shift_size, P_data_out_n>
top_cnn;
sc_status_reg_create_dummy(top_cnn_reg);
SC_CTOR(cnn)
: data_sink_forward(P_X_fifo_deep), data_buf_sink_forward(P_BUF_fifo_deep), w_sink_forward(P_W_fifo_deep),
data_source_forward(P_Y_fifo_deep), weight_ctrls_fifo(16), ctrl_row_size_pkg_fifo(16),
ctrl_window_size_fifo(16), ctrl_depth_fifo(16), ctrl_stride_fifo(16), ctrl_replay_fifo(16),
ctrl_row_N_fifo(16), ctrl_acf_fifo(16), ctrl_zeropad_fifo(16), SC_INST(top_cnn), SC_INST(reg1),
SC_INST(regend), SC_INST(r0_dma_ingress), SC_INST(r1_dma_egress), SC_INST(r2_data_W), SC_INST(r3_data_P),
SC_INST(r4_input_BW_N), SC_INST(r5_output_BW_N), SC_INST(r6_pe_n), SC_INST(r7_pe_bw_n), SC_INST(r8_wbuf_size),
SC_INST(r9_data_buf_clb_size), SC_INST(r10_data_buf_clb_n), SC_INST(r11_data_buf_shift_size),
SC_INST(r12_data_out_n), ctrl_output_channel_fifo(16), ctrl_db_output_fifo(16), ctrl_pool_depth_fifo(16),
ctrl_pool_type_fifo(16), ctrl_pool_N_fifo(16), ctrl_pool_size_fifo(16), ctrl_stitch_depth_fifo(16),
ctrl_stitch_buf_depth_fifo(1), ctrl_image_data_fifo(16)
{
top_cnn.clk(clk);
top_cnn.reset(reset);
/*SC_METHOD(reset_logic);
sensitive << reset << iclear;
SC_CTHREAD(clear_reg, clk.pos());*/
top_cnn.data_sink(data_sink_forward);
top_cnn.data_buf_sink(data_buf_sink_forward);
top_cnn.w_sink(w_sink_forward);
top_cnn.data_source(data_source_forward);
top_cnn.weight_ctrls_in(weight_ctrls_fifo);
// top_cnn.data_ctrls_in(data_ctrls_fifo);
top_cnn.ctrl_row_N(ctrl_row_N_fifo);
top_cnn.ctrl_row_size_pkg(ctrl_row_size_pkg_fifo);
top_cnn.ctrl_window_size(ctrl_window_size_fifo);
top_cnn.ctrl_depth(ctrl_depth_fifo);
top_cnn.ctrl_stride(ctrl_stride_fifo);
top_cnn.ctrl_replay(ctrl_replay_fifo);
top_cnn.ctrl_image_size(ctrl_image_size_fifo);
top_cnn.ctrl_acf(ctrl_acf_fifo);
top_cnn.ctrl_zeropad(ctrl_zeropad_fifo);
top_cnn.ctrl_output_channel(ctrl_output_channel_fifo);
top_cnn.ctrl_stitch_depth(ctrl_stitch_depth_fifo);
top_cnn.ctrl_stitch_buf_depth(ctrl_stitch_buf_depth_fifo);
top_cnn.ctrl_db_output(ctrl_db_output_fifo);
top_cnn.ctrl_image_data(ctrl_image_data_fifo);
top_cnn.ctrl_pool_depth(ctrl_pool_depth_fifo);
top_cnn.ctrl_pool_type(ctrl_pool_type_fifo);
top_cnn.ctrl_pool_N(ctrl_pool_N_fifo);
top_cnn.ctrl_pool_size(ctrl_pool_size_fifo);
// status reg
sc_status_module_connect(reg1);
sc_status_reg_connect(r0_dma_ingress, reg1);
sc_status_reg_connect(r1_dma_egress, r0_dma_ingress);
sc_status_reg_connect(r2_data_W, r1_dma_egress);
sc_status_reg_connect(r3_data_P, r2_data_W);
sc_status_reg_connect(r4_input_BW_N, r3_data_P);
sc_status_reg_connect(r5_output_BW_N, r4_input_BW_N);
sc_status_reg_connect(r6_pe_n, r5_output_BW_N);
sc_status_reg_connect(r7_pe_bw_n, r6_pe_n);
sc_status_reg_connect(r8_wbuf_size, r7_pe_bw_n);
sc_status_reg_connect(r9_data_buf_clb_size, r8_wbuf_size);
sc_status_reg_connect(r10_data_buf_clb_n, r9_data_buf_clb_size);
sc_status_reg_connect(r11_data_buf_shift_size, r10_data_buf_clb_n);
sc_status_reg_connect(r12_data_out_n, r11_data_buf_shift_size);
sc_status_end_connect(regend, r12_data_out_n);
SC_CTHREAD(thread_cnn_stream_source, clk.pos());
reset_signal_is(reset, true);
SC_CTHREAD(thread_cnn_stream_sink, clk.pos());
reset_signal_is(reset, true);
SC_CTHREAD(thread_cnn_stream_buf_sink, clk.pos());
reset_signal_is(reset, true);
SC_CTHREAD(thread_cnn_stream_w_sink, clk.pos());
reset_signal_is(reset, true);
SC_CTHREAD(thread_cnn_ctrl, clk.pos());
reset_signal_is(reset, true);
}
void thread_cnn_stream_source() {
SC_STREAM_INTERFACE_CREATE_SOURCE(data_source, "-bus_bundle M_AXIS_Y")
int count = 0;
while (true) {
hls_pipeline(1);
hwcore::pipes::SC_DATA_T(P_output_width) tmp_out = data_source_forward.read();
data_source.write(tmp_out);
count++;
r0_dma_ingress_status.write(count);
}
}
void thread_cnn_stream_sink() {
SC_STREAM_INTERFACE_CREATE_SINK(data_sink, "-bus_bundle S_AXIS_X")
int count = 0;
while (true) {
hls_pipeline(1);
hwcore::pipes::SC_DATA_T(P_input_width) tmp_in = data_sink.read();
data_sink_forward.write(tmp_in);
count++;
r1_dma_egress_status.write(count);
}
}
void thread_cnn_stream_buf_sink() {
SC_STREAM_INTERFACE_CREATE_SINK(data_buf_sink, "-bus_bundle S_AXIS_BUF")
while (true) {
hls_pipeline(1);
hwcore::pipes::SC_DATA_T(P_input_width) tmp_in = data_buf_sink.read();
data_buf_sink_forward.write(tmp_in);
}
}
void thread_cnn_stream_w_sink() {
SC_STREAM_INTERFACE_CREATE_SINK(w_sink, "-bus_bundle S_AXIS_W")
while (true) {
hls_pipeline(1);
hwcore::pipes::SC_DATA_T(P_input_width) tmp_in = w_sink.read();
w_sink_forward.write(tmp_in);
}
}
void thread_cnn_ctrl() {
SC_STREAM_INTERFACE_CREATE_SINK(ctrl_sink, "-bus_bundle S_AXIS_CTRL")
hwcore::pipes::SC_DATA_T(64) tmp_in;
status_reg_param_link();
while (true) {
do {
hls_pipeline(1);
tmp_in = ctrl_sink.read();
sc_uint<64> raw = tmp_in.data;
sc_uint<56> value = raw(56 - 1, 0);
sc_uint<8> address;
if (tmp_in.tkeep == 0) {
address = -1;
} else {
address = raw(64 - 1, 56);
}
#define add_new_reg_interface(name_, nr_) \
case nr_: \
name_##_fifo.write(value); \
break;
switch (address) {
add_new_reg_interface(weight_ctrls, 0);
add_new_reg_interface(ctrl_row_N, 1);
add_new_reg_interface(ctrl_row_size_pkg, 2);
add_new_reg_interface(ctrl_window_size, 3);
add_new_reg_interface(ctrl_depth, 4);
add_new_reg_interface(ctrl_stride, 5);
add_new_reg_interface(ctrl_replay, 6);
add_new_reg_interface(ctrl_image_size, 7);
add_new_reg_interface(ctrl_acf, 8);
add_new_reg_interface(ctrl_zeropad, 9);
add_new_reg_interface(ctrl_output_channel, 10);
add_new_reg_interface(ctrl_stitch_depth, 11);
add_new_reg_interface(ctrl_stitch_buf_depth, 12);
add_new_reg_interface(ctrl_db_output, 13);
add_new_reg_interface(ctrl_image_data, 14);
add_new_reg_interface(ctrl_pool_depth, 15);
add_new_reg_interface(ctrl_pool_type, 16);
add_new_reg_interface(ctrl_pool_N, 17);
add_new_reg_interface(ctrl_pool_size, 18);
default:
break;
|
mux_pcnt |
sc_port<sc_signal_in_if<bool>,0> mout_i {"mout_i" |
IP_RIVER |
sc_in_clk CLK;
sc_in<bool> RESET_N;
//interface bus
sc_in<bool> ACK;
sc_in<sc_uint<32>> DAT_I;
sc_in<bool> GRANT;
sc_in<sc_uint<32>> ADR_I;
sc_out<sc_uint<32>> ADR;
sc_out<sc_uint<32>> DAT_O;
sc_out<sc_uint<2>> SEL;
sc_out<bool> STB;
sc_out<bool> WE;
sc_out<bool> CYC;
// DCache-Core
sc_signal<sc_uint<32>> DATA_ADR_SM;
sc_signal<sc_uint<32>> DATA_SM;
sc_signal<bool> VALID_ADR_SM;
sc_signal<bool> STORE_SM;
sc_signal<bool> LOAD_SM;
sc_signal<sc_uint<2>> MEM_SIZE_SM;
sc_signal<sc_uint<32>> DATA_SDC;
sc_signal<bool> STALL_SDC;
// ICache-Core
sc_signal<sc_uint<32>> ADR_SI;
sc_signal<bool> ADR_VALID_SI;
sc_signal<sc_bv<32>> INST_SIC;
sc_signal<bool> STALL_SIC;
//DCache-Wrapper
sc_signal<bool> READ_SDC;
sc_signal<bool> WRITE_SDC;
sc_signal<bool> DTA_VALID_SDC;
sc_signal<sc_uint<32>> DCACHE_DT;
sc_signal<sc_uint<32>> A_SDC;
sc_signal<sc_uint<2>> SIZE_SDC;
sc_signal<sc_uint<32>> WRAPPER_DT;
sc_signal<bool> DCACHE_ACK;
sc_signal<bool> STALL_SW;
//ICache-Wrapper
sc_signal<bool> ICACHE_ACK;
sc_signal<sc_uint<32>> ICACHE_DT;
sc_signal<sc_uint<32>> A_SIC;
sc_signal<bool> DTA_VALID_SIC;
//Debug CORE
sc_in<sc_uint<32>> PC_RESET;
sc_out<sc_uint<32>> PC_VALUE;
sc_in<sc_uint<32>> PROC_ID;
void trace(sc_trace_file*);
core core_inst;
icache icache_inst;
dcache dcache_inst;
wb_river_mc wrapper_inst;
SC_CTOR(IP_RIVER):
core_inst("core"),
icache_inst("icache"),
dcache_inst("dcache"),
wrapper_inst("wb_river_mc")
{
//CORE map
core_inst.CLK(CLK);
core_inst.RESET(RESET_N);
core_inst.DEBUG_PC_READ(PC_VALUE);
core_inst.PC_INIT(PC_RESET);
core_inst.PROC_ID(PROC_ID);
core_inst.MCACHE_ADR_SM(DATA_ADR_SM);
core_inst.MCACHE_DATA_SM(DATA_SM);
core_inst.MCACHE_ADR_VALID_SM(VALID_ADR_SM);
core_inst.MCACHE_STORE_SM(STORE_SM);
core_inst.MCACHE_LOAD_SM(LOAD_SM);
core_inst.MCACHE_RESULT_SM(DATA_SDC);
core_inst.MCACHE_STALL_SM(STALL_SDC);
core_inst.MEM_SIZE_SM(MEM_SIZE_SM);
core_inst.ADR_SI(ADR_SI);
core_inst.ADR_VALID_SI(ADR_VALID_SI);
core_inst.INST_SIC(INST_SIC);
core_inst.STALL_SIC(STALL_SIC);
//DCache map
dcache_inst.CLK(CLK);
dcache_inst.RESET_N(RESET_N);
dcache_inst.DATA_ADR_SM(DATA_ADR_SM);
dcache_inst.DATA_SM(DATA_SM);
dcache_inst.LOAD_SM(LOAD_SM);
dcache_inst.STORE_SM(STORE_SM);
dcache_inst.VALID_ADR_SM(VALID_ADR_SM);
dcache_inst.MEM_SIZE_SM(MEM_SIZE_SM);
dcache_inst.DATA_SDC(DATA_SDC);
dcache_inst.STALL_SDC(STALL_SDC);
dcache_inst.DTA_VALID_SDC(DTA_VALID_SDC);
dcache_inst.READ_SDC(READ_SDC);
dcache_inst.WRITE_SDC(WRITE_SDC);
dcache_inst.SIZE_SDC(SIZE_SDC);
dcache_inst.DT_SDC(DCACHE_DT);
dcache_inst.A_SDC(A_SDC);
dcache_inst.DT_SW(WRAPPER_DT);
dcache_inst.ACK_SW(DCACHE_ACK);
dcache_inst.ADR_SW(ADR_I);
dcache_inst.GRANT(GRANT); // signal for snoopy control
dcache_inst.STALL_SW(STALL_SW);
//ICache map
icache_inst.CLK(CLK);
icache_inst.RESET_N(RESET_N);
icache_inst.ADR_SI(ADR_SI);
icache_inst.ADR_VALID_SI(ADR_VALID_SI);
icache_inst.INST_SIC(INST_SIC);
icache_inst.STALL_SIC(STALL_SIC);
icache_inst.DT_SW(ICACHE_DT);
icache_inst.A_SIC(A_SIC);
icache_inst.DTA_VALID_SIC(DTA_VALID_SIC);
icache_inst.ACK_SW(ICACHE_ACK);
icache_inst.STALL_SW(STALL_SW);
//Wrapper map
wrapper_inst.CLK(CLK);
wrapper_inst.RESET_N(RESET_N);
wrapper_inst.DAT_I(DAT_I);
wrapper_inst.ACK_I(ACK);
wrapper_inst.DAT_O(DAT_O);
wrapper_inst.ADR_O(ADR);
wrapper_inst.SEL_O(SEL);
wrapper_inst.WE_O(WE);
wrapper_inst.STB_O(STB);
wrapper_inst.A_IC(A_SIC);
wrapper_inst.DTA_VALID_IC(DTA_VALID_SIC);
wrapper_inst.DT_IC(ICACHE_DT);
wrapper_inst.ACK_IC(ICACHE_ACK);
wrapper_inst.DTA_VALID_DC(DTA_VALID_SDC);
wrapper_inst.READ_DC(READ_SDC);
wrapper_inst.WRITE_DC(WRITE_SDC);
wrapper_inst.SIZE_SEL_DC(SIZE_SDC);
wrapper_inst.DT_DC(DCACHE_DT);
wrapper_inst.A_DC(A_SDC);
wrapper_inst.DT_RM(WRAPPER_DT);
wrapper_inst.ACK_DC(DCACHE_ACK);
wrapper_inst.GRANT_I(GRANT);
wrapper_inst.CYC_O(CYC);
wrapper_inst.STALL_SW(STALL_SW);
}
|
icache |
// interface global
sc_in_clk CLK;
sc_in<bool> RESET_N;
// interface RiVer
sc_in<sc_uint<32> > ADR_SI;
sc_in<bool> ADR_VALID_SI;
sc_out<sc_bv<32> > INST_SIC;
sc_out<bool> STALL_SIC;
//interface wrapper
sc_in<sc_uint<32>> DT_SW;
sc_out<sc_uint<32>> A_SIC;
sc_out<bool> DTA_VALID_SIC;
sc_in<bool> ACK_SW;
sc_in<bool> STALL_SW;
//signals
sc_signal<sc_bv<32>> data[256][4];
sc_signal<sc_uint<20>> tag[256];
sc_signal<bool> data_validate[256];
sc_signal<sc_uint<20>> address_tag;
sc_signal<sc_uint<8>> address_index;
sc_signal<sc_uint<4>> address_offset;
sc_signal<sc_uint<20>> current_address_tag;
sc_signal<sc_uint<8>> current_address_index;
sc_signal<bool> hit;
sc_signal<sc_uint<3>> fsm_state;
void trace(sc_trace_file*);
void parse_adr();
void miss_detection();
void transition();
SC_CTOR(icache)
{
SC_METHOD(parse_adr);
sensitive << ADR_SI;
SC_METHOD(miss_detection);
sensitive << address_tag
<< address_index
<< address_offset
<< STALL_SIC;
for(int i=0; i < 256 ;i++){
sensitive << data[i][0]
<< data[i][1]
<< data[i][2]
<< data[i][3]
<< data_validate[i];
}
SC_THREAD(transition);
sensitive << CLK.neg();
reset_signal_is(RESET_N, false);
}
|
tb |
sc_in<bool> clk;
sc_out<bool> rst;
sc_out< sc_int<16> > inp;
sc_out<bool> inp_vld;
sc_in<bool> inp_rdy;
sc_in< sc_int<16> > outp;
sc_in<bool> outp_vld;
sc_out<bool> outp_rdy;
void source();
void sink();
FILE *outfp;
sc_time start_time[64], end_time[64], clock_period;
SC_HAS_PROCESS( tb );
tb( sc_module_name nm );
|
x1_multiplier |
// input :
sc_in<sc_bv<320>> IN_RX0;
sc_in<bool> SELECT_HIGHER_BITS_RX0;
sc_in<bool> SIGNED_RES_RX0;
sc_in<bool> X02X1_EMPTY_SX0;
sc_in<bool> X12X2_POP_SX2;
// output :
sc_out<sc_bv<128>> RES_RX1;
sc_out<bool> SELECT_HIGHER_BITS_RX1;
sc_out<bool> SIGNED_RES_RX1;
sc_out<bool> X12X2_EMPTY_SX1;
sc_out<bool> X02X1_POP_SX1;
// General interace :
sc_in_clk CLK;
sc_in<bool> RESET;
//data from input
sc_signal<sc_bv<64>> M[5];
//Res from stage 6
sc_signal<sc_bv<64>> product_s6[4];
//Res from stage 7
sc_signal<sc_bv<64>> product_s7[2];
//Res from stage 8
sc_signal<sc_bv<64>> product_s8[2];
// fifo x12x2
sc_signal<sc_bv<x12x2_size>> x12x2_din_sx1;
sc_signal<sc_bv<x12x2_size>> x12x2_dout_sx1;
sc_signal<bool> x12x2_full_sx1;
sc_signal<bool> x12x2_push_sx1;
fifo<x12x2_size> fifo_inst;
void parse_data();
//stage 6 (2 CSA)
void CSA1();
void CSA2();
//stage 7 (1 CSA remind product_s6 M3)
void CSA3();
//stage 8 (1 CSA)
void CSA4();
void manage_fifo();
void fifo_concat();
void fifo_unconcat();
void trace(sc_trace_file* tf);
SC_CTOR(x1_multiplier) :
fifo_inst("x12x2")
{
fifo_inst.DIN_S(x12x2_din_sx1);
fifo_inst.DOUT_R(x12x2_dout_sx1);
fifo_inst.EMPTY_S(X12X2_EMPTY_SX1);
fifo_inst.FULL_S(x12x2_full_sx1);
fifo_inst.PUSH_S(x12x2_push_sx1);
fifo_inst.POP_S(X12X2_POP_SX2);
fifo_inst.CLK(CLK);
fifo_inst.RESET_N(RESET);
SC_METHOD(parse_data);
sensitive << IN_RX0;
SC_METHOD(CSA1);
sensitive << M[0] << M[1] << M[2];
SC_METHOD(CSA3);
sensitive << product_s6[0] << product_s6[1] << M[3];
SC_METHOD(CSA4);
sensitive << product_s7[0] << product_s7[1] << M[4];
SC_METHOD(manage_fifo);
sensitive << x12x2_full_sx1 << X02X1_EMPTY_SX0;
SC_METHOD(fifo_concat);
sensitive << SELECT_HIGHER_BITS_RX0 << product_s8[0] << product_s8[1] << SIGNED_RES_RX0;
SC_METHOD(fifo_unconcat);
sensitive << x12x2_dout_sx1;
}
|
ACCNAME |
sc_in<bool> clock;
sc_in<bool> reset;
sc_fifo_in<DATA> din1;
sc_fifo_out<DATA> dout1;
// GEMM 1 Inputs
ACC_DTYPE<32> A1[IN_BUF_LEN];
ACC_DTYPE<32> A2[IN_BUF_LEN];
ACC_DTYPE<32> B1[IN_BUF_LEN];
ACC_DTYPE<32> B2[IN_BUF_LEN];
ACC_DTYPE<32> C1[IN_BUF_LEN * 4];
ACC_DTYPE<32> C2[IN_BUF_LEN * 4];
int qm;
sc_int<8> shift;
#ifndef __SYNTHESIS__
sc_signal<int, SC_MANY_WRITERS> lenX;
sc_signal<int, SC_MANY_WRITERS> lenY;
sc_signal<bool, SC_MANY_WRITERS> computeX;
sc_signal<bool, SC_MANY_WRITERS> computeY;
sc_signal<bool, SC_MANY_WRITERS> readX;
sc_signal<bool, SC_MANY_WRITERS> readY;
sc_signal<bool, SC_MANY_WRITERS> writeX;
sc_signal<bool, SC_MANY_WRITERS> writeY;
#else
sc_signal<int> lenX;
sc_signal<int> lenY;
sc_signal<bool> computeX;
sc_signal<bool> computeY;
sc_signal<bool> readX;
sc_signal<bool> readY;
sc_signal<bool> writeX;
sc_signal<bool> writeY;
#endif
void Control();
void Data_Read();
void PE_Add();
void Data_Write();
int Quantised_Multiplier(int, int, sc_int<8>);
SC_HAS_PROCESS(ACCNAME);
ACCNAME(sc_module_name name_) : sc_module(name_) {
SC_CTHREAD(Control, clock);
reset_signal_is(reset, true);
SC_CTHREAD(Data_Read, clock);
reset_signal_is(reset, true);
SC_CTHREAD(PE_Add, clock);
reset_signal_is(reset, true);
SC_CTHREAD(Data_Write, clock);
reset_signal_is(reset, true);
#pragma HLS RESOURCE variable = din1 core = AXI4Stream metadata = \
"-bus_bundle S_AXIS_DATA1" port_map = { \
{din1_0 TDATA } { \
din1_1 TLAST } }
#pragma HLS RESOURCE variable = dout1 core = AXI4Stream metadata = \
"-bus_bundle M_AXIS_DATA1" port_map = { \
{dout1_0 TDATA } { \
dout1_1 TLAST } }
}
|
E_fir_pe |
sc_in<bool> clk;
sc_in<bool> Rdy;
sc_out<bool> Vld;
sc_in<sc_uint<8> > Cin;
sc_in<sc_uint<4> > Xin;
sc_out<sc_uint<4> > Xout;
sc_in<sc_uint<4> > Yin;
sc_out<sc_uint<4> > Yout;
#define N_TX 3
#define N_RX 2
void pe_thread(void)
{
uint8_t x, y, txPacket[N_TX], rxPacket[N_RX];
while(true)
{
// Positive edge Clock
wait(clk.posedge_event());
txPacket[0] = (uint8_t)Cin.read(); // Cin
txPacket[1] = (uint8_t)(Yin.read())<<4 | (uint8_t)(Xin.read()); // Yin | Xin
txPacket[2] = (uint8_t)Rdy.read();
// Send to Emulator
for (int i=0; i<N_TX; i++)
{
x = txPacket[i];
while(write(fd, &x, 1)<=0) usleep(1);
}
// Receive from Emulator
for (int i=0; i<N_RX; i++)
{
while(read(fd, &y, 1)<=0) usleep(1);
rxPacket[i] = y;
}
Yout.write((sc_uint<4>)(rxPacket[0]>>4));
Xout.write((sc_uint<4>)(rxPacket[0] & 0x0F));
Vld.write(rxPacket[1]? true:false);
}
}
// Arduino Serial IF
int fd; // Serial port file descriptor
struct termios options; // Serial port setting
SC_CTOR(E_fir_pe):
clk("clk"),
Cin("Cin"), Xin("Xin"), Xout("Xout"),
Yin("Yin"), Yout("Yout")
{
SC_THREAD(pe_thread);
sensitive << clk;
// Arduino DUT
//fd = open("/dev/ttyACM0", O_RDWR | O_NDELAY | O_NOCTTY);
fd = open("/dev/ttyACM0", O_RDWR | O_NOCTTY);
if (fd < 0)
{
perror("Error opening serial port");
return;
}
// Set up serial port
options.c_cflag = B115200 | CS8 | CLOCAL | CREAD;
options.c_iflag = IGNPAR;
options.c_oflag = 0;
options.c_lflag = 0;
// Apply the settings
tcflush(fd, TCIFLUSH);
tcsetattr(fd, TCSANOW, &options);
// Establish Contact
int len = 0;
char rx;
while(!len)
len = read(fd, &rx, 1);
if (rx=='A')
write(fd, &rx, 1);
printf("Connection established...\n");
}
~E_fir_pe(void)
{
}
|
sc_dffrs_TB |
sc_clock clk;
sc_signal<bool> r, s, d, q;
Vdffrs* u_Vdffrs;
sc_trace_file* fp; // VCD file
SC_CTOR(sc_dffrs_TB): // constructor
clk("clk", 100, SC_NS, 0.5, 0.0, SC_NS, false)
{
// instantiate DUT
u_Vdffrs = new Vdffrs("u_Vdffrs");
// Binding
u_Vdffrs->clk(clk);
u_Vdffrs->r(r);
u_Vdffrs->s(s);
u_Vdffrs->d(d);
u_Vdffrs->q(q);
SC_THREAD(test_generator);
sensitive << clk;
// VCD Trace
fp = sc_create_vcd_trace_file("sc_dffrs_TB");
sc_trace(fp, clk, "clk");
sc_trace(fp, r, "r");
sc_trace(fp, s, "s");
sc_trace(fp, d, "d");
sc_trace(fp, q, "q");
}
void test_generator()
{
int test_count =0;
r.write(1);
s.write(1);
d.write(0);
while(true)
{
wait(clk.posedge_event());
wait(clk.negedge_event());
s.write(0);
wait(clk.posedge_event());
s.write(1);
wait(clk.negedge_event());
r.write(0);
wait(clk.posedge_event());
r.write(1);
wait(clk.posedge_event());
d = 1;
wait(clk.posedge_event());
d = false;
wait(clk.negedge_event());
d = 1;
wait(clk.posedge_event());
d = 0;
wait(clk.posedge_event());
d = 1;
wait(clk.posedge_event());
wait(clk.posedge_event());
r.write(1);
s.write(1);
d.write(1);
wait(clk.posedge_event());
r.write(0);
s.write(0);
//d.write(0);
wait(clk.posedge_event());
r.write(1);
s.write(1);
d.write(0);
wait(clk.posedge_event());
s.write(0);
wait(clk.posedge_event());
s.write(1);
wait(clk.posedge_event());
// Ending stimulus
wait(clk.posedge_event());
wait(clk.posedge_event());
sc_close_vcd_trace_file(fp);
sc_stop();
}
}
|
fila |
sc_in<bool > clock;
sc_in<bool > reset_n;
sc_in<regflit > data_in;
sc_in<bool > rx;
sc_out<bool > credit_o;
//sc_out<bool > ack_rx;
sc_out<bool > h;
sc_in<bool > ack_h;
sc_out<bool > data_av;
sc_out<regflit > data;
sc_in<bool > data_ack;
sc_out<bool > sender;
enum fila_out{S_INIT, S_PAYLOAD, S_SENDHEADER, S_HEADER, S_END, S_END2 |
s8 |
sc_in<sc_uint<6> > stage1_input;
sc_out<sc_uint<4> > stage1_output;
void s8_box();
SC_CTOR(s8)
{
SC_METHOD(s8_box);
sensitive << stage1_input;
}
|
fpu_driver |
#if MIXED_SIM
sc_out<sc_logic> rst;
sc_out<sc_logic> mult_en; // Signals that a multiply computation step should be performed
sc_out<sc_logic> add_en; // Signals that an add computation step should be performed
sc_out<sc_lv<16> > srf_in; // Scalar operand from SRF
sc_out<sc_lv<16> > grfa_in1[SIMD_WIDTH]; // Input 1 from GRF_A
sc_out<sc_lv<16> > grfa_in2[SIMD_WIDTH]; // Input 2 from GRF_A
sc_out<sc_lv<16> > grfb_in1[SIMD_WIDTH]; // Input 1 from GRF_B
sc_out<sc_lv<16> > grfb_in2[SIMD_WIDTH]; // Input 2 from GRF_B
// sc_out<sc_lv<16> > even_out[SIMD_WIDTH]; // Input from EVEN_BANK
// sc_out<sc_lv<16> > odd_out[SIMD_WIDTH]; // Input from ODD_BANK
sc_out<sc_lv<8> > mult_in1_sel; // Selects input 1 for addition
sc_out<sc_lv<8> > mult_in2_sel; // Selects input 2 for multiplication
sc_out<sc_lv<8> > add_in1_sel; // Selects input 1 for addition
sc_out<sc_lv<8> > add_in2_sel; // Selects input 2 for multiplication
sc_out<sc_logic> out_sel; // Selects the output: 0 for adder output, 1 for multiplier output
#else
sc_out<bool> rst;
sc_out<bool> mult_en; // Signals that a multiply computation step should be performed
sc_out<bool> add_en; // Signals that an add computation step should be performed
sc_out<half> srf_in; // Scalar operand from SRF
sc_out<half> grfa_in1[SIMD_WIDTH]; // Input 1 from GRF_A
sc_out<half> grfa_in2[SIMD_WIDTH]; // Input 2 from GRF_A
sc_out<half> grfb_in1[SIMD_WIDTH]; // Input 1 from GRF_B
sc_out<half> grfb_in2[SIMD_WIDTH]; // Input 2 from GRF_B
// sc_out<half> even_out[SIMD_WIDTH]; // Input from EVEN_BANK
// sc_out<half> odd_out[SIMD_WIDTH]; // Input from ODD_BANK
sc_out<uint8_t> mult_in1_sel; // Selects input 1 for addition
sc_out<uint8_t> mult_in2_sel; // Selects input 2 for multiplication
sc_out<uint8_t> add_in1_sel; // Selects input 1 for addition
sc_out<uint8_t> add_in2_sel; // Selects input 2 for multiplication
sc_out<bool> out_sel; // Selects the output: 0 for adder output, 1 for multiplier output
#endif
SC_CTOR(fpu_driver) {
SC_THREAD(driver_thread);
}
void driver_thread();
|
dut |
sc_in< bool > clk;
sc_in< bool > rst;
cynw_p2p< input_t >::in din; // TB to DUT, using struct input_t.
cynw_p2p< output_t >::out dout; // DUT to TB, using type output_t.
SC_CTOR( dut )
: clk( "clk" )
, rst( "rst" )
, din( "din" )
, dout( "dout" )
{
SC_CTHREAD( thread1, clk.pos() );
reset_signal_is( rst, false );
din.clk_rst( clk, rst );
dout.clk_rst( clk, rst );
}
void thread1();
|
scClk |
sc_out<bool> clk{"clk_o" |
E_fir_pe |
sc_in<bool> clk;
sc_in<sc_uint<8> > Cin;
sc_in<sc_uint<8> > Xin;
sc_out<sc_uint<8> > Xout;
sc_in<sc_uint<16> > Yin;
sc_out<sc_uint<16> > Yout;
#define N_TX 4
#define N_RX 3
void pe_thread(void)
{
uint8_t x, y, txPacket[N_TX], rxPacket[N_RX];
while(true)
{
wait(clk.posedge_event());
txPacket[3] = (uint8_t)(Yin.read()); // LSB of Yin
txPacket[2] = (uint8_t)(Yin.read()>>8); // MSB of Yin
txPacket[1] = (uint8_t)Xin.read(); // Xin
txPacket[0] = (uint8_t)Cin.read(); // Cin
// Send to Emulator
for (int i=0; i<N_TX; i++)
{
x = txPacket[i];
while(write(fd, &x, 1)<=0) usleep(1);
}
// Receive from Emulator
for (int i=0; i<N_RX; i++)
{
while(read(fd, &y, 1)<=0) usleep(1);
rxPacket[i] = y;
}
Xout.write( (uint8_t)rxPacket[0]);
Yout.write((uint16_t)rxPacket[1]<<8 | (uint16_t)rxPacket[2]);
}
}
// Arduino Serial IF
int fd; // Serial port file descriptor
struct termios options; // Serial port setting
SC_CTOR(E_fir_pe):
clk("clk"),
Cin("Cin"), Xin("Xin"), Xout("Xout"),
Yin("Yin"), Yout("Yout")
{
SC_THREAD(pe_thread);
sensitive << clk;
// Arduino DUT
//fd = open("/dev/ttyACM0", O_RDWR | O_NDELAY | O_NOCTTY);
fd = open("/dev/ttyACM0", O_RDWR | O_NOCTTY);
if (fd < 0)
{
perror("Error opening serial port");
return;
}
// Set up serial port
options.c_cflag = B115200 | CS8 | CLOCAL | CREAD;
options.c_iflag = IGNPAR;
options.c_oflag = 0;
options.c_lflag = 0;
// Apply the settings
tcflush(fd, TCIFLUSH);
tcsetattr(fd, TCSANOW, &options);
// Establish Contact
int len = 0;
char rx;
while(!len)
len = read(fd, &rx, 1);
if (rx=='A')
write(fd, &rx, 1);
printf("Connection established...\n");
}
~E_fir_pe(void)
{
}
|
ACCNAME |
//debug vars
bool print_po = false;
bool print_wo = false;
int simplecounter=0;
// int rows=0;
ACC_DTYPE<14> depth;
sc_in<bool> clock;
sc_in <bool> reset;
sc_fifo_in<DATA> din1;
sc_fifo_in<DATA> din2;
sc_fifo_in<DATA> din3;
sc_fifo_in<DATA> din4;
sc_fifo_out<DATA> dout1;
sc_fifo_out<DATA> dout2;
sc_fifo_out<DATA> dout3;
sc_fifo_out<DATA> dout4;
sc_signal<bool> read_inputs;
sc_signal<bool> rtake;
sc_signal<bool> ltake;
sc_signal<int> llen;
sc_signal<int> rlen;
sc_signal<int> lhs_block_max;
sc_signal<int> rhs_block_max;
#ifndef __SYNTHESIS__
sc_signal<bool,SC_MANY_WRITERS> d_in1;
sc_signal<bool,SC_MANY_WRITERS> d_in2;
sc_signal<bool,SC_MANY_WRITERS> d_in3;
sc_signal<bool,SC_MANY_WRITERS> d_in4;
sc_signal<bool,SC_MANY_WRITERS> schedule;
sc_signal<bool,SC_MANY_WRITERS> out_check;
sc_signal<bool,SC_MANY_WRITERS> gemm_unit_1_ready;
sc_signal<bool,SC_MANY_WRITERS> gemm_unit_2_ready;
sc_signal<bool,SC_MANY_WRITERS> gemm_unit_3_ready;
sc_signal<bool,SC_MANY_WRITERS> gemm_unit_4_ready;
sc_signal<bool,SC_MANY_WRITERS> write1;
sc_signal<bool,SC_MANY_WRITERS> write2;
sc_signal<bool,SC_MANY_WRITERS> write3;
sc_signal<bool,SC_MANY_WRITERS> write4;
sc_signal<bool,SC_MANY_WRITERS> arrange1;
sc_signal<bool,SC_MANY_WRITERS> arrange2;
sc_signal<bool,SC_MANY_WRITERS> arrange3;
sc_signal<bool,SC_MANY_WRITERS> arrange4;
sc_signal<bool,SC_MANY_WRITERS> write1_1;
sc_signal<bool,SC_MANY_WRITERS> write1_2;
sc_signal<bool,SC_MANY_WRITERS> write1_3;
sc_signal<bool,SC_MANY_WRITERS> write1_4;
sc_signal<bool,SC_MANY_WRITERS> write2_1;
sc_signal<bool,SC_MANY_WRITERS> write2_2;
sc_signal<bool,SC_MANY_WRITERS> write2_3;
sc_signal<bool,SC_MANY_WRITERS> write2_4;
sc_signal<bool,SC_MANY_WRITERS> write3_1;
sc_signal<bool,SC_MANY_WRITERS> write3_2;
sc_signal<bool,SC_MANY_WRITERS> write3_3;
sc_signal<bool,SC_MANY_WRITERS> write3_4;
sc_signal<bool,SC_MANY_WRITERS> write4_1;
sc_signal<bool,SC_MANY_WRITERS> write4_2;
sc_signal<bool,SC_MANY_WRITERS> write4_3;
sc_signal<bool,SC_MANY_WRITERS> write4_4;
#else
sc_signal<bool> d_in1;
sc_signal<bool> d_in2;
sc_signal<bool> d_in3;
sc_signal<bool> d_in4;
sc_signal<bool> schedule;
sc_signal<bool> out_check;
sc_signal<bool> gemm_unit_1_ready;
sc_signal<bool> gemm_unit_2_ready;
sc_signal<bool> gemm_unit_3_ready;
sc_signal<bool> gemm_unit_4_ready;
sc_signal<bool> write1;
sc_signal<bool> write2;
sc_signal<bool> write3;
sc_signal<bool> write4;
sc_signal<bool> arrange1;
sc_signal<bool> arrange2;
sc_signal<bool> arrange3;
sc_signal<bool> arrange4;
sc_signal<bool> write1_1;
sc_signal<bool> write1_2;
sc_signal<bool> write1_3;
sc_signal<bool> write1_4;
sc_signal<bool> write2_1;
sc_signal<bool> write2_2;
sc_signal<bool> write2_3;
sc_signal<bool> write2_4;
sc_signal<bool> write3_1;
sc_signal<bool> write3_2;
sc_signal<bool> write3_3;
sc_signal<bool> write3_4;
sc_signal<bool> write4_1;
sc_signal<bool> write4_2;
sc_signal<bool> write4_3;
sc_signal<bool> write4_4;
#endif
sc_signal<int> gemm_unit_1_l_pointer;
sc_signal<int> gemm_unit_2_l_pointer;
sc_signal<int> gemm_unit_3_l_pointer;
sc_signal<int> gemm_unit_4_l_pointer;
sc_signal<bool> gemm_unit_1_iwuse;
sc_signal<bool> gemm_unit_2_iwuse;
sc_signal<bool> gemm_unit_3_iwuse;
sc_signal<bool> gemm_unit_4_iwuse;
ADATA g1;
ADATA g2;
ADATA g3;
ADATA g4;
ADATA r1;
ADATA r2;
ADATA r3;
ADATA r4;
//GEMM 1 Inputs
ACC_DTYPE<32> lhsdata1a[2048];
ACC_DTYPE<32> lhsdata2a[2048];
ACC_DTYPE<32> lhsdata3a[2048];
ACC_DTYPE<32> lhsdata4a[2048];
//GEMM 2 Inputs
ACC_DTYPE<32> lhsdata1b[2048];
ACC_DTYPE<32> lhsdata2b[2048];
ACC_DTYPE<32> lhsdata3b[2048];
ACC_DTYPE<32> lhsdata4b[2048];
//GEMM 3 Inputs
ACC_DTYPE<32> lhsdata1c[2048];
ACC_DTYPE<32> lhsdata2c[2048];
ACC_DTYPE<32> lhsdata3c[2048];
ACC_DTYPE<32> lhsdata4c[2048];
//GEMM 4 Inputs
ACC_DTYPE<32> lhsdata1d[2048];
ACC_DTYPE<32> lhsdata2d[2048];
ACC_DTYPE<32> lhsdata3d[2048];
ACC_DTYPE<32> lhsdata4d[2048];
// //GEMM 1 Inputs
// ACC_DTYPE<32> lhsdata1a[4096];
// ACC_DTYPE<32> lhsdata2a[4096];
// ACC_DTYPE<32> lhsdata3a[4096];
// ACC_DTYPE<32> lhsdata4a[4096];
//
// //GEMM 2 Inputs
// ACC_DTYPE<32> lhsdata1b[4096];
// ACC_DTYPE<32> lhsdata2b[4096];
// ACC_DTYPE<32> lhsdata3b[4096];
// ACC_DTYPE<32> lhsdata4b[4096];
//
// //GEMM 3 Inputs
// ACC_DTYPE<32> lhsdata1c[4096];
// ACC_DTYPE<32> lhsdata2c[4096];
// ACC_DTYPE<32> lhsdata3c[4096];
// ACC_DTYPE<32> lhsdata4c[4096];
//
// //GEMM 4 Inputs
// ACC_DTYPE<32> lhsdata1d[4096];
// ACC_DTYPE<32> lhsdata2d[4096];
// ACC_DTYPE<32> lhsdata3d[4096];
// ACC_DTYPE<32> lhsdata4d[4096];
//Global Weights
ACC_DTYPE<32> rhsdata1[8192];
ACC_DTYPE<32> rhsdata2[8192];
ACC_DTYPE<32> rhsdata3[8192];
ACC_DTYPE<32> rhsdata4[8192];
//First Set (A)
ACC_DTYPE<32> rhs1a_1[2048];
ACC_DTYPE<32> rhs1b_1[2048];
ACC_DTYPE<32> rhs1c_1[2048];
ACC_DTYPE<32> rhs1d_1[2048];
ACC_DTYPE<32> rhs2a_1[2048];
ACC_DTYPE<32> rhs2b_1[2048];
ACC_DTYPE<32> rhs2c_1[2048];
ACC_DTYPE<32> rhs2d_1[2048];
ACC_DTYPE<32> rhs3a_1[2048];
ACC_DTYPE<32> rhs3b_1[2048];
ACC_DTYPE<32> rhs3c_1[2048];
ACC_DTYPE<32> rhs3d_1[2048];
ACC_DTYPE<32> rhs4a_1[2048];
ACC_DTYPE<32> rhs4b_1[2048];
ACC_DTYPE<32> rhs4c_1[2048];
ACC_DTYPE<32> rhs4d_1[2048];
// //First Set (A)
// ACC_DTYPE<32> rhs1a_1[1024];
// ACC_DTYPE<32> rhs1b_1[1024];
// ACC_DTYPE<32> rhs1c_1[1024];
// ACC_DTYPE<32> rhs1d_1[1024];
//
// ACC_DTYPE<32> rhs2a_1[1024];
// ACC_DTYPE<32> rhs2b_1[1024];
// ACC_DTYPE<32> rhs2c_1[1024];
// ACC_DTYPE<32> rhs2d_1[1024];
//
// ACC_DTYPE<32> rhs3a_1[1024];
// ACC_DTYPE<32> rhs3b_1[1024];
// ACC_DTYPE<32> rhs3c_1[1024];
// ACC_DTYPE<32> rhs3d_1[1024];
//
// ACC_DTYPE<32> rhs4a_1[1024];
// ACC_DTYPE<32> rhs4b_1[1024];
// ACC_DTYPE<32> rhs4c_1[1024];
// ACC_DTYPE<32> rhs4d_1[1024];
//new sums bram
ACC_DTYPE<32> lhs_sum1[512];
ACC_DTYPE<32> lhs_sum2[512];
ACC_DTYPE<32> lhs_sum3[512];
ACC_DTYPE<32> lhs_sum4[512];
ACC_DTYPE<32> rhs_sum1[512];
ACC_DTYPE<32> rhs_sum2[512];
ACC_DTYPE<32> rhs_sum3[512];
ACC_DTYPE<32> rhs_sum4[512];
//crf & crx
ACC_DTYPE<32> crf1[512];
ACC_DTYPE<32> crf2[512];
ACC_DTYPE<32> crf3[512];
ACC_DTYPE<32> crf4[512];
ACC_DTYPE<32> crx[512];
int ra=0;
sc_fifo<int> WRQ1;
sc_fifo<int> WRQ2;
sc_fifo<int> WRQ3;
sc_fifo<int> WRQ4;
sc_signal<int> w1S;
sc_signal<int> w2S;
sc_signal<int> w3S;
sc_signal<int> w4S;
#ifndef __SYNTHESIS__
int weight_max_index=0;
int input_max_index=0;
int local_weight_max_index=0;
int g1_macs=0;
int g2_macs=0;
int g3_macs=0;
int g4_macs=0;
int g1_out_count=0;
int g2_out_count=0;
int g3_out_count=0;
int g4_out_count=0;
#endif
sc_out<int> inS;
sc_out<int> read_cycle_count;
sc_out<int> process_cycle_count;
sc_out<int> gemm_1_idle;
sc_out<int> gemm_2_idle;
sc_out<int> gemm_3_idle;
sc_out<int> gemm_4_idle;
sc_out<int> gemm_1_write;
sc_out<int> gemm_2_write;
sc_out<int> gemm_3_write;
sc_out<int> gemm_4_write;
sc_out<int> gemm_1;
sc_out<int> gemm_2;
sc_out<int> gemm_3;
sc_out<int> gemm_4;
sc_out<int> wstall_1;
sc_out<int> wstall_2;
sc_out<int> wstall_3;
sc_out<int> wstall_4;
sc_out<int> rmax;
sc_out<int> lmax;
sc_out<int> outS;
sc_out<int> w1SS;
sc_out<int> w2SS;
sc_out<int> w3SS;
sc_out<int> w4SS;
sc_out<int> schS;
sc_out<int> p1S;
void Input_Handler();
void Output_Handler();
void Worker1();
void Worker2();
void Worker3();
void Worker4();
void Data_In1();
void Data_In2();
void Data_In3();
void Data_In4();
void Tracker();
void Scheduler();
void Post1();
void Post2();
void Post3();
void Post4();
void Arranger1();
void Arranger2();
void Arranger3();
void Arranger4();
void WSync1();
void WSync2();
void WSync3();
void WSync4();
void load_weights(int,int);
void schedule_gemm_unit(int, int, int, int);
int SHR(int,int);
void overwrite_weights_check();
void Read_Cycle_Counter();
void Process_Cycle_Counter();
void Writer_Cycle_Counter();
SC_HAS_PROCESS(ACCNAME);
// Parameters for the DUT
ACCNAME(sc_module_name name_) :sc_module(name_),WRQ1(512), WRQ2(512), WRQ3(512), WRQ4(512){
SC_CTHREAD(Input_Handler,clock.pos());
reset_signal_is(reset,true);
SC_CTHREAD(Worker1,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Worker2,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Worker3,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Worker4,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Output_Handler,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Data_In1,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Data_In2,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Data_In3,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Data_In4,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Scheduler,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Post1,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Post2,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Post3,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Post4,clock);
reset_signal_is(reset,true);
SC_CTHREAD(WSync1,clock);
reset_signal_is(reset,true);
SC_CTHREAD(WSync2,clock);
reset_signal_is(reset,true);
SC_CTHREAD(WSync3,clock);
reset_signal_is(reset,true);
SC_CTHREAD(WSync4,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Arranger1,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Arranger2,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Arranger3,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Arranger4,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Read_Cycle_Counter,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Process_Cycle_Counter,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Writer_Cycle_Counter,clock);
reset_signal_is(reset,true);
#pragma HLS RESOURCE variable=din1 core=AXI4Stream metadata="-bus_bundle S_AXIS_DATA1" port_map={{din1_0 TDATA} {din1_1 TLAST}}
#pragma HLS RESOURCE variable=din2 core=AXI4Stream metadata="-bus_bundle S_AXIS_DATA2" port_map={{din2_0 TDATA} {din2_1 TLAST}}
#pragma HLS RESOURCE variable=din3 core=AXI4Stream metadata="-bus_bundle S_AXIS_DATA3" port_map={{din3_0 TDATA} {din3_1 TLAST}}
#pragma HLS RESOURCE variable=din4 core=AXI4Stream metadata="-bus_bundle S_AXIS_DATA4" port_map={{din4_0 TDATA} {din4_1 TLAST}}
#pragma HLS RESOURCE variable=dout1 core=AXI4Stream metadata="-bus_bundle M_AXIS_DATA1" port_map={{dout1_0 TDATA} {dout1_1 TLAST}}
#pragma HLS RESOURCE variable=dout2 core=AXI4Stream metadata="-bus_bundle M_AXIS_DATA2" port_map={{dout2_0 TDATA} {dout2_1 TLAST}}
#pragma HLS RESOURCE variable=dout3 core=AXI4Stream metadata="-bus_bundle M_AXIS_DATA3" port_map={{dout3_0 TDATA} {dout3_1 TLAST}}
#pragma HLS RESOURCE variable=dout4 core=AXI4Stream metadata="-bus_bundle M_AXIS_DATA4" port_map={{dout4_0 TDATA} {dout4_1 TLAST}}
#pragma HLS RESET variable=reset
}
|
subbytes |
sc_in<bool> clk;
sc_in<bool> reset;
sc_in<bool> start_i;
sc_in<bool> decrypt_i;
sc_in<sc_biguint <128> > data_i;
sc_out<bool> ready_o;
sc_out<sc_biguint<128> > data_o;
//To sbox
sc_out<sc_uint<8> > sbox_data_o;
sc_in<sc_uint<8> > sbox_data_i;
sc_out<bool>sbox_decrypt_o;
void sub();
void registers();
sc_signal<sc_uint<5> > state, next_state;
sc_signal<sc_biguint<128> > data_reg, next_data_reg;
sc_signal<bool> next_ready_o;
SC_CTOR(subbytes)
{
SC_METHOD(registers);
sensitive << clk.pos();
sensitive << reset.neg();
SC_METHOD(sub);
sensitive << decrypt_i << start_i << state << data_i << sbox_data_i << data_reg;
}
|
full_adder |
public: sc_in<bool> a, b, cin;
public: sc_out<bool> sum, cout;
//---------------------------------------
public: SC_CTOR(full_adder)
{
SC_METHOD(process);
sensitive << a << b << cin;
}
//---------------------------------------
private: void process()
{
bool aANDb, aXORb, cinANDaXORb;
aANDb = a.read() & b.read();
aXORb = a.read() ^ b.read();
cinANDaXORb = cin.read() & aXORb;
//Calculate sum and carry out of the 1-BIT adder
sum = aXORb ^ cin.read();
cout = aANDb | cinANDaXORb;
//next_trigger(1, SC_NS);
}
//---------------------------------------
|
sc_fir8_tb |
sc_clock clk;
sc_signal<sc_uint<4> > Xin;
sc_signal<sc_uint<4> > Xout;
sc_signal<sc_uint<4> > Yin;
sc_signal<sc_uint<4> > Yout;
sc_signal<bool> Vld;
sc_signal<bool> Rdy;
#ifdef EMULATED
sc_signal<sc_uint<4> > E_Xout;
sc_signal<sc_uint<4> > E_Yout;
sc_signal<bool> E_Vld;
#endif
sc_fir8* u_sc_fir8;
// Test utilities
void Test_Gen();
void Test_Mon();
sc_uint<8> x[F_SAMPLE]; // Time seq. input
sc_uint<16> y[F_SAMPLE]; // Filter output
#ifdef VCD_TRACE_FIR8_TB
sc_trace_file* fp; // VCD file
#endif
SC_CTOR(sc_fir8_tb):
clk("clk", 100, SC_NS, 0.5, 0.0, SC_NS, false),
Vld("Vld"),
Rdy("Rdy"),
Xin("Xin"),
Xout("Xout"),
Yin("Yin"),
Yout("Yout")
{
SC_THREAD(Test_Gen);
sensitive << clk;
SC_THREAD(Test_Mon);
sensitive << clk;
// Instaltiate FIR8
u_sc_fir8 = new sc_fir8("u_sc_fir8");
u_sc_fir8->clk(clk);
u_sc_fir8->Xin(Xin);
u_sc_fir8->Xout(Xout);
u_sc_fir8->Yin(Yin);
u_sc_fir8->Yout(Yout);
u_sc_fir8->Rdy(Rdy);
u_sc_fir8->Vld(Vld);
#ifdef EMULATED
u_sc_fir8->E_Xout(E_Xout);
u_sc_fir8->E_Yout(E_Yout);
u_sc_fir8->E_Vld(E_Vld);
#endif
#ifdef VCD_TRACE_FIR8_TB
// WAVE
fp = sc_create_vcd_trace_file("sc_fir8_tb");
fp->set_time_unit(100, SC_PS); // resolution (trace) ps
sc_trace(fp, clk, "clk");
sc_trace(fp, Xin, "Xin");
sc_trace(fp, Xout, "Xout");
sc_trace(fp, Yin, "Yin");
sc_trace(fp, Yout, "Yout");
sc_trace(fp, Rdy, "Rdy");
sc_trace(fp, Vld, "Vld");
#endif
}
~sc_fir8_tb(void)
{
}
|
ACCNAME |
sc_in<bool> clock;
sc_in<bool> reset;
sc_fifo_in<DATA> din1;
sc_fifo_out<DATA> dout1;
// GEMM 1 Inputs
ACC_DTYPE<32> A1[IN_BUF_LEN];
ACC_DTYPE<32> A2[IN_BUF_LEN];
ACC_DTYPE<32> B1[IN_BUF_LEN];
ACC_DTYPE<32> B2[IN_BUF_LEN];
ACC_DTYPE<32> C1[IN_BUF_LEN * 4];
ACC_DTYPE<32> C2[IN_BUF_LEN * 4];
int qm;
sc_int<8> shift;
#ifndef __SYNTHESIS__
sc_signal<int, SC_MANY_WRITERS> lenX;
sc_signal<int, SC_MANY_WRITERS> lenY;
sc_signal<bool, SC_MANY_WRITERS> computeX;
sc_signal<bool, SC_MANY_WRITERS> computeY;
sc_signal<bool, SC_MANY_WRITERS> readX;
sc_signal<bool, SC_MANY_WRITERS> readY;
sc_signal<bool, SC_MANY_WRITERS> writeX;
sc_signal<bool, SC_MANY_WRITERS> writeY;
#else
sc_signal<int> lenX;
sc_signal<int> lenY;
sc_signal<bool> computeX;
sc_signal<bool> computeY;
sc_signal<bool> readX;
sc_signal<bool> readY;
sc_signal<bool> writeX;
sc_signal<bool> writeY;
#endif
void Control();
void Data_Read();
void PE_Add();
void Data_Write();
int Quantised_Multiplier(int, int, sc_int<8>);
SC_HAS_PROCESS(ACCNAME);
ACCNAME(sc_module_name name_) : sc_module(name_) {
SC_CTHREAD(Control, clock);
reset_signal_is(reset, true);
SC_CTHREAD(Data_Read, clock);
reset_signal_is(reset, true);
SC_CTHREAD(PE_Add, clock);
reset_signal_is(reset, true);
SC_CTHREAD(Data_Write, clock);
reset_signal_is(reset, true);
#pragma HLS RESOURCE variable = din1 core = AXI4Stream metadata = \
"-bus_bundle S_AXIS_DATA1" port_map = { \
{din1_0 TDATA } { \
din1_1 TLAST } }
#pragma HLS RESOURCE variable = dout1 core = AXI4Stream metadata = \
"-bus_bundle M_AXIS_DATA1" port_map = { \
{dout1_0 TDATA } { \
dout1_1 TLAST } }
}
|
dut |
sc_in< bool > clk;
sc_in< bool > rst;
cynw_p2p< input_t >::in din; // TB to DUT, using struct input_t.
cynw_p2p< output_t >::out dout; // DUT to TB, using type output_t.
SC_CTOR( dut )
: clk( "clk" )
, rst( "rst" )
, din( "din" )
, dout( "dout" )
{
SC_CTHREAD( thread1, clk.pos() );
reset_signal_is( rst, false );
din.clk_rst( clk, rst );
dout.clk_rst( clk, rst );
}
void thread1();
|
dut |
sc_in< bool > clk;
sc_in< bool > rst;
cynw_p2p< input_t >::in din; // TB to DUT, using struct input_t.
cynw_p2p< output_t >::out dout; // DUT to TB, using type output_t.
SC_CTOR( dut )
: clk( "clk" )
, rst( "rst" )
, din( "din" )
, dout( "dout" )
{
SC_CTHREAD( thread1, clk.pos() );
reset_signal_is( rst, false );
din.clk_rst( clk, rst );
dout.clk_rst( clk, rst );
}
void thread1();
|
dut |
sc_in< bool > clk;
sc_in< bool > rst;
cynw_p2p< input_t >::in din; // TB to DUT, using struct input_t.
cynw_p2p< output_t >::out dout; // DUT to TB, using type output_t.
SC_CTOR( dut )
: clk( "clk" )
, rst( "rst" )
, din( "din" )
, dout( "dout" )
{
SC_CTHREAD( thread1, clk.pos() );
reset_signal_is( rst, false );
din.clk_rst( clk, rst );
dout.clk_rst( clk, rst );
}
void thread1();
|
dut |
sc_in< bool > clk;
sc_in< bool > rst;
cynw_p2p< input_t >::in din; // TB to DUT, using struct input_t.
cynw_p2p< output_t >::out dout; // DUT to TB, using type output_t.
SC_CTOR( dut )
: clk( "clk" )
, rst( "rst" )
, din( "din" )
, dout( "dout" )
{
SC_CTHREAD( thread1, clk.pos() );
reset_signal_is( rst, false );
din.clk_rst( clk, rst );
dout.clk_rst( clk, rst );
}
void thread1();
|
riscv_soc |
public:
sc_in<bool> i_sys_nrst; // Power-on system reset active LOW
sc_in<bool> i_sys_clk; // System/Bus clock
sc_in<bool> i_dbg_nrst; // Reset from Debug interface (DMI). Reset everything except DMI
sc_in<bool> i_ddr_nrst; // DDR related logic reset (AXI clock transformator)
sc_in<bool> i_ddr_clk; // DDR memoru clock
// GPIO signals:
sc_in<sc_uint<12>> i_gpio;
sc_out<sc_uint<12>> o_gpio;
sc_out<sc_uint<12>> o_gpio_dir;
// JTAG signals:
sc_in<bool> i_jtag_trst;
sc_in<bool> i_jtag_tck;
sc_in<bool> i_jtag_tms;
sc_in<bool> i_jtag_tdi;
sc_out<bool> o_jtag_tdo;
sc_out<bool> o_jtag_vref;
// UART1 signals
sc_in<bool> i_uart1_rd;
sc_out<bool> o_uart1_td;
// SD-card signals:
sc_out<bool> o_sd_sclk; // Clock up to 50 MHz
sc_in<bool> i_sd_cmd; // Command response;
sc_out<bool> o_sd_cmd; // Command request; DO in SPI mode
sc_out<bool> o_sd_cmd_dir; // Direction bit: 1=input; 0=output
sc_in<bool> i_sd_dat0; // Data Line[0] input; DI in SPI mode
sc_out<bool> o_sd_dat0; // Data Line[0] output
sc_out<bool> o_sd_dat0_dir; // Direction bit: 1=input; 0=output
sc_in<bool> i_sd_dat1; // Data Line[1] input
sc_out<bool> o_sd_dat1; // Data Line[1] output
sc_out<bool> o_sd_dat1_dir; // Direction bit: 1=input; 0=output
sc_in<bool> i_sd_dat2; // Data Line[2] input
sc_out<bool> o_sd_dat2; // Data Line[2] output
sc_out<bool> o_sd_dat2_dir; // Direction bit: 1=input; 0=output
sc_in<bool> i_sd_cd_dat3; // Card Detect / Data Line[3] input
sc_out<bool> o_sd_cd_dat3; // Card Detect / Data Line[3] output; CS output in SPI mode
sc_out<bool> o_sd_cd_dat3_dir; // Direction bit: 1=input; 0=output
sc_in<bool> i_sd_detected; // SD-card detected
sc_in<bool> i_sd_protect; // SD-card write protect
// PLL and Reset interfaces:
sc_out<bool> o_dmreset; // Debug reset request. Everything except DMI.
sc_out<mapinfo_type> o_prci_pmapinfo; // PRCI mapping information
sc_in<dev_config_type> i_prci_pdevcfg; // PRCI device descriptor
sc_out<apb_in_type> o_prci_apbi; // APB: PLL and Reset configuration interface
sc_in<apb_out_type> i_prci_apbo; // APB: PLL and Reset configuration interface
// DDR interfaces:
sc_out<mapinfo_type> o_ddr_pmapinfo; // DDR configuration mapping information
sc_in<dev_config_type> i_ddr_pdevcfg; // DDR configuration device descriptor
sc_out<apb_in_type> o_ddr_apbi; // APB: DDR configuration interface
sc_in<apb_out_type> i_ddr_apbo; // APB: DDR configuration interface
sc_out<mapinfo_type> o_ddr_xmapinfo; // DDR memory bank mapping information
sc_in<dev_config_type> i_ddr_xdevcfg; // DDR memory bank descriptor
sc_out<axi4_slave_in_type> o_ddr_xslvi; // AXI DDR memory interface
sc_in<axi4_slave_out_type> i_ddr_xslvo; // AXI DDR memory interface
void comb();
SC_HAS_PROCESS(riscv_soc);
riscv_soc(sc_module_name name,
bool async_reset,
int sim_uart_speedup_rate);
virtual ~riscv_soc();
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
private:
bool async_reset_;
int sim_uart_speedup_rate_;
// Hardware SoC Identificator.
// Read Only unique platform identificator that could be read by FW
static const uint32_t SOC_HW_ID = 0x20220903;
// UARTx fifo log2(size) in bytes:
static const int SOC_UART1_LOG2_FIFOSZ = 4;
// Number of available generic IO pins:
static const int SOC_GPIO0_WIDTH = 12;
// SD-card in SPI mode buffer size. It should be at least log2(512) Bytes:
static const int SOC_SPI0_LOG2_FIFOSZ = 9;
// Number of contexts in PLIC controller.
// Example FU740: S7 Core0 (M) + 4xU74 Cores (M+S).
static const int SOC_PLIC_CONTEXT_TOTAL = 9;
// Any number up to 1024. Zero interrupt must be 0.
static const int SOC_PLIC_IRQ_TOTAL = 73;
sc_signal<axi4_master_out_type> acpo;
sc_signal<axi4_master_in_type> acpi;
bus0_mapinfo_vector bus0_mapinfo;
bus0_xmst_in_vector aximi;
bus0_xmst_out_vector aximo;
bus0_xslv_in_vector axisi;
bus0_xslv_out_vector axiso;
bus1_mapinfo_vector bus1_mapinfo;
bus1_apb_in_vector apbi;
bus1_apb_out_vector apbo;
soc_pnp_vector dev_pnp;
sc_signal<sc_uint<64>> wb_clint_mtimer;
sc_signal<sc_uint<CFG_CPU_MAX>> wb_clint_msip;
sc_signal<sc_uint<CFG_CPU_MAX>> wb_clint_mtip;
sc_signal<sc_uint<SOC_PLIC_CONTEXT_TOTAL>> wb_plic_xeip;
sc_signal<sc_uint<CFG_CPU_MAX>> wb_plic_meip;
sc_signal<sc_uint<CFG_CPU_MAX>> wb_plic_seip;
sc_signal<bool> w_irq_uart1;
sc_signal<sc_uint<SOC_GPIO0_WIDTH>> wb_irq_gpio;
sc_signal<bool> w_irq_pnp;
sc_signal<sc_biguint<SOC_PLIC_IRQ_TOTAL>> wb_ext_irqs;
axictrl_bus0 *bus0;
axi2apb_bus1 *bus1;
axi_rom<CFG_BOOTROM_LOG2_SIZE> *rom0;
axi_sram<CFG_SRAM_LOG2_SIZE> *sram0;
clint<CFG_CPU_MAX> *clint0;
plic<SOC_PLIC_CONTEXT_TOTAL, SOC_PLIC_IRQ_TOTAL> *plic0;
apb_uart<SOC_UART1_LOG2_FIFOSZ> *uart1;
apb_gpio<SOC_GPIO0_WIDTH> *gpio0;
sdctrl *sdctrl0;
apb_pnp<SOC_PNP_TOTAL> *pnp0;
Workgroup *group0;
cdc_axi_sync_tech *u_cdc_ddr0;
|
btclient |
sc_in<unsigned int> rx {"rx" |
ALEXNET |
CONV_RELU_1 m_CONV_RELU_1;
MAX_POOLING_1 m_MAX_POOLING_1;
CONV_RELU_2 m_CONV_RELU_2;
MAX_POOLING_2 m_MAX_POOLING_2;
CONV_RELU_3 m_CONV_RELU_3;
CONV_RELU_4 m_CONV_RELU_4;
CONV_RELU_5 m_CONV_RELU_5;
MAX_POOLING_3 m_MAX_POOLING_3;
LINEAR_RELU_1 m_LINEAR_RELU_1;
LINEAR_RELU_2 m_LINEAR_RELU_2;
LINEAR_3 m_LINEAR_3;
sc_in < bool > clk, rst;
sc_in < bool > in_valid;
sc_fifo < bool > conv1_valid;
sc_fifo < bool > mp1_valid;
sc_fifo < bool > conv2_valid;
sc_fifo < bool > mp2_valid;
sc_fifo < bool > conv3_valid;
sc_fifo < bool > conv4_valid;
sc_fifo < bool > conv5_valid;
sc_fifo < bool > mp3_valid;
sc_fifo < bool > linear1_valid;
sc_fifo < bool > linear2_valid;
sc_out < bool > linear3_valid;
sc_vector < sc_in < sc_fixed_fast<45,17> > > image{"image", 150528 |
tb |
// inputs
sc_in<bool> clk;
sc_in<sc_uint<64> > rt_des_data_i;
sc_in<bool> rt_des_ready_i;
// outputs
sc_out<bool> rt_load_o;
sc_out<sc_uint<64> >rt_des_data_o;
sc_out<sc_uint<64> >rt_des_key_o;
sc_out<bool> rt_decrypt_o;
sc_out<bool> rt_reset;
void send();
void recv();
SC_CTOR(tb)
{
SC_THREAD(send);
sensitive << clk.pos();
SC_THREAD(recv);
sensitive << rt_des_ready_i.pos();
}
~tb()
{
}
|
param_in |
sc_in<bool> clk;
sc_fifo_out<T> o;
void main(void) {
while ( 1 ) {
o.write(val);
if ( trace ) cout << modname << " put " << val << " at " << sc_time_stamp() << endl;
wait(clk.posedge_event());
}
}
SC_HAS_PROCESS(param_in);
param_in(sc_module_name name_, T val_, bool trace_=false) :
modname(name_), sc_module(name_), val(val_), trace(trace_)
{
SC_THREAD(main);
}
~param_in() { }
private:
// Local variables
T val;
// Service
bool trace;
sc_module_name modname;
|
Showcase0 |
// ports
sc_in<sc_uint<32>> a;
sc_in<sc_int<32>> b;
sc_out<sc_uint<32>> c;
sc_in_clk clk;
sc_out<sc_uint<1>> cmp_0;
sc_out<sc_uint<1>> cmp_1;
sc_out<sc_uint<1>> cmp_2;
sc_out<sc_uint<1>> cmp_3;
sc_out<sc_uint<1>> cmp_4;
sc_out<sc_uint<1>> cmp_5;
sc_out<sc_uint<32>> contOut;
sc_in<sc_uint<32>> d;
sc_in<sc_uint<1>> e;
sc_out<sc_uint<1>> f;
sc_out<sc_uint<16>> fitted;
sc_out<sc_uint<8>> g;
sc_out<sc_uint<8>> h;
sc_in<sc_uint<2>> i;
sc_out<sc_uint<8>> j;
sc_out<sc_uint<32>> k;
sc_out<sc_uint<1>> out;
sc_out<sc_uint<1>> output;
sc_in<sc_uint<1>> rst_n;
sc_out<sc_uint<8>> sc_signal_0;
// component instances
// internal signals
sc_uint<32> const_private_signal = sc_uint<32>("0x0000007B");
sc_int<8> fallingEdgeRam[4];
sc_uint<1> r = sc_uint<1>("0b0");
sc_uint<2> r_0 = sc_uint<2>("0b00");
sc_uint<2> r_1 = sc_uint<2>("0b00");
sc_signal<sc_uint<1>> r_next;
sc_signal<sc_uint<2>> r_next_0;
sc_signal<sc_uint<2>> r_next_1;
sc_uint<8> rom[4] = {sc_uint<8>("0x00"),
sc_uint<8>("0x01"),
sc_uint<8>("0x02"),
sc_uint<8>("0x03"),
|
tb_gpio |
public:
sc_signal_resolved pin1 {"pin1" |
tb |
public:
// Declaration of clock and reset parameters
sc_in < bool > clk;
sc_in < bool > rst;
// End of simulation signal.
sc_in < bool > program_end;
// Fetch enable signal.
sc_out < bool > fetch_en;
// CPU Reset
sc_out < bool > cpu_rst;
// Entry point
sc_out < unsigned > entry_point;
// TODO: removeme
// sc_in < bool > main_start;
// sc_in < bool > main_end;
// Instruction counters
sc_in < long int > icount;
sc_in < long int > j_icount;
sc_in < long int > b_icount;
sc_in < long int > m_icount;
sc_in < long int > o_icount;
sc_uint<XLEN> *imem;
sc_uint<XLEN> *dmem;
SC_HAS_PROCESS(tb);
tb(sc_module_name name, sc_uint<XLEN> imem[ICACHE_SIZE], sc_uint<XLEN> dmem[DCACHE_SIZE])
: clk("clk")
, rst("rst")
, program_end("program_end")
, fetch_en("fetch_en")
, cpu_rst("cpu_rst")
, entry_point("entry_point")
// , main_start("main_start")
// , main_end("main_end")
, icount("icount")
, j_icount("j_icount")
, b_icount("b_icount")
, m_icount("m_icount")
, o_icount("o_icount")
, imem(imem)
, dmem(dmem)
{
SC_CTHREAD(source, clk.pos());
reset_signal_is(rst, 0);
SC_CTHREAD(sink, clk.pos());
reset_signal_is(rst, 0);
}
void source();
void sink();
double exec_start;
// double exec_main_start;
|
plic |
public:
sc_in<bool> i_clk; // CPU clock
sc_in<bool> i_nrst; // Reset: active LOW
sc_in<mapinfo_type> i_mapinfo; // interconnect slot information
sc_out<dev_config_type> o_cfg; // Device descriptor
sc_in<axi4_slave_in_type> i_xslvi; // AXI Slave to Bridge interface
sc_out<axi4_slave_out_type> o_xslvo; // AXI Bridge to Slave interface
sc_in<sc_biguint<irqmax>> i_irq_request; // [0] must be tight to GND
sc_out<sc_uint<ctxmax>> o_ip;
void comb();
void registers();
SC_HAS_PROCESS(plic);
plic(sc_module_name name,
bool async_reset);
virtual ~plic();
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
private:
bool async_reset_;
struct plic_context_type {
sc_uint<4> priority_th;
sc_bv<1024> ie; // interrupt enable per context
sc_bv<(4 * 1024)> ip_prio; // interrupt pending priority per context
sc_uint<16> prio_mask; // pending interrupts priorites
sc_uint<4> sel_prio; // the most available priority
sc_uint<10> irq_idx; // currently selected most prio irq
sc_uint<10> irq_prio; // currently selected prio level
|
keyExpansion |
sc_in<sc_logic> key[128];
sc_out<sc_logic> w[1408];
sc_signal<sc_lv<1408>> w_lv;
sc_signal<sc_lv<128>> key_lv;
sc_lv<32> temp;
sc_lv<32> r;
sc_lv<32> rot;
sc_lv<32> x;
sc_lv<32> rconv;
sc_lv<32> new_k;
sc_lv<1408> w_temp;
SC_CTOR( keyExpansion ) {
SC_METHOD(eval);
dont_initialize();
sensitive << key_lv;
// convert w port (array of logic) to w_lv (logic_vector)
SC_THREAD(w_assignment);
sensitive << w_lv;
// convert key port (array of logic) to key_lv (logic_vector)
SC_THREAD(key_assignment);
// dont_initialize();
for(int i = 0; i < 128; i++){
SENSITIVITY(key, i);
}
}
void w_assignment(void){
while(true) {
for (int i = 0; i < 1408; i++){
w[1407 - i].write(w_lv.read()[i]);
}
wait(SC_ZERO_TIME);
wait();
}
}
void key_assignment(void){
while(true) {
sc_lv<128> key_lv_temp;
for (int i = 0; i < 128; i++){
key_lv_temp[i] = key[i].read();
}
key_lv.write(key_lv_temp.range(0, 127));
wait(SC_ZERO_TIME);
wait();
}
}
void eval(void){
const char* zeros = zero_fill(1408 - 128).c_str();
w_temp = (zeros, key_lv.read());
// std::cout << "key(): " << key_lv.read() << std::endl;
for (int i = 4; i < 4*(10 + 1); i = i + 1) {
temp = w_temp.range(1407 - (1407- (32 - 1)), 1407 - (1407));
// temp = w_temp.range((128 * (10 + 1) - 32), (128 * (10 + 1) - 32) + (32 - 1));
// std::cout << "R [" << i << "]" << std::endl;
// std::cout << "Initial temp: " << temp << std::endl;
// std::cout << "R [" << i << "]- w_temp.range(1407-32, 1407): " << w_temp.range(1407 - (1407- (32 - 1)), 1407 - (1407)) << std::endl;
if ((i % 4) == 0){
rot = rotword(temp); // A call to the function rotword() is done and the returned value is stored in rot.
x = subwordx(rot); //A call to the function subwordx() is done and the returned value is stored in x.
rconv = rconx(i/4); //A call to the function rconx() is done and the returned value is stored in rconv.
temp = x ^ rconv;
} else if (i % 4 == 4){
temp = subwordx(temp);
}
new_k = w_temp.range((1407 - (128*(10+1)-(4*32))), (1407 - ((128*(10+1)-(4*32))+(32-1)))) ^ temp;
w_temp = w_temp << 32;
// w_temp = (w_temp.range(1407 - 0, 1407 - ((128 * (10 + 1) - 32) - 1)), new_k);
w_temp = (w_temp.range(1407 - 0, 1407 - ((128 * (10 + 1) - 32) - 1)), new_k);
// std::cout << "!!!! "<< std::endl;
// std::cout << "rot: " << rot << std::endl;
// std::cout << "x: " << x << std::endl;
// std::cout << "rconv: " << rconv << std::endl;
// std::cout << "temp: " << temp << std::endl;
// std::cout << "new_k: " << new_k << std::endl;
// std::cout << "W-temp: " << w_temp << std::endl;
// std::cout << "------------------- "<< std::endl;
}
w_lv.write(w_temp);
// std::cout << "W : " << w_temp << std::endl;
}
|
st7735 |
sc_inout<gn_mixed> sda {"sda" |
cd4067 |
sc_in<bool> inh {"inh" |
apb_pnp |
public:
sc_in<bool> i_clk; // CPU clock
sc_in<bool> i_nrst; // Reset: active LOW
sc_in<mapinfo_type> i_mapinfo; // interconnect slot information
sc_vector<sc_in<dev_config_type>> i_cfg; // Device descriptors vector
sc_out<dev_config_type> o_cfg; // PNP Device descriptor
sc_in<apb_in_type> i_apbi; // APB Slave to Bridge interface
sc_out<apb_out_type> o_apbo; // APB Bridge to Slave interface
sc_out<bool> o_irq;
void comb();
void registers();
SC_HAS_PROCESS(apb_pnp);
apb_pnp(sc_module_name name,
bool async_reset,
sc_uint<32> hwid,
int cpu_max,
int l2cache_ena,
int plic_irq_max);
virtual ~apb_pnp();
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
private:
bool async_reset_;
sc_uint<32> hwid_;
int cpu_max_;
int l2cache_ena_;
int plic_irq_max_;
struct apb_pnp_registers {
sc_signal<sc_uint<32>> fw_id;
sc_signal<sc_uint<32>> idt_l;
sc_signal<sc_uint<32>> idt_m;
sc_signal<sc_uint<32>> malloc_addr_l;
sc_signal<sc_uint<32>> malloc_addr_m;
sc_signal<sc_uint<32>> malloc_size_l;
sc_signal<sc_uint<32>> malloc_size_m;
sc_signal<sc_uint<32>> fwdbg1;
sc_signal<sc_uint<32>> fwdbg2;
sc_signal<sc_uint<32>> fwdbg3;
sc_signal<sc_uint<32>> fwdbg4;
sc_signal<sc_uint<32>> fwdbg5;
sc_signal<sc_uint<32>> fwdbg6;
sc_signal<bool> irq;
sc_signal<bool> resp_valid;
sc_signal<sc_uint<32>> resp_rdata;
sc_signal<bool> resp_err;
} v, r;
void apb_pnp_r_reset(apb_pnp_registers &iv) {
iv.fw_id = 0;
iv.idt_l = 0;
iv.idt_m = 0;
iv.malloc_addr_l = 0;
iv.malloc_addr_m = 0;
iv.malloc_size_l = 0;
iv.malloc_size_m = 0;
iv.fwdbg1 = 0;
iv.fwdbg2 = 0;
iv.fwdbg3 = 0;
iv.fwdbg4 = 0;
iv.fwdbg5 = 0;
iv.fwdbg6 = 0;
iv.irq = 0;
iv.resp_valid = 0;
iv.resp_rdata = 0;
iv.resp_err = 0;
}
sc_signal<bool> w_req_valid;
sc_signal<sc_uint<32>> wb_req_addr;
sc_signal<bool> w_req_write;
sc_signal<sc_uint<32>> wb_req_wdata;
apb_slv *pslv0;
|
RegIntBank |
public:
sc_in<bool> i_clk; // CPU clock
sc_in<bool> i_nrst; // Reset: active LOW
sc_in<sc_uint<6>> i_radr1; // Port 1 read address
sc_out<sc_uint<RISCV_ARCH>> o_rdata1; // Port 1 read value
sc_out<sc_uint<CFG_REG_TAG_WIDTH>> o_rtag1; // Port 1 read tag value
sc_in<sc_uint<6>> i_radr2; // Port 2 read address
sc_out<sc_uint<RISCV_ARCH>> o_rdata2; // Port 2 read value
sc_out<sc_uint<CFG_REG_TAG_WIDTH>> o_rtag2; // Port 2 read tag value
sc_in<sc_uint<6>> i_waddr; // Writing value
sc_in<bool> i_wena; // Writing is enabled
sc_in<sc_uint<CFG_REG_TAG_WIDTH>> i_wtag; // Writing register tag
sc_in<sc_uint<RISCV_ARCH>> i_wdata; // Writing value
sc_in<bool> i_inorder; // Writing only if tag sequenced
sc_out<bool> o_ignored; // Sequenced writing is ignored because it was overwritten by executor (need for tracer)
sc_in<sc_uint<6>> i_dport_addr; // Debug port address
sc_in<bool> i_dport_ena; // Debug port is enabled
sc_in<bool> i_dport_write; // Debug port write is enabled
sc_in<sc_uint<RISCV_ARCH>> i_dport_wdata; // Debug port write value
sc_out<sc_uint<RISCV_ARCH>> o_dport_rdata; // Debug port read value
sc_out<sc_uint<RISCV_ARCH>> o_ra; // Return address for branch predictor
sc_out<sc_uint<RISCV_ARCH>> o_sp; // Stack Pointer for border control
sc_out<sc_uint<RISCV_ARCH>> o_gp;
sc_out<sc_uint<RISCV_ARCH>> o_tp;
sc_out<sc_uint<RISCV_ARCH>> o_t0;
sc_out<sc_uint<RISCV_ARCH>> o_t1;
sc_out<sc_uint<RISCV_ARCH>> o_t2;
sc_out<sc_uint<RISCV_ARCH>> o_fp;
sc_out<sc_uint<RISCV_ARCH>> o_s1;
sc_out<sc_uint<RISCV_ARCH>> o_a0;
sc_out<sc_uint<RISCV_ARCH>> o_a1;
sc_out<sc_uint<RISCV_ARCH>> o_a2;
sc_out<sc_uint<RISCV_ARCH>> o_a3;
sc_out<sc_uint<RISCV_ARCH>> o_a4;
sc_out<sc_uint<RISCV_ARCH>> o_a5;
sc_out<sc_uint<RISCV_ARCH>> o_a6;
sc_out<sc_uint<RISCV_ARCH>> o_a7;
sc_out<sc_uint<RISCV_ARCH>> o_s2;
sc_out<sc_uint<RISCV_ARCH>> o_s3;
sc_out<sc_uint<RISCV_ARCH>> o_s4;
sc_out<sc_uint<RISCV_ARCH>> o_s5;
sc_out<sc_uint<RISCV_ARCH>> o_s6;
sc_out<sc_uint<RISCV_ARCH>> o_s7;
sc_out<sc_uint<RISCV_ARCH>> o_s8;
sc_out<sc_uint<RISCV_ARCH>> o_s9;
sc_out<sc_uint<RISCV_ARCH>> o_s10;
sc_out<sc_uint<RISCV_ARCH>> o_s11;
sc_out<sc_uint<RISCV_ARCH>> o_t3;
sc_out<sc_uint<RISCV_ARCH>> o_t4;
sc_out<sc_uint<RISCV_ARCH>> o_t5;
sc_out<sc_uint<RISCV_ARCH>> o_t6;
void comb();
void registers();
SC_HAS_PROCESS(RegIntBank);
RegIntBank(sc_module_name name,
bool async_reset);
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
private:
bool async_reset_;
struct RegValueType {
sc_signal<sc_uint<RISCV_ARCH>> val;
sc_signal<sc_uint<CFG_REG_TAG_WIDTH>> tag;
|
_sc_stream_buffer |
typedef typename hwcore::pipes::SC_DATA_STREAM_T_trait<1 * W>::interface_T interface_T;
enum ctrls { newset = 0, reapeat = 1 |
_sc_stream_buffer_not_stream_while_write |
typedef typename hwcore::pipes::SC_DATA_STREAM_T_trait<1 * W>::interface_T interface_T;
enum ctrls { newset = 0, reapeat = 1 |
add_one_wrapper |
public:
sc_in< bool > clk;
sc_in< bool > rst;
cynw::cynw_p2p_base_in <sc_dt::sc_int <(int)32 >, HLS::hls_enum <(int)1 > > add_one_x;
cynw::cynw_p2p_base_out <sc_dt::sc_int <(int)32 >, HLS::hls_enum <(int)1 > > add_one_return;
// These signals are used to connect structured ports or ports that need
// type conversion to the RTL ports.
// create the netlist
void InitInstances( sc_int< 32 > _A[10]);
void InitThreads();
// delete the netlist
void DeleteInstances();
// The following threads are used to connect structured ports to the actual
// RTL ports.
SC_HAS_PROCESS(add_one_wrapper);
add_one_wrapper( sc_core::sc_module_name name, sc_int< 32 > _A[10] )
: sc_module(name)
,clk("clk")
,rst("rst")
,add_one_x("add_one_x")
,add_one_return("add_one_return")
,add_one0(0)
{
InitInstances( _A);
InitThreads();
}
// destructor
~add_one_wrapper()
{
DeleteInstances();
}
add_one* add_one0;
|
Filter |
protected:
//----------------------------Internal Variables----------------------------
#ifdef IPS_DUMP_EN
sc_trace_file* wf;
#endif // IPS_DUMP_EN
OUT* img_window_tmp;
OUT* kernel;
OUT* result_ptr;
// Event to trigger the filter execution
sc_event event;
//-----------------------------Internal Methods-----------------------------
void exec_filter();
void init();
public:
/**
* @brief Default constructor for Filter
*/
SC_HAS_PROCESS(Filter);
#ifdef IPS_DUMP_EN
/**
* @brief Construct a new Filter object
*
* @param name - name of the module
* @param wf - waveform file pointer
*/
Filter(sc_core::sc_module_name name, sc_core::sc_trace_file* wf)
: sc_core::sc_module(name), wf(wf)
#else
/**
* @brief Construct a new Filter object
*
* @param name - name of the module
*/
Filter(sc_core::sc_module_name name) : sc_core::sc_module(name)
#endif // IPS_DUMP_EN
{
// Calling this method by default since it is no time consumer
// It is assumed that this kernel is already loaded in the model
// Kernel does not change after synthesis
SC_METHOD(init);
// Thread waiting for the request
SC_THREAD(exec_filter);
}
//---------------------------------Methods---------------------------------
void filter(IN* img_window, OUT* result);
|
gndemux |
sc_port< sc_signal_out_if<gn_mixed>,0 > pin {"pin" |
Filter |
protected:
//----------------------------Internal Variables----------------------------
#ifdef IPS_DUMP_EN
sc_trace_file* wf;
#endif // IPS_DUMP_EN
OUT* kernel;
// Event to trigger the filter execution
sc_event event;
//-----------------------------Internal Methods-----------------------------
void exec_filter();
void init();
public:
sc_in<IN* > img_window;
sc_out<OUT > result;
/**
* @brief Default constructor for Filter
*/
SC_HAS_PROCESS(Filter);
#ifdef IPS_DUMP_EN
/**
* @brief Construct a new Filter object
*
* @param name - name of the module
* @param wf - waveform file pointer
*/
Filter(sc_core::sc_module_name name, sc_core::sc_trace_file* wf)
: sc_core::sc_module(name), wf(wf)
#else
/**
* @brief Construct a new Filter object
*
* @param name - name of the module
*/
Filter(sc_core::sc_module_name name) : sc_core::sc_module(name)
#endif // IPS_DUMP_EN
{
// Calling this method by default since it is no time consumer
// It is assumed that this kernel is already loaded in the model
// Kernel does not change after synthesis
SC_METHOD(init);
// Thread waiting for the request
SC_THREAD(exec_filter);
}
//---------------------------------Methods---------------------------------
void filter();
|
simple_bus_master_blocking |
// ports
sc_in_clk clock;
sc_port<simple_bus_blocking_if> bus_port;
// constructor
simple_bus_master_blocking(sc_module_name name_
, unsigned int unique_priority
, unsigned int address
, bool lock
, int timeout)
: sc_module(name_)
, m_unique_priority(unique_priority)
, m_address(address)
, m_lock(lock)
, m_timeout(timeout)
{
// process declaration
SC_THREAD(main_action);
sensitive << clock.pos();
}
// process
void main_action();
private:
unsigned int m_unique_priority;
unsigned int m_address;
bool m_lock;
int m_timeout;
|
fetch |
sc_port <mem_if> p_mem;
sc_port <breg_if> p_breg;
sc_fifo_in < contexto*> execute_fetch;
sc_fifo_out < contexto* > fetch_decode;
void fetch_method(){
while(true){
recebimento = execute_fetch.read();
escrita = recebimento;
PC = (p_breg->read(31));
#ifdef RASTREIA_PC
cout << "PC = " << PC << endl;
#endif
escrita->ri = p_mem->read(PC);
//Registrador 31 = PC
p_breg->write(31, PC +1);
//Instrucao que nao faz sentido lw $0, $0
//Interrompe execucao
if(escrita->ri == 0){
p_breg->dump_breg();
sc_stop();
exit(0);
} //if
fetch_decode.write(escrita);
} // while
}
SC_CTOR(fetch){
recebimento = new contexto();
escrita = new contexto();
SC_THREAD(fetch_method);
}
private:
contexto *escrita;
contexto *recebimento;
uint32_t PC;
|
GemmDriver |
sc_in<bool> clock;
sc_in <bool> reset;
sc_fifo_in<DATA> dout1;
sc_fifo_in<DATA> dout2;
sc_fifo_in<DATA> dout3;
sc_fifo_in<DATA> dout4;
sc_fifo_out<DATA> din1;
sc_fifo_out<DATA> din2;
sc_fifo_out<DATA> din3;
sc_fifo_out<DATA> din4;
bool sent;
bool retval;
//States
int states[9];
sc_signal<int> sourceS;
sc_signal<int> sinkS;
sc_in<int> inS;
sc_in<int> outS;
sc_in<int> w1S;
sc_in<int> w2S;
sc_in<int> w3S;
sc_in<int> w4S;
sc_in<int> schS;
sc_in<int> p1S;
sc_in<int> read_cycle_count;
sc_in<int> process_cycle_count;
sc_in<int> gemm_1_idle;
sc_in<int> gemm_2_idle;
sc_in<int> gemm_3_idle;
sc_in<int> gemm_4_idle;
sc_in<int> gemm_1_write;
sc_in<int> gemm_2_write;
sc_in<int> gemm_3_write;
sc_in<int> gemm_4_write;
sc_in<int> gemm_1;
sc_in<int> gemm_2;
sc_in<int> gemm_3;
sc_in<int> gemm_4;
sc_in<int> wstall_1;
sc_in<int> wstall_2;
sc_in<int> wstall_3;
sc_in<int> wstall_4;
sc_in<int> rmax;
sc_in<int> lmax;
int p_cycles= 0;
int waiting= 0;
int loading= 0;
int g1_idle= 0;
int g2_idle= 0;
int g3_idle= 0;
int g4_idle= 0;
int g1_write= 0;
int g2_write= 0;
int g3_write= 0;
int g4_write= 0;
int g1_gemm= 0;
int g2_gemm= 0;
int g3_gemm= 0;
int g4_gemm= 0;
int wstall1=0;
int wstall2=0;
int wstall3=0;
int wstall4=0;
int r_max=0;
int l_max=0;
void Source();
void Sink();
void Status();
void read_in();
void read_out();
SC_HAS_PROCESS(GemmDriver);
// Parameters for the DUT
GemmDriver(sc_module_name name_) :sc_module(name_) { // @suppress("Class members should be properly initialized")
SC_CTHREAD(Source, clock.pos());
reset_signal_is(reset,true);
SC_CTHREAD(Sink, clock.pos());
reset_signal_is(reset,true);
SC_CTHREAD(Status, clock.neg());
reset_signal_is(reset,true);
}
int inl0;
int inl1;
int inl2;
int inl3;
int in0[563840];
int in1[563840];
int in2[563840];
int in3[563840];
int out0[554800];
int out1[554800];
int out2[554800];
int out3[554800];
|
ACCNAME |
sc_in<bool> clock;
sc_in<bool> reset;
sc_in<unsigned int> start_acc;
sc_out<unsigned int> done_acc;
sc_in<bool> reset_acc;
sc_in<unsigned int> insn_count;
sc_in<unsigned int> insn_addr;
sc_in<unsigned int> input_addr;
sc_in<unsigned int> weight_addr;
sc_in<unsigned int> bias_addr;
sc_in<unsigned int> output_addr;
sc_in<int> crf;
sc_in<int> crx;
sc_in<int> ra;
sc_in<int> depth;
AXI4M_bus_port<unsigned long long> insn_port;
AXI4M_bus_port<unsigned long long> input_port;
AXI4M_bus_port<unsigned long long> weight_port;
AXI4M_bus_port<unsigned long long> bias_port;
AXI4M_bus_port<unsigned int> out_port;
// Instantiate memories
#ifndef __SYNTHESIS__
wgt_bt* wgt_mem1 = new wgt_bt[WGT_DEPTH];
wgt_bt* wgt_mem2 = new wgt_bt[WGT_DEPTH];
wgt_bt* wgt_mem3 = new wgt_bt[WGT_DEPTH];
wgt_bt* wgt_mem4 = new wgt_bt[WGT_DEPTH];
inp_bt* inp_mem1 = new inp_bt[INP_DEPTH];
inp_bt* inp_mem2 = new inp_bt[INP_DEPTH];
inp_bt* inp_mem3 = new inp_bt[INP_DEPTH];
inp_bt* inp_mem4 = new inp_bt[INP_DEPTH];
acc_bt* acc_mem = new acc_bt[ACC_DEPTH];
#else
wgt_bt wgt_mem1[WGT_DEPTH];
wgt_bt wgt_mem2[WGT_DEPTH];
wgt_bt wgt_mem3[WGT_DEPTH];
wgt_bt wgt_mem4[WGT_DEPTH];
inp_bt inp_mem1[INP_DEPTH];
inp_bt inp_mem2[INP_DEPTH];
inp_bt inp_mem3[INP_DEPTH];
inp_bt inp_mem4[INP_DEPTH];
acc_bt acc_mem[ACC_DEPTH];
#endif
out_bt out_mem[4][4];
#ifndef __SYNTHESIS__
sc_signal<bool, SC_MANY_WRITERS> wgt_load;
sc_signal<bool, SC_MANY_WRITERS> inp_load;
sc_signal<bool, SC_MANY_WRITERS> bias_load;
sc_signal<bool, SC_MANY_WRITERS> gemm_wait;
sc_signal<bool, SC_MANY_WRITERS> schedule;
sc_signal<bool, SC_MANY_WRITERS> storing;
#else
sc_signal<bool> wgt_load;
sc_signal<bool> inp_load;
sc_signal<bool> bias_load;
sc_signal<bool> gemm_wait;
sc_signal<bool> schedule;
sc_signal<bool> storing;
#endif
sc_signal<bool> loading;
sc_uint<64> wgt_insn1;
sc_uint<64> wgt_insn2;
sc_uint<64> inp_insn1;
sc_uint<64> inp_insn2;
sc_uint<64> bias_insn1;
sc_uint<64> bias_insn2;
// sc_signal<unsigned int> bias_load_doffset;
// sc_signal<unsigned int> bias_load_dstride;
// sc_signal<unsigned int> bias_minc;
// sc_signal<unsigned int> bias_load_length;
// Scheduler
sc_signal<unsigned int> wgt_block;
sc_signal<unsigned int> inp_block;
sc_signal<unsigned int> depth_val;
// GEMM Unit signals
sc_signal<unsigned int> wp_val;
sc_signal<unsigned int> ip_val;
// Store Unit signals
sc_signal<unsigned int> store_doffset;
sc_signal<unsigned int> store_dstride;
sc_signal<unsigned int> m_off;
sc_signal<unsigned int> n_off;
sc_signal<bool> fetch_resetted;
int start_count;
int done_count;
int ra_val;
int crf_val;
int crx_val;
bool resetted;
sc_int<64> pl;
sc_int<32> pr;
sc_int<32> msk;
sc_int<32> sm;
// // Profiling variable
// ClockCycles* per_batch_cycles = new ClockCycles("per_batch_cycles", true);
// std::vector<Metric*> profiling_vars = {per_batch_cycles |
InstrFetch |
sc_in<bool> i_clk;
sc_in<bool> i_nrst;
sc_in<bool> i_pipeline_hold;
sc_in<bool> i_mem_req_ready;
sc_out<bool> o_mem_addr_valid;
sc_out<sc_uint<BUS_ADDR_WIDTH>> o_mem_addr;
sc_in<bool> i_mem_data_valid;
sc_in<sc_uint<BUS_ADDR_WIDTH>> i_mem_data_addr;
sc_in<sc_uint<32>> i_mem_data;
sc_in<bool> i_mem_load_fault;
sc_out<bool> o_mem_resp_ready;
sc_in<sc_uint<BUS_ADDR_WIDTH>> i_e_npc;
sc_in<sc_uint<BUS_ADDR_WIDTH>> i_predict_npc;
sc_in<bool> i_predict;
sc_out<bool> o_predict_miss;
sc_out<bool> o_mem_req_fire; // used by branch predictor to form new npc value
sc_out<bool> o_ex_load_fault;
sc_out<bool> o_valid;
sc_out<sc_uint<BUS_ADDR_WIDTH>> o_pc;
sc_out<sc_uint<32>> o_instr;
sc_out<bool> o_hold; // Hold due no response from icache yet
sc_in<bool> i_br_fetch_valid; // Fetch injection address/instr are valid
sc_in<sc_uint<BUS_ADDR_WIDTH>> i_br_address_fetch; // Fetch injection address to skip ebreak instruciton only once
sc_in<sc_uint<32>> i_br_instr_fetch; // Real instruction value that was replaced by ebreak
sc_out<sc_biguint<DBG_FETCH_TRACE_SIZE*64>> o_instr_buf; // todo: remove it
void comb();
void registers();
SC_HAS_PROCESS(InstrFetch);
InstrFetch(sc_module_name name_);
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
private:
struct RegistersType {
sc_signal<bool> wait_resp;
sc_signal<sc_uint<5>> pipeline_init;
sc_signal<sc_uint<BUS_ADDR_WIDTH>> pc_z1;
sc_signal<sc_uint<BUS_ADDR_WIDTH>> raddr_not_resp_yet;
sc_signal<sc_uint<BUS_ADDR_WIDTH>> br_address;
sc_signal<sc_uint<32>> br_instr;
sc_signal<sc_biguint<DBG_FETCH_TRACE_SIZE*64>> instr_buf;
} v, r;
|
tb |
public:
sc_vector<sc_out<bool>> inp_a, inp_b;
sc_out<bool> inp_cin;
sc_vector<sc_in<bool>> sum;
sc_in<bool> co;
SC_HAS_PROCESS( tb );
bool a[6][4];
bool b[6][4];
tb( sc_module_name nm );
private:
void source();
void sink();
|
tb_top_imagedata_fix |
sc_clock clk;
sc_in<bool> iclk;
sc_signal<bool> reset;
typedef hwcore::pipes::sc_stream_imagedatafix<W, I, BW> stream_image_t;
typedef typename stream_image_t::din_T fifo_t;
stream_image_t imagefix_u0;
sc_fifo<fifo_t> din;
sc_fifo<fifo_t> dout;
sc_fifo<sc_uint<1> > enable;
SC_CTOR(tb_top_imagedata_fix) : clk("clk", sc_time(10, SC_NS)), SC_INST(imagefix_u0) {
iclk(clk);
SC_MODULE_LINK(imagefix_u0);
imagefix_u0.din(din);
imagefix_u0.dout(dout);
imagefix_u0.enable(enable);
SC_CTHREAD(wave_thread, iclk.pos());
HLS_DEBUG_EXEC(set_stack_size(128 * 10 * 1024 * 1024));
SC_CTHREAD(mon_thread, iclk.pos());
HLS_DEBUG_EXEC(set_stack_size(128 * 10 * 1024 * 1024));
}
sc_ufixed<8, 0> func(int a, int b, int c) {
sc_ufixed<8, 0> tmp = 0;
tmp(7, 5) = a;
tmp(4, 2) = b;
tmp(1, 0) = c;
return tmp;
}
void func_inv(sc_ufixed<8, 0> in, int &a, int &b, int &c) {
a = in(7, 5).to_int();
b = in(4, 2).to_int();
c = in(1, 0).to_int();
}
void wave_thread() {
reset.write(1);
wait();
reset.write(0);
wait();
sc_assert(BW >= 3);
const int image_size = 32;
sc_fixed<W, I> *realign_data = new sc_fixed<W, I>[image_size * image_size * BW];
for (int x = 0; x < image_size; x++) {
for (int y = 0; y < image_size; y++) {
for (int z = 0; z < BW; z++) {
int ptr_to = (x * image_size * BW) + (y * BW) + z;
if (z < 3) {
realign_data[ptr_to] = func(x, y, z);
std::cout << realign_data[ptr_to].to_float() << std::endl;
} else {
realign_data[ptr_to] = 0;
}
}
}
}
enable.write(0);
for (int i = 0; i < image_size * image_size; i++) {
fifo_t tmp_out;
tmp_out.setKeep();
tmp_out.setDataFixed<W, I, BW>(&realign_data[i * BW]);
tmp_out.tlast = (i == (image_size * image_size) - 1 ? 1 : 0);
din.write(tmp_out);
}
sc_ufixed<8, 0> *raw_data = new sc_ufixed<8, 0>[image_size * image_size * 3];
for (int x = 0; x < image_size; x++) {
for (int y = 0; y < image_size; y++) {
for (int z = 0; z < 3; z++) {
int ptr_to = (x * image_size * 3) + (y * 3) + z;
raw_data[ptr_to] = func(x, y, z);
std::cout << raw_data[ptr_to].to_float() << std::endl;
}
}
}
enable.write(1);
const int N = (image_size * image_size * 3 * 8) / (BW * W);
const int N_pr_pkg = (BW * W) / 8;
for (int i = 0; i < N; i++) {
fifo_t tmp_out;
tmp_out.setKeep();
tmp_out.setDataUfixed<8, 0, (BW * W) / 8>(&raw_data[i * N_pr_pkg]);
tmp_out.tlast = (i == N - 1 ? 1 : 0);
din.write(tmp_out);
}
while (true) {
wait();
}
}
void mon_thread() {
std::list<fifo_t> realign_data;
std::list<fifo_t> raw_data;
fifo_t tmp;
do {
tmp = dout.read();
realign_data.push_back(tmp);
} while (tmp.tlast == 0);
std::cout << "mon got N samples " << realign_data.size() << std::endl;
do {
tmp = dout.read();
raw_data.push_back(tmp);
} while (tmp.tlast == 0);
std::cout << "mon got N samples " << raw_data.size() << std::endl;
sc_assert(raw_data.size() == realign_data.size());
auto itr_realign_data = realign_data.begin();
auto itr_raw_data = raw_data.begin();
for (int i = 0; i < realign_data.size(); i++) {
sc_assert(*itr_realign_data == *itr_raw_data);
itr_realign_data++;
itr_raw_data++;
}
wait();
sc_stop();
}
|
Sensor_${sensor_name}_functional |
Core* core;
//Input Port
sc_core::sc_in <bool> enable;
sc_core::sc_in <unsigned int> address;
sc_core::sc_in <uint8_t*> data_in;
sc_core::sc_in <unsigned int> req_size;
sc_core::sc_in <bool> flag_wr;
sc_core::sc_in <bool> ready;
//Output Port
sc_core::sc_out <uint8_t*> data_out;
sc_core::sc_out <bool> go;
//Power Port
sc_core::sc_out <int> power_signal;
//Thermal Port
//sc_core::sc_out <int> thermal_signal;
SC_CTOR(Sensor_${sensor_name}_functional):
enable("Enable_signal"),
address("Address"),
data_in("Data_in"),
flag_wr("Flag"),
ready("Ready"),
data_out("Data_out"),
go("Go"),
power_signal("Func_to_Power_signal")
{
//printf("SENSOR :: systemc constructor");
register_memory = new uint8_t[${register_memory}];
SC_THREAD(sensor_logic);
sensitive << ready;
}
void sensor_logic();
Sensor_${sensor_name}_functional(){
//printf("SENSOR :: constructor");
}
~Sensor_${sensor_name}_functional(){
delete[]register_memory;
}
//Register Map
private:
uint8_t* register_memory;
int register_memory_size=${register_memory |
top)
//| {
//| sc_process_handle run_proc;
//|
//| SC_CTOR(top |
//| run_proc = sc_spawn(sc_bind(&run_phase,this),"run_phase");
//| |
InputSetup |
public:
sc_in_clk clk;
sc_in<bool> rst;
typedef SysPE::InputType InputType;
static const int N = SysArray::N; // # banks = N
static const int Entries = N*4; // # of entries per bank
static const int Capacity = N*Entries;
typedef ArbitratedScratchpad<InputType, Capacity, N, N, 0> MemType;
static const int IndexBits = nvhls::nbits<Entries-1>::val;
typedef NVUINTW(IndexBits) IndexType;
typedef NVUINTW(IndexBits+1) StartType;
typedef typename nvhls::nv_scvector <InputType, N> VectorType;
// Customized data type for Input Write Request
class WriteReq: public nvhls_message{
public:
VectorType data;
IndexType index;
static const unsigned int width = IndexType::width + VectorType::width;
template <unsigned int Size>
void Marshall(Marshaller<Size>& m) {
m& data;
m& index;
}
|
xtea_RTL_testbench |
private:
void run();
public:
sc_in_clk clk;
sc_out< bool > rst;
sc_in<sc_uint<1> > dout_rdy; // output from xtea module
sc_in<sc_uint<32> > result0_in;
sc_in<sc_uint<32> > result1_in;
sc_out<sc_uint<1> > din_rdy; // input for xtea module
sc_out<sc_uint<32> > word0_out;
sc_out<sc_uint<32> > word1_out;
sc_out<sc_uint<32> > key0_out;
sc_out<sc_uint<32> > key1_out;
sc_out<sc_uint<32> > key2_out;
sc_out<sc_uint<32> > key3_out;
sc_out< bool > mode_out;
SC_CTOR(xtea_RTL_testbench) {
SC_THREAD(run);
sensitive << clk.pos();
}
|
spimod |
public:
sc_out<bool> d_oen_o {"d_oen_o" |
EdgeDetector |
enum ed_icm_mode {
Any,
Pos,
Neg
|
Edge_Detector |
#ifndef USING_TLM_TB_EN
sc_inout<sc_uint<64>> data;
sc_in<sc_uint<24>> address;
#else
sc_uint<64> data;
sc_uint<64> address;
#endif // USING_TLM_TB_EN
const double delay_full_adder_1_bit = 0.361;
const double delay_full_adder = delay_full_adder_1_bit * 16;
const double delay_multiplier = 9.82;
const sc_int<16> sobelGradientX[3][3] = {{-1, 0, 1},
{-2, 0, 2},
{-1, 0, 1} |
MemAccess |
sc_in<bool> i_clk;
sc_in<bool> i_nrst;
sc_in<bool> i_e_valid; // Execution stage outputs are valid
sc_in<sc_uint<BUS_ADDR_WIDTH>> i_e_pc; // Execution stage instruction pointer
sc_in<sc_uint<32>> i_e_instr; // Execution stage instruction value
sc_in<sc_uint<5>> i_res_addr; // Register address to be written (0=no writing)
sc_in<sc_uint<RISCV_ARCH>> i_res_data; // Register value to be written
sc_in<bool> i_memop_sign_ext; // Load data with sign extending (if less than 8 Bytes)
sc_in<bool> i_memop_load; // Load data from memory and write to i_res_addr
sc_in<bool> i_memop_store; // Store i_res_data value into memory
sc_in<sc_uint<2>> i_memop_size; // Encoded memory transaction size in bytes: 0=1B; 1=2B; 2=4B; 3=8B
sc_in<sc_uint<BUS_ADDR_WIDTH>> i_memop_addr; // Memory access address
sc_out<bool> o_wena; // Write enable signal
sc_out<sc_uint<5>> o_waddr; // Output register address (0 = x0 = no write)
sc_out<sc_uint<RISCV_ARCH>> o_wdata; // Register value
// Memory interface:
sc_in<bool> i_mem_req_ready; // Data cache is ready to accept request
sc_out<bool> o_mem_valid; // Memory request is valid
sc_out<bool> o_mem_write; // Memory write request
sc_out<sc_uint<2>> o_mem_sz; // Encoded data size in bytes: 0=1B; 1=2B; 2=4B; 3=8B
sc_out<sc_uint<BUS_ADDR_WIDTH>> o_mem_addr; // Data path requested address
sc_out<sc_uint<BUS_DATA_WIDTH>> o_mem_data; // Data path requested data (write transaction)
sc_in<bool> i_mem_data_valid; // Data path memory response is valid
sc_in<sc_uint<BUS_ADDR_WIDTH>> i_mem_data_addr; // Data path memory response address
sc_in<sc_uint<BUS_DATA_WIDTH>> i_mem_data; // Data path memory response value
sc_out<bool> o_mem_resp_ready; // Pipeline is ready to accept memory operation response
sc_out<bool> o_hold; // Hold pipeline by data cache wait state reason
sc_out<bool> o_valid; // Output is valid
sc_out<sc_uint<BUS_ADDR_WIDTH>> o_pc; // Valid instruction pointer
sc_out<sc_uint<32>> o_instr; // Valid instruction value
void comb();
void registers();
SC_HAS_PROCESS(MemAccess);
MemAccess(sc_module_name name_);
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
private:
struct RegistersType {
sc_signal<bool> valid;
sc_signal<sc_uint<BUS_ADDR_WIDTH>> pc;
sc_signal<sc_uint<32>> instr;
sc_signal<bool> wena;
sc_signal<sc_uint<5>> waddr;
sc_signal<bool> sign_ext;
sc_signal<sc_uint<2>> size;
sc_signal<sc_uint<RISCV_ARCH>> wdata;
sc_signal<bool> wait_req;
sc_signal<bool> wait_req_write;
sc_signal<sc_uint<2>> wait_req_sz;
sc_signal<sc_uint<BUS_ADDR_WIDTH>> wait_req_addr;
sc_signal<sc_uint<RISCV_ARCH>> wait_req_wdata;
sc_signal<bool> wait_resp;
} v, r;
|
GemmDriver |
sc_in<bool> clock;
sc_in <bool> reset;
sc_fifo_in<DATA> dout1;
sc_fifo_in<DATA> dout2;
sc_fifo_in<DATA> dout3;
sc_fifo_in<DATA> dout4;
sc_fifo_out<DATA> din1;
sc_fifo_out<DATA> din2;
sc_fifo_out<DATA> din3;
sc_fifo_out<DATA> din4;
bool sent;
bool retval;
//States
int states[9];
sc_signal<int> sourceS;
sc_signal<int> sinkS;
sc_in<int> inS;
sc_in<int> outS;
sc_in<int> w1S;
sc_in<int> w2S;
sc_in<int> w3S;
sc_in<int> w4S;
sc_in<int> schS;
sc_in<int> p1S;
sc_in<int> read_cycle_count;
sc_in<int> process_cycle_count;
sc_in<int> gemm_1_idle;
sc_in<int> gemm_2_idle;
sc_in<int> gemm_3_idle;
sc_in<int> gemm_4_idle;
sc_in<int> gemm_1_write;
sc_in<int> gemm_2_write;
sc_in<int> gemm_3_write;
sc_in<int> gemm_4_write;
sc_in<int> gemm_1;
sc_in<int> gemm_2;
sc_in<int> gemm_3;
sc_in<int> gemm_4;
sc_in<int> wstall_1;
sc_in<int> wstall_2;
sc_in<int> wstall_3;
sc_in<int> wstall_4;
sc_in<int> rmax;
sc_in<int> lmax;
int p_cycles= 0;
int waiting= 0;
int loading= 0;
int g1_idle= 0;
int g2_idle= 0;
int g3_idle= 0;
int g4_idle= 0;
int g1_write= 0;
int g2_write= 0;
int g3_write= 0;
int g4_write= 0;
int g1_gemm= 0;
int g2_gemm= 0;
int g3_gemm= 0;
int g4_gemm= 0;
int wstall1=0;
int wstall2=0;
int wstall3=0;
int wstall4=0;
int r_max=0;
int l_max=0;
void Source();
void Sink();
void Status();
void read_in();
void read_out();
SC_HAS_PROCESS(GemmDriver);
// Parameters for the DUT
GemmDriver(sc_module_name name_) :sc_module(name_) { // @suppress("Class members should be properly initialized")
SC_CTHREAD(Source, clock.pos());
reset_signal_is(reset,true);
SC_CTHREAD(Sink, clock.pos());
reset_signal_is(reset,true);
SC_CTHREAD(Status, clock.neg());
reset_signal_is(reset,true);
}
int inl0;
int inl1;
int inl2;
int inl3;
int in0[563840];
int in1[563840];
int in2[563840];
int in3[563840];
int out0[554800];
int out1[554800];
int out2[554800];
int out3[554800];
|
top)
//| {
//| sc_process_handle run_proc;
//|
//| SC_CTOR(top |
//| run_proc = sc_spawn(sc_bind(&run_phase,this),"run_phase");
//| |
CacheTop |
public:
sc_in<bool> i_clk; // CPU clock
sc_in<bool> i_nrst; // Reset: active LOW
// Control path:
sc_in<bool> i_req_ctrl_valid; // Control request from CPU Core is valid
sc_in<sc_uint<RISCV_ARCH>> i_req_ctrl_addr; // Control request address
sc_out<bool> o_req_ctrl_ready; // Control request from CPU Core is accepted
sc_out<bool> o_resp_ctrl_valid; // ICache response is valid and can be accepted
sc_out<sc_uint<RISCV_ARCH>> o_resp_ctrl_addr; // ICache response address
sc_out<sc_uint<64>> o_resp_ctrl_data; // ICache read data
sc_out<bool> o_resp_ctrl_load_fault; // Bus response ERRSLV or ERRDEC on read
sc_in<bool> i_resp_ctrl_ready; // CPU Core is ready to accept ICache response
// Data path:
sc_in<bool> i_req_data_valid; // Data path request from CPU Core is valid
sc_in<sc_uint<MemopType_Total>> i_req_data_type; // Data write memopy operation flag
sc_in<sc_uint<RISCV_ARCH>> i_req_data_addr; // Memory operation address
sc_in<sc_uint<64>> i_req_data_wdata; // Memory operation write value
sc_in<sc_uint<8>> i_req_data_wstrb; // 8-bytes aligned strob
sc_in<sc_uint<2>> i_req_data_size;
sc_out<bool> o_req_data_ready; // Memory operation request accepted by DCache
sc_out<bool> o_resp_data_valid; // DCache response is ready
sc_out<sc_uint<RISCV_ARCH>> o_resp_data_addr; // DCache response address
sc_out<sc_uint<64>> o_resp_data_data; // DCache response read data
sc_out<bool> o_resp_data_load_fault; // Bus response ERRSLV or ERRDEC on read
sc_out<bool> o_resp_data_store_fault; // Bus response ERRSLV or ERRDEC on write
sc_in<bool> i_resp_data_ready; // CPU Core is ready to accept DCache repsonse
// Memory interface:
sc_in<bool> i_req_mem_ready; // System Bus is ready to accept memory operation request
sc_out<bool> o_req_mem_path; // 1=ctrl; 0=data path
sc_out<bool> o_req_mem_valid; // AXI memory request is valid
sc_out<sc_uint<REQ_MEM_TYPE_BITS>> o_req_mem_type; // AXI memory request type
sc_out<sc_uint<3>> o_req_mem_size; // request size: 0=1 B;...; 7=128 B
sc_out<sc_uint<CFG_CPU_ADDR_BITS>> o_req_mem_addr; // AXI memory request address
sc_out<sc_uint<L1CACHE_BYTES_PER_LINE>> o_req_mem_strob;// Writing strob. 1 bit per Byte (uncached only)
sc_out<sc_biguint<L1CACHE_LINE_BITS>> o_req_mem_data; // Writing data
sc_in<bool> i_resp_mem_valid; // AXI response is valid
sc_in<bool> i_resp_mem_path; // 0=ctrl; 1=data path
sc_in<sc_biguint<L1CACHE_LINE_BITS>> i_resp_mem_data; // Read data
sc_in<bool> i_resp_mem_load_fault; // data load error
sc_in<bool> i_resp_mem_store_fault; // data store error
// PMP interface:
sc_in<bool> i_pmp_ena; // PMP is active in S or U modes or if L/MPRV bit is set in M-mode
sc_in<bool> i_pmp_we; // write enable into PMP
sc_in<sc_uint<CFG_PMP_TBL_WIDTH>> i_pmp_region; // selected PMP region
sc_in<sc_uint<RISCV_ARCH>> i_pmp_start_addr; // PMP region start address
sc_in<sc_uint<RISCV_ARCH>> i_pmp_end_addr; // PMP region end address (inclusive)
sc_in<sc_uint<CFG_PMP_FL_TOTAL>> i_pmp_flags; // {ena, lock, r, w, x}
// $D Snoop interface:
sc_in<bool> i_req_snoop_valid;
sc_in<sc_uint<SNOOP_REQ_TYPE_BITS>> i_req_snoop_type;
sc_out<bool> o_req_snoop_ready;
sc_in<sc_uint<CFG_CPU_ADDR_BITS>> i_req_snoop_addr;
sc_in<bool> i_resp_snoop_ready;
sc_out<bool> o_resp_snoop_valid;
sc_out<sc_biguint<L1CACHE_LINE_BITS>> o_resp_snoop_data;
sc_out<sc_uint<DTAG_FL_TOTAL>> o_resp_snoop_flags;
// Debug signals:
sc_in<bool> i_flushi_valid; // address to clear icache is valid
sc_in<sc_uint<RISCV_ARCH>> i_flushi_addr; // clear ICache address from debug interface
sc_in<bool> i_flushd_valid;
sc_in<sc_uint<RISCV_ARCH>> i_flushd_addr;
sc_out<bool> o_flushd_end;
void comb();
SC_HAS_PROCESS(CacheTop);
CacheTop(sc_module_name name,
bool async_reset,
bool coherence_ena);
virtual ~CacheTop();
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
private:
bool async_reset_;
bool coherence_ena_;
static const int DATA_PATH = 0;
static const int CTRL_PATH = 1;
static const int QUEUE_WIDTH = (CFG_CPU_ADDR_BITS // o_req_mem_addr
+ REQ_MEM_TYPE_BITS // o_req_mem_type
+ 3 // o_req_mem_size
+ 1 // i_resp_mem_path
);
struct CacheOutputType {
sc_signal<bool> req_mem_valid;
sc_signal<sc_uint<REQ_MEM_TYPE_BITS>> req_mem_type;
sc_signal<sc_uint<3>> req_mem_size;
sc_signal<sc_uint<CFG_CPU_ADDR_BITS>> req_mem_addr;
sc_signal<sc_uint<L1CACHE_BYTES_PER_LINE>> req_mem_strob;
sc_signal<sc_biguint<L1CACHE_LINE_BITS>> req_mem_wdata;
sc_signal<sc_uint<CFG_CPU_ADDR_BITS>> mpu_addr;
sc_signal<sc_uint<CFG_CPU_ADDR_BITS>> resp_addr;
|
RAM |
sc_in_clk CLK;
sc_in<bool> RESET_N;
sc_in<sc_uint<32>> ADR_I;
sc_in<sc_uint<32>> DAT_I;
sc_in<bool> VALID_I;
sc_in<bool> WE_I;
sc_in<sc_uint<2>> MEM_SIZE;
sc_out<sc_uint<32>> DAT_O;
//signals
sc_signal<sc_uint<4>> current_state;
sc_signal<sc_uint<4>> future_state;
std::unordered_map<int,int>* RAM_REGISTERS;
void init_mem(std::unordered_map<int,int>*);
void reponse();
void trace(sc_trace_file*);
SC_CTOR(RAM)
{
SC_METHOD(reponse);
sensitive << CLK.neg();
}
|
vip_spi_transmitter |
public:
sc_in<bool> i_nrst;
sc_in<bool> i_clk;
sc_in<bool> i_csn;
sc_in<bool> i_sclk;
sc_in<bool> i_mosi;
sc_out<bool> o_miso;
sc_out<bool> o_req_valid;
sc_out<bool> o_req_write;
sc_out<sc_uint<32>> o_req_addr;
sc_out<sc_uint<32>> o_req_wdata;
sc_in<bool> i_req_ready;
sc_in<bool> i_resp_valid;
sc_in<sc_uint<32>> i_resp_rdata;
sc_out<bool> o_resp_ready;
void comb();
void registers();
SC_HAS_PROCESS(vip_spi_transmitter);
vip_spi_transmitter(sc_module_name name,
bool async_reset,
int scaler);
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
private:
bool async_reset_;
int scaler_;
int scaler_max;
int scaler_mid;
static const uint8_t state_cmd = 0;
static const uint8_t state_addr = 1;
static const uint8_t state_data = 2;
struct vip_spi_transmitter_registers {
sc_signal<sc_uint<2>> state;
sc_signal<bool> sclk;
sc_signal<sc_uint<32>> rxshift;
sc_signal<sc_uint<32>> txshift;
sc_signal<sc_uint<4>> bitcnt;
sc_signal<sc_uint<3>> bytecnt;
sc_signal<bool> byterdy;
sc_signal<bool> req_valid;
sc_signal<bool> req_write;
sc_signal<sc_uint<32>> req_addr;
sc_signal<sc_uint<32>> req_wdata;
} v, r;
void vip_spi_transmitter_r_reset(vip_spi_transmitter_registers &iv) {
iv.state = state_cmd;
iv.sclk = 0;
iv.rxshift = ~0ull;
iv.txshift = ~0ull;
iv.bitcnt = 0;
iv.bytecnt = 0;
iv.byterdy = 0;
iv.req_valid = 0;
iv.req_write = 0;
iv.req_addr = 0;
iv.req_wdata = 0;
}
|
_sc_stream_stitching |
typedef typename hwcore::pipes::SC_DATA_STREAM_T_trait<1 * W>::interface_T din_T;
typedef typename hwcore::pipes::SC_DATA_STREAM_T_trait<1 * W>::interface_T dout_T;
sc_in<bool> clk, reset;
sc_fifo_in<din_T> din_buf;
sc_fifo_in<din_T> din;
sc_fifo_out<dout_T> dout;
sc_fifo_in<sc_uint<16> > ctrl_depth;
sc_fifo_in<sc_uint<16> > ctrl_buf_depth;
SC_CTOR(_sc_stream_stitching) {
SC_CTHREAD(thread, clk.pos());
reset_signal_is(reset, true);
}
void thread() {
din_T tmp_in;
while (true) {
sc_uint<16> depth = ctrl_depth.read();
sc_uint<16> buf_depth = ctrl_buf_depth.read();
sc_uint<16> ptr = 0;
bool last = false;
do {
hls_pipeline(1);
if (ptr < buf_depth) {
tmp_in = din_buf.read();
tmp_in.tlast = 0;
} else {
tmp_in = din.read();
last = (tmp_in.tlast == 1);
}
dout.write(tmp_in);
ptr = (ptr + 1 >= depth ? sc_uint<16>(0) : sc_uint<16>(ptr + 1));
} while (!last);
}
}
|
i2c |
public:
sc_out<bool> scl_en_o {"scl_en_o" |
Workgroup |
public:
sc_in<bool> i_cores_nrst; // System reset without DMI inteface
sc_in<bool> i_dmi_nrst; // Debug interface reset
sc_in<bool> i_clk; // CPU clock
sc_in<bool> i_trst;
sc_in<bool> i_tck;
sc_in<bool> i_tms;
sc_in<bool> i_tdi;
sc_out<bool> o_tdo;
sc_in<sc_uint<CFG_CPU_MAX>> i_msip;
sc_in<sc_uint<CFG_CPU_MAX>> i_mtip;
sc_in<sc_uint<CFG_CPU_MAX>> i_meip;
sc_in<sc_uint<CFG_CPU_MAX>> i_seip;
sc_in<sc_uint<64>> i_mtimer; // Read-only shadow value of memory-mapped mtimer register (see CLINT).
// coherent port:
sc_in<axi4_master_out_type> i_acpo;
sc_out<axi4_master_in_type> o_acpi;
// System bus port
sc_out<dev_config_type> o_xmst_cfg; // Workgroup master interface descriptor
sc_in<axi4_master_in_type> i_msti;
sc_out<axi4_master_out_type> o_msto;
// APB debug access:
sc_in<mapinfo_type> i_dmi_mapinfo; // DMI APB itnerface mapping information
sc_out<dev_config_type> o_dmi_cfg; // DMI device descriptor
sc_in<apb_in_type> i_dmi_apbi;
sc_out<apb_out_type> o_dmi_apbo;
sc_out<bool> o_dmreset; // reset everything except DMI debug interface
void comb();
SC_HAS_PROCESS(Workgroup);
Workgroup(sc_module_name name,
bool async_reset,
uint32_t cpu_num,
uint32_t l2cache_ena);
virtual ~Workgroup();
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
private:
bool async_reset_;
uint32_t cpu_num_;
uint32_t l2cache_ena_;
bool coherence_ena;
static const uint32_t ACP_SLOT_IDX = CFG_CPU_MAX;
axi4_l1_out_vector coreo;
axi4_l1_in_vector corei;
sc_signal<axi4_l2_in_type> l2i;
sc_signal<axi4_l2_out_type> l2o;
dport_in_vector wb_dport_i;
dport_out_vector wb_dport_o;
hart_irq_vector vec_irq;
hart_signal_vector vec_halted;
hart_signal_vector vec_available;
hart_signal_vector vec_flush_l2;
sc_signal<sc_uint<CFG_CPU_MAX>> wb_halted;
sc_signal<sc_uint<CFG_CPU_MAX>> wb_available;
sc_signal<sc_uint<CFG_LOG2_CPU_MAX>> wb_dmi_hartsel;
sc_signal<bool> w_dmi_haltreq;
sc_signal<bool> w_dmi_resumereq;
sc_signal<bool> w_dmi_resethaltreq;
sc_signal<bool> w_dmi_hartreset;
sc_signal<bool> w_dmi_dport_req_valid;
sc_signal<sc_uint<DPortReq_Total>> wb_dmi_dport_req_type;
sc_signal<sc_uint<RISCV_ARCH>> wb_dmi_dport_addr;
sc_signal<sc_uint<RISCV_ARCH>> wb_dmi_dport_wdata;
sc_signal<sc_uint<3>> wb_dmi_dport_size;
sc_signal<bool> w_ic_dport_req_ready;
sc_signal<bool> w_dmi_dport_resp_ready;
sc_signal<bool> w_ic_dport_resp_valid;
sc_signal<bool> w_ic_dport_resp_error;
sc_signal<sc_uint<RISCV_ARCH>> wb_ic_dport_rdata;
sc_signal<sc_biguint<(32 * CFG_PROGBUF_REG_TOTAL)>> wb_progbuf;
sc_signal<bool> w_flush_l2;
dmidebug *dmi0;
ic_dport *dport_ic0;
ic_axi4_to_l1 *acp_bridge;
RiverAmba *cpux[CFG_CPU_MAX];
DummyCpu *dumx[CFG_CPU_MAX];
L2Top *l2cache;
L2Dummy *l2dummy;
L2SerDes *l2serdes0;
|
zeroenc |
public:
sc_in<sc_biguint<iwidth>> i_value; // Input value to encode
sc_out<sc_uint<shiftwidth>> o_shift; // First non-zero bit
void gen0();
SC_HAS_PROCESS(zeroenc);
zeroenc(sc_module_name name);
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
private:
sc_signal<sc_uint<shiftwidth>> wb_muxind[(iwidth + 1)];
|
nand_gate |
public:
sc_in<bool> inp_a, inp_b;
sc_out<bool> out;
SC_HAS_PROCESS(nand_gate);
nand_gate(sc_module_name nm);
private:
void nand_main(void);
|
processing_engine_module |
// PORTS
sc_in<bool> clk;
sc_in<bool> reset;
sc_fifo_in<float> from_scheduler_weight;
sc_fifo_in<float> from_scheduler_input;
sc_fifo_in< sc_uint<34> > from_scheduler_instructions;
sc_fifo_out<float> to_scheduler;
// STATES
sc_uint<30> state_length;
sc_uint<4> state_activation_function;
// PROCESS
void process(void);
// UTIL
float sigmoid(float input);
float relu(float input);
float softmax(float input);
SC_CTOR(processing_engine_module)
{
state_length = 0;
state_activation_function = 0;
SC_CTHREAD(process, clk.pos());
reset_signal_is(reset,true);
}
|
IP_RAM |
sc_in_clk CLK;
sc_in<bool> RESET_N;
sc_in<sc_uint<32>> DAT_I;
sc_in<sc_uint<32>> ADR_I;
sc_in<bool> CYC_I; // when asserted indicates that a valid bus cycle in progress
sc_in<sc_uint<2>> SEL_I; // select which words on DAT_O are valid
sc_in<bool> STB_I;
sc_in<bool> WE_I;
sc_out<sc_uint<32>> DAT_O;
sc_out<bool> ACK_O; // when asserted indicates the termination of a bus cycle
sc_in<bool> ARBITER_SEL_I;
//signals
sc_signal<sc_uint<32>> ADR;
sc_signal<sc_uint<32>> RAM_I;
sc_signal<sc_uint<32>> RAM_O;
sc_signal<sc_uint<2>> MEM_SIZE;
sc_signal<bool> WE;
sc_signal<bool> RAM2WRAPPER_VALID;
sc_signal<bool> WRAPPER2RAM_VALID;
void init_mem(std::unordered_map<int,int>*);
void trace(sc_trace_file*);
RAM ram_inst;
wb_ram_sc wrapper_inst;
SC_CTOR(IP_RAM):
ram_inst("RAM"),
wrapper_inst("wb_ram_sc")
{
wrapper_inst.CLK(CLK);
wrapper_inst.RESET_N(RESET_N);
wrapper_inst.DAT_I(DAT_I);
wrapper_inst.ADR_I(ADR_I);
wrapper_inst.CYC_I(CYC_I);
wrapper_inst.SEL_I(SEL_I);
wrapper_inst.STB_I(STB_I);
wrapper_inst.WE_I(WE_I);
wrapper_inst.DAT_O(DAT_O);
wrapper_inst.ACK_O(ACK_O);
wrapper_inst.RAM_DTA_RDY_O(RAM2WRAPPER_VALID);
wrapper_inst.RAM_DT_I(RAM_O);
wrapper_inst.RAM_DT_O(RAM_I);
wrapper_inst.RAM_ADR_O(ADR);
wrapper_inst.RAM_WE_O(WE);
wrapper_inst.RAM_SEL_O(MEM_SIZE);
wrapper_inst.ARBITER_SEL_I(ARBITER_SEL_I);
ram_inst.CLK(CLK);
ram_inst.RESET_N(RESET_N);
ram_inst.ADR_I(ADR);
ram_inst.DAT_I(RAM_I);
ram_inst.VALID_I(RAM2WRAPPER_VALID);
ram_inst.WE_I(WE);
ram_inst.MEM_SIZE(MEM_SIZE);
ram_inst.DAT_O(RAM_O);
}
|
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