shailja
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fine-tuned-codegen-6B-Verilog

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fine-tuned-codegen-6B-Verilog

Commit History

Create README.md

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shailja commited on Aug 30, 2023

Create LICENCE

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shailja commited on Feb 10, 2023

Upload fine-tuned-codegen-6B-1gpu.tar.zst

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shailja commited on Nov 24, 2022

Upload fine-tuned-codegen-6B-1gpu.tar.zst

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shailja commited on Nov 16, 2022

Upload 3 files

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shailja commited on Nov 7, 2022

Upload CodeGenForCausalLM

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shailja commited on Sep 18, 2022

initial commit

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shailja commited on Sep 18, 2022