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Ticket Name: DRA756: How deal with DRA74x/TDA2x PCIe soft reset signal?
Query Text:
Part Number: DRA756 Other Parts Discussed in Thread: PCF8575 According to the guide in the following link, http://software-dl.ti.com/processor-sdk-linux/esd/docs/latest/linux/Foundational_Components_Kernel_Drivers.html?highlight=pcie#pcie-end-point There is no setting of the reset pin of PCIe (for EP nor RC). diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index eedd930..93d9f17 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -1084,7 +1084,7 @@
vdd-supply = <&smps7_reg>;
};
-&pcie1_rc {
+&pcie1_ep {
status = "okay";
}; How to deal with the PCIe software reset signal on EVM? just ignore it? How about the hardware connection to RC device?
Responses:
Hi, I can only tell about hardware details of PCIe SW reset. This signal assertion, similarly to few other features on EVM, is accomplished via an external GPIO IC. IC type: PCF8575 IC ref: U58 Connected to: I2C1 of DRA75x I2C address: 40h PCI_SW_RESETn is on pin: 14 (D hex) Hope some of these helps.
Note that this reset will not propagate if PCI_RESET_SEL is high, which is selected by SW5-8 set to OFF.
Thank you for your reply. I know where the PCIe-sw-reset connects on hardware, What I want to know is, how to link it with PCIe controller, especially in Linux. in reference design shown in http://software-dl.ti.com/processor-sdk-linux/esd/docs/latest/linux/Foundational_Components_Kernel_Drivers.html?highlight=pcie#pcie-end-point &pcie1_ep {
status = "ok";
}; No binding of the gpio to PCIe controller.
I don't know the history for that. I hope this will get answered soon in this thread. Perhaps this wasn't implemented in Linux because Reset is not a mandatory signal for PCIe devices. Regards, Stan