sample_embedding_folder2/0762301.txt

Ticket Name: TDA2: Understanding Best Suitable TDA2X processor for the Cascaded Design

Query Text:
Part Number: TDA2 Other Parts Discussed in Thread: AWR1243 Hello, I am trying to figure out the maximum possible 2D and 3D complex FFT size possible using TDA2x and TDA2px for our application. For the cascaded design that will hopefully be released in the first quarter of 2019 by TI, could you please tell me what is the exact part number of TDA2x that you have used? Based on the datasheet of TDA2X ADAS processors, from Pg 142, TDA2xxT is the best processor to use because it has the fastest DSP and EVE processing speed. Based on pg 6, TDA2SXx and TDA2SGx of TDA2Sxx subfamily is the best processor because it suits all the hardware requirements for supporting 4 AWR1243s together. Also, could you also tell me the max datarate that the videoports of TDA2x can handle? TDA2x has only 3 VIP ports present. Then how do you connect and transfer data from four AWR1243s to the three VIP ports? Could you please give a brief explanation to it? Thank you! Best Regards, Nishant

Responses:
Nishant, The part number we use in the board is x5777 which is the pre-production part for the TDA2x device. This supports the mazimum speed grade mentioned in the Datasheet. For the exact number of FFTs that can be performed, I would advice you to feed your system configuration in the Radar System planner to see if your required usecase would fit in the device. TDA has 3 VIP instances. For the number of ports available for capture please refer to Figure 9-2. VIP Environment of the TRM. Here you would see each VIP has a slice. We are connecting the AWR1243 to VIN 1A, 2A, 3A, 4A. The data rate we are supporting from the default FPGA image is 150 MHz 16 bits which is sufficient for 2400 Mbps (600 Mbps 4-lane AWR configuration). Thanks and Regards, Piyali

Thank you Piyali for your help with all my questons! Best Regards, Nishant