sample_embedding_folder2/0762106.txt

Ticket Name: RTOS/TDA2: SBL halt

Query Text:
Part Number: TDA2 Tool/software: TI-RTOS Hi Expert, I'm running PROCESSOR SDK VISION v03.04.00 rtos on tda2eg custom board. It's OK to work. However, when OSC1 Crystal(AC13/15) is removed, the following halt problem occurs. Could you please give me some advise? Thanks in advance.

Responses:
Hi, You should set the board to a reserved boot mode and load SBL using CCS. After that do a single step to see where exactly the failure is occurring. Regards, Rishabh

Hi, I'm try load using CCS run binaries, but no any print. CCS log is below: IcePick_D: GEL Output: Ipu RTOS is released from Wait-In-Reset. IcePick_D: GEL Output: Ipu SIMCOP is released from Wait-In-Reset. IcePick_D: GEL Output: IVAHD C66 is released from Wait-In-Reset. IcePick_D: GEL Output: IVAHD ICONT1 is released from Wait-In-Reset. IcePick_D: GEL Output: IVAHD ICONT2 is released from Wait-In-Reset. CS_DAP_DebugSS: GEL Output: --->>> CONFIGURE DEBUG DPLL settings to 1.9 GHZs <<<--- CS_DAP_DebugSS: GEL Output: > Setup DebugSS 1.9GHz in progress... CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS Trace export clock (TPIU) to 97MHz CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS PLL Clocking 1.9GHz CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS ATB Clocking 380MHz CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS Trace export clock (TPIU) to 97MHz CS_DAP_DebugSS: GEL Output: --->>> TURNING ON L3_INSTR and L3_3 clocks required for debug instrumention <<<<<<---- CS_DAP_DebugSS: GEL Output: ---<<< L3 instrumentation clocks are enabled >>>> --- CS_DAP_DebugSS: GEL Output: --->>> Mapping TIMER supsend sources to default cores <<<<<<---- CS_DAP_PC: GEL Output: Cortex-A15 1 is not in WIR mode so nothing to do. CortexA15_0: GEL Output: --->>> TDA2Ex Target Connect Sequence Begins ... <<<--- CortexA15_0: GEL Output: --->>> TDA2Ex PG2.0 GP device <<<--- CortexA15_0: GEL Output: --->>> The core is in non-SECURE state. <<<--- CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPPNOM in progress... <<<--- CortexA15_0: GEL Output: Cortex A15 DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: Cortex A15 DPLL is already locked, now unlocking... CortexA15_0: GEL Output: Cortex A15 DPLL OPP 0 is DONE! CortexA15_0: GEL Output: IVA DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: IVA DPLL OPP 0 is DONE! CortexA15_0: GEL Output: PER DPLL OPP 0 clock config in progress... CortexA15_0: GEL Output: PER DPLL already locked, now unlocking CortexA15_0: GEL Output: PER DPLL OPP 0 is DONE! CortexA15_0: GEL Output: CORE DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: CORE DPLL OPP already locked, now unlocking.... CortexA15_0: GEL Output: CORE DPLL OPP 0 is DONE! CortexA15_0: GEL Output: ABE DPLL OPP 0 clock config in progress... CortexA15_0: GEL Output: ABE DPLL OPP 0 is DONE! CortexA15_0: GEL Output: GMAC DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: GMAC DPLL OPP 0 is DONE! CortexA15_0: GEL Output: GPU DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: GPU DPLL OPP 0 is DONE! CortexA15_0: GEL Output: DSP DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: DSP DPLL already locked, now unlocking.... CortexA15_0: GEL Output: DSP DPLL OPP 0 is DONE! CortexA15_0: GEL Output: PCIE_REF DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: PCIE_REF DPLL OPP 0 is DONE! CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPP 0 is DONE! <<<--- CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules in progress... <<<--- CortexA15_0: GEL Output: module_base: 0x4A009700 CortexA15_0: GEL Output: module_offset: 0x000000C8 CortexA15_0: GEL Output: TIMEOUT CortexA15_0: GEL Output: module_base: 0x4A009700 CortexA15_0: GEL Output: module_offset: 0x000000D0 CortexA15_0: GEL Output: TIMEOUT CortexA15_0: GEL Output: module_base: 0x4A009700 CortexA15_0: GEL Output: module_offset: 0x000000D8 CortexA15_0: GEL Output: TIMEOUT CortexA15_0: GEL Output: module_base: 0x4A009700 CortexA15_0: GEL Output: module_offset: 0x00000130 CortexA15_0: GEL Output: TIMEOUT CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules is DONE! <<<--- CortexA15_0: GEL Output: --->>> DDR3 Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DDR DPLL clock config for 666MHz is in progress... CortexA15_0: GEL Output: DDR DPLL already locked, now unlocking.... CortexA15_0: GEL Output: DDR DPLL clock config for 666MHz is in DONE! CortexA15_0: GEL Output: Launch full leveling CortexA15_0: GEL Output: Updating slave ratios in PHY_STATUSx registers CortexA15_0: GEL Output: as per HW leveling output CortexA15_0: GEL Output: HW leveling is now disabled. Using slave ratios from CortexA15_0: GEL Output: PHY_STATUSx registers CortexA15_0: GEL Output: --->>> DDR3 Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> TDA2Ex Begin All Pad Configuration for Vision Platform <<<--- CortexA15_0: GEL Output: --->>> TDA2Ex Begin All Pad Configuration for RGMII usage on EVM Platform <<<--- CortexA15_0: GEL Output: --->>> TDA2Ex Begin GMAC_SW MDIO Pad Configuration <<<--- CortexA15_0: GEL Output: --->>> TDA2Ex End GMAC_SW MDIO Pad Configuration <<<--- CortexA15_0: GEL Output: --->>> TDA2Ex Begin GMAC_SW RGMII0 Pad Configuration <<<--- CortexA15_0: GEL Output: --->>> TDA2Ex End GMAC_SW RGMII0 Pad Configuration <<<--- CortexA15_0: GEL Output: --->>> TDA2Ex Begin GMAC_SW RGMII1 Pad Configuration <<<--- CortexA15_0: GEL Output: --->>> TDA2Ex End GMAC_SW RGMII1 Pad Configuration <<<--- CortexA15_0: GEL Output: --->>> TDA2Ex End All Pad Configuration for RGMII usage on EVM Platform <<<--- CortexA15_0: GEL Output: --->>> TDA2Ex End All Pad Configuration for Vision Platform <<<--- CortexA15_0: GEL Output: --->>> TDA2Ex Target Connect Sequence DONE !!!!! <<<--- CortexA15_0: GEL Output: --->>> IPU1SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: --->>> IPU1SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> IPU2SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: --->>> IPU2SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> DSP1SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DEBUG: Clock is active ... CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ... CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful! CortexA15_0: GEL Output: --->>> DSP1SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> IVAHD Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DEBUG: Clock is active ... CortexA15_0: GEL Output: --->>> IVAHD Initialization is DONE! ... <<<--- CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in progress ... <<<--- CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in complete ... <<<--- Thanks in advance.

Hi, You need to remove gel files from target configuration before doing this. Regards, Rishabh

Hi, I haven't heard back from you, I'm assuming you were able to resolve your issue. If not, just post a reply below (or create a new thread if the thread has locked due to time-out). Regards, Rishabh