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| Ticket Name: TDA2: Conflict in power state and its status register | |
| Query Text: | |
| Part Number: TDA2 Hi Sir, As shown in the screen shot, PM_DSS_PWRSTCTRL DSS module power state is in off state but its status register showing it is in on state. Could you please explain why it is happening? Regards, Sagar | |
| Responses: | |
| Hi Sagar, PM_DSS_PWRSTST is showing the reset values. Are you facing any issue? Regards, Rishabh | |
| Hi Rishabh, Due to unused cores are in active state the power consumption is more beyond its limit. So need to verify whether these cores are in ON state or in OFF state. Regards, Sagar | |
| Hi Sagar, PM_DSS_PWRSTCTRL - "This register controls the DSS power state to reach upon a domain sleep transition". So it is the state expected to be reached on domain sleep transition. It is more of configuration/control register, what state to be when domain sleep transition happens whereas PM_DSS_PWRSTST - "This register provides a status on the current DSS power domain state. [warm reset insensitive]" . This provides the current state. So it means the domain is not gone to sleep state and it is ON | |
| Hi Sagar, DSS is not a CPU, you should look at unused CPUs. How are you making sure that unused CPUs are in low power state/turned off? What is the software that you are using? Regards, Rishabh | |
| Hi Rishabh, I am checking PM_xxx_PWRSTCTRL register[1:0] POWERSTATE bits to confirm whether it is in ON or OFF state. I am using TI SBL and debugging using Lauterbach. Regards, Sagar | |
| Hi Sagar, Did you build SBL for prod mode? As far as DSS is concerned, the module is off here as you can see in PWRSTCTRL register. Regards, Rishabh | |
| Hi Rishabh, No, it is not build for prod mode. Yes, it is in off state as per PWRSTCTRL, but status register showing it is in active state. PM_xxx_PWRSTST[1:0] POWERSTATEST . Status register should be update with OFF state. Regards, Sagar | |
| Hi Sagar, You need to build SBL for prod mode and then try. In dev mode SBL will enable all cores and power will be high. Regards, Rishabh | |
| Hi Rishabh, Is PWRSTCTRL register is enough to put core in off state? Regards, Sagar | |
| Hi, One reason not transition to OFF can be clocks still running. PD DSS encomapasses BB2D, DSS, HDMI, and HDMI_PHY. All these must be disabled from MODULEMODE and functional clocks stopped prior to issue PD collapse. Regards, Stan | |
| Hi Sagar, It's not only about PWRSTCTRL register. I strong recommend that you run using SBL as suggested first. Regards, Rishabh | |
| Hi Sagar, Did you see any different power numbers with TI SBL? Regards, Rishabh | |
| Hi, I haven't heard back from you, I'm assuming you were able to resolve your issue. If not, just post a reply below (or create a new thread if the thread has locked due to time-out). Regards, Rishabh | |