sample_embedding_folder2/0733955.txt

Ticket Name: TDA2: What is the DDR3L RAM max size supported using 16bits data bus width at each EMIF interface?

Query Text:
Part Number: TDA2 What is the DDR3L RAM max size supported using 16bits data bus width at each EMIF interface? Reference to the 'TDA2X Vision EVM Kit', if I change the RAM to 512MB (MT41K256M16TW-107) at each EMIF interface using only 16bits data bus width, can 16bits data bus able to support full 512MB RAM speed? Do I need to modify any software configuration setting from 'Linux and RTOS Processor SDK for Vision' to have it works upon boot up?

Responses:
Hi, I have forwarded your question to DDR expert. For VisionSDK changes you can look at chapter "6 Memory map of the application" in VisionSDK_Linux_DevelopmentGuide.pdf and VisionSDK_UserGuide_MemoryMap.pdf in docs folder of VisionSDK and also this Application Note: www.ti.com/.../spraca1.pdf Regards, Yordan

If you use 2 x 8Gb (8-bit width) DDR3L memories on each EMIF, you would have 4GB total memory. Note that only the MPU can access greater than 2GB DDR memory. The data bus width does not impact the DRAM frequency.