sample_embedding_folder2/0728362.txt

Ticket Name: Compiler/TDA2: EVE/KernelC :- Optimization techniques

Query Text:
Part Number: TDA2 Tool/software: TI C/C++ Compiler Hello There, What are the EVE and/or kernel C optimization techniques ?? Do we have any document for the same?? Regards, Kajal

Responses:
Hi Kajal, You can refer some examples in EVE software library released by TI to get some idea. Also please refer the TRM for EVE architecture, instruction set to correlate the software examples with the hardware architecture. Regards, Anshu

Hello Anshu, For now we don't have the TRM for EVE, once we get that we will go through it. But in meanwhile can you please tell us how to reduce the clock cycles in terms of cache & hardware memory utilization. In case of kernel C programming, we have optimized using 16 SIMD width. Do we have any further scope for optimization in Kernel C programming?? Regards, Kajal

Hi Kajal, EVE doesn't have data cache so there is nothing in terms of cache which can improve performance. Once you have optimized kernels ready then next step would be to set up DMA/ VCOP pipeline in such a way that you can find the data movement via DMA behind VCOP compute. You can refer app\morphology applet to see how it is done. Regarding kernel C optimization I would request you to go though EVE's programmers guide. To get access to this document please contact your local TI contact person. Regards, Anshu

Hi Kajal, We haven't heard back from you on this thread. Were you able to make progress? If yes please close this thread. Regards, Anshu