sample_embedding_folder2/0666398.txt

Ticket Name: RTOS/TDA3XEVM: C66x CPU clock in the platform

Query Text:
Part Number: TDA3XEVM Other Parts Discussed in Thread: SYSBIOS, TDA2 Tool/software: TI-RTOS Hello, I have imported the example project "benchmark_TDA3x_C66xx" into the CCS 7.4 and selected the platform of TDA3EVM. This platform is taken from SYS/BIOS 6.53.1.03. I am wondering, why the CPU clock is set to 600 MHz. The C66x of the TDA3 is specified to 500 MHz. What is wrong here? By the way, the following includes in the benchloop.c file must be changed from /* POSIX module Headers */ #include <ti/sysbios/posix/semaphore.h> #include <ti/sysbios/posix/pthread.h> in to #include <ti/posix/ccs/semaphore.h> #include <ti/posix/ccs/pthread.h> Best regards, Milan

Responses:
Hi Milan, I have forwarded your question to an expert for comment. Regards, Yordan

Hi Milan, This comes from a default definition from bios_6_XX_XX_XX\packages\ti\platforms\evmTDA3XX\package\ti_platforms_evmTDA3XX.java po.addFld("DSP", (Proto)om.findStrict("xdc.platform.IExeContext.Cpu", "ti.platforms.evmTDA3XX"), Global.newObject("id", "0", "clockRate", 600.0, "catalogName", "ti.catalog.c6000", "deviceName", "TDA3XX", "revision", "1.0"), "rh"); You are free to modify this in the project specific CFG file by setting: var BIOS = xdc.useModule('ti.sysbios.BIOS'); BIOS.cpuFreq.hi = 0; BIOS.cpuFreq.lo = 500000000; This will take effect for calculating the DSP software frequency. BTW, note niether of these settings actually dial up the PLL. I am not aware of the project benchmark_TDA3x_C66xx you mention. Can you please highlight where you have got this project from? Thanks and Regards, Piyali

Hi Piyali, thank you for your answer. I think the 600 MHz entry in the platform is an copy and paste error from TDA2 clocks. The project "benchmark_TDA3x_C66xx" comes from the TI Resource Explorer: I know, it is possible to set the clocks and memory settings with the SYS/BIOS cfg script. Is it possible to compile the software without the default platform or with a simple linker file? The separate platform handling makes the workflow too complicated. Best regards, Milan

Hi Milan, Thanks for pointing out the source. Since this is a BIOS based project, the first thing it will try to run is the XDC configuro step which looks for a platform. You can additionally add your own linker files but a base linker file will be created by this configuro step from the platform. It would help us, if you could kindly elaborate how you intend to use this project. We can check if there are any alternatives based on your feedback. Regarding the earlier comment regarding posix headers, you are right. It seems the example include paths correspond to older BIOS releases. I will inform our BIOS team to update this. Thanks and Regards, Piyali

Hi Piyali, I have chosen this project, because I want optimize an algorithm for the C66x with time measuring possibility. By this way I recognized that the CPU clock was set wrong in the platform, so that the time measurement can not be correct. The DSP runs with 500 MHz. Additional the CPU clock is also set wrong in the SYS/BIOS config. This is why I ask for to bypass the platform completely and to disable the XDC configuro. I would like to handle this configurations in the SYS/BIOS config and additionally in the linker file. In case of multicore processors the best way for clear configuration (CPU-Clock, memory, sections,...) would be in a single file. Is it possible? Best regards, Milan

Hi Milan, If you are looking only for measuring the time for an algorithm on the DSP and do not really have any BIOS dependency, you can also use a standalone non RTSC based CCS project. For profiling you can use the TSC timers in the C66x which run a the C66x frequency. I am copying the assembly code to read the timers for quick reference: .global _CSL_tscEnable .global CSL_tscEnable _CSL_tscEnable: BNOP B3, 4 ; MVC A4, TSCL ; Initiate CPU Timer by writing to TSCL .global _CSL_tscRead .global CSL_tscRead .sect ".text:cslsys_section:tsc" _CSL_tscRead: BNOP B3, 2 ; Branch Return Pointer MVC TSCL, B0 ; Read TSCL MVC TSCH, B1 ; Read TSCH || MV B0, A4 MV B1, A5 extern void CSL_tscEnable(void); extern CSL_Uint64 CSL_tscRead (void); Thanks and Regards, Piyali