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///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2005 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Source Synchronous Output Serializer
// /___/ /\ Filename : OSERDESE1.v
// \ \ / \ Timestamp : Tue Sep 16 15:30:44 PDT 2008
// \___\/\___\
//
// Revision:
// 09/16/08 - Initial version.
// 12/05/08 - IR 495397.
// 01/13/09 - IR 503429.
// 01/15/09 - IR 503783 CLKPERF is not inverted for OFB/ofb_out.
// 02/06/09 - CR 507373 Removed IOCLKGLITCH and CLKB
// 02/26/09 - CR 510489 fixed SHIFTIN2_in
// 03/16/09 - CR 512140 and 512139 -- sdf load errors
// 01/27/10 - CR 546419 Updated specify block
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 09/04/12 - 676501 CLK -> OFB specify path missing
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module OSERDESE1 (OCBEXTEND, OFB, OQ, SHIFTOUT1, SHIFTOUT2, TFB, TQ,
CLK, CLKDIV, CLKPERF, CLKPERFDELAY, D1, D2, D3, D4, D5, D6, OCE, ODV, RST, SHIFTIN1, SHIFTIN2, T1, T2, T3, T4, TCE, WC);
parameter DATA_RATE_OQ = "DDR";
parameter DATA_RATE_TQ = "DDR";
parameter integer DATA_WIDTH = 4;
parameter integer DDR3_DATA = 1;
parameter [0:0] INIT_OQ = 1'b0;
parameter [0:0] INIT_TQ = 1'b0;
parameter INTERFACE_TYPE = "DEFAULT";
parameter integer ODELAY_USED = 0;
parameter SERDES_MODE = "MASTER";
parameter [0:0] SRVAL_OQ = 1'b0;
parameter [0:0] SRVAL_TQ = 1'b0;
parameter integer TRISTATE_WIDTH = 4;
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
//-------------------------------------------------------------
// Outputs:
//-------------------------------------------------------------
// OQ: Data output
// TQ: Output of tristate mux
// SHIFTOUT1: Carry out data 1 for slave
// SHIFTOUT2: Carry out data 2 for slave
// OFB: O Feedback output
//
//-------------------------------------------------------------
// Inputs:
//-------------------------------------------------------------
//
// Inputs:
// CLK: High speed clock from DCM
// CLKB: Inverted High speed clock from DCM
// CLKDIV: Low speed divided clock from DCM
// CLKPERF: Performance Path clock
// CLKPERFDELAY: delayed Performance Path clock
// D1, D2, D3, D4, D5, D6 : Data inputs
// OCE: Clock enable for output data flops
// ODV: ODELAY value > 140 degrees
// RST: Reset control
// T1, T2, T3, T4: tristate inputs
// SHIFTIN1: Carry in data 1 for master from slave
// SHIFTIN2: Carry in data 2 for master from slave
// TCE: Tristate clock enable
// WC: Write command given by memory controller
output OCBEXTEND;
output OFB;
output OQ;
output SHIFTOUT1;
output SHIFTOUT2;
output TFB;
output TQ;
input CLK;
input CLKDIV;
input CLKPERF;
input CLKPERFDELAY;
input D1;
input D2;
input D3;
input D4;
input D5;
input D6;
input OCE;
input ODV;
input RST;
input SHIFTIN1;
input SHIFTIN2;
input T1;
input T2;
input T3;
input T4;
input TCE;
input WC;
//
wire SERDES, DDR_CLK_EDGE;
wire [5:0] SRTYPE;
wire WC_DELAY;
wire [4:0] SELFHEAL;
wire load;
wire qmux1, qmux, tmux1, tmux2;
wire data1, data2, triin1, triin2;
wire d2rnk2;
wire CLKD;
wire CLKDIVD;
wire iodelay_state;
// attribute
reg data_rate_int;
reg [3:0] data_width_int;
reg [1:0] tristate_width_int;
reg data_rate_oq_int;
reg [1:0] data_rate_tq_int;
reg ddr3_data_int;
reg interface_type_int;
reg odelay_used_int;
reg serdes_mode_int;
// Output signals
wire ioclkglitch_out, ocbextend_out, ofb_out, oq_out, tq_out, shiftout1_out, shiftout2_out;
// Other signals
tri0 GSR = glbl.GSR;
reg notifier;
wire CLK_in;
wire CLKDIV_in;
wire CLKPERF_in;
wire CLKPERFDELAY_in;
wire D1_in;
wire D2_in;
wire D3_in;
wire D4_in;
wire D5_in;
wire D6_in;
wire OCE_in;
wire ODV_in;
wire RST_in;
wire SHIFTIN1_in;
wire SHIFTIN2_in;
wire T1_in;
wire T2_in;
wire T3_in;
wire T4_in;
wire TCE_in;
wire WC_in;
`ifndef XIL_TIMING
assign CLK_in = CLK;
assign CLKDIV_in = CLKDIV;
assign D1_in = D1;
assign D2_in = D2;
assign D3_in = D3;
assign D4_in = D4;
assign D5_in = D5;
assign D6_in = D6;
assign OCE_in = OCE;
assign T1_in = T1;
assign T2_in = T2;
assign T3_in = T3;
assign T4_in = T4;
assign TCE_in = TCE;
assign WC_in = WC;
`endif // `ifndef XIL_TIMING
assign CLKPERF_in = CLKPERF;
// assign CLKPERFDELAY_in = CLKPERFDELAY;
// IR 495397 & IR 499954
// assign CLKPERFDELAY_in = (CLKPERFDELAY === 1'bx)? 1'b0 : CLKPERFDELAY;
generate
case (ODELAY_USED)
0: assign CLKPERFDELAY_in = CLKPERF;
1: assign CLKPERFDELAY_in = (CLKPERFDELAY === 1'bx)? 1'b0 : CLKPERFDELAY;
endcase
endgenerate
assign SHIFTIN1_in = SHIFTIN1;
assign SHIFTIN2_in = SHIFTIN2;
assign ODV_in = ODV;
assign RST_in = RST;
buf b_ocbextend (OCBEXTEND, ocbextend_out);
buf b_ofb (OFB, ofb_out);
buf b_oq (OQ, oq_out);
buf b_shiftout1 (SHIFTOUT1, shiftout1_out);
buf b_shiftout2 (SHIFTOUT2, shiftout2_out);
buf b_tfb (TFB, tfb_out);
buf b_tq (TQ, tq_out);
initial begin
//-------------------------------------------------
//----- DATA_RATE_OQ check
//-------------------------------------------------
case (DATA_RATE_OQ)
"SDR" : data_rate_oq_int <= 1'b1;
"DDR" : data_rate_oq_int <= 1'b0;
default : begin
$display("Attribute Syntax Error : The attribute DATA_RATE_OQ on OSERDESE1 instance %m is set to %s. Legal values for this attribute are SDR or DDR", DATA_RATE_OQ);
$finish;
end
endcase // case(DATA_RATE_OQ)
//-------------------------------------------------
//----- DATA_RATE_TQ check
//-------------------------------------------------
case (DATA_RATE_TQ)
"BUF" : data_rate_tq_int <= 2'b00;
"SDR" : data_rate_tq_int <= 2'b01;
"DDR" : data_rate_tq_int <= 2'b10;
default : begin
$display("Attribute Syntax Error : The attribute DATA_RATE_TQ on OSERDESE1 instance %m is set to %s. Legal values for this attribute are BUF, SDR or DDR", DATA_RATE_TQ);
$finish;
end
endcase // case(DATA_RATE_TQ)
//-------------------------------------------------
//----- DATA_WIDTH check
//-------------------------------------------------
case (DATA_WIDTH)
2, 3, 4, 5, 6, 7, 8, 10 : data_width_int = DATA_WIDTH;
default : begin
$display("Attribute Syntax Error : The attribute DATA_WIDTH on OSERDESE1 instance %m is set to %d. Legal values for this attribute are 2, 3, 4, 5, 6, 7, 8, or 10", DATA_WIDTH);
$finish;
end
endcase // case(DATA_WIDTH)
//-------------------------------------------------
//----- DDR3_DATA check
//-------------------------------------------------
case (DDR3_DATA)
0 : ddr3_data_int <= 1'b0;
1 : ddr3_data_int <= 1'b1;
default : begin
$display("Attribute Syntax Error : The attribute DDR3_DATA on OSERDESE1 instance %m is set to %d. Legal values for this attribute are 0 or 1", DDR3_DATA);
$finish;
end
endcase // case(DDR3_DATA)
//-------------------------------------------------
//----- INTERFACE_TYPE check
//-------------------------------------------------
case (INTERFACE_TYPE)
"DEFAULT" : interface_type_int <= 1'b0;
"MEMORY_DDR3" : interface_type_int <= 1'b1;
default : begin
$display("Attribute Syntax Error : The attribute INTERFACE_TYPE on OSERDESE1 instance %m is set to %s. Legal values for this attribute are DEFAULT, or MEMORY_DDR3", INTERFACE_TYPE);
$finish;
end
endcase // INTERFACE_TYPE
//-------------------------------------------------
//----- ODELAY_USED check
//-------------------------------------------------
case (ODELAY_USED)
// "FALSE" : odelay_used_int <= 1'b0;
// "TRUE" : odelay_used_int <= 1'b1;
0 : odelay_used_int <= 1'b0;
1 : odelay_used_int <= 1'b1;
default : begin
$display("Attribute Syntax Error : The attribute ODELAY_USED on OSERDESE1 instance %m is set to %s. Legal values for this attribute are FALSE or TRUE", ODELAY_USED);
$finish;
end
endcase // case(ODELAY_USED)
//-------------------------------------------------
//----- SERDES_MODE check
//-------------------------------------------------
case (SERDES_MODE)
"MASTER" : serdes_mode_int <= 1'b0;
"SLAVE" : serdes_mode_int <= 1'b1;
default : begin
$display("Attribute Syntax Error : The attribute SERDES_MODE on OSERDESE1 instance %m is set to %s. Legal values for this attribute are MASTER or SLAVE", SERDES_MODE);
$finish;
end
endcase // case(SERDES_MODE)
//-------------------------------------------------
//----- TRISTATE_WIDTH check
//-------------------------------------------------
case (TRISTATE_WIDTH)
1 : tristate_width_int <= 2'b00;
2 : tristate_width_int <= 2'b01;
4 : tristate_width_int <= 2'b10;
default : begin
$display("Attribute Syntax Error : The attribute TRISTATE_WIDTH on OSERDESE1 instance %m is set to %d. Legal values for this attribute are 1, 2 or 4", TRISTATE_WIDTH);
$finish;
end
endcase // case(TRISTATE_WIDTH)
//-------------------------------------------------
end // initial begin
//-------------------------------------------------
assign SERDES = 1'b1;
assign SRTYPE = 6'b111111;
assign DDR_CLK_EDGE = 1'b1;
assign WC_DELAY = 1'b0;
assign SELFHEAL = 5'b00000;
assign #0 CLKD = CLK;
assign #0 CLKDIVD = CLKDIV;
assign #10 ofb_out = (ODELAY_USED == 1)? CLKPERF : oq_out;
assign #10 tfb_out = iodelay_state;
/////////////////////////////////////////////////////////
//
// Delay assignments
//
/////////////////////////////////////////////////////////
// Data output delays
defparam dfront.FFD = 1; // clock to out delay for flip flops
// driven by clk
defparam datao.FFD = 1; // clock to out delay for flip flops
// driven by clk
defparam dfront.FFCD = 1; // clock to out delay for flip flops
// driven by clkdiv
defparam dfront.MXD = 1; // mux delay
defparam dfront.MXR1 = 1; // mux before 2nd rank of flops
// Programmable load generator
defparam dfront.ldgen.ffdcnt = 1;
defparam dfront.ldgen.mxdcnt = 1;
defparam dfront.ldgen.FFRST = 145; // clock to out delay for flop in PLSG
// Tristate output delays
defparam tfront.ffd = 1; // clock to out delay for flip flops
defparam tfront.mxd = 1; // mux delay
defparam trio.ffd = 1; // clock to out delay for flip flops
defparam trio.mxd = 1; // mux delay
//------------------------------------------------------------------
// Instantiate output data section
//------------------------------------------------------------------
rank12d_oserdese1_vlog dfront (.D1(D1_in), .D2(D2_in), .D3(D3_in), .D4(D4_in), .D5(D5_in), .D6(D6_in),
.d2rnk2(d2rnk2),
.SHIFTIN1(SHIFTIN1_in), .SHIFTIN2(SHIFTIN2_in),
.C(CLK_in), .CLKDIV(CLKDIV_in), .SR(RST_in), .OCE(OCE_in),
.data1(data1), .data2(data2), .SHIFTOUT1(shiftout1_out), .SHIFTOUT2(shiftout2_out),
.DATA_RATE_OQ(data_rate_oq_int), .DATA_WIDTH(data_width_int),
.SERDES_MODE(serdes_mode_int), .load(load),
.IOCLK_GLITCH(ioclkglitch_out),
.INIT_OQ(INIT_OQ), .SRVAL_OQ(SRVAL_OQ));
trif_oserdese1_vlog tfront (.T1(T1_in), .T2(T2_in), .T3(T3_in), .T4(T4_in), .load(load),
.C(CLK_in), .CLKDIV(CLKDIV_in), .SR(RST_in), .TCE(TCE_in),
.DATA_RATE_TQ(data_rate_tq_int), .TRISTATE_WIDTH(tristate_width_int),
.INIT_TQ(INIT_TQ), .SRVAL_TQ(SRVAL_TQ),
.data1(triin1), .data2(triin2));
txbuffer_oserdese1_vlog DDR3FIFO (.iodelay_state(iodelay_state), .qmux1(qmux1), .qmux2(qmux2), .tmux1(tmux1), .tmux2(tmux2),
.d1(data1), .d2(data2), .t1(triin1), .t2(triin2), .trif(tq_out),
.WC(WC_in), .ODV(ODV_in), .extra(ocbextend_out),
.clk(CLK_in), .clkdiv(CLKDIV_in), .bufo(CLKPERFDELAY_in), .bufop(CLKPERF_in), .rst(RST_in),
.ODELAY_USED(odelay_used_int), .DDR3_DATA(ddr3_data_int),
.DDR3_MODE(interface_type_int));
dout_oserdese1_vlog datao (.data1(qmux1), .data2(qmux2),
.CLK(CLK_in), .BUFO(CLKPERFDELAY_in), .SR(RST_in), .OCE(OCE_in),
.OQ(oq_out), .d2rnk2(d2rnk2),
.DATA_RATE_OQ(data_rate_oq_int),
.INIT_OQ(INIT_OQ), .SRVAL_OQ(SRVAL_OQ),
.DDR3_MODE(interface_type_int));
tout_oserdese1_vlog trio (.data1(tmux1), .data2(tmux2),
.CLK(CLK_in), .BUFO(CLKPERFDELAY_in), .SR(RST_in), .TCE(TCE_in),
.DATA_RATE_TQ(data_rate_tq_int), .TRISTATE_WIDTH(tristate_width_int),
.INIT_TQ(INIT_TQ), .SRVAL_TQ(SRVAL_TQ),
.TQ(tq_out), .DDR3_MODE(interface_type_int));
`ifndef XIL_TIMING
specify
( CLK => OFB) = (100, 100);
( CLK => OQ) = (100, 100);
( CLK => TQ) = (100, 100);
( CLKPERF => OQ) = (100, 100);
( CLKPERF => TQ) = (100, 100);
( CLKPERFDELAY => OQ) = (100, 100);
( CLKPERFDELAY => TQ) = (100, 100);
( T1 => TQ) = (0, 0);
specparam PATHPULSE$ = 0;
endspecify
`endif // `ifndef XIL_TIMING
`ifdef XIL_TIMING
//*** Timing Checks Start here
specify
( CLK => OFB) = (100:100:100, 100:100:100);
( CLK => OQ) = (100:100:100, 100:100:100);
( CLK => TQ) = (100:100:100, 100:100:100);
( CLKPERF => OQ) = (100:100:100, 100:100:100);
( CLKPERF => TQ) = (100:100:100, 100:100:100);
( CLKPERFDELAY => OQ) = (100:100:100, 100:100:100);
( CLKPERFDELAY => TQ) = (100:100:100, 100:100:100);
( T1 => TQ) = (0:0:0, 0:0:0);
$setuphold (posedge CLK, negedge OCE, 0:0:0, 0:0:0, notifier,,, CLK_in, OCE_in);
$setuphold (posedge CLK, negedge T1, 0:0:0, 0:0:0, notifier,,, CLK_in, T1_in);
$setuphold (posedge CLK, negedge TCE, 0:0:0, 0:0:0, notifier,,, CLK_in, TCE_in);
$setuphold (posedge CLK, posedge OCE, 0:0:0, 0:0:0, notifier,,, CLK_in, OCE_in);
$setuphold (posedge CLK, posedge T1, 0:0:0, 0:0:0, notifier,,, CLK_in, T1_in);
$setuphold (posedge CLK, posedge TCE, 0:0:0, 0:0:0, notifier,,, CLK_in, TCE_in);
$setuphold (posedge CLKDIV, negedge D1, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, D1_in);
$setuphold (posedge CLKDIV, negedge D2, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, D2_in);
$setuphold (posedge CLKDIV, negedge D3, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, D3_in);
$setuphold (posedge CLKDIV, negedge D4, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, D4_in);
$setuphold (posedge CLKDIV, negedge D5, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, D5_in);
$setuphold (posedge CLKDIV, negedge D6, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, D6_in);
$setuphold (posedge CLKDIV, negedge RST, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, RST_in);
$setuphold (posedge CLKDIV, negedge T1, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, T1_in);
$setuphold (posedge CLKDIV, negedge T2, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, T2_in);
$setuphold (posedge CLKDIV, negedge T3, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, T3_in);
$setuphold (posedge CLKDIV, negedge T4, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, T4_in);
$setuphold (posedge CLKDIV, negedge WC, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, WC_in);
$setuphold (posedge CLKDIV, posedge D1, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, D1_in);
$setuphold (posedge CLKDIV, posedge D2, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, D2_in);
$setuphold (posedge CLKDIV, posedge D3, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, D3_in);
$setuphold (posedge CLKDIV, posedge D4, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, D4_in);
$setuphold (posedge CLKDIV, posedge D5, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, D5_in);
$setuphold (posedge CLKDIV, posedge D6, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, D6_in);
$setuphold (posedge CLKDIV, posedge RST, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, RST_in);
$setuphold (posedge CLKDIV, posedge T1, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, T1_in);
$setuphold (posedge CLKDIV, posedge T2, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, T2_in);
$setuphold (posedge CLKDIV, posedge T3, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, T3_in);
$setuphold (posedge CLKDIV, posedge T4, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, T4_in);
$setuphold (posedge CLKDIV, posedge WC, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, WC_in);
specparam PATHPULSE$ = 0;
endspecify
`endif // `ifdef XIL_TIMING
endmodule // OSERDESE1
`timescale 1ps/1ps
/////////////////////////////////////////////////////////
//
// module selfheal_oserdese1_vlog
//
///////////////////////////////////////////////////////
//
// Self healing circuit for Mt Blanc
// This model ONLY works for SERDES operation!!
//
//
//
////////////////////////////////////////////////////////
//
//
//
/////////////////////////////////////////////////////////
//
// Inputs:
// dq3 - dq0: Data from load counter
// CLKDIV: Divided clock from PLL
// srint: RESET from load generator
// rst: Set/Reset control
//
//
//
// Outputs:
// SHO: Data output
//
//
//
// Programmable Points
// SELFHEAL: String of 5 bits. 1 as enable and 4 as compare
// Test attributes in model
//
//
//
//
//
////////////////////////////////////////////////////////////////////////////////
//
module selfheal_oserdese1_vlog (dq3, dq2, dq1, dq0,
CLKDIV, srint, rst,
SHO);
input dq3, dq2, dq1, dq0;
input CLKDIV, srint, rst;
output SHO;
reg shr;
reg SHO;
wire clkint;
wire error;
wire rst_in, rst_self_heal;
// Programmable Points
wire [4:0] SELFHEAL;
assign SELFHEAL = 5'b00000;
//////////////////////////////////////////////////
// Delay values
//
parameter FFD = 10; // clock to out delay for flip flops
// driven by clk
parameter FFCD = 10; // clock to out delay for flip flops
// driven by clkdiv
parameter MXD = 10; // 60 ps mux delay
parameter MXR1 = 10;
/////////////////////////////////////////
assign clkint = CLKDIV & SELFHEAL[4];
assign error = (((~SELFHEAL[4] ^ SELFHEAL[3]) ^ dq3) | ((~SELFHEAL[4] ^ SELFHEAL[2]) ^ dq2) | ((~SELFHEAL[4] ^ SELFHEAL[1]) ^ dq1) | ((~SELFHEAL[4] ^ SELFHEAL[0]) ^ dq0));
assign rst_in = (~SELFHEAL[4] | ~srint);
assign rst_self_heal = (rst | ~shr);
/////////////////////////////////////////
// Reset Flop
////////////////////////////////////////
always @ (posedge clkint or posedge rst)
begin
begin
if (rst)
begin
shr <= # FFD 1'b0;
end
else begin
shr <= #FFD rst_in;
end
end
end
// Self heal flop
always @ (posedge clkint or posedge rst_self_heal)
begin
begin
if (rst_self_heal)
begin
SHO <= 1'b0;
end
else
begin
SHO <= # FFD error;
end
end
end
endmodule
`timescale 1ps/1ps
////////////////////////////////////////////////////////
//
// module plg_oserdese1_vlog
//
////////////////////////////////////////////////////////
//
// Programmable Load Generator (PLG)
// Divide by 2-8 counter with load enable output
//
//
/////////////////////////////////////////////////////////
//
// Inputs:
// c23: Selects between divide by 2 or 3
// c45: Selects between divide by 4 or 5
// c67: Selects between divide by 6 or 7
// sel: Selects which divide function is chosen
// 00:2 or 3, 01:4 or 5, 10:6 or 7, 11:8
// clk: High speed clock from DCM
// clkdiv: Low speed clock from DCM
// rst: Reset
//
//
//
// Outputs:
//
// load: Loads serdes register at terminal count
//
//
// Test attributes:
// INIT_LOADCNT: 4-bits to init counter
// SRTYPE: 1-bit to control synchronous or asynchronous operation
// SELFHEAL: 5-bits to control self healing feature
//
//
//
////////////////////////////////////////////////////////////////////////////////
//
module plg_oserdese1_vlog (c23, c45, c67, sel,
clk, clkdiv, rst,
load, IOCLK_GLITCH);
input c23, c45, c67;
input [1:0] sel;
input clk, clkdiv, rst;
output load;
output IOCLK_GLITCH;
wire SRTYPE;
wire [3:0] INIT_LOADCNT;
wire [4:0] SELFHEAL;
assign SRTYPE = 1'b1;
assign INIT_LOADCNT = 4'b0000;
assign SELFHEAL = 5'b00000;
reg q0, q1, q2, q3;
reg qhr, qlr;
reg load, mux;
wire cntrrst;
assign cntrrst = IOCLK_GLITCH | rst;
// Parameters for gate delays
parameter ffdcnt = 1;
parameter mxdcnt = 1;
parameter FFRST = 145; // clock to out delay for flop in PLSG
//////////////////////////////////////////////////
tri0 GSR = glbl.GSR;
always @(GSR)
begin
if (GSR)
begin
assign q3 = INIT_LOADCNT[3];
assign q2 = INIT_LOADCNT[2];
assign q1 = INIT_LOADCNT[1];
assign q0 = INIT_LOADCNT[0];
end
else
begin
deassign q3;
deassign q2;
deassign q1;
deassign q0;
end
end
// flops for counter
// asynchronous reset
always @ (posedge qhr or posedge clk)
begin
if (qhr & !SRTYPE)
begin
q0 <= # ffdcnt 1'b0;
q1 <= # ffdcnt 1'b0;
q2 <= # ffdcnt 1'b0;
q3 <= # ffdcnt 1'b0;
end
else if (!SRTYPE)
begin
q3 <= # ffdcnt q2;
q2 <= # ffdcnt (!(!q0 & !q2) & q1);
q1 <= # ffdcnt q0;
q0 <= # ffdcnt mux;
end
end
// synchronous reset
always @ (posedge clk)
begin
if (qhr & SRTYPE)
begin
q0 <= # ffdcnt 1'b0;
q1 <= # ffdcnt 1'b0;
q2 <= # ffdcnt 1'b0;
q3 <= # ffdcnt 1'b0;
end
else if (SRTYPE)
begin
q3 <= # ffdcnt q2;
q2 <= # ffdcnt (!(!q0 & !q2) & q1);
q1 <= # ffdcnt q0;
q0 <= # ffdcnt mux;
end
end
// mux settings for counter
always @ (sel or c23 or c45 or c67 or q0 or q1 or q2 or q3)
begin
case (sel)
2'b00: mux <= # mxdcnt (!q0 & !(c23 & q1));
2'b01: mux <= # mxdcnt (!q1 & !(c45 & q2));
2'b10: mux <= # mxdcnt (!q2 & !(c67 & q3));
2'b11: mux <= # mxdcnt !q3;
default: mux <= # mxdcnt 1'b0;
endcase
end
// mux decoding for load signal
always @ (sel or c23 or c45 or c67 or q0 or q1 or q2 or q3)
begin
case (sel)
2'b00: load <= # mxdcnt q0;
2'b01: load <= # mxdcnt q0 & q1;
2'b10: load <= # mxdcnt q0 & q2;
2'b11: load <= # mxdcnt q0 & q3;
default: load <= # mxdcnt 1'b0;
endcase
end
// flops to reset counter
// Low speed flop
// asynchronous reset
always @ (posedge cntrrst or posedge clkdiv)
begin
if (cntrrst & !SRTYPE)
begin
qlr <= # FFRST 1'b1;
end
else if (!SRTYPE)
begin
qlr <= # FFRST 1'b0;
end
end
// synchronous reset
always @ (posedge clkdiv)
begin
if (cntrrst & SRTYPE)
begin
qlr <= # FFRST 1'b1;
end
else if (SRTYPE)
begin
qlr <= # FFRST 1'b0;
end
end
// High speed flop
// asynchronous reset
always @ (posedge cntrrst or posedge clk)
begin
if (cntrrst & !SRTYPE)
begin
qhr <= # ffdcnt 1'b1;
end
else if (!SRTYPE)
begin
qhr <= # ffdcnt qlr;
end
end
// synchronous reset
always @ (posedge clk)
begin
if (cntrrst & SRTYPE)
begin
qhr <= # ffdcnt 1'b1;
end
else if (SRTYPE)
begin
qhr <= # ffdcnt qlr;
end
end
selfheal_oserdese1_vlog fixcntr (.dq3(q3), .dq2(q2), .dq1(q1), .dq0(q0),
.CLKDIV(clkdiv), .srint(qlr), .rst(rst),
.SHO(IOCLK_GLITCH));
endmodule
`timescale 1ps/1ps
////////////////////////////////////////////////////////
//
// module rank12d_oserdese1_vlog
//
//
// This model ONLY works for SERDES operation!!
// Does not include tristate circuit
//
//
////////////////////////////////////////////////////////
//
// Inputs:
// D1: Data input 1
// D2: Data input 2
// D3: Data input 3
// D4: Data input 4
// D5: Data input 5
// D6: Data input 6
// C: High speed clock from DCM
// OCE: Clock enable for output data flops
// SR: Set/Reset control. For the last 3 flops in OQ
// (d1rnk2, d2rnk2 and d2nrnk2) this function is
// controlled bythe attributes SRVAL_OQ. In SERDES mode,
// SR is a RESET ONLY for all other flops! The flops will
// still be RESET even if SR is programmed to a SET!
// CLKDIV: Low speed divided clock from DCM
// SHIFTIN1: Carry in data 1 for master from slave
// SHIFTIN2: Carry in data 2 for master from slave
//
//
//
// Outputs:
// data1: Data output mux for top flop
// data2: Data output mux for bottom flop
// SHIFTOUT1: Carry out data 1 for slave
// SHIFTOUT2: Carry out data 2 for slave
// load: Used for the tristate when combined into a single model
//
//
//
// Programmable Points
// DATA_RATE_OQ: Rate control for data output, 1-bit
// sdr (1), ddr (0)
// DATA_WIDTH: Input data width,
// 4-bits, values can be from 2 to 10
// SERDES_MODE: Denotes master (0) or slave (1)
// SIM_X_INPUT: This attribute is NOT SUPPORTED in this model!!!
//
//
//
// Programmable points for Test model
// SRTYPE: This is a 4-bit field Sets asynchronous (0) or synchronous (1) set/reset
// 1st bit (msb) sets rank1 flops, 2nd bit sets 4 flops in rank 2,
// 3rd bit sets "3 legacy flops, and 4th (lsb) bit sets the counter
// INIT_ORANK1: Init value for 6 registers in 1st rank (6-bits)
// INIT_ORANK2_PARTIAL: Init value for bottom 4 registers in the 2nd rank (4-bits)
// INIT_LOADCNT: Init value for the load counter (4-bits)
// The other 2 registers in the load counter have init bits, but are
// not supported in this model
// SERDES: Indicates that SERDES mode is chosen
// SLEFHEAL: 5-bit to set self heal circuit
//
//
////////////////////////////////////////////////////////////////////////////////
//
module rank12d_oserdese1_vlog (D1, D2, D3, D4, D5, D6, d2rnk2,
SHIFTIN1, SHIFTIN2,
C, CLKDIV, SR, OCE,
data1, data2, SHIFTOUT1, SHIFTOUT2,
DATA_RATE_OQ, DATA_WIDTH,
SERDES_MODE, load,
IOCLK_GLITCH,
INIT_OQ, SRVAL_OQ);
input D1, D2, D3, D4, D5, D6;
input d2rnk2;
input SHIFTIN1, SHIFTIN2;
input C, CLKDIV, SR, OCE;
input INIT_OQ, SRVAL_OQ;
output data1, data2;
output SHIFTOUT1, SHIFTOUT2;
output load;
output IOCLK_GLITCH;
// Programmable Points
input DATA_RATE_OQ;
input [3:0] DATA_WIDTH;
input SERDES_MODE;
wire DDR_CLK_EDGE, SERDES;
wire [3:0] SRTYPE;
wire [4:0] SELFHEAL;
wire [3:0] INIT_ORANK2_PARTIAL;
wire [5:0] INIT_ORANK1;
assign DDR_CLK_EDGE = 1'b1;
assign SERDES = 1'b1;
assign SRTYPE = 4'b1111;
assign SELFHEAL = 5'b00000;
assign INIT_ORANK2_PARTIAL = 4'b0000;
assign INIT_ORANK1 = 6'b000000;
reg d1r, d2r, d3r, d4r, d5r, d6r;
reg d3rnk2, d4rnk2, d5rnk2, d6rnk2;
reg data1, data2, data3, data4, data5, data6;
reg ddr_data, odata_edge, sdata_edge;
reg c23, c45, c67;
reg [1:0] sel;
wire C2p, C3;
wire loadint;
wire [3:0] seloq;
wire oqsr, oqrev;
wire [2:0] sel1_4;
wire [3:0] sel5_6;
wire [4:0] plgcnt;
assign C2p = (C & DDR_CLK_EDGE) | (!C & !DDR_CLK_EDGE);
assign C3 = !C2p;
assign plgcnt = {DATA_RATE_OQ,DATA_WIDTH};
assign sel1_4 = {SERDES,loadint,DATA_RATE_OQ};
assign sel5_6 = {SERDES,SERDES_MODE,loadint,DATA_RATE_OQ};
assign load = loadint;
assign seloq = {OCE,DATA_RATE_OQ,oqsr,oqrev};
assign oqsr = !SRTYPE[1] & SR & !SRVAL_OQ;
assign oqrev = !SRTYPE[1] & SR & SRVAL_OQ;
//////////////////////////////////////////////////
// Delay values
//
parameter FFD = 1; // clock to out delay for flip flops
// driven by clk
parameter FFCD = 1; // clock to out delay for flip flops
// driven by clkdiv
parameter MXD = 1; // 60 ps mux delay
parameter MXR1 = 1;
////////////////////////////////////////////
// Initialization of flops with GSR for test model
///////////////////////////////////////////
tri0 GSR = glbl.GSR;
always @(GSR)
begin
if (GSR)
begin
assign d6rnk2 = INIT_ORANK2_PARTIAL[3];
assign d5rnk2 = INIT_ORANK2_PARTIAL[2];
assign d4rnk2 = INIT_ORANK2_PARTIAL[1];
assign d3rnk2 = INIT_ORANK2_PARTIAL[0];
assign d6r = INIT_ORANK1[5];
assign d5r = INIT_ORANK1[4];
assign d4r = INIT_ORANK1[3];
assign d3r = INIT_ORANK1[2];
assign d2r = INIT_ORANK1[1];
assign d1r = INIT_ORANK1[0];
end
else
begin
deassign d6rnk2;
deassign d5rnk2;
deassign d4rnk2;
deassign d3rnk2;
deassign d6r;
deassign d5r;
deassign d4r;
deassign d3r;
deassign d2r;
deassign d1r;
end
end
/////////////////////////////////////////
// Assign shiftout1 and shiftout2
assign SHIFTOUT1 = d3rnk2 & SERDES_MODE;
assign SHIFTOUT2 = d4rnk2 & SERDES_MODE;
// last 4 flops which only have reset and init
// asynchronous operation
always @ (posedge C or posedge SR)
begin
begin
if (SR & !SRTYPE[2])
begin
d3rnk2 <= # FFD 1'b0;
d4rnk2 <= # FFD 1'b0;
d5rnk2 <= # FFD 1'b0;
d6rnk2 <= # FFD 1'b0;
end
else if (!SRTYPE[2])
begin
d3rnk2 <= # FFD data3;
d4rnk2 <= # FFD data4;
d5rnk2 <= # FFD data5;
d6rnk2 <= # FFD data6;
end
end
end
// synchronous operation
always @ (posedge C)
begin
begin
if (SR & SRTYPE[2])
begin
d3rnk2 <= # FFD 1'b0;
d4rnk2 <= # FFD 1'b0;
d5rnk2 <= # FFD 1'b0;
d6rnk2 <= # FFD 1'b0;
end
else if (SRTYPE[2])
begin
d3rnk2 <= # FFD data3;
d4rnk2 <= # FFD data4;
d5rnk2 <= # FFD data5;
d6rnk2 <= # FFD data6;
end
end
end
///////////////////////////////////////////////////
// First rank of flops for input data
//////////////////////////////////////////////////
// asynchronous operation
always @ (posedge CLKDIV or posedge SR)
begin
begin
if (SR & !SRTYPE[3])
begin
d1r <= # FFCD 1'b0;
d2r <= # FFCD 1'b0;
d3r <= # FFCD 1'b0;
d4r <= # FFCD 1'b0;
d5r <= # FFCD 1'b0;
d6r <= # FFCD 1'b0;
end
else if (!SRTYPE[3])
begin
d1r <= # FFCD D1;
d2r <= # FFCD D2;
d3r <= # FFCD D3;
d4r <= # FFCD D4;
d5r <= # FFCD D5;
d6r <= # FFCD D6;
end
end
end
// synchronous operation
always @ (posedge CLKDIV)
begin
begin
if (SR & SRTYPE[3])
begin
d1r <= # FFCD 1'b0;
d2r <= # FFCD 1'b0;
d3r <= # FFCD 1'b0;
d4r <= # FFCD 1'b0;
d5r <= # FFCD 1'b0;
d6r <= # FFCD 1'b0;
end
else if (SRTYPE[3])
begin
d1r <= # FFCD D1;
d2r <= # FFCD D2;
d3r <= # FFCD D3;
d4r <= # FFCD D4;
d5r <= # FFCD D5;
d6r <= # FFCD D6;
end
end
end
// Muxs for 2nd rank of flops
always @ (sel1_4 or d1r or d2rnk2 or d3rnk2)
begin
casex (sel1_4)
3'b100: data1 <= # MXR1 d3rnk2;
3'b110: data1 <= # MXR1 d1r;
3'b101: data1 <= # MXR1 d2rnk2;
3'b111: data1 <= # MXR1 d1r;
default: data1 <= # MXR1 d3rnk2;
endcase
end
always @ (sel1_4 or d2r or d3rnk2 or d4rnk2)
begin
casex (sel1_4)
3'b100: data2 <= # MXR1 d4rnk2;
3'b110: data2 <= # MXR1 d2r;
3'b101: data2 <= # MXR1 d3rnk2;
3'b111: data2 <= # MXR1 d2r;
default: data2 <= # MXR1 d4rnk2;
endcase
end
//Note: To stop data rate of 00 from being illegal, register data is fed to mux
always @ (sel1_4 or d3r or d4rnk2 or d5rnk2)
begin
casex (sel1_4)
3'b100: data3 <= # MXR1 d5rnk2;
3'b110: data3 <= # MXR1 d3r;
3'b101: data3 <= # MXR1 d4rnk2;
3'b111: data3 <= # MXR1 d3r;
default: data3 <= # MXR1 d5rnk2;
endcase
end
always @ (sel1_4 or d4r or d5rnk2 or d6rnk2)
begin
casex (sel1_4)
3'b100: data4 <= # MXR1 d6rnk2;
3'b110: data4 <= # MXR1 d4r;
3'b101: data4 <= # MXR1 d5rnk2;
3'b111: data4 <= # MXR1 d4r;
default: data4 <= # MXR1 d6rnk2;
endcase
end
always @ (sel5_6 or d5r or d6rnk2 or SHIFTIN1)
begin
casex (sel5_6)
4'b1000: data5 <= # MXR1 SHIFTIN1;
4'b1010: data5 <= # MXR1 d5r;
4'b1001: data5 <= # MXR1 d6rnk2;
4'b1011: data5 <= # MXR1 d5r;
4'b1100: data5 <= # MXR1 1'b0;
4'b1110: data5 <= # MXR1 d5r;
4'b1101: data5 <= # MXR1 d6rnk2;
4'b1111: data5 <= # MXR1 d5r;
default: data5 <= # MXR1 SHIFTIN1;
endcase
end
always @ (sel5_6 or D6 or d6r or SHIFTIN1 or SHIFTIN2)
begin
casex (sel5_6)
4'b1000: data6 <= # MXR1 SHIFTIN2;
4'b1010: data6 <= # MXR1 d6r;
4'b1001: data6 <= # MXR1 SHIFTIN1;
4'b1011: data6 <= # MXR1 d6r;
4'b1100: data6 <= # MXR1 1'b0;
4'b1110: data6 <= # MXR1 d6r;
4'b1101: data6 <= # MXR1 1'b0;
4'b1111: data6 <= # MXR1 d6r;
default: data6 <= # MXR1 SHIFTIN2;
endcase
end
// instantiate programmable load generator
plg_oserdese1_vlog ldgen (.c23(c23), .c45(c45), .c67(c67), .sel(sel),
.clk(C), .clkdiv(CLKDIV), .rst(SR),
.load(loadint), .IOCLK_GLITCH(IOCLK_GLITCH));
// Set value of counter in programmable load generator
always @ (plgcnt or c23 or c45 or c67 or sel)
begin
casex (plgcnt)
5'b00100: begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b00; end
5'b00110: begin c23=1'b1; c45=1'b0; c67=1'b0; sel=2'b00; end
5'b01000: begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b01; end
5'b01010: begin c23=1'b0; c45=1'b1; c67=1'b0; sel=2'b01; end
5'b10010: begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b00; end
5'b10011: begin c23=1'b1; c45=1'b0; c67=1'b0; sel=2'b00; end
5'b10100: begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b01; end
5'b10101: begin c23=1'b0; c45=1'b1; c67=1'b0; sel=2'b01; end
5'b10110: begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b10; end
5'b10111: begin c23=1'b0; c45=1'b0; c67=1'b1; sel=2'b10; end
5'b11000: begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b11; end
default: $display("DATA_WIDTH %b and DATA_RATE_OQ %b at %t is an illegal value", DATA_WIDTH, DATA_RATE_OQ, $time);
endcase
end
endmodule
`timescale 1ps/1ps
//////////////////////////////////////////////////////////
//
// module trif_oserdese1_vlog
//
/////////////////////////////////////////////////////////
//
// Inputs:
//
// T1, T2, T3, T4: tristate inputs
// load: Programmable load generator output
// TCE: Tristate clock enable
// SR: Set/Reset control. For the last 3 flops in TQ
// (qt1, qt2 and qt2n) this function is
// controlled bythe attributes SRVAL_TQ. In SERDES mode,
// SR is a RESET ONLY for all other flops! The flops will
// still be RESET even if SR is programmed to a SET!
// C, C2: High speed clocks
// C2 drives 2nd latch and C3 (inverse of C2) drives
// 3rd latch in output section
// CLKDIV: Low speed clock
//
//
//
//
// Outputs:
//
// TQ: Output of tristate mux
//
//
// Programmable Options:
//
// DATA_RATE_TQ: 2-bit field for types of operaiton
// 0 (buf from T1), 1 (registered output from T1), 2 (ddr)
// TRISTATE_WIDTH: 2-bit field for input width
// 0 (width 1), 1 (width 2), 2 (width 4)
// INIT_TQ: Init TQ output (0,1)
// SRVAL_TQ: This bit to controls value of SR input.
// Only the last 3 flops (qt1, qt2 and qt2n) are
// affected by this bit.For SERDES mode, this bit
// should be set to '0' making SR a reset. This is the
// desired state since all other flops only
// respond to this pin as a reset. Their function
// cannot be changed. SR is 'O' for SET and '1' for RESET.
//
//
// Programmable Test Options:
// SRTYPE: Control S and R as asynchronous (0) or synchronous (1)
// 2-bit value. 1st bit (msb) controls the 4 input flops
// and the 2nd bit (lsb) controls the "3 legacy flops"
// DDR_CLK_EDGE: Same or opposite edge operation
//
//
//
////////////////////////////////////////////////////////////////////////////////
//
module trif_oserdese1_vlog (T1, T2, T3, T4, load,
C, CLKDIV, SR, TCE,
DATA_RATE_TQ, TRISTATE_WIDTH,
INIT_TQ, SRVAL_TQ,
data1, data2);
input T1, T2, T3, T4, load;
input C, CLKDIV, SR, TCE;
input [1:0] TRISTATE_WIDTH;
input [1:0] DATA_RATE_TQ;
input INIT_TQ, SRVAL_TQ;
output data1, data2;
wire DDR_CLK_EDGE;
wire [3:0] INIT_TRANK1;
wire [1:0] SRTYPE;
assign SRTYPE = 2'b11;
assign DDR_CLK_EDGE = 1'b1;
assign INIT_TRANK1 = 4'b0000;
reg t1r, t2r, t3r, t4r;
reg qt1, qt2, qt2n;
reg data1, data2;
reg sdata_edge, odata_edge, ddr_data;
wire C2p, C3;
wire load;
wire [6:0] tqsel;
wire [4:0] sel;
assign sel = {load,DATA_RATE_TQ,TRISTATE_WIDTH};
//////////////////////////////////////////////////
// Parameters for gate delays
parameter ffd = 1;
parameter mxd = 1;
/////////////////////////////
// Initialization of Flops
////////////////////////////
tri0 GSR = glbl.GSR;
always @(GSR)
begin
if (GSR)
begin
assign t1r = INIT_TRANK1[0];
assign t2r = INIT_TRANK1[1];
assign t3r = INIT_TRANK1[2];
assign t4r = INIT_TRANK1[3];
end
else
begin
deassign t1r;
deassign t2r;
deassign t3r;
deassign t4r;
end
end
// First rank of flops
// asynchronous reset operation
always @ (posedge CLKDIV or posedge SR)
begin
begin
if (SR & !SRTYPE[1])
begin
t1r <= # ffd 1'b0;
t2r <= # ffd 1'b0;
t3r <= # ffd 1'b0;
t4r <= # ffd 1'b0;
end
else if (!SRTYPE[1])
begin
t1r <= # ffd T1;
t2r <= # ffd T2;
t3r <= # ffd T3;
t4r <= # ffd T4;
end
end
end
// synchronous reset operation
always @ (posedge CLKDIV)
begin
begin
if (SR & SRTYPE[1])
begin
t1r <= # ffd 1'b0;
t2r <= # ffd 1'b0;
t3r <= # ffd 1'b0;
t4r <= # ffd 1'b0;
end
else if (SRTYPE[1])
begin
t1r <= # ffd T1;
t2r <= # ffd T2;
t3r <= # ffd T3;
t4r <= # ffd T4;
end
end
end
// Data Muxs for tristate otuput signals
always @ (sel or T1 or t1r or t3r)
begin
casex (sel)
5'b00000: data1 <= # mxd T1;
5'b10000: data1 <= # mxd T1;
5'bX0000: data1 <= # mxd T1;
5'b00100: data1 <= # mxd T1;
5'b10100: data1 <= # mxd T1;
5'bX0100: data1 <= # mxd T1;
5'b01001: data1 <= # mxd T1;
5'b11001: data1 <= # mxd T1;
5'b01010: data1 <= # mxd t3r;
5'b11010: data1 <= # mxd t1r;
// CR 551953 -- enabled TRISTATE_WIDTH to be 1 in DDR mode. No func change, but removed warnings
5'b01000: ;
5'b11000: ;
5'bX1000: ;
default: $display("DATA_RATE_TQ %b and/or TRISTATE_WIDTH %b at time %t are not supported by OSERDES", DATA_RATE_TQ,TRISTATE_WIDTH,$time);
endcase
end
// For data 2, width of 1 is inserted as acceptable for buf and sdr
// The capability exists in the device if the feature is added
always @ (sel or T2 or t2r or t4r)
begin
casex (sel)
5'b00000: data2 <= # mxd T2;
5'b00100: data2 <= # mxd T2;
5'b10000: data2 <= # mxd T2;
5'b10100: data2 <= # mxd T2;
5'bX0000: data2 <= # mxd T2;
5'bX0100: data2 <= # mxd T2;
5'b00X00: data2 <= # mxd T2;
5'b10X00: data2 <= # mxd T2;
5'bX0X00: data2 <= # mxd T2;
5'b01001: data2 <= # mxd T2;
5'b11001: data2 <= # mxd T2;
5'bX1001: data2 <= # mxd T2;
5'b01010: data2 <= # mxd t4r;
5'b11010: data2 <= # mxd t2r;
// CR 551953 -- enabled TRISTATE_WIDTH to be 1 in DDR mode. No func change, but removed warnings
5'b01000: ;
5'b11000: ;
5'bX1000: ;
default: $display("DATA_RATE_TQ %b and/or TRISTATE_WIDTH %b at time %t are not supported by OSERDES", DATA_RATE_TQ,TRISTATE_WIDTH,$time);
endcase
end
endmodule
`timescale 1ps/1ps
//////////////////////////////////////////////////////////
//
// module txbuffer_oserdese1_vlog
//
/////////////////////////////////////////////////////////
//
// FIFO and Control circuit for OSERDES
module txbuffer_oserdese1_vlog (iodelay_state, qmux1, qmux2, tmux1, tmux2,
d1, d2, t1, t2, trif,
WC, ODV, extra,
clk, clkdiv, bufo, bufop, rst,
ODELAY_USED, DDR3_DATA,
DDR3_MODE);
input d1, d2, t1, t2;
input trif;
input WC, ODV;
input rst;
input clk, clkdiv, bufo, bufop;
input ODELAY_USED, DDR3_DATA;
input DDR3_MODE;
output iodelay_state, extra;
output qmux1, qmux2, tmux1, tmux2;
wire WC_DELAY;
assign WC_DELAY = 1'b0;
wire rd_gap1;
wire rst_bufo_p, rst_bufg_p;
wire rst_bufo_rc, rst_bufg_wc, rst_cntr, rst_bufop_rc;
wire [1:0] qwc, qrd;
wire bufo_out;
fifo_tdpipe_oserdese1_vlog data1 (.muxout(inv_qmux1), .din(~d1), .qwc(qwc), .qrd(qrd),
.rd_gap1(rd_gap1),
.bufg_clk(clk), .bufo_clk(bufo), .rst_bufo_p(rst_bufo_p), .rst_bufg_p(rst_bufg_p),
.DDR3_DATA(DDR3_DATA), .extra(extra), .ODV(ODV), .DDR3_MODE(DDR3_MODE)
);
fifo_tdpipe_oserdese1_vlog data2 (.muxout(inv_qmux2), .din(~d2), .qwc(qwc), .qrd(qrd),
.rd_gap1(rd_gap1),
.bufg_clk(clk), .bufo_clk(bufo), .rst_bufo_p(rst_bufo_p), .rst_bufg_p(rst_bufg_p),
.DDR3_DATA(DDR3_DATA), .extra(extra), .ODV(ODV), .DDR3_MODE(DDR3_MODE)
);
fifo_tdpipe_oserdese1_vlog tris1 (.muxout(inv_tmux1), .din(~t1), .qwc(qwc), .qrd(qrd),
.rd_gap1(rd_gap1),
.bufg_clk(clk), .bufo_clk(bufo), .rst_bufo_p(rst_bufo_p), .rst_bufg_p(rst_bufg_p),
.DDR3_DATA(DDR3_DATA), .extra(extra), .ODV(ODV), .DDR3_MODE(DDR3_MODE)
);
fifo_tdpipe_oserdese1_vlog tris2 (.muxout(inv_tmux2), .din(~t2), .qwc(qwc), .qrd(qrd),
.rd_gap1(rd_gap1),
.bufg_clk(clk), .bufo_clk(bufo), .rst_bufo_p(rst_bufo_p), .rst_bufg_p(rst_bufg_p),
.DDR3_DATA(DDR3_DATA), .extra(extra), .ODV(ODV), .DDR3_MODE(DDR3_MODE)
);
wire qmux1 = ~inv_qmux1;
wire qmux2 = ~inv_qmux2;
wire tmux1 = ~inv_tmux1;
wire tmux2 = ~inv_tmux2;
fifo_reset_oserdese1_vlog rstckt (.rst_bufo_p(rst_bufo_p), .rst_bufo_rc(rst_bufo_rc),
.rst_bufg_p(rst_bufg_p), .rst_bufg_wc(rst_bufg_wc),
.rst_cntr(rst_cntr),
.bufg_clk(clk), .bufo_clk(bufo), .clkdiv(clkdiv), .rst(rst),
.divide_2(WC_DELAY), .bufop_clk(bufop), .rst_bufop_rc(rst_bufop_rc)
);
fifo_addr_oserdese1_vlog addcntr (.qwc(qwc), .qrd(qrd), .rd_gap1(rd_gap1), .rst_bufg_wc(rst_bufg_wc), .rst_bufo_rc(rst_bufo_rc), .bufg_clk(clk), .bufo_clk(bufo),
.data(DDR3_DATA), .extra(extra), .rst_bufop_rc(rst_bufop_rc), .bufop_clk(bufop)
);
iodlyctrl_npre_oserdese1_vlog idlyctrl (.iodelay_state(iodelay_state), .bufo_out(bufo_out), .rst_cntr(rst_cntr),
.wc(WC), .trif(trif),
.rst(rst_bufg_p), .bufg_clk(clk), .bufo_clk(bufo), .bufg_clkdiv(clkdiv),
.ddr3_dimm(ODELAY_USED), .wl6(WC_DELAY)
);
endmodule
`timescale 1ps/1ps
////////////////////////////////////////////////////////
//
// module fifo_tdpipe_oserdese1_vlog
//
////////////////////////////////////////////////////////
// FIFO for write path
module fifo_tdpipe_oserdese1_vlog (muxout, din, qwc, qrd,
rd_gap1,
bufg_clk, bufo_clk, rst_bufo_p, rst_bufg_p,
DDR3_DATA, extra, ODV, DDR3_MODE
);
input din;
input [1:0] qwc, qrd;
input rd_gap1;
input rst_bufo_p, rst_bufg_p;
input bufg_clk, bufo_clk;
input DDR3_DATA, ODV;
input extra;
input DDR3_MODE;
output muxout;
reg muxout;
reg qout1, qout2;
reg qout_int, qout_int2;
reg [4:1] fifo;
reg cin1;
reg omux;
wire [2:0] sel;
reg pipe1, pipe2;
wire selqoi, selqoi2;
wire [2:0] selmuxout;
// 4 flops that make up the basic FIFO. They are all clocked
// off of fast BUFG. The first flop is the top flop in the chain.
// The CE input is used to mux the inputs. If the flop is selected,
// CE is high and it takes data from the output of the mux. If the
// flop is not selected, it retains its data.
always @ (posedge bufg_clk or posedge rst_bufg_p)
begin
if (rst_bufg_p)
begin
fifo <= #10 4'b0000;
end
else if (!qwc[1] & !qwc[0])
begin
fifo <= #10 {fifo[4:2],din};
end
else if (!qwc[1] & qwc[0])
begin
fifo <= #10 {fifo[4:3],din,fifo[1]};
end
else if (qwc[1] & qwc[0])
begin
fifo <= #10 {fifo[4],din,fifo[2:1]};
end
else if (qwc[1] & !qwc[0])
begin
fifo <= #10 {din,fifo[3:1]};
end
end
// Capture stage top
// This is the top flop of the "3 flops" for ODDR. This flop, along with the read
// counter will be clocked off of bufo. A 4:1 mux wil decode the outputs of the
// read counter and load the write data. A subsequent 2:1 mux will decode between
// the fifo and the legacy operation
// OMUX
always @ (qrd or fifo)
begin
case (qrd)
2'b00: omux <= #10 fifo[1];
2'b01: omux <= #10 fifo[2];
2'b10: omux <= #10 fifo[4];
2'b11: omux <= #10 fifo[3];
default: omux <= #10 fifo[1];
endcase
end
always @ (posedge bufo_clk or posedge rst_bufo_p)
begin
if (rst_bufo_p)
begin
qout_int <= #10 1'b0;
qout_int2 <= #10 1'b0;
end
else
begin
qout_int <= #10 omux;
qout_int2 <= #10 qout_int;
end
end
assign #10 selqoi = ODV | rd_gap1;
always @ (selqoi or qout_int or omux)
begin
case(selqoi)
1'b0: qout1 <= #10 omux;
1'b1: qout1 <= #10 qout_int;
default: qout1 <= #10 omux;
endcase
end
assign #10 selqoi2 = ODV & rd_gap1;
always @ (selqoi2 or qout_int2 or qout_int)
begin
case(selqoi2)
1'b0: qout2 <= #10 qout_int;
1'b1: qout2 <= #10 qout_int2;
default qout2 <= #10 qout_int;
endcase
end
assign #14 selmuxout = {DDR3_MODE,DDR3_DATA,extra};
always @ (selmuxout or din or omux or qout1 or qout2)
begin
case (selmuxout)
3'b000: muxout = #1 din;
3'b001: muxout = #1 din;
3'b010: muxout = #1 din;
3'b011: muxout = #1 din;
3'b100: muxout = #1 omux;
3'b101: muxout = #1 omux;
3'b110: muxout = #1 qout1;
3'b111: muxout = #1 qout2;
default: muxout = #10 din;
endcase
end
endmodule
`timescale 1ps/1ps
////////////////////////////////////////////////////////
//
// module fifo_reset_oserdese1_vlog
//
////////////////////////////////////////////////////////
//
// TX FIFO reset
//
// This design performs 2 functions. One function is to reset all the
// flops in the TX FIFO. The other function is to respond to the signal
// rst_cntr. This signal comes from iodlyctrl and will be used to initiate an
// orderly transition to switch the DQ/DQS I/O from and read to a write.
// This process is required only for DDR3 DIMM support because the IODELAY
// is used for both the inputs and the outputs. The signal from the
// squelch circuit is a present fabric output. An additional input
// indicating that a write command was issued will be
// required for all I/O to support this signal.
//
// This design uses an asynchronous reset to reset all flops. After the
// reset is disabled, a 0 is propagated through the pipe stages to terminate
// the reset. The first 2 flops run off of the clkdiv domain. Their output
// feeds a latch to cross between the clkdiv and bufg_clk domain. The pipe
// stage for the bufg_clk domain is 3 deep, where the last flop is the
// reset signal for the bufg_clk domain. The 2nd flop of the bufg_clk pipe
// is fed to 2 flops that are in the bufo_clk domain. The 2 flops are
// to resolve metastability between the 2 clock domains.
//
// The circuit to enable an orderly transition from read to write uses the
// PREAMBLE_SYNCHED output of a portion of the squelch circuit. This pulse
// will initiate the reset sequence and also generate an enable which will
// switch the IODELAY from an IDELAY to an ODELAY. Timing is as specified in
// the "State of the Union" presentation.
//
//
module fifo_reset_oserdese1_vlog (rst_bufo_p, rst_bufo_rc,
rst_bufg_p, rst_bufg_wc,
rst_cntr,
bufg_clk, bufo_clk, clkdiv, rst,
divide_2, bufop_clk, rst_bufop_rc
);
input rst_cntr;
input rst;
input bufg_clk, bufo_clk, clkdiv;
input bufop_clk;
// Memory cell input to support divide by 1 operation
input divide_2;
output rst_bufo_p, rst_bufo_rc;
output rst_bufg_p, rst_bufg_wc;
output rst_bufop_rc;
reg [1:0] clkdiv_pipe;
reg bufg_pipe;
reg rst_cntr_reg;
reg [2:0] bufo_rst_p, bufo_rst_rc;
reg [1:0] bufop_rst_rc;
reg [1:0] bufg_rst_p, bufg_rst_wc;
wire bufg_clkdiv_latch, ltint1, ltint2, ltint3;
wire latch_in;
// 2 stage pipe for clkdiv domain to allow user to properly
// time everything
always @ (posedge bufg_clk or posedge rst)
begin
if (rst)
begin
rst_cntr_reg <= #10 1'b0;
end
else
begin
rst_cntr_reg <= #10 rst_cntr;
end
end
always @ (posedge clkdiv or posedge rst)
begin
if (rst)
begin
clkdiv_pipe <= #10 2'b11;
end
else
begin
clkdiv_pipe <= #10 {clkdiv_pipe[0],1'b0};
end
end
// Latch to compensate for clkdiv and bufg_clk clock skew
// Built of actual gates
assign #1 latch_in = clkdiv_pipe[1];
assign #1 bufg_clkdiv_latch = !(ltint1 && ltint3);
assign #1 ltint1 = !(latch_in && bufg_clk);
assign #1 ltint2 = !(ltint1 && bufg_clk);
assign #1 ltint3 = !(bufg_clkdiv_latch && ltint2);
// BUFG flop to register latch signal
always @ (posedge bufg_clk or posedge rst)
begin
if (rst)
begin
bufg_pipe <= #10 1'b1;
end
else
begin
bufg_pipe <= #10 bufg_clkdiv_latch;
end
end
// BUFG clock domain resests
always @ (posedge bufg_clk or posedge rst)
begin
if (rst)
begin
bufg_rst_p <= #10 2'b11;
end
else
begin
bufg_rst_p <= #10 {bufg_rst_p[0],bufg_pipe};
end
end
always @ (posedge bufg_clk or posedge rst_cntr or posedge rst)
begin
if (rst || rst_cntr)
begin
bufg_rst_wc <= #10 2'b11;
end
else
begin
bufg_rst_wc <= #10 {bufg_rst_wc[0],bufg_pipe};
end
end
// BUFO clock domain Resets
always @ (posedge bufo_clk or posedge rst)
begin
if (rst)
begin
bufo_rst_p <= #10 3'b111;
end
else
begin
bufo_rst_p <= #10 {bufo_rst_p[1:0],bufg_pipe};
end
end
always @ (posedge bufo_clk or posedge rst or posedge rst_cntr)
begin
if (rst || rst_cntr)
begin
bufo_rst_rc <= #10 3'b111;
end
else
begin
bufo_rst_rc <= #10 {bufo_rst_rc[1:0],bufg_pipe};
end
end
always @ (posedge bufop_clk or posedge rst or posedge rst_cntr)
begin
if (rst || rst_cntr)
begin
bufop_rst_rc <= #10 2'b11;
end
else
begin
bufop_rst_rc <= #10 {bufop_rst_rc[0],bufg_pipe};
end
end
// final reset assignments
assign rst_bufo_rc = bufo_rst_rc[1];
assign rst_bufo_p = bufo_rst_p[1];
assign rst_bufop_rc = bufop_rst_rc[1];
assign rst_bufg_wc = bufg_rst_wc[1];
assign rst_bufg_p = bufg_rst_p[1];
endmodule
`timescale 1ps/1ps
////////////////////////////////////////////////////////
//
// module fifo_addr_oserdese1_vlog
//
////////////////////////////////////////////////////////
// Read and Write address generators for TX FIFO
//
// This circuit contains 2 greycode read and write address generators
// that will be used with the TX FIFO. Both counters generate a
// count sequence of 00 -> 01 -> 11 -> 10 -> 00.
module fifo_addr_oserdese1_vlog (qwc, qrd, rd_gap1, rst_bufg_wc, rst_bufo_rc, bufg_clk, bufo_clk,
data, extra, rst_bufop_rc, bufop_clk
);
input bufg_clk, bufo_clk;
input rst_bufo_rc, rst_bufg_wc;
input rst_bufop_rc;
input data; // mc to tell if I/O is DDR3 DQ or DQS
input bufop_clk;
output qwc, qrd;
output rd_gap1, extra;
reg [1:0] qwc;
reg [1:0] qrd;
reg stop_rd, rd_gap1, extra;
reg rd_cor, rd_cor_cnt, rd_cor_cnt1;
wire qwc0_latch, qwc1_latch;
wire li01, li02, li03;
wire li11, li12, li13;
wire qwc0_latchn, qwc1_latchn;
wire li01n, li02n, li03n;
wire li11n, li12n, li13n;
reg stop_rdn, rd_cor_cntn, rd_cor_cnt1n, stop_rc;
reg [1:0] qwcd;
reg [1:0] qrdd;
reg stop_rdd, rd_gap1d, extrad;
reg rd_cord, rd_cor_cntd, rd_cor_cnt1d;
wire qwcd0_latch, qwcd1_latch;
wire li01d, li02d, li03d;
wire li11d, li12d, li13d;
// Write counter
// The write counter uses 2 flops to create the grey code pattern of
// 00 -> 01 -> 11 -> 10 -> 00. The write counter is initialized
// to 11 and the read counter will be initialized to 00. This gives
// a basic 2 clock separation to compensate for the phase differences.
// The write counter is clocked off of the bufg clock
always @ (posedge bufg_clk or posedge rst_bufg_wc)
begin
if (rst_bufg_wc)
begin
qwc <= # 10 2'b11;
end
else if (qwc[1] ^ qwc[0])
begin
qwc[1] <= # 10 ~qwc[1];
qwc[0] <= # 10 qwc[0];
end
else
begin
qwc[1] <= # 10 qwc[1];
qwc[0] <= # 10 ~qwc[0];
end
end
// Read counter
// The read counter uses 2 flops to create the grey code pattern of
// 00 -> 01 -> 11 -> 10 -> 00. The read counter is initialized
// to 00 and the write counter will be initialized to 11. This gives
// a basic 2 clock separation to compensate for the phase differences.
// The read counter is clocked off of the bufo clock
always @ (posedge bufo_clk or posedge rst_bufo_rc)
begin
if (rst_bufo_rc)
begin
qrd <= # 10 2'b00;
end
else if (stop_rd && !data)
begin
qrd <= #10 qrd;
end
else if (qrd[1] ^ qrd[0])
begin
qrd[1] <= # 10 ~qrd[1];
qrd[0] <= # 10 qrd[0];
end
else
begin
qrd[1] <= # 10 qrd[1];
qrd[0] <= # 10 ~qrd[0];
end
end
always @ (posedge bufo_clk or posedge rst_bufo_rc)
begin
if (rst_bufo_rc)
begin
rd_gap1 <= # 10 1'b0;
end
// else if ((qwc1_latch && qwc0_latch) && (qrd[0] ^ qrd[1]))
else if ((qwc1_latch && qwc0_latch) && (qrd[0]))
begin
rd_gap1 <= # 10 1'b1;
end
else
begin
rd_gap1 <= # 10 rd_gap1;
end
end
// Looking for 11
assign #1 qwc0_latch = !(li01 & li03);
assign #1 li01 = !(qwc[0] & bufo_clk);
assign #1 li02 = !(li01 & bufo_clk);
assign #1 li03 = !(qwc0_latch & li02);
assign #1 qwc1_latch = !(li11 & li13);
assign #1 li11 = !(qwc[1] & bufo_clk);
assign #1 li12 = !(li11 & bufo_clk);
assign #1 li13 = !(qwc1_latch & li12);
// The following counter is to match the control counter to see if the
// read counter did a hold after reset. This knowledge will enable the
// computation of the 'extra' output. This in turn can add the
// proper number of pipe stages to the output. The circuit must use
// the output of BUFO and not be modified by ODELAY. This is because
// the control pins PP clock was not modified by BUFO. If the
// control pins PP clock was modified by BUFO, the reset must be done
// with this in mind.
// Read counter
// The read counter uses 2 flops to create the grey code pattern of
// 00 -> 01 -> 11 -> 10 -> 00. The read counter is initialized
// to 00 and the write counter will be initialized to 11. This gives
// a basic 2 clock separation to compensate for the phase differences.
// The read counter is clocked off of the bufo clock
always @ (posedge bufop_clk or posedge rst_bufop_rc)
begin
if (rst_bufop_rc)
begin
qrdd <= # 10 2'b00;
end
else if (qrdd[1] ^ qrdd[0])
begin
qrdd[1] <= # 10 ~qrdd[1];
qrdd[0] <= # 10 qrdd[0];
end
else
begin
qrdd[1] <= # 10 qrdd[1];
qrdd[0] <= # 10 ~qrdd[0];
end
end
// Looking for 11
assign #1 qwcd0_latch = !(li01d & li03d);
assign #1 li01d = !(qwc[0] & bufop_clk);
assign #1 li02d = !(li01d & bufop_clk);
assign #1 li03d = !(qwcd0_latch & li02d);
assign #1 qwcd1_latch = !(li11d & li13d);
assign #1 li11d = !(qwc[1] & bufop_clk);
assign #1 li12d = !(li11d & bufop_clk);
assign #1 li13d = !(qwcd1_latch & li12d);
// Circuit to fix read address counters in non data pins
always @ (posedge bufop_clk or posedge rst_bufo_rc)
begin
if (rst_bufop_rc)
begin
stop_rd <= # 10 1'b0;
rd_cor_cnt <= #10 1'b0;
rd_cor_cnt1 <= #10 1'b0;
end
else if (((qwcd1_latch && qwcd0_latch) && (qrdd[0] ^ qrdd[1]) && !rd_cor_cnt1))
begin
stop_rd <= #10 1'b1;
rd_cor_cnt <= #10 1'b1;
rd_cor_cnt1 <= #10 rd_cor_cnt;
end
else
begin
stop_rd <= #10 1'b0;
rd_cor_cnt <= #10 1'b1;
rd_cor_cnt1 <= #10 rd_cor_cnt;
end
end
// Circuit to inform data if control counters habe been fixed
always @ (posedge bufop_clk or posedge rst_bufop_rc)
begin
if (rst_bufop_rc)
begin
extra <= #10 1'b0;
end
else if (stop_rd)
begin
extra <= #10 1'b1;
end
end
endmodule
`timescale 1ps/1ps
////////////////////////////////////////////////////////
//
// module iodlyctrl_npre_oserdese1_vlog
//
////////////////////////////////////////////////////////
//
// Circuit to automatically switch IODELAY from IDELAY to ODELAY using knowledge
// of write command. This circuit forces the user to wait 3 extra CLK/CLK# cycles
// when performing a read to write turnaround. The JEDEC DDR3 spec states that
// the turnaround can be done in 2 clock cycles. This circuit requires 5 clock
// cycles.
// This circuit is only used for a DDR3 appplication that uses DIMMs
module iodlyctrl_npre_oserdese1_vlog (iodelay_state, bufo_out, rst_cntr,
wc, trif,
rst, bufg_clk, bufo_clk, bufg_clkdiv,
ddr3_dimm, wl6
);
input wc;
input trif;
input rst;
input bufo_clk, bufg_clk, bufg_clkdiv;
input ddr3_dimm, wl6;
output iodelay_state, rst_cntr;
output bufo_out;
reg qw0cd, qw1cd;
reg turn, turn_p1;
reg rst_cntr;
reg w_to_w;
reg [2:0] wtw_cntr;
reg cmd0, cmd0_n6, cmd0_6, cmd1;
wire wr_cmd0;
wire lt0int1, lt0int2, lt0int3;
wire lt1int1, lt1int2, lt1int3;
wire latch_in;
reg qwcd;
assign bufo_out = bufo_clk;
// create turn signal for IODELAY
assign iodelay_state = (trif && ~w_to_w) & ((~turn && ~turn_p1) || ~ddr3_dimm);
// Registers to detect write command
// Registers using bufg clkdiv
always @ (posedge bufg_clkdiv)
begin
if (rst)
begin
qwcd <= #10 0;
end
else
begin
qwcd <= #10 wc;
end
end
// Latch to allow skew between CLK and CLKDIV from BUFGs
assign #1 wr_cmd0 = !(lt0int1 && lt0int3);
assign #1 lt0int1 = !(qwcd && bufg_clk);
assign #1 lt0int2 = !(lt0int1 && bufg_clk);
assign #1 lt0int3 = !(wr_cmd0 && lt0int2);
always @ (posedge bufg_clk)
begin
if (rst)
begin
cmd0_n6 <= #10 1'b0;
cmd0_6 <= #10 1'b0;
end
else
begin
cmd0_n6 <= #10 wr_cmd0;
cmd0_6 <= #10 cmd0_n6;
end
end
// mux to add extra pipe stage for WL = 6
always @ (cmd0_n6 or wl6 or cmd0_6)
begin
case (wl6)
1'b0: cmd0 <= #10 cmd0_n6;
1'b1: cmd0 <= #10 cmd0_6;
default: cmd0 <= #10 cmd0_n6;
endcase
end
// Turn IODELAY and reset FIFO read/write counters
//always @ (posedge bufg_clk)
// begin
// if (rst)
//
// begin
// turn <= #10 1'b0;
// rst_cntr <= #10 1'b0;
// end
// else if (w_to_w)
// begin
// turn <= #10 1'b1;
// rst_cntr <= #10 1'b0;
// end
// else if (cmd0 && !turn)
// begin
// turn <= #10 1'b1;
// rst_cntr <= #10 1'b1;
// end
// else if (~trif)
// begin
// turn <= #10 1'b0;
// rst_cntr <= #10 1'b0;
// end
// else if (turn)
// begin
// turn <= #10 1'b1;
// rst_cntr <= #10 1'b0;
// end
// else
// begin
// turn <= #10 1'b0;
// rst_cntr <= #10 1'b0;
// end
// end
always @ (posedge bufg_clk)
begin
begin
if (rst)
begin
turn <= #10 1'b0;
end
else
begin
turn <= #10 (w_to_w || (cmd0 && ~turn) ||
(~wtw_cntr[2] && turn));
end
end
begin
if (rst)
begin
rst_cntr <= #10 1'b0;
end
else
begin
rst_cntr <= #10 (~w_to_w && (cmd0 && ~turn));
end
end
end
always @ (posedge bufg_clk)
begin
if (rst)
begin
turn_p1 <= #10 1'b0;
end
else
begin
turn_p1 <= #10 turn;
end
end
// Detect multiple write commands and don"t turn IODELAY
//always @ (posedge bufg_clk)
// begin
// if (rst)
// begin
// w_to_w <= #10 1'b0;
// wtw_cntr <= #10 3'b000;
// end
// else if (cmd0 && turn_p1)
// begin
// w_to_w <= #10 1'b1;
// wtw_cntr <= #10 3'b000;
// end
// else if (wtw_cntr == 3'b101)
// begin
// w_to_w <= #10 1'b0;
// wtw_cntr <= #10 3'b000;
// end
// else if (w_to_w)
// begin
// w_to_w <= #10 1'b1;
// wtw_cntr <= #10 wtw_cntr + 1;
// end
// end
always @ (posedge bufg_clk)
begin
begin
if (rst)
begin
w_to_w <= #10 1'b0;
end
else
begin
w_to_w <= #10 ((cmd0 && turn_p1) ||
(w_to_w && (~wtw_cntr[2] || ~wtw_cntr[1])));
end
end
end
always @ (posedge bufg_clk)
begin
if (!(w_to_w || turn) || (cmd0 && turn_p1))
begin
wtw_cntr <= #10 3'b000;
end
else if (w_to_w || turn_p1)
begin
wtw_cntr <= #10 wtw_cntr + 1;
end
end
endmodule
`timescale 1ps/1ps
////////////////////////////////////////////////////////
//
// MODULE dout_oserdese1_vlog
//
// This model ONLY works for SERDES operation!!
// Does not include tristate circuit
//
/////////////////////////////////////////////////////////
//
// Inputs:
// data1: Data from FIFO
// data2: Data input FIFO
// CLK: High speed clock from DCM
// BUFO: Clock from performance path
// OCE: Clock enable for output data flops
// SR: Set/Reset control. For the last 3 flops in OQ
// (d1rnk2, d2rnk2 and d2nrnk2) this function is
// controlled bythe attributes SRVAL_OQ. In SERDES mode,
// SR is a RESET ONLY for all other flops! The flops will
// still be RESET even if SR is programmed to a SET!
//
//
//
// Outputs:
// OQ: Data output
//
//
//
// Programmable Points
// DATA_RATE_OQ: Rate control for data output, 1-bit
// sdr (1), ddr (0)
// INIT_OQ: Init OQ output "flop"
// SRVAL_OQ: This bit to controls value of SR input.
// Only the last 3 flops (d1rnk2, d2rnk2 and d2nrnk2)
// are affected by this bit.For SERDES mode, this bit
// should be set to '0' making SR a reset. This is the
// desired state since all other flops only respond to
// this pin as a reset. Their function cannot be
// changed. SR is '1' for SET and '0' for RESET.
//
//
//
// Programmable points for Test model
// SRTYPE: This is a 4-bit field Sets asynchronous (0) or synchronous (1) set/reset
// 1st bit (msb) sets rank1 flops, 2nd bit sets 4 flops in rank 2,
// 3rd bit sets "3 legacy flops, and 4th (lsb) bit sets the counter
// DDR_CLK_EDGE: Controls use of 2 or 3 flops for single case. Default to 1 for
// SERDES operation
//
//
///////////////////////////////////////////////////////////////////////////////
//
module dout_oserdese1_vlog (data1, data2,
CLK, BUFO, SR, OCE,
OQ, d2rnk2,
DATA_RATE_OQ,
INIT_OQ, SRVAL_OQ,
DDR3_MODE);
input data1, data2;
input CLK, SR, OCE;
input BUFO;
input INIT_OQ, SRVAL_OQ;
input DDR3_MODE;
output OQ;
output d2rnk2;
// Programmable Points
input DATA_RATE_OQ;
wire DDR_CLK_EDGE;
wire [3:0] SRTYPE;
assign DDR_CLK_EDGE = 1'b1;
assign SRTYPE = 4'b1111;
reg d1rnk2, d2rnk2, d2nrnk2;
reg OQ;
reg ddr_data, odata_edge, sdata_edge;
reg c23, c45, c67;
wire C;
wire C2p, C3;
wire [3:0] seloq;
wire oqsr, oqrev;
assign C = (BUFO & DDR3_MODE) | (CLK & !DDR3_MODE);
assign C2p = (C & DDR_CLK_EDGE) | (!C & !DDR_CLK_EDGE);
assign C3 = !C2p;
assign seloq = {OCE,DATA_RATE_OQ,oqsr,oqrev};
assign oqsr = !SRTYPE[1] & SR & !SRVAL_OQ;
assign oqrev = !SRTYPE[1] & SR & SRVAL_OQ;
//////////////////////////////////////////////////
// Delay values
//
parameter FFD = 1; // clock to out delay for flip flops
// driven by clk
parameter FFCD = 1; // clock to out delay for flip flops
// driven by clkdiv
parameter MXD = 1; // 60 ps mux delay
parameter MXR1 = 1;
////////////////////////////////////////////
// Initialization of flops with GSR for test model
///////////////////////////////////////////
tri0 GSR = glbl.GSR;
always @(GSR)
begin
if (GSR)
begin
assign OQ = INIT_OQ;
assign d1rnk2 = INIT_OQ;
assign d2rnk2 = INIT_OQ;
assign d2nrnk2 = INIT_OQ;
end
else
begin
deassign OQ;
deassign d1rnk2;
deassign d2rnk2;
deassign d2nrnk2;
end
end
/////////////////////////////////////////
/////////////////////////////////////////
// 3 flops to create DDR operations of 4 latches
////////////////////////////////////////
// Representation of top latch
// asynchronous operation
always @ (posedge C or posedge SR)
begin
begin
if (SR & !SRVAL_OQ & !SRTYPE[1])
begin
d1rnk2 <= # FFD 1'b0;
end
else if (SR & SRVAL_OQ & !SRTYPE[1])
begin
d1rnk2 <= # FFD 1'b1;
end
else if (!OCE & !SRTYPE[1])
begin
d1rnk2 <= # FFD OQ;
end
else if (!SRTYPE[1])
begin
d1rnk2 <= # FFD data1;
end
end
end
// synchronous operation
always @ (posedge C)
begin
begin
if (SR & !SRVAL_OQ & SRTYPE[1])
begin
d1rnk2 <= # FFD 1'b0;
end
else if (SR & SRVAL_OQ & SRTYPE[1])
begin
d1rnk2 <= # FFD 1'b1;
end
else if (!OCE & SRTYPE[1])
begin
d1rnk2 <= # FFD OQ;
end
else if (SRTYPE[1])
begin
d1rnk2 <= # FFD data1;
end
end
end
// Representation of 2nd latch
// asynchronous operation
always @ (posedge C2p or posedge SR)
begin
begin
if (SR & !SRVAL_OQ & !SRTYPE[1])
begin
d2rnk2 <= # FFD 1'b0;
end
else if (SR & SRVAL_OQ & !SRTYPE[1])
begin
d2rnk2 <= # FFD 1'b1;
end
else if (!OCE & !SRTYPE[1])
begin
d2rnk2 <= # FFD OQ;
end
else if (!SRTYPE[1])
begin
d2rnk2 <= # FFD data2;
end
end
end
// synchronous operation
always @ (posedge C2p)
begin
begin
if (SR & !SRVAL_OQ & SRTYPE[1])
begin
d2rnk2 <= # FFD 1'b0;
end
else if (SR & SRVAL_OQ & SRTYPE[1])
begin
d2rnk2 <= # FFD 1'b1;
end
else if (!OCE & SRTYPE[1])
begin
d2rnk2 <= # FFD OQ;
end
else if (SRTYPE[1])
begin
d2rnk2 <= # FFD data2;
end
end
end
// Representation of 3rd flop ( latch and output latch)
// asynchronous operation
always @ (posedge C3 or posedge SR)
begin
begin
if (SR & !SRVAL_OQ & !SRTYPE[1])
begin
d2nrnk2 <= # FFD 1'b0;
end
else if (SR & SRVAL_OQ & !SRTYPE[1])
begin
d2nrnk2 <= # FFD 1'b1;
end
else if (!OCE & !SRTYPE[1])
begin
d2nrnk2 <= # FFD OQ;
end
else if (!SRTYPE[1])
begin
d2nrnk2 <= # FFD d2rnk2;
end
end
end
// synchronous operation
always @ (posedge C3)
begin
begin
if (SR & !SRVAL_OQ & SRTYPE[1])
begin
d2nrnk2 <= # FFD 1'b0;
end
else if (SR & SRVAL_OQ & SRTYPE[1])
begin
d2nrnk2 <= # FFD 1'b1;
end
else if (!OCE & SRTYPE[1])
begin
d2nrnk2 <= # FFD OQ;
end
else if (SRTYPE[1])
begin
d2nrnk2 <= # FFD d2rnk2;
end
end
end
// Logic to generate same edge data from d1rnk2 and d2nrnk2;
always @ (C or C3 or d1rnk2 or d2nrnk2)
begin
sdata_edge <= # MXD (d1rnk2 & C) | (d2nrnk2 & C3);
end
// Mux to create opposite edge DDR data from d1rnk2 and d2rnk2
always @ (C or d1rnk2 or d2rnk2)
begin
case (C)
1'b0: odata_edge <= # MXD d2rnk2;
1'b1: odata_edge <= # MXD d1rnk2;
default: odata_edge <= # MXD d1rnk2;
endcase
end
// Logic to same edge and opposite data into just ddr data
always @ (ddr_data or sdata_edge or odata_edge or DDR_CLK_EDGE)
begin
ddr_data <= # MXD (odata_edge & !DDR_CLK_EDGE) | (sdata_edge & DDR_CLK_EDGE);
end
// Output mux to generate OQ
always @ (seloq or d1rnk2 or ddr_data or OQ)
begin
casex (seloq)
4'bXX01: OQ <= # MXD 1'b1;
4'bXX10: OQ <= # MXD 1'b0;
4'bXX11: OQ <= # MXD 1'b0;
4'bX000: OQ <= # MXD ddr_data;
4'bX100: OQ <= # MXD d1rnk2;
default: OQ <= # MXD ddr_data;
endcase
end
endmodule
`timescale 1ps/1ps
//////////////////////////////////////////////////////////
//
// module tout_oserdese1_vlog
//
// Tristate Output cell for Mt Blanc
//
//
////////////////////////////////////////////////////////
//
//
//
/////////////////////////////////////////////////////////
//
// Inputs:
//
// data1, data2: tristate inputs
// TCE: Tristate clock enable
// SR: Set/Reset control. For the last 3 flops in TQ
// (qt1, qt2 and qt2n) this function is
// controlled bythe attributes SRVAL_TQ. In SERDES mode,
// SR is a RESET ONLY for all other flops! The flops will
// still be RESET even if SR is programmed to a SET!
// CLK: High speed clocks
// C2 drives 2nd latch and C3 (inverse of C2) drives
// 3rd latch in output section
// BUFO: Performance path clock
//
//
//
//
// Outputs:
//
// TQ: Output of tristate mux
//
//
// Programmable Options:
//
// DATA_RATE_TQ: 2-bit field for types of operaiton
// 0 (buf from T1), 1 (registered output from T1), 2 (ddr)
// TRISTATE_WIDTH: 2-bit field for input width
// 0 (width 1), 1 (width 2), 2 (width 4)
// INIT_TQ: Init TQ output (0,1)
// SRVAL_TQ: This bit to controls value of SR input.
// Only the last 3 flops (qt1, qt2 and qt2n) are
// affected by this bit.For SERDES mode, this bit
// should be set to '0' making SR a reset. This is the
// desired state since all other flops only
// respond to this pin as a reset. Their function
// cannot be changed. SR is 'O' for SET and '1' for RESET.
//
//
// Programmable Test Options:
// SRTYPE: Control S and R as asynchronous (0) or synchronous (1)
// 2-bit value. 1st bit (msb) controls the 4 input flops
// and the 2nd bit (lsb) controls the "3 legacy flops"
// DDR_CLK_EDGE: Same or opposite edge operation
//
//
//
////////////////////////////////////////////////////////////////////////////////
//
module tout_oserdese1_vlog (data1, data2,
CLK, BUFO, SR, TCE,
DATA_RATE_TQ, TRISTATE_WIDTH,
INIT_TQ, SRVAL_TQ,
TQ, DDR3_MODE);
input data1, data2;
input CLK, BUFO, SR, TCE;
input [1:0] DATA_RATE_TQ, TRISTATE_WIDTH;
input INIT_TQ, SRVAL_TQ;
input DDR3_MODE;
output TQ;
wire DDR_CLK_EDGE;
wire [1:0] SRTYPE;
assign SRTYPE = 2'b11;
assign DDR_CLK_EDGE = 1'b1;
reg TQ;
reg t1r, t2r, t3r, t4r;
reg qt1, qt2, qt2n;
reg sdata_edge, odata_edge, ddr_data;
wire C;
wire C2p, C3;
wire load;
wire [5:0] tqsel;
wire tqsr, tqrev;
wire [4:0] sel;
assign C = (BUFO & DDR3_MODE) | (CLK & !DDR3_MODE);
assign C2p = (C & DDR_CLK_EDGE) | (!C & !DDR_CLK_EDGE);
assign C3 = !C2p;
assign tqsr = (!SRTYPE[0] & SR & !SRVAL_TQ) | (!SRTYPE[0] & SRVAL_TQ);
assign tqrev = (!SRTYPE[0] & SR & SRVAL_TQ) | (!SRTYPE[0] & !SRVAL_TQ);
assign tqsel = {TCE,DATA_RATE_TQ,TRISTATE_WIDTH,tqsr};
//////////////////////////////////////////////////
// Parameters for gate delays
parameter ffd = 1;
parameter mxd = 1;
/////////////////////////////
// Initialization of Flops
////////////////////////////
tri0 GSR = glbl.GSR;
always @(GSR)
begin
if (GSR)
begin
assign TQ = INIT_TQ;
assign qt1 = INIT_TQ;
assign qt2 = INIT_TQ;
assign qt2n = INIT_TQ;
end
else
begin
deassign TQ;
deassign qt1;
deassign qt2;
deassign qt2n;
end
end
/////////////////////////////////////////
// 3 flops to create DDR operations of 4 latches
////////////////////////////////////////
// Representation of top latch
// asynchronous operation
always @ (posedge C or posedge SR)
begin
begin
if (SR & !SRVAL_TQ & !SRTYPE[0])
begin
qt1 <= # ffd 1'b0;
end
else if (SR & SRVAL_TQ & !SRTYPE[0])
begin
qt1 <= # ffd 1'b1;
end
else if (!TCE & !SRTYPE[0])
begin
qt1 <= # ffd TQ;
end
else if (!SRTYPE[0])
begin
qt1 <= # ffd data1;
end
end
end
// synchronous operation
always @ (posedge C)
begin
begin
if (SR & !SRVAL_TQ & SRTYPE[0])
begin
qt1 <= # ffd 1'b0;
end
else if (SR & SRVAL_TQ & SRTYPE[0])
begin
qt1 <= # ffd 1'b1;
end
else if (!TCE & SRTYPE[0])
begin
qt1 <= # ffd TQ;
end
else if (SRTYPE[0])
begin
qt1 <= # ffd data1;
end
end
end
// Representation of 2nd latch
// asynchronous operation
always @ (posedge C2p or posedge SR)
begin
begin
if (SR & !SRVAL_TQ & !SRTYPE[0])
begin
qt2 <= # ffd 1'b0;
end
else if (SR & SRVAL_TQ & !SRTYPE[0])
begin
qt2 <= # ffd 1'b1;
end
else if (!TCE & !SRTYPE[0])
begin
qt2 <= # ffd TQ;
end
else if (!SRTYPE[0])
begin
qt2 <= # ffd data2;
end
end
end
// synchronous operation
always @ (posedge C2p)
begin
begin
if (SR & !SRVAL_TQ & SRTYPE[0])
begin
qt2 <= # ffd 1'b0;
end
else if (SR & SRVAL_TQ & SRTYPE[0])
begin
qt2 <= # ffd 1'b1;
end
else if (!TCE & SRTYPE[0])
begin
qt2 <= # ffd TQ;
end
else if (SRTYPE[0])
begin
qt2 <= # ffd data2;
end
end
end
// Representation of 3rd flop ( latch and output latch)
// asynchronous operation
always @ (posedge C3 or posedge SR)
begin
begin
if (SR & !SRVAL_TQ & !SRTYPE[0])
begin
qt2n <= # ffd 1'b0;
end
else if (SR & SRVAL_TQ & !SRTYPE[0])
begin
qt2n <= # ffd 1'b1;
end
else if (!TCE & !SRTYPE[0])
begin
qt2n <= # ffd TQ;
end
else if (!SRTYPE[0])
begin
qt2n <= # ffd qt2;
end
end
end
// synchronous operation
always @ (posedge C3)
begin
begin
if (SR & !SRVAL_TQ & SRTYPE[0])
begin
qt2n <= # ffd 1'b0;
end
else if (SR & SRVAL_TQ & SRTYPE[0])
begin
qt2n <= # ffd 1'b1;
end
else if (!TCE & SRTYPE[0])
begin
qt2n <= # ffd TQ;
end
else if (SRTYPE[0])
begin
qt2n <= # ffd qt2;
end
end
end
// Logic to generate same edge data from qt1, qt3;
always @ (C or C3 or qt1 or qt2n)
begin
sdata_edge <= # mxd (qt1 & C) | (qt2n & C3);
end
// Mux to create opposite edge DDR function
always @ (C or qt1 or qt2)
begin
case (C)
1'b0: odata_edge <= # mxd qt2;
1'b1: odata_edge <= # mxd qt1;
default: odata_edge <= 1'b0;
endcase
end
// Logic to same edge and opposite data into just ddr data
always @ (ddr_data or sdata_edge or odata_edge or DDR_CLK_EDGE)
begin
ddr_data <= # mxd (odata_edge & !DDR_CLK_EDGE) | (sdata_edge & DDR_CLK_EDGE);
end
// Output mux to generate TQ
// Note that the TQ mux can also support T2 combinatorial or
// registered outputs.
always @ (tqsel or data1 or ddr_data or qt1 or TQ)
begin
casex (tqsel)
6'bX01XX1: TQ <= # mxd 1'b0;
6'bX10XX1: TQ <= # mxd 1'b0;
6'bX01XX1: TQ <= # mxd 1'b0;
6'bX10XX1: TQ <= # mxd 1'b0;
6'bX0000X: TQ <= # mxd data1;
// 6'b001000: TQ <= # mxd TQ;
// 6'b010010: TQ <= # mxd TQ;
// 6'b010100: TQ <= # mxd TQ;
6'bX01000: TQ <= # mxd qt1;
6'bX10010: TQ <= # mxd ddr_data;
6'bX10100: TQ <= # mxd ddr_data;
default: TQ <= # mxd ddr_data;
endcase
end
endmodule
`endcelldefine
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2010 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=1;
counter_io c1_data();
counter_io c2_data();
//counter_io c3_data; // IEEE illegal, and VCS doesn't allow non-() as it does with cells
counter_io c3_data();
counter_ansi c1 (.clkm(clk),
.c_data(c1_data),
.i_value(4'h1));
counter_ansi c2 (.clkm(clk),
.c_data(c2_data),
.i_value(4'h2));
`ifdef VERILATOR counter_ansi `else counter_nansi `endif
/**/ c3 (.clkm(clk),
.c_data(c3_data),
.i_value(4'h3));
initial begin
c1_data.value = 4'h4;
c2_data.value = 4'h5;
c3_data.value = 4'h6;
end
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc<2) begin
c1_data.reset <= 1;
c2_data.reset <= 1;
c3_data.reset <= 1;
end
if (cyc==2) begin
c1_data.reset <= 0;
c2_data.reset <= 0;
c3_data.reset <= 0;
end
if (cyc==3) begin
if (c1_data.get_lcl() != 12345) $stop;
end
if (cyc==20) begin
$write("[%0t] c1 cyc%0d: c1 %0x %0x c2 %0x %0x c3 %0x %0x\n", $time, cyc,
c1_data.value, c1_data.reset,
c2_data.value, c2_data.reset,
c3_data.value, c3_data.reset);
if (c1_data.value != 2) $stop;
if (c2_data.value != 3) $stop;
if (c3_data.value != 4) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
interface counter_io;
logic [3:0] value;
logic reset;
integer lcl;
task set_lcl (input integer a); lcl=a; endtask
function integer get_lcl (); return lcl; endfunction
endinterface
interface ifunused;
logic unused;
endinterface
module counter_ansi
(
input clkm,
counter_io c_data,
input logic [3:0] i_value
);
initial begin
c_data.set_lcl(12345);
end
always @ (posedge clkm) begin
c_data.value <= c_data.reset ? i_value : c_data.value + 1;
end
endmodule : counter_ansi
`ifndef VERILATOR
// non-ansi modports not seen in the wild yet. Verilog-Perl needs parser improvement too.
module counter_nansi(clkm, c_data, i_value);
input clkm;
counter_io c_data;
input logic [3:0] i_value;
always @ (posedge clkm) begin
c_data.value <= c_data.reset ? i_value : c_data.value + 1;
end
endmodule : counter_nansi
`endif
module modunused (ifunused ifinunused);
ifunused ifunused();
endmodule
|
module mand_core (input clk,
input reset,
input [31:0] cx0,
input [31:0] cxstep, // will execute 11 threads
input [31:0] cy,
input rq,
output ack,
output [(7*11)-1:0] counters);
reg ack;
reg [(7*11)-1:0] counters;
/*
Since pipeline is 11-stage deep, we can issue 11 threads
one thread per cycle.
Once thread is retired, we check the output r, if it's > 16384,
thread is finalised, otherwise it is reschedulled back into
pipeline, increasing the counter.
When there are no active threads left, raise ACK and pass all the counters
as a 7*11-bit register.
*/
// control fsm
parameter S_IDLE = 0;
parameter S_ISSUE = 1;
parameter S_REISSUE = 2;
reg [2:0] state;
// pipeline input registers
reg [31:0] cx;
reg [31:0] i_vx;
reg [31:0] i_vy;
reg [31:0] i_dvx;
reg [31:0] i_dvy;
reg [6:0] i_counter;
reg [3:0] i_thrid;
wire [31:0] vx;
wire [31:0] vy;
wire [31:0] dvx;
wire [31:0] dvy;
wire [31:0] counter;
wire [31:0] thrid;
// pipeline stages registers:
reg [31:0] s00vx1;
reg [31:0] s00tmp1;
reg [31:0] s01tmp1A;
reg [31:0] s01tmp2;
reg [31:0] s01vx;
reg [31:0] s02vx;
reg [31:0] s02tmp1B;
reg [31:0] s02tmp2A;
reg [31:0] s03tmp1C;
reg [31:0] s03tmp2B;
reg [31:0] s03vx;
reg [31:0] s04tmp1D;
reg [31:0] s04tmp2C;
reg [31:0] s04vx;
reg [31:0] s05tmp2D;
reg [31:0] s05vy1;
reg [31:0] s05tmp3;
reg [31:0] s05vx;
reg [31:0] s06tmp3A;
reg [31:0] s06vx;
reg [31:0] s06vy;
reg [31:0] s06tmp2;
reg [31:0] s07tmp3B;
reg [31:0] s07vx;
reg [31:0] s07vy;
reg [31:0] s07tmp2;
reg [31:0] s08tmp3C;
reg [31:0] s08vx;
reg [31:0] s08vy;
reg [31:0] s08tmp2;
reg [31:0] s09tmp3D;
reg [31:0] s09vx;
reg [31:0] s09vy;
reg [31:0] s09tmp2;
reg [31:0] s10dvx;
reg [31:0] s10dvy;
reg [31:0] s10r;
reg [31:0] s10vx;
reg [31:0] s10vy;
// thrid and counter pipeline registers - just passing through
reg [3:0] s00thrid;
reg [3:0] s01thrid;
reg [3:0] s02thrid;
reg [3:0] s03thrid;
reg [3:0] s04thrid;
reg [3:0] s05thrid;
reg [3:0] s06thrid;
reg [3:0] s07thrid;
reg [3:0] s08thrid;
reg [3:0] s09thrid;
reg [3:0] s10thrid;
reg [6:0] s00counter;
reg [6:0] s01counter;
reg [6:0] s02counter;
reg [6:0] s03counter;
reg [6:0] s04counter;
reg [6:0] s05counter;
reg [6:0] s06counter;
reg [6:0] s07counter;
reg [6:0] s08counter;
reg [6:0] s09counter;
reg [6:0] s10counter;
// hoisted logic
wire [31:0] s05vy1_comb;
// xilinx ise does not infer a proper arithmetic shift for >>>
wire s1;
assign s1 = s04tmp1D[31];
assign s05vy1_comb = {s1,s1,s1,s1,s1,s1,s1,s1,s1,s1,s1,s04tmp1D[31:11]} + cy;
wire [31:0] s10dvx_comb;
wire [31:0] s10dvy_comb;
wire [31:0] s10r_comb;
wire s2;
assign s2 = s09tmp2[31];
assign s10dvx_comb = {s2,s2,s2,s2,s2,s2,s2,s2,s2,s2,s2,s2,s09tmp2[31:12]};
wire s3;
assign s3 = s09tmp3D[31];
assign s10dvy_comb = {s3,s3,s3,s3,s3,s3,s3,s3,s3,s3,s3,s3,s09tmp3D[31:12]};
assign s10r_comb = s10dvx_comb + s10dvy_comb;
/* reissue logic */
wire reissue;
assign reissue = (state == S_REISSUE) && (s10r < 16384) && (s10thrid !=0);
assign vx = reissue?s10vx:i_vx;
assign vy = reissue?s10vy:i_vy;
assign dvx = reissue?s10dvx:i_dvx;
assign dvy = reissue?s10dvy:i_dvy;
assign counter = reissue?s10counter+1:i_counter;
assign thrid = reissue?s10thrid:i_thrid;
always @(posedge clk)
if (!reset) begin
s00vx1 <= 0;
s00tmp1 <= 0;
s01tmp1A <= 0;
s01tmp2 <= 0;
s01vx <= 0;
s02vx <= 0;
s02tmp1B <= 0;
s02tmp2A <= 0;
s03tmp1C <= 0;
s03tmp2B <= 0;
s03vx <= 0;
s04tmp1D <= 0;
s04tmp2C <= 0;
s04vx <= 0;
s05tmp2D <= 0;
s05vy1 <= 0;
s05tmp3 <= 0;
s05vx <= 0;
s06tmp3A <= 0;
s06vx <= 0;
s06vy <= 0;
s06tmp2 <= 0;
s07tmp3B <= 0;
s07vx <= 0;
s07vy <= 0;
s07tmp2 <= 0;
s08tmp3C <= 0;
s08vx <= 0;
s08vy <= 0;
s08tmp2 <= 0;
s09tmp3D <= 0;
s09vx <= 0;
s09vy <= 0;
s09tmp2 <= 0;
s10dvx <= 0;
s10dvy <= 0;
s10r <= 0;
s10vx <= 0;
s10vy <= 0;
s00thrid <= 0;
s01thrid <= 0;
s02thrid <= 0;
s03thrid <= 0;
s04thrid <= 0;
s05thrid <= 0;
s06thrid <= 0;
s07thrid <= 0;
s08thrid <= 0;
s09thrid <= 0;
s10thrid <= 0;
s00counter <= 0;
s01counter <= 0;
s02counter <= 0;
s03counter <= 0;
s04counter <= 0;
s05counter <= 0;
s06counter <= 0;
s07counter <= 0;
s08counter <= 0;
s09counter <= 0;
s10counter <= 0;
end else begin // if (!reset)
// Flush thrid through the pipeline
s00thrid <= thrid;
s01thrid <= s00thrid;
s02thrid <= s01thrid;
s03thrid <= s02thrid;
s04thrid <= s03thrid;
s05thrid <= s04thrid;
s06thrid <= s05thrid;
s07thrid <= s06thrid;
s08thrid <= s07thrid;
s09thrid <= s08thrid;
s10thrid <= s09thrid;
s00counter <= counter;
s01counter <= s00counter;
s02counter <= s01counter;
s03counter <= s02counter;
s04counter <= s03counter;
s05counter <= s04counter;
s06counter <= s05counter;
s07counter <= s06counter;
s08counter <= s07counter;
s09counter <= s08counter;
s10counter <= s09counter;
// Stage0
// Inputs: dvx, dvy, cx, dy, vx, vy
s00vx1 <= dvx - dvy + cx;
s00tmp1 <= vx * vy;
// Stage1
s01tmp1A <= s00tmp1;
s01tmp2 <= s00vx1 * s00vx1;
s01vx <= s00vx1;
// Stage2
s02tmp1B <= s01tmp1A;
s02tmp2A <= s01tmp2;
s02vx <= s01vx;
// Stage3
s03tmp1C <= s02tmp1B;
s03tmp2B <= s02tmp2A;
s03vx <= s02vx;
// Stage4
s04tmp1D <= s03tmp1C;
s04tmp2C <= s03tmp2B;
s04vx <= s03vx;
// Stage5
s05tmp2D <= s04tmp2C;
s05vy1 <= s05vy1_comb; // (signed s04tmp1D >>> 11) + cy
s05tmp3 <= s05vy1_comb * s05vy1_comb;
s05vx <= s04vx;
// Stage6
s06tmp3A <= s05tmp3;
s06vx <= s05vx;
s06vy <= s05vy1;
s06tmp2 <= s05tmp2D;
// Stage7
s07tmp3B <= s06tmp3A;
s07vx <= s06vx;
s07vy <= s06vy;
s07tmp2 <= s06tmp2;
// Stage8
s08tmp3C <= s07tmp3B;
s08vx <= s07vx;
s08vy <= s07vy;
s08tmp2 <= s07tmp2;
// Stage9
s09tmp3D <= s08tmp3C;
s09vx <= s08vx;
s09vy <= s08vy;
s09tmp2 <= s08tmp2;
// Stage10
s10dvx <= s10dvx_comb;
s10dvy <= s10dvy_comb;
s10r <= s10r_comb;
s10vx <= s09vx;
s10vy <= s09vy;
end
// Main loop, thread management
reg [3:0] thrid1;
reg [6:0] iterations;
wire [(11*7)-1:0] counters_comb;
assign counters_comb =
{
(s10thrid==11)?s10counter:counters[(11*7)-1:10*7],
(s10thrid==10)?s10counter:counters[(10*7)-1:9*7],
(s10thrid==9)?s10counter:counters[( 9*7)-1:8*7],
(s10thrid==8)?s10counter:counters[( 8*7)-1:7*7],
(s10thrid==7)?s10counter:counters[( 7*7)-1:6*7],
(s10thrid==6)?s10counter:counters[( 6*7)-1:5*7],
(s10thrid==5)?s10counter:counters[( 5*7)-1:4*7],
(s10thrid==4)?s10counter:counters[( 4*7)-1:3*7],
(s10thrid==3)?s10counter:counters[( 3*7)-1:2*7],
(s10thrid==2)?s10counter:counters[(2*7)-1:1*7],
(s10thrid==1)?s10counter:counters[(1*7)-1:0]};
reg [4:0] reissues;
always @(posedge clk)
if (!reset) begin
state <= S_IDLE;
i_thrid <= 0;
i_dvx <= 0;
i_dvy <= 0;
i_vx <= 0;
i_vy <= 0;
counters <= 0;
iterations <= 0;
thrid1 <= 0;
ack <= 0;
cx <= 0;
reissues <= 0;
end else begin
counters <= counters_comb;
case(state)
S_IDLE: if (rq) begin
state <= S_ISSUE;
i_thrid <= 1;
cx <= cx0;
i_dvx <= 0;
i_dvy <= 0;
i_vx <= 0;
i_vy <= 0;
counters <= 0;
iterations <= 0;
ack <= 0;
reissues <= 0;
end else ack <= 0; // if (rq)
S_ISSUE: begin
i_thrid <= i_thrid + 1;
cx <= cx + cxstep;
if (i_thrid == 11) begin
cx <= cx0;
state <= S_REISSUE;
i_thrid <= 0;
i_counter <= 0;
thrid1 <= 1;
end
end
S_REISSUE: begin
if (thrid1 == 11) begin
cx <= cx0;
thrid1 <= 1;
reissues <= 0;
if (iterations == 100 || reissues == 0) begin
state <= S_IDLE;
ack <= 1;
end else begin
iterations <= iterations + 1;
end
end else begin
cx <= cx + cxstep;
thrid1 <= thrid1 + 1;
reissues <= reissues + reissue?1:0;
end
end
endcase
end
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE rev.B2 compliant synthesizable I2C Slave model ////
//// ////
//// ////
//// Authors: Richard Herveille ([email protected]) www.asics.ws ////
//// John Sheahan ([email protected]) ////
//// ////
//// Downloaded from: http://www.opencores.org/projects/i2c/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001,2002 Richard Herveille ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: i2c_slave_model.v,v 1.7 2006/09/04 09:08:51 rherveille Exp $
//
// $Date: 2006/09/04 09:08:51 $
// $Revision: 1.7 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: i2c_slave_model.v,v $
// Revision 1.7 2006/09/04 09:08:51 rherveille
// fixed (n)ack generation
//
// Revision 1.6 2005/02/28 11:33:48 rherveille
// Fixed Tsu:sta timing check.
// Added Thd:sta timing check.
//
// Revision 1.5 2003/12/05 11:05:19 rherveille
// Fixed slave address MSB='1' bug
//
// Revision 1.4 2003/09/11 08:25:37 rherveille
// Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'.
//
// Revision 1.3 2002/10/30 18:11:06 rherveille
// Added timing tests to i2c_model.
// Updated testbench.
//
// Revision 1.2 2002/03/17 10:26:38 rherveille
// Fixed some race conditions in the i2c-slave model.
// Added debug information.
// Added headers.
//
// Disabled debug print out and timing checks - [email protected]
`timescale 1ns / 10ps // removed include of timescale.v - [email protected]
module i2c_slave_model (scl, sda);
//
// parameters
//
parameter I2C_ADR = 7'b101_0000;
//
// input && outpus
//
input scl;
inout sda;
//
// Variable declaration
//
wire debug = 1'b0;
reg [7:0] mem [3:0]; // initiate memory
reg [7:0] mem_adr; // memory address
reg [7:0] mem_do; // memory data output
reg sta, d_sta;
reg sto, d_sto;
reg [7:0] sr; // 8bit shift register
reg rw; // read/write direction
wire my_adr; // my address called ??
wire i2c_reset; // i2c-statemachine reset
reg [2:0] bit_cnt; // 3bit downcounter
wire acc_done; // 8bits transfered
reg ld; // load downcounter
reg sda_o; // sda-drive level
wire sda_dly; // delayed version of sda
// statemachine declaration
parameter idle = 3'b000;
parameter slave_ack = 3'b001;
parameter get_mem_adr = 3'b010;
parameter gma_ack = 3'b011;
parameter data = 3'b100;
parameter data_ack = 3'b101;
reg [2:0] state; // synopsys enum_state
//
// module body
//
initial
begin
sda_o = 1'b1;
state = idle;
end
// generate shift register
always @(posedge scl)
sr <= #1 {sr[6:0],sda};
//detect my_address
assign my_adr = (sr[7:1] == I2C_ADR);
// FIXME: This should not be a generic assign, but rather
// qualified on address transfer phase and probably reset by stop
//generate bit-counter
always @(posedge scl)
if(ld)
bit_cnt <= #1 3'b111;
else
bit_cnt <= #1 bit_cnt - 3'h1;
//generate access done signal
assign acc_done = !(|bit_cnt);
// generate delayed version of sda
// this model assumes a hold time for sda after the falling edge of scl.
// According to the Phillips i2c spec, there s/b a 0 ns hold time for sda
// with regards to scl. If the data changes coincident with the clock, the
// acknowledge is missed
// Fix by Michael Sosnoski
assign #1 sda_dly = sda;
//detect start condition
always @(negedge sda)
if(scl)
begin
sta <= #1 1'b1;
d_sta <= #1 1'b0;
sto <= #1 1'b0;
if(debug)
$display("DEBUG i2c_slave; start condition detected at %t", $time);
end
else
sta <= #1 1'b0;
always @(posedge scl)
d_sta <= #1 sta;
// detect stop condition
always @(posedge sda)
if(scl)
begin
sta <= #1 1'b0;
sto <= #1 1'b1;
//if(debug)
// $display("DEBUG i2c_slave; stop condition detected at %t", $time);
end
else
sto <= #1 1'b0;
//generate i2c_reset signal
assign i2c_reset = sta || sto;
// generate statemachine
always @(negedge scl or posedge sto)
if (sto || (sta && !d_sta) )
begin
state <= #1 idle; // reset statemachine
sda_o <= #1 1'b1;
ld <= #1 1'b1;
end
else
begin
// initial settings
sda_o <= #1 1'b1;
ld <= #1 1'b0;
case(state) // synopsys full_case parallel_case
idle: // idle state
if (acc_done && my_adr)
begin
state <= #1 slave_ack;
rw <= #1 sr[0];
sda_o <= #1 1'b0; // generate i2c_ack
#2;
if(debug && rw)
$display("DEBUG i2c_slave; command byte received (read) at %t", $time);
if(debug && !rw)
$display("DEBUG i2c_slave; command byte received (write) at %t", $time);
if(rw)
begin
mem_do <= #1 mem[mem_adr];
if(debug)
begin
#2 $display("DEBUG i2c_slave; data block read %x from address %x (1)", mem_do, mem_adr);
#2 $display("DEBUG i2c_slave; memcheck [0]=%x, [1]=%x, [2]=%x", mem[4'h0], mem[4'h1], mem[4'h2]);
end
end
end
slave_ack:
begin
if(rw)
begin
state <= #1 data;
sda_o <= #1 mem_do[7];
end
else
state <= #1 get_mem_adr;
ld <= #1 1'b1;
end
get_mem_adr: // wait for memory address
if(acc_done)
begin
state <= #1 gma_ack;
mem_adr <= #1 sr; // store memory address
sda_o <= #1 !(sr <= 15); // generate i2c_ack, for valid address
if(debug)
#1 $display("DEBUG i2c_slave; address received. adr=%x, ack=%b", sr, sda_o);
end
gma_ack:
begin
state <= #1 data;
ld <= #1 1'b1;
end
data: // receive or drive data
begin
if(rw)
sda_o <= #1 mem_do[7];
if(acc_done)
begin
state <= #1 data_ack;
mem_adr <= #2 mem_adr + 8'h1;
sda_o <= #1 (rw && (mem_adr <= 15) ); // send ack on write, receive ack on read
if(rw)
begin
#3 mem_do <= mem[mem_adr];
if(debug)
#5 $display("DEBUG i2c_slave; data block read %x from address %x (2)", mem_do, mem_adr);
end
if(!rw)
begin
mem[ mem_adr[3:0] ] <= #1 sr; // store data in memory
if(debug)
#2 $display("DEBUG i2c_slave; data block write %x to address %x", sr, mem_adr);
end
end
end
data_ack:
begin
ld <= #1 1'b1;
if(rw)
if(sr[0]) // read operation && master send NACK
begin
state <= #1 idle;
sda_o <= #1 1'b1;
end
else
begin
state <= #1 data;
sda_o <= #1 mem_do[7];
end
else
begin
state <= #1 data;
sda_o <= #1 1'b1;
end
end
endcase
end
// read data from memory
always @(posedge scl)
if(!acc_done && rw)
mem_do <= #1 {mem_do[6:0], 1'b1}; // insert 1'b1 for host ack generation
// generate tri-states
assign sda = sda_o ? 1'bz : 1'b0;
//
// Timing checks
//
wire tst_sto = sto;
wire tst_sta = sta;
specify
specparam normal_scl_low = 4700,
normal_scl_high = 4000,
normal_tsu_sta = 4700,
normal_thd_sta = 4000,
normal_tsu_sto = 4000,
normal_tbuf = 4700,
fast_scl_low = 1300,
fast_scl_high = 600,
fast_tsu_sta = 1300,
fast_thd_sta = 600,
fast_tsu_sto = 600,
fast_tbuf = 1300;
// $width(negedge scl, fast_scl_low); // scl low time
// $width(posedge scl, fast_scl_high); // scl high time
// $setup(posedge scl, negedge sda &&& scl, fast_tsu_sta); // setup start
// $setup(negedge sda &&& scl, negedge scl, fast_thd_sta); // hold start
// $setup(posedge scl, posedge sda &&& scl, fast_tsu_sto); // setup stop
// $setup(posedge tst_sta, posedge tst_sto, fast_tbuf); // stop to start time
endspecify
endmodule
|
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module hps_sdram_p0_acv_ldc
(
pll_hr_clk,
pll_dq_clk,
pll_dqs_clk,
dll_phy_delayctrl,
afi_clk,
avl_clk,
adc_clk,
adc_clk_cps,
hr_clk
);
parameter DLL_DELAY_CTRL_WIDTH = "";
parameter ADC_PHASE_SETTING = 0;
parameter ADC_INVERT_PHASE = "false";
parameter IS_HHP_HPS = "false";
input pll_hr_clk;
input pll_dq_clk;
input pll_dqs_clk;
input [DLL_DELAY_CTRL_WIDTH-1:0] dll_phy_delayctrl;
output afi_clk;
output avl_clk;
output adc_clk;
output adc_clk_cps;
output hr_clk;
wire phy_clk_dqs;
wire phy_clk_dq;
wire phy_clk_hr;
wire phy_clk_dqs_2x;
wire phy_clk_addr_cmd;
wire phy_clk_addr_cmd_cps;
generate
if (IS_HHP_HPS == "true") begin
assign phy_clk_hr = pll_hr_clk;
assign phy_clk_dq = pll_dq_clk;
assign phy_clk_dqs = pll_dqs_clk;
assign phy_clk_dqs_2x = 1'b0;
end else begin
cyclonev_phy_clkbuf phy_clkbuf (
.inclk ({pll_hr_clk, pll_dq_clk, pll_dqs_clk, 1'b0}),
.outclk ({phy_clk_hr, phy_clk_dq, phy_clk_dqs, phy_clk_dqs_2x})
);
end
endgenerate
wire [3:0] leveled_dqs_clocks;
wire [3:0] leveled_hr_clocks;
wire hr_seq_clock;
cyclonev_leveling_delay_chain leveling_delay_chain_dqs (
.clkin (phy_clk_dqs),
.delayctrlin (dll_phy_delayctrl),
.clkout(leveled_dqs_clocks)
);
defparam leveling_delay_chain_dqs.physical_clock_source = "DQS";
assign afi_clk = leveled_dqs_clocks[0];
cyclonev_leveling_delay_chain leveling_delay_chain_hr (
.clkin (phy_clk_hr),
.delayctrlin (),
.clkout(leveled_hr_clocks)
);
defparam leveling_delay_chain_hr.physical_clock_source = "HR";
assign avl_clk = leveled_hr_clocks[0];
cyclonev_clk_phase_select clk_phase_select_addr_cmd (
.clkin(leveled_dqs_clocks),
.clkout(adc_clk_cps)
);
defparam clk_phase_select_addr_cmd.physical_clock_source = "ADD_CMD";
defparam clk_phase_select_addr_cmd.use_phasectrlin = "false";
defparam clk_phase_select_addr_cmd.phase_setting = ADC_PHASE_SETTING;
defparam clk_phase_select_addr_cmd.invert_phase = ADC_INVERT_PHASE;
cyclonev_clk_phase_select clk_phase_select_hr (
.phasectrlin(),
.phaseinvertctrl(),
.dqsin(),
`ifndef SIMGEN
.clkin (leveled_hr_clocks[0]),
`else
.clkin (leveled_hr_clocks),
`endif
.clkout (hr_seq_clock)
);
defparam clk_phase_select_hr.physical_clock_source = "HR";
defparam clk_phase_select_hr.use_phasectrlin = "false";
defparam clk_phase_select_hr.phase_setting = 0;
assign hr_clk = hr_seq_clock;
generate
if (ADC_INVERT_PHASE == "true")
begin
assign adc_clk = ~leveled_dqs_clocks[ADC_PHASE_SETTING];
end else begin
assign adc_clk = leveled_dqs_clocks[ADC_PHASE_SETTING];
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__EDFXBP_BLACKBOX_V
`define SKY130_FD_SC_HS__EDFXBP_BLACKBOX_V
/**
* edfxbp: Delay flop with loopback enable, non-inverted clock,
* complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__edfxbp (
Q ,
Q_N,
CLK,
D ,
DE
);
output Q ;
output Q_N;
input CLK;
input D ;
input DE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__EDFXBP_BLACKBOX_V
|
/******************************************************************************
This Source Code Form is subject to the terms of the
Open Hardware Description License, v. 1.0. If a copy
of the OHDL was not distributed with this file, You
can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
Description: Saturating counter branch predictor
This is FSM with 4 states: strongly not taken, weakly not taken,
weakly taken, strongly taken.
Fsm changes it state upon real(not predicted) flag.
If flag was "true" and instruction was bf or flag was "false" and
instruction was bnf fsm changes its state towards "taken". And vice versa
otherwise.
We predict flag on current fsm state and current branch type.
If we are in any "taken" state and current instruction is bf,
we predict flag to be "true". Or we're in any "not taken" state and
current instruction is bnf, we predict flag to be "true".
Copyright (C) 2016 Alexey Baturo <[email protected]>
******************************************************************************/
`include "mor1kx-defines.v"
module mor1kx_branch_predictor_saturation_counter
(
input clk,
input rst,
// Signals belonging to the stage where the branch is predicted.
output predicted_flag_o, //result of predictor
input execute_op_bf_i, // prev insn was bf
input execute_op_bnf_i, // prev insn was bnf
input op_bf_i, // cur insn is bf
input op_bnf_i, // cur insn is bnf
input padv_decode_i, // pipeline is moved
input flag_i, // prev predicted flag
// Signals belonging to the stage where the branch is resolved.
input prev_op_brcond_i, // prev op was cond brn
input branch_mispredict_i // prev brn was mispredicted
);
localparam [1:0]
STATE_STRONGLY_NOT_TAKEN = 2'b00,
STATE_WEAKLY_NOT_TAKEN = 2'b01,
STATE_WEAKLY_TAKEN = 2'b10,
STATE_STRONGLY_TAKEN = 2'b11;
reg [1:0] state = STATE_WEAKLY_TAKEN;
assign predicted_flag_o = (state[1] && op_bf_i) || (!state[1] && op_bnf_i);
wire brn_taken = (execute_op_bf_i && flag_i) || (execute_op_bnf_i && !flag_i);
always @(posedge clk) begin
if (rst) begin
state <= STATE_WEAKLY_TAKEN;
end else begin
if (prev_op_brcond_i && padv_decode_i) begin
if (!brn_taken) begin
// change fsm state:
// STATE_STRONGLY_TAKEN -> STATE_WEAKLY_TAKEN
// STATE_WEAKLY_TAKEN -> STATE_WEAKLY_NOT_TAKEN
// STATE_WEAKLY_NOT_TAKEN -> STATE_STRONGLY_NOT_TAKEN
// STATE_STRONGLY_NOT_TAKEN -> STATE_STRONGLY_NOT_TAKEN
case (state)
STATE_STRONGLY_TAKEN:
state <= STATE_WEAKLY_TAKEN;
STATE_WEAKLY_TAKEN:
state <= STATE_WEAKLY_NOT_TAKEN;
STATE_WEAKLY_NOT_TAKEN:
state <= STATE_STRONGLY_NOT_TAKEN;
STATE_STRONGLY_NOT_TAKEN:
state <= STATE_STRONGLY_NOT_TAKEN;
endcase
end else begin
// change fsm state:
// STATE_STRONGLY_NOT_TAKEN -> STATE_WEAKLY_NOT_TAKEN
// STATE_WEAKLY_NOT_TAKEN -> STATE_WEAKLY_TAKEN
// STATE_WEAKLY_TAKEN -> STATE_STRONGLY_TAKEN
// STATE_STRONGLY_TAKEN -> STATE_STRONGLY_TAKEN
case (state)
STATE_STRONGLY_NOT_TAKEN:
state <= STATE_WEAKLY_NOT_TAKEN;
STATE_WEAKLY_NOT_TAKEN:
state <= STATE_WEAKLY_TAKEN;
STATE_WEAKLY_TAKEN:
state <= STATE_STRONGLY_TAKEN;
STATE_STRONGLY_TAKEN:
state <= STATE_STRONGLY_TAKEN;
endcase
end
end
end
end
endmodule
|
//----------------------------------------------------------------------------
//`timescale 1 ns / 100 ps
module fifo_TB;
//----------------------------------------------------------------------------
// Parameter (may differ for physical synthesis)
//----------------------------------------------------------------------------
parameter tck = 2; // clock period in ns
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
reg clk;
reg rst;
reg rd,wr;
reg [7:0] data_in;
//----------------------------------------------------------------------------
// Device Under Test
//------------------------------------------------------------------
fifo uut(.reset(rst),.clk(clk),.rd1(rd),.wr1(wr),.data_in(data_in));
/* Clocking device */
initial begin
clk <= 0;
rst <=1;
#(2*tck) rst=0;
end
always #(tck/2) clk <= ~clk;
initial begin
wr<=1'b0; #1 ;
wr<=1'b1; #100 ;
wr<=1'b0; #1 ;
end
initial begin
rd<=1'b0; #25 ;
rd<=1'b1; #1020 ;
rd<=1'b0; #2 ;
end
initial begin
#4;
data_in="h"; #1;
data_in="o"; #1;
data_in="l"; #1;
data_in="a"; #1 ;
data_in=" "; #1 ;
data_in="m"; #1;
data_in="u"; #1 ;
data_in="n"; #1 ;
data_in="d"; #1 ;
data_in="o"; #1;
data_in="."; #1 ;
data_in="1"; #1 ;
data_in="2"; #1 ;
data_in="3"; #1 ;
data_in="4"; #1 ;
data_in="5"; #1 ;
data_in="6"; #1 ;
data_in="7"; #1;
data_in="8"; #1 ;
data_in="9"; #1 ;
data_in="0"; #1 ;
end
initial begin: TEST_CASE
$dumpfile("fifo_TB.vcd");
$dumpvars(-1, uut);
#(200) $finish;
end
endmodule //
|
`include "../include/tune.v"
module drammem(
input [9:0] ma,
inout [15:0] d,
input ras_n,
input ucas_n,
input lcas_n,
input we_n
);
parameter _verbose_ = 1;
parameter _add_to_addr_ = 0;
parameter _filter_out_ = 32'h91;
parameter _init_ = 1;
reg [15:0] array [0:1048575];
reg [15:0] dout;
reg [19:0] addr;
wire cas_n;
wire idle;
reg was_ras;
reg was_cas;
reg ready;
initial
begin : clear_mem
integer i;
if( _init_ )
begin
for(i=0;i<1048576;i=i+1)
array[i] = 16'hDEAD;
end
end
always @(negedge ras_n)
addr[9:0] <= ma[9:0];
assign cas_n = ucas_n & lcas_n;
always @(negedge cas_n)
begin
addr[19:10] <= ma[9:0];
end
always @(posedge cas_n, negedge cas_n)
ready <= ~cas_n; // to introduce delta-cycle in ready to allow capturing of CAS address before proceeding data
assign idle = ras_n & cas_n;
always @(negedge ras_n, posedge idle)
begin
if( idle )
was_ras <= 1'b0;
else // negedge ras_n
was_ras <= 1'b1;
end
always @(negedge cas_n, posedge idle)
begin
if( idle )
was_cas <= 1'b0;
else
if( was_ras )
was_cas <= 1'b1;
end
assign d = dout;
always @*
begin
if( ready && was_ras && was_cas && we_n && (~idle) ) // idle here is to prevent races at the end of all previous signals, which cause redundant read at the end of write
begin
dout = array[addr];
`ifdef DRAMMEM_VERBOSE
if( _verbose_ == 1 )
begin
if( addr != _filter_out_ )
$display("DRAM read at %t: ($%h)=>$%h",$time,addr*2+_add_to_addr_,dout);
end
`endif
end
else
begin
dout = 16'hZZZZ;
end
end
always @*
if( ready && was_ras && was_cas && (~we_n) && (~idle) )
begin
if( ~ucas_n )
array[addr][15:8] = d[15:8];
if( ~lcas_n )
array[addr][7:0] = d[7:0];
`ifdef DRAMMEM_VERBOSE
if( _verbose_ == 1 )
begin
if( addr != _filter_out_ )
$display("DRAM written at %t: ($%h)<=$%h.$%h",$time,addr*2+_add_to_addr_,ucas_n?8'hXX:d[15:8],lcas_n?8'hXX:d[7:0]);
end
`endif
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_protocol_converter_v2_1_b2s_incr_cmd.v
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_b2s_incr_cmd #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of AxADDR
// Range: 32.
parameter integer C_AXI_ADDR_WIDTH = 32
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk ,
input wire reset ,
input wire [C_AXI_ADDR_WIDTH-1:0] axaddr ,
input wire [7:0] axlen ,
input wire [2:0] axsize ,
// axhandshake = axvalid & axready
input wire axhandshake ,
output wire [C_AXI_ADDR_WIDTH-1:0] cmd_byte_addr ,
// Connections to/from fsm module
// signal to increment to the next mc transaction
input wire next ,
// signal to the fsm there is another transaction required
output reg next_pending
);
////////////////////////////////////////////////////////////////////////////////
// Wire and register declarations
////////////////////////////////////////////////////////////////////////////////
reg sel_first;
reg [11:0] axaddr_incr;
reg [8:0] axlen_cnt;
reg next_pending_r;
wire [3:0] axsize_shift;
wire [11:0] axsize_mask;
localparam L_AXI_ADDR_LOW_BIT = (C_AXI_ADDR_WIDTH >= 12) ? 12 : 11;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// calculate cmd_byte_addr
generate
if (C_AXI_ADDR_WIDTH > 12) begin : ADDR_GT_4K
assign cmd_byte_addr = (sel_first) ? axaddr : {axaddr[C_AXI_ADDR_WIDTH-1:L_AXI_ADDR_LOW_BIT],axaddr_incr[11:0]};
end else begin : ADDR_4K
assign cmd_byte_addr = (sel_first) ? axaddr : axaddr_incr[11:0];
end
endgenerate
assign axsize_shift = (1 << axsize[1:0]);
assign axsize_mask = ~(axsize_shift - 1'b1);
// Incremented version of axaddr
always @(posedge clk) begin
if (sel_first) begin
if(~next) begin
axaddr_incr <= axaddr[11:0] & axsize_mask;
end else begin
axaddr_incr <= (axaddr[11:0] & axsize_mask) + axsize_shift;
end
end else if (next) begin
axaddr_incr <= axaddr_incr + axsize_shift;
end
end
always @(posedge clk) begin
if (axhandshake)begin
axlen_cnt <= axlen;
next_pending_r <= (axlen >= 1);
end else if (next) begin
if (axlen_cnt > 1) begin
axlen_cnt <= axlen_cnt - 1;
next_pending_r <= ((axlen_cnt - 1) >= 1);
end else begin
axlen_cnt <= 9'd0;
next_pending_r <= 1'b0;
end
end
end
always @( * ) begin
if (axhandshake)begin
next_pending = (axlen >= 1);
end else if (next) begin
if (axlen_cnt > 1) begin
next_pending = ((axlen_cnt - 1) >= 1);
end else begin
next_pending = 1'b0;
end
end else begin
next_pending = next_pending_r;
end
end
// last and ignore signals to data channel. These signals are used for
// BL8 to ignore and insert data for even len transactions with offset
// and odd len transactions
// For odd len transactions with no offset the last read is ignored and
// last write is masked
// For odd len transactions with offset the first read is ignored and
// first write is masked
// For even len transactions with offset the last & first read is ignored and
// last& first write is masked
// For even len transactions no ingnores or masks.
// Indicates if we are on the first transaction of a mc translation with more
// than 1 transaction.
always @(posedge clk) begin
if (reset | axhandshake) begin
sel_first <= 1'b1;
end else if (next) begin
sel_first <= 1'b0;
end
end
endmodule
`default_nettype wire
|
/*---------------------------------------------------------------------------------------------------------------------
-- Author: Peter Hasza, [email protected]
--
-- Create Date: 04/02/2017
-- Module Name: regs_mod
-- Project Name: AXI_SPI_IF
-- Description:
-- Modole register instantiations
--
------------------------------ REVISION HISTORY -----------------------------------------------------------------------
--
-- 2017.apr.19 | hp3265 || Initial version
--
-----------------------------------------------------------------------------------------------------------------------*/
module regs_mod (
/* System Clock & Reset */
input clk_i, // System clock
input reset_n_i, // System asynchronous reset
/* Interface from System */
input spi_busy_i,
input trans_start_i,
input rx_empty_i,
input tx_full_i,
/* Interface towards APB Slave */
output [31:0] reg_control_o,
output [31:0] reg_trans_ctrl_o,
output [31:0] reg_status_o,
input [31:0] reg_data_i,
input reg_load_i,
input [1:0] reg_sel_i
);
/*=============================================================================================
-- Control Register | R(h)W
--=============================================================================================*/
// spi_clk_div | 3:0 || Clock ratio AXI / SPI || reset value : 1
// reserved | 7:4 || default 0 || reset value : 0
// data_order | 8:8 || 1: MSB first, 0: LSB first || reset value : 0
// CPOL | 9:9 || 1: SCLK HIGH in IDLE, 0: SCLK LOW in IDLE || reset value : 0
// CPHA | 10:10 || 1: Leading edge setup, Trailing edge sample
// 0: Leading edge sample, Trailing edge setup || reset value : 0
// reserved | 31:11 || default 0 || reset value : 0
reg [11:0] axi_spi_ctrl_reg;
always @ (posedge clk_i, negedge reset_n_i)
begin
if (!reset_n_i)
begin
axi_spi_ctrl_reg <= 32'd1;
end
else
if (reg_load_i & (reg_sel_i == 2'b0))
begin
axi_spi_ctrl_reg[10:8] <= reg_data_i[10:8];
axi_spi_ctrl_reg[3:0] <= reg_data_i[3:0];
end
end;
assign reg_control_o = {21'd0, axi_spi_ctrl_reg};
/*=============================================================================================
-- Transfer Control Register | R(h)W
--=============================================================================================*/
// slv_0_en | 0:0 || SS 0 enable (0 disable, 1 enable) || reset value : 0
// slv_1_en | 1:1 || SS 1 enable (0 disable, 1 enable) || reset value : 0
// slv_2_en | 2:2 || SS 2 enable (0 disable, 1 enable) || reset value : 0
// slv_3_en | 3:3 || SS 3 enable (0 disable, 1 enable) || reset value : 0
// reserved | 4:4 || default 0 || reset value : 0
// Bits per trans| 6:5 || Num of bits per tranfer || reset value : 0
// 00 - 8 default
// 01 - 16
// 10 - 32
// 11 - ignored
// reserved | 12:7 || default 0 || reset value : 0
// trans_start | 13:13 || 1: Transfer is ready to start, 0: IDLE || reset value : 0
// reserved | 31:14 || default 0 || reset value : 0
reg [13:0] trans_ctrl_reg;
always @ (posedge clk_i, negedge reset_n_i)
begin
if (!reset_n_i)
begin
trans_ctrl_reg <= 14'd0;
end
else
if (trans_start_i)
begin
trans_ctrl_reg <= trans_ctrl_reg &14'b01_1111_1111_1111;
end
else if (reg_load_i & (reg_sel_i == 2'b1))
begin
trans_ctrl_reg[3:0] <= reg_data_i[3:0];
trans_ctrl_reg[6:5] <= reg_data_i[6:5];
trans_ctrl_reg[13:13] <= reg_data_i[13:13];
end
end;
assign reg_trans_ctrl_o = {18'd0, trans_ctrl_reg};
/*=============================================================================================
-- Status Register | Read Only
--=============================================================================================*/
// spi_busy | 0:0 || Signals ongoing SPI transfer (0 idle, 1 busy) || reset value : 0
// rx_fifo_empty| 1:1 || SPI RD buffer empty at RD access || reset value : 0
// tx_fifo_full | 2:2 || SPI WR buffer full at WR access || reset value : 0
// reserved | 31:3 || default 0 || reset value : 0
reg [2:0] status_reg;
always @ (posedge clk_i, negedge reset_n_i)
begin
if (!reset_n_i)
begin
status_reg <= 0;
end
else
begin
status_reg[0] <= spi_busy_i;
status_reg[1] <= rx_empty_i;
status_reg[2] <= tx_full_i;
end
end;
assign reg_status_o = {29'd0, status_reg};
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A22O_BLACKBOX_V
`define SKY130_FD_SC_HDLL__A22O_BLACKBOX_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a22o (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A22O_BLACKBOX_V
|
module ts_pad (
inout wire pad,
input wire oe,
input wire op
);
assign pad = oe ? op : 1'bz;
endmodule
module test();
wire [1:0] bus;
reg oe1 = 1'b0;
reg oe2 = 1'b0;
reg oe3 = 1'b0;
reg oe4 = 1'b0;
reg oe5 = 1'b0;
reg oe6 = 1'b0;
wire op1 = 1'b0;
wire op2 = 1'b1;
wire op3 = 1'b1;
wire op4 = 1'b0;
wire op5 = 1'bx;
wire op6 = 1'bx;
ts_pad pad1(bus[0], oe1, op1);
ts_pad pad2(bus[1], oe2, op2);
ts_pad pad3(bus[0], oe3, op3);
ts_pad pad4(bus[1], oe4, op4);
bufif1(bus[0], op5, oe5);
bufif1(bus[1], op6, oe6);
integer multi;
integer forced;
integer countD;
integer count0;
integer count1;
integer countX;
reg failed = 0;
task check_results;
input integer expected_multi;
input integer expected_forced;
input integer expected_countD;
input integer expected_count0;
input integer expected_count1;
input integer expected_countX;
begin
$write("multi = %0d ", multi);
if (multi !== expected_multi) failed = 1;
if (expected_forced != -1) begin
$write("forced = %0d ", forced);
if (forced !== expected_forced) failed = 1;
end
if (expected_countD != -1) begin
$write("countD = %0d ", countD);
if (countD !== expected_countD) failed = 1;
end
if (expected_count0 != -1) begin
$write("count0 = %0d ", count0);
if (count0 !== expected_count0) failed = 1;
end
if (expected_count1 != -1) begin
$write("count1 = %0d ", count1);
if (count1 !== expected_count1) failed = 1;
end
if (expected_countX != -1) begin
$write("countX = %0d ", countX);
if (countX !== expected_countX) failed = 1;
end
$write("\n");
end
endtask
initial begin
#1;
multi = $countdrivers(bus[0], forced, countD, count0, count1, countX);
check_results(0, 0, 0, 0, 0, 0);
multi = $countdrivers(bus[1], forced, countD, count0, count1, countX);
check_results(0, 0, 0, 0, 0, 0);
multi = $countdrivers(pad1.pad, forced, countD, count0, count1, countX);
check_results(0, 0, 0, 0, 0, 0);
multi = $countdrivers(pad2.pad, forced, countD, count0, count1, countX);
check_results(0, 0, 0, 0, 0, 0);
$display("");
oe1 = 1'b1;
#1;
multi = $countdrivers(bus[0], forced, countD, count0, count1, countX);
check_results(0, 0, 1, 1, 0, 0);
multi = $countdrivers(bus[1], forced, countD, count0, count1, countX);
check_results(0, 0, 0, 0, 0, 0);
multi = $countdrivers(pad1.pad, forced, countD, count0, count1, countX);
check_results(0, 0, 1, 1, 0, 0);
multi = $countdrivers(pad2.pad, forced, countD, count0, count1, countX);
check_results(0, 0, 0, 0, 0, 0);
$display("");
oe2 = 1'b1;
#1;
multi = $countdrivers(bus[0], forced, countD, count0, count1, countX);
check_results(0, 0, 1, 1, 0, 0);
multi = $countdrivers(bus[1], forced, countD, count0, count1, countX);
check_results(0, 0, 1, 0, 1, 0);
multi = $countdrivers(pad1.pad, forced, countD, count0, count1, countX);
check_results(0, 0, 1, 1, 0, 0);
multi = $countdrivers(pad2.pad, forced, countD, count0, count1, countX);
check_results(0, 0, 1, 0, 1, 0);
$display("");
oe3 = 1'b1;
#1;
multi = $countdrivers(bus[0], forced, countD, count0, count1, countX);
check_results(1, 0, 2, 1, 1, 0);
multi = $countdrivers(bus[1], forced, countD, count0, count1, countX);
check_results(0, 0, 1, 0, 1, 0);
multi = $countdrivers(pad1.pad, forced, countD, count0, count1, countX);
check_results(1, 0, 2, 1, 1, 0);
multi = $countdrivers(pad2.pad, forced, countD, count0, count1, countX);
check_results(0, 0, 1, 0, 1, 0);
$display("");
oe4 = 1'b1;
#1;
multi = $countdrivers(bus[0], forced, countD, count0, count1, countX);
check_results(1, 0, 2, 1, 1, 0);
multi = $countdrivers(bus[1], forced, countD, count0, count1, countX);
check_results(1, 0, 2, 1, 1, 0);
multi = $countdrivers(pad1.pad, forced, countD, count0, count1, countX);
check_results(1, 0, 2, 1, 1, 0);
multi = $countdrivers(pad2.pad, forced, countD, count0, count1, countX);
check_results(1, 0, 2, 1, 1, 0);
$display("");
oe5 = 1'b1;
#1;
multi = $countdrivers(bus[0], forced, countD, count0, count1, countX);
check_results(1, 0, 3, 1, 1, 1);
multi = $countdrivers(bus[1], forced, countD, count0, count1, countX);
check_results(1, 0, 2, 1, 1, 0);
multi = $countdrivers(pad1.pad, forced, countD, count0, count1, countX);
check_results(1, 0, 3, 1, 1, 1);
multi = $countdrivers(pad2.pad, forced, countD, count0, count1, countX);
check_results(1, 0, 2, 1, 1, 0);
$display("");
oe6 = 1'b1;
#1;
multi = $countdrivers(bus[0], forced, countD, count0, count1, countX);
check_results(1, 0, 3, 1, 1, 1);
multi = $countdrivers(bus[1], forced, countD, count0, count1, countX);
check_results(1, 0, 3, 1, 1, 1);
multi = $countdrivers(pad1.pad, forced, countD, count0, count1, countX);
check_results(1, 0, 3, 1, 1, 1);
multi = $countdrivers(pad2.pad, forced, countD, count0, count1, countX);
check_results(1, 0, 3, 1, 1, 1);
$display("");
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A221OI_TB_V
`define SKY130_FD_SC_LP__A221OI_TB_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a221oi.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg C1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 C1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 B1 = 1'b1;
#260 B2 = 1'b1;
#280 C1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 B1 = 1'b0;
#440 B2 = 1'b0;
#460 C1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 C1 = 1'b1;
#660 B2 = 1'b1;
#680 B1 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 C1 = 1'bx;
#840 B2 = 1'bx;
#860 B1 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_lp__a221oi dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A221OI_TB_V
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: PA.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 18.1.0 Build 625 09/12/2018 SJ Lite Edition
// ************************************************************
//Copyright (C) 2018 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module PA (
clock,
data,
rdaddress,
wraddress,
wren,
q);
input clock;
input [7:0] data;
input [7:0] rdaddress;
input [7:0] wraddress;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({8{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 256,
altsyncram_component.numwords_b = 256,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 8,
altsyncram_component.widthad_b = 8,
altsyncram_component.width_a = 8,
altsyncram_component.width_b = 8,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "2048"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: USED_PORT: rdaddress 0 0 8 0 INPUT NODEFVAL "rdaddress[7..0]"
// Retrieval info: USED_PORT: wraddress 0 0 8 0 INPUT NODEFVAL "wraddress[7..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
// Retrieval info: CONNECT: @address_a 0 0 8 0 wraddress 0 0 8 0
// Retrieval info: CONNECT: @address_b 0 0 8 0 rdaddress 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_b 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL PA.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL PA.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL PA.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL PA.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL PA_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL PA_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// Copyright (C) 1991-2011 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// Quartus II 11.1 Build 216 11/01/2011
// ********** PRIMITIVE DEFINITIONS **********
`timescale 1 ps/1 ps
// ***** DFFE
primitive CYCLONE_PRIM_DFFE (Q, ENA, D, CLK, CLRN, PRN, notifier);
input D;
input CLRN;
input PRN;
input CLK;
input ENA;
input notifier;
output Q; reg Q;
initial Q = 1'b0;
table
// ENA D CLK CLRN PRN notifier : Qt : Qt+1
(??) ? ? 1 1 ? : ? : -; // pessimism
x ? ? 1 1 ? : ? : -; // pessimism
1 1 (01) 1 1 ? : ? : 1; // clocked data
1 1 (01) 1 x ? : ? : 1; // pessimism
1 1 ? 1 x ? : 1 : 1; // pessimism
1 0 0 1 x ? : 1 : 1; // pessimism
1 0 x 1 (?x) ? : 1 : 1; // pessimism
1 0 1 1 (?x) ? : 1 : 1; // pessimism
1 x 0 1 x ? : 1 : 1; // pessimism
1 x x 1 (?x) ? : 1 : 1; // pessimism
1 x 1 1 (?x) ? : 1 : 1; // pessimism
1 0 (01) 1 1 ? : ? : 0; // clocked data
1 0 (01) x 1 ? : ? : 0; // pessimism
1 0 ? x 1 ? : 0 : 0; // pessimism
0 ? ? x 1 ? : ? : -;
1 1 0 x 1 ? : 0 : 0; // pessimism
1 1 x (?x) 1 ? : 0 : 0; // pessimism
1 1 1 (?x) 1 ? : 0 : 0; // pessimism
1 x 0 x 1 ? : 0 : 0; // pessimism
1 x x (?x) 1 ? : 0 : 0; // pessimism
1 x 1 (?x) 1 ? : 0 : 0; // pessimism
// 1 1 (x1) 1 1 ? : 1 : 1; // reducing pessimism
// 1 0 (x1) 1 1 ? : 0 : 0;
1 ? (x1) 1 1 ? : ? : -; // spr 80166-ignore
// x->1 edge
1 1 (0x) 1 1 ? : 1 : 1;
1 0 (0x) 1 1 ? : 0 : 0;
? ? ? 0 0 ? : ? : 0; // clear wins preset
? ? ? 0 1 ? : ? : 0; // asynch clear
? ? ? 1 0 ? : ? : 1; // asynch set
1 ? (?0) 1 1 ? : ? : -; // ignore falling clock
1 ? (1x) 1 1 ? : ? : -; // ignore falling clock
1 * ? ? ? ? : ? : -; // ignore data edges
1 ? ? (?1) ? ? : ? : -; // ignore edges on
1 ? ? ? (?1) ? : ? : -; // set and clear
0 ? ? 1 1 ? : ? : -; // set and clear
? ? ? 1 1 * : ? : x; // spr 36954 - at any
// notifier event,
// output 'x'
endtable
endprimitive
primitive CYCLONE_PRIM_DFFEAS (q, d, clk, ena, clr, pre, ald, adt, sclr, sload, notifier );
input d,clk,ena,clr,pre,ald,adt,sclr,sload, notifier;
output q;
reg q;
initial
q = 1'b0;
table
////d,clk, ena,clr,pre,ald,adt,sclr,sload,notifier: q : q'
? ? ? 1 ? ? ? ? ? ? : ? : 0; // aclr
? ? ? 0 1 ? ? ? ? ? : ? : 1; // apre
? ? ? 0 0 1 0 ? ? ? : ? : 0; // aload 0
? ? ? 0 0 1 1 ? ? ? : ? : 1; // aload 1
0 (01) 1 0 0 0 ? 0 0 ? : ? : 0; // din 0
1 (01) 1 0 0 0 ? 0 0 ? : ? : 1; // din 1
? (01) 1 0 0 0 ? 1 ? ? : ? : 0; // sclr
? (01) 1 0 0 0 0 0 1 ? : ? : 0; // sload 0
? (01) 1 0 0 0 1 0 1 ? : ? : 1; // sload 1
? ? 0 0 0 0 ? ? ? ? : ? : -; // no asy no ena
* ? ? ? ? ? ? ? ? ? : ? : -; // data edges
? (?0) ? ? ? ? ? ? ? ? : ? : -; // ignore falling clk
? ? * ? ? ? ? ? ? ? : ? : -; // enable edges
? ? ? (?0)? ? ? ? ? ? : ? : -; // falling asynchs
? ? ? ? (?0) ? ? ? ? ? : ? : -;
? ? ? ? ? (?0) ? ? ? ? : ? : -;
? ? ? ? ? 0 * ? ? ? : ? : -; // ignore adata edges when not aloading
? ? ? ? ? ? ? * ? ? : ? : -; // sclr edges
? ? ? ? ? ? ? ? * ? : ? : -; // sload edges
? (x1) 1 0 0 0 ? 0 0 ? : ? : -; // ignore x->1 transition of clock
? ? 1 0 0 x ? 0 0 ? : ? : -; // ignore x input of aload
? ? ? 1 1 ? ? ? ? * : ? : x; // at any notifier event, output x
endtable
endprimitive
primitive CYCLONE_PRIM_DFFEAS_HIGH (q, d, clk, ena, clr, pre, ald, adt, sclr, sload, notifier );
input d,clk,ena,clr,pre,ald,adt,sclr,sload, notifier;
output q;
reg q;
initial
q = 1'b1;
table
////d,clk, ena,clr,pre,ald,adt,sclr,sload,notifier : q : q'
? ? ? 1 ? ? ? ? ? ? : ? : 0; // aclr
? ? ? 0 1 ? ? ? ? ? : ? : 1; // apre
? ? ? 0 0 1 0 ? ? ? : ? : 0; // aload 0
? ? ? 0 0 1 1 ? ? ? : ? : 1; // aload 1
0 (01) 1 0 0 0 ? 0 0 ? : ? : 0; // din 0
1 (01) 1 0 0 0 ? 0 0 ? : ? : 1; // din 1
? (01) 1 0 0 0 ? 1 ? ? : ? : 0; // sclr
? (01) 1 0 0 0 0 0 1 ? : ? : 0; // sload 0
? (01) 1 0 0 0 1 0 1 ? : ? : 1; // sload 1
? ? 0 0 0 0 ? ? ? ? : ? : -; // no asy no ena
* ? ? ? ? ? ? ? ? ? : ? : -; // data edges
? (?0) ? ? ? ? ? ? ? ? : ? : -; // ignore falling clk
? ? * ? ? ? ? ? ? ? : ? : -; // enable edges
? ? ? (?0)? ? ? ? ? ? : ? : -; // falling asynchs
? ? ? ? (?0) ? ? ? ? ? : ? : -;
? ? ? ? ? (?0) ? ? ? ? : ? : -;
? ? ? ? ? 0 * ? ? ? : ? : -; // ignore adata edges when not aloading
? ? ? ? ? ? ? * ? ? : ? : -; // sclr edges
? ? ? ? ? ? ? ? * ? : ? : -; // sload edges
? (x1) 1 0 0 0 ? 0 0 ? : ? : -; // ignore x->1 transition of clock
? ? 1 0 0 x ? 0 0 ? : ? : -; // ignore x input of aload
? ? ? 1 1 ? ? ? ? * : ? : x; // at any notifier event, output x
endtable
endprimitive
module cyclone_dffe ( Q, CLK, ENA, D, CLRN, PRN );
input D;
input CLK;
input CLRN;
input PRN;
input ENA;
output Q;
wire D_ipd;
wire ENA_ipd;
wire CLK_ipd;
wire PRN_ipd;
wire CLRN_ipd;
buf (D_ipd, D);
buf (ENA_ipd, ENA);
buf (CLK_ipd, CLK);
buf (PRN_ipd, PRN);
buf (CLRN_ipd, CLRN);
wire legal;
reg viol_notifier;
CYCLONE_PRIM_DFFE ( Q, ENA_ipd, D_ipd, CLK_ipd, CLRN_ipd, PRN_ipd, viol_notifier );
and(legal, ENA_ipd, CLRN_ipd, PRN_ipd);
specify
specparam TREG = 0;
specparam TREN = 0;
specparam TRSU = 0;
specparam TRH = 0;
specparam TRPR = 0;
specparam TRCL = 0;
$setup ( D, posedge CLK &&& legal, TRSU, viol_notifier ) ;
$hold ( posedge CLK &&& legal, D, TRH, viol_notifier ) ;
$setup ( ENA, posedge CLK &&& legal, TREN, viol_notifier ) ;
$hold ( posedge CLK &&& legal, ENA, 0, viol_notifier ) ;
( negedge CLRN => (Q +: 1'b0)) = ( TRCL, TRCL) ;
( negedge PRN => (Q +: 1'b1)) = ( TRPR, TRPR) ;
( posedge CLK => (Q +: D)) = ( TREG, TREG) ;
endspecify
endmodule
// ***** cyclone_mux21
module cyclone_mux21 (MO, A, B, S);
input A, B, S;
output MO;
wire A_in;
wire B_in;
wire S_in;
buf(A_in, A);
buf(B_in, B);
buf(S_in, S);
wire tmp_MO;
specify
(A => MO) = (0, 0);
(B => MO) = (0, 0);
(S => MO) = (0, 0);
endspecify
assign tmp_MO = (S_in == 1) ? B_in : A_in;
buf (MO, tmp_MO);
endmodule
// ***** cyclone_mux41
module cyclone_mux41 (MO, IN0, IN1, IN2, IN3, S);
input IN0;
input IN1;
input IN2;
input IN3;
input [1:0] S;
output MO;
wire IN0_in;
wire IN1_in;
wire IN2_in;
wire IN3_in;
wire S1_in;
wire S0_in;
buf(IN0_in, IN0);
buf(IN1_in, IN1);
buf(IN2_in, IN2);
buf(IN3_in, IN3);
buf(S1_in, S[1]);
buf(S0_in, S[0]);
wire tmp_MO;
specify
(IN0 => MO) = (0, 0);
(IN1 => MO) = (0, 0);
(IN2 => MO) = (0, 0);
(IN3 => MO) = (0, 0);
(S[1] => MO) = (0, 0);
(S[0] => MO) = (0, 0);
endspecify
assign tmp_MO = S1_in ? (S0_in ? IN3_in : IN2_in) : (S0_in ? IN1_in : IN0_in);
buf (MO, tmp_MO);
endmodule
// ***** cyclone_and1
module cyclone_and1 (Y, IN1);
input IN1;
output Y;
specify
(IN1 => Y) = (0, 0);
endspecify
buf (Y, IN1);
endmodule
// ***** cyclone_and16
module cyclone_and16 (Y, IN1);
input [15:0] IN1;
output [15:0] Y;
specify
(IN1 => Y) = (0, 0);
endspecify
buf (Y[0], IN1[0]);
buf (Y[1], IN1[1]);
buf (Y[2], IN1[2]);
buf (Y[3], IN1[3]);
buf (Y[4], IN1[4]);
buf (Y[5], IN1[5]);
buf (Y[6], IN1[6]);
buf (Y[7], IN1[7]);
buf (Y[8], IN1[8]);
buf (Y[9], IN1[9]);
buf (Y[10], IN1[10]);
buf (Y[11], IN1[11]);
buf (Y[12], IN1[12]);
buf (Y[13], IN1[13]);
buf (Y[14], IN1[14]);
buf (Y[15], IN1[15]);
endmodule
// ***** cyclone_bmux21
module cyclone_bmux21 (MO, A, B, S);
input [15:0] A, B;
input S;
output [15:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
// ***** cyclone_b17mux21
module cyclone_b17mux21 (MO, A, B, S);
input [16:0] A, B;
input S;
output [16:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
// ***** cyclone_nmux21
module cyclone_nmux21 (MO, A, B, S);
input A, B, S;
output MO;
assign MO = (S == 1) ? ~B : ~A;
endmodule
// ***** cyclone_b5mux21
module cyclone_b5mux21 (MO, A, B, S);
input [4:0] A, B;
input S;
output [4:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
// ********** END PRIMITIVE DEFINITIONS **********
///////////////////////////////////////////////////////////////////////
//
// Module Name : cyclone_asynch_lcell
//
// Description : Verilog simulation model for asynchronous LUT based
// module in Cyclone Lcell.
//
///////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module cyclone_asynch_lcell (
dataa,
datab,
datac,
datad,
cin,
cin0,
cin1,
inverta,
qfbkin,
regin,
combout,
cout,
cout0,
cout1
);
parameter operation_mode = "normal" ;
parameter sum_lutc_input = "datac";
parameter lut_mask = "ffff" ;
parameter cin_used = "false";
parameter cin0_used = "false";
parameter cin1_used = "false";
// INPUT PORTS
input dataa;
input datab;
input datac;
input datad ;
input cin;
input cin0;
input cin1;
input inverta;
input qfbkin;
// OUTPUT PORTS
output combout;
output cout;
output cout0;
output cout1;
output regin;
// INTERNAL VARIABLES
reg icout;
reg icout0;
reg icout1;
reg data;
reg lut_data;
reg inverta_dataa;
reg [15:0] bin_mask;
integer iop_mode;
reg [1:0] isum_lutc_input;
reg icin_used;
reg icin0_used;
reg icin1_used;
wire qfbk_mode;
// INPUT BUFFERS
wire idataa;
wire idatab;
wire idatac;
wire idatad;
wire icin;
wire icin0;
wire icin1;
wire iinverta;
buf (idataa, dataa);
buf (idatab, datab);
buf (idatac, datac);
buf (idatad, datad);
buf (icin, cin);
buf (icin0, cin0);
buf (icin1, cin1);
buf (iinverta, inverta);
assign qfbk_mode = (sum_lutc_input == "qfbk") ? 1'b1 : 1'b0;
specify
(dataa => combout) = (0, 0) ;
(datab => combout) = (0, 0) ;
(datac => combout) = (0, 0) ;
(datad => combout) = (0, 0) ;
(cin => combout) = (0, 0) ;
(cin0 => combout) = (0, 0) ;
(cin1 => combout) = (0, 0) ;
(inverta => combout) = (0, 0) ;
if (qfbk_mode == 1'b1)
(qfbkin => combout) = (0, 0) ;
(dataa => cout) = (0, 0);
(datab => cout) = (0, 0);
(cin => cout) = (0, 0) ;
(cin0 => cout) = (0, 0) ;
(cin1 => cout) = (0, 0) ;
(inverta => cout) = (0, 0);
(dataa => cout0) = (0, 0);
(datab => cout0) = (0, 0);
(cin0 => cout0) = (0, 0) ;
(inverta => cout0) = (0, 0);
(dataa => cout1) = (0, 0);
(datab => cout1) = (0, 0);
(cin1 => cout1) = (0, 0) ;
(inverta => cout1) = (0, 0);
(dataa => regin) = (0, 0) ;
(datab => regin) = (0, 0) ;
(datac => regin) = (0, 0) ;
(datad => regin) = (0, 0) ;
(cin => regin) = (0, 0) ;
(cin0 => regin) = (0, 0) ;
(cin1 => regin) = (0, 0) ;
(inverta => regin) = (0, 0) ;
if (qfbk_mode == 1'b1)
(qfbkin => regin) = (0, 0) ;
endspecify
function [16:1] str_to_bin ;
input [8*4:1] s;
reg [8*4:1] reg_s;
reg [4:1] digit [8:1];
reg [8:1] tmp;
integer m;
integer ivalue ;
begin
ivalue = 0;
reg_s = s;
for (m=1; m<=4; m= m+1 )
begin
tmp = reg_s[32:25];
digit[m] = tmp & 8'b00001111;
reg_s = reg_s << 8;
if (tmp[7] == 'b1)
digit[m] = digit[m] + 9;
end
str_to_bin = {digit[1], digit[2], digit[3], digit[4]};
end
endfunction
// 4-input LUT function
function lut4;
input [15:0] mask;
input dataa;
input datab;
input datac;
input datad;
begin
lut4 = datad ? ( datac ? ( datab ? ( dataa ? mask[15] : mask[14])
: ( dataa ? mask[13] : mask[12]))
: ( datab ? ( dataa ? mask[11] : mask[10])
: ( dataa ? mask[ 9] : mask[ 8])))
: ( datac ? ( datab ? ( dataa ? mask[ 7] : mask[ 6])
: ( dataa ? mask[ 5] : mask[ 4]))
: ( datab ? ( dataa ? mask[ 3] : mask[ 2])
: ( dataa ? mask[ 1] : mask[ 0])));
end
endfunction
initial
begin
bin_mask = str_to_bin(lut_mask);
if (operation_mode == "normal")
iop_mode = 0; // normal mode
else if (operation_mode == "arithmetic")
iop_mode = 1; // arithmetic mode
else
begin
$display ("Error: Invalid operation_mode specified\n");
$display ("Time: %0t Instance: %m", $time);
iop_mode = 2;
end
if (sum_lutc_input == "datac")
isum_lutc_input = 0;
else if (sum_lutc_input == "cin")
isum_lutc_input = 1;
else if (sum_lutc_input == "qfbk")
isum_lutc_input = 2;
else
begin
$display ("Error: Invalid sum_lutc_input specified\n");
$display ("Time: %0t Instance: %m", $time);
isum_lutc_input = 3;
end
if (cin_used == "true")
icin_used = 1;
else if (cin_used == "false")
icin_used = 0;
if (cin0_used == "true")
icin0_used = 1;
else if (cin0_used == "false")
icin0_used = 0;
if (cin1_used == "true")
icin1_used = 1;
else if (cin1_used == "false")
icin1_used = 0;
end
always @(idatad or idatac or idatab or idataa or icin or
icin0 or icin1 or iinverta or qfbkin)
begin
if (iinverta === 'b1) //invert dataa
inverta_dataa = !idataa;
else
inverta_dataa = idataa;
if (iop_mode == 0) // normal mode
begin
if (isum_lutc_input == 0) // datac
begin
data = lut4(bin_mask, inverta_dataa, idatab,
idatac, idatad);
end
else if (isum_lutc_input == 1) // cin
begin
if (icin0_used == 1 || icin1_used == 1)
begin
if (icin_used == 1)
data = (icin === 'b0) ?
lut4(bin_mask,
inverta_dataa,
idatab,
icin0,
idatad) :
lut4(bin_mask,
inverta_dataa,
idatab,
icin1,
idatad);
else // if cin is not used then inverta
// should be used in place of cin
data = (iinverta === 'b0) ?
lut4(bin_mask,
inverta_dataa,
idatab,
icin0,
idatad) :
lut4(bin_mask,
inverta_dataa,
idatab,
icin1,
idatad);
end
else
data = lut4(bin_mask, inverta_dataa, idatab,
icin, idatad);
end
else if(isum_lutc_input == 2) // qfbk
begin
data = lut4(bin_mask, inverta_dataa, idatab,
qfbkin, idatad);
end
end
else if (iop_mode == 1) // arithmetic mode
begin
// sum LUT
if (isum_lutc_input == 0) // datac
begin
data = lut4(bin_mask, inverta_dataa, idatab,
idatac, 'b1);
end
else if (isum_lutc_input == 1) // cin
begin
if (icin0_used == 1 || icin1_used == 1)
begin
if (icin_used == 1)
data = (icin === 'b0) ?
lut4(bin_mask,
inverta_dataa,
idatab,
icin0,
'b1) :
lut4(bin_mask,
inverta_dataa,
idatab,
icin1,
'b1);
else // if cin is not used then inverta
// should be used in place of cin
data = (iinverta === 'b0) ?
lut4(bin_mask,
inverta_dataa,
idatab,
icin0,
'b1) :
lut4(bin_mask,
inverta_dataa,
idatab,
icin1,
'b1);
end
else if (icin_used == 1)
data = lut4(bin_mask, inverta_dataa, idatab,
icin, 'b1);
else // cin is not used, inverta is used as cin
data = lut4(bin_mask, inverta_dataa, idatab,
iinverta, 'b1);
end
else if(isum_lutc_input == 2) // qfbk
begin
data = lut4(bin_mask, inverta_dataa, idatab,
qfbkin, 'b1);
end
// carry LUT
icout0 = lut4(bin_mask, inverta_dataa, idatab, icin0, 'b0);
icout1 = lut4(bin_mask, inverta_dataa, idatab, icin1, 'b0);
if (icin_used == 1)
begin
if (icin0_used == 1 || icin1_used == 1)
icout = (icin === 'b0) ? icout0 : icout1;
else
icout = lut4(bin_mask, inverta_dataa, idatab,
icin, 'b0);
end
else // inverta is used in place of cin
begin
if (icin0_used == 1 || icin1_used == 1)
icout = (iinverta === 'b0) ? icout0 : icout1;
else
icout = lut4(bin_mask, inverta_dataa, idatab,
iinverta, 'b0);
end
end
end
and (combout, data, 1'b1) ;
and (cout, icout, 1'b1) ;
and (cout0, icout0, 1'b1) ;
and (cout1, icout1, 1'b1) ;
and (regin, data, 1'b1) ;
endmodule
///////////////////////////////////////////////////////////////////////
//
// Module Name : cyclone_lcell_register
//
// Description : Verilog simulation model for register with control
// signals module in Cyclone Lcell.
//
///////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module cyclone_lcell_register (
clk,
aclr,
aload,
sclr,
sload,
ena,
datain,
datac,
regcascin,
devclrn,
devpor,
regout,
qfbkout
);
parameter synch_mode = "off";
parameter register_cascade_mode = "off";
parameter power_up = "low";
parameter x_on_violation = "on";
// INPUT PORTS
input clk;
input ena;
input aclr;
input aload;
input sclr;
input sload;
input datain;
input datac;
input regcascin;
input devclrn;
input devpor ;
// OUTPUT PORTS
output regout;
output qfbkout;
// INTERNAL VARIABLES
reg iregout;
wire reset;
wire nosload;
reg regcascin_viol;
reg datain_viol, datac_viol;
reg sclr_viol, sload_viol;
reg ena_viol, clk_per_viol;
reg violation;
reg clk_last_value;
reg ipower_up;
reg icascade_mode;
reg isynch_mode;
reg ix_on_violation;
// INPUT BUFFERS
wire clk_in;
wire iaclr;
wire iaload;
wire isclr;
wire isload;
wire iena;
wire idatac;
wire iregcascin;
wire idatain;
buf (clk_in, clk);
buf (iaclr, aclr);
buf (iaload, aload);
buf (isclr, sclr);
buf (isload, sload);
buf (iena, ena);
buf (idatac, datac);
buf (iregcascin, regcascin);
buf (idatain, datain);
assign reset = devpor && devclrn && (!iaclr) && (iena);
assign nosload = reset && (!isload);
specify
$setuphold (posedge clk &&& reset, regcascin, 0, 0, regcascin_viol) ;
$setuphold (posedge clk &&& nosload, datain, 0, 0, datain_viol) ;
$setuphold (posedge clk &&& reset, datac, 0, 0, datac_viol) ;
$setuphold (posedge clk &&& reset, sclr, 0, 0, sclr_viol) ;
$setuphold (posedge clk &&& reset, sload, 0, 0, sload_viol) ;
$setuphold (posedge clk &&& reset, ena, 0, 0, ena_viol) ;
(posedge clk => (regout +: iregout)) = 0 ;
(posedge aclr => (regout +: 1'b0)) = (0, 0) ;
(posedge aload => (regout +: iregout)) = (0, 0) ;
(datac => regout) = (0, 0) ;
(posedge clk => (qfbkout +: iregout)) = 0 ;
(posedge aclr => (qfbkout +: 1'b0)) = (0, 0) ;
(posedge aload => (qfbkout +: iregout)) = (0, 0) ;
(datac => qfbkout) = (0, 0) ;
endspecify
initial
begin
violation = 0;
clk_last_value = 'b0;
if (power_up == "low")
begin
iregout <= 'b0;
ipower_up = 0;
end
else if (power_up == "high")
begin
iregout <= 'b1;
ipower_up = 1;
end
if (register_cascade_mode == "on")
icascade_mode = 1;
else
icascade_mode = 0;
if (synch_mode == "on" )
isynch_mode = 1;
else
isynch_mode = 0;
if (x_on_violation == "on")
ix_on_violation = 1;
else
ix_on_violation = 0;
end
always @ (regcascin_viol or datain_viol or datac_viol or sclr_viol
or sload_viol or ena_viol or clk_per_viol)
begin
if (ix_on_violation == 1)
violation = 1;
end
always @ (clk_in or idatac or iaclr or posedge iaload
or devclrn or devpor or posedge violation)
begin
if (violation == 1'b1)
begin
violation = 0;
iregout <= 'bx;
end
else
begin
if (devpor == 'b0)
begin
if (ipower_up == 0) // "low"
iregout <= 'b0;
else if (ipower_up == 1) // "high"
iregout <= 'b1;
end
else if (devclrn == 'b0)
iregout <= 'b0;
else if (iaclr === 'b1)
iregout <= 'b0 ;
else if (iaload === 'b1)
iregout <= idatac;
else if (iena === 'b1 && clk_in === 'b1 &&
clk_last_value === 'b0)
begin
if (isynch_mode == 1)
begin
if (isclr === 'b1)
iregout <= 'b0 ;
else if (isload === 'b1)
iregout <= idatac;
else if (icascade_mode == 1)
iregout <= iregcascin;
else
iregout <= idatain;
end
else if (icascade_mode == 1)
iregout <= iregcascin;
else
iregout <= idatain;
end
end
clk_last_value = clk_in;
end
and (regout, iregout, 1'b1);
and (qfbkout, iregout, 1'b1);
endmodule
///////////////////////////////////////////////////////////////////////
//
// Module Name : cyclone_lcell
//
// Description : Verilog simulation model for Cyclone Lcell, including
// the following sub module(s):
// 1. cyclone_asynch_lcell
// 2. cyclone_lcell_register
//
///////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module cyclone_lcell (
clk,
dataa,
datab,
datac,
datad,
aclr,
aload,
sclr,
sload,
ena,
cin,
cin0,
cin1,
inverta,
regcascin,
devclrn,
devpor,
combout,
regout,
cout,
cout0,
cout1
);
parameter operation_mode = "normal" ;
parameter synch_mode = "off";
parameter register_cascade_mode = "off";
parameter sum_lutc_input = "datac";
parameter lut_mask = "ffff" ;
parameter power_up = "low";
parameter cin_used = "false";
parameter cin0_used = "false";
parameter cin1_used = "false";
parameter output_mode = "reg_and_comb";
parameter lpm_type = "cyclone_lcell";
parameter x_on_violation = "on";
// INPUT PORTS
input dataa;
input datab;
input datac;
input datad;
input clk;
input aclr;
input aload;
input sclr;
input sload;
input ena;
input cin;
input cin0;
input cin1;
input inverta;
input regcascin;
input devclrn;
input devpor ;
// OUTPUT PORTS
output combout;
output regout;
output cout;
output cout0;
output cout1;
tri1 devclrn;
tri1 devpor;
// INTERNAL VARIABLES
wire dffin, qfbkin;
cyclone_asynch_lcell lecomb (
.dataa(dataa),
.datab(datab),
.datac(datac),
.datad(datad),
.cin(cin),
.cin0(cin0),
.cin1(cin1),
.inverta(inverta),
.qfbkin(qfbkin),
.regin(dffin),
.combout(combout),
.cout(cout),
.cout0(cout0),
.cout1(cout1)
);
defparam lecomb.operation_mode = operation_mode;
defparam lecomb.sum_lutc_input = sum_lutc_input;
defparam lecomb.cin_used = cin_used;
defparam lecomb.cin0_used = cin0_used;
defparam lecomb.cin1_used = cin1_used;
defparam lecomb.lut_mask = lut_mask;
cyclone_lcell_register lereg (
.clk(clk),
.aclr(aclr),
.aload(aload),
.sclr(sclr),
.sload(sload),
.ena(ena),
.datain(dffin),
.datac(datac),
.regcascin(regcascin),
.devclrn(devclrn),
.devpor(devpor),
.regout(regout),
.qfbkout(qfbkin)
);
defparam lereg.synch_mode = synch_mode;
defparam lereg.register_cascade_mode = register_cascade_mode;
defparam lereg.power_up = power_up;
defparam lereg.x_on_violation = x_on_violation;
endmodule
//--------------------------------------------------------------------------
// Module Name : cyclone_ram_pulse_generator
// Description : Generate pulse to initiate memory read/write operations
//--------------------------------------------------------------------------
`timescale 1 ps/1 ps
module cyclone_ram_pulse_generator (
clk,
ena,
pulse,
cycle
);
input clk; // clock
input ena; // pulse enable
output pulse; // pulse
output cycle; // delayed clock
parameter start_delay = 1;
reg state;
reg clk_prev;
wire clk_ipd;
specify
specparam t_decode = 0,t_access = 0;
(posedge clk => (pulse +: state)) = (t_decode,t_access);
endspecify
buf #(start_delay) (clk_ipd,clk);
wire pulse_opd;
buf buf_pulse (pulse,pulse_opd);
initial clk_prev = 1'bx;
always @(clk_ipd or posedge pulse)
begin
if (pulse) state <= 1'b0;
else if (ena && clk_ipd === 1'b1 && clk_prev === 1'b0) state <= 1'b1;
clk_prev = clk_ipd;
end
assign cycle = clk_ipd;
assign pulse_opd = state;
endmodule
//--------------------------------------------------------------------------
// Module Name : cyclone_ram_register
// Description : Register module for RAM inputs/outputs
//--------------------------------------------------------------------------
`timescale 1 ps/1 ps
module cyclone_ram_register (
d,
clk,
aclr,
devclrn,
devpor,
ena,
q,
aclrout
);
parameter width = 1; // data width
parameter preset = 1'b0; // clear acts as preset
input [width - 1:0] d; // data
input clk; // clock
input aclr; // asynch clear
input devclrn,devpor; // device wide clear/reset
input ena; // clock enable
output [width - 1:0] q; // register output
output aclrout; // delayed asynch clear
wire ena_ipd;
wire clk_ipd;
wire aclr_ipd;
wire [width - 1:0] d_ipd;
buf buf_ena (ena_ipd,ena);
buf buf_clk (clk_ipd,clk);
buf buf_aclr (aclr_ipd,aclr);
buf buf_d [width - 1:0] (d_ipd,d);
wire [width - 1:0] q_opd;
buf buf_q [width - 1:0] (q,q_opd);
reg [width - 1:0] q_reg;
reg viol_notifier;
wire reset;
assign reset = devpor && devclrn && (!aclr_ipd) && (ena_ipd);
specify
$setup (d, posedge clk &&& reset, 0, viol_notifier);
$setup (aclr, posedge clk, 0, viol_notifier);
$setup (ena, posedge clk &&& reset, 0, viol_notifier );
$hold (posedge clk &&& reset, d , 0, viol_notifier);
$hold (posedge clk, aclr, 0, viol_notifier);
$hold (posedge clk &&& reset, ena , 0, viol_notifier );
(posedge clk => (q +: q_reg)) = (0,0);
(posedge aclr => (q +: q_reg)) = (0,0);
endspecify
initial q_reg <= (preset) ? {width{1'b1}} : 'b0;
always @(posedge clk_ipd or posedge aclr_ipd or negedge devclrn or negedge devpor)
begin
if (aclr_ipd || ~devclrn || ~devpor)
q_reg <= (preset) ? {width{1'b1}} : 'b0;
else if (ena_ipd)
q_reg <= d_ipd;
end
assign aclrout = aclr_ipd;
assign q_opd = q_reg;
endmodule
`timescale 1 ps/1 ps
`define PRIME 1
`define SEC 0
//--------------------------------------------------------------------------
// Module Name : cyclone_ram_block
// Description : Main RAM module
//--------------------------------------------------------------------------
module cyclone_ram_block
(
portadatain,
portaaddr,
portawe,
portbdatain,
portbaddr,
portbrewe,
clk0, clk1,
ena0, ena1,
clr0, clr1,
portabyteenamasks,
portbbyteenamasks,
devclrn,
devpor,
portadataout,
portbdataout
);
// -------- GLOBAL PARAMETERS ---------
parameter operation_mode = "single_port";
parameter mixed_port_feed_through_mode = "dont_care";
parameter ram_block_type = "auto";
parameter logical_ram_name = "ram_name";
parameter init_file = "init_file.hex";
parameter init_file_layout = "none";
parameter data_interleave_width_in_bits = 1;
parameter data_interleave_offset_in_bits = 1;
parameter port_a_logical_ram_depth = 0;
parameter port_a_logical_ram_width = 0;
parameter port_a_first_address = 0;
parameter port_a_last_address = 0;
parameter port_a_first_bit_number = 0;
parameter port_a_data_out_clear = "none";
parameter port_a_data_out_clock = "none";
parameter port_a_data_width = 1;
parameter port_a_address_width = 1;
parameter port_a_byte_enable_mask_width = 1;
parameter port_b_logical_ram_depth = 0;
parameter port_b_logical_ram_width = 0;
parameter port_b_first_address = 0;
parameter port_b_last_address = 0;
parameter port_b_first_bit_number = 0;
parameter port_b_data_in_clear = "none";
parameter port_b_address_clear = "none";
parameter port_b_read_enable_write_enable_clear = "none";
parameter port_b_byte_enable_clear = "none";
parameter port_b_data_out_clear = "none";
parameter port_b_data_in_clock = "clock1";
parameter port_b_address_clock = "clock1";
parameter port_b_read_enable_write_enable_clock = "clock1";
parameter port_b_byte_enable_clock = "clock1";
parameter port_b_data_out_clock = "none";
parameter port_b_data_width = 1;
parameter port_b_address_width = 1;
parameter port_b_byte_enable_mask_width = 1;
parameter power_up_uninitialized = "false";
parameter lpm_type = "cyclone_ram_block";
parameter lpm_hint = "true";
parameter connectivity_checking = "off";
parameter mem_init0 = 2048'b0;
parameter mem_init1 = 2560'b0;
// SIMULATION_ONLY_PARAMETERS_BEGIN
parameter port_a_data_in_clear = "none";
parameter port_a_address_clear = "none";
parameter port_a_write_enable_clear = "none";
parameter port_a_byte_enable_clear = "none";
parameter port_a_data_in_clock = "clock0";
parameter port_a_address_clock = "clock0";
parameter port_a_write_enable_clock = "clock0";
parameter port_a_byte_enable_clock = "clock0";
// SIMULATION_ONLY_PARAMETERS_END
// LOCAL_PARAMETERS_BEGIN
parameter primary_port_is_a = (port_b_data_width <= port_a_data_width) ? 1'b1 : 1'b0;
parameter primary_port_is_b = ~primary_port_is_a;
parameter mode_is_rom_or_sp = ((operation_mode == "rom") || (operation_mode == "single_port")) ? 1'b1 : 1'b0;
parameter data_width = (primary_port_is_a) ? port_a_data_width : port_b_data_width;
parameter data_unit_width = (mode_is_rom_or_sp | primary_port_is_b) ? port_a_data_width : port_b_data_width;
parameter address_width = (mode_is_rom_or_sp | primary_port_is_b) ? port_a_address_width : port_b_address_width;
parameter address_unit_width = (mode_is_rom_or_sp | primary_port_is_a) ? port_a_address_width : port_b_address_width;
parameter wired_mode = ((port_a_address_width == 1) && (port_a_address_width == port_b_address_width)
&& (port_a_data_width != port_b_data_width));
parameter num_rows = 1 << address_unit_width;
parameter num_cols = (mode_is_rom_or_sp) ? 1 : ( wired_mode ? 2 :
( (primary_port_is_a) ?
1 << (port_b_address_width - port_a_address_width) :
1 << (port_a_address_width - port_b_address_width) ) ) ;
parameter mask_width_prime = (primary_port_is_a) ?
port_a_byte_enable_mask_width : port_b_byte_enable_mask_width;
parameter mask_width_sec = (primary_port_is_a) ?
port_b_byte_enable_mask_width : port_a_byte_enable_mask_width;
parameter byte_size_a = port_a_data_width/port_a_byte_enable_mask_width;
parameter byte_size_b = port_b_data_width/port_b_byte_enable_mask_width;
parameter mode_is_dp = (operation_mode == "dual_port") ? 1'b1 : 1'b0;
// LOCAL_PARAMETERS_END
// -------- PORT DECLARATIONS ---------
input portawe;
input [port_a_data_width - 1:0] portadatain;
input [port_a_address_width - 1:0] portaaddr;
input [port_a_byte_enable_mask_width - 1:0] portabyteenamasks;
input portbrewe;
input [port_b_data_width - 1:0] portbdatain;
input [port_b_address_width - 1:0] portbaddr;
input [port_b_byte_enable_mask_width - 1:0] portbbyteenamasks;
input clr0,clr1;
input clk0,clk1;
input ena0,ena1;
input devclrn,devpor;
output [port_a_data_width - 1:0] portadataout;
output [port_b_data_width - 1:0] portbdataout;
tri0 portawe_int;
assign portawe_int = portawe;
tri0 [port_a_data_width - 1:0] portadatain_int;
assign portadatain_int = portadatain;
tri0 [port_a_address_width - 1:0] portaaddr_int;
assign portaaddr_int = portaaddr;
tri1 [port_a_byte_enable_mask_width - 1:0] portabyteenamasks_int;
assign portabyteenamasks_int = portabyteenamasks;
tri0 portbrewe_int;
assign portbrewe_int = portbrewe;
tri0 [port_b_data_width - 1:0] portbdatain_int;
assign portbdatain_int = portbdatain;
tri0 [port_b_address_width - 1:0] portbaddr_int;
assign portbaddr_int = portbaddr;
tri1 [port_b_byte_enable_mask_width - 1:0] portbbyteenamasks_int;
assign portbbyteenamasks_int = portbbyteenamasks;
tri0 clr0_int,clr1_int;
assign clr0_int = clr0;
assign clr1_int = clr1;
tri0 clk0_int,clk1_int;
assign clk0_int = clk0;
assign clk1_int = clk1;
tri1 ena0_int,ena1_int;
assign ena0_int = ena0;
assign ena1_int = ena1;
tri1 devclrn;
tri1 devpor;
// -------- INTERNAL signals ---------
// clock / clock enable
wire clk_a_in,clk_a_byteena,clk_a_out,clkena_a_out;
wire clk_b_in,clk_b_byteena,clk_b_out,clkena_b_out;
wire write_cycle_a,write_cycle_b;
// asynch clear
wire datain_a_clr,dataout_a_clr,datain_b_clr,dataout_b_clr;
wire addr_a_clr,addr_b_clr;
wire byteena_a_clr,byteena_b_clr;
wire we_a_clr,rewe_b_clr;
wire datain_a_clr_in,datain_b_clr_in;
wire addr_a_clr_in,addr_b_clr_in;
wire byteena_a_clr_in,byteena_b_clr_in;
wire we_a_clr_in,rewe_b_clr_in;
reg mem_invalidate;
wire [`PRIME:`SEC] clear_asserted_during_write;
reg clear_asserted_during_write_a,clear_asserted_during_write_b;
// port A registers
wire we_a_reg;
wire [port_a_address_width - 1:0] addr_a_reg;
wire [port_a_data_width - 1:0] datain_a_reg, dataout_a_reg;
reg [port_a_data_width - 1:0] dataout_a;
wire [port_a_byte_enable_mask_width - 1:0] byteena_a_reg;
reg out_a_is_reg;
// port B registers
wire rewe_b_reg;
wire [port_b_address_width - 1:0] addr_b_reg;
wire [port_b_data_width - 1:0] datain_b_reg, dataout_b_reg;
reg [port_b_data_width - 1:0] dataout_b;
wire [port_b_byte_enable_mask_width - 1:0] byteena_b_reg;
reg out_b_is_reg;
// placeholders for read/written data
reg [data_width - 1:0] read_data_latch;
reg [data_width - 1:0] mem_data;
reg [data_width - 1:0] old_mem_data;
reg [data_unit_width - 1:0] read_unit_data_latch;
reg [data_width - 1:0] mem_unit_data;
// pulses for A/B ports
wire write_pulse_a,write_pulse_b;
wire read_pulse_a,read_pulse_b;
wire read_pulse_a_feedthru,read_pulse_b_feedthru;
wire [address_unit_width - 1:0] addr_prime_reg; // registered address
wire [address_width - 1:0] addr_sec_reg;
wire [data_width - 1:0] datain_prime_reg; // registered data
wire [data_unit_width - 1:0] datain_sec_reg;
// pulses for primary/secondary ports
wire write_pulse_prime,write_pulse_sec;
wire read_pulse_prime,read_pulse_sec;
wire read_pulse_prime_feedthru,read_pulse_sec_feedthru;
reg [`PRIME:`SEC] dual_write; // simultaneous write to same location
// (row,column) coordinates
reg [address_unit_width - 1:0] row_sec;
reg [address_width + data_unit_width - address_unit_width - 1:0] col_sec;
// memory core
reg [data_width - 1:0] mem [num_rows - 1:0];
// byte enable
wire [data_width - 1:0] mask_vector_prime, mask_vector_prime_int;
wire [data_unit_width - 1:0] mask_vector_sec, mask_vector_sec_int;
reg [data_unit_width - 1:0] mask_vector_common_int;
reg [port_a_data_width - 1:0] mask_vector_a, mask_vector_a_int;
reg [port_b_data_width - 1:0] mask_vector_b, mask_vector_b_int;
// memory initialization
integer i,j,k,l;
integer addr_range_init;
reg [data_width - 1:0] init_mem_word;
reg [(port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1:0] mem_init;
// port active for read/write
wire active_a, active_b;
wire active_a_in, active_b_in;
wire active_write_a,active_write_b,active_write_clear_a,active_write_clear_b;
reg mode_is_rom,mode_is_sp,mode_is_bdp; // ram mode
reg ram_type; // ram type eg. MRAM
initial
begin
ram_type = (ram_block_type == "M-RAM" || ram_block_type == "m-ram" || ram_block_type == "MegaRAM" ||
(ram_block_type == "auto" && mixed_port_feed_through_mode == "dont_care" && port_b_read_enable_write_enable_clock == "clock0"));
mode_is_rom = (operation_mode == "rom");
mode_is_sp = (operation_mode == "single_port");
mode_is_bdp = (operation_mode == "bidir_dual_port");
out_a_is_reg = (port_a_data_out_clock == "none") ? 1'b0 : 1'b1;
out_b_is_reg = (port_b_data_out_clock == "none") ? 1'b0 : 1'b1;
// powerup output latches to 0
dataout_a = 'b0;
if (mode_is_dp || mode_is_bdp) dataout_b = 'b0;
for (i = 0; i < num_rows; i = i + 1) mem[i] = 'b0;
if ((init_file_layout == "port_a") || (init_file_layout == "port_b"))
begin
mem_init = {mem_init1,mem_init0};
addr_range_init = (primary_port_is_a) ?
port_a_last_address - port_a_first_address + 1 :
port_b_last_address - port_b_first_address + 1 ;
for (j = 0; j < addr_range_init; j = j + 1)
begin
for (k = 0; k < data_width; k = k + 1)
init_mem_word[k] = mem_init[j*data_width + k];
mem[j] = init_mem_word;
end
end
dual_write = 'b0;
end
assign clk_a_in = clk0_int;
assign clk_a_byteena = (port_a_byte_enable_clock == "none") ? 1'b0 : clk_a_in;
assign clk_a_out = (port_a_data_out_clock == "none") ? 1'b0 : (
(port_a_data_out_clock == "clock0") ? clk0_int : clk1_int);
assign clk_b_in = (port_b_read_enable_write_enable_clock == "clock0") ? clk0_int : clk1_int;
assign clk_b_byteena = (port_b_byte_enable_clock == "none") ? 1'b0 : (
(port_b_byte_enable_clock == "clock0") ? clk0_int : clk1_int);
assign clk_b_out = (port_b_data_out_clock == "none") ? 1'b0 : (
(port_b_data_out_clock == "clock0") ? clk0_int : clk1_int);
assign addr_a_clr_in = (port_a_address_clear == "none") ? 1'b0 : clr0_int;
assign addr_b_clr_in = (port_b_address_clear == "none") ? 1'b0 : (
(port_b_address_clear == "clear0") ? clr0_int : clr1_int);
assign datain_a_clr_in = (port_a_data_in_clear == "none") ? 1'b0 : clr0_int;
assign dataout_a_clr = (port_a_data_out_clear == "none") ? 1'b0 : (
(port_a_data_out_clear == "clear0") ? clr0_int : clr1_int);
assign datain_b_clr_in = (port_b_data_in_clear == "none") ? 1'b0 : (
(port_b_data_in_clear == "clear0") ? clr0_int : clr1_int);
assign dataout_b_clr = (port_b_data_out_clear == "none") ? 1'b0 : (
(port_b_data_out_clear == "clear0") ? clr0_int : clr1_int);
assign byteena_a_clr_in = (port_a_byte_enable_clear == "none") ? 1'b0 : clr0_int;
assign byteena_b_clr_in = (port_b_byte_enable_clear == "none") ? 1'b0 : (
(port_b_byte_enable_clear == "clear0") ? clr0_int : clr1_int);
assign we_a_clr_in = (port_a_write_enable_clear == "none") ? 1'b0 : clr0_int;
assign rewe_b_clr_in = (port_b_read_enable_write_enable_clear == "none") ? 1'b0 : (
(port_b_read_enable_write_enable_clear == "clear0") ? clr0_int : clr1_int);
assign active_a_in = ena0_int;
assign active_b_in = (port_b_read_enable_write_enable_clock == "clock0") ? ena0_int : ena1_int;
// Store clock enable value for SEAB/MEAB
// port A active
cyclone_ram_register active_port_a (
.d(active_a_in),
.clk(clk_a_in),
.aclr(1'b0),
.devclrn(1'b1),
.devpor(1'b1),
.ena(1'b1),
.q(active_a),.aclrout()
);
defparam active_port_a.width = 1;
assign active_write_a = active_a && (byteena_a_reg !== 'b0);
// port B active
cyclone_ram_register active_port_b (
.d(active_b_in),
.clk(clk_b_in),
.aclr(1'b0),
.devclrn(1'b1),
.devpor(1'b1),
.ena(1'b1),
.q(active_b),.aclrout()
);
defparam active_port_b.width = 1;
assign active_write_b = active_b && (byteena_b_reg !== 'b0);
// ------- A input registers -------
// write enable
cyclone_ram_register we_a_register (
.d(mode_is_rom ? 1'b0 : portawe_int),
.clk(clk_a_in),
.aclr(we_a_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.ena(active_a_in),
.q(we_a_reg),
.aclrout(we_a_clr)
);
defparam we_a_register.width = 1;
// address
cyclone_ram_register addr_a_register (
.d(portaaddr_int),
.clk(clk_a_in),
.aclr(addr_a_clr_in),
.devclrn(devclrn),.devpor(devpor),
.ena(active_a_in),
.q(addr_a_reg),
.aclrout(addr_a_clr)
);
defparam addr_a_register.width = port_a_address_width;
// data
cyclone_ram_register datain_a_register (
.d(portadatain_int),
.clk(clk_a_in),
.aclr(datain_a_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.ena(active_a_in),
.q(datain_a_reg),
.aclrout(datain_a_clr)
);
defparam datain_a_register.width = port_a_data_width;
// byte enable
cyclone_ram_register byteena_a_register (
.d(portabyteenamasks_int),
.clk(clk_a_byteena),
.aclr(byteena_a_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.ena(active_a_in),
.q(byteena_a_reg),
.aclrout(byteena_a_clr)
);
defparam byteena_a_register.width = port_a_byte_enable_mask_width;
defparam byteena_a_register.preset = 1'b1;
// ------- B input registers -------
// read/write enable
cyclone_ram_register rewe_b_register (
.d(portbrewe_int),
.clk(clk_b_in),
.aclr(rewe_b_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.ena(active_b_in),
.q(rewe_b_reg),
.aclrout(rewe_b_clr)
);
defparam rewe_b_register.width = 1;
defparam rewe_b_register.preset = mode_is_dp;
// address
cyclone_ram_register addr_b_register (
.d(portbaddr_int),
.clk(clk_b_in),
.aclr(addr_b_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.ena(active_b_in),
.q(addr_b_reg),
.aclrout(addr_b_clr)
);
defparam addr_b_register.width = port_b_address_width;
// data
cyclone_ram_register datain_b_register (
.d(portbdatain_int),
.clk(clk_b_in),
.aclr(datain_b_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.ena(active_b_in),
.q(datain_b_reg),
.aclrout(datain_b_clr)
);
defparam datain_b_register.width = port_b_data_width;
// byte enable
cyclone_ram_register byteena_b_register (
.d(portbbyteenamasks_int),
.clk(clk_b_byteena),
.aclr(byteena_b_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.ena(active_b_in),
.q(byteena_b_reg),
.aclrout(byteena_b_clr)
);
defparam byteena_b_register.width = port_b_byte_enable_mask_width;
defparam byteena_b_register.preset = 1'b1;
assign datain_prime_reg = (primary_port_is_a) ? datain_a_reg : datain_b_reg;
assign addr_prime_reg = (primary_port_is_a) ? addr_a_reg : addr_b_reg;
assign datain_sec_reg = (primary_port_is_a) ? datain_b_reg : datain_a_reg;
assign addr_sec_reg = (primary_port_is_a) ? addr_b_reg : addr_a_reg;
assign mask_vector_prime = (primary_port_is_a) ? mask_vector_a : mask_vector_b;
assign mask_vector_prime_int = (primary_port_is_a) ? mask_vector_a_int : mask_vector_b_int;
assign mask_vector_sec = (primary_port_is_a) ? mask_vector_b : mask_vector_a;
assign mask_vector_sec_int = (primary_port_is_a) ? mask_vector_b_int : mask_vector_a_int;
// Write pulse generation
cyclone_ram_pulse_generator wpgen_a (
.clk(ram_type ? clk_a_in : ~clk_a_in),
.ena(active_write_a & we_a_reg),
.pulse(write_pulse_a),
.cycle(write_cycle_a)
);
cyclone_ram_pulse_generator wpgen_b (
.clk(ram_type ? clk_b_in : ~clk_b_in),
.ena(active_write_b & mode_is_bdp & rewe_b_reg),
.pulse(write_pulse_b),
.cycle(write_cycle_b)
);
// Read pulse generation
cyclone_ram_pulse_generator rpgen_a (
.clk(clk_a_in),
.ena(active_a & ~we_a_reg),
.pulse(read_pulse_a),
.cycle()
);
cyclone_ram_pulse_generator rpgen_b (
.clk(clk_b_in),
.ena(active_b & (mode_is_dp ? rewe_b_reg : ~rewe_b_reg)),
.pulse(read_pulse_b),
.cycle()
);
assign write_pulse_prime = (primary_port_is_a) ? write_pulse_a : write_pulse_b;
assign read_pulse_prime = (primary_port_is_a) ? read_pulse_a : read_pulse_b;
assign read_pulse_prime_feedthru = (primary_port_is_a) ? read_pulse_a_feedthru : read_pulse_b_feedthru;
assign write_pulse_sec = (primary_port_is_a) ? write_pulse_b : write_pulse_a;
assign read_pulse_sec = (primary_port_is_a) ? read_pulse_b : read_pulse_a;
assign read_pulse_sec_feedthru = (primary_port_is_a) ? read_pulse_b_feedthru : read_pulse_a_feedthru;
// Create internal masks for byte enable processing
always @(byteena_a_reg)
begin
for (i = 0; i < port_a_data_width; i = i + 1)
begin
mask_vector_a[i] = (byteena_a_reg[i/byte_size_a] === 1'b1) ? 1'b0 : 1'bx;
mask_vector_a_int[i] = (byteena_a_reg[i/byte_size_a] === 1'b0) ? 1'b0 : 1'bx;
end
end
always @(byteena_b_reg)
begin
for (l = 0; l < port_b_data_width; l = l + 1)
begin
mask_vector_b[l] = (byteena_b_reg[l/byte_size_b] === 1'b1) ? 1'b0 : 1'bx;
mask_vector_b_int[l] = (byteena_b_reg[l/byte_size_b] === 1'b0) ? 1'b0 : 1'bx;
end
end
always @(posedge write_pulse_prime or posedge write_pulse_sec or
posedge read_pulse_prime or posedge read_pulse_sec
)
begin
// Write stage 1 : write X to memory
if (write_pulse_prime)
begin
old_mem_data = mem[addr_prime_reg];
mem_data = mem[addr_prime_reg] ^ mask_vector_prime_int;
mem[addr_prime_reg] = mem_data;
end
if (write_pulse_sec)
begin
row_sec = addr_sec_reg / num_cols; col_sec = (addr_sec_reg % num_cols) * data_unit_width;
mem_unit_data = mem[row_sec];
for (j = col_sec; j <= col_sec + data_unit_width - 1; j = j + 1)
mem_unit_data[j] = mem_unit_data[j] ^ mask_vector_sec_int[j - col_sec];
mem[row_sec] = mem_unit_data;
end
if ((addr_prime_reg == row_sec) && write_pulse_prime && write_pulse_sec) dual_write = 2'b11;
// Read stage 1 : read data from memory
if (read_pulse_prime)
read_data_latch = mem[addr_prime_reg];
if (read_pulse_sec)
begin
row_sec = addr_sec_reg / num_cols; col_sec = (addr_sec_reg % num_cols) * data_unit_width;
if ((row_sec == addr_prime_reg) && (write_pulse_prime))
mem_unit_data = old_mem_data;
else
mem_unit_data = mem[row_sec];
for (j = col_sec; j <= col_sec + data_unit_width - 1; j = j + 1)
read_unit_data_latch[j - col_sec] = mem_unit_data[j];
end
end
// Simultaneous write to same/overlapping location by both ports
always @(dual_write)
begin
if (dual_write == 2'b11)
begin
for (i = 0; i < data_unit_width; i = i + 1)
mask_vector_common_int[i] = mask_vector_prime_int[col_sec + i] &
mask_vector_sec_int[i];
end
else if (dual_write == 2'b01) mem_unit_data = mem[row_sec];
else if (dual_write == 'b0)
begin
mem_data = mem[addr_prime_reg];
for (i = 0; i < data_unit_width; i = i + 1)
mem_data[col_sec + i] = mem_data[col_sec + i] ^ mask_vector_common_int[i];
mem[addr_prime_reg] = mem_data;
end
end
// Write stage 2 : Write actual data to memory
always @(negedge write_pulse_prime)
begin
if (clear_asserted_during_write[`PRIME] !== 1'b1)
begin
for (i = 0; i < data_width; i = i + 1)
if (mask_vector_prime[i] == 1'b0)
mem_data[i] = datain_prime_reg[i];
mem[addr_prime_reg] = mem_data;
end
dual_write[`PRIME] = 1'b0;
end
always @(negedge write_pulse_sec)
begin
if (clear_asserted_during_write[`SEC] !== 1'b1)
begin
for (i = 0; i < data_unit_width; i = i + 1)
if (mask_vector_sec[i] == 1'b0)
mem_unit_data[col_sec + i] = datain_sec_reg[i];
mem[row_sec] = mem_unit_data;
end
dual_write[`SEC] = 1'b0;
end
// Read stage 2 : Send data to output
always @(negedge read_pulse_prime)
begin
if (primary_port_is_a)
dataout_a = read_data_latch;
else
dataout_b = read_data_latch;
end
always @(negedge read_pulse_sec)
begin
if (primary_port_is_b)
dataout_a = read_unit_data_latch;
else
dataout_b = read_unit_data_latch;
end
// Same port feed through
cyclone_ram_pulse_generator ftpgen_a (
.clk(clk_a_in),
.ena(active_a & ~mode_is_dp & we_a_reg),
.pulse(read_pulse_a_feedthru),.cycle()
);
cyclone_ram_pulse_generator ftpgen_b (
.clk(clk_b_in),
.ena(active_b & mode_is_bdp & rewe_b_reg),
.pulse(read_pulse_b_feedthru),.cycle()
);
always @(negedge read_pulse_prime_feedthru)
begin
if (primary_port_is_a)
dataout_a = datain_prime_reg ^ mask_vector_prime;
else
dataout_b = datain_prime_reg ^ mask_vector_prime;
end
always @(negedge read_pulse_sec_feedthru)
begin
if (primary_port_is_b)
dataout_a = datain_sec_reg ^ mask_vector_sec;
else
dataout_b = datain_sec_reg ^ mask_vector_sec;
end
// Input register clears
always @(posedge addr_a_clr or posedge datain_a_clr or posedge we_a_clr)
clear_asserted_during_write_a = write_pulse_a;
assign active_write_clear_a = active_write_a & write_cycle_a;
always @(posedge addr_a_clr)
begin
if (active_write_clear_a & we_a_reg)
mem_invalidate = 1'b1;
else if (active_a & ~we_a_reg)
begin
if (primary_port_is_a)
begin
read_data_latch = 'bx;
end
else
begin
read_unit_data_latch = 'bx;
end
dataout_a = 'bx;
end
end
always @(posedge datain_a_clr or posedge we_a_clr)
begin
if (active_write_clear_a & we_a_reg)
begin
if (primary_port_is_a)
mem[addr_prime_reg] = 'bx;
else
begin
mem_unit_data = mem[row_sec];
for (j = col_sec; j <= col_sec + data_unit_width - 1; j = j + 1)
mem_unit_data[j] = 1'bx;
mem[row_sec] = mem_unit_data;
end
if (primary_port_is_a)
begin
read_data_latch = 'bx;
end
else
begin
read_unit_data_latch = 'bx;
end
end
end
assign active_write_clear_b = active_write_b & write_cycle_b;
always @(posedge addr_b_clr or posedge datain_b_clr or
posedge rewe_b_clr)
clear_asserted_during_write_b = write_pulse_b;
always @(posedge addr_b_clr)
begin
if (mode_is_bdp & active_write_clear_b & rewe_b_reg)
mem_invalidate = 1'b1;
else if (active_b & (mode_is_dp & rewe_b_reg || mode_is_bdp & ~rewe_b_reg))
begin
if (primary_port_is_b)
begin
read_data_latch = 'bx;
end
else
begin
read_unit_data_latch = 'bx;
end
dataout_b = 'bx;
end
end
always @(posedge datain_b_clr or posedge rewe_b_clr)
begin
if (mode_is_bdp & active_write_clear_b & rewe_b_reg)
begin
if (primary_port_is_b)
mem[addr_prime_reg] = 'bx;
else
begin
mem_unit_data = mem[row_sec];
for (j = col_sec; j <= col_sec + data_unit_width - 1; j = j + 1)
mem_unit_data[j] = 'bx;
mem[row_sec] = mem_unit_data;
end
if (primary_port_is_b)
begin
read_data_latch = 'bx;
end
else
begin
read_unit_data_latch = 'bx;
end
end
end
assign clear_asserted_during_write[primary_port_is_a] = clear_asserted_during_write_a;
assign clear_asserted_during_write[primary_port_is_b] = clear_asserted_during_write_b;
always @(posedge mem_invalidate)
begin
for (i = 0; i < num_rows; i = i + 1) mem[i] = 'bx;
mem_invalidate = 1'b0;
end
// ------- Output registers --------
assign clkena_a_out = (port_a_data_out_clock == "clock0") ? ena0_int : ena1_int;
cyclone_ram_register dataout_a_register (
.d(dataout_a),
.clk(clk_a_out),
.aclr(dataout_a_clr),
.devclrn(devclrn),
.devpor(devpor),
.ena(clkena_a_out),
.q(dataout_a_reg),.aclrout()
);
defparam dataout_a_register.width = port_a_data_width;
assign portadataout = (out_a_is_reg) ? dataout_a_reg : dataout_a;
assign clkena_b_out = (port_b_data_out_clock == "clock0") ? ena0_int : ena1_int;
cyclone_ram_register dataout_b_register (
.d( dataout_b ),
.clk(clk_b_out),
.aclr(dataout_b_clr),
.devclrn(devclrn),.devpor(devpor),
.ena(clkena_b_out),
.q(dataout_b_reg),.aclrout()
);
defparam dataout_b_register.width = port_b_data_width;
assign portbdataout = (out_b_is_reg) ? dataout_b_reg : dataout_b;
endmodule // cyclone_ram_block
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : cyclone_m_cntr
//
// Description : Timing simulation model for the M counter. This is the
// loop feedback counter for the Cyclone PLL.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module cyclone_m_cntr (clk,
reset,
cout,
initial_value,
modulus,
time_delay);
// INPUT PORTS
input clk;
input reset;
input [31:0] initial_value;
input [31:0] modulus;
input [31:0] time_delay;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
integer count;
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg cout_tmp;
initial
begin
count = 1;
first_rising_edge = 1;
clk_last_value = 0;
end
always @(reset or clk)
begin
if (reset)
begin
count = 1;
tmp_cout = 0;
first_rising_edge = 1;
end
else begin
if (clk_last_value !== clk)
begin
if (clk === 1'b1 && first_rising_edge)
begin
first_rising_edge = 0;
tmp_cout = clk;
end
else if (first_rising_edge == 0)
begin
if (count < modulus)
count = count + 1;
else
begin
count = 1;
tmp_cout = ~tmp_cout;
end
end
end
end
clk_last_value = clk;
cout_tmp <= #(time_delay) tmp_cout;
end
and (cout, cout_tmp, 1'b1);
endmodule // cyclone_m_cntr
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : cyclone_n_cntr
//
// Description : Timing simulation model for the N counter. This is the
// input clock divide counter for the Cyclone PLL.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module cyclone_n_cntr (clk,
reset,
cout,
modulus,
time_delay);
// INPUT PORTS
input clk;
input reset;
input [31:0] modulus;
input [31:0] time_delay;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
integer count;
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg clk_last_valid_value;
reg cout_tmp;
initial
begin
count = 1;
first_rising_edge = 1;
clk_last_value = 0;
end
always @(reset or clk)
begin
if (reset)
begin
count = 1;
tmp_cout = 0;
first_rising_edge = 1;
end
else begin
if (clk_last_value !== clk)
begin
if (clk === 1'bx)
begin
$display("Warning : Invalid transition to 'X' detected on PLL input clk. This edge will be ignored.");
$display("Time: %0t Instance: %m", $time);
end
else if ((clk === 1'b1) && first_rising_edge)
begin
first_rising_edge = 0;
tmp_cout = clk;
end
else if ((first_rising_edge == 0) && (clk_last_valid_value !== clk))
begin
if (count < modulus)
count = count + 1;
else
begin
count = 1;
tmp_cout = ~tmp_cout;
end
end
end
end
clk_last_value = clk;
if (clk !== 1'bx)
clk_last_valid_value = clk;
cout_tmp <= #(time_delay) tmp_cout;
end
and (cout, cout_tmp, 1'b1);
endmodule // cyclone_n_cntr
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : cyclone_scale_cntr
//
// Description : Timing simulation model for the output scale-down counters.
// This is a common model for the L0, L1, G0, G1, G2, G3, E0,
// E1, E2 and E3 output counters of the Cyclone PLL.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module cyclone_scale_cntr (clk,
reset,
cout,
high,
low,
initial_value,
mode,
time_delay,
ph_tap);
// INPUT PORTS
input clk;
input reset;
input [31:0] high;
input [31:0] low;
input [31:0] initial_value;
input [8*6:1] mode;
input [31:0] time_delay;
input [31:0] ph_tap;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg init;
integer count;
integer output_shift_count;
reg cout_tmp;
reg [31:0] high_reg;
reg [31:0] low_reg;
reg high_cnt_xfer_done;
initial
begin
count = 1;
first_rising_edge = 0;
tmp_cout = 0;
output_shift_count = 0;
high_cnt_xfer_done = 0;
end
always @(clk or reset)
begin
if (init !== 1'b1)
begin
high_reg = high;
low_reg = low;
clk_last_value = 0;
init = 1'b1;
end
if (reset)
begin
count = 1;
output_shift_count = 0;
tmp_cout = 0;
first_rising_edge = 0;
end
else if (clk_last_value !== clk)
begin
if (mode == "off")
tmp_cout = 0;
else if (mode == "bypass")
tmp_cout = clk;
else if (first_rising_edge == 0)
begin
if (clk == 1)
begin
output_shift_count = output_shift_count + 1;
if (output_shift_count == initial_value)
begin
tmp_cout = clk;
first_rising_edge = 1;
end
end
end
else if (output_shift_count < initial_value)
begin
if (clk == 1)
output_shift_count = output_shift_count + 1;
end
else
begin
count = count + 1;
if (mode == "even" && (count == (high_reg*2) + 1))
begin
tmp_cout = 0;
if (high_cnt_xfer_done === 1'b1)
begin
low_reg = low;
high_cnt_xfer_done = 0;
end
end
else if (mode == "odd" && (count == (high_reg*2)))
begin
tmp_cout = 0;
if (high_cnt_xfer_done === 1'b1)
begin
low_reg = low;
high_cnt_xfer_done = 0;
end
end
else if (count == (high_reg + low_reg)*2 + 1)
begin
tmp_cout = 1;
count = 1; // reset count
if (high_reg != high)
begin
high_reg = high;
high_cnt_xfer_done = 1;
end
end
end
end
clk_last_value = clk;
cout_tmp <= #(time_delay) tmp_cout;
end
and (cout, cout_tmp, 1'b1);
endmodule // cyclone_scale_cntr
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : cyclone_pll_reg
//
// Description : Simulation model for a simple DFF.
// This is required for the generation of the bit slip-signals.
// No timing, powers upto 0.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps / 1ps
module cyclone_pll_reg (q,
clk,
ena,
d,
clrn,
prn);
// INPUT PORTS
input d;
input clk;
input clrn;
input prn;
input ena;
// OUTPUT PORTS
output q;
// INTERNAL VARIABLES
reg q;
// DEFAULT VALUES THRO' PULLUPs
tri1 prn, clrn, ena;
initial q = 0;
always @ (posedge clk or negedge clrn or negedge prn )
begin
if (prn == 1'b0)
q <= 1;
else if (clrn == 1'b0)
q <= 0;
else if ((clk == 1) & (ena == 1'b1))
q <= d;
end
endmodule // cyclone_pll_reg
//////////////////////////////////////////////////////////////////////////////
//
// Module Name : cyclone_pll
//
// Description : Timing simulation model for the Cyclone StratixGX PLL.
// In the functional mode, it is also the model for the altpll
// megafunction.
//
// Limitations : Does not support Spread Spectrum and Bandwidth.
//
// Outputs : Up to 10 output clocks, each defined by its own set of
// parameters. Locked output (active high) indicates when the
// PLL locks. clkbad, clkloss and activeclock are used for
// clock switchover to indicate which input clock has gone
// bad, when the clock switchover initiates and which input
// clock is being used as the reference, respectively.
// scandataout is the data output of the serial scan chain.
//
//////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
`define WORD_LENGTH 18
module cyclone_pll (inclk,
fbin,
ena,
clkswitch,
areset,
pfdena,
clkena,
extclkena,
scanclk,
scanaclr,
scandata,
clk,
extclk,
clkbad,
activeclock,
locked,
clkloss,
scandataout,
// lvds mode specific ports
comparator,
enable0,
enable1);
parameter operation_mode = "normal";
parameter qualify_conf_done = "off";
parameter compensate_clock = "clk0";
parameter pll_type = "auto";
parameter scan_chain = "long";
parameter lpm_type = "cyclone_pll";
parameter clk0_multiply_by = 1;
parameter clk0_divide_by = 1;
parameter clk0_phase_shift = 0;
parameter clk0_time_delay = 0;
parameter clk0_duty_cycle = 50;
parameter clk1_multiply_by = 1;
parameter clk1_divide_by = 1;
parameter clk1_phase_shift = 0;
parameter clk1_time_delay = 0;
parameter clk1_duty_cycle = 50;
parameter clk2_multiply_by = 1;
parameter clk2_divide_by = 1;
parameter clk2_phase_shift = 0;
parameter clk2_time_delay = 0;
parameter clk2_duty_cycle = 50;
parameter clk3_multiply_by = 1;
parameter clk3_divide_by = 1;
parameter clk3_phase_shift = 0;
parameter clk3_time_delay = 0;
parameter clk3_duty_cycle = 50;
parameter clk4_multiply_by = 1;
parameter clk4_divide_by = 1;
parameter clk4_phase_shift = 0;
parameter clk4_time_delay = 0;
parameter clk4_duty_cycle = 50;
parameter clk5_multiply_by = 1;
parameter clk5_divide_by = 1;
parameter clk5_phase_shift = 0;
parameter clk5_time_delay = 0;
parameter clk5_duty_cycle = 50;
parameter extclk0_multiply_by = 1;
parameter extclk0_divide_by = 1;
parameter extclk0_phase_shift = 0;
parameter extclk0_time_delay = 0;
parameter extclk0_duty_cycle = 50;
parameter extclk1_multiply_by = 1;
parameter extclk1_divide_by = 1;
parameter extclk1_phase_shift = 0;
parameter extclk1_time_delay = 0;
parameter extclk1_duty_cycle = 50;
parameter extclk2_multiply_by = 1;
parameter extclk2_divide_by = 1;
parameter extclk2_phase_shift = 0;
parameter extclk2_time_delay = 0;
parameter extclk2_duty_cycle = 50;
parameter extclk3_multiply_by = 1;
parameter extclk3_divide_by = 1;
parameter extclk3_phase_shift = 0;
parameter extclk3_time_delay = 0;
parameter extclk3_duty_cycle = 50;
parameter primary_clock = "inclk0";
parameter inclk0_input_frequency = 10000;
parameter inclk1_input_frequency = 10000;
parameter gate_lock_signal = "no";
parameter gate_lock_counter = 1;
parameter valid_lock_multiplier = 5;
parameter invalid_lock_multiplier = 5;
parameter switch_over_on_lossclk = "off";
parameter switch_over_on_gated_lock = "off";
parameter switch_over_counter = 1;
parameter enable_switch_over_counter = "off";
parameter feedback_source = "extclk0";
parameter bandwidth = 0;
parameter bandwidth_type = "auto";
parameter spread_frequency = 0;
parameter common_rx_tx = "off";
parameter rx_outclock_resource = "auto";
parameter use_vco_bypass = "false";
parameter use_dc_coupling = "false";
parameter pfd_min = 0;
parameter pfd_max = 0;
parameter vco_min = 0;
parameter vco_max = 0;
parameter vco_center = 0;
// ADVANCED USE PARAMETERS
parameter m_initial = 1;
parameter m = 0;
parameter n = 1;
parameter m2 = 1;
parameter n2 = 1;
parameter ss = 0;
parameter l0_high = 1;
parameter l0_low = 1;
parameter l0_initial = 1;
parameter l0_mode = "bypass";
parameter l0_ph = 0;
parameter l0_time_delay = 0;
parameter l1_high = 1;
parameter l1_low = 1;
parameter l1_initial = 1;
parameter l1_mode = "bypass";
parameter l1_ph = 0;
parameter l1_time_delay = 0;
parameter g0_high = 1;
parameter g0_low = 1;
parameter g0_initial = 1;
parameter g0_mode = "bypass";
parameter g0_ph = 0;
parameter g0_time_delay = 0;
parameter g1_high = 1;
parameter g1_low = 1;
parameter g1_initial = 1;
parameter g1_mode = "bypass";
parameter g1_ph = 0;
parameter g1_time_delay = 0;
parameter g2_high = 1;
parameter g2_low = 1;
parameter g2_initial = 1;
parameter g2_mode = "bypass";
parameter g2_ph = 0;
parameter g2_time_delay = 0;
parameter g3_high = 1;
parameter g3_low = 1;
parameter g3_initial = 1;
parameter g3_mode = "bypass";
parameter g3_ph = 0;
parameter g3_time_delay = 0;
parameter e0_high = 1;
parameter e0_low = 1;
parameter e0_initial = 1;
parameter e0_mode = "bypass";
parameter e0_ph = 0;
parameter e0_time_delay = 0;
parameter e1_high = 1;
parameter e1_low = 1;
parameter e1_initial = 1;
parameter e1_mode = "bypass";
parameter e1_ph = 0;
parameter e1_time_delay = 0;
parameter e2_high = 1;
parameter e2_low = 1;
parameter e2_initial = 1;
parameter e2_mode = "bypass";
parameter e2_ph = 0;
parameter e2_time_delay = 0;
parameter e3_high = 1;
parameter e3_low = 1;
parameter e3_initial = 1;
parameter e3_mode = "bypass";
parameter e3_ph = 0;
parameter e3_time_delay = 0;
parameter m_ph = 0;
parameter m_time_delay = 0;
parameter n_time_delay = 0;
parameter extclk0_counter = "e0";
parameter extclk1_counter = "e1";
parameter extclk2_counter = "e2";
parameter extclk3_counter = "e3";
parameter clk0_counter = "g0";
parameter clk1_counter = "g1";
parameter clk2_counter = "g2";
parameter clk3_counter = "g3";
parameter clk4_counter = "l0";
parameter clk5_counter = "l1";
// LVDS mode parameters
parameter enable0_counter = "l0";
parameter enable1_counter = "l0";
parameter charge_pump_current = 0;
parameter loop_filter_r = "1.0";
parameter loop_filter_c = 1;
parameter pll_compensation_delay = 0;
parameter simulation_type = "timing";
parameter source_is_pll = "off";
// SIMULATION_ONLY_PARAMETERS_BEGIN
parameter down_spread = "0.0";
parameter clk0_phase_shift_num = 0;
parameter clk1_phase_shift_num = 0;
parameter clk2_phase_shift_num = 0;
parameter family_name = "Cyclone";
parameter skip_vco = "off";
parameter clk0_use_even_counter_mode = "off";
parameter clk1_use_even_counter_mode = "off";
parameter clk2_use_even_counter_mode = "off";
parameter clk3_use_even_counter_mode = "off";
parameter clk4_use_even_counter_mode = "off";
parameter clk5_use_even_counter_mode = "off";
parameter extclk0_use_even_counter_mode = "off";
parameter extclk1_use_even_counter_mode = "off";
parameter extclk2_use_even_counter_mode = "off";
parameter extclk3_use_even_counter_mode = "off";
parameter clk0_use_even_counter_value = "off";
parameter clk1_use_even_counter_value = "off";
parameter clk2_use_even_counter_value = "off";
parameter clk3_use_even_counter_value = "off";
parameter clk4_use_even_counter_value = "off";
parameter clk5_use_even_counter_value = "off";
parameter extclk0_use_even_counter_value = "off";
parameter extclk1_use_even_counter_value = "off";
parameter extclk2_use_even_counter_value = "off";
parameter extclk3_use_even_counter_value = "off";
// SIMULATION_ONLY_PARAMETERS_END
// INPUT PORTS
input [1:0] inclk;
input fbin;
input ena;
input clkswitch;
input areset;
input pfdena;
input [5:0] clkena;
input [3:0] extclkena;
input scanclk;
input scanaclr;
input scandata;
// lvds specific input ports
input comparator;
// OUTPUT PORTS
output [5:0] clk;
output [3:0] extclk;
output [1:0] clkbad;
output activeclock;
output locked;
output clkloss;
output scandataout;
// lvds specific output ports
output enable0;
output enable1;
// BUFFER INPUTS
wire inclk0_ipd;
wire inclk1_ipd;
wire ena_ipd;
wire fbin_ipd;
wire areset_ipd;
wire pfdena_ipd;
wire clkena0_ipd;
wire clkena1_ipd;
wire clkena2_ipd;
wire clkena3_ipd;
wire clkena4_ipd;
wire clkena5_ipd;
wire extclkena0_ipd;
wire extclkena1_ipd;
wire extclkena2_ipd;
wire extclkena3_ipd;
wire scanclk_ipd;
wire scanaclr_ipd;
wire scandata_ipd;
wire comparator_ipd;
wire clkswitch_ipd;
buf (inclk0_ipd, inclk[0]);
buf (inclk1_ipd, inclk[1]);
buf (ena_ipd, ena);
buf (fbin_ipd, fbin);
buf (areset_ipd, areset);
buf (pfdena_ipd, pfdena);
buf (clkena0_ipd, clkena[0]);
buf (clkena1_ipd, clkena[1]);
buf (clkena2_ipd, clkena[2]);
buf (clkena3_ipd, clkena[3]);
buf (clkena4_ipd, clkena[4]);
buf (clkena5_ipd, clkena[5]);
buf (extclkena0_ipd, extclkena[0]);
buf (extclkena1_ipd, extclkena[1]);
buf (extclkena2_ipd, extclkena[2]);
buf (extclkena3_ipd, extclkena[3]);
buf (scanclk_ipd, scanclk);
buf (scanaclr_ipd, scanaclr);
buf (scandata_ipd, scandata);
buf (comparator_ipd, comparator);
buf (clkswitch_ipd, clkswitch);
// INTERNAL VARIABLES AND NETS
integer scan_chain_length;
integer i;
integer j;
integer k;
integer l_index;
integer gate_count;
integer egpp_offset;
integer sched_time;
integer delay_chain;
integer low;
integer high;
integer initial_delay;
integer fbk_phase;
integer fbk_delay;
integer phase_shift[0:7];
integer last_phase_shift[0:7];
integer m_times_vco_period;
integer new_m_times_vco_period;
integer refclk_period;
integer fbclk_period;
integer primary_clock_frequency;
integer high_time;
integer low_time;
integer my_rem;
integer tmp_rem;
integer rem;
integer tmp_vco_per;
integer vco_per;
integer offset;
integer temp_offset;
integer cycles_to_lock;
integer cycles_to_unlock;
integer l0_count;
integer l1_count;
integer loop_xplier;
integer loop_initial;
integer loop_ph;
integer loop_time_delay;
integer cycle_to_adjust;
integer total_pull_back;
integer pull_back_M;
integer pull_back_ext_cntr;
time fbclk_time;
time first_fbclk_time;
time refclk_time;
time scanaclr_rising_time;
time scanaclr_falling_time;
reg got_first_refclk;
reg got_second_refclk;
reg got_first_fbclk;
reg refclk_last_value;
reg fbclk_last_value;
reg inclk_last_value;
reg pll_is_locked;
reg pll_about_to_lock;
reg locked_tmp;
reg l0_got_first_rising_edge;
reg l1_got_first_rising_edge;
reg vco_l0_last_value;
reg vco_l1_last_value;
reg areset_ipd_last_value;
reg ena_ipd_last_value;
reg pfdena_ipd_last_value;
reg inclk_out_of_range;
reg schedule_vco_last_value;
reg gate_out;
reg vco_val;
reg [31:0] m_initial_val;
reg [31:0] m_val;
reg [31:0] m_val_tmp;
reg [31:0] m2_val;
reg [31:0] n_val;
reg [31:0] n_val_tmp;
reg [31:0] n2_val;
reg [31:0] m_time_delay_val;
reg [31:0] n_time_delay_val;
reg [31:0] m_delay;
reg [8*6:1] m_mode_val;
reg [8*6:1] m2_mode_val;
reg [8*6:1] n_mode_val;
reg [8*6:1] n2_mode_val;
reg [31:0] l0_high_val;
reg [31:0] l0_low_val;
reg [31:0] l0_initial_val;
reg [31:0] l0_time_delay_val;
reg [8*6:1] l0_mode_val;
reg [31:0] l1_high_val;
reg [31:0] l1_low_val;
reg [31:0] l1_initial_val;
reg [31:0] l1_time_delay_val;
reg [8*6:1] l1_mode_val;
reg [31:0] g0_high_val;
reg [31:0] g0_low_val;
reg [31:0] g0_initial_val;
reg [31:0] g0_time_delay_val;
reg [8*6:1] g0_mode_val;
reg [31:0] g1_high_val;
reg [31:0] g1_low_val;
reg [31:0] g1_initial_val;
reg [31:0] g1_time_delay_val;
reg [8*6:1] g1_mode_val;
reg [31:0] g2_high_val;
reg [31:0] g2_low_val;
reg [31:0] g2_initial_val;
reg [31:0] g2_time_delay_val;
reg [8*6:1] g2_mode_val;
reg [31:0] g3_high_val;
reg [31:0] g3_low_val;
reg [31:0] g3_initial_val;
reg [31:0] g3_time_delay_val;
reg [8*6:1] g3_mode_val;
reg [31:0] e0_high_val;
reg [31:0] e0_low_val;
reg [31:0] e0_initial_val;
reg [31:0] e0_time_delay_val;
reg [8*6:1] e0_mode_val;
reg [31:0] e1_high_val;
reg [31:0] e1_low_val;
reg [31:0] e1_initial_val;
reg [31:0] e1_time_delay_val;
reg [8*6:1] e1_mode_val;
reg [31:0] e2_high_val;
reg [31:0] e2_low_val;
reg [31:0] e2_initial_val;
reg [31:0] e2_time_delay_val;
reg [8*6:1] e2_mode_val;
reg [31:0] e3_high_val;
reg [31:0] e3_low_val;
reg [31:0] e3_initial_val;
reg [31:0] e3_time_delay_val;
reg [8*6:1] e3_mode_val;
reg scanclk_last_value;
reg scanaclr_last_value;
reg transfer;
reg transfer_enable;
reg [288:0] scan_data;
reg schedule_vco;
reg schedule_offset;
reg stop_vco;
reg inclk_n;
reg [7:0] vco_out;
wire inclk_l0;
wire inclk_l1;
wire inclk_m;
wire clk0_tmp;
wire clk1_tmp;
wire clk2_tmp;
wire clk3_tmp;
wire clk4_tmp;
wire clk5_tmp;
wire extclk0_tmp;
wire extclk1_tmp;
wire extclk2_tmp;
wire extclk3_tmp;
wire nce_l0;
wire nce_l1;
wire nce_temp;
reg vco_l0;
reg vco_l1;
wire clk0;
wire clk1;
wire clk2;
wire clk3;
wire clk4;
wire clk5;
wire extclk0;
wire extclk1;
wire extclk2;
wire extclk3;
wire ena0;
wire ena1;
wire ena2;
wire ena3;
wire ena4;
wire ena5;
wire extena0;
wire extena1;
wire extena2;
wire extena3;
wire refclk;
wire fbclk;
wire l0_clk;
wire l1_clk;
wire g0_clk;
wire g1_clk;
wire g2_clk;
wire g3_clk;
wire e0_clk;
wire e1_clk;
wire e2_clk;
wire e3_clk;
wire dffa_out;
wire dffb_out;
wire dffc_out;
wire dffd_out;
wire lvds_dffb_clk;
wire lvds_dffc_clk;
wire lvds_dffd_clk;
reg first_schedule;
wire enable0_tmp;
wire enable1_tmp;
wire enable_0;
wire enable_1;
reg l0_tmp;
reg l1_tmp;
reg vco_period_was_phase_adjusted;
reg phase_adjust_was_scheduled;
// for external feedback mode
reg [31:0] ext_fbk_cntr_high;
reg [31:0] ext_fbk_cntr_low;
reg [31:0] ext_fbk_cntr_modulus;
reg [31:0] ext_fbk_cntr_delay;
reg [8*2:1] ext_fbk_cntr;
reg [8*6:1] ext_fbk_cntr_mode;
integer ext_fbk_cntr_ph;
integer ext_fbk_cntr_initial;
wire inclk_e0;
wire inclk_e1;
wire inclk_e2;
wire inclk_e3;
wire [31:0] cntr_e0_initial;
wire [31:0] cntr_e1_initial;
wire [31:0] cntr_e2_initial;
wire [31:0] cntr_e3_initial;
wire [31:0] cntr_e0_delay;
wire [31:0] cntr_e1_delay;
wire [31:0] cntr_e2_delay;
wire [31:0] cntr_e3_delay;
reg [31:0] ext_fbk_delay;
// variables for clk_switch
reg clk0_is_bad;
reg clk1_is_bad;
reg inclk0_last_value;
reg inclk1_last_value;
reg other_clock_value;
reg other_clock_last_value;
reg primary_clk_is_bad;
reg current_clk_is_bad;
reg external_switch;
// reg [8*6:1] current_clock;
reg active_clock;
reg clkloss_tmp;
reg got_curr_clk_falling_edge_after_clkswitch;
reg active_clk_was_switched;
integer clk0_count;
integer clk1_count;
integer switch_over_count;
reg scandataout_tmp;
reg scandataout_trigger;
integer quiet_time;
reg pll_in_quiet_period;
time start_quiet_time;
reg quiet_period_violation;
reg reconfig_err;
reg scanclr_violation;
reg scanclr_clk_violation;
reg got_first_scanclk_after_scanclr_inactive_edge;
reg error;
reg no_warn;
// LOCAL_PARAMETERS_BEGIN
parameter EGPP_SCAN_CHAIN = 289;
parameter GPP_SCAN_CHAIN = 193;
parameter TRST = 5000;
parameter TRSTCLK = 5000;
// LOCAL_PARAMETERS_END
// internal variables for scaling of multiply_by and divide_by values
integer i_clk0_mult_by;
integer i_clk0_div_by;
integer i_clk1_mult_by;
integer i_clk1_div_by;
integer i_clk2_mult_by;
integer i_clk2_div_by;
integer i_clk3_mult_by;
integer i_clk3_div_by;
integer i_clk4_mult_by;
integer i_clk4_div_by;
integer i_clk5_mult_by;
integer i_clk5_div_by;
integer i_extclk0_mult_by;
integer i_extclk0_div_by;
integer i_extclk1_mult_by;
integer i_extclk1_div_by;
integer i_extclk2_mult_by;
integer i_extclk2_div_by;
integer i_extclk3_mult_by;
integer i_extclk3_div_by;
integer max_d_value;
integer new_multiplier;
// internal variables for storing the phase shift number.(used in lvds mode only)
integer i_clk0_phase_shift;
integer i_clk1_phase_shift;
integer i_clk2_phase_shift;
// user to advanced internal signals
integer i_m_initial;
integer i_m;
integer i_n;
integer i_m2;
integer i_n2;
integer i_ss;
integer i_l0_high;
integer i_l1_high;
integer i_g0_high;
integer i_g1_high;
integer i_g2_high;
integer i_g3_high;
integer i_e0_high;
integer i_e1_high;
integer i_e2_high;
integer i_e3_high;
integer i_l0_low;
integer i_l1_low;
integer i_g0_low;
integer i_g1_low;
integer i_g2_low;
integer i_g3_low;
integer i_e0_low;
integer i_e1_low;
integer i_e2_low;
integer i_e3_low;
integer i_l0_initial;
integer i_l1_initial;
integer i_g0_initial;
integer i_g1_initial;
integer i_g2_initial;
integer i_g3_initial;
integer i_e0_initial;
integer i_e1_initial;
integer i_e2_initial;
integer i_e3_initial;
reg [8*6:1] i_l0_mode;
reg [8*6:1] i_l1_mode;
reg [8*6:1] i_g0_mode;
reg [8*6:1] i_g1_mode;
reg [8*6:1] i_g2_mode;
reg [8*6:1] i_g3_mode;
reg [8*6:1] i_e0_mode;
reg [8*6:1] i_e1_mode;
reg [8*6:1] i_e2_mode;
reg [8*6:1] i_e3_mode;
integer i_vco_min;
integer i_vco_max;
integer i_vco_center;
integer i_pfd_min;
integer i_pfd_max;
integer i_l0_ph;
integer i_l1_ph;
integer i_g0_ph;
integer i_g1_ph;
integer i_g2_ph;
integer i_g3_ph;
integer i_e0_ph;
integer i_e1_ph;
integer i_e2_ph;
integer i_e3_ph;
integer i_m_ph;
integer m_ph_val;
integer i_l0_time_delay;
integer i_l1_time_delay;
integer i_g0_time_delay;
integer i_g1_time_delay;
integer i_g2_time_delay;
integer i_g3_time_delay;
integer i_e0_time_delay;
integer i_e1_time_delay;
integer i_e2_time_delay;
integer i_e3_time_delay;
integer i_m_time_delay;
integer i_n_time_delay;
integer i_extclk3_counter;
integer i_extclk2_counter;
integer i_extclk1_counter;
integer i_extclk0_counter;
integer i_clk5_counter;
integer i_clk4_counter;
integer i_clk3_counter;
integer i_clk2_counter;
integer i_clk1_counter;
integer i_clk0_counter;
integer i_charge_pump_current;
integer i_loop_filter_r;
integer max_neg_abs;
integer output_count;
integer new_divisor;
reg pll_is_in_reset;
// uppercase to lowercase parameter values
reg [8*`WORD_LENGTH:1] l_operation_mode;
reg [8*`WORD_LENGTH:1] l_pll_type;
reg [8*`WORD_LENGTH:1] l_qualify_conf_done;
reg [8*`WORD_LENGTH:1] l_compensate_clock;
reg [8*`WORD_LENGTH:1] l_scan_chain;
reg [8*`WORD_LENGTH:1] l_primary_clock;
reg [8*`WORD_LENGTH:1] l_gate_lock_signal;
reg [8*`WORD_LENGTH:1] l_switch_over_on_lossclk;
reg [8*`WORD_LENGTH:1] l_switch_over_on_gated_lock;
reg [8*`WORD_LENGTH:1] l_enable_switch_over_counter;
reg [8*`WORD_LENGTH:1] l_feedback_source;
reg [8*`WORD_LENGTH:1] l_bandwidth_type;
reg [8*`WORD_LENGTH:1] l_simulation_type;
reg [8*`WORD_LENGTH:1] l_enable0_counter;
reg [8*`WORD_LENGTH:1] l_enable1_counter;
integer current_clock;
reg is_fast_pll;
reg op_mode;
reg init;
specify
endspecify
// finds the closest integer fraction of a given pair of numerator and denominator.
task find_simple_integer_fraction;
input numerator;
input denominator;
input max_denom;
output fraction_num;
output fraction_div;
parameter max_iter = 20;
integer numerator;
integer denominator;
integer max_denom;
integer fraction_num;
integer fraction_div;
integer quotient_array[max_iter-1:0];
integer int_loop_iter;
integer int_quot;
integer m_value;
integer d_value;
integer old_m_value;
integer swap;
integer loop_iter;
integer num;
integer den;
integer i_max_iter;
begin
loop_iter = 0;
num = numerator;
den = denominator;
i_max_iter = max_iter;
while (loop_iter < i_max_iter)
begin
int_quot = num / den;
quotient_array[loop_iter] = int_quot;
num = num - (den*int_quot);
loop_iter=loop_iter+1;
if ((num == 0) || (max_denom != -1) || (loop_iter == i_max_iter))
begin
// calculate the numerator and denominator if there is a restriction on the
// max denom value or if the loop is ending
m_value = 0;
d_value = 1;
// get the rounded value at this stage for the remaining fraction
if (den != 0)
begin
m_value = (2*num/den);
end
// calculate the fraction numerator and denominator at this stage
for (int_loop_iter = loop_iter-1; int_loop_iter >= 0; int_loop_iter=int_loop_iter-1)
begin
if (m_value == 0)
begin
m_value = quotient_array[int_loop_iter];
d_value = 1;
end
else
begin
old_m_value = m_value;
m_value = quotient_array[int_loop_iter]*m_value + d_value;
d_value = old_m_value;
end
end
// if the denominator is less than the maximum denom_value or if there is no restriction save it
if ((d_value <= max_denom) || (max_denom == -1))
begin
if ((m_value == 0) || (d_value == 0))
begin
fraction_num = numerator;
fraction_div = denominator;
end
else
begin
fraction_num = m_value;
fraction_div = d_value;
end
end
// end the loop if the denomitor has overflown or the numerator is zero (no remainder during this round)
if (((d_value > max_denom) && (max_denom != -1)) || (num == 0))
begin
i_max_iter = loop_iter;
end
end
// swap the numerator and denominator for the next round
swap = den;
den = num;
num = swap;
end
end
endtask // find_simple_integer_fraction
// get the absolute value
function integer abs;
input value;
integer value;
begin
if (value < 0)
abs = value * -1;
else abs = value;
end
endfunction
// find twice the period of the slowest clock
function integer slowest_clk;
input L0, L0_mode, L1, L1_mode, G0, G0_mode, G1, G1_mode, G2, G2_mode, G3, G3_mode, E0, E0_mode, E1, E1_mode, E2, E2_mode, E3, E3_mode, scan_chain, refclk, m_mod;
integer L0, L1, G0, G1, G2, G3, E0, E1, E2, E3;
reg [8*6:1] L0_mode, L1_mode, G0_mode, G1_mode, G2_mode, G3_mode, E0_mode, E1_mode, E2_mode, E3_mode;
reg [8*5:1] scan_chain;
integer refclk;
reg [31:0] m_mod;
integer max_modulus;
begin
max_modulus = 1;
if (L0_mode != "bypass" && L0_mode != " off")
max_modulus = L0;
if (L1 > max_modulus && L1_mode != "bypass" && L1_mode != " off")
max_modulus = L1;
if (G0 > max_modulus && G0_mode != "bypass" && G0_mode != " off")
max_modulus = G0;
if (G1 > max_modulus && G1_mode != "bypass" && G1_mode != " off")
max_modulus = G1;
if (G2 > max_modulus && G2_mode != "bypass" && G2_mode != " off")
max_modulus = G2;
if (G3 > max_modulus && G3_mode != "bypass" && G3_mode != " off")
max_modulus = G3;
if (scan_chain == "long")
begin
if (E0 > max_modulus && E0_mode != "bypass" && E0_mode != " off")
max_modulus = E0;
if (E1 > max_modulus && E1_mode != "bypass" && E1_mode != " off")
max_modulus = E1;
if (E2 > max_modulus && E2_mode != "bypass" && E2_mode != " off")
max_modulus = E2;
if (E3 > max_modulus && E3_mode != "bypass" && E3_mode != " off")
max_modulus = E3;
end
slowest_clk = ((refclk/m_mod) * max_modulus *2);
end
endfunction
// count the number of digits in the given integer
function integer count_digit;
input X;
integer X;
integer count, result;
begin
count = 0;
result = X;
while (result != 0)
begin
result = (result / 10);
count = count + 1;
end
count_digit = count;
end
endfunction
// reduce the given huge number(X) to Y significant digits
function integer scale_num;
input X, Y;
integer X, Y;
integer count;
integer fac_ten, lc;
begin
fac_ten = 1;
count = count_digit(X);
for (lc = 0; lc < (count-Y); lc = lc + 1)
fac_ten = fac_ten * 10;
scale_num = (X / fac_ten);
end
endfunction
// find the greatest common denominator of X and Y
function integer gcd;
input X,Y;
integer X,Y;
integer L, S, R, G;
begin
if (X < Y) // find which is smaller.
begin
S = X;
L = Y;
end
else
begin
S = Y;
L = X;
end
R = S;
while ( R > 1)
begin
S = L;
L = R;
R = S % L; // divide bigger number by smaller.
// remainder becomes smaller number.
end
if (R == 0) // if evenly divisible then L is gcd else it is 1.
G = L;
else
G = R;
gcd = G;
end
endfunction
// find the least common multiple of A1 to A10
function integer lcm;
input A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, P;
integer A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, P;
integer M1, M2, M3, M4, M5 , M6, M7, M8, M9, R;
begin
M1 = (A1 * A2)/gcd(A1, A2);
M2 = (M1 * A3)/gcd(M1, A3);
M3 = (M2 * A4)/gcd(M2, A4);
M4 = (M3 * A5)/gcd(M3, A5);
M5 = (M4 * A6)/gcd(M4, A6);
M6 = (M5 * A7)/gcd(M5, A7);
M7 = (M6 * A8)/gcd(M6, A8);
M8 = (M7 * A9)/gcd(M7, A9);
M9 = (M8 * A10)/gcd(M8, A10);
if (M9 < 3)
R = 10;
else if ((M9 <= 10) && (M9 >= 3))
R = 4 * M9;
else if (M9 > 1000)
R = scale_num(M9,3);
else
R = M9;
lcm = R;
end
endfunction
// find the factor of division of the output clock frequency
// compared to the VCO
function integer output_counter_value;
input clk_divide, clk_mult, M, N;
integer clk_divide, clk_mult, M, N;
integer R;
begin
R = (clk_divide * M)/(clk_mult * N);
output_counter_value = R;
end
endfunction
// find the mode of each of the PLL counters - bypass, even or odd
function [8*6:1] counter_mode;
input duty_cycle;
input output_counter_value;
integer duty_cycle;
integer output_counter_value;
integer half_cycle_high;
reg [8*6:1] R;
begin
half_cycle_high = (2*duty_cycle*output_counter_value)/100;
if (output_counter_value == 1)
R = "bypass";
else if ((half_cycle_high % 2) == 0)
R = "even";
else
R = "odd";
counter_mode = R;
end
endfunction
// find the number of VCO clock cycles to hold the output clock high
function integer counter_high;
input output_counter_value, duty_cycle;
integer output_counter_value, duty_cycle;
integer half_cycle_high;
integer tmp_counter_high;
integer mode;
begin
half_cycle_high = (2*duty_cycle*output_counter_value)/100;
mode = ((half_cycle_high % 2) == 0);
tmp_counter_high = half_cycle_high/2;
counter_high = tmp_counter_high + !mode;
end
endfunction
// find the number of VCO clock cycles to hold the output clock low
function integer counter_low;
input output_counter_value, duty_cycle;
integer output_counter_value, duty_cycle, counter_h;
integer half_cycle_high;
integer mode;
integer tmp_counter_high;
begin
half_cycle_high = (2*duty_cycle*output_counter_value)/100;
mode = ((half_cycle_high % 2) == 0);
tmp_counter_high = half_cycle_high/2;
counter_h = tmp_counter_high + !mode;
counter_low = output_counter_value - counter_h;
if (counter_low == 0)
counter_low = 1;
end
endfunction
// find the smallest time delay amongst t1 to t10
function integer mintimedelay;
input t1, t2, t3, t4, t5, t6, t7, t8, t9, t10;
integer t1, t2, t3, t4, t5, t6, t7, t8, t9, t10;
integer m1,m2,m3,m4,m5,m6,m7,m8,m9;
begin
if (t1 < t2)
m1 = t1;
else
m1 = t2;
if (m1 < t3)
m2 = m1;
else
m2 = t3;
if (m2 < t4)
m3 = m2;
else
m3 = t4;
if (m3 < t5)
m4 = m3;
else
m4 = t5;
if (m4 < t6)
m5 = m4;
else
m5 = t6;
if (m5 < t7)
m6 = m5;
else
m6 = t7;
if (m6 < t8)
m7 = m6;
else
m7 = t8;
if (m7 < t9)
m8 = m7;
else
m8 = t9;
if (m8 < t10)
m9 = m8;
else
m9 = t10;
if (m9 > 0)
mintimedelay = m9;
else
mintimedelay = 0;
end
endfunction
// find the numerically largest negative number, and return its absolute value
function integer maxnegabs;
input t1, t2, t3, t4, t5, t6, t7, t8, t9, t10;
integer t1, t2, t3, t4, t5, t6, t7, t8, t9, t10;
integer m1,m2,m3,m4,m5,m6,m7,m8,m9;
begin
if (t1 < t2) m1 = t1; else m1 = t2;
if (m1 < t3) m2 = m1; else m2 = t3;
if (m2 < t4) m3 = m2; else m3 = t4;
if (m3 < t5) m4 = m3; else m4 = t5;
if (m4 < t6) m5 = m4; else m5 = t6;
if (m5 < t7) m6 = m5; else m6 = t7;
if (m6 < t8) m7 = m6; else m7 = t8;
if (m7 < t9) m8 = m7; else m8 = t9;
if (m8 < t10) m9 = m8; else m9 = t10;
maxnegabs = (m9 < 0) ? 0 - m9 : 0;
end
endfunction
// adjust the given tap_phase by adding the largest negative number (ph_base)
function integer ph_adjust;
input tap_phase, ph_base;
integer tap_phase, ph_base;
begin
ph_adjust = tap_phase + ph_base;
end
endfunction
// find the actual time delay for each PLL counter
function integer counter_time_delay;
input clk_time_delay, m_time_delay, n_time_delay;
integer clk_time_delay, m_time_delay, n_time_delay;
begin
counter_time_delay = clk_time_delay + m_time_delay - n_time_delay;
end
endfunction
// find the number of VCO clock cycles to wait initially before the first
// rising edge of the output clock
function integer counter_initial;
input tap_phase, m, n;
integer tap_phase, m, n, phase;
begin
if (tap_phase < 0) tap_phase = 0 - tap_phase;
// adding 0.5 for rounding correction (required in order to round
// to the nearest integer instead of truncating)
phase = ((tap_phase * m) / (360 * n)) + 0.5;
counter_initial = phase;
end
endfunction
// find which VCO phase tap to align the rising edge of the output clock to
function integer counter_ph;
input tap_phase;
input m,n;
integer m,n, phase;
integer tap_phase;
begin
// adding 0.5 for rounding correction
phase = (tap_phase * m / n) + 0.5;
counter_ph = (phase % 360) / 45;
end
endfunction
// convert the given string to length 6 by padding with spaces
function [8*6:1] translate_string;
input mode;
reg [8*6:1] new_mode;
begin
if (mode == "bypass")
new_mode = "bypass";
else if (mode == "even")
new_mode = " even";
else if (mode == "odd")
new_mode = " odd";
translate_string = new_mode;
end
endfunction
// convert string to integer with sign
function integer str2int;
input [8*16:1] s;
reg [8*16:1] reg_s;
reg [8:1] digit;
reg [8:1] tmp;
integer m, magnitude;
integer sign;
begin
sign = 1;
magnitude = 0;
reg_s = s;
for (m=1; m<=16; m=m+1)
begin
tmp = reg_s[128:121];
digit = tmp & 8'b00001111;
reg_s = reg_s << 8;
// Accumulate ascii digits 0-9 only.
if ((tmp>=48) && (tmp<=57))
magnitude = (magnitude * 10) + digit;
if (tmp == 45)
sign = -1; // Found a '-' character, i.e. number is negative.
end
str2int = sign*magnitude;
end
endfunction
// this is for cyclone lvds only
// convert phase delay to integer
function integer get_int_phase_shift;
input [8*16:1] s;
input i_phase_shift;
integer i_phase_shift;
begin
if (i_phase_shift != 0)
begin
get_int_phase_shift = i_phase_shift;
end
else
begin
get_int_phase_shift = str2int(s);
end
end
endfunction
// calculate the given phase shift (in ps) in terms of degrees
function integer get_phase_degree;
input phase_shift;
integer phase_shift, result;
begin
result = (phase_shift * 360) / inclk0_input_frequency;
// this is to round up the calculation result
if ( result > 0 )
result = result + 1;
else if ( result < 0 )
result = result - 1;
else
result = 0;
// assign the rounded up result
get_phase_degree = result;
end
endfunction
// convert uppercase parameter values to lowercase
// assumes that the maximum character length of a parameter is 18
function [8*`WORD_LENGTH:1] alpha_tolower;
input [8*`WORD_LENGTH:1] given_string;
reg [8*`WORD_LENGTH:1] return_string;
reg [8*`WORD_LENGTH:1] reg_string;
reg [8:1] tmp;
reg [8:1] conv_char;
integer byte_count;
begin
return_string = " "; // initialise strings to spaces
conv_char = " ";
reg_string = given_string;
for (byte_count = `WORD_LENGTH; byte_count >= 1; byte_count = byte_count - 1)
begin
tmp = reg_string[8*`WORD_LENGTH:(8*(`WORD_LENGTH-1)+1)];
reg_string = reg_string << 8;
if ((tmp >= 65) && (tmp <= 90)) // ASCII number of 'A' is 65, 'Z' is 90
begin
conv_char = tmp + 32; // 32 is the difference in the position of 'A' and 'a' in the ASCII char set
return_string = {return_string, conv_char};
end
else
return_string = {return_string, tmp};
end
alpha_tolower = return_string;
end
endfunction
initial
begin
// convert string parameter values from uppercase to lowercase,
// as expected in this model
l_operation_mode = alpha_tolower(operation_mode);
l_pll_type = alpha_tolower(pll_type);
l_qualify_conf_done = alpha_tolower(qualify_conf_done);
l_compensate_clock = alpha_tolower(compensate_clock);
l_scan_chain = alpha_tolower(scan_chain);
l_primary_clock = alpha_tolower(primary_clock);
l_gate_lock_signal = alpha_tolower(gate_lock_signal);
l_switch_over_on_lossclk = alpha_tolower(switch_over_on_lossclk);
l_switch_over_on_gated_lock = alpha_tolower(switch_over_on_gated_lock);
l_enable_switch_over_counter = alpha_tolower(enable_switch_over_counter);
l_feedback_source = alpha_tolower(feedback_source);
l_bandwidth_type = alpha_tolower(bandwidth_type);
l_simulation_type = alpha_tolower(simulation_type);
l_enable0_counter = alpha_tolower(enable0_counter);
l_enable1_counter = alpha_tolower(enable1_counter);
if (m == 0)
begin
// set the limit of the divide_by value that can be returned by
// the following function.
max_d_value = 500;
// scale down the multiply_by and divide_by values provided by the design
// before attempting to use them in the calculations below
find_simple_integer_fraction(clk0_multiply_by, clk0_divide_by,
max_d_value, i_clk0_mult_by, i_clk0_div_by);
find_simple_integer_fraction(clk1_multiply_by, clk1_divide_by,
max_d_value, i_clk1_mult_by, i_clk1_div_by);
find_simple_integer_fraction(clk2_multiply_by, clk2_divide_by,
max_d_value, i_clk2_mult_by, i_clk2_div_by);
find_simple_integer_fraction(clk3_multiply_by, clk3_divide_by,
max_d_value, i_clk3_mult_by, i_clk3_div_by);
find_simple_integer_fraction(clk4_multiply_by, clk4_divide_by,
max_d_value, i_clk4_mult_by, i_clk4_div_by);
find_simple_integer_fraction(clk5_multiply_by, clk5_divide_by,
max_d_value, i_clk5_mult_by, i_clk5_div_by);
find_simple_integer_fraction(extclk0_multiply_by, extclk0_divide_by,
max_d_value, i_extclk0_mult_by, i_extclk0_div_by);
find_simple_integer_fraction(extclk1_multiply_by, extclk1_divide_by,
max_d_value, i_extclk1_mult_by, i_extclk1_div_by);
find_simple_integer_fraction(extclk2_multiply_by, extclk2_divide_by,
max_d_value, i_extclk2_mult_by, i_extclk2_div_by);
find_simple_integer_fraction(extclk3_multiply_by, extclk3_divide_by,
max_d_value, i_extclk3_mult_by, i_extclk3_div_by);
// convert user parameters to advanced
i_n = 1;
if (l_pll_type == "lvds")
i_m = clk0_multiply_by;
else
i_m = lcm (i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by, i_clk5_mult_by,
i_extclk0_mult_by,
i_extclk1_mult_by, i_extclk2_mult_by,
i_extclk3_mult_by, inclk0_input_frequency);
i_m_time_delay = maxnegabs (str2int(clk0_time_delay),
str2int(clk1_time_delay),
str2int(clk2_time_delay),
str2int(clk3_time_delay),
str2int(clk4_time_delay),
str2int(clk5_time_delay),
str2int(extclk0_time_delay),
str2int(extclk1_time_delay),
str2int(extclk2_time_delay),
str2int(extclk3_time_delay));
i_n_time_delay = mintimedelay(str2int(clk0_time_delay),
str2int(clk1_time_delay),
str2int(clk2_time_delay),
str2int(clk3_time_delay),
str2int(clk4_time_delay),
str2int(clk5_time_delay),
str2int(extclk0_time_delay),
str2int(extclk1_time_delay),
str2int(extclk2_time_delay),
str2int(extclk3_time_delay));
if (l_pll_type == "lvds")
i_g0_high = counter_high(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
else
i_g0_high = counter_high(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_g1_high = counter_high(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_g2_high = counter_high(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_g3_high = counter_high(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
if (l_pll_type == "lvds")
begin
i_l0_high = i_g0_high;
i_l1_high = i_g0_high;
end
else
begin
i_l0_high = counter_high(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_l1_high = counter_high(output_counter_value(i_clk5_div_by,
i_clk5_mult_by, i_m, i_n), clk5_duty_cycle);
end
i_e0_high = counter_high(output_counter_value(i_extclk0_div_by,
i_extclk0_mult_by, i_m, i_n), extclk0_duty_cycle);
i_e1_high = counter_high(output_counter_value(i_extclk1_div_by,
i_extclk1_mult_by, i_m, i_n), extclk1_duty_cycle);
i_e2_high = counter_high(output_counter_value(i_extclk2_div_by,
i_extclk2_mult_by, i_m, i_n), extclk2_duty_cycle);
i_e3_high = counter_high(output_counter_value(i_extclk3_div_by,
i_extclk3_mult_by, i_m, i_n), extclk3_duty_cycle);
if (l_pll_type == "lvds")
i_g0_low = counter_low(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
else
i_g0_low = counter_low(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_g1_low = counter_low(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_g2_low = counter_low(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_g3_low = counter_low(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
if (l_pll_type == "lvds")
begin
i_l0_low = i_g0_low;
i_l1_low = i_g0_low;
end
else
begin
i_l0_low = counter_low(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_l1_low = counter_low(output_counter_value(i_clk5_div_by,
i_clk5_mult_by, i_m, i_n), clk5_duty_cycle);
end
i_e0_low = counter_low(output_counter_value(i_extclk0_div_by,
i_extclk0_mult_by, i_m, i_n), extclk0_duty_cycle);
i_e1_low = counter_low(output_counter_value(i_extclk1_div_by,
i_extclk1_mult_by, i_m, i_n), extclk1_duty_cycle);
i_e2_low = counter_low(output_counter_value(i_extclk2_div_by,
i_extclk2_mult_by, i_m, i_n), extclk2_duty_cycle);
i_e3_low = counter_low(output_counter_value(i_extclk3_div_by,
i_extclk3_mult_by, i_m, i_n), extclk3_duty_cycle);
if (l_pll_type == "flvds")
begin
// Need to readjust phase shift values when the clock multiply value has been readjusted.
new_multiplier = clk0_multiply_by / i_clk0_mult_by;
i_clk0_phase_shift = (clk0_phase_shift_num * new_multiplier);
i_clk1_phase_shift = (clk1_phase_shift_num * new_multiplier);
i_clk2_phase_shift = (clk2_phase_shift_num * new_multiplier);
end
else
begin
i_clk0_phase_shift = get_int_phase_shift(clk0_phase_shift, clk0_phase_shift_num);
i_clk1_phase_shift = get_int_phase_shift(clk1_phase_shift, clk1_phase_shift_num);
i_clk2_phase_shift = get_int_phase_shift(clk2_phase_shift, clk2_phase_shift_num);
end
max_neg_abs = maxnegabs(i_clk0_phase_shift,
i_clk1_phase_shift,
i_clk2_phase_shift,
str2int(clk3_phase_shift),
str2int(clk4_phase_shift),
str2int(clk5_phase_shift),
str2int(extclk0_phase_shift),
str2int(extclk1_phase_shift),
str2int(extclk2_phase_shift),
str2int(extclk3_phase_shift));
if (l_pll_type == "lvds")
i_g0_initial = counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs)), i_m, i_n);
else
i_g0_initial = counter_initial(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs)), i_m, i_n);
i_g1_initial = counter_initial(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs)), i_m, i_n);
i_g2_initial = counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs)), i_m, i_n);
i_g3_initial = counter_initial(get_phase_degree(ph_adjust(str2int(clk3_phase_shift), max_neg_abs)), i_m, i_n);
if (l_pll_type == "lvds")
begin
i_l0_initial = i_g0_initial;
i_l1_initial = i_g0_initial;
end
else
begin
i_l0_initial = counter_initial(get_phase_degree(ph_adjust(str2int(clk4_phase_shift), max_neg_abs)), i_m, i_n);
i_l1_initial = counter_initial(get_phase_degree(ph_adjust(str2int(clk5_phase_shift), max_neg_abs)), i_m, i_n);
end
i_e0_initial = counter_initial(get_phase_degree(ph_adjust(str2int(extclk0_phase_shift), max_neg_abs)), i_m, i_n);
i_e1_initial = counter_initial(get_phase_degree(ph_adjust(str2int(extclk1_phase_shift), max_neg_abs)), i_m, i_n);
i_e2_initial = counter_initial(get_phase_degree(ph_adjust(str2int(extclk2_phase_shift), max_neg_abs)), i_m, i_n);
i_e3_initial = counter_initial(get_phase_degree(ph_adjust(str2int(extclk3_phase_shift), max_neg_abs)), i_m, i_n);
if (l_pll_type == "lvds")
i_g0_mode = counter_mode(clk2_duty_cycle, output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n));
else
i_g0_mode = counter_mode(clk0_duty_cycle, output_counter_value(i_clk0_div_by, i_clk0_mult_by, i_m, i_n));
i_g1_mode = counter_mode(clk1_duty_cycle,output_counter_value(i_clk1_div_by, i_clk1_mult_by, i_m, i_n));
i_g2_mode = counter_mode(clk2_duty_cycle,output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n));
i_g3_mode = counter_mode(clk3_duty_cycle,output_counter_value(i_clk3_div_by, i_clk3_mult_by, i_m, i_n));
if (l_pll_type == "lvds")
begin
i_l0_mode = "bypass";
i_l1_mode = "bypass";
end
else
begin
i_l0_mode = counter_mode(clk4_duty_cycle,output_counter_value(i_clk4_div_by, i_clk4_mult_by, i_m, i_n));
i_l1_mode = counter_mode(clk5_duty_cycle,output_counter_value(i_clk5_div_by, i_clk5_mult_by, i_m, i_n));
end
i_e0_mode = counter_mode(extclk0_duty_cycle,output_counter_value(i_extclk0_div_by, i_extclk0_mult_by, i_m, i_n));
i_e1_mode = counter_mode(extclk1_duty_cycle,output_counter_value(i_extclk1_div_by, i_extclk1_mult_by, i_m, i_n));
i_e2_mode = counter_mode(extclk2_duty_cycle,output_counter_value(i_extclk2_div_by, i_extclk2_mult_by, i_m, i_n));
i_e3_mode = counter_mode(extclk3_duty_cycle,output_counter_value(i_extclk3_div_by, i_extclk3_mult_by, i_m, i_n));
i_m_ph = counter_ph(get_phase_degree(max_neg_abs), i_m, i_n);
i_m_initial = counter_initial(get_phase_degree(max_neg_abs), i_m, i_n);
if (l_pll_type == "lvds")
i_g0_ph = counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs)), i_m, i_n);
else
i_g0_ph = counter_ph(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs)), i_m, i_n);
i_g1_ph = counter_ph(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs)), i_m, i_n);
i_g2_ph = counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs)), i_m, i_n);
i_g3_ph = counter_ph(get_phase_degree(ph_adjust(str2int(clk3_phase_shift),max_neg_abs)), i_m, i_n);
if (l_pll_type == "lvds")
begin
i_l0_ph = i_g0_ph;
i_l1_ph = i_g0_ph;
end
else
begin
i_l0_ph = counter_ph(get_phase_degree(ph_adjust(str2int(clk4_phase_shift),max_neg_abs)), i_m, i_n);
i_l1_ph = counter_ph(get_phase_degree(ph_adjust(str2int(clk5_phase_shift),max_neg_abs)), i_m, i_n);
end
i_e0_ph = counter_ph(get_phase_degree(ph_adjust(str2int(extclk0_phase_shift),max_neg_abs)), i_m, i_n);
i_e1_ph = counter_ph(get_phase_degree(ph_adjust(str2int(extclk1_phase_shift),max_neg_abs)), i_m, i_n);
i_e2_ph = counter_ph(get_phase_degree(ph_adjust(str2int(extclk2_phase_shift),max_neg_abs)), i_m, i_n);
i_e3_ph = counter_ph(get_phase_degree(ph_adjust(str2int(extclk3_phase_shift),max_neg_abs)), i_m, i_n);
if (l_pll_type == "lvds")
i_g0_time_delay = counter_time_delay ( str2int(clk2_time_delay),
i_m_time_delay,
i_n_time_delay);
else
i_g0_time_delay = counter_time_delay ( str2int(clk0_time_delay),
i_m_time_delay,
i_n_time_delay);
i_g1_time_delay = counter_time_delay ( str2int(clk1_time_delay),
i_m_time_delay,
i_n_time_delay);
i_g2_time_delay = counter_time_delay ( str2int(clk2_time_delay),
i_m_time_delay,
i_n_time_delay);
i_g3_time_delay = counter_time_delay ( str2int(clk3_time_delay),
i_m_time_delay,
i_n_time_delay);
if (l_pll_type == "lvds")
begin
i_l0_time_delay = i_g0_time_delay;
i_l1_time_delay = i_g0_time_delay;
end
else
begin
i_l0_time_delay = counter_time_delay ( str2int(clk4_time_delay),
i_m_time_delay,
i_n_time_delay);
i_l1_time_delay = counter_time_delay ( str2int(clk5_time_delay),
i_m_time_delay,
i_n_time_delay);
end
i_e0_time_delay = counter_time_delay ( str2int( extclk0_time_delay),
i_m_time_delay,
i_n_time_delay);
i_e1_time_delay = counter_time_delay ( str2int( extclk1_time_delay),
i_m_time_delay,
i_n_time_delay);
i_e2_time_delay = counter_time_delay ( str2int( extclk2_time_delay),
i_m_time_delay,
i_n_time_delay);
i_e3_time_delay = counter_time_delay ( str2int( extclk3_time_delay),
i_m_time_delay,
i_n_time_delay);
i_extclk3_counter = "e3" ;
i_extclk2_counter = "e2" ;
i_extclk1_counter = "e1" ;
i_extclk0_counter = "e0" ;
i_clk5_counter = "l1" ;
i_clk4_counter = "l0" ;
i_clk3_counter = "g3" ;
i_clk2_counter = "g2" ;
i_clk1_counter = "g1" ;
if (l_pll_type == "lvds")
begin
l_enable0_counter = "l0";
l_enable1_counter = "l1";
i_clk0_counter = "l0" ;
end
else
i_clk0_counter = "g0" ;
// in external feedback mode, need to adjust M value to take
// into consideration the external feedback counter value
if (l_operation_mode == "external_feedback")
begin
// if there is a negative phase shift, m_initial can only be 1
if (max_neg_abs > 0)
i_m_initial = 1;
if (l_feedback_source == "extclk0")
begin
if (i_e0_mode == "bypass")
output_count = 1;
else
output_count = i_e0_high + i_e0_low;
end
else if (l_feedback_source == "extclk1")
begin
if (i_e1_mode == "bypass")
output_count = 1;
else
output_count = i_e1_high + i_e1_low;
end
else if (l_feedback_source == "extclk2")
begin
if (i_e2_mode == "bypass")
output_count = 1;
else
output_count = i_e2_high + i_e2_low;
end
else if (l_feedback_source == "extclk3")
begin
if (i_e3_mode == "bypass")
output_count = 1;
else
output_count = i_e3_high + i_e3_low;
end
else // default to e0
begin
if (i_e0_mode == "bypass")
output_count = 1;
else
output_count = i_e0_high + i_e0_low;
end
new_divisor = gcd(i_m, output_count);
i_m = i_m / new_divisor;
i_n = output_count / new_divisor;
end
end
else
begin // m != 0
i_n = n;
i_m = m;
i_l0_high = l0_high;
i_l1_high = l1_high;
i_g0_high = g0_high;
i_g1_high = g1_high;
i_g2_high = g2_high;
i_g3_high = g3_high;
i_e0_high = e0_high;
i_e1_high = e1_high;
i_e2_high = e2_high;
i_e3_high = e3_high;
i_l0_low = l0_low;
i_l1_low = l1_low;
i_g0_low = g0_low;
i_g1_low = g1_low;
i_g2_low = g2_low;
i_g3_low = g3_low;
i_e0_low = e0_low;
i_e1_low = e1_low;
i_e2_low = e2_low;
i_e3_low = e3_low;
i_l0_initial = l0_initial;
i_l1_initial = l1_initial;
i_g0_initial = g0_initial;
i_g1_initial = g1_initial;
i_g2_initial = g2_initial;
i_g3_initial = g3_initial;
i_e0_initial = e0_initial;
i_e1_initial = e1_initial;
i_e2_initial = e2_initial;
i_e3_initial = e3_initial;
i_l0_mode = alpha_tolower(l0_mode);
i_l1_mode = alpha_tolower(l1_mode);
i_g0_mode = alpha_tolower(g0_mode);
i_g1_mode = alpha_tolower(g1_mode);
i_g2_mode = alpha_tolower(g2_mode);
i_g3_mode = alpha_tolower(g3_mode);
i_e0_mode = alpha_tolower(e0_mode);
i_e1_mode = alpha_tolower(e1_mode);
i_e2_mode = alpha_tolower(e2_mode);
i_e3_mode = alpha_tolower(e3_mode);
i_l0_ph = l0_ph;
i_l1_ph = l1_ph;
i_g0_ph = g0_ph;
i_g1_ph = g1_ph;
i_g2_ph = g2_ph;
i_g3_ph = g3_ph;
i_e0_ph = e0_ph;
i_e1_ph = e1_ph;
i_e2_ph = e2_ph;
i_e3_ph = e3_ph;
i_m_ph = m_ph; // default
i_m_initial = m_initial;
i_l0_time_delay = l0_time_delay;
i_l1_time_delay = l1_time_delay;
i_g0_time_delay = g0_time_delay;
i_g1_time_delay = g1_time_delay;
i_g2_time_delay = g2_time_delay;
i_g3_time_delay = g3_time_delay;
i_e0_time_delay = e0_time_delay;
i_e1_time_delay = e1_time_delay;
i_e2_time_delay = e2_time_delay;
i_e3_time_delay = e3_time_delay;
i_m_time_delay = m_time_delay;
i_n_time_delay = n_time_delay;
i_extclk3_counter = alpha_tolower(extclk3_counter);
i_extclk2_counter = alpha_tolower(extclk2_counter);
i_extclk1_counter = alpha_tolower(extclk1_counter);
i_extclk0_counter = alpha_tolower(extclk0_counter);
i_clk5_counter = alpha_tolower(clk5_counter);
i_clk4_counter = alpha_tolower(clk4_counter);
i_clk3_counter = alpha_tolower(clk3_counter);
i_clk2_counter = alpha_tolower(clk2_counter);
i_clk1_counter = alpha_tolower(clk1_counter);
i_clk0_counter = alpha_tolower(clk0_counter);
end // user to advanced conversion
// set the scan_chain length
if (l_scan_chain == "long")
scan_chain_length = EGPP_SCAN_CHAIN;
else if (l_scan_chain == "short")
scan_chain_length = GPP_SCAN_CHAIN;
if (l_primary_clock == "inclk0")
begin
refclk_period = inclk0_input_frequency * i_n;
primary_clock_frequency = inclk0_input_frequency;
end
else if (l_primary_clock == "inclk1")
begin
refclk_period = inclk1_input_frequency * i_n;
primary_clock_frequency = inclk1_input_frequency;
end
m_times_vco_period = refclk_period;
new_m_times_vco_period = refclk_period;
fbclk_period = 0;
high_time = 0;
low_time = 0;
schedule_vco = 0;
schedule_offset = 1;
vco_out[7:0] = 8'b0;
fbclk_last_value = 0;
offset = 0;
temp_offset = 0;
got_first_refclk = 0;
got_first_fbclk = 0;
fbclk_time = 0;
first_fbclk_time = 0;
refclk_time = 0;
first_schedule = 1;
sched_time = 0;
vco_val = 0;
l0_got_first_rising_edge = 0;
l1_got_first_rising_edge = 0;
vco_l0_last_value = 0;
l0_count = 1;
l1_count = 1;
l0_tmp = 0;
l1_tmp = 0;
gate_count = 0;
gate_out = 0;
initial_delay = 0;
fbk_phase = 0;
for (i = 0; i <= 7; i = i + 1)
begin
phase_shift[i] = 0;
last_phase_shift[i] = 0;
end
fbk_delay = 0;
inclk_n = 0;
cycle_to_adjust = 0;
m_delay = 0;
vco_l0 = 0;
vco_l1 = 0;
total_pull_back = 0;
pull_back_M = 0;
pull_back_ext_cntr = 0;
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 0;
ena_ipd_last_value = 0;
inclk_out_of_range = 0;
scandataout_tmp = 0;
scandataout_trigger = 0;
schedule_vco_last_value = 0;
// set initial values for counter parameters
m_initial_val = i_m_initial;
m_val = i_m;
m_time_delay_val = i_m_time_delay;
n_val = i_n;
n_time_delay_val = i_n_time_delay;
m_ph_val = i_m_ph;
m2_val = m2;
n2_val = n2;
if (m_val == 1)
m_mode_val = "bypass";
if (m2_val == 1)
m2_mode_val = "bypass";
if (n_val == 1)
n_mode_val = "bypass";
if (n2_val == 1)
n2_mode_val = "bypass";
if (skip_vco == "on")
begin
m_val = 1;
m_initial_val = 1;
m_time_delay_val = 0;
m_ph_val = 0;
end
l0_high_val = i_l0_high;
l0_low_val = i_l0_low;
l0_initial_val = i_l0_initial;
l0_mode_val = i_l0_mode;
l0_time_delay_val = i_l0_time_delay;
l1_high_val = i_l1_high;
l1_low_val = i_l1_low;
l1_initial_val = i_l1_initial;
l1_mode_val = i_l1_mode;
l1_time_delay_val = i_l1_time_delay;
g0_high_val = i_g0_high;
g0_low_val = i_g0_low;
g0_initial_val = i_g0_initial;
g0_mode_val = i_g0_mode;
g0_time_delay_val = i_g0_time_delay;
g1_high_val = i_g1_high;
g1_low_val = i_g1_low;
g1_initial_val = i_g1_initial;
g1_mode_val = i_g1_mode;
g1_time_delay_val = i_g1_time_delay;
g2_high_val = i_g2_high;
g2_low_val = i_g2_low;
g2_initial_val = i_g2_initial;
g2_mode_val = i_g2_mode;
g2_time_delay_val = i_g2_time_delay;
g3_high_val = i_g3_high;
g3_low_val = i_g3_low;
g3_initial_val = i_g3_initial;
g3_mode_val = i_g3_mode;
g3_time_delay_val = i_g3_time_delay;
e0_high_val = i_e0_high;
e0_low_val = i_e0_low;
e0_initial_val = i_e0_initial;
e0_mode_val = i_e0_mode;
e0_time_delay_val = i_e0_time_delay;
e1_high_val = i_e1_high;
e1_low_val = i_e1_low;
e1_initial_val = i_e1_initial;
e1_mode_val = i_e1_mode;
e1_time_delay_val = i_e1_time_delay;
e2_high_val = i_e2_high;
e2_low_val = i_e2_low;
e2_initial_val = i_e2_initial;
e2_mode_val = i_e2_mode;
e2_time_delay_val = i_e2_time_delay;
e3_high_val = i_e3_high;
e3_low_val = i_e3_low;
e3_initial_val = i_e3_initial;
e3_mode_val = i_e3_mode;
e3_time_delay_val = i_e3_time_delay;
i = 0;
j = 0;
inclk_last_value = 0;
ext_fbk_cntr_ph = 0;
ext_fbk_cntr_initial = 1;
// initialize clkswitch variables
clk0_is_bad = 0;
clk1_is_bad = 0;
inclk0_last_value = 0;
inclk1_last_value = 0;
other_clock_value = 0;
other_clock_last_value = 0;
primary_clk_is_bad = 0;
current_clk_is_bad = 0;
external_switch = 0;
// current_clock = l_primary_clock;
if (l_primary_clock == "inclk0")
current_clock = 0;
else
current_clock = 1;
if (l_primary_clock == "inclk0")
active_clock = 0;
else
active_clock = 1;
clkloss_tmp = 0;
got_curr_clk_falling_edge_after_clkswitch = 0;
clk0_count = 0;
clk1_count = 0;
switch_over_count = 0;
active_clk_was_switched = 0;
// initialize quiet_time
quiet_time = slowest_clk ( l0_high_val+l0_low_val, l0_mode_val,
l1_high_val+l1_low_val, l1_mode_val,
g0_high_val+g0_low_val, g0_mode_val,
g1_high_val+g1_low_val, g1_mode_val,
g2_high_val+g2_low_val, g2_mode_val,
g3_high_val+g3_low_val, g3_mode_val,
e0_high_val+e0_low_val, e0_mode_val,
e1_high_val+e1_low_val, e1_mode_val,
e2_high_val+e2_low_val, e2_mode_val,
e3_high_val+e3_low_val, e3_mode_val,
l_scan_chain,
refclk_period, m_val);
pll_in_quiet_period = 0;
start_quiet_time = 0;
quiet_period_violation = 0;
reconfig_err = 0;
scanclr_violation = 0;
scanclr_clk_violation = 0;
got_first_scanclk_after_scanclr_inactive_edge = 0;
error = 0;
scanaclr_rising_time = 0;
scanaclr_falling_time = 0;
// VCO feedback loop settings for external feedback mode
// first find which ext counter is used for feedback
if (l_operation_mode == "external_feedback")
begin
if (l_feedback_source == "extclk0")
begin
if (i_extclk0_counter == "e0")
ext_fbk_cntr = "e0";
else if (i_extclk0_counter == "e1")
ext_fbk_cntr = "e1";
else if (i_extclk0_counter == "e2")
ext_fbk_cntr = "e2";
else if (i_extclk0_counter == "e3")
ext_fbk_cntr = "e3";
else ext_fbk_cntr = "e0";
end
else if (l_feedback_source == "extclk1")
begin
if (i_extclk1_counter == "e0")
ext_fbk_cntr = "e0";
else if (i_extclk1_counter == "e1")
ext_fbk_cntr = "e1";
else if (i_extclk1_counter == "e2")
ext_fbk_cntr = "e2";
else if (i_extclk1_counter == "e3")
ext_fbk_cntr = "e3";
else ext_fbk_cntr = "e0";
end
else if (l_feedback_source == "extclk2")
begin
if (i_extclk2_counter == "e0")
ext_fbk_cntr = "e0";
else if (i_extclk2_counter == "e1")
ext_fbk_cntr = "e1";
else if (i_extclk2_counter == "e2")
ext_fbk_cntr = "e2";
else if (i_extclk2_counter == "e3")
ext_fbk_cntr = "e3";
else ext_fbk_cntr = "e0";
end
else if (l_feedback_source == "extclk3")
begin
if (i_extclk3_counter == "e0")
ext_fbk_cntr = "e0";
else if (i_extclk3_counter == "e1")
ext_fbk_cntr = "e1";
else if (i_extclk3_counter == "e2")
ext_fbk_cntr = "e2";
else if (i_extclk3_counter == "e3")
ext_fbk_cntr = "e3";
else ext_fbk_cntr = "e0";
end
// now save this counter's parameters
if (ext_fbk_cntr == "e0")
begin
ext_fbk_cntr_high = e0_high_val;
ext_fbk_cntr_low = e0_low_val;
ext_fbk_cntr_ph = i_e0_ph;
ext_fbk_cntr_initial = i_e0_initial;
ext_fbk_cntr_delay = e0_time_delay_val;
ext_fbk_cntr_mode = e0_mode_val;
end
else if (ext_fbk_cntr == "e1")
begin
ext_fbk_cntr_high = e1_high_val;
ext_fbk_cntr_low = e1_low_val;
ext_fbk_cntr_ph = i_e1_ph;
ext_fbk_cntr_initial = i_e1_initial;
ext_fbk_cntr_delay = e1_time_delay_val;
ext_fbk_cntr_mode = e1_mode_val;
end
else if (ext_fbk_cntr == "e2")
begin
ext_fbk_cntr_high = e2_high_val;
ext_fbk_cntr_low = e2_low_val;
ext_fbk_cntr_ph = i_e2_ph;
ext_fbk_cntr_initial = i_e2_initial;
ext_fbk_cntr_delay = e2_time_delay_val;
ext_fbk_cntr_mode = e2_mode_val;
end
else if (ext_fbk_cntr == "e3")
begin
ext_fbk_cntr_high = e3_high_val;
ext_fbk_cntr_low = e3_low_val;
ext_fbk_cntr_ph = i_e3_ph;
ext_fbk_cntr_initial = i_e3_initial;
ext_fbk_cntr_delay = e3_time_delay_val;
ext_fbk_cntr_mode = e3_mode_val;
end
if (ext_fbk_cntr_mode == "bypass")
ext_fbk_cntr_modulus = 1;
else
ext_fbk_cntr_modulus = ext_fbk_cntr_high + ext_fbk_cntr_low;
end
l_index = 1;
stop_vco = 0;
cycles_to_lock = 0;
cycles_to_unlock = 0;
if (l_pll_type == "fast")
locked_tmp = 1;
else
locked_tmp = 0;
pll_is_locked = 0;
pll_about_to_lock = 0;
no_warn = 0;
m_val_tmp = m_val;
n_val_tmp = n_val;
pll_is_in_reset = 0;
if (l_pll_type == "fast" || l_pll_type == "lvds")
is_fast_pll = 1;
else is_fast_pll = 0;
end
assign inclk_m = l_operation_mode == "external_feedback" ? (l_feedback_source == "extclk0" ? extclk0_tmp :
l_feedback_source == "extclk1" ? extclk1_tmp :
l_feedback_source == "extclk2" ? extclk2_tmp :
l_feedback_source == "extclk3" ? extclk3_tmp : 1'b0) :
vco_out[m_ph_val];
cyclone_m_cntr m1 (.clk(inclk_m),
.reset(areset_ipd || (!ena_ipd) || stop_vco),
.cout(fbclk),
.initial_value(m_initial_val),
.modulus(m_val),
.time_delay(m_delay));
always @(clkswitch_ipd)
begin
if (clkswitch_ipd == 1'b1)
external_switch = 1;
clkloss_tmp <= clkswitch_ipd;
end
always @(inclk0_ipd or inclk1_ipd)
begin
// save the inclk event value
if (inclk0_ipd !== inclk0_last_value)
begin
if (current_clock !== 0)
other_clock_value = inclk0_ipd;
end
if (inclk1_ipd !== inclk1_last_value)
begin
if (current_clock !== 1)
other_clock_value = inclk1_ipd;
end
// check if either input clk is bad
if (inclk0_ipd === 1'b1 && inclk0_ipd !== inclk0_last_value)
begin
clk0_count = clk0_count + 1;
clk0_is_bad = 0;
if (current_clock == 0)
current_clk_is_bad = 0;
clk1_count = 0;
if (clk0_count > 2)
begin
// no event on other clk for 2 cycles
clk1_is_bad = 1;
if (current_clock == 1)
current_clk_is_bad = 1;
end
end
if (inclk1_ipd === 1'b1 && inclk1_ipd !== inclk1_last_value)
begin
clk1_count = clk1_count + 1;
clk1_is_bad = 0;
if (current_clock == 1)
current_clk_is_bad = 0;
clk0_count = 0;
if (clk1_count > 2)
begin
// no event on other clk for 2 cycles
clk0_is_bad = 1;
if (current_clock == 0)
current_clk_is_bad = 1;
end
end
// check if the bad clk is the primary clock
if (((l_primary_clock == "inclk0") && (clk0_is_bad == 1'b1)) || ((l_primary_clock == "inclk1") && (clk1_is_bad == 1'b1)))
primary_clk_is_bad = 1;
else
primary_clk_is_bad = 0;
// actual switching
if ((inclk0_ipd !== inclk0_last_value) && (current_clock == 0))
begin
if (external_switch == 1'b1)
begin
if (!got_curr_clk_falling_edge_after_clkswitch)
begin
if (inclk0_ipd === 1'b0)
got_curr_clk_falling_edge_after_clkswitch = 1;
inclk_n = inclk0_ipd;
end
end
else inclk_n = inclk0_ipd;
end
if ((inclk1_ipd !== inclk1_last_value) && (current_clock == 1))
begin
if (external_switch == 1'b1)
begin
if (!got_curr_clk_falling_edge_after_clkswitch)
begin
if (inclk1_ipd === 1'b0)
got_curr_clk_falling_edge_after_clkswitch = 1;
inclk_n = inclk1_ipd;
end
end
else inclk_n = inclk1_ipd;
end
if ((other_clock_value == 1'b1) && (other_clock_value != other_clock_last_value) && (l_switch_over_on_lossclk == "on") && (l_enable_switch_over_counter == "on") && primary_clk_is_bad)
switch_over_count = switch_over_count + 1;
if ((other_clock_value == 1'b0) && (other_clock_value != other_clock_last_value))
begin
if ((external_switch && (got_curr_clk_falling_edge_after_clkswitch || current_clk_is_bad)) || (l_switch_over_on_lossclk == "on" && primary_clk_is_bad && ((l_enable_switch_over_counter == "off" || switch_over_count == switch_over_counter))))
begin
got_curr_clk_falling_edge_after_clkswitch = 0;
if (current_clock == 0)
begin
current_clock = 1;
end
else
begin
current_clock = 0;
end
active_clock = ~active_clock;
active_clk_was_switched = 1;
switch_over_count = 0;
external_switch = 0;
current_clk_is_bad = 0;
end
end
if (l_switch_over_on_lossclk == "on" && (clkswitch_ipd != 1'b1))
begin
if (primary_clk_is_bad)
clkloss_tmp = 1;
else
clkloss_tmp = 0;
end
inclk0_last_value = inclk0_ipd;
inclk1_last_value = inclk1_ipd;
other_clock_last_value = other_clock_value;
end
and (clkbad[0], clk0_is_bad, 1'b1);
and (clkbad[1], clk1_is_bad, 1'b1);
and (activeclock, active_clock, 1'b1);
and (clkloss, clkloss_tmp, 1'b1);
cyclone_n_cntr n1 ( .clk(inclk_n),
.reset(areset_ipd),
.cout(refclk),
.modulus(n_val),
.time_delay(n_time_delay_val));
cyclone_scale_cntr l0 ( .clk(vco_out[i_l0_ph]),
.reset(areset_ipd || (!ena_ipd) || stop_vco),
.cout(l0_clk),
.high(l0_high_val),
.low(l0_low_val),
.initial_value(l0_initial_val),
.mode(l0_mode_val),
.time_delay(l0_time_delay_val),
.ph_tap(i_l0_ph));
cyclone_scale_cntr l1 ( .clk(vco_out[i_l1_ph]),
.reset(areset_ipd || (!ena_ipd) || stop_vco),
.cout(l1_clk),
.high(l1_high_val),
.low(l1_low_val),
.initial_value(l1_initial_val),
.mode(l1_mode_val),
.time_delay(l1_time_delay_val),
.ph_tap(i_l1_ph));
cyclone_scale_cntr g0 ( .clk(vco_out[i_g0_ph]),
.reset(areset_ipd || (!ena_ipd) || stop_vco),
.cout(g0_clk),
.high(g0_high_val),
.low(g0_low_val),
.initial_value(g0_initial_val),
.mode(g0_mode_val),
.time_delay(g0_time_delay_val),
.ph_tap(i_g0_ph));
cyclone_pll_reg lvds_dffa ( .d(comparator_ipd),
.clrn(1'b1),
.prn(1'b1),
.ena(1'b1),
.clk(g0_clk),
.q(dffa_out));
cyclone_pll_reg lvds_dffb ( .d(dffa_out),
.clrn(1'b1),
.prn(1'b1),
.ena(1'b1),
.clk(lvds_dffb_clk),
.q(dffb_out));
assign lvds_dffb_clk = (l_enable0_counter == "l0") ? l0_clk : (l_enable0_counter == "l1") ? l1_clk : 1'b0;
cyclone_pll_reg lvds_dffc ( .d(dffb_out),
.clrn(1'b1),
.prn(1'b1),
.ena(1'b1),
.clk(lvds_dffc_clk),
.q(dffc_out));
assign lvds_dffc_clk = (l_enable0_counter == "l0") ? l0_clk : (l_enable0_counter == "l1") ? l1_clk : 1'b0;
assign nce_temp = ~dffc_out && dffb_out;
cyclone_pll_reg lvds_dffd ( .d(nce_temp),
.clrn(1'b1),
.prn(1'b1),
.ena(1'b1),
.clk(~lvds_dffd_clk),
.q(dffd_out));
assign lvds_dffd_clk = (l_enable0_counter == "l0") ? l0_clk : (l_enable0_counter == "l1") ? l1_clk : 1'b0;
assign nce_l0 = (l_enable0_counter == "l0") ? dffd_out : 1'b0;
assign nce_l1 = (l_enable0_counter == "l1") ? dffd_out : 1'b0;
cyclone_scale_cntr g1 ( .clk(vco_out[i_g1_ph]),
.reset(areset_ipd || (!ena_ipd) || stop_vco),
.cout(g1_clk),
.high(g1_high_val),
.low(g1_low_val),
.initial_value(g1_initial_val),
.mode(g1_mode_val),
.time_delay(g1_time_delay_val),
.ph_tap(i_g1_ph));
cyclone_scale_cntr g2 ( .clk(vco_out[i_g2_ph]),
.reset(areset_ipd || (!ena_ipd) || stop_vco),
.cout(g2_clk),
.high(g2_high_val),
.low(g2_low_val),
.initial_value(g2_initial_val),
.mode(g2_mode_val),
.time_delay(g2_time_delay_val),
.ph_tap(i_g2_ph));
cyclone_scale_cntr g3 ( .clk(vco_out[i_g3_ph]),
.reset(areset_ipd || (!ena_ipd) || stop_vco),
.cout(g3_clk),
.high(g3_high_val),
.low(g3_low_val),
.initial_value(g3_initial_val),
.mode(g3_mode_val),
.time_delay(g3_time_delay_val),
.ph_tap(i_g3_ph));
assign cntr_e0_initial = (l_operation_mode == "external_feedback" && ext_fbk_cntr == "e0") ? 1 : e0_initial_val;
assign cntr_e0_delay = (l_operation_mode == "external_feedback" && ext_fbk_cntr == "e0") ? ext_fbk_delay : e0_time_delay_val;
cyclone_scale_cntr e0 ( .clk(vco_out[i_e0_ph]),
.reset(areset_ipd || (!ena_ipd) || stop_vco),
.cout(e0_clk),
.high(e0_high_val),
.low(e0_low_val),
.initial_value(cntr_e0_initial),
.mode(e0_mode_val),
.time_delay(cntr_e0_delay),
.ph_tap(i_e0_ph));
assign cntr_e1_initial = (l_operation_mode == "external_feedback" && ext_fbk_cntr == "e1") ? 1 : e1_initial_val;
assign cntr_e1_delay = (l_operation_mode == "external_feedback" && ext_fbk_cntr == "e1") ? ext_fbk_delay : e1_time_delay_val;
cyclone_scale_cntr e1 ( .clk(vco_out[i_e1_ph]),
.reset(areset_ipd || (!ena_ipd) || stop_vco),
.cout(e1_clk),
.high(e1_high_val),
.low(e1_low_val),
.initial_value(cntr_e1_initial),
.mode(e1_mode_val),
.time_delay(cntr_e1_delay),
.ph_tap(i_e1_ph));
assign cntr_e2_initial = (l_operation_mode == "external_feedback" && ext_fbk_cntr == "e2") ? 1 : e2_initial_val;
assign cntr_e2_delay = (l_operation_mode == "external_feedback" && ext_fbk_cntr == "e2") ? ext_fbk_delay : e2_time_delay_val;
cyclone_scale_cntr e2 ( .clk(vco_out[i_e2_ph]),
.reset(areset_ipd || (!ena_ipd) || stop_vco),
.cout(e2_clk),
.high(e2_high_val),
.low(e2_low_val),
.initial_value(cntr_e2_initial),
.mode(e2_mode_val),
.time_delay(cntr_e2_delay),
.ph_tap(i_e2_ph));
assign cntr_e3_initial = (l_operation_mode == "external_feedback" && ext_fbk_cntr == "e3") ? 1 : e3_initial_val;
assign cntr_e3_delay = (l_operation_mode == "external_feedback" && ext_fbk_cntr == "e3") ? ext_fbk_delay : e3_time_delay_val;
cyclone_scale_cntr e3 ( .clk(vco_out[i_e3_ph]),
.reset(areset_ipd || (!ena_ipd) || stop_vco),
.cout(e3_clk),
.high(e3_high_val),
.low(e3_low_val),
.initial_value(cntr_e3_initial),
.mode(e3_mode_val),
.time_delay(cntr_e3_delay),
.ph_tap(i_e3_ph));
always @((vco_out[i_l0_ph] && is_fast_pll) or posedge areset_ipd or negedge ena_ipd or stop_vco)
begin
if ((areset_ipd == 1'b1) || (ena_ipd == 1'b0) || (stop_vco == 1'b1))
begin
l0_count = 1;
l0_got_first_rising_edge = 0;
end
else begin
if (nce_l0 == 1'b0)
begin
if (l0_got_first_rising_edge == 1'b0)
begin
if (vco_out[i_l0_ph] == 1'b1 && vco_out[i_l0_ph] != vco_l0_last_value)
l0_got_first_rising_edge = 1;
end
else if (vco_out[i_l0_ph] != vco_l0_last_value)
begin
l0_count = l0_count + 1;
if (l0_count == (l0_high_val + l0_low_val) * 2)
l0_count = 1;
end
end
if (vco_out[i_l0_ph] == 1'b0 && vco_out[i_l0_ph] != vco_l0_last_value)
begin
if (l0_count == 1)
begin
l0_tmp = 1;
l0_got_first_rising_edge = 0;
end
else l0_tmp = 0;
end
end
vco_l0_last_value = vco_out[i_l0_ph];
end
always @((vco_out[i_l1_ph] && is_fast_pll) or posedge areset_ipd or negedge ena_ipd or stop_vco)
begin
if (areset_ipd == 1'b1 || ena_ipd == 1'b0 || stop_vco == 1'b1)
begin
l1_count = 1;
l1_got_first_rising_edge = 0;
end
else begin
if (nce_l1 == 1'b0)
begin
if (l1_got_first_rising_edge == 1'b0)
begin
if (vco_out[i_l1_ph] == 1'b1 && vco_out[i_l1_ph] != vco_l1_last_value)
l1_got_first_rising_edge = 1;
end
else if (vco_out[i_l1_ph] != vco_l1_last_value)
begin
l1_count = l1_count + 1;
if (l1_count == (l1_high_val + l1_low_val) * 2)
l1_count = 1;
end
end
if (vco_out[i_l1_ph] == 1'b0 && vco_out[i_l1_ph] != vco_l1_last_value)
begin
if (l1_count == 1)
begin
l1_tmp = 1;
l1_got_first_rising_edge = 0;
end
else l1_tmp = 0;
end
end
vco_l1_last_value = vco_out[i_l1_ph];
end
assign enable0_tmp = (l_enable0_counter == "l0") ? l0_tmp : l1_tmp;
assign enable1_tmp = (l_enable1_counter == "l0") ? l0_tmp : l1_tmp;
always @ (inclk_n or ena_ipd or areset_ipd)
begin
if (areset_ipd == 'b1)
begin
gate_count = 0;
gate_out = 0;
end
else if (inclk_n == 'b1 && inclk_last_value != inclk_n)
if (ena_ipd == 'b1)
begin
gate_count = gate_count + 1;
if (gate_count == gate_lock_counter)
gate_out = 1;
end
inclk_last_value = inclk_n;
end
assign locked = (l_gate_lock_signal == "yes") ? gate_out && locked_tmp : locked_tmp;
always @ (scanclk_ipd or scanaclr_ipd)
begin
if (scanaclr_ipd === 1'b1 && scanaclr_last_value === 1'b0)
scanaclr_rising_time = $time;
else if (scanaclr_ipd === 1'b0 && scanaclr_last_value === 1'b1)
begin
scanaclr_falling_time = $time;
// check for scanaclr active pulse width
if ($time - scanaclr_rising_time < TRST)
begin
scanclr_violation = 1;
$display ("Warning : Detected SCANACLR ACTIVE pulse width violation. Required is 5000 ps, actual is %0t. Reconfiguration may not work.", $time - scanaclr_rising_time);
$display ("Time: %0t Instance: %m", $time);
end
else begin
scanclr_violation = 0;
for (i = 0; i <= scan_chain_length; i = i + 1)
scan_data[i] = 0;
end
got_first_scanclk_after_scanclr_inactive_edge = 0;
end
else if ((scanclk_ipd === 'b1 && scanclk_last_value !== scanclk_ipd) && (got_first_scanclk_after_scanclr_inactive_edge === 1'b0) && ($time - scanaclr_falling_time < TRSTCLK))
begin
scanclr_clk_violation = 1;
$display ("Warning : Detected SCANACLR INACTIVE time violation before rising edge of SCANCLK. Required is 5000 ps, actual is %0t. Reconfiguration may not work.", $time - scanaclr_falling_time);
$display ("Time: %0t Instance: %m", $time);
got_first_scanclk_after_scanclr_inactive_edge = 1;
end
else if (scanclk_ipd == 'b1 && scanclk_last_value != scanclk_ipd && scanaclr_ipd === 1'b0)
begin
if (pll_in_quiet_period && ($time - start_quiet_time < quiet_time))
begin
$display("Time: %0t", $time, " Warning : Detected transition on SCANCLK during quiet time. PLL may not function correctly.");
$display ("Time: %0t Instance: %m", $time);
quiet_period_violation = 1;
end
else begin
pll_in_quiet_period = 0;
for (j = scan_chain_length-1; j >= 1; j = j - 1)
begin
scan_data[j] = scan_data[j - 1];
end
scan_data[0] = scandata_ipd;
end
if (got_first_scanclk_after_scanclr_inactive_edge === 1'b0)
begin
got_first_scanclk_after_scanclr_inactive_edge = 1;
scanclr_clk_violation = 0;
end
end
else if (scanclk_ipd === 1'b0 && scanclk_last_value !== scanclk_ipd && scanaclr_ipd === 1'b0)
begin
if (pll_in_quiet_period && ($time - start_quiet_time < quiet_time))
begin
$display("Time: %0t", $time, " Warning : Detected transition on SCANCLK during quiet time. PLL may not function correctly.");
$display ("Time: %0t Instance: %m", $time);
quiet_period_violation = 1;
end
else if (scan_data[scan_chain_length-1] == 1'b1)
begin
pll_in_quiet_period = 1;
quiet_period_violation = 0;
reconfig_err = 0;
start_quiet_time = $time;
// initiate transfer
scandataout_tmp <= 1'b1;
quiet_time = slowest_clk ( l0_high_val+l0_low_val, l0_mode_val,
l1_high_val+l1_low_val, l1_mode_val,
g0_high_val+g0_low_val, g0_mode_val,
g1_high_val+g1_low_val, g1_mode_val,
g2_high_val+g2_low_val, g2_mode_val,
g3_high_val+g3_low_val, g3_mode_val,
e0_high_val+e0_low_val, e0_mode_val,
e1_high_val+e1_low_val, e1_mode_val,
e2_high_val+e2_low_val, e2_mode_val,
e3_high_val+e3_low_val, e3_mode_val,
l_scan_chain,
refclk_period, m_val);
scandataout_trigger <= #(quiet_time) ~scandataout_trigger;
transfer <= 1;
end
end
scanclk_last_value = scanclk_ipd;
scanaclr_last_value = scanaclr_ipd;
end
always @(scandataout_trigger)
begin
if (areset_ipd === 1'b0)
scandataout_tmp <= 1'b0;
end
always @(posedge transfer)
begin
if (transfer == 1'b1)
begin
$display("NOTE : Reconfiguring PLL");
$display ("Time: %0t Instance: %m", $time);
if (l_scan_chain == "long")
begin
// cntr e3
error = 0;
if (scan_data[273] == 1'b1)
begin
e3_mode_val = "bypass";
if (scan_data[283] == 1'b1)
begin
e3_mode_val = "off";
$display("Warning : The specified bit settings will turn OFF the E3 counter. It cannot be turned on unless the part is re-initialized.");
$display ("Time: %0t Instance: %m", $time);
end
end
else if (scan_data[283] == 1'b1)
e3_mode_val = "odd";
else
e3_mode_val = "even";
// before reading delay bits, clear e3_time_delay_val
e3_time_delay_val = 32'b0;
e3_time_delay_val = scan_data[287:284];
e3_time_delay_val = e3_time_delay_val * 250;
if (e3_time_delay_val > 3000)
e3_time_delay_val = 3000;
e3_high_val[8:0] <= scan_data[272:264];
e3_low_val[8:0] <= scan_data[282:274];
if (scan_data[272:264] == 9'b000000000)
e3_high_val[9:0] <= 10'b1000000000;
else
e3_high_val[9] <= 1'b0;
if (scan_data[282:274] == 9'b000000000)
e3_low_val[9:0] <= 10'b1000000000;
else
e3_low_val[9] <= 1'b0;
if (ext_fbk_cntr == "e3")
begin
ext_fbk_cntr_high = e3_high_val;
ext_fbk_cntr_low = e3_low_val;
ext_fbk_cntr_delay = e3_time_delay_val;
ext_fbk_cntr_mode = e3_mode_val;
end
// cntr e2
if (scan_data[249] == 1'b1)
begin
e2_mode_val = "bypass";
if (scan_data[259] == 1'b1)
begin
e2_mode_val = "off";
$display("Warning : The specified bit settings will turn OFF the E2 counter. It cannot be turned on unless the part is re-initialized.");
$display ("Time: %0t Instance: %m", $time);
end
end
else if (scan_data[259] == 1'b1)
e2_mode_val = "odd";
else
e2_mode_val = "even";
e2_time_delay_val = 32'b0;
e2_time_delay_val = scan_data[263:260];
e2_time_delay_val = e2_time_delay_val * 250;
if (e2_time_delay_val > 3000)
e2_time_delay_val = 3000;
e2_high_val[8:0] <= scan_data[248:240];
e2_low_val[8:0] <= scan_data[258:250];
if (scan_data[248:240] == 9'b000000000)
e2_high_val[9:0] <= 10'b1000000000;
else
e2_high_val[9] <= 1'b0;
if (scan_data[258:250] == 9'b000000000)
e2_low_val[9:0] <= 10'b1000000000;
else
e2_low_val[9] <= 1'b0;
if (ext_fbk_cntr == "e2")
begin
ext_fbk_cntr_high = e2_high_val;
ext_fbk_cntr_low = e2_low_val;
ext_fbk_cntr_delay = e2_time_delay_val;
ext_fbk_cntr_mode = e2_mode_val;
end
// cntr e1
if (scan_data[225] == 1'b1)
begin
e1_mode_val = "bypass";
if (scan_data[235] == 1'b1)
begin
e1_mode_val = "off";
$display("Warning : The specified bit settings will turn OFF the E1 counter. It cannot be turned on unless the part is re-initialized.");
$display ("Time: %0t Instance: %m", $time);
end
end
else if (scan_data[235] == 1'b1)
e1_mode_val = "odd";
else
e1_mode_val = "even";
e1_time_delay_val = 32'b0;
e1_time_delay_val = scan_data[239:236];
e1_time_delay_val = e1_time_delay_val * 250;
if (e1_time_delay_val > 3000)
e1_time_delay_val = 3000;
e1_high_val[8:0] <= scan_data[224:216];
e1_low_val[8:0] <= scan_data[234:226];
if (scan_data[224:216] == 9'b000000000)
e1_high_val[9:0] <= 10'b1000000000;
else
e1_high_val[9] <= 1'b0;
if (scan_data[234:226] == 9'b000000000)
e1_low_val[9:0] <= 10'b1000000000;
else
e1_low_val[9] <= 1'b0;
if (ext_fbk_cntr == "e1")
begin
ext_fbk_cntr_high = e1_high_val;
ext_fbk_cntr_low = e1_low_val;
ext_fbk_cntr_delay = e1_time_delay_val;
ext_fbk_cntr_mode = e1_mode_val;
end
// cntr e0
if (scan_data[201] == 1'b1)
begin
e0_mode_val = "bypass";
if (scan_data[211] == 1'b1)
begin
e0_mode_val = "off";
$display("Warning : The specified bit settings will turn OFF the E0 counter. It cannot be turned on unless the part is re-initialized.");
$display ("Time: %0t Instance: %m", $time);
end
end
else if (scan_data[211] == 1'b1)
e0_mode_val = "odd";
else
e0_mode_val = "even";
e0_time_delay_val = 32'b0;
e0_time_delay_val = scan_data[215:212];
e0_time_delay_val = e0_time_delay_val * 250;
if (e0_time_delay_val > 3000)
e0_time_delay_val = 3000;
e0_high_val[8:0] <= scan_data[200:192];
e0_low_val[8:0] <= scan_data[210:202];
if (scan_data[200:192] == 9'b000000000)
e0_high_val[9:0] <= 10'b1000000000;
else
e0_high_val[9] <= 1'b0;
if (scan_data[210:202] == 9'b000000000)
e0_low_val[9:0] <= 10'b1000000000;
else
e0_low_val[9] <= 1'b0;
if (ext_fbk_cntr == "e0")
begin
ext_fbk_cntr_high = e0_high_val;
ext_fbk_cntr_low = e0_low_val;
ext_fbk_cntr_delay = e0_time_delay_val;
ext_fbk_cntr_mode = e0_mode_val;
end
end
// cntr l1
if (scan_data[177] == 1'b1)
begin
l1_mode_val = "bypass";
if (scan_data[187] == 1'b1)
begin
l1_mode_val = "off";
$display("Warning : The specified bit settings will turn OFF the L1 counter. It cannot be turned on unless the part is re-initialized.");
$display ("Time: %0t Instance: %m", $time);
end
end
else if (scan_data[187] == 1'b1)
l1_mode_val = "odd";
else
l1_mode_val = "even";
l1_time_delay_val = 32'b0;
l1_time_delay_val = scan_data[191:188];
l1_time_delay_val = l1_time_delay_val * 250;
if (l1_time_delay_val > 3000)
l1_time_delay_val = 3000;
l1_high_val[8:0] <= scan_data[176:168];
l1_low_val[8:0] <= scan_data[186:178];
if (scan_data[176:168] == 9'b000000000)
l1_high_val[9:0] <= 10'b1000000000;
else
l1_high_val[9] <= 1'b0;
if (scan_data[186:178] == 9'b000000000)
l1_low_val[9:0] <= 10'b1000000000;
else
l1_low_val[9] <= 1'b0;
// cntr l0
if (scan_data[153] == 1'b1)
begin
l0_mode_val = "bypass";
if (scan_data[163] == 1'b1)
begin
l0_mode_val = "off";
$display("Warning : The specified bit settings will turn OFF the L0 counter. It cannot be turned on unless the part is re-initialized.");
$display ("Time: %0t Instance: %m", $time);
end
end
else if (scan_data[163] == 1'b1)
l0_mode_val = "odd";
else
l0_mode_val = "even";
l0_time_delay_val = 32'b0;
l0_time_delay_val = scan_data[167:164];
l0_time_delay_val = l0_time_delay_val * 250;
if (l0_time_delay_val > 3000)
l0_time_delay_val = 3000;
l0_high_val[8:0] <= scan_data[152:144];
l0_low_val[8:0] <= scan_data[162:154];
if (scan_data[152:144] == 9'b000000000)
l0_high_val[9:0] <= 10'b1000000000;
else
l0_high_val[9] <= 1'b0;
if (scan_data[162:154] == 9'b000000000)
l0_low_val[9:0] <= 10'b1000000000;
else
l0_low_val[9] <= 1'b0;
// cntr g3
if (scan_data[129] == 1'b1)
begin
g3_mode_val = "bypass";
if (scan_data[139] == 1'b1)
begin
g3_mode_val = "off";
$display("Warning : The specified bit settings will turn OFF the G3 counter. It cannot be turned on unless the part is re-initialized.");
$display ("Time: %0t Instance: %m", $time);
end
end
else if (scan_data[139] == 1'b1)
g3_mode_val = "odd";
else
g3_mode_val = "even";
g3_time_delay_val = 32'b0;
g3_time_delay_val = scan_data[143:140];
g3_time_delay_val = g3_time_delay_val * 250;
if (g3_time_delay_val > 3000)
g3_time_delay_val = 3000;
g3_high_val[8:0] <= scan_data[128:120];
g3_low_val[8:0] <= scan_data[138:130];
if (scan_data[128:120] == 9'b000000000)
g3_high_val[9:0] <= 10'b1000000000;
else
g3_high_val[9] <= 1'b0;
if (scan_data[138:130] == 9'b000000000)
g3_low_val[9:0] <= 10'b1000000000;
else
g3_low_val[9] <= 1'b0;
// cntr g2
if (scan_data[105] == 1'b1)
begin
g2_mode_val = "bypass";
if (scan_data[115] == 1'b1)
begin
g2_mode_val = "off";
$display("Warning : The specified bit settings will turn OFF the G2 counter. It cannot be turned on unless the part is re-initialized.");
$display ("Time: %0t Instance: %m", $time);
end
end
else if (scan_data[115] == 1'b1)
g2_mode_val = "odd";
else
g2_mode_val = "even";
g2_time_delay_val = 32'b0;
g2_time_delay_val = scan_data[119:116];
g2_time_delay_val = g2_time_delay_val * 250;
if (g2_time_delay_val > 3000)
g2_time_delay_val = 3000;
g2_high_val[8:0] <= scan_data[104:96];
g2_low_val[8:0] <= scan_data[114:106];
if (scan_data[104:96] == 9'b000000000)
g2_high_val[9:0] <= 10'b1000000000;
else
g2_high_val[9] <= 1'b0;
if (scan_data[114:106] == 9'b000000000)
g2_low_val[9:0] <= 10'b1000000000;
else
g2_low_val[9] <= 1'b0;
// cntr g1
if (scan_data[81] == 1'b1)
begin
g1_mode_val = "bypass";
if (scan_data[91] == 1'b1)
begin
g1_mode_val = "off";
$display("Warning : The specified bit settings will turn OFF the G1 counter. It cannot be turned on unless the part is re-initialized.");
$display ("Time: %0t Instance: %m", $time);
end
end
else if (scan_data[91] == 1'b1)
g1_mode_val = "odd";
else
g1_mode_val = "even";
g1_time_delay_val = 32'b0;
g1_time_delay_val = scan_data[95:92];
g1_time_delay_val = g1_time_delay_val * 250;
if (g1_time_delay_val > 3000)
g1_time_delay_val = 3000;
g1_high_val[8:0] <= scan_data[80:72];
g1_low_val[8:0] <= scan_data[90:82];
if (scan_data[80:72] == 9'b000000000)
g1_high_val[9:0] <= 10'b1000000000;
else
g1_high_val[9] <= 1'b0;
if (scan_data[90:82] == 9'b000000000)
g1_low_val[9:0] <= 10'b1000000000;
else
g1_low_val[9] <= 1'b0;
// cntr g0
if (scan_data[57] == 1'b1)
begin
g0_mode_val = "bypass";
if (scan_data[67] == 1'b1)
begin
g0_mode_val = "off";
$display("Warning : The specified bit settings will turn OFF the G0 counter. It cannot be turned on unless the part is re-initialized.");
$display ("Time: %0t Instance: %m", $time);
end
end
else if (scan_data[67] == 1'b1)
g0_mode_val = "odd";
else
g0_mode_val = "even";
g0_time_delay_val = 32'b0;
g0_time_delay_val = scan_data[71:68];
g0_time_delay_val = g0_time_delay_val * 250;
if (g0_time_delay_val > 3000)
g0_time_delay_val = 3000;
g0_high_val[8:0] <= scan_data[56:48];
g0_low_val[8:0] <= scan_data[66:58];
if (scan_data[56:48] == 9'b000000000)
g0_high_val[9:0] <= 10'b1000000000;
else
g0_high_val[9] <= 1'b0;
if (scan_data[66:58] == 9'b000000000)
g0_low_val[9:0] <= 10'b1000000000;
else
g0_low_val[9] <= 1'b0;
// cntr M
error = 0;
m_val_tmp = 0;
m_val_tmp[8:0] = scan_data[32:24];
if (scan_data[33] !== 1'b1)
begin
if (m_val_tmp[8:0] == 9'b000000001)
begin
reconfig_err = 1;
error = 1;
$display ("Warning : Illegal 1 value for M counter. Instead, the M counter should be BYPASSED. Reconfiguration may not work.");
$display ("Time: %0t Instance: %m", $time);
end
else if (m_val_tmp[8:0] == 9'b000000000)
m_val_tmp[9:0] = 10'b1000000000;
if (error == 1'b0)
begin
if (m_mode_val === "bypass")
$display ("Warning : M counter switched from BYPASS mode to enabled (M modulus = %d). PLL may lose lock.", m_val_tmp[9:0]);
else
$display("PLL reconfigured with : M modulus = %d ", m_val_tmp[9:0]);
$display ("Time: %0t Instance: %m", $time);
m_mode_val = "";
end
end
else if (scan_data[33] == 1'b1)
begin
if (scan_data[24] !== 1'b0)
begin
reconfig_err = 1;
error = 1;
$display ("Warning : Illegal value for counter M in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work.");
$display ("Time: %0t Instance: %m", $time);
end
else begin
if (m_mode_val !== "bypass")
$display ("Warning : M counter switched from enabled to BYPASS mode. PLL may lose lock.");
m_val_tmp[9:0] = 10'b0000000001;
m_mode_val = "bypass";
$display("PLL reconfigured with : M modulus = %d ", m_val_tmp[9:0]);
$display ("Time: %0t Instance: %m", $time);
end
end
if (skip_vco == "on")
m_val_tmp[9:0] = 10'b0000000001;
// cntr M2
if (ss > 0)
begin
error = 0;
m2_val[8:0] = scan_data[42:34];
if (scan_data[43] !== 1'b1)
begin
if (m2_val[8:0] == 9'b000000001)
begin
reconfig_err = 1;
error = 1;
$display ("Warning : Illegal 1 value for M2 counter. Instead, the M2 counter should be BYPASSED. Reconfiguration may not work.");
$display ("Time: %0t Instance: %m", $time);
end
else if (m2_val[8:0] == 9'b000000000)
m2_val[9:0] = 10'b1000000000;
if (error == 1'b0)
begin
if (m2_mode_val === "bypass")
begin
$display ("Warning : M2 counter switched from BYPASS mode to enabled (M2 modulus = %d). Pll may lose lock.", m2_val[9:0]);
$display ("Time: %0t Instance: %m", $time);
end
else
begin
$display(" M2 modulus = %d ", m2_val[9:0]);
$display ("Time: %0t Instance: %m", $time);
end
m2_mode_val = "";
end
end
else if (scan_data[43] == 1'b1)
begin
if (scan_data[34] !== 1'b0)
begin
reconfig_err = 1;
error = 1;
$display ("Warning : Illegal value for counter M2 in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work.");
$display ("Time: %0t Instance: %m", $time);
end
else begin
if (m2_mode_val !== "bypass")
begin
$display ("Warning : M2 counter switched from enabled to BYPASS mode. PLL may lose lock.");
end
m2_val[9:0] = 10'b0000000001;
m2_mode_val = "bypass";
$display(" M2 modulus = %d ", m2_val[9:0]);
$display ("Time: %0t Instance: %m", $time);
end
end
if (m_mode_val != m2_mode_val)
begin
reconfig_err = 1;
error = 1;
$display ("Warning : Incompatible modes for M1/M2 counters. Either both should be BYASSED or both NON-BYPASSED. Reconfiguration may not work.");
$display ("Time: %0t Instance: %m", $time);
end
end
m_time_delay_val = 32'b0;
m_time_delay_val = scan_data[47:44];
m_time_delay_val = m_time_delay_val * 250;
if (m_time_delay_val > 3000)
m_time_delay_val = 3000;
if (skip_vco == "on")
m_time_delay_val = 32'b0;
$display(" M time delay = %0d", m_time_delay_val);
$display ("Time: %0t Instance: %m", $time);
// cntr N
error = 0;
n_val_tmp[8:0] = scan_data[8:0];
n_val_tmp[9] = 1'b0;
if (scan_data[9] !== 1'b1)
begin
if (n_val_tmp[8:0] == 9'b000000001)
begin
reconfig_err = 1;
error = 1;
$display ("Warning : Illegal 1 value for N counter. Instead, the N counter should be BYPASSED. Reconfiguration may not work.");
$display ("Time: %0t Instance: %m", $time);
end
else if (n_val_tmp[8:0] == 9'b000000000)
n_val_tmp[9:0] = 10'b1000000000;
if (error == 1'b0)
begin
if (n_mode_val === "bypass")
begin
$display ("Warning : N counter switched from BYPASS mode to enabled (N modulus = %d). PLL may lose lock.", n_val_tmp[9:0]);
$display ("Time: %0t Instance: %m", $time);
end
else
begin
$display(" N modulus = %d ", n_val_tmp[9:0]);
$display ("Time: %0t Instance: %m", $time);
end
n_mode_val = "";
end
end
else if (scan_data[9] == 1'b1) // bypass
begin
if (scan_data[0] !== 1'b0)
begin
reconfig_err = 1;
error = 1;
$display ("Warning : Illegal value for counter N in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work.");
$display ("Time: %0t Instance: %m", $time);
end
else begin
if (n_mode_val !== "bypass")
begin
$display ("Warning : N counter switched from enabled to BYPASS mode. PLL may lose lock.");
$display ("Time: %0t Instance: %m", $time);
end
n_val_tmp[9:0] = 10'b0000000001;
n_mode_val = "bypass";
$display(" N modulus = %d ", n_val_tmp[9:0]);
$display ("Time: %0t Instance: %m", $time);
end
end
// cntr N2
if (ss > 0)
begin
error = 0;
n2_val[8:0] = scan_data[18:10];
if (scan_data[19] !== 1'b1)
begin
if (n2_val[8:0] == 9'b000000001)
begin
reconfig_err = 1;
error = 1;
$display ("Warning : Illegal 1 value for N2 counter. Instead, the N2 counter should be BYPASSED. Reconfiguration may not work.");
$display ("Time: %0t Instance: %m", $time);
end
else if (n2_val[8:0] == 9'b000000000)
n2_val = 10'b1000000000;
if (error == 1'b0)
begin
if (n2_mode_val === "bypass")
begin
$display ("Warning : N2 counter switched from BYPASS mode to enabled (N2 modulus = %d). PLL may lose lock.", n2_val[9:0]);
$display ("Time: %0t Instance: %m", $time);
end
else
begin
$display(" N2 modulus = %d ", n2_val[9:0]);
$display ("Time: %0t Instance: %m", $time);
end
n2_mode_val = "";
end
end
else if (scan_data[19] == 1'b1) // bypass
begin
if (scan_data[10] !== 1'b0)
begin
reconfig_err = 1;
error = 1;
$display ("Warning : Illegal value for counter N2 in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work.");
$display ("Time: %0t Instance: %m", $time);
end
else begin
if (n2_mode_val !== "bypass")
begin
$display ("Warning : N2 counter switched from enabled to BYPASS mode. PLL may lose lock.");
$display ("Time: %0t Instance: %m", $time);
end
n2_val[9:0] = 10'b0000000001;
n2_mode_val = "bypass";
$display(" N2 modulus = %d ", n2_val[9:0]);
$display ("Time: %0t Instance: %m", $time);
end
end
if (n_mode_val != n2_mode_val)
begin
reconfig_err = 1;
error = 1;
$display ("Warning : Incompatible modes for N1/N2 counters. Either both should be BYASSED or both NON-BYPASSED.");
$display ("Time: %0t Instance: %m", $time);
end
end // ss > 0
n_time_delay_val = 32'b0;
n_time_delay_val = scan_data[23:20];
n_time_delay_val = n_time_delay_val * 250;
if (n_time_delay_val > 3000)
n_time_delay_val = 3000;
$display(" N time delay = %0d", n_time_delay_val);
$display ("Time: %0t Instance: %m", $time);
transfer <= 0;
// clear the scan_chain
for (i = 0; i <= scan_chain_length; i = i + 1)
scan_data[i] = 0;
end
end
always @(negedge transfer)
begin
if (l_scan_chain == "long")
begin
$display(" E3 high = %d, E3 low = %d, E3 mode = %s, E3 time delay = %0d", e3_high_val[9:0], e3_low_val[9:0], e3_mode_val, e3_time_delay_val);
$display(" E2 high = %d, E2 low = %d, E2 mode = %s, E2 time delay = %0d", e2_high_val[9:0], e2_low_val[9:0], e2_mode_val, e2_time_delay_val);
$display(" E1 high = %d, E1 low = %d, E1 mode = %s, E1 time delay = %0d", e1_high_val[9:0], e1_low_val[9:0], e1_mode_val, e1_time_delay_val);
$display(" E0 high = %d, E0 low = %d, E0 mode = %s, E0 time delay = %0d", e0_high_val[9:0], e0_low_val[9:0], e0_mode_val, e0_time_delay_val);
end
$display(" L1 high = %d, L1 low = %d, L1 mode = %s, L1 time delay = %0d", l1_high_val[9:0], l1_low_val[9:0], l1_mode_val, l1_time_delay_val);
$display(" L0 high = %d, L0 low = %d, L0 mode = %s, L0 time delay = %0d", l0_high_val[9:0], l0_low_val[9:0], l0_mode_val, l0_time_delay_val);
$display(" G3 high = %d, G3 low = %d, G3 mode = %s, G3 time delay = %0d", g3_high_val[9:0], g3_low_val[9:0], g3_mode_val, g3_time_delay_val);
$display(" G2 high = %d, G2 low = %d, G2 mode = %s, G2 time delay = %0d", g2_high_val[9:0], g2_low_val[9:0], g2_mode_val, g2_time_delay_val);
$display(" G1 high = %d, G1 low = %d, G1 mode = %s, G1 time delay = %0d", g1_high_val[9:0], g1_low_val[9:0], g1_mode_val, g1_time_delay_val);
$display(" G0 high = %d, G0 low = %d, G0 mode = %s, G0 time delay = %0d", g0_high_val[9:0], g0_low_val[9:0], g0_mode_val, g0_time_delay_val);
$display ("Time: %0t Instance: %m", $time);
end
always @(schedule_vco or areset_ipd or ena_ipd)
begin
sched_time = 0;
for (i = 0; i <= 7; i=i+1)
last_phase_shift[i] = phase_shift[i];
cycle_to_adjust = 0;
l_index = 1;
m_times_vco_period = new_m_times_vco_period;
// give appropriate messages
// if areset was asserted
if (areset_ipd == 1'b1 && areset_ipd_last_value !== areset_ipd)
begin
$display (" Note : %s PLL was reset", family_name);
$display ("Time: %0t Instance: %m", $time);
end
// if areset is deasserted
if (areset_ipd === 1'b0 && areset_ipd_last_value === 1'b1)
begin
// deassert scandataout now and allow reconfig to complete if
// areset was high during reconfig
if (scandataout_tmp === 1'b1)
scandataout_tmp <= #(quiet_time) 1'b0;
end
// if ena was deasserted
if (ena_ipd == 1'b0 && ena_ipd_last_value !== ena_ipd)
begin
$display (" Note : %s PLL was disabled", family_name);
$display ("Time: %0t Instance: %m", $time);
end
// illegal value on areset_ipd
if (areset_ipd === 1'bx && (areset_ipd_last_value === 1'b0 || areset_ipd_last_value === 1'b1))
begin
$display("Warning : Illegal value 'X' detected on ARESET input");
$display ("Time: %0t Instance: %m", $time);
end
if ((schedule_vco !== schedule_vco_last_value) && (areset_ipd == 1'b1 || ena_ipd == 1'b0 || stop_vco == 1'b1))
begin
if (areset_ipd === 1'b1)
pll_is_in_reset = 1;
// drop VCO taps to 0
for (i = 0; i <= 7; i=i+1)
begin
for (j = 0; j <= last_phase_shift[i] + 1; j=j+1)
vco_out[i] <= #(j) 1'b0;
phase_shift[i] = 0;
last_phase_shift[i] = 0;
end
// reset lock parameters
locked_tmp = 0;
if (l_pll_type == "fast")
locked_tmp = 1;
pll_is_locked = 0;
pll_about_to_lock = 0;
cycles_to_lock = 0;
cycles_to_unlock = 0;
got_first_refclk = 0;
got_second_refclk = 0;
refclk_time = 0;
got_first_fbclk = 0;
fbclk_time = 0;
first_fbclk_time = 0;
fbclk_period = 0;
first_schedule = 1;
schedule_offset = 1;
vco_val = 0;
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 0;
// reset enable0 and enable1 counter parameters
// l0_count = 1;
// l1_count = 1;
// l0_got_first_rising_edge = 0;
// l1_got_first_rising_edge = 0;
end else if (ena_ipd === 1'b1 && areset_ipd === 1'b0 && stop_vco === 1'b0)
begin
// else note areset deassert time
// note it as refclk_time to prevent false triggering
// of stop_vco after areset
if (areset_ipd === 1'b0 && areset_ipd_last_value === 1'b1 && pll_is_in_reset === 1'b1)
begin
refclk_time = $time;
pll_is_in_reset = 0;
end
// calculate loop_xplier : this will be different from m_val in ext. fbk mode
loop_xplier = m_val;
loop_initial = i_m_initial - 1;
loop_ph = i_m_ph;
loop_time_delay = m_time_delay_val;
if (l_operation_mode == "external_feedback")
begin
if (ext_fbk_cntr_mode == "bypass")
ext_fbk_cntr_modulus = 1;
else
ext_fbk_cntr_modulus = ext_fbk_cntr_high + ext_fbk_cntr_low;
loop_xplier = m_val * (ext_fbk_cntr_modulus);
loop_ph = ext_fbk_cntr_ph;
loop_initial = ext_fbk_cntr_initial - 1 + ((i_m_initial - 1) * (ext_fbk_cntr_modulus));
loop_time_delay = m_time_delay_val + ext_fbk_cntr_delay;
end
// convert initial value to delay
initial_delay = (loop_initial * m_times_vco_period)/loop_xplier;
// convert loop ph_tap to delay
rem = m_times_vco_period % loop_xplier;
vco_per = m_times_vco_period/loop_xplier;
if (rem != 0)
vco_per = vco_per + 1;
fbk_phase = (loop_ph * vco_per)/8;
if (l_operation_mode == "external_feedback")
begin
pull_back_ext_cntr = ext_fbk_cntr_delay + (ext_fbk_cntr_initial - 1) * (m_times_vco_period/loop_xplier) + fbk_phase;
while (pull_back_ext_cntr > refclk_period)
pull_back_ext_cntr = pull_back_ext_cntr - refclk_period;
pull_back_M = m_time_delay_val + (i_m_initial - 1) * (ext_fbk_cntr_modulus) * (m_times_vco_period/loop_xplier);
while (pull_back_M > refclk_period)
pull_back_M = pull_back_M - refclk_period;
end
else begin
pull_back_ext_cntr = 0;
pull_back_M = initial_delay + m_time_delay_val + fbk_phase;
end
total_pull_back = pull_back_M + pull_back_ext_cntr;
if (l_simulation_type == "timing")
total_pull_back = total_pull_back + pll_compensation_delay;
while (total_pull_back > refclk_period)
total_pull_back = total_pull_back - refclk_period;
if (total_pull_back > 0)
offset = refclk_period - total_pull_back;
if (l_operation_mode == "external_feedback")
begin
fbk_delay = pull_back_M;
if (l_simulation_type == "timing")
fbk_delay = fbk_delay + pll_compensation_delay;
ext_fbk_delay = pull_back_ext_cntr - fbk_phase;
end
else begin
fbk_delay = total_pull_back - fbk_phase;
if (fbk_delay < 0)
begin
offset = offset - fbk_phase;
fbk_delay = total_pull_back;
end
end
// assign m_delay
m_delay = fbk_delay;
for (i = 1; i <= loop_xplier; i=i+1)
begin
// adjust cycles
tmp_vco_per = m_times_vco_period/loop_xplier;
if (rem != 0 && l_index <= rem)
begin
tmp_rem = (loop_xplier * l_index) % rem;
cycle_to_adjust = (loop_xplier * l_index) / rem;
if (tmp_rem != 0)
cycle_to_adjust = cycle_to_adjust + 1;
end
if (cycle_to_adjust == i)
begin
tmp_vco_per = tmp_vco_per + 1;
l_index = l_index + 1;
end
// calculate high and low periods
high_time = tmp_vco_per/2;
if (tmp_vco_per % 2 != 0)
high_time = high_time + 1;
low_time = tmp_vco_per - high_time;
// schedule the rising and falling egdes
for (j=0; j<=1; j=j+1)
begin
vco_val = ~vco_val;
if (vco_val == 1'b0)
sched_time = sched_time + high_time;
else
sched_time = sched_time + low_time;
// add offset
if (schedule_offset == 1'b1)
begin
sched_time = sched_time + offset;
schedule_offset = 0;
end
// schedule taps with appropriate phase shifts
for (k = 0; k <= 7; k=k+1)
begin
phase_shift[k] = (k*tmp_vco_per)/8;
if (first_schedule)
vco_out[k] <= #(sched_time + phase_shift[k]) vco_val;
else
vco_out[k] <= #(sched_time + last_phase_shift[k]) vco_val;
end
end
end
if (first_schedule)
begin
vco_val = ~vco_val;
if (vco_val == 1'b0)
sched_time = sched_time + high_time;
else
sched_time = sched_time + low_time;
for (k = 0; k <= 7; k=k+1)
begin
phase_shift[k] = (k*tmp_vco_per)/8;
vco_out[k] <= #(sched_time+phase_shift[k]) vco_val;
end
first_schedule = 0;
end
// this may no longer be required
if (sched_time > 0)
schedule_vco <= #(sched_time) ~schedule_vco;
if (vco_period_was_phase_adjusted)
begin
m_times_vco_period = refclk_period;
new_m_times_vco_period = refclk_period;
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 1;
tmp_vco_per = m_times_vco_period/loop_xplier;
for (k = 0; k <= 7; k=k+1)
phase_shift[k] = (k*tmp_vco_per)/8;
end
end
areset_ipd_last_value = areset_ipd;
ena_ipd_last_value = ena_ipd;
schedule_vco_last_value = schedule_vco;
end
always @(pfdena_ipd)
begin
if (pfdena_ipd === 1'b0)
begin
locked_tmp = 1'bx;
pll_is_locked = 0;
cycles_to_lock = 0;
$display (" Note : PFDENA was deasserted");
$display ("Time: %0t Instance: %m", $time);
end
else if (pfdena_ipd === 1'b1 && pfdena_ipd_last_value === 1'b0)
begin
// PFD was disabled, now enabled again
got_first_refclk = 0;
got_second_refclk = 0;
refclk_time = $time;
end
pfdena_ipd_last_value = pfdena_ipd;
end
always @(negedge refclk)
begin
refclk_last_value = refclk;
end
always @(negedge fbclk)
begin
fbclk_last_value = fbclk;
end
always @(posedge refclk or posedge fbclk)
begin
if (refclk == 1'b1 && refclk_last_value !== refclk && areset_ipd === 1'b0)
begin
n_val <= n_val_tmp;
if (! got_first_refclk)
begin
got_first_refclk = 1;
end else
begin
got_second_refclk = 1;
refclk_period = $time - refclk_time;
// check if incoming freq. will cause VCO range to be
// exceeded
if ( (vco_max != 0 && vco_min != 0) && (skip_vco == "off") && (pfdena_ipd === 1'b1) &&
((refclk_period/loop_xplier > vco_max) ||
(refclk_period/loop_xplier < vco_min)) )
begin
if (pll_is_locked == 1'b1)
begin
$display ("Warning : Input clock freq. is not within VCO range. PLL may lose lock");
$display ("Time: %0t Instance: %m", $time);
if (inclk_out_of_range === 1'b1)
begin
// unlock
pll_is_locked = 0;
locked_tmp = 0;
if (l_pll_type == "fast")
locked_tmp = 1;
pll_about_to_lock = 0;
cycles_to_lock = 0;
$display ("Note : %s PLL lost lock", family_name);
$display ("Time: %0t Instance: %m", $time);
first_schedule = 1;
schedule_offset = 1;
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 0;
end
end
else begin
if (no_warn == 0)
begin
$display ("Warning : Input clock freq. is not within VCO range. PLL may not lock");
$display ("Time: %0t Instance: %m", $time);
no_warn = 1;
end
end
inclk_out_of_range = 1;
end
else begin
inclk_out_of_range = 0;
end
end
if (stop_vco == 1'b1)
begin
stop_vco = 0;
schedule_vco = ~schedule_vco;
end
refclk_time = $time;
end
if (fbclk == 1'b1 && fbclk_last_value !== fbclk)
begin
m_val <= m_val_tmp;
if (!got_first_fbclk)
begin
got_first_fbclk = 1;
first_fbclk_time = $time;
end
else
fbclk_period = $time - fbclk_time;
// need refclk_period here, so initialized to proper value above
if ( ( ($time - refclk_time > 1.5 * refclk_period) && pfdena_ipd === 1'b1 && pll_is_locked == 1'b1) || ( ($time - refclk_time > 5 * refclk_period) && pfdena_ipd === 1'b1) )
begin
stop_vco = 1;
// reset
got_first_refclk = 0;
got_first_fbclk = 0;
got_second_refclk = 0;
if (pll_is_locked == 1'b1)
begin
pll_is_locked = 0;
locked_tmp = 0;
if (l_pll_type == "fast")
locked_tmp = 1;
$display ("Note : %s PLL lost lock due to loss of input clock", family_name);
$display ("Time: %0t Instance: %m", $time);
end
pll_about_to_lock = 0;
cycles_to_lock = 0;
cycles_to_unlock = 0;
first_schedule = 1;
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 0;
end
fbclk_time = $time;
end
if (got_second_refclk && pfdena_ipd === 1'b1 && (!inclk_out_of_range))
begin
// now we know actual incoming period
// if (abs(refclk_period - fbclk_period) > 2)
// begin
// new_m_times_vco_period = refclk_period;
// end
// else if (abs(fbclk_time - refclk_time) <= 2 || (refclk_period - abs(fbclk_time - refclk_time) <= 2))
if (abs(fbclk_time - refclk_time) <= 5 || (got_first_fbclk && abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5))
begin
// considered in phase
if (cycles_to_lock == valid_lock_multiplier - 1)
pll_about_to_lock <= 1;
if (cycles_to_lock == valid_lock_multiplier)
begin
if (pll_is_locked === 1'b0)
begin
$display (" Note : %s PLL locked to incoming clock", family_name);
$display ("Time: %0t Instance: %m", $time);
end
pll_is_locked = 1;
locked_tmp = 1;
if (l_pll_type == "fast")
locked_tmp = 0;
end
// increment lock counter only if the second part of the above
// time check is NOT true
if (!(abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5))
begin
cycles_to_lock = cycles_to_lock + 1;
end
// adjust m_times_vco_period
new_m_times_vco_period = refclk_period;
end else
begin
// if locked, begin unlock
if (pll_is_locked)
begin
cycles_to_unlock = cycles_to_unlock + 1;
if (cycles_to_unlock == invalid_lock_multiplier)
begin
pll_is_locked = 0;
locked_tmp = 0;
if (l_pll_type == "fast")
locked_tmp = 1;
pll_about_to_lock = 0;
cycles_to_lock = 0;
$display ("Note : %s PLL lost lock", family_name);
$display ("Time: %0t Instance: %m", $time);
first_schedule = 1;
schedule_offset = 1;
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 0;
end
end
if (abs(refclk_period - fbclk_period) <= 2)
begin
// frequency is still good
if ($time == fbclk_time && (!phase_adjust_was_scheduled))
begin
if (abs(fbclk_time - refclk_time) > refclk_period/2)
begin
if (abs(fbclk_time - refclk_time) > 1.5 * refclk_period)
begin
// input clock may have stopped : do nothing
end
else begin
new_m_times_vco_period = m_times_vco_period + (refclk_period - abs(fbclk_time - refclk_time));
vco_period_was_phase_adjusted = 1;
end
end else
begin
new_m_times_vco_period = m_times_vco_period - abs(fbclk_time - refclk_time);
vco_period_was_phase_adjusted = 1;
end
end
end else
begin
new_m_times_vco_period = refclk_period;
phase_adjust_was_scheduled = 0;
end
end
end
if (quiet_period_violation == 1'b1 || reconfig_err == 1'b1 || scanclr_violation == 1'b1 || scanclr_clk_violation == 1'b1)
begin
locked_tmp = 0;
if (l_pll_type == "fast")
locked_tmp = 1;
end
refclk_last_value = refclk;
fbclk_last_value = fbclk;
end
assign clk0_tmp = i_clk0_counter == "l0" ? l0_clk : i_clk0_counter == "l1" ? l1_clk : i_clk0_counter == "g0" ? g0_clk : i_clk0_counter == "g1" ? g1_clk : i_clk0_counter == "g2" ? g2_clk : i_clk0_counter == "g3" ? g3_clk : 1'b0;
assign clk0 = (areset_ipd === 1'b1 || ena_ipd === 1'b0) || (pll_about_to_lock == 1'b1 && !quiet_period_violation && !reconfig_err && !scanclr_violation && !scanclr_clk_violation) ? clk0_tmp : 1'bx;
cyclone_dffe ena0_reg ( .D(clkena0_ipd),
.CLRN(1'b1),
.PRN(1'b1),
.ENA(1'b1),
.CLK(!clk0_tmp),
.Q(ena0));
assign clk1_tmp = i_clk1_counter == "l0" ? l0_clk : i_clk1_counter == "l1" ? l1_clk : i_clk1_counter == "g0" ? g0_clk : i_clk1_counter == "g1" ? g1_clk : i_clk1_counter == "g2" ? g2_clk : i_clk1_counter == "g3" ? g3_clk : 1'b0;
assign clk1 = (areset_ipd === 1'b1 || ena_ipd === 1'b0) || (pll_about_to_lock == 1'b1 && !quiet_period_violation && !reconfig_err && !scanclr_violation && !scanclr_clk_violation) ? clk1_tmp : 1'bx;
cyclone_dffe ena1_reg ( .D(clkena1_ipd),
.CLRN(1'b1),
.PRN(1'b1),
.ENA(1'b1),
.CLK(!clk1_tmp),
.Q(ena1));
assign clk2_tmp = i_clk2_counter == "l0" ? l0_clk : i_clk2_counter == "l1" ? l1_clk : i_clk2_counter == "g0" ? g0_clk : i_clk2_counter == "g1" ? g1_clk : i_clk2_counter == "g2" ? g2_clk : i_clk2_counter == "g3" ? g3_clk : 1'b0;
assign clk2 = (areset_ipd === 1'b1 || ena_ipd === 1'b0) || (pll_about_to_lock == 1'b1 && !quiet_period_violation && !reconfig_err && !scanclr_violation && !scanclr_clk_violation) ? clk2_tmp : 1'bx;
cyclone_dffe ena2_reg ( .D(clkena2_ipd),
.CLRN(1'b1),
.PRN(1'b1),
.ENA(1'b1),
.CLK(!clk2_tmp),
.Q(ena2));
assign clk3_tmp = i_clk3_counter == "l0" ? l0_clk : i_clk3_counter == "l1" ? l1_clk : i_clk3_counter == "g0" ? g0_clk : i_clk3_counter == "g1" ? g1_clk : i_clk3_counter == "g2" ? g2_clk : i_clk3_counter == "g3" ? g3_clk : 1'b0;
assign clk3 = (areset_ipd === 1'b1 || ena_ipd === 1'b0) || (pll_about_to_lock == 1'b1 && !quiet_period_violation && !reconfig_err && !scanclr_violation && !scanclr_clk_violation) ? clk3_tmp : 1'bx;
cyclone_dffe ena3_reg ( .D(clkena3_ipd),
.CLRN(1'b1),
.PRN(1'b1),
.ENA(1'b1),
.CLK(!clk3_tmp),
.Q(ena3));
assign clk4_tmp = i_clk4_counter == "l0" ? l0_clk : i_clk4_counter == "l1" ? l1_clk : i_clk4_counter == "g0" ? g0_clk : i_clk4_counter == "g1" ? g1_clk : i_clk4_counter == "g2" ? g2_clk : i_clk4_counter == "g3" ? g3_clk : 1'b0;
assign clk4 = (areset_ipd === 1'b1 || ena_ipd === 1'b0) || (pll_about_to_lock == 1'b1 && !quiet_period_violation && !reconfig_err && !scanclr_violation && !scanclr_clk_violation) ? clk4_tmp : 1'bx;
cyclone_dffe ena4_reg ( .D(clkena4_ipd),
.CLRN(1'b1),
.PRN(1'b1),
.ENA(1'b1),
.CLK(!clk4_tmp),
.Q(ena4));
assign clk5_tmp = i_clk5_counter == "l0" ? l0_clk : i_clk5_counter == "l1" ? l1_clk : i_clk5_counter == "g0" ? g0_clk : i_clk5_counter == "g1" ? g1_clk : i_clk5_counter == "g2" ? g2_clk : i_clk5_counter == "g3" ? g3_clk : 1'b0;
assign clk5 = (areset_ipd === 1'b1 || ena_ipd === 1'b0) || (pll_about_to_lock == 1'b1 && !quiet_period_violation && !reconfig_err && !scanclr_violation && !scanclr_clk_violation) ? clk5_tmp : 1'bx;
cyclone_dffe ena5_reg ( .D(clkena5_ipd),
.CLRN(1'b1),
.PRN(1'b1),
.ENA(1'b1),
.CLK(!clk5_tmp),
.Q(ena5));
assign extclk0_tmp = i_extclk0_counter == "e0" ? e0_clk : i_extclk0_counter == "e1" ? e1_clk : i_extclk0_counter == "e2" ? e2_clk : i_extclk0_counter == "e3" ? e3_clk : i_extclk0_counter == "g0" ? g0_clk : 1'b0;
assign extclk0 = (areset_ipd === 1'b1 || ena_ipd === 1'b0) || (pll_about_to_lock == 1'b1 && !quiet_period_violation && !reconfig_err && !scanclr_violation && !scanclr_clk_violation) ? extclk0_tmp : 1'bx;
cyclone_dffe extena0_reg ( .D(extclkena0_ipd),
.CLRN(1'b1),
.PRN(1'b1),
.ENA(1'b1),
.CLK(!extclk0_tmp),
.Q(extena0));
assign extclk1_tmp = i_extclk1_counter == "e0" ? e0_clk : i_extclk1_counter == "e1" ? e1_clk : i_extclk1_counter == "e2" ? e2_clk : i_extclk1_counter == "e3" ? e3_clk : i_extclk1_counter == "g0" ? g0_clk : 1'b0;
assign extclk1 = (areset_ipd === 1'b1 || ena_ipd === 1'b0) || (pll_about_to_lock == 1'b1 && !quiet_period_violation && !reconfig_err && !scanclr_violation && !scanclr_clk_violation) ? extclk1_tmp : 1'bx;
cyclone_dffe extena1_reg ( .D(extclkena1_ipd),
.CLRN(1'b1),
.PRN(1'b1),
.ENA(1'b1),
.CLK(!extclk1_tmp),
.Q(extena1));
assign extclk2_tmp = i_extclk2_counter == "e0" ? e0_clk : i_extclk2_counter == "e1" ? e1_clk : i_extclk2_counter == "e2" ? e2_clk : i_extclk2_counter == "e3" ? e3_clk : i_extclk2_counter == "g0" ? g0_clk : 1'b0;
assign extclk2 = (areset_ipd === 1'b1 || ena_ipd === 1'b0) || (pll_about_to_lock == 1'b1 && !quiet_period_violation && !reconfig_err && !scanclr_violation && !scanclr_clk_violation) ? extclk2_tmp : 1'bx;
cyclone_dffe extena2_reg ( .D(extclkena2_ipd),
.CLRN(1'b1),
.PRN(1'b1),
.ENA(1'b1),
.CLK(!extclk2_tmp),
.Q(extena2));
assign extclk3_tmp = i_extclk3_counter == "e0" ? e0_clk : i_extclk3_counter == "e1" ? e1_clk : i_extclk3_counter == "e2" ? e2_clk : i_extclk3_counter == "e3" ? e3_clk : i_extclk3_counter == "g0" ? g0_clk : 1'b0;
assign extclk3 = (areset_ipd === 1'b1 || ena_ipd === 1'b0) || (pll_about_to_lock == 1'b1 && !quiet_period_violation && !reconfig_err && !scanclr_violation && !scanclr_clk_violation) ? extclk3_tmp : 1'bx;
cyclone_dffe extena3_reg ( .D(extclkena3_ipd),
.CLRN(1'b1),
.PRN(1'b1),
.ENA(1'b1),
.CLK(!extclk3_tmp),
.Q(extena3));
assign enable_0 = (areset_ipd === 1'b1 || ena_ipd === 1'b0) || pll_about_to_lock == 1'b1 ? enable0_tmp : 1'bx;
assign enable_1 = (areset_ipd === 1'b1 || ena_ipd === 1'b0) || pll_about_to_lock == 1'b1 ? enable1_tmp : 1'bx;
// ACCELERATE OUTPUTS
and (clk[0], ena0, clk0);
and (clk[1], ena1, clk1);
and (clk[2], ena2, clk2);
and (clk[3], ena3, clk3);
and (clk[4], ena4, clk4);
and (clk[5], ena5, clk5);
and (extclk[0], extena0, extclk0);
and (extclk[1], extena1, extclk1);
and (extclk[2], extena2, extclk2);
and (extclk[3], extena3, extclk3);
and (enable0, 1'b1, enable_0);
and (enable1, 1'b1, enable_1);
and (scandataout, 1'b1, scandataout_tmp);
endmodule // cyclone_pll
//////////////////////////////////////////////////////////////////////////////
//
// Module Name : cyclone_dll
//
// Description : Simulation model for the Cyclone DLL.
//
// Outputs : Delayctrlout output (active high) indicates when the
// DLL locks to the incoming clock
//
//////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module cyclone_dll (clk,
delayctrlout
);
// GLOBAL PARAMETERS
parameter input_frequency = "10000 ps";
parameter phase_shift = "0";
parameter sim_valid_lock = 1;
parameter sim_invalid_lock = 5;
parameter lpm_type = "cyclone_dll";
// INPUT PORTS
input clk;
// OUTPUT PORTS
output delayctrlout;
// INTERNAL NETS AND VARIABLES
reg clk_ipd_last_value;
reg got_first_rising_edge;
reg got_first_falling_edge;
reg dll_is_locked;
reg start_clk_detect;
reg start_clk_detect_last_value;
reg violation;
reg duty_cycle_warn;
reg input_freq_warn;
time clk_ipd_last_rising_edge;
time clk_ipd_last_falling_edge;
integer clk_per_tolerance;
integer duty_cycle;
integer clk_detect_count;
integer half_cycles_to_lock;
integer half_cycles_to_keep_lock;
integer input_period;
// BUFFER INPUTS
wire clk_ipd;
buf (clk_ipd, clk);
// FUNCTIONS
// convert string to integer with sign
function integer str2int;
input [8*16:1] s;
reg [8*16:1] reg_s;
reg [8:1] digit;
reg [8:1] tmp;
integer m, magnitude;
integer sign;
begin
sign = 1;
magnitude = 0;
reg_s = s;
for (m=1; m<=16; m=m+1)
begin
tmp = reg_s[128:121];
digit = tmp & 8'b00001111;
reg_s = reg_s << 8;
// Accumulate ascii digits 0-9 only.
if ((tmp>=48) && (tmp<=57))
magnitude = (magnitude * 10) + digit;
if (tmp == 45)
sign = -1; // Found a '-' character, i.e. number is negative.
end
str2int = sign*magnitude;
end
endfunction
initial
begin
clk_ipd_last_value = 0;
got_first_rising_edge = 0;
got_first_falling_edge = 0;
clk_ipd_last_rising_edge = 0;
clk_ipd_last_falling_edge = 0;
input_period = str2int(input_frequency);
duty_cycle = input_period/2;
clk_per_tolerance = input_period * 0.1;
// if sim_valid_lock == 0, DLL starts out locked.
if (sim_valid_lock == 0)
dll_is_locked = 1;
else
dll_is_locked = 0;
clk_detect_count = 0;
start_clk_detect = 0;
start_clk_detect_last_value = 0;
half_cycles_to_lock = 0;
half_cycles_to_keep_lock = 0;
violation = 0;
duty_cycle_warn = 1;
input_freq_warn = 1;
end
always @(clk_ipd)
begin
if (clk_ipd == 1'b1 && clk_ipd != clk_ipd_last_value)
begin
// rising edge
if (got_first_rising_edge == 1'b0)
begin
got_first_rising_edge = 1;
half_cycles_to_lock = half_cycles_to_lock + 1;
if (sim_valid_lock > 0 && half_cycles_to_lock >= sim_valid_lock && violation == 1'b0)
begin
dll_is_locked <= 1;
$display(" Note : DLL locked to incoming clock.");
$display("Time: %0t Instance: %m", $time);
end
// start the internal clock that will monitor
// the input clock
start_clk_detect <= 1;
end
else
begin
// reset clock event counter
clk_detect_count = 0;
// check for clk_period violation
if ( (($time - clk_ipd_last_rising_edge) < (input_period - clk_per_tolerance)) || (($time - clk_ipd_last_rising_edge) > (input_period + clk_per_tolerance)) )
begin
violation = 1;
if (input_freq_warn === 1'b1)
begin
$display(" Warning : Input frequency violation");
$display("Time: %0t Instance: %m", $time);
input_freq_warn = 0;
end
end
else if ( (($time - clk_ipd_last_falling_edge) < (duty_cycle - clk_per_tolerance/2)) || (($time - clk_ipd_last_falling_edge) > (duty_cycle + clk_per_tolerance/2)) )
begin
// duty cycle violation
violation = 1;
if (duty_cycle_warn === 1'b1)
begin
$display(" Warning : Duty Cycle violation");
$display("Time: %0t Instance: %m", $time);
duty_cycle_warn = 0;
end
end
else
violation = 0;
if (violation)
begin
if (dll_is_locked)
begin
half_cycles_to_keep_lock = half_cycles_to_keep_lock + 1;
if (half_cycles_to_keep_lock > sim_invalid_lock)
begin
dll_is_locked <= 0;
$display(" Warning : DLL lost lock due to input frequency/Duty cycle violation.");
$display("Time: %0t Instance: %m", $time);
// reset lock and unlock counters
half_cycles_to_lock = 0;
half_cycles_to_keep_lock = 0;
got_first_rising_edge = 0;
got_first_falling_edge = 0;
end
end
else
half_cycles_to_lock = 0;
end
else begin
if (dll_is_locked == 1'b0)
begin
// increment lock counter
half_cycles_to_lock = half_cycles_to_lock + 1;
if (half_cycles_to_lock > sim_valid_lock)
begin
dll_is_locked <= 1;
$display(" Note : DLL locked to incoming clock.");
$display("Time: %0t Instance: %m", $time);
end
end
else
half_cycles_to_keep_lock = 0;
end
end
clk_ipd_last_rising_edge = $time;
end
else if (clk_ipd == 1'b0 && clk_ipd != clk_ipd_last_value)
begin
// falling edge
// reset clock event counter
clk_detect_count = 0;
got_first_falling_edge = 1;
if (got_first_rising_edge == 1'b1)
begin
// check for duty cycle violation
if ( (($time - clk_ipd_last_rising_edge) < (duty_cycle - clk_per_tolerance/2)) || (($time - clk_ipd_last_rising_edge) > (duty_cycle + clk_per_tolerance/2)) )
begin
violation = 1;
if (duty_cycle_warn === 1'b1)
begin
$display(" Warning : Duty Cycle violation");
$display("Time: %0t Instance: %m", $time);
duty_cycle_warn = 0;
end
end
else
violation = 0;
if (dll_is_locked)
begin
if (violation)
begin
half_cycles_to_keep_lock = half_cycles_to_keep_lock + 1;
if (half_cycles_to_keep_lock > sim_invalid_lock)
begin
dll_is_locked <= 0;
$display(" Warning : DLL lost lock due to input frequency/Duty cycle violation.");
$display("Time: %0t Instance: %m", $time);
// reset lock and unlock counters
half_cycles_to_lock = 0;
half_cycles_to_keep_lock = 0;
got_first_rising_edge = 0;
got_first_falling_edge = 0;
end
end
else
half_cycles_to_keep_lock = 0;
end
else
begin
if (violation)
begin
// reset_lock_counter
half_cycles_to_lock = 0;
end
else
begin
// increment lock counter
half_cycles_to_lock = half_cycles_to_lock + 1;
end
end
end
else
begin
// first clk edge is falling edge, do nothing
end
clk_ipd_last_falling_edge = $time;
end
else
begin
// illegal value
if (dll_is_locked && (got_first_rising_edge == 1'b1 || got_first_falling_edge == 1'b1))
begin
dll_is_locked <= 0;
// reset lock and unlock counters
half_cycles_to_lock = 0;
half_cycles_to_keep_lock = 0;
got_first_rising_edge = 0;
got_first_falling_edge = 0;
$display(" Error : Illegal value detected on input clock. DLL will lose lock.");
$display("Time: %0t Instance: %m", $time);
end
else if (got_first_rising_edge == 1'b1 || got_first_falling_edge == 1'b1)
begin
// clock started up, then went to 'X'
// this is to weed out the 'X' at start of simulation
$display(" Error : Illegal value detected on input clock.");
$display("Time: %0t Instance: %m", $time);
// reset lock counter
half_cycles_to_lock = 0;
end
end
clk_ipd_last_value = clk_ipd;
end
// ********************************************************************
// The following block generates the internal clock that is used to
// track loss of input clock. A counter counts events on this internal
// clock, and is reset to 0 on event on input clock. If input clock
// flatlines, the counter will exceed the limit and DLL will lose lock.
// Events on internal clock are scheduled at the max. allowable input
// clock tolerance, to allow 'sim_invalid_lock' parameter value = 1.
// ********************************************************************
always @(start_clk_detect)
begin
if (start_clk_detect != start_clk_detect_last_value)
begin
// increment clock event counter
clk_detect_count = clk_detect_count + 1;
if (dll_is_locked)
begin
if (clk_detect_count > sim_invalid_lock)
begin
dll_is_locked = 0;
$display(" Warning : DLL lost lock due to loss of input clock.");
$display("Time: %0t Instance: %m", $time);
// reset lock and unlock counters
half_cycles_to_lock = 0;
half_cycles_to_keep_lock = 0;
got_first_rising_edge = 0;
got_first_falling_edge = 0;
clk_detect_count = 0;
start_clk_detect <= #(input_period/2) 1'b0;
end
else
start_clk_detect <= #(input_period/2 + clk_per_tolerance/2) ~start_clk_detect;
end
else if (clk_detect_count > 10)
begin
$display(" Warning : No input clock. DLL will not lock.");
$display("Time: %0t Instance: %m", $time);
clk_detect_count = 0;
end
else
start_clk_detect <= #(input_period/2 + clk_per_tolerance/2) ~start_clk_detect;
end
// save this event value
start_clk_detect_last_value = start_clk_detect;
end
// ACCELERATE OUTPUTS
and (delayctrlout, 1'b1, dll_is_locked);
endmodule
//--------------------------------------------------------------------
//
// Module Name : cyclone_jtag
//
// Description : Cyclone JTAG Verilog Simulation model
//
//--------------------------------------------------------------------
`timescale 1 ps/1 ps
module cyclone_jtag (
tms,
tck,
tdi,
ntrst,
tdoutap,
tdouser,
tdo,
tmsutap,
tckutap,
tdiutap,
shiftuser,
clkdruser,
updateuser,
runidleuser,
usr1user);
input tms;
input tck;
input tdi;
input ntrst;
input tdoutap;
input tdouser;
output tdo;
output tmsutap;
output tckutap;
output tdiutap;
output shiftuser;
output clkdruser;
output updateuser;
output runidleuser;
output usr1user;
parameter lpm_type = "cyclone_jtag";
endmodule
//--------------------------------------------------------------------
//
// Module Name : cyclone_crcblock
//
// Description : Cyclone CRCBLOCK Verilog Simulation model
//
//--------------------------------------------------------------------
`timescale 1 ps/1 ps
module cyclone_crcblock (
clk,
shiftnld,
ldsrc,
crcerror,
regout);
input clk;
input shiftnld;
input ldsrc;
output crcerror;
output regout;
assign crcerror = 1'b0;
assign regout = 1'b0;
parameter oscillator_divider = 1;
parameter lpm_type = "cyclone_crcblock";
endmodule
//------------------------------------------------------------------
//
// Module Name : cyclone_routing_wire
//
// Description : Simulation model for a simple routing wire
//
//------------------------------------------------------------------
`timescale 1ps / 1ps
module cyclone_routing_wire (
datain,
dataout
);
// INPUT PORTS
input datain;
// OUTPUT PORTS
output dataout;
// INTERNAL VARIABLES
wire dataout_tmp;
specify
(datain => dataout) = (0, 0) ;
endspecify
assign dataout_tmp = datain;
and (dataout, dataout_tmp, 1'b1);
endmodule // cyclone_routing_wire
///////////////////////////////////////////////////////////////////////
//
// Module Name : cyclone_asynch_io
//
// Description : Verilog simulation model for asynchronous submodule
// in Cyclone IO.
//
///////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module cyclone_asynch_io
(
datain,
oe,
regin,
padio,
combout,
regout
);
// INPUT/OUTPUT PORTS
inout padio;
// INPUT PORTS
input datain;
input oe;
input regin;
// OUTPUT PORTS
output combout;
output regout;
parameter operation_mode = "input";
parameter bus_hold = "false";
parameter open_drain_output = "false";
// INTERNAL VARIABLES
reg prev_value;
reg tmp_padio;
reg tmp_combout;
reg buf_control;
// INPUT BUFFERS
wire datain_in;
wire oe_in;
buf(datain_in, datain);
buf(oe_in, oe);
tri padio_tmp;
specify
(padio => combout) = (0,0);
(datain => padio) = (0, 0);
(posedge oe => (padio +: padio_tmp)) = (0, 0);
(negedge oe => (padio +: 1'bz)) = (0, 0);
(regin => regout) = (0, 0);
endspecify
initial
begin
prev_value = 'b0;
tmp_padio = 'bz;
end
always @(datain_in or oe_in or padio)
begin
if (bus_hold == "true" )
begin
buf_control = 'b1;
if ( operation_mode == "input")
begin
if (padio == 1'bz)
tmp_combout = prev_value;
else
begin
prev_value = padio;
tmp_combout = padio;
end
tmp_padio = 1'bz;
end
else
begin
if ( operation_mode == "output" || operation_mode == "bidir")
begin
if ( oe_in == 1)
begin
if ( open_drain_output == "true" )
begin
if (datain_in == 0)
begin
tmp_padio = 1'b0;
prev_value = 1'b0;
end
else if (datain_in == 1'bx)
begin
tmp_padio = 1'bx;
prev_value = 1'bx;
end
else // output of tri is 'Z'
begin
if ( operation_mode == "bidir")
prev_value = padio;
tmp_padio = 1'bz;
end
end
else // open drain_output = false;
begin
tmp_padio = datain_in;
prev_value = datain_in;
end
end
else if ( oe_in == 0 )
begin
if (operation_mode == "bidir")
prev_value = padio;
tmp_padio = 1'bz;
end
else // oe == 'X'
begin
tmp_padio = 1'bx;
prev_value = 1'bx;
end
end
if ( operation_mode == "output")
tmp_combout = 1'bz;
else
tmp_combout = padio;
end
end
else // bus hold is false
begin
buf_control = 'b0;
if ( operation_mode == "input")
begin
tmp_combout = padio;
end
else if (operation_mode == "output" || operation_mode == "bidir")
begin
if ( operation_mode == "bidir")
tmp_combout = padio;
if ( oe_in == 1 )
begin
if ( open_drain_output == "true" )
begin
if (datain_in == 0)
tmp_padio = 1'b0;
else if ( datain_in == 1'bx)
tmp_padio = 1'bx;
else
tmp_padio = 1'bz;
end
else
tmp_padio = datain_in;
end
else if ( oe_in == 0 )
tmp_padio = 1'bz;
else
tmp_padio = 1'bx;
end
else
begin
$display ("Error: Invalid operation_mode specified in cyclone io atom!\n");
$display ("Time: %0t Instance: %m", $time);
end
end
end
bufif1 (weak1, weak0) b(padio_tmp, prev_value, buf_control); //weak value
pmos (padio_tmp, tmp_padio, 'b0);
pmos (combout, tmp_combout, 'b0);
pmos (padio, padio_tmp, 'b0);
and (regout, regin, 1'b1);
endmodule
///////////////////////////////////////////////////////////////////////
//
// Module Name : cyclone_io
//
// Description : Verilog simulation model for Cyclone IO.
//
///////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module cyclone_io
(
datain,
oe,
outclk,
outclkena,
inclk,
inclkena,
areset,
sreset,
devclrn,
devpor,
devoe,
padio,
combout,
regout
);
parameter operation_mode = "input";
parameter open_drain_output = "false";
parameter bus_hold = "false";
parameter output_register_mode = "none";
parameter output_async_reset = "none";
parameter output_sync_reset = "none";
parameter output_power_up = "low";
parameter tie_off_output_clock_enable = "false";
parameter oe_register_mode = "none";
parameter oe_async_reset = "none";
parameter oe_sync_reset = "none";
parameter oe_power_up = "low";
parameter tie_off_oe_clock_enable = "false";
parameter input_register_mode = "none";
parameter input_async_reset = "none";
parameter input_sync_reset = "none";
parameter input_power_up = "low";
parameter lpm_type = "cyclone_io";
// INPUT/OUTPUT PORTS
inout padio;
// INPUT PORTS
input datain;
input oe;
input outclk;
input outclkena;
input inclk;
input inclkena;
input areset;
input sreset;
input devclrn;
input devpor;
input devoe;
// OUTPUT PORTS
output combout;
output regout;
tri1 devclrn;
tri1 devpor;
tri1 devoe;
// INTERNAL VARIABLES
wire out_reg_clk_ena;
wire oe_reg_clk_ena;
wire tmp_oe_reg_out;
wire tmp_input_reg_out;
wire tmp_output_reg_out;
wire inreg_sreset_is_used;
wire outreg_sreset_is_used;
wire oereg_sreset_is_used;
wire inreg_sreset;
wire outreg_sreset;
wire oereg_sreset;
wire in_reg_aclr;
wire in_reg_apreset;
wire oe_reg_aclr;
wire oe_reg_apreset;
wire oe_reg_sel;
wire out_reg_aclr;
wire out_reg_apreset;
wire out_reg_sel;
wire input_reg_pu_low;
wire output_reg_pu_low;
wire oe_reg_pu_low;
wire inreg_D;
wire outreg_D;
wire oereg_D;
wire tmp_datain;
wire tmp_oe;
wire iareset;
wire isreset;
assign input_reg_pu_low = ( input_power_up == "low") ? 'b0 : 'b1;
assign output_reg_pu_low = ( output_power_up == "low") ? 'b0 : 'b1;
assign oe_reg_pu_low = ( oe_power_up == "low") ? 'b0 : 'b1;
assign out_reg_sel = (output_register_mode == "register" ) ? 'b1 : 'b0;
assign oe_reg_sel = ( oe_register_mode == "register" ) ? 'b1 : 'b0;
assign iareset = ( areset === 'b0 || areset === 'b1 ) ? !areset : 'b1;
assign isreset = ( sreset === 'b0 || sreset === 'b1 ) ? sreset : 'b0;
// output register signals
assign out_reg_aclr = (output_async_reset == "clear") ? iareset : 'b1;
assign out_reg_apreset = ( output_async_reset == "preset") ? iareset : 'b1;
assign outreg_sreset_is_used = ( output_sync_reset == "none") ? 'b0 : 'b1;
assign outreg_sreset = (output_sync_reset == "clear") ? 'b0 : 'b1;
// oe register signals
assign oe_reg_aclr = ( oe_async_reset == "clear") ? iareset : 'b1;
assign oe_reg_apreset = ( oe_async_reset == "preset") ? iareset : 'b1;
assign oereg_sreset_is_used = ( oe_sync_reset == "none") ? 'b0 : 'b1;
assign oereg_sreset = (oe_sync_reset == "clear") ? 'b0 : 'b1;
// input register signals
assign in_reg_aclr = ( input_async_reset == "clear") ? iareset : 'b1;
assign in_reg_apreset = ( input_async_reset == "preset") ? iareset : 'b1;
assign inreg_sreset_is_used = ( input_sync_reset == "none") ? 'b0 : 'b1;
assign inreg_sreset = (input_sync_reset == "clear") ? 'b0 : 'b1;
// oe and output register clock enable signals
assign out_reg_clk_ena = ( tie_off_output_clock_enable == "true") ? 'b1 : outclkena;
assign oe_reg_clk_ena = ( tie_off_oe_clock_enable == "true") ? 'b1 : outclkena;
// input reg
cyclone_mux21 inreg_D_mux (
.MO (inreg_D),
.A (padio),
.B (inreg_sreset),
.S (isreset && inreg_sreset_is_used)
);
cyclone_dffe input_reg (
.Q (tmp_input_reg_out),
.CLK (inclk),
.ENA (inclkena),
.D (inreg_D),
.CLRN (in_reg_aclr && devclrn && (input_reg_pu_low || devpor)),
.PRN (in_reg_apreset && (!input_reg_pu_low || devpor))
);
//output reg
cyclone_mux21 outreg_D_mux (
.MO (outreg_D),
.A (datain),
.B (outreg_sreset),
.S (isreset && outreg_sreset_is_used)
);
cyclone_dffe output_reg (
.Q (tmp_output_reg_out),
.CLK (outclk),
.ENA (out_reg_clk_ena),
.D (outreg_D),
.CLRN (out_reg_aclr && devclrn && (output_reg_pu_low || devpor)),
.PRN (out_reg_apreset && (!output_reg_pu_low || devpor))
);
//oe reg
cyclone_mux21 oereg_D_mux (
.MO (oereg_D),
.A (oe),
.B (oereg_sreset),
.S (isreset && oereg_sreset_is_used)
);
cyclone_dffe oe_reg (
.Q (tmp_oe_reg_out),
.CLK (outclk),
.ENA (oe_reg_clk_ena),
.D (oereg_D),
.CLRN (oe_reg_aclr && devclrn && (oe_reg_pu_low || devpor)),
.PRN (oe_reg_apreset && (!oe_reg_pu_low || devpor))
);
// asynchronous block
assign tmp_oe = (oe_reg_sel == 'b1) ? tmp_oe_reg_out : oe;
assign tmp_datain = ((operation_mode == "output" ||
operation_mode == "bidir") &&
out_reg_sel == 'b1 ) ? tmp_output_reg_out : datain;
cyclone_asynch_io asynch_inst(
.datain(tmp_datain),
.oe(tmp_oe),
.regin(tmp_input_reg_out),
.padio(padio),
.combout(combout),
.regout(regout)
);
defparam asynch_inst.operation_mode = operation_mode;
defparam asynch_inst.bus_hold = bus_hold;
defparam asynch_inst.open_drain_output = open_drain_output;
endmodule
//---------------------------------------------------------------------
//
// Module Name : cyclone_asmiblock
//
// Description : Cyclone ASMIBLOCK Verilog Simulation model
//
//---------------------------------------------------------------------
`timescale 1 ps/1 ps
module cyclone_asmiblock
(
dclkin,
scein,
sdoin,
data0out,
oe
);
input dclkin;
input scein;
input sdoin;
input oe;
output data0out;
parameter lpm_type = "cyclone_asmiblock";
endmodule // cyclone_asmiblock
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon Jun 05 00:58:43 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/ZyboIP/examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_vga_buffer_1_1/system_vga_buffer_1_1_stub.v
// Design : system_vga_buffer_1_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "vga_buffer,Vivado 2016.4" *)
module system_vga_buffer_1_1(clk_w, clk_r, wen, x_addr_w, y_addr_w, x_addr_r,
y_addr_r, data_w, data_r)
/* synthesis syn_black_box black_box_pad_pin="clk_w,clk_r,wen,x_addr_w[9:0],y_addr_w[9:0],x_addr_r[9:0],y_addr_r[9:0],data_w[23:0],data_r[23:0]" */;
input clk_w;
input clk_r;
input wen;
input [9:0]x_addr_w;
input [9:0]y_addr_w;
input [9:0]x_addr_r;
input [9:0]y_addr_r;
input [23:0]data_w;
output [23:0]data_r;
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//mac_queue.v
// Derived from NetFPGA Project.
///////////////////////////////////////////////////////////////////////////////
module dma_queue
#(
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH=DATA_WIDTH/8,
parameter ENABLE_HEADER = 0,
parameter STAGE_NUMBER = 'hff,
parameter PORT_NUMBER = 0
)(// --- register interface
/*input mac_grp_reg_req,
input mac_grp_reg_rd_wr_L,
input [31:0] mac_grp_reg_addr,
input [31:0] mac_grp_reg_wr_data,
output [31:0] mac_grp_reg_rd_data,
output mac_grp_reg_ack,*/
// --- output to data path interface
output [DATA_WIDTH-1:0] out_data,
output [CTRL_WIDTH-1:0] out_ctrl,
output out_wr,
input out_rdy,
// --- input from data path interface
input [DATA_WIDTH-1:0] in_data,
input [CTRL_WIDTH-1:0] in_ctrl,
input in_wr,
output in_rdy,
// --- input from mac interface
input [31:0] s_rx_axis_tdata,
input s_rx_axis_tvalid,
input s_rx_axis_tlast,
output s_rx_axis_tready,
input [3:0] s_rx_axis_tkeep,
// --- output to mac interface
output m_tx_axis_tvalid,
output [31:0] m_tx_axis_tdata,
output m_tx_axis_tlast,
output [3:0] m_tx_axis_tkeep,
input m_tx_axis_tready,
//--- misc
output [11:0] tx_pkt_byte_cnt,
output tx_pkt_byte_cnt_vld,
input axis_aclk,
input clk,
input reset
);
//wire [11:0] tx_pkt_byte_cnt;
wire [9:0] tx_pkt_word_cnt;
wire [11:0] rx_pkt_byte_cnt;
wire [9:0] rx_pkt_word_cnt;
rx_queue
#(
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.ENABLE_HEADER(ENABLE_HEADER),
.STAGE_NUMBER(STAGE_NUMBER),
.PORT_NUMBER(PORT_NUMBER)
) rx_queue
( // user data path interface
.out_ctrl (out_ctrl),
.out_wr (out_wr),
.out_data (out_data),
.out_rdy (out_rdy),
// gmac interface
.s_rx_axis_aclk (axis_aclk),
.s_rx_axis_tdata (s_rx_axis_tdata),
.s_rx_axis_tvalid (s_rx_axis_tvalid),
.s_rx_axis_tlast (s_rx_axis_tlast),
.s_rx_axis_tkeep (s_rx_axis_tkeep),
.s_rx_axis_tready (s_rx_axis_tready),
// reg signals
.rx_pkt_good (rx_pkt_good),
.rx_pkt_bad (rx_pkt_bad),
.rx_pkt_dropped (rx_pkt_dropped),
.rx_pkt_byte_cnt (rx_pkt_byte_cnt),
.rx_pkt_word_cnt (rx_pkt_word_cnt),
.rx_pkt_pulled (rx_pkt_pulled),
//.rx_queue_en (rx_queue_en),
// misc
.reset (reset),
.clk (clk)
);
dma_tx_queue
#(
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.ENABLE_HEADER(ENABLE_HEADER),
.STAGE_NUMBER(STAGE_NUMBER)
) tx_queue
(// data path interface
.in_ctrl (in_ctrl),
.in_wr (in_wr),
.in_data (in_data),
.in_rdy (in_rdy),
// gmac interface
.m_tx_axis_aclk (axis_aclk),
.m_tx_axis_tdata (m_tx_axis_tdata),
.m_tx_axis_tvalid (m_tx_axis_tvalid),
.m_tx_axis_tlast (m_tx_axis_tlast),
.m_tx_axis_tkeep (m_tx_axis_tkeep),
.m_tx_axis_tready (m_tx_axis_tready),
// reg signals
//.tx_queue_en (tx_queue_en),
//.tx_pkt_sent (tx_pkt_sent),
.tx_pkt_stored (tx_pkt_stored),
.tx_pkt_byte_cnt (tx_pkt_byte_cnt),
.tx_pkt_byte_cnt_vld (tx_pkt_byte_cnt_vld),
.tx_pkt_word_cnt (tx_pkt_word_cnt),
// misc
.reset (reset),
.clk (clk)
);
/*
eth_queue_regs
#(
.CTRL_WIDTH(CTRL_WIDTH)
) eth_queue_regs
(
.mac_grp_reg_req (mac_grp_reg_req),
.mac_grp_reg_rd_wr_L (mac_grp_reg_rd_wr_L),
.mac_grp_reg_addr (mac_grp_reg_addr),
.mac_grp_reg_wr_data (mac_grp_reg_wr_data),
.mac_grp_reg_rd_data (mac_grp_reg_rd_data),
.mac_grp_reg_ack (mac_grp_reg_ack),
// interface to rx queue
.rx_pkt_good (rx_pkt_good),
.rx_pkt_bad (rx_pkt_bad),
.rx_pkt_dropped (rx_pkt_dropped),
.rx_pkt_byte_cnt (rx_pkt_byte_cnt),
.rx_pkt_word_cnt (rx_pkt_word_cnt),
.rx_pkt_pulled (rx_pkt_pulled),
.rx_queue_en (rx_queue_en),
// interface to tx queue
.tx_queue_en (tx_queue_en),
.tx_pkt_sent (tx_pkt_sent),
.tx_pkt_stored (tx_pkt_stored),
.tx_pkt_byte_cnt (tx_pkt_byte_cnt),
.tx_pkt_word_cnt (tx_pkt_word_cnt),
.clk (clk),
.reset (reset)
);*/
endmodule // nf2_mac_grp
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: K.39
// \ \ Application: netgen
// / / Filename: lpm_mult.v
// /___/ /\ Timestamp: Thu Dec 10 15:26:42 2009
// \ \ / \
// \___\/\___\
//
// Command : -intstyle ise -w -sim -ofmt verilog /root/NF2/projects/ngnp/synth/coregen/tmp/_cg/lpm_mult.ngc /root/NF2/projects/ngnp/synth/coregen/tmp/_cg/lpm_mult.v
// Device : 2vp50ff1152-7
// Input file : /root/NF2/projects/ngnp/synth/coregen/tmp/_cg/lpm_mult.ngc
// Output file : /root/NF2/projects/ngnp/synth/coregen/tmp/_cg/lpm_mult.v
// # of Modules : 1
// Design Name : lpm_mult
// Xilinx : /opt/Xilinx/10.1/ISE
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Development System Reference Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module lpm_mult (
sclr, ce, clk, a, b, p
);
input sclr;
input ce;
input clk;
input [32 : 0] a;
input [32 : 0] b;
output [65 : 0] p;
// synthesis translate_off
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[0] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[1] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[2] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[3] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[4] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[5] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[6] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[7] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[8] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[9] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[10] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[11] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[12] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[13] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[14] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[15] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[16] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[17] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[18] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[19] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[20] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[21] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[22] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[23] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[24] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[25] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[26] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[27] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[28] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[29] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[30] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[31] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[32] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[33] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[34] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[35] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[36] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[37] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[38] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[39] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[40] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[41] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[42] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[43] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[44] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[45] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[46] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[47] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[52] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[0] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[1] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[2] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[3] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[4] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[5] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[6] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[7] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[8] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[9] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[10] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[11] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[12] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[13] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[14] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[15] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[16] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[17] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[18] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[19] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[20] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[21] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[22] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[23] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[24] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[25] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[26] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[27] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[28] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[29] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[30] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[31] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[32] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[33] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[34] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[35] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[36] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[37] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[38] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[39] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[40] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[41] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[42] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[43] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[44] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[45] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[46] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[47] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[52] ;
wire NLW_VCC_P_UNCONNECTED;
wire NLW_GND_G_UNCONNECTED;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/use_mult18x18.appMULT[0].bppMULT[0].no_Mreg.m18x18_P<35>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/use_mult18x18.appMULT[0].bppMULT[1].no_Mreg.m18x18_P<35>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/use_mult18x18.appMULT[0].bppMULT[1].no_Mreg.m18x18_P<34>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/use_mult18x18.appMULT[0].bppMULT[1].no_Mreg.m18x18_P<33>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/use_mult18x18.appMULT[1].bppMULT[0].no_Mreg.m18x18_P<35>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/use_mult18x18.appMULT[1].bppMULT[0].no_Mreg.m18x18_P<34>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/use_mult18x18.appMULT[1].bppMULT[0].no_Mreg.m18x18_P<33>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/use_mult18x18.appMULT[1].bppMULT[1].no_Mreg.m18x18_P<35>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/use_mult18x18.appMULT[1].bppMULT[1].no_Mreg.m18x18_P<34>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/use_mult18x18.appMULT[1].bppMULT[1].no_Mreg.m18x18_P<33>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/use_mult18x18.appMULT[1].bppMULT[1].no_Mreg.m18x18_P<32>_UNCONNECTED ;
wire [32 : 0] a_2;
wire [32 : 0] b_3;
wire [31 : 0] \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut ;
wire [30 : 0] \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy ;
wire [32 : 0] \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut ;
wire [31 : 0] \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy ;
wire [32 : 0] \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 ;
wire [50 : 0] \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut ;
wire [49 : 0] \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy ;
wire [31 : 0] \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 ;
wire [34 : 0] \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> ;
wire [32 : 0] \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> ;
wire [32 : 0] \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> ;
wire [31 : 0] \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> ;
wire [16 : 0] \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/bp20r ;
wire [0 : 0] \BU2/zero_detect ;
assign
a_2[32] = a[32],
a_2[31] = a[31],
a_2[30] = a[30],
a_2[29] = a[29],
a_2[28] = a[28],
a_2[27] = a[27],
a_2[26] = a[26],
a_2[25] = a[25],
a_2[24] = a[24],
a_2[23] = a[23],
a_2[22] = a[22],
a_2[21] = a[21],
a_2[20] = a[20],
a_2[19] = a[19],
a_2[18] = a[18],
a_2[17] = a[17],
a_2[16] = a[16],
a_2[15] = a[15],
a_2[14] = a[14],
a_2[13] = a[13],
a_2[12] = a[12],
a_2[11] = a[11],
a_2[10] = a[10],
a_2[9] = a[9],
a_2[8] = a[8],
a_2[7] = a[7],
a_2[6] = a[6],
a_2[5] = a[5],
a_2[4] = a[4],
a_2[3] = a[3],
a_2[2] = a[2],
a_2[1] = a[1],
a_2[0] = a[0],
b_3[32] = b[32],
b_3[31] = b[31],
b_3[30] = b[30],
b_3[29] = b[29],
b_3[28] = b[28],
b_3[27] = b[27],
b_3[26] = b[26],
b_3[25] = b[25],
b_3[24] = b[24],
b_3[23] = b[23],
b_3[22] = b[22],
b_3[21] = b[21],
b_3[20] = b[20],
b_3[19] = b[19],
b_3[18] = b[18],
b_3[17] = b[17],
b_3[16] = b[16],
b_3[15] = b[15],
b_3[14] = b[14],
b_3[13] = b[13],
b_3[12] = b[12],
b_3[11] = b[11],
b_3[10] = b[10],
b_3[9] = b[9],
b_3[8] = b[8],
b_3[7] = b[7],
b_3[6] = b[6],
b_3[5] = b[5],
b_3[4] = b[4],
b_3[3] = b[3],
b_3[2] = b[2],
b_3[1] = b[1],
b_3[0] = b[0],
p[65] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[52] ,
p[64] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[47] ,
p[63] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[46] ,
p[62] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[45] ,
p[61] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[44] ,
p[60] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[43] ,
p[59] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[42] ,
p[58] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[41] ,
p[57] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[40] ,
p[56] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[39] ,
p[55] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[38] ,
p[54] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[37] ,
p[53] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[36] ,
p[52] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[35] ,
p[51] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[34] ,
p[50] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[33] ,
p[49] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[32] ,
p[48] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[31] ,
p[47] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[30] ,
p[46] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[29] ,
p[45] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[28] ,
p[44] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[27] ,
p[43] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[26] ,
p[42] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[25] ,
p[41] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[24] ,
p[40] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[23] ,
p[39] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[22] ,
p[38] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[21] ,
p[37] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[20] ,
p[36] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[19] ,
p[35] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[18] ,
p[34] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[17] ,
p[33] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[16] ,
p[32] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[15] ,
p[31] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[14] ,
p[30] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[13] ,
p[29] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[12] ,
p[28] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[11] ,
p[27] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[10] ,
p[26] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[9] ,
p[25] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[8] ,
p[24] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[7] ,
p[23] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[6] ,
p[22] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[5] ,
p[21] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[4] ,
p[20] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[3] ,
p[19] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[2] ,
p[18] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[1] ,
p[17] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[0] ,
p[16] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/bp20r [16],
p[15] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/bp20r [15],
p[14] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/bp20r [14],
p[13] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/bp20r [13],
p[12] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/bp20r [12],
p[11] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/bp20r [11],
p[10] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/bp20r [10],
p[9] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/bp20r [9],
p[8] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/bp20r [8],
p[7] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/bp20r [7],
p[6] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/bp20r [6],
p[5] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/bp20r [5],
p[4] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/bp20r [4],
p[3] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/bp20r [3],
p[2] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/bp20r [2],
p[1] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/bp20r [1],
p[0] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/bp20r [0];
VCC VCC_0 (
.P(NLW_VCC_P_UNCONNECTED)
);
GND GND_1 (
.G(NLW_GND_G_UNCONNECTED)
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/bp20r_0 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [0]),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/bp20r [0])
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/bp20r_1 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [1]),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/bp20r [1])
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/bp20r_2 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [2]),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/bp20r [2])
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/bp20r_3 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [3]),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/bp20r [3])
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/bp20r_4 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [4]),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/bp20r [4])
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/bp20r_5 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [5]),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/bp20r [5])
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/bp20r_6 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [6]),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/bp20r [6])
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/bp20r_7 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [7]),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/bp20r [7])
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/bp20r_8 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [8]),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/bp20r [8])
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/bp20r_9 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [9]),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/bp20r [9])
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/bp20r_10 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [10]),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/bp20r [10])
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/bp20r_11 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [11]),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/bp20r [11])
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/bp20r_12 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [12]),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/bp20r [12])
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/bp20r_13 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [13]),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/bp20r [13])
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/bp20r_14 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [14]),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/bp20r [14])
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/bp20r_15 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [15]),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/bp20r [15])
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/bp20r_16 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [16]),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/bp20r [16])
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r_0 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[0] ),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[0] )
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r_1 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[1] ),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[1] )
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r_2 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[2] ),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[2] )
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r_3 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[3] ),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[3] )
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r_4 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[4] ),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[4] )
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r_5 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[5] ),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[5] )
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r_6 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[6] ),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[6] )
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r_7 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[7] ),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[7] )
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r_8 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[8] ),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[8] )
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r_9 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[9] ),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[9] )
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r_10 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[10] ),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[10] )
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r_11 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[11] ),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[11] )
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r_12 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[12] ),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[12] )
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r_13 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[13] ),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[13] )
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r_14 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[14] ),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[14] )
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r_15 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[15] ),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[15] )
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r_16 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[16] ),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[16] )
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r_17 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[17] ),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[17] )
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r_18 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[18] ),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[18] )
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r_19 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[19] ),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[19] )
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r_20 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[20] ),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[20] )
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r_21 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[21] ),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[21] )
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r_22 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[22] ),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[22] )
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r_23 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[23] ),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[23] )
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r_24 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[24] ),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[24] )
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r_25 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[25] ),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[25] )
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r_26 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[26] ),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[26] )
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r_27 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[27] ),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[27] )
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r_28 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[28] ),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[28] )
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r_29 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[29] ),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[29] )
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r_30 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[30] ),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[30] )
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r_31 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[31] ),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[31] )
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r_32 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[32] ),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[32] )
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r_33 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[33] ),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[33] )
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r_34 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[34] ),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[34] )
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r_35 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[35] ),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[35] )
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r_36 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[36] ),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[36] )
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r_37 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[37] ),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[37] )
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r_38 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[38] ),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[38] )
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r_39 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[39] ),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[39] )
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r_40 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[40] ),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[40] )
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r_41 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[41] ),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[41] )
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r_42 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[42] ),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[42] )
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r_43 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[43] ),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[43] )
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r_44 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[44] ),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[44] )
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r_45 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[45] ),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[45] )
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r_46 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[46] ),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[46] )
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r_47 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[47] ),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[47] )
);
FDRE #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r_52 (
.C(clk),
.CE(ce),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[52] ),
.R(sclr),
.Q(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20r[52] )
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut<0> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [17]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [0]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [0])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy<0> (
.CI(\BU2/zero_detect [0]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [17]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [0]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [0])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_xor<0> (
.CI(\BU2/zero_detect [0]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [0]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [0])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut<1> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [18]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [1]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [1])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy<1> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [0]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [18]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [1]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [1])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_xor<1> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [0]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [1]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [1])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut<2> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [19]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [2]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [2])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy<2> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [1]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [19]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [2]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [2])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_xor<2> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [1]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [2]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [2])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut<3> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [20]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [3]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [3])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy<3> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [2]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [20]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [3]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [3])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_xor<3> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [2]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [3]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [3])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut<4> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [21]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [4]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [4])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy<4> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [3]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [21]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [4]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [4])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_xor<4> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [3]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [4]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [4])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut<5> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [22]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [5]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [5])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy<5> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [4]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [22]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [5]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [5])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_xor<5> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [4]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [5]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [5])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut<6> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [23]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [6]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [6])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy<6> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [5]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [23]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [6]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [6])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_xor<6> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [5]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [6]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [6])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut<7> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [24]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [7]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [7])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy<7> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [6]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [24]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [7]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [7])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_xor<7> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [6]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [7]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [7])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut<8> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [25]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [8]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [8])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy<8> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [7]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [25]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [8]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [8])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_xor<8> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [7]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [8]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [8])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut<9> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [26]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [9]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [9])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy<9> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [8]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [26]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [9]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [9])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_xor<9> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [8]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [9]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [9])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut<10> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [27]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [10]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [10])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy<10> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [9]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [27]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [10]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [10])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_xor<10> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [9]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [10]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [10])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut<11> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [28]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [11]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [11])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy<11> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [10]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [28]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [11]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [11])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_xor<11> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [10]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [11]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [11])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut<12> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [29]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [12]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [12])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy<12> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [11]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [29]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [12]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [12])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_xor<12> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [11]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [12]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [12])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut<13> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [30]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [13]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [13])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy<13> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [12]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [30]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [13]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [13])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_xor<13> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [12]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [13]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [13])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut<14> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [31]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [14]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [14])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy<14> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [13]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [31]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [14]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [14])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_xor<14> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [13]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [14]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [14])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut<15> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [32]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [15]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [15])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy<15> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [14]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [32]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [15]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [15])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_xor<15> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [14]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [15]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [15])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut<16> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [32]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [16]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [16])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy<16> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [15]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [32]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [16]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [16])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_xor<16> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [15]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [16]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [16])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut<17> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [32]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [17]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [17])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy<17> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [16]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [32]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [17]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [17])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_xor<17> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [16]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [17]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [17])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut<18> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [32]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [18]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [18])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy<18> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [17]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [32]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [18]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [18])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_xor<18> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [17]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [18]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [18])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut<19> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [32]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [19]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [19])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy<19> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [18]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [32]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [19]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [19])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_xor<19> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [18]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [19]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [19])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut<20> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [32]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [20]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [20])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy<20> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [19]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [32]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [20]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [20])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_xor<20> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [19]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [20]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [20])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut<21> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [32]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [21]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [21])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy<21> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [20]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [32]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [21]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [21])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_xor<21> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [20]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [21]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [21])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut<22> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [32]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [22]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [22])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy<22> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [21]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [32]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [22]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [22])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_xor<22> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [21]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [22]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [22])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut<23> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [32]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [23]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [23])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy<23> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [22]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [32]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [23]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [23])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_xor<23> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [22]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [23]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [23])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut<24> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [32]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [24]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [24])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy<24> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [23]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [32]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [24]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [24])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_xor<24> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [23]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [24]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [24])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut<25> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [32]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [25]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [25])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy<25> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [24]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [32]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [25]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [25])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_xor<25> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [24]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [25]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [25])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut<26> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [32]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [26]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [26])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy<26> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [25]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [32]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [26]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [26])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_xor<26> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [25]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [26]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [26])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut<27> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [32]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [27]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [27])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy<27> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [26]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [32]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [27]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [27])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_xor<27> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [26]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [27]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [27])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut<28> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [32]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [28]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [28])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy<28> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [27]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [32]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [28]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [28])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_xor<28> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [27]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [28]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [28])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut<29> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [32]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [29]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [29])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy<29> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [28]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [32]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [29]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [29])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_xor<29> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [28]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [29]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [29])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut<30> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [32]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [30]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [30])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy<30> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [29]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [32]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [30]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [30])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_xor<30> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [29]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [30]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [30])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut<31> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [32]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [31]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [31])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_xor<31> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_cy [30]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s11_add0000_lut [31]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [31])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut<0> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [17]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [0]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [0])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy<0> (
.CI(\BU2/zero_detect [0]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [17]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [0]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [0])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_xor<0> (
.CI(\BU2/zero_detect [0]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [0]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [0])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut<1> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [18]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [1]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [1])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy<1> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [0]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [18]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [1]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [1])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_xor<1> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [0]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [1]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [1])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut<2> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [19]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [2]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [2])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy<2> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [1]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [19]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [2]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [2])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_xor<2> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [1]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [2]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [2])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut<3> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [20]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [3]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [3])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy<3> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [2]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [20]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [3]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [3])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_xor<3> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [2]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [3]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [3])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut<4> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [21]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [4]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [4])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy<4> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [3]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [21]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [4]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [4])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_xor<4> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [3]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [4]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [4])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut<5> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [22]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [5]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [5])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy<5> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [4]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [22]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [5]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [5])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_xor<5> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [4]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [5]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [5])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut<6> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [23]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [6]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [6])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy<6> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [5]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [23]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [6]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [6])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_xor<6> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [5]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [6]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [6])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut<7> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [24]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [7]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [7])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy<7> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [6]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [24]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [7]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [7])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_xor<7> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [6]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [7]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [7])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut<8> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [25]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [8]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [8])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy<8> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [7]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [25]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [8]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [8])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_xor<8> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [7]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [8]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [8])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut<9> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [26]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [9]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [9])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy<9> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [8]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [26]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [9]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [9])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_xor<9> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [8]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [9]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [9])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut<10> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [27]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [10]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [10])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy<10> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [9]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [27]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [10]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [10])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_xor<10> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [9]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [10]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [10])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut<11> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [28]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [11]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [11])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy<11> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [10]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [28]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [11]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [11])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_xor<11> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [10]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [11]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [11])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut<12> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [29]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [12]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [12])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy<12> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [11]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [29]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [12]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [12])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_xor<12> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [11]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [12]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [12])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut<13> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [30]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [13]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [13])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy<13> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [12]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [30]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [13]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [13])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_xor<13> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [12]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [13]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [13])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut<14> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [31]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [14]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [14])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy<14> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [13]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [31]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [14]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [14])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_xor<14> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [13]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [14]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [14])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut<15> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [32]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [15]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [15])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy<15> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [14]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [32]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [15]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [15])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_xor<15> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [14]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [15]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [15])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut<16> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [33]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [16]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [16])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy<16> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [15]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [33]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [16]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [16])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_xor<16> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [15]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [16]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [16])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut<17> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [34]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [17]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [17])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy<17> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [16]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [34]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [17]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [17])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_xor<17> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [16]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [17]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [17])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut<18> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [34]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [18]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [18])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy<18> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [17]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [34]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [18]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [18])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_xor<18> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [17]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [18]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [18])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut<19> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [34]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [19]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [19])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy<19> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [18]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [34]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [19]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [19])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_xor<19> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [18]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [19]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [19])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut<20> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [34]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [20]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [20])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy<20> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [19]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [34]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [20]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [20])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_xor<20> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [19]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [20]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [20])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut<21> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [34]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [21]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [21])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy<21> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [20]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [34]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [21]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [21])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_xor<21> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [20]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [21]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [21])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut<22> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [34]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [22]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [22])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy<22> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [21]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [34]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [22]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [22])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_xor<22> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [21]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [22]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [22])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut<23> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [34]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [23]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [23])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy<23> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [22]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [34]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [23]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [23])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_xor<23> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [22]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [23]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [23])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut<24> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [34]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [24]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [24])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy<24> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [23]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [34]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [24]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [24])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_xor<24> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [23]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [24]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [24])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut<25> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [34]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [25]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [25])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy<25> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [24]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [34]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [25]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [25])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_xor<25> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [24]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [25]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [25])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut<26> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [34]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [26]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [26])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy<26> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [25]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [34]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [26]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [26])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_xor<26> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [25]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [26]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [26])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut<27> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [34]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [27]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [27])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy<27> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [26]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [34]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [27]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [27])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_xor<27> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [26]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [27]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [27])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut<28> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [34]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [28]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [28])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy<28> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [27]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [34]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [28]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [28])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_xor<28> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [27]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [28]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [28])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut<29> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [34]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [29]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [29])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy<29> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [28]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [34]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [29]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [29])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_xor<29> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [28]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [29]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [29])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut<30> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [34]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [30]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [30])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy<30> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [29]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [34]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [30]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [30])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_xor<30> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [29]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [30]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [30])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut<31> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [34]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [31]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [31])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy<31> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [30]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [34]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [31]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [31])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_xor<31> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [30]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [31]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [31])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut<32> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [34]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [32]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [32])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_xor<32> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_cy [31]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s10_add0000_lut [32]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [32])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut<0> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [0]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [0]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [0])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy<0> (
.CI(\BU2/zero_detect [0]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [0]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [0]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [0])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_xor<0> (
.CI(\BU2/zero_detect [0]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [0]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[0] )
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut<1> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [1]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [1]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [1])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy<1> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [0]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [1]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [1]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [1])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_xor<1> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [0]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [1]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[1] )
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut<2> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [2]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [2]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [2])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy<2> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [1]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [2]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [2]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [2])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_xor<2> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [1]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [2]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[2] )
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut<3> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [3]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [3]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [3])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy<3> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [2]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [3]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [3]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [3])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_xor<3> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [2]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [3]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[3] )
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut<4> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [4]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [4]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [4])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy<4> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [3]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [4]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [4]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [4])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_xor<4> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [3]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [4]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[4] )
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut<5> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [5]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [5]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [5])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy<5> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [4]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [5]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [5]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [5])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_xor<5> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [4]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [5]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[5] )
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut<6> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [6]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [6]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [6])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy<6> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [5]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [6]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [6]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [6])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_xor<6> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [5]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [6]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[6] )
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut<7> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [7]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [7]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [7])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy<7> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [6]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [7]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [7]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [7])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_xor<7> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [6]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [7]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[7] )
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut<8> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [8]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [8]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [8])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy<8> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [7]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [8]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [8]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [8])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_xor<8> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [7]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [8]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[8] )
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut<9> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [9]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [9]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [9])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy<9> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [8]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [9]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [9]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [9])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_xor<9> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [8]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [9]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[9] )
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut<10> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [10]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [10]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [10])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy<10> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [9]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [10]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [10]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [10])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_xor<10> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [9]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [10]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[10] )
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut<11> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [11]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [11]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [11])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy<11> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [10]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [11]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [11]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [11])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_xor<11> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [10]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [11]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[11] )
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut<12> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [12]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [12]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [12])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy<12> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [11]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [12]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [12]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [12])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_xor<12> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [11]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [12]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[12] )
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut<13> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [13]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [13]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [13])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy<13> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [12]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [13]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [13]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [13])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_xor<13> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [12]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [13]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[13] )
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut<14> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [14]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [14]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [14])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy<14> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [13]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [14]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [14]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [14])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_xor<14> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [13]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [14]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[14] )
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut<15> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [15]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [15]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [15])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy<15> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [14]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [15]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [15]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [15])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_xor<15> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [14]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [15]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[15] )
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut<16> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [16]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [16]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [16])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy<16> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [15]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [16]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [16]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [16])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_xor<16> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [15]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [16]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[16] )
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut<17> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [17]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [0]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [17])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy<17> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [16]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [17]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [17]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [17])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_xor<17> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [16]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [17]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[17] )
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut<18> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [18]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [1]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [18])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy<18> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [17]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [18]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [18]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [18])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_xor<18> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [17]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [18]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[18] )
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut<19> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [19]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [2]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [19])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy<19> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [18]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [19]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [19]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [19])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_xor<19> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [18]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [19]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[19] )
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut<20> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [20]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [3]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [20])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy<20> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [19]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [20]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [20]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [20])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_xor<20> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [19]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [20]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[20] )
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut<21> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [21]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [4]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [21])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy<21> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [20]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [21]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [21]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [21])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_xor<21> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [20]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [21]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[21] )
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut<22> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [22]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [5]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [22])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy<22> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [21]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [22]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [22]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [22])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_xor<22> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [21]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [22]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[22] )
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut<23> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [23]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [6]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [23])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy<23> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [22]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [23]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [23]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [23])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_xor<23> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [22]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [23]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[23] )
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut<24> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [24]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [7]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [24])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy<24> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [23]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [24]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [24]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [24])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_xor<24> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [23]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [24]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[24] )
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut<25> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [25]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [8]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [25])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy<25> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [24]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [25]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [25]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [25])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_xor<25> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [24]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [25]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[25] )
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut<26> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [26]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [9]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [26])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy<26> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [25]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [26]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [26]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [26])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_xor<26> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [25]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [26]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[26] )
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut<27> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [27]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [10]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [27])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy<27> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [26]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [27]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [27]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [27])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_xor<27> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [26]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [27]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[27] )
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut<28> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [28]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [11]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [28])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy<28> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [27]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [28]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [28]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [28])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_xor<28> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [27]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [28]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[28] )
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut<29> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [29]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [12]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [29])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy<29> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [28]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [29]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [29]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [29])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_xor<29> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [28]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [29]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[29] )
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut<30> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [30]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [13]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [30])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy<30> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [29]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [30]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [30]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [30])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_xor<30> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [29]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [30]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[30] )
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut<31> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [31]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [14]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [31])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy<31> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [30]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [31]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [31]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [31])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_xor<31> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [30]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [31]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[31] )
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut<32> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [32]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [15]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [32])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy<32> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [31]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [32]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [32]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [32])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_xor<32> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [31]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [32]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[32] )
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut<33> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [32]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [16]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [33])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy<33> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [32]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [32]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [33]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [33])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_xor<33> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [32]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [33]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[33] )
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut<34> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [32]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [17]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [34])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy<34> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [33]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [32]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [34]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [34])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_xor<34> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [33]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [34]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[34] )
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut<35> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [32]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [18]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [35])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy<35> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [34]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [32]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [35]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [35])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_xor<35> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [34]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [35]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[35] )
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut<36> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [32]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [19]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [36])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy<36> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [35]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [32]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [36]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [36])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_xor<36> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [35]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [36]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[36] )
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut<37> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [32]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [20]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [37])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy<37> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [36]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [32]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [37]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [37])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_xor<37> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [36]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [37]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[37] )
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut<38> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [32]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [21]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [38])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy<38> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [37]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [32]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [38]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [38])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_xor<38> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [37]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [38]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[38] )
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut<39> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [32]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [22]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [39])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy<39> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [38]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [32]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [39]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [39])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_xor<39> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [38]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [39]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[39] )
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut<40> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [32]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [23]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [40])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy<40> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [39]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [32]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [40]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [40])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_xor<40> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [39]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [40]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[40] )
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut<41> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [32]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [24]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [41])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy<41> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [40]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [32]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [41]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [41])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_xor<41> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [40]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [41]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[41] )
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut<42> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [32]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [25]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [42])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy<42> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [41]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [32]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [42]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [42])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_xor<42> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [41]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [42]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[42] )
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut<43> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [32]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [26]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [43])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy<43> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [42]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [32]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [43]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [43])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_xor<43> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [42]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [43]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[43] )
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut<44> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [32]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [27]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [44])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy<44> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [43]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [32]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [44]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [44])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_xor<44> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [43]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [44]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[44] )
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut<45> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [32]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [28]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [45])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy<45> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [44]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [32]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [45]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [45])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_xor<45> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [44]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [45]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[45] )
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut<46> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [32]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [29]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [46])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy<46> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [45]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [32]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [46]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [46])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_xor<46> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [45]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [46]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[46] )
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut<47> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [32]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [30]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [47])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy<47> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [46]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [32]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [47]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [47])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_xor<47> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [46]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [47]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[47] )
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut<48> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [32]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [31]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [48])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy<48> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [47]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [32]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [48]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [48])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut<49> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [32]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [31]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [49])
);
MUXCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy<49> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [48]),
.DI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [32]),
.S(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [49]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [49])
);
LUT2 #(
.INIT ( 4'h6 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut<50> (
.I0(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s10 [32]),
.I1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s11 [31]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [50])
);
XORCY \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_xor<50> (
.CI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_cy [49]),
.LI(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/Madd_s20_lut [50]),
.O(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/s20[52] )
);
MULT18X18 \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/use_mult18x18.appMULT[0].bppMULT[0].no_Mreg.m18x18 (
.A({\BU2/zero_detect [0], a_2[16], a_2[15], a_2[14], a_2[13], a_2[12], a_2[11], a_2[10], a_2[9], a_2[8], a_2[7], a_2[6], a_2[5], a_2[4], a_2[3],
a_2[2], a_2[1], a_2[0]}),
.B({\BU2/zero_detect [0], b_3[16], b_3[15], b_3[14], b_3[13], b_3[12], b_3[11], b_3[10], b_3[9], b_3[8], b_3[7], b_3[6], b_3[5], b_3[4], b_3[3],
b_3[2], b_3[1], b_3[0]}),
.P({
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/use_mult18x18.appMULT[0].bppMULT[0].no_Mreg.m18x18_P<35>_UNCONNECTED
, \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [34],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [33],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [32],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [31],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [30],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [29],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [28],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [27],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [26],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [25],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [24],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [23],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [22],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [21],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [20],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [19],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [18],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [16],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [15],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [14],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [13],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [12],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [11],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [10],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [9],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [8],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [7],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [6],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [5],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [4],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [3],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [2],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [1],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><0> [0]})
);
MULT18X18 \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/use_mult18x18.appMULT[0].bppMULT[1].no_Mreg.m18x18 (
.A({\BU2/zero_detect [0], a_2[16], a_2[15], a_2[14], a_2[13], a_2[12], a_2[11], a_2[10], a_2[9], a_2[8], a_2[7], a_2[6], a_2[5], a_2[4], a_2[3],
a_2[2], a_2[1], a_2[0]}),
.B({b_3[32], b_3[32], b_3[32], b_3[31], b_3[30], b_3[29], b_3[28], b_3[27], b_3[26], b_3[25], b_3[24], b_3[23], b_3[22], b_3[21], b_3[20], b_3[19]
, b_3[18], b_3[17]}),
.P({
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/use_mult18x18.appMULT[0].bppMULT[1].no_Mreg.m18x18_P<35>_UNCONNECTED
,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/use_mult18x18.appMULT[0].bppMULT[1].no_Mreg.m18x18_P<34>_UNCONNECTED
,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/use_mult18x18.appMULT[0].bppMULT[1].no_Mreg.m18x18_P<33>_UNCONNECTED
, \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [32],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [31],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [30],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [29],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [28],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [27],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [26],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [25],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [24],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [23],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [22],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [21],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [20],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [19],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [18],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [16],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [15],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [14],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [13],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [12],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [11],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [10],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [9],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [8],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [7],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [6],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [5],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [4],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [3],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [2],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [1],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<0><1> [0]})
);
MULT18X18 \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/use_mult18x18.appMULT[1].bppMULT[0].no_Mreg.m18x18 (
.A({a_2[32], a_2[32], a_2[32], a_2[31], a_2[30], a_2[29], a_2[28], a_2[27], a_2[26], a_2[25], a_2[24], a_2[23], a_2[22], a_2[21], a_2[20], a_2[19]
, a_2[18], a_2[17]}),
.B({\BU2/zero_detect [0], b_3[16], b_3[15], b_3[14], b_3[13], b_3[12], b_3[11], b_3[10], b_3[9], b_3[8], b_3[7], b_3[6], b_3[5], b_3[4], b_3[3],
b_3[2], b_3[1], b_3[0]}),
.P({
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/use_mult18x18.appMULT[1].bppMULT[0].no_Mreg.m18x18_P<35>_UNCONNECTED
,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/use_mult18x18.appMULT[1].bppMULT[0].no_Mreg.m18x18_P<34>_UNCONNECTED
,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/use_mult18x18.appMULT[1].bppMULT[0].no_Mreg.m18x18_P<33>_UNCONNECTED
, \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [32],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [31],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [30],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [29],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [28],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [27],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [26],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [25],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [24],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [23],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [22],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [21],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [20],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [19],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [18],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [16],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [15],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [14],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [13],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [12],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [11],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [10],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [9],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [8],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [7],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [6],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [5],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [4],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [3],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [2],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [1],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><0> [0]})
);
MULT18X18 \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/use_mult18x18.appMULT[1].bppMULT[1].no_Mreg.m18x18 (
.A({a_2[32], a_2[32], a_2[32], a_2[31], a_2[30], a_2[29], a_2[28], a_2[27], a_2[26], a_2[25], a_2[24], a_2[23], a_2[22], a_2[21], a_2[20], a_2[19]
, a_2[18], a_2[17]}),
.B({b_3[32], b_3[32], b_3[32], b_3[31], b_3[30], b_3[29], b_3[28], b_3[27], b_3[26], b_3[25], b_3[24], b_3[23], b_3[22], b_3[21], b_3[20], b_3[19]
, b_3[18], b_3[17]}),
.P({
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/use_mult18x18.appMULT[1].bppMULT[1].no_Mreg.m18x18_P<35>_UNCONNECTED
,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/use_mult18x18.appMULT[1].bppMULT[1].no_Mreg.m18x18_P<34>_UNCONNECTED
,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/use_mult18x18.appMULT[1].bppMULT[1].no_Mreg.m18x18_P<33>_UNCONNECTED
,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/use_mult18x18.appMULT[1].bppMULT[1].no_Mreg.m18x18_P<32>_UNCONNECTED
, \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [31],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [30],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [29],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [28],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [27],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [26],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [25],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [24],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [23],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [22],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [21],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [20],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [19],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [18],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [16],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [15],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [14],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [13],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [12],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [11],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [10],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [9],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [8],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [7],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [6],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [5],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [4],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [3],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [2],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [1],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gMULT18.iMULT18/pi_Mreg<1><1> [0]})
);
GND \BU2/XST_GND (
.G(\BU2/zero_detect [0])
);
// synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
wire GSR;
wire GTS;
wire PRLD;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
// synthesis translate_on
|
//
// my_fpga_test_count_dn_1k.v
//
`timescale 1ns/1ps
`define ms(t) (t * 1e6)
`define ns(t) (t)
module my_fpga_test_count_dn_1k;
reg clk = 0, n_rst = 0;
reg up = 0, dn = 0;
wire [31:0] cnt;
wire [3:0] cnt_1k;
reg in1 = 0, in2 = 0;
wire out1, out2;
time t, u;
my_fpga uut(clk, n_rst, up, dn, cnt, cnt_1k, in1, in2, out1, out2);
tbmsgs msgs();
always
#5 clk = ~clk;
initial
begin
msgs.testcase("my_fpga count dn 1k", 1);
#1000
n_rst = 1;
#1000
@(negedge clk);
dn <= 1;
// wait until cnt_1k output is 0xf
begin : break1
while (1) begin
@(negedge clk);
if (cnt_1k == 4'hf) begin
t = $time;
disable break1;
end
end
end
// wait until cnt_1k output is 0x5
begin : break2
while (1) begin
@(negedge clk);
if (cnt_1k == 4'h5) begin
t = $time - t;
disable break2;
end
end
end
msgs.check(t > `ms(10) - `ns(100) && t < `ms(10) + `ns(100),
"cnt_1k output should count at 1KHz");
msgs.tested("count 1k output");
msgs.testcase_complete();
$stop;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:57:50 08/25/2009
// Design Name:
// Module Name: mcu_cmd
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module mcu_cmd(
input clk,
input cmd_ready,
input param_ready,
input [7:0] cmd_data,
input [7:0] param_data,
output [2:0] mcu_mapper,
output reg mcu_rrq = 0,
output mcu_write,
output reg mcu_wrq = 0,
input mcu_rq_rdy,
output [7:0] mcu_data_out,
input [7:0] mcu_data_in,
output [7:0] spi_data_out,
input [31:0] spi_byte_cnt,
input [2:0] spi_bit_cnt,
output [23:0] addr_out,
output [23:0] saveram_mask_out,
output [23:0] rom_mask_out,
// SD "DMA" extension
output SD_DMA_EN,
input SD_DMA_STATUS,
input SD_DMA_NEXTADDR,
input [7:0] SD_DMA_SRAM_DATA,
input SD_DMA_SRAM_WE,
output [1:0] SD_DMA_TGT,
output SD_DMA_PARTIAL,
output [10:0] SD_DMA_PARTIAL_START,
output [10:0] SD_DMA_PARTIAL_END,
output reg SD_DMA_START_MID_BLOCK,
output reg SD_DMA_END_MID_BLOCK,
// DAC
output [10:0] dac_addr_out,
input DAC_STATUS,
output reg dac_play_out = 0,
output reg dac_reset_out = 0,
output reg [2:0] dac_vol_select_out = 3'b000,
output reg dac_palmode_out = 0,
output reg [8:0] dac_ptr_out = 0,
// MSU data
output [13:0] msu_addr_out,
input [7:0] MSU_STATUS,
output [5:0] msu_status_reset_out,
output [5:0] msu_status_set_out,
output msu_status_reset_we,
input [31:0] msu_addressrq,
input [15:0] msu_trackrq,
input [7:0] msu_volumerq,
output [13:0] msu_ptr_out,
output msu_reset_out,
// feature enable
output reg [7:0] featurebits_out,
output reg region_out,
// SNES sync/clk
input snes_sysclk,
// snes cmd interface
input [7:0] snescmd_data_in,
output reg [7:0] snescmd_data_out,
output reg [8:0] snescmd_addr_out,
output reg snescmd_we_out,
// cheat configuration
output reg [7:0] cheat_pgm_idx_out,
output reg [31:0] cheat_pgm_data_out,
output reg cheat_pgm_we_out,
// debug
output DBG_mcu_nextaddr
);
initial begin
region_out = 0;
SD_DMA_START_MID_BLOCK = 0;
SD_DMA_END_MID_BLOCK = 0;
end
wire [31:0] snes_sysclk_freq;
clk_test snes_clk_test (
.clk(clk),
.sysclk(snes_sysclk),
.snes_sysclk_freq(snes_sysclk_freq)
);
reg [2:0] MAPPER_BUF;
reg [23:0] ADDR_OUT_BUF;
reg [10:0] DAC_ADDR_OUT_BUF;
reg [7:0] DAC_VOL_OUT_BUF;
reg [13:0] MSU_ADDR_OUT_BUF;
reg [13:0] MSU_PTR_OUT_BUF;
reg [5:0] msu_status_set_out_buf;
reg [5:0] msu_status_reset_out_buf;
reg msu_status_reset_we_buf = 0;
reg MSU_RESET_OUT_BUF;
reg [31:0] SNES_SYSCLK_FREQ_BUF;
reg [7:0] MCU_DATA_OUT_BUF;
reg [7:0] MCU_DATA_IN_BUF;
reg [2:0] mcu_nextaddr_buf;
wire mcu_nextaddr;
reg DAC_STATUSr;
reg SD_DMA_STATUSr;
reg [7:0] MSU_STATUSr;
always @(posedge clk) begin
DAC_STATUSr <= DAC_STATUS;
SD_DMA_STATUSr <= SD_DMA_STATUS;
MSU_STATUSr <= MSU_STATUS;
end
reg SD_DMA_PARTIALr;
assign SD_DMA_PARTIAL = SD_DMA_PARTIALr;
reg SD_DMA_ENr;
assign SD_DMA_EN = SD_DMA_ENr;
reg [1:0] SD_DMA_TGTr;
assign SD_DMA_TGT = SD_DMA_TGTr;
reg [10:0] SD_DMA_PARTIAL_STARTr;
reg [10:0] SD_DMA_PARTIAL_ENDr;
assign SD_DMA_PARTIAL_START = SD_DMA_PARTIAL_STARTr;
assign SD_DMA_PARTIAL_END = SD_DMA_PARTIAL_ENDr;
reg [23:0] SAVERAM_MASK;
reg [23:0] ROM_MASK;
assign spi_data_out = MCU_DATA_IN_BUF;
initial begin
ADDR_OUT_BUF = 0;
DAC_ADDR_OUT_BUF = 0;
MSU_ADDR_OUT_BUF = 0;
SD_DMA_ENr = 0;
MAPPER_BUF = 1;
SD_DMA_PARTIALr = 0;
end
// command interpretation
always @(posedge clk) begin
snescmd_we_out <= 1'b0;
cheat_pgm_we_out <= 1'b0;
dac_reset_out <= 1'b0;
MSU_RESET_OUT_BUF <= 1'b0;
if (cmd_ready) begin
case (cmd_data[7:4])
4'h3: // select mapper
MAPPER_BUF <= cmd_data[2:0];
4'h4: begin// SD DMA
SD_DMA_ENr <= 1;
SD_DMA_TGTr <= cmd_data[1:0];
SD_DMA_PARTIALr <= cmd_data[2];
end
4'h8: SD_DMA_TGTr <= 2'b00;
4'h9: SD_DMA_TGTr <= 2'b00; // cmd_data[1:0]; // not implemented
// 4'hE:
// select memory unit
endcase
end else if (param_ready) begin
casex (cmd_data[7:0])
8'h1x:
case (spi_byte_cnt)
32'h2:
ROM_MASK[23:16] <= param_data;
32'h3:
ROM_MASK[15:8] <= param_data;
32'h4:
ROM_MASK[7:0] <= param_data;
endcase
8'h2x:
case (spi_byte_cnt)
32'h2:
SAVERAM_MASK[23:16] <= param_data;
32'h3:
SAVERAM_MASK[15:8] <= param_data;
32'h4:
SAVERAM_MASK[7:0] <= param_data;
endcase
8'h4x:
SD_DMA_ENr <= 1'b0;
8'h6x:
case (spi_byte_cnt)
32'h2: begin
SD_DMA_START_MID_BLOCK <= param_data[7];
SD_DMA_PARTIAL_STARTr[10:9] <= param_data[1:0];
end
32'h3:
SD_DMA_PARTIAL_STARTr[8:0] <= {param_data, 1'b0};
32'h4: begin
SD_DMA_END_MID_BLOCK <= param_data[7];
SD_DMA_PARTIAL_ENDr[10:9] <= param_data[1:0];
end
32'h5:
SD_DMA_PARTIAL_ENDr[8:0] <= {param_data, 1'b0};
endcase
8'h9x:
MCU_DATA_OUT_BUF <= param_data;
8'hd0:
case (spi_byte_cnt)
32'h2:
snescmd_addr_out[7:0] <= param_data;
32'h3:
snescmd_addr_out[8] <= param_data[0];
endcase
8'hd1:
snescmd_addr_out <= snescmd_addr_out + 1;
8'hd2: begin
case (spi_byte_cnt)
32'h2:
snescmd_we_out <= 1'b1;
32'h3:
snescmd_addr_out <= snescmd_addr_out + 1;
endcase
snescmd_data_out <= param_data;
end
8'hd3: begin
case (spi_byte_cnt)
32'h2:
cheat_pgm_idx_out <= param_data[2:0];
32'h3:
cheat_pgm_data_out[31:24] <= param_data;
32'h4:
cheat_pgm_data_out[23:16] <= param_data;
32'h5:
cheat_pgm_data_out[15:8] <= param_data;
32'h6: begin
cheat_pgm_data_out[7:0] <= param_data;
cheat_pgm_we_out <= 1'b1;
end
endcase
end
8'he0:
case (spi_byte_cnt)
32'h2: begin
msu_status_set_out_buf <= param_data[5:0];
end
32'h3: begin
msu_status_reset_out_buf <= param_data[5:0];
msu_status_reset_we_buf <= 1'b1;
end
32'h4:
msu_status_reset_we_buf <= 1'b0;
endcase
8'he1: // pause DAC
dac_play_out <= 1'b0;
8'he2: // resume DAC
dac_play_out <= 1'b1;
8'he3: // reset DAC (set DAC playback address = 0)
case (spi_byte_cnt)
32'h2:
dac_ptr_out[8] <= param_data[0];
32'h3: begin
dac_ptr_out[7:0] <= param_data;
dac_reset_out <= 1'b1; // reset by default value, see above
end
endcase
8'he4: // reset MSU read buffer pointer
case (spi_byte_cnt)
32'h2: begin
MSU_PTR_OUT_BUF[13:8] <= param_data[5:0];
MSU_PTR_OUT_BUF[7:0] <= 8'h0;
end
32'h3: begin
MSU_PTR_OUT_BUF[7:0] <= param_data;
MSU_RESET_OUT_BUF <= 1'b1;
end
endcase
8'hec: // set DAC properties
begin
dac_vol_select_out <= param_data[2:0];
dac_palmode_out <= param_data[7];
end
8'hed:
featurebits_out <= param_data;
8'hee:
region_out <= param_data[0];
endcase
end
end
always @(posedge clk) begin
if(param_ready && cmd_data[7:4] == 4'h0) begin
case (cmd_data[1:0])
2'b01: begin
case (spi_byte_cnt)
32'h2: begin
DAC_ADDR_OUT_BUF[10:8] <= param_data[2:0];
DAC_ADDR_OUT_BUF[7:0] <= 8'b0;
end
32'h3:
DAC_ADDR_OUT_BUF[7:0] <= param_data;
endcase
end
2'b10: begin
case (spi_byte_cnt)
32'h2: begin
MSU_ADDR_OUT_BUF[13:8] <= param_data[5:0];
MSU_ADDR_OUT_BUF[7:0] <= 8'b0;
end
32'h3:
MSU_ADDR_OUT_BUF[7:0] <= param_data;
endcase
end
default:
case (spi_byte_cnt)
32'h2: begin
ADDR_OUT_BUF[23:16] <= param_data;
ADDR_OUT_BUF[15:0] <= 16'b0;
end
32'h3:
ADDR_OUT_BUF[15:8] <= param_data;
32'h4:
ADDR_OUT_BUF[7:0] <= param_data;
endcase
endcase
end else if (SD_DMA_NEXTADDR | (mcu_nextaddr & (cmd_data[7:5] == 3'h4)
&& (cmd_data[3])
&& (spi_byte_cnt >= (32'h1+cmd_data[4])))
) begin
case (SD_DMA_TGTr)
2'b00: ADDR_OUT_BUF <= ADDR_OUT_BUF + 1;
2'b01: DAC_ADDR_OUT_BUF <= DAC_ADDR_OUT_BUF + 1;
2'b10: MSU_ADDR_OUT_BUF <= MSU_ADDR_OUT_BUF + 1;
endcase
end
end
// value fetch during last SPI bit
always @(posedge clk) begin
if (cmd_data[7:4] == 4'h8 && mcu_nextaddr)
MCU_DATA_IN_BUF <= mcu_data_in;
else if (cmd_ready | param_ready /* bit_cnt == 7 */) begin
if (cmd_data[7:0] == 8'hF0)
MCU_DATA_IN_BUF <= 8'hA5;
else if (cmd_data[7:0] == 8'hF1)
case (spi_byte_cnt[0])
1'b1: // buffer status (1st byte)
MCU_DATA_IN_BUF <= {SD_DMA_STATUSr, DAC_STATUSr, MSU_STATUSr[7], 5'b0};
1'b0: // control status (2nd byte)
MCU_DATA_IN_BUF <= {1'b0, MSU_STATUSr[6:0]};
endcase
else if (cmd_data[7:0] == 8'hF2)
case (spi_byte_cnt)
32'h1:
MCU_DATA_IN_BUF <= msu_addressrq[31:24];
32'h2:
MCU_DATA_IN_BUF <= msu_addressrq[23:16];
32'h3:
MCU_DATA_IN_BUF <= msu_addressrq[15:8];
32'h4:
MCU_DATA_IN_BUF <= msu_addressrq[7:0];
endcase
else if (cmd_data[7:0] == 8'hF3)
case (spi_byte_cnt)
32'h1:
MCU_DATA_IN_BUF <= msu_trackrq[15:8];
32'h2:
MCU_DATA_IN_BUF <= msu_trackrq[7:0];
endcase
else if (cmd_data[7:0] == 8'hF4)
MCU_DATA_IN_BUF <= msu_volumerq;
else if (cmd_data[7:0] == 8'hFE)
case (spi_byte_cnt)
32'h1:
SNES_SYSCLK_FREQ_BUF <= snes_sysclk_freq;
32'h2:
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[31:24];
32'h3:
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[23:16];
32'h4:
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[15:8];
32'h5:
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[7:0];
endcase
else if (cmd_data[7:0] == 8'hFF)
MCU_DATA_IN_BUF <= param_data;
else if (cmd_data[7:0] == 8'hD1)
MCU_DATA_IN_BUF <= snescmd_data_in;
end
end
// nextaddr pulse generation
always @(posedge clk) begin
mcu_nextaddr_buf <= {mcu_nextaddr_buf[1:0], mcu_rq_rdy};
end
always @(posedge clk) begin
mcu_rrq <= 1'b0;
if((param_ready | cmd_ready) && cmd_data[7:4] == 4'h8) begin
mcu_rrq <= 1'b1;
end
end
always @(posedge clk) begin
mcu_wrq <= 1'b0;
if(param_ready && cmd_data[7:4] == 4'h9) begin
mcu_wrq <= 1'b1;
end
end
// trigger for nextaddr
assign mcu_nextaddr = mcu_nextaddr_buf == 2'b01;
assign mcu_write = SD_DMA_STATUS
? (SD_DMA_TGTr == 2'b00
? SD_DMA_SRAM_WE
: 1'b1
)
: 1'b1;
assign addr_out = ADDR_OUT_BUF;
assign dac_addr_out = DAC_ADDR_OUT_BUF;
assign msu_addr_out = MSU_ADDR_OUT_BUF;
assign msu_status_reset_we = msu_status_reset_we_buf;
assign msu_status_reset_out = msu_status_reset_out_buf;
assign msu_status_set_out = msu_status_set_out_buf;
assign msu_reset_out = MSU_RESET_OUT_BUF;
assign msu_ptr_out = MSU_PTR_OUT_BUF;
assign mcu_data_out = SD_DMA_STATUS ? SD_DMA_SRAM_DATA : MCU_DATA_OUT_BUF;
assign mcu_mapper = MAPPER_BUF;
assign rom_mask_out = ROM_MASK;
assign saveram_mask_out = SAVERAM_MASK;
assign DBG_mcu_nextaddr = mcu_nextaddr;
endmodule
|
module adv7513_reconfig (
input clock,
input [7:0] data_in,
input [7:0] clock_config_data,
input [1:0] colorspace_in,
output ADV7513Config adv7513Config,
output [7:0] clock_data_out,
output [1:0] colorspace_out,
output adv7513_reconf
);
`include "../config/adv_config.v"
reg [7:0] data_in_reg = 0;
reg [1:0] colorspace_in_reg = 0;
reg [7:0] clock_config_data_reg = 0;
reg [7:0] clock_data_out_reg = 8'b_0110_0000;
reg [1:0] colorspace_reg = 0;
reg adv7513_reconf_reg;
ADV7513Config adv7513Config_reg;
initial begin
adv7513Config_reg <= ADV7513_CONFIG_1080P;
end
assign adv7513Config = adv7513Config_reg;
assign clock_data_out = clock_data_out_reg;
assign adv7513_reconf = adv7513_reconf_reg;
assign colorspace_out = colorspace_reg;
always @(posedge clock) begin
data_in_reg <= data_in;
colorspace_in_reg <= colorspace_in;
clock_config_data_reg <= clock_config_data;
if (data_in_reg != data_in
|| colorspace_in_reg != colorspace_in
|| clock_config_data_reg != clock_config_data
) begin
adv7513_reconf_reg <= 1'b1;
if (data_in_reg != data_in) begin
case (data_in[6:0])
// RECONF
7'h00: adv7513Config_reg <= ADV7513_CONFIG_1080P;
7'h01: adv7513Config_reg <= ADV7513_CONFIG_960P;
7'h02: adv7513Config_reg <= ADV7513_CONFIG_480P;
7'h03: adv7513Config_reg <= ADV7513_CONFIG_VGA;
7'h04: adv7513Config_reg <= ADV7513_CONFIG_288P;
7'h05: adv7513Config_reg <= ADV7513_CONFIG_288P;
7'h06: adv7513Config_reg <= ADV7513_CONFIG_288P;
7'h07: adv7513Config_reg <= ADV7513_CONFIG_288P;
7'h08: adv7513Config_reg <= ADV7513_CONFIG_576P;
7'h09: adv7513Config_reg <= ADV7513_CONFIG_576P;
7'h0A: adv7513Config_reg <= ADV7513_CONFIG_576P;
7'h0B: adv7513Config_reg <= ADV7513_CONFIG_576P;
7'h10: adv7513Config_reg <= ADV7513_CONFIG_240P_1080P;
7'h11: adv7513Config_reg <= ADV7513_CONFIG_240P_960P;
7'h12: adv7513Config_reg <= ADV7513_CONFIG_240P_480P;
7'h13: adv7513Config_reg <= ADV7513_CONFIG_240P_VGA;
7'h20: adv7513Config_reg <= ADV7513_CONFIG_480I;
7'h21: adv7513Config_reg <= ADV7513_CONFIG_480I;
7'h22: adv7513Config_reg <= ADV7513_CONFIG_480I;
7'h23: adv7513Config_reg <= ADV7513_CONFIG_480I;
7'h40: adv7513Config_reg <= ADV7513_CONFIG_576I;
7'h41: adv7513Config_reg <= ADV7513_CONFIG_576I;
7'h42: adv7513Config_reg <= ADV7513_CONFIG_576I;
7'h43: adv7513Config_reg <= ADV7513_CONFIG_576I;
endcase
end
if (clock_config_data_reg != clock_config_data) begin
//clock_data_out_reg <= clock_config_data[7:5] << 5;
case (clock_config_data)
0: clock_data_out_reg <= 8'b_0000_0000; // -1.2ns
1: clock_data_out_reg <= 8'b_0010_0000; // -0.8ns
2: clock_data_out_reg <= 8'b_0100_0000; // -0.4ns
3: clock_data_out_reg <= 8'b_0110_0000; // no delay
4: clock_data_out_reg <= 8'b_1000_0000; // 0.4ns
5: clock_data_out_reg <= 8'b_1010_0000; // 0.8ns
6: clock_data_out_reg <= 8'b_1100_0000; // 1.2ns
7: clock_data_out_reg <= 8'b_1110_0000; // 1.6ns
endcase
end
colorspace_reg <= colorspace_in;
end else begin
adv7513_reconf_reg <= 0;
end
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: cpx_buf_p0.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: cpx_buf_p0
// Description: datapath portion of CPX
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
`include "sys.h"
`include "iop.h"
module cpx_buf_p0(/*AUTOARG*/
// Outputs
scache0_cpx_req_bufp0_cq, scache0_cpx_atom_bufp0_cq,
cpx_scache0_grant_bufp0_ca, cpx_spc0_data_rdy_bufp0_cx,
// Inputs
scache0_cpx_req_bufpt_cq_l, scache0_cpx_atom_bufpt_cq_l,
cpx_scache0_grant_bufp1_ca_l, cpx_spc0_data_rdy_bufp1_cx
);
output [7:0] scache0_cpx_req_bufp0_cq;
output scache0_cpx_atom_bufp0_cq;
output [7:0] cpx_scache0_grant_bufp0_ca;
output cpx_spc0_data_rdy_bufp0_cx;
input [7:0] scache0_cpx_req_bufpt_cq_l;
input scache0_cpx_atom_bufpt_cq_l;
input [7:0] cpx_scache0_grant_bufp1_ca_l;
input cpx_spc0_data_rdy_bufp1_cx;
assign scache0_cpx_req_bufp0_cq[7:0] = ~scache0_cpx_req_bufpt_cq_l[7:0];
assign scache0_cpx_atom_bufp0_cq = ~scache0_cpx_atom_bufpt_cq_l;
assign cpx_scache0_grant_bufp0_ca = ~cpx_scache0_grant_bufp1_ca_l;
assign cpx_spc0_data_rdy_bufp0_cx = cpx_spc0_data_rdy_bufp1_cx;
endmodule
|
`timescale 1ns / 1ps
module top_sch(clk_in,
Drive_mfm_in,
Drive_sector_in,
rst_in,
SPI_clk,
SPI_CS,
SPI_MOSI,
SPI_CurWordIsHeader,
drive_command_n,
drive_command_p,
drive_sel0_n,
drive_sel0_p,
drive_sel1_n,
drive_sel1_p,
drive_clock_p,
drive_clock_n,
writeGate_p,
writeGate_n,
writeData_p,
writeData_n,
drive_ready,
SPI_CommandAndWriteEmpty,
SPI_DataWAIT,
SPI_MISO,
crcInvalid,
commandAndWriteFIFO_prog_full);
input clk_in;
input Drive_mfm_in;
input Drive_sector_in;
input rst_in;
input SPI_clk;
input SPI_CS;
input SPI_MOSI;
input drive_ready;
output drive_command_n;
output drive_command_p;
output drive_sel0_n;
output drive_sel0_p;
output drive_sel1_n;
output drive_sel1_p;
output writeData_p;
output writeData_n;
output writeGate_p;
output writeGate_n;
output SPI_CommandAndWriteEmpty;
output SPI_CurWordIsHeader;
output SPI_DataWAIT;
output SPI_MISO;
output crcInvalid;
output commandAndWriteFIFO_prog_full;
output drive_clock_p;
output drive_clock_n;
wire currentRealBit;
wire currentRealBitValid;
wire skipMFMBit;
wire MFMEdgeStrobe;
wire [2:0] decode_state;
wire headerBitIn;
wire headerBitInStrobe;
wire drive_sel0;
wire drive_sel1;
wire writeData;
wire drive_clock;
wire writeGate;
wire mfmData;
wire [8:0] cylNum;
wire [5:0] sectorNum;
wire headNumReady;
wire headNum;
wire cylNumReady;
wire sectorNumReady;
wire FIFOReadEnable;
wire drive_command;
wire [16:0] dataOut;
wire dataOutReady;
wire inhibit_read;
wire rst_ReadDatapath;
wire beginWriteNow;
wire rst_in;
wire SPI_FIFOAcceptingData;
wire SPIInterface_DataAvailable;
wire [15:0] internalMOSI;
wire [16:0] internalMISO;
wire [15:0] SPICommandWord;
wire SPI_clk_sync;
assign SPI_CurWordIsHeader = internalMISO[16];
commandAndWriteFIFO commandAndWriteFIFO0 (.din(internalMOSI),
.clk(clk_in),
.rd_en(FIFOReadEnable),
.srst(rst_in),
.wr_en(SPIInterface_DataAvailable),
.dout(SPICommandWord),
.empty(SPI_CommandAndWriteEmpty),
.full(),
.prog_full(commandAndWriteFIFO_prog_full));
dataFIFO dataFIFO0 (.din(dataOut),
.rd_en(SPIInterface_DataAvailable),
.srst(rst_ReadDatapath),
.clk(clk_in),
.wr_en(dataOutReady),
.dout(internalMISO),
.empty(SPI_DataWAIT),
.full(),
.prog_empty(SPI_FIFOAcceptingData));
spi_slave spi0 (.clk(clk_in),
.rst(rst_in),
.ss(SPI_CS),
.mosi(SPI_MOSI),
.miso(SPI_MISO),
.sck(SPI_clk_sync),
.done(SPIInterface_DataAvailable),
.din(internalMISO[15:0]),
.dout(internalMOSI));
OR2 FSMResetOR (.I0(rst_in),
.I1(inhibit_read),
.O(rst_ReadDatapath));
headerDecode headerDecode0 (.clk(clk_in),
.decode_state(decode_state[2:0]),
.headerBitIn(headerBitIn),
.headerBitInStrobe(headerBitInStrobe),
.rst(rst_ReadDatapath),
.crcInvalid(crcInvalid),
.cylNum(cylNum[8:0]),
.cylNumReady(cylNumReady),
.headNum(headNum),
.headNumReady(headNumReady),
.sectorNum(sectorNum[5:0]),
.sectorNumReady(sectorNumReady));
decodeFSM decodeFSM0 (.clk(clk_in),
.currentRealBit(currentRealBit),
.currentRealBitValid(currentRealBitValid),
.prog_empty(SPI_FIFOAcceptingData),
.rst(rst_ReadDatapath),
.sectorPulse(sectorPulse),
.wordOut(dataOut),
.wordOutReady(dataOutReady),
.decode_state(decode_state[2:0]),
.headerOut(headerBitIn),
.headerOutStrobe(headerBitInStrobe),
.skipMFMBit(skipMFMBit),
.beginWriteNow(beginWriteNow));
mfmDecode mfmDecode0 (.clk(clk_in),
.mfmEdge(MFMEdgeStrobe),
.mfmIn(mfmData),
.rst(rst_in),
.skipMFMBit(skipMFMBit),
.currentRealBit(currentRealBit),
.currentRealBitValid(currentRealBitValid));
edgeDetect mfmEdgeDetect (.clk(clk_in),
.data(mfmData),
.rst(rst_in),
.strobe(MFMEdgeStrobe));
inputSync mfmInputSync (.async_in(Drive_mfm_in),
.clk(clk_in),
.rst(rst_in),
.sync_out(mfmData));
inputSync readySync (.async_in(Drive_sector_in),
.clk(clk_in),
.rst(rst_in),
.sync_out(sectorPulse));
inputSync sectorSync (.async_in(drive_ready),
.clk(clk_in),
.rst(rst_in),
.sync_out(driveReady));
inputSync SPIclkSync (.async_in(SPI_clk),
.clk(clk_in),
.rst(rst_in),
.sync_out(SPI_clk_sync));
driveControl driveControl0 (.clk(clk_in),
.cylNumIn(cylNum[8:0]),
.cylNumInReady(cylNumReady),
.headNumIn(headNum),
.headNumInReady(headNumReady),
.rst(rst_in),
.sectorNumIn(sectorNum[5:0]),
.sectorNumInReady(sectorNumReady),
.sector_pulse(sectorPulse),
.SPICommandWord(SPICommandWord),
.SPIFIFOEmpty(SPI_CommandAndWriteEmpty),
.drive_command(drive_command),
.FIFOReadEnable(FIFOReadEnable),
.inhibit_read(inhibit_read),
.writeData(writeData),
.writeGate(writeGate),
.drive_ready(driveReady),
.drive_clock(drive_clock),
.beginWriteNow(beginWriteNow),
.SPIProgFull(commandAndWriteFIFO_prog_full));
GND XLXI_51 (.G(drive_sel0));
GND XLXI_53 (.G(drive_sel1));
//The drive attributes have to be here because the OBUF construct has a default value
OBUF #(.DRIVE(16)) drivesel0_bufp (.I(drive_sel0),
.O(drive_sel0_p));
OBUF #(.DRIVE(16)) drivesel0_bufn (.I(~drive_sel0),
.O(drive_sel0_n));
OBUF #(.DRIVE(16)) drivesel1_bufp (.I(drive_sel1),
.O(drive_sel1_p));
OBUF #(.DRIVE(16)) drivesel1_bufn (.I(~drive_sel1),
.O(drive_sel1_n));
OBUF #(.DRIVE(16)) writeData_bufp (.I(writeData),
.O(writeData_p));
OBUF #(.DRIVE(16)) writeData_bufn (.I(~writeData),
.O(writeData_n));
/*OBUFDS XLXI_63 (.I(writeGate),
.O(writeGate_p),
.OB(writeGate_n));*/
OBUF #(.DRIVE(16)) writeGate_bufp (.I(writeGate),
.O(writeGate_p));
OBUF #(.DRIVE(16)) writeGate_bufn (.I(~writeGate),
.O(writeGate_n));
OBUF #(.DRIVE(16)) driveClock_bufp (.I(drive_clock),
.O(drive_clock_p));
OBUF #(.DRIVE(16)) driveClock_bufn (.I(~drive_clock),
.O(drive_clock_n));
OBUF #(.DRIVE(16)) drive_command_bufp (.I(drive_command),
.O(drive_command_p));
OBUF #(.DRIVE(16)) drive_command_bufn (.I(~drive_command),
.O(drive_command_n));
endmodule
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_unused_ports.v
*
* Date : 2012-11
*
* Description : Semantic checks for unused ports.
*
*****************************************************************************/
/* CAN */
assign CAN0_PHY_TX = 0;
assign CAN1_PHY_TX = 0;
always @(CAN0_PHY_RX or CAN1_PHY_RX)
begin
if(CAN0_PHY_RX | CAN1_PHY_RX)
$display("[%0d] : %0s : CAN Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* ETHERNET */
/* ------------------------------------------- */
assign ENET0_GMII_TX_EN = 0;
assign ENET0_GMII_TX_ER = 0;
assign ENET0_MDIO_MDC = 0;
assign ENET0_MDIO_O = 0; /// confirm
assign ENET0_MDIO_T = 0;
assign ENET0_PTP_DELAY_REQ_RX = 0;
assign ENET0_PTP_DELAY_REQ_TX = 0;
assign ENET0_PTP_PDELAY_REQ_RX = 0;
assign ENET0_PTP_PDELAY_REQ_TX = 0;
assign ENET0_PTP_PDELAY_RESP_RX = 0;
assign ENET0_PTP_PDELAY_RESP_TX = 0;
assign ENET0_PTP_SYNC_FRAME_RX = 0;
assign ENET0_PTP_SYNC_FRAME_TX = 0;
assign ENET0_SOF_RX = 0;
assign ENET0_SOF_TX = 0;
assign ENET0_GMII_TXD = 0;
always@(ENET0_GMII_COL or ENET0_GMII_CRS or ENET0_EXT_INTIN or
ENET0_GMII_RX_CLK or ENET0_GMII_RX_DV or ENET0_GMII_RX_ER or
ENET0_GMII_TX_CLK or ENET0_MDIO_I or ENET0_GMII_RXD)
begin
if(ENET0_GMII_COL | ENET0_GMII_CRS | ENET0_EXT_INTIN |
ENET0_GMII_RX_CLK | ENET0_GMII_RX_DV | ENET0_GMII_RX_ER |
ENET0_GMII_TX_CLK | ENET0_MDIO_I )
$display("[%0d] : %0s : ETHERNET Interface is not supported.",$time, DISP_ERR);
end
assign ENET1_GMII_TX_EN = 0;
assign ENET1_GMII_TX_ER = 0;
assign ENET1_MDIO_MDC = 0;
assign ENET1_MDIO_O = 0;/// confirm
assign ENET1_MDIO_T = 0;
assign ENET1_PTP_DELAY_REQ_RX = 0;
assign ENET1_PTP_DELAY_REQ_TX = 0;
assign ENET1_PTP_PDELAY_REQ_RX = 0;
assign ENET1_PTP_PDELAY_REQ_TX = 0;
assign ENET1_PTP_PDELAY_RESP_RX = 0;
assign ENET1_PTP_PDELAY_RESP_TX = 0;
assign ENET1_PTP_SYNC_FRAME_RX = 0;
assign ENET1_PTP_SYNC_FRAME_TX = 0;
assign ENET1_SOF_RX = 0;
assign ENET1_SOF_TX = 0;
assign ENET1_GMII_TXD = 0;
always@(ENET1_GMII_COL or ENET1_GMII_CRS or ENET1_EXT_INTIN or
ENET1_GMII_RX_CLK or ENET1_GMII_RX_DV or ENET1_GMII_RX_ER or
ENET1_GMII_TX_CLK or ENET1_MDIO_I or ENET1_GMII_RXD)
begin
if(ENET1_GMII_COL | ENET1_GMII_CRS | ENET1_EXT_INTIN |
ENET1_GMII_RX_CLK | ENET1_GMII_RX_DV | ENET1_GMII_RX_ER |
ENET1_GMII_TX_CLK | ENET1_MDIO_I )
$display("[%0d] : %0s : ETHERNET Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* GPIO */
/* ------------------------------------------- */
assign GPIO_O = 0;
assign GPIO_T = 0;
always@(GPIO_I)
begin
if(GPIO_I !== 0)
$display("[%0d] : %0s : GPIO Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* I2C */
/* ------------------------------------------- */
assign I2C0_SDA_O = 0;
assign I2C0_SDA_T = 0;
assign I2C0_SCL_O = 0;
assign I2C0_SCL_T = 0;
assign I2C1_SDA_O = 0;
assign I2C1_SDA_T = 0;
assign I2C1_SCL_O = 0;
assign I2C1_SCL_T = 0;
always@(I2C0_SDA_I or I2C0_SCL_I or I2C1_SDA_I or I2C1_SCL_I )
begin
if(I2C0_SDA_I | I2C0_SCL_I | I2C1_SDA_I | I2C1_SCL_I)
$display("[%0d] : %0s : I2C Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* JTAG */
/* ------------------------------------------- */
assign PJTAG_TD_T = 0;
assign PJTAG_TD_O = 0;
always@(PJTAG_TCK or PJTAG_TMS or PJTAG_TD_I)
begin
if(PJTAG_TCK | PJTAG_TMS | PJTAG_TD_I)
$display("[%0d] : %0s : JTAG Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* SDIO */
/* ------------------------------------------- */
assign SDIO0_CLK = 0;
assign SDIO0_CMD_O = 0;
assign SDIO0_CMD_T = 0;
assign SDIO0_DATA_O = 0;
assign SDIO0_DATA_T = 0;
assign SDIO0_LED = 0;
assign SDIO0_BUSPOW = 0;
assign SDIO0_BUSVOLT = 0;
always@(SDIO0_CLK_FB or SDIO0_CMD_I or SDIO0_DATA_I or SDIO0_CDN or SDIO0_WP )
begin
if(SDIO0_CLK_FB | SDIO0_CMD_I | SDIO0_CDN | SDIO0_WP )
$display("[%0d] : %0s : SDIO Interface is not supported.",$time, DISP_ERR);
end
assign SDIO1_CLK = 0;
assign SDIO1_CMD_O = 0;
assign SDIO1_CMD_T = 0;
assign SDIO1_DATA_O = 0;
assign SDIO1_DATA_T = 0;
assign SDIO1_LED = 0;
assign SDIO1_BUSPOW = 0;
assign SDIO1_BUSVOLT = 0;
always@(SDIO1_CLK_FB or SDIO1_CMD_I or SDIO1_DATA_I or SDIO1_CDN or SDIO1_WP )
begin
if(SDIO1_CLK_FB | SDIO1_CMD_I | SDIO1_CDN | SDIO1_WP )
$display("[%0d] : %0s : SDIO Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* SPI */
/* ------------------------------------------- */
assign SPI0_SCLK_O = 0;
assign SPI0_SCLK_T = 0;
assign SPI0_MOSI_O = 0;
assign SPI0_MOSI_T = 0;
assign SPI0_MISO_O = 0;
assign SPI0_MISO_T = 0;
assign SPI0_SS_O = 0; /// confirm
assign SPI0_SS1_O = 0;/// confirm
assign SPI0_SS2_O = 0;/// confirm
assign SPI0_SS_T = 0;
always@(SPI0_SCLK_I or SPI0_MOSI_I or SPI0_MISO_I or SPI0_SS_I)
begin
if(SPI0_SCLK_I | SPI0_MOSI_I | SPI0_MISO_I | SPI0_SS_I)
$display("[%0d] : %0s : SPI Interface is not supported.",$time, DISP_ERR);
end
assign SPI1_SCLK_O = 0;
assign SPI1_SCLK_T = 0;
assign SPI1_MOSI_O = 0;
assign SPI1_MOSI_T = 0;
assign SPI1_MISO_O = 0;
assign SPI1_MISO_T = 0;
assign SPI1_SS_O = 0;
assign SPI1_SS1_O = 0;
assign SPI1_SS2_O = 0;
assign SPI1_SS_T = 0;
always@(SPI1_SCLK_I or SPI1_MOSI_I or SPI1_MISO_I or SPI1_SS_I)
begin
if(SPI1_SCLK_I | SPI1_MOSI_I | SPI1_MISO_I | SPI1_SS_I)
$display("[%0d] : %0s : SPI Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* UART */
/* ------------------------------------------- */
/// confirm
assign UART0_DTRN = 0;
assign UART0_RTSN = 0;
assign UART0_TX = 0;
always@(UART0_CTSN or UART0_DCDN or UART0_DSRN or UART0_RIN or UART0_RX)
begin
if(UART0_CTSN | UART0_DCDN | UART0_DSRN | UART0_RIN | UART0_RX)
$display("[%0d] : %0s : UART Interface is not supported.",$time, DISP_ERR);
end
assign UART1_DTRN = 0;
assign UART1_RTSN = 0;
assign UART1_TX = 0;
always@(UART1_CTSN or UART1_DCDN or UART1_DSRN or UART1_RIN or UART1_RX)
begin
if(UART1_CTSN | UART1_DCDN | UART1_DSRN | UART1_RIN | UART1_RX)
$display("[%0d] : %0s : UART Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* TTC */
/* ------------------------------------------- */
assign TTC0_WAVE0_OUT = 0;
assign TTC0_WAVE1_OUT = 0;
assign TTC0_WAVE2_OUT = 0;
always@(TTC0_CLK0_IN or TTC0_CLK1_IN or TTC0_CLK2_IN)
begin
if(TTC0_CLK0_IN | TTC0_CLK1_IN | TTC0_CLK2_IN)
$display("[%0d] : %0s : TTC Interface is not supported.",$time, DISP_ERR);
end
assign TTC1_WAVE0_OUT = 0;
assign TTC1_WAVE1_OUT = 0;
assign TTC1_WAVE2_OUT = 0;
always@(TTC1_CLK0_IN or TTC1_CLK1_IN or TTC1_CLK2_IN)
begin
if(TTC1_CLK0_IN | TTC1_CLK1_IN | TTC1_CLK2_IN)
$display("[%0d] : %0s : TTC Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* WDT */
/* ------------------------------------------- */
assign WDT_RST_OUT = 0;
always@(WDT_CLK_IN)
begin
if(WDT_CLK_IN)
$display("[%0d] : %0s : WDT Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* TRACE */
/* ------------------------------------------- */
assign TRACE_CTL = 0;
assign TRACE_DATA = 0;
always@(TRACE_CLK)
begin
if(TRACE_CLK)
$display("[%0d] : %0s : TRACE Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* USB */
/* ------------------------------------------- */
assign USB0_PORT_INDCTL = 0;
assign USB0_VBUS_PWRSELECT = 0;
always@(USB0_VBUS_PWRFAULT)
begin
if(USB0_VBUS_PWRFAULT)
$display("[%0d] : %0s : USB Interface is not supported.",$time, DISP_ERR);
end
assign USB1_PORT_INDCTL = 0;
assign USB1_VBUS_PWRSELECT = 0;
always@(USB1_VBUS_PWRFAULT)
begin
if(USB1_VBUS_PWRFAULT)
$display("[%0d] : %0s : USB Interface is not supported.",$time, DISP_ERR);
end
always@(SRAM_INTIN)
begin
if(SRAM_INTIN)
$display("[%0d] : %0s : SRAM_INTIN is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* DMA */
/* ------------------------------------------- */
assign DMA0_DATYPE = 0;
assign DMA0_DAVALID = 0;
assign DMA0_DRREADY = 0;
assign DMA0_RSTN = 0;
always@(DMA0_ACLK or DMA0_DAREADY or DMA0_DRLAST or DMA0_DRVALID or DMA0_DRTYPE)
begin
if(DMA0_ACLK | DMA0_DAREADY | DMA0_DRLAST | DMA0_DRVALID | DMA0_DRTYPE)
$display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR);
end
assign DMA1_DATYPE = 0;
assign DMA1_DAVALID = 0;
assign DMA1_DRREADY = 0;
assign DMA1_RSTN = 0;
always@(DMA1_ACLK or DMA1_DAREADY or DMA1_DRLAST or DMA1_DRVALID or DMA1_DRTYPE)
begin
if(DMA1_ACLK | DMA1_DAREADY | DMA1_DRLAST | DMA1_DRVALID | DMA1_DRTYPE)
$display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR);
end
assign DMA2_DATYPE = 0;
assign DMA2_DAVALID = 0;
assign DMA2_DRREADY = 0;
assign DMA2_RSTN = 0;
always@(DMA2_ACLK or DMA2_DAREADY or DMA2_DRLAST or DMA2_DRVALID or DMA2_DRTYPE)
begin
if(DMA2_ACLK | DMA2_DAREADY | DMA2_DRLAST | DMA2_DRVALID | DMA2_DRTYPE)
$display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR);
end
assign DMA3_DATYPE = 0;
assign DMA3_DAVALID = 0;
assign DMA3_DRREADY = 0;
assign DMA3_RSTN = 0;
always@(DMA3_ACLK or DMA3_DAREADY or DMA3_DRLAST or DMA3_DRVALID or DMA3_DRTYPE)
begin
if(DMA3_ACLK | DMA3_DAREADY | DMA3_DRLAST | DMA3_DRVALID | DMA3_DRTYPE)
$display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* FTM */
/* ------------------------------------------- */
assign FTMT_F2P_TRIGACK = 0;
assign FTMT_P2F_TRIG = 0;
assign FTMT_P2F_DEBUG = 0;
always@(FTMD_TRACEIN_DATA or FTMD_TRACEIN_VALID or FTMD_TRACEIN_CLK or
FTMD_TRACEIN_ATID or FTMT_F2P_TRIG or FTMT_F2P_DEBUG or FTMT_P2F_TRIGACK)
begin
if(FTMD_TRACEIN_DATA | FTMD_TRACEIN_VALID | FTMD_TRACEIN_CLK | FTMD_TRACEIN_ATID | FTMT_F2P_TRIG | FTMT_F2P_DEBUG | FTMT_P2F_TRIGACK)
$display("[%0d] : %0s : FTM Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* EVENT */
/* ------------------------------------------- */
assign EVENT_EVENTO = 0;
assign EVENT_STANDBYWFE = 0;
assign EVENT_STANDBYWFI = 0;
always@(EVENT_EVENTI)
begin
if(EVENT_EVENTI)
$display("[%0d] : %0s : EVENT Interface is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* MIO */
/* ------------------------------------------- */
always@(MIO)
begin
if(MIO !== 0)
$display("[%0d] : %0s : MIO is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* FCLK_TRIG */
/* ------------------------------------------- */
always@(FCLK_CLKTRIG3_N or FCLK_CLKTRIG2_N or FCLK_CLKTRIG1_N or FCLK_CLKTRIG0_N )
begin
if(FCLK_CLKTRIG3_N | FCLK_CLKTRIG2_N | FCLK_CLKTRIG1_N | FCLK_CLKTRIG0_N )
$display("[%0d] : %0s : FCLK_TRIG is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* MISC */
/* ------------------------------------------- */
always@(FPGA_IDLE_N)
begin
if(FPGA_IDLE_N)
$display("[%0d] : %0s : FPGA_IDLE_N is not supported.",$time, DISP_ERR);
end
always@(DDR_ARB)
begin
if(DDR_ARB !== 0)
$display("[%0d] : %0s : DDR_ARB is not supported.",$time, DISP_ERR);
end
always@(Core0_nFIQ or Core0_nIRQ or Core1_nFIQ or Core1_nIRQ )
begin
if(Core0_nFIQ | Core0_nIRQ | Core1_nFIQ | Core1_nIRQ)
$display("[%0d] : %0s : CORE FIQ,IRQ is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* DDR */
/* ------------------------------------------- */
assign DDR_WEB = 0;
always@(DDR_Clk or DDR_CS_n)
begin
if(!DDR_CS_n)
$display("[%0d] : %0s : EXTERNAL DDR is not supported.",$time, DISP_ERR);
end
/* ------------------------------------------- */
/* IRQ_P2F */
/* ------------------------------------------- */
assign IRQ_P2F_DMAC_ABORT = 0;
assign IRQ_P2F_DMAC0 = 0;
assign IRQ_P2F_DMAC1 = 0;
assign IRQ_P2F_DMAC2 = 0;
assign IRQ_P2F_DMAC3 = 0;
assign IRQ_P2F_DMAC4 = 0;
assign IRQ_P2F_DMAC5 = 0;
assign IRQ_P2F_DMAC6 = 0;
assign IRQ_P2F_DMAC7 = 0;
assign IRQ_P2F_SMC = 0;
assign IRQ_P2F_QSPI = 0;
assign IRQ_P2F_CTI = 0;
assign IRQ_P2F_GPIO = 0;
assign IRQ_P2F_USB0 = 0;
assign IRQ_P2F_ENET0 = 0;
assign IRQ_P2F_ENET_WAKE0 = 0;
assign IRQ_P2F_SDIO0 = 0;
assign IRQ_P2F_I2C0 = 0;
assign IRQ_P2F_SPI0 = 0;
assign IRQ_P2F_UART0 = 0;
assign IRQ_P2F_CAN0 = 0;
assign IRQ_P2F_USB1 = 0;
assign IRQ_P2F_ENET1 = 0;
assign IRQ_P2F_ENET_WAKE1 = 0;
assign IRQ_P2F_SDIO1 = 0;
assign IRQ_P2F_I2C1 = 0;
assign IRQ_P2F_SPI1 = 0;
assign IRQ_P2F_UART1 = 0;
assign IRQ_P2F_CAN1 = 0;
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__PROBEC_P_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__PROBEC_P_BEHAVIORAL_PP_V
/**
* probec_p: Virtual current probe point.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__probec_p (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__PROBEC_P_BEHAVIORAL_PP_V |
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: channel_128.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Represents a RIFFA channel. Contains a RX port and a
// TX port.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module channel_128 #(
parameter C_DATA_WIDTH = 9'd128,
parameter C_MAX_READ_REQ = 2, // Max read: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
// Local parameters
parameter C_RX_FIFO_DEPTH = 1024,
parameter C_TX_FIFO_DEPTH = 512,
parameter C_SG_FIFO_DEPTH = 1024,
parameter C_DATA_WORD_WIDTH = clog2((C_DATA_WIDTH/32)+1)
)
(
input CLK,
input RST,
input [2:0] CONFIG_MAX_READ_REQUEST_SIZE, // Maximum read payload: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
input [2:0] CONFIG_MAX_PAYLOAD_SIZE, // Maximum write payload: 000=128B, 001=256B, 010=512B, 011=1024B
input [31:0] PIO_DATA, // Single word programmed I/O data
input [C_DATA_WIDTH-1:0] ENG_DATA, // Main incoming data
output SG_RX_BUF_RECVD, // Scatter gather RX buffer completely read (ready for next if applicable)
input SG_RX_BUF_LEN_VALID, // Scatter gather RX buffer length valid
input SG_RX_BUF_ADDR_HI_VALID, // Scatter gather RX buffer high address valid
input SG_RX_BUF_ADDR_LO_VALID, // Scatter gather RX buffer low address valid
output SG_TX_BUF_RECVD, // Scatter gather TX buffer completely read (ready for next if applicable)
input SG_TX_BUF_LEN_VALID, // Scatter gather TX buffer length valid
input SG_TX_BUF_ADDR_HI_VALID, // Scatter gather TX buffer high address valid
input SG_TX_BUF_ADDR_LO_VALID, // Scatter gather TX buffer low address valid
input TXN_RX_LEN_VALID, // Read transaction length valid
input TXN_RX_OFF_LAST_VALID, // Read transaction offset/last valid
output [31:0] TXN_RX_DONE_LEN, // Read transaction actual transfer length
output TXN_RX_DONE, // Read transaction done
input TXN_RX_DONE_ACK, // Read transaction actual transfer length read
output TXN_TX, // Write transaction notification
input TXN_TX_ACK, // Write transaction acknowledged
output [31:0] TXN_TX_LEN, // Write transaction length
output [31:0] TXN_TX_OFF_LAST, // Write transaction offset/last
output [31:0] TXN_TX_DONE_LEN, // Write transaction actual transfer length
output TXN_TX_DONE, // Write transaction done
input TXN_TX_DONE_ACK, // Write transaction actual transfer length read
output RX_REQ, // Read request
input RX_REQ_ACK, // Read request accepted
output [1:0] RX_REQ_TAG, // Read request data tag
output [63:0] RX_REQ_ADDR, // Read request address
output [9:0] RX_REQ_LEN, // Read request length
output TX_REQ, // Outgoing write request
input TX_REQ_ACK, // Outgoing write request acknowledged
output [63:0] TX_ADDR, // Outgoing write high address
output [9:0] TX_LEN, // Outgoing write length (in 32 bit words)
output [C_DATA_WIDTH-1:0] TX_DATA, // Outgoing write data
input TX_DATA_REN, // Outgoing write data read enable
input TX_SENT, // Outgoing write complete
input [C_DATA_WORD_WIDTH-1:0] MAIN_DATA_EN, // Main incoming data enable
input MAIN_DONE, // Main incoming data complete
input MAIN_ERR, // Main incoming data completed with error
input [C_DATA_WORD_WIDTH-1:0] SG_RX_DATA_EN, // Scatter gather for RX incoming data enable
input SG_RX_DONE, // Scatter gather for RX incoming data complete
input SG_RX_ERR, // Scatter gather for RX incoming data completed with error
input [C_DATA_WORD_WIDTH-1:0] SG_TX_DATA_EN, // Scatter gather for TX incoming data enable
input SG_TX_DONE, // Scatter gather for TX incoming data complete
input SG_TX_ERR, // Scatter gather for TX incoming data completed with error
input CHNL_RX_CLK, // Channel read clock
output CHNL_RX, // Channel read receive signal
input CHNL_RX_ACK, // Channle read received signal
output CHNL_RX_LAST, // Channel last read
output [31:0] CHNL_RX_LEN, // Channel read length
output [30:0] CHNL_RX_OFF, // Channel read offset
output [C_DATA_WIDTH-1:0] CHNL_RX_DATA, // Channel read data
output CHNL_RX_DATA_VALID, // Channel read data valid
input CHNL_RX_DATA_REN, // Channel read data has been recieved
input CHNL_TX_CLK, // Channel write clock
input CHNL_TX, // Channel write receive signal
output CHNL_TX_ACK, // Channel write acknowledgement signal
input CHNL_TX_LAST, // Channel last write
input [31:0] CHNL_TX_LEN, // Channel write length (in 32 bit words)
input [30:0] CHNL_TX_OFF, // Channel write offset
input [C_DATA_WIDTH-1:0] CHNL_TX_DATA, // Channel write data
input CHNL_TX_DATA_VALID, // Channel write data valid
output CHNL_TX_DATA_REN // Channel write data has been recieved
);
`include "functions.vh"
wire [C_DATA_WIDTH-1:0] wTxSgData;
wire wTxSgDataEmpty;
wire wTxSgDataRen;
wire wTxSgDataErr;
wire wTxSgDataRst;
// Receiving port (data to the channel)
rx_port_128 #(
.C_DATA_WIDTH(C_DATA_WIDTH),
.C_MAIN_FIFO_DEPTH(C_RX_FIFO_DEPTH),
.C_SG_FIFO_DEPTH(C_SG_FIFO_DEPTH),
.C_MAX_READ_REQ(C_MAX_READ_REQ)
) rxPort (
.RST(RST),
.CLK(CLK),
.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),
.SG_RX_BUF_RECVD(SG_RX_BUF_RECVD),
.SG_RX_BUF_DATA(PIO_DATA),
.SG_RX_BUF_LEN_VALID(SG_RX_BUF_LEN_VALID),
.SG_RX_BUF_ADDR_HI_VALID(SG_RX_BUF_ADDR_HI_VALID),
.SG_RX_BUF_ADDR_LO_VALID(SG_RX_BUF_ADDR_LO_VALID),
.SG_TX_BUF_RECVD(SG_TX_BUF_RECVD),
.SG_TX_BUF_DATA(PIO_DATA),
.SG_TX_BUF_LEN_VALID(SG_TX_BUF_LEN_VALID),
.SG_TX_BUF_ADDR_HI_VALID(SG_TX_BUF_ADDR_HI_VALID),
.SG_TX_BUF_ADDR_LO_VALID(SG_TX_BUF_ADDR_LO_VALID),
.SG_DATA(wTxSgData),
.SG_DATA_EMPTY(wTxSgDataEmpty),
.SG_DATA_REN(wTxSgDataRen),
.SG_RST(wTxSgDataRst),
.SG_ERR(wTxSgDataErr),
.TXN_DATA(PIO_DATA),
.TXN_LEN_VALID(TXN_RX_LEN_VALID),
.TXN_OFF_LAST_VALID(TXN_RX_OFF_LAST_VALID),
.TXN_DONE_LEN(TXN_RX_DONE_LEN),
.TXN_DONE(TXN_RX_DONE),
.TXN_DONE_ACK(TXN_RX_DONE_ACK),
.RX_REQ(RX_REQ),
.RX_REQ_ACK(RX_REQ_ACK),
.RX_REQ_TAG(RX_REQ_TAG),
.RX_REQ_ADDR(RX_REQ_ADDR),
.RX_REQ_LEN(RX_REQ_LEN),
.MAIN_DATA(ENG_DATA),
.MAIN_DATA_EN(MAIN_DATA_EN),
.MAIN_DONE(MAIN_DONE),
.MAIN_ERR(MAIN_ERR),
.SG_RX_DATA(ENG_DATA),
.SG_RX_DATA_EN(SG_RX_DATA_EN),
.SG_RX_DONE(SG_RX_DONE),
.SG_RX_ERR(SG_RX_ERR),
.SG_TX_DATA(ENG_DATA),
.SG_TX_DATA_EN(SG_TX_DATA_EN),
.SG_TX_DONE(SG_TX_DONE),
.SG_TX_ERR(SG_TX_ERR),
.CHNL_CLK(CHNL_RX_CLK),
.CHNL_RX(CHNL_RX),
.CHNL_RX_ACK(CHNL_RX_ACK),
.CHNL_RX_LAST(CHNL_RX_LAST),
.CHNL_RX_LEN(CHNL_RX_LEN),
.CHNL_RX_OFF(CHNL_RX_OFF),
.CHNL_RX_DATA(CHNL_RX_DATA),
.CHNL_RX_DATA_VALID(CHNL_RX_DATA_VALID),
.CHNL_RX_DATA_REN(CHNL_RX_DATA_REN)
);
// Sending port (data from the channel)
tx_port_128 #(
.C_DATA_WIDTH(C_DATA_WIDTH),
.C_FIFO_DEPTH(C_TX_FIFO_DEPTH)
) txPort (
.CLK(CLK),
.RST(RST),
.CONFIG_MAX_PAYLOAD_SIZE(CONFIG_MAX_PAYLOAD_SIZE),
.TXN(TXN_TX),
.TXN_ACK(TXN_TX_ACK),
.TXN_LEN(TXN_TX_LEN),
.TXN_OFF_LAST(TXN_TX_OFF_LAST),
.TXN_DONE_LEN(TXN_TX_DONE_LEN),
.TXN_DONE(TXN_TX_DONE),
.TXN_DONE_ACK(TXN_TX_DONE_ACK),
.SG_DATA(wTxSgData),
.SG_DATA_EMPTY(wTxSgDataEmpty),
.SG_DATA_REN(wTxSgDataRen),
.SG_RST(wTxSgDataRst),
.SG_ERR(wTxSgDataErr),
.TX_REQ(TX_REQ),
.TX_REQ_ACK(TX_REQ_ACK),
.TX_ADDR(TX_ADDR),
.TX_LEN(TX_LEN),
.TX_DATA(TX_DATA),
.TX_DATA_REN(TX_DATA_REN),
.TX_SENT(TX_SENT),
.CHNL_CLK(CHNL_TX_CLK),
.CHNL_TX(CHNL_TX),
.CHNL_TX_ACK(CHNL_TX_ACK),
.CHNL_TX_LAST(CHNL_TX_LAST),
.CHNL_TX_LEN(CHNL_TX_LEN),
.CHNL_TX_OFF(CHNL_TX_OFF),
.CHNL_TX_DATA(CHNL_TX_DATA),
.CHNL_TX_DATA_VALID(CHNL_TX_DATA_VALID),
.CHNL_TX_DATA_REN(CHNL_TX_DATA_REN)
);
endmodule
|
//----------------------------------------------------------------------------
//-- Ejemplo que saca una secuencia en los leds, usando una memoria
//-- rom de 16x4
//------------------------------------------
//-- (C) BQ. October 2015. Written by Juan Gonzalez (Obijuan)
//-- GPL license
//----------------------------------------------------------------------------
`default_nettype none
`include "divider.vh"
module romleds (input wire clk,
output wire [3:0] leds);
//- Tiempo de envio
parameter DELAY = `T_500ms; //`T_1s;
reg [3:0] addr;
reg rstn = 0;
wire clk_delay;
//-- Instanciar la memoria rom
rom16x4
ROM (
.clk(clk),
.addr(addr),
.data(leds)
);
//-- Contador
always @(negedge clk)
if (rstn == 0)
addr <= 0;
else if (clk_delay)
addr <= addr + 1;
//---------------------------
//-- Temporizador
//---------------------------
dividerp1 #(.M(DELAY))
DIV0 ( .clk(clk),
.clk_out(clk_delay)
);
//-- Inicializador
always @(negedge clk)
rstn <= 1;
endmodule
|
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * Copyright INRIA, CNRS and contributors *)
(* <O___,, * (see version control and CREDITS file for authors & dates) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
(* This file is (C) Copyright 2006-2015 Microsoft Corporation and Inria. *)
(** #<style> .doc { font-family: monospace; white-space: pre; } </style># **)
Require Import ssreflect.
(**
This file contains the basic definitions and notations for working with
functions. The definitions provide for:
- Pair projections:
p.1 == first element of a pair
p.2 == second element of a pair
These notations also apply to p : P /\ Q, via an and >-> pair coercion.
- Simplifying functions, beta-reduced by /= and simpl:
#[#fun : T => E#]# == constant function from type T that returns E
#[#fun x => E#]# == unary function
#[#fun x : T => E#]# == unary function with explicit domain type
#[#fun x y => E#]# == binary function
#[#fun x y : T => E#]# == binary function with common domain type
#[#fun (x : T) y => E#]# \
#[#fun (x : xT) (y : yT) => E#]# | == binary function with (some) explicit,
#[#fun x (y : T) => E#]# / independent domain types for each argument
- Partial functions using option type:
oapp f d ox == if ox is Some x returns f x, d otherwise
odflt d ox == if ox is Some x returns x, d otherwise
obind f ox == if ox is Some x returns f x, None otherwise
omap f ox == if ox is Some x returns Some (f x), None otherwise
- Singleton types:
all_equal_to x0 == x0 is the only value in its type, so any such value
can be rewritten to x0.
- A generic wrapper type:
wrapped T == the inductive type with values Wrap x for x : T.
unwrap w == the projection of w : wrapped T on T.
wrap x == the canonical injection of x : T into wrapped T; it is
equivalent to Wrap x, but is declared as a (default)
Canonical Structure, which lets the Coq HO unification
automatically expand x into unwrap (wrap x). The delta
reduction of wrap x to Wrap can be exploited to
introduce controlled nondeterminism in Canonical
Structure inference, as in the implementation of
the mxdirect predicate in matrix.v.
- The empty type:
void == a notation for the Empty_set type of the standard library.
of_void T == the canonical injection void -> T.
- Sigma types:
tag w == the i of w : {i : I & T i}.
tagged w == the T i component of w : {i : I & T i}.
Tagged T x == the {i : I & T i} with component x : T i.
tag2 w == the i of w : {i : I & T i & U i}.
tagged2 w == the T i component of w : {i : I & T i & U i}.
tagged2' w == the U i component of w : {i : I & T i & U i}.
Tagged2 T U x y == the {i : I & T i} with components x : T i and y : U i.
sval u == the x of u : {x : T | P x}.
s2val u == the x of u : {x : T | P x & Q x}.
The properties of sval u, s2val u are given by lemmas svalP, s2valP, and
s2valP'. We provide coercions sigT2 >-> sigT and sig2 >-> sig >-> sigT.
A suite of lemmas (all_sig, ...) let us skolemize sig, sig2, sigT, sigT2
and pair, e.g.,
have /all_sig#[#f fP#]# (x : T): {y : U | P y} by ...
yields an f : T -> U such that fP : forall x, P (f x).
- Identity functions:
id == NOTATION for the explicit identity function fun x => x.
@id T == notation for the explicit identity at type T.
idfun == an expression with a head constant, convertible to id;
idfun x simplifies to x.
@idfun T == the expression above, specialized to type T.
phant_id x y == the function type phantom _ x -> phantom _ y.
*** In addition to their casual use in functional programming, identity
functions are often used to trigger static unification as part of the
construction of dependent Records and Structures. For example, if we need
a structure sT over a type T, we take as arguments T, sT, and a "dummy"
function T -> sort sT:
Definition foo T sT & T -> sort sT := ...
We can avoid specifying sT directly by calling foo (@id T), or specify
the call completely while still ensuring the consistency of T and sT, by
calling @foo T sT idfun. The phant_id type allows us to extend this trick
to non-Type canonical projections. It also allows us to sidestep
dependent type constraints when building explicit records, e.g., given
Record r := R {x; y : T(x)}.
if we need to build an r from a given y0 while inferring some x0, such
that y0 : T(x0), we pose
Definition mk_r .. y .. (x := ...) y' & phant_id y y' := R x y'.
Calling @mk_r .. y0 .. id will cause Coq to use y' := y0, while checking
the dependent type constraint y0 : T(x0).
- Extensional equality for functions and relations (i.e. functions of two
arguments):
f1 =1 f2 == f1 x is equal to f2 x for all x.
f1 =1 f2 :> A == ... and f2 is explicitly typed.
f1 =2 f2 == f1 x y is equal to f2 x y for all x y.
f1 =2 f2 :> A == ... and f2 is explicitly typed.
- Composition for total and partial functions:
f^~ y == function f with second argument specialised to y,
i.e., fun x => f x y
CAVEAT: conditional (non-maximal) implicit arguments
of f are NOT inserted in this context
@^~ x == application at x, i.e., fun f => f x
#[#eta f#]# == the explicit eta-expansion of f, i.e., fun x => f x
CAVEAT: conditional (non-maximal) implicit arguments
of f are NOT inserted in this context.
fun=> v := the constant function fun _ => v.
f1 \o f2 == composition of f1 and f2.
Note: (f1 \o f2) x simplifies to f1 (f2 x).
f1 \; f2 == categorical composition of f1 and f2. This expands to
to f2 \o f1 and (f1 \; f2) x simplifies to f2 (f1 x).
pcomp f1 f2 == composition of partial functions f1 and f2.
- Properties of functions:
injective f <-> f is injective.
cancel f g <-> g is a left inverse of f / f is a right inverse of g.
pcancel f g <-> g is a left inverse of f where g is partial.
ocancel f g <-> g is a left inverse of f where f is partial.
bijective f <-> f is bijective (has a left and right inverse).
involutive f <-> f is involutive.
- Properties for operations.
left_id e op <-> e is a left identity for op (e op x = x).
right_id e op <-> e is a right identity for op (x op e = x).
left_inverse e inv op <-> inv is a left inverse for op wrt identity e,
i.e., (inv x) op x = e.
right_inverse e inv op <-> inv is a right inverse for op wrt identity e
i.e., x op (i x) = e.
self_inverse e op <-> each x is its own op-inverse (x op x = e).
idempotent op <-> op is idempotent for op (x op x = x).
associative op <-> op is associative, i.e.,
x op (y op z) = (x op y) op z.
commutative op <-> op is commutative (x op y = y op x).
left_commutative op <-> op is left commutative, i.e.,
x op (y op z) = y op (x op z).
right_commutative op <-> op is right commutative, i.e.,
(x op y) op z = (x op z) op y.
left_zero z op <-> z is a left zero for op (z op x = z).
right_zero z op <-> z is a right zero for op (x op z = z).
left_distributive op1 op2 <-> op1 distributes over op2 to the left:
(x op2 y) op1 z = (x op1 z) op2 (y op1 z).
right_distributive op1 op2 <-> op distributes over add to the right:
x op1 (y op2 z) = (x op1 z) op2 (x op1 z).
interchange op1 op2 <-> op1 and op2 satisfy an interchange law:
(x op2 y) op1 (z op2 t) = (x op1 z) op2 (y op1 t).
Note that interchange op op is a commutativity property.
left_injective op <-> op is injective in its left argument:
x op y = z op y -> x = z.
right_injective op <-> op is injective in its right argument:
x op y = x op z -> y = z.
left_loop inv op <-> op, inv obey the inverse loop left axiom:
(inv x) op (x op y) = y for all x, y, i.e.,
op (inv x) is always a left inverse of op x
rev_left_loop inv op <-> op, inv obey the inverse loop reverse left
axiom: x op ((inv x) op y) = y, for all x, y.
right_loop inv op <-> op, inv obey the inverse loop right axiom:
(x op y) op (inv y) = x for all x, y.
rev_right_loop inv op <-> op, inv obey the inverse loop reverse right
axiom: (x op (inv y)) op y = x for all x, y.
Note that familiar "cancellation" identities like x + y - y = x or
x - y + y = x are respectively instances of right_loop and rev_right_loop
The corresponding lemmas will use the K and NK/VK suffixes, respectively.
- Morphisms for functions and relations:
{morph f : x / a >-> r} <-> f is a morphism with respect to functions
(fun x => a) and (fun x => r); if r == R#[#x#]#,
this states that f a = R#[#f x#]# for all x.
{morph f : x / a} <-> f is a morphism with respect to the
function expression (fun x => a). This is
shorthand for {morph f : x / a >-> a}; note
that the two instances of a are often
interpreted at different types.
{morph f : x y / a >-> r} <-> f is a morphism with respect to functions
(fun x y => a) and (fun x y => r).
{morph f : x y / a} <-> f is a morphism with respect to the
function expression (fun x y => a).
{homo f : x / a >-> r} <-> f is a homomorphism with respect to the
predicates (fun x => a) and (fun x => r);
if r == R#[#x#]#, this states that a -> R#[#f x#]#
for all x.
{homo f : x / a} <-> f is a homomorphism with respect to the
predicate expression (fun x => a).
{homo f : x y / a >-> r} <-> f is a homomorphism with respect to the
relations (fun x y => a) and (fun x y => r).
{homo f : x y / a} <-> f is a homomorphism with respect to the
relation expression (fun x y => a).
{mono f : x / a >-> r} <-> f is monotone with respect to projectors
(fun x => a) and (fun x => r); if r == R#[#x#]#,
this states that R#[#f x#]# = a for all x.
{mono f : x / a} <-> f is monotone with respect to the projector
expression (fun x => a).
{mono f : x y / a >-> r} <-> f is monotone with respect to relators
(fun x y => a) and (fun x y => r).
{mono f : x y / a} <-> f is monotone with respect to the relator
expression (fun x y => a).
The file also contains some basic lemmas for the above concepts.
Lemmas relative to cancellation laws use some abbreviated suffixes:
K - a cancellation rule like esymK : cancel (@esym T x y) (@esym T y x).
LR - a lemma moving an operation from the left hand side of a relation to
the right hand side, like canLR: cancel g f -> x = g y -> f x = y.
RL - a lemma moving an operation from the right to the left, e.g., canRL.
Beware that the LR and RL orientations refer to an "apply" (back chaining)
usage; when using the same lemmas with "have" or "move" (forward chaining)
the directions will be reversed!. **)
Set Implicit Arguments.
Unset Strict Implicit.
Unset Printing Implicit Defensive.
(** Parsing / printing declarations. *)
Reserved Notation "p .1" (at level 2, left associativity, format "p .1").
Reserved Notation "p .2" (at level 2, left associativity, format "p .2").
Reserved Notation "f ^~ y" (at level 10, y at level 8, no associativity,
format "f ^~ y").
Reserved Notation "@^~ x" (at level 10, x at level 8, no associativity,
format "@^~ x").
Reserved Notation "[ 'eta' f ]" (at level 0, format "[ 'eta' f ]").
Reserved Notation "'fun' => E" (at level 200, format "'fun' => E").
Reserved Notation "[ 'fun' : T => E ]" (at level 0,
format "'[hv' [ 'fun' : T => '/ ' E ] ']'").
Reserved Notation "[ 'fun' x => E ]" (at level 0,
x name, format "'[hv' [ 'fun' x => '/ ' E ] ']'").
Reserved Notation "[ 'fun' x : T => E ]" (at level 0,
x name, format "'[hv' [ 'fun' x : T => '/ ' E ] ']'").
Reserved Notation "[ 'fun' x y => E ]" (at level 0,
x name, y name, format "'[hv' [ 'fun' x y => '/ ' E ] ']'").
Reserved Notation "[ 'fun' x y : T => E ]" (at level 0,
x name, y name, format "'[hv' [ 'fun' x y : T => '/ ' E ] ']'").
Reserved Notation "[ 'fun' ( x : T ) y => E ]" (at level 0,
x name, y name, format "'[hv' [ 'fun' ( x : T ) y => '/ ' E ] ']'").
Reserved Notation "[ 'fun' x ( y : T ) => E ]" (at level 0,
x name, y name, format "'[hv' [ 'fun' x ( y : T ) => '/ ' E ] ']'").
Reserved Notation "[ 'fun' ( x : T ) ( y : U ) => E ]" (at level 0,
x name, y name, format "[ 'fun' ( x : T ) ( y : U ) => E ]" ).
Reserved Notation "f =1 g" (at level 70, no associativity).
Reserved Notation "f =1 g :> A" (at level 70, g at next level, A at level 90).
Reserved Notation "f =2 g" (at level 70, no associativity).
Reserved Notation "f =2 g :> A" (at level 70, g at next level, A at level 90).
Reserved Notation "f \o g" (at level 50, format "f \o '/ ' g").
Reserved Notation "f \; g" (at level 60, right associativity,
format "f \; '/ ' g").
Reserved Notation "{ 'morph' f : x / a >-> r }" (at level 0, f at level 99,
x name, format "{ 'morph' f : x / a >-> r }").
Reserved Notation "{ 'morph' f : x / a }" (at level 0, f at level 99,
x name, format "{ 'morph' f : x / a }").
Reserved Notation "{ 'morph' f : x y / a >-> r }" (at level 0, f at level 99,
x name, y name, format "{ 'morph' f : x y / a >-> r }").
Reserved Notation "{ 'morph' f : x y / a }" (at level 0, f at level 99,
x name, y name, format "{ 'morph' f : x y / a }").
Reserved Notation "{ 'homo' f : x / a >-> r }" (at level 0, f at level 99,
x name, format "{ 'homo' f : x / a >-> r }").
Reserved Notation "{ 'homo' f : x / a }" (at level 0, f at level 99,
x name, format "{ 'homo' f : x / a }").
Reserved Notation "{ 'homo' f : x y / a >-> r }" (at level 0, f at level 99,
x name, y name, format "{ 'homo' f : x y / a >-> r }").
Reserved Notation "{ 'homo' f : x y / a }" (at level 0, f at level 99,
x name, y name, format "{ 'homo' f : x y / a }").
Reserved Notation "{ 'homo' f : x y /~ a }" (at level 0, f at level 99,
x name, y name, format "{ 'homo' f : x y /~ a }").
Reserved Notation "{ 'mono' f : x / a >-> r }" (at level 0, f at level 99,
x name, format "{ 'mono' f : x / a >-> r }").
Reserved Notation "{ 'mono' f : x / a }" (at level 0, f at level 99,
x name, format "{ 'mono' f : x / a }").
Reserved Notation "{ 'mono' f : x y / a >-> r }" (at level 0, f at level 99,
x name, y name, format "{ 'mono' f : x y / a >-> r }").
Reserved Notation "{ 'mono' f : x y / a }" (at level 0, f at level 99,
x name, y name, format "{ 'mono' f : x y / a }").
Reserved Notation "{ 'mono' f : x y /~ a }" (at level 0, f at level 99,
x name, y name, format "{ 'mono' f : x y /~ a }").
Reserved Notation "@ 'id' T" (at level 10, T at level 8, format "@ 'id' T").
Reserved Notation "@ 'sval'" (at level 10, format "@ 'sval'").
(**
Syntax for defining auxiliary recursive function.
Usage:
Section FooDefinition.
Variables (g1 : T1) (g2 : T2). (globals)
Fixoint foo_auxiliary (a3 : T3) ... :=
body, using #[#rec e3, ... #]# for recursive calls
where " #[# 'rec' a3 , a4 , ... #]#" := foo_auxiliary.
Definition foo x y .. := #[#rec e1, ... #]#.
+ proofs about foo
End FooDefinition. **)
Reserved Notation "[ 'rec' a ]" (at level 0,
format "[ 'rec' a ]").
Reserved Notation "[ 'rec' a , b ]" (at level 0,
format "[ 'rec' a , b ]").
Reserved Notation "[ 'rec' a , b , c ]" (at level 0,
format "[ 'rec' a , b , c ]").
Reserved Notation "[ 'rec' a , b , c , d ]" (at level 0,
format "[ 'rec' a , b , c , d ]").
Reserved Notation "[ 'rec' a , b , c , d , e ]" (at level 0,
format "[ 'rec' a , b , c , d , e ]").
Reserved Notation "[ 'rec' a , b , c , d , e , f ]" (at level 0,
format "[ 'rec' a , b , c , d , e , f ]").
Reserved Notation "[ 'rec' a , b , c , d , e , f , g ]" (at level 0,
format "[ 'rec' a , b , c , d , e , f , g ]").
Reserved Notation "[ 'rec' a , b , c , d , e , f , g , h ]" (at level 0,
format "[ 'rec' a , b , c , d , e , f , g , h ]").
Reserved Notation "[ 'rec' a , b , c , d , e , f , g , h , i ]" (at level 0,
format "[ 'rec' a , b , c , d , e , f , g , h , i ]").
Reserved Notation "[ 'rec' a , b , c , d , e , f , g , h , i , j ]" (at level 0,
format "[ 'rec' a , b , c , d , e , f , g , h , i , j ]").
Declare Scope pair_scope.
Delimit Scope pair_scope with PAIR.
Open Scope pair_scope.
(** Notations for pair/conjunction projections **)
Notation "p .1" := (fst p) : pair_scope.
Notation "p .2" := (snd p) : pair_scope.
Coercion pair_of_and P Q (PandQ : P /\ Q) := (proj1 PandQ, proj2 PandQ).
Definition all_pair I T U (w : forall i : I, T i * U i) :=
(fun i => (w i).1, fun i => (w i).2).
(**
Complements on the option type constructor, used below to
encode partial functions. **)
Module Option.
Definition apply aT rT (f : aT -> rT) x u := if u is Some y then f y else x.
Definition default T := apply (fun x : T => x).
Definition bind aT rT (f : aT -> option rT) := apply f None.
Definition map aT rT (f : aT -> rT) := bind (fun x => Some (f x)).
End Option.
Notation oapp := Option.apply.
Notation odflt := Option.default.
Notation obind := Option.bind.
Notation omap := Option.map.
Notation some := (@Some _) (only parsing).
(** Shorthand for some basic equality lemmas. **)
Notation erefl := refl_equal.
Notation ecast i T e x := (let: erefl in _ = i := e return T in x).
Definition esym := sym_eq.
Definition nesym := sym_not_eq.
Definition etrans := trans_eq.
Definition congr1 := f_equal.
Definition congr2 := f_equal2.
(** Force at least one implicit when used as a view. **)
Prenex Implicits esym nesym.
(** A predicate for singleton types. **)
Definition all_equal_to T (x0 : T) := forall x, unkeyed x = x0.
Lemma unitE : all_equal_to tt. Proof. by case. Qed.
(** A generic wrapper type **)
#[universes(template)]
Structure wrapped T := Wrap {unwrap : T}.
Canonical wrap T x := @Wrap T x.
Prenex Implicits unwrap wrap Wrap.
Declare Scope fun_scope.
Delimit Scope fun_scope with FUN.
Open Scope fun_scope.
(** Notations for argument transpose **)
Notation "f ^~ y" := (fun x => f x y) : fun_scope.
Notation "@^~ x" := (fun f => f x) : fun_scope.
(**
Definitions and notation for explicit functions with simplification,
i.e., which simpl and /= beta expand (this is complementary to nosimpl). **)
#[universes(template)]
Variant simpl_fun (aT rT : Type) := SimplFun of aT -> rT.
Section SimplFun.
Variables aT rT : Type.
Definition fun_of_simpl (f : simpl_fun aT rT) := fun x => let: SimplFun lam := f in lam x.
End SimplFun.
Coercion fun_of_simpl : simpl_fun >-> Funclass.
Notation "[ 'fun' : T => E ]" := (SimplFun (fun _ : T => E)) : fun_scope.
Notation "[ 'fun' x => E ]" := (SimplFun (fun x => E)) : fun_scope.
Notation "[ 'fun' x y => E ]" := (fun x => [fun y => E]) : fun_scope.
Notation "[ 'fun' x : T => E ]" := (SimplFun (fun x : T => E))
(only parsing) : fun_scope.
Notation "[ 'fun' x y : T => E ]" := (fun x : T => [fun y : T => E])
(only parsing) : fun_scope.
Notation "[ 'fun' ( x : T ) y => E ]" := (fun x : T => [fun y => E])
(only parsing) : fun_scope.
Notation "[ 'fun' x ( y : T ) => E ]" := (fun x => [fun y : T => E])
(only parsing) : fun_scope.
Notation "[ 'fun' ( x : T ) ( y : U ) => E ]" := (fun x : T => [fun y : U => E])
(only parsing) : fun_scope.
(** For delta functions in eqtype.v. **)
Definition SimplFunDelta aT rT (f : aT -> aT -> rT) := [fun z => f z z].
(**
Extensional equality, for unary and binary functions, including syntactic
sugar. **)
Section ExtensionalEquality.
Variables A B C : Type.
Definition eqfun (f g : B -> A) : Prop := forall x, f x = g x.
Definition eqrel (r s : C -> B -> A) : Prop := forall x y, r x y = s x y.
Lemma frefl f : eqfun f f. Proof. by []. Qed.
Lemma fsym f g : eqfun f g -> eqfun g f. Proof. by move=> eq_fg x. Qed.
Lemma ftrans f g h : eqfun f g -> eqfun g h -> eqfun f h.
Proof. by move=> eq_fg eq_gh x; rewrite eq_fg. Qed.
Lemma rrefl r : eqrel r r. Proof. by []. Qed.
End ExtensionalEquality.
Typeclasses Opaque eqfun.
Typeclasses Opaque eqrel.
#[global]
Hint Resolve frefl rrefl : core.
Notation "f1 =1 f2" := (eqfun f1 f2) : fun_scope.
Notation "f1 =1 f2 :> A" := (f1 =1 (f2 : A)) : fun_scope.
Notation "f1 =2 f2" := (eqrel f1 f2) : fun_scope.
Notation "f1 =2 f2 :> A" := (f1 =2 (f2 : A)) : fun_scope.
Section Composition.
Variables A B C : Type.
Definition comp (f : B -> A) (g : C -> B) x := f (g x).
Definition catcomp g f := comp f g.
Definition pcomp (f : B -> option A) (g : C -> option B) x := obind f (g x).
Lemma eq_comp f f' g g' : f =1 f' -> g =1 g' -> comp f g =1 comp f' g'.
Proof. by move=> eq_ff' eq_gg' x; rewrite /comp eq_gg' eq_ff'. Qed.
End Composition.
Arguments comp {A B C} f g x /.
Arguments catcomp {A B C} g f x /.
Notation "f1 \o f2" := (comp f1 f2) : fun_scope.
Notation "f1 \; f2" := (catcomp f1 f2) : fun_scope.
Notation "[ 'eta' f ]" := (fun x => f x) : fun_scope.
Notation "'fun' => E" := (fun _ => E) : fun_scope.
Notation id := (fun x => x).
Notation "@ 'id' T" := (fun x : T => x) (only parsing) : fun_scope.
Definition idfun T x : T := x.
Arguments idfun {T} x /.
Definition phant_id T1 T2 v1 v2 := phantom T1 v1 -> phantom T2 v2.
(** The empty type. **)
Notation void := Empty_set.
Definition of_void T (x : void) : T := match x with end.
(** Strong sigma types. **)
Section Tag.
Variables (I : Type) (i : I) (T_ U_ : I -> Type).
Definition tag := projT1.
Definition tagged : forall w, T_(tag w) := @projT2 I [eta T_].
Definition Tagged x := @existT I [eta T_] i x.
Definition tag2 (w : @sigT2 I T_ U_) := let: existT2 _ _ i _ _ := w in i.
Definition tagged2 w : T_(tag2 w) := let: existT2 _ _ _ x _ := w in x.
Definition tagged2' w : U_(tag2 w) := let: existT2 _ _ _ _ y := w in y.
Definition Tagged2 x y := @existT2 I [eta T_] [eta U_] i x y.
End Tag.
Arguments Tagged [I i].
Arguments Tagged2 [I i].
Prenex Implicits tag tagged Tagged tag2 tagged2 tagged2' Tagged2.
Coercion tag_of_tag2 I T_ U_ (w : @sigT2 I T_ U_) :=
Tagged (fun i => T_ i * U_ i)%type (tagged2 w, tagged2' w).
Lemma all_tag I T U :
(forall x : I, {y : T x & U x y}) ->
{f : forall x, T x & forall x, U x (f x)}.
Proof. by move=> fP; exists (fun x => tag (fP x)) => x; case: (fP x). Qed.
Lemma all_tag2 I T U V :
(forall i : I, {y : T i & U i y & V i y}) ->
{f : forall i, T i & forall i, U i (f i) & forall i, V i (f i)}.
Proof. by case/all_tag=> f /all_pair[]; exists f. Qed.
(** Refinement types. **)
(** Prenex Implicits and renaming. **)
Notation sval := (@proj1_sig _ _).
Notation "@ 'sval'" := (@proj1_sig) (at level 10, format "@ 'sval'").
Section Sig.
Variables (T : Type) (P Q : T -> Prop).
Lemma svalP (u : sig P) : P (sval u). Proof. by case: u. Qed.
Definition s2val (u : sig2 P Q) := let: exist2 _ _ x _ _ := u in x.
Lemma s2valP u : P (s2val u). Proof. by case: u. Qed.
Lemma s2valP' u : Q (s2val u). Proof. by case: u. Qed.
End Sig.
Prenex Implicits svalP s2val s2valP s2valP'.
Coercion tag_of_sig I P (u : @sig I P) := Tagged P (svalP u).
Coercion sig_of_sig2 I P Q (u : @sig2 I P Q) :=
exist (fun i => P i /\ Q i) (s2val u) (conj (s2valP u) (s2valP' u)).
Lemma all_sig I T P :
(forall x : I, {y : T x | P x y}) ->
{f : forall x, T x | forall x, P x (f x)}.
Proof. by case/all_tag=> f; exists f. Qed.
Lemma all_sig2 I T P Q :
(forall x : I, {y : T x | P x y & Q x y}) ->
{f : forall x, T x | forall x, P x (f x) & forall x, Q x (f x)}.
Proof. by case/all_sig=> f /all_pair[]; exists f. Qed.
Section Morphism.
Variables (aT rT sT : Type) (f : aT -> rT).
(** Morphism property for unary and binary functions **)
Definition morphism_1 aF rF := forall x, f (aF x) = rF (f x).
Definition morphism_2 aOp rOp := forall x y, f (aOp x y) = rOp (f x) (f y).
(** Homomorphism property for unary and binary relations **)
Definition homomorphism_1 (aP rP : _ -> Prop) := forall x, aP x -> rP (f x).
Definition homomorphism_2 (aR rR : _ -> _ -> Prop) :=
forall x y, aR x y -> rR (f x) (f y).
(** Stability property for unary and binary relations **)
Definition monomorphism_1 (aP rP : _ -> sT) := forall x, rP (f x) = aP x.
Definition monomorphism_2 (aR rR : _ -> _ -> sT) :=
forall x y, rR (f x) (f y) = aR x y.
End Morphism.
Notation "{ 'morph' f : x / a >-> r }" :=
(morphism_1 f (fun x => a) (fun x => r)) : type_scope.
Notation "{ 'morph' f : x / a }" :=
(morphism_1 f (fun x => a) (fun x => a)) : type_scope.
Notation "{ 'morph' f : x y / a >-> r }" :=
(morphism_2 f (fun x y => a) (fun x y => r)) : type_scope.
Notation "{ 'morph' f : x y / a }" :=
(morphism_2 f (fun x y => a) (fun x y => a)) : type_scope.
Notation "{ 'homo' f : x / a >-> r }" :=
(homomorphism_1 f (fun x => a) (fun x => r)) : type_scope.
Notation "{ 'homo' f : x / a }" :=
(homomorphism_1 f (fun x => a) (fun x => a)) : type_scope.
Notation "{ 'homo' f : x y / a >-> r }" :=
(homomorphism_2 f (fun x y => a) (fun x y => r)) : type_scope.
Notation "{ 'homo' f : x y / a }" :=
(homomorphism_2 f (fun x y => a) (fun x y => a)) : type_scope.
Notation "{ 'homo' f : x y /~ a }" :=
(homomorphism_2 f (fun y x => a) (fun x y => a)) : type_scope.
Notation "{ 'mono' f : x / a >-> r }" :=
(monomorphism_1 f (fun x => a) (fun x => r)) : type_scope.
Notation "{ 'mono' f : x / a }" :=
(monomorphism_1 f (fun x => a) (fun x => a)) : type_scope.
Notation "{ 'mono' f : x y / a >-> r }" :=
(monomorphism_2 f (fun x y => a) (fun x y => r)) : type_scope.
Notation "{ 'mono' f : x y / a }" :=
(monomorphism_2 f (fun x y => a) (fun x y => a)) : type_scope.
Notation "{ 'mono' f : x y /~ a }" :=
(monomorphism_2 f (fun y x => a) (fun x y => a)) : type_scope.
(**
In an intuitionistic setting, we have two degrees of injectivity. The
weaker one gives only simplification, and the strong one provides a left
inverse (we show in `fintype' that they coincide for finite types).
We also define an intermediate version where the left inverse is only a
partial function. **)
Section Injections.
Variables (rT aT : Type) (f : aT -> rT).
Definition injective := forall x1 x2, f x1 = f x2 -> x1 = x2.
Definition cancel g := forall x, g (f x) = x.
Definition pcancel g := forall x, g (f x) = Some x.
Definition ocancel (g : aT -> option rT) h := forall x, oapp h x (g x) = x.
Lemma can_pcan g : cancel g -> pcancel (fun y => Some (g y)).
Proof. by move=> fK x; congr (Some _). Qed.
Lemma pcan_inj g : pcancel g -> injective.
Proof. by move=> fK x y /(congr1 g); rewrite !fK => [[]]. Qed.
Lemma can_inj g : cancel g -> injective.
Proof. by move/can_pcan; apply: pcan_inj. Qed.
Lemma canLR g x y : cancel g -> x = f y -> g x = y.
Proof. by move=> fK ->. Qed.
Lemma canRL g x y : cancel g -> f x = y -> x = g y.
Proof. by move=> fK <-. Qed.
End Injections.
Lemma Some_inj {T : nonPropType} : injective (@Some T).
Proof. by move=> x y []. Qed.
Lemma of_voidK T : pcancel (of_void T) [fun _ => None].
Proof. by case. Qed.
(** cancellation lemmas for dependent type casts. **)
Lemma esymK T x y : cancel (@esym T x y) (@esym T y x).
Proof. by case: y /. Qed.
Lemma etrans_id T x y (eqxy : x = y :> T) : etrans (erefl x) eqxy = eqxy.
Proof. by case: y / eqxy. Qed.
Section InjectionsTheory.
Variables (A B C : Type) (f g : B -> A) (h : C -> B).
Lemma inj_id : injective (@id A).
Proof. by []. Qed.
Lemma inj_can_sym f' : cancel f f' -> injective f' -> cancel f' f.
Proof. by move=> fK injf' x; apply: injf'. Qed.
Lemma inj_comp : injective f -> injective h -> injective (f \o h).
Proof. by move=> injf injh x y /injf; apply: injh. Qed.
Lemma inj_compr : injective (f \o h) -> injective h.
Proof. by move=> injfh x y /(congr1 f) /injfh. Qed.
Lemma can_comp f' h' : cancel f f' -> cancel h h' -> cancel (f \o h) (h' \o f').
Proof. by move=> fK hK x; rewrite /= fK hK. Qed.
Lemma pcan_pcomp f' h' :
pcancel f f' -> pcancel h h' -> pcancel (f \o h) (pcomp h' f').
Proof. by move=> fK hK x; rewrite /pcomp fK /= hK. Qed.
Lemma eq_inj : injective f -> f =1 g -> injective g.
Proof. by move=> injf eqfg x y; rewrite -2!eqfg; apply: injf. Qed.
Lemma eq_can f' g' : cancel f f' -> f =1 g -> f' =1 g' -> cancel g g'.
Proof. by move=> fK eqfg eqfg' x; rewrite -eqfg -eqfg'. Qed.
Lemma inj_can_eq f' : cancel f f' -> injective f' -> cancel g f' -> f =1 g.
Proof. by move=> fK injf' gK x; apply: injf'; rewrite fK. Qed.
End InjectionsTheory.
Section Bijections.
Variables (A B : Type) (f : B -> A).
Variant bijective : Prop := Bijective g of cancel f g & cancel g f.
Hypothesis bijf : bijective.
Lemma bij_inj : injective f.
Proof. by case: bijf => g fK _; apply: can_inj fK. Qed.
Lemma bij_can_sym f' : cancel f' f <-> cancel f f'.
Proof.
split=> fK; first exact: inj_can_sym fK bij_inj.
by case: bijf => h _ hK x; rewrite -[x]hK fK.
Qed.
Lemma bij_can_eq f' f'' : cancel f f' -> cancel f f'' -> f' =1 f''.
Proof.
by move=> fK fK'; apply: (inj_can_eq _ bij_inj); apply/bij_can_sym.
Qed.
End Bijections.
Section BijectionsTheory.
Variables (A B C : Type) (f : B -> A) (h : C -> B).
Lemma eq_bij : bijective f -> forall g, f =1 g -> bijective g.
Proof. by case=> f' fK f'K g eqfg; exists f'; eapply eq_can; eauto. Qed.
Lemma bij_comp : bijective f -> bijective h -> bijective (f \o h).
Proof.
by move=> [f' fK f'K] [h' hK h'K]; exists (h' \o f'); apply: can_comp; auto.
Qed.
Lemma bij_can_bij : bijective f -> forall f', cancel f f' -> bijective f'.
Proof. by move=> bijf; exists f; first by apply/(bij_can_sym bijf). Qed.
End BijectionsTheory.
Section Involutions.
Variables (A : Type) (f : A -> A).
Definition involutive := cancel f f.
Hypothesis Hf : involutive.
Lemma inv_inj : injective f. Proof. exact: can_inj Hf. Qed.
Lemma inv_bij : bijective f. Proof. by exists f. Qed.
End Involutions.
Section OperationProperties.
Variables S T R : Type.
Section SopTisR.
Implicit Type op : S -> T -> R.
Definition left_inverse e inv op := forall x, op (inv x) x = e.
Definition right_inverse e inv op := forall x, op x (inv x) = e.
Definition left_injective op := forall x, injective (op^~ x).
Definition right_injective op := forall y, injective (op y).
End SopTisR.
Section SopTisS.
Implicit Type op : S -> T -> S.
Definition right_id e op := forall x, op x e = x.
Definition left_zero z op := forall x, op z x = z.
Definition right_commutative op := forall x y z, op (op x y) z = op (op x z) y.
Definition left_distributive op add :=
forall x y z, op (add x y) z = add (op x z) (op y z).
Definition right_loop inv op := forall y, cancel (op^~ y) (op^~ (inv y)).
Definition rev_right_loop inv op := forall y, cancel (op^~ (inv y)) (op^~ y).
End SopTisS.
Section SopTisT.
Implicit Type op : S -> T -> T.
Definition left_id e op := forall x, op e x = x.
Definition right_zero z op := forall x, op x z = z.
Definition left_commutative op := forall x y z, op x (op y z) = op y (op x z).
Definition right_distributive op add :=
forall x y z, op x (add y z) = add (op x y) (op x z).
Definition left_loop inv op := forall x, cancel (op x) (op (inv x)).
Definition rev_left_loop inv op := forall x, cancel (op (inv x)) (op x).
End SopTisT.
Section SopSisT.
Implicit Type op : S -> S -> T.
Definition self_inverse e op := forall x, op x x = e.
Definition commutative op := forall x y, op x y = op y x.
End SopSisT.
Section SopSisS.
Implicit Type op : S -> S -> S.
Definition idempotent op := forall x, op x x = x.
Definition associative op := forall x y z, op x (op y z) = op (op x y) z.
Definition interchange op1 op2 :=
forall x y z t, op1 (op2 x y) (op2 z t) = op2 (op1 x z) (op1 y t).
End SopSisS.
End OperationProperties.
|
module tester();
reg clk;
reg reset;
reg [7:0] interrupts;
wire [15:0] address_bus;
wire [15:0] data_bus;
wire [15:0] led;
wire read, write, halt;
reg [1:0] counter;
always #1 clk=!clk;
initial begin
clk = 0;
reset = 1;
counter = 0;
interrupts = 0;
$dumpfile("dff.vcd");
$dumpvars;
#10 interrupts[7] = 1;
#1 interrupts[7] = 0;
#300 $finish;
end
always @ (posedge clk) begin
counter <= counter + 1;
if (&counter)
reset <= 0;
end
wire cs_diodes; assign cs_diodes = address_bus[15:12] == 4'b1001;
Diodes diodes(data_bus, led, cs_diodes, write);
wire cs_ram; assign cs_ram = !address_bus[15];
Ram ram(
.clk(clk),
.data_bus(data_bus),
.address_bus(address_bus[10:0]),
.enable(cs_ram),
.write(write),
.read(read));
Cpu cpu(
.clk(clk),
.reset(reset),
.data_bus(data_bus),
.address_bus(address_bus),
.r(read),
.w(write),
.interrupts(interrupts),
.halt(halt));
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2006 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=0;
reg [63:0] crc;
wire [65:0] outData; // From fifo of fifo.v
wire [15:0] inData = crc[15:0];
wire [1:0] inWordPtr = crc[17:16];
wire wrEn = crc[20];
wire [1:0] wrPtr = crc[33:32];
wire [1:0] rdPtr = crc[34:33];
fifo fifo (
// Outputs
.outData (outData[65:0]),
// Inputs
.clk (clk),
.inWordPtr (inWordPtr[1:0]),
.inData (inData[15:0]),
.rdPtr (rdPtr),
.wrPtr (wrPtr),
.wrEn (wrEn));
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d crc=%b q=%x\n",$time, cyc, crc, outData);
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc==90) begin
if (outData[63:0] != 64'hd9bcbc276f0984ea) $stop;
end
else if (cyc==91) begin
if (outData[63:0] != 64'hef77cd9b13a866f0) $stop;
end
else if (cyc==92) begin
if (outData[63:0] != 64'h2750cd9b13a866f0) $stop;
end
else if (cyc==93) begin
if (outData[63:0] != 64'h4ea0bc276f0984ea) $stop;
end
else if (cyc==94) begin
if (outData[63:0] != 64'h9d41bc276f0984ea) $stop;
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module fifo (/*AUTOARG*/
// Outputs
outData,
// Inputs
clk, inWordPtr, inData, wrPtr, rdPtr, wrEn
);
parameter fifoDepthLog2 = 1;
parameter fifoDepth = 1<<fifoDepthLog2;
`define PTRBITS (fifoDepthLog2+1)
`define PTRBITSM1 fifoDepthLog2
`define PTRBITSM2 (fifoDepthLog2-1)
input clk;
input [1:0] inWordPtr;
input [15:0] inData;
input [`PTRBITSM1:0] wrPtr;
input [`PTRBITSM1:0] rdPtr;
output [65:0] outData;
input wrEn;
reg [65:0] outData;
// verilator lint_off VARHIDDEN
// verilator lint_off LITENDIAN
reg [65:0] fifo[0:fifoDepth-1];
// verilator lint_on LITENDIAN
// verilator lint_on VARHIDDEN
//reg [65:0] temp;
always @(posedge clk) begin
//$write ("we=%x PT=%x ID=%x D=%x\n", wrEn, wrPtr[`PTRBITSM2:0], {1'b0,~inWordPtr,4'b0}, inData[15:0]);
if (wrEn) begin
fifo[ wrPtr[`PTRBITSM2:0] ][{1'b0,~inWordPtr,4'b0}+:16] <= inData[15:0];
// Equivelent to:
//temp = fifo[ wrPtr[`PTRBITSM2:0] ];
//temp [{1'b0,~inWordPtr,4'b0}+:16] = inData[15:0];
//fifo[ wrPtr[`PTRBITSM2:0] ] <= temp;
end
outData <= fifo[rdPtr[`PTRBITSM2:0]];
end
endmodule
|
// DESCRIPTION: Verilator: Verilog example module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
// ======================================================================
// This is intended to be a complex example of several features, please also
// see the simpler examples/make_hello_c.
module top
(
// Declare some signals so we can see how I/O works
input clk,
input fastclk,
input reset_l,
output wire [1:0] out_small,
output wire [39:0] out_quad,
output wire [69:0] out_wide,
input [1:0] in_small,
input [39:0] in_quad,
input [69:0] in_wide
);
// Connect up the outputs, using some trivial logic
assign out_small = ~reset_l ? '0 : (in_small + 2'b1);
assign out_quad = ~reset_l ? '0 : (in_quad + 40'b1);
assign out_wide = ~reset_l ? '0 : (in_wide + 70'b1);
// And an example sub module. The submodule will print stuff.
sub sub (/*AUTOINST*/
// Inputs
.clk (clk),
.fastclk (fastclk),
.reset_l (reset_l));
// Print some stuff as an example
initial begin
$display("[%0t] Model running...\n", $time);
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sparc_tlu_penc64.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: sparc_tlu_penc64
// Description:
// 64 -> 6 priority encoder
// Bit 63 has the highest priority
//
*/
module sparc_tlu_penc64 (/*AUTOARG*/
// Outputs
out,
// Inputs
in
);
input [63:0] in;
output [5:0] out;
reg [5:0] out;
integer i;
always @ (in)
begin
//
// code modified for verplex to avoid inferred latches
// if (in == 64'b0) // don't want a latch
out = 6'b0;
// else
for (i=0;i<64;i=i+1)
begin
if (in[i])
out[5:0] = i[5:0];
end
end
endmodule // sparc_tlu_penc64
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2006 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=0;
reg [63:0] crc;
reg [31:0] sum;
wire [15:0] out0;
wire [15:0] out1;
wire [15:0] inData = crc[15:0];
wire wr0a = crc[16];
wire wr0b = crc[17];
wire wr1a = crc[18];
wire wr1b = crc[19];
fifo fifo (
// Outputs
.out0 (out0[15:0]),
.out1 (out1[15:0]),
// Inputs
.clk (clk),
.wr0a (wr0a),
.wr0b (wr0b),
.wr1a (wr1a),
.wr1b (wr1b),
.inData (inData[15:0]));
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d crc=%x q=%x\n",$time, cyc, crc, sum);
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 32'h0;
end
else if (cyc>10 && cyc<90) begin
sum <= {sum[30:0],sum[31]} ^ {out1, out0};
end
else if (cyc==99) begin
if (sum !== 32'he8bbd130) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module fifo (/*AUTOARG*/
// Outputs
out0, out1,
// Inputs
clk, wr0a, wr0b, wr1a, wr1b, inData
);
input clk;
input wr0a;
input wr0b;
input wr1a;
input wr1b;
input [15:0] inData;
output [15:0] out0;
output [15:0] out1;
reg [15:0] mem [1:0];
reg [15:0] memtemp2 [1:0];
reg [15:0] memtemp3 [1:0];
assign out0 = {mem[0] ^ memtemp2[0]};
assign out1 = {mem[1] ^ memtemp3[1]};
always @(posedge clk) begin
// These mem assignments must be done in order after processing
if (wr0a) begin
memtemp2[0] <= inData;
mem[0] <= inData;
end
if (wr0b) begin
memtemp3[0] <= inData;
mem[0] <= ~inData;
end
if (wr1a) begin
memtemp3[1] <= inData;
mem[1] <= inData;
end
if (wr1b) begin
memtemp2[1] <= inData;
mem[1] <= ~inData;
end
end
endmodule
|
`include "common.vh"
`timescale 1ms/10us
module Tenyr(
input clk, reset, inout halt,
output[7:0] seg, output[3:0] an, inout[23:0] gpio,
output[2:0] vgaRed, vgaGreen, output[2:1] vgaBlue, output hsync, vsync, inframe
);
parameter RAMABITS = 13;
wire d_wen, d_stb, d_cyc, d_ack;
wire i_wen, i_stb, i_cyc, i_ack;
wire[3:0] d_sel, i_sel;
wire valid_clk, clk_vga, clk_core;
wire[31:0] i_adr;
wire[31:0] d_adr, d_to_slav, i_to_slav;
wire[31:0] d_to_mast, i_to_mast;
assign i_ack = i_stb;
tenyr_mainclock clocks(
.clk_in ( clk ), .clk_core ( clk_core ),
.reset ( reset ), .clk_vga ( clk_vga ),
.locked ( )
);
Core core(
.clk ( clk_core ),
.halt ( halt ),
.reset ( reset ),
.adr_o ( d_adr ),
.dat_o ( d_to_slav ),
.dat_i ( d_to_mast ),
.wen_o ( d_wen ),
.sel_o ( d_sel ),
.stb_o ( d_stb ),
.ack_i ( d_ack ),
.err_i ( 1'b0 ),
.rty_i ( 1'b0 ),
.cyc_o ( d_cyc )
);
// -----------------------------------------------------------------------------
// MEMORY ----------------------------------------------------------------------
wire r_wen, r_stb, r_cyc, r_ack;
wire[3:0] r_sel;
wire[31:0] r_adr, r_ddn, r_dup;
TwoPortRAM #(
.INIT(0),
.PBITS(32), .ABITS(RAMABITS), .OFFSET(`RESETVECTOR)
) ram(
.clka ( clk_core ), .clkb ( '0 ),
.ena ( r_stb ), .enb ( '0 ),
.acka ( r_ack ), .ackb ( ),
.wea ( r_wen ), .web ( '0 ),
.addra ( r_adr ), .addrb ( '0 ),
.dina ( r_ddn ), .dinb ( '0 ),
.douta ( r_dup ), .doutb ( )
);
// -----------------------------------------------------------------------------
// DEVICES ---------------------------------------------------------------------
wire s_wen, s_stb, s_cyc;
wire[3:0] s_sel;
wire[31:0] s_adr, s_ddn, s_dup;
wire s_stbcyc = s_stb & s_cyc;
`ifdef SERIAL
// TODO write a hardware-compatible serial device ; rename to eliminate `Sim`
SimWrap_simserial #(.BASE(32'h20), .SIZE(2)) serial(
.clk ( clk_core ), .reset ( reset ), .enable ( s_stbcyc ),
.rw ( s_wen ), .addr ( s_adr ), .data ( s_ddn )
);
`endif
wire g_wen, g_stb, g_cyc, g_ack;
wire[3:0] g_sel;
wire[31:0] g_adr, g_ddn, g_dup;
wire g_stbcyc = g_stb & g_cyc;
Seg7 seg7(
.clk ( clk_core ), .rw ( g_wen ), .seg ( seg ),
.reset ( reset ), .addr ( g_adr ), .an ( an ),
.strobe ( g_stbcyc ), .d_in ( g_ddn ), .d_out ( g_dup ), .ack( g_ack )
);
wire o_wen, o_stb, o_cyc;
wire[3:0] o_sel;
wire[31:0] o_adr, o_ddn, o_dup;
wire o_stbcyc = o_stb & o_cyc;
Gpio #(.COUNT(24)) gio(
.clk ( clk_core ), .rw ( o_wen ), .gpio ( gpio ),
.reset ( reset ), .addr ( o_adr ), .data_i ( o_ddn ),
.strobe ( o_stbcyc ), .data_o ( o_dup )
);
wire v_wen, v_stb, v_cyc;
wire[3:0] v_sel;
wire[31:0] v_adr, v_ddn, v_dup;
wire v_stbcyc = v_stb & v_cyc;
`ifdef VGA
VGAwrap vga(
.clk_core ( clk_core ), .rw ( v_wen ), .vgaRed ( vgaRed ),
.clk_vga ( clk_vga ), .addr ( v_adr ), .vgaGreen ( vgaGreen ),
.en ( 1'b1 ), .d_in ( v_ddn ), .vgaBlue ( vgaBlue ),
.reset ( reset ), .d_out ( v_dup ), .hsync ( hsync ),
.strobe ( v_stbcyc ), .vsync ( vsync ),
.inframe ( inframe )
);
`endif
wire x_wen, x_stb, x_cyc;
wire[3:0] x_sel;
wire[31:0] x_adr, x_ddn, x_dup;
assign x_dup = 32'hffffffff;
wb_mux #(
.num_slaves(6),
.MATCH_ADDR({
// GPIO 7-seg VGA display serial port memory default
32'h200,32'h100,`VIDEO_ADDR ,32'h00000020,`RESETVECTOR,-32'sd1 }),
.MATCH_MASK({
-32'd4 ,-32'd2 ,32'hffff0000,32'hfffffffe,32'hffffd000,-32'sd1 })
) mux (
.wb_clk_i ( clk_core ),
.wb_rst_i ( reset ),
.wbm_adr_i ( d_adr ),
.wbm_dat_i ( d_to_slav ),
.wbm_dat_o ( d_to_mast ),
.wbm_we_i ( d_wen ),
.wbm_sel_i ( d_sel ),
.wbm_stb_i ( d_stb ),
.wbm_ack_o ( d_ack ),
.wbm_err_o ( /* TODO */ ),
.wbm_rty_o ( /* TODO */ ),
.wbm_cyc_i ( d_cyc ),
// gpio 7-seg VGA serial mem def.
.wbs_adr_o ({ o_adr, g_adr, v_adr, s_adr, r_adr, x_adr }),
.wbs_dat_o ({ o_ddn, g_ddn, v_ddn, s_ddn, r_ddn, x_ddn }),
.wbs_dat_i ({ o_dup, g_dup, v_dup, s_dup, r_dup, x_dup }),
.wbs_we_o ({ o_wen, g_wen, v_wen, s_wen, r_wen, x_wen }),
.wbs_sel_o ({ o_sel, g_sel, v_sel, s_sel, r_sel, x_sel }),
.wbs_stb_o ({ o_stb, g_stb, v_stb, s_stb, r_stb, x_stb }),
.wbs_ack_i ({ o_stb, g_ack, v_stb, s_stb, r_ack, x_stb }),
.wbs_err_i ({ 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 }),
.wbs_rty_i ({ 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 }),
.wbs_cyc_o ({ o_cyc, g_cyc, v_cyc, s_cyc, r_cyc, x_cyc }),
// unused ports
.wbm_cti_i ( '0 ),
.wbm_bte_i ( '0 ),
.wbs_cti_o ( ),
.wbs_bte_o ( )
);
endmodule
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// -----------------------------------------------------------
// PLI byte transport HDL interface
//
// @author jyeap, gkwan
// -----------------------------------------------------------
`timescale 1 ns / 1 ns
module altera_pli_streaming (
clk,
reset_n,
// source out
source_valid,
source_data,
source_ready,
// sink in
sink_valid,
sink_data,
sink_ready,
// resetrequest
resetrequest
);
parameter PLI_PORT = 50000;
parameter PURPOSE = 0;
input clk;
input reset_n;
output reg source_valid;
output reg [7 : 0] source_data;
input source_ready;
input sink_valid;
input [7 : 0] sink_data;
output reg sink_ready;
output reg resetrequest;
//synthesis translate_off
reg pli_out_valid;
reg pli_in_ready;
reg [7 : 0] pli_out_data;
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
pli_out_valid <= 0;
pli_out_data <= 'b0;
pli_in_ready <= 0;
end
else begin
`ifdef MODEL_TECH
$do_transaction(
PLI_PORT,
pli_out_valid,
source_ready,
pli_out_data,
sink_valid,
pli_in_ready,
sink_data);
`endif
end
end
//synthesis translate_on
wire [7:0] jtag_source_data;
wire jtag_source_valid;
wire jtag_sink_ready;
wire jtag_resetrequest;
altera_jtag_dc_streaming #(.PURPOSE(PURPOSE)) jtag_dc_streaming (
.clk(clk),
.reset_n(reset_n),
.source_data(jtag_source_data),
.source_valid(jtag_source_valid),
.sink_data(sink_data),
.sink_valid(sink_valid),
.sink_ready(jtag_sink_ready),
.resetrequest(jtag_resetrequest)
);
always @* begin
source_valid = jtag_source_valid;
source_data = jtag_source_data;
sink_ready = jtag_sink_ready;
resetrequest = jtag_resetrequest;
//synthesis translate_off
source_valid = pli_out_valid;
source_data = pli_out_data;
sink_ready = pli_in_ready;
resetrequest = 0;
//synthesis translate_on
end
endmodule
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// hps_sdram.v
// This file was auto-generated from altera_mem_if_hps_emif_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 16.0 211
`timescale 1 ps / 1 ps
module hps_sdram (
input wire pll_ref_clk, // pll_ref_clk.clk
input wire global_reset_n, // global_reset.reset_n
input wire soft_reset_n, // soft_reset.reset_n
output wire [14:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire [0:0] mem_ck, // .mem_ck
output wire [0:0] mem_ck_n, // .mem_ck_n
output wire [0:0] mem_cke, // .mem_cke
output wire [0:0] mem_cs_n, // .mem_cs_n
output wire [3:0] mem_dm, // .mem_dm
output wire [0:0] mem_ras_n, // .mem_ras_n
output wire [0:0] mem_cas_n, // .mem_cas_n
output wire [0:0] mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [31:0] mem_dq, // .mem_dq
inout wire [3:0] mem_dqs, // .mem_dqs
inout wire [3:0] mem_dqs_n, // .mem_dqs_n
output wire [0:0] mem_odt, // .mem_odt
input wire oct_rzqin // oct.rzqin
);
wire pll_afi_clk_clk; // pll:afi_clk -> [c0:afi_clk, p0:afi_clk]
wire pll_afi_half_clk_clk; // pll:afi_half_clk -> [c0:afi_half_clk, p0:afi_half_clk]
wire [4:0] p0_afi_afi_rlat; // p0:afi_rlat -> c0:afi_rlat
wire p0_afi_afi_cal_success; // p0:afi_cal_success -> c0:afi_cal_success
wire [79:0] p0_afi_afi_rdata; // p0:afi_rdata -> c0:afi_rdata
wire [3:0] p0_afi_afi_wlat; // p0:afi_wlat -> c0:afi_wlat
wire p0_afi_afi_cal_fail; // p0:afi_cal_fail -> c0:afi_cal_fail
wire [0:0] p0_afi_afi_rdata_valid; // p0:afi_rdata_valid -> c0:afi_rdata_valid
wire p0_afi_reset_reset; // p0:afi_reset_n -> c0:afi_reset_n
wire [4:0] c0_afi_afi_rdata_en_full; // c0:afi_rdata_en_full -> p0:afi_rdata_en_full
wire [0:0] c0_afi_afi_rst_n; // c0:afi_rst_n -> p0:afi_rst_n
wire [4:0] c0_afi_afi_dqs_burst; // c0:afi_dqs_burst -> p0:afi_dqs_burst
wire [19:0] c0_afi_afi_addr; // c0:afi_addr -> p0:afi_addr
wire [9:0] c0_afi_afi_dm; // c0:afi_dm -> p0:afi_dm
wire [0:0] c0_afi_afi_mem_clk_disable; // c0:afi_mem_clk_disable -> p0:afi_mem_clk_disable
wire [0:0] c0_afi_afi_we_n; // c0:afi_we_n -> p0:afi_we_n
wire [4:0] c0_afi_afi_rdata_en; // c0:afi_rdata_en -> p0:afi_rdata_en
wire [1:0] c0_afi_afi_odt; // c0:afi_odt -> p0:afi_odt
wire [0:0] c0_afi_afi_ras_n; // c0:afi_ras_n -> p0:afi_ras_n
wire [1:0] c0_afi_afi_cke; // c0:afi_cke -> p0:afi_cke
wire [4:0] c0_afi_afi_wdata_valid; // c0:afi_wdata_valid -> p0:afi_wdata_valid
wire [79:0] c0_afi_afi_wdata; // c0:afi_wdata -> p0:afi_wdata
wire [2:0] c0_afi_afi_ba; // c0:afi_ba -> p0:afi_ba
wire [0:0] c0_afi_afi_cas_n; // c0:afi_cas_n -> p0:afi_cas_n
wire [1:0] c0_afi_afi_cs_n; // c0:afi_cs_n -> p0:afi_cs_n
wire [7:0] c0_hard_phy_cfg_cfg_tmrd; // c0:cfg_tmrd -> p0:cfg_tmrd
wire [23:0] c0_hard_phy_cfg_cfg_dramconfig; // c0:cfg_dramconfig -> p0:cfg_dramconfig
wire [7:0] c0_hard_phy_cfg_cfg_rowaddrwidth; // c0:cfg_rowaddrwidth -> p0:cfg_rowaddrwidth
wire [7:0] c0_hard_phy_cfg_cfg_devicewidth; // c0:cfg_devicewidth -> p0:cfg_devicewidth
wire [15:0] c0_hard_phy_cfg_cfg_trefi; // c0:cfg_trefi -> p0:cfg_trefi
wire [7:0] c0_hard_phy_cfg_cfg_tcl; // c0:cfg_tcl -> p0:cfg_tcl
wire [7:0] c0_hard_phy_cfg_cfg_csaddrwidth; // c0:cfg_csaddrwidth -> p0:cfg_csaddrwidth
wire [7:0] c0_hard_phy_cfg_cfg_coladdrwidth; // c0:cfg_coladdrwidth -> p0:cfg_coladdrwidth
wire [7:0] c0_hard_phy_cfg_cfg_trfc; // c0:cfg_trfc -> p0:cfg_trfc
wire [7:0] c0_hard_phy_cfg_cfg_addlat; // c0:cfg_addlat -> p0:cfg_addlat
wire [7:0] c0_hard_phy_cfg_cfg_bankaddrwidth; // c0:cfg_bankaddrwidth -> p0:cfg_bankaddrwidth
wire [7:0] c0_hard_phy_cfg_cfg_interfacewidth; // c0:cfg_interfacewidth -> p0:cfg_interfacewidth
wire [7:0] c0_hard_phy_cfg_cfg_twr; // c0:cfg_twr -> p0:cfg_twr
wire [7:0] c0_hard_phy_cfg_cfg_caswrlat; // c0:cfg_caswrlat -> p0:cfg_caswrlat
wire p0_ctl_clk_clk; // p0:ctl_clk -> c0:ctl_clk
wire p0_ctl_reset_reset; // p0:ctl_reset_n -> c0:ctl_reset_n
wire p0_io_int_io_intaficalfail; // p0:io_intaficalfail -> c0:io_intaficalfail
wire p0_io_int_io_intaficalsuccess; // p0:io_intaficalsuccess -> c0:io_intaficalsuccess
wire [15:0] oct_oct_sharing_parallelterminationcontrol; // oct:parallelterminationcontrol -> p0:parallelterminationcontrol
wire [15:0] oct_oct_sharing_seriesterminationcontrol; // oct:seriesterminationcontrol -> p0:seriesterminationcontrol
wire pll_pll_sharing_pll_write_clk; // pll:pll_write_clk -> p0:pll_write_clk
wire pll_pll_sharing_pll_avl_clk; // pll:pll_avl_clk -> p0:pll_avl_clk
wire pll_pll_sharing_pll_write_clk_pre_phy_clk; // pll:pll_write_clk_pre_phy_clk -> p0:pll_write_clk_pre_phy_clk
wire pll_pll_sharing_pll_addr_cmd_clk; // pll:pll_addr_cmd_clk -> p0:pll_addr_cmd_clk
wire pll_pll_sharing_pll_config_clk; // pll:pll_config_clk -> p0:pll_config_clk
wire pll_pll_sharing_pll_avl_phy_clk; // pll:pll_avl_phy_clk -> p0:pll_avl_phy_clk
wire pll_pll_sharing_afi_phy_clk; // pll:afi_phy_clk -> p0:afi_phy_clk
wire pll_pll_sharing_pll_mem_clk; // pll:pll_mem_clk -> p0:pll_mem_clk
wire pll_pll_sharing_pll_locked; // pll:pll_locked -> p0:pll_locked
wire pll_pll_sharing_pll_mem_phy_clk; // pll:pll_mem_phy_clk -> p0:pll_mem_phy_clk
wire p0_dll_clk_clk; // p0:dll_clk -> dll:clk
wire p0_dll_sharing_dll_pll_locked; // p0:dll_pll_locked -> dll:dll_pll_locked
wire [6:0] dll_dll_sharing_dll_delayctrl; // dll:dll_delayctrl -> p0:dll_delayctrl
hps_sdram_pll pll (
.global_reset_n (global_reset_n), // global_reset.reset_n
.pll_ref_clk (pll_ref_clk), // pll_ref_clk.clk
.afi_clk (pll_afi_clk_clk), // afi_clk.clk
.afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk
.pll_mem_clk (pll_pll_sharing_pll_mem_clk), // pll_sharing.pll_mem_clk
.pll_write_clk (pll_pll_sharing_pll_write_clk), // .pll_write_clk
.pll_locked (pll_pll_sharing_pll_locked), // .pll_locked
.pll_write_clk_pre_phy_clk (pll_pll_sharing_pll_write_clk_pre_phy_clk), // .pll_write_clk_pre_phy_clk
.pll_addr_cmd_clk (pll_pll_sharing_pll_addr_cmd_clk), // .pll_addr_cmd_clk
.pll_avl_clk (pll_pll_sharing_pll_avl_clk), // .pll_avl_clk
.pll_config_clk (pll_pll_sharing_pll_config_clk), // .pll_config_clk
.pll_mem_phy_clk (pll_pll_sharing_pll_mem_phy_clk), // .pll_mem_phy_clk
.afi_phy_clk (pll_pll_sharing_afi_phy_clk), // .afi_phy_clk
.pll_avl_phy_clk (pll_pll_sharing_pll_avl_phy_clk) // .pll_avl_phy_clk
);
hps_sdram_p0 p0 (
.global_reset_n (global_reset_n), // global_reset.reset_n
.soft_reset_n (soft_reset_n), // soft_reset.reset_n
.afi_reset_n (p0_afi_reset_reset), // afi_reset.reset_n
.afi_reset_export_n (), // afi_reset_export.reset_n
.ctl_reset_n (p0_ctl_reset_reset), // ctl_reset.reset_n
.afi_clk (pll_afi_clk_clk), // afi_clk.clk
.afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk
.ctl_clk (p0_ctl_clk_clk), // ctl_clk.clk
.avl_clk (), // avl_clk.clk
.avl_reset_n (), // avl_reset.reset_n
.scc_clk (), // scc_clk.clk
.scc_reset_n (), // scc_reset.reset_n
.avl_address (), // avl.address
.avl_write (), // .write
.avl_writedata (), // .writedata
.avl_read (), // .read
.avl_readdata (), // .readdata
.avl_waitrequest (), // .waitrequest
.dll_clk (p0_dll_clk_clk), // dll_clk.clk
.afi_addr (c0_afi_afi_addr), // afi.afi_addr
.afi_ba (c0_afi_afi_ba), // .afi_ba
.afi_cke (c0_afi_afi_cke), // .afi_cke
.afi_cs_n (c0_afi_afi_cs_n), // .afi_cs_n
.afi_ras_n (c0_afi_afi_ras_n), // .afi_ras_n
.afi_we_n (c0_afi_afi_we_n), // .afi_we_n
.afi_cas_n (c0_afi_afi_cas_n), // .afi_cas_n
.afi_rst_n (c0_afi_afi_rst_n), // .afi_rst_n
.afi_odt (c0_afi_afi_odt), // .afi_odt
.afi_dqs_burst (c0_afi_afi_dqs_burst), // .afi_dqs_burst
.afi_wdata_valid (c0_afi_afi_wdata_valid), // .afi_wdata_valid
.afi_wdata (c0_afi_afi_wdata), // .afi_wdata
.afi_dm (c0_afi_afi_dm), // .afi_dm
.afi_rdata (p0_afi_afi_rdata), // .afi_rdata
.afi_rdata_en (c0_afi_afi_rdata_en), // .afi_rdata_en
.afi_rdata_en_full (c0_afi_afi_rdata_en_full), // .afi_rdata_en_full
.afi_rdata_valid (p0_afi_afi_rdata_valid), // .afi_rdata_valid
.afi_wlat (p0_afi_afi_wlat), // .afi_wlat
.afi_rlat (p0_afi_afi_rlat), // .afi_rlat
.afi_cal_success (p0_afi_afi_cal_success), // .afi_cal_success
.afi_cal_fail (p0_afi_afi_cal_fail), // .afi_cal_fail
.scc_data (), // scc.scc_data
.scc_dqs_ena (), // .scc_dqs_ena
.scc_dqs_io_ena (), // .scc_dqs_io_ena
.scc_dq_ena (), // .scc_dq_ena
.scc_dm_ena (), // .scc_dm_ena
.capture_strobe_tracking (), // .capture_strobe_tracking
.scc_upd (), // .scc_upd
.cfg_addlat (c0_hard_phy_cfg_cfg_addlat), // hard_phy_cfg.cfg_addlat
.cfg_bankaddrwidth (c0_hard_phy_cfg_cfg_bankaddrwidth), // .cfg_bankaddrwidth
.cfg_caswrlat (c0_hard_phy_cfg_cfg_caswrlat), // .cfg_caswrlat
.cfg_coladdrwidth (c0_hard_phy_cfg_cfg_coladdrwidth), // .cfg_coladdrwidth
.cfg_csaddrwidth (c0_hard_phy_cfg_cfg_csaddrwidth), // .cfg_csaddrwidth
.cfg_devicewidth (c0_hard_phy_cfg_cfg_devicewidth), // .cfg_devicewidth
.cfg_dramconfig (c0_hard_phy_cfg_cfg_dramconfig), // .cfg_dramconfig
.cfg_interfacewidth (c0_hard_phy_cfg_cfg_interfacewidth), // .cfg_interfacewidth
.cfg_rowaddrwidth (c0_hard_phy_cfg_cfg_rowaddrwidth), // .cfg_rowaddrwidth
.cfg_tcl (c0_hard_phy_cfg_cfg_tcl), // .cfg_tcl
.cfg_tmrd (c0_hard_phy_cfg_cfg_tmrd), // .cfg_tmrd
.cfg_trefi (c0_hard_phy_cfg_cfg_trefi), // .cfg_trefi
.cfg_trfc (c0_hard_phy_cfg_cfg_trfc), // .cfg_trfc
.cfg_twr (c0_hard_phy_cfg_cfg_twr), // .cfg_twr
.afi_mem_clk_disable (c0_afi_afi_mem_clk_disable), // afi_mem_clk_disable.afi_mem_clk_disable
.pll_mem_clk (pll_pll_sharing_pll_mem_clk), // pll_sharing.pll_mem_clk
.pll_write_clk (pll_pll_sharing_pll_write_clk), // .pll_write_clk
.pll_locked (pll_pll_sharing_pll_locked), // .pll_locked
.pll_write_clk_pre_phy_clk (pll_pll_sharing_pll_write_clk_pre_phy_clk), // .pll_write_clk_pre_phy_clk
.pll_addr_cmd_clk (pll_pll_sharing_pll_addr_cmd_clk), // .pll_addr_cmd_clk
.pll_avl_clk (pll_pll_sharing_pll_avl_clk), // .pll_avl_clk
.pll_config_clk (pll_pll_sharing_pll_config_clk), // .pll_config_clk
.pll_mem_phy_clk (pll_pll_sharing_pll_mem_phy_clk), // .pll_mem_phy_clk
.afi_phy_clk (pll_pll_sharing_afi_phy_clk), // .afi_phy_clk
.pll_avl_phy_clk (pll_pll_sharing_pll_avl_phy_clk), // .pll_avl_phy_clk
.dll_pll_locked (p0_dll_sharing_dll_pll_locked), // dll_sharing.dll_pll_locked
.dll_delayctrl (dll_dll_sharing_dll_delayctrl), // .dll_delayctrl
.seriesterminationcontrol (oct_oct_sharing_seriesterminationcontrol), // oct_sharing.seriesterminationcontrol
.parallelterminationcontrol (oct_oct_sharing_parallelterminationcontrol), // .parallelterminationcontrol
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_dm (mem_dm), // .mem_dm
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.io_intaficalfail (p0_io_int_io_intaficalfail), // io_int.io_intaficalfail
.io_intaficalsuccess (p0_io_int_io_intaficalsuccess), // .io_intaficalsuccess
.csr_soft_reset_req (1'b0), // (terminated)
.io_intaddrdout (64'b0000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.io_intbadout (12'b000000000000), // (terminated)
.io_intcasndout (4'b0000), // (terminated)
.io_intckdout (4'b0000), // (terminated)
.io_intckedout (8'b00000000), // (terminated)
.io_intckndout (4'b0000), // (terminated)
.io_intcsndout (8'b00000000), // (terminated)
.io_intdmdout (20'b00000000000000000000), // (terminated)
.io_intdqdin (), // (terminated)
.io_intdqdout (180'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.io_intdqoe (90'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.io_intdqsbdout (20'b00000000000000000000), // (terminated)
.io_intdqsboe (10'b0000000000), // (terminated)
.io_intdqsdout (20'b00000000000000000000), // (terminated)
.io_intdqslogicdqsena (10'b0000000000), // (terminated)
.io_intdqslogicfiforeset (5'b00000), // (terminated)
.io_intdqslogicincrdataen (10'b0000000000), // (terminated)
.io_intdqslogicincwrptr (10'b0000000000), // (terminated)
.io_intdqslogicoct (10'b0000000000), // (terminated)
.io_intdqslogicrdatavalid (), // (terminated)
.io_intdqslogicreadlatency (25'b0000000000000000000000000), // (terminated)
.io_intdqsoe (10'b0000000000), // (terminated)
.io_intodtdout (8'b00000000), // (terminated)
.io_intrasndout (4'b0000), // (terminated)
.io_intresetndout (4'b0000), // (terminated)
.io_intwendout (4'b0000), // (terminated)
.io_intafirlat (), // (terminated)
.io_intafiwlat () // (terminated)
);
altera_mem_if_hhp_qseq_synth_top #(
.MEM_IF_DM_WIDTH (4),
.MEM_IF_DQS_WIDTH (4),
.MEM_IF_CS_WIDTH (1),
.MEM_IF_DQ_WIDTH (32)
) seq (
);
altera_mem_if_hard_memory_controller_top_cyclonev #(
.MEM_IF_DQS_WIDTH (4),
.MEM_IF_CS_WIDTH (1),
.MEM_IF_CHIP_BITS (1),
.MEM_IF_CLK_PAIR_COUNT (1),
.CSR_ADDR_WIDTH (10),
.CSR_DATA_WIDTH (8),
.CSR_BE_WIDTH (1),
.AVL_ADDR_WIDTH (27),
.AVL_DATA_WIDTH (64),
.AVL_SIZE_WIDTH (3),
.AVL_DATA_WIDTH_PORT_0 (1),
.AVL_ADDR_WIDTH_PORT_0 (1),
.AVL_NUM_SYMBOLS_PORT_0 (1),
.LSB_WFIFO_PORT_0 (5),
.MSB_WFIFO_PORT_0 (5),
.LSB_RFIFO_PORT_0 (5),
.MSB_RFIFO_PORT_0 (5),
.AVL_DATA_WIDTH_PORT_1 (1),
.AVL_ADDR_WIDTH_PORT_1 (1),
.AVL_NUM_SYMBOLS_PORT_1 (1),
.LSB_WFIFO_PORT_1 (5),
.MSB_WFIFO_PORT_1 (5),
.LSB_RFIFO_PORT_1 (5),
.MSB_RFIFO_PORT_1 (5),
.AVL_DATA_WIDTH_PORT_2 (1),
.AVL_ADDR_WIDTH_PORT_2 (1),
.AVL_NUM_SYMBOLS_PORT_2 (1),
.LSB_WFIFO_PORT_2 (5),
.MSB_WFIFO_PORT_2 (5),
.LSB_RFIFO_PORT_2 (5),
.MSB_RFIFO_PORT_2 (5),
.AVL_DATA_WIDTH_PORT_3 (1),
.AVL_ADDR_WIDTH_PORT_3 (1),
.AVL_NUM_SYMBOLS_PORT_3 (1),
.LSB_WFIFO_PORT_3 (5),
.MSB_WFIFO_PORT_3 (5),
.LSB_RFIFO_PORT_3 (5),
.MSB_RFIFO_PORT_3 (5),
.AVL_DATA_WIDTH_PORT_4 (1),
.AVL_ADDR_WIDTH_PORT_4 (1),
.AVL_NUM_SYMBOLS_PORT_4 (1),
.LSB_WFIFO_PORT_4 (5),
.MSB_WFIFO_PORT_4 (5),
.LSB_RFIFO_PORT_4 (5),
.MSB_RFIFO_PORT_4 (5),
.AVL_DATA_WIDTH_PORT_5 (1),
.AVL_ADDR_WIDTH_PORT_5 (1),
.AVL_NUM_SYMBOLS_PORT_5 (1),
.LSB_WFIFO_PORT_5 (5),
.MSB_WFIFO_PORT_5 (5),
.LSB_RFIFO_PORT_5 (5),
.MSB_RFIFO_PORT_5 (5),
.ENUM_ATTR_COUNTER_ONE_RESET ("DISABLED"),
.ENUM_ATTR_COUNTER_ZERO_RESET ("DISABLED"),
.ENUM_ATTR_STATIC_CONFIG_VALID ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_0 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_1 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_2 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_3 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_4 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_5 ("DISABLED"),
.ENUM_CAL_REQ ("DISABLED"),
.ENUM_CFG_BURST_LENGTH ("BL_8"),
.ENUM_CFG_INTERFACE_WIDTH ("DWIDTH_32"),
.ENUM_CFG_SELF_RFSH_EXIT_CYCLES ("SELF_RFSH_EXIT_CYCLES_512"),
.ENUM_CFG_STARVE_LIMIT ("STARVE_LIMIT_10"),
.ENUM_CFG_TYPE ("DDR3"),
.ENUM_CLOCK_OFF_0 ("DISABLED"),
.ENUM_CLOCK_OFF_1 ("DISABLED"),
.ENUM_CLOCK_OFF_2 ("DISABLED"),
.ENUM_CLOCK_OFF_3 ("DISABLED"),
.ENUM_CLOCK_OFF_4 ("DISABLED"),
.ENUM_CLOCK_OFF_5 ("DISABLED"),
.ENUM_CLR_INTR ("NO_CLR_INTR"),
.ENUM_CMD_PORT_IN_USE_0 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_1 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_2 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_3 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_4 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_5 ("FALSE"),
.ENUM_CPORT0_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT0_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT0_TYPE ("DISABLE"),
.ENUM_CPORT0_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT1_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT1_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT1_TYPE ("DISABLE"),
.ENUM_CPORT1_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT2_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT2_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT2_TYPE ("DISABLE"),
.ENUM_CPORT2_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT3_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT3_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT3_TYPE ("DISABLE"),
.ENUM_CPORT3_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT4_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT4_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT4_TYPE ("DISABLE"),
.ENUM_CPORT4_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT5_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT5_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT5_TYPE ("DISABLE"),
.ENUM_CPORT5_WFIFO_MAP ("FIFO_0"),
.ENUM_CTL_ADDR_ORDER ("CHIP_ROW_BANK_COL"),
.ENUM_CTL_ECC_ENABLED ("CTL_ECC_DISABLED"),
.ENUM_CTL_ECC_RMW_ENABLED ("CTL_ECC_RMW_DISABLED"),
.ENUM_CTL_REGDIMM_ENABLED ("REGDIMM_DISABLED"),
.ENUM_CTL_USR_REFRESH ("CTL_USR_REFRESH_DISABLED"),
.ENUM_CTRL_WIDTH ("DATA_WIDTH_64_BIT"),
.ENUM_DELAY_BONDING ("BONDING_LATENCY_0"),
.ENUM_DFX_BYPASS_ENABLE ("DFX_BYPASS_DISABLED"),
.ENUM_DISABLE_MERGING ("MERGING_ENABLED"),
.ENUM_ECC_DQ_WIDTH ("ECC_DQ_WIDTH_0"),
.ENUM_ENABLE_ATPG ("DISABLED"),
.ENUM_ENABLE_BONDING_0 ("DISABLED"),
.ENUM_ENABLE_BONDING_1 ("DISABLED"),
.ENUM_ENABLE_BONDING_2 ("DISABLED"),
.ENUM_ENABLE_BONDING_3 ("DISABLED"),
.ENUM_ENABLE_BONDING_4 ("DISABLED"),
.ENUM_ENABLE_BONDING_5 ("DISABLED"),
.ENUM_ENABLE_BONDING_WRAPBACK ("DISABLED"),
.ENUM_ENABLE_DQS_TRACKING ("ENABLED"),
.ENUM_ENABLE_ECC_CODE_OVERWRITES ("DISABLED"),
.ENUM_ENABLE_FAST_EXIT_PPD ("DISABLED"),
.ENUM_ENABLE_INTR ("DISABLED"),
.ENUM_ENABLE_NO_DM ("DISABLED"),
.ENUM_ENABLE_PIPELINEGLOBAL ("DISABLED"),
.ENUM_GANGED_ARF ("DISABLED"),
.ENUM_GEN_DBE ("GEN_DBE_DISABLED"),
.ENUM_GEN_SBE ("GEN_SBE_DISABLED"),
.ENUM_INC_SYNC ("FIFO_SET_2"),
.ENUM_LOCAL_IF_CS_WIDTH ("ADDR_WIDTH_0"),
.ENUM_MASK_CORR_DROPPED_INTR ("DISABLED"),
.ENUM_MASK_DBE_INTR ("DISABLED"),
.ENUM_MASK_SBE_INTR ("DISABLED"),
.ENUM_MEM_IF_AL ("AL_0"),
.ENUM_MEM_IF_BANKADDR_WIDTH ("ADDR_WIDTH_3"),
.ENUM_MEM_IF_BURSTLENGTH ("MEM_IF_BURSTLENGTH_8"),
.ENUM_MEM_IF_COLADDR_WIDTH ("ADDR_WIDTH_10"),
.ENUM_MEM_IF_CS_PER_RANK ("MEM_IF_CS_PER_RANK_1"),
.ENUM_MEM_IF_CS_WIDTH ("MEM_IF_CS_WIDTH_1"),
.ENUM_MEM_IF_DQ_PER_CHIP ("MEM_IF_DQ_PER_CHIP_8"),
.ENUM_MEM_IF_DQS_WIDTH ("DQS_WIDTH_4"),
.ENUM_MEM_IF_DWIDTH ("MEM_IF_DWIDTH_32"),
.ENUM_MEM_IF_MEMTYPE ("DDR3_SDRAM"),
.ENUM_MEM_IF_ROWADDR_WIDTH ("ADDR_WIDTH_15"),
.ENUM_MEM_IF_SPEEDBIN ("DDR3_1600_8_8_8"),
.ENUM_MEM_IF_TCCD ("TCCD_4"),
.ENUM_MEM_IF_TCL ("TCL_7"),
.ENUM_MEM_IF_TCWL ("TCWL_7"),
.ENUM_MEM_IF_TFAW ("TFAW_15"),
.ENUM_MEM_IF_TMRD ("TMRD_4"),
.ENUM_MEM_IF_TRAS ("TRAS_14"),
.ENUM_MEM_IF_TRC ("TRC_20"),
.ENUM_MEM_IF_TRCD ("TRCD_6"),
.ENUM_MEM_IF_TRP ("TRP_6"),
.ENUM_MEM_IF_TRRD ("TRRD_3"),
.ENUM_MEM_IF_TRTP ("TRTP_3"),
.ENUM_MEM_IF_TWR ("TWR_6"),
.ENUM_MEM_IF_TWTR ("TWTR_4"),
.ENUM_MMR_CFG_MEM_BL ("MP_BL_8"),
.ENUM_OUTPUT_REGD ("DISABLED"),
.ENUM_PDN_EXIT_CYCLES ("SLOW_EXIT"),
.ENUM_PORT0_WIDTH ("PORT_32_BIT"),
.ENUM_PORT1_WIDTH ("PORT_32_BIT"),
.ENUM_PORT2_WIDTH ("PORT_32_BIT"),
.ENUM_PORT3_WIDTH ("PORT_32_BIT"),
.ENUM_PORT4_WIDTH ("PORT_32_BIT"),
.ENUM_PORT5_WIDTH ("PORT_32_BIT"),
.ENUM_PRIORITY_0_0 ("WEIGHT_0"),
.ENUM_PRIORITY_0_1 ("WEIGHT_0"),
.ENUM_PRIORITY_0_2 ("WEIGHT_0"),
.ENUM_PRIORITY_0_3 ("WEIGHT_0"),
.ENUM_PRIORITY_0_4 ("WEIGHT_0"),
.ENUM_PRIORITY_0_5 ("WEIGHT_0"),
.ENUM_PRIORITY_1_0 ("WEIGHT_0"),
.ENUM_PRIORITY_1_1 ("WEIGHT_0"),
.ENUM_PRIORITY_1_2 ("WEIGHT_0"),
.ENUM_PRIORITY_1_3 ("WEIGHT_0"),
.ENUM_PRIORITY_1_4 ("WEIGHT_0"),
.ENUM_PRIORITY_1_5 ("WEIGHT_0"),
.ENUM_PRIORITY_2_0 ("WEIGHT_0"),
.ENUM_PRIORITY_2_1 ("WEIGHT_0"),
.ENUM_PRIORITY_2_2 ("WEIGHT_0"),
.ENUM_PRIORITY_2_3 ("WEIGHT_0"),
.ENUM_PRIORITY_2_4 ("WEIGHT_0"),
.ENUM_PRIORITY_2_5 ("WEIGHT_0"),
.ENUM_PRIORITY_3_0 ("WEIGHT_0"),
.ENUM_PRIORITY_3_1 ("WEIGHT_0"),
.ENUM_PRIORITY_3_2 ("WEIGHT_0"),
.ENUM_PRIORITY_3_3 ("WEIGHT_0"),
.ENUM_PRIORITY_3_4 ("WEIGHT_0"),
.ENUM_PRIORITY_3_5 ("WEIGHT_0"),
.ENUM_PRIORITY_4_0 ("WEIGHT_0"),
.ENUM_PRIORITY_4_1 ("WEIGHT_0"),
.ENUM_PRIORITY_4_2 ("WEIGHT_0"),
.ENUM_PRIORITY_4_3 ("WEIGHT_0"),
.ENUM_PRIORITY_4_4 ("WEIGHT_0"),
.ENUM_PRIORITY_4_5 ("WEIGHT_0"),
.ENUM_PRIORITY_5_0 ("WEIGHT_0"),
.ENUM_PRIORITY_5_1 ("WEIGHT_0"),
.ENUM_PRIORITY_5_2 ("WEIGHT_0"),
.ENUM_PRIORITY_5_3 ("WEIGHT_0"),
.ENUM_PRIORITY_5_4 ("WEIGHT_0"),
.ENUM_PRIORITY_5_5 ("WEIGHT_0"),
.ENUM_PRIORITY_6_0 ("WEIGHT_0"),
.ENUM_PRIORITY_6_1 ("WEIGHT_0"),
.ENUM_PRIORITY_6_2 ("WEIGHT_0"),
.ENUM_PRIORITY_6_3 ("WEIGHT_0"),
.ENUM_PRIORITY_6_4 ("WEIGHT_0"),
.ENUM_PRIORITY_6_5 ("WEIGHT_0"),
.ENUM_PRIORITY_7_0 ("WEIGHT_0"),
.ENUM_PRIORITY_7_1 ("WEIGHT_0"),
.ENUM_PRIORITY_7_2 ("WEIGHT_0"),
.ENUM_PRIORITY_7_3 ("WEIGHT_0"),
.ENUM_PRIORITY_7_4 ("WEIGHT_0"),
.ENUM_PRIORITY_7_5 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_0 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_1 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_2 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_3 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_4 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_5 ("WEIGHT_0"),
.ENUM_RCFG_USER_PRIORITY_0 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_1 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_2 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_3 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_4 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_5 ("PRIORITY_1"),
.ENUM_RD_DWIDTH_0 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_1 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_2 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_3 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_4 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_5 ("DWIDTH_0"),
.ENUM_RD_FIFO_IN_USE_0 ("FALSE"),
.ENUM_RD_FIFO_IN_USE_1 ("FALSE"),
.ENUM_RD_FIFO_IN_USE_2 ("FALSE"),
.ENUM_RD_FIFO_IN_USE_3 ("FALSE"),
.ENUM_RD_PORT_INFO_0 ("USE_NO"),
.ENUM_RD_PORT_INFO_1 ("USE_NO"),
.ENUM_RD_PORT_INFO_2 ("USE_NO"),
.ENUM_RD_PORT_INFO_3 ("USE_NO"),
.ENUM_RD_PORT_INFO_4 ("USE_NO"),
.ENUM_RD_PORT_INFO_5 ("USE_NO"),
.ENUM_READ_ODT_CHIP ("ODT_DISABLED"),
.ENUM_REORDER_DATA ("DATA_REORDERING"),
.ENUM_RFIFO0_CPORT_MAP ("CMD_PORT_0"),
.ENUM_RFIFO1_CPORT_MAP ("CMD_PORT_0"),
.ENUM_RFIFO2_CPORT_MAP ("CMD_PORT_0"),
.ENUM_RFIFO3_CPORT_MAP ("CMD_PORT_0"),
.ENUM_SINGLE_READY_0 ("CONCATENATE_RDY"),
.ENUM_SINGLE_READY_1 ("CONCATENATE_RDY"),
.ENUM_SINGLE_READY_2 ("CONCATENATE_RDY"),
.ENUM_SINGLE_READY_3 ("CONCATENATE_RDY"),
.ENUM_STATIC_WEIGHT_0 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_1 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_2 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_3 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_4 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_5 ("WEIGHT_0"),
.ENUM_SYNC_MODE_0 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_1 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_2 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_3 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_4 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_5 ("ASYNCHRONOUS"),
.ENUM_TEST_MODE ("NORMAL_MODE"),
.ENUM_THLD_JAR1_0 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_1 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_2 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_3 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_4 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_5 ("THRESHOLD_32"),
.ENUM_THLD_JAR2_0 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_1 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_2 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_3 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_4 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_5 ("THRESHOLD_16"),
.ENUM_USE_ALMOST_EMPTY_0 ("EMPTY"),
.ENUM_USE_ALMOST_EMPTY_1 ("EMPTY"),
.ENUM_USE_ALMOST_EMPTY_2 ("EMPTY"),
.ENUM_USE_ALMOST_EMPTY_3 ("EMPTY"),
.ENUM_USER_ECC_EN ("DISABLE"),
.ENUM_USER_PRIORITY_0 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_1 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_2 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_3 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_4 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_5 ("PRIORITY_1"),
.ENUM_WFIFO0_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO0_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WFIFO1_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO1_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WFIFO2_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO2_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WFIFO3_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO3_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WR_DWIDTH_0 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_1 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_2 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_3 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_4 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_5 ("DWIDTH_0"),
.ENUM_WR_FIFO_IN_USE_0 ("FALSE"),
.ENUM_WR_FIFO_IN_USE_1 ("FALSE"),
.ENUM_WR_FIFO_IN_USE_2 ("FALSE"),
.ENUM_WR_FIFO_IN_USE_3 ("FALSE"),
.ENUM_WR_PORT_INFO_0 ("USE_NO"),
.ENUM_WR_PORT_INFO_1 ("USE_NO"),
.ENUM_WR_PORT_INFO_2 ("USE_NO"),
.ENUM_WR_PORT_INFO_3 ("USE_NO"),
.ENUM_WR_PORT_INFO_4 ("USE_NO"),
.ENUM_WR_PORT_INFO_5 ("USE_NO"),
.ENUM_WRITE_ODT_CHIP ("WRITE_CHIP0_ODT0_CHIP1"),
.INTG_MEM_AUTO_PD_CYCLES (0),
.INTG_CYC_TO_RLD_JARS_0 (1),
.INTG_CYC_TO_RLD_JARS_1 (1),
.INTG_CYC_TO_RLD_JARS_2 (1),
.INTG_CYC_TO_RLD_JARS_3 (1),
.INTG_CYC_TO_RLD_JARS_4 (1),
.INTG_CYC_TO_RLD_JARS_5 (1),
.INTG_EXTRA_CTL_CLK_ACT_TO_ACT (0),
.INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK (0),
.INTG_EXTRA_CTL_CLK_ACT_TO_PCH (0),
.INTG_EXTRA_CTL_CLK_ACT_TO_RDWR (0),
.INTG_EXTRA_CTL_CLK_ARF_PERIOD (0),
.INTG_EXTRA_CTL_CLK_ARF_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT (0),
.INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_PCH_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_PDN_PERIOD (0),
.INTG_EXTRA_CTL_CLK_PDN_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_RD_TO_PCH (0),
.INTG_EXTRA_CTL_CLK_RD_TO_RD (0),
.INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP (0),
.INTG_EXTRA_CTL_CLK_RD_TO_WR (2),
.INTG_EXTRA_CTL_CLK_RD_TO_WR_BC (2),
.INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP (2),
.INTG_EXTRA_CTL_CLK_SRF_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL (0),
.INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_WR_TO_PCH (0),
.INTG_EXTRA_CTL_CLK_WR_TO_RD (3),
.INTG_EXTRA_CTL_CLK_WR_TO_RD_BC (3),
.INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP (3),
.INTG_EXTRA_CTL_CLK_WR_TO_WR (0),
.INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP (0),
.INTG_MEM_IF_TREFI (3120),
.INTG_MEM_IF_TRFC (120),
.INTG_RCFG_SUM_WT_PRIORITY_0 (0),
.INTG_RCFG_SUM_WT_PRIORITY_1 (0),
.INTG_RCFG_SUM_WT_PRIORITY_2 (0),
.INTG_RCFG_SUM_WT_PRIORITY_3 (0),
.INTG_RCFG_SUM_WT_PRIORITY_4 (0),
.INTG_RCFG_SUM_WT_PRIORITY_5 (0),
.INTG_RCFG_SUM_WT_PRIORITY_6 (0),
.INTG_RCFG_SUM_WT_PRIORITY_7 (0),
.INTG_SUM_WT_PRIORITY_0 (0),
.INTG_SUM_WT_PRIORITY_1 (0),
.INTG_SUM_WT_PRIORITY_2 (0),
.INTG_SUM_WT_PRIORITY_3 (0),
.INTG_SUM_WT_PRIORITY_4 (0),
.INTG_SUM_WT_PRIORITY_5 (0),
.INTG_SUM_WT_PRIORITY_6 (0),
.INTG_SUM_WT_PRIORITY_7 (0),
.INTG_POWER_SAVING_EXIT_CYCLES (5),
.INTG_MEM_CLK_ENTRY_CYCLES (10),
.ENUM_ENABLE_BURST_INTERRUPT ("DISABLED"),
.ENUM_ENABLE_BURST_TERMINATE ("DISABLED"),
.AFI_RATE_RATIO (1),
.AFI_ADDR_WIDTH (15),
.AFI_BANKADDR_WIDTH (3),
.AFI_CONTROL_WIDTH (1),
.AFI_CS_WIDTH (1),
.AFI_DM_WIDTH (8),
.AFI_DQ_WIDTH (64),
.AFI_ODT_WIDTH (1),
.AFI_WRITE_DQS_WIDTH (4),
.AFI_RLAT_WIDTH (6),
.AFI_WLAT_WIDTH (6),
.HARD_PHY (1)
) c0 (
.afi_clk (pll_afi_clk_clk), // afi_clk.clk
.afi_reset_n (p0_afi_reset_reset), // afi_reset.reset_n
.ctl_reset_n (p0_ctl_reset_reset), // ctl_reset.reset_n
.afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk
.ctl_clk (p0_ctl_clk_clk), // ctl_clk.clk
.local_init_done (), // status.local_init_done
.local_cal_success (), // .local_cal_success
.local_cal_fail (), // .local_cal_fail
.afi_addr (c0_afi_afi_addr), // afi.afi_addr
.afi_ba (c0_afi_afi_ba), // .afi_ba
.afi_cke (c0_afi_afi_cke), // .afi_cke
.afi_cs_n (c0_afi_afi_cs_n), // .afi_cs_n
.afi_ras_n (c0_afi_afi_ras_n), // .afi_ras_n
.afi_we_n (c0_afi_afi_we_n), // .afi_we_n
.afi_cas_n (c0_afi_afi_cas_n), // .afi_cas_n
.afi_rst_n (c0_afi_afi_rst_n), // .afi_rst_n
.afi_odt (c0_afi_afi_odt), // .afi_odt
.afi_mem_clk_disable (c0_afi_afi_mem_clk_disable), // .afi_mem_clk_disable
.afi_init_req (), // .afi_init_req
.afi_cal_req (), // .afi_cal_req
.afi_seq_busy (), // .afi_seq_busy
.afi_ctl_refresh_done (), // .afi_ctl_refresh_done
.afi_ctl_long_idle (), // .afi_ctl_long_idle
.afi_dqs_burst (c0_afi_afi_dqs_burst), // .afi_dqs_burst
.afi_wdata_valid (c0_afi_afi_wdata_valid), // .afi_wdata_valid
.afi_wdata (c0_afi_afi_wdata), // .afi_wdata
.afi_dm (c0_afi_afi_dm), // .afi_dm
.afi_rdata (p0_afi_afi_rdata), // .afi_rdata
.afi_rdata_en (c0_afi_afi_rdata_en), // .afi_rdata_en
.afi_rdata_en_full (c0_afi_afi_rdata_en_full), // .afi_rdata_en_full
.afi_rdata_valid (p0_afi_afi_rdata_valid), // .afi_rdata_valid
.afi_wlat (p0_afi_afi_wlat), // .afi_wlat
.afi_rlat (p0_afi_afi_rlat), // .afi_rlat
.afi_cal_success (p0_afi_afi_cal_success), // .afi_cal_success
.afi_cal_fail (p0_afi_afi_cal_fail), // .afi_cal_fail
.cfg_addlat (c0_hard_phy_cfg_cfg_addlat), // hard_phy_cfg.cfg_addlat
.cfg_bankaddrwidth (c0_hard_phy_cfg_cfg_bankaddrwidth), // .cfg_bankaddrwidth
.cfg_caswrlat (c0_hard_phy_cfg_cfg_caswrlat), // .cfg_caswrlat
.cfg_coladdrwidth (c0_hard_phy_cfg_cfg_coladdrwidth), // .cfg_coladdrwidth
.cfg_csaddrwidth (c0_hard_phy_cfg_cfg_csaddrwidth), // .cfg_csaddrwidth
.cfg_devicewidth (c0_hard_phy_cfg_cfg_devicewidth), // .cfg_devicewidth
.cfg_dramconfig (c0_hard_phy_cfg_cfg_dramconfig), // .cfg_dramconfig
.cfg_interfacewidth (c0_hard_phy_cfg_cfg_interfacewidth), // .cfg_interfacewidth
.cfg_rowaddrwidth (c0_hard_phy_cfg_cfg_rowaddrwidth), // .cfg_rowaddrwidth
.cfg_tcl (c0_hard_phy_cfg_cfg_tcl), // .cfg_tcl
.cfg_tmrd (c0_hard_phy_cfg_cfg_tmrd), // .cfg_tmrd
.cfg_trefi (c0_hard_phy_cfg_cfg_trefi), // .cfg_trefi
.cfg_trfc (c0_hard_phy_cfg_cfg_trfc), // .cfg_trfc
.cfg_twr (c0_hard_phy_cfg_cfg_twr), // .cfg_twr
.io_intaficalfail (p0_io_int_io_intaficalfail), // io_int.io_intaficalfail
.io_intaficalsuccess (p0_io_int_io_intaficalsuccess), // .io_intaficalsuccess
.mp_cmd_clk_0 (1'b0), // (terminated)
.mp_cmd_reset_n_0 (1'b1), // (terminated)
.mp_cmd_clk_1 (1'b0), // (terminated)
.mp_cmd_reset_n_1 (1'b1), // (terminated)
.mp_cmd_clk_2 (1'b0), // (terminated)
.mp_cmd_reset_n_2 (1'b1), // (terminated)
.mp_cmd_clk_3 (1'b0), // (terminated)
.mp_cmd_reset_n_3 (1'b1), // (terminated)
.mp_cmd_clk_4 (1'b0), // (terminated)
.mp_cmd_reset_n_4 (1'b1), // (terminated)
.mp_cmd_clk_5 (1'b0), // (terminated)
.mp_cmd_reset_n_5 (1'b1), // (terminated)
.mp_rfifo_clk_0 (1'b0), // (terminated)
.mp_rfifo_reset_n_0 (1'b1), // (terminated)
.mp_wfifo_clk_0 (1'b0), // (terminated)
.mp_wfifo_reset_n_0 (1'b1), // (terminated)
.mp_rfifo_clk_1 (1'b0), // (terminated)
.mp_rfifo_reset_n_1 (1'b1), // (terminated)
.mp_wfifo_clk_1 (1'b0), // (terminated)
.mp_wfifo_reset_n_1 (1'b1), // (terminated)
.mp_rfifo_clk_2 (1'b0), // (terminated)
.mp_rfifo_reset_n_2 (1'b1), // (terminated)
.mp_wfifo_clk_2 (1'b0), // (terminated)
.mp_wfifo_reset_n_2 (1'b1), // (terminated)
.mp_rfifo_clk_3 (1'b0), // (terminated)
.mp_rfifo_reset_n_3 (1'b1), // (terminated)
.mp_wfifo_clk_3 (1'b0), // (terminated)
.mp_wfifo_reset_n_3 (1'b1), // (terminated)
.csr_clk (1'b0), // (terminated)
.csr_reset_n (1'b1), // (terminated)
.avl_ready_0 (), // (terminated)
.avl_burstbegin_0 (1'b0), // (terminated)
.avl_addr_0 (1'b0), // (terminated)
.avl_rdata_valid_0 (), // (terminated)
.avl_rdata_0 (), // (terminated)
.avl_wdata_0 (1'b0), // (terminated)
.avl_be_0 (1'b0), // (terminated)
.avl_read_req_0 (1'b0), // (terminated)
.avl_write_req_0 (1'b0), // (terminated)
.avl_size_0 (3'b000), // (terminated)
.avl_ready_1 (), // (terminated)
.avl_burstbegin_1 (1'b0), // (terminated)
.avl_addr_1 (1'b0), // (terminated)
.avl_rdata_valid_1 (), // (terminated)
.avl_rdata_1 (), // (terminated)
.avl_wdata_1 (1'b0), // (terminated)
.avl_be_1 (1'b0), // (terminated)
.avl_read_req_1 (1'b0), // (terminated)
.avl_write_req_1 (1'b0), // (terminated)
.avl_size_1 (3'b000), // (terminated)
.avl_ready_2 (), // (terminated)
.avl_burstbegin_2 (1'b0), // (terminated)
.avl_addr_2 (1'b0), // (terminated)
.avl_rdata_valid_2 (), // (terminated)
.avl_rdata_2 (), // (terminated)
.avl_wdata_2 (1'b0), // (terminated)
.avl_be_2 (1'b0), // (terminated)
.avl_read_req_2 (1'b0), // (terminated)
.avl_write_req_2 (1'b0), // (terminated)
.avl_size_2 (3'b000), // (terminated)
.avl_ready_3 (), // (terminated)
.avl_burstbegin_3 (1'b0), // (terminated)
.avl_addr_3 (1'b0), // (terminated)
.avl_rdata_valid_3 (), // (terminated)
.avl_rdata_3 (), // (terminated)
.avl_wdata_3 (1'b0), // (terminated)
.avl_be_3 (1'b0), // (terminated)
.avl_read_req_3 (1'b0), // (terminated)
.avl_write_req_3 (1'b0), // (terminated)
.avl_size_3 (3'b000), // (terminated)
.avl_ready_4 (), // (terminated)
.avl_burstbegin_4 (1'b0), // (terminated)
.avl_addr_4 (1'b0), // (terminated)
.avl_rdata_valid_4 (), // (terminated)
.avl_rdata_4 (), // (terminated)
.avl_wdata_4 (1'b0), // (terminated)
.avl_be_4 (1'b0), // (terminated)
.avl_read_req_4 (1'b0), // (terminated)
.avl_write_req_4 (1'b0), // (terminated)
.avl_size_4 (3'b000), // (terminated)
.avl_ready_5 (), // (terminated)
.avl_burstbegin_5 (1'b0), // (terminated)
.avl_addr_5 (1'b0), // (terminated)
.avl_rdata_valid_5 (), // (terminated)
.avl_rdata_5 (), // (terminated)
.avl_wdata_5 (1'b0), // (terminated)
.avl_be_5 (1'b0), // (terminated)
.avl_read_req_5 (1'b0), // (terminated)
.avl_write_req_5 (1'b0), // (terminated)
.avl_size_5 (3'b000), // (terminated)
.csr_write_req (1'b0), // (terminated)
.csr_read_req (1'b0), // (terminated)
.csr_waitrequest (), // (terminated)
.csr_addr (10'b0000000000), // (terminated)
.csr_be (1'b0), // (terminated)
.csr_wdata (8'b00000000), // (terminated)
.csr_rdata (), // (terminated)
.csr_rdata_valid (), // (terminated)
.local_multicast (1'b0), // (terminated)
.local_refresh_req (1'b0), // (terminated)
.local_refresh_chip (1'b0), // (terminated)
.local_refresh_ack (), // (terminated)
.local_self_rfsh_req (1'b0), // (terminated)
.local_self_rfsh_chip (1'b0), // (terminated)
.local_self_rfsh_ack (), // (terminated)
.local_deep_powerdn_req (1'b0), // (terminated)
.local_deep_powerdn_chip (1'b0), // (terminated)
.local_deep_powerdn_ack (), // (terminated)
.local_powerdn_ack (), // (terminated)
.local_priority (1'b0), // (terminated)
.bonding_in_1 (4'b0000), // (terminated)
.bonding_in_2 (6'b000000), // (terminated)
.bonding_in_3 (6'b000000), // (terminated)
.bonding_out_1 (), // (terminated)
.bonding_out_2 (), // (terminated)
.bonding_out_3 () // (terminated)
);
altera_mem_if_oct_cyclonev #(
.OCT_TERM_CONTROL_WIDTH (16)
) oct (
.oct_rzqin (oct_rzqin), // oct.rzqin
.seriesterminationcontrol (oct_oct_sharing_seriesterminationcontrol), // oct_sharing.seriesterminationcontrol
.parallelterminationcontrol (oct_oct_sharing_parallelterminationcontrol) // .parallelterminationcontrol
);
altera_mem_if_dll_cyclonev #(
.DLL_DELAY_CTRL_WIDTH (7),
.DLL_OFFSET_CTRL_WIDTH (6),
.DELAY_BUFFER_MODE ("HIGH"),
.DELAY_CHAIN_LENGTH (8),
.DLL_INPUT_FREQUENCY_PS_STR ("2500 ps")
) dll (
.clk (p0_dll_clk_clk), // clk.clk
.dll_pll_locked (p0_dll_sharing_dll_pll_locked), // dll_sharing.dll_pll_locked
.dll_delayctrl (dll_dll_sharing_dll_delayctrl) // .dll_delayctrl
);
endmodule
|
//--------------------------------------------------------------------------
// --
// OneWireMaster --
// A synthesizable 1-wire master peripheral --
// Copyright 1999-2005 Dallas Semiconductor Corporation --
// --
//--------------------------------------------------------------------------
// --
// Purpose: Provides timing and control of Dallas 1-wire bus --
// through a memory-mapped peripheral --
// File: OneWireMaster.v --
// Date: February 1, 2005 --
// Version: v2.100 --
// Authors: Rick Downs and Charles Hill, --
// Dallas Semiconductor Corporation --
// --
// Note: This source code is available for use without license. --
// Dallas Semiconductor is not responsible for the --
// functionality or utility of this product. --
// --
// REV: Updated 1-Wire timings to match App Note 126 - SKH --
// Added in Async MR of DQ_CONTROL - GAG --
// Changed WriteZero TimeSlotCnt to 60 instead of only 30 to --
// match OneWire Spec. - GAG --
// Added in bit control mode, left dqz for other function - GAG--
// Added strong pullup enable signal - GAG --
// Modified pd so it will not fire until the entire PD routine --
// has completed - GAG --
// Added OW_LOW interrupt and OW_SHORT interrupt - GAG --
// Added PPM and LLM for long line situations - GAG --
// Changed logic for rsrf and rbf int flags - GAG --
// Significant changes to improve synthesis - English --
// Ported to Verilog - Sandelin --
//--------------------------------------------------------------------------
module onewiremaster (
BIT_CTL, clk, clk_1us_en, clr_activate_intr, DQ_IN, EN_FOW, EOWL,
EOWSH, epd, erbf, ersf, etbe, etmt, FOW, ias, LLM, MR, OD,
owr, pd, PPM, rbf_reset, sr_a, STP_SPLY, STPEN, tbe, xmit_buffer,
clear_interrupts, DQ_CONTROL, FSM_CLK, INTR,
OneWireIO_eq_Load, OW_LOW, OW_SHORT, pdr, rbf, rcvr_buffer, reset_owr,
rsrf, STPZ, temt);
input BIT_CTL; // enable only single bit transmitions
input clk; //Master clk; much faster than 1us
input clk_1us_en; // 1us reference clock
input clr_activate_intr;
input DQ_IN; // OW data input
input EN_FOW; // enable force OW functionality
input EOWL; // enable One wire bus low interrupt
input EOWSH; // enable One Wire bus short interrupt
input epd; // enable presence detect interrupt
input erbf; // enable receive buffer full interrupt
input ersf; // enable receive shift register full int.
input etbe; // enable transmit buffer empty interrupt
input etmt; // enable transmit shift inputister empty int.
input FOW; // Force OW value low
input ias; // INTR active state
input LLM; // long line mode enable
input MR; // master reset
input OD; // enable overdrive
input owr; // one wire reset ???
input pd; // presence detect interrupt
input PPM; // presence pulse masking enable
input rbf_reset; // clear for receive buffer full interrupt
input sr_a; // search rom accelorator enable
input STP_SPLY; // enable strong pull up supply mode
input STPEN; // enable strong pull up output
input tbe; // transmit buffer empty interrupt
input [7:0] xmit_buffer; // transmit buffer
output clear_interrupts;
output DQ_CONTROL; // OW pulldown control
output FSM_CLK; // state machine clk
output INTR; // One wire master interrupt output signal
output OneWireIO_eq_Load;
output OW_LOW; // One wire low interrupt
output OW_SHORT; // One wire short interrupt
output pdr; // presence detect result
output rbf; // receive buffer full int
output [7:0] rcvr_buffer; // receive register
output reset_owr; //
output rsrf; // receive shift reg full interrupt
output STPZ; // Strong pullup control (active low)
output temt; // transmit shift reg empty interrupt
//
// Define the states
//
parameter [2:0] Idle = 3'b000, // Idle
CheckOWR = 3'b001, // Check for shorted OW
Reset_Low = 3'b010, // Start reset
PD_Wait = 3'b011, // release line for 1T
PD_Sample = 3'b100, // sample line after slowest 1T over
Reset_High = 3'b101, // recover OW line level
PD_Force = 3'b110, // mask the presence pulse
PD_Release = 3'b111; // recover OW line level
parameter [4:0] IdleS= 5'b00000, // Idle state
Load= 5'b00001, // Load byte
CheckOW= 5'b00010, // Check for shorted line
DQLOW= 5'b00011, // Start of timeslot
WriteZero= 5'b00100, // Write a zero to the 1-wire
WriteOne= 5'b00101, // Write a one to the 1-wire
ReadBit= 5'b00110, // Search Rom Accelerator read bit
FirstPassSR=5'b00111, // Used by SRA
WriteBitSR= 5'b01000, // Decide what bit value to write in SRA
WriteBit= 5'b01001, // Writes the chosen bit in SRA
WaitTS= 5'b01010, // Wait for end of time slot
IndexInc= 5'b01011, // Increments bit index
UpdateBuff= 5'b01100, // Updates states of rbf
ODWriteZero=5'b01101, // Write a zero @ OD speed to OW
ODWriteOne= 5'b01110, // Write a one @ OD speed to OW
ClrLowDone= 5'b01111; // disable stpupz before pulldown
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// micro-second count for bit transitions and sample
parameter [6:0] // Standard speed
bit_ts_writeone_high = 7'b0000110, // release-1 @6 us
bit_ts_writeone_high_ll = 7'b0001000, // rel-1-LLM @8 us
bit_ts_sample = 7'b0001111, // sample @15 us
bit_ts_sample_ll = 7'b0011000, // sample/llm @24 us
bit_ts_writezero_high = 7'b0111100, // release-0 @60 us
bit_ts_end = 7'b1000110, // end @70 us
bit_ts_end_ll = 7'b1010000, // end @80 us
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// Overdrive speed
// note that due to the state machine architecture, the
// writeone_high_od and sample_od must be 1 and 2 us.
// writezero_high_od and end_od are adjustable, so long
// as writezero_high_od does not exceed a particular
// 1-Wire device max low time.
bit_ts_writeone_high_od = 7'b0000001, // release-1 @1 us
bit_ts_sample_od = 7'b0000010, // sample @2 us
bit_ts_writezero_high_od = 7'b0001000, // release-0 @8 us
bit_ts_end_od = 7'b0001001; // end @10 us
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// micro-second count for reset transitions
parameter [10:0] // Standard speed
reset_ts_release = 11'b01001011000, // release @600 us
reset_ts_no_stpz = 11'b01001100010, // stpz=1 @610 us
reset_ts_ppm = 11'b01001101100, // pp-mask @620 us
reset_ts_sample = 11'b01010011110, // sample @670 us
reset_ts_llsample= 11'b01010101101, // sample @685 us
reset_ts_ppm_end = 11'b01010110010, // ppm-end @690 us
reset_ts_stpz = 11'b01110110110, // stpz @950 us
reset_ts_recover = 11'b01111000000, // recover @960 us
reset_ts_end = 11'b10000111000, // end @1080 us
// Overdrive speed
reset_ts_release_od = 11'b00001000110, // release @70 us
reset_ts_no_stpz_od = 11'b00001001011, // stpz=1 @75 us
reset_ts_sample_od = 11'b00001001111, // sample @79 us
reset_ts_stpz_od = 11'b00001101001, // stpz @105 us
reset_ts_recover_od = 11'b00001110011, // recover @115 us
reset_ts_end_od = 11'b00010000000; // end @128 us
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
wire owr; // 1W reset command
wire sr_a; // search ROM accelerator command
// interrupt register
wire pd; // presence detect done flag
reg pdr; // presence detect result
wire tbe; // transmit buffer empty flag
reg temt; // transmit shift register empty flag
wire temt_ext; // temt extended flag
reg rbf; // receive buffer full flag
reg rsrf; // receive shift register full flag
reg OW_SHORT; // OW line shorted interrupt
reg OW_LOW; // OW line low interrupt
reg INTR;
//wire rsrf_reset; // clear signal for rsrf
reg set_rbf; // set signal for rbf
// interrupt enable register
wire epd; // enable presence detect interrupt
wire ias; // INTR active state
wire etbe; // enable transmit buffer empty interrupt
wire etmt; // enable transmit shift register empty int.
wire erbf; // enable receive buffer full interrupt
wire ersf; // enable receive shift register full int.
wire EOWSH; // enable ow shorted interrupt
wire EOWL; // enable ow low interrupt
wire clr_activate_intr;
reg reset_owr;
reg activate_intr;
reg dly_clr_activate_intr;
reg clear_interrupts;
reg SET_RSHRT; // set ow_short prior to ow reset
reg SET_IOSHRT; // set ow_short prior to tx a bit
wire [7:0] xmit_buffer; // transmit buffer
reg [7:0] xmit_shiftreg; // transmit shift register
reg [7:0] rcvr_buffer; // receive buffer
reg [7:0] rcvr_shiftreg; // receive shift register
reg last_rcvr_bit; // active on index = 7 to begin shift to rbe
reg byte_done;
reg byte_done_flag, bdext1; // signals to stretch byte_done
reg First; // for Search ROM accelerator
reg BitRead1;
reg BitRead2;
reg BitWrite;
reg [2:0] OneWireReset;
reg [4:0] OneWireIO;
reg [10:0] count;
//reg [4:0] smCnt;
reg [3:0] index;
reg [6:0] TimeSlotCnt;
reg PD_READ;
reg LOW_DONE;
reg DQ_CONTROL_F;
wire DQ_CONTROL;
wire STPZ;
reg DQ_IN_HIGH;
reg OD_DQH;
reg rbf_set;
reg rsrf_reset;
reg ROW;
// wire FSM_CLK = clk_1us;
wire FSM_CLK = clk;
//
// 1 wire control
//
assign DQ_CONTROL = MR ? 1'b1 : DQ_CONTROL_F; //GAG added in asynch RESET
always @(posedge clk) //GAG added in ODWriteZero
begin
if(clk_1us_en)
begin
DQ_CONTROL_F <=
(EN_FOW == 1) && (FOW == 1)?0:
OneWireReset == Reset_Low?0:
OneWireReset == PD_Wait?1:
OneWireReset == PD_Force?0:
OneWireIO == DQLOW?0:
OneWireIO == WriteZero?0:
OneWireIO == ODWriteZero?0:
OneWireIO == WriteBit?0:
1;
end
end
wire OneWireIO_eq_Load = OneWireIO == Load;
//
// Strong Pullup control section - GAG
// not pulling line low, not checking for pres detect, and
// OW has recovered from read
// SPLY is only for enabling STP when a slave requires high current
// and STP_SPLY is enabled
//
wire SPLY = (STP_SPLY && (OneWireReset == Idle) && (OneWireIO == IdleS));
assign STPZ = !(STPEN && DQ_CONTROL && DQ_IN_HIGH
&& (PD_READ || LOW_DONE || SPLY));
always @(posedge MR or posedge FSM_CLK)
begin
if (MR)
begin
DQ_IN_HIGH <= 0;
OD_DQH <=0;
end
else if(clk_1us_en)
begin
if (OD)
if(DQ_IN && !DQ_IN_HIGH && !OD_DQH)
begin
DQ_IN_HIGH <= 1;
OD_DQH <=1;
end
else if(OD_DQH && DQ_IN)
DQ_IN_HIGH <= 0;
else
begin
OD_DQH <=0;
DQ_IN_HIGH <= 0;
end
else
begin
if(DQ_IN && !DQ_IN_HIGH)
DQ_IN_HIGH <= 1;
else if (DQ_IN && DQ_IN_HIGH)
DQ_IN_HIGH <= DQ_IN_HIGH;
else
DQ_IN_HIGH <= 0;
end
end
end
//
// Update receive buffer and the rsrf and rbf int flags
//
always @(posedge MR or posedge rbf_reset or posedge rbf_set)
if (MR)
rbf <= 0;
else if (rbf_reset) //note that rbf resets at the beginning of the RX buff read
rbf <= 0;
else
rbf <= 1;
always @(posedge MR or posedge FSM_CLK)
if (MR)
rsrf <= 1'b0;
else if(clk_1us_en)
begin
if (last_rcvr_bit || BIT_CTL)
begin
if (OneWireIO == IndexInc)
rsrf <= 1'b1;
else if (rsrf_reset)
rsrf <= 1'b0;
end
else if (rsrf_reset || (OneWireIO == DQLOW))
rsrf <= 1'b0;
end
always @(posedge FSM_CLK or posedge MR)
if (MR)
begin
rcvr_buffer <= 0;
rbf_set <= 0;
end
else if(clk_1us_en)
if (rsrf && !rbf)
begin
rcvr_buffer <= rcvr_shiftreg;
rbf_set <= 1'b1;
rsrf_reset <= 1'b1;
end
else
begin
rbf_set <= 1'b0;
if (!rsrf)
rsrf_reset <= 1'b0;
end
//
// Update OW shorted interrupt
//
always @(posedge MR or posedge FSM_CLK)
begin
if(MR)
OW_SHORT <= 1'b0;
else if(clk_1us_en)
begin
if (SET_RSHRT || SET_IOSHRT)
OW_SHORT <= 1'b1;
else if (clr_activate_intr)
OW_SHORT <= 1'b0;
else
OW_SHORT <= OW_SHORT;
end
end
//
// Update OW bus low interrupt
//
always @(posedge MR or posedge FSM_CLK)
begin
if (MR)
OW_LOW <= 0;
else if(clk_1us_en)
begin
if (!DQ_IN && (OneWireReset == Idle) && (OneWireIO == IdleS))
OW_LOW <= 1;
else if (clr_activate_intr)
OW_LOW <= 0;
else
OW_LOW <= OW_LOW;
end
end
///////////////////////////////////////////////////////////////
// The following section handles the interrupt itself
///////////////////////////////////////////////////////////////
//
// Create clear interrupts
//
always @(posedge MR or posedge FSM_CLK)
if (MR)
begin
//dly_clr_activate_intr <= 1'b0;
clear_interrupts <= 1'b0;
end // if (MR)
else if(clk_1us_en)
begin
//dly_clr_activate_intr<=clr_activate_intr;
clear_interrupts<=clr_activate_intr;
//clear_interrupts <= dly_clr_activate_intr ;
end
wire acint_reset = MR || clr_activate_intr;
//
// Check for active interrupt
//
always @(posedge acint_reset or posedge FSM_CLK)
if(acint_reset)
activate_intr <= 1'b0;
else if(clk_1us_en)
case(1)
pd && epd:
activate_intr <= 1'b1;
tbe && etbe && !temt:
activate_intr <= 1'b1;
temt_ext && etmt:
activate_intr <= 1'b1;
rbf && erbf:
activate_intr <= 1'b1;
rsrf && ersf:
activate_intr <= 1'b1;
OW_LOW && EOWL:
activate_intr <= 1'b1;
OW_SHORT && EOWSH:
activate_intr <= 1'b1;
endcase // case(1)
//
// Create INTR signal by checking for active interrupt and active
// state of INTR
//
always @(activate_intr or ias)
case({activate_intr,ias})
2'b11:
INTR <= 1'b1;
2'b01:
INTR <= 1'b0;
2'b10:
INTR <= 1'b1; // shughes - 8-16-04 - was 1'b0
default:
INTR <= 1'b0; // shughes - 8-16-04 - was 1'b1
endcase // case({activate_intr,ias})
//--------------------------------------------------------------------------
//
// OneWireReset
//
// this state machine performs the 1-wire reset and presence detect
// - Added OD for overdrive speed presence detect
// - Added PD_LOW bit for strong pullup control
//
// Idle : OW high - waiting to issue a PD
// CheckOWR : OW high - checks for shorted OW line
// Reset_Low : OW low - held down for GT8 OW osc periods
// PD_Wait : OW high - released and waits for 1T
// PD_Sample : OW high - checks to see if a slave is out there pulling
// OW low for 4T
// Reset_High : OW high - slave, if any, release OW and host lets it recover
//--------------------------------------------------------------------------
always @(posedge FSM_CLK or posedge MR)
if(MR) begin
pdr <= 1'b1; // Added default state to conform to spec - SDS
OneWireReset <= Idle;
//smCnt <= 0; // added to init simulations
count <= 0;
PD_READ <= 0; // Added PD_READ - GAG
reset_owr <= 0;
SET_RSHRT <= 0; //
ROW <= 0;
end
else if(clk_1us_en)
begin
if(!owr)
begin
count <= 0;
ROW <= 0;
reset_owr <= 0;
OneWireReset <= Idle;
end
else
case(OneWireReset)
Idle: begin
if (ROW)
reset_owr <= 1;
else
begin
count <= 0;
SET_RSHRT <=0;
reset_owr <= 0;
OneWireReset <= CheckOWR;
end
end
CheckOWR: begin
OneWireReset <= Reset_Low;
if(!DQ_IN)
SET_RSHRT <= 1;
end
Reset_Low: begin
count <= count + 1;
PD_READ <= 0; // Added PD_READ - GAG
if(OD) // Added OD - GAG
begin
// tRSTL - OD
if(count == reset_ts_release_od)
begin
OneWireReset <= PD_Wait;
PD_READ <= 1;
end
end
// tRSTL - STD
else if(count == reset_ts_release)
begin
OneWireReset <= PD_Wait;
PD_READ <= 1;
end
end
PD_Wait: begin
SET_RSHRT <= 0;
count <= count + 1;
if(!DQ_IN & DQ_CONTROL_F) begin
OneWireReset <= PD_Sample;
//smCnt <= 0;
end
else if(OD)
begin
// (tRSTL + pull-up time) - OD
if(count==reset_ts_no_stpz_od)
// disables stp_sply
PD_READ <= 0; // Be sure to turn off 4 MPD mode
// tMSP - OD
else if(count == reset_ts_sample_od)
begin
OneWireReset <= PD_Sample;
//smCnt <= 0;
end
end
// (tRSTL + pull-up time) - STD
else if(count == reset_ts_no_stpz)
// disables stp_sply
PD_READ <= 0; // Be sure to turn off 4 MPD mode
// tPPM1 - STD
else if((count == reset_ts_ppm) && PPM)
OneWireReset <= PD_Force;
// tMSP - STD
else if(count == reset_ts_llsample && !LLM)
begin
OneWireReset <= PD_Sample;
//smCnt <= 0;
end
else if(count == reset_ts_sample && LLM)
begin
OneWireReset <= PD_Sample;
//smCnt <= 0;
end
end
PD_Sample: begin
PD_READ <= 0;
count <= count + 1;
//smCnt <= smCnt + 1;
//if (OD) // Added OD - GAG
// begin
// if(smCnt == 3-1)
// begin
pdr <= DQ_IN;
OneWireReset <= Reset_High;
// end
// end
//else
// if(smCnt == 30-1)
// begin
// pdr <= DQ_IN;
// OneWireReset <= Reset_High;
// end
end
Reset_High: begin
count <= count + 1;
if (OD) // Added OD - GAG
begin
if (count == reset_ts_stpz_od)
begin
if (DQ_IN)
PD_READ <= 1;
end
else if (count == reset_ts_recover_od)
begin
PD_READ <= 0;
end
else if (count == reset_ts_end_od)
begin
PD_READ <= 0;
OneWireReset <= Idle;
ROW <= 1;
end
end
else
begin
if(count == reset_ts_stpz)
begin
if (DQ_IN)
PD_READ <= 1;
end
else if (count == reset_ts_recover)
begin
PD_READ <= 0;
end
else if (count == reset_ts_end)
begin
PD_READ <= 0;
OneWireReset <= Idle;
ROW <= 1;
end
end
end
PD_Force: begin
count <= count + 1;
// tPPM2
if (count == reset_ts_ppm_end)
begin
OneWireReset <= PD_Release;
end
end
PD_Release: begin
count <= count + 1;
pdr <= 0; //force valid result
if(count == reset_ts_stpz)
begin
if (DQ_IN)
PD_READ <= 1;
end
else if (count == reset_ts_recover)
begin
PD_READ <= 0;
end
else if (count == reset_ts_end)
begin
PD_READ <= 0;
OneWireReset <= Idle;
ROW <= 1;
end
end
endcase
end
//--------------------------------------------------------------------------
//
// OneWireIO
//
// this state machine performs the 1-wire writing and reading
// - Added ODWriteZero and ODWriteOne for overdrive timing
//
// IdleS : Waiting for transmit byte to be loaded
// ClrLowDone : Disables strong pullup before pulldown turns on
// Load : Loads byte to shift reg
// CheckOW : Checks for OW short
// DQLOW : Starts time slot with OW = 0
// ODWriteZero : Completes write of 0 bit / read bit in OD speed
// ODWriteOne : Completes write of 1 bit / read bit in OD speed
// WriteZero : Completes write of 0 bit / read bit in standard speed
// WriteOne : Completes write of 1 bit / read bit in standard speed
// ReadBit : AutoSearchRom : Reads the first bit value
// FirstPassSR : AutoSearchRom : Decides to do another read or the write
// WriteBitSR : AutoSearchRom : Determines the bit to write
// WriteBit : AutoSearchRom : Writes the bit
// WatiTS : Allows OW to recover for the remainder of the time slot
// IndexInc : Increment the index to send out next bit (in byte)
// UpdateBuff : Allows other signals to update following finished byte/bit
//--------------------------------------------------------------------------
// The following 2 registers are to stretch the temt signal to catch the
// temt interrupt source - SDS
always @(posedge MR or posedge FSM_CLK)
if(MR)
bdext1 <= 1'b0;
else if(clk_1us_en)
bdext1 <= byte_done;
always @(posedge MR or posedge FSM_CLK)
if(MR)
byte_done_flag <= 1'b0;
else if(clk_1us_en)
byte_done_flag <= bdext1;
assign temt_ext = temt && byte_done_flag;
// The index variable has been decoded explicitly in this state machine
// so that the code would compile on the Cypress warp compiler - SDS
always @(posedge FSM_CLK or posedge MR)
if(MR) begin
index <= 0;
TimeSlotCnt <= 0;
temt <= 1'b1;
last_rcvr_bit <= 1'b0;
rcvr_shiftreg <= 0;
OneWireIO <= IdleS;
BitRead1<=0;
BitRead2<=0;
BitWrite<=0;
First <= 1'b0;
byte_done <= 1'b0;
xmit_shiftreg<=0;
LOW_DONE <= 0;
SET_IOSHRT <= 0;
end
else if(clk_1us_en)
case(OneWireIO)
// IdleS state clears variables and waits for something to be
// deposited in the transmit buffer. When something is there,
// the next state is Load.
IdleS:
begin
byte_done <= 1'b0;
index <= 0;
last_rcvr_bit <= 1'b0;
First <= 1'b0;
TimeSlotCnt <= 0;
LOW_DONE <= 0;
SET_IOSHRT <= 0;
temt <= 1'b1;
if(!tbe)
begin
if(STPEN)
OneWireIO <= ClrLowDone;
else
OneWireIO <= Load;
end
else
OneWireIO <= IdleS;
end
// New state added to be sure the strong pullup will be disabled
// before the OW pulldown turns on
ClrLowDone:
begin
LOW_DONE <= 0;
if (!LOW_DONE)
OneWireIO <= Load;
end
// Load transfers the transmit buffer to the transmit shift register,
// then clears the transmit shift register empty interrupt. The next
// state is then DQLOW.
Load:
begin
xmit_shiftreg <= xmit_buffer;
rcvr_shiftreg <= 0;
temt <= 1'b0;
LOW_DONE <= 0;
OneWireIO <= CheckOW;
end
// Checks OW value before sending out every bit to see if line
// was forced low by some other means at an incorrect time
CheckOW:
begin
OneWireIO <= DQLOW;
//TimeSlotCnt <= TimeSlotCnt + 1;
if (!DQ_IN)
SET_IOSHRT <= 1;
end
// DQLOW pulls the DQ line low for 1us, beginning a timeslot.
// If sr_a is 0, it is a normal write/read operation. If sr_a
// is a 1, then you must go into Search ROM accelerator mode.
// If OD is 1, the part is in overdrive and must perform
// ODWrites instead of normal Writes while OD is 0.
DQLOW:
begin
TimeSlotCnt <= TimeSlotCnt + 1;
LOW_DONE <= 0;
if (OD)
begin
//if(TimeSlotCnt==bit_ts_writeone_high_od)
//begin
if(!sr_a)
begin
case(index)
0:
if(!xmit_shiftreg[0])
OneWireIO <= ODWriteZero;
else
OneWireIO <= ODWriteOne;
1:
if(!xmit_shiftreg[1])
OneWireIO <= ODWriteZero;
else
OneWireIO <= ODWriteOne;
2:
if(!xmit_shiftreg[2])
OneWireIO <= ODWriteZero;
else
OneWireIO <= ODWriteOne;
3:
if(!xmit_shiftreg[3])
OneWireIO <= ODWriteZero;
else
OneWireIO <= ODWriteOne;
4:
if(!xmit_shiftreg[4])
OneWireIO <= ODWriteZero;
else
OneWireIO <= ODWriteOne;
5:
if(!xmit_shiftreg[5])
OneWireIO <= ODWriteZero;
else
OneWireIO <= ODWriteOne;
6:
if(!xmit_shiftreg[6])
OneWireIO <= ODWriteZero;
else
OneWireIO <= ODWriteOne;
7:
if(!xmit_shiftreg[7])
OneWireIO <= ODWriteZero;
else
OneWireIO <= ODWriteOne;
endcase // case(index)
end
else // Search Rom Accelerator mode
OneWireIO <= ReadBit;
end
//end
else if(((TimeSlotCnt==bit_ts_writeone_high) && !LLM) ||
((TimeSlotCnt==bit_ts_writeone_high_ll) && LLM))
begin
if(!sr_a) // Normal write
begin
case(index)
0:
if(!xmit_shiftreg[0])
OneWireIO <= WriteZero;
else
OneWireIO <= WriteOne;
1:
if(!xmit_shiftreg[1])
OneWireIO <= WriteZero;
else
OneWireIO <= WriteOne;
2:
if(!xmit_shiftreg[2])
OneWireIO <= WriteZero;
else
OneWireIO <= WriteOne;
3:
if(!xmit_shiftreg[3])
OneWireIO <= WriteZero;
else
OneWireIO <= WriteOne;
4:
if(!xmit_shiftreg[4])
OneWireIO <= WriteZero;
else
OneWireIO <= WriteOne;
5:
if(!xmit_shiftreg[5])
OneWireIO <= WriteZero;
else
OneWireIO <= WriteOne;
6:
if(!xmit_shiftreg[6])
OneWireIO <= WriteZero;
else
OneWireIO <= WriteOne;
7:
if(!xmit_shiftreg[7])
OneWireIO <= WriteZero;
else
OneWireIO <= WriteOne;
endcase // case(index)
end
else // Search Rom Accelerator mode
OneWireIO <= ReadBit;
end
end
// WriteZero and WriteOne are identical, except for what they do to
// DQ (assigned in concurrent assignments). They both read DQ after
// 15us, then move on to wait for the end of the timeslot, unless
// running in Long Line mode which extends the sample time out to 22
WriteZero:
begin
TimeSlotCnt <= TimeSlotCnt + 1;
if(((TimeSlotCnt==bit_ts_sample) && !sr_a && !LLM) ||
((TimeSlotCnt==bit_ts_sample_ll) && !sr_a && LLM))
case(index)
0:
rcvr_shiftreg[0] <= DQ_IN;
1:
rcvr_shiftreg[1] <= DQ_IN;
2:
rcvr_shiftreg[2] <= DQ_IN;
3:
rcvr_shiftreg[3] <= DQ_IN;
4:
rcvr_shiftreg[4] <= DQ_IN;
5:
rcvr_shiftreg[5] <= DQ_IN;
6:
rcvr_shiftreg[6] <= DQ_IN;
7:
rcvr_shiftreg[7] <= DQ_IN;
endcase
if(TimeSlotCnt == bit_ts_writezero_high) //62 7_25_01
OneWireIO <= WaitTS;
if(DQ_IN)
LOW_DONE <= 1;
end
WriteOne:
begin
TimeSlotCnt <= TimeSlotCnt + 1;
if(((TimeSlotCnt==bit_ts_sample) && !sr_a && !LLM) ||
((TimeSlotCnt==bit_ts_sample_ll) && !sr_a && LLM))
case(index)
0:
rcvr_shiftreg[0] <= DQ_IN;
1:
rcvr_shiftreg[1] <= DQ_IN;
2:
rcvr_shiftreg[2] <= DQ_IN;
3:
rcvr_shiftreg[3] <= DQ_IN;
4:
rcvr_shiftreg[4] <= DQ_IN;
5:
rcvr_shiftreg[5] <= DQ_IN;
6:
rcvr_shiftreg[6] <= DQ_IN;
7:
rcvr_shiftreg[7] <= DQ_IN;
endcase
if(TimeSlotCnt == bit_ts_writezero_high) //62 7_25_01
OneWireIO <= WaitTS;
if(DQ_IN)
LOW_DONE <= 1;
end
// ADDED ODWRITE states here GAG
// ODWriteZero and ODWriteOne are identical, except for what they
// do to DQ (assigned in concurrent assignments). They both read
// DQ after 3us, then move on to wait for the end of the timeslot.
ODWriteZero:
begin
TimeSlotCnt <= TimeSlotCnt + 1;
if((TimeSlotCnt == bit_ts_sample_od) && !sr_a)
case(index)
0:
rcvr_shiftreg[0] <= DQ_IN;
1:
rcvr_shiftreg[1] <= DQ_IN;
2:
rcvr_shiftreg[2] <= DQ_IN;
3:
rcvr_shiftreg[3] <= DQ_IN;
4:
rcvr_shiftreg[4] <= DQ_IN;
5:
rcvr_shiftreg[5] <= DQ_IN;
6:
rcvr_shiftreg[6] <= DQ_IN;
7:
rcvr_shiftreg[7] <= DQ_IN;
endcase
if(TimeSlotCnt == bit_ts_writezero_high_od)
OneWireIO <= WaitTS;
if(DQ_IN)
LOW_DONE <= 1;
end
ODWriteOne:
begin
TimeSlotCnt <= TimeSlotCnt + 1;
if((TimeSlotCnt == bit_ts_sample_od) && !sr_a)
case(index)
0:
rcvr_shiftreg[0] <= DQ_IN;
1:
rcvr_shiftreg[1] <= DQ_IN;
2:
rcvr_shiftreg[2] <= DQ_IN;
3:
rcvr_shiftreg[3] <= DQ_IN;
4:
rcvr_shiftreg[4] <= DQ_IN;
5:
rcvr_shiftreg[5] <= DQ_IN;
6:
rcvr_shiftreg[6] <= DQ_IN;
7:
rcvr_shiftreg[7] <= DQ_IN;
endcase
if(TimeSlotCnt == bit_ts_writezero_high_od)
OneWireIO <= WaitTS;
if(DQ_IN)
LOW_DONE <= 1;
end
// ReadBit used by the SRA to do the required bit reads
ReadBit:
begin
TimeSlotCnt <= TimeSlotCnt + 1;
if(DQ_IN)
LOW_DONE <= 1;
if(OD)
begin
if(TimeSlotCnt == bit_ts_sample_od)
if(!First)
BitRead1 <= DQ_IN;
else
BitRead2 <= DQ_IN;
if(TimeSlotCnt == bit_ts_writezero_high_od) //7 7_25_01
OneWireIO <= FirstPassSR;
end
else
begin
if(((TimeSlotCnt == bit_ts_sample)&&!LLM) || ((TimeSlotCnt == bit_ts_sample_ll)&&LLM))
if(!First)
BitRead1 <= DQ_IN;
else
BitRead2 <= DQ_IN;
if(TimeSlotCnt == bit_ts_writezero_high)
OneWireIO <= FirstPassSR;
end
end
// FirstPassSR decides whether to do another read or to do the
// bit write.
FirstPassSR:
begin
TimeSlotCnt <= TimeSlotCnt + 1;
LOW_DONE <= 0;
if(OD)
begin
if(TimeSlotCnt == bit_ts_end_od)
begin
TimeSlotCnt <= 0;
if(!First)
begin
First <= 1'b1;
OneWireIO <= DQLOW;
end
else
begin
OneWireIO <= WriteBitSR;
end
end
end
else
begin
if(((TimeSlotCnt==bit_ts_end) && !LLM) || ((TimeSlotCnt==bit_ts_end_ll) && LLM))
begin
TimeSlotCnt <= 0;
if(!First)
begin
First <= 1'b1;
OneWireIO <= DQLOW;
end
else
begin
OneWireIO <= WriteBitSR;
end // else: !if(!First)
end
end
end
// WriteBitSR will now determine the bit necessary to write
// for the Search ROM to proceed.
WriteBitSR:
begin
case({BitRead1,BitRead2})
2'b00: begin
case(index)
0: begin
BitWrite <= xmit_shiftreg[1];
rcvr_shiftreg[0] <= 1'b1;
end
1: begin
BitWrite <= xmit_shiftreg[2];
rcvr_shiftreg[1] <= 1'b1;
end
2: begin
BitWrite <= xmit_shiftreg[3];
rcvr_shiftreg[2] <= 1'b1;
end
3: begin
BitWrite <= xmit_shiftreg[4];
rcvr_shiftreg[3] <= 1'b1;
end
4: begin
BitWrite <= xmit_shiftreg[5];
rcvr_shiftreg[4] <= 1'b1;
end
5: begin
BitWrite <= xmit_shiftreg[6];
rcvr_shiftreg[5] <= 1'b1;
end
6: begin
BitWrite <= xmit_shiftreg[7];
rcvr_shiftreg[6] <= 1'b1;
end
7: begin
BitWrite <= xmit_shiftreg[0];
rcvr_shiftreg[7] <= 1'b1;
end
endcase
end
2'b01: begin
BitWrite <= 1'b0;
case(index)
0:
rcvr_shiftreg[0] <= 1'b0;
1:
rcvr_shiftreg[1] <= 1'b0;
2:
rcvr_shiftreg[2] <= 1'b0;
3:
rcvr_shiftreg[3] <= 1'b0;
4:
rcvr_shiftreg[4] <= 1'b0;
5:
rcvr_shiftreg[5] <= 1'b0;
6:
rcvr_shiftreg[6] <= 1'b0;
7:
rcvr_shiftreg[7] <= 1'b0;
endcase
end
2'b10: begin
BitWrite <= 1'b1;
case(index)
0:
rcvr_shiftreg[0] <= 1'b0;
1:
rcvr_shiftreg[1] <= 1'b0;
2:
rcvr_shiftreg[2] <= 1'b0;
3:
rcvr_shiftreg[3] <= 1'b0;
4:
rcvr_shiftreg[4] <= 1'b0;
5:
rcvr_shiftreg[5] <= 1'b0;
6:
rcvr_shiftreg[6] <= 1'b0;
7:
rcvr_shiftreg[7] <= 1'b0;
endcase
end
2'b11: begin
BitWrite <= 1'b1;
case(index)
0: begin
rcvr_shiftreg[0] <= 1'b1;
rcvr_shiftreg[1] <= 1'b1;
end
1: begin
rcvr_shiftreg[1] <= 1'b1;
rcvr_shiftreg[2] <= 1'b1;
end
2: begin
rcvr_shiftreg[2] <= 1'b1;
rcvr_shiftreg[3] <= 1'b1;
end
3: begin
rcvr_shiftreg[3] <= 1'b1;
rcvr_shiftreg[4] <= 1'b1;
end
4: begin
rcvr_shiftreg[4] <= 1'b1;
rcvr_shiftreg[5] <= 1'b1;
end
5: begin
rcvr_shiftreg[5] <= 1'b1;
rcvr_shiftreg[6] <= 1'b1;
end
6: begin
rcvr_shiftreg[6] <= 1'b1;
rcvr_shiftreg[7] <= 1'b1;
end
7: begin
rcvr_shiftreg[7] <= 1'b1;
rcvr_shiftreg[0] <= 1'b1;
end
endcase
end
endcase // case({BitRead1,BitRead2})
OneWireIO <= WriteBit;
end
// WriteBit actually writes the chosen bit to the One Wire bus.
WriteBit:
begin
TimeSlotCnt <= TimeSlotCnt + 1;
case(index)
0:
rcvr_shiftreg[1] <= BitWrite;
1:
rcvr_shiftreg[2] <= BitWrite;
2:
rcvr_shiftreg[3] <= BitWrite;
3:
rcvr_shiftreg[4] <= BitWrite;
4:
rcvr_shiftreg[5] <= BitWrite;
5:
rcvr_shiftreg[6] <= BitWrite;
6:
rcvr_shiftreg[7] <= BitWrite;
7:
rcvr_shiftreg[0] <= BitWrite;
endcase
if(!BitWrite)
begin
if(OD)
OneWireIO <= ODWriteZero;
else
OneWireIO <= WriteZero;
end
else
begin
if(OD && (TimeSlotCnt == bit_ts_writeone_high_od))
OneWireIO <= ODWriteOne;
else if (!LLM && (TimeSlotCnt == bit_ts_writeone_high)) //5 7_25_01
OneWireIO <= WriteOne;
else if (LLM && (TimeSlotCnt == bit_ts_writeone_high_ll))
OneWireIO <= WriteOne;
end
end
// WaitTS waits until the timeslot is completed, 80us. When done with
// that timeslot, the index will be incremented.
WaitTS:
begin
SET_IOSHRT <= 0;
TimeSlotCnt <= TimeSlotCnt + 1;
if(OD)
begin
if(TimeSlotCnt == bit_ts_end_od) //11 7_25_01
OneWireIO <= IndexInc;
end
else
if(((TimeSlotCnt == bit_ts_end) && !LLM) || ((TimeSlotCnt==bit_ts_end_ll) && LLM))
OneWireIO <= IndexInc;
if(DQ_IN)
LOW_DONE <= 1;
end
// IndexInc incs the index by 1 if normal write, by 2 if in SRA
IndexInc:
begin
if(!sr_a)
index <= index + 1;
else
begin
index <= index + 2;
First <= 1'b0;
end
if(BIT_CTL || (index == 8-1 && !sr_a) || (index == 8-2 && sr_a) )
begin // Added BIT_CTL - GAG
byte_done <= 1'b1;
OneWireIO <= UpdateBuff;
end
else
begin
if((index == 7-1) && !sr_a)
last_rcvr_bit <= 1'b1;
else
if((index == 6-2) && sr_a)
last_rcvr_bit <= 1'b1;
OneWireIO <= DQLOW;
TimeSlotCnt <= 0;
end
LOW_DONE <= 0;
end
UpdateBuff:
begin
OneWireIO <= IdleS;
if(DQ_IN && STP_SPLY)
LOW_DONE <= 1;
end
endcase
endmodule
|
//-----------------------------------------------------------------
// AltOR32
// Alternative Lightweight OpenRisc
// V2.0
// Ultra-Embedded.com
// Copyright 2011 - 2013
//
// Email: [email protected]
//
// License: LGPL
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2013 Ultra-Embedded.com
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, write to the
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
// Boston, MA 02111-1307 USA
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Module:
//-----------------------------------------------------------------
module dmem_mux3
(
// Outputs
output reg [31:0] out0_addr_o,
output reg [31:0] out0_data_o,
input [31:0] out0_data_i,
output reg [3:0] out0_sel_o,
output reg out0_we_o,
output reg out0_stb_o,
output reg out0_cyc_o,
output reg [2:0] out0_cti_o,
input out0_ack_i,
input out0_stall_i,
output reg [31:0] out1_addr_o,
output reg [31:0] out1_data_o,
input [31:0] out1_data_i,
output reg [3:0] out1_sel_o,
output reg out1_we_o,
output reg out1_stb_o,
output reg out1_cyc_o,
output reg [2:0] out1_cti_o,
input out1_ack_i,
input out1_stall_i,
output reg [31:0] out2_addr_o,
output reg [31:0] out2_data_o,
input [31:0] out2_data_i,
output reg [3:0] out2_sel_o,
output reg out2_we_o,
output reg out2_stb_o,
output reg out2_cyc_o,
output reg [2:0] out2_cti_o,
input out2_ack_i,
input out2_stall_i,
// Input
input [31:0] mem_addr_i,
input [31:0] mem_data_i,
output reg[31:0] mem_data_o,
input [3:0] mem_sel_i,
input mem_we_i,
input mem_stb_i,
input mem_cyc_i,
input [2:0] mem_cti_i,
output reg mem_ack_o,
output reg mem_stall_o
);
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
parameter ADDR_MUX_START = 28;
//-----------------------------------------------------------------
// Request
//-----------------------------------------------------------------
always @ *
begin
out0_addr_o = 32'h00000000;
out0_data_o = 32'h00000000;
out0_sel_o = 4'b0000;
out0_we_o = 1'b0;
out0_stb_o = 1'b0;
out0_cyc_o = 1'b0;
out0_cti_o = 3'b0;
out1_addr_o = 32'h00000000;
out1_data_o = 32'h00000000;
out1_sel_o = 4'b0000;
out1_we_o = 1'b0;
out1_stb_o = 1'b0;
out1_cyc_o = 1'b0;
out1_cti_o = 3'b0;
out2_addr_o = 32'h00000000;
out2_data_o = 32'h00000000;
out2_sel_o = 4'b0000;
out2_we_o = 1'b0;
out2_stb_o = 1'b0;
out2_cyc_o = 1'b0;
out2_cti_o = 3'b0;
case (mem_addr_i[ADDR_MUX_START+2-1:ADDR_MUX_START])
2'd0:
begin
out0_addr_o = mem_addr_i;
out0_data_o = mem_data_i;
out0_sel_o = mem_sel_i;
out0_we_o = mem_we_i;
out0_stb_o = mem_stb_i;
out0_cyc_o = mem_cyc_i;
out0_cti_o = mem_cti_i;
end
2'd1:
begin
out1_addr_o = mem_addr_i;
out1_data_o = mem_data_i;
out1_sel_o = mem_sel_i;
out1_we_o = mem_we_i;
out1_stb_o = mem_stb_i;
out1_cyc_o = mem_cyc_i;
out1_cti_o = mem_cti_i;
end
2'd2:
begin
out2_addr_o = mem_addr_i;
out2_data_o = mem_data_i;
out2_sel_o = mem_sel_i;
out2_we_o = mem_we_i;
out2_stb_o = mem_stb_i;
out2_cyc_o = mem_cyc_i;
out2_cti_o = mem_cti_i;
end
default :
;
endcase
end
//-----------------------------------------------------------------
// Response
//-----------------------------------------------------------------
always @ *
begin
case (mem_addr_i[ADDR_MUX_START+2-1:ADDR_MUX_START])
2'd0:
begin
mem_data_o = out0_data_i;
mem_stall_o = out0_stall_i;
mem_ack_o = out0_ack_i;
end
2'd1:
begin
mem_data_o = out1_data_i;
mem_stall_o = out1_stall_i;
mem_ack_o = out1_ack_i;
end
2'd2:
begin
mem_data_o = out2_data_i;
mem_stall_o = out2_stall_i;
mem_ack_o = out2_ack_i;
end
default :
begin
mem_data_o = 32'h00000000;
mem_stall_o = 1'b0;
mem_ack_o = 1'b0;
end
endcase
end
endmodule
|
// -------------------------------------------------------------
//
// File Name: /Users/thilina/ConvLayerAccelerator/64_7/codegen/mac/hdlsrc/mac_fixpt.v
// Created: 2017-03-17 17:53:20
//
// Generated by MATLAB 9.1, MATLAB Coder 3.2 and HDL Coder 3.9
//
//
//
// -- -------------------------------------------------------------
// -- Rate and Clocking Details
// -- -------------------------------------------------------------
// Design base rate: 1
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: mac_fixpt
// Source Path: mac_fixpt
// Hierarchy Level: 0
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module mac_fixpt
(
M_0,
M_1,
M_2,
M_3,
M_4,
M_5,
M_6,
M_7,
M_8,
M_9,
M_10,
M_11,
M_12,
M_13,
M_14,
M_15,
M_16,
M_17,
M_18,
M_19,
M_20,
M_21,
M_22,
M_23,
M_24,
M_25,
M_26,
M_27,
M_28,
M_29,
M_30,
M_31,
M_32,
M_33,
M_34,
M_35,
M_36,
M_37,
M_38,
M_39,
M_40,
M_41,
M_42,
M_43,
M_44,
M_45,
M_46,
M_47,
M_48,
M_49,
M_50,
M_51,
M_52,
M_53,
M_54,
M_55,
M_56,
M_57,
M_58,
M_59,
M_60,
M_61,
M_62,
M_63,
N_0,
N_1,
N_2,
N_3,
N_4,
N_5,
N_6,
W_0,
W_1,
W_2,
W_3,
W_4,
W_5,
W_6,
Tm,
Tn,
M_out_0,
M_out_1,
M_out_2,
M_out_3,
M_out_4,
M_out_5,
M_out_6,
M_out_7,
M_out_8,
M_out_9,
M_out_10,
M_out_11,
M_out_12,
M_out_13,
M_out_14,
M_out_15,
M_out_16,
M_out_17,
M_out_18,
M_out_19,
M_out_20,
M_out_21,
M_out_22,
M_out_23,
M_out_24,
M_out_25,
M_out_26,
M_out_27,
M_out_28,
M_out_29,
M_out_30,
M_out_31,
M_out_32,
M_out_33,
M_out_34,
M_out_35,
M_out_36,
M_out_37,
M_out_38,
M_out_39,
M_out_40,
M_out_41,
M_out_42,
M_out_43,
M_out_44,
M_out_45,
M_out_46,
M_out_47,
M_out_48,
M_out_49,
M_out_50,
M_out_51,
M_out_52,
M_out_53,
M_out_54,
M_out_55,
M_out_56,
M_out_57,
M_out_58,
M_out_59,
M_out_60,
M_out_61,
M_out_62,
M_out_63
);
input M_0; // ufix1
input M_1; // ufix1
input M_2; // ufix1
input M_3; // ufix1
input M_4; // ufix1
input M_5; // ufix1
input M_6; // ufix1
input M_7; // ufix1
input M_8; // ufix1
input M_9; // ufix1
input M_10; // ufix1
input M_11; // ufix1
input M_12; // ufix1
input M_13; // ufix1
input M_14; // ufix1
input M_15; // ufix1
input M_16; // ufix1
input M_17; // ufix1
input M_18; // ufix1
input M_19; // ufix1
input M_20; // ufix1
input M_21; // ufix1
input M_22; // ufix1
input M_23; // ufix1
input M_24; // ufix1
input M_25; // ufix1
input M_26; // ufix1
input M_27; // ufix1
input M_28; // ufix1
input M_29; // ufix1
input M_30; // ufix1
input M_31; // ufix1
input M_32; // ufix1
input M_33; // ufix1
input M_34; // ufix1
input M_35; // ufix1
input M_36; // ufix1
input M_37; // ufix1
input M_38; // ufix1
input M_39; // ufix1
input M_40; // ufix1
input M_41; // ufix1
input M_42; // ufix1
input M_43; // ufix1
input M_44; // ufix1
input M_45; // ufix1
input M_46; // ufix1
input M_47; // ufix1
input M_48; // ufix1
input M_49; // ufix1
input M_50; // ufix1
input M_51; // ufix1
input M_52; // ufix1
input M_53; // ufix1
input M_54; // ufix1
input M_55; // ufix1
input M_56; // ufix1
input M_57; // ufix1
input M_58; // ufix1
input M_59; // ufix1
input M_60; // ufix1
input M_61; // ufix1
input M_62; // ufix1
input M_63; // ufix1
input N_0; // ufix1
input N_1; // ufix1
input N_2; // ufix1
input N_3; // ufix1
input N_4; // ufix1
input N_5; // ufix1
input N_6; // ufix1
input [13:0] W_0; // ufix14_En13
input [13:0] W_1; // ufix14_En13
input [13:0] W_2; // ufix14_En13
input [13:0] W_3; // ufix14_En13
input [13:0] W_4; // ufix14_En13
input [13:0] W_5; // ufix14_En13
input [13:0] W_6; // ufix14_En13
input [6:0] Tm; // ufix7
input [2:0] Tn; // ufix3
output [13:0] M_out_0; // ufix14_En12
output [13:0] M_out_1; // ufix14_En12
output [13:0] M_out_2; // ufix14_En12
output [13:0] M_out_3; // ufix14_En12
output [13:0] M_out_4; // ufix14_En12
output [13:0] M_out_5; // ufix14_En12
output [13:0] M_out_6; // ufix14_En12
output [13:0] M_out_7; // ufix14_En12
output [13:0] M_out_8; // ufix14_En12
output [13:0] M_out_9; // ufix14_En12
output [13:0] M_out_10; // ufix14_En12
output [13:0] M_out_11; // ufix14_En12
output [13:0] M_out_12; // ufix14_En12
output [13:0] M_out_13; // ufix14_En12
output [13:0] M_out_14; // ufix14_En12
output [13:0] M_out_15; // ufix14_En12
output [13:0] M_out_16; // ufix14_En12
output [13:0] M_out_17; // ufix14_En12
output [13:0] M_out_18; // ufix14_En12
output [13:0] M_out_19; // ufix14_En12
output [13:0] M_out_20; // ufix14_En12
output [13:0] M_out_21; // ufix14_En12
output [13:0] M_out_22; // ufix14_En12
output [13:0] M_out_23; // ufix14_En12
output [13:0] M_out_24; // ufix14_En12
output [13:0] M_out_25; // ufix14_En12
output [13:0] M_out_26; // ufix14_En12
output [13:0] M_out_27; // ufix14_En12
output [13:0] M_out_28; // ufix14_En12
output [13:0] M_out_29; // ufix14_En12
output [13:0] M_out_30; // ufix14_En12
output [13:0] M_out_31; // ufix14_En12
output [13:0] M_out_32; // ufix14_En12
output [13:0] M_out_33; // ufix14_En12
output [13:0] M_out_34; // ufix14_En12
output [13:0] M_out_35; // ufix14_En12
output [13:0] M_out_36; // ufix14_En12
output [13:0] M_out_37; // ufix14_En12
output [13:0] M_out_38; // ufix14_En12
output [13:0] M_out_39; // ufix14_En12
output [13:0] M_out_40; // ufix14_En12
output [13:0] M_out_41; // ufix14_En12
output [13:0] M_out_42; // ufix14_En12
output [13:0] M_out_43; // ufix14_En12
output [13:0] M_out_44; // ufix14_En12
output [13:0] M_out_45; // ufix14_En12
output [13:0] M_out_46; // ufix14_En12
output [13:0] M_out_47; // ufix14_En12
output [13:0] M_out_48; // ufix14_En12
output [13:0] M_out_49; // ufix14_En12
output [13:0] M_out_50; // ufix14_En12
output [13:0] M_out_51; // ufix14_En12
output [13:0] M_out_52; // ufix14_En12
output [13:0] M_out_53; // ufix14_En12
output [13:0] M_out_54; // ufix14_En12
output [13:0] M_out_55; // ufix14_En12
output [13:0] M_out_56; // ufix14_En12
output [13:0] M_out_57; // ufix14_En12
output [13:0] M_out_58; // ufix14_En12
output [13:0] M_out_59; // ufix14_En12
output [13:0] M_out_60; // ufix14_En12
output [13:0] M_out_61; // ufix14_En12
output [13:0] M_out_62; // ufix14_En12
output [13:0] M_out_63; // ufix14_En12
wire [0:63] M; // ufix1 [64]
wire [0:6] N; // ufix1 [7]
wire [13:0] W [0:6]; // ufix14_En13 [7]
reg [13:0] M_out [0:63]; // ufix14_En12 [64]
reg [13:0] mac_fixpt_M_local [0:63]; // ufix14_En12 [64]
reg [13:0] mac_fixpt_M_local_0 [0:63]; // ufix14_En12 [64]
reg signed [31:0] mac_fixpt_t_0; // int32
reg signed [31:0] mac_fixpt_t_1; // int32
reg signed [31:0] mac_fixpt_t_2; // int32
reg [15:0] mac_fixpt_add_cast; // ufix16_En13
reg [13:0] mac_fixpt_t_3; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_0; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1; // ufix16_En13
reg [15:0] mac_fixpt_add_temp; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_2; // ufix16_En13
reg [13:0] mac_fixpt_t_4; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_3; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_4; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_0; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_5; // ufix16_En13
reg [13:0] mac_fixpt_t_5; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_6; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_7; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_1; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_8; // ufix16_En13
reg [13:0] mac_fixpt_t_6; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_9; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_10; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_2; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_11; // ufix16_En13
reg [13:0] mac_fixpt_t_7; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_12; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_13; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_3; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_14; // ufix16_En13
reg [13:0] mac_fixpt_t_8; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_15; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_16; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_4; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_17; // ufix16_En13
reg [13:0] mac_fixpt_t_9; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_18; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_19; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_5; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_20; // ufix16_En13
reg [13:0] mac_fixpt_t_10; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_21; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_22; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_6; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_23; // ufix16_En13
reg [13:0] mac_fixpt_t_11; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_24; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_25; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_7; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_26; // ufix16_En13
reg [13:0] mac_fixpt_t_12; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_27; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_28; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_8; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_29; // ufix16_En13
reg [13:0] mac_fixpt_t_13; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_30; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_31; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_9; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_32; // ufix16_En13
reg [13:0] mac_fixpt_t_14; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_33; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_34; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_10; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_35; // ufix16_En13
reg [13:0] mac_fixpt_t_15; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_36; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_37; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_11; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_38; // ufix16_En13
reg [13:0] mac_fixpt_t_16; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_39; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_40; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_12; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_41; // ufix16_En13
reg [13:0] mac_fixpt_t_17; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_42; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_43; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_13; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_44; // ufix16_En13
reg [13:0] mac_fixpt_t_18; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_45; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_46; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_14; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_47; // ufix16_En13
reg [13:0] mac_fixpt_t_19; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_48; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_49; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_15; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_50; // ufix16_En13
reg [13:0] mac_fixpt_t_20; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_51; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_52; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_16; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_53; // ufix16_En13
reg [13:0] mac_fixpt_t_21; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_54; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_55; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_17; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_56; // ufix16_En13
reg [13:0] mac_fixpt_t_22; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_57; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_58; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_18; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_59; // ufix16_En13
reg [13:0] mac_fixpt_t_23; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_60; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_61; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_19; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_62; // ufix16_En13
reg [13:0] mac_fixpt_t_24; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_63; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_64; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_20; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_65; // ufix16_En13
reg [13:0] mac_fixpt_t_25; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_66; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_67; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_21; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_68; // ufix16_En13
reg [13:0] mac_fixpt_t_26; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_69; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_70; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_22; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_71; // ufix16_En13
reg [13:0] mac_fixpt_t_27; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_72; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_73; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_23; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_74; // ufix16_En13
reg [13:0] mac_fixpt_t_28; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_75; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_76; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_24; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_77; // ufix16_En13
reg [13:0] mac_fixpt_t_29; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_78; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_79; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_25; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_80; // ufix16_En13
reg [13:0] mac_fixpt_t_30; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_81; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_82; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_26; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_83; // ufix16_En13
reg [13:0] mac_fixpt_t_31; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_84; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_85; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_27; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_86; // ufix16_En13
reg [13:0] mac_fixpt_t_32; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_87; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_88; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_28; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_89; // ufix16_En13
reg [13:0] mac_fixpt_t_33; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_90; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_91; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_29; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_92; // ufix16_En13
reg [13:0] mac_fixpt_t_34; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_93; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_94; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_30; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_95; // ufix16_En13
reg [13:0] mac_fixpt_t_35; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_96; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_97; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_31; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_98; // ufix16_En13
reg [13:0] mac_fixpt_t_36; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_99; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_100; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_32; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_101; // ufix16_En13
reg [13:0] mac_fixpt_t_37; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_102; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_103; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_33; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_104; // ufix16_En13
reg [13:0] mac_fixpt_t_38; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_105; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_106; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_34; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_107; // ufix16_En13
reg [13:0] mac_fixpt_t_39; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_108; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_109; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_35; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_110; // ufix16_En13
reg [13:0] mac_fixpt_t_40; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_111; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_112; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_36; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_113; // ufix16_En13
reg [13:0] mac_fixpt_t_41; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_114; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_115; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_37; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_116; // ufix16_En13
reg [13:0] mac_fixpt_t_42; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_117; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_118; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_38; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_119; // ufix16_En13
reg [13:0] mac_fixpt_t_43; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_120; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_121; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_39; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_122; // ufix16_En13
reg [13:0] mac_fixpt_t_44; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_123; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_124; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_40; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_125; // ufix16_En13
reg [13:0] mac_fixpt_t_45; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_126; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_127; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_41; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_128; // ufix16_En13
reg [13:0] mac_fixpt_t_46; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_129; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_130; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_42; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_131; // ufix16_En13
reg [13:0] mac_fixpt_t_47; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_132; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_133; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_43; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_134; // ufix16_En13
reg [13:0] mac_fixpt_t_48; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_135; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_136; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_44; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_137; // ufix16_En13
reg [13:0] mac_fixpt_t_49; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_138; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_139; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_45; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_140; // ufix16_En13
reg [13:0] mac_fixpt_t_50; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_141; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_142; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_46; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_143; // ufix16_En13
reg [13:0] mac_fixpt_t_51; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_144; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_145; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_47; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_146; // ufix16_En13
reg [13:0] mac_fixpt_t_52; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_147; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_148; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_48; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_149; // ufix16_En13
reg [13:0] mac_fixpt_t_53; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_150; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_151; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_49; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_152; // ufix16_En13
reg [13:0] mac_fixpt_t_54; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_153; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_154; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_50; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_155; // ufix16_En13
reg [13:0] mac_fixpt_t_55; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_156; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_157; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_51; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_158; // ufix16_En13
reg [13:0] mac_fixpt_t_56; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_159; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_160; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_52; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_161; // ufix16_En13
reg [13:0] mac_fixpt_t_57; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_162; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_163; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_53; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_164; // ufix16_En13
reg [13:0] mac_fixpt_t_58; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_165; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_166; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_54; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_167; // ufix16_En13
reg [13:0] mac_fixpt_t_59; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_168; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_169; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_55; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_170; // ufix16_En13
reg [13:0] mac_fixpt_t_60; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_171; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_172; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_56; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_173; // ufix16_En13
reg [13:0] mac_fixpt_t_61; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_174; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_175; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_57; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_176; // ufix16_En13
reg [13:0] mac_fixpt_t_62; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_177; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_178; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_58; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_179; // ufix16_En13
reg [13:0] mac_fixpt_t_63; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_180; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_181; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_59; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_182; // ufix16_En13
reg [13:0] mac_fixpt_t_64; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_183; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_184; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_60; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_185; // ufix16_En13
reg [13:0] mac_fixpt_t_65; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_186; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_187; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_61; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_188; // ufix16_En13
reg [13:0] mac_fixpt_t_66; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_189; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_190; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_62; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_191; // ufix16_En13
reg [13:0] mac_fixpt_t_67; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_192; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_193; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_63; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_194; // ufix16_En13
reg [13:0] mac_fixpt_t_68; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_195; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_196; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_64; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_197; // ufix16_En13
reg [13:0] mac_fixpt_t_69; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_198; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_199; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_65; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_200; // ufix16_En13
reg [13:0] mac_fixpt_t_70; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_201; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_202; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_66; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_203; // ufix16_En13
reg [13:0] mac_fixpt_t_71; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_204; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_205; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_67; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_206; // ufix16_En13
reg [13:0] mac_fixpt_t_72; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_207; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_208; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_68; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_209; // ufix16_En13
reg [13:0] mac_fixpt_t_73; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_210; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_211; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_69; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_212; // ufix16_En13
reg [13:0] mac_fixpt_t_74; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_213; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_214; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_70; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_215; // ufix16_En13
reg [13:0] mac_fixpt_t_75; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_216; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_217; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_71; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_218; // ufix16_En13
reg [13:0] mac_fixpt_t_76; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_219; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_220; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_72; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_221; // ufix16_En13
reg [13:0] mac_fixpt_t_77; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_222; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_223; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_73; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_224; // ufix16_En13
reg [13:0] mac_fixpt_t_78; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_225; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_226; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_74; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_227; // ufix16_En13
reg [13:0] mac_fixpt_t_79; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_228; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_229; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_75; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_230; // ufix16_En13
reg [13:0] mac_fixpt_t_80; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_231; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_232; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_76; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_233; // ufix16_En13
reg [13:0] mac_fixpt_t_81; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_234; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_235; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_77; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_236; // ufix16_En13
reg [13:0] mac_fixpt_t_82; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_237; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_238; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_78; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_239; // ufix16_En13
reg [13:0] mac_fixpt_t_83; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_240; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_241; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_79; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_242; // ufix16_En13
reg [13:0] mac_fixpt_t_84; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_243; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_244; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_80; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_245; // ufix16_En13
reg [13:0] mac_fixpt_t_85; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_246; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_247; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_81; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_248; // ufix16_En13
reg [13:0] mac_fixpt_t_86; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_249; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_250; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_82; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_251; // ufix16_En13
reg [13:0] mac_fixpt_t_87; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_252; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_253; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_83; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_254; // ufix16_En13
reg [13:0] mac_fixpt_t_88; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_255; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_256; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_84; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_257; // ufix16_En13
reg [13:0] mac_fixpt_t_89; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_258; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_259; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_85; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_260; // ufix16_En13
reg [13:0] mac_fixpt_t_90; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_261; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_262; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_86; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_263; // ufix16_En13
reg [13:0] mac_fixpt_t_91; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_264; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_265; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_87; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_266; // ufix16_En13
reg [13:0] mac_fixpt_t_92; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_267; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_268; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_88; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_269; // ufix16_En13
reg [13:0] mac_fixpt_t_93; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_270; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_271; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_89; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_272; // ufix16_En13
reg [13:0] mac_fixpt_t_94; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_273; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_274; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_90; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_275; // ufix16_En13
reg [13:0] mac_fixpt_t_95; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_276; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_277; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_91; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_278; // ufix16_En13
reg [13:0] mac_fixpt_t_96; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_279; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_280; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_92; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_281; // ufix16_En13
reg [13:0] mac_fixpt_t_97; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_282; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_283; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_93; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_284; // ufix16_En13
reg [13:0] mac_fixpt_t_98; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_285; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_286; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_94; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_287; // ufix16_En13
reg [13:0] mac_fixpt_t_99; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_288; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_289; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_95; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_290; // ufix16_En13
reg [13:0] mac_fixpt_t_100; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_291; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_292; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_96; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_293; // ufix16_En13
reg [13:0] mac_fixpt_t_101; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_294; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_295; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_97; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_296; // ufix16_En13
reg [13:0] mac_fixpt_t_102; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_297; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_298; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_98; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_299; // ufix16_En13
reg [13:0] mac_fixpt_t_103; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_300; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_301; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_99; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_302; // ufix16_En13
reg [13:0] mac_fixpt_t_104; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_303; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_304; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_100; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_305; // ufix16_En13
reg [13:0] mac_fixpt_t_105; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_306; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_307; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_101; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_308; // ufix16_En13
reg [13:0] mac_fixpt_t_106; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_309; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_310; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_102; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_311; // ufix16_En13
reg [13:0] mac_fixpt_t_107; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_312; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_313; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_103; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_314; // ufix16_En13
reg [13:0] mac_fixpt_t_108; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_315; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_316; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_104; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_317; // ufix16_En13
reg [13:0] mac_fixpt_t_109; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_318; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_319; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_105; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_320; // ufix16_En13
reg [13:0] mac_fixpt_t_110; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_321; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_322; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_106; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_323; // ufix16_En13
reg [13:0] mac_fixpt_t_111; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_324; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_325; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_107; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_326; // ufix16_En13
reg [13:0] mac_fixpt_t_112; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_327; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_328; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_108; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_329; // ufix16_En13
reg [13:0] mac_fixpt_t_113; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_330; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_331; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_109; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_332; // ufix16_En13
reg [13:0] mac_fixpt_t_114; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_333; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_334; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_110; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_335; // ufix16_En13
reg [13:0] mac_fixpt_t_115; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_336; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_337; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_111; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_338; // ufix16_En13
reg [13:0] mac_fixpt_t_116; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_339; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_340; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_112; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_341; // ufix16_En13
reg [13:0] mac_fixpt_t_117; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_342; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_343; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_113; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_344; // ufix16_En13
reg [13:0] mac_fixpt_t_118; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_345; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_346; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_114; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_347; // ufix16_En13
reg [13:0] mac_fixpt_t_119; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_348; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_349; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_115; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_350; // ufix16_En13
reg [13:0] mac_fixpt_t_120; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_351; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_352; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_116; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_353; // ufix16_En13
reg [13:0] mac_fixpt_t_121; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_354; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_355; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_117; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_356; // ufix16_En13
reg [13:0] mac_fixpt_t_122; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_357; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_358; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_118; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_359; // ufix16_En13
reg [13:0] mac_fixpt_t_123; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_360; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_361; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_119; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_362; // ufix16_En13
reg [13:0] mac_fixpt_t_124; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_363; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_364; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_120; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_365; // ufix16_En13
reg [13:0] mac_fixpt_t_125; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_366; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_367; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_121; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_368; // ufix16_En13
reg [13:0] mac_fixpt_t_126; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_369; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_370; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_122; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_371; // ufix16_En13
reg [13:0] mac_fixpt_t_127; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_372; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_373; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_123; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_374; // ufix16_En13
reg [13:0] mac_fixpt_t_128; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_375; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_376; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_124; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_377; // ufix16_En13
reg [13:0] mac_fixpt_t_129; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_378; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_379; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_125; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_380; // ufix16_En13
reg [13:0] mac_fixpt_t_130; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_381; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_382; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_126; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_383; // ufix16_En13
reg [13:0] mac_fixpt_t_131; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_384; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_385; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_127; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_386; // ufix16_En13
reg [13:0] mac_fixpt_t_132; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_387; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_388; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_128; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_389; // ufix16_En13
reg [13:0] mac_fixpt_t_133; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_390; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_391; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_129; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_392; // ufix16_En13
reg [13:0] mac_fixpt_t_134; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_393; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_394; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_130; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_395; // ufix16_En13
reg [13:0] mac_fixpt_t_135; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_396; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_397; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_131; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_398; // ufix16_En13
reg [13:0] mac_fixpt_t_136; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_399; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_400; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_132; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_401; // ufix16_En13
reg [13:0] mac_fixpt_t_137; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_402; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_403; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_133; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_404; // ufix16_En13
reg [13:0] mac_fixpt_t_138; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_405; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_406; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_134; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_407; // ufix16_En13
reg [13:0] mac_fixpt_t_139; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_408; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_409; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_135; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_410; // ufix16_En13
reg [13:0] mac_fixpt_t_140; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_411; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_412; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_136; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_413; // ufix16_En13
reg [13:0] mac_fixpt_t_141; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_414; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_415; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_137; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_416; // ufix16_En13
reg [13:0] mac_fixpt_t_142; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_417; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_418; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_138; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_419; // ufix16_En13
reg [13:0] mac_fixpt_t_143; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_420; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_421; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_139; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_422; // ufix16_En13
reg [13:0] mac_fixpt_t_144; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_423; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_424; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_140; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_425; // ufix16_En13
reg [13:0] mac_fixpt_t_145; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_426; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_427; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_141; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_428; // ufix16_En13
reg [13:0] mac_fixpt_t_146; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_429; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_430; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_142; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_431; // ufix16_En13
reg [13:0] mac_fixpt_t_147; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_432; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_433; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_143; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_434; // ufix16_En13
reg [13:0] mac_fixpt_t_148; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_435; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_436; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_144; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_437; // ufix16_En13
reg [13:0] mac_fixpt_t_149; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_438; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_439; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_145; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_440; // ufix16_En13
reg [13:0] mac_fixpt_t_150; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_441; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_442; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_146; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_443; // ufix16_En13
reg [13:0] mac_fixpt_t_151; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_444; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_445; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_147; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_446; // ufix16_En13
reg [13:0] mac_fixpt_t_152; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_447; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_448; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_148; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_449; // ufix16_En13
reg [13:0] mac_fixpt_t_153; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_450; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_451; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_149; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_452; // ufix16_En13
reg [13:0] mac_fixpt_t_154; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_453; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_454; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_150; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_455; // ufix16_En13
reg [13:0] mac_fixpt_t_155; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_456; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_457; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_151; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_458; // ufix16_En13
reg [13:0] mac_fixpt_t_156; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_459; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_460; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_152; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_461; // ufix16_En13
reg [13:0] mac_fixpt_t_157; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_462; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_463; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_153; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_464; // ufix16_En13
reg [13:0] mac_fixpt_t_158; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_465; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_466; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_154; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_467; // ufix16_En13
reg [13:0] mac_fixpt_t_159; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_468; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_469; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_155; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_470; // ufix16_En13
reg [13:0] mac_fixpt_t_160; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_471; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_472; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_156; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_473; // ufix16_En13
reg [13:0] mac_fixpt_t_161; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_474; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_475; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_157; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_476; // ufix16_En13
reg [13:0] mac_fixpt_t_162; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_477; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_478; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_158; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_479; // ufix16_En13
reg [13:0] mac_fixpt_t_163; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_480; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_481; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_159; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_482; // ufix16_En13
reg [13:0] mac_fixpt_t_164; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_483; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_484; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_160; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_485; // ufix16_En13
reg [13:0] mac_fixpt_t_165; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_486; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_487; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_161; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_488; // ufix16_En13
reg [13:0] mac_fixpt_t_166; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_489; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_490; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_162; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_491; // ufix16_En13
reg [13:0] mac_fixpt_t_167; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_492; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_493; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_163; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_494; // ufix16_En13
reg [13:0] mac_fixpt_t_168; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_495; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_496; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_164; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_497; // ufix16_En13
reg [13:0] mac_fixpt_t_169; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_498; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_499; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_165; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_500; // ufix16_En13
reg [13:0] mac_fixpt_t_170; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_501; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_502; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_166; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_503; // ufix16_En13
reg [13:0] mac_fixpt_t_171; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_504; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_505; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_167; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_506; // ufix16_En13
reg [13:0] mac_fixpt_t_172; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_507; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_508; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_168; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_509; // ufix16_En13
reg [13:0] mac_fixpt_t_173; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_510; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_511; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_169; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_512; // ufix16_En13
reg [13:0] mac_fixpt_t_174; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_513; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_514; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_170; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_515; // ufix16_En13
reg [13:0] mac_fixpt_t_175; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_516; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_517; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_171; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_518; // ufix16_En13
reg [13:0] mac_fixpt_t_176; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_519; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_520; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_172; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_521; // ufix16_En13
reg [13:0] mac_fixpt_t_177; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_522; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_523; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_173; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_524; // ufix16_En13
reg [13:0] mac_fixpt_t_178; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_525; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_526; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_174; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_527; // ufix16_En13
reg [13:0] mac_fixpt_t_179; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_528; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_529; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_175; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_530; // ufix16_En13
reg [13:0] mac_fixpt_t_180; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_531; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_532; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_176; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_533; // ufix16_En13
reg [13:0] mac_fixpt_t_181; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_534; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_535; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_177; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_536; // ufix16_En13
reg [13:0] mac_fixpt_t_182; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_537; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_538; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_178; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_539; // ufix16_En13
reg [13:0] mac_fixpt_t_183; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_540; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_541; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_179; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_542; // ufix16_En13
reg [13:0] mac_fixpt_t_184; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_543; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_544; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_180; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_545; // ufix16_En13
reg [13:0] mac_fixpt_t_185; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_546; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_547; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_181; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_548; // ufix16_En13
reg [13:0] mac_fixpt_t_186; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_549; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_550; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_182; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_551; // ufix16_En13
reg [13:0] mac_fixpt_t_187; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_552; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_553; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_183; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_554; // ufix16_En13
reg [13:0] mac_fixpt_t_188; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_555; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_556; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_184; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_557; // ufix16_En13
reg [13:0] mac_fixpt_t_189; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_558; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_559; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_185; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_560; // ufix16_En13
reg [13:0] mac_fixpt_t_190; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_561; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_562; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_186; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_563; // ufix16_En13
reg [13:0] mac_fixpt_t_191; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_564; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_565; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_187; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_566; // ufix16_En13
reg [13:0] mac_fixpt_t_192; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_567; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_568; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_188; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_569; // ufix16_En13
reg [13:0] mac_fixpt_t_193; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_570; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_571; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_189; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_572; // ufix16_En13
reg [13:0] mac_fixpt_t_194; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_573; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_574; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_190; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_575; // ufix16_En13
reg [13:0] mac_fixpt_t_195; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_576; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_577; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_191; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_578; // ufix16_En13
reg [13:0] mac_fixpt_t_196; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_579; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_580; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_192; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_581; // ufix16_En13
reg [13:0] mac_fixpt_t_197; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_582; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_583; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_193; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_584; // ufix16_En13
reg [13:0] mac_fixpt_t_198; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_585; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_586; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_194; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_587; // ufix16_En13
reg [13:0] mac_fixpt_t_199; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_588; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_589; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_195; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_590; // ufix16_En13
reg [13:0] mac_fixpt_t_200; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_591; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_592; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_196; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_593; // ufix16_En13
reg [13:0] mac_fixpt_t_201; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_594; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_595; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_197; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_596; // ufix16_En13
reg [13:0] mac_fixpt_t_202; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_597; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_598; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_198; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_599; // ufix16_En13
reg [13:0] mac_fixpt_t_203; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_600; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_601; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_199; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_602; // ufix16_En13
reg [13:0] mac_fixpt_t_204; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_603; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_604; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_200; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_605; // ufix16_En13
reg [13:0] mac_fixpt_t_205; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_606; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_607; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_201; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_608; // ufix16_En13
reg [13:0] mac_fixpt_t_206; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_609; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_610; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_202; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_611; // ufix16_En13
reg [13:0] mac_fixpt_t_207; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_612; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_613; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_203; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_614; // ufix16_En13
reg [13:0] mac_fixpt_t_208; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_615; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_616; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_204; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_617; // ufix16_En13
reg [13:0] mac_fixpt_t_209; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_618; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_619; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_205; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_620; // ufix16_En13
reg [13:0] mac_fixpt_t_210; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_621; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_622; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_206; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_623; // ufix16_En13
reg [13:0] mac_fixpt_t_211; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_624; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_625; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_207; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_626; // ufix16_En13
reg [13:0] mac_fixpt_t_212; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_627; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_628; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_208; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_629; // ufix16_En13
reg [13:0] mac_fixpt_t_213; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_630; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_631; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_209; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_632; // ufix16_En13
reg [13:0] mac_fixpt_t_214; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_633; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_634; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_210; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_635; // ufix16_En13
reg [13:0] mac_fixpt_t_215; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_636; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_637; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_211; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_638; // ufix16_En13
reg [13:0] mac_fixpt_t_216; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_639; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_640; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_212; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_641; // ufix16_En13
reg [13:0] mac_fixpt_t_217; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_642; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_643; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_213; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_644; // ufix16_En13
reg [13:0] mac_fixpt_t_218; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_645; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_646; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_214; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_647; // ufix16_En13
reg [13:0] mac_fixpt_t_219; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_648; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_649; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_215; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_650; // ufix16_En13
reg [13:0] mac_fixpt_t_220; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_651; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_652; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_216; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_653; // ufix16_En13
reg [13:0] mac_fixpt_t_221; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_654; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_655; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_217; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_656; // ufix16_En13
reg [13:0] mac_fixpt_t_222; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_657; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_658; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_218; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_659; // ufix16_En13
reg [13:0] mac_fixpt_t_223; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_660; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_661; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_219; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_662; // ufix16_En13
reg [13:0] mac_fixpt_t_224; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_663; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_664; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_220; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_665; // ufix16_En13
reg [13:0] mac_fixpt_t_225; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_666; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_667; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_221; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_668; // ufix16_En13
reg [13:0] mac_fixpt_t_226; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_669; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_670; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_222; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_671; // ufix16_En13
reg [13:0] mac_fixpt_t_227; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_672; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_673; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_223; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_674; // ufix16_En13
reg [13:0] mac_fixpt_t_228; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_675; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_676; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_224; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_677; // ufix16_En13
reg [13:0] mac_fixpt_t_229; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_678; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_679; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_225; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_680; // ufix16_En13
reg [13:0] mac_fixpt_t_230; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_681; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_682; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_226; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_683; // ufix16_En13
reg [13:0] mac_fixpt_t_231; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_684; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_685; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_227; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_686; // ufix16_En13
reg [13:0] mac_fixpt_t_232; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_687; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_688; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_228; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_689; // ufix16_En13
reg [13:0] mac_fixpt_t_233; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_690; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_691; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_229; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_692; // ufix16_En13
reg [13:0] mac_fixpt_t_234; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_693; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_694; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_230; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_695; // ufix16_En13
reg [13:0] mac_fixpt_t_235; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_696; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_697; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_231; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_698; // ufix16_En13
reg [13:0] mac_fixpt_t_236; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_699; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_700; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_232; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_701; // ufix16_En13
reg [13:0] mac_fixpt_t_237; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_702; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_703; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_233; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_704; // ufix16_En13
reg [13:0] mac_fixpt_t_238; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_705; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_706; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_234; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_707; // ufix16_En13
reg [13:0] mac_fixpt_t_239; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_708; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_709; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_235; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_710; // ufix16_En13
reg [13:0] mac_fixpt_t_240; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_711; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_712; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_236; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_713; // ufix16_En13
reg [13:0] mac_fixpt_t_241; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_714; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_715; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_237; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_716; // ufix16_En13
reg [13:0] mac_fixpt_t_242; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_717; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_718; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_238; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_719; // ufix16_En13
reg [13:0] mac_fixpt_t_243; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_720; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_721; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_239; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_722; // ufix16_En13
reg [13:0] mac_fixpt_t_244; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_723; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_724; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_240; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_725; // ufix16_En13
reg [13:0] mac_fixpt_t_245; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_726; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_727; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_241; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_728; // ufix16_En13
reg [13:0] mac_fixpt_t_246; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_729; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_730; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_242; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_731; // ufix16_En13
reg [13:0] mac_fixpt_t_247; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_732; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_733; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_243; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_734; // ufix16_En13
reg [13:0] mac_fixpt_t_248; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_735; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_736; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_244; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_737; // ufix16_En13
reg [13:0] mac_fixpt_t_249; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_738; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_739; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_245; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_740; // ufix16_En13
reg [13:0] mac_fixpt_t_250; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_741; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_742; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_246; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_743; // ufix16_En13
reg [13:0] mac_fixpt_t_251; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_744; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_745; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_247; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_746; // ufix16_En13
reg [13:0] mac_fixpt_t_252; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_747; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_748; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_248; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_749; // ufix16_En13
reg [13:0] mac_fixpt_t_253; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_750; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_751; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_249; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_752; // ufix16_En13
reg [13:0] mac_fixpt_t_254; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_753; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_754; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_250; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_755; // ufix16_En13
reg [13:0] mac_fixpt_t_255; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_756; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_757; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_251; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_758; // ufix16_En13
reg [13:0] mac_fixpt_t_256; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_759; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_760; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_252; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_761; // ufix16_En13
reg [13:0] mac_fixpt_t_257; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_762; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_763; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_253; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_764; // ufix16_En13
reg [13:0] mac_fixpt_t_258; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_765; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_766; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_254; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_767; // ufix16_En13
reg [13:0] mac_fixpt_t_259; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_768; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_769; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_255; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_770; // ufix16_En13
reg [13:0] mac_fixpt_t_260; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_771; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_772; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_256; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_773; // ufix16_En13
reg [13:0] mac_fixpt_t_261; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_774; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_775; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_257; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_776; // ufix16_En13
reg [13:0] mac_fixpt_t_262; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_777; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_778; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_258; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_779; // ufix16_En13
reg [13:0] mac_fixpt_t_263; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_780; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_781; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_259; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_782; // ufix16_En13
reg [13:0] mac_fixpt_t_264; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_783; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_784; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_260; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_785; // ufix16_En13
reg [13:0] mac_fixpt_t_265; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_786; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_787; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_261; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_788; // ufix16_En13
reg [13:0] mac_fixpt_t_266; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_789; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_790; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_262; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_791; // ufix16_En13
reg [13:0] mac_fixpt_t_267; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_792; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_793; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_263; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_794; // ufix16_En13
reg [13:0] mac_fixpt_t_268; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_795; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_796; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_264; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_797; // ufix16_En13
reg [13:0] mac_fixpt_t_269; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_798; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_799; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_265; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_800; // ufix16_En13
reg [13:0] mac_fixpt_t_270; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_801; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_802; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_266; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_803; // ufix16_En13
reg [13:0] mac_fixpt_t_271; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_804; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_805; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_267; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_806; // ufix16_En13
reg [13:0] mac_fixpt_t_272; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_807; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_808; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_268; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_809; // ufix16_En13
reg [13:0] mac_fixpt_t_273; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_810; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_811; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_269; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_812; // ufix16_En13
reg [13:0] mac_fixpt_t_274; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_813; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_814; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_270; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_815; // ufix16_En13
reg [13:0] mac_fixpt_t_275; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_816; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_817; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_271; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_818; // ufix16_En13
reg [13:0] mac_fixpt_t_276; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_819; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_820; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_272; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_821; // ufix16_En13
reg [13:0] mac_fixpt_t_277; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_822; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_823; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_273; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_824; // ufix16_En13
reg [13:0] mac_fixpt_t_278; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_825; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_826; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_274; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_827; // ufix16_En13
reg [13:0] mac_fixpt_t_279; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_828; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_829; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_275; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_830; // ufix16_En13
reg [13:0] mac_fixpt_t_280; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_831; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_832; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_276; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_833; // ufix16_En13
reg [13:0] mac_fixpt_t_281; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_834; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_835; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_277; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_836; // ufix16_En13
reg [13:0] mac_fixpt_t_282; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_837; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_838; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_278; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_839; // ufix16_En13
reg [13:0] mac_fixpt_t_283; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_840; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_841; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_279; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_842; // ufix16_En13
reg [13:0] mac_fixpt_t_284; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_843; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_844; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_280; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_845; // ufix16_En13
reg [13:0] mac_fixpt_t_285; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_846; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_847; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_281; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_848; // ufix16_En13
reg [13:0] mac_fixpt_t_286; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_849; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_850; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_282; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_851; // ufix16_En13
reg [13:0] mac_fixpt_t_287; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_852; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_853; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_283; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_854; // ufix16_En13
reg [13:0] mac_fixpt_t_288; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_855; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_856; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_284; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_857; // ufix16_En13
reg [13:0] mac_fixpt_t_289; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_858; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_859; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_285; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_860; // ufix16_En13
reg [13:0] mac_fixpt_t_290; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_861; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_862; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_286; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_863; // ufix16_En13
reg [13:0] mac_fixpt_t_291; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_864; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_865; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_287; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_866; // ufix16_En13
reg [13:0] mac_fixpt_t_292; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_867; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_868; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_288; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_869; // ufix16_En13
reg [13:0] mac_fixpt_t_293; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_870; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_871; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_289; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_872; // ufix16_En13
reg [13:0] mac_fixpt_t_294; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_873; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_874; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_290; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_875; // ufix16_En13
reg [13:0] mac_fixpt_t_295; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_876; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_877; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_291; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_878; // ufix16_En13
reg [13:0] mac_fixpt_t_296; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_879; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_880; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_292; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_881; // ufix16_En13
reg [13:0] mac_fixpt_t_297; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_882; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_883; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_293; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_884; // ufix16_En13
reg [13:0] mac_fixpt_t_298; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_885; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_886; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_294; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_887; // ufix16_En13
reg [13:0] mac_fixpt_t_299; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_888; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_889; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_295; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_890; // ufix16_En13
reg [13:0] mac_fixpt_t_300; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_891; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_892; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_296; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_893; // ufix16_En13
reg [13:0] mac_fixpt_t_301; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_894; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_895; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_297; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_896; // ufix16_En13
reg [13:0] mac_fixpt_t_302; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_897; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_898; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_298; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_899; // ufix16_En13
reg [13:0] mac_fixpt_t_303; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_900; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_901; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_299; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_902; // ufix16_En13
reg [13:0] mac_fixpt_t_304; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_903; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_904; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_300; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_905; // ufix16_En13
reg [13:0] mac_fixpt_t_305; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_906; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_907; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_301; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_908; // ufix16_En13
reg [13:0] mac_fixpt_t_306; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_909; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_910; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_302; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_911; // ufix16_En13
reg [13:0] mac_fixpt_t_307; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_912; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_913; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_303; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_914; // ufix16_En13
reg [13:0] mac_fixpt_t_308; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_915; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_916; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_304; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_917; // ufix16_En13
reg [13:0] mac_fixpt_t_309; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_918; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_919; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_305; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_920; // ufix16_En13
reg [13:0] mac_fixpt_t_310; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_921; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_922; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_306; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_923; // ufix16_En13
reg [13:0] mac_fixpt_t_311; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_924; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_925; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_307; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_926; // ufix16_En13
reg [13:0] mac_fixpt_t_312; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_927; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_928; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_308; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_929; // ufix16_En13
reg [13:0] mac_fixpt_t_313; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_930; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_931; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_309; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_932; // ufix16_En13
reg [13:0] mac_fixpt_t_314; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_933; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_934; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_310; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_935; // ufix16_En13
reg [13:0] mac_fixpt_t_315; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_936; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_937; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_311; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_938; // ufix16_En13
reg [13:0] mac_fixpt_t_316; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_939; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_940; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_312; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_941; // ufix16_En13
reg [13:0] mac_fixpt_t_317; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_942; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_943; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_313; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_944; // ufix16_En13
reg [13:0] mac_fixpt_t_318; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_945; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_946; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_314; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_947; // ufix16_En13
reg [13:0] mac_fixpt_t_319; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_948; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_949; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_315; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_950; // ufix16_En13
reg [13:0] mac_fixpt_t_320; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_951; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_952; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_316; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_953; // ufix16_En13
reg [13:0] mac_fixpt_t_321; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_954; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_955; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_317; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_956; // ufix16_En13
reg [13:0] mac_fixpt_t_322; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_957; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_958; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_318; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_959; // ufix16_En13
reg [13:0] mac_fixpt_t_323; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_960; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_961; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_319; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_962; // ufix16_En13
reg [13:0] mac_fixpt_t_324; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_963; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_964; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_320; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_965; // ufix16_En13
reg [13:0] mac_fixpt_t_325; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_966; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_967; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_321; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_968; // ufix16_En13
reg [13:0] mac_fixpt_t_326; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_969; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_970; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_322; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_971; // ufix16_En13
reg [13:0] mac_fixpt_t_327; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_972; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_973; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_323; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_974; // ufix16_En13
reg [13:0] mac_fixpt_t_328; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_975; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_976; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_324; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_977; // ufix16_En13
reg [13:0] mac_fixpt_t_329; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_978; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_979; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_325; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_980; // ufix16_En13
reg [13:0] mac_fixpt_t_330; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_981; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_982; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_326; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_983; // ufix16_En13
reg [13:0] mac_fixpt_t_331; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_984; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_985; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_327; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_986; // ufix16_En13
reg [13:0] mac_fixpt_t_332; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_987; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_988; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_328; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_989; // ufix16_En13
reg [13:0] mac_fixpt_t_333; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_990; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_991; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_329; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_992; // ufix16_En13
reg [13:0] mac_fixpt_t_334; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_993; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_994; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_330; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_995; // ufix16_En13
reg [13:0] mac_fixpt_t_335; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_996; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_997; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_331; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_998; // ufix16_En13
reg [13:0] mac_fixpt_t_336; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_999; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1000; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_332; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1001; // ufix16_En13
reg [13:0] mac_fixpt_t_337; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1002; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1003; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_333; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1004; // ufix16_En13
reg [13:0] mac_fixpt_t_338; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1005; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1006; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_334; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1007; // ufix16_En13
reg [13:0] mac_fixpt_t_339; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1008; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1009; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_335; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1010; // ufix16_En13
reg [13:0] mac_fixpt_t_340; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1011; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1012; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_336; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1013; // ufix16_En13
reg [13:0] mac_fixpt_t_341; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1014; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1015; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_337; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1016; // ufix16_En13
reg [13:0] mac_fixpt_t_342; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1017; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1018; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_338; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1019; // ufix16_En13
reg [13:0] mac_fixpt_t_343; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1020; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1021; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_339; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1022; // ufix16_En13
reg [13:0] mac_fixpt_t_344; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1023; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1024; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_340; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1025; // ufix16_En13
reg [13:0] mac_fixpt_t_345; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1026; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1027; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_341; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1028; // ufix16_En13
reg [13:0] mac_fixpt_t_346; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1029; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1030; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_342; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1031; // ufix16_En13
reg [13:0] mac_fixpt_t_347; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1032; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1033; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_343; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1034; // ufix16_En13
reg [13:0] mac_fixpt_t_348; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1035; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1036; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_344; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1037; // ufix16_En13
reg [13:0] mac_fixpt_t_349; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1038; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1039; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_345; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1040; // ufix16_En13
reg [13:0] mac_fixpt_t_350; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1041; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1042; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_346; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1043; // ufix16_En13
reg [13:0] mac_fixpt_t_351; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1044; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1045; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_347; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1046; // ufix16_En13
reg [13:0] mac_fixpt_t_352; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1047; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1048; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_348; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1049; // ufix16_En13
reg [13:0] mac_fixpt_t_353; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1050; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1051; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_349; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1052; // ufix16_En13
reg [13:0] mac_fixpt_t_354; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1053; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1054; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_350; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1055; // ufix16_En13
reg [13:0] mac_fixpt_t_355; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1056; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1057; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_351; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1058; // ufix16_En13
reg [13:0] mac_fixpt_t_356; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1059; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1060; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_352; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1061; // ufix16_En13
reg [13:0] mac_fixpt_t_357; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1062; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1063; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_353; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1064; // ufix16_En13
reg [13:0] mac_fixpt_t_358; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1065; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1066; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_354; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1067; // ufix16_En13
reg [13:0] mac_fixpt_t_359; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1068; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1069; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_355; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1070; // ufix16_En13
reg [13:0] mac_fixpt_t_360; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1071; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1072; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_356; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1073; // ufix16_En13
reg [13:0] mac_fixpt_t_361; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1074; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1075; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_357; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1076; // ufix16_En13
reg [13:0] mac_fixpt_t_362; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1077; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1078; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_358; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1079; // ufix16_En13
reg [13:0] mac_fixpt_t_363; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1080; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1081; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_359; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1082; // ufix16_En13
reg [13:0] mac_fixpt_t_364; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1083; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1084; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_360; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1085; // ufix16_En13
reg [13:0] mac_fixpt_t_365; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1086; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1087; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_361; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1088; // ufix16_En13
reg [13:0] mac_fixpt_t_366; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1089; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1090; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_362; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1091; // ufix16_En13
reg [13:0] mac_fixpt_t_367; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1092; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1093; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_363; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1094; // ufix16_En13
reg [13:0] mac_fixpt_t_368; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1095; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1096; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_364; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1097; // ufix16_En13
reg [13:0] mac_fixpt_t_369; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1098; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1099; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_365; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1100; // ufix16_En13
reg [13:0] mac_fixpt_t_370; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1101; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1102; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_366; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1103; // ufix16_En13
reg [13:0] mac_fixpt_t_371; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1104; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1105; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_367; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1106; // ufix16_En13
reg [13:0] mac_fixpt_t_372; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1107; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1108; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_368; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1109; // ufix16_En13
reg [13:0] mac_fixpt_t_373; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1110; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1111; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_369; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1112; // ufix16_En13
reg [13:0] mac_fixpt_t_374; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1113; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1114; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_370; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1115; // ufix16_En13
reg [13:0] mac_fixpt_t_375; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1116; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1117; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_371; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1118; // ufix16_En13
reg [13:0] mac_fixpt_t_376; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1119; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1120; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_372; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1121; // ufix16_En13
reg [13:0] mac_fixpt_t_377; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1122; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1123; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_373; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1124; // ufix16_En13
reg [13:0] mac_fixpt_t_378; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1125; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1126; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_374; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1127; // ufix16_En13
reg [13:0] mac_fixpt_t_379; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1128; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1129; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_375; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1130; // ufix16_En13
reg [13:0] mac_fixpt_t_380; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1131; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1132; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_376; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1133; // ufix16_En13
reg [13:0] mac_fixpt_t_381; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1134; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1135; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_377; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1136; // ufix16_En13
reg [13:0] mac_fixpt_t_382; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1137; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1138; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_378; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1139; // ufix16_En13
reg [13:0] mac_fixpt_t_383; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1140; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1141; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_379; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1142; // ufix16_En13
reg [13:0] mac_fixpt_t_384; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1143; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1144; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_380; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1145; // ufix16_En13
reg [13:0] mac_fixpt_t_385; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1146; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1147; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_381; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1148; // ufix16_En13
reg [13:0] mac_fixpt_t_386; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1149; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1150; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_382; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1151; // ufix16_En13
reg [13:0] mac_fixpt_t_387; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1152; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1153; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_383; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1154; // ufix16_En13
reg [13:0] mac_fixpt_t_388; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1155; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1156; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_384; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1157; // ufix16_En13
reg [13:0] mac_fixpt_t_389; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1158; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1159; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_385; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1160; // ufix16_En13
reg [13:0] mac_fixpt_t_390; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1161; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1162; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_386; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1163; // ufix16_En13
reg [13:0] mac_fixpt_t_391; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1164; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1165; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_387; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1166; // ufix16_En13
reg [13:0] mac_fixpt_t_392; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1167; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1168; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_388; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1169; // ufix16_En13
reg [13:0] mac_fixpt_t_393; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1170; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1171; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_389; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1172; // ufix16_En13
reg [13:0] mac_fixpt_t_394; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1173; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1174; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_390; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1175; // ufix16_En13
reg [13:0] mac_fixpt_t_395; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1176; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1177; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_391; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1178; // ufix16_En13
reg [13:0] mac_fixpt_t_396; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1179; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1180; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_392; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1181; // ufix16_En13
reg [13:0] mac_fixpt_t_397; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1182; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1183; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_393; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1184; // ufix16_En13
reg [13:0] mac_fixpt_t_398; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1185; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1186; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_394; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1187; // ufix16_En13
reg [13:0] mac_fixpt_t_399; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1188; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1189; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_395; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1190; // ufix16_En13
reg [13:0] mac_fixpt_t_400; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1191; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1192; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_396; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1193; // ufix16_En13
reg [13:0] mac_fixpt_t_401; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1194; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1195; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_397; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1196; // ufix16_En13
reg [13:0] mac_fixpt_t_402; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1197; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1198; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_398; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1199; // ufix16_En13
reg [13:0] mac_fixpt_t_403; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1200; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1201; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_399; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1202; // ufix16_En13
reg [13:0] mac_fixpt_t_404; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1203; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1204; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_400; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1205; // ufix16_En13
reg [13:0] mac_fixpt_t_405; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1206; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1207; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_401; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1208; // ufix16_En13
reg [13:0] mac_fixpt_t_406; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1209; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1210; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_402; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1211; // ufix16_En13
reg [13:0] mac_fixpt_t_407; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1212; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1213; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_403; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1214; // ufix16_En13
reg [13:0] mac_fixpt_t_408; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1215; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1216; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_404; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1217; // ufix16_En13
reg [13:0] mac_fixpt_t_409; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1218; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1219; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_405; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1220; // ufix16_En13
reg [13:0] mac_fixpt_t_410; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1221; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1222; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_406; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1223; // ufix16_En13
reg [13:0] mac_fixpt_t_411; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1224; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1225; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_407; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1226; // ufix16_En13
reg [13:0] mac_fixpt_t_412; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1227; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1228; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_408; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1229; // ufix16_En13
reg [13:0] mac_fixpt_t_413; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1230; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1231; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_409; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1232; // ufix16_En13
reg [13:0] mac_fixpt_t_414; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1233; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1234; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_410; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1235; // ufix16_En13
reg [13:0] mac_fixpt_t_415; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1236; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1237; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_411; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1238; // ufix16_En13
reg [13:0] mac_fixpt_t_416; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1239; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1240; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_412; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1241; // ufix16_En13
reg [13:0] mac_fixpt_t_417; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1242; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1243; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_413; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1244; // ufix16_En13
reg [13:0] mac_fixpt_t_418; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1245; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1246; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_414; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1247; // ufix16_En13
reg [13:0] mac_fixpt_t_419; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1248; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1249; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_415; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1250; // ufix16_En13
reg [13:0] mac_fixpt_t_420; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1251; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1252; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_416; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1253; // ufix16_En13
reg [13:0] mac_fixpt_t_421; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1254; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1255; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_417; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1256; // ufix16_En13
reg [13:0] mac_fixpt_t_422; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1257; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1258; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_418; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1259; // ufix16_En13
reg [13:0] mac_fixpt_t_423; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1260; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1261; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_419; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1262; // ufix16_En13
reg [13:0] mac_fixpt_t_424; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1263; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1264; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_420; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1265; // ufix16_En13
reg [13:0] mac_fixpt_t_425; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1266; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1267; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_421; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1268; // ufix16_En13
reg [13:0] mac_fixpt_t_426; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1269; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1270; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_422; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1271; // ufix16_En13
reg [13:0] mac_fixpt_t_427; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1272; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1273; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_423; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1274; // ufix16_En13
reg [13:0] mac_fixpt_t_428; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1275; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1276; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_424; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1277; // ufix16_En13
reg [13:0] mac_fixpt_t_429; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1278; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1279; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_425; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1280; // ufix16_En13
reg [13:0] mac_fixpt_t_430; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1281; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1282; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_426; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1283; // ufix16_En13
reg [13:0] mac_fixpt_t_431; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1284; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1285; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_427; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1286; // ufix16_En13
reg [13:0] mac_fixpt_t_432; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1287; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1288; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_428; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1289; // ufix16_En13
reg [13:0] mac_fixpt_t_433; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1290; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1291; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_429; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1292; // ufix16_En13
reg [13:0] mac_fixpt_t_434; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1293; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1294; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_430; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1295; // ufix16_En13
reg [13:0] mac_fixpt_t_435; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1296; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1297; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_431; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1298; // ufix16_En13
reg [13:0] mac_fixpt_t_436; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1299; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1300; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_432; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1301; // ufix16_En13
reg [13:0] mac_fixpt_t_437; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1302; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1303; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_433; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1304; // ufix16_En13
reg [13:0] mac_fixpt_t_438; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1305; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1306; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_434; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1307; // ufix16_En13
reg [13:0] mac_fixpt_t_439; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1308; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1309; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_435; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1310; // ufix16_En13
reg [13:0] mac_fixpt_t_440; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1311; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1312; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_436; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1313; // ufix16_En13
reg [13:0] mac_fixpt_t_441; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1314; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1315; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_437; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1316; // ufix16_En13
reg [13:0] mac_fixpt_t_442; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1317; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1318; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_438; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1319; // ufix16_En13
reg [13:0] mac_fixpt_t_443; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1320; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1321; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_439; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1322; // ufix16_En13
reg [13:0] mac_fixpt_t_444; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1323; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1324; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_440; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1325; // ufix16_En13
reg [13:0] mac_fixpt_t_445; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1326; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1327; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_441; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1328; // ufix16_En13
reg [13:0] mac_fixpt_t_446; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1329; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1330; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_442; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1331; // ufix16_En13
reg [13:0] mac_fixpt_t_447; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1332; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1333; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_443; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1334; // ufix16_En13
reg [13:0] mac_fixpt_t_448; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1335; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1336; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_444; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1337; // ufix16_En13
reg [13:0] mac_fixpt_t_449; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1338; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1339; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_445; // ufix16_En13
reg [15:0] mac_fixpt_add_cast_1340; // ufix16_En13
reg [13:0] mac_fixpt_t_450; // ufix14_En13
reg [14:0] mac_fixpt_add_cast_1341; // ufix15_En13
reg [15:0] mac_fixpt_add_cast_1342; // ufix16_En13
reg [15:0] mac_fixpt_add_temp_446; // ufix16_En13
assign M[0] = M_0;
assign M[1] = M_1;
assign M[2] = M_2;
assign M[3] = M_3;
assign M[4] = M_4;
assign M[5] = M_5;
assign M[6] = M_6;
assign M[7] = M_7;
assign M[8] = M_8;
assign M[9] = M_9;
assign M[10] = M_10;
assign M[11] = M_11;
assign M[12] = M_12;
assign M[13] = M_13;
assign M[14] = M_14;
assign M[15] = M_15;
assign M[16] = M_16;
assign M[17] = M_17;
assign M[18] = M_18;
assign M[19] = M_19;
assign M[20] = M_20;
assign M[21] = M_21;
assign M[22] = M_22;
assign M[23] = M_23;
assign M[24] = M_24;
assign M[25] = M_25;
assign M[26] = M_26;
assign M[27] = M_27;
assign M[28] = M_28;
assign M[29] = M_29;
assign M[30] = M_30;
assign M[31] = M_31;
assign M[32] = M_32;
assign M[33] = M_33;
assign M[34] = M_34;
assign M[35] = M_35;
assign M[36] = M_36;
assign M[37] = M_37;
assign M[38] = M_38;
assign M[39] = M_39;
assign M[40] = M_40;
assign M[41] = M_41;
assign M[42] = M_42;
assign M[43] = M_43;
assign M[44] = M_44;
assign M[45] = M_45;
assign M[46] = M_46;
assign M[47] = M_47;
assign M[48] = M_48;
assign M[49] = M_49;
assign M[50] = M_50;
assign M[51] = M_51;
assign M[52] = M_52;
assign M[53] = M_53;
assign M[54] = M_54;
assign M[55] = M_55;
assign M[56] = M_56;
assign M[57] = M_57;
assign M[58] = M_58;
assign M[59] = M_59;
assign M[60] = M_60;
assign M[61] = M_61;
assign M[62] = M_62;
assign M[63] = M_63;
assign N[0] = N_0;
assign N[1] = N_1;
assign N[2] = N_2;
assign N[3] = N_3;
assign N[4] = N_4;
assign N[5] = N_5;
assign N[6] = N_6;
assign W[0] = W_0;
assign W[1] = W_1;
assign W[2] = W_2;
assign W[3] = W_3;
assign W[4] = W_4;
assign W[5] = W_5;
assign W[6] = W_6;
always @* begin
//HDL code generation from MATLAB function: mac_fixpt
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
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// Processing Element, a simple mac
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// Processing Element, a simple mac
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// Processing Element, a simple mac
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// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
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// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
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// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
// Processing Element, a simple mac
//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
// %
// Generated by MATLAB 9.1 and Fixed-Point Designer 5.3 %
// %
//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
// Author: Thilina Mallawa Arachchi
// Email address: [email protected]
// March 2017; Last revision: 17-March-2017
//MAC simply multiplies and accumalates
for(mac_fixpt_t_0 = 32'sd0; mac_fixpt_t_0 <= 32'sd63; mac_fixpt_t_0 = mac_fixpt_t_0 + 32'sd1) begin
mac_fixpt_M_local[mac_fixpt_t_0] = 14'b00000000000000;
end
mac_fixpt_M_local[0] = {1'b0, {M[0], 12'b000000000000}};
mac_fixpt_M_local[1] = {1'b0, {M[1], 12'b000000000000}};
mac_fixpt_M_local[2] = {1'b0, {M[2], 12'b000000000000}};
mac_fixpt_M_local[3] = {1'b0, {M[3], 12'b000000000000}};
mac_fixpt_M_local[4] = {1'b0, {M[4], 12'b000000000000}};
mac_fixpt_M_local[5] = {1'b0, {M[5], 12'b000000000000}};
mac_fixpt_M_local[6] = {1'b0, {M[6], 12'b000000000000}};
mac_fixpt_M_local[7] = {1'b0, {M[7], 12'b000000000000}};
mac_fixpt_M_local[8] = {1'b0, {M[8], 12'b000000000000}};
mac_fixpt_M_local[9] = {1'b0, {M[9], 12'b000000000000}};
mac_fixpt_M_local[10] = {1'b0, {M[10], 12'b000000000000}};
mac_fixpt_M_local[11] = {1'b0, {M[11], 12'b000000000000}};
mac_fixpt_M_local[12] = {1'b0, {M[12], 12'b000000000000}};
mac_fixpt_M_local[13] = {1'b0, {M[13], 12'b000000000000}};
mac_fixpt_M_local[14] = {1'b0, {M[14], 12'b000000000000}};
mac_fixpt_M_local[15] = {1'b0, {M[15], 12'b000000000000}};
mac_fixpt_M_local[16] = {1'b0, {M[16], 12'b000000000000}};
mac_fixpt_M_local[17] = {1'b0, {M[17], 12'b000000000000}};
mac_fixpt_M_local[18] = {1'b0, {M[18], 12'b000000000000}};
mac_fixpt_M_local[19] = {1'b0, {M[19], 12'b000000000000}};
mac_fixpt_M_local[20] = {1'b0, {M[20], 12'b000000000000}};
mac_fixpt_M_local[21] = {1'b0, {M[21], 12'b000000000000}};
mac_fixpt_M_local[22] = {1'b0, {M[22], 12'b000000000000}};
mac_fixpt_M_local[23] = {1'b0, {M[23], 12'b000000000000}};
mac_fixpt_M_local[24] = {1'b0, {M[24], 12'b000000000000}};
mac_fixpt_M_local[25] = {1'b0, {M[25], 12'b000000000000}};
mac_fixpt_M_local[26] = {1'b0, {M[26], 12'b000000000000}};
mac_fixpt_M_local[27] = {1'b0, {M[27], 12'b000000000000}};
mac_fixpt_M_local[28] = {1'b0, {M[28], 12'b000000000000}};
mac_fixpt_M_local[29] = {1'b0, {M[29], 12'b000000000000}};
mac_fixpt_M_local[30] = {1'b0, {M[30], 12'b000000000000}};
mac_fixpt_M_local[31] = {1'b0, {M[31], 12'b000000000000}};
mac_fixpt_M_local[32] = {1'b0, {M[32], 12'b000000000000}};
mac_fixpt_M_local[33] = {1'b0, {M[33], 12'b000000000000}};
mac_fixpt_M_local[34] = {1'b0, {M[34], 12'b000000000000}};
mac_fixpt_M_local[35] = {1'b0, {M[35], 12'b000000000000}};
mac_fixpt_M_local[36] = {1'b0, {M[36], 12'b000000000000}};
mac_fixpt_M_local[37] = {1'b0, {M[37], 12'b000000000000}};
mac_fixpt_M_local[38] = {1'b0, {M[38], 12'b000000000000}};
mac_fixpt_M_local[39] = {1'b0, {M[39], 12'b000000000000}};
mac_fixpt_M_local[40] = {1'b0, {M[40], 12'b000000000000}};
mac_fixpt_M_local[41] = {1'b0, {M[41], 12'b000000000000}};
mac_fixpt_M_local[42] = {1'b0, {M[42], 12'b000000000000}};
mac_fixpt_M_local[43] = {1'b0, {M[43], 12'b000000000000}};
mac_fixpt_M_local[44] = {1'b0, {M[44], 12'b000000000000}};
mac_fixpt_M_local[45] = {1'b0, {M[45], 12'b000000000000}};
mac_fixpt_M_local[46] = {1'b0, {M[46], 12'b000000000000}};
mac_fixpt_M_local[47] = {1'b0, {M[47], 12'b000000000000}};
mac_fixpt_M_local[48] = {1'b0, {M[48], 12'b000000000000}};
mac_fixpt_M_local[49] = {1'b0, {M[49], 12'b000000000000}};
mac_fixpt_M_local[50] = {1'b0, {M[50], 12'b000000000000}};
mac_fixpt_M_local[51] = {1'b0, {M[51], 12'b000000000000}};
mac_fixpt_M_local[52] = {1'b0, {M[52], 12'b000000000000}};
mac_fixpt_M_local[53] = {1'b0, {M[53], 12'b000000000000}};
mac_fixpt_M_local[54] = {1'b0, {M[54], 12'b000000000000}};
mac_fixpt_M_local[55] = {1'b0, {M[55], 12'b000000000000}};
mac_fixpt_M_local[56] = {1'b0, {M[56], 12'b000000000000}};
mac_fixpt_M_local[57] = {1'b0, {M[57], 12'b000000000000}};
mac_fixpt_M_local[58] = {1'b0, {M[58], 12'b000000000000}};
for(mac_fixpt_t_1 = 32'sd0; mac_fixpt_t_1 <= 32'sd63; mac_fixpt_t_1 = mac_fixpt_t_1 + 32'sd1) begin
mac_fixpt_M_local_0[mac_fixpt_t_1] = mac_fixpt_M_local[mac_fixpt_t_1];
end
mac_fixpt_M_local_0[59] = {1'b0, {M[59], 12'b000000000000}};
mac_fixpt_M_local_0[60] = {1'b0, {M[60], 12'b000000000000}};
mac_fixpt_M_local_0[61] = {1'b0, {M[61], 12'b000000000000}};
mac_fixpt_M_local_0[62] = {1'b0, {M[62], 12'b000000000000}};
mac_fixpt_M_local_0[63] = {1'b0, {M[63], 12'b000000000000}};
if (7'b0000001 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast = {1'b0, {mac_fixpt_M_local[0], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_3 = W[0];
end
else begin
mac_fixpt_t_3 = 14'b00000000000000;
end
mac_fixpt_add_cast_0 = {1'b0, mac_fixpt_t_3};
mac_fixpt_add_cast_1 = {1'b0, mac_fixpt_add_cast_0};
mac_fixpt_add_temp = mac_fixpt_add_cast + mac_fixpt_add_cast_1;
mac_fixpt_M_local_0[0] = mac_fixpt_add_temp[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_5 = {1'b0, {mac_fixpt_M_local_0[0], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_5 = W[1];
end
else begin
mac_fixpt_t_5 = 14'b00000000000000;
end
mac_fixpt_add_cast_6 = {1'b0, mac_fixpt_t_5};
mac_fixpt_add_cast_7 = {1'b0, mac_fixpt_add_cast_6};
mac_fixpt_add_temp_1 = mac_fixpt_add_cast_5 + mac_fixpt_add_cast_7;
mac_fixpt_M_local_0[0] = mac_fixpt_add_temp_1[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_14 = {1'b0, {mac_fixpt_M_local_0[0], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_8 = W[2];
end
else begin
mac_fixpt_t_8 = 14'b00000000000000;
end
mac_fixpt_add_cast_15 = {1'b0, mac_fixpt_t_8};
mac_fixpt_add_cast_16 = {1'b0, mac_fixpt_add_cast_15};
mac_fixpt_add_temp_4 = mac_fixpt_add_cast_14 + mac_fixpt_add_cast_16;
mac_fixpt_M_local_0[0] = mac_fixpt_add_temp_4[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_26 = {1'b0, {mac_fixpt_M_local_0[0], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_12 = W[3];
end
else begin
mac_fixpt_t_12 = 14'b00000000000000;
end
mac_fixpt_add_cast_27 = {1'b0, mac_fixpt_t_12};
mac_fixpt_add_cast_28 = {1'b0, mac_fixpt_add_cast_27};
mac_fixpt_add_temp_8 = mac_fixpt_add_cast_26 + mac_fixpt_add_cast_28;
mac_fixpt_M_local_0[0] = mac_fixpt_add_temp_8[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_41 = {1'b0, {mac_fixpt_M_local_0[0], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_17 = W[4];
end
else begin
mac_fixpt_t_17 = 14'b00000000000000;
end
mac_fixpt_add_cast_42 = {1'b0, mac_fixpt_t_17};
mac_fixpt_add_cast_43 = {1'b0, mac_fixpt_add_cast_42};
mac_fixpt_add_temp_13 = mac_fixpt_add_cast_41 + mac_fixpt_add_cast_43;
mac_fixpt_M_local_0[0] = mac_fixpt_add_temp_13[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_59 = {1'b0, {mac_fixpt_M_local_0[0], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_23 = W[5];
end
else begin
mac_fixpt_t_23 = 14'b00000000000000;
end
mac_fixpt_add_cast_60 = {1'b0, mac_fixpt_t_23};
mac_fixpt_add_cast_61 = {1'b0, mac_fixpt_add_cast_60};
mac_fixpt_add_temp_19 = mac_fixpt_add_cast_59 + mac_fixpt_add_cast_61;
mac_fixpt_M_local_0[0] = mac_fixpt_add_temp_19[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_80 = {1'b0, {mac_fixpt_M_local_0[0], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_30 = W[6];
end
else begin
mac_fixpt_t_30 = 14'b00000000000000;
end
mac_fixpt_add_cast_81 = {1'b0, mac_fixpt_t_30};
mac_fixpt_add_cast_82 = {1'b0, mac_fixpt_add_cast_81};
mac_fixpt_add_temp_26 = mac_fixpt_add_cast_80 + mac_fixpt_add_cast_82;
mac_fixpt_M_local_0[0] = mac_fixpt_add_temp_26[14:1];
end
end
if (7'b0000010 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_2 = {1'b0, {mac_fixpt_M_local_0[1], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_4 = W[0];
end
else begin
mac_fixpt_t_4 = 14'b00000000000000;
end
mac_fixpt_add_cast_3 = {1'b0, mac_fixpt_t_4};
mac_fixpt_add_cast_4 = {1'b0, mac_fixpt_add_cast_3};
mac_fixpt_add_temp_0 = mac_fixpt_add_cast_2 + mac_fixpt_add_cast_4;
mac_fixpt_M_local_0[1] = mac_fixpt_add_temp_0[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_11 = {1'b0, {mac_fixpt_M_local_0[1], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_7 = W[1];
end
else begin
mac_fixpt_t_7 = 14'b00000000000000;
end
mac_fixpt_add_cast_12 = {1'b0, mac_fixpt_t_7};
mac_fixpt_add_cast_13 = {1'b0, mac_fixpt_add_cast_12};
mac_fixpt_add_temp_3 = mac_fixpt_add_cast_11 + mac_fixpt_add_cast_13;
mac_fixpt_M_local_0[1] = mac_fixpt_add_temp_3[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_23 = {1'b0, {mac_fixpt_M_local_0[1], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_11 = W[2];
end
else begin
mac_fixpt_t_11 = 14'b00000000000000;
end
mac_fixpt_add_cast_24 = {1'b0, mac_fixpt_t_11};
mac_fixpt_add_cast_25 = {1'b0, mac_fixpt_add_cast_24};
mac_fixpt_add_temp_7 = mac_fixpt_add_cast_23 + mac_fixpt_add_cast_25;
mac_fixpt_M_local_0[1] = mac_fixpt_add_temp_7[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_38 = {1'b0, {mac_fixpt_M_local_0[1], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_16 = W[3];
end
else begin
mac_fixpt_t_16 = 14'b00000000000000;
end
mac_fixpt_add_cast_39 = {1'b0, mac_fixpt_t_16};
mac_fixpt_add_cast_40 = {1'b0, mac_fixpt_add_cast_39};
mac_fixpt_add_temp_12 = mac_fixpt_add_cast_38 + mac_fixpt_add_cast_40;
mac_fixpt_M_local_0[1] = mac_fixpt_add_temp_12[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_56 = {1'b0, {mac_fixpt_M_local_0[1], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_22 = W[4];
end
else begin
mac_fixpt_t_22 = 14'b00000000000000;
end
mac_fixpt_add_cast_57 = {1'b0, mac_fixpt_t_22};
mac_fixpt_add_cast_58 = {1'b0, mac_fixpt_add_cast_57};
mac_fixpt_add_temp_18 = mac_fixpt_add_cast_56 + mac_fixpt_add_cast_58;
mac_fixpt_M_local_0[1] = mac_fixpt_add_temp_18[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_77 = {1'b0, {mac_fixpt_M_local_0[1], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_29 = W[5];
end
else begin
mac_fixpt_t_29 = 14'b00000000000000;
end
mac_fixpt_add_cast_78 = {1'b0, mac_fixpt_t_29};
mac_fixpt_add_cast_79 = {1'b0, mac_fixpt_add_cast_78};
mac_fixpt_add_temp_25 = mac_fixpt_add_cast_77 + mac_fixpt_add_cast_79;
mac_fixpt_M_local_0[1] = mac_fixpt_add_temp_25[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_101 = {1'b0, {mac_fixpt_M_local_0[1], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_37 = W[6];
end
else begin
mac_fixpt_t_37 = 14'b00000000000000;
end
mac_fixpt_add_cast_102 = {1'b0, mac_fixpt_t_37};
mac_fixpt_add_cast_103 = {1'b0, mac_fixpt_add_cast_102};
mac_fixpt_add_temp_33 = mac_fixpt_add_cast_101 + mac_fixpt_add_cast_103;
mac_fixpt_M_local_0[1] = mac_fixpt_add_temp_33[14:1];
end
end
if (7'b0000011 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_8 = {1'b0, {mac_fixpt_M_local_0[2], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_6 = W[0];
end
else begin
mac_fixpt_t_6 = 14'b00000000000000;
end
mac_fixpt_add_cast_9 = {1'b0, mac_fixpt_t_6};
mac_fixpt_add_cast_10 = {1'b0, mac_fixpt_add_cast_9};
mac_fixpt_add_temp_2 = mac_fixpt_add_cast_8 + mac_fixpt_add_cast_10;
mac_fixpt_M_local_0[2] = mac_fixpt_add_temp_2[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_20 = {1'b0, {mac_fixpt_M_local_0[2], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_10 = W[1];
end
else begin
mac_fixpt_t_10 = 14'b00000000000000;
end
mac_fixpt_add_cast_21 = {1'b0, mac_fixpt_t_10};
mac_fixpt_add_cast_22 = {1'b0, mac_fixpt_add_cast_21};
mac_fixpt_add_temp_6 = mac_fixpt_add_cast_20 + mac_fixpt_add_cast_22;
mac_fixpt_M_local_0[2] = mac_fixpt_add_temp_6[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_35 = {1'b0, {mac_fixpt_M_local_0[2], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_15 = W[2];
end
else begin
mac_fixpt_t_15 = 14'b00000000000000;
end
mac_fixpt_add_cast_36 = {1'b0, mac_fixpt_t_15};
mac_fixpt_add_cast_37 = {1'b0, mac_fixpt_add_cast_36};
mac_fixpt_add_temp_11 = mac_fixpt_add_cast_35 + mac_fixpt_add_cast_37;
mac_fixpt_M_local_0[2] = mac_fixpt_add_temp_11[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_53 = {1'b0, {mac_fixpt_M_local_0[2], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_21 = W[3];
end
else begin
mac_fixpt_t_21 = 14'b00000000000000;
end
mac_fixpt_add_cast_54 = {1'b0, mac_fixpt_t_21};
mac_fixpt_add_cast_55 = {1'b0, mac_fixpt_add_cast_54};
mac_fixpt_add_temp_17 = mac_fixpt_add_cast_53 + mac_fixpt_add_cast_55;
mac_fixpt_M_local_0[2] = mac_fixpt_add_temp_17[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_74 = {1'b0, {mac_fixpt_M_local_0[2], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_28 = W[4];
end
else begin
mac_fixpt_t_28 = 14'b00000000000000;
end
mac_fixpt_add_cast_75 = {1'b0, mac_fixpt_t_28};
mac_fixpt_add_cast_76 = {1'b0, mac_fixpt_add_cast_75};
mac_fixpt_add_temp_24 = mac_fixpt_add_cast_74 + mac_fixpt_add_cast_76;
mac_fixpt_M_local_0[2] = mac_fixpt_add_temp_24[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_98 = {1'b0, {mac_fixpt_M_local_0[2], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_36 = W[5];
end
else begin
mac_fixpt_t_36 = 14'b00000000000000;
end
mac_fixpt_add_cast_99 = {1'b0, mac_fixpt_t_36};
mac_fixpt_add_cast_100 = {1'b0, mac_fixpt_add_cast_99};
mac_fixpt_add_temp_32 = mac_fixpt_add_cast_98 + mac_fixpt_add_cast_100;
mac_fixpt_M_local_0[2] = mac_fixpt_add_temp_32[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_122 = {1'b0, {mac_fixpt_M_local_0[2], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_44 = W[6];
end
else begin
mac_fixpt_t_44 = 14'b00000000000000;
end
mac_fixpt_add_cast_123 = {1'b0, mac_fixpt_t_44};
mac_fixpt_add_cast_124 = {1'b0, mac_fixpt_add_cast_123};
mac_fixpt_add_temp_40 = mac_fixpt_add_cast_122 + mac_fixpt_add_cast_124;
mac_fixpt_M_local_0[2] = mac_fixpt_add_temp_40[14:1];
end
end
if (7'b0000100 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_17 = {1'b0, {mac_fixpt_M_local_0[3], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_9 = W[0];
end
else begin
mac_fixpt_t_9 = 14'b00000000000000;
end
mac_fixpt_add_cast_18 = {1'b0, mac_fixpt_t_9};
mac_fixpt_add_cast_19 = {1'b0, mac_fixpt_add_cast_18};
mac_fixpt_add_temp_5 = mac_fixpt_add_cast_17 + mac_fixpt_add_cast_19;
mac_fixpt_M_local_0[3] = mac_fixpt_add_temp_5[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_32 = {1'b0, {mac_fixpt_M_local_0[3], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_14 = W[1];
end
else begin
mac_fixpt_t_14 = 14'b00000000000000;
end
mac_fixpt_add_cast_33 = {1'b0, mac_fixpt_t_14};
mac_fixpt_add_cast_34 = {1'b0, mac_fixpt_add_cast_33};
mac_fixpt_add_temp_10 = mac_fixpt_add_cast_32 + mac_fixpt_add_cast_34;
mac_fixpt_M_local_0[3] = mac_fixpt_add_temp_10[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_50 = {1'b0, {mac_fixpt_M_local_0[3], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_20 = W[2];
end
else begin
mac_fixpt_t_20 = 14'b00000000000000;
end
mac_fixpt_add_cast_51 = {1'b0, mac_fixpt_t_20};
mac_fixpt_add_cast_52 = {1'b0, mac_fixpt_add_cast_51};
mac_fixpt_add_temp_16 = mac_fixpt_add_cast_50 + mac_fixpt_add_cast_52;
mac_fixpt_M_local_0[3] = mac_fixpt_add_temp_16[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_71 = {1'b0, {mac_fixpt_M_local_0[3], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_27 = W[3];
end
else begin
mac_fixpt_t_27 = 14'b00000000000000;
end
mac_fixpt_add_cast_72 = {1'b0, mac_fixpt_t_27};
mac_fixpt_add_cast_73 = {1'b0, mac_fixpt_add_cast_72};
mac_fixpt_add_temp_23 = mac_fixpt_add_cast_71 + mac_fixpt_add_cast_73;
mac_fixpt_M_local_0[3] = mac_fixpt_add_temp_23[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_95 = {1'b0, {mac_fixpt_M_local_0[3], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_35 = W[4];
end
else begin
mac_fixpt_t_35 = 14'b00000000000000;
end
mac_fixpt_add_cast_96 = {1'b0, mac_fixpt_t_35};
mac_fixpt_add_cast_97 = {1'b0, mac_fixpt_add_cast_96};
mac_fixpt_add_temp_31 = mac_fixpt_add_cast_95 + mac_fixpt_add_cast_97;
mac_fixpt_M_local_0[3] = mac_fixpt_add_temp_31[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_119 = {1'b0, {mac_fixpt_M_local_0[3], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_43 = W[5];
end
else begin
mac_fixpt_t_43 = 14'b00000000000000;
end
mac_fixpt_add_cast_120 = {1'b0, mac_fixpt_t_43};
mac_fixpt_add_cast_121 = {1'b0, mac_fixpt_add_cast_120};
mac_fixpt_add_temp_39 = mac_fixpt_add_cast_119 + mac_fixpt_add_cast_121;
mac_fixpt_M_local_0[3] = mac_fixpt_add_temp_39[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_143 = {1'b0, {mac_fixpt_M_local_0[3], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_51 = W[6];
end
else begin
mac_fixpt_t_51 = 14'b00000000000000;
end
mac_fixpt_add_cast_144 = {1'b0, mac_fixpt_t_51};
mac_fixpt_add_cast_145 = {1'b0, mac_fixpt_add_cast_144};
mac_fixpt_add_temp_47 = mac_fixpt_add_cast_143 + mac_fixpt_add_cast_145;
mac_fixpt_M_local_0[3] = mac_fixpt_add_temp_47[14:1];
end
end
if (7'b0000101 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_29 = {1'b0, {mac_fixpt_M_local_0[4], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_13 = W[0];
end
else begin
mac_fixpt_t_13 = 14'b00000000000000;
end
mac_fixpt_add_cast_30 = {1'b0, mac_fixpt_t_13};
mac_fixpt_add_cast_31 = {1'b0, mac_fixpt_add_cast_30};
mac_fixpt_add_temp_9 = mac_fixpt_add_cast_29 + mac_fixpt_add_cast_31;
mac_fixpt_M_local_0[4] = mac_fixpt_add_temp_9[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_47 = {1'b0, {mac_fixpt_M_local_0[4], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_19 = W[1];
end
else begin
mac_fixpt_t_19 = 14'b00000000000000;
end
mac_fixpt_add_cast_48 = {1'b0, mac_fixpt_t_19};
mac_fixpt_add_cast_49 = {1'b0, mac_fixpt_add_cast_48};
mac_fixpt_add_temp_15 = mac_fixpt_add_cast_47 + mac_fixpt_add_cast_49;
mac_fixpt_M_local_0[4] = mac_fixpt_add_temp_15[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_68 = {1'b0, {mac_fixpt_M_local_0[4], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_26 = W[2];
end
else begin
mac_fixpt_t_26 = 14'b00000000000000;
end
mac_fixpt_add_cast_69 = {1'b0, mac_fixpt_t_26};
mac_fixpt_add_cast_70 = {1'b0, mac_fixpt_add_cast_69};
mac_fixpt_add_temp_22 = mac_fixpt_add_cast_68 + mac_fixpt_add_cast_70;
mac_fixpt_M_local_0[4] = mac_fixpt_add_temp_22[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_92 = {1'b0, {mac_fixpt_M_local_0[4], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_34 = W[3];
end
else begin
mac_fixpt_t_34 = 14'b00000000000000;
end
mac_fixpt_add_cast_93 = {1'b0, mac_fixpt_t_34};
mac_fixpt_add_cast_94 = {1'b0, mac_fixpt_add_cast_93};
mac_fixpt_add_temp_30 = mac_fixpt_add_cast_92 + mac_fixpt_add_cast_94;
mac_fixpt_M_local_0[4] = mac_fixpt_add_temp_30[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_116 = {1'b0, {mac_fixpt_M_local_0[4], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_42 = W[4];
end
else begin
mac_fixpt_t_42 = 14'b00000000000000;
end
mac_fixpt_add_cast_117 = {1'b0, mac_fixpt_t_42};
mac_fixpt_add_cast_118 = {1'b0, mac_fixpt_add_cast_117};
mac_fixpt_add_temp_38 = mac_fixpt_add_cast_116 + mac_fixpt_add_cast_118;
mac_fixpt_M_local_0[4] = mac_fixpt_add_temp_38[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_140 = {1'b0, {mac_fixpt_M_local_0[4], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_50 = W[5];
end
else begin
mac_fixpt_t_50 = 14'b00000000000000;
end
mac_fixpt_add_cast_141 = {1'b0, mac_fixpt_t_50};
mac_fixpt_add_cast_142 = {1'b0, mac_fixpt_add_cast_141};
mac_fixpt_add_temp_46 = mac_fixpt_add_cast_140 + mac_fixpt_add_cast_142;
mac_fixpt_M_local_0[4] = mac_fixpt_add_temp_46[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_164 = {1'b0, {mac_fixpt_M_local_0[4], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_58 = W[6];
end
else begin
mac_fixpt_t_58 = 14'b00000000000000;
end
mac_fixpt_add_cast_165 = {1'b0, mac_fixpt_t_58};
mac_fixpt_add_cast_166 = {1'b0, mac_fixpt_add_cast_165};
mac_fixpt_add_temp_54 = mac_fixpt_add_cast_164 + mac_fixpt_add_cast_166;
mac_fixpt_M_local_0[4] = mac_fixpt_add_temp_54[14:1];
end
end
if (7'b0000110 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_44 = {1'b0, {mac_fixpt_M_local_0[5], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_18 = W[0];
end
else begin
mac_fixpt_t_18 = 14'b00000000000000;
end
mac_fixpt_add_cast_45 = {1'b0, mac_fixpt_t_18};
mac_fixpt_add_cast_46 = {1'b0, mac_fixpt_add_cast_45};
mac_fixpt_add_temp_14 = mac_fixpt_add_cast_44 + mac_fixpt_add_cast_46;
mac_fixpt_M_local_0[5] = mac_fixpt_add_temp_14[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_65 = {1'b0, {mac_fixpt_M_local_0[5], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_25 = W[1];
end
else begin
mac_fixpt_t_25 = 14'b00000000000000;
end
mac_fixpt_add_cast_66 = {1'b0, mac_fixpt_t_25};
mac_fixpt_add_cast_67 = {1'b0, mac_fixpt_add_cast_66};
mac_fixpt_add_temp_21 = mac_fixpt_add_cast_65 + mac_fixpt_add_cast_67;
mac_fixpt_M_local_0[5] = mac_fixpt_add_temp_21[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_89 = {1'b0, {mac_fixpt_M_local_0[5], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_33 = W[2];
end
else begin
mac_fixpt_t_33 = 14'b00000000000000;
end
mac_fixpt_add_cast_90 = {1'b0, mac_fixpt_t_33};
mac_fixpt_add_cast_91 = {1'b0, mac_fixpt_add_cast_90};
mac_fixpt_add_temp_29 = mac_fixpt_add_cast_89 + mac_fixpt_add_cast_91;
mac_fixpt_M_local_0[5] = mac_fixpt_add_temp_29[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_113 = {1'b0, {mac_fixpt_M_local_0[5], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_41 = W[3];
end
else begin
mac_fixpt_t_41 = 14'b00000000000000;
end
mac_fixpt_add_cast_114 = {1'b0, mac_fixpt_t_41};
mac_fixpt_add_cast_115 = {1'b0, mac_fixpt_add_cast_114};
mac_fixpt_add_temp_37 = mac_fixpt_add_cast_113 + mac_fixpt_add_cast_115;
mac_fixpt_M_local_0[5] = mac_fixpt_add_temp_37[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_137 = {1'b0, {mac_fixpt_M_local_0[5], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_49 = W[4];
end
else begin
mac_fixpt_t_49 = 14'b00000000000000;
end
mac_fixpt_add_cast_138 = {1'b0, mac_fixpt_t_49};
mac_fixpt_add_cast_139 = {1'b0, mac_fixpt_add_cast_138};
mac_fixpt_add_temp_45 = mac_fixpt_add_cast_137 + mac_fixpt_add_cast_139;
mac_fixpt_M_local_0[5] = mac_fixpt_add_temp_45[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_161 = {1'b0, {mac_fixpt_M_local_0[5], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_57 = W[5];
end
else begin
mac_fixpt_t_57 = 14'b00000000000000;
end
mac_fixpt_add_cast_162 = {1'b0, mac_fixpt_t_57};
mac_fixpt_add_cast_163 = {1'b0, mac_fixpt_add_cast_162};
mac_fixpt_add_temp_53 = mac_fixpt_add_cast_161 + mac_fixpt_add_cast_163;
mac_fixpt_M_local_0[5] = mac_fixpt_add_temp_53[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_185 = {1'b0, {mac_fixpt_M_local_0[5], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_65 = W[6];
end
else begin
mac_fixpt_t_65 = 14'b00000000000000;
end
mac_fixpt_add_cast_186 = {1'b0, mac_fixpt_t_65};
mac_fixpt_add_cast_187 = {1'b0, mac_fixpt_add_cast_186};
mac_fixpt_add_temp_61 = mac_fixpt_add_cast_185 + mac_fixpt_add_cast_187;
mac_fixpt_M_local_0[5] = mac_fixpt_add_temp_61[14:1];
end
end
if (7'b0000111 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_62 = {1'b0, {mac_fixpt_M_local_0[6], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_24 = W[0];
end
else begin
mac_fixpt_t_24 = 14'b00000000000000;
end
mac_fixpt_add_cast_63 = {1'b0, mac_fixpt_t_24};
mac_fixpt_add_cast_64 = {1'b0, mac_fixpt_add_cast_63};
mac_fixpt_add_temp_20 = mac_fixpt_add_cast_62 + mac_fixpt_add_cast_64;
mac_fixpt_M_local_0[6] = mac_fixpt_add_temp_20[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_86 = {1'b0, {mac_fixpt_M_local_0[6], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_32 = W[1];
end
else begin
mac_fixpt_t_32 = 14'b00000000000000;
end
mac_fixpt_add_cast_87 = {1'b0, mac_fixpt_t_32};
mac_fixpt_add_cast_88 = {1'b0, mac_fixpt_add_cast_87};
mac_fixpt_add_temp_28 = mac_fixpt_add_cast_86 + mac_fixpt_add_cast_88;
mac_fixpt_M_local_0[6] = mac_fixpt_add_temp_28[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_110 = {1'b0, {mac_fixpt_M_local_0[6], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_40 = W[2];
end
else begin
mac_fixpt_t_40 = 14'b00000000000000;
end
mac_fixpt_add_cast_111 = {1'b0, mac_fixpt_t_40};
mac_fixpt_add_cast_112 = {1'b0, mac_fixpt_add_cast_111};
mac_fixpt_add_temp_36 = mac_fixpt_add_cast_110 + mac_fixpt_add_cast_112;
mac_fixpt_M_local_0[6] = mac_fixpt_add_temp_36[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_134 = {1'b0, {mac_fixpt_M_local_0[6], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_48 = W[3];
end
else begin
mac_fixpt_t_48 = 14'b00000000000000;
end
mac_fixpt_add_cast_135 = {1'b0, mac_fixpt_t_48};
mac_fixpt_add_cast_136 = {1'b0, mac_fixpt_add_cast_135};
mac_fixpt_add_temp_44 = mac_fixpt_add_cast_134 + mac_fixpt_add_cast_136;
mac_fixpt_M_local_0[6] = mac_fixpt_add_temp_44[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_158 = {1'b0, {mac_fixpt_M_local_0[6], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_56 = W[4];
end
else begin
mac_fixpt_t_56 = 14'b00000000000000;
end
mac_fixpt_add_cast_159 = {1'b0, mac_fixpt_t_56};
mac_fixpt_add_cast_160 = {1'b0, mac_fixpt_add_cast_159};
mac_fixpt_add_temp_52 = mac_fixpt_add_cast_158 + mac_fixpt_add_cast_160;
mac_fixpt_M_local_0[6] = mac_fixpt_add_temp_52[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_182 = {1'b0, {mac_fixpt_M_local_0[6], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_64 = W[5];
end
else begin
mac_fixpt_t_64 = 14'b00000000000000;
end
mac_fixpt_add_cast_183 = {1'b0, mac_fixpt_t_64};
mac_fixpt_add_cast_184 = {1'b0, mac_fixpt_add_cast_183};
mac_fixpt_add_temp_60 = mac_fixpt_add_cast_182 + mac_fixpt_add_cast_184;
mac_fixpt_M_local_0[6] = mac_fixpt_add_temp_60[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_206 = {1'b0, {mac_fixpt_M_local_0[6], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_72 = W[6];
end
else begin
mac_fixpt_t_72 = 14'b00000000000000;
end
mac_fixpt_add_cast_207 = {1'b0, mac_fixpt_t_72};
mac_fixpt_add_cast_208 = {1'b0, mac_fixpt_add_cast_207};
mac_fixpt_add_temp_68 = mac_fixpt_add_cast_206 + mac_fixpt_add_cast_208;
mac_fixpt_M_local_0[6] = mac_fixpt_add_temp_68[14:1];
end
end
if (7'b0001000 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_83 = {1'b0, {mac_fixpt_M_local_0[7], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_31 = W[0];
end
else begin
mac_fixpt_t_31 = 14'b00000000000000;
end
mac_fixpt_add_cast_84 = {1'b0, mac_fixpt_t_31};
mac_fixpt_add_cast_85 = {1'b0, mac_fixpt_add_cast_84};
mac_fixpt_add_temp_27 = mac_fixpt_add_cast_83 + mac_fixpt_add_cast_85;
mac_fixpt_M_local_0[7] = mac_fixpt_add_temp_27[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_107 = {1'b0, {mac_fixpt_M_local_0[7], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_39 = W[1];
end
else begin
mac_fixpt_t_39 = 14'b00000000000000;
end
mac_fixpt_add_cast_108 = {1'b0, mac_fixpt_t_39};
mac_fixpt_add_cast_109 = {1'b0, mac_fixpt_add_cast_108};
mac_fixpt_add_temp_35 = mac_fixpt_add_cast_107 + mac_fixpt_add_cast_109;
mac_fixpt_M_local_0[7] = mac_fixpt_add_temp_35[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_131 = {1'b0, {mac_fixpt_M_local_0[7], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_47 = W[2];
end
else begin
mac_fixpt_t_47 = 14'b00000000000000;
end
mac_fixpt_add_cast_132 = {1'b0, mac_fixpt_t_47};
mac_fixpt_add_cast_133 = {1'b0, mac_fixpt_add_cast_132};
mac_fixpt_add_temp_43 = mac_fixpt_add_cast_131 + mac_fixpt_add_cast_133;
mac_fixpt_M_local_0[7] = mac_fixpt_add_temp_43[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_155 = {1'b0, {mac_fixpt_M_local_0[7], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_55 = W[3];
end
else begin
mac_fixpt_t_55 = 14'b00000000000000;
end
mac_fixpt_add_cast_156 = {1'b0, mac_fixpt_t_55};
mac_fixpt_add_cast_157 = {1'b0, mac_fixpt_add_cast_156};
mac_fixpt_add_temp_51 = mac_fixpt_add_cast_155 + mac_fixpt_add_cast_157;
mac_fixpt_M_local_0[7] = mac_fixpt_add_temp_51[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_179 = {1'b0, {mac_fixpt_M_local_0[7], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_63 = W[4];
end
else begin
mac_fixpt_t_63 = 14'b00000000000000;
end
mac_fixpt_add_cast_180 = {1'b0, mac_fixpt_t_63};
mac_fixpt_add_cast_181 = {1'b0, mac_fixpt_add_cast_180};
mac_fixpt_add_temp_59 = mac_fixpt_add_cast_179 + mac_fixpt_add_cast_181;
mac_fixpt_M_local_0[7] = mac_fixpt_add_temp_59[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_203 = {1'b0, {mac_fixpt_M_local_0[7], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_71 = W[5];
end
else begin
mac_fixpt_t_71 = 14'b00000000000000;
end
mac_fixpt_add_cast_204 = {1'b0, mac_fixpt_t_71};
mac_fixpt_add_cast_205 = {1'b0, mac_fixpt_add_cast_204};
mac_fixpt_add_temp_67 = mac_fixpt_add_cast_203 + mac_fixpt_add_cast_205;
mac_fixpt_M_local_0[7] = mac_fixpt_add_temp_67[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_227 = {1'b0, {mac_fixpt_M_local_0[7], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_79 = W[6];
end
else begin
mac_fixpt_t_79 = 14'b00000000000000;
end
mac_fixpt_add_cast_228 = {1'b0, mac_fixpt_t_79};
mac_fixpt_add_cast_229 = {1'b0, mac_fixpt_add_cast_228};
mac_fixpt_add_temp_75 = mac_fixpt_add_cast_227 + mac_fixpt_add_cast_229;
mac_fixpt_M_local_0[7] = mac_fixpt_add_temp_75[14:1];
end
end
if (7'b0001001 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_104 = {1'b0, {mac_fixpt_M_local_0[8], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_38 = W[0];
end
else begin
mac_fixpt_t_38 = 14'b00000000000000;
end
mac_fixpt_add_cast_105 = {1'b0, mac_fixpt_t_38};
mac_fixpt_add_cast_106 = {1'b0, mac_fixpt_add_cast_105};
mac_fixpt_add_temp_34 = mac_fixpt_add_cast_104 + mac_fixpt_add_cast_106;
mac_fixpt_M_local_0[8] = mac_fixpt_add_temp_34[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_128 = {1'b0, {mac_fixpt_M_local_0[8], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_46 = W[1];
end
else begin
mac_fixpt_t_46 = 14'b00000000000000;
end
mac_fixpt_add_cast_129 = {1'b0, mac_fixpt_t_46};
mac_fixpt_add_cast_130 = {1'b0, mac_fixpt_add_cast_129};
mac_fixpt_add_temp_42 = mac_fixpt_add_cast_128 + mac_fixpt_add_cast_130;
mac_fixpt_M_local_0[8] = mac_fixpt_add_temp_42[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_152 = {1'b0, {mac_fixpt_M_local_0[8], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_54 = W[2];
end
else begin
mac_fixpt_t_54 = 14'b00000000000000;
end
mac_fixpt_add_cast_153 = {1'b0, mac_fixpt_t_54};
mac_fixpt_add_cast_154 = {1'b0, mac_fixpt_add_cast_153};
mac_fixpt_add_temp_50 = mac_fixpt_add_cast_152 + mac_fixpt_add_cast_154;
mac_fixpt_M_local_0[8] = mac_fixpt_add_temp_50[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_176 = {1'b0, {mac_fixpt_M_local_0[8], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_62 = W[3];
end
else begin
mac_fixpt_t_62 = 14'b00000000000000;
end
mac_fixpt_add_cast_177 = {1'b0, mac_fixpt_t_62};
mac_fixpt_add_cast_178 = {1'b0, mac_fixpt_add_cast_177};
mac_fixpt_add_temp_58 = mac_fixpt_add_cast_176 + mac_fixpt_add_cast_178;
mac_fixpt_M_local_0[8] = mac_fixpt_add_temp_58[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_200 = {1'b0, {mac_fixpt_M_local_0[8], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_70 = W[4];
end
else begin
mac_fixpt_t_70 = 14'b00000000000000;
end
mac_fixpt_add_cast_201 = {1'b0, mac_fixpt_t_70};
mac_fixpt_add_cast_202 = {1'b0, mac_fixpt_add_cast_201};
mac_fixpt_add_temp_66 = mac_fixpt_add_cast_200 + mac_fixpt_add_cast_202;
mac_fixpt_M_local_0[8] = mac_fixpt_add_temp_66[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_224 = {1'b0, {mac_fixpt_M_local_0[8], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_78 = W[5];
end
else begin
mac_fixpt_t_78 = 14'b00000000000000;
end
mac_fixpt_add_cast_225 = {1'b0, mac_fixpt_t_78};
mac_fixpt_add_cast_226 = {1'b0, mac_fixpt_add_cast_225};
mac_fixpt_add_temp_74 = mac_fixpt_add_cast_224 + mac_fixpt_add_cast_226;
mac_fixpt_M_local_0[8] = mac_fixpt_add_temp_74[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_248 = {1'b0, {mac_fixpt_M_local_0[8], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_86 = W[6];
end
else begin
mac_fixpt_t_86 = 14'b00000000000000;
end
mac_fixpt_add_cast_249 = {1'b0, mac_fixpt_t_86};
mac_fixpt_add_cast_250 = {1'b0, mac_fixpt_add_cast_249};
mac_fixpt_add_temp_82 = mac_fixpt_add_cast_248 + mac_fixpt_add_cast_250;
mac_fixpt_M_local_0[8] = mac_fixpt_add_temp_82[14:1];
end
end
if (7'b0001010 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_125 = {1'b0, {mac_fixpt_M_local_0[9], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_45 = W[0];
end
else begin
mac_fixpt_t_45 = 14'b00000000000000;
end
mac_fixpt_add_cast_126 = {1'b0, mac_fixpt_t_45};
mac_fixpt_add_cast_127 = {1'b0, mac_fixpt_add_cast_126};
mac_fixpt_add_temp_41 = mac_fixpt_add_cast_125 + mac_fixpt_add_cast_127;
mac_fixpt_M_local_0[9] = mac_fixpt_add_temp_41[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_149 = {1'b0, {mac_fixpt_M_local_0[9], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_53 = W[1];
end
else begin
mac_fixpt_t_53 = 14'b00000000000000;
end
mac_fixpt_add_cast_150 = {1'b0, mac_fixpt_t_53};
mac_fixpt_add_cast_151 = {1'b0, mac_fixpt_add_cast_150};
mac_fixpt_add_temp_49 = mac_fixpt_add_cast_149 + mac_fixpt_add_cast_151;
mac_fixpt_M_local_0[9] = mac_fixpt_add_temp_49[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_173 = {1'b0, {mac_fixpt_M_local_0[9], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_61 = W[2];
end
else begin
mac_fixpt_t_61 = 14'b00000000000000;
end
mac_fixpt_add_cast_174 = {1'b0, mac_fixpt_t_61};
mac_fixpt_add_cast_175 = {1'b0, mac_fixpt_add_cast_174};
mac_fixpt_add_temp_57 = mac_fixpt_add_cast_173 + mac_fixpt_add_cast_175;
mac_fixpt_M_local_0[9] = mac_fixpt_add_temp_57[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_197 = {1'b0, {mac_fixpt_M_local_0[9], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_69 = W[3];
end
else begin
mac_fixpt_t_69 = 14'b00000000000000;
end
mac_fixpt_add_cast_198 = {1'b0, mac_fixpt_t_69};
mac_fixpt_add_cast_199 = {1'b0, mac_fixpt_add_cast_198};
mac_fixpt_add_temp_65 = mac_fixpt_add_cast_197 + mac_fixpt_add_cast_199;
mac_fixpt_M_local_0[9] = mac_fixpt_add_temp_65[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_221 = {1'b0, {mac_fixpt_M_local_0[9], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_77 = W[4];
end
else begin
mac_fixpt_t_77 = 14'b00000000000000;
end
mac_fixpt_add_cast_222 = {1'b0, mac_fixpt_t_77};
mac_fixpt_add_cast_223 = {1'b0, mac_fixpt_add_cast_222};
mac_fixpt_add_temp_73 = mac_fixpt_add_cast_221 + mac_fixpt_add_cast_223;
mac_fixpt_M_local_0[9] = mac_fixpt_add_temp_73[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_245 = {1'b0, {mac_fixpt_M_local_0[9], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_85 = W[5];
end
else begin
mac_fixpt_t_85 = 14'b00000000000000;
end
mac_fixpt_add_cast_246 = {1'b0, mac_fixpt_t_85};
mac_fixpt_add_cast_247 = {1'b0, mac_fixpt_add_cast_246};
mac_fixpt_add_temp_81 = mac_fixpt_add_cast_245 + mac_fixpt_add_cast_247;
mac_fixpt_M_local_0[9] = mac_fixpt_add_temp_81[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_269 = {1'b0, {mac_fixpt_M_local_0[9], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_93 = W[6];
end
else begin
mac_fixpt_t_93 = 14'b00000000000000;
end
mac_fixpt_add_cast_270 = {1'b0, mac_fixpt_t_93};
mac_fixpt_add_cast_271 = {1'b0, mac_fixpt_add_cast_270};
mac_fixpt_add_temp_89 = mac_fixpt_add_cast_269 + mac_fixpt_add_cast_271;
mac_fixpt_M_local_0[9] = mac_fixpt_add_temp_89[14:1];
end
end
if (7'b0001011 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_146 = {1'b0, {mac_fixpt_M_local_0[10], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_52 = W[0];
end
else begin
mac_fixpt_t_52 = 14'b00000000000000;
end
mac_fixpt_add_cast_147 = {1'b0, mac_fixpt_t_52};
mac_fixpt_add_cast_148 = {1'b0, mac_fixpt_add_cast_147};
mac_fixpt_add_temp_48 = mac_fixpt_add_cast_146 + mac_fixpt_add_cast_148;
mac_fixpt_M_local_0[10] = mac_fixpt_add_temp_48[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_170 = {1'b0, {mac_fixpt_M_local_0[10], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_60 = W[1];
end
else begin
mac_fixpt_t_60 = 14'b00000000000000;
end
mac_fixpt_add_cast_171 = {1'b0, mac_fixpt_t_60};
mac_fixpt_add_cast_172 = {1'b0, mac_fixpt_add_cast_171};
mac_fixpt_add_temp_56 = mac_fixpt_add_cast_170 + mac_fixpt_add_cast_172;
mac_fixpt_M_local_0[10] = mac_fixpt_add_temp_56[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_194 = {1'b0, {mac_fixpt_M_local_0[10], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_68 = W[2];
end
else begin
mac_fixpt_t_68 = 14'b00000000000000;
end
mac_fixpt_add_cast_195 = {1'b0, mac_fixpt_t_68};
mac_fixpt_add_cast_196 = {1'b0, mac_fixpt_add_cast_195};
mac_fixpt_add_temp_64 = mac_fixpt_add_cast_194 + mac_fixpt_add_cast_196;
mac_fixpt_M_local_0[10] = mac_fixpt_add_temp_64[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_218 = {1'b0, {mac_fixpt_M_local_0[10], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_76 = W[3];
end
else begin
mac_fixpt_t_76 = 14'b00000000000000;
end
mac_fixpt_add_cast_219 = {1'b0, mac_fixpt_t_76};
mac_fixpt_add_cast_220 = {1'b0, mac_fixpt_add_cast_219};
mac_fixpt_add_temp_72 = mac_fixpt_add_cast_218 + mac_fixpt_add_cast_220;
mac_fixpt_M_local_0[10] = mac_fixpt_add_temp_72[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_242 = {1'b0, {mac_fixpt_M_local_0[10], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_84 = W[4];
end
else begin
mac_fixpt_t_84 = 14'b00000000000000;
end
mac_fixpt_add_cast_243 = {1'b0, mac_fixpt_t_84};
mac_fixpt_add_cast_244 = {1'b0, mac_fixpt_add_cast_243};
mac_fixpt_add_temp_80 = mac_fixpt_add_cast_242 + mac_fixpt_add_cast_244;
mac_fixpt_M_local_0[10] = mac_fixpt_add_temp_80[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_266 = {1'b0, {mac_fixpt_M_local_0[10], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_92 = W[5];
end
else begin
mac_fixpt_t_92 = 14'b00000000000000;
end
mac_fixpt_add_cast_267 = {1'b0, mac_fixpt_t_92};
mac_fixpt_add_cast_268 = {1'b0, mac_fixpt_add_cast_267};
mac_fixpt_add_temp_88 = mac_fixpt_add_cast_266 + mac_fixpt_add_cast_268;
mac_fixpt_M_local_0[10] = mac_fixpt_add_temp_88[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_290 = {1'b0, {mac_fixpt_M_local_0[10], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_100 = W[6];
end
else begin
mac_fixpt_t_100 = 14'b00000000000000;
end
mac_fixpt_add_cast_291 = {1'b0, mac_fixpt_t_100};
mac_fixpt_add_cast_292 = {1'b0, mac_fixpt_add_cast_291};
mac_fixpt_add_temp_96 = mac_fixpt_add_cast_290 + mac_fixpt_add_cast_292;
mac_fixpt_M_local_0[10] = mac_fixpt_add_temp_96[14:1];
end
end
if (7'b0001100 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_167 = {1'b0, {mac_fixpt_M_local_0[11], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_59 = W[0];
end
else begin
mac_fixpt_t_59 = 14'b00000000000000;
end
mac_fixpt_add_cast_168 = {1'b0, mac_fixpt_t_59};
mac_fixpt_add_cast_169 = {1'b0, mac_fixpt_add_cast_168};
mac_fixpt_add_temp_55 = mac_fixpt_add_cast_167 + mac_fixpt_add_cast_169;
mac_fixpt_M_local_0[11] = mac_fixpt_add_temp_55[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_191 = {1'b0, {mac_fixpt_M_local_0[11], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_67 = W[1];
end
else begin
mac_fixpt_t_67 = 14'b00000000000000;
end
mac_fixpt_add_cast_192 = {1'b0, mac_fixpt_t_67};
mac_fixpt_add_cast_193 = {1'b0, mac_fixpt_add_cast_192};
mac_fixpt_add_temp_63 = mac_fixpt_add_cast_191 + mac_fixpt_add_cast_193;
mac_fixpt_M_local_0[11] = mac_fixpt_add_temp_63[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_215 = {1'b0, {mac_fixpt_M_local_0[11], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_75 = W[2];
end
else begin
mac_fixpt_t_75 = 14'b00000000000000;
end
mac_fixpt_add_cast_216 = {1'b0, mac_fixpt_t_75};
mac_fixpt_add_cast_217 = {1'b0, mac_fixpt_add_cast_216};
mac_fixpt_add_temp_71 = mac_fixpt_add_cast_215 + mac_fixpt_add_cast_217;
mac_fixpt_M_local_0[11] = mac_fixpt_add_temp_71[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_239 = {1'b0, {mac_fixpt_M_local_0[11], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_83 = W[3];
end
else begin
mac_fixpt_t_83 = 14'b00000000000000;
end
mac_fixpt_add_cast_240 = {1'b0, mac_fixpt_t_83};
mac_fixpt_add_cast_241 = {1'b0, mac_fixpt_add_cast_240};
mac_fixpt_add_temp_79 = mac_fixpt_add_cast_239 + mac_fixpt_add_cast_241;
mac_fixpt_M_local_0[11] = mac_fixpt_add_temp_79[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_263 = {1'b0, {mac_fixpt_M_local_0[11], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_91 = W[4];
end
else begin
mac_fixpt_t_91 = 14'b00000000000000;
end
mac_fixpt_add_cast_264 = {1'b0, mac_fixpt_t_91};
mac_fixpt_add_cast_265 = {1'b0, mac_fixpt_add_cast_264};
mac_fixpt_add_temp_87 = mac_fixpt_add_cast_263 + mac_fixpt_add_cast_265;
mac_fixpt_M_local_0[11] = mac_fixpt_add_temp_87[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_287 = {1'b0, {mac_fixpt_M_local_0[11], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_99 = W[5];
end
else begin
mac_fixpt_t_99 = 14'b00000000000000;
end
mac_fixpt_add_cast_288 = {1'b0, mac_fixpt_t_99};
mac_fixpt_add_cast_289 = {1'b0, mac_fixpt_add_cast_288};
mac_fixpt_add_temp_95 = mac_fixpt_add_cast_287 + mac_fixpt_add_cast_289;
mac_fixpt_M_local_0[11] = mac_fixpt_add_temp_95[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_311 = {1'b0, {mac_fixpt_M_local_0[11], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_107 = W[6];
end
else begin
mac_fixpt_t_107 = 14'b00000000000000;
end
mac_fixpt_add_cast_312 = {1'b0, mac_fixpt_t_107};
mac_fixpt_add_cast_313 = {1'b0, mac_fixpt_add_cast_312};
mac_fixpt_add_temp_103 = mac_fixpt_add_cast_311 + mac_fixpt_add_cast_313;
mac_fixpt_M_local_0[11] = mac_fixpt_add_temp_103[14:1];
end
end
if (7'b0001101 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_188 = {1'b0, {mac_fixpt_M_local_0[12], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_66 = W[0];
end
else begin
mac_fixpt_t_66 = 14'b00000000000000;
end
mac_fixpt_add_cast_189 = {1'b0, mac_fixpt_t_66};
mac_fixpt_add_cast_190 = {1'b0, mac_fixpt_add_cast_189};
mac_fixpt_add_temp_62 = mac_fixpt_add_cast_188 + mac_fixpt_add_cast_190;
mac_fixpt_M_local_0[12] = mac_fixpt_add_temp_62[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_212 = {1'b0, {mac_fixpt_M_local_0[12], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_74 = W[1];
end
else begin
mac_fixpt_t_74 = 14'b00000000000000;
end
mac_fixpt_add_cast_213 = {1'b0, mac_fixpt_t_74};
mac_fixpt_add_cast_214 = {1'b0, mac_fixpt_add_cast_213};
mac_fixpt_add_temp_70 = mac_fixpt_add_cast_212 + mac_fixpt_add_cast_214;
mac_fixpt_M_local_0[12] = mac_fixpt_add_temp_70[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_236 = {1'b0, {mac_fixpt_M_local_0[12], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_82 = W[2];
end
else begin
mac_fixpt_t_82 = 14'b00000000000000;
end
mac_fixpt_add_cast_237 = {1'b0, mac_fixpt_t_82};
mac_fixpt_add_cast_238 = {1'b0, mac_fixpt_add_cast_237};
mac_fixpt_add_temp_78 = mac_fixpt_add_cast_236 + mac_fixpt_add_cast_238;
mac_fixpt_M_local_0[12] = mac_fixpt_add_temp_78[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_260 = {1'b0, {mac_fixpt_M_local_0[12], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_90 = W[3];
end
else begin
mac_fixpt_t_90 = 14'b00000000000000;
end
mac_fixpt_add_cast_261 = {1'b0, mac_fixpt_t_90};
mac_fixpt_add_cast_262 = {1'b0, mac_fixpt_add_cast_261};
mac_fixpt_add_temp_86 = mac_fixpt_add_cast_260 + mac_fixpt_add_cast_262;
mac_fixpt_M_local_0[12] = mac_fixpt_add_temp_86[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_284 = {1'b0, {mac_fixpt_M_local_0[12], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_98 = W[4];
end
else begin
mac_fixpt_t_98 = 14'b00000000000000;
end
mac_fixpt_add_cast_285 = {1'b0, mac_fixpt_t_98};
mac_fixpt_add_cast_286 = {1'b0, mac_fixpt_add_cast_285};
mac_fixpt_add_temp_94 = mac_fixpt_add_cast_284 + mac_fixpt_add_cast_286;
mac_fixpt_M_local_0[12] = mac_fixpt_add_temp_94[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_308 = {1'b0, {mac_fixpt_M_local_0[12], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_106 = W[5];
end
else begin
mac_fixpt_t_106 = 14'b00000000000000;
end
mac_fixpt_add_cast_309 = {1'b0, mac_fixpt_t_106};
mac_fixpt_add_cast_310 = {1'b0, mac_fixpt_add_cast_309};
mac_fixpt_add_temp_102 = mac_fixpt_add_cast_308 + mac_fixpt_add_cast_310;
mac_fixpt_M_local_0[12] = mac_fixpt_add_temp_102[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_332 = {1'b0, {mac_fixpt_M_local_0[12], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_114 = W[6];
end
else begin
mac_fixpt_t_114 = 14'b00000000000000;
end
mac_fixpt_add_cast_333 = {1'b0, mac_fixpt_t_114};
mac_fixpt_add_cast_334 = {1'b0, mac_fixpt_add_cast_333};
mac_fixpt_add_temp_110 = mac_fixpt_add_cast_332 + mac_fixpt_add_cast_334;
mac_fixpt_M_local_0[12] = mac_fixpt_add_temp_110[14:1];
end
end
if (7'b0001110 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_209 = {1'b0, {mac_fixpt_M_local_0[13], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_73 = W[0];
end
else begin
mac_fixpt_t_73 = 14'b00000000000000;
end
mac_fixpt_add_cast_210 = {1'b0, mac_fixpt_t_73};
mac_fixpt_add_cast_211 = {1'b0, mac_fixpt_add_cast_210};
mac_fixpt_add_temp_69 = mac_fixpt_add_cast_209 + mac_fixpt_add_cast_211;
mac_fixpt_M_local_0[13] = mac_fixpt_add_temp_69[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_233 = {1'b0, {mac_fixpt_M_local_0[13], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_81 = W[1];
end
else begin
mac_fixpt_t_81 = 14'b00000000000000;
end
mac_fixpt_add_cast_234 = {1'b0, mac_fixpt_t_81};
mac_fixpt_add_cast_235 = {1'b0, mac_fixpt_add_cast_234};
mac_fixpt_add_temp_77 = mac_fixpt_add_cast_233 + mac_fixpt_add_cast_235;
mac_fixpt_M_local_0[13] = mac_fixpt_add_temp_77[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_257 = {1'b0, {mac_fixpt_M_local_0[13], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_89 = W[2];
end
else begin
mac_fixpt_t_89 = 14'b00000000000000;
end
mac_fixpt_add_cast_258 = {1'b0, mac_fixpt_t_89};
mac_fixpt_add_cast_259 = {1'b0, mac_fixpt_add_cast_258};
mac_fixpt_add_temp_85 = mac_fixpt_add_cast_257 + mac_fixpt_add_cast_259;
mac_fixpt_M_local_0[13] = mac_fixpt_add_temp_85[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_281 = {1'b0, {mac_fixpt_M_local_0[13], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_97 = W[3];
end
else begin
mac_fixpt_t_97 = 14'b00000000000000;
end
mac_fixpt_add_cast_282 = {1'b0, mac_fixpt_t_97};
mac_fixpt_add_cast_283 = {1'b0, mac_fixpt_add_cast_282};
mac_fixpt_add_temp_93 = mac_fixpt_add_cast_281 + mac_fixpt_add_cast_283;
mac_fixpt_M_local_0[13] = mac_fixpt_add_temp_93[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_305 = {1'b0, {mac_fixpt_M_local_0[13], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_105 = W[4];
end
else begin
mac_fixpt_t_105 = 14'b00000000000000;
end
mac_fixpt_add_cast_306 = {1'b0, mac_fixpt_t_105};
mac_fixpt_add_cast_307 = {1'b0, mac_fixpt_add_cast_306};
mac_fixpt_add_temp_101 = mac_fixpt_add_cast_305 + mac_fixpt_add_cast_307;
mac_fixpt_M_local_0[13] = mac_fixpt_add_temp_101[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_329 = {1'b0, {mac_fixpt_M_local_0[13], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_113 = W[5];
end
else begin
mac_fixpt_t_113 = 14'b00000000000000;
end
mac_fixpt_add_cast_330 = {1'b0, mac_fixpt_t_113};
mac_fixpt_add_cast_331 = {1'b0, mac_fixpt_add_cast_330};
mac_fixpt_add_temp_109 = mac_fixpt_add_cast_329 + mac_fixpt_add_cast_331;
mac_fixpt_M_local_0[13] = mac_fixpt_add_temp_109[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_353 = {1'b0, {mac_fixpt_M_local_0[13], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_121 = W[6];
end
else begin
mac_fixpt_t_121 = 14'b00000000000000;
end
mac_fixpt_add_cast_354 = {1'b0, mac_fixpt_t_121};
mac_fixpt_add_cast_355 = {1'b0, mac_fixpt_add_cast_354};
mac_fixpt_add_temp_117 = mac_fixpt_add_cast_353 + mac_fixpt_add_cast_355;
mac_fixpt_M_local_0[13] = mac_fixpt_add_temp_117[14:1];
end
end
if (7'b0001111 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_230 = {1'b0, {mac_fixpt_M_local_0[14], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_80 = W[0];
end
else begin
mac_fixpt_t_80 = 14'b00000000000000;
end
mac_fixpt_add_cast_231 = {1'b0, mac_fixpt_t_80};
mac_fixpt_add_cast_232 = {1'b0, mac_fixpt_add_cast_231};
mac_fixpt_add_temp_76 = mac_fixpt_add_cast_230 + mac_fixpt_add_cast_232;
mac_fixpt_M_local_0[14] = mac_fixpt_add_temp_76[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_254 = {1'b0, {mac_fixpt_M_local_0[14], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_88 = W[1];
end
else begin
mac_fixpt_t_88 = 14'b00000000000000;
end
mac_fixpt_add_cast_255 = {1'b0, mac_fixpt_t_88};
mac_fixpt_add_cast_256 = {1'b0, mac_fixpt_add_cast_255};
mac_fixpt_add_temp_84 = mac_fixpt_add_cast_254 + mac_fixpt_add_cast_256;
mac_fixpt_M_local_0[14] = mac_fixpt_add_temp_84[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_278 = {1'b0, {mac_fixpt_M_local_0[14], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_96 = W[2];
end
else begin
mac_fixpt_t_96 = 14'b00000000000000;
end
mac_fixpt_add_cast_279 = {1'b0, mac_fixpt_t_96};
mac_fixpt_add_cast_280 = {1'b0, mac_fixpt_add_cast_279};
mac_fixpt_add_temp_92 = mac_fixpt_add_cast_278 + mac_fixpt_add_cast_280;
mac_fixpt_M_local_0[14] = mac_fixpt_add_temp_92[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_302 = {1'b0, {mac_fixpt_M_local_0[14], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_104 = W[3];
end
else begin
mac_fixpt_t_104 = 14'b00000000000000;
end
mac_fixpt_add_cast_303 = {1'b0, mac_fixpt_t_104};
mac_fixpt_add_cast_304 = {1'b0, mac_fixpt_add_cast_303};
mac_fixpt_add_temp_100 = mac_fixpt_add_cast_302 + mac_fixpt_add_cast_304;
mac_fixpt_M_local_0[14] = mac_fixpt_add_temp_100[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_326 = {1'b0, {mac_fixpt_M_local_0[14], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_112 = W[4];
end
else begin
mac_fixpt_t_112 = 14'b00000000000000;
end
mac_fixpt_add_cast_327 = {1'b0, mac_fixpt_t_112};
mac_fixpt_add_cast_328 = {1'b0, mac_fixpt_add_cast_327};
mac_fixpt_add_temp_108 = mac_fixpt_add_cast_326 + mac_fixpt_add_cast_328;
mac_fixpt_M_local_0[14] = mac_fixpt_add_temp_108[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_350 = {1'b0, {mac_fixpt_M_local_0[14], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_120 = W[5];
end
else begin
mac_fixpt_t_120 = 14'b00000000000000;
end
mac_fixpt_add_cast_351 = {1'b0, mac_fixpt_t_120};
mac_fixpt_add_cast_352 = {1'b0, mac_fixpt_add_cast_351};
mac_fixpt_add_temp_116 = mac_fixpt_add_cast_350 + mac_fixpt_add_cast_352;
mac_fixpt_M_local_0[14] = mac_fixpt_add_temp_116[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_374 = {1'b0, {mac_fixpt_M_local_0[14], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_128 = W[6];
end
else begin
mac_fixpt_t_128 = 14'b00000000000000;
end
mac_fixpt_add_cast_375 = {1'b0, mac_fixpt_t_128};
mac_fixpt_add_cast_376 = {1'b0, mac_fixpt_add_cast_375};
mac_fixpt_add_temp_124 = mac_fixpt_add_cast_374 + mac_fixpt_add_cast_376;
mac_fixpt_M_local_0[14] = mac_fixpt_add_temp_124[14:1];
end
end
if (7'b0010000 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_251 = {1'b0, {mac_fixpt_M_local_0[15], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_87 = W[0];
end
else begin
mac_fixpt_t_87 = 14'b00000000000000;
end
mac_fixpt_add_cast_252 = {1'b0, mac_fixpt_t_87};
mac_fixpt_add_cast_253 = {1'b0, mac_fixpt_add_cast_252};
mac_fixpt_add_temp_83 = mac_fixpt_add_cast_251 + mac_fixpt_add_cast_253;
mac_fixpt_M_local_0[15] = mac_fixpt_add_temp_83[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_275 = {1'b0, {mac_fixpt_M_local_0[15], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_95 = W[1];
end
else begin
mac_fixpt_t_95 = 14'b00000000000000;
end
mac_fixpt_add_cast_276 = {1'b0, mac_fixpt_t_95};
mac_fixpt_add_cast_277 = {1'b0, mac_fixpt_add_cast_276};
mac_fixpt_add_temp_91 = mac_fixpt_add_cast_275 + mac_fixpt_add_cast_277;
mac_fixpt_M_local_0[15] = mac_fixpt_add_temp_91[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_299 = {1'b0, {mac_fixpt_M_local_0[15], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_103 = W[2];
end
else begin
mac_fixpt_t_103 = 14'b00000000000000;
end
mac_fixpt_add_cast_300 = {1'b0, mac_fixpt_t_103};
mac_fixpt_add_cast_301 = {1'b0, mac_fixpt_add_cast_300};
mac_fixpt_add_temp_99 = mac_fixpt_add_cast_299 + mac_fixpt_add_cast_301;
mac_fixpt_M_local_0[15] = mac_fixpt_add_temp_99[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_323 = {1'b0, {mac_fixpt_M_local_0[15], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_111 = W[3];
end
else begin
mac_fixpt_t_111 = 14'b00000000000000;
end
mac_fixpt_add_cast_324 = {1'b0, mac_fixpt_t_111};
mac_fixpt_add_cast_325 = {1'b0, mac_fixpt_add_cast_324};
mac_fixpt_add_temp_107 = mac_fixpt_add_cast_323 + mac_fixpt_add_cast_325;
mac_fixpt_M_local_0[15] = mac_fixpt_add_temp_107[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_347 = {1'b0, {mac_fixpt_M_local_0[15], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_119 = W[4];
end
else begin
mac_fixpt_t_119 = 14'b00000000000000;
end
mac_fixpt_add_cast_348 = {1'b0, mac_fixpt_t_119};
mac_fixpt_add_cast_349 = {1'b0, mac_fixpt_add_cast_348};
mac_fixpt_add_temp_115 = mac_fixpt_add_cast_347 + mac_fixpt_add_cast_349;
mac_fixpt_M_local_0[15] = mac_fixpt_add_temp_115[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_371 = {1'b0, {mac_fixpt_M_local_0[15], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_127 = W[5];
end
else begin
mac_fixpt_t_127 = 14'b00000000000000;
end
mac_fixpt_add_cast_372 = {1'b0, mac_fixpt_t_127};
mac_fixpt_add_cast_373 = {1'b0, mac_fixpt_add_cast_372};
mac_fixpt_add_temp_123 = mac_fixpt_add_cast_371 + mac_fixpt_add_cast_373;
mac_fixpt_M_local_0[15] = mac_fixpt_add_temp_123[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_395 = {1'b0, {mac_fixpt_M_local_0[15], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_135 = W[6];
end
else begin
mac_fixpt_t_135 = 14'b00000000000000;
end
mac_fixpt_add_cast_396 = {1'b0, mac_fixpt_t_135};
mac_fixpt_add_cast_397 = {1'b0, mac_fixpt_add_cast_396};
mac_fixpt_add_temp_131 = mac_fixpt_add_cast_395 + mac_fixpt_add_cast_397;
mac_fixpt_M_local_0[15] = mac_fixpt_add_temp_131[14:1];
end
end
if (7'b0010001 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_272 = {1'b0, {mac_fixpt_M_local_0[16], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_94 = W[0];
end
else begin
mac_fixpt_t_94 = 14'b00000000000000;
end
mac_fixpt_add_cast_273 = {1'b0, mac_fixpt_t_94};
mac_fixpt_add_cast_274 = {1'b0, mac_fixpt_add_cast_273};
mac_fixpt_add_temp_90 = mac_fixpt_add_cast_272 + mac_fixpt_add_cast_274;
mac_fixpt_M_local_0[16] = mac_fixpt_add_temp_90[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_296 = {1'b0, {mac_fixpt_M_local_0[16], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_102 = W[1];
end
else begin
mac_fixpt_t_102 = 14'b00000000000000;
end
mac_fixpt_add_cast_297 = {1'b0, mac_fixpt_t_102};
mac_fixpt_add_cast_298 = {1'b0, mac_fixpt_add_cast_297};
mac_fixpt_add_temp_98 = mac_fixpt_add_cast_296 + mac_fixpt_add_cast_298;
mac_fixpt_M_local_0[16] = mac_fixpt_add_temp_98[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_320 = {1'b0, {mac_fixpt_M_local_0[16], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_110 = W[2];
end
else begin
mac_fixpt_t_110 = 14'b00000000000000;
end
mac_fixpt_add_cast_321 = {1'b0, mac_fixpt_t_110};
mac_fixpt_add_cast_322 = {1'b0, mac_fixpt_add_cast_321};
mac_fixpt_add_temp_106 = mac_fixpt_add_cast_320 + mac_fixpt_add_cast_322;
mac_fixpt_M_local_0[16] = mac_fixpt_add_temp_106[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_344 = {1'b0, {mac_fixpt_M_local_0[16], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_118 = W[3];
end
else begin
mac_fixpt_t_118 = 14'b00000000000000;
end
mac_fixpt_add_cast_345 = {1'b0, mac_fixpt_t_118};
mac_fixpt_add_cast_346 = {1'b0, mac_fixpt_add_cast_345};
mac_fixpt_add_temp_114 = mac_fixpt_add_cast_344 + mac_fixpt_add_cast_346;
mac_fixpt_M_local_0[16] = mac_fixpt_add_temp_114[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_368 = {1'b0, {mac_fixpt_M_local_0[16], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_126 = W[4];
end
else begin
mac_fixpt_t_126 = 14'b00000000000000;
end
mac_fixpt_add_cast_369 = {1'b0, mac_fixpt_t_126};
mac_fixpt_add_cast_370 = {1'b0, mac_fixpt_add_cast_369};
mac_fixpt_add_temp_122 = mac_fixpt_add_cast_368 + mac_fixpt_add_cast_370;
mac_fixpt_M_local_0[16] = mac_fixpt_add_temp_122[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_392 = {1'b0, {mac_fixpt_M_local_0[16], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_134 = W[5];
end
else begin
mac_fixpt_t_134 = 14'b00000000000000;
end
mac_fixpt_add_cast_393 = {1'b0, mac_fixpt_t_134};
mac_fixpt_add_cast_394 = {1'b0, mac_fixpt_add_cast_393};
mac_fixpt_add_temp_130 = mac_fixpt_add_cast_392 + mac_fixpt_add_cast_394;
mac_fixpt_M_local_0[16] = mac_fixpt_add_temp_130[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_416 = {1'b0, {mac_fixpt_M_local_0[16], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_142 = W[6];
end
else begin
mac_fixpt_t_142 = 14'b00000000000000;
end
mac_fixpt_add_cast_417 = {1'b0, mac_fixpt_t_142};
mac_fixpt_add_cast_418 = {1'b0, mac_fixpt_add_cast_417};
mac_fixpt_add_temp_138 = mac_fixpt_add_cast_416 + mac_fixpt_add_cast_418;
mac_fixpt_M_local_0[16] = mac_fixpt_add_temp_138[14:1];
end
end
if (7'b0010010 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_293 = {1'b0, {mac_fixpt_M_local_0[17], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_101 = W[0];
end
else begin
mac_fixpt_t_101 = 14'b00000000000000;
end
mac_fixpt_add_cast_294 = {1'b0, mac_fixpt_t_101};
mac_fixpt_add_cast_295 = {1'b0, mac_fixpt_add_cast_294};
mac_fixpt_add_temp_97 = mac_fixpt_add_cast_293 + mac_fixpt_add_cast_295;
mac_fixpt_M_local_0[17] = mac_fixpt_add_temp_97[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_317 = {1'b0, {mac_fixpt_M_local_0[17], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_109 = W[1];
end
else begin
mac_fixpt_t_109 = 14'b00000000000000;
end
mac_fixpt_add_cast_318 = {1'b0, mac_fixpt_t_109};
mac_fixpt_add_cast_319 = {1'b0, mac_fixpt_add_cast_318};
mac_fixpt_add_temp_105 = mac_fixpt_add_cast_317 + mac_fixpt_add_cast_319;
mac_fixpt_M_local_0[17] = mac_fixpt_add_temp_105[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_341 = {1'b0, {mac_fixpt_M_local_0[17], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_117 = W[2];
end
else begin
mac_fixpt_t_117 = 14'b00000000000000;
end
mac_fixpt_add_cast_342 = {1'b0, mac_fixpt_t_117};
mac_fixpt_add_cast_343 = {1'b0, mac_fixpt_add_cast_342};
mac_fixpt_add_temp_113 = mac_fixpt_add_cast_341 + mac_fixpt_add_cast_343;
mac_fixpt_M_local_0[17] = mac_fixpt_add_temp_113[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_365 = {1'b0, {mac_fixpt_M_local_0[17], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_125 = W[3];
end
else begin
mac_fixpt_t_125 = 14'b00000000000000;
end
mac_fixpt_add_cast_366 = {1'b0, mac_fixpt_t_125};
mac_fixpt_add_cast_367 = {1'b0, mac_fixpt_add_cast_366};
mac_fixpt_add_temp_121 = mac_fixpt_add_cast_365 + mac_fixpt_add_cast_367;
mac_fixpt_M_local_0[17] = mac_fixpt_add_temp_121[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_389 = {1'b0, {mac_fixpt_M_local_0[17], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_133 = W[4];
end
else begin
mac_fixpt_t_133 = 14'b00000000000000;
end
mac_fixpt_add_cast_390 = {1'b0, mac_fixpt_t_133};
mac_fixpt_add_cast_391 = {1'b0, mac_fixpt_add_cast_390};
mac_fixpt_add_temp_129 = mac_fixpt_add_cast_389 + mac_fixpt_add_cast_391;
mac_fixpt_M_local_0[17] = mac_fixpt_add_temp_129[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_413 = {1'b0, {mac_fixpt_M_local_0[17], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_141 = W[5];
end
else begin
mac_fixpt_t_141 = 14'b00000000000000;
end
mac_fixpt_add_cast_414 = {1'b0, mac_fixpt_t_141};
mac_fixpt_add_cast_415 = {1'b0, mac_fixpt_add_cast_414};
mac_fixpt_add_temp_137 = mac_fixpt_add_cast_413 + mac_fixpt_add_cast_415;
mac_fixpt_M_local_0[17] = mac_fixpt_add_temp_137[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_437 = {1'b0, {mac_fixpt_M_local_0[17], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_149 = W[6];
end
else begin
mac_fixpt_t_149 = 14'b00000000000000;
end
mac_fixpt_add_cast_438 = {1'b0, mac_fixpt_t_149};
mac_fixpt_add_cast_439 = {1'b0, mac_fixpt_add_cast_438};
mac_fixpt_add_temp_145 = mac_fixpt_add_cast_437 + mac_fixpt_add_cast_439;
mac_fixpt_M_local_0[17] = mac_fixpt_add_temp_145[14:1];
end
end
if (7'b0010011 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_314 = {1'b0, {mac_fixpt_M_local_0[18], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_108 = W[0];
end
else begin
mac_fixpt_t_108 = 14'b00000000000000;
end
mac_fixpt_add_cast_315 = {1'b0, mac_fixpt_t_108};
mac_fixpt_add_cast_316 = {1'b0, mac_fixpt_add_cast_315};
mac_fixpt_add_temp_104 = mac_fixpt_add_cast_314 + mac_fixpt_add_cast_316;
mac_fixpt_M_local_0[18] = mac_fixpt_add_temp_104[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_338 = {1'b0, {mac_fixpt_M_local_0[18], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_116 = W[1];
end
else begin
mac_fixpt_t_116 = 14'b00000000000000;
end
mac_fixpt_add_cast_339 = {1'b0, mac_fixpt_t_116};
mac_fixpt_add_cast_340 = {1'b0, mac_fixpt_add_cast_339};
mac_fixpt_add_temp_112 = mac_fixpt_add_cast_338 + mac_fixpt_add_cast_340;
mac_fixpt_M_local_0[18] = mac_fixpt_add_temp_112[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_362 = {1'b0, {mac_fixpt_M_local_0[18], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_124 = W[2];
end
else begin
mac_fixpt_t_124 = 14'b00000000000000;
end
mac_fixpt_add_cast_363 = {1'b0, mac_fixpt_t_124};
mac_fixpt_add_cast_364 = {1'b0, mac_fixpt_add_cast_363};
mac_fixpt_add_temp_120 = mac_fixpt_add_cast_362 + mac_fixpt_add_cast_364;
mac_fixpt_M_local_0[18] = mac_fixpt_add_temp_120[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_386 = {1'b0, {mac_fixpt_M_local_0[18], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_132 = W[3];
end
else begin
mac_fixpt_t_132 = 14'b00000000000000;
end
mac_fixpt_add_cast_387 = {1'b0, mac_fixpt_t_132};
mac_fixpt_add_cast_388 = {1'b0, mac_fixpt_add_cast_387};
mac_fixpt_add_temp_128 = mac_fixpt_add_cast_386 + mac_fixpt_add_cast_388;
mac_fixpt_M_local_0[18] = mac_fixpt_add_temp_128[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_410 = {1'b0, {mac_fixpt_M_local_0[18], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_140 = W[4];
end
else begin
mac_fixpt_t_140 = 14'b00000000000000;
end
mac_fixpt_add_cast_411 = {1'b0, mac_fixpt_t_140};
mac_fixpt_add_cast_412 = {1'b0, mac_fixpt_add_cast_411};
mac_fixpt_add_temp_136 = mac_fixpt_add_cast_410 + mac_fixpt_add_cast_412;
mac_fixpt_M_local_0[18] = mac_fixpt_add_temp_136[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_434 = {1'b0, {mac_fixpt_M_local_0[18], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_148 = W[5];
end
else begin
mac_fixpt_t_148 = 14'b00000000000000;
end
mac_fixpt_add_cast_435 = {1'b0, mac_fixpt_t_148};
mac_fixpt_add_cast_436 = {1'b0, mac_fixpt_add_cast_435};
mac_fixpt_add_temp_144 = mac_fixpt_add_cast_434 + mac_fixpt_add_cast_436;
mac_fixpt_M_local_0[18] = mac_fixpt_add_temp_144[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_458 = {1'b0, {mac_fixpt_M_local_0[18], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_156 = W[6];
end
else begin
mac_fixpt_t_156 = 14'b00000000000000;
end
mac_fixpt_add_cast_459 = {1'b0, mac_fixpt_t_156};
mac_fixpt_add_cast_460 = {1'b0, mac_fixpt_add_cast_459};
mac_fixpt_add_temp_152 = mac_fixpt_add_cast_458 + mac_fixpt_add_cast_460;
mac_fixpt_M_local_0[18] = mac_fixpt_add_temp_152[14:1];
end
end
if (7'b0010100 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_335 = {1'b0, {mac_fixpt_M_local_0[19], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_115 = W[0];
end
else begin
mac_fixpt_t_115 = 14'b00000000000000;
end
mac_fixpt_add_cast_336 = {1'b0, mac_fixpt_t_115};
mac_fixpt_add_cast_337 = {1'b0, mac_fixpt_add_cast_336};
mac_fixpt_add_temp_111 = mac_fixpt_add_cast_335 + mac_fixpt_add_cast_337;
mac_fixpt_M_local_0[19] = mac_fixpt_add_temp_111[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_359 = {1'b0, {mac_fixpt_M_local_0[19], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_123 = W[1];
end
else begin
mac_fixpt_t_123 = 14'b00000000000000;
end
mac_fixpt_add_cast_360 = {1'b0, mac_fixpt_t_123};
mac_fixpt_add_cast_361 = {1'b0, mac_fixpt_add_cast_360};
mac_fixpt_add_temp_119 = mac_fixpt_add_cast_359 + mac_fixpt_add_cast_361;
mac_fixpt_M_local_0[19] = mac_fixpt_add_temp_119[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_383 = {1'b0, {mac_fixpt_M_local_0[19], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_131 = W[2];
end
else begin
mac_fixpt_t_131 = 14'b00000000000000;
end
mac_fixpt_add_cast_384 = {1'b0, mac_fixpt_t_131};
mac_fixpt_add_cast_385 = {1'b0, mac_fixpt_add_cast_384};
mac_fixpt_add_temp_127 = mac_fixpt_add_cast_383 + mac_fixpt_add_cast_385;
mac_fixpt_M_local_0[19] = mac_fixpt_add_temp_127[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_407 = {1'b0, {mac_fixpt_M_local_0[19], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_139 = W[3];
end
else begin
mac_fixpt_t_139 = 14'b00000000000000;
end
mac_fixpt_add_cast_408 = {1'b0, mac_fixpt_t_139};
mac_fixpt_add_cast_409 = {1'b0, mac_fixpt_add_cast_408};
mac_fixpt_add_temp_135 = mac_fixpt_add_cast_407 + mac_fixpt_add_cast_409;
mac_fixpt_M_local_0[19] = mac_fixpt_add_temp_135[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_431 = {1'b0, {mac_fixpt_M_local_0[19], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_147 = W[4];
end
else begin
mac_fixpt_t_147 = 14'b00000000000000;
end
mac_fixpt_add_cast_432 = {1'b0, mac_fixpt_t_147};
mac_fixpt_add_cast_433 = {1'b0, mac_fixpt_add_cast_432};
mac_fixpt_add_temp_143 = mac_fixpt_add_cast_431 + mac_fixpt_add_cast_433;
mac_fixpt_M_local_0[19] = mac_fixpt_add_temp_143[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_455 = {1'b0, {mac_fixpt_M_local_0[19], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_155 = W[5];
end
else begin
mac_fixpt_t_155 = 14'b00000000000000;
end
mac_fixpt_add_cast_456 = {1'b0, mac_fixpt_t_155};
mac_fixpt_add_cast_457 = {1'b0, mac_fixpt_add_cast_456};
mac_fixpt_add_temp_151 = mac_fixpt_add_cast_455 + mac_fixpt_add_cast_457;
mac_fixpt_M_local_0[19] = mac_fixpt_add_temp_151[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_479 = {1'b0, {mac_fixpt_M_local_0[19], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_163 = W[6];
end
else begin
mac_fixpt_t_163 = 14'b00000000000000;
end
mac_fixpt_add_cast_480 = {1'b0, mac_fixpt_t_163};
mac_fixpt_add_cast_481 = {1'b0, mac_fixpt_add_cast_480};
mac_fixpt_add_temp_159 = mac_fixpt_add_cast_479 + mac_fixpt_add_cast_481;
mac_fixpt_M_local_0[19] = mac_fixpt_add_temp_159[14:1];
end
end
if (7'b0010101 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_356 = {1'b0, {mac_fixpt_M_local_0[20], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_122 = W[0];
end
else begin
mac_fixpt_t_122 = 14'b00000000000000;
end
mac_fixpt_add_cast_357 = {1'b0, mac_fixpt_t_122};
mac_fixpt_add_cast_358 = {1'b0, mac_fixpt_add_cast_357};
mac_fixpt_add_temp_118 = mac_fixpt_add_cast_356 + mac_fixpt_add_cast_358;
mac_fixpt_M_local_0[20] = mac_fixpt_add_temp_118[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_380 = {1'b0, {mac_fixpt_M_local_0[20], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_130 = W[1];
end
else begin
mac_fixpt_t_130 = 14'b00000000000000;
end
mac_fixpt_add_cast_381 = {1'b0, mac_fixpt_t_130};
mac_fixpt_add_cast_382 = {1'b0, mac_fixpt_add_cast_381};
mac_fixpt_add_temp_126 = mac_fixpt_add_cast_380 + mac_fixpt_add_cast_382;
mac_fixpt_M_local_0[20] = mac_fixpt_add_temp_126[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_404 = {1'b0, {mac_fixpt_M_local_0[20], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_138 = W[2];
end
else begin
mac_fixpt_t_138 = 14'b00000000000000;
end
mac_fixpt_add_cast_405 = {1'b0, mac_fixpt_t_138};
mac_fixpt_add_cast_406 = {1'b0, mac_fixpt_add_cast_405};
mac_fixpt_add_temp_134 = mac_fixpt_add_cast_404 + mac_fixpt_add_cast_406;
mac_fixpt_M_local_0[20] = mac_fixpt_add_temp_134[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_428 = {1'b0, {mac_fixpt_M_local_0[20], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_146 = W[3];
end
else begin
mac_fixpt_t_146 = 14'b00000000000000;
end
mac_fixpt_add_cast_429 = {1'b0, mac_fixpt_t_146};
mac_fixpt_add_cast_430 = {1'b0, mac_fixpt_add_cast_429};
mac_fixpt_add_temp_142 = mac_fixpt_add_cast_428 + mac_fixpt_add_cast_430;
mac_fixpt_M_local_0[20] = mac_fixpt_add_temp_142[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_452 = {1'b0, {mac_fixpt_M_local_0[20], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_154 = W[4];
end
else begin
mac_fixpt_t_154 = 14'b00000000000000;
end
mac_fixpt_add_cast_453 = {1'b0, mac_fixpt_t_154};
mac_fixpt_add_cast_454 = {1'b0, mac_fixpt_add_cast_453};
mac_fixpt_add_temp_150 = mac_fixpt_add_cast_452 + mac_fixpt_add_cast_454;
mac_fixpt_M_local_0[20] = mac_fixpt_add_temp_150[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_476 = {1'b0, {mac_fixpt_M_local_0[20], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_162 = W[5];
end
else begin
mac_fixpt_t_162 = 14'b00000000000000;
end
mac_fixpt_add_cast_477 = {1'b0, mac_fixpt_t_162};
mac_fixpt_add_cast_478 = {1'b0, mac_fixpt_add_cast_477};
mac_fixpt_add_temp_158 = mac_fixpt_add_cast_476 + mac_fixpt_add_cast_478;
mac_fixpt_M_local_0[20] = mac_fixpt_add_temp_158[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_500 = {1'b0, {mac_fixpt_M_local_0[20], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_170 = W[6];
end
else begin
mac_fixpt_t_170 = 14'b00000000000000;
end
mac_fixpt_add_cast_501 = {1'b0, mac_fixpt_t_170};
mac_fixpt_add_cast_502 = {1'b0, mac_fixpt_add_cast_501};
mac_fixpt_add_temp_166 = mac_fixpt_add_cast_500 + mac_fixpt_add_cast_502;
mac_fixpt_M_local_0[20] = mac_fixpt_add_temp_166[14:1];
end
end
if (7'b0010110 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_377 = {1'b0, {mac_fixpt_M_local_0[21], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_129 = W[0];
end
else begin
mac_fixpt_t_129 = 14'b00000000000000;
end
mac_fixpt_add_cast_378 = {1'b0, mac_fixpt_t_129};
mac_fixpt_add_cast_379 = {1'b0, mac_fixpt_add_cast_378};
mac_fixpt_add_temp_125 = mac_fixpt_add_cast_377 + mac_fixpt_add_cast_379;
mac_fixpt_M_local_0[21] = mac_fixpt_add_temp_125[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_401 = {1'b0, {mac_fixpt_M_local_0[21], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_137 = W[1];
end
else begin
mac_fixpt_t_137 = 14'b00000000000000;
end
mac_fixpt_add_cast_402 = {1'b0, mac_fixpt_t_137};
mac_fixpt_add_cast_403 = {1'b0, mac_fixpt_add_cast_402};
mac_fixpt_add_temp_133 = mac_fixpt_add_cast_401 + mac_fixpt_add_cast_403;
mac_fixpt_M_local_0[21] = mac_fixpt_add_temp_133[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_425 = {1'b0, {mac_fixpt_M_local_0[21], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_145 = W[2];
end
else begin
mac_fixpt_t_145 = 14'b00000000000000;
end
mac_fixpt_add_cast_426 = {1'b0, mac_fixpt_t_145};
mac_fixpt_add_cast_427 = {1'b0, mac_fixpt_add_cast_426};
mac_fixpt_add_temp_141 = mac_fixpt_add_cast_425 + mac_fixpt_add_cast_427;
mac_fixpt_M_local_0[21] = mac_fixpt_add_temp_141[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_449 = {1'b0, {mac_fixpt_M_local_0[21], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_153 = W[3];
end
else begin
mac_fixpt_t_153 = 14'b00000000000000;
end
mac_fixpt_add_cast_450 = {1'b0, mac_fixpt_t_153};
mac_fixpt_add_cast_451 = {1'b0, mac_fixpt_add_cast_450};
mac_fixpt_add_temp_149 = mac_fixpt_add_cast_449 + mac_fixpt_add_cast_451;
mac_fixpt_M_local_0[21] = mac_fixpt_add_temp_149[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_473 = {1'b0, {mac_fixpt_M_local_0[21], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_161 = W[4];
end
else begin
mac_fixpt_t_161 = 14'b00000000000000;
end
mac_fixpt_add_cast_474 = {1'b0, mac_fixpt_t_161};
mac_fixpt_add_cast_475 = {1'b0, mac_fixpt_add_cast_474};
mac_fixpt_add_temp_157 = mac_fixpt_add_cast_473 + mac_fixpt_add_cast_475;
mac_fixpt_M_local_0[21] = mac_fixpt_add_temp_157[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_497 = {1'b0, {mac_fixpt_M_local_0[21], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_169 = W[5];
end
else begin
mac_fixpt_t_169 = 14'b00000000000000;
end
mac_fixpt_add_cast_498 = {1'b0, mac_fixpt_t_169};
mac_fixpt_add_cast_499 = {1'b0, mac_fixpt_add_cast_498};
mac_fixpt_add_temp_165 = mac_fixpt_add_cast_497 + mac_fixpt_add_cast_499;
mac_fixpt_M_local_0[21] = mac_fixpt_add_temp_165[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_521 = {1'b0, {mac_fixpt_M_local_0[21], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_177 = W[6];
end
else begin
mac_fixpt_t_177 = 14'b00000000000000;
end
mac_fixpt_add_cast_522 = {1'b0, mac_fixpt_t_177};
mac_fixpt_add_cast_523 = {1'b0, mac_fixpt_add_cast_522};
mac_fixpt_add_temp_173 = mac_fixpt_add_cast_521 + mac_fixpt_add_cast_523;
mac_fixpt_M_local_0[21] = mac_fixpt_add_temp_173[14:1];
end
end
if (7'b0010111 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_398 = {1'b0, {mac_fixpt_M_local_0[22], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_136 = W[0];
end
else begin
mac_fixpt_t_136 = 14'b00000000000000;
end
mac_fixpt_add_cast_399 = {1'b0, mac_fixpt_t_136};
mac_fixpt_add_cast_400 = {1'b0, mac_fixpt_add_cast_399};
mac_fixpt_add_temp_132 = mac_fixpt_add_cast_398 + mac_fixpt_add_cast_400;
mac_fixpt_M_local_0[22] = mac_fixpt_add_temp_132[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_422 = {1'b0, {mac_fixpt_M_local_0[22], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_144 = W[1];
end
else begin
mac_fixpt_t_144 = 14'b00000000000000;
end
mac_fixpt_add_cast_423 = {1'b0, mac_fixpt_t_144};
mac_fixpt_add_cast_424 = {1'b0, mac_fixpt_add_cast_423};
mac_fixpt_add_temp_140 = mac_fixpt_add_cast_422 + mac_fixpt_add_cast_424;
mac_fixpt_M_local_0[22] = mac_fixpt_add_temp_140[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_446 = {1'b0, {mac_fixpt_M_local_0[22], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_152 = W[2];
end
else begin
mac_fixpt_t_152 = 14'b00000000000000;
end
mac_fixpt_add_cast_447 = {1'b0, mac_fixpt_t_152};
mac_fixpt_add_cast_448 = {1'b0, mac_fixpt_add_cast_447};
mac_fixpt_add_temp_148 = mac_fixpt_add_cast_446 + mac_fixpt_add_cast_448;
mac_fixpt_M_local_0[22] = mac_fixpt_add_temp_148[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_470 = {1'b0, {mac_fixpt_M_local_0[22], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_160 = W[3];
end
else begin
mac_fixpt_t_160 = 14'b00000000000000;
end
mac_fixpt_add_cast_471 = {1'b0, mac_fixpt_t_160};
mac_fixpt_add_cast_472 = {1'b0, mac_fixpt_add_cast_471};
mac_fixpt_add_temp_156 = mac_fixpt_add_cast_470 + mac_fixpt_add_cast_472;
mac_fixpt_M_local_0[22] = mac_fixpt_add_temp_156[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_494 = {1'b0, {mac_fixpt_M_local_0[22], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_168 = W[4];
end
else begin
mac_fixpt_t_168 = 14'b00000000000000;
end
mac_fixpt_add_cast_495 = {1'b0, mac_fixpt_t_168};
mac_fixpt_add_cast_496 = {1'b0, mac_fixpt_add_cast_495};
mac_fixpt_add_temp_164 = mac_fixpt_add_cast_494 + mac_fixpt_add_cast_496;
mac_fixpt_M_local_0[22] = mac_fixpt_add_temp_164[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_518 = {1'b0, {mac_fixpt_M_local_0[22], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_176 = W[5];
end
else begin
mac_fixpt_t_176 = 14'b00000000000000;
end
mac_fixpt_add_cast_519 = {1'b0, mac_fixpt_t_176};
mac_fixpt_add_cast_520 = {1'b0, mac_fixpt_add_cast_519};
mac_fixpt_add_temp_172 = mac_fixpt_add_cast_518 + mac_fixpt_add_cast_520;
mac_fixpt_M_local_0[22] = mac_fixpt_add_temp_172[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_542 = {1'b0, {mac_fixpt_M_local_0[22], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_184 = W[6];
end
else begin
mac_fixpt_t_184 = 14'b00000000000000;
end
mac_fixpt_add_cast_543 = {1'b0, mac_fixpt_t_184};
mac_fixpt_add_cast_544 = {1'b0, mac_fixpt_add_cast_543};
mac_fixpt_add_temp_180 = mac_fixpt_add_cast_542 + mac_fixpt_add_cast_544;
mac_fixpt_M_local_0[22] = mac_fixpt_add_temp_180[14:1];
end
end
if (7'b0011000 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_419 = {1'b0, {mac_fixpt_M_local_0[23], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_143 = W[0];
end
else begin
mac_fixpt_t_143 = 14'b00000000000000;
end
mac_fixpt_add_cast_420 = {1'b0, mac_fixpt_t_143};
mac_fixpt_add_cast_421 = {1'b0, mac_fixpt_add_cast_420};
mac_fixpt_add_temp_139 = mac_fixpt_add_cast_419 + mac_fixpt_add_cast_421;
mac_fixpt_M_local_0[23] = mac_fixpt_add_temp_139[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_443 = {1'b0, {mac_fixpt_M_local_0[23], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_151 = W[1];
end
else begin
mac_fixpt_t_151 = 14'b00000000000000;
end
mac_fixpt_add_cast_444 = {1'b0, mac_fixpt_t_151};
mac_fixpt_add_cast_445 = {1'b0, mac_fixpt_add_cast_444};
mac_fixpt_add_temp_147 = mac_fixpt_add_cast_443 + mac_fixpt_add_cast_445;
mac_fixpt_M_local_0[23] = mac_fixpt_add_temp_147[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_467 = {1'b0, {mac_fixpt_M_local_0[23], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_159 = W[2];
end
else begin
mac_fixpt_t_159 = 14'b00000000000000;
end
mac_fixpt_add_cast_468 = {1'b0, mac_fixpt_t_159};
mac_fixpt_add_cast_469 = {1'b0, mac_fixpt_add_cast_468};
mac_fixpt_add_temp_155 = mac_fixpt_add_cast_467 + mac_fixpt_add_cast_469;
mac_fixpt_M_local_0[23] = mac_fixpt_add_temp_155[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_491 = {1'b0, {mac_fixpt_M_local_0[23], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_167 = W[3];
end
else begin
mac_fixpt_t_167 = 14'b00000000000000;
end
mac_fixpt_add_cast_492 = {1'b0, mac_fixpt_t_167};
mac_fixpt_add_cast_493 = {1'b0, mac_fixpt_add_cast_492};
mac_fixpt_add_temp_163 = mac_fixpt_add_cast_491 + mac_fixpt_add_cast_493;
mac_fixpt_M_local_0[23] = mac_fixpt_add_temp_163[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_515 = {1'b0, {mac_fixpt_M_local_0[23], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_175 = W[4];
end
else begin
mac_fixpt_t_175 = 14'b00000000000000;
end
mac_fixpt_add_cast_516 = {1'b0, mac_fixpt_t_175};
mac_fixpt_add_cast_517 = {1'b0, mac_fixpt_add_cast_516};
mac_fixpt_add_temp_171 = mac_fixpt_add_cast_515 + mac_fixpt_add_cast_517;
mac_fixpt_M_local_0[23] = mac_fixpt_add_temp_171[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_539 = {1'b0, {mac_fixpt_M_local_0[23], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_183 = W[5];
end
else begin
mac_fixpt_t_183 = 14'b00000000000000;
end
mac_fixpt_add_cast_540 = {1'b0, mac_fixpt_t_183};
mac_fixpt_add_cast_541 = {1'b0, mac_fixpt_add_cast_540};
mac_fixpt_add_temp_179 = mac_fixpt_add_cast_539 + mac_fixpt_add_cast_541;
mac_fixpt_M_local_0[23] = mac_fixpt_add_temp_179[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_563 = {1'b0, {mac_fixpt_M_local_0[23], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_191 = W[6];
end
else begin
mac_fixpt_t_191 = 14'b00000000000000;
end
mac_fixpt_add_cast_564 = {1'b0, mac_fixpt_t_191};
mac_fixpt_add_cast_565 = {1'b0, mac_fixpt_add_cast_564};
mac_fixpt_add_temp_187 = mac_fixpt_add_cast_563 + mac_fixpt_add_cast_565;
mac_fixpt_M_local_0[23] = mac_fixpt_add_temp_187[14:1];
end
end
if (7'b0011001 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_440 = {1'b0, {mac_fixpt_M_local_0[24], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_150 = W[0];
end
else begin
mac_fixpt_t_150 = 14'b00000000000000;
end
mac_fixpt_add_cast_441 = {1'b0, mac_fixpt_t_150};
mac_fixpt_add_cast_442 = {1'b0, mac_fixpt_add_cast_441};
mac_fixpt_add_temp_146 = mac_fixpt_add_cast_440 + mac_fixpt_add_cast_442;
mac_fixpt_M_local_0[24] = mac_fixpt_add_temp_146[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_464 = {1'b0, {mac_fixpt_M_local_0[24], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_158 = W[1];
end
else begin
mac_fixpt_t_158 = 14'b00000000000000;
end
mac_fixpt_add_cast_465 = {1'b0, mac_fixpt_t_158};
mac_fixpt_add_cast_466 = {1'b0, mac_fixpt_add_cast_465};
mac_fixpt_add_temp_154 = mac_fixpt_add_cast_464 + mac_fixpt_add_cast_466;
mac_fixpt_M_local_0[24] = mac_fixpt_add_temp_154[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_488 = {1'b0, {mac_fixpt_M_local_0[24], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_166 = W[2];
end
else begin
mac_fixpt_t_166 = 14'b00000000000000;
end
mac_fixpt_add_cast_489 = {1'b0, mac_fixpt_t_166};
mac_fixpt_add_cast_490 = {1'b0, mac_fixpt_add_cast_489};
mac_fixpt_add_temp_162 = mac_fixpt_add_cast_488 + mac_fixpt_add_cast_490;
mac_fixpt_M_local_0[24] = mac_fixpt_add_temp_162[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_512 = {1'b0, {mac_fixpt_M_local_0[24], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_174 = W[3];
end
else begin
mac_fixpt_t_174 = 14'b00000000000000;
end
mac_fixpt_add_cast_513 = {1'b0, mac_fixpt_t_174};
mac_fixpt_add_cast_514 = {1'b0, mac_fixpt_add_cast_513};
mac_fixpt_add_temp_170 = mac_fixpt_add_cast_512 + mac_fixpt_add_cast_514;
mac_fixpt_M_local_0[24] = mac_fixpt_add_temp_170[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_536 = {1'b0, {mac_fixpt_M_local_0[24], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_182 = W[4];
end
else begin
mac_fixpt_t_182 = 14'b00000000000000;
end
mac_fixpt_add_cast_537 = {1'b0, mac_fixpt_t_182};
mac_fixpt_add_cast_538 = {1'b0, mac_fixpt_add_cast_537};
mac_fixpt_add_temp_178 = mac_fixpt_add_cast_536 + mac_fixpt_add_cast_538;
mac_fixpt_M_local_0[24] = mac_fixpt_add_temp_178[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_560 = {1'b0, {mac_fixpt_M_local_0[24], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_190 = W[5];
end
else begin
mac_fixpt_t_190 = 14'b00000000000000;
end
mac_fixpt_add_cast_561 = {1'b0, mac_fixpt_t_190};
mac_fixpt_add_cast_562 = {1'b0, mac_fixpt_add_cast_561};
mac_fixpt_add_temp_186 = mac_fixpt_add_cast_560 + mac_fixpt_add_cast_562;
mac_fixpt_M_local_0[24] = mac_fixpt_add_temp_186[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_584 = {1'b0, {mac_fixpt_M_local_0[24], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_198 = W[6];
end
else begin
mac_fixpt_t_198 = 14'b00000000000000;
end
mac_fixpt_add_cast_585 = {1'b0, mac_fixpt_t_198};
mac_fixpt_add_cast_586 = {1'b0, mac_fixpt_add_cast_585};
mac_fixpt_add_temp_194 = mac_fixpt_add_cast_584 + mac_fixpt_add_cast_586;
mac_fixpt_M_local_0[24] = mac_fixpt_add_temp_194[14:1];
end
end
if (7'b0011010 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_461 = {1'b0, {mac_fixpt_M_local_0[25], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_157 = W[0];
end
else begin
mac_fixpt_t_157 = 14'b00000000000000;
end
mac_fixpt_add_cast_462 = {1'b0, mac_fixpt_t_157};
mac_fixpt_add_cast_463 = {1'b0, mac_fixpt_add_cast_462};
mac_fixpt_add_temp_153 = mac_fixpt_add_cast_461 + mac_fixpt_add_cast_463;
mac_fixpt_M_local_0[25] = mac_fixpt_add_temp_153[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_485 = {1'b0, {mac_fixpt_M_local_0[25], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_165 = W[1];
end
else begin
mac_fixpt_t_165 = 14'b00000000000000;
end
mac_fixpt_add_cast_486 = {1'b0, mac_fixpt_t_165};
mac_fixpt_add_cast_487 = {1'b0, mac_fixpt_add_cast_486};
mac_fixpt_add_temp_161 = mac_fixpt_add_cast_485 + mac_fixpt_add_cast_487;
mac_fixpt_M_local_0[25] = mac_fixpt_add_temp_161[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_509 = {1'b0, {mac_fixpt_M_local_0[25], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_173 = W[2];
end
else begin
mac_fixpt_t_173 = 14'b00000000000000;
end
mac_fixpt_add_cast_510 = {1'b0, mac_fixpt_t_173};
mac_fixpt_add_cast_511 = {1'b0, mac_fixpt_add_cast_510};
mac_fixpt_add_temp_169 = mac_fixpt_add_cast_509 + mac_fixpt_add_cast_511;
mac_fixpt_M_local_0[25] = mac_fixpt_add_temp_169[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_533 = {1'b0, {mac_fixpt_M_local_0[25], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_181 = W[3];
end
else begin
mac_fixpt_t_181 = 14'b00000000000000;
end
mac_fixpt_add_cast_534 = {1'b0, mac_fixpt_t_181};
mac_fixpt_add_cast_535 = {1'b0, mac_fixpt_add_cast_534};
mac_fixpt_add_temp_177 = mac_fixpt_add_cast_533 + mac_fixpt_add_cast_535;
mac_fixpt_M_local_0[25] = mac_fixpt_add_temp_177[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_557 = {1'b0, {mac_fixpt_M_local_0[25], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_189 = W[4];
end
else begin
mac_fixpt_t_189 = 14'b00000000000000;
end
mac_fixpt_add_cast_558 = {1'b0, mac_fixpt_t_189};
mac_fixpt_add_cast_559 = {1'b0, mac_fixpt_add_cast_558};
mac_fixpt_add_temp_185 = mac_fixpt_add_cast_557 + mac_fixpt_add_cast_559;
mac_fixpt_M_local_0[25] = mac_fixpt_add_temp_185[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_581 = {1'b0, {mac_fixpt_M_local_0[25], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_197 = W[5];
end
else begin
mac_fixpt_t_197 = 14'b00000000000000;
end
mac_fixpt_add_cast_582 = {1'b0, mac_fixpt_t_197};
mac_fixpt_add_cast_583 = {1'b0, mac_fixpt_add_cast_582};
mac_fixpt_add_temp_193 = mac_fixpt_add_cast_581 + mac_fixpt_add_cast_583;
mac_fixpt_M_local_0[25] = mac_fixpt_add_temp_193[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_605 = {1'b0, {mac_fixpt_M_local_0[25], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_205 = W[6];
end
else begin
mac_fixpt_t_205 = 14'b00000000000000;
end
mac_fixpt_add_cast_606 = {1'b0, mac_fixpt_t_205};
mac_fixpt_add_cast_607 = {1'b0, mac_fixpt_add_cast_606};
mac_fixpt_add_temp_201 = mac_fixpt_add_cast_605 + mac_fixpt_add_cast_607;
mac_fixpt_M_local_0[25] = mac_fixpt_add_temp_201[14:1];
end
end
if (7'b0011011 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_482 = {1'b0, {mac_fixpt_M_local_0[26], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_164 = W[0];
end
else begin
mac_fixpt_t_164 = 14'b00000000000000;
end
mac_fixpt_add_cast_483 = {1'b0, mac_fixpt_t_164};
mac_fixpt_add_cast_484 = {1'b0, mac_fixpt_add_cast_483};
mac_fixpt_add_temp_160 = mac_fixpt_add_cast_482 + mac_fixpt_add_cast_484;
mac_fixpt_M_local_0[26] = mac_fixpt_add_temp_160[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_506 = {1'b0, {mac_fixpt_M_local_0[26], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_172 = W[1];
end
else begin
mac_fixpt_t_172 = 14'b00000000000000;
end
mac_fixpt_add_cast_507 = {1'b0, mac_fixpt_t_172};
mac_fixpt_add_cast_508 = {1'b0, mac_fixpt_add_cast_507};
mac_fixpt_add_temp_168 = mac_fixpt_add_cast_506 + mac_fixpt_add_cast_508;
mac_fixpt_M_local_0[26] = mac_fixpt_add_temp_168[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_530 = {1'b0, {mac_fixpt_M_local_0[26], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_180 = W[2];
end
else begin
mac_fixpt_t_180 = 14'b00000000000000;
end
mac_fixpt_add_cast_531 = {1'b0, mac_fixpt_t_180};
mac_fixpt_add_cast_532 = {1'b0, mac_fixpt_add_cast_531};
mac_fixpt_add_temp_176 = mac_fixpt_add_cast_530 + mac_fixpt_add_cast_532;
mac_fixpt_M_local_0[26] = mac_fixpt_add_temp_176[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_554 = {1'b0, {mac_fixpt_M_local_0[26], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_188 = W[3];
end
else begin
mac_fixpt_t_188 = 14'b00000000000000;
end
mac_fixpt_add_cast_555 = {1'b0, mac_fixpt_t_188};
mac_fixpt_add_cast_556 = {1'b0, mac_fixpt_add_cast_555};
mac_fixpt_add_temp_184 = mac_fixpt_add_cast_554 + mac_fixpt_add_cast_556;
mac_fixpt_M_local_0[26] = mac_fixpt_add_temp_184[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_578 = {1'b0, {mac_fixpt_M_local_0[26], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_196 = W[4];
end
else begin
mac_fixpt_t_196 = 14'b00000000000000;
end
mac_fixpt_add_cast_579 = {1'b0, mac_fixpt_t_196};
mac_fixpt_add_cast_580 = {1'b0, mac_fixpt_add_cast_579};
mac_fixpt_add_temp_192 = mac_fixpt_add_cast_578 + mac_fixpt_add_cast_580;
mac_fixpt_M_local_0[26] = mac_fixpt_add_temp_192[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_602 = {1'b0, {mac_fixpt_M_local_0[26], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_204 = W[5];
end
else begin
mac_fixpt_t_204 = 14'b00000000000000;
end
mac_fixpt_add_cast_603 = {1'b0, mac_fixpt_t_204};
mac_fixpt_add_cast_604 = {1'b0, mac_fixpt_add_cast_603};
mac_fixpt_add_temp_200 = mac_fixpt_add_cast_602 + mac_fixpt_add_cast_604;
mac_fixpt_M_local_0[26] = mac_fixpt_add_temp_200[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_626 = {1'b0, {mac_fixpt_M_local_0[26], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_212 = W[6];
end
else begin
mac_fixpt_t_212 = 14'b00000000000000;
end
mac_fixpt_add_cast_627 = {1'b0, mac_fixpt_t_212};
mac_fixpt_add_cast_628 = {1'b0, mac_fixpt_add_cast_627};
mac_fixpt_add_temp_208 = mac_fixpt_add_cast_626 + mac_fixpt_add_cast_628;
mac_fixpt_M_local_0[26] = mac_fixpt_add_temp_208[14:1];
end
end
if (7'b0011100 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_503 = {1'b0, {mac_fixpt_M_local_0[27], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_171 = W[0];
end
else begin
mac_fixpt_t_171 = 14'b00000000000000;
end
mac_fixpt_add_cast_504 = {1'b0, mac_fixpt_t_171};
mac_fixpt_add_cast_505 = {1'b0, mac_fixpt_add_cast_504};
mac_fixpt_add_temp_167 = mac_fixpt_add_cast_503 + mac_fixpt_add_cast_505;
mac_fixpt_M_local_0[27] = mac_fixpt_add_temp_167[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_527 = {1'b0, {mac_fixpt_M_local_0[27], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_179 = W[1];
end
else begin
mac_fixpt_t_179 = 14'b00000000000000;
end
mac_fixpt_add_cast_528 = {1'b0, mac_fixpt_t_179};
mac_fixpt_add_cast_529 = {1'b0, mac_fixpt_add_cast_528};
mac_fixpt_add_temp_175 = mac_fixpt_add_cast_527 + mac_fixpt_add_cast_529;
mac_fixpt_M_local_0[27] = mac_fixpt_add_temp_175[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_551 = {1'b0, {mac_fixpt_M_local_0[27], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_187 = W[2];
end
else begin
mac_fixpt_t_187 = 14'b00000000000000;
end
mac_fixpt_add_cast_552 = {1'b0, mac_fixpt_t_187};
mac_fixpt_add_cast_553 = {1'b0, mac_fixpt_add_cast_552};
mac_fixpt_add_temp_183 = mac_fixpt_add_cast_551 + mac_fixpt_add_cast_553;
mac_fixpt_M_local_0[27] = mac_fixpt_add_temp_183[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_575 = {1'b0, {mac_fixpt_M_local_0[27], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_195 = W[3];
end
else begin
mac_fixpt_t_195 = 14'b00000000000000;
end
mac_fixpt_add_cast_576 = {1'b0, mac_fixpt_t_195};
mac_fixpt_add_cast_577 = {1'b0, mac_fixpt_add_cast_576};
mac_fixpt_add_temp_191 = mac_fixpt_add_cast_575 + mac_fixpt_add_cast_577;
mac_fixpt_M_local_0[27] = mac_fixpt_add_temp_191[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_599 = {1'b0, {mac_fixpt_M_local_0[27], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_203 = W[4];
end
else begin
mac_fixpt_t_203 = 14'b00000000000000;
end
mac_fixpt_add_cast_600 = {1'b0, mac_fixpt_t_203};
mac_fixpt_add_cast_601 = {1'b0, mac_fixpt_add_cast_600};
mac_fixpt_add_temp_199 = mac_fixpt_add_cast_599 + mac_fixpt_add_cast_601;
mac_fixpt_M_local_0[27] = mac_fixpt_add_temp_199[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_623 = {1'b0, {mac_fixpt_M_local_0[27], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_211 = W[5];
end
else begin
mac_fixpt_t_211 = 14'b00000000000000;
end
mac_fixpt_add_cast_624 = {1'b0, mac_fixpt_t_211};
mac_fixpt_add_cast_625 = {1'b0, mac_fixpt_add_cast_624};
mac_fixpt_add_temp_207 = mac_fixpt_add_cast_623 + mac_fixpt_add_cast_625;
mac_fixpt_M_local_0[27] = mac_fixpt_add_temp_207[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_647 = {1'b0, {mac_fixpt_M_local_0[27], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_219 = W[6];
end
else begin
mac_fixpt_t_219 = 14'b00000000000000;
end
mac_fixpt_add_cast_648 = {1'b0, mac_fixpt_t_219};
mac_fixpt_add_cast_649 = {1'b0, mac_fixpt_add_cast_648};
mac_fixpt_add_temp_215 = mac_fixpt_add_cast_647 + mac_fixpt_add_cast_649;
mac_fixpt_M_local_0[27] = mac_fixpt_add_temp_215[14:1];
end
end
if (7'b0011101 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_524 = {1'b0, {mac_fixpt_M_local_0[28], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_178 = W[0];
end
else begin
mac_fixpt_t_178 = 14'b00000000000000;
end
mac_fixpt_add_cast_525 = {1'b0, mac_fixpt_t_178};
mac_fixpt_add_cast_526 = {1'b0, mac_fixpt_add_cast_525};
mac_fixpt_add_temp_174 = mac_fixpt_add_cast_524 + mac_fixpt_add_cast_526;
mac_fixpt_M_local_0[28] = mac_fixpt_add_temp_174[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_548 = {1'b0, {mac_fixpt_M_local_0[28], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_186 = W[1];
end
else begin
mac_fixpt_t_186 = 14'b00000000000000;
end
mac_fixpt_add_cast_549 = {1'b0, mac_fixpt_t_186};
mac_fixpt_add_cast_550 = {1'b0, mac_fixpt_add_cast_549};
mac_fixpt_add_temp_182 = mac_fixpt_add_cast_548 + mac_fixpt_add_cast_550;
mac_fixpt_M_local_0[28] = mac_fixpt_add_temp_182[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_572 = {1'b0, {mac_fixpt_M_local_0[28], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_194 = W[2];
end
else begin
mac_fixpt_t_194 = 14'b00000000000000;
end
mac_fixpt_add_cast_573 = {1'b0, mac_fixpt_t_194};
mac_fixpt_add_cast_574 = {1'b0, mac_fixpt_add_cast_573};
mac_fixpt_add_temp_190 = mac_fixpt_add_cast_572 + mac_fixpt_add_cast_574;
mac_fixpt_M_local_0[28] = mac_fixpt_add_temp_190[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_596 = {1'b0, {mac_fixpt_M_local_0[28], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_202 = W[3];
end
else begin
mac_fixpt_t_202 = 14'b00000000000000;
end
mac_fixpt_add_cast_597 = {1'b0, mac_fixpt_t_202};
mac_fixpt_add_cast_598 = {1'b0, mac_fixpt_add_cast_597};
mac_fixpt_add_temp_198 = mac_fixpt_add_cast_596 + mac_fixpt_add_cast_598;
mac_fixpt_M_local_0[28] = mac_fixpt_add_temp_198[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_620 = {1'b0, {mac_fixpt_M_local_0[28], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_210 = W[4];
end
else begin
mac_fixpt_t_210 = 14'b00000000000000;
end
mac_fixpt_add_cast_621 = {1'b0, mac_fixpt_t_210};
mac_fixpt_add_cast_622 = {1'b0, mac_fixpt_add_cast_621};
mac_fixpt_add_temp_206 = mac_fixpt_add_cast_620 + mac_fixpt_add_cast_622;
mac_fixpt_M_local_0[28] = mac_fixpt_add_temp_206[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_644 = {1'b0, {mac_fixpt_M_local_0[28], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_218 = W[5];
end
else begin
mac_fixpt_t_218 = 14'b00000000000000;
end
mac_fixpt_add_cast_645 = {1'b0, mac_fixpt_t_218};
mac_fixpt_add_cast_646 = {1'b0, mac_fixpt_add_cast_645};
mac_fixpt_add_temp_214 = mac_fixpt_add_cast_644 + mac_fixpt_add_cast_646;
mac_fixpt_M_local_0[28] = mac_fixpt_add_temp_214[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_668 = {1'b0, {mac_fixpt_M_local_0[28], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_226 = W[6];
end
else begin
mac_fixpt_t_226 = 14'b00000000000000;
end
mac_fixpt_add_cast_669 = {1'b0, mac_fixpt_t_226};
mac_fixpt_add_cast_670 = {1'b0, mac_fixpt_add_cast_669};
mac_fixpt_add_temp_222 = mac_fixpt_add_cast_668 + mac_fixpt_add_cast_670;
mac_fixpt_M_local_0[28] = mac_fixpt_add_temp_222[14:1];
end
end
if (7'b0011110 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_545 = {1'b0, {mac_fixpt_M_local_0[29], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_185 = W[0];
end
else begin
mac_fixpt_t_185 = 14'b00000000000000;
end
mac_fixpt_add_cast_546 = {1'b0, mac_fixpt_t_185};
mac_fixpt_add_cast_547 = {1'b0, mac_fixpt_add_cast_546};
mac_fixpt_add_temp_181 = mac_fixpt_add_cast_545 + mac_fixpt_add_cast_547;
mac_fixpt_M_local_0[29] = mac_fixpt_add_temp_181[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_569 = {1'b0, {mac_fixpt_M_local_0[29], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_193 = W[1];
end
else begin
mac_fixpt_t_193 = 14'b00000000000000;
end
mac_fixpt_add_cast_570 = {1'b0, mac_fixpt_t_193};
mac_fixpt_add_cast_571 = {1'b0, mac_fixpt_add_cast_570};
mac_fixpt_add_temp_189 = mac_fixpt_add_cast_569 + mac_fixpt_add_cast_571;
mac_fixpt_M_local_0[29] = mac_fixpt_add_temp_189[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_593 = {1'b0, {mac_fixpt_M_local_0[29], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_201 = W[2];
end
else begin
mac_fixpt_t_201 = 14'b00000000000000;
end
mac_fixpt_add_cast_594 = {1'b0, mac_fixpt_t_201};
mac_fixpt_add_cast_595 = {1'b0, mac_fixpt_add_cast_594};
mac_fixpt_add_temp_197 = mac_fixpt_add_cast_593 + mac_fixpt_add_cast_595;
mac_fixpt_M_local_0[29] = mac_fixpt_add_temp_197[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_617 = {1'b0, {mac_fixpt_M_local_0[29], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_209 = W[3];
end
else begin
mac_fixpt_t_209 = 14'b00000000000000;
end
mac_fixpt_add_cast_618 = {1'b0, mac_fixpt_t_209};
mac_fixpt_add_cast_619 = {1'b0, mac_fixpt_add_cast_618};
mac_fixpt_add_temp_205 = mac_fixpt_add_cast_617 + mac_fixpt_add_cast_619;
mac_fixpt_M_local_0[29] = mac_fixpt_add_temp_205[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_641 = {1'b0, {mac_fixpt_M_local_0[29], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_217 = W[4];
end
else begin
mac_fixpt_t_217 = 14'b00000000000000;
end
mac_fixpt_add_cast_642 = {1'b0, mac_fixpt_t_217};
mac_fixpt_add_cast_643 = {1'b0, mac_fixpt_add_cast_642};
mac_fixpt_add_temp_213 = mac_fixpt_add_cast_641 + mac_fixpt_add_cast_643;
mac_fixpt_M_local_0[29] = mac_fixpt_add_temp_213[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_665 = {1'b0, {mac_fixpt_M_local_0[29], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_225 = W[5];
end
else begin
mac_fixpt_t_225 = 14'b00000000000000;
end
mac_fixpt_add_cast_666 = {1'b0, mac_fixpt_t_225};
mac_fixpt_add_cast_667 = {1'b0, mac_fixpt_add_cast_666};
mac_fixpt_add_temp_221 = mac_fixpt_add_cast_665 + mac_fixpt_add_cast_667;
mac_fixpt_M_local_0[29] = mac_fixpt_add_temp_221[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_689 = {1'b0, {mac_fixpt_M_local_0[29], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_233 = W[6];
end
else begin
mac_fixpt_t_233 = 14'b00000000000000;
end
mac_fixpt_add_cast_690 = {1'b0, mac_fixpt_t_233};
mac_fixpt_add_cast_691 = {1'b0, mac_fixpt_add_cast_690};
mac_fixpt_add_temp_229 = mac_fixpt_add_cast_689 + mac_fixpt_add_cast_691;
mac_fixpt_M_local_0[29] = mac_fixpt_add_temp_229[14:1];
end
end
if (7'b0011111 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_566 = {1'b0, {mac_fixpt_M_local_0[30], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_192 = W[0];
end
else begin
mac_fixpt_t_192 = 14'b00000000000000;
end
mac_fixpt_add_cast_567 = {1'b0, mac_fixpt_t_192};
mac_fixpt_add_cast_568 = {1'b0, mac_fixpt_add_cast_567};
mac_fixpt_add_temp_188 = mac_fixpt_add_cast_566 + mac_fixpt_add_cast_568;
mac_fixpt_M_local_0[30] = mac_fixpt_add_temp_188[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_590 = {1'b0, {mac_fixpt_M_local_0[30], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_200 = W[1];
end
else begin
mac_fixpt_t_200 = 14'b00000000000000;
end
mac_fixpt_add_cast_591 = {1'b0, mac_fixpt_t_200};
mac_fixpt_add_cast_592 = {1'b0, mac_fixpt_add_cast_591};
mac_fixpt_add_temp_196 = mac_fixpt_add_cast_590 + mac_fixpt_add_cast_592;
mac_fixpt_M_local_0[30] = mac_fixpt_add_temp_196[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_614 = {1'b0, {mac_fixpt_M_local_0[30], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_208 = W[2];
end
else begin
mac_fixpt_t_208 = 14'b00000000000000;
end
mac_fixpt_add_cast_615 = {1'b0, mac_fixpt_t_208};
mac_fixpt_add_cast_616 = {1'b0, mac_fixpt_add_cast_615};
mac_fixpt_add_temp_204 = mac_fixpt_add_cast_614 + mac_fixpt_add_cast_616;
mac_fixpt_M_local_0[30] = mac_fixpt_add_temp_204[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_638 = {1'b0, {mac_fixpt_M_local_0[30], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_216 = W[3];
end
else begin
mac_fixpt_t_216 = 14'b00000000000000;
end
mac_fixpt_add_cast_639 = {1'b0, mac_fixpt_t_216};
mac_fixpt_add_cast_640 = {1'b0, mac_fixpt_add_cast_639};
mac_fixpt_add_temp_212 = mac_fixpt_add_cast_638 + mac_fixpt_add_cast_640;
mac_fixpt_M_local_0[30] = mac_fixpt_add_temp_212[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_662 = {1'b0, {mac_fixpt_M_local_0[30], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_224 = W[4];
end
else begin
mac_fixpt_t_224 = 14'b00000000000000;
end
mac_fixpt_add_cast_663 = {1'b0, mac_fixpt_t_224};
mac_fixpt_add_cast_664 = {1'b0, mac_fixpt_add_cast_663};
mac_fixpt_add_temp_220 = mac_fixpt_add_cast_662 + mac_fixpt_add_cast_664;
mac_fixpt_M_local_0[30] = mac_fixpt_add_temp_220[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_686 = {1'b0, {mac_fixpt_M_local_0[30], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_232 = W[5];
end
else begin
mac_fixpt_t_232 = 14'b00000000000000;
end
mac_fixpt_add_cast_687 = {1'b0, mac_fixpt_t_232};
mac_fixpt_add_cast_688 = {1'b0, mac_fixpt_add_cast_687};
mac_fixpt_add_temp_228 = mac_fixpt_add_cast_686 + mac_fixpt_add_cast_688;
mac_fixpt_M_local_0[30] = mac_fixpt_add_temp_228[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_710 = {1'b0, {mac_fixpt_M_local_0[30], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_240 = W[6];
end
else begin
mac_fixpt_t_240 = 14'b00000000000000;
end
mac_fixpt_add_cast_711 = {1'b0, mac_fixpt_t_240};
mac_fixpt_add_cast_712 = {1'b0, mac_fixpt_add_cast_711};
mac_fixpt_add_temp_236 = mac_fixpt_add_cast_710 + mac_fixpt_add_cast_712;
mac_fixpt_M_local_0[30] = mac_fixpt_add_temp_236[14:1];
end
end
if (7'b0100000 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_587 = {1'b0, {mac_fixpt_M_local_0[31], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_199 = W[0];
end
else begin
mac_fixpt_t_199 = 14'b00000000000000;
end
mac_fixpt_add_cast_588 = {1'b0, mac_fixpt_t_199};
mac_fixpt_add_cast_589 = {1'b0, mac_fixpt_add_cast_588};
mac_fixpt_add_temp_195 = mac_fixpt_add_cast_587 + mac_fixpt_add_cast_589;
mac_fixpt_M_local_0[31] = mac_fixpt_add_temp_195[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_611 = {1'b0, {mac_fixpt_M_local_0[31], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_207 = W[1];
end
else begin
mac_fixpt_t_207 = 14'b00000000000000;
end
mac_fixpt_add_cast_612 = {1'b0, mac_fixpt_t_207};
mac_fixpt_add_cast_613 = {1'b0, mac_fixpt_add_cast_612};
mac_fixpt_add_temp_203 = mac_fixpt_add_cast_611 + mac_fixpt_add_cast_613;
mac_fixpt_M_local_0[31] = mac_fixpt_add_temp_203[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_635 = {1'b0, {mac_fixpt_M_local_0[31], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_215 = W[2];
end
else begin
mac_fixpt_t_215 = 14'b00000000000000;
end
mac_fixpt_add_cast_636 = {1'b0, mac_fixpt_t_215};
mac_fixpt_add_cast_637 = {1'b0, mac_fixpt_add_cast_636};
mac_fixpt_add_temp_211 = mac_fixpt_add_cast_635 + mac_fixpt_add_cast_637;
mac_fixpt_M_local_0[31] = mac_fixpt_add_temp_211[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_659 = {1'b0, {mac_fixpt_M_local_0[31], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_223 = W[3];
end
else begin
mac_fixpt_t_223 = 14'b00000000000000;
end
mac_fixpt_add_cast_660 = {1'b0, mac_fixpt_t_223};
mac_fixpt_add_cast_661 = {1'b0, mac_fixpt_add_cast_660};
mac_fixpt_add_temp_219 = mac_fixpt_add_cast_659 + mac_fixpt_add_cast_661;
mac_fixpt_M_local_0[31] = mac_fixpt_add_temp_219[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_683 = {1'b0, {mac_fixpt_M_local_0[31], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_231 = W[4];
end
else begin
mac_fixpt_t_231 = 14'b00000000000000;
end
mac_fixpt_add_cast_684 = {1'b0, mac_fixpt_t_231};
mac_fixpt_add_cast_685 = {1'b0, mac_fixpt_add_cast_684};
mac_fixpt_add_temp_227 = mac_fixpt_add_cast_683 + mac_fixpt_add_cast_685;
mac_fixpt_M_local_0[31] = mac_fixpt_add_temp_227[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_707 = {1'b0, {mac_fixpt_M_local_0[31], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_239 = W[5];
end
else begin
mac_fixpt_t_239 = 14'b00000000000000;
end
mac_fixpt_add_cast_708 = {1'b0, mac_fixpt_t_239};
mac_fixpt_add_cast_709 = {1'b0, mac_fixpt_add_cast_708};
mac_fixpt_add_temp_235 = mac_fixpt_add_cast_707 + mac_fixpt_add_cast_709;
mac_fixpt_M_local_0[31] = mac_fixpt_add_temp_235[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_731 = {1'b0, {mac_fixpt_M_local_0[31], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_247 = W[6];
end
else begin
mac_fixpt_t_247 = 14'b00000000000000;
end
mac_fixpt_add_cast_732 = {1'b0, mac_fixpt_t_247};
mac_fixpt_add_cast_733 = {1'b0, mac_fixpt_add_cast_732};
mac_fixpt_add_temp_243 = mac_fixpt_add_cast_731 + mac_fixpt_add_cast_733;
mac_fixpt_M_local_0[31] = mac_fixpt_add_temp_243[14:1];
end
end
if (7'b0100001 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_608 = {1'b0, {mac_fixpt_M_local_0[32], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_206 = W[0];
end
else begin
mac_fixpt_t_206 = 14'b00000000000000;
end
mac_fixpt_add_cast_609 = {1'b0, mac_fixpt_t_206};
mac_fixpt_add_cast_610 = {1'b0, mac_fixpt_add_cast_609};
mac_fixpt_add_temp_202 = mac_fixpt_add_cast_608 + mac_fixpt_add_cast_610;
mac_fixpt_M_local_0[32] = mac_fixpt_add_temp_202[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_632 = {1'b0, {mac_fixpt_M_local_0[32], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_214 = W[1];
end
else begin
mac_fixpt_t_214 = 14'b00000000000000;
end
mac_fixpt_add_cast_633 = {1'b0, mac_fixpt_t_214};
mac_fixpt_add_cast_634 = {1'b0, mac_fixpt_add_cast_633};
mac_fixpt_add_temp_210 = mac_fixpt_add_cast_632 + mac_fixpt_add_cast_634;
mac_fixpt_M_local_0[32] = mac_fixpt_add_temp_210[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_656 = {1'b0, {mac_fixpt_M_local_0[32], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_222 = W[2];
end
else begin
mac_fixpt_t_222 = 14'b00000000000000;
end
mac_fixpt_add_cast_657 = {1'b0, mac_fixpt_t_222};
mac_fixpt_add_cast_658 = {1'b0, mac_fixpt_add_cast_657};
mac_fixpt_add_temp_218 = mac_fixpt_add_cast_656 + mac_fixpt_add_cast_658;
mac_fixpt_M_local_0[32] = mac_fixpt_add_temp_218[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_680 = {1'b0, {mac_fixpt_M_local_0[32], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_230 = W[3];
end
else begin
mac_fixpt_t_230 = 14'b00000000000000;
end
mac_fixpt_add_cast_681 = {1'b0, mac_fixpt_t_230};
mac_fixpt_add_cast_682 = {1'b0, mac_fixpt_add_cast_681};
mac_fixpt_add_temp_226 = mac_fixpt_add_cast_680 + mac_fixpt_add_cast_682;
mac_fixpt_M_local_0[32] = mac_fixpt_add_temp_226[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_704 = {1'b0, {mac_fixpt_M_local_0[32], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_238 = W[4];
end
else begin
mac_fixpt_t_238 = 14'b00000000000000;
end
mac_fixpt_add_cast_705 = {1'b0, mac_fixpt_t_238};
mac_fixpt_add_cast_706 = {1'b0, mac_fixpt_add_cast_705};
mac_fixpt_add_temp_234 = mac_fixpt_add_cast_704 + mac_fixpt_add_cast_706;
mac_fixpt_M_local_0[32] = mac_fixpt_add_temp_234[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_728 = {1'b0, {mac_fixpt_M_local_0[32], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_246 = W[5];
end
else begin
mac_fixpt_t_246 = 14'b00000000000000;
end
mac_fixpt_add_cast_729 = {1'b0, mac_fixpt_t_246};
mac_fixpt_add_cast_730 = {1'b0, mac_fixpt_add_cast_729};
mac_fixpt_add_temp_242 = mac_fixpt_add_cast_728 + mac_fixpt_add_cast_730;
mac_fixpt_M_local_0[32] = mac_fixpt_add_temp_242[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_752 = {1'b0, {mac_fixpt_M_local_0[32], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_254 = W[6];
end
else begin
mac_fixpt_t_254 = 14'b00000000000000;
end
mac_fixpt_add_cast_753 = {1'b0, mac_fixpt_t_254};
mac_fixpt_add_cast_754 = {1'b0, mac_fixpt_add_cast_753};
mac_fixpt_add_temp_250 = mac_fixpt_add_cast_752 + mac_fixpt_add_cast_754;
mac_fixpt_M_local_0[32] = mac_fixpt_add_temp_250[14:1];
end
end
if (7'b0100010 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_629 = {1'b0, {mac_fixpt_M_local_0[33], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_213 = W[0];
end
else begin
mac_fixpt_t_213 = 14'b00000000000000;
end
mac_fixpt_add_cast_630 = {1'b0, mac_fixpt_t_213};
mac_fixpt_add_cast_631 = {1'b0, mac_fixpt_add_cast_630};
mac_fixpt_add_temp_209 = mac_fixpt_add_cast_629 + mac_fixpt_add_cast_631;
mac_fixpt_M_local_0[33] = mac_fixpt_add_temp_209[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_653 = {1'b0, {mac_fixpt_M_local_0[33], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_221 = W[1];
end
else begin
mac_fixpt_t_221 = 14'b00000000000000;
end
mac_fixpt_add_cast_654 = {1'b0, mac_fixpt_t_221};
mac_fixpt_add_cast_655 = {1'b0, mac_fixpt_add_cast_654};
mac_fixpt_add_temp_217 = mac_fixpt_add_cast_653 + mac_fixpt_add_cast_655;
mac_fixpt_M_local_0[33] = mac_fixpt_add_temp_217[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_677 = {1'b0, {mac_fixpt_M_local_0[33], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_229 = W[2];
end
else begin
mac_fixpt_t_229 = 14'b00000000000000;
end
mac_fixpt_add_cast_678 = {1'b0, mac_fixpt_t_229};
mac_fixpt_add_cast_679 = {1'b0, mac_fixpt_add_cast_678};
mac_fixpt_add_temp_225 = mac_fixpt_add_cast_677 + mac_fixpt_add_cast_679;
mac_fixpt_M_local_0[33] = mac_fixpt_add_temp_225[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_701 = {1'b0, {mac_fixpt_M_local_0[33], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_237 = W[3];
end
else begin
mac_fixpt_t_237 = 14'b00000000000000;
end
mac_fixpt_add_cast_702 = {1'b0, mac_fixpt_t_237};
mac_fixpt_add_cast_703 = {1'b0, mac_fixpt_add_cast_702};
mac_fixpt_add_temp_233 = mac_fixpt_add_cast_701 + mac_fixpt_add_cast_703;
mac_fixpt_M_local_0[33] = mac_fixpt_add_temp_233[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_725 = {1'b0, {mac_fixpt_M_local_0[33], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_245 = W[4];
end
else begin
mac_fixpt_t_245 = 14'b00000000000000;
end
mac_fixpt_add_cast_726 = {1'b0, mac_fixpt_t_245};
mac_fixpt_add_cast_727 = {1'b0, mac_fixpt_add_cast_726};
mac_fixpt_add_temp_241 = mac_fixpt_add_cast_725 + mac_fixpt_add_cast_727;
mac_fixpt_M_local_0[33] = mac_fixpt_add_temp_241[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_749 = {1'b0, {mac_fixpt_M_local_0[33], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_253 = W[5];
end
else begin
mac_fixpt_t_253 = 14'b00000000000000;
end
mac_fixpt_add_cast_750 = {1'b0, mac_fixpt_t_253};
mac_fixpt_add_cast_751 = {1'b0, mac_fixpt_add_cast_750};
mac_fixpt_add_temp_249 = mac_fixpt_add_cast_749 + mac_fixpt_add_cast_751;
mac_fixpt_M_local_0[33] = mac_fixpt_add_temp_249[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_773 = {1'b0, {mac_fixpt_M_local_0[33], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_261 = W[6];
end
else begin
mac_fixpt_t_261 = 14'b00000000000000;
end
mac_fixpt_add_cast_774 = {1'b0, mac_fixpt_t_261};
mac_fixpt_add_cast_775 = {1'b0, mac_fixpt_add_cast_774};
mac_fixpt_add_temp_257 = mac_fixpt_add_cast_773 + mac_fixpt_add_cast_775;
mac_fixpt_M_local_0[33] = mac_fixpt_add_temp_257[14:1];
end
end
if (7'b0100011 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_650 = {1'b0, {mac_fixpt_M_local_0[34], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_220 = W[0];
end
else begin
mac_fixpt_t_220 = 14'b00000000000000;
end
mac_fixpt_add_cast_651 = {1'b0, mac_fixpt_t_220};
mac_fixpt_add_cast_652 = {1'b0, mac_fixpt_add_cast_651};
mac_fixpt_add_temp_216 = mac_fixpt_add_cast_650 + mac_fixpt_add_cast_652;
mac_fixpt_M_local_0[34] = mac_fixpt_add_temp_216[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_674 = {1'b0, {mac_fixpt_M_local_0[34], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_228 = W[1];
end
else begin
mac_fixpt_t_228 = 14'b00000000000000;
end
mac_fixpt_add_cast_675 = {1'b0, mac_fixpt_t_228};
mac_fixpt_add_cast_676 = {1'b0, mac_fixpt_add_cast_675};
mac_fixpt_add_temp_224 = mac_fixpt_add_cast_674 + mac_fixpt_add_cast_676;
mac_fixpt_M_local_0[34] = mac_fixpt_add_temp_224[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_698 = {1'b0, {mac_fixpt_M_local_0[34], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_236 = W[2];
end
else begin
mac_fixpt_t_236 = 14'b00000000000000;
end
mac_fixpt_add_cast_699 = {1'b0, mac_fixpt_t_236};
mac_fixpt_add_cast_700 = {1'b0, mac_fixpt_add_cast_699};
mac_fixpt_add_temp_232 = mac_fixpt_add_cast_698 + mac_fixpt_add_cast_700;
mac_fixpt_M_local_0[34] = mac_fixpt_add_temp_232[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_722 = {1'b0, {mac_fixpt_M_local_0[34], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_244 = W[3];
end
else begin
mac_fixpt_t_244 = 14'b00000000000000;
end
mac_fixpt_add_cast_723 = {1'b0, mac_fixpt_t_244};
mac_fixpt_add_cast_724 = {1'b0, mac_fixpt_add_cast_723};
mac_fixpt_add_temp_240 = mac_fixpt_add_cast_722 + mac_fixpt_add_cast_724;
mac_fixpt_M_local_0[34] = mac_fixpt_add_temp_240[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_746 = {1'b0, {mac_fixpt_M_local_0[34], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_252 = W[4];
end
else begin
mac_fixpt_t_252 = 14'b00000000000000;
end
mac_fixpt_add_cast_747 = {1'b0, mac_fixpt_t_252};
mac_fixpt_add_cast_748 = {1'b0, mac_fixpt_add_cast_747};
mac_fixpt_add_temp_248 = mac_fixpt_add_cast_746 + mac_fixpt_add_cast_748;
mac_fixpt_M_local_0[34] = mac_fixpt_add_temp_248[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_770 = {1'b0, {mac_fixpt_M_local_0[34], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_260 = W[5];
end
else begin
mac_fixpt_t_260 = 14'b00000000000000;
end
mac_fixpt_add_cast_771 = {1'b0, mac_fixpt_t_260};
mac_fixpt_add_cast_772 = {1'b0, mac_fixpt_add_cast_771};
mac_fixpt_add_temp_256 = mac_fixpt_add_cast_770 + mac_fixpt_add_cast_772;
mac_fixpt_M_local_0[34] = mac_fixpt_add_temp_256[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_794 = {1'b0, {mac_fixpt_M_local_0[34], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_268 = W[6];
end
else begin
mac_fixpt_t_268 = 14'b00000000000000;
end
mac_fixpt_add_cast_795 = {1'b0, mac_fixpt_t_268};
mac_fixpt_add_cast_796 = {1'b0, mac_fixpt_add_cast_795};
mac_fixpt_add_temp_264 = mac_fixpt_add_cast_794 + mac_fixpt_add_cast_796;
mac_fixpt_M_local_0[34] = mac_fixpt_add_temp_264[14:1];
end
end
if (7'b0100100 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_671 = {1'b0, {mac_fixpt_M_local_0[35], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_227 = W[0];
end
else begin
mac_fixpt_t_227 = 14'b00000000000000;
end
mac_fixpt_add_cast_672 = {1'b0, mac_fixpt_t_227};
mac_fixpt_add_cast_673 = {1'b0, mac_fixpt_add_cast_672};
mac_fixpt_add_temp_223 = mac_fixpt_add_cast_671 + mac_fixpt_add_cast_673;
mac_fixpt_M_local_0[35] = mac_fixpt_add_temp_223[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_695 = {1'b0, {mac_fixpt_M_local_0[35], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_235 = W[1];
end
else begin
mac_fixpt_t_235 = 14'b00000000000000;
end
mac_fixpt_add_cast_696 = {1'b0, mac_fixpt_t_235};
mac_fixpt_add_cast_697 = {1'b0, mac_fixpt_add_cast_696};
mac_fixpt_add_temp_231 = mac_fixpt_add_cast_695 + mac_fixpt_add_cast_697;
mac_fixpt_M_local_0[35] = mac_fixpt_add_temp_231[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_719 = {1'b0, {mac_fixpt_M_local_0[35], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_243 = W[2];
end
else begin
mac_fixpt_t_243 = 14'b00000000000000;
end
mac_fixpt_add_cast_720 = {1'b0, mac_fixpt_t_243};
mac_fixpt_add_cast_721 = {1'b0, mac_fixpt_add_cast_720};
mac_fixpt_add_temp_239 = mac_fixpt_add_cast_719 + mac_fixpt_add_cast_721;
mac_fixpt_M_local_0[35] = mac_fixpt_add_temp_239[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_743 = {1'b0, {mac_fixpt_M_local_0[35], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_251 = W[3];
end
else begin
mac_fixpt_t_251 = 14'b00000000000000;
end
mac_fixpt_add_cast_744 = {1'b0, mac_fixpt_t_251};
mac_fixpt_add_cast_745 = {1'b0, mac_fixpt_add_cast_744};
mac_fixpt_add_temp_247 = mac_fixpt_add_cast_743 + mac_fixpt_add_cast_745;
mac_fixpt_M_local_0[35] = mac_fixpt_add_temp_247[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_767 = {1'b0, {mac_fixpt_M_local_0[35], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_259 = W[4];
end
else begin
mac_fixpt_t_259 = 14'b00000000000000;
end
mac_fixpt_add_cast_768 = {1'b0, mac_fixpt_t_259};
mac_fixpt_add_cast_769 = {1'b0, mac_fixpt_add_cast_768};
mac_fixpt_add_temp_255 = mac_fixpt_add_cast_767 + mac_fixpt_add_cast_769;
mac_fixpt_M_local_0[35] = mac_fixpt_add_temp_255[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_791 = {1'b0, {mac_fixpt_M_local_0[35], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_267 = W[5];
end
else begin
mac_fixpt_t_267 = 14'b00000000000000;
end
mac_fixpt_add_cast_792 = {1'b0, mac_fixpt_t_267};
mac_fixpt_add_cast_793 = {1'b0, mac_fixpt_add_cast_792};
mac_fixpt_add_temp_263 = mac_fixpt_add_cast_791 + mac_fixpt_add_cast_793;
mac_fixpt_M_local_0[35] = mac_fixpt_add_temp_263[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_815 = {1'b0, {mac_fixpt_M_local_0[35], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_275 = W[6];
end
else begin
mac_fixpt_t_275 = 14'b00000000000000;
end
mac_fixpt_add_cast_816 = {1'b0, mac_fixpt_t_275};
mac_fixpt_add_cast_817 = {1'b0, mac_fixpt_add_cast_816};
mac_fixpt_add_temp_271 = mac_fixpt_add_cast_815 + mac_fixpt_add_cast_817;
mac_fixpt_M_local_0[35] = mac_fixpt_add_temp_271[14:1];
end
end
if (7'b0100101 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_692 = {1'b0, {mac_fixpt_M_local_0[36], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_234 = W[0];
end
else begin
mac_fixpt_t_234 = 14'b00000000000000;
end
mac_fixpt_add_cast_693 = {1'b0, mac_fixpt_t_234};
mac_fixpt_add_cast_694 = {1'b0, mac_fixpt_add_cast_693};
mac_fixpt_add_temp_230 = mac_fixpt_add_cast_692 + mac_fixpt_add_cast_694;
mac_fixpt_M_local_0[36] = mac_fixpt_add_temp_230[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_716 = {1'b0, {mac_fixpt_M_local_0[36], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_242 = W[1];
end
else begin
mac_fixpt_t_242 = 14'b00000000000000;
end
mac_fixpt_add_cast_717 = {1'b0, mac_fixpt_t_242};
mac_fixpt_add_cast_718 = {1'b0, mac_fixpt_add_cast_717};
mac_fixpt_add_temp_238 = mac_fixpt_add_cast_716 + mac_fixpt_add_cast_718;
mac_fixpt_M_local_0[36] = mac_fixpt_add_temp_238[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_740 = {1'b0, {mac_fixpt_M_local_0[36], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_250 = W[2];
end
else begin
mac_fixpt_t_250 = 14'b00000000000000;
end
mac_fixpt_add_cast_741 = {1'b0, mac_fixpt_t_250};
mac_fixpt_add_cast_742 = {1'b0, mac_fixpt_add_cast_741};
mac_fixpt_add_temp_246 = mac_fixpt_add_cast_740 + mac_fixpt_add_cast_742;
mac_fixpt_M_local_0[36] = mac_fixpt_add_temp_246[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_764 = {1'b0, {mac_fixpt_M_local_0[36], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_258 = W[3];
end
else begin
mac_fixpt_t_258 = 14'b00000000000000;
end
mac_fixpt_add_cast_765 = {1'b0, mac_fixpt_t_258};
mac_fixpt_add_cast_766 = {1'b0, mac_fixpt_add_cast_765};
mac_fixpt_add_temp_254 = mac_fixpt_add_cast_764 + mac_fixpt_add_cast_766;
mac_fixpt_M_local_0[36] = mac_fixpt_add_temp_254[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_788 = {1'b0, {mac_fixpt_M_local_0[36], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_266 = W[4];
end
else begin
mac_fixpt_t_266 = 14'b00000000000000;
end
mac_fixpt_add_cast_789 = {1'b0, mac_fixpt_t_266};
mac_fixpt_add_cast_790 = {1'b0, mac_fixpt_add_cast_789};
mac_fixpt_add_temp_262 = mac_fixpt_add_cast_788 + mac_fixpt_add_cast_790;
mac_fixpt_M_local_0[36] = mac_fixpt_add_temp_262[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_812 = {1'b0, {mac_fixpt_M_local_0[36], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_274 = W[5];
end
else begin
mac_fixpt_t_274 = 14'b00000000000000;
end
mac_fixpt_add_cast_813 = {1'b0, mac_fixpt_t_274};
mac_fixpt_add_cast_814 = {1'b0, mac_fixpt_add_cast_813};
mac_fixpt_add_temp_270 = mac_fixpt_add_cast_812 + mac_fixpt_add_cast_814;
mac_fixpt_M_local_0[36] = mac_fixpt_add_temp_270[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_836 = {1'b0, {mac_fixpt_M_local_0[36], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_282 = W[6];
end
else begin
mac_fixpt_t_282 = 14'b00000000000000;
end
mac_fixpt_add_cast_837 = {1'b0, mac_fixpt_t_282};
mac_fixpt_add_cast_838 = {1'b0, mac_fixpt_add_cast_837};
mac_fixpt_add_temp_278 = mac_fixpt_add_cast_836 + mac_fixpt_add_cast_838;
mac_fixpt_M_local_0[36] = mac_fixpt_add_temp_278[14:1];
end
end
if (7'b0100110 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_713 = {1'b0, {mac_fixpt_M_local_0[37], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_241 = W[0];
end
else begin
mac_fixpt_t_241 = 14'b00000000000000;
end
mac_fixpt_add_cast_714 = {1'b0, mac_fixpt_t_241};
mac_fixpt_add_cast_715 = {1'b0, mac_fixpt_add_cast_714};
mac_fixpt_add_temp_237 = mac_fixpt_add_cast_713 + mac_fixpt_add_cast_715;
mac_fixpt_M_local_0[37] = mac_fixpt_add_temp_237[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_737 = {1'b0, {mac_fixpt_M_local_0[37], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_249 = W[1];
end
else begin
mac_fixpt_t_249 = 14'b00000000000000;
end
mac_fixpt_add_cast_738 = {1'b0, mac_fixpt_t_249};
mac_fixpt_add_cast_739 = {1'b0, mac_fixpt_add_cast_738};
mac_fixpt_add_temp_245 = mac_fixpt_add_cast_737 + mac_fixpt_add_cast_739;
mac_fixpt_M_local_0[37] = mac_fixpt_add_temp_245[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_761 = {1'b0, {mac_fixpt_M_local_0[37], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_257 = W[2];
end
else begin
mac_fixpt_t_257 = 14'b00000000000000;
end
mac_fixpt_add_cast_762 = {1'b0, mac_fixpt_t_257};
mac_fixpt_add_cast_763 = {1'b0, mac_fixpt_add_cast_762};
mac_fixpt_add_temp_253 = mac_fixpt_add_cast_761 + mac_fixpt_add_cast_763;
mac_fixpt_M_local_0[37] = mac_fixpt_add_temp_253[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_785 = {1'b0, {mac_fixpt_M_local_0[37], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_265 = W[3];
end
else begin
mac_fixpt_t_265 = 14'b00000000000000;
end
mac_fixpt_add_cast_786 = {1'b0, mac_fixpt_t_265};
mac_fixpt_add_cast_787 = {1'b0, mac_fixpt_add_cast_786};
mac_fixpt_add_temp_261 = mac_fixpt_add_cast_785 + mac_fixpt_add_cast_787;
mac_fixpt_M_local_0[37] = mac_fixpt_add_temp_261[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_809 = {1'b0, {mac_fixpt_M_local_0[37], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_273 = W[4];
end
else begin
mac_fixpt_t_273 = 14'b00000000000000;
end
mac_fixpt_add_cast_810 = {1'b0, mac_fixpt_t_273};
mac_fixpt_add_cast_811 = {1'b0, mac_fixpt_add_cast_810};
mac_fixpt_add_temp_269 = mac_fixpt_add_cast_809 + mac_fixpt_add_cast_811;
mac_fixpt_M_local_0[37] = mac_fixpt_add_temp_269[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_833 = {1'b0, {mac_fixpt_M_local_0[37], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_281 = W[5];
end
else begin
mac_fixpt_t_281 = 14'b00000000000000;
end
mac_fixpt_add_cast_834 = {1'b0, mac_fixpt_t_281};
mac_fixpt_add_cast_835 = {1'b0, mac_fixpt_add_cast_834};
mac_fixpt_add_temp_277 = mac_fixpt_add_cast_833 + mac_fixpt_add_cast_835;
mac_fixpt_M_local_0[37] = mac_fixpt_add_temp_277[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_857 = {1'b0, {mac_fixpt_M_local_0[37], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_289 = W[6];
end
else begin
mac_fixpt_t_289 = 14'b00000000000000;
end
mac_fixpt_add_cast_858 = {1'b0, mac_fixpt_t_289};
mac_fixpt_add_cast_859 = {1'b0, mac_fixpt_add_cast_858};
mac_fixpt_add_temp_285 = mac_fixpt_add_cast_857 + mac_fixpt_add_cast_859;
mac_fixpt_M_local_0[37] = mac_fixpt_add_temp_285[14:1];
end
end
if (7'b0100111 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_734 = {1'b0, {mac_fixpt_M_local_0[38], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_248 = W[0];
end
else begin
mac_fixpt_t_248 = 14'b00000000000000;
end
mac_fixpt_add_cast_735 = {1'b0, mac_fixpt_t_248};
mac_fixpt_add_cast_736 = {1'b0, mac_fixpt_add_cast_735};
mac_fixpt_add_temp_244 = mac_fixpt_add_cast_734 + mac_fixpt_add_cast_736;
mac_fixpt_M_local_0[38] = mac_fixpt_add_temp_244[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_758 = {1'b0, {mac_fixpt_M_local_0[38], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_256 = W[1];
end
else begin
mac_fixpt_t_256 = 14'b00000000000000;
end
mac_fixpt_add_cast_759 = {1'b0, mac_fixpt_t_256};
mac_fixpt_add_cast_760 = {1'b0, mac_fixpt_add_cast_759};
mac_fixpt_add_temp_252 = mac_fixpt_add_cast_758 + mac_fixpt_add_cast_760;
mac_fixpt_M_local_0[38] = mac_fixpt_add_temp_252[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_782 = {1'b0, {mac_fixpt_M_local_0[38], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_264 = W[2];
end
else begin
mac_fixpt_t_264 = 14'b00000000000000;
end
mac_fixpt_add_cast_783 = {1'b0, mac_fixpt_t_264};
mac_fixpt_add_cast_784 = {1'b0, mac_fixpt_add_cast_783};
mac_fixpt_add_temp_260 = mac_fixpt_add_cast_782 + mac_fixpt_add_cast_784;
mac_fixpt_M_local_0[38] = mac_fixpt_add_temp_260[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_806 = {1'b0, {mac_fixpt_M_local_0[38], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_272 = W[3];
end
else begin
mac_fixpt_t_272 = 14'b00000000000000;
end
mac_fixpt_add_cast_807 = {1'b0, mac_fixpt_t_272};
mac_fixpt_add_cast_808 = {1'b0, mac_fixpt_add_cast_807};
mac_fixpt_add_temp_268 = mac_fixpt_add_cast_806 + mac_fixpt_add_cast_808;
mac_fixpt_M_local_0[38] = mac_fixpt_add_temp_268[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_830 = {1'b0, {mac_fixpt_M_local_0[38], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_280 = W[4];
end
else begin
mac_fixpt_t_280 = 14'b00000000000000;
end
mac_fixpt_add_cast_831 = {1'b0, mac_fixpt_t_280};
mac_fixpt_add_cast_832 = {1'b0, mac_fixpt_add_cast_831};
mac_fixpt_add_temp_276 = mac_fixpt_add_cast_830 + mac_fixpt_add_cast_832;
mac_fixpt_M_local_0[38] = mac_fixpt_add_temp_276[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_854 = {1'b0, {mac_fixpt_M_local_0[38], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_288 = W[5];
end
else begin
mac_fixpt_t_288 = 14'b00000000000000;
end
mac_fixpt_add_cast_855 = {1'b0, mac_fixpt_t_288};
mac_fixpt_add_cast_856 = {1'b0, mac_fixpt_add_cast_855};
mac_fixpt_add_temp_284 = mac_fixpt_add_cast_854 + mac_fixpt_add_cast_856;
mac_fixpt_M_local_0[38] = mac_fixpt_add_temp_284[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_878 = {1'b0, {mac_fixpt_M_local_0[38], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_296 = W[6];
end
else begin
mac_fixpt_t_296 = 14'b00000000000000;
end
mac_fixpt_add_cast_879 = {1'b0, mac_fixpt_t_296};
mac_fixpt_add_cast_880 = {1'b0, mac_fixpt_add_cast_879};
mac_fixpt_add_temp_292 = mac_fixpt_add_cast_878 + mac_fixpt_add_cast_880;
mac_fixpt_M_local_0[38] = mac_fixpt_add_temp_292[14:1];
end
end
if (7'b0101000 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_755 = {1'b0, {mac_fixpt_M_local_0[39], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_255 = W[0];
end
else begin
mac_fixpt_t_255 = 14'b00000000000000;
end
mac_fixpt_add_cast_756 = {1'b0, mac_fixpt_t_255};
mac_fixpt_add_cast_757 = {1'b0, mac_fixpt_add_cast_756};
mac_fixpt_add_temp_251 = mac_fixpt_add_cast_755 + mac_fixpt_add_cast_757;
mac_fixpt_M_local_0[39] = mac_fixpt_add_temp_251[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_779 = {1'b0, {mac_fixpt_M_local_0[39], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_263 = W[1];
end
else begin
mac_fixpt_t_263 = 14'b00000000000000;
end
mac_fixpt_add_cast_780 = {1'b0, mac_fixpt_t_263};
mac_fixpt_add_cast_781 = {1'b0, mac_fixpt_add_cast_780};
mac_fixpt_add_temp_259 = mac_fixpt_add_cast_779 + mac_fixpt_add_cast_781;
mac_fixpt_M_local_0[39] = mac_fixpt_add_temp_259[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_803 = {1'b0, {mac_fixpt_M_local_0[39], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_271 = W[2];
end
else begin
mac_fixpt_t_271 = 14'b00000000000000;
end
mac_fixpt_add_cast_804 = {1'b0, mac_fixpt_t_271};
mac_fixpt_add_cast_805 = {1'b0, mac_fixpt_add_cast_804};
mac_fixpt_add_temp_267 = mac_fixpt_add_cast_803 + mac_fixpt_add_cast_805;
mac_fixpt_M_local_0[39] = mac_fixpt_add_temp_267[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_827 = {1'b0, {mac_fixpt_M_local_0[39], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_279 = W[3];
end
else begin
mac_fixpt_t_279 = 14'b00000000000000;
end
mac_fixpt_add_cast_828 = {1'b0, mac_fixpt_t_279};
mac_fixpt_add_cast_829 = {1'b0, mac_fixpt_add_cast_828};
mac_fixpt_add_temp_275 = mac_fixpt_add_cast_827 + mac_fixpt_add_cast_829;
mac_fixpt_M_local_0[39] = mac_fixpt_add_temp_275[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_851 = {1'b0, {mac_fixpt_M_local_0[39], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_287 = W[4];
end
else begin
mac_fixpt_t_287 = 14'b00000000000000;
end
mac_fixpt_add_cast_852 = {1'b0, mac_fixpt_t_287};
mac_fixpt_add_cast_853 = {1'b0, mac_fixpt_add_cast_852};
mac_fixpt_add_temp_283 = mac_fixpt_add_cast_851 + mac_fixpt_add_cast_853;
mac_fixpt_M_local_0[39] = mac_fixpt_add_temp_283[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_875 = {1'b0, {mac_fixpt_M_local_0[39], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_295 = W[5];
end
else begin
mac_fixpt_t_295 = 14'b00000000000000;
end
mac_fixpt_add_cast_876 = {1'b0, mac_fixpt_t_295};
mac_fixpt_add_cast_877 = {1'b0, mac_fixpt_add_cast_876};
mac_fixpt_add_temp_291 = mac_fixpt_add_cast_875 + mac_fixpt_add_cast_877;
mac_fixpt_M_local_0[39] = mac_fixpt_add_temp_291[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_899 = {1'b0, {mac_fixpt_M_local_0[39], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_303 = W[6];
end
else begin
mac_fixpt_t_303 = 14'b00000000000000;
end
mac_fixpt_add_cast_900 = {1'b0, mac_fixpt_t_303};
mac_fixpt_add_cast_901 = {1'b0, mac_fixpt_add_cast_900};
mac_fixpt_add_temp_299 = mac_fixpt_add_cast_899 + mac_fixpt_add_cast_901;
mac_fixpt_M_local_0[39] = mac_fixpt_add_temp_299[14:1];
end
end
if (7'b0101001 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_776 = {1'b0, {mac_fixpt_M_local_0[40], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_262 = W[0];
end
else begin
mac_fixpt_t_262 = 14'b00000000000000;
end
mac_fixpt_add_cast_777 = {1'b0, mac_fixpt_t_262};
mac_fixpt_add_cast_778 = {1'b0, mac_fixpt_add_cast_777};
mac_fixpt_add_temp_258 = mac_fixpt_add_cast_776 + mac_fixpt_add_cast_778;
mac_fixpt_M_local_0[40] = mac_fixpt_add_temp_258[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_800 = {1'b0, {mac_fixpt_M_local_0[40], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_270 = W[1];
end
else begin
mac_fixpt_t_270 = 14'b00000000000000;
end
mac_fixpt_add_cast_801 = {1'b0, mac_fixpt_t_270};
mac_fixpt_add_cast_802 = {1'b0, mac_fixpt_add_cast_801};
mac_fixpt_add_temp_266 = mac_fixpt_add_cast_800 + mac_fixpt_add_cast_802;
mac_fixpt_M_local_0[40] = mac_fixpt_add_temp_266[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_824 = {1'b0, {mac_fixpt_M_local_0[40], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_278 = W[2];
end
else begin
mac_fixpt_t_278 = 14'b00000000000000;
end
mac_fixpt_add_cast_825 = {1'b0, mac_fixpt_t_278};
mac_fixpt_add_cast_826 = {1'b0, mac_fixpt_add_cast_825};
mac_fixpt_add_temp_274 = mac_fixpt_add_cast_824 + mac_fixpt_add_cast_826;
mac_fixpt_M_local_0[40] = mac_fixpt_add_temp_274[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_848 = {1'b0, {mac_fixpt_M_local_0[40], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_286 = W[3];
end
else begin
mac_fixpt_t_286 = 14'b00000000000000;
end
mac_fixpt_add_cast_849 = {1'b0, mac_fixpt_t_286};
mac_fixpt_add_cast_850 = {1'b0, mac_fixpt_add_cast_849};
mac_fixpt_add_temp_282 = mac_fixpt_add_cast_848 + mac_fixpt_add_cast_850;
mac_fixpt_M_local_0[40] = mac_fixpt_add_temp_282[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_872 = {1'b0, {mac_fixpt_M_local_0[40], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_294 = W[4];
end
else begin
mac_fixpt_t_294 = 14'b00000000000000;
end
mac_fixpt_add_cast_873 = {1'b0, mac_fixpt_t_294};
mac_fixpt_add_cast_874 = {1'b0, mac_fixpt_add_cast_873};
mac_fixpt_add_temp_290 = mac_fixpt_add_cast_872 + mac_fixpt_add_cast_874;
mac_fixpt_M_local_0[40] = mac_fixpt_add_temp_290[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_896 = {1'b0, {mac_fixpt_M_local_0[40], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_302 = W[5];
end
else begin
mac_fixpt_t_302 = 14'b00000000000000;
end
mac_fixpt_add_cast_897 = {1'b0, mac_fixpt_t_302};
mac_fixpt_add_cast_898 = {1'b0, mac_fixpt_add_cast_897};
mac_fixpt_add_temp_298 = mac_fixpt_add_cast_896 + mac_fixpt_add_cast_898;
mac_fixpt_M_local_0[40] = mac_fixpt_add_temp_298[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_920 = {1'b0, {mac_fixpt_M_local_0[40], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_310 = W[6];
end
else begin
mac_fixpt_t_310 = 14'b00000000000000;
end
mac_fixpt_add_cast_921 = {1'b0, mac_fixpt_t_310};
mac_fixpt_add_cast_922 = {1'b0, mac_fixpt_add_cast_921};
mac_fixpt_add_temp_306 = mac_fixpt_add_cast_920 + mac_fixpt_add_cast_922;
mac_fixpt_M_local_0[40] = mac_fixpt_add_temp_306[14:1];
end
end
if (7'b0101010 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_797 = {1'b0, {mac_fixpt_M_local_0[41], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_269 = W[0];
end
else begin
mac_fixpt_t_269 = 14'b00000000000000;
end
mac_fixpt_add_cast_798 = {1'b0, mac_fixpt_t_269};
mac_fixpt_add_cast_799 = {1'b0, mac_fixpt_add_cast_798};
mac_fixpt_add_temp_265 = mac_fixpt_add_cast_797 + mac_fixpt_add_cast_799;
mac_fixpt_M_local_0[41] = mac_fixpt_add_temp_265[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_821 = {1'b0, {mac_fixpt_M_local_0[41], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_277 = W[1];
end
else begin
mac_fixpt_t_277 = 14'b00000000000000;
end
mac_fixpt_add_cast_822 = {1'b0, mac_fixpt_t_277};
mac_fixpt_add_cast_823 = {1'b0, mac_fixpt_add_cast_822};
mac_fixpt_add_temp_273 = mac_fixpt_add_cast_821 + mac_fixpt_add_cast_823;
mac_fixpt_M_local_0[41] = mac_fixpt_add_temp_273[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_845 = {1'b0, {mac_fixpt_M_local_0[41], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_285 = W[2];
end
else begin
mac_fixpt_t_285 = 14'b00000000000000;
end
mac_fixpt_add_cast_846 = {1'b0, mac_fixpt_t_285};
mac_fixpt_add_cast_847 = {1'b0, mac_fixpt_add_cast_846};
mac_fixpt_add_temp_281 = mac_fixpt_add_cast_845 + mac_fixpt_add_cast_847;
mac_fixpt_M_local_0[41] = mac_fixpt_add_temp_281[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_869 = {1'b0, {mac_fixpt_M_local_0[41], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_293 = W[3];
end
else begin
mac_fixpt_t_293 = 14'b00000000000000;
end
mac_fixpt_add_cast_870 = {1'b0, mac_fixpt_t_293};
mac_fixpt_add_cast_871 = {1'b0, mac_fixpt_add_cast_870};
mac_fixpt_add_temp_289 = mac_fixpt_add_cast_869 + mac_fixpt_add_cast_871;
mac_fixpt_M_local_0[41] = mac_fixpt_add_temp_289[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_893 = {1'b0, {mac_fixpt_M_local_0[41], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_301 = W[4];
end
else begin
mac_fixpt_t_301 = 14'b00000000000000;
end
mac_fixpt_add_cast_894 = {1'b0, mac_fixpt_t_301};
mac_fixpt_add_cast_895 = {1'b0, mac_fixpt_add_cast_894};
mac_fixpt_add_temp_297 = mac_fixpt_add_cast_893 + mac_fixpt_add_cast_895;
mac_fixpt_M_local_0[41] = mac_fixpt_add_temp_297[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_917 = {1'b0, {mac_fixpt_M_local_0[41], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_309 = W[5];
end
else begin
mac_fixpt_t_309 = 14'b00000000000000;
end
mac_fixpt_add_cast_918 = {1'b0, mac_fixpt_t_309};
mac_fixpt_add_cast_919 = {1'b0, mac_fixpt_add_cast_918};
mac_fixpt_add_temp_305 = mac_fixpt_add_cast_917 + mac_fixpt_add_cast_919;
mac_fixpt_M_local_0[41] = mac_fixpt_add_temp_305[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_941 = {1'b0, {mac_fixpt_M_local_0[41], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_317 = W[6];
end
else begin
mac_fixpt_t_317 = 14'b00000000000000;
end
mac_fixpt_add_cast_942 = {1'b0, mac_fixpt_t_317};
mac_fixpt_add_cast_943 = {1'b0, mac_fixpt_add_cast_942};
mac_fixpt_add_temp_313 = mac_fixpt_add_cast_941 + mac_fixpt_add_cast_943;
mac_fixpt_M_local_0[41] = mac_fixpt_add_temp_313[14:1];
end
end
if (7'b0101011 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_818 = {1'b0, {mac_fixpt_M_local_0[42], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_276 = W[0];
end
else begin
mac_fixpt_t_276 = 14'b00000000000000;
end
mac_fixpt_add_cast_819 = {1'b0, mac_fixpt_t_276};
mac_fixpt_add_cast_820 = {1'b0, mac_fixpt_add_cast_819};
mac_fixpt_add_temp_272 = mac_fixpt_add_cast_818 + mac_fixpt_add_cast_820;
mac_fixpt_M_local_0[42] = mac_fixpt_add_temp_272[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_842 = {1'b0, {mac_fixpt_M_local_0[42], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_284 = W[1];
end
else begin
mac_fixpt_t_284 = 14'b00000000000000;
end
mac_fixpt_add_cast_843 = {1'b0, mac_fixpt_t_284};
mac_fixpt_add_cast_844 = {1'b0, mac_fixpt_add_cast_843};
mac_fixpt_add_temp_280 = mac_fixpt_add_cast_842 + mac_fixpt_add_cast_844;
mac_fixpt_M_local_0[42] = mac_fixpt_add_temp_280[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_866 = {1'b0, {mac_fixpt_M_local_0[42], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_292 = W[2];
end
else begin
mac_fixpt_t_292 = 14'b00000000000000;
end
mac_fixpt_add_cast_867 = {1'b0, mac_fixpt_t_292};
mac_fixpt_add_cast_868 = {1'b0, mac_fixpt_add_cast_867};
mac_fixpt_add_temp_288 = mac_fixpt_add_cast_866 + mac_fixpt_add_cast_868;
mac_fixpt_M_local_0[42] = mac_fixpt_add_temp_288[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_890 = {1'b0, {mac_fixpt_M_local_0[42], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_300 = W[3];
end
else begin
mac_fixpt_t_300 = 14'b00000000000000;
end
mac_fixpt_add_cast_891 = {1'b0, mac_fixpt_t_300};
mac_fixpt_add_cast_892 = {1'b0, mac_fixpt_add_cast_891};
mac_fixpt_add_temp_296 = mac_fixpt_add_cast_890 + mac_fixpt_add_cast_892;
mac_fixpt_M_local_0[42] = mac_fixpt_add_temp_296[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_914 = {1'b0, {mac_fixpt_M_local_0[42], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_308 = W[4];
end
else begin
mac_fixpt_t_308 = 14'b00000000000000;
end
mac_fixpt_add_cast_915 = {1'b0, mac_fixpt_t_308};
mac_fixpt_add_cast_916 = {1'b0, mac_fixpt_add_cast_915};
mac_fixpt_add_temp_304 = mac_fixpt_add_cast_914 + mac_fixpt_add_cast_916;
mac_fixpt_M_local_0[42] = mac_fixpt_add_temp_304[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_938 = {1'b0, {mac_fixpt_M_local_0[42], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_316 = W[5];
end
else begin
mac_fixpt_t_316 = 14'b00000000000000;
end
mac_fixpt_add_cast_939 = {1'b0, mac_fixpt_t_316};
mac_fixpt_add_cast_940 = {1'b0, mac_fixpt_add_cast_939};
mac_fixpt_add_temp_312 = mac_fixpt_add_cast_938 + mac_fixpt_add_cast_940;
mac_fixpt_M_local_0[42] = mac_fixpt_add_temp_312[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_962 = {1'b0, {mac_fixpt_M_local_0[42], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_324 = W[6];
end
else begin
mac_fixpt_t_324 = 14'b00000000000000;
end
mac_fixpt_add_cast_963 = {1'b0, mac_fixpt_t_324};
mac_fixpt_add_cast_964 = {1'b0, mac_fixpt_add_cast_963};
mac_fixpt_add_temp_320 = mac_fixpt_add_cast_962 + mac_fixpt_add_cast_964;
mac_fixpt_M_local_0[42] = mac_fixpt_add_temp_320[14:1];
end
end
if (7'b0101100 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_839 = {1'b0, {mac_fixpt_M_local_0[43], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_283 = W[0];
end
else begin
mac_fixpt_t_283 = 14'b00000000000000;
end
mac_fixpt_add_cast_840 = {1'b0, mac_fixpt_t_283};
mac_fixpt_add_cast_841 = {1'b0, mac_fixpt_add_cast_840};
mac_fixpt_add_temp_279 = mac_fixpt_add_cast_839 + mac_fixpt_add_cast_841;
mac_fixpt_M_local_0[43] = mac_fixpt_add_temp_279[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_863 = {1'b0, {mac_fixpt_M_local_0[43], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_291 = W[1];
end
else begin
mac_fixpt_t_291 = 14'b00000000000000;
end
mac_fixpt_add_cast_864 = {1'b0, mac_fixpt_t_291};
mac_fixpt_add_cast_865 = {1'b0, mac_fixpt_add_cast_864};
mac_fixpt_add_temp_287 = mac_fixpt_add_cast_863 + mac_fixpt_add_cast_865;
mac_fixpt_M_local_0[43] = mac_fixpt_add_temp_287[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_887 = {1'b0, {mac_fixpt_M_local_0[43], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_299 = W[2];
end
else begin
mac_fixpt_t_299 = 14'b00000000000000;
end
mac_fixpt_add_cast_888 = {1'b0, mac_fixpt_t_299};
mac_fixpt_add_cast_889 = {1'b0, mac_fixpt_add_cast_888};
mac_fixpt_add_temp_295 = mac_fixpt_add_cast_887 + mac_fixpt_add_cast_889;
mac_fixpt_M_local_0[43] = mac_fixpt_add_temp_295[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_911 = {1'b0, {mac_fixpt_M_local_0[43], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_307 = W[3];
end
else begin
mac_fixpt_t_307 = 14'b00000000000000;
end
mac_fixpt_add_cast_912 = {1'b0, mac_fixpt_t_307};
mac_fixpt_add_cast_913 = {1'b0, mac_fixpt_add_cast_912};
mac_fixpt_add_temp_303 = mac_fixpt_add_cast_911 + mac_fixpt_add_cast_913;
mac_fixpt_M_local_0[43] = mac_fixpt_add_temp_303[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_935 = {1'b0, {mac_fixpt_M_local_0[43], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_315 = W[4];
end
else begin
mac_fixpt_t_315 = 14'b00000000000000;
end
mac_fixpt_add_cast_936 = {1'b0, mac_fixpt_t_315};
mac_fixpt_add_cast_937 = {1'b0, mac_fixpt_add_cast_936};
mac_fixpt_add_temp_311 = mac_fixpt_add_cast_935 + mac_fixpt_add_cast_937;
mac_fixpt_M_local_0[43] = mac_fixpt_add_temp_311[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_959 = {1'b0, {mac_fixpt_M_local_0[43], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_323 = W[5];
end
else begin
mac_fixpt_t_323 = 14'b00000000000000;
end
mac_fixpt_add_cast_960 = {1'b0, mac_fixpt_t_323};
mac_fixpt_add_cast_961 = {1'b0, mac_fixpt_add_cast_960};
mac_fixpt_add_temp_319 = mac_fixpt_add_cast_959 + mac_fixpt_add_cast_961;
mac_fixpt_M_local_0[43] = mac_fixpt_add_temp_319[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_983 = {1'b0, {mac_fixpt_M_local_0[43], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_331 = W[6];
end
else begin
mac_fixpt_t_331 = 14'b00000000000000;
end
mac_fixpt_add_cast_984 = {1'b0, mac_fixpt_t_331};
mac_fixpt_add_cast_985 = {1'b0, mac_fixpt_add_cast_984};
mac_fixpt_add_temp_327 = mac_fixpt_add_cast_983 + mac_fixpt_add_cast_985;
mac_fixpt_M_local_0[43] = mac_fixpt_add_temp_327[14:1];
end
end
if (7'b0101101 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_860 = {1'b0, {mac_fixpt_M_local_0[44], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_290 = W[0];
end
else begin
mac_fixpt_t_290 = 14'b00000000000000;
end
mac_fixpt_add_cast_861 = {1'b0, mac_fixpt_t_290};
mac_fixpt_add_cast_862 = {1'b0, mac_fixpt_add_cast_861};
mac_fixpt_add_temp_286 = mac_fixpt_add_cast_860 + mac_fixpt_add_cast_862;
mac_fixpt_M_local_0[44] = mac_fixpt_add_temp_286[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_884 = {1'b0, {mac_fixpt_M_local_0[44], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_298 = W[1];
end
else begin
mac_fixpt_t_298 = 14'b00000000000000;
end
mac_fixpt_add_cast_885 = {1'b0, mac_fixpt_t_298};
mac_fixpt_add_cast_886 = {1'b0, mac_fixpt_add_cast_885};
mac_fixpt_add_temp_294 = mac_fixpt_add_cast_884 + mac_fixpt_add_cast_886;
mac_fixpt_M_local_0[44] = mac_fixpt_add_temp_294[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_908 = {1'b0, {mac_fixpt_M_local_0[44], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_306 = W[2];
end
else begin
mac_fixpt_t_306 = 14'b00000000000000;
end
mac_fixpt_add_cast_909 = {1'b0, mac_fixpt_t_306};
mac_fixpt_add_cast_910 = {1'b0, mac_fixpt_add_cast_909};
mac_fixpt_add_temp_302 = mac_fixpt_add_cast_908 + mac_fixpt_add_cast_910;
mac_fixpt_M_local_0[44] = mac_fixpt_add_temp_302[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_932 = {1'b0, {mac_fixpt_M_local_0[44], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_314 = W[3];
end
else begin
mac_fixpt_t_314 = 14'b00000000000000;
end
mac_fixpt_add_cast_933 = {1'b0, mac_fixpt_t_314};
mac_fixpt_add_cast_934 = {1'b0, mac_fixpt_add_cast_933};
mac_fixpt_add_temp_310 = mac_fixpt_add_cast_932 + mac_fixpt_add_cast_934;
mac_fixpt_M_local_0[44] = mac_fixpt_add_temp_310[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_956 = {1'b0, {mac_fixpt_M_local_0[44], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_322 = W[4];
end
else begin
mac_fixpt_t_322 = 14'b00000000000000;
end
mac_fixpt_add_cast_957 = {1'b0, mac_fixpt_t_322};
mac_fixpt_add_cast_958 = {1'b0, mac_fixpt_add_cast_957};
mac_fixpt_add_temp_318 = mac_fixpt_add_cast_956 + mac_fixpt_add_cast_958;
mac_fixpt_M_local_0[44] = mac_fixpt_add_temp_318[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_980 = {1'b0, {mac_fixpt_M_local_0[44], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_330 = W[5];
end
else begin
mac_fixpt_t_330 = 14'b00000000000000;
end
mac_fixpt_add_cast_981 = {1'b0, mac_fixpt_t_330};
mac_fixpt_add_cast_982 = {1'b0, mac_fixpt_add_cast_981};
mac_fixpt_add_temp_326 = mac_fixpt_add_cast_980 + mac_fixpt_add_cast_982;
mac_fixpt_M_local_0[44] = mac_fixpt_add_temp_326[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_1004 = {1'b0, {mac_fixpt_M_local_0[44], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_338 = W[6];
end
else begin
mac_fixpt_t_338 = 14'b00000000000000;
end
mac_fixpt_add_cast_1005 = {1'b0, mac_fixpt_t_338};
mac_fixpt_add_cast_1006 = {1'b0, mac_fixpt_add_cast_1005};
mac_fixpt_add_temp_334 = mac_fixpt_add_cast_1004 + mac_fixpt_add_cast_1006;
mac_fixpt_M_local_0[44] = mac_fixpt_add_temp_334[14:1];
end
end
if (7'b0101110 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_881 = {1'b0, {mac_fixpt_M_local_0[45], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_297 = W[0];
end
else begin
mac_fixpt_t_297 = 14'b00000000000000;
end
mac_fixpt_add_cast_882 = {1'b0, mac_fixpt_t_297};
mac_fixpt_add_cast_883 = {1'b0, mac_fixpt_add_cast_882};
mac_fixpt_add_temp_293 = mac_fixpt_add_cast_881 + mac_fixpt_add_cast_883;
mac_fixpt_M_local_0[45] = mac_fixpt_add_temp_293[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_905 = {1'b0, {mac_fixpt_M_local_0[45], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_305 = W[1];
end
else begin
mac_fixpt_t_305 = 14'b00000000000000;
end
mac_fixpt_add_cast_906 = {1'b0, mac_fixpt_t_305};
mac_fixpt_add_cast_907 = {1'b0, mac_fixpt_add_cast_906};
mac_fixpt_add_temp_301 = mac_fixpt_add_cast_905 + mac_fixpt_add_cast_907;
mac_fixpt_M_local_0[45] = mac_fixpt_add_temp_301[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_929 = {1'b0, {mac_fixpt_M_local_0[45], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_313 = W[2];
end
else begin
mac_fixpt_t_313 = 14'b00000000000000;
end
mac_fixpt_add_cast_930 = {1'b0, mac_fixpt_t_313};
mac_fixpt_add_cast_931 = {1'b0, mac_fixpt_add_cast_930};
mac_fixpt_add_temp_309 = mac_fixpt_add_cast_929 + mac_fixpt_add_cast_931;
mac_fixpt_M_local_0[45] = mac_fixpt_add_temp_309[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_953 = {1'b0, {mac_fixpt_M_local_0[45], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_321 = W[3];
end
else begin
mac_fixpt_t_321 = 14'b00000000000000;
end
mac_fixpt_add_cast_954 = {1'b0, mac_fixpt_t_321};
mac_fixpt_add_cast_955 = {1'b0, mac_fixpt_add_cast_954};
mac_fixpt_add_temp_317 = mac_fixpt_add_cast_953 + mac_fixpt_add_cast_955;
mac_fixpt_M_local_0[45] = mac_fixpt_add_temp_317[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_977 = {1'b0, {mac_fixpt_M_local_0[45], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_329 = W[4];
end
else begin
mac_fixpt_t_329 = 14'b00000000000000;
end
mac_fixpt_add_cast_978 = {1'b0, mac_fixpt_t_329};
mac_fixpt_add_cast_979 = {1'b0, mac_fixpt_add_cast_978};
mac_fixpt_add_temp_325 = mac_fixpt_add_cast_977 + mac_fixpt_add_cast_979;
mac_fixpt_M_local_0[45] = mac_fixpt_add_temp_325[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_1001 = {1'b0, {mac_fixpt_M_local_0[45], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_337 = W[5];
end
else begin
mac_fixpt_t_337 = 14'b00000000000000;
end
mac_fixpt_add_cast_1002 = {1'b0, mac_fixpt_t_337};
mac_fixpt_add_cast_1003 = {1'b0, mac_fixpt_add_cast_1002};
mac_fixpt_add_temp_333 = mac_fixpt_add_cast_1001 + mac_fixpt_add_cast_1003;
mac_fixpt_M_local_0[45] = mac_fixpt_add_temp_333[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_1025 = {1'b0, {mac_fixpt_M_local_0[45], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_345 = W[6];
end
else begin
mac_fixpt_t_345 = 14'b00000000000000;
end
mac_fixpt_add_cast_1026 = {1'b0, mac_fixpt_t_345};
mac_fixpt_add_cast_1027 = {1'b0, mac_fixpt_add_cast_1026};
mac_fixpt_add_temp_341 = mac_fixpt_add_cast_1025 + mac_fixpt_add_cast_1027;
mac_fixpt_M_local_0[45] = mac_fixpt_add_temp_341[14:1];
end
end
if (7'b0101111 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_902 = {1'b0, {mac_fixpt_M_local_0[46], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_304 = W[0];
end
else begin
mac_fixpt_t_304 = 14'b00000000000000;
end
mac_fixpt_add_cast_903 = {1'b0, mac_fixpt_t_304};
mac_fixpt_add_cast_904 = {1'b0, mac_fixpt_add_cast_903};
mac_fixpt_add_temp_300 = mac_fixpt_add_cast_902 + mac_fixpt_add_cast_904;
mac_fixpt_M_local_0[46] = mac_fixpt_add_temp_300[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_926 = {1'b0, {mac_fixpt_M_local_0[46], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_312 = W[1];
end
else begin
mac_fixpt_t_312 = 14'b00000000000000;
end
mac_fixpt_add_cast_927 = {1'b0, mac_fixpt_t_312};
mac_fixpt_add_cast_928 = {1'b0, mac_fixpt_add_cast_927};
mac_fixpt_add_temp_308 = mac_fixpt_add_cast_926 + mac_fixpt_add_cast_928;
mac_fixpt_M_local_0[46] = mac_fixpt_add_temp_308[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_950 = {1'b0, {mac_fixpt_M_local_0[46], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_320 = W[2];
end
else begin
mac_fixpt_t_320 = 14'b00000000000000;
end
mac_fixpt_add_cast_951 = {1'b0, mac_fixpt_t_320};
mac_fixpt_add_cast_952 = {1'b0, mac_fixpt_add_cast_951};
mac_fixpt_add_temp_316 = mac_fixpt_add_cast_950 + mac_fixpt_add_cast_952;
mac_fixpt_M_local_0[46] = mac_fixpt_add_temp_316[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_974 = {1'b0, {mac_fixpt_M_local_0[46], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_328 = W[3];
end
else begin
mac_fixpt_t_328 = 14'b00000000000000;
end
mac_fixpt_add_cast_975 = {1'b0, mac_fixpt_t_328};
mac_fixpt_add_cast_976 = {1'b0, mac_fixpt_add_cast_975};
mac_fixpt_add_temp_324 = mac_fixpt_add_cast_974 + mac_fixpt_add_cast_976;
mac_fixpt_M_local_0[46] = mac_fixpt_add_temp_324[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_998 = {1'b0, {mac_fixpt_M_local_0[46], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_336 = W[4];
end
else begin
mac_fixpt_t_336 = 14'b00000000000000;
end
mac_fixpt_add_cast_999 = {1'b0, mac_fixpt_t_336};
mac_fixpt_add_cast_1000 = {1'b0, mac_fixpt_add_cast_999};
mac_fixpt_add_temp_332 = mac_fixpt_add_cast_998 + mac_fixpt_add_cast_1000;
mac_fixpt_M_local_0[46] = mac_fixpt_add_temp_332[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_1022 = {1'b0, {mac_fixpt_M_local_0[46], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_344 = W[5];
end
else begin
mac_fixpt_t_344 = 14'b00000000000000;
end
mac_fixpt_add_cast_1023 = {1'b0, mac_fixpt_t_344};
mac_fixpt_add_cast_1024 = {1'b0, mac_fixpt_add_cast_1023};
mac_fixpt_add_temp_340 = mac_fixpt_add_cast_1022 + mac_fixpt_add_cast_1024;
mac_fixpt_M_local_0[46] = mac_fixpt_add_temp_340[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_1046 = {1'b0, {mac_fixpt_M_local_0[46], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_352 = W[6];
end
else begin
mac_fixpt_t_352 = 14'b00000000000000;
end
mac_fixpt_add_cast_1047 = {1'b0, mac_fixpt_t_352};
mac_fixpt_add_cast_1048 = {1'b0, mac_fixpt_add_cast_1047};
mac_fixpt_add_temp_348 = mac_fixpt_add_cast_1046 + mac_fixpt_add_cast_1048;
mac_fixpt_M_local_0[46] = mac_fixpt_add_temp_348[14:1];
end
end
if (7'b0110000 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_923 = {1'b0, {mac_fixpt_M_local_0[47], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_311 = W[0];
end
else begin
mac_fixpt_t_311 = 14'b00000000000000;
end
mac_fixpt_add_cast_924 = {1'b0, mac_fixpt_t_311};
mac_fixpt_add_cast_925 = {1'b0, mac_fixpt_add_cast_924};
mac_fixpt_add_temp_307 = mac_fixpt_add_cast_923 + mac_fixpt_add_cast_925;
mac_fixpt_M_local_0[47] = mac_fixpt_add_temp_307[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_947 = {1'b0, {mac_fixpt_M_local_0[47], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_319 = W[1];
end
else begin
mac_fixpt_t_319 = 14'b00000000000000;
end
mac_fixpt_add_cast_948 = {1'b0, mac_fixpt_t_319};
mac_fixpt_add_cast_949 = {1'b0, mac_fixpt_add_cast_948};
mac_fixpt_add_temp_315 = mac_fixpt_add_cast_947 + mac_fixpt_add_cast_949;
mac_fixpt_M_local_0[47] = mac_fixpt_add_temp_315[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_971 = {1'b0, {mac_fixpt_M_local_0[47], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_327 = W[2];
end
else begin
mac_fixpt_t_327 = 14'b00000000000000;
end
mac_fixpt_add_cast_972 = {1'b0, mac_fixpt_t_327};
mac_fixpt_add_cast_973 = {1'b0, mac_fixpt_add_cast_972};
mac_fixpt_add_temp_323 = mac_fixpt_add_cast_971 + mac_fixpt_add_cast_973;
mac_fixpt_M_local_0[47] = mac_fixpt_add_temp_323[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_995 = {1'b0, {mac_fixpt_M_local_0[47], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_335 = W[3];
end
else begin
mac_fixpt_t_335 = 14'b00000000000000;
end
mac_fixpt_add_cast_996 = {1'b0, mac_fixpt_t_335};
mac_fixpt_add_cast_997 = {1'b0, mac_fixpt_add_cast_996};
mac_fixpt_add_temp_331 = mac_fixpt_add_cast_995 + mac_fixpt_add_cast_997;
mac_fixpt_M_local_0[47] = mac_fixpt_add_temp_331[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_1019 = {1'b0, {mac_fixpt_M_local_0[47], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_343 = W[4];
end
else begin
mac_fixpt_t_343 = 14'b00000000000000;
end
mac_fixpt_add_cast_1020 = {1'b0, mac_fixpt_t_343};
mac_fixpt_add_cast_1021 = {1'b0, mac_fixpt_add_cast_1020};
mac_fixpt_add_temp_339 = mac_fixpt_add_cast_1019 + mac_fixpt_add_cast_1021;
mac_fixpt_M_local_0[47] = mac_fixpt_add_temp_339[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_1043 = {1'b0, {mac_fixpt_M_local_0[47], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_351 = W[5];
end
else begin
mac_fixpt_t_351 = 14'b00000000000000;
end
mac_fixpt_add_cast_1044 = {1'b0, mac_fixpt_t_351};
mac_fixpt_add_cast_1045 = {1'b0, mac_fixpt_add_cast_1044};
mac_fixpt_add_temp_347 = mac_fixpt_add_cast_1043 + mac_fixpt_add_cast_1045;
mac_fixpt_M_local_0[47] = mac_fixpt_add_temp_347[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_1067 = {1'b0, {mac_fixpt_M_local_0[47], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_359 = W[6];
end
else begin
mac_fixpt_t_359 = 14'b00000000000000;
end
mac_fixpt_add_cast_1068 = {1'b0, mac_fixpt_t_359};
mac_fixpt_add_cast_1069 = {1'b0, mac_fixpt_add_cast_1068};
mac_fixpt_add_temp_355 = mac_fixpt_add_cast_1067 + mac_fixpt_add_cast_1069;
mac_fixpt_M_local_0[47] = mac_fixpt_add_temp_355[14:1];
end
end
if (7'b0110001 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_944 = {1'b0, {mac_fixpt_M_local_0[48], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_318 = W[0];
end
else begin
mac_fixpt_t_318 = 14'b00000000000000;
end
mac_fixpt_add_cast_945 = {1'b0, mac_fixpt_t_318};
mac_fixpt_add_cast_946 = {1'b0, mac_fixpt_add_cast_945};
mac_fixpt_add_temp_314 = mac_fixpt_add_cast_944 + mac_fixpt_add_cast_946;
mac_fixpt_M_local_0[48] = mac_fixpt_add_temp_314[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_968 = {1'b0, {mac_fixpt_M_local_0[48], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_326 = W[1];
end
else begin
mac_fixpt_t_326 = 14'b00000000000000;
end
mac_fixpt_add_cast_969 = {1'b0, mac_fixpt_t_326};
mac_fixpt_add_cast_970 = {1'b0, mac_fixpt_add_cast_969};
mac_fixpt_add_temp_322 = mac_fixpt_add_cast_968 + mac_fixpt_add_cast_970;
mac_fixpt_M_local_0[48] = mac_fixpt_add_temp_322[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_992 = {1'b0, {mac_fixpt_M_local_0[48], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_334 = W[2];
end
else begin
mac_fixpt_t_334 = 14'b00000000000000;
end
mac_fixpt_add_cast_993 = {1'b0, mac_fixpt_t_334};
mac_fixpt_add_cast_994 = {1'b0, mac_fixpt_add_cast_993};
mac_fixpt_add_temp_330 = mac_fixpt_add_cast_992 + mac_fixpt_add_cast_994;
mac_fixpt_M_local_0[48] = mac_fixpt_add_temp_330[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_1016 = {1'b0, {mac_fixpt_M_local_0[48], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_342 = W[3];
end
else begin
mac_fixpt_t_342 = 14'b00000000000000;
end
mac_fixpt_add_cast_1017 = {1'b0, mac_fixpt_t_342};
mac_fixpt_add_cast_1018 = {1'b0, mac_fixpt_add_cast_1017};
mac_fixpt_add_temp_338 = mac_fixpt_add_cast_1016 + mac_fixpt_add_cast_1018;
mac_fixpt_M_local_0[48] = mac_fixpt_add_temp_338[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_1040 = {1'b0, {mac_fixpt_M_local_0[48], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_350 = W[4];
end
else begin
mac_fixpt_t_350 = 14'b00000000000000;
end
mac_fixpt_add_cast_1041 = {1'b0, mac_fixpt_t_350};
mac_fixpt_add_cast_1042 = {1'b0, mac_fixpt_add_cast_1041};
mac_fixpt_add_temp_346 = mac_fixpt_add_cast_1040 + mac_fixpt_add_cast_1042;
mac_fixpt_M_local_0[48] = mac_fixpt_add_temp_346[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_1064 = {1'b0, {mac_fixpt_M_local_0[48], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_358 = W[5];
end
else begin
mac_fixpt_t_358 = 14'b00000000000000;
end
mac_fixpt_add_cast_1065 = {1'b0, mac_fixpt_t_358};
mac_fixpt_add_cast_1066 = {1'b0, mac_fixpt_add_cast_1065};
mac_fixpt_add_temp_354 = mac_fixpt_add_cast_1064 + mac_fixpt_add_cast_1066;
mac_fixpt_M_local_0[48] = mac_fixpt_add_temp_354[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_1088 = {1'b0, {mac_fixpt_M_local_0[48], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_366 = W[6];
end
else begin
mac_fixpt_t_366 = 14'b00000000000000;
end
mac_fixpt_add_cast_1089 = {1'b0, mac_fixpt_t_366};
mac_fixpt_add_cast_1090 = {1'b0, mac_fixpt_add_cast_1089};
mac_fixpt_add_temp_362 = mac_fixpt_add_cast_1088 + mac_fixpt_add_cast_1090;
mac_fixpt_M_local_0[48] = mac_fixpt_add_temp_362[14:1];
end
end
if (7'b0110010 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_965 = {1'b0, {mac_fixpt_M_local_0[49], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_325 = W[0];
end
else begin
mac_fixpt_t_325 = 14'b00000000000000;
end
mac_fixpt_add_cast_966 = {1'b0, mac_fixpt_t_325};
mac_fixpt_add_cast_967 = {1'b0, mac_fixpt_add_cast_966};
mac_fixpt_add_temp_321 = mac_fixpt_add_cast_965 + mac_fixpt_add_cast_967;
mac_fixpt_M_local_0[49] = mac_fixpt_add_temp_321[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_989 = {1'b0, {mac_fixpt_M_local_0[49], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_333 = W[1];
end
else begin
mac_fixpt_t_333 = 14'b00000000000000;
end
mac_fixpt_add_cast_990 = {1'b0, mac_fixpt_t_333};
mac_fixpt_add_cast_991 = {1'b0, mac_fixpt_add_cast_990};
mac_fixpt_add_temp_329 = mac_fixpt_add_cast_989 + mac_fixpt_add_cast_991;
mac_fixpt_M_local_0[49] = mac_fixpt_add_temp_329[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_1013 = {1'b0, {mac_fixpt_M_local_0[49], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_341 = W[2];
end
else begin
mac_fixpt_t_341 = 14'b00000000000000;
end
mac_fixpt_add_cast_1014 = {1'b0, mac_fixpt_t_341};
mac_fixpt_add_cast_1015 = {1'b0, mac_fixpt_add_cast_1014};
mac_fixpt_add_temp_337 = mac_fixpt_add_cast_1013 + mac_fixpt_add_cast_1015;
mac_fixpt_M_local_0[49] = mac_fixpt_add_temp_337[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_1037 = {1'b0, {mac_fixpt_M_local_0[49], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_349 = W[3];
end
else begin
mac_fixpt_t_349 = 14'b00000000000000;
end
mac_fixpt_add_cast_1038 = {1'b0, mac_fixpt_t_349};
mac_fixpt_add_cast_1039 = {1'b0, mac_fixpt_add_cast_1038};
mac_fixpt_add_temp_345 = mac_fixpt_add_cast_1037 + mac_fixpt_add_cast_1039;
mac_fixpt_M_local_0[49] = mac_fixpt_add_temp_345[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_1061 = {1'b0, {mac_fixpt_M_local_0[49], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_357 = W[4];
end
else begin
mac_fixpt_t_357 = 14'b00000000000000;
end
mac_fixpt_add_cast_1062 = {1'b0, mac_fixpt_t_357};
mac_fixpt_add_cast_1063 = {1'b0, mac_fixpt_add_cast_1062};
mac_fixpt_add_temp_353 = mac_fixpt_add_cast_1061 + mac_fixpt_add_cast_1063;
mac_fixpt_M_local_0[49] = mac_fixpt_add_temp_353[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_1085 = {1'b0, {mac_fixpt_M_local_0[49], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_365 = W[5];
end
else begin
mac_fixpt_t_365 = 14'b00000000000000;
end
mac_fixpt_add_cast_1086 = {1'b0, mac_fixpt_t_365};
mac_fixpt_add_cast_1087 = {1'b0, mac_fixpt_add_cast_1086};
mac_fixpt_add_temp_361 = mac_fixpt_add_cast_1085 + mac_fixpt_add_cast_1087;
mac_fixpt_M_local_0[49] = mac_fixpt_add_temp_361[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_1109 = {1'b0, {mac_fixpt_M_local_0[49], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_373 = W[6];
end
else begin
mac_fixpt_t_373 = 14'b00000000000000;
end
mac_fixpt_add_cast_1110 = {1'b0, mac_fixpt_t_373};
mac_fixpt_add_cast_1111 = {1'b0, mac_fixpt_add_cast_1110};
mac_fixpt_add_temp_369 = mac_fixpt_add_cast_1109 + mac_fixpt_add_cast_1111;
mac_fixpt_M_local_0[49] = mac_fixpt_add_temp_369[14:1];
end
end
if (7'b0110011 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_986 = {1'b0, {mac_fixpt_M_local_0[50], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_332 = W[0];
end
else begin
mac_fixpt_t_332 = 14'b00000000000000;
end
mac_fixpt_add_cast_987 = {1'b0, mac_fixpt_t_332};
mac_fixpt_add_cast_988 = {1'b0, mac_fixpt_add_cast_987};
mac_fixpt_add_temp_328 = mac_fixpt_add_cast_986 + mac_fixpt_add_cast_988;
mac_fixpt_M_local_0[50] = mac_fixpt_add_temp_328[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_1010 = {1'b0, {mac_fixpt_M_local_0[50], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_340 = W[1];
end
else begin
mac_fixpt_t_340 = 14'b00000000000000;
end
mac_fixpt_add_cast_1011 = {1'b0, mac_fixpt_t_340};
mac_fixpt_add_cast_1012 = {1'b0, mac_fixpt_add_cast_1011};
mac_fixpt_add_temp_336 = mac_fixpt_add_cast_1010 + mac_fixpt_add_cast_1012;
mac_fixpt_M_local_0[50] = mac_fixpt_add_temp_336[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_1034 = {1'b0, {mac_fixpt_M_local_0[50], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_348 = W[2];
end
else begin
mac_fixpt_t_348 = 14'b00000000000000;
end
mac_fixpt_add_cast_1035 = {1'b0, mac_fixpt_t_348};
mac_fixpt_add_cast_1036 = {1'b0, mac_fixpt_add_cast_1035};
mac_fixpt_add_temp_344 = mac_fixpt_add_cast_1034 + mac_fixpt_add_cast_1036;
mac_fixpt_M_local_0[50] = mac_fixpt_add_temp_344[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_1058 = {1'b0, {mac_fixpt_M_local_0[50], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_356 = W[3];
end
else begin
mac_fixpt_t_356 = 14'b00000000000000;
end
mac_fixpt_add_cast_1059 = {1'b0, mac_fixpt_t_356};
mac_fixpt_add_cast_1060 = {1'b0, mac_fixpt_add_cast_1059};
mac_fixpt_add_temp_352 = mac_fixpt_add_cast_1058 + mac_fixpt_add_cast_1060;
mac_fixpt_M_local_0[50] = mac_fixpt_add_temp_352[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_1082 = {1'b0, {mac_fixpt_M_local_0[50], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_364 = W[4];
end
else begin
mac_fixpt_t_364 = 14'b00000000000000;
end
mac_fixpt_add_cast_1083 = {1'b0, mac_fixpt_t_364};
mac_fixpt_add_cast_1084 = {1'b0, mac_fixpt_add_cast_1083};
mac_fixpt_add_temp_360 = mac_fixpt_add_cast_1082 + mac_fixpt_add_cast_1084;
mac_fixpt_M_local_0[50] = mac_fixpt_add_temp_360[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_1106 = {1'b0, {mac_fixpt_M_local_0[50], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_372 = W[5];
end
else begin
mac_fixpt_t_372 = 14'b00000000000000;
end
mac_fixpt_add_cast_1107 = {1'b0, mac_fixpt_t_372};
mac_fixpt_add_cast_1108 = {1'b0, mac_fixpt_add_cast_1107};
mac_fixpt_add_temp_368 = mac_fixpt_add_cast_1106 + mac_fixpt_add_cast_1108;
mac_fixpt_M_local_0[50] = mac_fixpt_add_temp_368[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_1130 = {1'b0, {mac_fixpt_M_local_0[50], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_380 = W[6];
end
else begin
mac_fixpt_t_380 = 14'b00000000000000;
end
mac_fixpt_add_cast_1131 = {1'b0, mac_fixpt_t_380};
mac_fixpt_add_cast_1132 = {1'b0, mac_fixpt_add_cast_1131};
mac_fixpt_add_temp_376 = mac_fixpt_add_cast_1130 + mac_fixpt_add_cast_1132;
mac_fixpt_M_local_0[50] = mac_fixpt_add_temp_376[14:1];
end
end
if (7'b0110100 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_1007 = {1'b0, {mac_fixpt_M_local_0[51], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_339 = W[0];
end
else begin
mac_fixpt_t_339 = 14'b00000000000000;
end
mac_fixpt_add_cast_1008 = {1'b0, mac_fixpt_t_339};
mac_fixpt_add_cast_1009 = {1'b0, mac_fixpt_add_cast_1008};
mac_fixpt_add_temp_335 = mac_fixpt_add_cast_1007 + mac_fixpt_add_cast_1009;
mac_fixpt_M_local_0[51] = mac_fixpt_add_temp_335[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_1031 = {1'b0, {mac_fixpt_M_local_0[51], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_347 = W[1];
end
else begin
mac_fixpt_t_347 = 14'b00000000000000;
end
mac_fixpt_add_cast_1032 = {1'b0, mac_fixpt_t_347};
mac_fixpt_add_cast_1033 = {1'b0, mac_fixpt_add_cast_1032};
mac_fixpt_add_temp_343 = mac_fixpt_add_cast_1031 + mac_fixpt_add_cast_1033;
mac_fixpt_M_local_0[51] = mac_fixpt_add_temp_343[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_1055 = {1'b0, {mac_fixpt_M_local_0[51], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_355 = W[2];
end
else begin
mac_fixpt_t_355 = 14'b00000000000000;
end
mac_fixpt_add_cast_1056 = {1'b0, mac_fixpt_t_355};
mac_fixpt_add_cast_1057 = {1'b0, mac_fixpt_add_cast_1056};
mac_fixpt_add_temp_351 = mac_fixpt_add_cast_1055 + mac_fixpt_add_cast_1057;
mac_fixpt_M_local_0[51] = mac_fixpt_add_temp_351[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_1079 = {1'b0, {mac_fixpt_M_local_0[51], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_363 = W[3];
end
else begin
mac_fixpt_t_363 = 14'b00000000000000;
end
mac_fixpt_add_cast_1080 = {1'b0, mac_fixpt_t_363};
mac_fixpt_add_cast_1081 = {1'b0, mac_fixpt_add_cast_1080};
mac_fixpt_add_temp_359 = mac_fixpt_add_cast_1079 + mac_fixpt_add_cast_1081;
mac_fixpt_M_local_0[51] = mac_fixpt_add_temp_359[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_1103 = {1'b0, {mac_fixpt_M_local_0[51], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_371 = W[4];
end
else begin
mac_fixpt_t_371 = 14'b00000000000000;
end
mac_fixpt_add_cast_1104 = {1'b0, mac_fixpt_t_371};
mac_fixpt_add_cast_1105 = {1'b0, mac_fixpt_add_cast_1104};
mac_fixpt_add_temp_367 = mac_fixpt_add_cast_1103 + mac_fixpt_add_cast_1105;
mac_fixpt_M_local_0[51] = mac_fixpt_add_temp_367[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_1127 = {1'b0, {mac_fixpt_M_local_0[51], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_379 = W[5];
end
else begin
mac_fixpt_t_379 = 14'b00000000000000;
end
mac_fixpt_add_cast_1128 = {1'b0, mac_fixpt_t_379};
mac_fixpt_add_cast_1129 = {1'b0, mac_fixpt_add_cast_1128};
mac_fixpt_add_temp_375 = mac_fixpt_add_cast_1127 + mac_fixpt_add_cast_1129;
mac_fixpt_M_local_0[51] = mac_fixpt_add_temp_375[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_1151 = {1'b0, {mac_fixpt_M_local_0[51], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_387 = W[6];
end
else begin
mac_fixpt_t_387 = 14'b00000000000000;
end
mac_fixpt_add_cast_1152 = {1'b0, mac_fixpt_t_387};
mac_fixpt_add_cast_1153 = {1'b0, mac_fixpt_add_cast_1152};
mac_fixpt_add_temp_383 = mac_fixpt_add_cast_1151 + mac_fixpt_add_cast_1153;
mac_fixpt_M_local_0[51] = mac_fixpt_add_temp_383[14:1];
end
end
if (7'b0110101 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_1028 = {1'b0, {mac_fixpt_M_local_0[52], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_346 = W[0];
end
else begin
mac_fixpt_t_346 = 14'b00000000000000;
end
mac_fixpt_add_cast_1029 = {1'b0, mac_fixpt_t_346};
mac_fixpt_add_cast_1030 = {1'b0, mac_fixpt_add_cast_1029};
mac_fixpt_add_temp_342 = mac_fixpt_add_cast_1028 + mac_fixpt_add_cast_1030;
mac_fixpt_M_local_0[52] = mac_fixpt_add_temp_342[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_1052 = {1'b0, {mac_fixpt_M_local_0[52], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_354 = W[1];
end
else begin
mac_fixpt_t_354 = 14'b00000000000000;
end
mac_fixpt_add_cast_1053 = {1'b0, mac_fixpt_t_354};
mac_fixpt_add_cast_1054 = {1'b0, mac_fixpt_add_cast_1053};
mac_fixpt_add_temp_350 = mac_fixpt_add_cast_1052 + mac_fixpt_add_cast_1054;
mac_fixpt_M_local_0[52] = mac_fixpt_add_temp_350[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_1076 = {1'b0, {mac_fixpt_M_local_0[52], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_362 = W[2];
end
else begin
mac_fixpt_t_362 = 14'b00000000000000;
end
mac_fixpt_add_cast_1077 = {1'b0, mac_fixpt_t_362};
mac_fixpt_add_cast_1078 = {1'b0, mac_fixpt_add_cast_1077};
mac_fixpt_add_temp_358 = mac_fixpt_add_cast_1076 + mac_fixpt_add_cast_1078;
mac_fixpt_M_local_0[52] = mac_fixpt_add_temp_358[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_1100 = {1'b0, {mac_fixpt_M_local_0[52], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_370 = W[3];
end
else begin
mac_fixpt_t_370 = 14'b00000000000000;
end
mac_fixpt_add_cast_1101 = {1'b0, mac_fixpt_t_370};
mac_fixpt_add_cast_1102 = {1'b0, mac_fixpt_add_cast_1101};
mac_fixpt_add_temp_366 = mac_fixpt_add_cast_1100 + mac_fixpt_add_cast_1102;
mac_fixpt_M_local_0[52] = mac_fixpt_add_temp_366[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_1124 = {1'b0, {mac_fixpt_M_local_0[52], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_378 = W[4];
end
else begin
mac_fixpt_t_378 = 14'b00000000000000;
end
mac_fixpt_add_cast_1125 = {1'b0, mac_fixpt_t_378};
mac_fixpt_add_cast_1126 = {1'b0, mac_fixpt_add_cast_1125};
mac_fixpt_add_temp_374 = mac_fixpt_add_cast_1124 + mac_fixpt_add_cast_1126;
mac_fixpt_M_local_0[52] = mac_fixpt_add_temp_374[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_1148 = {1'b0, {mac_fixpt_M_local_0[52], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_386 = W[5];
end
else begin
mac_fixpt_t_386 = 14'b00000000000000;
end
mac_fixpt_add_cast_1149 = {1'b0, mac_fixpt_t_386};
mac_fixpt_add_cast_1150 = {1'b0, mac_fixpt_add_cast_1149};
mac_fixpt_add_temp_382 = mac_fixpt_add_cast_1148 + mac_fixpt_add_cast_1150;
mac_fixpt_M_local_0[52] = mac_fixpt_add_temp_382[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_1172 = {1'b0, {mac_fixpt_M_local_0[52], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_394 = W[6];
end
else begin
mac_fixpt_t_394 = 14'b00000000000000;
end
mac_fixpt_add_cast_1173 = {1'b0, mac_fixpt_t_394};
mac_fixpt_add_cast_1174 = {1'b0, mac_fixpt_add_cast_1173};
mac_fixpt_add_temp_390 = mac_fixpt_add_cast_1172 + mac_fixpt_add_cast_1174;
mac_fixpt_M_local_0[52] = mac_fixpt_add_temp_390[14:1];
end
end
if (7'b0110110 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_1049 = {1'b0, {mac_fixpt_M_local_0[53], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_353 = W[0];
end
else begin
mac_fixpt_t_353 = 14'b00000000000000;
end
mac_fixpt_add_cast_1050 = {1'b0, mac_fixpt_t_353};
mac_fixpt_add_cast_1051 = {1'b0, mac_fixpt_add_cast_1050};
mac_fixpt_add_temp_349 = mac_fixpt_add_cast_1049 + mac_fixpt_add_cast_1051;
mac_fixpt_M_local_0[53] = mac_fixpt_add_temp_349[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_1073 = {1'b0, {mac_fixpt_M_local_0[53], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_361 = W[1];
end
else begin
mac_fixpt_t_361 = 14'b00000000000000;
end
mac_fixpt_add_cast_1074 = {1'b0, mac_fixpt_t_361};
mac_fixpt_add_cast_1075 = {1'b0, mac_fixpt_add_cast_1074};
mac_fixpt_add_temp_357 = mac_fixpt_add_cast_1073 + mac_fixpt_add_cast_1075;
mac_fixpt_M_local_0[53] = mac_fixpt_add_temp_357[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_1097 = {1'b0, {mac_fixpt_M_local_0[53], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_369 = W[2];
end
else begin
mac_fixpt_t_369 = 14'b00000000000000;
end
mac_fixpt_add_cast_1098 = {1'b0, mac_fixpt_t_369};
mac_fixpt_add_cast_1099 = {1'b0, mac_fixpt_add_cast_1098};
mac_fixpt_add_temp_365 = mac_fixpt_add_cast_1097 + mac_fixpt_add_cast_1099;
mac_fixpt_M_local_0[53] = mac_fixpt_add_temp_365[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_1121 = {1'b0, {mac_fixpt_M_local_0[53], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_377 = W[3];
end
else begin
mac_fixpt_t_377 = 14'b00000000000000;
end
mac_fixpt_add_cast_1122 = {1'b0, mac_fixpt_t_377};
mac_fixpt_add_cast_1123 = {1'b0, mac_fixpt_add_cast_1122};
mac_fixpt_add_temp_373 = mac_fixpt_add_cast_1121 + mac_fixpt_add_cast_1123;
mac_fixpt_M_local_0[53] = mac_fixpt_add_temp_373[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_1145 = {1'b0, {mac_fixpt_M_local_0[53], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_385 = W[4];
end
else begin
mac_fixpt_t_385 = 14'b00000000000000;
end
mac_fixpt_add_cast_1146 = {1'b0, mac_fixpt_t_385};
mac_fixpt_add_cast_1147 = {1'b0, mac_fixpt_add_cast_1146};
mac_fixpt_add_temp_381 = mac_fixpt_add_cast_1145 + mac_fixpt_add_cast_1147;
mac_fixpt_M_local_0[53] = mac_fixpt_add_temp_381[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_1169 = {1'b0, {mac_fixpt_M_local_0[53], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_393 = W[5];
end
else begin
mac_fixpt_t_393 = 14'b00000000000000;
end
mac_fixpt_add_cast_1170 = {1'b0, mac_fixpt_t_393};
mac_fixpt_add_cast_1171 = {1'b0, mac_fixpt_add_cast_1170};
mac_fixpt_add_temp_389 = mac_fixpt_add_cast_1169 + mac_fixpt_add_cast_1171;
mac_fixpt_M_local_0[53] = mac_fixpt_add_temp_389[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_1193 = {1'b0, {mac_fixpt_M_local_0[53], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_401 = W[6];
end
else begin
mac_fixpt_t_401 = 14'b00000000000000;
end
mac_fixpt_add_cast_1194 = {1'b0, mac_fixpt_t_401};
mac_fixpt_add_cast_1195 = {1'b0, mac_fixpt_add_cast_1194};
mac_fixpt_add_temp_397 = mac_fixpt_add_cast_1193 + mac_fixpt_add_cast_1195;
mac_fixpt_M_local_0[53] = mac_fixpt_add_temp_397[14:1];
end
end
if (7'b0110111 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_1070 = {1'b0, {mac_fixpt_M_local_0[54], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_360 = W[0];
end
else begin
mac_fixpt_t_360 = 14'b00000000000000;
end
mac_fixpt_add_cast_1071 = {1'b0, mac_fixpt_t_360};
mac_fixpt_add_cast_1072 = {1'b0, mac_fixpt_add_cast_1071};
mac_fixpt_add_temp_356 = mac_fixpt_add_cast_1070 + mac_fixpt_add_cast_1072;
mac_fixpt_M_local_0[54] = mac_fixpt_add_temp_356[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_1094 = {1'b0, {mac_fixpt_M_local_0[54], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_368 = W[1];
end
else begin
mac_fixpt_t_368 = 14'b00000000000000;
end
mac_fixpt_add_cast_1095 = {1'b0, mac_fixpt_t_368};
mac_fixpt_add_cast_1096 = {1'b0, mac_fixpt_add_cast_1095};
mac_fixpt_add_temp_364 = mac_fixpt_add_cast_1094 + mac_fixpt_add_cast_1096;
mac_fixpt_M_local_0[54] = mac_fixpt_add_temp_364[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_1118 = {1'b0, {mac_fixpt_M_local_0[54], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_376 = W[2];
end
else begin
mac_fixpt_t_376 = 14'b00000000000000;
end
mac_fixpt_add_cast_1119 = {1'b0, mac_fixpt_t_376};
mac_fixpt_add_cast_1120 = {1'b0, mac_fixpt_add_cast_1119};
mac_fixpt_add_temp_372 = mac_fixpt_add_cast_1118 + mac_fixpt_add_cast_1120;
mac_fixpt_M_local_0[54] = mac_fixpt_add_temp_372[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_1142 = {1'b0, {mac_fixpt_M_local_0[54], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_384 = W[3];
end
else begin
mac_fixpt_t_384 = 14'b00000000000000;
end
mac_fixpt_add_cast_1143 = {1'b0, mac_fixpt_t_384};
mac_fixpt_add_cast_1144 = {1'b0, mac_fixpt_add_cast_1143};
mac_fixpt_add_temp_380 = mac_fixpt_add_cast_1142 + mac_fixpt_add_cast_1144;
mac_fixpt_M_local_0[54] = mac_fixpt_add_temp_380[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_1166 = {1'b0, {mac_fixpt_M_local_0[54], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_392 = W[4];
end
else begin
mac_fixpt_t_392 = 14'b00000000000000;
end
mac_fixpt_add_cast_1167 = {1'b0, mac_fixpt_t_392};
mac_fixpt_add_cast_1168 = {1'b0, mac_fixpt_add_cast_1167};
mac_fixpt_add_temp_388 = mac_fixpt_add_cast_1166 + mac_fixpt_add_cast_1168;
mac_fixpt_M_local_0[54] = mac_fixpt_add_temp_388[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_1190 = {1'b0, {mac_fixpt_M_local_0[54], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_400 = W[5];
end
else begin
mac_fixpt_t_400 = 14'b00000000000000;
end
mac_fixpt_add_cast_1191 = {1'b0, mac_fixpt_t_400};
mac_fixpt_add_cast_1192 = {1'b0, mac_fixpt_add_cast_1191};
mac_fixpt_add_temp_396 = mac_fixpt_add_cast_1190 + mac_fixpt_add_cast_1192;
mac_fixpt_M_local_0[54] = mac_fixpt_add_temp_396[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_1214 = {1'b0, {mac_fixpt_M_local_0[54], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_408 = W[6];
end
else begin
mac_fixpt_t_408 = 14'b00000000000000;
end
mac_fixpt_add_cast_1215 = {1'b0, mac_fixpt_t_408};
mac_fixpt_add_cast_1216 = {1'b0, mac_fixpt_add_cast_1215};
mac_fixpt_add_temp_404 = mac_fixpt_add_cast_1214 + mac_fixpt_add_cast_1216;
mac_fixpt_M_local_0[54] = mac_fixpt_add_temp_404[14:1];
end
end
if (7'b0111000 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_1091 = {1'b0, {mac_fixpt_M_local_0[55], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_367 = W[0];
end
else begin
mac_fixpt_t_367 = 14'b00000000000000;
end
mac_fixpt_add_cast_1092 = {1'b0, mac_fixpt_t_367};
mac_fixpt_add_cast_1093 = {1'b0, mac_fixpt_add_cast_1092};
mac_fixpt_add_temp_363 = mac_fixpt_add_cast_1091 + mac_fixpt_add_cast_1093;
mac_fixpt_M_local_0[55] = mac_fixpt_add_temp_363[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_1115 = {1'b0, {mac_fixpt_M_local_0[55], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_375 = W[1];
end
else begin
mac_fixpt_t_375 = 14'b00000000000000;
end
mac_fixpt_add_cast_1116 = {1'b0, mac_fixpt_t_375};
mac_fixpt_add_cast_1117 = {1'b0, mac_fixpt_add_cast_1116};
mac_fixpt_add_temp_371 = mac_fixpt_add_cast_1115 + mac_fixpt_add_cast_1117;
mac_fixpt_M_local_0[55] = mac_fixpt_add_temp_371[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_1139 = {1'b0, {mac_fixpt_M_local_0[55], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_383 = W[2];
end
else begin
mac_fixpt_t_383 = 14'b00000000000000;
end
mac_fixpt_add_cast_1140 = {1'b0, mac_fixpt_t_383};
mac_fixpt_add_cast_1141 = {1'b0, mac_fixpt_add_cast_1140};
mac_fixpt_add_temp_379 = mac_fixpt_add_cast_1139 + mac_fixpt_add_cast_1141;
mac_fixpt_M_local_0[55] = mac_fixpt_add_temp_379[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_1163 = {1'b0, {mac_fixpt_M_local_0[55], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_391 = W[3];
end
else begin
mac_fixpt_t_391 = 14'b00000000000000;
end
mac_fixpt_add_cast_1164 = {1'b0, mac_fixpt_t_391};
mac_fixpt_add_cast_1165 = {1'b0, mac_fixpt_add_cast_1164};
mac_fixpt_add_temp_387 = mac_fixpt_add_cast_1163 + mac_fixpt_add_cast_1165;
mac_fixpt_M_local_0[55] = mac_fixpt_add_temp_387[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_1187 = {1'b0, {mac_fixpt_M_local_0[55], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_399 = W[4];
end
else begin
mac_fixpt_t_399 = 14'b00000000000000;
end
mac_fixpt_add_cast_1188 = {1'b0, mac_fixpt_t_399};
mac_fixpt_add_cast_1189 = {1'b0, mac_fixpt_add_cast_1188};
mac_fixpt_add_temp_395 = mac_fixpt_add_cast_1187 + mac_fixpt_add_cast_1189;
mac_fixpt_M_local_0[55] = mac_fixpt_add_temp_395[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_1211 = {1'b0, {mac_fixpt_M_local_0[55], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_407 = W[5];
end
else begin
mac_fixpt_t_407 = 14'b00000000000000;
end
mac_fixpt_add_cast_1212 = {1'b0, mac_fixpt_t_407};
mac_fixpt_add_cast_1213 = {1'b0, mac_fixpt_add_cast_1212};
mac_fixpt_add_temp_403 = mac_fixpt_add_cast_1211 + mac_fixpt_add_cast_1213;
mac_fixpt_M_local_0[55] = mac_fixpt_add_temp_403[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_1235 = {1'b0, {mac_fixpt_M_local_0[55], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_415 = W[6];
end
else begin
mac_fixpt_t_415 = 14'b00000000000000;
end
mac_fixpt_add_cast_1236 = {1'b0, mac_fixpt_t_415};
mac_fixpt_add_cast_1237 = {1'b0, mac_fixpt_add_cast_1236};
mac_fixpt_add_temp_411 = mac_fixpt_add_cast_1235 + mac_fixpt_add_cast_1237;
mac_fixpt_M_local_0[55] = mac_fixpt_add_temp_411[14:1];
end
end
if (7'b0111001 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_1112 = {1'b0, {mac_fixpt_M_local_0[56], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_374 = W[0];
end
else begin
mac_fixpt_t_374 = 14'b00000000000000;
end
mac_fixpt_add_cast_1113 = {1'b0, mac_fixpt_t_374};
mac_fixpt_add_cast_1114 = {1'b0, mac_fixpt_add_cast_1113};
mac_fixpt_add_temp_370 = mac_fixpt_add_cast_1112 + mac_fixpt_add_cast_1114;
mac_fixpt_M_local_0[56] = mac_fixpt_add_temp_370[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_1136 = {1'b0, {mac_fixpt_M_local_0[56], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_382 = W[1];
end
else begin
mac_fixpt_t_382 = 14'b00000000000000;
end
mac_fixpt_add_cast_1137 = {1'b0, mac_fixpt_t_382};
mac_fixpt_add_cast_1138 = {1'b0, mac_fixpt_add_cast_1137};
mac_fixpt_add_temp_378 = mac_fixpt_add_cast_1136 + mac_fixpt_add_cast_1138;
mac_fixpt_M_local_0[56] = mac_fixpt_add_temp_378[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_1160 = {1'b0, {mac_fixpt_M_local_0[56], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_390 = W[2];
end
else begin
mac_fixpt_t_390 = 14'b00000000000000;
end
mac_fixpt_add_cast_1161 = {1'b0, mac_fixpt_t_390};
mac_fixpt_add_cast_1162 = {1'b0, mac_fixpt_add_cast_1161};
mac_fixpt_add_temp_386 = mac_fixpt_add_cast_1160 + mac_fixpt_add_cast_1162;
mac_fixpt_M_local_0[56] = mac_fixpt_add_temp_386[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_1184 = {1'b0, {mac_fixpt_M_local_0[56], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_398 = W[3];
end
else begin
mac_fixpt_t_398 = 14'b00000000000000;
end
mac_fixpt_add_cast_1185 = {1'b0, mac_fixpt_t_398};
mac_fixpt_add_cast_1186 = {1'b0, mac_fixpt_add_cast_1185};
mac_fixpt_add_temp_394 = mac_fixpt_add_cast_1184 + mac_fixpt_add_cast_1186;
mac_fixpt_M_local_0[56] = mac_fixpt_add_temp_394[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_1208 = {1'b0, {mac_fixpt_M_local_0[56], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_406 = W[4];
end
else begin
mac_fixpt_t_406 = 14'b00000000000000;
end
mac_fixpt_add_cast_1209 = {1'b0, mac_fixpt_t_406};
mac_fixpt_add_cast_1210 = {1'b0, mac_fixpt_add_cast_1209};
mac_fixpt_add_temp_402 = mac_fixpt_add_cast_1208 + mac_fixpt_add_cast_1210;
mac_fixpt_M_local_0[56] = mac_fixpt_add_temp_402[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_1232 = {1'b0, {mac_fixpt_M_local_0[56], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_414 = W[5];
end
else begin
mac_fixpt_t_414 = 14'b00000000000000;
end
mac_fixpt_add_cast_1233 = {1'b0, mac_fixpt_t_414};
mac_fixpt_add_cast_1234 = {1'b0, mac_fixpt_add_cast_1233};
mac_fixpt_add_temp_410 = mac_fixpt_add_cast_1232 + mac_fixpt_add_cast_1234;
mac_fixpt_M_local_0[56] = mac_fixpt_add_temp_410[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_1256 = {1'b0, {mac_fixpt_M_local_0[56], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_422 = W[6];
end
else begin
mac_fixpt_t_422 = 14'b00000000000000;
end
mac_fixpt_add_cast_1257 = {1'b0, mac_fixpt_t_422};
mac_fixpt_add_cast_1258 = {1'b0, mac_fixpt_add_cast_1257};
mac_fixpt_add_temp_418 = mac_fixpt_add_cast_1256 + mac_fixpt_add_cast_1258;
mac_fixpt_M_local_0[56] = mac_fixpt_add_temp_418[14:1];
end
end
if (7'b0111010 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_1133 = {1'b0, {mac_fixpt_M_local_0[57], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_381 = W[0];
end
else begin
mac_fixpt_t_381 = 14'b00000000000000;
end
mac_fixpt_add_cast_1134 = {1'b0, mac_fixpt_t_381};
mac_fixpt_add_cast_1135 = {1'b0, mac_fixpt_add_cast_1134};
mac_fixpt_add_temp_377 = mac_fixpt_add_cast_1133 + mac_fixpt_add_cast_1135;
mac_fixpt_M_local_0[57] = mac_fixpt_add_temp_377[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_1157 = {1'b0, {mac_fixpt_M_local_0[57], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_389 = W[1];
end
else begin
mac_fixpt_t_389 = 14'b00000000000000;
end
mac_fixpt_add_cast_1158 = {1'b0, mac_fixpt_t_389};
mac_fixpt_add_cast_1159 = {1'b0, mac_fixpt_add_cast_1158};
mac_fixpt_add_temp_385 = mac_fixpt_add_cast_1157 + mac_fixpt_add_cast_1159;
mac_fixpt_M_local_0[57] = mac_fixpt_add_temp_385[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_1181 = {1'b0, {mac_fixpt_M_local_0[57], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_397 = W[2];
end
else begin
mac_fixpt_t_397 = 14'b00000000000000;
end
mac_fixpt_add_cast_1182 = {1'b0, mac_fixpt_t_397};
mac_fixpt_add_cast_1183 = {1'b0, mac_fixpt_add_cast_1182};
mac_fixpt_add_temp_393 = mac_fixpt_add_cast_1181 + mac_fixpt_add_cast_1183;
mac_fixpt_M_local_0[57] = mac_fixpt_add_temp_393[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_1205 = {1'b0, {mac_fixpt_M_local_0[57], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_405 = W[3];
end
else begin
mac_fixpt_t_405 = 14'b00000000000000;
end
mac_fixpt_add_cast_1206 = {1'b0, mac_fixpt_t_405};
mac_fixpt_add_cast_1207 = {1'b0, mac_fixpt_add_cast_1206};
mac_fixpt_add_temp_401 = mac_fixpt_add_cast_1205 + mac_fixpt_add_cast_1207;
mac_fixpt_M_local_0[57] = mac_fixpt_add_temp_401[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_1229 = {1'b0, {mac_fixpt_M_local_0[57], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_413 = W[4];
end
else begin
mac_fixpt_t_413 = 14'b00000000000000;
end
mac_fixpt_add_cast_1230 = {1'b0, mac_fixpt_t_413};
mac_fixpt_add_cast_1231 = {1'b0, mac_fixpt_add_cast_1230};
mac_fixpt_add_temp_409 = mac_fixpt_add_cast_1229 + mac_fixpt_add_cast_1231;
mac_fixpt_M_local_0[57] = mac_fixpt_add_temp_409[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_1253 = {1'b0, {mac_fixpt_M_local_0[57], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_421 = W[5];
end
else begin
mac_fixpt_t_421 = 14'b00000000000000;
end
mac_fixpt_add_cast_1254 = {1'b0, mac_fixpt_t_421};
mac_fixpt_add_cast_1255 = {1'b0, mac_fixpt_add_cast_1254};
mac_fixpt_add_temp_417 = mac_fixpt_add_cast_1253 + mac_fixpt_add_cast_1255;
mac_fixpt_M_local_0[57] = mac_fixpt_add_temp_417[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_1277 = {1'b0, {mac_fixpt_M_local_0[57], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_429 = W[6];
end
else begin
mac_fixpt_t_429 = 14'b00000000000000;
end
mac_fixpt_add_cast_1278 = {1'b0, mac_fixpt_t_429};
mac_fixpt_add_cast_1279 = {1'b0, mac_fixpt_add_cast_1278};
mac_fixpt_add_temp_425 = mac_fixpt_add_cast_1277 + mac_fixpt_add_cast_1279;
mac_fixpt_M_local_0[57] = mac_fixpt_add_temp_425[14:1];
end
end
if (7'b0111011 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_1154 = {1'b0, {mac_fixpt_M_local_0[58], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_388 = W[0];
end
else begin
mac_fixpt_t_388 = 14'b00000000000000;
end
mac_fixpt_add_cast_1155 = {1'b0, mac_fixpt_t_388};
mac_fixpt_add_cast_1156 = {1'b0, mac_fixpt_add_cast_1155};
mac_fixpt_add_temp_384 = mac_fixpt_add_cast_1154 + mac_fixpt_add_cast_1156;
mac_fixpt_M_local_0[58] = mac_fixpt_add_temp_384[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_1178 = {1'b0, {mac_fixpt_M_local_0[58], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_396 = W[1];
end
else begin
mac_fixpt_t_396 = 14'b00000000000000;
end
mac_fixpt_add_cast_1179 = {1'b0, mac_fixpt_t_396};
mac_fixpt_add_cast_1180 = {1'b0, mac_fixpt_add_cast_1179};
mac_fixpt_add_temp_392 = mac_fixpt_add_cast_1178 + mac_fixpt_add_cast_1180;
mac_fixpt_M_local_0[58] = mac_fixpt_add_temp_392[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_1202 = {1'b0, {mac_fixpt_M_local_0[58], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_404 = W[2];
end
else begin
mac_fixpt_t_404 = 14'b00000000000000;
end
mac_fixpt_add_cast_1203 = {1'b0, mac_fixpt_t_404};
mac_fixpt_add_cast_1204 = {1'b0, mac_fixpt_add_cast_1203};
mac_fixpt_add_temp_400 = mac_fixpt_add_cast_1202 + mac_fixpt_add_cast_1204;
mac_fixpt_M_local_0[58] = mac_fixpt_add_temp_400[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_1226 = {1'b0, {mac_fixpt_M_local_0[58], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_412 = W[3];
end
else begin
mac_fixpt_t_412 = 14'b00000000000000;
end
mac_fixpt_add_cast_1227 = {1'b0, mac_fixpt_t_412};
mac_fixpt_add_cast_1228 = {1'b0, mac_fixpt_add_cast_1227};
mac_fixpt_add_temp_408 = mac_fixpt_add_cast_1226 + mac_fixpt_add_cast_1228;
mac_fixpt_M_local_0[58] = mac_fixpt_add_temp_408[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_1250 = {1'b0, {mac_fixpt_M_local_0[58], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_420 = W[4];
end
else begin
mac_fixpt_t_420 = 14'b00000000000000;
end
mac_fixpt_add_cast_1251 = {1'b0, mac_fixpt_t_420};
mac_fixpt_add_cast_1252 = {1'b0, mac_fixpt_add_cast_1251};
mac_fixpt_add_temp_416 = mac_fixpt_add_cast_1250 + mac_fixpt_add_cast_1252;
mac_fixpt_M_local_0[58] = mac_fixpt_add_temp_416[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_1274 = {1'b0, {mac_fixpt_M_local_0[58], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_428 = W[5];
end
else begin
mac_fixpt_t_428 = 14'b00000000000000;
end
mac_fixpt_add_cast_1275 = {1'b0, mac_fixpt_t_428};
mac_fixpt_add_cast_1276 = {1'b0, mac_fixpt_add_cast_1275};
mac_fixpt_add_temp_424 = mac_fixpt_add_cast_1274 + mac_fixpt_add_cast_1276;
mac_fixpt_M_local_0[58] = mac_fixpt_add_temp_424[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_1295 = {1'b0, {mac_fixpt_M_local_0[58], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_435 = W[6];
end
else begin
mac_fixpt_t_435 = 14'b00000000000000;
end
mac_fixpt_add_cast_1296 = {1'b0, mac_fixpt_t_435};
mac_fixpt_add_cast_1297 = {1'b0, mac_fixpt_add_cast_1296};
mac_fixpt_add_temp_431 = mac_fixpt_add_cast_1295 + mac_fixpt_add_cast_1297;
mac_fixpt_M_local_0[58] = mac_fixpt_add_temp_431[14:1];
end
end
if (7'b0111100 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_1175 = {1'b0, {mac_fixpt_M_local_0[59], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_395 = W[0];
end
else begin
mac_fixpt_t_395 = 14'b00000000000000;
end
mac_fixpt_add_cast_1176 = {1'b0, mac_fixpt_t_395};
mac_fixpt_add_cast_1177 = {1'b0, mac_fixpt_add_cast_1176};
mac_fixpt_add_temp_391 = mac_fixpt_add_cast_1175 + mac_fixpt_add_cast_1177;
mac_fixpt_M_local_0[59] = mac_fixpt_add_temp_391[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_1199 = {1'b0, {mac_fixpt_M_local_0[59], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_403 = W[1];
end
else begin
mac_fixpt_t_403 = 14'b00000000000000;
end
mac_fixpt_add_cast_1200 = {1'b0, mac_fixpt_t_403};
mac_fixpt_add_cast_1201 = {1'b0, mac_fixpt_add_cast_1200};
mac_fixpt_add_temp_399 = mac_fixpt_add_cast_1199 + mac_fixpt_add_cast_1201;
mac_fixpt_M_local_0[59] = mac_fixpt_add_temp_399[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_1223 = {1'b0, {mac_fixpt_M_local_0[59], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_411 = W[2];
end
else begin
mac_fixpt_t_411 = 14'b00000000000000;
end
mac_fixpt_add_cast_1224 = {1'b0, mac_fixpt_t_411};
mac_fixpt_add_cast_1225 = {1'b0, mac_fixpt_add_cast_1224};
mac_fixpt_add_temp_407 = mac_fixpt_add_cast_1223 + mac_fixpt_add_cast_1225;
mac_fixpt_M_local_0[59] = mac_fixpt_add_temp_407[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_1247 = {1'b0, {mac_fixpt_M_local_0[59], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_419 = W[3];
end
else begin
mac_fixpt_t_419 = 14'b00000000000000;
end
mac_fixpt_add_cast_1248 = {1'b0, mac_fixpt_t_419};
mac_fixpt_add_cast_1249 = {1'b0, mac_fixpt_add_cast_1248};
mac_fixpt_add_temp_415 = mac_fixpt_add_cast_1247 + mac_fixpt_add_cast_1249;
mac_fixpt_M_local_0[59] = mac_fixpt_add_temp_415[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_1271 = {1'b0, {mac_fixpt_M_local_0[59], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_427 = W[4];
end
else begin
mac_fixpt_t_427 = 14'b00000000000000;
end
mac_fixpt_add_cast_1272 = {1'b0, mac_fixpt_t_427};
mac_fixpt_add_cast_1273 = {1'b0, mac_fixpt_add_cast_1272};
mac_fixpt_add_temp_423 = mac_fixpt_add_cast_1271 + mac_fixpt_add_cast_1273;
mac_fixpt_M_local_0[59] = mac_fixpt_add_temp_423[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_1292 = {1'b0, {mac_fixpt_M_local_0[59], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_434 = W[5];
end
else begin
mac_fixpt_t_434 = 14'b00000000000000;
end
mac_fixpt_add_cast_1293 = {1'b0, mac_fixpt_t_434};
mac_fixpt_add_cast_1294 = {1'b0, mac_fixpt_add_cast_1293};
mac_fixpt_add_temp_430 = mac_fixpt_add_cast_1292 + mac_fixpt_add_cast_1294;
mac_fixpt_M_local_0[59] = mac_fixpt_add_temp_430[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_1310 = {1'b0, {mac_fixpt_M_local_0[59], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_440 = W[6];
end
else begin
mac_fixpt_t_440 = 14'b00000000000000;
end
mac_fixpt_add_cast_1311 = {1'b0, mac_fixpt_t_440};
mac_fixpt_add_cast_1312 = {1'b0, mac_fixpt_add_cast_1311};
mac_fixpt_add_temp_436 = mac_fixpt_add_cast_1310 + mac_fixpt_add_cast_1312;
mac_fixpt_M_local_0[59] = mac_fixpt_add_temp_436[14:1];
end
end
if (7'b0111101 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_1196 = {1'b0, {mac_fixpt_M_local_0[60], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_402 = W[0];
end
else begin
mac_fixpt_t_402 = 14'b00000000000000;
end
mac_fixpt_add_cast_1197 = {1'b0, mac_fixpt_t_402};
mac_fixpt_add_cast_1198 = {1'b0, mac_fixpt_add_cast_1197};
mac_fixpt_add_temp_398 = mac_fixpt_add_cast_1196 + mac_fixpt_add_cast_1198;
mac_fixpt_M_local_0[60] = mac_fixpt_add_temp_398[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_1220 = {1'b0, {mac_fixpt_M_local_0[60], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_410 = W[1];
end
else begin
mac_fixpt_t_410 = 14'b00000000000000;
end
mac_fixpt_add_cast_1221 = {1'b0, mac_fixpt_t_410};
mac_fixpt_add_cast_1222 = {1'b0, mac_fixpt_add_cast_1221};
mac_fixpt_add_temp_406 = mac_fixpt_add_cast_1220 + mac_fixpt_add_cast_1222;
mac_fixpt_M_local_0[60] = mac_fixpt_add_temp_406[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_1244 = {1'b0, {mac_fixpt_M_local_0[60], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_418 = W[2];
end
else begin
mac_fixpt_t_418 = 14'b00000000000000;
end
mac_fixpt_add_cast_1245 = {1'b0, mac_fixpt_t_418};
mac_fixpt_add_cast_1246 = {1'b0, mac_fixpt_add_cast_1245};
mac_fixpt_add_temp_414 = mac_fixpt_add_cast_1244 + mac_fixpt_add_cast_1246;
mac_fixpt_M_local_0[60] = mac_fixpt_add_temp_414[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_1268 = {1'b0, {mac_fixpt_M_local_0[60], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_426 = W[3];
end
else begin
mac_fixpt_t_426 = 14'b00000000000000;
end
mac_fixpt_add_cast_1269 = {1'b0, mac_fixpt_t_426};
mac_fixpt_add_cast_1270 = {1'b0, mac_fixpt_add_cast_1269};
mac_fixpt_add_temp_422 = mac_fixpt_add_cast_1268 + mac_fixpt_add_cast_1270;
mac_fixpt_M_local_0[60] = mac_fixpt_add_temp_422[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_1289 = {1'b0, {mac_fixpt_M_local_0[60], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_433 = W[4];
end
else begin
mac_fixpt_t_433 = 14'b00000000000000;
end
mac_fixpt_add_cast_1290 = {1'b0, mac_fixpt_t_433};
mac_fixpt_add_cast_1291 = {1'b0, mac_fixpt_add_cast_1290};
mac_fixpt_add_temp_429 = mac_fixpt_add_cast_1289 + mac_fixpt_add_cast_1291;
mac_fixpt_M_local_0[60] = mac_fixpt_add_temp_429[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_1307 = {1'b0, {mac_fixpt_M_local_0[60], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_439 = W[5];
end
else begin
mac_fixpt_t_439 = 14'b00000000000000;
end
mac_fixpt_add_cast_1308 = {1'b0, mac_fixpt_t_439};
mac_fixpt_add_cast_1309 = {1'b0, mac_fixpt_add_cast_1308};
mac_fixpt_add_temp_435 = mac_fixpt_add_cast_1307 + mac_fixpt_add_cast_1309;
mac_fixpt_M_local_0[60] = mac_fixpt_add_temp_435[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_1322 = {1'b0, {mac_fixpt_M_local_0[60], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_444 = W[6];
end
else begin
mac_fixpt_t_444 = 14'b00000000000000;
end
mac_fixpt_add_cast_1323 = {1'b0, mac_fixpt_t_444};
mac_fixpt_add_cast_1324 = {1'b0, mac_fixpt_add_cast_1323};
mac_fixpt_add_temp_440 = mac_fixpt_add_cast_1322 + mac_fixpt_add_cast_1324;
mac_fixpt_M_local_0[60] = mac_fixpt_add_temp_440[14:1];
end
end
if (7'b0111110 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_1217 = {1'b0, {mac_fixpt_M_local_0[61], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_409 = W[0];
end
else begin
mac_fixpt_t_409 = 14'b00000000000000;
end
mac_fixpt_add_cast_1218 = {1'b0, mac_fixpt_t_409};
mac_fixpt_add_cast_1219 = {1'b0, mac_fixpt_add_cast_1218};
mac_fixpt_add_temp_405 = mac_fixpt_add_cast_1217 + mac_fixpt_add_cast_1219;
mac_fixpt_M_local_0[61] = mac_fixpt_add_temp_405[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_1241 = {1'b0, {mac_fixpt_M_local_0[61], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_417 = W[1];
end
else begin
mac_fixpt_t_417 = 14'b00000000000000;
end
mac_fixpt_add_cast_1242 = {1'b0, mac_fixpt_t_417};
mac_fixpt_add_cast_1243 = {1'b0, mac_fixpt_add_cast_1242};
mac_fixpt_add_temp_413 = mac_fixpt_add_cast_1241 + mac_fixpt_add_cast_1243;
mac_fixpt_M_local_0[61] = mac_fixpt_add_temp_413[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_1265 = {1'b0, {mac_fixpt_M_local_0[61], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_425 = W[2];
end
else begin
mac_fixpt_t_425 = 14'b00000000000000;
end
mac_fixpt_add_cast_1266 = {1'b0, mac_fixpt_t_425};
mac_fixpt_add_cast_1267 = {1'b0, mac_fixpt_add_cast_1266};
mac_fixpt_add_temp_421 = mac_fixpt_add_cast_1265 + mac_fixpt_add_cast_1267;
mac_fixpt_M_local_0[61] = mac_fixpt_add_temp_421[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_1286 = {1'b0, {mac_fixpt_M_local_0[61], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_432 = W[3];
end
else begin
mac_fixpt_t_432 = 14'b00000000000000;
end
mac_fixpt_add_cast_1287 = {1'b0, mac_fixpt_t_432};
mac_fixpt_add_cast_1288 = {1'b0, mac_fixpt_add_cast_1287};
mac_fixpt_add_temp_428 = mac_fixpt_add_cast_1286 + mac_fixpt_add_cast_1288;
mac_fixpt_M_local_0[61] = mac_fixpt_add_temp_428[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_1304 = {1'b0, {mac_fixpt_M_local_0[61], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_438 = W[4];
end
else begin
mac_fixpt_t_438 = 14'b00000000000000;
end
mac_fixpt_add_cast_1305 = {1'b0, mac_fixpt_t_438};
mac_fixpt_add_cast_1306 = {1'b0, mac_fixpt_add_cast_1305};
mac_fixpt_add_temp_434 = mac_fixpt_add_cast_1304 + mac_fixpt_add_cast_1306;
mac_fixpt_M_local_0[61] = mac_fixpt_add_temp_434[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_1319 = {1'b0, {mac_fixpt_M_local_0[61], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_443 = W[5];
end
else begin
mac_fixpt_t_443 = 14'b00000000000000;
end
mac_fixpt_add_cast_1320 = {1'b0, mac_fixpt_t_443};
mac_fixpt_add_cast_1321 = {1'b0, mac_fixpt_add_cast_1320};
mac_fixpt_add_temp_439 = mac_fixpt_add_cast_1319 + mac_fixpt_add_cast_1321;
mac_fixpt_M_local_0[61] = mac_fixpt_add_temp_439[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_1331 = {1'b0, {mac_fixpt_M_local_0[61], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_447 = W[6];
end
else begin
mac_fixpt_t_447 = 14'b00000000000000;
end
mac_fixpt_add_cast_1332 = {1'b0, mac_fixpt_t_447};
mac_fixpt_add_cast_1333 = {1'b0, mac_fixpt_add_cast_1332};
mac_fixpt_add_temp_443 = mac_fixpt_add_cast_1331 + mac_fixpt_add_cast_1333;
mac_fixpt_M_local_0[61] = mac_fixpt_add_temp_443[14:1];
end
end
if (7'b0111111 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_1238 = {1'b0, {mac_fixpt_M_local_0[62], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_416 = W[0];
end
else begin
mac_fixpt_t_416 = 14'b00000000000000;
end
mac_fixpt_add_cast_1239 = {1'b0, mac_fixpt_t_416};
mac_fixpt_add_cast_1240 = {1'b0, mac_fixpt_add_cast_1239};
mac_fixpt_add_temp_412 = mac_fixpt_add_cast_1238 + mac_fixpt_add_cast_1240;
mac_fixpt_M_local_0[62] = mac_fixpt_add_temp_412[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_1262 = {1'b0, {mac_fixpt_M_local_0[62], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_424 = W[1];
end
else begin
mac_fixpt_t_424 = 14'b00000000000000;
end
mac_fixpt_add_cast_1263 = {1'b0, mac_fixpt_t_424};
mac_fixpt_add_cast_1264 = {1'b0, mac_fixpt_add_cast_1263};
mac_fixpt_add_temp_420 = mac_fixpt_add_cast_1262 + mac_fixpt_add_cast_1264;
mac_fixpt_M_local_0[62] = mac_fixpt_add_temp_420[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_1283 = {1'b0, {mac_fixpt_M_local_0[62], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_431 = W[2];
end
else begin
mac_fixpt_t_431 = 14'b00000000000000;
end
mac_fixpt_add_cast_1284 = {1'b0, mac_fixpt_t_431};
mac_fixpt_add_cast_1285 = {1'b0, mac_fixpt_add_cast_1284};
mac_fixpt_add_temp_427 = mac_fixpt_add_cast_1283 + mac_fixpt_add_cast_1285;
mac_fixpt_M_local_0[62] = mac_fixpt_add_temp_427[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_1301 = {1'b0, {mac_fixpt_M_local_0[62], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_437 = W[3];
end
else begin
mac_fixpt_t_437 = 14'b00000000000000;
end
mac_fixpt_add_cast_1302 = {1'b0, mac_fixpt_t_437};
mac_fixpt_add_cast_1303 = {1'b0, mac_fixpt_add_cast_1302};
mac_fixpt_add_temp_433 = mac_fixpt_add_cast_1301 + mac_fixpt_add_cast_1303;
mac_fixpt_M_local_0[62] = mac_fixpt_add_temp_433[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_1316 = {1'b0, {mac_fixpt_M_local_0[62], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_442 = W[4];
end
else begin
mac_fixpt_t_442 = 14'b00000000000000;
end
mac_fixpt_add_cast_1317 = {1'b0, mac_fixpt_t_442};
mac_fixpt_add_cast_1318 = {1'b0, mac_fixpt_add_cast_1317};
mac_fixpt_add_temp_438 = mac_fixpt_add_cast_1316 + mac_fixpt_add_cast_1318;
mac_fixpt_M_local_0[62] = mac_fixpt_add_temp_438[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_1328 = {1'b0, {mac_fixpt_M_local_0[62], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_446 = W[5];
end
else begin
mac_fixpt_t_446 = 14'b00000000000000;
end
mac_fixpt_add_cast_1329 = {1'b0, mac_fixpt_t_446};
mac_fixpt_add_cast_1330 = {1'b0, mac_fixpt_add_cast_1329};
mac_fixpt_add_temp_442 = mac_fixpt_add_cast_1328 + mac_fixpt_add_cast_1330;
mac_fixpt_M_local_0[62] = mac_fixpt_add_temp_442[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_1337 = {1'b0, {mac_fixpt_M_local_0[62], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_449 = W[6];
end
else begin
mac_fixpt_t_449 = 14'b00000000000000;
end
mac_fixpt_add_cast_1338 = {1'b0, mac_fixpt_t_449};
mac_fixpt_add_cast_1339 = {1'b0, mac_fixpt_add_cast_1338};
mac_fixpt_add_temp_445 = mac_fixpt_add_cast_1337 + mac_fixpt_add_cast_1339;
mac_fixpt_M_local_0[62] = mac_fixpt_add_temp_445[14:1];
end
end
if (7'b1000000 <= Tm) begin
if (3'b001 <= Tn) begin
mac_fixpt_add_cast_1259 = {1'b0, {mac_fixpt_M_local_0[63], 1'b0}};
if (N[0] == 1'b1) begin
mac_fixpt_t_423 = W[0];
end
else begin
mac_fixpt_t_423 = 14'b00000000000000;
end
mac_fixpt_add_cast_1260 = {1'b0, mac_fixpt_t_423};
mac_fixpt_add_cast_1261 = {1'b0, mac_fixpt_add_cast_1260};
mac_fixpt_add_temp_419 = mac_fixpt_add_cast_1259 + mac_fixpt_add_cast_1261;
mac_fixpt_M_local_0[63] = mac_fixpt_add_temp_419[14:1];
end
if (3'b010 <= Tn) begin
mac_fixpt_add_cast_1280 = {1'b0, {mac_fixpt_M_local_0[63], 1'b0}};
if (N[1] == 1'b1) begin
mac_fixpt_t_430 = W[1];
end
else begin
mac_fixpt_t_430 = 14'b00000000000000;
end
mac_fixpt_add_cast_1281 = {1'b0, mac_fixpt_t_430};
mac_fixpt_add_cast_1282 = {1'b0, mac_fixpt_add_cast_1281};
mac_fixpt_add_temp_426 = mac_fixpt_add_cast_1280 + mac_fixpt_add_cast_1282;
mac_fixpt_M_local_0[63] = mac_fixpt_add_temp_426[14:1];
end
if (3'b011 <= Tn) begin
mac_fixpt_add_cast_1298 = {1'b0, {mac_fixpt_M_local_0[63], 1'b0}};
if (N[2] == 1'b1) begin
mac_fixpt_t_436 = W[2];
end
else begin
mac_fixpt_t_436 = 14'b00000000000000;
end
mac_fixpt_add_cast_1299 = {1'b0, mac_fixpt_t_436};
mac_fixpt_add_cast_1300 = {1'b0, mac_fixpt_add_cast_1299};
mac_fixpt_add_temp_432 = mac_fixpt_add_cast_1298 + mac_fixpt_add_cast_1300;
mac_fixpt_M_local_0[63] = mac_fixpt_add_temp_432[14:1];
end
if (3'b100 <= Tn) begin
mac_fixpt_add_cast_1313 = {1'b0, {mac_fixpt_M_local_0[63], 1'b0}};
if (N[3] == 1'b1) begin
mac_fixpt_t_441 = W[3];
end
else begin
mac_fixpt_t_441 = 14'b00000000000000;
end
mac_fixpt_add_cast_1314 = {1'b0, mac_fixpt_t_441};
mac_fixpt_add_cast_1315 = {1'b0, mac_fixpt_add_cast_1314};
mac_fixpt_add_temp_437 = mac_fixpt_add_cast_1313 + mac_fixpt_add_cast_1315;
mac_fixpt_M_local_0[63] = mac_fixpt_add_temp_437[14:1];
end
if (3'b101 <= Tn) begin
mac_fixpt_add_cast_1325 = {1'b0, {mac_fixpt_M_local_0[63], 1'b0}};
if (N[4] == 1'b1) begin
mac_fixpt_t_445 = W[4];
end
else begin
mac_fixpt_t_445 = 14'b00000000000000;
end
mac_fixpt_add_cast_1326 = {1'b0, mac_fixpt_t_445};
mac_fixpt_add_cast_1327 = {1'b0, mac_fixpt_add_cast_1326};
mac_fixpt_add_temp_441 = mac_fixpt_add_cast_1325 + mac_fixpt_add_cast_1327;
mac_fixpt_M_local_0[63] = mac_fixpt_add_temp_441[14:1];
end
if (3'b110 <= Tn) begin
mac_fixpt_add_cast_1334 = {1'b0, {mac_fixpt_M_local_0[63], 1'b0}};
if (N[5] == 1'b1) begin
mac_fixpt_t_448 = W[5];
end
else begin
mac_fixpt_t_448 = 14'b00000000000000;
end
mac_fixpt_add_cast_1335 = {1'b0, mac_fixpt_t_448};
mac_fixpt_add_cast_1336 = {1'b0, mac_fixpt_add_cast_1335};
mac_fixpt_add_temp_444 = mac_fixpt_add_cast_1334 + mac_fixpt_add_cast_1336;
mac_fixpt_M_local_0[63] = mac_fixpt_add_temp_444[14:1];
end
if (3'b111 <= Tn) begin
mac_fixpt_add_cast_1340 = {1'b0, {mac_fixpt_M_local_0[63], 1'b0}};
if (N[6] == 1'b1) begin
mac_fixpt_t_450 = W[6];
end
else begin
mac_fixpt_t_450 = 14'b00000000000000;
end
mac_fixpt_add_cast_1341 = {1'b0, mac_fixpt_t_450};
mac_fixpt_add_cast_1342 = {1'b0, mac_fixpt_add_cast_1341};
mac_fixpt_add_temp_446 = mac_fixpt_add_cast_1340 + mac_fixpt_add_cast_1342;
mac_fixpt_M_local_0[63] = mac_fixpt_add_temp_446[14:1];
end
end
for(mac_fixpt_t_2 = 32'sd0; mac_fixpt_t_2 <= 32'sd63; mac_fixpt_t_2 = mac_fixpt_t_2 + 32'sd1) begin
M_out[mac_fixpt_t_2] = 14'b00000000000000;
end
M_out[0] = mac_fixpt_M_local_0[0];
M_out[1] = mac_fixpt_M_local_0[1];
M_out[2] = mac_fixpt_M_local_0[2];
M_out[3] = mac_fixpt_M_local_0[3];
M_out[4] = mac_fixpt_M_local_0[4];
M_out[5] = mac_fixpt_M_local_0[5];
M_out[6] = mac_fixpt_M_local_0[6];
M_out[7] = mac_fixpt_M_local_0[7];
M_out[8] = mac_fixpt_M_local_0[8];
M_out[9] = mac_fixpt_M_local_0[9];
M_out[10] = mac_fixpt_M_local_0[10];
M_out[11] = mac_fixpt_M_local_0[11];
M_out[12] = mac_fixpt_M_local_0[12];
M_out[13] = mac_fixpt_M_local_0[13];
M_out[14] = mac_fixpt_M_local_0[14];
M_out[15] = mac_fixpt_M_local_0[15];
M_out[16] = mac_fixpt_M_local_0[16];
M_out[17] = mac_fixpt_M_local_0[17];
M_out[18] = mac_fixpt_M_local_0[18];
M_out[19] = mac_fixpt_M_local_0[19];
M_out[20] = mac_fixpt_M_local_0[20];
M_out[21] = mac_fixpt_M_local_0[21];
M_out[22] = mac_fixpt_M_local_0[22];
M_out[23] = mac_fixpt_M_local_0[23];
M_out[24] = mac_fixpt_M_local_0[24];
M_out[25] = mac_fixpt_M_local_0[25];
M_out[26] = mac_fixpt_M_local_0[26];
M_out[27] = mac_fixpt_M_local_0[27];
M_out[28] = mac_fixpt_M_local_0[28];
M_out[29] = mac_fixpt_M_local_0[29];
M_out[30] = mac_fixpt_M_local_0[30];
M_out[31] = mac_fixpt_M_local_0[31];
M_out[32] = mac_fixpt_M_local_0[32];
M_out[33] = mac_fixpt_M_local_0[33];
M_out[34] = mac_fixpt_M_local_0[34];
M_out[35] = mac_fixpt_M_local_0[35];
M_out[36] = mac_fixpt_M_local_0[36];
M_out[37] = mac_fixpt_M_local_0[37];
M_out[38] = mac_fixpt_M_local_0[38];
M_out[39] = mac_fixpt_M_local_0[39];
M_out[40] = mac_fixpt_M_local_0[40];
M_out[41] = mac_fixpt_M_local_0[41];
M_out[42] = mac_fixpt_M_local_0[42];
M_out[43] = mac_fixpt_M_local_0[43];
M_out[44] = mac_fixpt_M_local_0[44];
M_out[45] = mac_fixpt_M_local_0[45];
M_out[46] = mac_fixpt_M_local_0[46];
M_out[47] = mac_fixpt_M_local_0[47];
M_out[48] = mac_fixpt_M_local_0[48];
M_out[49] = mac_fixpt_M_local_0[49];
M_out[50] = mac_fixpt_M_local_0[50];
M_out[51] = mac_fixpt_M_local_0[51];
M_out[52] = mac_fixpt_M_local_0[52];
M_out[53] = mac_fixpt_M_local_0[53];
M_out[54] = mac_fixpt_M_local_0[54];
M_out[55] = mac_fixpt_M_local_0[55];
M_out[56] = mac_fixpt_M_local_0[56];
M_out[57] = mac_fixpt_M_local_0[57];
M_out[58] = mac_fixpt_M_local_0[58];
M_out[59] = mac_fixpt_M_local_0[59];
M_out[60] = mac_fixpt_M_local_0[60];
M_out[61] = mac_fixpt_M_local_0[61];
M_out[62] = mac_fixpt_M_local_0[62];
M_out[63] = mac_fixpt_M_local_0[63];
end
assign M_out_0 = M_out[0];
assign M_out_1 = M_out[1];
assign M_out_2 = M_out[2];
assign M_out_3 = M_out[3];
assign M_out_4 = M_out[4];
assign M_out_5 = M_out[5];
assign M_out_6 = M_out[6];
assign M_out_7 = M_out[7];
assign M_out_8 = M_out[8];
assign M_out_9 = M_out[9];
assign M_out_10 = M_out[10];
assign M_out_11 = M_out[11];
assign M_out_12 = M_out[12];
assign M_out_13 = M_out[13];
assign M_out_14 = M_out[14];
assign M_out_15 = M_out[15];
assign M_out_16 = M_out[16];
assign M_out_17 = M_out[17];
assign M_out_18 = M_out[18];
assign M_out_19 = M_out[19];
assign M_out_20 = M_out[20];
assign M_out_21 = M_out[21];
assign M_out_22 = M_out[22];
assign M_out_23 = M_out[23];
assign M_out_24 = M_out[24];
assign M_out_25 = M_out[25];
assign M_out_26 = M_out[26];
assign M_out_27 = M_out[27];
assign M_out_28 = M_out[28];
assign M_out_29 = M_out[29];
assign M_out_30 = M_out[30];
assign M_out_31 = M_out[31];
assign M_out_32 = M_out[32];
assign M_out_33 = M_out[33];
assign M_out_34 = M_out[34];
assign M_out_35 = M_out[35];
assign M_out_36 = M_out[36];
assign M_out_37 = M_out[37];
assign M_out_38 = M_out[38];
assign M_out_39 = M_out[39];
assign M_out_40 = M_out[40];
assign M_out_41 = M_out[41];
assign M_out_42 = M_out[42];
assign M_out_43 = M_out[43];
assign M_out_44 = M_out[44];
assign M_out_45 = M_out[45];
assign M_out_46 = M_out[46];
assign M_out_47 = M_out[47];
assign M_out_48 = M_out[48];
assign M_out_49 = M_out[49];
assign M_out_50 = M_out[50];
assign M_out_51 = M_out[51];
assign M_out_52 = M_out[52];
assign M_out_53 = M_out[53];
assign M_out_54 = M_out[54];
assign M_out_55 = M_out[55];
assign M_out_56 = M_out[56];
assign M_out_57 = M_out[57];
assign M_out_58 = M_out[58];
assign M_out_59 = M_out[59];
assign M_out_60 = M_out[60];
assign M_out_61 = M_out[61];
assign M_out_62 = M_out[62];
assign M_out_63 = M_out[63];
endmodule // mac_fixpt
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:10:24 11/22/2016
// Design Name:
// Module Name: mouse_out
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module mouse_out(
input wire [9:0] mouse_x,
input wire [8:0] mouse_y,
input btnm,
output reg [4:0]code
);
reg [1:0] row;
reg [2:0] column;
always @(*)
begin
if (mouse_y >= 204 && mouse_y < 228) //fila 0
begin
row = 0;
end
else if(mouse_y >= 248 && mouse_y < 272) //fila 1
begin
row = 1;
end
else if(mouse_y >= 292 && mouse_y < 316) //fila 2
begin
row = 2; //ninguna fila
end
else
begin
row = 3;
end
if (mouse_x >= 220 && mouse_x < 244) //columna 0
begin
column = 0;
end
else if(mouse_x >= 264 && mouse_x < 288) //columna 1
begin
column = 1;
end
else if(mouse_x >= 308 && mouse_x < 332) //columna 2
begin
column = 2;
end
else if(mouse_x >= 352 && mouse_x < 376) //columna 3
begin
column = 3;
end
else if(mouse_x >= 396 && mouse_x < 420) //columna 4
begin
column = 4;
end
else if(mouse_x >= 440 && mouse_x < 462) //columna 5
begin
column = 5;
end
else //ninguna fila
begin
column = 6;
end
end
always @(*)
begin
if(btnm && row < 3 && column < 6)
begin
code = {(row * 6) + column}[4:0];
end
else
begin
code = 5'b10010;
end
end
endmodule
|
// altera message_off 10230 10036
`include "alt_mem_ddrx_define.iv"
`timescale 1 ps / 1 ps
module alt_mem_ddrx_tbp
#( parameter
CFG_CTL_TBP_NUM = 4,
CFG_CTL_SHADOW_TBP_NUM = 4,
CFG_ENABLE_SHADOW_TBP = 0,
CFG_DWIDTH_RATIO = 2,
CFG_CTL_ARBITER_TYPE = "ROWCOL",
CFG_MEM_IF_CHIP = 1, // one hot
CFG_MEM_IF_CS_WIDTH = 1, // binary encoded
CFG_MEM_IF_BA_WIDTH = 3,
CFG_MEM_IF_ROW_WIDTH = 13,
CFG_MEM_IF_COL_WIDTH = 10,
CFG_LOCAL_ID_WIDTH = 8,
CFG_INT_SIZE_WIDTH = 4,
CFG_DATA_ID_WIDTH = 10,
CFG_REG_REQ = 0,
CFG_REG_GRANT = 0,
CFG_DATA_REORDERING_TYPE = "INTER_BANK",
CFG_DISABLE_READ_REODERING = 0,
CFG_DISABLE_PRIORITY = 0,
CFG_PORT_WIDTH_REORDER_DATA = 1,
CFG_PORT_WIDTH_STARVE_LIMIT = 6,
CFG_PORT_WIDTH_TYPE = 3,
T_PARAM_ACT_TO_RDWR_WIDTH = 4,
T_PARAM_ACT_TO_ACT_WIDTH = 4,
T_PARAM_ACT_TO_PCH_WIDTH = 4,
T_PARAM_RD_TO_PCH_WIDTH = 4,
T_PARAM_WR_TO_PCH_WIDTH = 4,
T_PARAM_PCH_TO_VALID_WIDTH = 4,
T_PARAM_RD_AP_TO_VALID_WIDTH = 4,
T_PARAM_WR_AP_TO_VALID_WIDTH = 4
)
(
ctl_clk,
ctl_reset_n,
// Cmd gen interface
tbp_full,
tbp_empty,
cmd_gen_load,
cmd_gen_waiting_to_load,
cmd_gen_chipsel,
cmd_gen_bank,
cmd_gen_row,
cmd_gen_col,
cmd_gen_write,
cmd_gen_read,
cmd_gen_size,
cmd_gen_localid,
cmd_gen_dataid,
cmd_gen_priority,
cmd_gen_rmw_correct,
cmd_gen_rmw_partial,
cmd_gen_autopch,
cmd_gen_complete,
cmd_gen_same_chipsel_addr,
cmd_gen_same_bank_addr,
cmd_gen_same_row_addr,
cmd_gen_same_col_addr,
cmd_gen_same_read_cmd,
cmd_gen_same_write_cmd,
cmd_gen_same_shadow_chipsel_addr,
cmd_gen_same_shadow_bank_addr,
cmd_gen_same_shadow_row_addr,
// Arbiter interface
row_req,
act_req,
pch_req,
row_grant,
act_grant,
pch_grant,
col_req,
rd_req,
wr_req,
col_grant,
rd_grant,
wr_grant,
log2_row_grant,
log2_col_grant,
log2_act_grant,
log2_pch_grant,
log2_rd_grant,
log2_wr_grant,
or_row_grant,
or_col_grant,
tbp_read,
tbp_write,
tbp_precharge,
tbp_activate,
tbp_chipsel,
tbp_bank,
tbp_row,
tbp_col,
tbp_shadow_chipsel,
tbp_shadow_bank,
tbp_shadow_row,
tbp_size,
tbp_localid,
tbp_dataid,
tbp_ap,
tbp_burst_chop,
tbp_age,
tbp_priority,
tbp_rmw_correct,
tbp_rmw_partial,
sb_tbp_precharge_all,
sb_do_precharge_all,
// Timer value
t_param_act_to_rdwr,
t_param_act_to_act,
t_param_act_to_pch,
t_param_rd_to_pch,
t_param_wr_to_pch,
t_param_pch_to_valid,
t_param_rd_ap_to_valid,
t_param_wr_ap_to_valid,
// Misc interface
tbp_bank_closed,
tbp_timer_ready,
tbp_load,
data_complete,
data_rmw_complete,
data_rmw_fetch,
// Config interface
cfg_reorder_data,
cfg_starve_limit,
cfg_type,
cfg_enable_ecc,
cfg_enable_no_dm
);
localparam integer CFG_MEM_IF_BA_WIDTH_SQRD = 2**CFG_MEM_IF_BA_WIDTH;
localparam TBP_COUNTER_OFFSET = (CFG_REG_GRANT) ? 2 : 1;
localparam RDWR_AP_TO_VALID_WIDTH = (T_PARAM_RD_AP_TO_VALID_WIDTH > T_PARAM_WR_AP_TO_VALID_WIDTH) ? T_PARAM_RD_AP_TO_VALID_WIDTH : T_PARAM_WR_AP_TO_VALID_WIDTH;
localparam COL_TIMER_WIDTH = T_PARAM_ACT_TO_RDWR_WIDTH;
localparam ROW_TIMER_WIDTH = (T_PARAM_ACT_TO_ACT_WIDTH > RDWR_AP_TO_VALID_WIDTH) ? T_PARAM_ACT_TO_ACT_WIDTH : RDWR_AP_TO_VALID_WIDTH;
localparam TRC_TIMER_WIDTH = T_PARAM_ACT_TO_ACT_WIDTH;
localparam COMBINED_TIMER_WIDTH = (ROW_TIMER_WIDTH > TRC_TIMER_WIDTH) ? ROW_TIMER_WIDTH : TRC_TIMER_WIDTH;
// Start of port declaration
input ctl_clk;
input ctl_reset_n;
output tbp_full;
output tbp_empty;
input cmd_gen_load;
input cmd_gen_waiting_to_load;
input [CFG_MEM_IF_CS_WIDTH-1:0] cmd_gen_chipsel;
input [CFG_MEM_IF_BA_WIDTH-1:0] cmd_gen_bank;
input [CFG_MEM_IF_ROW_WIDTH-1:0] cmd_gen_row;
input [CFG_MEM_IF_COL_WIDTH-1:0] cmd_gen_col;
input cmd_gen_write;
input cmd_gen_read;
input [CFG_INT_SIZE_WIDTH-1:0] cmd_gen_size;
input [CFG_LOCAL_ID_WIDTH-1:0] cmd_gen_localid;
input [CFG_DATA_ID_WIDTH-1:0] cmd_gen_dataid;
input cmd_gen_priority;
input cmd_gen_rmw_correct;
input cmd_gen_rmw_partial;
input cmd_gen_autopch;
input cmd_gen_complete;
input [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_chipsel_addr;
input [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_bank_addr;
input [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_row_addr;
input [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_col_addr;
input [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_read_cmd;
input [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_write_cmd;
input [CFG_CTL_SHADOW_TBP_NUM-1:0] cmd_gen_same_shadow_chipsel_addr;
input [CFG_CTL_SHADOW_TBP_NUM-1:0] cmd_gen_same_shadow_bank_addr;
input [CFG_CTL_SHADOW_TBP_NUM-1:0] cmd_gen_same_shadow_row_addr;
output [CFG_CTL_TBP_NUM-1:0] row_req;
output [CFG_CTL_TBP_NUM-1:0] act_req;
output [CFG_CTL_TBP_NUM-1:0] pch_req;
input [CFG_CTL_TBP_NUM-1:0] row_grant;
input [CFG_CTL_TBP_NUM-1:0] act_grant;
input [CFG_CTL_TBP_NUM-1:0] pch_grant;
output [CFG_CTL_TBP_NUM-1:0] col_req;
output [CFG_CTL_TBP_NUM-1:0] rd_req;
output [CFG_CTL_TBP_NUM-1:0] wr_req;
input [CFG_CTL_TBP_NUM-1:0] col_grant;
input [CFG_CTL_TBP_NUM-1:0] rd_grant;
input [CFG_CTL_TBP_NUM-1:0] wr_grant;
input [log2(CFG_CTL_TBP_NUM)-1:0] log2_row_grant;
input [log2(CFG_CTL_TBP_NUM)-1:0] log2_col_grant;
input [log2(CFG_CTL_TBP_NUM)-1:0] log2_act_grant;
input [log2(CFG_CTL_TBP_NUM)-1:0] log2_pch_grant;
input [log2(CFG_CTL_TBP_NUM)-1:0] log2_rd_grant;
input [log2(CFG_CTL_TBP_NUM)-1:0] log2_wr_grant;
input or_row_grant;
input or_col_grant;
output [CFG_CTL_TBP_NUM-1:0] tbp_read;
output [CFG_CTL_TBP_NUM-1:0] tbp_write;
output [CFG_CTL_TBP_NUM-1:0] tbp_precharge;
output [CFG_CTL_TBP_NUM-1:0] tbp_activate;
output [(CFG_CTL_TBP_NUM*CFG_MEM_IF_CS_WIDTH)-1:0] tbp_chipsel;
output [(CFG_CTL_TBP_NUM*CFG_MEM_IF_BA_WIDTH)-1:0] tbp_bank;
output [(CFG_CTL_TBP_NUM*CFG_MEM_IF_ROW_WIDTH)-1:0] tbp_row;
output [(CFG_CTL_TBP_NUM*CFG_MEM_IF_COL_WIDTH)-1:0] tbp_col;
output [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_CS_WIDTH)-1:0] tbp_shadow_chipsel;
output [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_BA_WIDTH)-1:0] tbp_shadow_bank;
output [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_ROW_WIDTH)-1:0] tbp_shadow_row;
output [(CFG_CTL_TBP_NUM*CFG_INT_SIZE_WIDTH)-1:0] tbp_size;
output [(CFG_CTL_TBP_NUM*CFG_LOCAL_ID_WIDTH)-1:0] tbp_localid;
output [(CFG_CTL_TBP_NUM*CFG_DATA_ID_WIDTH)-1:0] tbp_dataid;
output [CFG_CTL_TBP_NUM-1:0] tbp_ap;
output [CFG_CTL_TBP_NUM-1:0] tbp_burst_chop;
output [(CFG_CTL_TBP_NUM*CFG_CTL_TBP_NUM)-1:0] tbp_age;
output [CFG_CTL_TBP_NUM-1:0] tbp_priority;
output [CFG_CTL_TBP_NUM-1:0] tbp_rmw_correct;
output [CFG_CTL_TBP_NUM-1:0] tbp_rmw_partial;
input [CFG_CTL_TBP_NUM-1:0] sb_tbp_precharge_all;
input [CFG_MEM_IF_CHIP-1:0] sb_do_precharge_all;
input [T_PARAM_ACT_TO_RDWR_WIDTH-1:0] t_param_act_to_rdwr;
input [T_PARAM_ACT_TO_ACT_WIDTH-1:0] t_param_act_to_act;
input [T_PARAM_ACT_TO_PCH_WIDTH-1:0] t_param_act_to_pch;
input [T_PARAM_RD_TO_PCH_WIDTH-1:0] t_param_rd_to_pch;
input [T_PARAM_WR_TO_PCH_WIDTH-1:0] t_param_wr_to_pch;
input [T_PARAM_PCH_TO_VALID_WIDTH-1:0] t_param_pch_to_valid;
input [T_PARAM_RD_AP_TO_VALID_WIDTH-1:0] t_param_rd_ap_to_valid;
input [T_PARAM_WR_AP_TO_VALID_WIDTH-1:0] t_param_wr_ap_to_valid;
output [CFG_MEM_IF_CHIP-1:0] tbp_bank_closed;
output [CFG_MEM_IF_CHIP-1:0] tbp_timer_ready;
output [CFG_CTL_TBP_NUM-1:0] tbp_load;
input [CFG_CTL_TBP_NUM-1:0] data_complete;
input data_rmw_complete;
output data_rmw_fetch;
input [CFG_PORT_WIDTH_REORDER_DATA-1:0] cfg_reorder_data;
input [CFG_PORT_WIDTH_STARVE_LIMIT-1:0] cfg_starve_limit;
input [CFG_PORT_WIDTH_TYPE-1:0] cfg_type;
input cfg_enable_ecc;
input cfg_enable_no_dm;
// End of port declaration
// Logic operators
wire tbp_full;
wire tbp_empty;
wire [CFG_CTL_TBP_NUM-1:0] tbp_load;
wire [CFG_CTL_TBP_NUM-1:0] load_tbp;
reg [CFG_CTL_TBP_NUM-1:0] load_tbp_index;
wire [CFG_CTL_TBP_NUM-1:0] flush_tbp;
reg [CFG_CTL_TBP_NUM-1:0] precharge_tbp;
reg [CFG_CTL_TBP_NUM-1:0] row_req;
reg [CFG_CTL_TBP_NUM-1:0] act_req;
reg [CFG_CTL_TBP_NUM-1:0] pch_req;
reg [CFG_CTL_TBP_NUM-1:0] col_req;
reg [CFG_CTL_TBP_NUM-1:0] rd_req;
reg [CFG_CTL_TBP_NUM-1:0] wr_req;
wire cfg_enable_rmw;
reg int_tbp_full;
wire int_tbp_empty;
reg [CFG_CTL_TBP_NUM-1:0] valid;
wire [CFG_CTL_TBP_NUM-1:0] valid_combi;
reg [CFG_MEM_IF_CS_WIDTH-1:0] chipsel [CFG_CTL_TBP_NUM-1:0];
reg [CFG_MEM_IF_BA_WIDTH-1:0] bank [CFG_CTL_TBP_NUM-1:0];
reg [CFG_MEM_IF_ROW_WIDTH-1:0] row [CFG_CTL_TBP_NUM-1:0];
reg [CFG_MEM_IF_COL_WIDTH-1:0] col [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] write;
reg [CFG_CTL_TBP_NUM-1:0] read;
wire [CFG_CTL_TBP_NUM-1:0] precharge;
wire [CFG_CTL_TBP_NUM-1:0] activate;
reg [CFG_INT_SIZE_WIDTH-1:0] size [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] autopch;
reg [CFG_LOCAL_ID_WIDTH-1:0] localid [CFG_CTL_TBP_NUM-1:0];
reg [CFG_DATA_ID_WIDTH-1:0] dataid [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] priority_a;
reg [CFG_CTL_TBP_NUM-1:0] activated;
reg [CFG_CTL_TBP_NUM-1:0] activated_p;
reg [CFG_CTL_TBP_NUM-1:0] activated_combi;
reg [CFG_CTL_TBP_NUM-1:0] precharged;
reg [CFG_CTL_TBP_NUM-1:0] precharged_combi;
reg [CFG_CTL_TBP_NUM-1:0] not_done_tbp_row_pass_flush;
reg [CFG_CTL_TBP_NUM-1:0] not_done_tbp_row_pass_flush_r;
reg [CFG_CTL_TBP_NUM-1:0] done_tbp_row_pass_flush;
reg [CFG_CTL_TBP_NUM-1:0] done_tbp_row_pass_flush_r;
reg [CFG_CTL_TBP_NUM-1:0] open_row_pass;
reg [CFG_CTL_TBP_NUM-1:0] open_row_pass_r;
reg [CFG_CTL_TBP_NUM-1:0] open_row_passed;
wire [CFG_CTL_TBP_NUM-1:0] open_row_pass_flush;
reg [CFG_CTL_TBP_NUM-1:0] open_row_pass_flush_r;
reg [CFG_CTL_TBP_NUM-1:0] log2_open_row_pass_flush [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] log2_open_row_pass_flush_r [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] done;
reg [CFG_CTL_TBP_NUM-1:0] done_combi;
reg [CFG_CTL_TBP_NUM-1:0] complete;
reg [CFG_CTL_TBP_NUM-1:0] complete_rd;
reg [CFG_CTL_TBP_NUM-1:0] complete_wr;
reg [CFG_CTL_TBP_NUM-1:0] complete_combi;
reg [CFG_CTL_TBP_NUM-1:0] complete_combi_rd;
reg [CFG_CTL_TBP_NUM-1:0] complete_combi_wr;
reg [CFG_CTL_TBP_NUM-1:0] wst;
reg [CFG_CTL_TBP_NUM-1:0] wst_p;
reg [CFG_CTL_TBP_NUM-1:0] ssb;
reg [CFG_CTL_TBP_NUM-1:0] ssbr;
reg [CFG_CTL_TBP_NUM-1:0] ap;
reg [CFG_CTL_TBP_NUM-1:0] real_ap;
reg [CFG_CTL_TBP_NUM-1:0] rmw_correct;
reg [CFG_CTL_TBP_NUM-1:0] rmw_partial;
reg [CFG_CTL_TBP_NUM-1:0] rmw;
reg [CFG_CTL_TBP_NUM-1:0] require_flush;
reg [CFG_CTL_TBP_NUM-1:0] require_flush_calc;
reg [CFG_CTL_TBP_NUM-1:0] require_pch_combi [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] require_pch;
reg [CFG_CTL_TBP_NUM-1:0] burst_chop;
reg [CFG_CTL_TBP_NUM-1:0] age [CFG_CTL_TBP_NUM-1:0];
reg [CFG_PORT_WIDTH_STARVE_LIMIT-1:0] starvation [CFG_CTL_TBP_NUM-1:0];
// bit vectors
reg [CFG_CTL_TBP_NUM-1:0] apvo_combi; // vector for smart autopch open page
reg [CFG_CTL_TBP_NUM-1:0] apvo; // vector for smart autopch open page
reg [CFG_CTL_TBP_NUM-1:0] apvc_combi; // vector for smart autopch close page
reg [CFG_CTL_TBP_NUM-1:0] apvc; // vector for smart autopch close page
reg [CFG_CTL_TBP_NUM-1:0] rpv_combi [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] rpv [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] cpv_combi [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] cpv [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] wrt_combi [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] wrt [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] sbv_combi [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] sbv [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] sbvt_combi [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] sbvt [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] shadow_rpv_combi [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] shadow_rpv [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] shadow_sbvt_combi [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] shadow_sbvt [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] or_wrt;
reg [CFG_CTL_TBP_NUM-1:0] nor_rpv;
reg [CFG_CTL_TBP_NUM-1:0] nor_cpv;
reg [CFG_CTL_TBP_NUM-1:0] nor_wrt;
reg [CFG_CTL_TBP_NUM-1:0] nor_sbv;
reg [CFG_CTL_TBP_NUM-1:0] nor_sbvt;
wire [CFG_CTL_TBP_NUM-1:0] tbp_read;
wire [CFG_CTL_TBP_NUM-1:0] tbp_write;
wire [CFG_CTL_TBP_NUM-1:0] tbp_ap;
wire [(CFG_CTL_TBP_NUM*CFG_MEM_IF_CS_WIDTH)-1:0] tbp_chipsel;
wire [(CFG_CTL_TBP_NUM*CFG_MEM_IF_BA_WIDTH)-1:0] tbp_bank;
wire [(CFG_CTL_TBP_NUM*CFG_MEM_IF_ROW_WIDTH)-1:0] tbp_row;
wire [(CFG_CTL_TBP_NUM*CFG_MEM_IF_COL_WIDTH)-1:0] tbp_col;
wire [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_CS_WIDTH)-1:0] tbp_shadow_chipsel;
wire [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_BA_WIDTH)-1:0] tbp_shadow_bank;
wire [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_ROW_WIDTH)-1:0] tbp_shadow_row;
wire [(CFG_CTL_TBP_NUM*CFG_INT_SIZE_WIDTH)-1:0] tbp_size;
wire [(CFG_CTL_TBP_NUM*CFG_LOCAL_ID_WIDTH)-1:0] tbp_localid;
wire [(CFG_CTL_TBP_NUM*CFG_DATA_ID_WIDTH)-1:0] tbp_dataid;
wire [(CFG_CTL_TBP_NUM*CFG_CTL_TBP_NUM)-1:0] tbp_age;
wire [CFG_CTL_TBP_NUM-1:0] tbp_priority;
wire [CFG_CTL_TBP_NUM-1:0] tbp_rmw_correct;
wire [CFG_CTL_TBP_NUM-1:0] tbp_rmw_partial;
wire [CFG_MEM_IF_CHIP-1:0] tbp_bank_closed;
wire [CFG_MEM_IF_CHIP-1:0] tbp_timer_ready;
reg [CFG_MEM_IF_CHIP-1:0] bank_closed;
reg [CFG_MEM_IF_CHIP-1:0] timer_ready;
reg [CFG_CTL_TBP_NUM-1:0] int_bank_closed [CFG_MEM_IF_CHIP-1:0];
reg [CFG_CTL_TBP_NUM-1:0] int_timer_ready [CFG_MEM_IF_CHIP-1:0];
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] int_shadow_timer_ready [CFG_MEM_IF_CHIP-1:0];
reg [CFG_CTL_TBP_NUM-1:0] same_command_read;
reg [CFG_CTL_TBP_NUM-1:0] same_chip_bank_row;
reg [CFG_CTL_TBP_NUM-1:0] same_chip_bank_diff_row;
reg [CFG_CTL_TBP_NUM-1:0] same_chip_bank;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] same_shadow_command_read;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] same_shadow_chip_bank_row;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] same_shadow_chip_bank_diff_row;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] same_shadow_chip_bank;
reg [CFG_CTL_TBP_NUM-1:0] pre_calculated_same_chip_bank_diff_row [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] pre_calculated_same_chip_bank_row [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] pre_calculated_same_chip_bank [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] pre_calculated_same_shadow_chip_bank [CFG_CTL_TBP_NUM-1:0];
reg [COL_TIMER_WIDTH-1:0] col_timer [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] col_timer_ready;
reg [CFG_CTL_TBP_NUM-1:0] col_timer_pre_ready;
reg [COMBINED_TIMER_WIDTH-1:0] combined_timer [CFG_CTL_TBP_NUM-1:0];
reg [ROW_TIMER_WIDTH-1:0] row_timer_combi [CFG_CTL_TBP_NUM-1:0];
reg [ROW_TIMER_WIDTH-1:0] row_timer [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] row_timer_ready;
reg [CFG_CTL_TBP_NUM-1:0] row_timer_pre_ready;
reg [TRC_TIMER_WIDTH-1:0] trc_timer [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] trc_timer_ready;
reg [CFG_CTL_TBP_NUM-1:0] trc_timer_pre_ready;
reg [CFG_CTL_TBP_NUM-1:0] trc_timer_pre_ready_combi;
reg [CFG_CTL_TBP_NUM-1:0] pch_ready;
reg [CFG_CTL_TBP_NUM-1:0] compare_t_param_rd_to_pch_greater_than_row_timer;
reg [CFG_CTL_TBP_NUM-1:0] compare_t_param_wr_to_pch_greater_than_row_timer;
reg compare_t_param_act_to_rdwr_less_than_offset;
reg compare_t_param_act_to_act_less_than_offset;
reg compare_t_param_act_to_pch_less_than_offset;
reg compare_t_param_rd_to_pch_less_than_offset;
reg compare_t_param_wr_to_pch_less_than_offset;
reg compare_t_param_pch_to_valid_less_than_offset;
reg compare_t_param_rd_ap_to_valid_less_than_offset;
reg compare_t_param_wr_ap_to_valid_less_than_offset;
reg compare_offset_t_param_act_to_rdwr_less_than_0;
reg compare_offset_t_param_act_to_rdwr_less_than_1;
reg [T_PARAM_ACT_TO_RDWR_WIDTH-1:0] offset_t_param_act_to_rdwr;
reg [T_PARAM_ACT_TO_ACT_WIDTH-1:0] offset_t_param_act_to_act;
reg [T_PARAM_ACT_TO_PCH_WIDTH-1:0] offset_t_param_act_to_pch;
reg [T_PARAM_RD_TO_PCH_WIDTH-1:0] offset_t_param_rd_to_pch;
reg [T_PARAM_WR_TO_PCH_WIDTH-1:0] offset_t_param_wr_to_pch;
reg [T_PARAM_PCH_TO_VALID_WIDTH-1:0] offset_t_param_pch_to_valid;
reg [T_PARAM_RD_AP_TO_VALID_WIDTH-1:0] offset_t_param_rd_ap_to_valid;
reg [T_PARAM_WR_AP_TO_VALID_WIDTH-1:0] offset_t_param_wr_ap_to_valid;
reg [CFG_CTL_TBP_NUM-1:0] can_act;
reg [CFG_CTL_TBP_NUM-1:0] can_pch;
reg [CFG_CTL_TBP_NUM-1:0] can_rd;
reg [CFG_CTL_TBP_NUM-1:0] can_wr;
reg [CFG_CTL_TBP_NUM-1:0] finish_tbp;
wire [CFG_CTL_SHADOW_TBP_NUM-1:0] flush_shadow_tbp;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] push_tbp_combi;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] push_tbp;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] ready_to_push_tbp_combi;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] ready_to_push_tbp;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] shadow_valid;
reg [CFG_MEM_IF_CS_WIDTH-1:0] shadow_chipsel [CFG_CTL_SHADOW_TBP_NUM-1:0];
reg [CFG_MEM_IF_BA_WIDTH-1:0] shadow_bank [CFG_CTL_SHADOW_TBP_NUM-1:0];
reg [CFG_MEM_IF_ROW_WIDTH-1:0] shadow_row [CFG_CTL_SHADOW_TBP_NUM-1:0];
reg [ROW_TIMER_WIDTH-1:0] shadow_row_timer [CFG_CTL_SHADOW_TBP_NUM-1:0];
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] shadow_row_timer_pre_ready;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] shadow_row_timer_ready;
wire one = 1'b1;
wire zero = 1'b0;
integer i;
integer j;
genvar k;
//----------------------------------------------------------------------------------------------------
// Output port assignments
//----------------------------------------------------------------------------------------------------
assign tbp_read = read;
assign tbp_write = write;
assign tbp_ap = real_ap;
assign tbp_burst_chop = burst_chop;
assign tbp_precharge = precharge;
assign tbp_activate = activate;
assign tbp_priority = priority_a;
assign tbp_rmw_correct = rmw_correct;
assign tbp_rmw_partial = rmw_partial;
generate
begin
for(k=0; k<CFG_CTL_TBP_NUM; k=k+1)
begin : tbp_name
assign tbp_chipsel[(k*CFG_MEM_IF_CS_WIDTH)+CFG_MEM_IF_CS_WIDTH-1:k*CFG_MEM_IF_CS_WIDTH] = chipsel[k];
assign tbp_bank [(k*CFG_MEM_IF_BA_WIDTH)+CFG_MEM_IF_BA_WIDTH-1:k*CFG_MEM_IF_BA_WIDTH] = bank [k];
assign tbp_row [(k*CFG_MEM_IF_ROW_WIDTH)+CFG_MEM_IF_ROW_WIDTH-1:k*CFG_MEM_IF_ROW_WIDTH] = row [k];
assign tbp_col [(k*CFG_MEM_IF_COL_WIDTH)+CFG_MEM_IF_COL_WIDTH-1:k*CFG_MEM_IF_COL_WIDTH] = col [k];
assign tbp_localid[(k*CFG_LOCAL_ID_WIDTH)+CFG_LOCAL_ID_WIDTH-1:k*CFG_LOCAL_ID_WIDTH] = localid[k];
assign tbp_dataid [(k*CFG_DATA_ID_WIDTH)+CFG_DATA_ID_WIDTH-1:k*CFG_DATA_ID_WIDTH] = dataid [k];
assign tbp_age [(k*CFG_CTL_TBP_NUM)+CFG_CTL_TBP_NUM-1:k*CFG_CTL_TBP_NUM] = age [k];
assign tbp_size [(k*CFG_INT_SIZE_WIDTH)+CFG_INT_SIZE_WIDTH-1:k*CFG_INT_SIZE_WIDTH] = size [k];
end
for(k=0; k<CFG_CTL_SHADOW_TBP_NUM; k=k+1)
begin : tbp_shadow_name
if (CFG_ENABLE_SHADOW_TBP)
begin
assign tbp_shadow_chipsel[(k*CFG_MEM_IF_CS_WIDTH)+CFG_MEM_IF_CS_WIDTH-1:k*CFG_MEM_IF_CS_WIDTH] = shadow_chipsel[k];
assign tbp_shadow_bank [(k*CFG_MEM_IF_BA_WIDTH)+CFG_MEM_IF_BA_WIDTH-1:k*CFG_MEM_IF_BA_WIDTH] = shadow_bank [k];
assign tbp_shadow_row [(k*CFG_MEM_IF_ROW_WIDTH)+CFG_MEM_IF_ROW_WIDTH-1:k*CFG_MEM_IF_ROW_WIDTH] = shadow_row [k];
end
else
begin
assign tbp_shadow_chipsel[(k*CFG_MEM_IF_CS_WIDTH)+CFG_MEM_IF_CS_WIDTH-1:k*CFG_MEM_IF_CS_WIDTH] = 0;
assign tbp_shadow_bank [(k*CFG_MEM_IF_BA_WIDTH)+CFG_MEM_IF_BA_WIDTH-1:k*CFG_MEM_IF_BA_WIDTH] = 0;
assign tbp_shadow_row [(k*CFG_MEM_IF_ROW_WIDTH)+CFG_MEM_IF_ROW_WIDTH-1:k*CFG_MEM_IF_ROW_WIDTH] = 0;
end
end
end
endgenerate
assign tbp_full = int_tbp_full;
assign tbp_empty = int_tbp_empty;
assign int_tbp_empty = &(valid ^~ done); // empty if valid and done are the same
assign load_tbp = (~int_tbp_full & cmd_gen_load) ? load_tbp_index : 0;
assign flush_tbp = open_row_pass_flush_r | finish_tbp | (done & precharge_tbp);
assign tbp_load = load_tbp;
assign tbp_bank_closed = bank_closed;
assign tbp_timer_ready = timer_ready;
assign precharge = activated;
assign activate = ~activated;
//----------------------------------------------------------------------------------------------------
// TBP General Functions
//----------------------------------------------------------------------------------------------------
assign cfg_enable_rmw = cfg_enable_ecc | cfg_enable_no_dm;
assign valid_combi = (valid | load_tbp) & ~flush_tbp;
// Decide which TBP to load
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
load_tbp_index <= 0;
end
else
begin
load_tbp_index <= ~valid_combi & (valid_combi + 1);
end
end
// Assert when TBP is full to prevent further load
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_tbp_full <= 0;
end
else
begin
int_tbp_full <= &valid_combi;
end
end
//----------------------------------------------------------------------------------------------------
// Finish TBP
//----------------------------------------------------------------------------------------------------
// Logic to determine when can we flush a done TBP
// in non-shadow TBP case, we can only flush once the timer finished counting
// in shadow TBP case, we can flush once it is pushed into shadow TBP
always @ (*)
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
if (CFG_ENABLE_SHADOW_TBP)
begin
finish_tbp[i] = push_tbp[i] | (done[i] & precharged[i] & row_timer_pre_ready[i] & trc_timer_pre_ready[i]);
end
else
begin
finish_tbp[i] = done[i] & precharged[i] & row_timer_pre_ready[i] & trc_timer_pre_ready[i];
end
end
end
//----------------------------------------------------------------------------------------------------
// Shadow TBP Logic
//----------------------------------------------------------------------------------------------------
// Determine when can we flush TBP
assign flush_shadow_tbp = shadow_valid & shadow_row_timer_pre_ready;
// Determine when it's ready to push into shadow TBP
always @ (*)
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
if (CFG_ENABLE_SHADOW_TBP)
begin
if (flush_tbp[i]) // TBP might flush before shadow TBP is still allocated
begin
ready_to_push_tbp_combi[i] = 1'b0;
end
else if (push_tbp[i]) // we want push_tbp to pulse for one clock cycle only
begin
ready_to_push_tbp_combi[i] = 1'b0;
end
else if ((col_grant[i] && real_ap[i]) || (pch_grant[i] && done[i])) // indicate ready to push TBP once TBP is done
begin
ready_to_push_tbp_combi[i] = 1'b1;
end
else
begin
ready_to_push_tbp_combi[i] = ready_to_push_tbp[i];
end
end
else
begin
ready_to_push_tbp_combi[i] = zero;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
ready_to_push_tbp[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
ready_to_push_tbp[i] <= ready_to_push_tbp_combi[i];
end
end
end
// Determine when to push into shadow TBP
always @ (*)
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
if (CFG_ENABLE_SHADOW_TBP)
begin
if (push_tbp[i]) // we want push_tbp to pulse for one clock cycle only
begin
push_tbp_combi[i] = 1'b0;
end
else if (ready_to_push_tbp_combi[i] && shadow_row_timer_pre_ready[i]) // prevent pushing into an allocated shadow TBP
begin
push_tbp_combi[i] = 1'b1;
end
else
begin
push_tbp_combi[i] = push_tbp[i];
end
end
else
begin
push_tbp_combi[i] = zero;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
push_tbp[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
push_tbp[i] <= push_tbp_combi[i];
end
end
end
// Shadow TBP information
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
shadow_chipsel[i] <= 0;
shadow_bank [i] <= 0;
shadow_row [i] <= 0;
end
end
else
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
if (CFG_ENABLE_SHADOW_TBP)
begin
if (push_tbp_combi[i])
begin
shadow_chipsel[i] <= chipsel[i];
shadow_bank [i] <= bank [i];
shadow_row [i] <= row [i];
end
end
else
begin
shadow_chipsel[i] <= 0;
shadow_bank [i] <= 0;
shadow_row [i] <= 0;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
shadow_valid[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
if (CFG_ENABLE_SHADOW_TBP)
begin
if (flush_shadow_tbp[i])
begin
shadow_valid[i] <= 1'b0;
end
else if (push_tbp[i])
begin
shadow_valid[i] <= 1'b1;
end
end
else
begin
shadow_valid[i] <= 1'b0;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
shadow_row_timer [i] <= 0;
shadow_row_timer_pre_ready[i] <= 1'b0;
shadow_row_timer_ready [i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
if (CFG_ENABLE_SHADOW_TBP)
begin
if (push_tbp[i])
begin
if (!row_timer_pre_ready[i] || !trc_timer_pre_ready[i])
begin
// Decide to take the larger timer value between row/trc timer
if (row_timer[i] > trc_timer[i])
begin
shadow_row_timer[i] <= row_timer[i] - 1'b1;
end
else
begin
shadow_row_timer[i] <= trc_timer[i] - 1'b1;
end
shadow_row_timer_pre_ready[i] <= 1'b0;
shadow_row_timer_ready [i] <= 1'b0;
end
else
begin
shadow_row_timer [i] <= 0;
shadow_row_timer_pre_ready[i] <= 1'b1;
shadow_row_timer_ready [i] <= 1'b1;
end
end
else
begin
if (shadow_row_timer[i] != 0)
begin
shadow_row_timer[i] <= shadow_row_timer[i] - 1'b1;
end
if (shadow_row_timer[i] <= 1)
begin
shadow_row_timer_ready[i] <= 1'b1;
end
if (shadow_row_timer[i] <= 2)
begin
shadow_row_timer_pre_ready[i] <= 1'b1;
end
end
end
else
begin
shadow_row_timer [i] <= 0;
shadow_row_timer_pre_ready[i] <= 1'b0;
shadow_row_timer_ready [i] <= 1'b0;
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Request logic
//----------------------------------------------------------------------------------------------------
// Can_* logic for request logic, indicate whether TBP can request now
// Can activate
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
can_act[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (activated_combi[i]) // activated, so there is no need to enable activate again
begin
can_act[i] <= 1'b0;
end
else if (col_grant[i]) //done, there is no need to enable activate again
begin
can_act[i] <= 1'b0;
end
else if (load_tbp[i]) // new TBP command, assume no open-row-pass (handled by statement above)
begin
can_act[i] <= 1'b1;
end
else if
(
!done[i] && valid[i] &&
(
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW" && (precharge_tbp[i] || pch_grant[i])) ||
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && (precharge_tbp[i] )) ||
(!cfg_reorder_data && precharge_tbp[i])
)
)
// precharge or precharge all command, re-enable since it is not done
// (INTER_ROW) we need to validate pch_grant because precharge might happen to a newly loaded TBP due to TBP interlock case (see require_pch logic)
begin
can_act[i] <= 1'b1;
end
end
end
end
// Can precharge
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
can_pch[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
can_pch[i] <= one; // there is no logic required for precharge, keeping this for future use
end
end
end
// Can read
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
can_rd[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (col_grant[i] || done[i]) // done, there is no need to enable read again
begin
can_rd[i] <= 1'b0;
end
else if
(
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW" && (precharge_tbp[i] || pch_grant[i])) ||
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && (precharge_tbp[i] )) ||
(!cfg_reorder_data && precharge_tbp[i])
)
// precharge or precharge all command, can't read since bank is not active
// (INTER_ROW) we need to validate pch_grant because precharge might happen to a newly loaded TBP due to TBP interlock case (see require_pch logic)
begin
can_rd[i] <= 1'b0;
end
else if (((act_grant[i] && compare_t_param_act_to_rdwr_less_than_offset) || open_row_pass[i] || activated[i]) && col_timer_pre_ready[i]) // activated and timer is ready
begin
can_rd[i] <= 1'b1;
end
end
end
end
// Can write
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
can_wr[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (col_grant[i] || done[i]) // done, there is no need to enable read again
begin
can_wr[i] <= 1'b0;
end
else if
(
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW" && (precharge_tbp[i] || pch_grant[i])) ||
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && (precharge_tbp[i] )) ||
(!cfg_reorder_data && precharge_tbp[i])
)
// precharge or precharge all command, can't write since bank is not active
// (INTER_ROW) we need to validate pch_grant because precharge might happen to a newly loaded TBP due to TBP interlock case (see require_pch logic)
begin
can_wr[i] <= 1'b0;
end
else if (((act_grant[i] && compare_t_param_act_to_rdwr_less_than_offset) || open_row_pass[i] || activated[i]) && col_timer_pre_ready[i]) // activated and timer is ready
begin
can_wr[i] <= 1'b1;
end
end
end
end
// Row request
always @(*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
row_req[i] = act_req[i] | pch_req[i];
end
end
// Column request
always @(*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
col_req[i] = rd_req[i] | wr_req[i];
end
end
// Individual activate, precharge, read and write request logic
always @ (*)
begin
for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
begin
act_req[i] = nor_rpv[i] & nor_sbv[i] & nor_sbvt[i] & ~or_wrt[i] & can_act[i];
pch_req[i] = require_pch[i] & pch_ready[i] & can_pch[i];
rd_req [i] = nor_cpv[i] & can_rd[i] & complete_rd[i];
wr_req [i] = nor_cpv[i] & can_wr[i] & complete_wr[i];
end
end
//----------------------------------------------------------------------------------------------------
// Valid logic
//----------------------------------------------------------------------------------------------------
// Indicates that current TBP is valid after load an invalid after flush
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
valid[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (load_tbp[i])
begin
valid[i] <= 1'b1;
end
else if (flush_tbp[i])
begin
valid[i] <= 1'b0;
end
end
end
end
//----------------------------------------------------------------------------------------------------
// TBP information
//----------------------------------------------------------------------------------------------------
// Keeps information from cmd_gen after load
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
chipsel [i] <= 0;
bank [i] <= 0;
row [i] <= 0;
col [i] <= 0;
write [i] <= 0;
read [i] <= 0;
size [i] <= 0;
autopch [i] <= 0;
localid [i] <= 0;
dataid [i] <= 0;
rmw_correct[i] <= 0;
rmw_partial[i] <= 0;
rmw [i] <= 0;
end
else
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (load_tbp[i])
begin
chipsel [i] <= cmd_gen_chipsel;
bank [i] <= cmd_gen_bank;
row [i] <= cmd_gen_row;
col [i] <= cmd_gen_col;
write [i] <= cmd_gen_write;
read [i] <= cmd_gen_read;
size [i] <= cmd_gen_size;
autopch [i] <= cmd_gen_autopch;
localid [i] <= cmd_gen_localid;
dataid [i] <= cmd_gen_dataid;
rmw_correct[i] <= cmd_gen_rmw_correct;
rmw_partial[i] <= cmd_gen_rmw_partial;
rmw [i] <= cmd_gen_rmw_partial | cmd_gen_rmw_correct;
end
end
end
// Priority information
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
priority_a[i] <= 1'b0;
end
else
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (CFG_DISABLE_PRIORITY == 1)
begin
priority_a[i] <= zero;
end
else
begin
if (load_tbp[i])
begin
if (cfg_reorder_data) // priority will be ignored when data reordering is OFF
begin
priority_a[i] <= cmd_gen_priority;
end
else
begin
priority_a[i] <= 1'b0;
end
end
else if (starvation[i] == cfg_starve_limit) // assert priority when starvation limit is reached
begin
priority_a[i] <= 1'b1;
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Row dependency vector
//----------------------------------------------------------------------------------------------------
// RPV, TBP is only allowed to request row command when RPV is all zero, meaning no dependencies on other TBPs
always @(*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (load_tbp[i])
begin
if
(
!flush_tbp[j] && !push_tbp[j] &&
(
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW" && valid[j] && (same_chip_bank_row[j] || (same_chip_bank[j] && (rmw_partial[j] || rmw_correct[j])))) ||
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && valid[j] && same_chip_bank[j]) ||
(!cfg_reorder_data && valid[j] && same_chip_bank[j])
)
)
// (INTER_ROW) Set RPV to '1' when a new TBP has same-chip-bank-row address with any other existing TBPs
// (INTER_ROW) Set RPV to '1' when existing TBP is a RMW command, we don't allow reordering between RMW commands
// This is to prevent activate going to the later RMW commands
// (INTER_BANK) Set RPV to '1' when a new TBP has same-chip-bank address with any other existing TBPs
// (NON_REORDER) Set RPV to '1' when a new TBP has same-chip-bank address with any other existing TBPs, to allow command reordering
begin
rpv_combi[i][j] = 1'b1;
end
else
begin
rpv_combi[i][j] = 1'b0;
end
end
else if (flush_tbp[j] || push_tbp[j])
// (INTER_ROW) Set RPV to '0' after flush
// (INTER_BANK) Set RPV to '0' after flush
begin
rpv_combi[i][j] = 1'b0;
end
else
begin
rpv_combi[i][j] = rpv[i][j];
end
end
end
end
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
begin
if (CFG_ENABLE_SHADOW_TBP)
begin
if (load_tbp[i])
begin
if (!flush_shadow_tbp[j] && ((shadow_valid[j] && same_shadow_chip_bank[j]) || (push_tbp[j] && same_chip_bank[j])))
// Set Shadow RPV to '1' when a new TBP has same-chip-bank address with any other existing TBPs
begin
shadow_rpv_combi[i][j] = 1'b1;
end
else
begin
shadow_rpv_combi[i][j] = 1'b0;
end
end
else if (push_tbp[j] && rpv[i][j])
// If there is a push_tbp and RPV is set to '1'
// We need to shift RPV to Shadow RPV
begin
shadow_rpv_combi[i][j] = 1'b1;
end
else if (flush_shadow_tbp[j])
// (INTER_ROW) Set RPV to '0' after flush
// (INTER_BANK) Set RPV to '0' after flush
begin
shadow_rpv_combi[i][j] = 1'b0;
end
else
begin
shadow_rpv_combi[i][j] = shadow_rpv[i][j];
end
end
else
begin
shadow_rpv_combi[i][j] = zero;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
nor_rpv[i] <= 1'b0;
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
rpv[i][j] <= 1'b0;
end
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
nor_rpv[i] <= ~|{shadow_rpv_combi[i], rpv_combi[i]};
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (i == j) // Hard-coded to '0' for own vector bit, since we only need to know the dependencies for other TBPs not ourself
begin
rpv[i][j] <= 1'b0;
end
else
begin
rpv[i][j] <= rpv_combi[i][j];
end
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
begin
shadow_rpv[i][j] <= 1'b0;
end
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
begin
shadow_rpv[i][j] <= shadow_rpv_combi[i][j];
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Column dependency vector
//----------------------------------------------------------------------------------------------------
// CPV, TBP is only allowed to request column command when CPV is all zero, meaning no dependencies on other TBPs
always @(*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (load_tbp[i])
begin
if
(
!flush_tbp[j] && !col_grant[j] &&
(
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW" && valid[j] && !done[j] && (priority_a[j] || same_chip_bank_row[j] || (rmw[j] && (cmd_gen_rmw_partial || cmd_gen_rmw_correct)) || same_command_read[j])) ||
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && valid[j] && !done[j] && (priority_a[j] || same_chip_bank [j] || (rmw[j] && (cmd_gen_rmw_partial || cmd_gen_rmw_correct)) || same_command_read[j])) ||
(!cfg_reorder_data && valid[j] && !done[j])
)
)
// (INTER_ROW) Set CPV to '1' when a new TBP has same-chip-bank-row address with any other existing TBPs
// (INTER_ROW) Set CPV to '1' when existing TBP is a RMW command, we don't allow reordering between RMW commands
// (INTER_ROW) Set CPV to '1' when existing TBP is a priority command, we don't want new TBP to take over priority command
// (INTER_BANK) Set CPV to '1' when a new TBP has same-chip-bank address with any other existing TBPs
// (INTER_BANK) Set CPV to '1' when existing TBP is a RMW command, we don't allow reordering between RMW commands
// (INTER_BANK) Set CPV to '1' when existing TBP is a priority command, we don't want new TBP to take over priority command
// (NON_REORDER) Set CPV to '1' when a new TBP is loaded, all column command must be executed in order
begin
cpv_combi[i][j] = 1'b1;
end
else
begin
cpv_combi[i][j] = 1'b0;
end
end
else if (col_grant[j])
// (INTER_ROW) Set CPV to '0' after col_grant
// (INTER_BANK) Set CPV to '0' after col_grant
begin
cpv_combi[i][j] = 1'b0;
end
else
begin
cpv_combi[i][j] = cpv[i][j];
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
nor_cpv[i] <= 1'b0;
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
cpv[i][j] <= 1'b0;
end
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
nor_cpv[i] <= ~|cpv_combi[i];
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (i == j) // Hard-coded to '0' for own vector bit, since we only need to know the dependencies for other TBPs not ourself
begin
cpv[i][j] <= 1'b0;
end
else
begin
cpv[i][j] <= cpv_combi[i][j];
end
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Activate related logic
//----------------------------------------------------------------------------------------------------
// Open-row-pass flush logic
// after a granted command and WST (open row pass to another TBP with same page from just granted command) OR
// after a done command and WST (open row pass to another TBP with same page from a done command with page open)
// Logic to determine which not-done TBP should be flushed to perform open-row-pass
always @ (*)
begin
not_done_tbp_row_pass_flush = col_grant & wst_p;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
not_done_tbp_row_pass_flush_r[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
not_done_tbp_row_pass_flush_r[i] <= not_done_tbp_row_pass_flush[i];
end
end
end
// Logic to determine which done TBP should be flushed to perform open-row-pass
always @ (*)
begin
done_tbp_row_pass_flush = done & wst_p & ~row_grant & ~precharge_tbp;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
done_tbp_row_pass_flush_r[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (done_tbp_row_pass_flush_r[i])
begin
done_tbp_row_pass_flush_r[i] <= 1'b0;
end
else
begin
done_tbp_row_pass_flush_r[i] <= done_tbp_row_pass_flush[i];
end
end
end
end
// Using done_tbp_row_pass_flush_r to improve timing
// it's acceptable to add one clock cycle latency when performing open-row-pass from a done command
// [REMARK] there is potential to optimize the flush logic (for done-open-row-pass case), because flush_tbp depends on open_row_pass_flush logic
assign open_row_pass_flush = not_done_tbp_row_pass_flush | done_tbp_row_pass_flush;
// Open-row-pass logic, TBP will pass related information to same page command (increase efficiency)
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
open_row_pass[i] = |open_row_pass_flush && or_wrt[i] && |(wrt[i] & open_row_pass_flush);
end
end
// Open-row-passed logic, keep signal high once there is a open-row-pass to current TBP
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
open_row_passed[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (open_row_pass[i])
begin
open_row_passed[i] <= 1'b1;
end
else if (flush_tbp[i])
begin
open_row_passed[i] <= 1'b0;
end
end
end
end
// Registered version
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
open_row_pass_r [i] <= 1'b0;
open_row_pass_flush_r[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
open_row_pass_r [i] <= open_row_pass [i];
open_row_pass_flush_r[i] <= open_row_pass_flush[i];
end
end
end
// Activated logic
// indicate that current TBP is activated by activate command or open-row-pass
always @(*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (act_grant[i] || open_row_pass[i])
begin
activated_combi[i] = 1'b1;
end
else
begin
activated_combi[i] = 1'b0;
end
end
end
// activated need not to be validated with valid
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
activated [i] <= 1'b0;
activated_p[i] <= 1'b0;
end
end
else
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
activated_p[i] <= activated_combi[i]; // activated pulse
if (flush_tbp[i] || pch_grant[i])
begin
activated[i] <= 1'b0;
end
else if (precharge_tbp[i])
begin
activated[i] <= 1'b0;
end
else if (activated_combi[i])
begin
activated[i] <= 1'b1;
end
end
end
//----------------------------------------------------------------------------------------------------
// Precharge related logic
//----------------------------------------------------------------------------------------------------
// Precharge all logic
// indicate which TBP is precharged cause of sideband precharge all command
always @(*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
precharge_tbp[i] = sb_tbp_precharge_all[i];
end
end
// Precharge logic
// indicate which TBP is precharged
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (load_tbp[i])
begin
precharged_combi[i] = 1'b0;
end
else if (activated_combi[i] && cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW")
// Only required in INTER-ROW reordering case since TBP might request precharge after TBP load
// due to TBP interlock case
begin
precharged_combi[i] = 1'b0;
end
else if (col_grant[i] && real_ap[i])
begin
precharged_combi[i] = 1'b1;
end
else if (pch_grant[i])
begin
precharged_combi[i] = 1'b1;
end
else
begin
precharged_combi[i] = precharged[i];
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
precharged[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
precharged[i] <= precharged_combi[i];
end
end
end
//----------------------------------------------------------------------------------------------------
// Auto-precharge related logic
//----------------------------------------------------------------------------------------------------
// Auto precharge related logic, to determine which TBP should be closed or kept open
// OPP - autoprecharge when there is another command to same chip-bank different row
// CPP - do not autoprecharge when there is another command to the same chip-bank-row
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (flush_tbp[i])
begin
apvo_combi[i] = 1'b0;
apvc_combi[i] = 1'b0;
end
else if
(
(load_tbp[i] && CFG_DATA_REORDERING_TYPE == "INTER_ROW") || // load self
(
(|load_tbp && !load_tbp[i]) && // load other TBP
(
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW") ||
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && !ssb[i]) ||
(!cfg_reorder_data && !ssb[i])
)
)
)
// (INTER_ROW) update multiple times whenever there is a load so that it'll get the latest AP info
// (INTER_BANK) only update this once after same chip-bank command is loaded, masked by SSB (seen same bank)
// (NON_REORDER) only update this once after same chip-bank command is loaded, masked by SSB (seen same bank)
begin
if
(
(load_tbp[i] && |(valid & same_chip_bank_diff_row) && cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW") ||
((|load_tbp && !load_tbp[i]) && valid[i] && same_chip_bank_diff_row[i])
)
// (INTER_ROW) on self load, set to '1' if other valid TBP is same-chip-bank-diff-row with self
// set to '1' if there is a new command with same-chip-bank-diff-row with current TBP
begin
apvo_combi[i] = 1'b1;
end
else
begin
apvo_combi[i] = apvo[i];
end
if ((|load_tbp && !load_tbp[i]) && valid[i] && same_chip_bank_row[i])
// set to '1' if there is a new command with same-chip-bank-row with current TBP
begin
apvc_combi[i] = 1'b1;
end
else
begin
apvc_combi[i] = apvc[i];
end
end
else
begin
apvo_combi[i] = apvo[i];
apvc_combi[i] = apvc[i];
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
apvo[i] <= 1'b0;
apvc[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
apvo[i] <= apvo_combi[i];
apvc[i] <= apvc_combi[i];
end
end
end
// Auto precharge
always @(*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (apvc[i]) // keeping a page open have higher priority that keeping a close page (improve efficiency)
begin
ap[i] = 1'b0;
end
else if (apvo[i])
begin
ap[i] = 1'b1;
end
else
begin
ap[i] = autopch[i] | require_flush[i];
end
end
end
// Real auto-precharge
// purpose is to make pipelining easier in the future (if needed)
always @ (*)
begin
real_ap = ap;
end
//----------------------------------------------------------------------------------------------------
// Done logic
//----------------------------------------------------------------------------------------------------
// Indicate that current TBP has finished issuing column command
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (load_tbp[i])
begin
done_combi[i] = 1'b0;
end
else if (flush_tbp[i])
begin
done_combi[i] = 1'b0;
end
else if (col_grant[i])
begin
done_combi[i] = 1'b1;
end
else
begin
done_combi[i] = done[i];
end
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
done[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
done[i] <= done_combi[i];
end
end
end
//----------------------------------------------------------------------------------------------------
// Complete logic
//----------------------------------------------------------------------------------------------------
reg [CFG_CTL_TBP_NUM-1:0] partial_vector_combi [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] partial_vector [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] load_rmw_data;
reg [CFG_CTL_TBP_NUM-1:0] all_complete_vector;
reg all_complete;
wire data_rmw_fetch = data_rmw_complete && !all_complete;
// Partial information, to indicate which partial command should receive the current data_rmw_complete
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (i == j)
begin
partial_vector_combi[i][j] = zero;
end
else
begin
if (load_tbp[i] && (cmd_gen_rmw_partial || cmd_gen_rmw_correct) && cmd_gen_write) // only required for partial write commands
begin
if (!done[j] && valid[j] && rmw[j] && write[j] && !load_rmw_data[j] && !complete_wr[j]) // compare with current valid and not done RMW commands
begin
partial_vector_combi[i][j] = 1'b1;
end
else
begin
partial_vector_combi[i][j] = 1'b0;
end
end
else if (load_rmw_data[j])
begin
partial_vector_combi[i][j] = 1'b0;
end
else
begin
partial_vector_combi[i][j] = partial_vector[i][j];
end
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
partial_vector[i][j] <= 1'b0;
end
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
partial_vector[i][j] <= partial_vector_combi[i][j];
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
load_rmw_data[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (~|partial_vector_combi[i] && data_rmw_complete)
begin
load_rmw_data[i] <= 1'b1;
end
else
begin
load_rmw_data[i] <= 1'b0;
end
end
end
end
// Indicate that the data for current TBP is complete and ready to be issued
always @(*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (load_tbp[i])
begin
if (cmd_gen_read)
begin
complete_combi_rd[i] = cmd_gen_complete;
complete_combi_wr[i] = 1'b0;
end
else
begin
complete_combi_rd[i] = 1'b0;
complete_combi_wr[i] = cmd_gen_complete;
end
end
else if (write[i] && !complete[i])
begin
complete_combi_rd[i] = complete_rd[i];
if (cfg_enable_rmw)
begin
complete_combi_wr[i] = load_rmw_data[i];
end
else
begin
complete_combi_wr[i] = data_complete[i];
end
end
else
begin
complete_combi_rd[i] = complete_rd[i];
complete_combi_wr[i] = complete_wr[i];
end
end
end
always @ (*)
begin
complete_combi = complete_combi_rd | complete_combi_wr;
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
complete <= 0;
complete_rd <= 0;
complete_wr <= 0;
end
else
begin
complete <= complete_combi;
complete_rd <= complete_combi_rd;
complete_wr <= complete_combi_wr;
end
end
// To indicate that all TBP has completed, expect non-valid TBP
always @ (*)
begin
all_complete = &all_complete_vector;
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (!valid[i])
begin
all_complete_vector[i] = 1'b1;
end
else
begin
all_complete_vector[i] = complete[i];
end
end
end
//----------------------------------------------------------------------------------------------------
// Same bank vector logic
//----------------------------------------------------------------------------------------------------
// This bit vector (same bank vector) is to stop a TBP from requesting activate when another row in the same chip-bank was granted
// SBV stops TBP from requesting activate when there is another same-chip-bank-diff-row was granted
// prevents activate to and activated bank
always @(*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (CFG_DATA_REORDERING_TYPE == "INTER_BANK")
begin
// There is no need to SBV in INTER_BANK case
sbv_combi[i][j] = zero;
end
else if (CFG_DATA_REORDERING_TYPE == "INTER_ROW")
begin
if
(
(load_tbp[i] && !flush_tbp[j] && (activated[j] || activated_combi[j]) && same_chip_bank_diff_row[j]) ||
(activated_combi[j] && valid[i] && pre_calculated_same_chip_bank_diff_row [i][j])
)
// Set SBV to '1' if new TBP is same-chip-bank-diff-row with other existing TBP
// Set SBV to '1' if there is a row_grant or open-row-pass to other existing TBP with same-chip-bank-diff-row
begin
sbv_combi[i][j] = 1'b1;
end
else if (flush_tbp[j] || pch_grant[j] || precharge_tbp[j])
// Set SBV to '0' if there is a flush to other TBP
// Set SBV to '0' if there is a precharge to other TBP
// Set SBV to '0' if there is a precharge all command from sideband
begin
sbv_combi[i][j] = 1'b0;
end
else
begin
sbv_combi[i][j] = sbv[i][j];
end
end
else
begin
sbv_combi[i][j] = sbv[i][j];
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
nor_sbv[i] <= 1'b0;
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
sbv[i][j] <= 1'b0;
end
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
nor_sbv[i] <= ~|sbv_combi[i];
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (i == j) // Hard-coded to '0' for own vector bit, since we only need to know the dependencies for other TBPs not ourself
begin
sbv[i][j] <= 1'b0;
end
else
begin
sbv[i][j] <= sbv_combi[i][j];
end
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Same bank timer vector logic
//----------------------------------------------------------------------------------------------------
// SBTV stops TBP from requesting activate when the timer for same-chip-bank is still running
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (CFG_DATA_REORDERING_TYPE == "INTER_BANK")
begin
sbvt_combi[i][j] = zero;
end
else if (CFG_DATA_REORDERING_TYPE == "INTER_ROW")
begin
if (flush_tbp[i])
begin
sbvt_combi[i][j] = 1'b0;
end
else if (push_tbp[j])
begin
sbvt_combi[i][j] = 1'b0;
end
else if
(
(pch_grant[j] || (col_grant[j] && real_ap[j])) &&
(
(load_tbp[i] && same_chip_bank[j]) ||
(valid[i] && pre_calculated_same_chip_bank[i][j])
)
)
// Set to '1' when there is a precharge/auto-precharge to same-chip-bank address
begin
sbvt_combi[i][j] = 1'b1;
end
else if
(
precharged[j] && valid[j] &&
(
(load_tbp[i] && same_chip_bank[j]) ||
(valid[i] && pre_calculated_same_chip_bank[i][j])
)
)
// Set to '1' when same-chip-bank address TBP is still in precharge state
begin
sbvt_combi[i][j] = ~row_timer_pre_ready[j];
end
else
begin
sbvt_combi[i][j] = zero;
end
end
else
begin
sbvt_combi[i][j] = sbvt[i][j];
end
end
end
end
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
begin
if (CFG_ENABLE_SHADOW_TBP)
begin
if (CFG_DATA_REORDERING_TYPE == "INTER_BANK")
begin
shadow_sbvt_combi[i][j] = zero;
end
else if (CFG_DATA_REORDERING_TYPE == "INTER_ROW")
begin
if (flush_shadow_tbp[j])
begin
shadow_sbvt_combi[i][j] = 1'b0;
end
else if (push_tbp[j] && sbvt[i][j])
begin
shadow_sbvt_combi[i][j] = 1'b1;
end
else if (valid[i] && shadow_valid[j] && pre_calculated_same_shadow_chip_bank[i][j])
// Set to 'timer-pre-ready' when own TBP is valid, shadow TBP is valid and same chip-bank address
begin
shadow_sbvt_combi[i][j] = ~shadow_row_timer_pre_ready[j];
end
else
begin
shadow_sbvt_combi[i][j] = shadow_sbvt[i][j];
end
end
else
begin
shadow_sbvt_combi[i][j] = zero;
end
end
else
begin
shadow_sbvt_combi[i][j] = zero;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
sbvt[i][j] <= 1'b0;
end
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
nor_sbvt[i] <= ~|{shadow_sbvt_combi[i], sbvt_combi[i]};
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (i == j) // Hard-coded to '0' for own vector bit, since we only need to know the dependencies for other TBPs not ourself
begin
sbvt[i][j] <= 1'b0;
end
else
begin
sbvt[i][j] <= sbvt_combi[i][j];
end
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
begin
shadow_sbvt[i][j] <= 1'b0;
end
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
begin
shadow_sbvt[i][j] <= shadow_sbvt_combi[i][j];
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Seen same bank logic
//----------------------------------------------------------------------------------------------------
// Indicate that it sees a new TBP which is same-chip-bank with current TBP
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
ssb[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (flush_tbp[i])
begin
ssb[i] <= 1'b0;
end
else if (load_tbp[j] && valid[i] && same_chip_bank[i])
begin
ssb[i] <= 1'b1;
end
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Seen same bank row logic
//----------------------------------------------------------------------------------------------------
// Indicate that it sees a new TBP which is same-chip-bank-row with current TBP
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
ssbr[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (flush_tbp[i])
begin
ssbr[i] <= 1'b0;
end
else if (load_tbp[j] && valid[i] && same_chip_bank_row[i])
begin
ssbr[i] <= 1'b1;
end
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Will send transfer logic
//----------------------------------------------------------------------------------------------------
// Indicate that it will pass current TBP information (timing/page) over to other TBP
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
wst [i] <= 1'b0;
wst_p[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (load_tbp[i]) // Reset back to '0'
begin
wst [i] <= 1'b0;
wst_p[i] <= 1'b0;
end
else if
(
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW" && precharged_combi[i] && done_combi[i]) ||
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && precharged_combi[i] ) ||
(!cfg_reorder_data && precharged_combi[i])
)
// Set to '0' when there is a precharge to current TBP, after a precharge, it's not possible to perform open-row-pass anymore
// (INTER_ROW) included done_combi because precharge can happen to a newly loaded TBP due to TBP interlock case (see require_pch logic)
// to make sure we're able to open-row-pass a not-done precharged command
begin
wst [i] <= 1'b0;
wst_p[i] <= 1'b0;
end
else if (open_row_pass_flush[i]) // make sure open-row-pass only asserts for one clock cycle
begin
wst_p[i] <= 1'b0;
end
else if
(
load_tbp[j] && same_chip_bank_row[i] &&
(
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW" && !ssbr[i] && !(precharged_combi[i] && done_combi[i])) ||
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && !ssb [i] && !(precharged_combi[i] )) ||
(!cfg_reorder_data && !ssb[i] && !precharged_combi[i])
)
)
// Set to '1' when there is a new TBP being loaded, with same-chip-bank-row with current TBP
// make sure current TBP is not precharged so that information can be pass over to same-chip-bank-row TBP
// (INTER_ROW) included done_combi because precharge can happen to a newly loaded TBP due to TBP interlock case (see require_pch logic)
// to make sure we're able to open-row-pass a not-done precharged command
// (INTER_BANK) make sure SSB is not set (only set WST once)
// (NON_REORDER) make sure SSB is not set (only set WST once)
begin
wst [i] <= 1'b1;
wst_p[i] <= 1'b1;
end
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Will receive transfer logic
//----------------------------------------------------------------------------------------------------
// Indicate that it will receive TBP information (timing/page) from other TBP (also tells which TBP it is receiving from)
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if
(
load_tbp[i] && !flush_tbp[j] && valid[j] && same_chip_bank_row[j] &&
(
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW" && !ssbr[j]) ||
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && !ssb [j]) ||
(!cfg_reorder_data && !ssb[j])
)
)
// Set to '1' when there is a new TBp being loaded, with same-chip-bank-row with other existing TBP
// provided other TBP is valid and not precharged
// (INTER_BANK) make sure SSB of other TBP is not set, to handle row interrupt case
begin
wrt_combi[i][j] = 1'b1;
end
else if (flush_tbp[j])
begin
wrt_combi[i][j] = 1'b0;
end
else
begin
wrt_combi[i][j] = wrt[i][j];
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
begin
wrt [i] <= 0;
or_wrt [i] <= 1'b0;
nor_wrt[i] <= 1'b0;
end
end
else
begin
for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
begin
or_wrt [i] <= |wrt_combi[i];
nor_wrt[i] <= ~|wrt_combi[i];
for (j = 0;j < CFG_CTL_TBP_NUM;j = j + 1)
begin
if (i == j)
wrt[i][j] <= 1'b0;
else
wrt[i][j] <= wrt_combi[i][j];
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Require flush logic
//----------------------------------------------------------------------------------------------------
// On demand flush selection, command with same chip-bank-diff-row first, we dont want to precharge twice
// if there are none, flush cmd to diff chip-bank, we might have cmd to the same row in tbp already
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
require_flush[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (CFG_CTL_TBP_NUM == 1)
begin
require_flush[i] <= cmd_gen_load | cmd_gen_waiting_to_load;
end
else
begin
if (|flush_tbp) // tbp will not be full on the next clock cycle
begin
require_flush[i] <= 1'b0;
end
else if (int_tbp_full && (cmd_gen_load | cmd_gen_waiting_to_load))
begin
if (same_chip_bank_row[i])
require_flush[i] <= 1'b0;
else
require_flush[i] <= 1'b1;
end
else
begin
require_flush[i] <= 1'b0;
end
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Require precharge logic
//----------------------------------------------------------------------------------------------------
// Precharge request logic, to clear up lockup state in TBP
always @(*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (CFG_DATA_REORDERING_TYPE == "INTER_BANK")
begin
require_pch_combi[i][j] = zero;
end
else
begin
if (i == j)
begin
require_pch_combi[i][j] = 1'b0;
end
else if (activated[i] && !done[i])
begin
if (cpv[i][j] && sbv[j][i])
begin
require_pch_combi[i][j] = 1'b1;
end
else
begin
require_pch_combi[i][j] = 1'b0;
end
end
else
begin
require_pch_combi[i][j] = 1'b0;
end
end
end
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
require_pch[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (flush_tbp[i])
begin
require_pch[i] <= 1'b0;
end
else
begin
// included real_ap since real_ap is part of precharge request (!apvc so that it will deassert pch_req when not needed)
require_pch[i] <= |require_pch_combi[i] | (done[i] & real_ap[i] & !apvc_combi[i]);
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Address/command comparison logic
//----------------------------------------------------------------------------------------------------
// Command comparator
always @ (*)
begin
if (CFG_DISABLE_READ_REODERING) // logic only enabled when parameter is set to '1'
begin
same_command_read = cmd_gen_same_read_cmd;
end
else
begin
same_command_read = {CFG_CTL_TBP_NUM{zero}};
end
end
always @ (*)
begin
same_shadow_command_read = {CFG_CTL_SHADOW_TBP_NUM{zero}};
end
// Address comparator
always @(*)
begin
same_chip_bank = cmd_gen_same_chipsel_addr & cmd_gen_same_bank_addr;
same_chip_bank_row = cmd_gen_same_chipsel_addr & cmd_gen_same_bank_addr & cmd_gen_same_row_addr;
same_chip_bank_diff_row = cmd_gen_same_chipsel_addr & cmd_gen_same_bank_addr & ~cmd_gen_same_row_addr;
end
always @ (*)
begin
same_shadow_chip_bank = cmd_gen_same_shadow_chipsel_addr & cmd_gen_same_shadow_bank_addr;
same_shadow_chip_bank_row = cmd_gen_same_shadow_chipsel_addr & cmd_gen_same_shadow_bank_addr & cmd_gen_same_shadow_row_addr;
same_shadow_chip_bank_diff_row = cmd_gen_same_shadow_chipsel_addr & cmd_gen_same_shadow_bank_addr & ~cmd_gen_same_shadow_row_addr;
end
// Registered version, to improve fMAX
generate
begin
genvar i_tbp;
genvar j_tbp;
for (i_tbp = 0;i_tbp < CFG_CTL_TBP_NUM;i_tbp = i_tbp + 1)
begin : i_compare_loop
for (j_tbp = 0;j_tbp < CFG_CTL_TBP_NUM;j_tbp = j_tbp + 1)
begin : j_compare_loop
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
pre_calculated_same_chip_bank_diff_row [i_tbp][j_tbp] <= 1'b0;
pre_calculated_same_chip_bank_row [i_tbp][j_tbp] <= 1'b0;
pre_calculated_same_chip_bank [i_tbp][j_tbp] <= 1'b0;
end
else
begin
if (load_tbp [i_tbp])
begin
pre_calculated_same_chip_bank_diff_row [i_tbp][j_tbp] <= same_chip_bank_diff_row [j_tbp];
pre_calculated_same_chip_bank_row [i_tbp][j_tbp] <= same_chip_bank_row [j_tbp];
pre_calculated_same_chip_bank [i_tbp][j_tbp] <= same_chip_bank [j_tbp];
end
else if (load_tbp [j_tbp])
begin
if (chipsel [i_tbp] == cmd_gen_chipsel && bank [i_tbp] == cmd_gen_bank && row [i_tbp] != cmd_gen_row)
pre_calculated_same_chip_bank_diff_row [i_tbp][j_tbp] <= 1'b1;
else
pre_calculated_same_chip_bank_diff_row [i_tbp][j_tbp] <= 1'b0;
if (chipsel [i_tbp] == cmd_gen_chipsel && bank [i_tbp] == cmd_gen_bank && row [i_tbp] == cmd_gen_row)
pre_calculated_same_chip_bank_row [i_tbp][j_tbp] <= 1'b1;
else
pre_calculated_same_chip_bank_row [i_tbp][j_tbp] <= 1'b0;
if (chipsel [i_tbp] == cmd_gen_chipsel && bank [i_tbp] == cmd_gen_bank)
pre_calculated_same_chip_bank [i_tbp][j_tbp] <= 1'b1;
else
pre_calculated_same_chip_bank [i_tbp][j_tbp] <= 1'b0;
end
else if (chipsel [i_tbp] == chipsel [j_tbp] && bank [i_tbp] == bank [j_tbp])
begin
if (row [i_tbp] != row [j_tbp])
begin
pre_calculated_same_chip_bank_diff_row [i_tbp][j_tbp] <= 1'b1;
pre_calculated_same_chip_bank_row [i_tbp][j_tbp] <= 1'b0;
end
else
begin
pre_calculated_same_chip_bank_diff_row [i_tbp][j_tbp] <= 1'b0;
pre_calculated_same_chip_bank_row [i_tbp][j_tbp] <= 1'b1;
end
pre_calculated_same_chip_bank [i_tbp][j_tbp] <= 1'b1;
end
else
begin
pre_calculated_same_chip_bank_diff_row [i_tbp][j_tbp] <= 1'b0;
pre_calculated_same_chip_bank_row [i_tbp][j_tbp] <= 1'b0;
pre_calculated_same_chip_bank [i_tbp][j_tbp] <= 1'b0;
end
end
end
end
end
for (i_tbp = 0;i_tbp < CFG_CTL_TBP_NUM;i_tbp = i_tbp + 1)
begin : i_compare_loop_shadow
for (j_tbp = 0;j_tbp < CFG_CTL_SHADOW_TBP_NUM;j_tbp = j_tbp + 1)
begin : j_compare_loop_shadow
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
pre_calculated_same_shadow_chip_bank [i_tbp][j_tbp] <= 1'b0;
end
else
begin
if (load_tbp [i_tbp])
begin
if (push_tbp [j_tbp])
pre_calculated_same_shadow_chip_bank [i_tbp][j_tbp] <= same_chip_bank [j_tbp];
else
pre_calculated_same_shadow_chip_bank [i_tbp][j_tbp] <= same_shadow_chip_bank [j_tbp];
end
else if (push_tbp [j_tbp])
begin
if (chipsel [i_tbp] == chipsel [j_tbp] && bank [i_tbp] == bank [j_tbp])
pre_calculated_same_shadow_chip_bank [i_tbp][j_tbp] <= 1'b1;
else
pre_calculated_same_shadow_chip_bank [i_tbp][j_tbp] <= 1'b0;
end
else if (chipsel [i_tbp] == shadow_chipsel [j_tbp] && bank [i_tbp] == shadow_bank [j_tbp])
begin
pre_calculated_same_shadow_chip_bank [i_tbp][j_tbp] <= 1'b1;
end
else
begin
pre_calculated_same_shadow_chip_bank [i_tbp][j_tbp] <= 1'b0;
end
end
end
end
end
end
endgenerate
//----------------------------------------------------------------------------------------------------
// Bank specific timer related logic
//----------------------------------------------------------------------------------------------------
// Offset timing paramter to achieve accurate timing gap between commands
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
compare_t_param_act_to_rdwr_less_than_offset <= 0;
compare_t_param_act_to_act_less_than_offset <= 0;
compare_t_param_act_to_pch_less_than_offset <= 0;
compare_t_param_rd_to_pch_less_than_offset <= 0;
compare_t_param_wr_to_pch_less_than_offset <= 0;
compare_t_param_pch_to_valid_less_than_offset <= 0;
compare_t_param_rd_ap_to_valid_less_than_offset <= 0;
compare_t_param_wr_ap_to_valid_less_than_offset <= 0;
compare_offset_t_param_act_to_rdwr_less_than_0 <= 0;
compare_offset_t_param_act_to_rdwr_less_than_1 <= 0;
end
else
begin
if (t_param_act_to_rdwr > TBP_COUNTER_OFFSET)
begin
compare_t_param_act_to_rdwr_less_than_offset <= 1'b0;
end
else
begin
compare_t_param_act_to_rdwr_less_than_offset <= 1'b1;
end
if (t_param_act_to_act > TBP_COUNTER_OFFSET)
begin
compare_t_param_act_to_act_less_than_offset <= 1'b0;
end
else
begin
compare_t_param_act_to_act_less_than_offset <= 1'b1;
end
if (t_param_act_to_pch > TBP_COUNTER_OFFSET)
begin
compare_t_param_act_to_pch_less_than_offset <= 1'b0;
end
else
begin
compare_t_param_act_to_pch_less_than_offset <= 1'b1;
end
if (t_param_rd_to_pch > TBP_COUNTER_OFFSET)
begin
compare_t_param_rd_to_pch_less_than_offset <= 1'b0;
end
else
begin
compare_t_param_rd_to_pch_less_than_offset <= 1'b1;
end
if (t_param_wr_to_pch > TBP_COUNTER_OFFSET)
begin
compare_t_param_wr_to_pch_less_than_offset <= 1'b0;
end
else
begin
compare_t_param_wr_to_pch_less_than_offset <= 1'b1;
end
if (t_param_pch_to_valid > TBP_COUNTER_OFFSET)
begin
compare_t_param_pch_to_valid_less_than_offset <= 1'b0;
end
else
begin
compare_t_param_pch_to_valid_less_than_offset <= 1'b1;
end
if (t_param_rd_ap_to_valid > TBP_COUNTER_OFFSET)
begin
compare_t_param_rd_ap_to_valid_less_than_offset <= 1'b0;
end
else
begin
compare_t_param_rd_ap_to_valid_less_than_offset <= 1'b1;
end
if (t_param_wr_ap_to_valid > TBP_COUNTER_OFFSET)
begin
compare_t_param_wr_ap_to_valid_less_than_offset <= 1'b0;
end
else
begin
compare_t_param_wr_ap_to_valid_less_than_offset <= 1'b1;
end
if (offset_t_param_act_to_rdwr <= 0)
begin
compare_offset_t_param_act_to_rdwr_less_than_0 <= 1'b1;
end
else
begin
compare_offset_t_param_act_to_rdwr_less_than_0 <= 1'b0;
end
if (offset_t_param_act_to_rdwr <= 1)
begin
compare_offset_t_param_act_to_rdwr_less_than_1 <= 1'b1;
end
else
begin
compare_offset_t_param_act_to_rdwr_less_than_1 <= 1'b0;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
offset_t_param_act_to_rdwr <= 0;
offset_t_param_act_to_act <= 0;
offset_t_param_act_to_pch <= 0;
offset_t_param_rd_to_pch <= 0;
offset_t_param_wr_to_pch <= 0;
offset_t_param_pch_to_valid <= 0;
offset_t_param_rd_ap_to_valid <= 0;
offset_t_param_wr_ap_to_valid <= 0;
end
else
begin
if (!compare_t_param_act_to_rdwr_less_than_offset)
begin
offset_t_param_act_to_rdwr <= t_param_act_to_rdwr - TBP_COUNTER_OFFSET;
end
else
begin
offset_t_param_act_to_rdwr <= 0;
end
if (!compare_t_param_act_to_act_less_than_offset)
begin
offset_t_param_act_to_act <= t_param_act_to_act - TBP_COUNTER_OFFSET;
end
else
begin
offset_t_param_act_to_act <= 0;
end
if (!compare_t_param_act_to_pch_less_than_offset)
begin
offset_t_param_act_to_pch <= t_param_act_to_pch - TBP_COUNTER_OFFSET;
end
else
begin
offset_t_param_act_to_pch <= 0;
end
if (!compare_t_param_rd_to_pch_less_than_offset)
begin
offset_t_param_rd_to_pch <= t_param_rd_to_pch - TBP_COUNTER_OFFSET;
end
else
begin
offset_t_param_rd_to_pch <= 0;
end
if (!compare_t_param_wr_to_pch_less_than_offset)
begin
offset_t_param_wr_to_pch <= t_param_wr_to_pch - TBP_COUNTER_OFFSET;
end
else
begin
offset_t_param_wr_to_pch <= 0;
end
if (!compare_t_param_pch_to_valid_less_than_offset)
begin
offset_t_param_pch_to_valid <= t_param_pch_to_valid - TBP_COUNTER_OFFSET;
end
else
begin
offset_t_param_pch_to_valid <= 0;
end
if (!compare_t_param_rd_ap_to_valid_less_than_offset)
begin
offset_t_param_rd_ap_to_valid <= t_param_rd_ap_to_valid - TBP_COUNTER_OFFSET;
end
else
begin
offset_t_param_rd_ap_to_valid <= 0;
end
if (!compare_t_param_wr_ap_to_valid_less_than_offset)
begin
offset_t_param_wr_ap_to_valid <= t_param_wr_ap_to_valid - TBP_COUNTER_OFFSET;
end
else
begin
offset_t_param_wr_ap_to_valid <= 0;
end
end
end
// Pre-calculated logic to improve timing, for row_timer and trc_timer
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
compare_t_param_rd_to_pch_greater_than_row_timer [i] <= 1'b0;
compare_t_param_wr_to_pch_greater_than_row_timer [i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (t_param_rd_to_pch > ((row_timer[i] > 1) ? (row_timer[i] - 1'b1) : 0))
begin
compare_t_param_rd_to_pch_greater_than_row_timer[i] <= 1'b1;
end
else
begin
compare_t_param_rd_to_pch_greater_than_row_timer[i] <= 1'b0;
end
if (t_param_wr_to_pch > ((row_timer[i] > 1) ? (row_timer[i] - 1'b1) : 0))
begin
compare_t_param_wr_to_pch_greater_than_row_timer[i] <= 1'b1;
end
else
begin
compare_t_param_wr_to_pch_greater_than_row_timer[i] <= 1'b0;
end
end
end
end
// Column timer logic
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
col_timer [i] <= 0;
col_timer_ready [i] <= 1'b0;
col_timer_pre_ready[i] <= 1'b0;
end
else
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (row_grant[i])
begin
if (compare_t_param_act_to_rdwr_less_than_offset)
begin
col_timer [i] <= 0;
col_timer_ready [i] <= 1'b1;
col_timer_pre_ready[i] <= 1'b1;
end
else
begin
col_timer [i] <= offset_t_param_act_to_rdwr;
if (compare_offset_t_param_act_to_rdwr_less_than_0)
begin
col_timer_ready [i] <= 1'b1;
end
else
begin
col_timer_ready [i] <= 1'b0;
end
if (compare_offset_t_param_act_to_rdwr_less_than_1)
begin
col_timer_pre_ready[i] <= 1'b1;
end
else
begin
col_timer_pre_ready[i] <= 1'b0;
end
end
end
else
begin
if (col_timer[i] != 0)
begin
col_timer[i] <= col_timer[i] - 1'b1;
end
if (col_timer[i] <= 1)
begin
col_timer_ready[i] <= 1'b1;
end
else
begin
col_timer_ready[i] <= 1'b0;
end
if (col_timer[i] <= 2)
begin
col_timer_pre_ready[i] <= 1'b1;
end
else
begin
col_timer_pre_ready[i] <= 1'b0;
end
end
end
end
// log2 result of open-row-pass-flush, to be used during timer information pass
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
log2_open_row_pass_flush[i] = log2(open_row_pass_flush & wrt[i]);
end
end
// Registered version
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
log2_open_row_pass_flush_r[i] <= 0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
log2_open_row_pass_flush_r[i] <= log2_open_row_pass_flush[i];
end
end
end
// Combined timer logic
// compare between row_timer and trc_timer and take the largest value
// to be used in open_row_pass only
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
combined_timer[i] <= 0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (CFG_REG_GRANT == 0 && open_row_pass_r[i]) // for QR controller only
begin
if (col_grant[i])
begin
if (row_timer_combi[i] > combined_timer[log2_open_row_pass_flush_r[i]])
begin
combined_timer[i] <= row_timer_combi[i];
end
else
begin
combined_timer[i] <= (combined_timer[log2_open_row_pass_flush_r[i]] > 1'b1) ? (combined_timer[log2_open_row_pass_flush_r[i]] - 1'b1) : 1'b1;
end
end
else
begin
combined_timer[i] <= (combined_timer[log2_open_row_pass_flush_r[i]] > 1'b1) ? (combined_timer[log2_open_row_pass_flush_r[i]] - 1'b1) : 1'b1;
end
end
else
begin
if (row_timer_combi[i] > trc_timer[i])
begin
combined_timer[i] <= row_timer_combi[i];
end
else
begin
combined_timer[i] <= (trc_timer[i] > 1'b1) ? (trc_timer[i] - 1'b1) : 1'b1;
end
end
end
end
end
// Row timer logic
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (trc_timer[i] <= 1)
begin
trc_timer_pre_ready_combi[i] = 1'b1;
end
else
begin
trc_timer_pre_ready_combi[i] = 1'b0;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
trc_timer [i] <= 0;
trc_timer_ready [i] <= 1'b0;
trc_timer_pre_ready[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
// Reset row_timer after push
if (push_tbp[i])
begin
trc_timer [i] <= 0;
trc_timer_ready [i] <= 1'b1;
trc_timer_pre_ready[i] <= 1'b1;
end
// We need to update the timer as soon as possible when CFG_REG_GRANT == 0
// because after open-row-pass, row grant can happen on the next clock cycle
else if (CFG_REG_GRANT == 0 && open_row_pass[i])
begin
trc_timer_ready [i] <= 1'b0;
trc_timer_pre_ready[i] <= 1'b0;
end
else if
(open_row_pass_r[i])
begin
trc_timer [i] <= combined_timer[log2_open_row_pass_flush_r[i]] - 1'b1;
trc_timer_ready [i] <= 1'b0;
trc_timer_pre_ready[i] <= 1'b0;
end
else if (act_grant[i])
begin
trc_timer [i] <= offset_t_param_act_to_act;
trc_timer_ready [i] <= 1'b0;
trc_timer_pre_ready[i] <= 1'b0;
end
else
begin
if (trc_timer[i] != 0)
begin
trc_timer[i] <= trc_timer[i] - 1'b1;
end
if (trc_timer[i] <= 1)
begin
trc_timer_ready[i] <= 1'b1;
end
if (trc_timer[i] <= 2)
begin
trc_timer_pre_ready[i] <= 1'b1;
end
end
end
end
end
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (rd_grant[i])
begin
if (real_ap[i])
begin
row_timer_combi[i] = offset_t_param_rd_ap_to_valid;
end
else
begin
if
(
(CFG_REG_GRANT == 1 && compare_t_param_rd_to_pch_greater_than_row_timer[i]) ||
(CFG_REG_GRANT == 0 && t_param_rd_to_pch > row_timer[i])
)
begin
row_timer_combi[i] = offset_t_param_rd_to_pch;
end
else
begin
row_timer_combi[i] = row_timer[i] - 1'b1;
end
end
end
else if (wr_grant[i])
begin
if (real_ap[i])
begin
row_timer_combi[i] = offset_t_param_wr_ap_to_valid;
end
else
begin
if
(
(CFG_REG_GRANT == 1 && compare_t_param_wr_to_pch_greater_than_row_timer[i]) ||
(CFG_REG_GRANT == 0 && t_param_wr_to_pch > row_timer[i])
)
begin
row_timer_combi[i] = offset_t_param_wr_to_pch;
end
else
begin
row_timer_combi[i] = row_timer[i] - 1'b1;
end
end
end
else
begin
if (row_timer[i] != 0)
begin
row_timer_combi[i] = row_timer[i] - 1'b1;
end
else
begin
row_timer_combi[i] = 0;
end
end
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
row_timer [i] <= 0;
row_timer_ready [i] <= 1'b0;
row_timer_pre_ready[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
// Reset row_timer after push
if (push_tbp[i])
begin
row_timer [i] <= 0;
row_timer_ready [i] <= 1'b1;
row_timer_pre_ready[i] <= 1'b1;
end
else if (act_grant[i])
begin
if (compare_t_param_act_to_pch_less_than_offset)
begin
row_timer [i] <= 0;
row_timer_ready [i] <= 1'b1;
row_timer_pre_ready[i] <= 1'b1;
end
else
begin
// Load tRAS after precharge command
row_timer [i] <= offset_t_param_act_to_pch;
row_timer_ready [i] <= 1'b0;
row_timer_pre_ready[i] <= 1'b0;
end
end
else if (pch_grant[i])
begin
if (compare_t_param_pch_to_valid_less_than_offset)
begin
row_timer [i] <= 0;
row_timer_ready [i] <= 1'b1;
row_timer_pre_ready[i] <= 1'b1;
end
else
begin
// Load tRP after precharge command
row_timer [i] <= offset_t_param_pch_to_valid;
row_timer_ready [i] <= 1'b0;
row_timer_pre_ready[i] <= 1'b0;
end
end
else if (col_grant[i])
begin
row_timer [i] <= row_timer_combi[i];
row_timer_ready [i] <= 1'b0;
row_timer_pre_ready[i] <= 1'b0;
end
else
begin
if (row_timer[i] != 0)
begin
row_timer[i] <= row_timer[i] - 1'b1;
end
if (row_timer[i] <= 1)
begin
row_timer_ready[i] <= 1'b1;
end
if (row_timer[i] <= 2)
begin
row_timer_pre_ready[i] <= 1'b1;
end
end
end
end
end
// Logic to let precharge request logic that it is ready to request now
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
pch_ready[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (open_row_pass[i] || open_row_pass_r[i] || pch_grant[i] || col_grant[i])
// disable pch_ready after open-row-pass and grant
// since precharge is not needed immediately after TBP is loaded
begin
pch_ready[i] <= 1'b0;
end
else if (row_timer_pre_ready[i] && ((trc_timer_pre_ready[i] && open_row_passed[i]) || !open_row_passed[i]) && !precharged[i])
// disable pch_ready if current TBP is precharged
// only compare with trc_timer if TBP is an open_row_pass command
begin
pch_ready[i] <= 1'b1;
end
else
begin
pch_ready[i] <= 1'b0;
end
end
end
end
// Logic to let sideband know which chip contains active banks
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_MEM_IF_CHIP; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
int_bank_closed[i][j] <= 1'b0;
end
end
end
else
begin
for (i=0; i<CFG_MEM_IF_CHIP; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (chipsel[j] == i && valid[j])
begin
if (sb_tbp_precharge_all[j])
begin
int_bank_closed[i][j] <= 1'b1;
end
else if (precharged_combi[j])
begin
int_bank_closed[i][j] <= 1'b1;
end
else if (activated_combi[j])
begin
int_bank_closed[i][j] <= 1'b0;
end
end
else
begin
int_bank_closed[i][j] <= 1'b1; // else default to '0'
end
end
end
end
end
// Logic to let sideband know which chip contains running timer
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_MEM_IF_CHIP; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
int_timer_ready[i][j] <= 1'b0;
end
end
end
else
begin
for (i=0; i<CFG_MEM_IF_CHIP; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (chipsel[j] == i)
begin
if (col_grant[j] || row_grant[j])
begin
int_timer_ready[i][j] <= 1'b0;
end
else if (trc_timer_pre_ready[j] && row_timer_pre_ready[j])
begin
int_timer_ready[i][j] <= 1'b1;
end
else
begin
int_timer_ready[i][j] <= 1'b0;
end
end
else
begin
int_timer_ready[i][j] <= 1'b1; // else default to '1'
end
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_MEM_IF_CHIP; i=i+1)
begin
for (j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
begin
int_shadow_timer_ready[i][j] <= 1'b0;
end
end
end
else
begin
for (i=0; i<CFG_MEM_IF_CHIP; i=i+1)
begin
for (j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
begin
if (CFG_ENABLE_SHADOW_TBP)
begin
if (shadow_chipsel[j] == i)
begin
if (push_tbp[j])
begin
int_shadow_timer_ready[i][j] <= 1'b0;
end
else if (shadow_row_timer_pre_ready[j])
begin
int_shadow_timer_ready[i][j] <= 1'b1;
end
else
begin
int_shadow_timer_ready[i][j] <= 1'b0;
end
end
else
begin
int_shadow_timer_ready[i][j] <= 1'b1; // else default to '1'
end
end
else
begin
int_shadow_timer_ready[i][j] <= one;
end
end
end
end
end
always @ (*)
begin
for (i=0; i<CFG_MEM_IF_CHIP; i=i+1)
begin
bank_closed[i] = &int_bank_closed[i];
timer_ready[i] = &{int_shadow_timer_ready[i], int_timer_ready[i]};
end
end
//----------------------------------------------------------------------------------------------------
// Age logic
//----------------------------------------------------------------------------------------------------
// To tell the current age of each TBP entry
// so that arbiter will be able to grant the oldest entry (if there is a tie-break)
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
age[i] <= 0;
else
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (i == j)
begin
age[i][j] <= 1'b0;
end
else
begin
if (load_tbp[i])
if (!flush_tbp[j] && (valid[j]))
age[i][j] <= 1'b1;
else
age[i][j] <= 1'b0;
else if (flush_tbp[j])
age[i][j] <= 1'b0;
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Starvation logic
//----------------------------------------------------------------------------------------------------
// Logic will increments when there is a col_grant to other TBP
// will cause priority to be asserted when the count reaches starvation threshold
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
starvation[i] <= 0;
else
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (load_tbp[i] || done[i]) // stop starvation count when the current TBP is done
starvation[i] <= 0;
else if (|col_grant && starvation[i] < cfg_starve_limit)
starvation[i] <= starvation[i]+1'b1;
end
end
//----------------------------------------------------------------------------------------------------
// Burst chop logic
//----------------------------------------------------------------------------------------------------
// Logic to determine whether we will issue burst chop in DDR3 mode only
generate
begin
if (CFG_DWIDTH_RATIO == 2)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
begin
burst_chop [i] <= 1'b0;
end
end
else
begin
for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
begin
if (cfg_type == `MMR_TYPE_DDR3)
begin
if (load_tbp [i])
begin
if (cmd_gen_size <= 2'd2 && cmd_gen_col [(CFG_DWIDTH_RATIO / 2)] == 1'b0)
burst_chop [i] <= 1'b1;
else if (cmd_gen_size == 1'b1)
burst_chop [i] <= 1'b1;
else
burst_chop [i] <= 1'b0;
end
end
else
begin
burst_chop [i] <= 1'b0;
end
end
end
end
end
else if (CFG_DWIDTH_RATIO == 4)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
begin
burst_chop [i] <= 1'b0;
end
end
else
begin
for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
begin
if (cfg_type == `MMR_TYPE_DDR3)
begin
if (load_tbp [i])
begin
if (cmd_gen_size == 1'b1)
burst_chop [i] <= 1'b1;
else
burst_chop [i] <= 1'b0;
end
end
else
begin
burst_chop [i] <= 1'b0;
end
end
end
end
end
else if (CFG_DWIDTH_RATIO == 8)
begin
// Burst chop is not available in quarter rate
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
begin
burst_chop [i] <= 1'b0;
end
end
else
begin
for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
begin
burst_chop [i] <= 1'b0;
end
end
end
end
end
endgenerate
//----------------------------------------------------------------------------------------------------------------
function integer log2;
input [31:0] value;
integer i;
begin
log2 = 0;
for(i = 0; 2**i < value; i = i + 1)
begin
log2 = i + 1;
end
end
endfunction
endmodule
|
// megafunction wizard: %ALTPLL%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module pll (
inclk0,
c0,
c1,
c2,
locked);
input inclk0;
output c0;
output c1;
output c2;
output locked;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "300.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "0.256000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "25.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "0.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "300.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "0.25600000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "25.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "6"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3125"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "16"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003,2004 Matt Ettus
// Copyright 2007 Free Software Foundation, Inc.
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
`define TX_IN_BAND
`define RX_IN_BAND
`include "config.vh"
`include "../../../firmware/include/fpga_regs_common.v"
`include "../../../firmware/include/fpga_regs_standard.v"
module usrp_inband_usb
(output MYSTERY_SIGNAL,
input master_clk,
input SCLK,
input SDI,
inout SDO,
input SEN_FPGA,
input FX2_1,
output FX2_2,
output FX2_3,
input wire [11:0] rx_a_a,
input wire [11:0] rx_b_a,
//input wire [11:0] rx_a_b,
//input wire [11:0] rx_b_b,
output wire [13:0] tx_a,
//output wire [13:0] tx_b,
output wire TXSYNC_A,
//output wire TXSYNC_B,
// USB interface
input usbclk,
input wire [5:0] usbctl,
output wire [1:0] usbrdy,
input wire [3:0] usbrdy2,
inout [15:0] usbdata, // NB Careful, inout
// These are the general purpose i/o's that go to the daughterboard slots
inout wire [15:0] io_tx_a,
//inout wire [15:0] io_tx_b,
inout wire [15:0] io_rx_a,
//inout wire [15:0] io_rx_b
output wire test_bit0,
output wire test_bit1
);
wire [15:0] debugdata,debugctrl;
assign MYSTERY_SIGNAL = 1'b0;
wire clk64;
assign clk64 = master_clk;
wire WR = usbctl[0];
wire RD = usbctl[1];
wire OE = usbctl[2];
wire have_space, have_pkt_rdy;
assign usbrdy[0] = have_space;
assign usbrdy[1] = have_pkt_rdy;
wire rx_overrun;
wire clear_status = FX2_1;
assign FX2_2 = rx_overrun;
assign FX2_3 = (tx_underrun == 0);
wire [15:0] usbdata_out;
wire [3:0] dac0mux,dac1mux,dac2mux,dac3mux;
wire tx_realsignals;
wire [3:0] rx_numchan;
wire [2:0] tx_numchan;
wire [7:0] interp_rate, decim_rate;
wire [15:0] tx_debugbus, rx_debugbus;
wire enable_tx, enable_rx;
wire tx_dsp_reset, rx_dsp_reset, tx_bus_reset, rx_bus_reset;
wire [7:0] settings;
// Tri-state bus macro
bustri bustri( .data(usbdata_out),.enabledt(OE),.tridata(usbdata) );
wire [15:0] ch0tx,ch1tx,ch2tx,ch3tx; //,ch4tx,ch5tx,ch6tx,ch7tx;
wire [15:0] ch0rx,ch1rx,ch2rx,ch3rx,ch4rx,ch5rx,ch6rx,ch7rx;
// TX
wire [15:0] i_out_0,i_out_1,q_out_0,q_out_1;
wire [15:0] bb_tx_i0,bb_tx_q0,bb_tx_i1,bb_tx_q1; // bb_tx_i2,bb_tx_q2,bb_tx_i3,bb_tx_q3;
wire strobe_interp, tx_sample_strobe;
wire tx_empty;
wire serial_strobe;
wire [6:0] serial_addr;
wire [31:0] serial_data;
reg [15:0] debug_counter;
reg [15:0] loopback_i_0,loopback_q_0;
//Connection RX inband <-> TX inband
wire rx_WR;
wire [15:0] rx_databus;
wire rx_WR_done;
wire rx_WR_enabled;
wire [31:0] rssi_0,rssi_1,rssi_2,rssi_3;
wire [15:0] reg_0,reg_1,reg_2,reg_3;
wire [6:0] reg_addr;
wire [31:0] reg_data_out;
wire [31:0] reg_data_in;
wire [1:0] reg_io_enable;
wire [31:0] rssi_threshhold;
wire [31:0] rssi_wait;
wire [6:0] addr_wr;
wire [31:0] data_wr;
wire strobe_wr;
wire [6:0] addr_db;
wire [31:0] data_db;
wire strobe_db;
assign serial_strobe = strobe_db | strobe_wr;
assign serial_addr = (strobe_db)? (addr_db) : (addr_wr);
assign serial_data = (strobe_db)? (data_db) : (data_wr);
//assign serial_strobe = strobe_db;
//assign serial_data = data_db;
//assign serial_addr = addr_db;
//wires for register connection
wire [11:0] atr_tx_delay;
wire [11:0] atr_rx_delay;
wire [7:0] master_controls;
wire [3:0] debug_en;
wire [15:0] atr_mask_0;
wire [15:0] atr_txval_0;
wire [15:0] atr_rxval_0;
wire [15:0] atr_mask_1;
wire [15:0] atr_txval_1;
wire [15:0] atr_rxval_1;
wire [15:0] atr_mask_2;
wire [15:0] atr_txval_2;
wire [15:0] atr_rxval_2;
wire [15:0] atr_mask_3;
wire [15:0] atr_txval_3;
wire [15:0] atr_rxval_3;
wire [7:0] txa_refclk;
wire [7:0] txb_refclk;
wire [7:0] rxa_refclk;
wire [7:0] rxb_refclk;
register_io register_control
(.clk(clk64),.reset(1'b0),.enable(reg_io_enable),.addr(reg_addr),.datain(reg_data_in),
.dataout(reg_data_out), .data_wr(data_wr), .addr_wr(addr_wr), .strobe_wr(strobe_wr),
.rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2),
.rssi_3(rssi_3), .threshhold(rssi_threshhold), .rssi_wait(rssi_wait),
.reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3),
.interp_rate(interp_rate), .decim_rate(decim_rate), .misc(settings),
.txmux({dac3mux,dac2mux,dac1mux,dac0mux,tx_realsignals,tx_numchan}),
.atr_tx_delay(atr_tx_delay), .atr_rx_delay(atr_rx_delay), .master_controls(master_controls),
.debug_en(debug_en), .atr_mask_0(atr_mask_0), .atr_txval_0(atr_txval_0), .atr_rxval_0(atr_rxval_0),
.atr_mask_1(atr_mask_1), .atr_txval_1(atr_txval_1), .atr_rxval_1(atr_rxval_1),
.atr_mask_2(atr_mask_2), .atr_txval_2(atr_txval_2), .atr_rxval_2(atr_rxval_2),
.atr_mask_3(atr_mask_3), .atr_txval_3(atr_txval_3), .atr_rxval_3(atr_rxval_3),
.txa_refclk(txa_refclk), .txb_refclk(txb_refclk), .rxa_refclk(rxa_refclk), .rxb_refclk(rxb_refclk));
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Transmit Side
`ifdef TX_ON
assign bb_tx_i0 = ch0tx;
assign bb_tx_q0 = ch1tx;
assign bb_tx_i1 = ch2tx;
assign bb_tx_q1 = ch3tx;
wire [1:0] tx_underrun;
wire stop;
wire [15:0] stop_time;
`ifdef TX_IN_BAND
tx_buffer_inband tx_buffer
( .usbclk(usbclk),.bus_reset(tx_bus_reset),.reset(tx_dsp_reset),
.usbdata(usbdata),.WR(WR),.have_space(have_space),
.tx_underrun(tx_underrun),.channels({tx_numchan,1'b0}),
.tx_i_0(ch0tx),.tx_q_0(ch1tx),
.tx_i_1(ch2tx),.tx_q_1(ch3tx),
.tx_i_2(),.tx_q_2(),
.tx_i_3(),.tx_q_3(),
.txclk(clk64),.txstrobe(strobe_interp),
.clear_status(clear_status),
.tx_empty(tx_empty),
.rx_WR(rx_WR),
.rx_databus(rx_databus),
.rx_WR_done(rx_WR_done),
.rx_WR_enabled(rx_WR_enabled),
.reg_addr(reg_addr),
.reg_data_out(reg_data_out),
.reg_data_in(reg_data_in),
.reg_io_enable(reg_io_enable),
.debugbus(tx_debugbus),
.rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2),
.rssi_3(rssi_3), .threshhold(rssi_threshhold), .rssi_wait(rssi_wait),
.stop(stop), .stop_time(stop_time),
.test_bit0(test_bit0),
.test_bit1(test_bit1));
`else
tx_buffer tx_buffer
( .usbclk(usbclk),.bus_reset(tx_bus_reset),.reset(tx_dsp_reset),
.usbdata(usbdata),.WR(WR),.have_space(have_space),.tx_underrun(tx_underrun),
.channels({tx_numchan,1'b0}),
.tx_i_0(ch0tx),.tx_q_0(ch1tx),
.tx_i_1(ch2tx),.tx_q_1(ch3tx),
.tx_i_2(),.tx_q_2(),
.tx_i_3(),.tx_q_3(),
.txclk(clk64),.txstrobe(strobe_interp),
.clear_status(clear_status),
.tx_empty(tx_empty));
`endif
`ifdef TX_EN_0
tx_chain tx_chain_0
( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx),
.interp_rate(interp_rate),.sample_strobe(tx_sample_strobe),
.interpolator_strobe(strobe_interp),.freq(),
.i_in(bb_tx_i0),.q_in(bb_tx_q0),.i_out(i_out_0),.q_out(q_out_0) );
`else
assign i_out_0=16'd0;
assign q_out_0=16'd0;
`endif
`ifdef TX_EN_1
tx_chain tx_chain_1
( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx),
.interp_rate(interp_rate),.sample_strobe(tx_sample_strobe),
.interpolator_strobe(strobe_interp),.freq(),
.i_in(bb_tx_i1),.q_in(bb_tx_q1),.i_out(i_out_1),.q_out(q_out_1) );
`else
assign i_out_1=16'd0;
assign q_out_1=16'd0;
`endif
setting_reg #(`FR_TX_MUX)
sr_txmux(.clock(clk64),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),
.out({dac3mux,dac2mux,dac1mux,dac0mux,tx_realsignals,tx_numchan}));
wire [15:0] tx_a_a = dac0mux[3] ? (dac0mux[1] ? (dac0mux[0] ? q_out_1 : i_out_1) : (dac0mux[0] ? q_out_0 : i_out_0)) : 16'b0011111111111111;
wire [15:0] tx_b_a = dac1mux[3] ? (dac1mux[1] ? (dac1mux[0] ? q_out_1 : i_out_1) : (dac1mux[0] ? q_out_0 : i_out_0)) : 16'b0011111111111111;
//wire [15:0] tx_a_b = dac2mux[3] ? (dac2mux[1] ? (dac2mux[0] ? q_out_1 : i_out_1) : (dac2mux[0] ? q_out_0 : i_out_0)) : 16'b0;
//wire [15:0] tx_b_b = dac3mux[3] ? (dac3mux[1] ? (dac3mux[0] ? q_out_1 : i_out_1) : (dac3mux[0] ? q_out_0 : i_out_0)) : 16'b0;
wire txsync = tx_sample_strobe;
assign TXSYNC_A = txsync;
//assign TXSYNC_B = txsync;
assign tx_a = txsync ? tx_b_a[15:2] : tx_a_a[15:2];
//assign tx_b = txsync ? tx_b_b[15:2] : tx_a_b[15:2];
`endif // `ifdef TX_ON
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Receive Side
`ifdef RX_ON
wire rx_sample_strobe,strobe_decim,hb_strobe;
wire [15:0] bb_rx_i0,bb_rx_q0,bb_rx_i1,bb_rx_q1,
bb_rx_i2,bb_rx_q2,bb_rx_i3,bb_rx_q3;
wire loopback = settings[0];
wire counter = settings[1];
always @(posedge clk64)
if(rx_dsp_reset)
debug_counter <= #1 16'd0;
else if(~enable_rx)
debug_counter <= #1 16'd0;
else if(hb_strobe)
debug_counter <=#1 debug_counter + 16'd2;
always @(posedge clk64)
if(strobe_interp)
begin
loopback_i_0 <= #1 ch0tx;
loopback_q_0 <= #1 ch1tx;
end
assign ch0rx = bb_rx_i0;
assign ch1rx = bb_rx_q0;
assign ch2rx = bb_rx_i1;
assign ch3rx = bb_rx_q1;
assign ch4rx = bb_rx_i2;
assign ch5rx = bb_rx_q2;
assign ch6rx = bb_rx_i3;
assign ch7rx = bb_rx_q3;
wire [15:0] ddc0_in_i,ddc0_in_q,ddc1_in_i,ddc1_in_q,ddc2_in_i,ddc2_in_q,ddc3_in_i,ddc3_in_q;
adc_interface adc_interface(.clock(clk64),.reset(rx_dsp_reset),.enable(1'b1),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.rx_a_a(rx_a_a),.rx_b_a(rx_b_a),.rx_a_b(rx_a_a),.rx_b_b(rx_b_a),
.rssi_0(rssi_0),.rssi_1(rssi_1),.rssi_2(rssi_2),.rssi_3(rssi_3),
.ddc0_in_i(ddc0_in_i),.ddc0_in_q(ddc0_in_q),
.ddc1_in_i(ddc1_in_i),.ddc1_in_q(ddc1_in_q),
.ddc2_in_i(ddc2_in_i),.ddc2_in_q(ddc2_in_q),
.ddc3_in_i(ddc3_in_i),.ddc3_in_q(ddc3_in_q),.rx_numchan(rx_numchan));
`ifdef RX_IN_BAND
rx_buffer_inband rx_buffer
( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset),
.reset_regs(rx_dsp_reset),
.usbdata(usbdata_out),.RD(RD),.have_pkt_rdy(have_pkt_rdy),.rx_overrun(rx_overrun),
.channels(rx_numchan),
.ch_0(ch0rx),.ch_1(ch1rx),
.ch_2(ch2rx),.ch_3(ch3rx),
.ch_4(ch4rx),.ch_5(ch5rx),
.ch_6(ch6rx),.ch_7(ch7rx),
.rxclk(clk64),.rxstrobe(hb_strobe),
.clear_status(clear_status),
.rx_WR(rx_WR),
.rx_databus(rx_databus),
.rx_WR_done(rx_WR_done),
.rx_WR_enabled(rx_WR_enabled),
.debugbus(rx_debugbus),
.rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2), .rssi_3(rssi_3),
.tx_underrun(tx_underrun));
`else
rx_buffer rx_buffer
( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset),
.reset_regs(rx_dsp_reset),
.usbdata(usbdata_out),.RD(RD),.have_pkt_rdy(have_pkt_rdy),.rx_overrun(rx_overrun),
.channels(rx_numchan),
.ch_0(ch0rx),.ch_1(ch1rx),
.ch_2(ch2rx),.ch_3(ch3rx),
.ch_4(ch4rx),.ch_5(ch5rx),
.ch_6(ch6rx),.ch_7(ch7rx),
.rxclk(clk64),.rxstrobe(hb_strobe),
.clear_status(clear_status),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe));
`endif
`ifdef RX_EN_0
rx_chain #(`FR_RX_FREQ_0,`FR_RX_PHASE_0) rx_chain_0
( .clock(clk64),.reset(1'b0),.enable(enable_rx),
.decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(hb_strobe),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.i_in(ddc0_in_i),.q_in(ddc0_in_q),.i_out(bb_rx_i0),.q_out(bb_rx_q0),.debugdata(debugdata),.debugctrl(debugctrl));
`else
assign bb_rx_i0=16'd0;
assign bb_rx_q0=16'd0;
`endif
`ifdef RX_EN_1
rx_chain #(`FR_RX_FREQ_1,`FR_RX_PHASE_1) rx_chain_1
( .clock(clk64),.reset(1'b0),.enable(enable_rx),
.decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.i_in(ddc1_in_i),.q_in(ddc1_in_q),.i_out(bb_rx_i1),.q_out(bb_rx_q1));
`else
assign bb_rx_i1=16'd0;
assign bb_rx_q1=16'd0;
`endif
`ifdef RX_EN_2
rx_chain #(`FR_RX_FREQ_2,`FR_RX_PHASE_2) rx_chain_2
( .clock(clk64),.reset(1'b0),.enable(enable_rx),
.decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.i_in(ddc2_in_i),.q_in(ddc2_in_q),.i_out(bb_rx_i2),.q_out(bb_rx_q2));
`else
assign bb_rx_i2=16'd0;
assign bb_rx_q2=16'd0;
`endif
`ifdef RX_EN_3
rx_chain #(`FR_RX_FREQ_3,`FR_RX_PHASE_3) rx_chain_3
( .clock(clk64),.reset(1'b0),.enable(enable_rx),
.decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.i_in(ddc3_in_i),.q_in(ddc3_in_q),.i_out(bb_rx_i3),.q_out(bb_rx_q3));
`else
assign bb_rx_i3=16'd0;
assign bb_rx_q3=16'd0;
`endif
`endif // `ifdef RX_ON
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Control Functions
wire [31:0] capabilities;
assign capabilities[7] = `TX_CAP_HB;
assign capabilities[6:4] = `TX_CAP_NCHAN;
assign capabilities[3] = `RX_CAP_HB;
assign capabilities[2:0] = `RX_CAP_NCHAN;
serial_io serial_io
( .master_clk(clk64),.serial_clock(SCLK),.serial_data_in(SDI),
.enable(SEN_FPGA),.reset(1'b0),.serial_data_out(SDO),
.serial_addr(addr_db),.serial_data(data_db),.serial_strobe(strobe_db),
.readback_0({io_rx_a,io_tx_a}),.readback_1({io_rx_a,io_tx_a}),.readback_2(capabilities),.readback_3(32'hf0f0931a),
.readback_4(rssi_0),.readback_5(rssi_1),.readback_6(rssi_2),.readback_7(rssi_3)
);
//implementing freeze mode
/*
reg [15:0] timestop;
wire stop;
wire [15:0] stop_time;
assign clk64 = (timestop == 0) ? master_clk : 0;
always @(posedge master_clk)
if (timestop[15:0] != 0)
timestop <= timestop - 16'd1;
else if (stop)
timestop <= stop_time;
*/
master_control master_control
( .master_clk(clk64),.usbclk(usbclk),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset),
.tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset),
.enable_tx(enable_tx),.enable_rx(enable_rx),
.interp_rate(interp_rate),.decim_rate(decim_rate),
.tx_sample_strobe(tx_sample_strobe),.strobe_interp(strobe_interp),
.rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim),
.tx_empty(tx_empty), .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3),
.atr_tx_delay(atr_tx_delay), .atr_rx_delay(atr_rx_delay),
.master_controls(master_controls), .debug_en(debug_en),
.atr_mask_0(atr_mask_0), .atr_txval_0(atr_txval_0), .atr_rxval_0(atr_rxval_0),
.atr_mask_1(atr_mask_1), .atr_txval_1(atr_txval_1), .atr_rxval_1(atr_rxval_1),
.atr_mask_2(atr_mask_2), .atr_txval_2(atr_txval_2), .atr_rxval_2(atr_rxval_2),
.atr_mask_3(atr_mask_3), .atr_txval_3(atr_txval_3), .atr_rxval_3(atr_rxval_3),
.txa_refclk(txa_refclk), .txb_refclk(txb_refclk), .rxa_refclk(rxa_refclk), .rxb_refclk(rxb_refclk),
.debug_0(tx_debugbus), .debug_1(rx_debugbus));
io_pins io_pins
(.io_0(io_tx_a),.io_1(io_rx_a),
.reg_0(reg_0),.reg_1(reg_1),
.clock(clk64),.rx_reset(rx_dsp_reset),.tx_reset(tx_dsp_reset),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe));
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Misc Settings
setting_reg #(`FR_MODE) sr_misc(.clock(clk64),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(settings));
reg forb;
always @(posedge usbclk)
begin
if (strobe_db) forb <= 1;
end
endmodule // usrp_inband_usb
|
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_protocol_converter_v2_1_9_b2s_b_channel.v
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_9_b2s_b_channel #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of ID signals.
// Range: >= 1.
parameter integer C_ID_WIDTH = 4
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk,
input wire reset,
// AXI signals
output wire [C_ID_WIDTH-1:0] s_bid,
output wire [1:0] s_bresp,
output wire s_bvalid,
input wire s_bready,
input wire [1:0] m_bresp,
input wire m_bvalid,
output wire m_bready,
// Signals to/from the axi_protocol_converter_v2_1_9_b2s_aw_channel modules
input wire b_push,
input wire [C_ID_WIDTH-1:0] b_awid,
input wire [7:0] b_awlen,
input wire b_resp_rdy,
output wire b_full
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
// AXI protocol responses:
localparam [1:0] LP_RESP_OKAY = 2'b00;
localparam [1:0] LP_RESP_EXOKAY = 2'b01;
localparam [1:0] LP_RESP_SLVERROR = 2'b10;
localparam [1:0] LP_RESP_DECERR = 2'b11;
// FIFO settings
localparam P_WIDTH = C_ID_WIDTH + 8;
localparam P_DEPTH = 4;
localparam P_AWIDTH = 2;
localparam P_RWIDTH = 2;
localparam P_RDEPTH = 4;
localparam P_RAWIDTH = 2;
////////////////////////////////////////////////////////////////////////////////
// Wire and register declarations
////////////////////////////////////////////////////////////////////////////////
reg bvalid_i;
wire [C_ID_WIDTH-1:0] bid_i;
wire shandshake;
reg shandshake_r;
wire mhandshake;
reg mhandshake_r;
wire b_empty;
wire bresp_full;
wire bresp_empty;
wire [7:0] b_awlen_i;
reg [7:0] bresp_cnt;
reg [1:0] s_bresp_acc;
wire [1:0] s_bresp_acc_r;
reg [1:0] s_bresp_i;
wire need_to_update_bresp;
wire bresp_push;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// assign AXI outputs
assign s_bid = bid_i;
assign s_bresp = s_bresp_acc_r;
assign s_bvalid = bvalid_i;
assign shandshake = s_bvalid & s_bready;
assign mhandshake = m_bvalid & m_bready;
always @(posedge clk) begin
if (reset | shandshake) begin
bvalid_i <= 1'b0;
end else if (~b_empty & ~shandshake_r & ~bresp_empty) begin
bvalid_i <= 1'b1;
end
end
always @(posedge clk) begin
shandshake_r <= shandshake;
mhandshake_r <= mhandshake;
end
axi_protocol_converter_v2_1_9_b2s_simple_fifo #(
.C_WIDTH (P_WIDTH),
.C_AWIDTH (P_AWIDTH),
.C_DEPTH (P_DEPTH)
)
bid_fifo_0
(
.clk ( clk ) ,
.rst ( reset ) ,
.wr_en ( b_push ) ,
.rd_en ( shandshake_r ) ,
.din ( {b_awid, b_awlen} ) ,
.dout ( {bid_i, b_awlen_i}) ,
.a_full ( ) ,
.full ( b_full ) ,
.a_empty ( ) ,
.empty ( b_empty )
);
assign m_bready = ~mhandshake_r & bresp_empty;
/////////////////////////////////////////////////////////////////////////////
// Update if more critical.
assign need_to_update_bresp = ( m_bresp > s_bresp_acc );
// Select accumultated or direct depending on setting.
always @( * ) begin
if ( need_to_update_bresp ) begin
s_bresp_i = m_bresp;
end else begin
s_bresp_i = s_bresp_acc;
end
end
/////////////////////////////////////////////////////////////////////////////
// Accumulate MI-side BRESP.
always @ (posedge clk) begin
if (reset | bresp_push ) begin
s_bresp_acc <= LP_RESP_OKAY;
end else if ( mhandshake ) begin
s_bresp_acc <= s_bresp_i;
end
end
assign bresp_push = ( mhandshake_r ) & (bresp_cnt == b_awlen_i) & ~b_empty;
always @ (posedge clk) begin
if (reset | bresp_push ) begin
bresp_cnt <= 8'h00;
end else if ( mhandshake_r ) begin
bresp_cnt <= bresp_cnt + 1'b1;
end
end
axi_protocol_converter_v2_1_9_b2s_simple_fifo #(
.C_WIDTH (P_RWIDTH),
.C_AWIDTH (P_RAWIDTH),
.C_DEPTH (P_RDEPTH)
)
bresp_fifo_0
(
.clk ( clk ) ,
.rst ( reset ) ,
.wr_en ( bresp_push ) ,
.rd_en ( shandshake_r ) ,
.din ( s_bresp_acc ) ,
.dout ( s_bresp_acc_r) ,
.a_full ( ) ,
.full ( bresp_full ) ,
.a_empty ( ) ,
.empty ( bresp_empty )
);
endmodule
`default_nettype wire
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2017 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2018.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / HBM_REF_CLK
// /___/ /\ Filename : HBM_REF_CLK.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module HBM_REF_CLK
`ifdef XIL_TIMING
#(
parameter LOC = "UNPLACED"
)
`endif
(
input REF_CLK
);
// define constants
localparam MODULE_NAME = "HBM_REF_CLK";
tri0 glblGSR = glbl.GSR;
`ifndef XIL_TIMING
initial begin
$display("Error: [Unisim %s-100] SIMPRIM primitive is not intended for direct instantiation in RTL or functional netlists. This primitive is only available in the SIMPRIM library for implemented netlists, please ensure you are pointing to the correct library. Instance %m", MODULE_NAME);
#1 $finish;
end
`endif
// begin behavioral model
// end behavioral model
endmodule
`endcelldefine
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2014 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2014.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Differential Input Buffer with Offset Calibration
// /___/ /\ Filename : IBUFDSE3.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module IBUFDSE3 #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter DIFF_TERM = "FALSE",
parameter DQS_BIAS = "FALSE",
parameter IBUF_LOW_PWR = "TRUE",
parameter IOSTANDARD = "DEFAULT",
parameter integer SIM_INPUT_BUFFER_OFFSET = 0,
parameter USE_IBUFDISABLE = "FALSE"
)(
output O,
input I,
input IB,
input IBUFDISABLE,
input [3:0] OSC,
input [1:0] OSC_EN
);
// define constants
localparam MODULE_NAME = "IBUFDSE3";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
localparam DIFF_TERM_FALSE = 0;
localparam DIFF_TERM_TRUE = 1;
localparam DQS_BIAS_FALSE = 0;
localparam DQS_BIAS_TRUE = 1;
localparam IBUF_LOW_PWR_FALSE = 1;
localparam IBUF_LOW_PWR_TRUE = 0;
localparam USE_IBUFDISABLE_FALSE = 0;
localparam USE_IBUFDISABLE_TRUE = 1;
// include dynamic registers - XILINX test only
reg trig_attr = 1'b0;
localparam [40:1] DIFF_TERM_REG = DIFF_TERM;
localparam [40:1] DQS_BIAS_REG = DQS_BIAS;
localparam [40:1] IBUF_LOW_PWR_REG = IBUF_LOW_PWR;
localparam integer SIM_INPUT_BUFFER_OFFSET_REG = SIM_INPUT_BUFFER_OFFSET;
localparam [40:1] USE_IBUFDISABLE_REG = USE_IBUFDISABLE;
wire DIFF_TERM_BIN;
wire DQS_BIAS_BIN;
wire IBUF_LOW_PWR_BIN;
wire USE_IBUFDISABLE_BIN;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
tri0 glblGSR = glbl.GSR;
reg O_out;
reg O_OSC_in;
wire O_delay;
wire IBUFDISABLE_in;
wire IB_in;
wire I_in;
wire [1:0] OSC_EN_in;
wire [3:0] OSC_in;
wire IBUFDISABLE_delay;
wire IB_delay;
wire I_delay;
wire [1:0] OSC_EN_delay;
wire [3:0] OSC_delay;
assign #(out_delay) O = O_delay;
// inputs with no timing checks
assign #(in_delay) IBUFDISABLE_delay = IBUFDISABLE;
assign #(in_delay) IB_delay = IB;
assign #(in_delay) I_delay = I;
assign #(in_delay) OSC_EN_delay = OSC_EN;
assign #(in_delay) OSC_delay = OSC;
assign IBUFDISABLE_in = IBUFDISABLE_delay;
assign IB_in = IB_delay;
assign I_in = I_delay;
assign OSC_EN_in = OSC_EN_delay;
assign OSC_in = OSC_delay;
integer OSC_int = 0;
assign O_delay = (OSC_EN_in === 2'b11) ? O_OSC_in : (OSC_EN_in === 2'b10 || OSC_EN_in === 2'b01) ? 1'bx : O_out;
always @ (OSC_in or OSC_EN_in) begin
OSC_int = OSC_in[2:0] * 5;
if (OSC_in[3] == 1'b0 )
OSC_int = -1*OSC_int;
if(OSC_EN_in == 2'b11) begin
if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) < 0)
O_OSC_in <= 1'b0;
else if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) > 0)
O_OSC_in <= 1'b1;
else if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) == 0)
O_OSC_in <= ~O_OSC_in;
end
end
initial begin
if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) < 0)
O_OSC_in <= 1'b0;
else if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) > 0)
O_OSC_in <= 1'b1;
else if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) == 0)
O_OSC_in <= 1'bx;
end
assign DIFF_TERM_BIN =
(DIFF_TERM_REG == "FALSE") ? DIFF_TERM_FALSE :
(DIFF_TERM_REG == "TRUE") ? DIFF_TERM_TRUE :
DIFF_TERM_FALSE;
assign DQS_BIAS_BIN =
(DQS_BIAS_REG == "FALSE") ? DQS_BIAS_FALSE :
(DQS_BIAS_REG == "TRUE") ? DQS_BIAS_TRUE :
DQS_BIAS_FALSE;
assign IBUF_LOW_PWR_BIN =
(IBUF_LOW_PWR_REG == "TRUE") ? IBUF_LOW_PWR_TRUE :
(IBUF_LOW_PWR_REG == "FALSE") ? IBUF_LOW_PWR_FALSE :
IBUF_LOW_PWR_TRUE;
assign USE_IBUFDISABLE_BIN =
(USE_IBUFDISABLE_REG == "FALSE") ? USE_IBUFDISABLE_FALSE :
(USE_IBUFDISABLE_REG == "TRUE") ? USE_IBUFDISABLE_TRUE :
USE_IBUFDISABLE_FALSE;
initial begin
#1;
trig_attr = ~trig_attr;
end
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((SIM_INPUT_BUFFER_OFFSET_REG < -50) || (SIM_INPUT_BUFFER_OFFSET_REG > 50))) begin
$display("Error: [Unisim %s-105] SIM_INPUT_BUFFER_OFFSET attribute is set to %d. Legal values for this attribute are -50 to 50. Instance: %m", MODULE_NAME, SIM_INPUT_BUFFER_OFFSET_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(DIFF_TERM_REG != "TRUE" && DIFF_TERM_REG != "FALSE")) begin
$display("Error: [Unisim %s-101] DIFF_TERM attribute is set to %s. Legal values for this attribute are TRUE or FALSE. . Instance: %m", MODULE_NAME, DIFF_TERM_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DQS_BIAS_REG != "FALSE") &&
(DQS_BIAS_REG != "TRUE"))) begin
$display("Error: [Unisim %s-102] DQS_BIAS attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, DQS_BIAS_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((IBUF_LOW_PWR_REG != "TRUE") &&
(IBUF_LOW_PWR_REG != "FALSE"))) begin
$display("Error: [Unisim %s-103] IBUF_LOW_PWR attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, IBUF_LOW_PWR_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((USE_IBUFDISABLE_REG != "FALSE") &&
(USE_IBUFDISABLE_REG != "TRUE"))) begin
$display("Error: [Unisim %s-106] USE_IBUFDISABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, USE_IBUFDISABLE_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
always @(I_in or IB_in or DQS_BIAS_BIN or IBUFDISABLE_in or USE_IBUFDISABLE_BIN) begin
if (USE_IBUFDISABLE_BIN == 1'b1 && IBUFDISABLE_in == 1'b1)
O_out <= 1'b0;
else if ((USE_IBUFDISABLE_BIN == 1'b1 && IBUFDISABLE_in == 1'b0) || (USE_IBUFDISABLE_BIN == 1'b0)) begin
if (I_in == 1'b1 && IB_in == 1'b0)
O_out <= 1'b1;
else if (I_in == 1'b0 && IB_in == 1'b1)
O_out <= 1'b0;
else if ((I_in === 1'bz || I_in == 1'b0) && (IB_in === 1'bz || IB_in == 1'b1))
if (DQS_BIAS_BIN == 1'b1)
O_out <= 1'b0;
else
O_out <= 1'bx;
else if ((I_in === 1'bx) || (IB_in === 1'bx))
O_out <= 1'bx;
end
else begin
O_out <= 1'bx;
end
end
endmodule
`endcelldefine
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module gen_sync
( input clock,
input reset,
input enable,
input [7:0] rate,
output wire sync );
// parameter width = 8;
reg [7:0] counter;
assign sync = |(((rate+1)>>1)& counter);
always @(posedge clock)
if(reset || ~enable)
counter <= #1 0;
else if(counter == rate)
counter <= #1 0;
else
counter <= #1 counter + 8'd1;
endmodule // gen_sync
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2015 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
Require Import ZAxioms ZMulOrder ZSgnAbs NZDiv.
(** * Euclidean Division for integers, Euclid convention
We use here the "usual" formulation of the Euclid Theorem
[forall a b, b<>0 -> exists b q, a = b*q+r /\ 0 < r < |b| ]
The outcome of the modulo function is hence always positive.
This corresponds to convention "E" in the following paper:
R. Boute, "The Euclidean definition of the functions div and mod",
ACM Transactions on Programming Languages and Systems,
Vol. 14, No.2, pp. 127-144, April 1992.
See files [ZDivTrunc] and [ZDivFloor] for others conventions.
We simply extend NZDiv with a bound for modulo that holds
regardless of the sign of a and b. This new specification
subsume mod_bound_pos, which nonetheless stays there for
subtyping. Note also that ZAxiomSig now already contain
a div and a modulo (that follow the Floor convention).
We just ignore them here.
*)
Module Type EuclidSpec (Import A : ZAxiomsSig')(Import B : DivMod' A).
Axiom mod_always_pos : forall a b, b ~= 0 -> 0 <= a mod b < abs b.
End EuclidSpec.
Module Type ZEuclid (Z:ZAxiomsSig) := NZDiv.NZDiv Z <+ EuclidSpec Z.
Module Type ZEuclid' (Z:ZAxiomsSig) := NZDiv.NZDiv' Z <+ EuclidSpec Z.
Module ZEuclidProp
(Import A : ZAxiomsSig')
(Import B : ZMulOrderProp A)
(Import C : ZSgnAbsProp A B)
(Import D : ZEuclid' A).
Module Import Private_NZDiv := Nop <+ NZDivProp A D B.
(** Another formulation of the main equation *)
Lemma mod_eq :
forall a b, b~=0 -> a mod b == a - b*(a/b).
Proof.
intros.
rewrite <- add_move_l.
symmetry. now apply div_mod.
Qed.
Ltac pos_or_neg a :=
let LT := fresh "LT" in
let LE := fresh "LE" in
destruct (le_gt_cases 0 a) as [LE|LT]; [|rewrite <- opp_pos_neg in LT].
(** Uniqueness theorems *)
Theorem div_mod_unique : forall b q1 q2 r1 r2 : t,
0<=r1<abs b -> 0<=r2<abs b ->
b*q1+r1 == b*q2+r2 -> q1 == q2 /\ r1 == r2.
Proof.
intros b q1 q2 r1 r2 Hr1 Hr2 EQ.
pos_or_neg b.
rewrite abs_eq in * by trivial.
apply div_mod_unique with b; trivial.
rewrite abs_neq' in * by auto using lt_le_incl.
rewrite eq_sym_iff. apply div_mod_unique with (-b); trivial.
rewrite 2 mul_opp_l.
rewrite add_move_l, sub_opp_r.
rewrite <-add_assoc.
symmetry. rewrite add_move_l, sub_opp_r.
now rewrite (add_comm r2), (add_comm r1).
Qed.
Theorem div_unique:
forall a b q r, 0<=r<abs b -> a == b*q + r -> q == a/b.
Proof.
intros a b q r Hr EQ.
assert (Hb : b~=0).
pos_or_neg b.
rewrite abs_eq in Hr; intuition; order.
rewrite <- opp_0, eq_opp_r. rewrite abs_neq' in Hr; intuition; order.
destruct (div_mod_unique b q (a/b) r (a mod b)); trivial.
now apply mod_always_pos.
now rewrite <- div_mod.
Qed.
Theorem mod_unique:
forall a b q r, 0<=r<abs b -> a == b*q + r -> r == a mod b.
Proof.
intros a b q r Hr EQ.
assert (Hb : b~=0).
pos_or_neg b.
rewrite abs_eq in Hr; intuition; order.
rewrite <- opp_0, eq_opp_r. rewrite abs_neq' in Hr; intuition; order.
destruct (div_mod_unique b q (a/b) r (a mod b)); trivial.
now apply mod_always_pos.
now rewrite <- div_mod.
Qed.
(** Sign rules *)
Lemma div_opp_r : forall a b, b~=0 -> a/(-b) == -(a/b).
Proof.
intros. symmetry.
apply div_unique with (a mod b).
rewrite abs_opp; now apply mod_always_pos.
rewrite mul_opp_opp; now apply div_mod.
Qed.
Lemma mod_opp_r : forall a b, b~=0 -> a mod (-b) == a mod b.
Proof.
intros. symmetry.
apply mod_unique with (-(a/b)).
rewrite abs_opp; now apply mod_always_pos.
rewrite mul_opp_opp; now apply div_mod.
Qed.
Lemma div_opp_l_z : forall a b, b~=0 -> a mod b == 0 ->
(-a)/b == -(a/b).
Proof.
intros a b Hb Hab. symmetry.
apply div_unique with (-(a mod b)).
rewrite Hab, opp_0. split; [order|].
pos_or_neg b; [rewrite abs_eq | rewrite abs_neq']; order.
now rewrite mul_opp_r, <-opp_add_distr, <-div_mod.
Qed.
Lemma div_opp_l_nz : forall a b, b~=0 -> a mod b ~= 0 ->
(-a)/b == -(a/b)-sgn b.
Proof.
intros a b Hb Hab. symmetry.
apply div_unique with (abs b -(a mod b)).
rewrite lt_sub_lt_add_l.
rewrite <- le_add_le_sub_l. nzsimpl.
rewrite <- (add_0_l (abs b)) at 2.
rewrite <- add_lt_mono_r.
destruct (mod_always_pos a b); intuition order.
rewrite <- 2 add_opp_r, mul_add_distr_l, 2 mul_opp_r.
rewrite sgn_abs.
rewrite add_shuffle2, add_opp_diag_l; nzsimpl.
rewrite <-opp_add_distr, <-div_mod; order.
Qed.
Lemma mod_opp_l_z : forall a b, b~=0 -> a mod b == 0 ->
(-a) mod b == 0.
Proof.
intros a b Hb Hab. symmetry.
apply mod_unique with (-(a/b)).
split; [order|now rewrite abs_pos].
now rewrite <-opp_0, <-Hab, mul_opp_r, <-opp_add_distr, <-div_mod.
Qed.
Lemma mod_opp_l_nz : forall a b, b~=0 -> a mod b ~= 0 ->
(-a) mod b == abs b - (a mod b).
Proof.
intros a b Hb Hab. symmetry.
apply mod_unique with (-(a/b)-sgn b).
rewrite lt_sub_lt_add_l.
rewrite <- le_add_le_sub_l. nzsimpl.
rewrite <- (add_0_l (abs b)) at 2.
rewrite <- add_lt_mono_r.
destruct (mod_always_pos a b); intuition order.
rewrite <- 2 add_opp_r, mul_add_distr_l, 2 mul_opp_r.
rewrite sgn_abs.
rewrite add_shuffle2, add_opp_diag_l; nzsimpl.
rewrite <-opp_add_distr, <-div_mod; order.
Qed.
Lemma div_opp_opp_z : forall a b, b~=0 -> a mod b == 0 ->
(-a)/(-b) == a/b.
Proof.
intros. now rewrite div_opp_r, div_opp_l_z, opp_involutive.
Qed.
Lemma div_opp_opp_nz : forall a b, b~=0 -> a mod b ~= 0 ->
(-a)/(-b) == a/b + sgn(b).
Proof.
intros. rewrite div_opp_r, div_opp_l_nz by trivial.
now rewrite opp_sub_distr, opp_involutive.
Qed.
Lemma mod_opp_opp_z : forall a b, b~=0 -> a mod b == 0 ->
(-a) mod (-b) == 0.
Proof.
intros. now rewrite mod_opp_r, mod_opp_l_z.
Qed.
Lemma mod_opp_opp_nz : forall a b, b~=0 -> a mod b ~= 0 ->
(-a) mod (-b) == abs b - a mod b.
Proof.
intros. now rewrite mod_opp_r, mod_opp_l_nz.
Qed.
(** A division by itself returns 1 *)
Lemma div_same : forall a, a~=0 -> a/a == 1.
Proof.
intros. symmetry. apply div_unique with 0.
split; [order|now rewrite abs_pos].
now nzsimpl.
Qed.
Lemma mod_same : forall a, a~=0 -> a mod a == 0.
Proof.
intros.
rewrite mod_eq, div_same by trivial. nzsimpl. apply sub_diag.
Qed.
(** A division of a small number by a bigger one yields zero. *)
Theorem div_small: forall a b, 0<=a<b -> a/b == 0.
Proof. exact div_small. Qed.
(** Same situation, in term of modulo: *)
Theorem mod_small: forall a b, 0<=a<b -> a mod b == a.
Proof. exact mod_small. Qed.
(** * Basic values of divisions and modulo. *)
Lemma div_0_l: forall a, a~=0 -> 0/a == 0.
Proof.
intros. pos_or_neg a. apply div_0_l; order.
apply opp_inj. rewrite <- div_opp_r, opp_0 by trivial. now apply div_0_l.
Qed.
Lemma mod_0_l: forall a, a~=0 -> 0 mod a == 0.
Proof.
intros; rewrite mod_eq, div_0_l; now nzsimpl.
Qed.
Lemma div_1_r: forall a, a/1 == a.
Proof.
intros. symmetry. apply div_unique with 0.
assert (H:=lt_0_1); rewrite abs_pos; intuition; order.
now nzsimpl.
Qed.
Lemma mod_1_r: forall a, a mod 1 == 0.
Proof.
intros. rewrite mod_eq, div_1_r; nzsimpl; auto using sub_diag.
apply neq_sym, lt_neq; apply lt_0_1.
Qed.
Lemma div_1_l: forall a, 1<a -> 1/a == 0.
Proof. exact div_1_l. Qed.
Lemma mod_1_l: forall a, 1<a -> 1 mod a == 1.
Proof. exact mod_1_l. Qed.
Lemma div_mul : forall a b, b~=0 -> (a*b)/b == a.
Proof.
intros. symmetry. apply div_unique with 0.
split; [order|now rewrite abs_pos].
nzsimpl; apply mul_comm.
Qed.
Lemma mod_mul : forall a b, b~=0 -> (a*b) mod b == 0.
Proof.
intros. rewrite mod_eq, div_mul by trivial. rewrite mul_comm; apply sub_diag.
Qed.
Theorem div_unique_exact a b q: b~=0 -> a == b*q -> q == a/b.
Proof.
intros Hb H. rewrite H, mul_comm. symmetry. now apply div_mul.
Qed.
(** * Order results about mod and div *)
(** A modulo cannot grow beyond its starting point. *)
Theorem mod_le: forall a b, 0<=a -> b~=0 -> a mod b <= a.
Proof.
intros. pos_or_neg b. apply mod_le; order.
rewrite <- mod_opp_r by trivial. apply mod_le; order.
Qed.
Theorem div_pos : forall a b, 0<=a -> 0<b -> 0<= a/b.
Proof. exact div_pos. Qed.
Lemma div_str_pos : forall a b, 0<b<=a -> 0 < a/b.
Proof. exact div_str_pos. Qed.
Lemma div_small_iff : forall a b, b~=0 -> (a/b==0 <-> 0<=a<abs b).
Proof.
intros a b Hb.
split.
intros EQ.
rewrite (div_mod a b Hb), EQ; nzsimpl.
now apply mod_always_pos.
intros. pos_or_neg b.
apply div_small.
now rewrite <- (abs_eq b).
apply opp_inj; rewrite opp_0, <- div_opp_r by trivial.
apply div_small.
rewrite <- (abs_neq' b) by order. trivial.
Qed.
Lemma mod_small_iff : forall a b, b~=0 -> (a mod b == a <-> 0<=a<abs b).
Proof.
intros.
rewrite <- div_small_iff, mod_eq by trivial.
rewrite sub_move_r, <- (add_0_r a) at 1. rewrite add_cancel_l.
rewrite eq_sym_iff, eq_mul_0. tauto.
Qed.
(** As soon as the divisor is strictly greater than 1,
the division is strictly decreasing. *)
Lemma div_lt : forall a b, 0<a -> 1<b -> a/b < a.
Proof. exact div_lt. Qed.
(** [le] is compatible with a positive division. *)
Lemma div_le_mono : forall a b c, 0<c -> a<=b -> a/c <= b/c.
Proof.
intros a b c Hc Hab.
rewrite lt_eq_cases in Hab. destruct Hab as [LT|EQ];
[|rewrite EQ; order].
rewrite <- lt_succ_r.
rewrite (mul_lt_mono_pos_l c) by order.
nzsimpl.
rewrite (add_lt_mono_r _ _ (a mod c)).
rewrite <- div_mod by order.
apply lt_le_trans with b; trivial.
rewrite (div_mod b c) at 1 by order.
rewrite <- add_assoc, <- add_le_mono_l.
apply le_trans with (c+0).
nzsimpl; destruct (mod_always_pos b c); try order.
rewrite abs_eq in *; order.
rewrite <- add_le_mono_l. destruct (mod_always_pos a c); order.
Qed.
(** In this convention, [div] performs Rounding-Toward-Bottom
when divisor is positive, and Rounding-Toward-Top otherwise.
Since we cannot speak of rational values here, we express this
fact by multiplying back by [b], and this leads to a nice
unique statement.
*)
Lemma mul_div_le : forall a b, b~=0 -> b*(a/b) <= a.
Proof.
intros.
rewrite (div_mod a b) at 2; trivial.
rewrite <- (add_0_r (b*(a/b))) at 1.
rewrite <- add_le_mono_l.
now destruct (mod_always_pos a b).
Qed.
(** Giving a reversed bound is slightly more complex *)
Lemma mul_succ_div_gt: forall a b, 0<b -> a < b*(S (a/b)).
Proof.
intros.
nzsimpl.
rewrite (div_mod a b) at 1; try order.
rewrite <- add_lt_mono_l.
destruct (mod_always_pos a b). order.
rewrite abs_eq in *; order.
Qed.
Lemma mul_pred_div_gt: forall a b, b<0 -> a < b*(P (a/b)).
Proof.
intros a b Hb.
rewrite mul_pred_r, <- add_opp_r.
rewrite (div_mod a b) at 1; try order.
rewrite <- add_lt_mono_l.
destruct (mod_always_pos a b). order.
rewrite <- opp_pos_neg in Hb. rewrite abs_neq' in *; order.
Qed.
(** NB: The three previous properties could be used as
specifications for [div]. *)
(** Inequality [mul_div_le] is exact iff the modulo is zero. *)
Lemma div_exact : forall a b, b~=0 -> (a == b*(a/b) <-> a mod b == 0).
Proof.
intros.
rewrite (div_mod a b) at 1; try order.
rewrite <- (add_0_r (b*(a/b))) at 2.
apply add_cancel_l.
Qed.
(** Some additionnal inequalities about div. *)
Theorem div_lt_upper_bound:
forall a b q, 0<b -> a < b*q -> a/b < q.
Proof.
intros.
rewrite (mul_lt_mono_pos_l b) by trivial.
apply le_lt_trans with a; trivial.
apply mul_div_le; order.
Qed.
Theorem div_le_upper_bound:
forall a b q, 0<b -> a <= b*q -> a/b <= q.
Proof.
intros.
rewrite <- (div_mul q b) by order.
apply div_le_mono; trivial. now rewrite mul_comm.
Qed.
Theorem div_le_lower_bound:
forall a b q, 0<b -> b*q <= a -> q <= a/b.
Proof.
intros.
rewrite <- (div_mul q b) by order.
apply div_le_mono; trivial. now rewrite mul_comm.
Qed.
(** A division respects opposite monotonicity for the divisor *)
Lemma div_le_compat_l: forall p q r, 0<=p -> 0<q<=r -> p/r <= p/q.
Proof. exact div_le_compat_l. Qed.
(** * Relations between usual operations and mod and div *)
Lemma mod_add : forall a b c, c~=0 ->
(a + b * c) mod c == a mod c.
Proof.
intros.
symmetry.
apply mod_unique with (a/c+b); trivial.
now apply mod_always_pos.
rewrite mul_add_distr_l, add_shuffle0, <- div_mod by order.
now rewrite mul_comm.
Qed.
Lemma div_add : forall a b c, c~=0 ->
(a + b * c) / c == a / c + b.
Proof.
intros.
apply (mul_cancel_l _ _ c); try order.
apply (add_cancel_r _ _ ((a+b*c) mod c)).
rewrite <- div_mod, mod_add by order.
rewrite mul_add_distr_l, add_shuffle0, <- div_mod by order.
now rewrite mul_comm.
Qed.
Lemma div_add_l: forall a b c, b~=0 ->
(a * b + c) / b == a + c / b.
Proof.
intros a b c. rewrite (add_comm _ c), (add_comm a).
now apply div_add.
Qed.
(** Cancellations. *)
(** With the current convention, the following isn't always true
when [c<0]: [-3*-1 / -2*-1 = 3/2 = 1] while [-3/-2 = 2] *)
Lemma div_mul_cancel_r : forall a b c, b~=0 -> 0<c ->
(a*c)/(b*c) == a/b.
Proof.
intros.
symmetry.
apply div_unique with ((a mod b)*c).
(* ineqs *)
rewrite abs_mul, (abs_eq c) by order.
rewrite <-(mul_0_l c), <-mul_lt_mono_pos_r, <-mul_le_mono_pos_r by trivial.
now apply mod_always_pos.
(* equation *)
rewrite (div_mod a b) at 1 by order.
rewrite mul_add_distr_r.
rewrite add_cancel_r.
rewrite <- 2 mul_assoc. now rewrite (mul_comm c).
Qed.
Lemma div_mul_cancel_l : forall a b c, b~=0 -> 0<c ->
(c*a)/(c*b) == a/b.
Proof.
intros. rewrite !(mul_comm c); now apply div_mul_cancel_r.
Qed.
Lemma mul_mod_distr_l: forall a b c, b~=0 -> 0<c ->
(c*a) mod (c*b) == c * (a mod b).
Proof.
intros.
rewrite <- (add_cancel_l _ _ ((c*b)* ((c*a)/(c*b)))).
rewrite <- div_mod.
rewrite div_mul_cancel_l by trivial.
rewrite <- mul_assoc, <- mul_add_distr_l, mul_cancel_l by order.
apply div_mod; order.
rewrite <- neq_mul_0; intuition; order.
Qed.
Lemma mul_mod_distr_r: forall a b c, b~=0 -> 0<c ->
(a*c) mod (b*c) == (a mod b) * c.
Proof.
intros. rewrite !(mul_comm _ c); now rewrite mul_mod_distr_l.
Qed.
(** Operations modulo. *)
Theorem mod_mod: forall a n, n~=0 ->
(a mod n) mod n == a mod n.
Proof.
intros. rewrite mod_small_iff by trivial.
now apply mod_always_pos.
Qed.
Lemma mul_mod_idemp_l : forall a b n, n~=0 ->
((a mod n)*b) mod n == (a*b) mod n.
Proof.
intros a b n Hn. symmetry.
rewrite (div_mod a n) at 1 by order.
rewrite add_comm, (mul_comm n), (mul_comm _ b).
rewrite mul_add_distr_l, mul_assoc.
rewrite mod_add by trivial.
now rewrite mul_comm.
Qed.
Lemma mul_mod_idemp_r : forall a b n, n~=0 ->
(a*(b mod n)) mod n == (a*b) mod n.
Proof.
intros. rewrite !(mul_comm a). now apply mul_mod_idemp_l.
Qed.
Theorem mul_mod: forall a b n, n~=0 ->
(a * b) mod n == ((a mod n) * (b mod n)) mod n.
Proof.
intros. now rewrite mul_mod_idemp_l, mul_mod_idemp_r.
Qed.
Lemma add_mod_idemp_l : forall a b n, n~=0 ->
((a mod n)+b) mod n == (a+b) mod n.
Proof.
intros a b n Hn. symmetry.
rewrite (div_mod a n) at 1 by order.
rewrite <- add_assoc, add_comm, mul_comm.
now rewrite mod_add.
Qed.
Lemma add_mod_idemp_r : forall a b n, n~=0 ->
(a+(b mod n)) mod n == (a+b) mod n.
Proof.
intros. rewrite !(add_comm a). now apply add_mod_idemp_l.
Qed.
Theorem add_mod: forall a b n, n~=0 ->
(a+b) mod n == (a mod n + b mod n) mod n.
Proof.
intros. now rewrite add_mod_idemp_l, add_mod_idemp_r.
Qed.
(** With the current convention, the following result isn't always
true with a negative intermediate divisor. For instance
[ 3/(-2)/(-2) = 1 <> 0 = 3 / (-2*-2) ] and
[ 3/(-2)/2 = -1 <> 0 = 3 / (-2*2) ]. *)
Lemma div_div : forall a b c, 0<b -> c~=0 ->
(a/b)/c == a/(b*c).
Proof.
intros a b c Hb Hc.
apply div_unique with (b*((a/b) mod c) + a mod b).
(* begin 0<= ... <abs(b*c) *)
rewrite abs_mul.
destruct (mod_always_pos (a/b) c), (mod_always_pos a b); try order.
split.
apply add_nonneg_nonneg; trivial.
apply mul_nonneg_nonneg; order.
apply lt_le_trans with (b*((a/b) mod c) + abs b).
now rewrite <- add_lt_mono_l.
rewrite (abs_eq b) by order.
now rewrite <- mul_succ_r, <- mul_le_mono_pos_l, le_succ_l.
(* end 0<= ... < abs(b*c) *)
rewrite (div_mod a b) at 1 by order.
rewrite add_assoc, add_cancel_r.
rewrite <- mul_assoc, <- mul_add_distr_l, mul_cancel_l by order.
apply div_mod; order.
Qed.
(** Similarly, the following result doesn't always hold when [b<0].
For instance [3 mod (-2*-2)) = 3] while
[3 mod (-2) + (-2)*((3/-2) mod -2) = -1]. *)
Lemma mod_mul_r : forall a b c, 0<b -> c~=0 ->
a mod (b*c) == a mod b + b*((a/b) mod c).
Proof.
intros a b c Hb Hc.
apply add_cancel_l with (b*c*(a/(b*c))).
rewrite <- div_mod by (apply neq_mul_0; split; order).
rewrite <- div_div by trivial.
rewrite add_assoc, add_shuffle0, <- mul_assoc, <- mul_add_distr_l.
rewrite <- div_mod by order.
apply div_mod; order.
Qed.
(** A last inequality: *)
Theorem div_mul_le:
forall a b c, 0<=a -> 0<b -> 0<=c -> c*(a/b) <= (c*a)/b.
Proof. exact div_mul_le. Qed.
(** mod is related to divisibility *)
Lemma mod_divides : forall a b, b~=0 ->
(a mod b == 0 <-> (b|a)).
Proof.
intros a b Hb. split.
intros Hab. exists (a/b). rewrite mul_comm.
rewrite (div_mod a b Hb) at 1. rewrite Hab; now nzsimpl.
intros (c,Hc). rewrite Hc. now apply mod_mul.
Qed.
End ZEuclidProp.
|
`timescale 1ns / 1ps
// Copyright (C) 2008 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
module mux(opA,opB,sum,dsp_sel,out);
input [3:0] opA,opB;
input [4:0] sum;
input [1:0] dsp_sel;
output [3:0] out;
reg cout;
always @ (sum)
begin
if (sum[4] == 1)
cout <= 4'b0001;
else
cout <= 4'b0000;
end
reg out;
always @(dsp_sel,sum,cout,opB,opA)
begin
if (dsp_sel == 2'b00)
out <= sum[3:0];
else if (dsp_sel == 2'b01)
out <= cout;
else if (dsp_sel == 2'b10)
out <= opB;
else if (dsp_sel == 2'b11)
out <= opA;
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: ctu_lib.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
//
// Cluster Name: CTU
//
//-----------------------------------------------------------------------------
`include "sys.h"
//---------------------------
//
// Lauching clock: raw_clk_out
// Receiving clock : jbus_clk
// Method: Latch for hold time
//
//---------------------------
module ctu_synch_ref_jl(/*AUTOARG*/
// Outputs
syncdata,
// Inputs
pll_raw_clk_out, presyncdata
);
// synopsys template
parameter SIZE = 1;
input pll_raw_clk_out;
input [SIZE-1:0] presyncdata;
output [SIZE-1:0] syncdata;
wire [SIZE-1:0] presyncdata_in;
bw_u1_scanl_2x u_ctu_synch_ref_jl_0 [SIZE-1:0]
(.sd (presyncdata[SIZE-1:0]),
.ck (pll_raw_clk_out),
.so (syncdata[SIZE-1:0])
);
endmodule
//---------------------------
//
// Lauching clock: jbus_clk
// Receiving clock : raw_clk_out
// Method: Latch for hold time
//
//---------------------------
module ctu_synch_jl_ref(/*AUTOARG*/
// Outputs
syncdata,
// Inputs
jbus_clk, presyncdata
);
// synopsys template
parameter SIZE = 1;
input jbus_clk;
input [SIZE-1:0] presyncdata;
output [SIZE-1:0] syncdata;
wire [SIZE-1:0] presyncdata_in;
bw_u1_scanl_2x u_ctu_synch_jl_ref_0 [SIZE-1:0]
(.sd (presyncdata[SIZE-1:0]),
.ck (jbus_clk),
.so (syncdata[SIZE-1:0])
);
endmodule
//---------------------------
//
// Lauching clock: cmp_clk
// Receiving clock : cmp_gclk
//
//---------------------------
// Before re-time with gclk,
// the data needs to be register with local clock
// to garuantee setup
// Since the timing is very tight (200 ps setup skew)
// We move the testmode mux to cmp_clk domain
// before sending it to cmp_gclk
// All clock enable signals
module ctu_synch_cl_cg (/*AUTOARG*/
// Outputs
syncdata,
// Inputs
cmp_clk, start_clk_cl, arst_l, force_cken, presyncdata
);
// synopsys template
parameter SIZE = 1;
input cmp_clk;
input start_clk_cl;
input arst_l;
input force_cken;
input [SIZE-1:0] presyncdata;
output [SIZE-1:0] syncdata;
wire [SIZE-1:0] presyncdata_muxed;
assign presyncdata_muxed = force_cken? { SIZE {1'b1}} : {SIZE {start_clk_cl}} & presyncdata;
dffrl_async_ns #(SIZE) u_synch_jl_cl_ff1_nsr(
.din (presyncdata_muxed[SIZE-1:0]),
.clk (cmp_clk),
.rst_l(arst_l),
.q (syncdata[SIZE-1:0]));
endmodule
//---------------------------
//
// Lauching clock: cmp_clk
// Receiving clock : dram_gclk
// Method: sync pulse (one clock earlier than dram_tx_sync)
// data available on rising edge of dram_clk
// then clocked by dram_gclk on next edge
//
//---------------------------
module ctu_synch_cl_dl(/*AUTOARG*/
// Outputs
syncdata,
// Inputs
cmp_clk, ctu_dram_tx_sync_early, presyncdata
);
// synopsys template
parameter SIZE = 1;
input cmp_clk;
input ctu_dram_tx_sync_early;
input [SIZE-1:0] presyncdata;
output [SIZE-1:0] syncdata;
dffe_ns #(SIZE) u_synch_cl_dl_ff0(
.din (presyncdata[SIZE-1:0]),
.clk (cmp_clk),
.en(ctu_dram_tx_sync_early),
.q (syncdata[SIZE-1:0]));
endmodule
//---------------------------
//
// Lauching clock: jbus_clk
// Receiving clock : pseudo dram_clk (make use of coincident edge)
// Method: jbus_clk -> cmp_clk through coin edges
//
//---------------------------
module ctu_synch_jl_dl (/*AUTOARG*/
// Outputs
syncdata,
// Inputs
cmp_clk, jbus_rx_sync, coin_edge, arst_l, presyncdata
);
// synopsys template
parameter SIZE = 1;
input cmp_clk;
input jbus_rx_sync;
input coin_edge;
input arst_l;
input [SIZE-1:0] presyncdata;
output [SIZE-1:0] syncdata;
wire [SIZE-1:0] presyncdata_in;
wire [SIZE-1:0] presyncdata_in_nxt;
wire [SIZE-1:0] syncdata_nxt;
assign presyncdata_in_nxt = jbus_rx_sync ? presyncdata: presyncdata_in;
dffrl_async_ns #(SIZE) u_synch_cl_dl_ff0(
.din (presyncdata_in_nxt[SIZE-1:0]),
.clk (cmp_clk),
.rst_l(arst_l),
.q (presyncdata_in[SIZE-1:0]));
assign syncdata_nxt = coin_edge ? presyncdata_in : syncdata;
dffrl_async_ns #(SIZE) u_synch_cl_dl_ff2(
.din (syncdata_nxt[SIZE-1:0]),
.clk (cmp_clk),
.rst_l(arst_l),
.q (syncdata[SIZE-1:0]));
endmodule
//---------------------------
//
// Asynchronous interface
//
//---------------------------
module ctu_synchronizer (/*AUTOARG*/
// Outputs
syncdata,
// Inputs
clk, presyncdata
);
// synopsys template
parameter SIZE = 1;
input clk;
input [SIZE-1:0] presyncdata;
output [SIZE-1:0] syncdata;
wire [SIZE-1:0] presyncdata_tmp;
bw_u1_syncff_4x u_synchronizer_syncff [SIZE-1:0](.q(presyncdata_tmp),
.so(),
.ck(clk),
.d(presyncdata),
.sd(),
.se(1'b0)
);
bw_u1_soff_2x u_synchronizer_ff[SIZE-1:0] (.q(syncdata),
.so(),
.ck(clk),
.d(presyncdata_tmp),
.sd(),
.se(1'b0)
);
endmodule
//---------------------------
//
// Asynchronous interface (clock select blocks)
//
//---------------------------
module ctu_clksel_async_synchronizer (/*AUTOARG*/
// Outputs
syncdata,
// Inputs
clk, presyncdata, arst_l, aset_l
);
// synopsys template
parameter SIZE = 1;
input clk;
input [SIZE-1:0] presyncdata;
input arst_l;
input aset_l;
output [SIZE-1:0] syncdata;
wire [SIZE-1:0] presyncdata_in0;
wire [SIZE-1:0] presyncdata_in1;
bw_u1_soffasr_2x u_synchronizer_ff0_nsr[SIZE-1:0] (.q( presyncdata_in0),
.so(),
.ck(clk),
.d(presyncdata),
.sd(),
.se(1'b0),
.r_l (arst_l),
.s_l (aset_l)
);
bw_u1_soffasr_2x u_synchronizer_ff1_nsr[SIZE-1:0] (.q( presyncdata_in1),
.so(),
.ck(clk),
.d(presyncdata_in0),
.sd(),
.se(1'b0),
.r_l (arst_l),
.s_l (aset_l)
);
bw_u1_soffasr_2x u_synchronizer_neg_ff_nsr[SIZE-1:0] (.q( syncdata[SIZE-1:0]),
.so(),
.ck(~clk),
.d(presyncdata_in1[SIZE-1:0]),
.sd(),
.se(1'b0),
.r_l (arst_l),
.s_l (aset_l)
);
endmodule
module ctu_mux21 (d0, d1, s, z);
// synopsys template
parameter SIZE = 1;
input [SIZE-1:0] d0 ; // data in
input [SIZE-1:0] d1 ; // data in
input s; // select
output [SIZE-1:0] z ;
wire [SIZE-1:0] z_pre ;
// assign z = s ? d1 : d0;
bw_u1_muxi21_4x u_muxi21 [SIZE-1:0] (
.z(z_pre), .d0(d0), .d1(d1), .s(s) );
bw_u1_inv_5x u_inv [SIZE-1:0] (
.z(z), .a(z_pre));
endmodule
//---------------------------
//
// clock select components used in jtag
//
//---------------------------
module ctu_jtag_clk_sel_0_0_ff (/*AUTOARG*/
// Outputs
sel_clk,
// Inputs
test_mode_pin, trst, pll_bypass_pin, sel_ff
);
input test_mode_pin;
input trst;
input pll_bypass_pin;
input sel_ff;
output sel_clk;
wire tmp0, tmp1;
bw_u1_oai21_4x u_oai21 (.z(tmp0), .a(test_mode_pin), .b1(trst), .b2(pll_bypass_pin));
bw_u1_nand2_4x u_nand2 (.z(tmp1), .a(tmp0), .b(sel_ff));
bw_u1_inv_8x u_inv (.z(sel_clk), .a(tmp1) );
endmodule
module ctu_jtag_clk_sel_1_0_ff (/*AUTOARG*/
// Outputs
sel_clk,
// Inputs
test_mode_pin, trst, pll_bypass_pin, sel_ff
);
input test_mode_pin;
input trst;
input pll_bypass_pin;
input sel_ff;
output sel_clk;
wire tmp0, tmp1;
bw_u1_nand2_4x u_nand2 (.z(tmp0), .a(test_mode_pin), .b(pll_bypass_pin));
bw_u1_aoi22_4x u_aoi22 (.z(tmp1), .a1(test_mode_pin), .a2(trst), .b1(tmp0), .b2(sel_ff));
bw_u1_inv_8x u_inv (.z(sel_clk), .a(tmp1));
endmodule
module ctu_jtag_clk_sel_0_1_ff (/*AUTOARG*/
// Outputs
sel_clk,
// Inputs
test_mode_pin, trst, pll_bypass_pin, sel_ff
);
input test_mode_pin;
input trst;
input pll_bypass_pin;
input sel_ff;
output sel_clk;
wire tmp;
bw_u1_aoi21_4x u_aoi21_0 (.z(tmp), .a(sel_ff), .b1(test_mode_pin), .b2(pll_bypass_pin));
bw_u1_aoi21_4x u_aoi21_1 (.z(sel_clk), .a(tmp), .b1(test_mode_pin), .b2(trst));
endmodule
//---------------------------
//
// gated clock components
//
//---------------------------
module ctu_and2 (z, a, b);
output z;
input a;
input b;
bw_u1_nand2_4x u_nand2 ( .z(tmp), .a(a), .b(b) );
bw_u1_inv_8x u_inv ( .z(z), .a(tmp) );
endmodule
module ctu_and3 (z, a, b,c);
output z;
input a;
input b;
input c;
bw_u1_nand3_4x u_nand2 ( .z(tmp), .a(a), .b(b), .c(c) );
bw_u1_inv_8x u_inv ( .z(z), .a(tmp) );
endmodule
module ctu_inv (z, a);
output z;
input a;
bw_u1_inv_8x u_inv ( .z(z), .a(a) );
endmodule
module ctu_or2 (z, a, b);
output z;
input a;
input b;
bw_u1_nor2_4x u_nor2 ( .z(tmp), .a(a), .b(b) );
bw_u1_inv_8x u_inv ( .z(z), .a(tmp) );
endmodule
module ctu_nor2 (z, a, b);
output z;
input a;
input b;
bw_u1_nor2_4x u_nor2 ( .z(z), .a(a), .b(b) );
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2019 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
`define checkg(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%g' exp='%g'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
integer i;
typedef integer q_t[$];
initial begin
q_t iq;
iq.push_back(42);
end
always @ (posedge clk) begin
cyc <= cyc + 1;
begin
// Very simple test using bit
bit q[$];
bit x;
`checkh($left(q), 0);
`checkh($right(q), -1);
`checkh($increment(q), -1);
`checkh($low(q), 0);
`checkh($high(q), -1);
`checkh($size(q), 0);
`checkh($dimensions(q), 1);
// $bits is unsupported in several other simulators, see bug1646
// Unsup: `checkh($bits(q), 0);
q.push_back(1'b1);
`checkh($left(q), 0);
`checkh($right(q), 0);
`checkh($increment(q), -1);
`checkh($low(q), 0);
`checkh($high(q), 0);
`checkh($size(q), 1);
`checkh($dimensions(q), 1);
// Unsup: `checkh($bits(q), 2);
`checkh(q.size(), 1);
q.push_back(1'b1);
q.push_back(1'b0);
q.push_back(1'b1);
`checkh($left(q), 0);
`checkh($right(q), 3);
`checkh($low(q), 0);
`checkh($high(q), 3);
`checkh($size(q), 4);
// Unsup: `checkh($bits(q), 4);
`checkh(q.size(), 4);
x = q.pop_back(); `checkh(x, 1'b1);
`checkh($left(q), 0);
`checkh($right(q), 2);
`checkh($low(q), 0);
`checkh($high(q), 2);
`checkh($size(q), 3);
// sure those are working now..
x = q.pop_front(); `checkh(x, 1'b1);
x = q.pop_front(); `checkh(x, 1'b1);
x = q.pop_front(); `checkh(x, 1'b0);
`checkh(q.size(), 0);
end
begin
// Simple test using integer
typedef bit [3:0] nibble_t;
nibble_t q[$];
nibble_t v;
`checkh($left(q), 0);
`checkh($right(q), -1);
`checkh($increment(q), -1);
`checkh($low(q), 0);
`checkh($high(q), -1);
`checkh($size(q), 0);
`checkh($dimensions(q), 2);
i = q.size(); `checkh(i, 0);
q.push_back(4'd1); // 1
q.push_front(4'd2); // 2 1
q.push_back(4'd3); // 2 1 3
i = q.size; `checkh(i, 3); // Also checks no parens
end
begin
// Strings
string q[$];
string v;
int j = 0;
// Empty queue checks
`checkh($left(q), 0);
`checkh($right(q), -1);
`checkh($increment(q), -1);
`checkh($low(q), 0);
`checkh($high(q), -1);
`checkh($size(q), 0);
`checkh($dimensions(q), 2);
//Unsup: `checkh($bits(q), 0);
q.push_front("f1");
//Unsup: `checkh($bits(q), 16);
q.push_back("b1");
q.push_front("f2");
q.push_back("b2");
i = q.size(); `checkh(i, 4);
v = q[0]; `checks(v, "f2");
v = q[1]; `checks(v, "f1");
v = q[2]; `checks(v, "b1");
v = q[3]; `checks(v, "b2");
v = q[4]; `checks(v, "");
//Unsup: `checkh(q[$], "b2");
v = $sformatf("%p", q); `checks(v, "'{\"f2\", \"f1\", \"b1\", \"b2\"} ");
//Unsup: q.delete(1);
//Unsup: v = q[1]; `checks(v, "b1");
//Unsup: q.insert(0, "ins0");
//Unsup: q.insert(3, "ins3");
//v = q[0]; `checks(v, "ins0");
//v = q[3]; `checks(v, "ins3");
foreach (q[i]) begin
j++;
v = q[i];
if (i == 0) `checks(v, "f2");
if (i == 1) `checks(v, "f1");
if (i == 2) `checks(v, "b1");
if (i == 3) `checks(v, "b2");
end
`checkh(j,4);
q.pop_front();
v = q.pop_front(); `checks(v, "f1");
v = q.pop_back(); `checks(v, "b2");
v = q.pop_back(); `checks(v, "b1");
i = q.size(); `checkh(i, 0);
// Empty queue, this should be 0
foreach (q[i]) begin
j++;
end
`checkh(j,4);
q.push_front("non-empty");
i = q.size(); `checkh(i, 1);
q.delete();
i = q.size(); `checkh(i, 0);
v = q.pop_front(); `checks(v, ""); // Was empty, optional warning
v = q.pop_back(); `checks(v, ""); // Was empty, optional warning
// Conversion of insert/delete with zero to operator
q.push_front("front");
q.insert(0, "newfront");
i = q.size(); `checkh(i, 2);
q.delete(0);
i = q.size(); `checkh(i, 1);
`checks(q[0], "front");
//Unsup: `checks(q[$], "front");
end
begin
typedef struct packed {
bit [7:0] opcode;
bit [23:0] addr;
} instruction; // named structure type
instruction q[$];
`checkh($dimensions(q), 2);
//Unsup: `checkh($bits(q), 0);
end
// testing a wide queue
begin
typedef struct packed {
bit [7:0] opcode;
bit [23:0] addr;
bit [127:0] data;
} instructionW; // named structure type
instructionW inst_push;
instructionW inst_pop;
instructionW q[$];
`checkh($dimensions(q), 2);
`checkh(q[0].opcode, 0);
`checkh(q[0].addr, 0);
`checkh(q[0].data, 0);
inst_push.opcode = 1;
inst_push.addr = 42;
inst_push.data = {4{32'hdeadbeef}};
q.push_back(inst_push);
`checkh(q[0].opcode, 1);
`checkh(q[0].addr, 42);
`checkh(q[0].data, {4{32'hdeadbeef}});
inst_pop = q.pop_front();
`checkh(inst_pop.opcode, 1);
`checkh(inst_pop.addr, 42);
`checkh(inst_pop.data, {4{32'hdeadbeef}});
`checkh(q.size(), 0);
`checkh(q[0].opcode, 0);
`checkh(q[0].addr, 0);
`checkh(q[0].data, 0);
end
/* Unsup:
begin
int q[4][$];
q[0].push_back(0);
q[0].push_back(1);
q[1].push_back(2);
q[2].push_back(3);
end
*/
// See t_queue_unsup_bad for more unsupported stuff
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2005,2006 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
`include "../../firmware/include/fpga_regs_common.v"
`include "../../firmware/include/fpga_regs_standard.v"
module io_pins
( inout wire [15:0] io_0, inout wire [15:0] io_1,
input wire [15:0] reg_0, input wire [15:0] reg_1,
input clock, input rx_reset, input tx_reset,
input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe);
reg [15:0] io_0_oe,io_1_oe;
bidir_reg bidir_reg_0 (.tristate(io_0),.oe(io_0_oe),.reg_val(reg_0));
bidir_reg bidir_reg_1 (.tristate(io_1),.oe(io_1_oe),.reg_val(reg_1));
// Upper 16 bits are mask for lower 16
always @(posedge clock)
if(serial_strobe)
case(serial_addr)
`FR_OE_0 : io_0_oe
<= #1 (io_0_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
`FR_OE_1 : io_1_oe
<= #1 (io_1_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
endcase // case(serial_addr)
endmodule // io_pins
|
//-----------------------------------------------------
// Design Name : pri_encoder_using_assign
// File Name : pri_encoder_using_assign.v
// Function : Pri Encoder using assign
// Coder : Deepak Kumar Tala
//-----------------------------------------------------
module pri_encoder_using_assign (
binary_out , // 4 bit binary output
encoder_in , // 16-bit input
enable // Enable for the encoder
);
output [3:0] binary_out ;
input enable ;
input [15:0] encoder_in ;
wire [3:0] binary_out ;
assign binary_out = (!enable) ? 0 : (
(encoder_in == 16'bxxxx_xxxx_xxxx_xxx1) ? 0 :
(encoder_in == 16'bxxxx_xxxx_xxxx_xx10) ? 1 :
(encoder_in == 16'bxxxx_xxxx_xxxx_x100) ? 2 :
(encoder_in == 16'bxxxx_xxxx_xxxx_1000) ? 3 :
(encoder_in == 16'bxxxx_xxxx_xxx1_0000) ? 4 :
(encoder_in == 16'bxxxx_xxxx_xx10_0000) ? 5 :
(encoder_in == 16'bxxxx_xxxx_x100_0000) ? 6 :
(encoder_in == 16'bxxxx_xxxx_1000_0000) ? 7 :
(encoder_in == 16'bxxxx_xxx1_0000_0000) ? 8 :
(encoder_in == 16'bxxxx_xx10_0000_0000) ? 9 :
(encoder_in == 16'bxxxx_x100_0000_0000) ? 10 :
(encoder_in == 16'bxxxx_1000_0000_0000) ? 11 :
(encoder_in == 16'bxxx1_0000_0000_0000) ? 12 :
(encoder_in == 16'bxx10_0000_0000_0000) ? 13 :
(encoder_in == 16'bx100_0000_0000_0000) ? 14 : 15);
endmodule
|
/*
* Copyright 2012, Homer Hsing <[email protected]>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* one AES round for every two clock cycles */
module one_round (clk, state_in, key, state_out);
input clk;
input [127:0] state_in, key;
output reg [127:0] state_out;
wire [31:0] s0, s1, s2, s3,
z0, z1, z2, z3,
p00, p01, p02, p03,
p10, p11, p12, p13,
p20, p21, p22, p23,
p30, p31, p32, p33,
k0, k1, k2, k3;
assign {k0, k1, k2, k3} = key;
assign {s0, s1, s2, s3} = state_in;
table_lookup
t0 (clk, s0, p00, p01, p02, p03),
t1 (clk, s1, p10, p11, p12, p13),
t2 (clk, s2, p20, p21, p22, p23),
t3 (clk, s3, p30, p31, p32, p33);
assign z0 = p00 ^ p11 ^ p22 ^ p33 ^ k0;
assign z1 = p03 ^ p10 ^ p21 ^ p32 ^ k1;
assign z2 = p02 ^ p13 ^ p20 ^ p31 ^ k2;
assign z3 = p01 ^ p12 ^ p23 ^ p30 ^ k3;
always @ (posedge clk)
state_out <= {z0, z1, z2, z3};
endmodule
/* AES final round for every two clock cycles */
module final_round (clk, state_in, key_in, state_out);
input clk;
input [127:0] state_in;
input [127:0] key_in;
output reg [127:0] state_out;
wire [31:0] s0, s1, s2, s3,
z0, z1, z2, z3,
k0, k1, k2, k3;
wire [7:0] p00, p01, p02, p03,
p10, p11, p12, p13,
p20, p21, p22, p23,
p30, p31, p32, p33;
assign {k0, k1, k2, k3} = key_in;
assign {s0, s1, s2, s3} = state_in;
S4
S4_1 (clk, s0, {p00, p01, p02, p03}),
S4_2 (clk, s1, {p10, p11, p12, p13}),
S4_3 (clk, s2, {p20, p21, p22, p23}),
S4_4 (clk, s3, {p30, p31, p32, p33});
assign z0 = {p00, p11, p22, p33} ^ k0;
assign z1 = {p10, p21, p32, p03} ^ k1;
assign z2 = {p20, p31, p02, p13} ^ k2;
assign z3 = {p30, p01, p12, p23} ^ k3;
always @ (posedge clk)
state_out <= {z0, z1, z2, z3};
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version:%version
// \ \ Application: MIG
// / / Filename: mig_7series_v2_3_poc_pd.v
// /___/ /\ Date Last Modified: $$
// \ \ / \ Date Created:Tue 15 Jan 2014
// \___\/\___\
//
//Device: Virtex-7
//Design Name: DDR3 SDRAM
//Purpose: IDDR used as phase detector. The pos_edge and neg_edge stuff
// prevents any noise that could happen when the phase shift clock is very
// nearly aligned to the fabric clock.
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1 ps / 1 ps
module mig_7series_v2_3_poc_pd #
(parameter POC_USE_METASTABLE_SAMP = "FALSE",
parameter SIM_CAL_OPTION = "NONE",
parameter TCQ = 100)
(/*AUTOARG*/
// Outputs
pd_out,
// Inputs
iddr_rst, clk, kclk, mmcm_ps_clk
);
input iddr_rst;
input clk;
input kclk;
input mmcm_ps_clk;
wire q1;
IDDR #
(.DDR_CLK_EDGE ("OPPOSITE_EDGE"),
.INIT_Q1 (1'b0),
.INIT_Q2 (1'b0),
.SRTYPE ("SYNC"))
u_phase_detector
(.Q1 (q1),
.Q2 (),
.C (mmcm_ps_clk),
.CE (1'b1),
.D (kclk),
.R (iddr_rst),
.S (1'b0));
// Path from q1 to xxx_edge_samp must be constrained to be less than 1/4 cycle. FIXME
reg pos_edge_samp;
generate if (SIM_CAL_OPTION == "NONE" || POC_USE_METASTABLE_SAMP == "TRUE") begin : no_eXes
always @(posedge clk) pos_edge_samp <= #TCQ q1;
end else begin : eXes
reg q1_delayed;
reg rising_clk_seen;
always @(posedge mmcm_ps_clk) begin
rising_clk_seen <= 1'b0;
q1_delayed <= 1'bx;
end
always @(posedge clk) begin
rising_clk_seen = 1'b1;
if (rising_clk_seen) q1_delayed <= q1;
end
always @(posedge clk) begin
pos_edge_samp <= q1_delayed;
end
end endgenerate
reg pd_out_r;
always @(posedge clk) pd_out_r <= #TCQ pos_edge_samp;
output pd_out;
assign pd_out = pd_out_r;
endmodule // mic_7series_v2_3_poc_pd
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKDLYBUF4S15_1_V
`define SKY130_FD_SC_LP__CLKDLYBUF4S15_1_V
/**
* clkdlybuf4s15: Clock Delay Buffer 4-stage 0.15um length inner stage
* gates.
*
* Verilog wrapper for clkdlybuf4s15 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__clkdlybuf4s15.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkdlybuf4s15_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__clkdlybuf4s15 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkdlybuf4s15_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__clkdlybuf4s15 base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKDLYBUF4S15_1_V
|
(** * Poly: Polymorphism and Higher-Order Functions *)
(* Final reminder: Please do not put solutions to the exercises in
publicly accessible places. Thank you!! *)
(* Suppress some annoying warnings from Coq: *)
Set Warnings "-notation-overridden,-parsing".
From LF Require Export Lists.
(* ################################################################# *)
(** * Polymorphism *)
(** In this chapter we continue our development of basic
concepts of functional programming. The critical new ideas are
_polymorphism_ (abstracting functions over the types of the data
they manipulate) and _higher-order functions_ (treating functions
as data). We begin with polymorphism. *)
(* ================================================================= *)
(** ** Polymorphic Lists *)
(** For the last couple of chapters, we've been working just
with lists of numbers. Obviously, interesting programs also need
to be able to manipulate lists with elements from other types --
lists of strings, lists of booleans, lists of lists, etc. We
_could_ just define a new inductive datatype for each of these,
for example... *)
Inductive boollist : Type :=
| bool_nil
| bool_cons (b : bool) (l : boollist).
(** ... but this would quickly become tedious, partly because we
have to make up different constructor names for each datatype, but
mostly because we would also need to define new versions of all
our list manipulating functions ([length], [rev], etc.) for each
new datatype definition. *)
(** To avoid all this repetition, Coq supports _polymorphic_
inductive type definitions. For example, here is a _polymorphic
list_ datatype. *)
Inductive list (X:Type) : Type :=
| nil
| cons (x : X) (l : list X).
(** This is exactly like the definition of [natlist] from the
previous chapter, except that the [nat] argument to the [cons]
constructor has been replaced by an arbitrary type [X], a binding
for [X] has been added to the header, and the occurrences of
[natlist] in the types of the constructors have been replaced by
[list X]. (We can re-use the constructor names [nil] and [cons]
because the earlier definition of [natlist] was inside of a
[Module] definition that is now out of scope.)
What sort of thing is [list] itself? One good way to think
about it is that [list] is a _function_ from [Type]s to
[Inductive] definitions; or, to put it another way, [list] is a
function from [Type]s to [Type]s. For any particular type [X],
the type [list X] is an [Inductive]ly defined set of lists whose
elements are of type [X]. *)
Check list.
(* ===> list : Type -> Type *)
(** The parameter [X] in the definition of [list] automatically
becomes a parameter to the constructors [nil] and [cons] -- that
is, [nil] and [cons] are now polymorphic constructors; when we use
them, we must now provide a first argument that is the type of the
list they are building. For example, [nil nat] constructs the
empty list of type [nat]. *)
Check (nil nat).
(* ===> nil nat : list nat *)
(** Similarly, [cons nat] adds an element of type [nat] to a list of
type [list nat]. Here is an example of forming a list containing
just the natural number 3. *)
Check (cons nat 3 (nil nat)).
(* ===> cons nat 3 (nil nat) : list nat *)
(** What might the type of [nil] be? We can read off the type [list X]
from the definition, but this omits the binding for [X] which is
the parameter to [list]. [Type -> list X] does not explain the
meaning of [X]. [(X : Type) -> list X] comes closer. Coq's
notation for this situation is [forall X : Type, list X]. *)
Check nil.
(* ===> nil : forall X : Type, list X *)
(** Similarly, the type of [cons] from the definition looks like
[X -> list X -> list X], but using this convention to explain the
meaning of [X] results in the type [forall X, X -> list X -> list
X]. *)
Check cons.
(* ===> cons : forall X : Type, X -> list X -> list X *)
(** (Side note on notation: In .v files, the "forall" quantifier
is spelled out in letters. In the generated HTML files and in the
way various IDEs show .v files (with certain settings of their
display controls), [forall] is usually typeset as the usual
mathematical "upside down A," but you'll still see the spelled-out
"forall" in a few places. This is just a quirk of typesetting:
there is no difference in meaning.) *)
(** Having to supply a type argument for each use of a list
constructor may seem an awkward burden, but we will soon see
ways of reducing that burden. *)
Check (cons nat 2 (cons nat 1 (nil nat))).
(** (We've written [nil] and [cons] explicitly here because we haven't
yet defined the [ [] ] and [::] notations for the new version of
lists. We'll do that in a bit.) *)
(** We can now go back and make polymorphic versions of all the
list-processing functions that we wrote before. Here is [repeat],
for example: *)
Fixpoint repeat (X : Type) (x : X) (count : nat) : list X :=
match count with
| 0 => nil X
| S count' => cons X x (repeat X x count')
end.
(** As with [nil] and [cons], we can use [repeat] by applying it
first to a type and then to an element of this type (and a number): *)
Example test_repeat1 :
repeat nat 4 2 = cons nat 4 (cons nat 4 (nil nat)).
Proof. reflexivity. Qed.
(** To use [repeat] to build other kinds of lists, we simply
instantiate it with an appropriate type parameter: *)
Example test_repeat2 :
repeat bool false 1 = cons bool false (nil bool).
Proof. reflexivity. Qed.
(** **** Exercise: 2 stars, standard (mumble_grumble)
Consider the following two inductively defined types. *)
Module MumbleGrumble.
Inductive mumble : Type :=
| a
| b (x : mumble) (y : nat)
| c.
Inductive grumble (X:Type) : Type :=
| d (m : mumble)
| e (x : X).
(** Which of the following are well-typed elements of [grumble X] for
some type [X]? (Add YES or NO to each line.)
- [d (b a 5)]
- [d mumble (b a 5)]
- [d bool (b a 5)]
- [e bool true]
- [e mumble (b c 0)]
- [e bool (b c 0)]
- [c] *)
(* FILL IN HERE *)
End MumbleGrumble.
(* Do not modify the following line: *)
Definition manual_grade_for_mumble_grumble : option (nat*string) := None.
(** [] *)
(* ----------------------------------------------------------------- *)
(** *** Type Annotation Inference *)
(** Let's write the definition of [repeat] again, but this time we
won't specify the types of any of the arguments. Will Coq still
accept it? *)
Fixpoint repeat' X x count : list X :=
match count with
| 0 => nil X
| S count' => cons X x (repeat' X x count')
end.
(** Indeed it will. Let's see what type Coq has assigned to [repeat']: *)
Check repeat'.
(* ===> forall X : Type, X -> nat -> list X *)
Check repeat.
(* ===> forall X : Type, X -> nat -> list X *)
(** It has exactly the same type as [repeat]. Coq was able
to use _type inference_ to deduce what the types of [X], [x], and
[count] must be, based on how they are used. For example, since
[X] is used as an argument to [cons], it must be a [Type], since
[cons] expects a [Type] as its first argument; matching [count]
with [0] and [S] means it must be a [nat]; and so on.
This powerful facility means we don't always have to write
explicit type annotations everywhere, although explicit type
annotations are still quite useful as documentation and sanity
checks, so we will continue to use them most of the time. You
should try to find a balance in your own code between too many
type annotations (which can clutter and distract) and too
few (which forces readers to perform type inference in their heads
in order to understand your code). *)
(* ----------------------------------------------------------------- *)
(** *** Type Argument Synthesis *)
(** To use a polymorphic function, we need to pass it one or
more types in addition to its other arguments. For example, the
recursive call in the body of the [repeat] function above must
pass along the type [X]. But since the second argument to
[repeat] is an element of [X], it seems entirely obvious that the
first argument can only be [X] -- why should we have to write it
explicitly?
Fortunately, Coq permits us to avoid this kind of redundancy. In
place of any type argument we can write a "hole" [_], which can be
read as "Please try to figure out for yourself what belongs here."
More precisely, when Coq encounters a [_], it will attempt to
_unify_ all locally available information -- the type of the
function being applied, the types of the other arguments, and the
type expected by the context in which the application appears --
to determine what concrete type should replace the [_].
This may sound similar to type annotation inference -- indeed, the
two procedures rely on the same underlying mechanisms. Instead of
simply omitting the types of some arguments to a function, like
repeat' X x count : list X :=
we can also replace the types with [_]
repeat' (X : _) (x : _) (count : _) : list X :=
to tell Coq to attempt to infer the missing information.
Using holes, the [repeat] function can be written like this: *)
Fixpoint repeat'' X x count : list X :=
match count with
| 0 => nil _
| S count' => cons _ x (repeat'' _ x count')
end.
(** In this instance, we don't save much by writing [_] instead of
[X]. But in many cases the difference in both keystrokes and
readability is nontrivial. For example, suppose we want to write
down a list containing the numbers [1], [2], and [3]. Instead of
writing this... *)
Definition list123 :=
cons nat 1 (cons nat 2 (cons nat 3 (nil nat))).
(** ...we can use holes to write this: *)
Definition list123' :=
cons _ 1 (cons _ 2 (cons _ 3 (nil _))).
(* ----------------------------------------------------------------- *)
(** *** Implicit Arguments *)
(** We can go further and even avoid writing [_]'s in most cases by
telling Coq _always_ to infer the type argument(s) of a given
function.
The [Arguments] directive specifies the name of the function (or
constructor) and then lists its argument names, with curly braces
around any arguments to be treated as implicit. (If some
arguments of a definition don't have a name, as is often the case
for constructors, they can be marked with a wildcard pattern
[_].) *)
Arguments nil {X}.
Arguments cons {X} _ _.
Arguments repeat {X} x count.
(** Now, we don't have to supply type arguments at all: *)
Definition list123'' := cons 1 (cons 2 (cons 3 nil)).
(** Alternatively, we can declare an argument to be implicit
when defining the function itself, by surrounding it in curly
braces instead of parens. For example: *)
Fixpoint repeat''' {X : Type} (x : X) (count : nat) : list X :=
match count with
| 0 => nil
| S count' => cons x (repeat''' x count')
end.
(** (Note that we didn't even have to provide a type argument to the
recursive call to [repeat''']; indeed, it would be invalid to
provide one!)
We will use the latter style whenever possible, but we will
continue to use explicit [Argument] declarations for [Inductive]
constructors. The reason for this is that marking the parameter
of an inductive type as implicit causes it to become implicit for
the type itself, not just for its constructors. For instance,
consider the following alternative definition of the [list]
type: *)
Inductive list' {X:Type} : Type :=
| nil'
| cons' (x : X) (l : list').
(** Because [X] is declared as implicit for the _entire_ inductive
definition including [list'] itself, we now have to write just
[list'] whether we are talking about lists of numbers or booleans
or anything else, rather than [list' nat] or [list' bool] or
whatever; this is a step too far. *)
(** Let's finish by re-implementing a few other standard list
functions on our new polymorphic lists... *)
Fixpoint app {X : Type} (l1 l2 : list X)
: (list X) :=
match l1 with
| nil => l2
| cons h t => cons h (app t l2)
end.
Fixpoint rev {X:Type} (l:list X) : list X :=
match l with
| nil => nil
| cons h t => app (rev t) (cons h nil)
end.
Fixpoint length {X : Type} (l : list X) : nat :=
match l with
| nil => 0
| cons _ l' => S (length l')
end.
Example test_rev1 :
rev (cons 1 (cons 2 nil)) = (cons 2 (cons 1 nil)).
Proof. reflexivity. Qed.
Example test_rev2:
rev (cons true nil) = cons true nil.
Proof. reflexivity. Qed.
Example test_length1: length (cons 1 (cons 2 (cons 3 nil))) = 3.
Proof. reflexivity. Qed.
(* ----------------------------------------------------------------- *)
(** *** Supplying Type Arguments Explicitly *)
(** One small problem with declaring arguments [Implicit] is
that, occasionally, Coq does not have enough local information to
determine a type argument; in such cases, we need to tell Coq that
we want to give the argument explicitly just this time. For
example, suppose we write this: *)
Fail Definition mynil := nil.
(** (The [Fail] qualifier that appears before [Definition] can be
used with _any_ command, and is used to ensure that that command
indeed fails when executed. If the command does fail, Coq prints
the corresponding error message, but continues processing the rest
of the file.)
Here, Coq gives us an error because it doesn't know what type
argument to supply to [nil]. We can help it by providing an
explicit type declaration (so that Coq has more information
available when it gets to the "application" of [nil]): *)
Definition mynil : list nat := nil.
(** Alternatively, we can force the implicit arguments to be explicit by
prefixing the function name with [@]. *)
Check @nil.
Definition mynil' := @nil nat.
(** Using argument synthesis and implicit arguments, we can
define convenient notation for lists, as before. Since we have
made the constructor type arguments implicit, Coq will know to
automatically infer these when we use the notations. *)
Notation "x :: y" := (cons x y)
(at level 60, right associativity).
Notation "[ ]" := nil.
Notation "[ x ; .. ; y ]" := (cons x .. (cons y []) ..).
Notation "x ++ y" := (app x y)
(at level 60, right associativity).
(** Now lists can be written just the way we'd hope: *)
Definition list123''' := [1; 2; 3].
(* ----------------------------------------------------------------- *)
(** *** Exercises *)
(** **** Exercise: 2 stars, standard, optional (poly_exercises)
Here are a few simple exercises, just like ones in the [Lists]
chapter, for practice with polymorphism. Complete the proofs below. *)
Theorem app_nil_r : forall (X:Type), forall l:list X,
l ++ [] = l.
Proof.
(* FILL IN HERE *) Admitted.
Theorem app_assoc : forall A (l m n:list A),
l ++ m ++ n = (l ++ m) ++ n.
Proof.
(* FILL IN HERE *) Admitted.
Lemma app_length : forall (X:Type) (l1 l2 : list X),
length (l1 ++ l2) = length l1 + length l2.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, standard, optional (more_poly_exercises)
Here are some slightly more interesting ones... *)
Theorem rev_app_distr: forall X (l1 l2 : list X),
rev (l1 ++ l2) = rev l2 ++ rev l1.
Proof.
(* FILL IN HERE *) Admitted.
Theorem rev_involutive : forall X : Type, forall l : list X,
rev (rev l) = l.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ================================================================= *)
(** ** Polymorphic Pairs *)
(** Following the same pattern, the type definition we gave in
the last chapter for pairs of numbers can be generalized to
_polymorphic pairs_, often called _products_: *)
Inductive prod (X Y : Type) : Type :=
| pair (x : X) (y : Y).
Arguments pair {X} {Y} _ _.
(** As with lists, we make the type arguments implicit and define the
familiar concrete notation. *)
Notation "( x , y )" := (pair x y).
(** We can also use the [Notation] mechanism to define the standard
notation for product _types_: *)
Notation "X * Y" := (prod X Y) : type_scope.
(** (The annotation [: type_scope] tells Coq that this abbreviation
should only be used when parsing types. This avoids a clash with
the multiplication symbol.) *)
(** It is easy at first to get [(x,y)] and [X*Y] confused.
Remember that [(x,y)] is a _value_ built from two other values,
while [X*Y] is a _type_ built from two other types. If [x] has
type [X] and [y] has type [Y], then [(x,y)] has type [X*Y]. *)
(** The first and second projection functions now look pretty
much as they would in any functional programming language. *)
Definition fst {X Y : Type} (p : X * Y) : X :=
match p with
| (x, y) => x
end.
Definition snd {X Y : Type} (p : X * Y) : Y :=
match p with
| (x, y) => y
end.
(** The following function takes two lists and combines them
into a list of pairs. In other functional languages, it is often
called [zip]; we call it [combine] for consistency with Coq's
standard library. *)
Fixpoint combine {X Y : Type} (lx : list X) (ly : list Y)
: list (X*Y) :=
match lx, ly with
| [], _ => []
| _, [] => []
| x :: tx, y :: ty => (x, y) :: (combine tx ty)
end.
(** **** Exercise: 1 star, standard, optional (combine_checks)
Try answering the following questions on paper and
checking your answers in Coq:
- What is the type of [combine] (i.e., what does [Check
@combine] print?)
- What does
Compute (combine [1;2] [false;false;true;true]).
print?
[] *)
(** **** Exercise: 2 stars, standard, recommended (split)
The function [split] is the right inverse of [combine]: it takes a
list of pairs and returns a pair of lists. In many functional
languages, it is called [unzip].
Fill in the definition of [split] below. Make sure it passes the
given unit test. *)
Fixpoint split {X Y : Type} (l : list (X*Y))
: (list X) * (list Y)
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
Example test_split:
split [(1,false);(2,false)] = ([1;2],[false;false]).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ================================================================= *)
(** ** Polymorphic Options *)
(** One last polymorphic type for now: _polymorphic options_,
which generalize [natoption] from the previous chapter. (We put
the definition inside a module because the standard library
already defines [option] and it's this one that we want to use
below.) *)
Module OptionPlayground.
Inductive option (X:Type) : Type :=
| Some (x : X)
| None.
Arguments Some {X} _.
Arguments None {X}.
End OptionPlayground.
(** We can now rewrite the [nth_error] function so that it works
with any type of lists. *)
Fixpoint nth_error {X : Type} (l : list X) (n : nat)
: option X :=
match l with
| [] => None
| a :: l' => if n =? O then Some a else nth_error l' (pred n)
end.
Example test_nth_error1 : nth_error [4;5;6;7] 0 = Some 4.
Proof. reflexivity. Qed.
Example test_nth_error2 : nth_error [[1];[2]] 1 = Some [2].
Proof. reflexivity. Qed.
Example test_nth_error3 : nth_error [true] 2 = None.
Proof. reflexivity. Qed.
(** **** Exercise: 1 star, standard, optional (hd_error_poly)
Complete the definition of a polymorphic version of the
[hd_error] function from the last chapter. Be sure that it
passes the unit tests below. *)
Definition hd_error {X : Type} (l : list X) : option X
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
(** Once again, to force the implicit arguments to be explicit,
we can use [@] before the name of the function. *)
Check @hd_error.
Example test_hd_error1 : hd_error [1;2] = Some 1.
(* FILL IN HERE *) Admitted.
Example test_hd_error2 : hd_error [[1];[2]] = Some [1].
(* FILL IN HERE *) Admitted.
(** [] *)
(* ################################################################# *)
(** * Functions as Data *)
(** Like many other modern programming languages -- including
all functional languages (ML, Haskell, Scheme, Scala, Clojure,
etc.) -- Coq treats functions as first-class citizens, allowing
them to be passed as arguments to other functions, returned as
results, stored in data structures, etc. *)
(* ================================================================= *)
(** ** Higher-Order Functions *)
(** Functions that manipulate other functions are often called
_higher-order_ functions. Here's a simple one: *)
Definition doit3times {X:Type} (f:X->X) (n:X) : X :=
f (f (f n)).
(** The argument [f] here is itself a function (from [X] to
[X]); the body of [doit3times] applies [f] three times to some
value [n]. *)
Check @doit3times.
(* ===> doit3times : forall X : Type, (X -> X) -> X -> X *)
Example test_doit3times: doit3times minustwo 9 = 3.
Proof. reflexivity. Qed.
Example test_doit3times': doit3times negb true = false.
Proof. reflexivity. Qed.
(* ================================================================= *)
(** ** Filter *)
(** Here is a more useful higher-order function, taking a list
of [X]s and a _predicate_ on [X] (a function from [X] to [bool])
and "filtering" the list, returning a new list containing just
those elements for which the predicate returns [true]. *)
Fixpoint filter {X:Type} (test: X->bool) (l:list X)
: (list X) :=
match l with
| [] => []
| h :: t => if test h then h :: (filter test t)
else filter test t
end.
(** For example, if we apply [filter] to the predicate [evenb]
and a list of numbers [l], it returns a list containing just the
even members of [l]. *)
Example test_filter1: filter evenb [1;2;3;4] = [2;4].
Proof. reflexivity. Qed.
Definition length_is_1 {X : Type} (l : list X) : bool :=
(length l) =? 1.
Example test_filter2:
filter length_is_1
[ [1; 2]; [3]; [4]; [5;6;7]; []; [8] ]
= [ [3]; [4]; [8] ].
Proof. reflexivity. Qed.
(** We can use [filter] to give a concise version of the
[countoddmembers] function from the [Lists] chapter. *)
Definition countoddmembers' (l:list nat) : nat :=
length (filter oddb l).
Example test_countoddmembers'1: countoddmembers' [1;0;3;1;4;5] = 4.
Proof. reflexivity. Qed.
Example test_countoddmembers'2: countoddmembers' [0;2;4] = 0.
Proof. reflexivity. Qed.
Example test_countoddmembers'3: countoddmembers' nil = 0.
Proof. reflexivity. Qed.
(* ================================================================= *)
(** ** Anonymous Functions *)
(** It is arguably a little sad, in the example just above, to
be forced to define the function [length_is_1] and give it a name
just to be able to pass it as an argument to [filter], since we
will probably never use it again. Moreover, this is not an
isolated example: when using higher-order functions, we often want
to pass as arguments "one-off" functions that we will never use
again; having to give each of these functions a name would be
tedious.
Fortunately, there is a better way. We can construct a function
"on the fly" without declaring it at the top level or giving it a
name. *)
Example test_anon_fun':
doit3times (fun n => n * n) 2 = 256.
Proof. reflexivity. Qed.
(** The expression [(fun n => n * n)] can be read as "the function
that, given a number [n], yields [n * n]." *)
(** Here is the [filter] example, rewritten to use an anonymous
function. *)
Example test_filter2':
filter (fun l => (length l) =? 1)
[ [1; 2]; [3]; [4]; [5;6;7]; []; [8] ]
= [ [3]; [4]; [8] ].
Proof. reflexivity. Qed.
(** **** Exercise: 2 stars, standard (filter_even_gt7)
Use [filter] (instead of [Fixpoint]) to write a Coq function
[filter_even_gt7] that takes a list of natural numbers as input
and returns a list of just those that are even and greater than
7. *)
Definition filter_even_gt7 (l : list nat) : list nat
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
Example test_filter_even_gt7_1 :
filter_even_gt7 [1;2;6;9;10;3;12;8] = [10;12;8].
(* FILL IN HERE *) Admitted.
Example test_filter_even_gt7_2 :
filter_even_gt7 [5;2;6;19;129] = [].
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, standard (partition)
Use [filter] to write a Coq function [partition]:
partition : forall X : Type,
(X -> bool) -> list X -> list X * list X
Given a set [X], a test function of type [X -> bool] and a [list
X], [partition] should return a pair of lists. The first member of
the pair is the sublist of the original list containing the
elements that satisfy the test, and the second is the sublist
containing those that fail the test. The order of elements in the
two sublists should be the same as their order in the original
list. *)
Definition partition {X : Type}
(test : X -> bool)
(l : list X)
: list X * list X
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
Example test_partition1: partition oddb [1;2;3;4;5] = ([1;3;5], [2;4]).
(* FILL IN HERE *) Admitted.
Example test_partition2: partition (fun x => false) [5;9;0] = ([], [5;9;0]).
(* FILL IN HERE *) Admitted.
(** [] *)
(* ================================================================= *)
(** ** Map *)
(** Another handy higher-order function is called [map]. *)
Fixpoint map {X Y: Type} (f:X->Y) (l:list X) : (list Y) :=
match l with
| [] => []
| h :: t => (f h) :: (map f t)
end.
(** It takes a function [f] and a list [ l = [n1, n2, n3, ...] ]
and returns the list [ [f n1, f n2, f n3,...] ], where [f] has
been applied to each element of [l] in turn. For example: *)
Example test_map1: map (fun x => plus 3 x) [2;0;2] = [5;3;5].
Proof. reflexivity. Qed.
(** The element types of the input and output lists need not be
the same, since [map] takes _two_ type arguments, [X] and [Y]; it
can thus be applied to a list of numbers and a function from
numbers to booleans to yield a list of booleans: *)
Example test_map2:
map oddb [2;1;2;5] = [false;true;false;true].
Proof. reflexivity. Qed.
(** It can even be applied to a list of numbers and
a function from numbers to _lists_ of booleans to
yield a _list of lists_ of booleans: *)
Example test_map3:
map (fun n => [evenb n;oddb n]) [2;1;2;5]
= [[true;false];[false;true];[true;false];[false;true]].
Proof. reflexivity. Qed.
(* ----------------------------------------------------------------- *)
(** *** Exercises *)
(** **** Exercise: 3 stars, standard (map_rev)
Show that [map] and [rev] commute. You may need to define an
auxiliary lemma. *)
Theorem map_rev : forall (X Y : Type) (f : X -> Y) (l : list X),
map f (rev l) = rev (map f l).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, standard, recommended (flat_map)
The function [map] maps a [list X] to a [list Y] using a function
of type [X -> Y]. We can define a similar function, [flat_map],
which maps a [list X] to a [list Y] using a function [f] of type
[X -> list Y]. Your definition should work by 'flattening' the
results of [f], like so:
flat_map (fun n => [n;n+1;n+2]) [1;5;10]
= [1; 2; 3; 5; 6; 7; 10; 11; 12].
*)
Fixpoint flat_map {X Y: Type} (f: X -> list Y) (l: list X)
: (list Y)
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
Example test_flat_map1:
flat_map (fun n => [n;n;n]) [1;5;4]
= [1; 1; 1; 5; 5; 5; 4; 4; 4].
(* FILL IN HERE *) Admitted.
(** [] *)
(** Lists are not the only inductive type for which [map] makes sense.
Here is a [map] for the [option] type: *)
Definition option_map {X Y : Type} (f : X -> Y) (xo : option X)
: option Y :=
match xo with
| None => None
| Some x => Some (f x)
end.
(** **** Exercise: 2 stars, standard, optional (implicit_args)
The definitions and uses of [filter] and [map] use implicit
arguments in many places. Replace the curly braces around the
implicit arguments with parentheses, and then fill in explicit
type parameters where necessary and use Coq to check that you've
done so correctly. (This exercise is not to be turned in; it is
probably easiest to do it on a _copy_ of this file that you can
throw away afterwards.)
[] *)
(* ================================================================= *)
(** ** Fold *)
(** An even more powerful higher-order function is called
[fold]. This function is the inspiration for the "[reduce]"
operation that lies at the heart of Google's map/reduce
distributed programming framework. *)
Fixpoint fold {X Y: Type} (f: X->Y->Y) (l: list X) (b: Y)
: Y :=
match l with
| nil => b
| h :: t => f h (fold f t b)
end.
(** Intuitively, the behavior of the [fold] operation is to
insert a given binary operator [f] between every pair of elements
in a given list. For example, [ fold plus [1;2;3;4] ] intuitively
means [1+2+3+4]. To make this precise, we also need a "starting
element" that serves as the initial second input to [f]. So, for
example,
fold plus [1;2;3;4] 0
yields
1 + (2 + (3 + (4 + 0))).
Some more examples: *)
Check (fold andb).
(* ===> fold andb : list bool -> bool -> bool *)
Example fold_example1 :
fold mult [1;2;3;4] 1 = 24.
Proof. reflexivity. Qed.
Example fold_example2 :
fold andb [true;true;false;true] true = false.
Proof. reflexivity. Qed.
Example fold_example3 :
fold app [[1];[];[2;3];[4]] [] = [1;2;3;4].
Proof. reflexivity. Qed.
(** **** Exercise: 1 star, advanced (fold_types_different)
Observe that the type of [fold] is parameterized by _two_ type
variables, [X] and [Y], and the parameter [f] is a binary operator
that takes an [X] and a [Y] and returns a [Y]. Can you think of a
situation where it would be useful for [X] and [Y] to be
different? *)
(* FILL IN HERE *)
(* Do not modify the following line: *)
Definition manual_grade_for_fold_types_different : option (nat*string) := None.
(** [] *)
(* ================================================================= *)
(** ** Functions That Construct Functions *)
(** Most of the higher-order functions we have talked about so
far take functions as arguments. Let's look at some examples that
involve _returning_ functions as the results of other functions.
To begin, here is a function that takes a value [x] (drawn from
some type [X]) and returns a function from [nat] to [X] that
yields [x] whenever it is called, ignoring its [nat] argument. *)
Definition constfun {X: Type} (x: X) : nat->X :=
fun (k:nat) => x.
Definition ftrue := constfun true.
Example constfun_example1 : ftrue 0 = true.
Proof. reflexivity. Qed.
Example constfun_example2 : (constfun 5) 99 = 5.
Proof. reflexivity. Qed.
(** In fact, the multiple-argument functions we have already
seen are also examples of passing functions as data. To see why,
recall the type of [plus]. *)
Check plus.
(* ==> nat -> nat -> nat *)
(** Each [->] in this expression is actually a _binary_ operator
on types. This operator is _right-associative_, so the type of
[plus] is really a shorthand for [nat -> (nat -> nat)] -- i.e., it
can be read as saying that "[plus] is a one-argument function that
takes a [nat] and returns a one-argument function that takes
another [nat] and returns a [nat]." In the examples above, we
have always applied [plus] to both of its arguments at once, but
if we like we can supply just the first. This is called _partial
application_. *)
Definition plus3 := plus 3.
Check plus3.
Example test_plus3 : plus3 4 = 7.
Proof. reflexivity. Qed.
Example test_plus3' : doit3times plus3 0 = 9.
Proof. reflexivity. Qed.
Example test_plus3'' : doit3times (plus 3) 0 = 9.
Proof. reflexivity. Qed.
(* ################################################################# *)
(** * Additional Exercises *)
Module Exercises.
(** **** Exercise: 2 stars, standard (fold_length)
Many common functions on lists can be implemented in terms of
[fold]. For example, here is an alternative definition of [length]: *)
Definition fold_length {X : Type} (l : list X) : nat :=
fold (fun _ n => S n) l 0.
Example test_fold_length1 : fold_length [4;7;0] = 3.
Proof. reflexivity. Qed.
(** Prove the correctness of [fold_length]. (Hint: It may help to
know that [reflexivity] simplifies expressions a bit more
aggressively than [simpl] does -- i.e., you may find yourself in a
situation where [simpl] does nothing but [reflexivity] solves the
goal.) *)
Theorem fold_length_correct : forall X (l : list X),
fold_length l = length l.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, standard (fold_map)
We can also define [map] in terms of [fold]. Finish [fold_map]
below. *)
Definition fold_map {X Y: Type} (f: X -> Y) (l: list X) : list Y
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
(** Write down a theorem [fold_map_correct] in Coq stating that
[fold_map] is correct, and prove it. (Hint: again, remember that
[reflexivity] simplifies expressions a bit more aggressively than
[simpl].) *)
(* FILL IN HERE *)
(* Do not modify the following line: *)
Definition manual_grade_for_fold_map : option (nat*string) := None.
(** [] *)
(** **** Exercise: 2 stars, advanced (currying)
In Coq, a function [f : A -> B -> C] really has the type [A
-> (B -> C)]. That is, if you give [f] a value of type [A], it
will give you function [f' : B -> C]. If you then give [f'] a
value of type [B], it will return a value of type [C]. This
allows for partial application, as in [plus3]. Processing a list
of arguments with functions that return functions is called
_currying_, in honor of the logician Haskell Curry.
Conversely, we can reinterpret the type [A -> B -> C] as [(A *
B) -> C]. This is called _uncurrying_. With an uncurried binary
function, both arguments must be given at once as a pair; there is
no partial application. *)
(** We can define currying as follows: *)
Definition prod_curry {X Y Z : Type}
(f : X * Y -> Z) (x : X) (y : Y) : Z := f (x, y).
(** As an exercise, define its inverse, [prod_uncurry]. Then prove
the theorems below to show that the two are inverses. *)
Definition prod_uncurry {X Y Z : Type}
(f : X -> Y -> Z) (p : X * Y) : Z
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
(** As a (trivial) example of the usefulness of currying, we can use it
to shorten one of the examples that we saw above: *)
Example test_map1': map (plus 3) [2;0;2] = [5;3;5].
Proof. reflexivity. Qed.
(** Thought exercise: before running the following commands, can you
calculate the types of [prod_curry] and [prod_uncurry]? *)
Check @prod_curry.
Check @prod_uncurry.
Theorem uncurry_curry : forall (X Y Z : Type)
(f : X -> Y -> Z)
x y,
prod_curry (prod_uncurry f) x y = f x y.
Proof.
(* FILL IN HERE *) Admitted.
Theorem curry_uncurry : forall (X Y Z : Type)
(f : (X * Y) -> Z) (p : X * Y),
prod_uncurry (prod_curry f) p = f p.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, advanced (nth_error_informal)
Recall the definition of the [nth_error] function:
Fixpoint nth_error {X : Type} (l : list X) (n : nat) : option X :=
match l with
| [] => None
| a :: l' => if n =? O then Some a else nth_error l' (pred n)
end.
Write an informal proof of the following theorem:
forall X n l, length l = n -> @nth_error X l n = None
*)
(* FILL IN HERE *)
(* Do not modify the following line: *)
Definition manual_grade_for_informal_proof : option (nat*string) := None.
(** [] *)
(** The following exercises explore an alternative way of defining
natural numbers, using the so-called _Church numerals_, named
after mathematician Alonzo Church. We can represent a natural
number [n] as a function that takes a function [f] as a parameter
and returns [f] iterated [n] times. *)
Module Church.
Definition cnat := forall X : Type, (X -> X) -> X -> X.
(** Let's see how to write some numbers with this notation. Iterating
a function once should be the same as just applying it. Thus: *)
Definition one : cnat :=
fun (X : Type) (f : X -> X) (x : X) => f x.
(** Similarly, [two] should apply [f] twice to its argument: *)
Definition two : cnat :=
fun (X : Type) (f : X -> X) (x : X) => f (f x).
(** Defining [zero] is somewhat trickier: how can we "apply a function
zero times"? The answer is actually simple: just return the
argument untouched. *)
Definition zero : cnat :=
fun (X : Type) (f : X -> X) (x : X) => x.
(** More generally, a number [n] can be written as [fun X f x => f (f
... (f x) ...)], with [n] occurrences of [f]. Notice in
particular how the [doit3times] function we've defined previously
is actually just the Church representation of [3]. *)
Definition three : cnat := @doit3times.
(** Complete the definitions of the following functions. Make sure
that the corresponding unit tests pass by proving them with
[reflexivity]. *)
(** **** Exercise: 1 star, advanced (church_succ) *)
(** Successor of a natural number: given a Church numeral [n],
the successor [succ n] is a function that iterates its
argument once more than [n]. *)
Definition succ (n : cnat) : cnat
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
Example succ_1 : succ zero = one.
Proof. (* FILL IN HERE *) Admitted.
Example succ_2 : succ one = two.
Proof. (* FILL IN HERE *) Admitted.
Example succ_3 : succ two = three.
Proof. (* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star, advanced (church_plus) *)
(** Addition of two natural numbers: *)
Definition plus (n m : cnat) : cnat
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
Example plus_1 : plus zero one = one.
Proof. (* FILL IN HERE *) Admitted.
Example plus_2 : plus two three = plus three two.
Proof. (* FILL IN HERE *) Admitted.
Example plus_3 :
plus (plus two two) three = plus one (plus three three).
Proof. (* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, advanced (church_mult) *)
(** Multiplication: *)
Definition mult (n m : cnat) : cnat
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
Example mult_1 : mult one one = one.
Proof. (* FILL IN HERE *) Admitted.
Example mult_2 : mult zero (plus three three) = zero.
Proof. (* FILL IN HERE *) Admitted.
Example mult_3 : mult two three = plus three three.
Proof. (* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, advanced (church_exp) *)
(** Exponentiation: *)
(** (_Hint_: Polymorphism plays a crucial role here. However,
choosing the right type to iterate over can be tricky. If you hit
a "Universe inconsistency" error, try iterating over a different
type. Iterating over [cnat] itself is usually problematic.) *)
Definition exp (n m : cnat) : cnat
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
Example exp_1 : exp two two = plus two two.
Proof. (* FILL IN HERE *) Admitted.
Example exp_2 : exp three zero = one.
Proof. (* FILL IN HERE *) Admitted.
Example exp_3 : exp three two = plus (mult two (mult two two)) one.
Proof. (* FILL IN HERE *) Admitted.
(** [] *)
End Church.
End Exercises.
(* Wed Jan 9 12:02:44 EST 2019 *)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFSTP_2_V
`define SKY130_FD_SC_LP__SDFSTP_2_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog wrapper for sdfstp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__sdfstp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sdfstp_2 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__sdfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sdfstp_2 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__sdfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFSTP_2_V
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
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// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
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// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
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// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
// IP Revision: 11
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module system_auto_pc_1 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [1 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
input wire [3 : 0] s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [63 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [7 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [1 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [1 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
input wire [3 : 0] s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [1 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [63 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWID" *)
output wire [1 : 0] m_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
output wire [3 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
output wire [1 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WID" *)
output wire [1 : 0] m_axi_wid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [63 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [7 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
output wire m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BID" *)
input wire [1 : 0] m_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARID" *)
output wire [1 : 0] m_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
output wire [3 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
output wire [2 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
output wire [1 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
output wire [1 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
output wire [3 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
output wire [3 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RID" *)
input wire [1 : 0] m_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [63 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
input wire m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_protocol_converter_v2_1_11_axi_protocol_converter #(
.C_FAMILY("zynq"),
.C_M_AXI_PROTOCOL(1),
.C_S_AXI_PROTOCOL(0),
.C_IGNORE_ID(0),
.C_AXI_ID_WIDTH(2),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(64),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_TRANSLATION_MODE(2)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(s_axi_awregion),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(2'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(s_axi_arregion),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(m_axi_awid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(m_axi_awqos),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(m_axi_wid),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(m_axi_bid),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(m_axi_arid),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(m_axi_arqos),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(m_axi_rid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
module try_top(/*autoarg*/
// Outputs
out_momo,
// Inputs
in_momo
);
//bug1105 - should be [1:0]
/*autoinput*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [0] [127:0] in_momo; // To try0 of try1.v, ...
// End of automatics
/*autooutput*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [0] [127:0] out_momo; // From try0 of try1.v, ...
// End of automatics
/* try1 auto_template "try\(.*\)"
(
.out_momo (out_momo[@][]),
.in_momo (in_momo[@][]),
);*/
try1 try0 (/*autoinst*/
// Outputs
.out_momo (out_momo[0][127:0]), // Templated
// Inputs
.in_momo (in_momo[0][127:0])); // Templated
try1 try1 (/*autoinst*/
// Outputs
.out_momo (out_momo[1][127:0]), // Templated
// Inputs
.in_momo (in_momo[1][127:0])); // Templated
endmodule // try_top
module try1(/*autoarg*/
// Outputs
out_momo,
// Inputs
in_momo
);
input [127:0] in_momo;
output [127:0] out_momo;
endmodule // try1
|
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
// NOTE: This is still WIP.
(* techmap_celltype = "$alu" *)
module _80_altera_a10gx_alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
//output [Y_WIDTH-1:0] CO;
output CO;
wire _TECHMAP_FAIL_ = Y_WIDTH <= 4;
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
wire [Y_WIDTH-1:0] AA = A_buf;
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
//wire [Y_WIDTH:0] C = {CO, CI};
wire [Y_WIDTH+1:0] COx;
wire [Y_WIDTH+1:0] C = {COx, CI};
/* Start implementation */
(* keep *) fiftyfivenm_lcell_comb #(.lut_mask(16'b0000_0000_1010_1010), .sum_lutc_input("cin")) carry_start (.cout(COx[0]), .dataa(C[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1));
genvar i;
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice
if(i==Y_WIDTH-1) begin
(* keep *) fiftyfivenm_lcell_comb #(.lut_mask(16'b1111_0000_1110_0000), .sum_lutc_input("cin")) carry_end (.combout(COx[Y_WIDTH]), .dataa(1'b1), .datab(1'b1), .datac(1'b1), .datad(1'b1), .cin(C[Y_WIDTH]));
assign CO = COx[Y_WIDTH];
end
else
fiftyfivenm_lcell_comb #(.lut_mask(16'b1001_0110_1110_1000), .sum_lutc_input("cin")) arith_cell (.combout(Y[i]), .cout(COx[i+1]), .dataa(AA[i]), .datab(BB[i]), .datac(1'b1), .datad(1'b1), .cin(C[i+1]));
end: slice
endgenerate
/* End implementation */
assign X = AA ^ BB;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
module sky130_fd_io__top_gpio_ovtv2 ( IN, IN_H, TIE_HI_ESD, TIE_LO_ESD, AMUXBUS_A,
AMUXBUS_B, PAD, PAD_A_ESD_0_H, PAD_A_ESD_1_H, PAD_A_NOESD_H,
ANALOG_EN, ANALOG_POL, ANALOG_SEL, DM, ENABLE_H, ENABLE_INP_H, ENABLE_VDDA_H, ENABLE_VDDIO, ENABLE_VSWITCH_H, HLD_H_N,
HLD_OVR, IB_MODE_SEL, INP_DIS, OE_N, OUT, SLOW, SLEW_CTL, VTRIP_SEL, HYS_TRIM, VINREF );
input OUT;
input OE_N;
input HLD_H_N;
input ENABLE_H;
input ENABLE_INP_H;
input ENABLE_VDDA_H;
input ENABLE_VDDIO;
input ENABLE_VSWITCH_H;
input INP_DIS;
input VTRIP_SEL;
input HYS_TRIM;
input SLOW;
input [1:0] SLEW_CTL;
input HLD_OVR;
input ANALOG_EN;
input ANALOG_SEL;
input ANALOG_POL;
input [2:0] DM;
input [1:0] IB_MODE_SEL;
input VINREF;
supply1 vddio;
supply1 vddio_q;
supply1 vdda;
supply1 vccd;
supply1 vswitch;
supply1 vcchib;
supply1 vpb;
supply1 vpbhib;
supply0 vssd;
supply0 vssio;
supply0 vssio_q;
supply0 vssa;
inout PAD;
inout PAD_A_NOESD_H,PAD_A_ESD_0_H,PAD_A_ESD_1_H;
inout AMUXBUS_A;
inout AMUXBUS_B;
output IN;
output IN_H;
output TIE_HI_ESD, TIE_LO_ESD;
wire hld_h_n_del;
wire hld_h_n_buf;
reg [2:0] dm_final;
reg [1:0] slew_ctl_final;
reg slow_final, vtrip_sel_final, inp_dis_final, out_final, oe_n_final, hld_ovr_final, hys_trim_final, analog_en_final,analog_en_vdda, analog_en_vswitch,analog_en_vddio_q;
reg [1:0] ib_mode_sel_final;
wire [2:0] dm_del;
wire [1:0] slew_ctl_del;
wire [1:0] ib_mode_sel_del;
wire slow_del, vtrip_sel_del, inp_dis_del, out_del, oe_n_del, hld_ovr_del, hys_trim_del;
wire [2:0] dm_buf;
wire [1:0] slew_ctl_buf;
wire [1:0] ib_mode_sel_buf;
wire slow_buf, vtrip_sel_buf, inp_dis_buf, out_buf, oe_n_buf, hld_ovr_buf, hys_trim_buf;
reg notifier_dm, notifier_slow, notifier_oe_n, notifier_out, notifier_vtrip_sel, notifier_hld_ovr, notifier_inp_dis;
reg notifier_slew_ctl, notifier_ib_mode_sel, notifier_hys_trim;
reg notifier_enable_h, notifier, dummy_notifier1;
assign hld_h_n_buf = hld_h_n_del;
assign hld_ovr_buf = hld_ovr_del;
assign dm_buf = dm_del;
assign inp_dis_buf = inp_dis_del;
assign vtrip_sel_buf = vtrip_sel_del;
assign slow_buf = slow_del;
assign oe_n_buf = oe_n_del;
assign out_buf = out_del;
assign ib_mode_sel_buf = ib_mode_sel_del;
assign slew_ctl_buf = slew_ctl_del;
assign hys_trim_buf = hys_trim_del;
specify
( INP_DIS => IN) = (0:0:0 , 0:0:0);
( INP_DIS => IN_H) = (0:0:0 , 0:0:0);
if ( IB_MODE_SEL[1]==1'b0 & IB_MODE_SEL[0]==1'b1 ) ( PAD => IN) = (0:0:0 , 0:0:0);
if ( IB_MODE_SEL[1]==1'b0 & IB_MODE_SEL[0]==1'b1 ) ( PAD => IN_H) = (0:0:0 , 0:0:0);
if ( OE_N==1'b0 & DM[2]==1'b1 & DM[1]==1'b1 & DM[0]==1'b0 & SLOW==1'b0 ) ( OUT => PAD) = (0:0:0 , 0:0:0);
if ( OE_N==1'b0 & DM[2]==1'b1 & DM[1]==1'b1 & DM[0]==1'b0 & SLOW==1'b1 ) ( OUT => PAD) = (0:0:0 , 0:0:0);
if ( OE_N==1'b0 & DM[2]==1'b1 & DM[1]==1'b0 & DM[0]==1'b0 & SLOW==1'b0 ) ( OUT => PAD) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
if ( DM[2]==1'b1 & DM[1]==1'b0 & DM[0]==1'b0 & SLOW==1'b1 & SLEW_CTL[1]==1'b0 & SLEW_CTL[0]==1'b0 ) ( OE_N => PAD) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
if ( OE_N==1'b0 & DM[2]==1'b1 & DM[1]==1'b1 & DM[0]==1'b1 & SLOW==1'b0 ) ( OUT => PAD ) = (0:0:0 , 0:0:0);
if ( DM[2]==1'b1 & DM[1]==1'b0 & DM[0]==1'b0 & SLOW==1'b1 & SLEW_CTL[1]==1'b0 & SLEW_CTL[0]==1'b1 ) ( OE_N => PAD) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
if ( OE_N==1'b0 & DM[2]==1'b1 & DM[1]==1'b1 & DM[0]==1'b1 & SLOW==1'b1 ) ( OUT => PAD) = (0:0:0 , 0:0:0);
if ( OE_N==1'b0 & DM[2]==1'b1 & DM[1]==1'b0 & DM[0]==1'b1 & SLOW==1'b0 ) ( OUT => PAD) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
if ( DM[2]==1'b1 & DM[1]==1'b1 & DM[0]==1'b0 & SLOW==1'b0 ) ( OE_N => PAD) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
if ( OE_N==1'b0 & DM[2]==1'b1 & DM[1]==1'b0 & DM[0]==1'b1 & SLOW==1'b1 ) ( OUT => PAD ) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
if ( DM[2]==1'b1 & DM[1]==1'b1 & DM[0]==1'b0 & SLOW==1'b1 ) ( OE_N => PAD) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
if ( DM[2]==1'b1 & DM[1]==1'b0 & DM[0]==1'b0 & SLOW==1'b1 & SLEW_CTL[1]==1'b1 & SLEW_CTL[0]==1'b0 ) ( OE_N => PAD) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
if ( DM[2]==1'b1 & DM[1]==1'b0 & DM[0]==1'b0 & SLOW==1'b0 ) ( OE_N => PAD) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
if ( IB_MODE_SEL[1]==1'b1 & HYS_TRIM==1'b0 ) ( PAD => IN) = (0:0:0 , 0:0:0);
if ( IB_MODE_SEL[1]==1'b1 & HYS_TRIM==1'b0 ) ( PAD => IN_H) = (0:0:0 , 0:0:0);
if ( DM[2]==1'b1 & DM[1]==1'b0 & DM[0]==1'b0 & SLOW==1'b1 & SLEW_CTL[1]==1'b1 & SLEW_CTL[0]==1'b1 ) ( OE_N => PAD) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
if ( DM[2]==1'b1 & DM[1]==1'b1 & DM[0]==1'b1 & SLOW==1'b0 ) ( OE_N => PAD) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
if ( IB_MODE_SEL[1]==1'b1 & HYS_TRIM==1'b1 ) ( PAD => IN) = (0:0:0 , 0:0:0);
if ( IB_MODE_SEL[1]==1'b1 & HYS_TRIM==1'b1 ) ( PAD => IN_H) = (0:0:0 , 0:0:0);
if ( DM[2]==1'b1 & DM[1]==1'b1 & DM[0]==1'b1 & SLOW==1'b1 ) ( OE_N => PAD) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
if ( OE_N==1'b0 & DM[2]==1'b1 & DM[1]==1'b0 & DM[0]==1'b0 & SLOW==1'b1 & SLEW_CTL[1]==1'b1 & SLEW_CTL[0]==1'b0 ) ( OUT=> PAD) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
if ( DM[2]==1'b1 & DM[1]==1'b0 & DM[0]==1'b1 & SLOW==1'b0 ) ( OE_N => PAD) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
if ( OE_N==1'b0 & DM[2]==1'b1 & DM[1]==1'b0 & DM[0]==1'b0 & SLOW==1'b1 & SLEW_CTL[1]==1'b1 & SLEW_CTL[0]==1'b1 ) ( OUT => PAD) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
if ( DM[2]==1'b1 & DM[1]==1'b0 & DM[0]==1'b1 & SLOW==1'b1 ) ( OE_N => PAD) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
if ( DM[2]==1'b0 & DM[1]==1'b1 & DM[0]==1'b0 & SLOW==1'b0 ) ( OE_N => PAD ) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
if ( DM[2]==1'b0 & DM[1]==1'b1 & DM[0]==1'b0 & SLOW==1'b1 ) ( OE_N => PAD) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
if ( DM[2]==1'b0 & DM[1]==1'b1 & DM[0]==1'b1 & SLOW==1'b0 ) ( OE_N => PAD) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
if ( DM[2]==1'b0 & DM[1]==1'b1 & DM[0]==1'b1 & SLOW==1'b1 ) ( OE_N => PAD) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
if ( OE_N==1'b0 & DM[2]==1'b0 & DM[1]==1'b1 & DM[0]==1'b0 & SLOW==1'b0 ) ( OUT => PAD) = (0:0:0 , 0:0:0);
if ( OE_N==1'b0 & DM[2]==1'b1 & DM[1]==1'b0 & DM[0]==1'b0 & SLOW==1'b1 & SLEW_CTL[1]==1'b0 & SLEW_CTL[0]==1'b0 ) ( OUT => PAD) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
if ( OE_N==1'b0 & DM[2]==1'b0 & DM[1]==1'b1 & DM[0]==1'b0 & SLOW==1'b1 ) ( OUT => PAD) = (0:0:0 , 0:0:0);
if ( OE_N==1'b0 & DM[2]==1'b1 & DM[1]==1'b0 & DM[0]==1'b0 & SLOW==1'b1 & SLEW_CTL[1]==1'b0 & SLEW_CTL[0]==1'b1 ) ( OUT => PAD) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
if ( IB_MODE_SEL[1]==1'b0 & IB_MODE_SEL[0]==1'b0 & VTRIP_SEL==1'b0 ) ( PAD => IN) = (0:0:0 , 0:0:0);
if ( IB_MODE_SEL[1]==1'b0 & IB_MODE_SEL[0]==1'b0 & VTRIP_SEL==1'b0 ) ( PAD => IN_H) = (0:0:0 , 0:0:0);
if ( OE_N==1'b0 & DM[2]==1'b0 & DM[1]==1'b1 & DM[0]==1'b1 & SLOW==1'b0 ) ( OUT => PAD) = (0:0:0 , 0:0:0);
if ( IB_MODE_SEL[1]==1'b0 & IB_MODE_SEL[0]==1'b0 & VTRIP_SEL==1'b1 ) ( PAD => IN) = (0:0:0 , 0:0:0);
if ( IB_MODE_SEL[1]==1'b0 & IB_MODE_SEL[0]==1'b0 & VTRIP_SEL==1'b1 ) ( PAD => IN_H) = (0:0:0 , 0:0:0);
if ( OE_N==1'b0 & DM[2]==1'b0 & DM[1]==1'b1 & DM[0]==1'b1 & SLOW==1'b1 ) ( OUT => PAD) = (0:0:0 , 0:0:0);
$width (negedge HLD_H_N, (15.500:0:15.500));
$width (posedge HLD_H_N, (15.500:0:15.500));
$width (negedge HLD_OVR, (15.500:0:15.500));
$width (posedge HLD_OVR, (15.500:0:15.500));
specparam tsetup = 5;
specparam tsetup1 = 0;
specparam thold = 5;
$setuphold (posedge ENABLE_H, negedge HLD_H_N, tsetup, thold, notifier_enable_h);
$setuphold (posedge ENABLE_VDDIO, posedge ENABLE_H, tsetup1, thold, notifier_enable_h);
$setuphold (negedge ENABLE_H, negedge ENABLE_VDDIO, tsetup1, thold, notifier_enable_h);
$setuphold (negedge HLD_H_N, posedge HLD_OVR, tsetup, thold, notifier_hld_ovr, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, hld_ovr_del);
$setuphold (negedge HLD_H_N, negedge HLD_OVR, tsetup, thold, notifier_hld_ovr, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, hld_ovr_del);
$setuphold (negedge HLD_H_N, posedge DM[2], tsetup, thold, notifier_dm, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, dm_del[2]);
$setuphold (negedge HLD_H_N, negedge DM[2], tsetup, thold, notifier_dm, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, dm_del[2]);
$setuphold (negedge HLD_H_N, posedge DM[1], tsetup, thold, notifier_dm, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, dm_del[1]);
$setuphold (negedge HLD_H_N, negedge DM[1], tsetup, thold, notifier_dm, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, dm_del[1]);
$setuphold (negedge HLD_H_N, posedge DM[0], tsetup, thold, notifier_dm, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, dm_del[0]);
$setuphold (negedge HLD_H_N, negedge DM[0], tsetup, thold, notifier_dm, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, dm_del[0]);
$setuphold (negedge HLD_H_N, posedge INP_DIS, tsetup, thold, notifier_inp_dis, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, inp_dis_del);
$setuphold (negedge HLD_H_N, negedge INP_DIS, tsetup, thold, notifier_inp_dis, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, inp_dis_del);
$setuphold (negedge HLD_H_N, posedge VTRIP_SEL, tsetup, thold, notifier_vtrip_sel, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, vtrip_sel_del);
$setuphold (negedge HLD_H_N, negedge VTRIP_SEL, tsetup, thold, notifier_vtrip_sel, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, vtrip_sel_del);
$setuphold (negedge HLD_H_N, posedge HYS_TRIM, tsetup, thold, notifier_hys_trim, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, hys_trim_del);
$setuphold (negedge HLD_H_N, negedge HYS_TRIM, tsetup, thold, notifier_hys_trim, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, hys_trim_del);
$setuphold (negedge HLD_H_N, posedge SLOW, tsetup, thold, notifier_slow, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, slow_del);
$setuphold (negedge HLD_H_N, negedge SLOW, tsetup, thold, notifier_slow, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, slow_del);
$setuphold (negedge HLD_H_N, posedge OE_N, tsetup, thold, notifier_oe_n, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, oe_n_del);
$setuphold (negedge HLD_H_N, negedge OE_N, tsetup, thold, notifier_oe_n, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, oe_n_del);
$setuphold (negedge HLD_H_N, posedge OUT, tsetup, thold, notifier_out, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, out_del);
$setuphold (negedge HLD_H_N, negedge OUT, tsetup, thold, notifier_out, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, out_del);
$setuphold (negedge HLD_H_N, posedge SLEW_CTL[1], tsetup, thold, notifier_slew_ctl, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, slew_ctl_del[1]);
$setuphold (negedge HLD_H_N, negedge SLEW_CTL[1], tsetup, thold, notifier_slew_ctl, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, slew_ctl_del[1]);
$setuphold (negedge HLD_H_N, posedge SLEW_CTL[0], tsetup, thold, notifier_slew_ctl, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, slew_ctl_del[0]);
$setuphold (negedge HLD_H_N, negedge SLEW_CTL[0], tsetup, thold, notifier_slew_ctl, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, slew_ctl_del[0]);
$setuphold (negedge HLD_H_N, posedge IB_MODE_SEL[1], tsetup, thold, notifier_ib_mode_sel, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, ib_mode_sel_del[1]);
$setuphold (negedge HLD_H_N, negedge IB_MODE_SEL[1], tsetup, thold, notifier_ib_mode_sel, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, ib_mode_sel_del[1]);
$setuphold (negedge HLD_H_N, posedge IB_MODE_SEL[0], tsetup, thold, notifier_ib_mode_sel, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, ib_mode_sel_del[0]);
$setuphold (negedge HLD_H_N, negedge IB_MODE_SEL[0], tsetup, thold, notifier_ib_mode_sel, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, ib_mode_sel_del[0]);
$setuphold (posedge HLD_H_N, posedge HLD_OVR, tsetup, thold, notifier_hld_ovr, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, hld_ovr_del);
$setuphold (posedge HLD_H_N, negedge HLD_OVR, tsetup, thold, notifier_hld_ovr, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, hld_ovr_del);
$setuphold (posedge HLD_H_N, posedge DM[2], tsetup, thold, notifier_dm, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, dm_del[2]);
$setuphold (posedge HLD_H_N, negedge DM[2], tsetup, thold, notifier_dm, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, dm_del[2]);
$setuphold (posedge HLD_H_N, posedge DM[1], tsetup, thold, notifier_dm, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, dm_del[1]);
$setuphold (posedge HLD_H_N, negedge DM[1], tsetup, thold, notifier_dm, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, dm_del[1]);
$setuphold (posedge HLD_H_N, posedge DM[0], tsetup, thold, notifier_dm, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, dm_del[0]);
$setuphold (posedge HLD_H_N, negedge DM[0], tsetup, thold, notifier_dm, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, dm_del[0]);
$setuphold (posedge HLD_H_N, posedge INP_DIS, tsetup, thold, notifier_inp_dis, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, inp_dis_del);
$setuphold (posedge HLD_H_N, negedge INP_DIS, tsetup, thold, notifier_inp_dis, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, inp_dis_del);
$setuphold (posedge HLD_H_N, posedge VTRIP_SEL, tsetup, thold, notifier_vtrip_sel, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, vtrip_sel_del);
$setuphold (posedge HLD_H_N, negedge VTRIP_SEL, tsetup, thold, notifier_vtrip_sel, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, vtrip_sel_del);
$setuphold (posedge HLD_H_N, posedge HYS_TRIM, tsetup, thold, notifier_hys_trim, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, hys_trim_del);
$setuphold (posedge HLD_H_N, negedge HYS_TRIM, tsetup, thold, notifier_hys_trim, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, hys_trim_del);
$setuphold (posedge HLD_H_N, posedge SLOW, tsetup, thold, notifier_slow, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, slow_del);
$setuphold (posedge HLD_H_N, negedge SLOW, tsetup, thold, notifier_slow, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, slow_del);
$setuphold (posedge HLD_H_N, posedge OE_N, tsetup, thold, notifier_oe_n, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, oe_n_del);
$setuphold (posedge HLD_H_N, negedge OE_N, tsetup, thold, notifier_oe_n, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, oe_n_del);
$setuphold (posedge HLD_H_N, posedge OUT, tsetup, thold, notifier_out, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, out_del);
$setuphold (posedge HLD_H_N, negedge OUT, tsetup, thold, notifier_out, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, out_del);
$setuphold (posedge HLD_H_N, posedge SLEW_CTL[1], tsetup, thold, notifier_slew_ctl, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, slew_ctl_del[1]);
$setuphold (posedge HLD_H_N, negedge SLEW_CTL[1], tsetup, thold, notifier_slew_ctl, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, slew_ctl_del[1]);
$setuphold (posedge HLD_H_N, posedge SLEW_CTL[0], tsetup, thold, notifier_slew_ctl, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, slew_ctl_del[0]);
$setuphold (posedge HLD_H_N, negedge SLEW_CTL[0], tsetup, thold, notifier_slew_ctl, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, slew_ctl_del[0]);
$setuphold (posedge HLD_H_N, posedge IB_MODE_SEL[1], tsetup, thold, notifier_ib_mode_sel, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, ib_mode_sel_del[1]);
$setuphold (posedge HLD_H_N, negedge IB_MODE_SEL[1], tsetup, thold, notifier_ib_mode_sel, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, ib_mode_sel_del[1]);
$setuphold (posedge HLD_H_N, posedge IB_MODE_SEL[0], tsetup, thold, notifier_ib_mode_sel, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, ib_mode_sel_del[0]);
$setuphold (posedge HLD_H_N, negedge IB_MODE_SEL[0], tsetup, thold, notifier_ib_mode_sel, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, ib_mode_sel_del[0]);
$setuphold (posedge HLD_OVR, negedge HLD_H_N, tsetup, thold, notifier_hld_ovr, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_ovr_del, hld_h_n_del);
$setuphold (posedge DM[2], negedge HLD_H_N, tsetup, thold, notifier_dm, ENABLE_H==1'b1, ENABLE_H==1'b1, dm_del[2], hld_h_n_del);
$setuphold (posedge DM[1], negedge HLD_H_N, tsetup, thold, notifier_dm, ENABLE_H==1'b1, ENABLE_H==1'b1, dm_del[1], hld_h_n_del);
$setuphold (posedge DM[0], negedge HLD_H_N, tsetup, thold, notifier_dm, ENABLE_H==1'b1, ENABLE_H==1'b1, dm_del[0], hld_h_n_del);
$setuphold (posedge INP_DIS, negedge HLD_H_N, tsetup, thold, notifier_inp_dis, ENABLE_H==1'b1, ENABLE_H==1'b1, inp_dis_del, hld_h_n_del);
$setuphold (posedge VTRIP_SEL, negedge HLD_H_N, tsetup, thold, notifier_vtrip_sel, ENABLE_H==1'b1, ENABLE_H==1'b1, vtrip_sel_del, hld_h_n_del);
$setuphold (posedge HYS_TRIM, negedge HLD_H_N, tsetup, thold, notifier_hys_trim, ENABLE_H==1'b1, ENABLE_H==1'b1, hys_trim_del, hld_h_n_del);
$setuphold (posedge SLOW, negedge HLD_H_N, tsetup, thold, notifier_slow, ENABLE_H==1'b1, ENABLE_H==1'b1, slow_del, hld_h_n_del);
$setuphold (posedge OE_N, negedge HLD_H_N, tsetup, thold, notifier_oe_n, ENABLE_H==1'b1, ENABLE_H==1'b1, oe_n_del, hld_h_n_del);
$setuphold (posedge OUT, negedge HLD_H_N, tsetup, thold, notifier_out, ENABLE_H==1'b1, ENABLE_H==1'b1, out_del, hld_h_n_del);
$setuphold (posedge SLEW_CTL[1], negedge HLD_H_N, tsetup, thold, notifier_slew_ctl, ENABLE_H==1'b1, ENABLE_H==1'b1, slew_ctl_del[1], hld_h_n_del);
$setuphold (posedge SLEW_CTL[0], negedge HLD_H_N, tsetup, thold, notifier_slew_ctl, ENABLE_H==1'b1, ENABLE_H==1'b1, slew_ctl_del[0], hld_h_n_del);
$setuphold (posedge IB_MODE_SEL[1], negedge HLD_H_N, tsetup, thold, notifier_ib_mode_sel, ENABLE_H==1'b1, ENABLE_H==1'b1, ib_mode_sel_del[1], hld_h_n_del);
$setuphold (posedge IB_MODE_SEL[0], negedge HLD_H_N, tsetup, thold, notifier_ib_mode_sel, ENABLE_H==1'b1, ENABLE_H==1'b1, ib_mode_sel_del[0], hld_h_n_del);
endspecify
wire pwr_good_amux = 1;
wire pwr_good_inpbuff_hv = 1;
wire pwr_good_inpbuff_lv = 1;
wire pwr_good_output_driver = 1;
wire pwr_good_hold_mode = 1;
wire pwr_good_hold_ovr_mode = 1;
wire pwr_good_active_mode = 1;
wire pwr_good_hold_mode_vdda = 1;
wire pwr_good_active_mode_vdda = 1;
wire pwr_good_amux_vccd = 1;
wire pwr_good_analog_en_vdda = 1;
wire pwr_good_analog_en_vddio_q = 1;
wire pwr_good_analog_en_vswitch = 1;
parameter MAX_WARNING_COUNT = 100;
wire pad_tristate = oe_n_final === 1 || dm_final === 3'b000 || dm_final === 3'b001;
wire x_on_pad = !pwr_good_output_driver
|| (dm_final !== 3'b000 && dm_final !== 3'b001 && oe_n_final===1'bx)
|| (^dm_final[2:0] === 1'bx && oe_n_final===1'b0)
|| (slow_final===1'bx && dm_final !== 3'b000 && dm_final !== 3'b001 && oe_n_final===1'b0)
|| (slow_final===1'b1 && ^slew_ctl_final[1:0] ===1'bx && dm_final === 3'b100 && oe_n_final===1'b0);
`ifdef SKY130_FD_IO_TOP_GPIO_OVTV2_SLOW_BEHV
parameter SLOW_1_DELAY= 70 ;
parameter SLOW_0_DELAY= 40;
`else
parameter SLOW_1_DELAY= 0;
parameter SLOW_0_DELAY= 0;
`endif
`ifdef SKY130_FD_IO_TOP_GPIO_OVTV2_SLEW_BEHV
parameter SLEW_00_DELAY= 127 ;
parameter SLEW_01_DELAY= 109;
parameter SLEW_10_DELAY= 193;
parameter SLEW_11_DELAY= 136;
`else
parameter SLEW_00_DELAY= 0 ;
parameter SLEW_01_DELAY= 0;
parameter SLEW_10_DELAY= 0;
parameter SLEW_11_DELAY= 0;
`endif
integer slow_1_delay,slow_0_delay,slow_delay,slew_00_delay,slew_01_delay,slew_10_delay,slew_11_delay;
initial slow_1_delay = SLOW_1_DELAY;
initial slow_0_delay = SLOW_0_DELAY;
initial slew_00_delay = SLEW_00_DELAY;
initial slew_01_delay = SLEW_01_DELAY;
initial slew_10_delay = SLEW_10_DELAY;
initial slew_11_delay = SLEW_11_DELAY;
always @(*)
begin
if (SLOW===1)
begin
if (DM[2]===1 && DM[1]===0 && DM[0]===0)
begin
`ifdef SKY130_FD_IO_TOP_GPIO_OVTV2_SLEW_BEHV
if (SLEW_CTL[1] ===0 && SLEW_CTL[0] ===0)
slow_delay = slew_00_delay;
else if (SLEW_CTL[1] ===0 && SLEW_CTL[0] ===1)
slow_delay = slew_01_delay;
else if (SLEW_CTL[1] ===1 && SLEW_CTL[0] ===0)
slow_delay = slew_10_delay;
else if (SLEW_CTL[1] ===1 && SLEW_CTL[0] ===1)
slow_delay = slew_11_delay;
`else
slow_delay = slow_1_delay;
`endif
end
else
slow_delay = slow_1_delay;
end
else
slow_delay = slow_0_delay;
end
bufif1 (pull1, strong0) #slow_delay dm2 (PAD, out_final, x_on_pad===1 ? 1'bx : (pad_tristate===0 && dm_final===3'b010));
bufif1 (strong1, pull0) #slow_delay dm3 (PAD, out_final, x_on_pad===1 ? 1'bx : (pad_tristate===0 && dm_final===3'b011));
bufif1 (highz1, strong0) #slow_delay dm4 (PAD, out_final, x_on_pad===1 ? 1'bx : (pad_tristate===0 && dm_final===3'b100));
bufif1 (strong1, highz0) #slow_delay dm5 (PAD, out_final, x_on_pad===1 ? 1'bx : (pad_tristate===0 && dm_final===3'b101));
bufif1 (strong1, strong0) #slow_delay dm6 (PAD, out_final, x_on_pad===1 ? 1'bx : (pad_tristate===0 && dm_final===3'b110));
bufif1 (pull1, pull0) #slow_delay dm7 (PAD, out_final, x_on_pad===1 ? 1'bx : (pad_tristate===0 && dm_final===3'b111));
tran pad_esd_1 (PAD,PAD_A_NOESD_H);
tran pad_esd_2 (PAD,PAD_A_ESD_0_H);
tran pad_esd_3 (PAD,PAD_A_ESD_1_H);
wire x_on_in_hv = (ENABLE_H===0 && ^ENABLE_INP_H===1'bx)
|| (inp_dis_final===1'bx && ^dm_final[2:0]!==1'bx && dm_final !== 3'b000)
|| (^ENABLE_H===1'bx)
|| (inp_dis_final===0 && ^dm_final[2:0] === 1'bx)
|| (^ib_mode_sel_final===1'bx && inp_dis_final===0 && dm_final !== 3'b000)
|| (vtrip_sel_final===1'bx && inp_dis_final===0 && dm_final !== 3'b000 && ib_mode_sel_final===2'b00)
|| (^ENABLE_VDDIO===1'bx && inp_dis_final===0 && dm_final !== 3'b000 && ib_mode_sel_final===2'b01)
|| (ib_mode_sel_final[1]===1'b1 && VINREF !== 1'b1 && inp_dis_final===0 && dm_final !== 3'b000)
|| (ib_mode_sel_final[1]===1'b1 && hys_trim_final===1'bx && inp_dis_final===0 && dm_final !== 3'b000);
wire x_on_in_lv = (ENABLE_H===0 && ^ENABLE_VDDIO===1'bx)
|| (ENABLE_H===0 && ^ENABLE_INP_H===1'bx)
|| (inp_dis_final===1'bx && ^dm_final[2:0]!==1'bx && dm_final !== 3'b000)
|| (^ENABLE_H===1'bx)
|| (inp_dis_final===0 && ^dm_final[2:0] === 1'bx)
|| (^ib_mode_sel_final===1'bx && inp_dis_final===0 && dm_final !== 3'b000)
|| (vtrip_sel_final===1'bx && inp_dis_final===0 && dm_final !== 3'b000 && ib_mode_sel_final===2'b00)
|| (^ENABLE_VDDIO===1'bx && inp_dis_final===0 && dm_final !== 3'b000 )
|| (ib_mode_sel_final[1]===1'b1 && VINREF !== 1'b1 && inp_dis_final===0 && dm_final !== 3'b000)
|| (ib_mode_sel_final[1]===1'b1 && hys_trim_final===1'bx && inp_dis_final===0 && dm_final !== 3'b000);
wire disable_inp_buff = ENABLE_H===1 ? (dm_final===3'b000 || inp_dis_final===1) : ENABLE_INP_H===0;
assign IN_H = (x_on_in_hv===1 || pwr_good_inpbuff_hv===0) ? 1'bx : (disable_inp_buff===1 ? 0 : (^PAD===1'bx ? 1'bx : PAD));
wire disable_inp_buff_lv = ENABLE_H===1 ? (dm_final===3'b000 || inp_dis_final===1) : ENABLE_VDDIO===0;
assign IN = (x_on_in_lv ===1 || pwr_good_inpbuff_lv===0) ? 1'bx : (disable_inp_buff_lv===1 ? 0 : (^PAD===1'bx ? 1'bx : PAD));
assign TIE_HI_ESD = vddio===1'b1 ? 1'b1 : 1'bx;
assign TIE_LO_ESD = vssio===1'b0 ? 1'b0 : 1'bx;
wire functional_mode_amux = (pwr_good_analog_en_vdda ===1 && pwr_good_analog_en_vddio_q ===1 && pwr_good_analog_en_vswitch ===1 );
wire x_on_analog_en_vdda = (pwr_good_analog_en_vdda !==1
|| (functional_mode_amux ==1 && (ENABLE_H !==0 && ^hld_h_n_buf === 1'bx) || (hld_h_n_buf!== 0 && ^ENABLE_H=== 1'bx) || pwr_good_amux_vccd !==1 )
|| (functional_mode_amux ==1 && (hld_h_n_buf ===1 && ENABLE_H===1 && ^ANALOG_EN === 1'bx && ENABLE_VDDA_H ===1 && ENABLE_VSWITCH_H===1 ) || (hld_h_n_buf ===1 && ENABLE_H===1 && ANALOG_EN ===0 && ^ENABLE_VDDA_H ===1'bx) ));
wire zero_on_analog_en_vdda = ( (pwr_good_analog_en_vdda ===1 && ENABLE_VDDA_H ===0)
|| (pwr_good_analog_en_vdda ===1 && pwr_good_analog_en_vddio_q ===1 && hld_h_n_buf===0)
|| (pwr_good_analog_en_vdda ===1 && pwr_good_analog_en_vddio_q ===1 && ENABLE_H===0)
|| (pwr_good_analog_en_vdda ===1 && pwr_good_analog_en_vddio_q ===1 && pwr_good_amux_vccd && ANALOG_EN===0) );
wire x_on_analog_en_vddio_q = ( pwr_good_analog_en_vddio_q !==1
|| (functional_mode_amux ==1 && (ENABLE_H !==0 && ^hld_h_n_buf === 1'bx) || (hld_h_n_buf!== 0 && ^ENABLE_H=== 1'bx) || pwr_good_amux_vccd !==1 )
|| (functional_mode_amux ==1 && (hld_h_n_buf ===1 && ENABLE_H===1 && ^ANALOG_EN === 1'bx && ENABLE_VDDA_H ===1 && ENABLE_VSWITCH_H===1 ) ));
wire zero_on_analog_en_vddio_q = ( (pwr_good_analog_en_vddio_q ===1 && hld_h_n_buf===0)
|| (pwr_good_analog_en_vddio_q ===1 && ENABLE_H===0)
|| (pwr_good_analog_en_vddio_q ===1 && pwr_good_amux_vccd && ANALOG_EN===0) );
wire x_on_analog_en_vswitch = (pwr_good_analog_en_vswitch !==1
|| (functional_mode_amux ==1 && (ENABLE_H !==0 && ^hld_h_n_buf === 1'bx) || (hld_h_n_buf!== 0 && ^ENABLE_H=== 1'bx) || pwr_good_amux_vccd !==1 )
|| (functional_mode_amux ==1 && (hld_h_n_buf ===1 && ENABLE_H===1 && ^ANALOG_EN === 1'bx && ENABLE_VDDA_H ===1 && ENABLE_VSWITCH_H===1 ) || (hld_h_n_buf ===1 && ENABLE_H===1 && ANALOG_EN ===0 && ^ENABLE_VSWITCH_H ===1'bx) ));
wire zero_on_analog_en_vswitch = ( (pwr_good_analog_en_vswitch ===1 && ENABLE_VSWITCH_H ===0)
|| (pwr_good_analog_en_vswitch ===1 && pwr_good_analog_en_vddio_q ===1 && hld_h_n_buf===0)
|| (pwr_good_analog_en_vswitch ===1 && pwr_good_analog_en_vddio_q ===1 && ENABLE_H===0)
|| (pwr_good_analog_en_vswitch ===1 && pwr_good_analog_en_vddio_q ===1 && pwr_good_amux_vccd && ANALOG_EN===0) );
always @(*)
begin : LATCH_dm
if (^ENABLE_H===1'bx || !pwr_good_hold_mode || (ENABLE_H===1 && ^hld_h_n_buf===1'bx))
begin
dm_final <= 3'bxxx;
end
else if (ENABLE_H===0)
begin
dm_final <= 3'b000;
end
else if (hld_h_n_buf===1)
begin
dm_final <= (^dm_buf[2:0] === 1'bx || !pwr_good_active_mode) ? 3'bxxx : dm_buf;
end
end
always @(notifier_enable_h or notifier_dm)
begin
disable LATCH_dm; dm_final <= 3'bxxx;
end
always @(*)
begin : LATCH_inp_dis
if (^ENABLE_H===1'bx || !pwr_good_hold_mode || (ENABLE_H===1 && ^hld_h_n_buf===1'bx))
begin
inp_dis_final <= 1'bx;
end
else if (ENABLE_H===0)
begin
inp_dis_final <= 1'b1;
end
else if (hld_h_n_buf===1)
begin
inp_dis_final <= (^inp_dis_buf === 1'bx || !pwr_good_active_mode) ? 1'bx : inp_dis_buf;
end
end
always @(notifier_enable_h or notifier_inp_dis)
begin
disable LATCH_inp_dis; inp_dis_final <= 1'bx;
end
always @(*)
begin : LATCH_ib_mode_sel
if (^ENABLE_H===1'bx || !pwr_good_hold_mode || (ENABLE_H===1 && ^hld_h_n_buf===1'bx))
begin
ib_mode_sel_final <= 2'bxx;
end
else if (ENABLE_H===0)
begin
ib_mode_sel_final <= 2'b00;
end
else if (hld_h_n_buf===1)
begin
ib_mode_sel_final <= (^ib_mode_sel_buf[1:0] === 1'bx || !pwr_good_active_mode) ? 2'bxx : ib_mode_sel_buf;
end
end
always @(notifier_enable_h or notifier_ib_mode_sel)
begin
disable LATCH_ib_mode_sel; ib_mode_sel_final <= 2'bxx;
end
always @(*)
begin : LATCH_slew_ctl_final
if (^ENABLE_H===1'bx || !pwr_good_hold_mode || (ENABLE_H===1 && ^hld_h_n_buf===1'bx))
begin
slew_ctl_final <= 2'bxx;
end
else if (ENABLE_H===0)
begin
slew_ctl_final <= 2'b00;
end
else if (hld_h_n_buf===1)
begin
slew_ctl_final <= (^slew_ctl_buf[1:0] === 1'bx || !pwr_good_active_mode) ? 2'bxx : slew_ctl_buf;
end
end
always @(notifier_enable_h or notifier_slew_ctl)
begin
disable LATCH_slew_ctl_final; slew_ctl_final <= 2'bxx;
end
always @(*)
begin : LATCH_vtrip_sel
if (^ENABLE_H===1'bx || !pwr_good_hold_mode || (ENABLE_H===1 && ^hld_h_n_buf===1'bx))
begin
vtrip_sel_final <= 1'bx;
end
else if (ENABLE_H===0)
begin
vtrip_sel_final <= 1'b0;
end
else if (hld_h_n_buf===1)
begin
vtrip_sel_final <= (^vtrip_sel_buf === 1'bx || !pwr_good_active_mode) ? 1'bx : vtrip_sel_buf;
end
end
always @(notifier_enable_h or notifier_vtrip_sel)
begin
disable LATCH_vtrip_sel; vtrip_sel_final <= 1'bx;
end
always @(*)
begin : LATCH_hys_trim
if (^ENABLE_H===1'bx || !pwr_good_hold_mode || (ENABLE_H===1 && ^hld_h_n_buf===1'bx))
begin
hys_trim_final <= 1'bx;
end
else if (ENABLE_H===0)
begin
hys_trim_final <= 1'b0;
end
else if (hld_h_n_buf===1)
begin
hys_trim_final <= (^hys_trim_buf === 1'bx || !pwr_good_active_mode) ? 1'bx : hys_trim_buf;
end
end
always @(notifier_enable_h or notifier_hys_trim)
begin
disable LATCH_hys_trim; hys_trim_final <= 1'bx;
end
always @(*)
begin : LATCH_slow
if (^ENABLE_H===1'bx || !pwr_good_hold_mode || (ENABLE_H===1 && ^hld_h_n_buf===1'bx))
begin
slow_final <= 1'bx;
end
else if (ENABLE_H===0)
begin
slow_final <= 1'b0;
end
else if (hld_h_n_buf===1)
begin
slow_final <= (^slow_buf === 1'bx || !pwr_good_active_mode) ? 1'bx : slow_buf;
end
end
always @(notifier_enable_h or notifier_slow)
begin
disable LATCH_slow; slow_final <= 1'bx;
end
always @(*)
begin : LATCH_hld_ovr
if (^ENABLE_H===1'bx || !pwr_good_hold_mode || (ENABLE_H===1 && ^hld_h_n_buf===1'bx))
begin
hld_ovr_final <= 1'bx;
end
else if (ENABLE_H===0)
begin
hld_ovr_final <= 1'b0;
end
else if (hld_h_n_buf===1)
begin
hld_ovr_final <= (^hld_ovr_buf === 1'bx || !pwr_good_active_mode) ? 1'bx : hld_ovr_buf;
end
end
always @(notifier_enable_h or notifier_hld_ovr)
begin
disable LATCH_hld_ovr; hld_ovr_final <= 1'bx;
end
always @(*)
begin : LATCH_oe_n
if (^ENABLE_H===1'bx || !pwr_good_hold_mode || (ENABLE_H===1 && (^hld_h_n_buf===1'bx || (hld_h_n_buf===0 && hld_ovr_final===1'bx)|| (hld_h_n_buf===1 && hld_ovr_final===1'bx))))
begin
oe_n_final <= 1'bx;
end
else if (ENABLE_H===0)
begin
oe_n_final <= 1'b1;
end
else if (hld_h_n_buf===1 || hld_ovr_final===1)
begin
oe_n_final <= (^oe_n_buf === 1'bx || !pwr_good_hold_ovr_mode) ? 1'bx : oe_n_buf;
end
end
always @(notifier_enable_h or notifier_oe_n)
begin
disable LATCH_oe_n; oe_n_final <= 1'bx;
end
always @(*)
begin : LATCH_out
if (^ENABLE_H===1'bx || !pwr_good_hold_mode || (ENABLE_H===1 && (^hld_h_n_buf===1'bx ||(hld_h_n_buf===0 && hld_ovr_final===1'bx)||(hld_h_n_buf===1 && hld_ovr_final===1'bx))))
begin
out_final <= 1'bx;
end
else if (ENABLE_H===0)
begin
out_final <= 1'b1;
end
else if (hld_h_n_buf===1 || hld_ovr_final===1)
begin
out_final <= (^out_buf === 1'bx || !pwr_good_hold_ovr_mode) ? 1'bx : out_buf;
end
end
always @(notifier_enable_h or notifier_out)
begin
disable LATCH_out; out_final <= 1'bx;
end
always @(*)
begin
if (x_on_analog_en_vdda ===1 )
begin
analog_en_vdda <= 1'bx;
end
else if ( zero_on_analog_en_vdda ===1 )
begin
analog_en_vdda <= 1'b0;
end
else if (x_on_analog_en_vdda !==1 && zero_on_analog_en_vdda !==1)
begin
analog_en_vdda <= ANALOG_EN;
end
if (x_on_analog_en_vddio_q ===1 )
begin
analog_en_vddio_q <= 1'bx;
end
else if ( zero_on_analog_en_vddio_q ===1 )
begin
analog_en_vddio_q <= 1'b0;
end
else if ( x_on_analog_en_vddio_q !==1 && zero_on_analog_en_vddio_q !==1)
begin
analog_en_vddio_q <= ANALOG_EN;
end
if (x_on_analog_en_vswitch ===1 )
begin
analog_en_vswitch <= 1'bx;
end
else if ( zero_on_analog_en_vswitch ===1 )
begin
analog_en_vswitch <= 1'b0;
end
else if (x_on_analog_en_vswitch !==1 && zero_on_analog_en_vswitch !==1)
begin
analog_en_vswitch <= ANALOG_EN;
end
if ( (analog_en_vswitch ===1'bx && analog_en_vdda ===1'bx) || (analog_en_vswitch ===1'bx && analog_en_vddio_q ===1'bx) || (analog_en_vddio_q ===1'bx && analog_en_vdda ===1'bx ) )
begin
analog_en_final <= 1'bx;
end
else if (analog_en_vdda ===1'bx && (analog_en_vddio_q ===1 ||analog_en_vswitch===1 ))
begin
analog_en_final <= 1'bx;
end
else if (analog_en_vddio_q ===1'bx && (analog_en_vdda ===1 ||analog_en_vswitch===1 ))
begin
analog_en_final <= 1'bx;
end
else if (analog_en_vswitch===1'bx && (analog_en_vdda ===1 || analog_en_vddio_q ===1 ))
begin
analog_en_final <= 1'bx;
end
else if ((analog_en_vdda ===0 && analog_en_vddio_q ===0 )|| (analog_en_vdda ===0 && analog_en_vswitch===0 ) || (analog_en_vddio_q ===0 && analog_en_vswitch===0 ))
begin
analog_en_final <=0;
end
else if (analog_en_vdda ===1 && analog_en_vddio_q ===1 && analog_en_vswitch ===1)
begin
analog_en_final <=1;
end
end
wire [2:0] amux_select = {ANALOG_SEL, ANALOG_POL, out_buf};
wire invalid_controls_amux = (analog_en_final===1'bx && inp_dis_final===1)
|| !pwr_good_amux
|| (analog_en_final===1 && ^amux_select[2:0] === 1'bx && inp_dis_final===1);
wire enable_pad_amuxbus_a = invalid_controls_amux ? 1'bx : (amux_select===3'b001 || amux_select===3'b010) && (analog_en_final===1);
wire enable_pad_amuxbus_b = invalid_controls_amux ? 1'bx : (amux_select===3'b101 || amux_select===3'b110) && (analog_en_final===1);
wire enable_pad_vssio_q = invalid_controls_amux ? 1'bx : (amux_select===3'b100 || amux_select===3'b000) && (analog_en_final===1);
wire enable_pad_vddio_q = invalid_controls_amux ? 1'bx : (amux_select===3'b011 || amux_select===3'b111) && (analog_en_final===1);
tranif1 pad_amuxbus_a (PAD, AMUXBUS_A, enable_pad_amuxbus_a);
tranif1 pad_amuxbus_b (PAD, AMUXBUS_B, enable_pad_amuxbus_b);
bufif1 pad_vddio_q (PAD, vddio_q, enable_pad_vddio_q);
bufif1 pad_vssio_q (PAD, vssio_q, enable_pad_vssio_q);
reg dis_err_msgs;
integer msg_count_pad,msg_count_pad1,msg_count_pad2,msg_count_pad3,msg_count_pad4,msg_count_pad5,msg_count_pad6,msg_count_pad7,msg_count_pad8,msg_count_pad9,msg_count_pad10,msg_count_pad11,msg_count_pad12;
initial
begin
dis_err_msgs = 1'b1;
msg_count_pad = 0;
msg_count_pad1 = 0;
msg_count_pad2 = 0;
msg_count_pad3 = 0;
msg_count_pad4 = 0;
msg_count_pad5 = 0;
msg_count_pad6 = 0;
msg_count_pad7 = 0;
msg_count_pad8 = 0;
msg_count_pad9 = 0;
msg_count_pad10 = 0;
msg_count_pad11 = 0;
msg_count_pad12 = 0;
`ifdef SKY130_FD_IO_TOP_GPIO_OVTV2_DIS_ERR_MSGS
`else
#1;
dis_err_msgs = 1'b0;
`endif
end
wire #100 error_enable_vddio = (ENABLE_VDDIO===0 && ENABLE_H===1);
event event_error_enable_vddio;
always @(error_enable_vddio)
begin
if (!dis_err_msgs)
begin
if (error_enable_vddio===1)
begin
msg_count_pad = msg_count_pad + 1;
->event_error_enable_vddio;
if (msg_count_pad <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpio_ovtv2 : Enable_h (= %b) and ENABLE_VDDIO (= %b) are complement of each \other. This is an illegal combination as ENABLE_VDDIO and ENABLE_H are the same input signals IN different power \domains %m", ENABLE_H, ENABLE_VDDIO, $stime);
end
else
if (msg_count_pad == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpio_ovtv2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vdda = ( vdda===1 && vddio_q !==1 && ENABLE_VDDA_H===1 );
event event_error_vdda;
always @(error_vdda)
begin
if (!dis_err_msgs)
begin
if (error_vdda===1)
begin
msg_count_pad1 = msg_count_pad1 + 1;
->event_error_vdda;
if (msg_count_pad1 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpio_ovtv2 : ENABLE_VDDA_H (= %b) cannot be 1 when vdda (= %b) and vddio_q (= %b) %m",ENABLE_VDDA_H, vdda,vddio_q,$stime);
end
else
if (msg_count_pad1 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpio_ovtv2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vdda2 = ( vdda===1 && vddio_q ===1 && vswitch !==1 && ENABLE_H===1 && hld_h_n_buf ===1 && vccd===1 && ANALOG_EN ===1 );
event event_error_vdda2;
always @(error_vdda2)
begin
if (!dis_err_msgs)
begin
if (error_vdda2===1)
begin
msg_count_pad2 = msg_count_pad2 + 1;
->event_error_vdda2;
if (msg_count_pad2 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpio_ovtv2 : ANALOG_EN (= %b) cannot be 1 when vdda (= %b) , vddio_q (= %b) , vswitch(= %b), ENABLE_H (= %b),hld_h_n_buf (= %b) and vccd (= %b) %m",ANALOG_EN,vdda,vddio_q,vswitch,ENABLE_H,hld_h_n_buf,vccd,$stime);
end
else
if (msg_count_pad2 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpio_ovtv2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vdda3 = ( vdda===1 && vddio_q ===1 && vswitch !==1 && ENABLE_H===1 && hld_h_n_buf ===1 && vccd !==1 );
event event_error_vdda3;
always @(error_vdda3)
begin
if (!dis_err_msgs)
begin
if (error_vdda3===1)
begin
msg_count_pad3 = msg_count_pad3 + 1;
->event_error_vdda3;
if (msg_count_pad3 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpio_ovtv2 : vccd (= %b) cannot be any value other than 1 when vdda (= %b) , vddio_q (= %b) , vswitch(= %b), ENABLE_H (= %b) and hld_h_n_buf (= %b) %m",vccd,vdda,vddio_q,vswitch,ENABLE_H,hld_h_n_buf,$stime);
end
else
if (msg_count_pad3 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpio_ovtv2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vswitch1 = (vdda !==1 && vddio_q !==1 && vswitch ===1 && (ENABLE_VSWITCH_H===1)) ;
event event_error_vswitch1;
always @(error_vswitch1)
begin
if (!dis_err_msgs)
begin
if (error_vswitch1===1)
begin
msg_count_pad4 = msg_count_pad4 + 1;
->event_error_vswitch1;
if (msg_count_pad4 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpio_ovtv2 : ENABLE_VSWITCH_H (= %b) cannot be 1 when vdda (= %b) , vddio_q (= %b) & vswitch(= %b) %m",ENABLE_VSWITCH_H,vdda,vddio_q,vswitch,$stime);
end
else
if (msg_count_pad4 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpio_ovtv2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vswitch2 = (vdda !==1 && vddio_q !==1 && vswitch ===1 && vccd===1 && ANALOG_EN===1);
event event_error_vswitch2;
always @(error_vswitch2)
begin
if (!dis_err_msgs)
begin
if (error_vswitch2===1)
begin
msg_count_pad5 = msg_count_pad5 + 1;
->event_error_vswitch2;
if (msg_count_pad5 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpio_ovtv2 : ANALOG_EN (= %b) cannot be 1 when vdda (= %b) , vddio_q (= %b) , vswitch(= %b) & vccd(= %b) %m",ANALOG_EN,vdda,vddio_q,vswitch,vccd,$stime);
end
else
if (msg_count_pad5 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpio_ovtv2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vswitch3 = (vdda ===1 && vddio_q !==1 && vswitch ===1 && ENABLE_VSWITCH_H===1);
event event_error_vswitch3;
always @(error_vswitch3)
begin
if (!dis_err_msgs)
begin
if (error_vswitch3===1)
begin
msg_count_pad6 = msg_count_pad6 + 1;
->event_error_vswitch3;
if (msg_count_pad6 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpio_ovtv2 : ENABLE_VSWITCH_H(= %b) cannot be 1 when vdda (= %b) , vddio_q (= %b) & vswitch(= %b) %m",ENABLE_VSWITCH_H,vdda,vddio_q,vswitch,$stime);
end
else
if (msg_count_pad6 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpio_ovtv2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vswitch4 = (vdda !==1 && vddio_q ===1 && vswitch ===1 && ENABLE_VSWITCH_H===1);
event event_error_vswitch4;
always @(error_vswitch4)
begin
if (!dis_err_msgs)
begin
if (error_vswitch4===1)
begin
msg_count_pad7 = msg_count_pad7 + 1;
->event_error_vswitch4;
if (msg_count_pad7 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpio_ovtv2 : ENABLE_VSWITCH_H(= %b) cannot be 1 when vdda (= %b) , vddio_q (= %b) & vswitch(= %b) %m",ENABLE_VSWITCH_H,vdda,vddio_q,vswitch,$stime);
end
else
if (msg_count_pad7 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpio_ovtv2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vswitch5 = (vdda !==1 && vddio_q ===1 && vswitch ===1 && ENABLE_H ===1 && hld_h_n_buf ===1 && vccd ===1 && ANALOG_EN===1);
event event_error_vswitch5;
always @(error_vswitch5)
begin
if (!dis_err_msgs)
begin
if (error_vswitch5===1)
begin
msg_count_pad8 = msg_count_pad8 + 1;
->event_error_vswitch5;
if (msg_count_pad8 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpio_ovtv2 : ANALOG_EN(= %b) cannot be 1 when vdda (= %b) , vddio_q (= %b) , vswitch(= %b),ENABLE_H (= %b),hld_h_n_buf (= %b) and vccd (= %b) %m",ANALOG_EN,vdda,vddio_q,vswitch,ENABLE_H,hld_h_n_buf,vccd,$stime);
end
else
if (msg_count_pad8 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpio_ovtv2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vddio_q1 = (vdda !==1 && vddio_q ===1 && vswitch !==1 && ENABLE_H ===1 && hld_h_n_buf ===1 && vccd!==1);
event event_error_vddio_q1;
always @(error_vddio_q1)
begin
if (!dis_err_msgs)
begin
if (error_vddio_q1===1)
begin
msg_count_pad9 = msg_count_pad9 + 1;
->event_error_vddio_q1;
if (msg_count_pad9 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpio_ovtv2 : vccd(= %b) cannot be any value other than 1 when vdda (= %b) , vddio_q (= %b) , vswitch(= %b),ENABLE_H (= %b) and hld_h_n_buf (= %b) %m",vccd,vdda,vddio_q,vswitch,ENABLE_H,hld_h_n_buf,$stime);
end
else
if (msg_count_pad9 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpio_ovtv2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vddio_q2 = (vdda !==1 && vddio_q ===1 && vswitch !==1 && ENABLE_H ===1 && hld_h_n_buf ===1 && vccd ===1 && ANALOG_EN===1);
event event_error_vddio_q2;
always @(error_vddio_q2)
begin
if (!dis_err_msgs)
begin
if (error_vddio_q2===1)
begin
msg_count_pad10 = msg_count_pad10 + 1;
->event_error_vddio_q2;
if (msg_count_pad10 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpio_ovtv2 : ANALOG_EN(= %b) cannot be 1 when vdda (= %b) , vddio_q (= %b) , vswitch(= %b),ENABLE_H (= %b) , hld_h_n_buf (= %b) && vccd (= %b) %m",ANALOG_EN, vdda,vddio_q,vswitch,ENABLE_H,hld_h_n_buf,vccd,$stime);
end
else
if (msg_count_pad10 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpio_ovtv2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_supply_good = ( vdda ===1 && vddio_q ===1 && vswitch ===1 && ENABLE_H ===1 && hld_h_n_buf ===1 && vccd ===1 && ANALOG_EN===1 && ENABLE_VSWITCH_H !==1 && ENABLE_VSWITCH_H !==0 );
event event_error_supply_good;
always @(error_supply_good)
begin
if (!dis_err_msgs)
begin
if (error_supply_good===1)
begin
msg_count_pad11 = msg_count_pad11 + 1;
->event_error_supply_good;
if (msg_count_pad11 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpio_ovtv2 : ENABLE_VSWITCH_H(= %b) should be either 1 or 0 when vdda (= %b) , vddio_q (= %b) , vswitch(= %b), ENABLE_H (= %b), hld_h_n_buf (= %b) ,vccd (= %b) and ANALOG_EN(= %b) %m",ENABLE_VSWITCH_H, vdda,vddio_q,vswitch,ENABLE_H,hld_h_n_buf,vccd,ANALOG_EN,$stime);
end
else
if (msg_count_pad11 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpio_ovtv2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vdda_vddioq_vswitch2 = ( vdda ===1 && vddio_q ===1 && vswitch ===1 && ENABLE_H ===1 && hld_h_n_buf ===1 && vccd ===1 && ANALOG_EN===1 && ENABLE_VDDA_H !==1 && ENABLE_VDDA_H !==0 );
event event_error_vdda_vddioq_vswitch2;
always @(error_vdda_vddioq_vswitch2)
begin
if (!dis_err_msgs)
begin
if (error_vdda_vddioq_vswitch2===1)
begin
msg_count_pad12 = msg_count_pad12 + 1;
->event_error_vdda_vddioq_vswitch2;
if (msg_count_pad12 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpio_ovtv2 : ENABLE_VDDA_H(= %b) should be either 1 or 0 when vdda (= %b) , vddio_q (= %b) , vswitch(= %b), ENABLE_H (= %b), hld_h_n_buf (= %b) ,vccd (= %b) and ANALOG_EN(= %b) %m",ENABLE_VDDA_H, vdda,vddio_q,vswitch,ENABLE_H,hld_h_n_buf,vccd,ANALOG_EN,$stime);
end
else
if (msg_count_pad12 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpio_ovtv2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
endmodule
|
Require Import TestSuite.admit.
(** [not tac] is equivalent to [fail tac "succeeds"] if [tac] succeeds, and is equivalent to [idtac] if [tac] fails *)
Tactic Notation "not" tactic3(tac) :=
(tryif tac then fail 0 tac "succeeds" else idtac); (* error if the tactic solved all goals *) [].
(** Test if a tactic succeeds, but always roll-back the results *)
Tactic Notation "test" tactic3(tac) := tryif not tac then fail 0 tac "fails" else idtac.
Goal Set.
Proof.
not fail.
not not idtac.
not fail 0.
(** Would be nice if we could get [not fail 1] to pass, maybe *)
not not admit.
not not test admit.
not progress test admit.
(* test grouping *)
not (not idtac; fail).
assert True.
all:not fail.
2:not fail.
all:admit.
Defined.
Goal Set.
Proof.
test idtac.
test try fail.
test admit.
test match goal with |- Set => idtac end.
test (idtac; match goal with |- Set => idtac end).
(* test grouping *)
first [ (test idtac; fail); fail 1 | idtac ].
try test fail.
try test test fail.
test test idtac.
test test admit.
Fail test fail.
test (idtac; []).
test (assert True; [|]).
(* would be nice, perhaps, if we could catch [fail 1] and not just [fail 0] this *)
try ((test fail); fail 1).
assert True.
all:test idtac.
all:test admit.
2:test admit.
all:admit.
Defined.
|
// Copyright (C) 2020-2021 The SymbiFlow Authors.
//
// Use of this source code is governed by a ISC-style
// license that can be found in the LICENSE file or at
// https://opensource.org/licenses/ISC
//
// SPDX-License-Identifier:ISC
// Basic DFF
module \$_DFF_P_ (D, C, Q);
input D;
input C;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dff _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C));
endmodule
// Async reset
module \$_DFF_PP0_ (D, C, R, Q);
input D;
input C;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dffr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R));
endmodule
// Async set
module \$_DFF_PP1_ (D, C, R, Q);
input D;
input C;
input R;
output Q;
dffs _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .S(R));
endmodule
// Async reset, enable
module \$_DFFE_PP0P_ (D, C, E, R, Q);
input D;
input C;
input E;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dffre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(R));
endmodule
// Async set, enable
module \$_DFFE_PP1P_ (D, C, E, R, Q);
input D;
input C;
input E;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dffse _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(S));
endmodule
// Async set & reset
module \$_DFFSR_PPP_ (D, C, R, S, Q);
input D;
input C;
input R;
input S;
output Q;
dffsr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R), .S(S));
endmodule
// Async set, reset & enable
module \$_DFFSRE_PPPP_ (D, Q, C, E, R, S);
input D;
input C;
input E;
input R;
input S;
output Q;
dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(S));
endmodule
// Latch with async set and reset
module \$_DLATCHSR_PPP_ (input E, S, R, D, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
latchsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(R), .S(S));
endmodule
// The following techmap operation are not performed right now
// as Negative edge FF are not legalized in synth_quicklogic for qlf_k6n10
// but in case we implement clock inversion in the future, the support is ready for it.
module \$_DFF_N_ (D, C, Q);
input D;
input C;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dff #(.IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C));
endmodule
module \$_DFF_NP0_ (D, C, R, Q);
input D;
input C;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dffr #(.IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R));
endmodule
module \$_DFF_NP1_ (D, C, R, Q);
input D;
input C;
input R;
output Q;
dffs #(.IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .S(R));
endmodule
module \$_DFFE_NP0P_ (D, C, E, R, Q);
input D;
input C;
input E;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dffre #(.IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(R));
endmodule
module \$_DFFE_NP1P_ (D, C, E, R, Q);
input D;
input C;
input E;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dffse #(.IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(S));
endmodule
module \$_DFFSR_NPP_ (D, C, R, S, Q);
input D;
input C;
input R;
input S;
output Q;
dffsr #(.IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R), .S(S));
endmodule
module \$_DFFSRE_PPPP_ (D, C, E, R, S, Q);
input D;
input C;
input E;
input R;
input S;
output Q;
dffsre #(.IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(S));
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: VC709_Gen3x4If128.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Top level module for RIFFA 2.2 reference design for the
// the Xilinx VC709 Development Board.
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`include "functions.vh"
`include "riffa.vh"
`include "ultrascale.vh"
`timescale 1ps / 1ps
module VC709_Gen3x4If128
#(// Number of RIFFA Channels
parameter C_NUM_CHNL = 1,
// Number of PCIe Lanes
parameter C_NUM_LANES = 4,
// Settings from Vivado IP Generator
parameter C_PCI_DATA_WIDTH = 128,
parameter C_MAX_PAYLOAD_BYTES = 256,
parameter C_LOG_NUM_TAGS = 5
)
(output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXP,
output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXN,
input [(C_NUM_LANES - 1) : 0] PCI_EXP_RXP,
input [(C_NUM_LANES - 1) : 0] PCI_EXP_RXN,
output [7:0] LED,
input PCIE_REFCLK_P,
input PCIE_REFCLK_N,
input PCIE_RESET_N
);
// Clocks, etc
wire user_lnk_up;
wire user_clk;
wire user_reset;
wire pcie_refclk;
wire pcie_reset_n;
// Interface: RQ (TXC)
wire s_axis_rq_tlast;
wire [C_PCI_DATA_WIDTH-1:0] s_axis_rq_tdata;
wire [`SIG_RQ_TUSER_W-1:0] s_axis_rq_tuser;
wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_rq_tkeep;
wire s_axis_rq_tready;
wire s_axis_rq_tvalid;
// Interface: RC (RXC)
wire [C_PCI_DATA_WIDTH-1:0] m_axis_rc_tdata;
wire [`SIG_RC_TUSER_W-1:0] m_axis_rc_tuser;
wire m_axis_rc_tlast;
wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_rc_tkeep;
wire m_axis_rc_tvalid;
wire m_axis_rc_tready;
// Interface: CQ (RXR)
wire [C_PCI_DATA_WIDTH-1:0] m_axis_cq_tdata;
wire [`SIG_CQ_TUSER_W-1:0] m_axis_cq_tuser;
wire m_axis_cq_tlast;
wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_cq_tkeep;
wire m_axis_cq_tvalid;
wire m_axis_cq_tready;
// Interface: CC (TXC)
wire [C_PCI_DATA_WIDTH-1:0] s_axis_cc_tdata;
wire [`SIG_CC_TUSER_W-1:0] s_axis_cc_tuser;
wire s_axis_cc_tlast;
wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_cc_tkeep;
wire s_axis_cc_tvalid;
wire s_axis_cc_tready;
// Configuration (CFG) Interface
wire [3:0] pcie_rq_seq_num;
wire pcie_rq_seq_num_vld;
wire [5:0] pcie_rq_tag;
wire pcie_rq_tag_vld;
wire pcie_cq_np_req;
wire [5:0] pcie_cq_np_req_count;
wire cfg_phy_link_down;
wire [3:0] cfg_negotiated_width; // CONFIG_LINK_WIDTH
wire [2:0] cfg_current_speed; // CONFIG_LINK_RATE
wire [2:0] cfg_max_payload; // CONFIG_MAX_PAYLOAD
wire [2:0] cfg_max_read_req; // CONFIG_MAX_READ_REQUEST
wire [7:0] cfg_function_status; // [2] = CONFIG_BUS_MASTER_ENABLE
wire [5:0] cfg_function_power_state; // Ignorable but not removable
wire [11:0] cfg_vf_status; // Ignorable but not removable
wire [17:0] cfg_vf_power_state; // Ignorable but not removable
wire [1:0] cfg_link_power_state; // Ignorable but not removable
// Error Reporting Interface
wire cfg_err_cor_out;
wire cfg_err_nonfatal_out;
wire cfg_err_fatal_out;
wire cfg_ltr_enable;
wire [5:0] cfg_ltssm_state;// TODO: Connect to LED's
wire [1:0] cfg_rcb_status;
wire [1:0] cfg_dpa_substate_change;
wire [1:0] cfg_obff_enable;
wire cfg_pl_status_change;
wire [1:0] cfg_tph_requester_enable;
wire [5:0] cfg_tph_st_mode;
wire [5:0] cfg_vf_tph_requester_enable;
wire [17:0] cfg_vf_tph_st_mode;
wire [7:0] cfg_fc_ph;
wire [11:0] cfg_fc_pd;
wire [7:0] cfg_fc_nph;
wire [11:0] cfg_fc_npd;
wire [7:0] cfg_fc_cplh;
wire [11:0] cfg_fc_cpld;
wire [2:0] cfg_fc_sel;
// Interrupt Interface Signals
wire [3:0] cfg_interrupt_int;
wire [1:0] cfg_interrupt_pending;
wire cfg_interrupt_sent;
wire [1:0] cfg_interrupt_msi_enable;
wire [5:0] cfg_interrupt_msi_vf_enable;
wire [5:0] cfg_interrupt_msi_mmenable;
wire cfg_interrupt_msi_mask_update;
wire [31:0] cfg_interrupt_msi_data;
wire [3:0] cfg_interrupt_msi_select;
wire [31:0] cfg_interrupt_msi_int;
wire [63:0] cfg_interrupt_msi_pending_status;
wire cfg_interrupt_msi_sent;
wire cfg_interrupt_msi_fail;
wire [2:0] cfg_interrupt_msi_attr;
wire cfg_interrupt_msi_tph_present;
wire [1:0] cfg_interrupt_msi_tph_type;
wire [8:0] cfg_interrupt_msi_tph_st_tag;
wire [2:0] cfg_interrupt_msi_function_number;
wire rst_out;
wire [C_NUM_CHNL-1:0] chnl_rx_clk;
wire [C_NUM_CHNL-1:0] chnl_rx;
wire [C_NUM_CHNL-1:0] chnl_rx_ack;
wire [C_NUM_CHNL-1:0] chnl_rx_last;
wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_rx_len;
wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_rx_off;
wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_rx_data;
wire [C_NUM_CHNL-1:0] chnl_rx_data_valid;
wire [C_NUM_CHNL-1:0] chnl_rx_data_ren;
wire [C_NUM_CHNL-1:0] chnl_tx_clk;
wire [C_NUM_CHNL-1:0] chnl_tx;
wire [C_NUM_CHNL-1:0] chnl_tx_ack;
wire [C_NUM_CHNL-1:0] chnl_tx_last;
wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_tx_len;
wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_tx_off;
wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_tx_data;
wire [C_NUM_CHNL-1:0] chnl_tx_data_valid;
wire [C_NUM_CHNL-1:0] chnl_tx_data_ren;
genvar chnl;
IBUF
#()
pci_reset_n_ibuf
(.O(pcie_reset_n),
.I(PCIE_RESET_N));
IBUFDS_GTE2
#()
refclk_ibuf
(.O(pcie_refclk),
.ODIV2(),
.I(PCIE_REFCLK_P),
.CEB(1'b0),
.IB(PCIE_REFCLK_N));
OBUF
#()
led_0_obuf
(.O(LED[0]),
.I(cfg_ltssm_state[0]));
OBUF
#()
led_1_obuf
(.O(LED[1]),
.I(cfg_ltssm_state[1]));
OBUF
#()
led_2_obuf
(.O(LED[2]),
.I(cfg_ltssm_state[2]));
OBUF
#()
led_3_obuf
(.O(LED[3]),
.I(cfg_ltssm_state[3]));
OBUF
#()
led_4_obuf
(.O(LED[4]),
.I(cfg_ltssm_state[4]));
OBUF
#()
led_5_obuf
(.O(LED[5]),
.I(cfg_ltssm_state[5]));
OBUF
#()
led_6_obuf
(.O(LED[6]),
.I(pcie_reset_n));
OBUF
#()
led_7_obuf
(.O(LED[7]),
.I(rst_out));
// Core Top Level Wrapper
PCIeGen3x4If128
#()
pcie3_7x_0_i
(//---------------------------------------------------------------------
// PCI Express (pci_exp) Interface
//---------------------------------------------------------------------
.pci_exp_txn ( PCI_EXP_TXN ),
.pci_exp_txp ( PCI_EXP_TXP ),
.pci_exp_rxn ( PCI_EXP_RXN ),
.pci_exp_rxp ( PCI_EXP_RXP ),
//---------------------------------------------------------------------
// AXI Interface
//---------------------------------------------------------------------
.user_clk ( user_clk ),
.user_reset ( user_reset ),
.user_lnk_up ( user_lnk_up ),
.user_app_rdy ( ),
.s_axis_rq_tlast ( s_axis_rq_tlast ),
.s_axis_rq_tdata ( s_axis_rq_tdata ),
.s_axis_rq_tuser ( s_axis_rq_tuser ),
.s_axis_rq_tkeep ( s_axis_rq_tkeep ),
.s_axis_rq_tready ( s_axis_rq_tready ),
.s_axis_rq_tvalid ( s_axis_rq_tvalid ),
.m_axis_rc_tdata ( m_axis_rc_tdata ),
.m_axis_rc_tuser ( m_axis_rc_tuser ),
.m_axis_rc_tlast ( m_axis_rc_tlast ),
.m_axis_rc_tkeep ( m_axis_rc_tkeep ),
.m_axis_rc_tvalid ( m_axis_rc_tvalid ),
.m_axis_rc_tready ( {22{m_axis_rc_tready}} ),
.m_axis_cq_tdata ( m_axis_cq_tdata ),
.m_axis_cq_tuser ( m_axis_cq_tuser ),
.m_axis_cq_tlast ( m_axis_cq_tlast ),
.m_axis_cq_tkeep ( m_axis_cq_tkeep ),
.m_axis_cq_tvalid ( m_axis_cq_tvalid ),
.m_axis_cq_tready ( {22{m_axis_cq_tready}} ),
.s_axis_cc_tdata ( s_axis_cc_tdata ),
.s_axis_cc_tuser ( s_axis_cc_tuser ),
.s_axis_cc_tlast ( s_axis_cc_tlast ),
.s_axis_cc_tkeep ( s_axis_cc_tkeep ),
.s_axis_cc_tvalid ( s_axis_cc_tvalid ),
.s_axis_cc_tready ( s_axis_cc_tready ),
//---------------------------------------------------------------------
// Configuration (CFG) Interface
//---------------------------------------------------------------------
.pcie_rq_seq_num ( pcie_rq_seq_num ),
.pcie_rq_seq_num_vld ( pcie_rq_seq_num_vld ),
.pcie_rq_tag ( pcie_rq_tag ),
.pcie_rq_tag_vld ( pcie_rq_tag_vld ),
.pcie_cq_np_req ( pcie_cq_np_req ),
.pcie_cq_np_req_count ( pcie_cq_np_req_count ),
.cfg_phy_link_down ( cfg_phy_link_down ),
.cfg_phy_link_status ( cfg_phy_link_status),
.cfg_negotiated_width ( cfg_negotiated_width ),
.cfg_current_speed ( cfg_current_speed ),
.cfg_max_payload ( cfg_max_payload ),
.cfg_max_read_req ( cfg_max_read_req ),
.cfg_function_status ( cfg_function_status ),
.cfg_function_power_state ( cfg_function_power_state ),
.cfg_vf_status ( cfg_vf_status ),
.cfg_vf_power_state ( cfg_vf_power_state ),
.cfg_link_power_state ( cfg_link_power_state ),
// Error Reporting Interface
.cfg_err_cor_out ( cfg_err_cor_out ),
.cfg_err_nonfatal_out ( cfg_err_nonfatal_out ),
.cfg_err_fatal_out ( cfg_err_fatal_out ),
.cfg_ltr_enable ( cfg_ltr_enable ),
.cfg_ltssm_state ( cfg_ltssm_state ),
.cfg_rcb_status ( cfg_rcb_status ),
.cfg_dpa_substate_change ( cfg_dpa_substate_change ),
.cfg_obff_enable ( cfg_obff_enable ),
.cfg_pl_status_change ( cfg_pl_status_change ),
.cfg_tph_requester_enable ( cfg_tph_requester_enable ),
.cfg_tph_st_mode ( cfg_tph_st_mode ),
.cfg_vf_tph_requester_enable ( cfg_vf_tph_requester_enable ),
.cfg_vf_tph_st_mode ( cfg_vf_tph_st_mode ),
.cfg_fc_ph ( cfg_fc_ph ),
.cfg_fc_pd ( cfg_fc_pd ),
.cfg_fc_nph ( cfg_fc_nph ),
.cfg_fc_npd ( cfg_fc_npd ),
.cfg_fc_cplh ( cfg_fc_cplh ),
.cfg_fc_cpld ( cfg_fc_cpld ),
.cfg_fc_sel ( cfg_fc_sel ),
//---------------------------------------------------------------------
// EP Only
//---------------------------------------------------------------------
// Interrupt Interface Signals
.cfg_interrupt_int ( cfg_interrupt_int ),
.cfg_interrupt_pending ( cfg_interrupt_pending ),
.cfg_interrupt_sent ( cfg_interrupt_sent ),
.cfg_interrupt_msi_enable ( cfg_interrupt_msi_enable ),
.cfg_interrupt_msi_vf_enable ( cfg_interrupt_msi_vf_enable ),
.cfg_interrupt_msi_mmenable ( cfg_interrupt_msi_mmenable ),
.cfg_interrupt_msi_mask_update ( cfg_interrupt_msi_mask_update ),
.cfg_interrupt_msi_data ( cfg_interrupt_msi_data ),
.cfg_interrupt_msi_select ( cfg_interrupt_msi_select ),
.cfg_interrupt_msi_int ( cfg_interrupt_msi_int ),
.cfg_interrupt_msi_pending_status ( cfg_interrupt_msi_pending_status ),
.cfg_interrupt_msi_sent ( cfg_interrupt_msi_sent ),
.cfg_interrupt_msi_fail ( cfg_interrupt_msi_fail ),
.cfg_interrupt_msi_attr ( cfg_interrupt_msi_attr ),
.cfg_interrupt_msi_tph_present ( cfg_interrupt_msi_tph_present ),
.cfg_interrupt_msi_tph_type ( cfg_interrupt_msi_tph_type ),
.cfg_interrupt_msi_tph_st_tag ( cfg_interrupt_msi_tph_st_tag ),
.cfg_interrupt_msi_function_number ( cfg_interrupt_msi_function_number ),
//---------------------------------------------------------------------
// System(SYS) Interface
//---------------------------------------------------------------------
.sys_clk (pcie_refclk),
.sys_reset (~pcie_reset_n));
riffa_wrapper_vc709
#(/*AUTOINSTPARAM*/
// Parameters
.C_LOG_NUM_TAGS (C_LOG_NUM_TAGS),
.C_NUM_CHNL (C_NUM_CHNL),
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_MAX_PAYLOAD_BYTES (C_MAX_PAYLOAD_BYTES))
riffa
(// Outputs
.M_AXIS_CQ_TREADY (m_axis_cq_tready),
.M_AXIS_RC_TREADY (m_axis_rc_tready),
.S_AXIS_CC_TVALID (s_axis_cc_tvalid),
.S_AXIS_CC_TLAST (s_axis_cc_tlast),
.S_AXIS_CC_TDATA (s_axis_cc_tdata[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_CC_TKEEP (s_axis_cc_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
.S_AXIS_CC_TUSER (s_axis_cc_tuser[`SIG_CC_TUSER_W-1:0]),
.S_AXIS_RQ_TVALID (s_axis_rq_tvalid),
.S_AXIS_RQ_TLAST (s_axis_rq_tlast),
.S_AXIS_RQ_TDATA (s_axis_rq_tdata[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_RQ_TKEEP (s_axis_rq_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
.S_AXIS_RQ_TUSER (s_axis_rq_tuser[`SIG_RQ_TUSER_W-1:0]),
.USER_CLK (user_clk),
.USER_RESET (user_reset),
.CFG_INTERRUPT_INT (cfg_interrupt_int[3:0]),
.CFG_INTERRUPT_PENDING (cfg_interrupt_pending[1:0]),
.CFG_INTERRUPT_MSI_SELECT (cfg_interrupt_msi_select[3:0]),
.CFG_INTERRUPT_MSI_INT (cfg_interrupt_msi_int[31:0]),
.CFG_INTERRUPT_MSI_PENDING_STATUS(cfg_interrupt_msi_pending_status[63:0]),
.CFG_INTERRUPT_MSI_ATTR (cfg_interrupt_msi_attr[2:0]),
.CFG_INTERRUPT_MSI_TPH_PRESENT (cfg_interrupt_msi_tph_present),
.CFG_INTERRUPT_MSI_TPH_TYPE (cfg_interrupt_msi_tph_type[1:0]),
.CFG_INTERRUPT_MSI_TPH_ST_TAG (cfg_interrupt_msi_tph_st_tag[8:0]),
.CFG_INTERRUPT_MSI_FUNCTION_NUMBER(cfg_interrupt_msi_function_number[2:0]),
.CFG_FC_SEL (cfg_fc_sel[2:0]),
.PCIE_CQ_NP_REQ (pcie_cq_np_req),
.RST_OUT (rst_out),
.CHNL_RX (chnl_rx[C_NUM_CHNL-1:0]),
.CHNL_RX_LAST (chnl_rx_last[C_NUM_CHNL-1:0]),
.CHNL_RX_LEN (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
.CHNL_RX_OFF (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
.CHNL_RX_DATA (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_RX_DATA_VALID (chnl_rx_data_valid[C_NUM_CHNL-1:0]),
.CHNL_TX_ACK (chnl_tx_ack[C_NUM_CHNL-1:0]),
.CHNL_TX_DATA_REN (chnl_tx_data_ren[C_NUM_CHNL-1:0]),
// Inputs
.M_AXIS_CQ_TVALID (m_axis_cq_tvalid),
.M_AXIS_CQ_TLAST (m_axis_cq_tlast),
.M_AXIS_CQ_TDATA (m_axis_cq_tdata[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_CQ_TKEEP (m_axis_cq_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
.M_AXIS_CQ_TUSER (m_axis_cq_tuser[`SIG_CQ_TUSER_W-1:0]),
.M_AXIS_RC_TVALID (m_axis_rc_tvalid),
.M_AXIS_RC_TLAST (m_axis_rc_tlast),
.M_AXIS_RC_TDATA (m_axis_rc_tdata[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_RC_TKEEP (m_axis_rc_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
.M_AXIS_RC_TUSER (m_axis_rc_tuser[`SIG_RC_TUSER_W-1:0]),
.S_AXIS_CC_TREADY (s_axis_cc_tready),
.S_AXIS_RQ_TREADY (s_axis_rq_tready),
.CFG_INTERRUPT_MSI_ENABLE (cfg_interrupt_msi_enable[1:0]),
.CFG_INTERRUPT_MSI_MASK_UPDATE (cfg_interrupt_msi_mask_update),
.CFG_INTERRUPT_MSI_DATA (cfg_interrupt_msi_data[31:0]),
.CFG_INTERRUPT_MSI_SENT (cfg_interrupt_msi_sent),
.CFG_INTERRUPT_MSI_FAIL (cfg_interrupt_msi_fail),
.CFG_FC_CPLH (cfg_fc_cplh[7:0]),
.CFG_FC_CPLD (cfg_fc_cpld[11:0]),
.CFG_NEGOTIATED_WIDTH (cfg_negotiated_width[3:0]),
.CFG_CURRENT_SPEED (cfg_current_speed[2:0]),
.CFG_MAX_PAYLOAD (cfg_max_payload[2:0]),
.CFG_MAX_READ_REQ (cfg_max_read_req[2:0]),
.CFG_FUNCTION_STATUS (cfg_function_status[7:0]),
.CFG_RCB_STATUS (cfg_rcb_status[1:0]),
.CHNL_RX_CLK (chnl_rx_clk[C_NUM_CHNL-1:0]),
.CHNL_RX_ACK (chnl_rx_ack[C_NUM_CHNL-1:0]),
.CHNL_RX_DATA_REN (chnl_rx_data_ren[C_NUM_CHNL-1:0]),
.CHNL_TX_CLK (chnl_tx_clk[C_NUM_CHNL-1:0]),
.CHNL_TX (chnl_tx[C_NUM_CHNL-1:0]),
.CHNL_TX_LAST (chnl_tx_last[C_NUM_CHNL-1:0]),
.CHNL_TX_LEN (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
.CHNL_TX_OFF (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
.CHNL_TX_DATA (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_TX_DATA_VALID (chnl_tx_data_valid[C_NUM_CHNL-1:0]));
generate
for (chnl = 0; chnl < C_NUM_CHNL; chnl = chnl + 1) begin : test_channels
chnl_tester
#(
.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)
)
module1
(.CLK(user_clk),
.RST(rst_out), // riffa_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[chnl]),
.CHNL_RX(chnl_rx[chnl]),
.CHNL_RX_ACK(chnl_rx_ack[chnl]),
.CHNL_RX_LAST(chnl_rx_last[chnl]),
.CHNL_RX_LEN(chnl_rx_len[32*chnl +:32]),
.CHNL_RX_OFF(chnl_rx_off[31*chnl +:31]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[chnl]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[chnl]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[chnl]),
.CHNL_TX(chnl_tx[chnl]),
.CHNL_TX_ACK(chnl_tx_ack[chnl]),
.CHNL_TX_LAST(chnl_tx_last[chnl]),
.CHNL_TX_LEN(chnl_tx_len[32*chnl +:32]),
.CHNL_TX_OFF(chnl_tx_off[31*chnl +:31]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[chnl]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[chnl])
);
end
endgenerate
endmodule
// Local Variables:
// verilog-library-directories:("." "../../../engine/" "ultrascale/rx/" "ultrascale/tx/" "classic/rx/" "classic/tx/" "../../../riffa/")
// End:
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
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// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
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// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
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// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
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// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_0_core_top_gtp_pipe_reset.v
// Version : 3.0
//------------------------------------------------------------------------------
// Filename : gtp_pipe_reset.v
// Description : GTP PIPE Reset Module for 7 Series Transceiver
// Version : 19.0
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//---------- PIPE Reset Module -------------------------------------------------
(* DowngradeIPIdentifiedWarnings = "yes" *)
module pcie_7x_0_core_top_gtp_pipe_reset #
(
//---------- Global ------------------------------------
parameter PCIE_SIM_SPEEDUP = "FALSE", // PCIe sim speedup
parameter PCIE_LANE = 1, // PCIe number of lanes
//---------- Local -------------------------------------
parameter CFG_WAIT_MAX = 6'd63, // Configuration wait max
parameter BYPASS_RXCDRLOCK = 1 // Bypass RXCDRLOCK
)
(
//---------- Input -------------------------------------
input RST_CLK,
input RST_RXUSRCLK,
input RST_DCLK,
input RST_RST_N,
input [PCIE_LANE-1:0] RST_DRP_DONE,
input [PCIE_LANE-1:0] RST_RXPMARESETDONE,
input RST_PLLLOCK,
input [PCIE_LANE-1:0] RST_RATE_IDLE,
input [PCIE_LANE-1:0] RST_RXCDRLOCK,
input RST_MMCM_LOCK,
input [PCIE_LANE-1:0] RST_RESETDONE,
input [PCIE_LANE-1:0] RST_PHYSTATUS,
input [PCIE_LANE-1:0] RST_TXSYNC_DONE,
//---------- Output ------------------------------------
output RST_CPLLRESET,
output RST_CPLLPD,
output reg RST_DRP_START,
output reg RST_DRP_X16,
output RST_RXUSRCLK_RESET,
output RST_DCLK_RESET,
output RST_GTRESET,
output RST_USERRDY,
output RST_TXSYNC_START,
output RST_IDLE,
output [ 4:0] RST_FSM
);
//---------- Input Register ----------------------------
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] drp_done_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rxpmaresetdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg plllock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rate_idle_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rxcdrlock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] resetdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] phystatus_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] txsync_done_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] drp_done_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rxpmaresetdone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg plllock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rate_idle_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rxcdrlock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] resetdone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] phystatus_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] txsync_done_reg2;
//---------- Internal Signal ---------------------------
reg [ 5:0] cfg_wait_cnt = 6'd0;
//---------- Output Register ---------------------------
reg pllreset = 1'd0;
reg pllpd = 1'd0;
reg rxusrclk_rst_reg1 = 1'd0;
reg rxusrclk_rst_reg2 = 1'd0;
reg dclk_rst_reg1 = 1'd0;
reg dclk_rst_reg2 = 1'd0;
reg gtreset = 1'd0;
reg userrdy = 1'd0;
reg [ 4:0] fsm = 5'h1;
//---------- FSM ---------------------------------------
localparam FSM_IDLE = 5'h0;
localparam FSM_CFG_WAIT = 5'h1;
localparam FSM_PLLRESET = 5'h2;
localparam FSM_DRP_X16_START = 5'h3;
localparam FSM_DRP_X16_DONE = 5'h4;
localparam FSM_PLLLOCK = 5'h5;
localparam FSM_GTRESET = 5'h6;
localparam FSM_RXPMARESETDONE_1 = 5'h7;
localparam FSM_RXPMARESETDONE_2 = 5'h8;
localparam FSM_DRP_X20_START = 5'h9;
localparam FSM_DRP_X20_DONE = 5'hA;
localparam FSM_MMCM_LOCK = 5'hB;
localparam FSM_RESETDONE = 5'hC;
localparam FSM_TXSYNC_START = 5'hD;
localparam FSM_TXSYNC_DONE = 5'hE;
//---------- Input FF ----------------------------------------------------------
always @ (posedge RST_CLK)
begin
if (!RST_RST_N)
begin
//---------- 1st Stage FF --------------------------
drp_done_reg1 <= {PCIE_LANE{1'd0}};
rxpmaresetdone_reg1 <= {PCIE_LANE{1'd0}};
plllock_reg1 <= 1'd0;
rate_idle_reg1 <= {PCIE_LANE{1'd0}};
rxcdrlock_reg1 <= {PCIE_LANE{1'd0}};
mmcm_lock_reg1 <= 1'd0;
resetdone_reg1 <= {PCIE_LANE{1'd0}};
phystatus_reg1 <= {PCIE_LANE{1'd0}};
txsync_done_reg1 <= {PCIE_LANE{1'd0}};
//---------- 2nd Stage FF --------------------------
drp_done_reg2 <= {PCIE_LANE{1'd0}};
rxpmaresetdone_reg2 <= {PCIE_LANE{1'd0}};
plllock_reg2 <= 1'd0;
rate_idle_reg2 <= {PCIE_LANE{1'd0}};
rxcdrlock_reg2 <= {PCIE_LANE{1'd0}};
mmcm_lock_reg2 <= 1'd0;
resetdone_reg2 <= {PCIE_LANE{1'd0}};
phystatus_reg2 <= {PCIE_LANE{1'd0}};
txsync_done_reg2 <= {PCIE_LANE{1'd0}};
end
else
begin
//---------- 1st Stage FF --------------------------
drp_done_reg1 <= RST_DRP_DONE;
rxpmaresetdone_reg1 <= RST_RXPMARESETDONE;
plllock_reg1 <= RST_PLLLOCK;
rate_idle_reg1 <= RST_RATE_IDLE;
rxcdrlock_reg1 <= RST_RXCDRLOCK;
mmcm_lock_reg1 <= RST_MMCM_LOCK;
resetdone_reg1 <= RST_RESETDONE;
phystatus_reg1 <= RST_PHYSTATUS;
txsync_done_reg1 <= RST_TXSYNC_DONE;
//---------- 2nd Stage FF --------------------------
drp_done_reg2 <= drp_done_reg1;
rxpmaresetdone_reg2 <= rxpmaresetdone_reg1;
plllock_reg2 <= plllock_reg1;
rate_idle_reg2 <= rate_idle_reg1;
rxcdrlock_reg2 <= rxcdrlock_reg1;
mmcm_lock_reg2 <= mmcm_lock_reg1;
resetdone_reg2 <= resetdone_reg1;
phystatus_reg2 <= phystatus_reg1;
txsync_done_reg2 <= txsync_done_reg1;
end
end
//---------- Configuration Reset Wait Counter ----------------------------------
always @ (posedge RST_CLK)
begin
if (!RST_RST_N)
cfg_wait_cnt <= 6'd0;
else
//---------- Increment Configuration Reset Wait Counter
if ((fsm == FSM_CFG_WAIT) && (cfg_wait_cnt < CFG_WAIT_MAX))
cfg_wait_cnt <= cfg_wait_cnt + 6'd1;
//---------- Hold Configuration Reset Wait Counter -
else if ((fsm == FSM_CFG_WAIT) && (cfg_wait_cnt == CFG_WAIT_MAX))
cfg_wait_cnt <= cfg_wait_cnt;
//---------- Reset Configuration Reset Wait Counter
else
cfg_wait_cnt <= 6'd0;
end
//---------- PIPE Reset FSM ----------------------------------------------------
always @ (posedge RST_CLK)
begin
if (!RST_RST_N)
begin
fsm <= FSM_CFG_WAIT;
pllreset <= 1'd0;
pllpd <= 1'd0;
gtreset <= 1'd0;
userrdy <= 1'd0;
end
else
begin
case (fsm)
//---------- Idle State ----------------------------
FSM_IDLE :
begin
if (!RST_RST_N)
begin
fsm <= FSM_CFG_WAIT;
pllreset <= 1'd0;
pllpd <= 1'd0;
gtreset <= 1'd0;
userrdy <= 1'd0;
end
else
begin
fsm <= FSM_IDLE;
pllreset <= pllreset;
pllpd <= pllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
end
//---------- Wait for Configuration Reset Delay ---
FSM_CFG_WAIT :
begin
fsm <= ((cfg_wait_cnt == CFG_WAIT_MAX) ? FSM_PLLRESET : FSM_CFG_WAIT);
pllreset <= pllreset;
pllpd <= pllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Hold PLL and GTP Channel in Reset ----
FSM_PLLRESET :
begin
fsm <= (((~plllock_reg2) && (&(~resetdone_reg2))) ? FSM_DRP_X16_START : FSM_PLLRESET);
pllreset <= 1'd1;
pllpd <= pllpd;
gtreset <= 1'd1;
userrdy <= userrdy;
end
//---------- Start DRP x16 -------------------------
FSM_DRP_X16_START :
begin
fsm <= &(~drp_done_reg2) ? FSM_DRP_X16_DONE : FSM_DRP_X16_START;
pllreset <= pllreset;
pllpd <= pllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Wait for DRP x16 Done -----------------
FSM_DRP_X16_DONE :
begin
fsm <= (&drp_done_reg2) ? FSM_PLLLOCK : FSM_DRP_X16_DONE;
pllreset <= pllreset;
pllpd <= pllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Wait for PLL Lock --------------------
FSM_PLLLOCK :
begin
fsm <= (plllock_reg2 ? FSM_GTRESET : FSM_PLLLOCK);
pllreset <= 1'd0;
pllpd <= pllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Release GTRESET -----------------------
FSM_GTRESET :
begin
fsm <= FSM_RXPMARESETDONE_1;
pllreset <= pllreset;
pllpd <= pllpd;
gtreset <= 1'b0;
userrdy <= userrdy;
end
//---------- Wait for RXPMARESETDONE Assertion -----
FSM_RXPMARESETDONE_1 :
begin
fsm <= (&rxpmaresetdone_reg2 || (PCIE_SIM_SPEEDUP == "TRUE")) ? FSM_RXPMARESETDONE_2 : FSM_RXPMARESETDONE_1;
pllreset <= pllreset;
pllpd <= pllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Wait for RXPMARESETDONE De-assertion --
FSM_RXPMARESETDONE_2 :
begin
fsm <= (&(~rxpmaresetdone_reg2) || (PCIE_SIM_SPEEDUP == "TRUE")) ? FSM_DRP_X20_START : FSM_RXPMARESETDONE_2;
pllreset <= pllreset;
pllpd <= pllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Start DRP x20 -------------------------
FSM_DRP_X20_START :
begin
fsm <= &(~drp_done_reg2) ? FSM_DRP_X20_DONE : FSM_DRP_X20_START;
pllreset <= pllreset;
pllpd <= pllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Wait for DRP x20 Done -----------------
FSM_DRP_X20_DONE :
begin
fsm <= (&drp_done_reg2) ? FSM_MMCM_LOCK : FSM_DRP_X20_DONE;
pllreset <= pllreset;
pllpd <= pllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Wait for MMCM and RX CDR Lock ---------
FSM_MMCM_LOCK :
begin
if (mmcm_lock_reg2 && (&rxcdrlock_reg2 || (BYPASS_RXCDRLOCK == 1)))
begin
fsm <= FSM_RESETDONE;
pllreset <= pllreset;
pllpd <= pllpd;
gtreset <= gtreset;
userrdy <= 1'd1;
end
else
begin
fsm <= FSM_MMCM_LOCK;
pllreset <= pllreset;
pllpd <= pllpd;
gtreset <= gtreset;
userrdy <= 1'd0;
end
end
//---------- Wait for [TX/RX]RESETDONE and PHYSTATUS
FSM_RESETDONE :
begin
fsm <= (&resetdone_reg2 && (&(~phystatus_reg2)) ? FSM_TXSYNC_START : FSM_RESETDONE);
pllreset <= pllreset;
pllpd <= pllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Start TX Sync -------------------------
FSM_TXSYNC_START :
begin
fsm <= (&(~txsync_done_reg2) ? FSM_TXSYNC_DONE : FSM_TXSYNC_START);
pllreset <= pllreset;
pllpd <= pllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Wait for TX Sync Done -----------------
FSM_TXSYNC_DONE :
begin
fsm <= (&txsync_done_reg2 ? FSM_IDLE : FSM_TXSYNC_DONE);
pllreset <= pllreset;
pllpd <= pllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Default State -------------------------
default :
begin
fsm <= FSM_CFG_WAIT;
pllreset <= 1'd0;
pllpd <= 1'd0;
gtreset <= 1'd0;
userrdy <= 1'd0;
end
endcase
end
end
//---------- RXUSRCLK Reset Synchronizer ---------------------------------------
always @ (posedge RST_RXUSRCLK)
begin
if (pllreset)
begin
rxusrclk_rst_reg1 <= 1'd1;
rxusrclk_rst_reg2 <= 1'd1;
end
else
begin
rxusrclk_rst_reg1 <= 1'd0;
rxusrclk_rst_reg2 <= rxusrclk_rst_reg1;
end
end
//---------- DCLK Reset Synchronizer -------------------------------------------
always @ (posedge RST_DCLK)
begin
if (fsm == FSM_CFG_WAIT)
begin
dclk_rst_reg1 <= 1'd1;
dclk_rst_reg2 <= dclk_rst_reg1;
end
else
begin
dclk_rst_reg1 <= 1'd0;
dclk_rst_reg2 <= dclk_rst_reg1;
end
end
//---------- PIPE Reset Output -------------------------------------------------
assign RST_CPLLRESET = pllreset;
assign RST_CPLLPD = pllpd;
assign RST_RXUSRCLK_RESET = rxusrclk_rst_reg2;
assign RST_DCLK_RESET = dclk_rst_reg2;
assign RST_GTRESET = gtreset;
assign RST_USERRDY = userrdy;
assign RST_TXSYNC_START = (fsm == FSM_TXSYNC_START);
assign RST_IDLE = (fsm == FSM_IDLE);
assign RST_FSM = fsm;
//--------------------------------------------------------------------------------------------------
// Register Output
//--------------------------------------------------------------------------------------------------
always @ (posedge RST_CLK)
begin
if (!RST_RST_N)
begin
RST_DRP_START <= 1'd0;
RST_DRP_X16 <= 1'd0;
end
else
begin
RST_DRP_START <= (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X20_START);
RST_DRP_X16 <= (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X16_DONE);
end
end
endmodule
|
module rd_port_9_to_1 (
port0_rd_en,
port0_rd_addr,
port1_rd_en,
port1_rd_addr,
port2_rd_en,
port2_rd_addr,
port3_rd_en,
port3_rd_addr,
port4_rd_en,
port4_rd_addr,
port5_rd_en,
port5_rd_addr,
port6_rd_en,
port6_rd_addr,
port7_rd_en,
port7_rd_addr,
port8_rd_en,
port8_rd_addr,
rd_addr
);
parameter WIDTH = 1;
input port0_rd_en;
input [WIDTH - 1:0] port0_rd_addr;
input port1_rd_en;
input [WIDTH - 1:0] port1_rd_addr;
input port2_rd_en;
input [WIDTH - 1:0] port2_rd_addr;
input port3_rd_en;
input [WIDTH - 1:0] port3_rd_addr;
input port4_rd_en;
input [WIDTH - 1:0] port4_rd_addr;
input port5_rd_en;
input [WIDTH - 1:0] port5_rd_addr;
input port6_rd_en;
input [WIDTH - 1:0] port6_rd_addr;
input port7_rd_en;
input [WIDTH - 1:0] port7_rd_addr;
input port8_rd_en;
input [WIDTH - 1:0] port8_rd_addr;
output [WIDTH - 1:0] rd_addr;
reg [WIDTH - 1:0] rd_addr;
always @ (
port0_rd_en or port1_rd_en or port2_rd_en or port3_rd_en or port4_rd_en or
port5_rd_en or port6_rd_en or port7_rd_en or port8_rd_en or
port0_rd_addr or port1_rd_addr or port2_rd_addr or port3_rd_addr or
port4_rd_addr or port5_rd_addr or port6_rd_addr or port7_rd_addr or port8_rd_addr)
begin
casex({port8_rd_en, port7_rd_en, port6_rd_en, port5_rd_en, port4_rd_en,
port3_rd_en, port2_rd_en, port1_rd_en, port0_rd_en})
9'b000000001: rd_addr <= port0_rd_addr;
9'b000000010: rd_addr <= port1_rd_addr;
9'b000000100: rd_addr <= port2_rd_addr;
9'b000001000: rd_addr <= port3_rd_addr;
9'b000010000: rd_addr <= port4_rd_addr;
9'b000100000: rd_addr <= port5_rd_addr;
9'b001000000: rd_addr <= port6_rd_addr;
9'b010000000: rd_addr <= port7_rd_addr;
9'b100000000: rd_addr <= port8_rd_addr;
default: rd_addr <= 6'bxxxxxx;
endcase
end
endmodule
|
/*
* MBus Copyright 2015 Regents of the University of Michigan
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`include "include/mbus_def.v"
module mbus_ext_int(
input CLKIN,
input RESETn,
input REQ_INT,
input BUS_BUSYn,
input BC_PWR_ON,
input LC_PWR_ON,
output reg EXTERNAL_INT_TO_WIRE,
output reg EXTERNAL_INT_TO_BUS,
input CLR_EXT_INT
);
wire RESETn_local = (RESETn & CLKIN);
wire RESETn_local2 = (RESETn & (~CLR_EXT_INT));
wire INT_BUSY = (REQ_INT & BUS_BUSYn);
always @ (posedge INT_BUSY or negedge RESETn_local)
begin
if (~RESETn_local)
EXTERNAL_INT_TO_WIRE <= 0;
else
begin
case ({BC_PWR_ON, LC_PWR_ON})
// Both in sleep
{`IO_HOLD, `IO_HOLD}: begin EXTERNAL_INT_TO_WIRE <= 1; end
// Both in sleep, BC is on, LC is off,
// only interrupt when the bus is not busy
{`IO_RELEASE, `IO_HOLD}: begin if (BUS_BUSYn) EXTERNAL_INT_TO_WIRE <= 1; end
// If both is on, doing nothing,
// BC is off, LC is on is a non-exist state
default: begin end
endcase
end
end
always @ (posedge INT_BUSY or negedge RESETn_local2)
begin
if (~RESETn_local2)
EXTERNAL_INT_TO_BUS <= 0;
else
begin
case ({BC_PWR_ON, LC_PWR_ON})
// Both in sleep
{`IO_HOLD, `IO_HOLD}: begin EXTERNAL_INT_TO_BUS <= 1; end
// Both in sleep, BC is on, LC is off,
// only interrupt when the bus is not busy
{`IO_RELEASE, `IO_HOLD}: begin if (BUS_BUSYn) EXTERNAL_INT_TO_BUS <= 1; end
// If both is on, doing nothing,
// BC is off, LC is on is a non-exist state
default: begin end
endcase
end
end
endmodule
|
(** * MoreCoq: More About Coq *)
Require Export Poly.
(** This chapter introduces several more Coq tactics that,
together, allow us to prove many more theorems about the
functional programs we are writing. *)
(* ###################################################### *)
(** * The [apply] Tactic *)
(** We often encounter situations where the goal to be proved is
exactly the same as some hypothesis in the context or some
previously proved lemma. *)
Theorem silly1 : forall (n m o p : nat),
n = m ->
[n;o] = [n;p] ->
[n;o] = [m;p].
Proof.
intros n m o p eq1 eq2.
rewrite <- eq1.
(* At this point, we could finish with
"[rewrite -> eq2. reflexivity.]" as we have
done several times above. But we can achieve the
same effect in a single step by using the
[apply] tactic instead: *)
apply eq2. Qed.
(** The [apply] tactic also works with _conditional_ hypotheses
and lemmas: if the statement being applied is an implication, then
the premises of this implication will be added to the list of
subgoals needing to be proved. *)
Theorem silly2 : forall (n m o p : nat),
n = m ->
(forall (q r : nat), q = r -> [q;o] = [r;p]) ->
[n;o] = [m;p].
Proof.
intros n m o p eq1 eq2.
apply eq2. apply eq1. Qed.
(** You may find it instructive to experiment with this proof
and see if there is a way to complete it using just [rewrite]
instead of [apply]. *)
(** Typically, when we use [apply H], the statement [H] will
begin with a [forall] binding some _universal variables_. When
Coq matches the current goal against the conclusion of [H], it
will try to find appropriate values for these variables. For
example, when we do [apply eq2] in the following proof, the
universal variable [q] in [eq2] gets instantiated with [n] and [r]
gets instantiated with [m]. *)
Theorem silly2a : forall (n m : nat),
(n,n) = (m,m) ->
(forall (q r : nat), (q,q) = (r,r) -> [q] = [r]) ->
[n] = [m].
Proof.
intros n m eq1 eq2.
apply eq2. apply eq1. Qed.
(** **** Exercise: 2 stars, optional (silly_ex) *)
(** Complete the following proof without using [simpl]. *)
Theorem silly_ex :
(forall n, evenb n = true -> oddb (S n) = true) ->
evenb 3 = true ->
oddb 4 = true.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** To use the [apply] tactic, the (conclusion of the) fact
being applied must match the goal _exactly_ -- for example, [apply]
will not work if the left and right sides of the equality are
swapped. *)
Theorem silly3_firsttry : forall (n : nat),
true = beq_nat n 5 ->
beq_nat (S (S n)) 7 = true.
Proof.
intros n H.
simpl.
(* Here we cannot use [apply] directly *)
Abort.
(** In this case we can use the [symmetry] tactic, which switches the
left and right sides of an equality in the goal. *)
Theorem silly3 : forall (n : nat),
true = beq_nat n 5 ->
beq_nat (S (S n)) 7 = true.
Proof.
intros n H.
symmetry.
simpl. (* Actually, this [simpl] is unnecessary, since
[apply] will do a [simpl] step first. *)
apply H. Qed.
(** **** Exercise: 3 stars (apply_exercise1) *)
(** Hint: you can use [apply] with previously defined lemmas, not
just hypotheses in the context. Remember that [SearchAbout] is
your friend. *)
Theorem rev_exercise1 : forall (l l' : list nat),
l = rev l' ->
l' = rev l.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star, optional (apply_rewrite) *)
(** Briefly explain the difference between the tactics [apply] and
[rewrite]. Are there situations where both can usefully be
applied?
(* FILL IN HERE *)
*)
(** [] *)
(* ###################################################### *)
(** * The [apply ... with ...] Tactic *)
(** The following silly example uses two rewrites in a row to
get from [[a,b]] to [[e,f]]. *)
Example trans_eq_example : forall (a b c d e f : nat),
[a;b] = [c;d] ->
[c;d] = [e;f] ->
[a;b] = [e;f].
Proof.
intros a b c d e f eq1 eq2.
rewrite -> eq1. rewrite -> eq2. reflexivity. Qed.
(** Since this is a common pattern, we might
abstract it out as a lemma recording once and for all
the fact that equality is transitive. *)
Theorem trans_eq : forall (X:Type) (n m o : X),
n = m -> m = o -> n = o.
Proof.
intros X n m o eq1 eq2. rewrite -> eq1. rewrite -> eq2.
reflexivity. Qed.
(** Now, we should be able to use [trans_eq] to
prove the above example. However, to do this we need
a slight refinement of the [apply] tactic. *)
Example trans_eq_example' : forall (a b c d e f : nat),
[a;b] = [c;d] ->
[c;d] = [e;f] ->
[a;b] = [e;f].
Proof.
intros a b c d e f eq1 eq2.
(* If we simply tell Coq [apply trans_eq] at this point,
it can tell (by matching the goal against the
conclusion of the lemma) that it should instantiate [X]
with [[nat]], [n] with [[a,b]], and [o] with [[e,f]].
However, the matching process doesn't determine an
instantiation for [m]: we have to supply one explicitly
by adding [with (m:=[c,d])] to the invocation of
[apply]. *)
apply trans_eq with (m:=[c;d]). apply eq1. apply eq2. Qed.
(** Actually, we usually don't have to include the name [m]
in the [with] clause; Coq is often smart enough to
figure out which instantiation we're giving. We could
instead write: [apply trans_eq with [c,d]]. *)
(** **** Exercise: 3 stars, optional (apply_with_exercise) *)
Example trans_eq_exercise : forall (n m o p : nat),
m = (minustwo o) ->
(n + p) = m ->
(n + p) = (minustwo o).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################### *)
(** * The [inversion] tactic *)
(** Recall the definition of natural numbers:
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
It is clear from this definition that every number has one of two
forms: either it is the constructor [O] or it is built by applying
the constructor [S] to another number. But there is more here than
meets the eye: implicit in the definition (and in our informal
understanding of how datatype declarations work in other
programming languages) are two other facts:
- The constructor [S] is _injective_. That is, the only way we can
have [S n = S m] is if [n = m].
- The constructors [O] and [S] are _disjoint_. That is, [O] is not
equal to [S n] for any [n]. *)
(** Similar principles apply to all inductively defined types: all
constructors are injective, and the values built from distinct
constructors are never equal. For lists, the [cons] constructor is
injective and [nil] is different from every non-empty list. For
booleans, [true] and [false] are unequal. (Since neither [true]
nor [false] take any arguments, their injectivity is not an issue.) *)
(** Coq provides a tactic called [inversion] that allows us to exploit
these principles in proofs.
The [inversion] tactic is used like this. Suppose [H] is a
hypothesis in the context (or a previously proven lemma) of the
form
c a1 a2 ... an = d b1 b2 ... bm
for some constructors [c] and [d] and arguments [a1 ... an] and
[b1 ... bm]. Then [inversion H] instructs Coq to "invert" this
equality to extract the information it contains about these terms:
- If [c] and [d] are the same constructor, then we know, by the
injectivity of this constructor, that [a1 = b1], [a2 = b2],
etc.; [inversion H] adds these facts to the context, and tries
to use them to rewrite the goal.
- If [c] and [d] are different constructors, then the hypothesis
[H] is contradictory. That is, a false assumption has crept
into the context, and this means that any goal whatsoever is
provable! In this case, [inversion H] marks the current goal as
completed and pops it off the goal stack. *)
(** The [inversion] tactic is probably easier to understand by
seeing it in action than from general descriptions like the above.
Below you will find example theorems that demonstrate the use of
[inversion] and exercises to test your understanding. *)
Theorem eq_add_S : forall (n m : nat),
S n = S m ->
n = m.
Proof.
intros n m eq. inversion eq. reflexivity. Qed.
Theorem silly4 : forall (n m : nat),
[n] = [m] ->
n = m.
Proof.
intros n o eq. inversion eq. reflexivity. Qed.
(** As a convenience, the [inversion] tactic can also
destruct equalities between complex values, binding
multiple variables as it goes. *)
Theorem silly5 : forall (n m o : nat),
[n;m] = [o;o] ->
[n] = [m].
Proof.
intros n m o eq. inversion eq. reflexivity. Qed.
(** **** Exercise: 1 star (sillyex1) *)
Example sillyex1 : forall (X : Type) (x y z : X) (l j : list X),
x :: y :: l = z :: j ->
y :: l = x :: j ->
x = y.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
Theorem silly6 : forall (n : nat),
S n = O ->
2 + 2 = 5.
Proof.
intros n contra. inversion contra. Qed.
Theorem silly7 : forall (n m : nat),
false = true ->
[n] = [m].
Proof.
intros n m contra. inversion contra. Qed.
(** **** Exercise: 1 star (sillyex2) *)
Example sillyex2 : forall (X : Type) (x y z : X) (l j : list X),
x :: y :: l = [] ->
y :: l = z :: j ->
x = z.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** While the injectivity of constructors allows us to reason
[forall (n m : nat), S n = S m -> n = m], the reverse direction of
the implication is an instance of a more general fact about
constructors and functions, which we will often find useful: *)
Theorem f_equal : forall (A B : Type) (f: A -> B) (x y: A),
x = y -> f x = f y.
Proof. intros A B f x y eq. rewrite eq. reflexivity. Qed.
(** Here's another illustration of [inversion]. This is a slightly
roundabout way of stating a fact that we have already proved
above. The extra equalities force us to do a little more
equational reasoning and exercise some of the tactics we've seen
recently. *)
Theorem length_snoc' : forall (X : Type) (v : X)
(l : list X) (n : nat),
length l = n ->
length (snoc l v) = S n.
Proof.
intros X v l. induction l as [| v' l'].
Case "l = []". intros n eq. rewrite <- eq. reflexivity.
Case "l = v' :: l'". intros n eq. simpl. destruct n as [| n'].
SCase "n = 0". inversion eq.
SCase "n = S n'".
apply f_equal. apply IHl'. inversion eq. reflexivity. Qed.
(** **** Exercise: 2 stars, optional (practice) *)
(** A couple more nontrivial but not-too-complicated proofs to work
together in class, or for you to work as exercises. They may
involve applying lemmas from earlier lectures or homeworks. *)
Theorem beq_nat_0_l : forall n,
beq_nat 0 n = true -> n = 0.
Proof.
(* FILL IN HERE *) Admitted.
Theorem beq_nat_0_r : forall n,
beq_nat n 0 = true -> n = 0.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################### *)
(** * Using Tactics on Hypotheses *)
(** By default, most tactics work on the goal formula and leave
the context unchanged. However, most tactics also have a variant
that performs a similar operation on a statement in the context.
For example, the tactic [simpl in H] performs simplification in
the hypothesis named [H] in the context. *)
Theorem S_inj : forall (n m : nat) (b : bool),
beq_nat (S n) (S m) = b ->
beq_nat n m = b.
Proof.
intros n m b H. simpl in H. apply H. Qed.
(** Similarly, the tactic [apply L in H] matches some
conditional statement [L] (of the form [L1 -> L2], say) against a
hypothesis [H] in the context. However, unlike ordinary
[apply] (which rewrites a goal matching [L2] into a subgoal [L1]),
[apply L in H] matches [H] against [L1] and, if successful,
replaces it with [L2].
In other words, [apply L in H] gives us a form of "forward
reasoning" -- from [L1 -> L2] and a hypothesis matching [L1], it
gives us a hypothesis matching [L2]. By contrast, [apply L] is
"backward reasoning" -- it says that if we know [L1->L2] and we
are trying to prove [L2], it suffices to prove [L1].
Here is a variant of a proof from above, using forward reasoning
throughout instead of backward reasoning. *)
Theorem silly3' : forall (n : nat),
(beq_nat n 5 = true -> beq_nat (S (S n)) 7 = true) ->
true = beq_nat n 5 ->
true = beq_nat (S (S n)) 7.
Proof.
intros n eq H.
symmetry in H. apply eq in H. symmetry in H.
apply H. Qed.
(** Forward reasoning starts from what is _given_ (premises,
previously proven theorems) and iteratively draws conclusions from
them until the goal is reached. Backward reasoning starts from
the _goal_, and iteratively reasons about what would imply the
goal, until premises or previously proven theorems are reached.
If you've seen informal proofs before (for example, in a math or
computer science class), they probably used forward reasoning. In
general, Coq tends to favor backward reasoning, but in some
situations the forward style can be easier to use or to think
about. *)
(** **** Exercise: 3 stars (plus_n_n_injective) *)
(** Practice using "in" variants in this exercise. *)
Theorem plus_n_n_injective : forall n m,
n + n = m + m ->
n = m.
Proof.
intros n. induction n as [| n'].
(* Hint: use the plus_n_Sm lemma *)
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################### *)
(** * Varying the Induction Hypothesis *)
(** Sometimes it is important to control the exact form of the
induction hypothesis when carrying out inductive proofs in Coq.
In particular, we need to be careful about which of the
assumptions we move (using [intros]) from the goal to the context
before invoking the [induction] tactic. For example, suppose
we want to show that the [double] function is injective -- i.e.,
that it always maps different arguments to different results:
Theorem double_injective: forall n m, double n = double m -> n = m.
The way we _start_ this proof is a little bit delicate: if we
begin it with
intros n. induction n.
]]
all is well. But if we begin it with
intros n m. induction n.
we get stuck in the middle of the inductive case... *)
Theorem double_injective_FAILED : forall n m,
double n = double m ->
n = m.
Proof.
intros n m. induction n as [| n'].
Case "n = O". simpl. intros eq. destruct m as [| m'].
SCase "m = O". reflexivity.
SCase "m = S m'". inversion eq.
Case "n = S n'". intros eq. destruct m as [| m'].
SCase "m = O". inversion eq.
SCase "m = S m'". apply f_equal.
(* Here we are stuck. The induction hypothesis, [IHn'], does
not give us [n' = m'] -- there is an extra [S] in the
way -- so the goal is not provable. *)
Abort.
(** What went wrong? *)
(** The problem is that, at the point we invoke the induction
hypothesis, we have already introduced [m] into the context --
intuitively, we have told Coq, "Let's consider some particular
[n] and [m]..." and we now have to prove that, if [double n =
double m] for _this particular_ [n] and [m], then [n = m].
The next tactic, [induction n] says to Coq: We are going to show
the goal by induction on [n]. That is, we are going to prove that
the proposition
- [P n] = "if [double n = double m], then [n = m]"
holds for all [n] by showing
- [P O]
(i.e., "if [double O = double m] then [O = m]")
- [P n -> P (S n)]
(i.e., "if [double n = double m] then [n = m]" implies "if
[double (S n) = double m] then [S n = m]").
If we look closely at the second statement, it is saying something
rather strange: it says that, for a _particular_ [m], if we know
- "if [double n = double m] then [n = m]"
then we can prove
- "if [double (S n) = double m] then [S n = m]".
To see why this is strange, let's think of a particular [m] --
say, [5]. The statement is then saying that, if we know
- [Q] = "if [double n = 10] then [n = 5]"
then we can prove
- [R] = "if [double (S n) = 10] then [S n = 5]".
But knowing [Q] doesn't give us any help with proving [R]! (If we
tried to prove [R] from [Q], we would say something like "Suppose
[double (S n) = 10]..." but then we'd be stuck: knowing that
[double (S n)] is [10] tells us nothing about whether [double n]
is [10], so [Q] is useless at this point.) *)
(** To summarize: Trying to carry out this proof by induction on [n]
when [m] is already in the context doesn't work because we are
trying to prove a relation involving _every_ [n] but just a
_single_ [m]. *)
(** The good proof of [double_injective] leaves [m] in the goal
statement at the point where the [induction] tactic is invoked on
[n]: *)
Theorem double_injective : forall n m,
double n = double m ->
n = m.
Proof.
intros n. induction n as [| n'].
Case "n = O". simpl. intros m eq. destruct m as [| m'].
SCase "m = O". reflexivity.
SCase "m = S m'". inversion eq.
Case "n = S n'".
(* Notice that both the goal and the induction
hypothesis have changed: the goal asks us to prove
something more general (i.e., to prove the
statement for _every_ [m]), but the IH is
correspondingly more flexible, allowing us to
choose any [m] we like when we apply the IH. *)
intros m eq.
(* Now we choose a particular [m] and introduce the
assumption that [double n = double m]. Since we
are doing a case analysis on [n], we need a case
analysis on [m] to keep the two "in sync." *)
destruct m as [| m'].
SCase "m = O".
(* The 0 case is trivial *)
inversion eq.
SCase "m = S m'".
apply f_equal.
(* At this point, since we are in the second
branch of the [destruct m], the [m'] mentioned
in the context at this point is actually the
predecessor of the one we started out talking
about. Since we are also in the [S] branch of
the induction, this is perfect: if we
instantiate the generic [m] in the IH with the
[m'] that we are talking about right now (this
instantiation is performed automatically by
[apply]), then [IHn'] gives us exactly what we
need to finish the proof. *)
apply IHn'. inversion eq. reflexivity. Qed.
(** What this teaches us is that we need to be careful about using
induction to try to prove something too specific: If we're proving
a property of [n] and [m] by induction on [n], we may need to
leave [m] generic. *)
(** The proof of this theorem has to be treated similarly: *)
(** **** Exercise: 2 stars (beq_nat_true) *)
Theorem beq_nat_true : forall n m,
beq_nat n m = true -> n = m.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, advanced (beq_nat_true_informal) *)
(** Give a careful informal proof of [beq_nat_true], being as explicit
as possible about quantifiers. *)
(* FILL IN HERE *)
(** [] *)
(** The strategy of doing fewer [intros] before an [induction] doesn't
always work directly; sometimes a little _rearrangement_ of
quantified variables is needed. Suppose, for example, that we
wanted to prove [double_injective] by induction on [m] instead of
[n]. *)
Theorem double_injective_take2_FAILED : forall n m,
double n = double m ->
n = m.
Proof.
intros n m. induction m as [| m'].
Case "m = O". simpl. intros eq. destruct n as [| n'].
SCase "n = O". reflexivity.
SCase "n = S n'". inversion eq.
Case "m = S m'". intros eq. destruct n as [| n'].
SCase "n = O". inversion eq.
SCase "n = S n'". apply f_equal.
(* Stuck again here, just like before. *)
Abort.
(** The problem is that, to do induction on [m], we must first
introduce [n]. (If we simply say [induction m] without
introducing anything first, Coq will automatically introduce
[n] for us!) *)
(** What can we do about this? One possibility is to rewrite the
statement of the lemma so that [m] is quantified before [n]. This
will work, but it's not nice: We don't want to have to mangle the
statements of lemmas to fit the needs of a particular strategy for
proving them -- we want to state them in the most clear and
natural way. *)
(** What we can do instead is to first introduce all the
quantified variables and then _re-generalize_ one or more of
them, taking them out of the context and putting them back at
the beginning of the goal. The [generalize dependent] tactic
does this. *)
Theorem double_injective_take2 : forall n m,
double n = double m ->
n = m.
Proof.
intros n m.
(* [n] and [m] are both in the context *)
generalize dependent n.
(* Now [n] is back in the goal and we can do induction on
[m] and get a sufficiently general IH. *)
induction m as [| m'].
Case "m = O". simpl. intros n eq. destruct n as [| n'].
SCase "n = O". reflexivity.
SCase "n = S n'". inversion eq.
Case "m = S m'". intros n eq. destruct n as [| n'].
SCase "n = O". inversion eq.
SCase "n = S n'". apply f_equal.
apply IHm'. inversion eq. reflexivity. Qed.
(** Let's look at an informal proof of this theorem. Note that
the proposition we prove by induction leaves [n] quantified,
corresponding to the use of generalize dependent in our formal
proof.
_Theorem_: For any nats [n] and [m], if [double n = double m], then
[n = m].
_Proof_: Let [m] be a [nat]. We prove by induction on [m] that, for
any [n], if [double n = double m] then [n = m].
- First, suppose [m = 0], and suppose [n] is a number such
that [double n = double m]. We must show that [n = 0].
Since [m = 0], by the definition of [double] we have [double n =
0]. There are two cases to consider for [n]. If [n = 0] we are
done, since this is what we wanted to show. Otherwise, if [n = S
n'] for some [n'], we derive a contradiction: by the definition of
[double] we would have [double n = S (S (double n'))], but this
contradicts the assumption that [double n = 0].
- Otherwise, suppose [m = S m'] and that [n] is again a number such
that [double n = double m]. We must show that [n = S m'], with
the induction hypothesis that for every number [s], if [double s =
double m'] then [s = m'].
By the fact that [m = S m'] and the definition of [double], we
have [double n = S (S (double m'))]. There are two cases to
consider for [n].
If [n = 0], then by definition [double n = 0], a contradiction.
Thus, we may assume that [n = S n'] for some [n'], and again by
the definition of [double] we have [S (S (double n')) = S (S
(double m'))], which implies by inversion that [double n' = double
m'].
Instantiating the induction hypothesis with [n'] thus allows us to
conclude that [n' = m'], and it follows immediately that [S n' = S
m']. Since [S n' = n] and [S m' = m], this is just what we wanted
to show. [] *)
(** **** Exercise: 3 stars (gen_dep_practice) *)
(** Prove this by induction on [l]. *)
Theorem index_after_last: forall (n : nat) (X : Type) (l : list X),
length l = n ->
index n l = None.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, advanced, optional (index_after_last_informal) *)
(** Write an informal proof corresponding to your Coq proof
of [index_after_last]:
_Theorem_: For all sets [X], lists [l : list X], and numbers
[n], if [length l = n] then [index n l = None].
_Proof_:
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 3 stars, optional (gen_dep_practice_more) *)
(** Prove this by induction on [l]. *)
Theorem length_snoc''' : forall (n : nat) (X : Type)
(v : X) (l : list X),
length l = n ->
length (snoc l v) = S n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, optional (app_length_cons) *)
(** Prove this by induction on [l1], without using [app_length]. *)
Theorem app_length_cons : forall (X : Type) (l1 l2 : list X)
(x : X) (n : nat),
length (l1 ++ (x :: l2)) = n ->
S (length (l1 ++ l2)) = n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 4 stars, optional (app_length_twice) *)
(** Prove this by induction on [l], without using app_length. *)
Theorem app_length_twice : forall (X:Type) (n:nat) (l:list X),
length l = n ->
length (l ++ l) = n + n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################### *)
(** * Using [destruct] on Compound Expressions *)
(** We have seen many examples where the [destruct] tactic is
used to perform case analysis of the value of some variable. But
sometimes we need to reason by cases on the result of some
_expression_. We can also do this with [destruct].
Here are some examples: *)
Definition sillyfun (n : nat) : bool :=
if beq_nat n 3 then false
else if beq_nat n 5 then false
else false.
Theorem sillyfun_false : forall (n : nat),
sillyfun n = false.
Proof.
intros n. unfold sillyfun.
destruct (beq_nat n 3).
Case "beq_nat n 3 = true". reflexivity.
Case "beq_nat n 3 = false". destruct (beq_nat n 5).
SCase "beq_nat n 5 = true". reflexivity.
SCase "beq_nat n 5 = false". reflexivity. Qed.
(** After unfolding [sillyfun] in the above proof, we find that
we are stuck on [if (beq_nat n 3) then ... else ...]. Well,
either [n] is equal to [3] or it isn't, so we use [destruct
(beq_nat n 3)] to let us reason about the two cases.
In general, the [destruct] tactic can be used to perform case
analysis of the results of arbitrary computations. If [e] is an
expression whose type is some inductively defined type [T], then,
for each constructor [c] of [T], [destruct e] generates a subgoal
in which all occurrences of [e] (in the goal and in the context)
are replaced by [c].
*)
(** **** Exercise: 1 star (override_shadow) *)
Theorem override_shadow : forall (X:Type) x1 x2 k1 k2 (f : nat->X),
(override (override f k1 x2) k1 x1) k2 = (override f k1 x1) k2.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, optional (combine_split) *)
(** Complete the proof below *)
Theorem combine_split : forall X Y (l : list (X * Y)) l1 l2,
split l = (l1, l2) ->
combine l1 l2 = l.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** Sometimes, doing a [destruct] on a compound expression (a
non-variable) will erase information we need to complete a proof. *)
(** For example, suppose
we define a function [sillyfun1] like this: *)
Definition sillyfun1 (n : nat) : bool :=
if beq_nat n 3 then true
else if beq_nat n 5 then true
else false.
(** And suppose that we want to convince Coq of the rather
obvious observation that [sillyfun1 n] yields [true] only when [n]
is odd. By analogy with the proofs we did with [sillyfun] above,
it is natural to start the proof like this: *)
Theorem sillyfun1_odd_FAILED : forall (n : nat),
sillyfun1 n = true ->
oddb n = true.
Proof.
intros n eq. unfold sillyfun1 in eq.
destruct (beq_nat n 3).
(* stuck... *)
Abort.
(** We get stuck at this point because the context does not
contain enough information to prove the goal! The problem is that
the substitution peformed by [destruct] is too brutal -- it threw
away every occurrence of [beq_nat n 3], but we need to keep some
memory of this expression and how it was destructed, because we
need to be able to reason that since, in this branch of the case
analysis, [beq_nat n 3 = true], it must be that [n = 3], from
which it follows that [n] is odd.
What we would really like is to substitute away all existing
occurences of [beq_nat n 3], but at the same time add an equation
to the context that records which case we are in. The [eqn:]
qualifier allows us to introduce such an equation (with whatever
name we choose). *)
Theorem sillyfun1_odd : forall (n : nat),
sillyfun1 n = true ->
oddb n = true.
Proof.
intros n eq. unfold sillyfun1 in eq.
destruct (beq_nat n 3) eqn:Heqe3.
(* Now we have the same state as at the point where we got stuck
above, except that the context contains an extra equality
assumption, which is exactly what we need to make progress. *)
Case "e3 = true". apply beq_nat_true in Heqe3.
rewrite -> Heqe3. reflexivity.
Case "e3 = false".
(* When we come to the second equality test in the body of the
function we are reasoning about, we can use [eqn:] again in the
same way, allow us to finish the proof. *)
destruct (beq_nat n 5) eqn:Heqe5.
SCase "e5 = true".
apply beq_nat_true in Heqe5.
rewrite -> Heqe5. reflexivity.
SCase "e5 = false". inversion eq. Qed.
(** **** Exercise: 2 stars (destruct_eqn_practice) *)
Theorem bool_fn_applied_thrice :
forall (f : bool -> bool) (b : bool),
f (f (f b)) = f b.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars (override_same) *)
Theorem override_same : forall (X:Type) x1 k1 k2 (f : nat->X),
f k1 = x1 ->
(override f k1 x1) k2 = f k2.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ################################################################## *)
(** * Review *)
(** We've now seen a bunch of Coq's fundamental tactics. We'll
introduce a few more as we go along through the coming lectures,
and later in the course we'll introduce some more powerful
_automation_ tactics that make Coq do more of the low-level work
in many cases. But basically we've got what we need to get work
done.
Here are the ones we've seen:
- [intros]:
move hypotheses/variables from goal to context
- [reflexivity]:
finish the proof (when the goal looks like [e = e])
- [apply]:
prove goal using a hypothesis, lemma, or constructor
- [apply... in H]:
apply a hypothesis, lemma, or constructor to a hypothesis in
the context (forward reasoning)
- [apply... with...]:
explicitly specify values for variables that cannot be
determined by pattern matching
- [simpl]:
simplify computations in the goal
- [simpl in H]:
... or a hypothesis
- [rewrite]:
use an equality hypothesis (or lemma) to rewrite the goal
- [rewrite ... in H]:
... or a hypothesis
- [symmetry]:
changes a goal of the form [t=u] into [u=t]
- [symmetry in H]:
changes a hypothesis of the form [t=u] into [u=t]
- [unfold]:
replace a defined constant by its right-hand side in the goal
- [unfold... in H]:
... or a hypothesis
- [destruct... as...]:
case analysis on values of inductively defined types
- [destruct... eqn:...]:
specify the name of an equation to be added to the context,
recording the result of the case analysis
- [induction... as...]:
induction on values of inductively defined types
- [inversion]:
reason by injectivity and distinctness of constructors
- [assert (e) as H]:
introduce a "local lemma" [e] and call it [H]
- [generalize dependent x]:
move the variable [x] (and anything else that depends on it)
from the context back to an explicit hypothesis in the goal
formula
*)
(* ###################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 3 stars (beq_nat_sym) *)
Theorem beq_nat_sym : forall (n m : nat),
beq_nat n m = beq_nat m n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, advanced, optional (beq_nat_sym_informal) *)
(** Give an informal proof of this lemma that corresponds to your
formal proof above:
Theorem: For any [nat]s [n] [m], [beq_nat n m = beq_nat m n].
Proof:
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 3 stars, optional (beq_nat_trans) *)
Theorem beq_nat_trans : forall n m p,
beq_nat n m = true ->
beq_nat m p = true ->
beq_nat n p = true.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, advanced (split_combine) *)
(** We have just proven that for all lists of pairs, [combine] is the
inverse of [split]. How would you formalize the statement that
[split] is the inverse of [combine]?
Complete the definition of [split_combine_statement] below with a
property that states that [split] is the inverse of
[combine]. Then, prove that the property holds. (Be sure to leave
your induction hypothesis general by not doing [intros] on more
things than necessary. Hint: what property do you need of [l1]
and [l2] for [split] [combine l1 l2 = (l1,l2)] to be true?) *)
Definition split_combine_statement : Prop :=
(* FILL IN HERE *) admit.
Theorem split_combine : split_combine_statement.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars (override_permute) *)
Theorem override_permute : forall (X:Type) x1 x2 k1 k2 k3 (f : nat->X),
beq_nat k2 k1 = false ->
(override (override f k2 x2) k1 x1) k3 = (override (override f k1 x1) k2 x2) k3.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, advanced (filter_exercise) *)
(** This one is a bit challenging. Pay attention to the form of your IH. *)
Theorem filter_exercise : forall (X : Type) (test : X -> bool)
(x : X) (l lf : list X),
filter test l = x :: lf ->
test x = true.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 4 stars, advanced (forall_exists_challenge) *)
(** Define two recursive [Fixpoints], [forallb] and [existsb]. The
first checks whether every element in a list satisfies a given
predicate:
forallb oddb [1;3;5;7;9] = true
forallb negb [false;false] = true
forallb evenb [0;2;4;5] = false
forallb (beq_nat 5) [] = true
The second checks whether there exists an element in the list that
satisfies a given predicate:
existsb (beq_nat 5) [0;2;3;6] = false
existsb (andb true) [true;true;false] = true
existsb oddb [1;0;0;0;0;3] = true
existsb evenb [] = false
Next, define a _nonrecursive_ version of [existsb] -- call it
[existsb'] -- using [forallb] and [negb].
Prove that [existsb'] and [existsb] have the same behavior.
*)
(* FILL IN HERE *)
(** [] *)
(* $Date: 2013-07-17 16:19:11 -0400 (Wed, 17 Jul 2013) $ *)
|
// ====================================================================
// Radio-86RK FPGA REPLICA
//
// Copyright (C) 2011 Dmitry Tselikov
//
// This core is distributed under modified BSD license.
// For complete licensing information see LICENSE.TXT.
// --------------------------------------------------------------------
//
// An open implementation of Radio-86RK home computer
//
// Author: Dmitry Tselikov http://bashkiria-2m.narod.ru/
//
// Design File: radio86rk.v
//
// Top level design file.
// --------------------------------------------------------------------
// Ported to "Aeon Lite" by Dmitriy Schapotschkin aka ILoveSpeccy
// http://www.speccyland.net '2015
module radio86rk(
input clk50,
inout [15:0] SRAM_DQ, // SRAM Data bus 16 Bits
output [17:0] SRAM_ADDR, // SRAM Address bus 18 Bits
output SRAM_UB_N, // SRAM High-byte Data Mask
output SRAM_LB_N, // SRAM Low-byte Data Mask
output SRAM_WE_N, // SRAM Write Enable
output SRAM_CE_N, // SRAM Chip Enable
output SRAM_OE_N, // SRAM Output Enable
output SOUND_L,
output SOUND_R,
output VGA_HS,
output VGA_VS,
output [3:0] VGA_R,
output [3:0] VGA_G,
output [3:0] VGA_B,
input PS2_CLK,
input PS2_DAT,
input SD_DAT, // SD Card Data (MISO)
output SD_DAT3, // SD Card Data 3 (CSn)
output SD_CMD, // SD Card Command Signal (MOSI)
output SD_CLK // SD Card Clock (SCK)
);
reg startup;
reg tapein = 1'b0;
wire hdla;
wire cpurst;
wire videomode;
wire[7:0] ppa1_o;
wire[7:0] ppa1_a;
wire[7:0] ppa1_b;
wire[7:0] ppa1_c;
//////////////////// RESET ////////////////////
reg[3:0] reset_cnt;
reg reset_n;
wire reset = ~reset_n;
always @(posedge clk50) begin
// if (KEY[0] && reset_cnt==4'd14)
if (!cpurst && reset_cnt==4'd14)
reset_n <= 1'b1;
else begin
reset_n <= 1'b0;
reset_cnt <= reset_cnt+4'd1;
end
end
//////////////////// MEM ////////////////////
wire sram_msb = 0;
wire[7:0] mem_o = sram_msb ? SRAM_DQ[15:8] : SRAM_DQ[7:0];
wire[7:0] rom_o;
assign SRAM_DQ[7:0] = SRAM_WE_N| sram_msb ? 8'bZZZZZZZZ : cpu_o;
assign SRAM_DQ[15:8] = 8'bZZZZZZZZ; // SRAM_WE_N|~sram_msb ? 8'bZZZZZZZZ : cpu_o;
assign SRAM_ADDR = vid_rd ? {3'b000,vid_addr[14:0]} : {3'b000,addrbus[14:0]};
assign SRAM_UB_N = vid_rd ? 1'b0 : ~sram_msb;
assign SRAM_LB_N = vid_rd ? 1'b0 : sram_msb;
assign SRAM_WE_N = vid_rd ? 1'b1 : cpu_wr_n|addrbus[15]|hlda;
assign SRAM_OE_N = ~(vid_rd|cpu_rd);
assign SRAM_CE_N = 0;
biossd rom(.clka(clk50), .addra({addrbus[11]|startup,addrbus[10:0]}), .douta(rom_o));
//////////////////// CPU ////////////////////
wire[15:0] addrbus;
wire[7:0] cpu_o;
wire cpu_sync;
wire cpu_rd;
wire cpu_wr_n;
wire cpu_int;
wire cpu_inta_n;
wire inte;
reg[7:0] cpu_i;
always @(*)
casex (addrbus[15:13])
3'b0xx: cpu_i = startup ? rom_o : mem_o;
3'b100: cpu_i = ppa1_o;
3'b101: cpu_i = sd_o;
3'b110: cpu_i = crt_o;
3'b111: cpu_i = rom_o;
endcase
wire ppa1_we_n = addrbus[15:13]!=3'b100|cpu_wr_n;
wire ppa2_we_n = addrbus[15:13]!=3'b101|cpu_wr_n;
wire crt_we_n = addrbus[15:13]!=3'b110|cpu_wr_n;
wire crt_rd_n = addrbus[15:13]!=3'b110|~cpu_rd;
wire dma_we_n = addrbus[15:13]!=3'b111|cpu_wr_n;
reg cpu_flag;
reg[10:0] cpu_cnt;
wire cpu_ce = cpu_ce2;
wire cpu_ce2 = cpu_flag^cpu_cnt[10];
always @(posedge clk50) begin
cpu_cnt <= cpu_cnt + 11'd41;
cpu_flag <= cpu_flag^cpu_ce2;
startup <= reset|(startup&~addrbus[15]);
end
k580wm80a CPU(.clk(clk50), .ce(cpu_ce & hlda==0), .reset(reset),
.idata(cpu_i), .addr(addrbus), .sync(cpu_sync), .rd(cpu_rd), .wr_n(cpu_wr_n),
.intr(cpu_int), .inta_n(cpu_inta_n), .odata(cpu_o), .inte_o(inte));
//////////////////// VIDEO ////////////////////
wire[7:0] crt_o;
wire[3:0] vid_line;
wire[6:0] vid_char;
wire[15:0] vid_addr;
wire[3:0] dma_dack;
wire[7:0] dma_o;
wire[1:0] vid_lattr;
wire[1:0] vid_gattr;
wire vid_cce,vid_drq,vid_irq;
wire vid_lten,vid_vsp,vid_rvv,vid_hilight;
wire dma_owe_n,dma_ord_n,dma_oiowe_n,dma_oiord_n;
wire vid_rd = ~dma_oiord_n;
k580wt57 dma(.clk(clk50), .ce(vid_cce), .reset(reset),
.iaddr(addrbus[3:0]), .idata(cpu_o), .drq({1'b0,vid_drq,2'b00}), .iwe_n(dma_we_n), .ird_n(1'b1),
.hlda(hlda), .hrq(hlda), .dack(dma_dack), .odata(dma_o), .oaddr(vid_addr),
.owe_n(dma_owe_n), .ord_n(dma_ord_n), .oiowe_n(dma_oiowe_n), .oiord_n(dma_oiord_n) );
k580wg75 crt(.clk(clk50), .ce(vid_cce),
.iaddr(addrbus[0]), .idata(cpu_o), .iwe_n(crt_we_n), .ird_n(crt_rd_n),
.vrtc(VGA_VS), .hrtc(VGA_HS), .dack(dma_dack[2]), .ichar(mem_o), .drq(vid_drq), .irq(vid_irq),
.odata(crt_o), .line(vid_line), .ochar(vid_char), .lten(vid_lten), .vsp(vid_vsp),
.rvv(vid_rvv), .hilight(vid_hilight), .lattr(vid_lattr), .gattr(vid_gattr) );
rk_video vid(.clk50mhz(clk50), .hr(VGA_HS), .vr(VGA_VS), .cce(vid_cce),
.r(VGA_R), .g(VGA_G), .b(VGA_B), .line(vid_line), .ichar(vid_char),
.vsp(vid_vsp), .lten(vid_lten), .rvv(vid_rvv), .videomode(videomode) );
//////////////////// KBD ////////////////////
wire[7:0] kbd_o;
wire[2:0] kbd_shift;
rk_kbd kbd(.clk(clk50), .reset(reset), .ps2_clk(PS2_CLK), .ps2_dat(PS2_DAT),
.addr(~ppa1_a), .odata(kbd_o), .cpurst(cpurst), .videomode(videomode), .shift(kbd_shift));
//////////////////// SYS PPA ////////////////////
k580ww55 ppa1(.clk(clk50), .reset(reset), .addr(addrbus[1:0]), .we_n(ppa1_we_n),
.idata(cpu_o), .odata(ppa1_o), .ipa(ppa1_a), .opa(ppa1_a),
.ipb(~kbd_o), .opb(ppa1_b), .ipc({~kbd_shift,tapein,ppa1_c[3:0]}), .opc(ppa1_c));
//////////////////// SOUND ////////////////////
assign SOUND_L = ppa1_c[0]^inte;
assign SOUND_R = ppa1_c[0]^inte;
//////////////////// SD CARD ////////////////////
reg sdcs;
reg sdclk;
reg sdcmd;
reg[6:0] sddata;
wire[7:0] sd_o = {sddata, SD_DAT};
assign SD_DAT3 = ~sdcs;
assign SD_CMD = sdcmd;
assign SD_CLK = sdclk;
always @(posedge clk50 or posedge reset) begin
if (reset) begin
sdcs <= 1'b0;
sdclk <= 1'b0;
sdcmd <= 1'h1;
end else begin
if (addrbus[0]==1'b0 && ~ppa2_we_n) sdcs <= cpu_o[0];
if (addrbus[0]==1'b1 && ~ppa2_we_n) begin
if (sdclk) sddata <= {sddata[5:0],SD_DAT};
sdcmd <= cpu_o[7];
sdclk <= 1'b0;
end
if (cpu_rd) sdclk <= 1'b1;
end
end
endmodule
|
// Copyright 2012 by Alastair M. Robinson
//
// This file is part of Minimig
//
// Minimig is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3 of the License, or
// (at your option) any later version.
//
// Minimig is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//
// A minimal implementation of the Akiko C2P register - 16-bit for now, worry about 32-bit
// width later.
//
// -- AMR --
//
// 2012-03-23 - initial version
module akiko
(
input clk,
input clk7_en.
input reset,
input [23:1] address_in,
input [15:0] data_in,
output [15:0] data_out,
input rd,
input sel_akiko // $B8xxxx
);
//0xb80038 - just the one register, but 32-bits wide.
reg [127:0] shifter;
reg [6:0] wrpointer;
wire sel;
// address decoding
assign sel = sel_akiko && address_in[7:1]==8'b0011_100; // 0x38
always @(posedge clk)
if (clk7_en) begin
if (reset)
wrpointer <= 0;
else if (!rd && sel) // write to C2P reg...
begin
case(wrpointer)
0 : shifter[127:112] <= data_in[15:0];
1 : shifter[111:96] <= data_in[15:0];
2 : shifter[95:80] <= data_in[15:0];
3 : shifter[79:64] <= data_in[15:0];
4 : shifter[63:48] <= data_in[15:0];
5 : shifter[47:32] <= data_in[15:0];
6 : shifter[31:16] <= data_in[15:0];
7 : shifter[15:0] <= data_in[15:0];
endcase
wrpointer <= wrpointer + 1;
end
else if (rd && sel) // read from C2P reg
begin
shifter[127:0] <= {shifter[126:0],1'b0};
wrpointer <= 0;
end
end
assign data_out[15:0] = sel_akiko && rd ? {shifter[127],shifter[119],shifter[111],shifter[103],shifter[95],shifter[87],
shifter[79],shifter[71],shifter[63],shifter[55],shifter[47],shifter[39],shifter[31],
shifter[23],shifter[15],shifter[7]} : 16'b0 ;
endmodule
|
(* -*- coding: utf-8 -*- *)
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2015 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(** * Typeclass-based relations, tactics and standard instances
This is the basic theory needed to formalize morphisms and setoids.
Author: Matthieu Sozeau
Institution: LRI, CNRS UMR 8623 - University Paris Sud
*)
Require Export Coq.Classes.Init.
Require Import Coq.Program.Basics.
Require Import Coq.Program.Tactics.
Generalizable Variables A B C D R S T U l eqA eqB eqC eqD.
Set Universe Polymorphism.
Definition crelation (A : Type) := A -> A -> Type.
Definition arrow (A B : Type) := A -> B.
Definition flip {A B C : Type} (f : A -> B -> C) := fun x y => f y x.
Definition iffT (A B : Type) := ((A -> B) * (B -> A))%type.
(** We allow to unfold the [crelation] definition while doing morphism search. *)
Section Defs.
Context {A : Type}.
(** We rebind crelational properties in separate classes to be able to overload each proof. *)
Class Reflexive (R : crelation A) :=
reflexivity : forall x : A, R x x.
Definition complement (R : crelation A) : crelation A :=
fun x y => R x y -> False.
(** Opaque for proof-search. *)
Typeclasses Opaque complement iffT.
(** These are convertible. *)
Lemma complement_inverse R : complement (flip R) = flip (complement R).
Proof. reflexivity. Qed.
Class Irreflexive (R : crelation A) :=
irreflexivity : Reflexive (complement R).
Class Symmetric (R : crelation A) :=
symmetry : forall {x y}, R x y -> R y x.
Class Asymmetric (R : crelation A) :=
asymmetry : forall {x y}, R x y -> (complement R y x : Type).
Class Transitive (R : crelation A) :=
transitivity : forall {x y z}, R x y -> R y z -> R x z.
(** Various combinations of reflexivity, symmetry and transitivity. *)
(** A [PreOrder] is both Reflexive and Transitive. *)
Class PreOrder (R : crelation A) := {
PreOrder_Reflexive :> Reflexive R | 2 ;
PreOrder_Transitive :> Transitive R | 2 }.
(** A [StrictOrder] is both Irreflexive and Transitive. *)
Class StrictOrder (R : crelation A) := {
StrictOrder_Irreflexive :> Irreflexive R ;
StrictOrder_Transitive :> Transitive R }.
(** By definition, a strict order is also asymmetric *)
Global Instance StrictOrder_Asymmetric `(StrictOrder R) : Asymmetric R.
Proof. firstorder. Qed.
(** A partial equivalence crelation is Symmetric and Transitive. *)
Class PER (R : crelation A) := {
PER_Symmetric :> Symmetric R | 3 ;
PER_Transitive :> Transitive R | 3 }.
(** Equivalence crelations. *)
Class Equivalence (R : crelation A) := {
Equivalence_Reflexive :> Reflexive R ;
Equivalence_Symmetric :> Symmetric R ;
Equivalence_Transitive :> Transitive R }.
(** An Equivalence is a PER plus reflexivity. *)
Global Instance Equivalence_PER {R} `(Equivalence R) : PER R | 10 :=
{ PER_Symmetric := Equivalence_Symmetric ;
PER_Transitive := Equivalence_Transitive }.
(** We can now define antisymmetry w.r.t. an equivalence crelation on the carrier. *)
Class Antisymmetric eqA `{equ : Equivalence eqA} (R : crelation A) :=
antisymmetry : forall {x y}, R x y -> R y x -> eqA x y.
Class subrelation (R R' : crelation A) :=
is_subrelation : forall {x y}, R x y -> R' x y.
(** Any symmetric crelation is equal to its inverse. *)
Lemma subrelation_symmetric R `(Symmetric R) : subrelation (flip R) R.
Proof. hnf. intros x y H'. red in H'. apply symmetry. assumption. Qed.
Section flip.
Lemma flip_Reflexive `{Reflexive R} : Reflexive (flip R).
Proof. tauto. Qed.
Program Definition flip_Irreflexive `(Irreflexive R) : Irreflexive (flip R) :=
irreflexivity (R:=R).
Program Definition flip_Symmetric `(Symmetric R) : Symmetric (flip R) :=
fun x y H => symmetry (R:=R) H.
Program Definition flip_Asymmetric `(Asymmetric R) : Asymmetric (flip R) :=
fun x y H H' => asymmetry (R:=R) H H'.
Program Definition flip_Transitive `(Transitive R) : Transitive (flip R) :=
fun x y z H H' => transitivity (R:=R) H' H.
Program Definition flip_Antisymmetric `(Antisymmetric eqA R) :
Antisymmetric eqA (flip R).
Proof. firstorder. Qed.
(** Inversing the larger structures *)
Lemma flip_PreOrder `(PreOrder R) : PreOrder (flip R).
Proof. firstorder. Qed.
Lemma flip_StrictOrder `(StrictOrder R) : StrictOrder (flip R).
Proof. firstorder. Qed.
Lemma flip_PER `(PER R) : PER (flip R).
Proof. firstorder. Qed.
Lemma flip_Equivalence `(Equivalence R) : Equivalence (flip R).
Proof. firstorder. Qed.
End flip.
Section complement.
Definition complement_Irreflexive `(Reflexive R)
: Irreflexive (complement R).
Proof. firstorder. Qed.
Definition complement_Symmetric `(Symmetric R) : Symmetric (complement R).
Proof. firstorder. Qed.
End complement.
(** Rewrite crelation on a given support: declares a crelation as a rewrite
crelation for use by the generalized rewriting tactic.
It helps choosing if a rewrite should be handled
by the generalized or the regular rewriting tactic using leibniz equality.
Users can declare an [RewriteRelation A RA] anywhere to declare default
crelations. This is also done automatically by the [Declare Relation A RA]
commands. *)
Class RewriteRelation (RA : crelation A).
(** Any [Equivalence] declared in the context is automatically considered
a rewrite crelation. *)
Global Instance equivalence_rewrite_crelation `(Equivalence eqA) : RewriteRelation eqA.
(** Leibniz equality. *)
Section Leibniz.
Global Instance eq_Reflexive : Reflexive (@eq A) := @eq_refl A.
Global Instance eq_Symmetric : Symmetric (@eq A) := @eq_sym A.
Global Instance eq_Transitive : Transitive (@eq A) := @eq_trans A.
(** Leibinz equality [eq] is an equivalence crelation.
The instance has low priority as it is always applicable
if only the type is constrained. *)
Global Program Instance eq_equivalence : Equivalence (@eq A) | 10.
End Leibniz.
End Defs.
(** Default rewrite crelations handled by [setoid_rewrite]. *)
Instance: RewriteRelation impl.
Instance: RewriteRelation iff.
(** Hints to drive the typeclass resolution avoiding loops
due to the use of full unification. *)
Hint Extern 1 (Reflexive (complement _)) => class_apply @irreflexivity : typeclass_instances.
Hint Extern 3 (Symmetric (complement _)) => class_apply complement_Symmetric : typeclass_instances.
Hint Extern 3 (Irreflexive (complement _)) => class_apply complement_Irreflexive : typeclass_instances.
Hint Extern 3 (Reflexive (flip _)) => apply flip_Reflexive : typeclass_instances.
Hint Extern 3 (Irreflexive (flip _)) => class_apply flip_Irreflexive : typeclass_instances.
Hint Extern 3 (Symmetric (flip _)) => class_apply flip_Symmetric : typeclass_instances.
Hint Extern 3 (Asymmetric (flip _)) => class_apply flip_Asymmetric : typeclass_instances.
Hint Extern 3 (Antisymmetric (flip _)) => class_apply flip_Antisymmetric : typeclass_instances.
Hint Extern 3 (Transitive (flip _)) => class_apply flip_Transitive : typeclass_instances.
Hint Extern 3 (StrictOrder (flip _)) => class_apply flip_StrictOrder : typeclass_instances.
Hint Extern 3 (PreOrder (flip _)) => class_apply flip_PreOrder : typeclass_instances.
Hint Extern 4 (subrelation (flip _) _) =>
class_apply @subrelation_symmetric : typeclass_instances.
Hint Resolve irreflexivity : ord.
Unset Implicit Arguments.
(** A HintDb for crelations. *)
Ltac solve_crelation :=
match goal with
| [ |- ?R ?x ?x ] => reflexivity
| [ H : ?R ?x ?y |- ?R ?y ?x ] => symmetry ; exact H
end.
Hint Extern 4 => solve_crelation : crelations.
(** We can already dualize all these properties. *)
(** * Standard instances. *)
Ltac reduce_hyp H :=
match type of H with
| context [ _ <-> _ ] => fail 1
| _ => red in H ; try reduce_hyp H
end.
Ltac reduce_goal :=
match goal with
| [ |- _ <-> _ ] => fail 1
| _ => red ; intros ; try reduce_goal
end.
Tactic Notation "reduce" "in" hyp(Hid) := reduce_hyp Hid.
Ltac reduce := reduce_goal.
Tactic Notation "apply" "*" constr(t) :=
first [ refine t | refine (t _) | refine (t _ _) | refine (t _ _ _) | refine (t _ _ _ _) |
refine (t _ _ _ _ _) | refine (t _ _ _ _ _ _) | refine (t _ _ _ _ _ _ _) ].
Ltac simpl_crelation :=
unfold flip, impl, arrow ; try reduce ; program_simpl ;
try ( solve [ dintuition ]).
Local Obligation Tactic := simpl_crelation.
(** Logical implication. *)
Program Instance impl_Reflexive : Reflexive impl.
Program Instance impl_Transitive : Transitive impl.
(** Logical equivalence. *)
Instance iff_Reflexive : Reflexive iff := iff_refl.
Instance iff_Symmetric : Symmetric iff := iff_sym.
Instance iff_Transitive : Transitive iff := iff_trans.
(** Logical equivalence [iff] is an equivalence crelation. *)
Program Instance iff_equivalence : Equivalence iff.
Program Instance arrow_Reflexive : Reflexive arrow.
Program Instance arrow_Transitive : Transitive arrow.
Instance iffT_Reflexive : Reflexive iffT.
Proof. firstorder. Defined.
Instance iffT_Symmetric : Symmetric iffT.
Proof. firstorder. Defined.
Instance iffT_Transitive : Transitive iffT.
Proof. firstorder. Defined.
(** We now develop a generalization of results on crelations for arbitrary predicates.
The resulting theory can be applied to homogeneous binary crelations but also to
arbitrary n-ary predicates. *)
Local Open Scope list_scope.
(** A compact representation of non-dependent arities, with the codomain singled-out. *)
(** We define the various operations which define the algebra on binary crelations *)
Section Binary.
Context {A : Type}.
Definition relation_equivalence : crelation (crelation A) :=
fun R R' => forall x y, iffT (R x y) (R' x y).
Global Instance: RewriteRelation relation_equivalence.
Definition relation_conjunction (R : crelation A) (R' : crelation A) : crelation A :=
fun x y => prod (R x y) (R' x y).
Definition relation_disjunction (R : crelation A) (R' : crelation A) : crelation A :=
fun x y => sum (R x y) (R' x y).
(** Relation equivalence is an equivalence, and subrelation defines a partial order. *)
Set Automatic Introduction.
Global Instance relation_equivalence_equivalence :
Equivalence relation_equivalence.
Proof. split; red; unfold relation_equivalence, iffT. firstorder.
firstorder.
intros. specialize (X x0 y0). specialize (X0 x0 y0). firstorder.
Qed.
Global Instance relation_implication_preorder : PreOrder (@subrelation A).
Proof. firstorder. Qed.
(** *** Partial Order.
A partial order is a preorder which is additionally antisymmetric.
We give an equivalent definition, up-to an equivalence crelation
on the carrier. *)
Class PartialOrder eqA `{equ : Equivalence A eqA} R `{preo : PreOrder A R} :=
partial_order_equivalence : relation_equivalence eqA (relation_conjunction R (flip R)).
(** The equivalence proof is sufficient for proving that [R] must be a
morphism for equivalence (see Morphisms). It is also sufficient to
show that [R] is antisymmetric w.r.t. [eqA] *)
Global Instance partial_order_antisym `(PartialOrder eqA R) : ! Antisymmetric A eqA R.
Proof with auto.
reduce_goal.
apply H. firstorder.
Qed.
Lemma PartialOrder_inverse `(PartialOrder eqA R) : PartialOrder eqA (flip R).
Proof. unfold flip; constructor; unfold flip. intros. apply H. apply symmetry. apply X.
unfold relation_conjunction. intros [H1 H2]. apply H. constructor; assumption. Qed.
End Binary.
Hint Extern 3 (PartialOrder (flip _)) => class_apply PartialOrder_inverse : typeclass_instances.
(** The partial order defined by subrelation and crelation equivalence. *)
(* Program Instance subrelation_partial_order : *)
(* ! PartialOrder (crelation A) relation_equivalence subrelation. *)
(* Obligation Tactic := idtac. *)
(* Next Obligation. *)
(* Proof. *)
(* intros x. refine (fun x => x). *)
(* Qed. *)
Typeclasses Opaque relation_equivalence.
|
`timescale 1 ns / 1 ps
`default_nettype none
`define WIDTH 16
module SB_RAM2048x2(
output [1:0] RDATA,
input RCLK, RCLKE, RE,
input [10:0] RADDR,
input WCLK, WCLKE, WE,
input [10:0] WADDR,
input [1:0] MASK, WDATA
);
parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
wire [15:0] rd;
SB_RAM40_4K #(
.WRITE_MODE(3),
.READ_MODE(3),
.INIT_0(INIT_0),
.INIT_1(INIT_1),
.INIT_2(INIT_2),
.INIT_3(INIT_3),
.INIT_4(INIT_4),
.INIT_5(INIT_5),
.INIT_6(INIT_6),
.INIT_7(INIT_7),
.INIT_8(INIT_8),
.INIT_9(INIT_9),
.INIT_A(INIT_A),
.INIT_B(INIT_B),
.INIT_C(INIT_C),
.INIT_D(INIT_D),
.INIT_E(INIT_E),
.INIT_F(INIT_F)
) _ram (
.RDATA(rd),
.RADDR(RADDR),
.RCLK(RCLK), .RCLKE(RCLKE), .RE(RE),
.WCLK(WCLK), .WCLKE(WCLKE), .WE(WE),
.WADDR(WADDR),
.MASK(16'h0000), .WDATA({4'b0, WDATA[1], 7'b0, WDATA[0], 3'b0}));
assign RDATA[0] = rd[3];
assign RDATA[1] = rd[11];
endmodule
module top(input oscillator,
output D1,
output D2,
output D3,
output D4,
output D5,
output D6,
output D7,
output D8,
output TXD, // UART TX
input RXD, // UART RX
output CTS, // UART CTS - PIO3_05
input RTS, // UART RTS - PIO3_06
output PIOS_00, // Flash SCK
input PIOS_01, // Flash MISO
output PIOS_02, // Flash MOSI
output PIOS_03, // Flash CS
output PIO1_18, // IR TXD
input PIO1_19, // IR RXD
output PIO1_20, // IR SD
inout PORTA0,
inout PORTA1,
inout PORTA2,
inout PORTA3,
inout PORTA4,
inout PORTA5,
inout PORTA6,
inout PORTA7,
inout PORTA8,
inout PORTA9,
inout PORTA10,
inout PORTA11,
inout PORTA12,
inout PORTA13,
inout PORTA14,
inout PORTA15,
inout PORTB0,
inout PORTB1,
inout PORTB2,
inout PORTB3,
inout PORTB4,
inout PORTB5,
inout PORTB6,
inout PORTB7,
inout PORTB8,
inout PORTB9,
inout PORTB10,
inout PORTB11,
inout PORTB12,
inout PORTB13,
inout PORTB14,
inout PORTB15,
inout PORTC0,
inout PORTC1,
inout PORTC2,
inout PORTC3,
inout PORTC4,
inout PORTC5,
inout PORTC6,
inout PORTC7,
inout PORTC8,
inout PORTC9,
inout PORTC10,
inout PORTC11,
inout PORTC12,
inout PORTC13,
inout PORTC14,
inout PORTC15,
input resetq,
);
wire clk;
SB_PLL40_CORE #(.FEEDBACK_PATH("SIMPLE"),
.PLLOUT_SELECT("GENCLK"),
.DIVR(4'b0000),
.DIVF(7'd2),
.DIVQ(3'b000),
.FILTER_RANGE(3'b001),
) uut (
.REFERENCECLK(oscillator),
.PLLOUTCORE(clk),
//.PLLOUTGLOBAL(clk),
//.LOCK(D5),
.RESETB(1'b1),
.BYPASS(1'b0)
);
wire io_rd, io_wr;
wire [15:0] mem_addr;
wire mem_wr;
wire [15:0] dout;
wire [15:0] io_din;
wire [12:0] code_addr;
reg unlocked = 0;
`include "../build/ram.v"
reg interrupt = 0;
// ###### PROCESSOR #####################################
j1 _j1(
.clk(clk),
.resetq(resetq),
.io_rd(io_rd),
.io_wr(io_wr),
.mem_wr(mem_wr),
.dout(dout),
.io_din(io_din),
.mem_addr(mem_addr),
.code_addr(code_addr),
.insn_from_memory(insn),
.interrupt_request(interrupt)
);
// ###### TICKS #########################################
reg [15:0] ticks;
wire [16:0] ticks_plus_1 = ticks + 1;
always @(posedge clk)
if (io_wr & mem_addr[14])
ticks <= dout;
else
ticks <= ticks_plus_1;
always @(posedge clk) // Generate interrupt on ticks overflow
interrupt <= ticks_plus_1[16];
// ###### PORTA ###########################################
reg [15:0] porta_dir; // 1:output, 0:input
reg [15:0] porta_out;
wire [15:0] porta_in;
SB_IO #(.PIN_TYPE(6'b1010_01)) ioa0 (.PACKAGE_PIN(PORTA0), .D_OUT_0(porta_out[0]), .D_IN_0(porta_in[0]), .OUTPUT_ENABLE(porta_dir[0]));
SB_IO #(.PIN_TYPE(6'b1010_01)) ioa1 (.PACKAGE_PIN(PORTA1), .D_OUT_0(porta_out[1]), .D_IN_0(porta_in[1]), .OUTPUT_ENABLE(porta_dir[1]));
SB_IO #(.PIN_TYPE(6'b1010_01)) ioa2 (.PACKAGE_PIN(PORTA2), .D_OUT_0(porta_out[2]), .D_IN_0(porta_in[2]), .OUTPUT_ENABLE(porta_dir[2]));
SB_IO #(.PIN_TYPE(6'b1010_01)) ioa3 (.PACKAGE_PIN(PORTA3), .D_OUT_0(porta_out[3]), .D_IN_0(porta_in[3]), .OUTPUT_ENABLE(porta_dir[3]));
SB_IO #(.PIN_TYPE(6'b1010_01)) ioa4 (.PACKAGE_PIN(PORTA4), .D_OUT_0(porta_out[4]), .D_IN_0(porta_in[4]), .OUTPUT_ENABLE(porta_dir[4]));
SB_IO #(.PIN_TYPE(6'b1010_01)) ioa5 (.PACKAGE_PIN(PORTA5), .D_OUT_0(porta_out[5]), .D_IN_0(porta_in[5]), .OUTPUT_ENABLE(porta_dir[5]));
SB_IO #(.PIN_TYPE(6'b1010_01)) ioa6 (.PACKAGE_PIN(PORTA6), .D_OUT_0(porta_out[6]), .D_IN_0(porta_in[6]), .OUTPUT_ENABLE(porta_dir[6]));
SB_IO #(.PIN_TYPE(6'b1010_01)) ioa7 (.PACKAGE_PIN(PORTA7), .D_OUT_0(porta_out[7]), .D_IN_0(porta_in[7]), .OUTPUT_ENABLE(porta_dir[7]));
SB_IO #(.PIN_TYPE(6'b1010_01)) ioa8 (.PACKAGE_PIN(PORTA8), .D_OUT_0(porta_out[8]), .D_IN_0(porta_in[8]), .OUTPUT_ENABLE(porta_dir[8]));
SB_IO #(.PIN_TYPE(6'b1010_01)) ioa9 (.PACKAGE_PIN(PORTA9), .D_OUT_0(porta_out[9]), .D_IN_0(porta_in[9]), .OUTPUT_ENABLE(porta_dir[9]));
SB_IO #(.PIN_TYPE(6'b1010_01)) ioa10 (.PACKAGE_PIN(PORTA10), .D_OUT_0(porta_out[10]), .D_IN_0(porta_in[10]), .OUTPUT_ENABLE(porta_dir[10]));
SB_IO #(.PIN_TYPE(6'b1010_01)) ioa11 (.PACKAGE_PIN(PORTA11), .D_OUT_0(porta_out[11]), .D_IN_0(porta_in[11]), .OUTPUT_ENABLE(porta_dir[11]));
SB_IO #(.PIN_TYPE(6'b1010_01)) ioa12 (.PACKAGE_PIN(PORTA12), .D_OUT_0(porta_out[12]), .D_IN_0(porta_in[12]), .OUTPUT_ENABLE(porta_dir[12]));
SB_IO #(.PIN_TYPE(6'b1010_01)) ioa13 (.PACKAGE_PIN(PORTA13), .D_OUT_0(porta_out[13]), .D_IN_0(porta_in[13]), .OUTPUT_ENABLE(porta_dir[13]));
SB_IO #(.PIN_TYPE(6'b1010_01)) ioa14 (.PACKAGE_PIN(PORTA14), .D_OUT_0(porta_out[14]), .D_IN_0(porta_in[14]), .OUTPUT_ENABLE(porta_dir[14]));
SB_IO #(.PIN_TYPE(6'b1010_01)) ioa15 (.PACKAGE_PIN(PORTA15), .D_OUT_0(porta_out[15]), .D_IN_0(porta_in[15]), .OUTPUT_ENABLE(porta_dir[15]));
// ###### PORTB ###########################################
reg [15:0] portb_dir; // 1:output, 0:input
reg [15:0] portb_out;
wire [15:0] portb_in;
SB_IO #(.PIN_TYPE(6'b1010_01)) iob0 (.PACKAGE_PIN(PORTB0), .D_OUT_0(portb_out[0]), .D_IN_0(portb_in[0]), .OUTPUT_ENABLE(portb_dir[0]));
SB_IO #(.PIN_TYPE(6'b1010_01)) iob1 (.PACKAGE_PIN(PORTB1), .D_OUT_0(portb_out[1]), .D_IN_0(portb_in[1]), .OUTPUT_ENABLE(portb_dir[1]));
SB_IO #(.PIN_TYPE(6'b1010_01)) iob2 (.PACKAGE_PIN(PORTB2), .D_OUT_0(portb_out[2]), .D_IN_0(portb_in[2]), .OUTPUT_ENABLE(portb_dir[2]));
SB_IO #(.PIN_TYPE(6'b1010_01)) iob3 (.PACKAGE_PIN(PORTB3), .D_OUT_0(portb_out[3]), .D_IN_0(portb_in[3]), .OUTPUT_ENABLE(portb_dir[3]));
SB_IO #(.PIN_TYPE(6'b1010_01)) iob4 (.PACKAGE_PIN(PORTB4), .D_OUT_0(portb_out[4]), .D_IN_0(portb_in[4]), .OUTPUT_ENABLE(portb_dir[4]));
SB_IO #(.PIN_TYPE(6'b1010_01)) iob5 (.PACKAGE_PIN(PORTB5), .D_OUT_0(portb_out[5]), .D_IN_0(portb_in[5]), .OUTPUT_ENABLE(portb_dir[5]));
SB_IO #(.PIN_TYPE(6'b1010_01)) iob6 (.PACKAGE_PIN(PORTB6), .D_OUT_0(portb_out[6]), .D_IN_0(portb_in[6]), .OUTPUT_ENABLE(portb_dir[6]));
SB_IO #(.PIN_TYPE(6'b1010_01)) iob7 (.PACKAGE_PIN(PORTB7), .D_OUT_0(portb_out[7]), .D_IN_0(portb_in[7]), .OUTPUT_ENABLE(portb_dir[7]));
SB_IO #(.PIN_TYPE(6'b1010_01)) iob8 (.PACKAGE_PIN(PORTB8), .D_OUT_0(portb_out[8]), .D_IN_0(portb_in[8]), .OUTPUT_ENABLE(portb_dir[8]));
SB_IO #(.PIN_TYPE(6'b1010_01)) iob9 (.PACKAGE_PIN(PORTB9), .D_OUT_0(portb_out[9]), .D_IN_0(portb_in[9]), .OUTPUT_ENABLE(portb_dir[9]));
SB_IO #(.PIN_TYPE(6'b1010_01)) iob10 (.PACKAGE_PIN(PORTB10), .D_OUT_0(portb_out[10]), .D_IN_0(portb_in[10]), .OUTPUT_ENABLE(portb_dir[10]));
SB_IO #(.PIN_TYPE(6'b1010_01)) iob11 (.PACKAGE_PIN(PORTB11), .D_OUT_0(portb_out[11]), .D_IN_0(portb_in[11]), .OUTPUT_ENABLE(portb_dir[11]));
SB_IO #(.PIN_TYPE(6'b1010_01)) iob12 (.PACKAGE_PIN(PORTB12), .D_OUT_0(portb_out[12]), .D_IN_0(portb_in[12]), .OUTPUT_ENABLE(portb_dir[12]));
SB_IO #(.PIN_TYPE(6'b1010_01)) iob13 (.PACKAGE_PIN(PORTB13), .D_OUT_0(portb_out[13]), .D_IN_0(portb_in[13]), .OUTPUT_ENABLE(portb_dir[13]));
SB_IO #(.PIN_TYPE(6'b1010_01)) iob14 (.PACKAGE_PIN(PORTB14), .D_OUT_0(portb_out[14]), .D_IN_0(portb_in[14]), .OUTPUT_ENABLE(portb_dir[14]));
SB_IO #(.PIN_TYPE(6'b1010_01)) iob15 (.PACKAGE_PIN(PORTB15), .D_OUT_0(portb_out[15]), .D_IN_0(portb_in[15]), .OUTPUT_ENABLE(portb_dir[15]));
// ###### PORTC ###########################################
reg [15:0] portc_dir; // 1:output, 0:input
reg [15:0] portc_out;
wire [15:0] portc_in;
SB_IO #(.PIN_TYPE(6'b1010_01)) ioc0 (.PACKAGE_PIN(PORTC0), .D_OUT_0(portc_out[0]), .D_IN_0(portc_in[0]), .OUTPUT_ENABLE(portc_dir[0]));
SB_IO #(.PIN_TYPE(6'b1010_01)) ioc1 (.PACKAGE_PIN(PORTC1), .D_OUT_0(portc_out[1]), .D_IN_0(portc_in[1]), .OUTPUT_ENABLE(portc_dir[1]));
SB_IO #(.PIN_TYPE(6'b1010_01)) ioc2 (.PACKAGE_PIN(PORTC2), .D_OUT_0(portc_out[2]), .D_IN_0(portc_in[2]), .OUTPUT_ENABLE(portc_dir[2]));
SB_IO #(.PIN_TYPE(6'b1010_01)) ioc3 (.PACKAGE_PIN(PORTC3), .D_OUT_0(portc_out[3]), .D_IN_0(portc_in[3]), .OUTPUT_ENABLE(portc_dir[3]));
SB_IO #(.PIN_TYPE(6'b1010_01)) ioc4 (.PACKAGE_PIN(PORTC4), .D_OUT_0(portc_out[4]), .D_IN_0(portc_in[4]), .OUTPUT_ENABLE(portc_dir[4]));
SB_IO #(.PIN_TYPE(6'b1010_01)) ioc5 (.PACKAGE_PIN(PORTC5), .D_OUT_0(portc_out[5]), .D_IN_0(portc_in[5]), .OUTPUT_ENABLE(portc_dir[5]));
SB_IO #(.PIN_TYPE(6'b1010_01)) ioc6 (.PACKAGE_PIN(PORTC6), .D_OUT_0(portc_out[6]), .D_IN_0(portc_in[6]), .OUTPUT_ENABLE(portc_dir[6]));
SB_IO #(.PIN_TYPE(6'b1010_01)) ioc7 (.PACKAGE_PIN(PORTC7), .D_OUT_0(portc_out[7]), .D_IN_0(portc_in[7]), .OUTPUT_ENABLE(portc_dir[7]));
SB_IO #(.PIN_TYPE(6'b1010_01)) ioc8 (.PACKAGE_PIN(PORTC8), .D_OUT_0(portc_out[8]), .D_IN_0(portc_in[8]), .OUTPUT_ENABLE(portc_dir[8]));
SB_IO #(.PIN_TYPE(6'b1010_01)) ioc9 (.PACKAGE_PIN(PORTC9), .D_OUT_0(portc_out[9]), .D_IN_0(portc_in[9]), .OUTPUT_ENABLE(portc_dir[9]));
SB_IO #(.PIN_TYPE(6'b1010_01)) ioc10 (.PACKAGE_PIN(PORTC10), .D_OUT_0(portc_out[10]), .D_IN_0(portc_in[10]), .OUTPUT_ENABLE(portc_dir[10]));
SB_IO #(.PIN_TYPE(6'b1010_01)) ioc11 (.PACKAGE_PIN(PORTC11), .D_OUT_0(portc_out[11]), .D_IN_0(portc_in[11]), .OUTPUT_ENABLE(portc_dir[11]));
SB_IO #(.PIN_TYPE(6'b1010_01)) ioc12 (.PACKAGE_PIN(PORTC12), .D_OUT_0(portc_out[12]), .D_IN_0(portc_in[12]), .OUTPUT_ENABLE(portc_dir[12]));
SB_IO #(.PIN_TYPE(6'b1010_01)) ioc13 (.PACKAGE_PIN(PORTC13), .D_OUT_0(portc_out[13]), .D_IN_0(portc_in[13]), .OUTPUT_ENABLE(portc_dir[13]));
SB_IO #(.PIN_TYPE(6'b1010_01)) ioc14 (.PACKAGE_PIN(PORTC14), .D_OUT_0(portc_out[14]), .D_IN_0(portc_in[14]), .OUTPUT_ENABLE(portc_dir[14]));
SB_IO #(.PIN_TYPE(6'b1010_01)) ioc15 (.PACKAGE_PIN(PORTC15), .D_OUT_0(portc_out[15]), .D_IN_0(portc_in[15]), .OUTPUT_ENABLE(portc_dir[15]));
// ###### UART ##########################################
wire uart0_valid, uart0_busy;
wire [7:0] uart0_data;
wire uart0_wr = io_wr & mem_addr[12];
wire uart0_rd = io_rd & mem_addr[12];
wire UART0_RX;
buart _uart0 (
.clk(clk),
.resetq(1'b1),
.rx(RXD),
.tx(TXD),
.rd(uart0_rd),
.wr(uart0_wr),
.valid(uart0_valid),
.busy(uart0_busy),
.tx_data(dout[7:0]),
.rx_data(uart0_data));
// ###### LEDS & PIOS ###################################
reg [5:0] PIOS;
assign {CTS, PIO1_20, PIO1_18, PIOS_00, PIOS_02, PIOS_03} = PIOS;
reg [7:0] LEDS;
assign {D8,D7,D6,D5,D4,D3,D2,D1} = LEDS;
// ###### RING OSCILLATOR ###############################
wire [1:0] buffers_in, buffers_out;
assign buffers_in = {buffers_out[0:0], ~buffers_out[1]};
SB_LUT4 #(
.LUT_INIT(16'd2)
) buffers [1:0] (
.O(buffers_out),
.I0(buffers_in),
.I1(1'b0),
.I2(1'b0),
.I3(1'b0)
);
wire random = ~buffers_out[1];
// ###### IO PORTS ######################################
/* bit READ WRITE
0001 0 PMOD in
0002 1 PMOD out PMOD out
0004 2 PMOD dir PMOD dir
0008 3 misc.out misc.out
0010 4 header 1 in
0020 5 header 1 out header 1 out
0040 6 header 1 dir header 1 dir
0080 7
0100 8 header 2 in
0200 9 header 2 out header 2 out
0400 10 header 2 dir header 2 dir
0800 11
1000 12 UART RX UART TX
2000 13 misc.in
4000 14 ticks clear ticks
8000 15
*/
assign io_din =
(mem_addr[ 0] ? porta_in : 16'd0) |
(mem_addr[ 1] ? porta_out : 16'd0) |
(mem_addr[ 2] ? porta_dir : 16'd0) |
(mem_addr[ 3] ? { 2'd0, LEDS, PIOS} : 16'd0) |
(mem_addr[ 4] ? portb_in : 16'd0) |
(mem_addr[ 5] ? portb_out : 16'd0) |
(mem_addr[ 6] ? portb_dir : 16'd0) |
(mem_addr[ 8] ? portc_in : 16'd0) |
(mem_addr[ 9] ? portc_out : 16'd0) |
(mem_addr[10] ? portc_dir : 16'd0) |
(mem_addr[12] ? { 8'd0, uart0_data} : 16'd0) |
(mem_addr[13] ? {10'd0, random, RTS, PIO1_19, PIOS_01, uart0_valid, !uart0_busy} : 16'd0) |
(mem_addr[14] ? ticks : 16'd0) ;
// Very few gates needed: Simply trigger warmboot by any IO access to $8000 / $8001 / $8002 / $8003.
// SB_WARMBOOT _sb_warmboot ( .BOOT(io_wr & mem_addr[15]), .S1(mem_addr[1]), .S0(mem_addr[0]) );
always @(posedge clk) begin
if (io_wr & mem_addr[1]) porta_out <= dout;
if (io_wr & mem_addr[2]) porta_dir <= dout;
if (io_wr & mem_addr[3]) {LEDS, PIOS} <= dout[13:0];
if (io_wr & mem_addr[5]) portb_out <= dout;
if (io_wr & mem_addr[6]) portb_dir <= dout;
if (io_wr & mem_addr[9]) portc_out <= dout;
if (io_wr & mem_addr[10]) portc_dir <= dout;
end
// ###### MEMLOCK #######################################
// This is a workaround to protect memory contents during Reset.
// Somehow it happens sometimes that the first memory location is corrupted during startup,
// and as an IO write is one of the earliest things which are done, memory write access is unlocked
// only after the processor is up and running and sending its welcome message.
always @(negedge resetq or posedge clk)
if (!resetq) unlocked <= 0;
else unlocked <= unlocked | io_wr;
endmodule // top
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2010 by Wilson Snyder.
module t (/*AUTOARG*/
// Outputs
data_out,
// Inputs
wr, wa, rst_l, rd, ra, data_in, clk
);
input clk;
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [31:0] data_in; // To sub of reg_1r1w.v
input [7:0] ra; // To sub of reg_1r1w.v
input rd; // To sub of reg_1r1w.v
input rst_l; // To sub of reg_1r1w.v
input [7:0] wa; // To sub of reg_1r1w.v
input wr; // To sub of reg_1r1w.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [31:0] data_out; // From sub of reg_1r1w.v
// End of automatics
reg_1r1w #(.WIDTH(32), .DEPTH(256), .ADRWID(8))
sub
(/*AUTOINST*/
// Outputs
.data_out (data_out[31:0]),
// Inputs
.data_in (data_in[31:0]),
.ra (ra[7:0]),
.wa (wa[7:0]),
.wr (wr),
.rd (rd),
.clk (clk),
.rst_l (rst_l));
endmodule
module reg_1r1w
#(
parameter WIDTH=32,
parameter ADRWID=10,
parameter DEPTH=1024,
parameter RST=0
)
(/*AUTOARG*/
// Outputs
data_out,
// Inputs
data_in, ra, wa, wr, rd, clk, rst_l
);
input [WIDTH-1:0] data_in;
input [ADRWID-1:0] ra;
input [ADRWID-1:0] wa;
input wr;
input rd;
input clk;
input rst_l;
output [WIDTH-1:0] data_out;
reg [WIDTH-1:0] array [DEPTH-1:0];
reg [ADRWID-1:0] ra_r, wa_r;
reg [WIDTH-1:0] data_in_r;
reg wr_r;
reg rd_r;
integer x;
// Message 679
always @(posedge clk) begin
int tmp = x + 1;
if (tmp !== x + 1) $stop;
end
always @(posedge clk or negedge rst_l) begin
if (!rst_l) begin
for (x=0; x<DEPTH; x=x+1) begin // <== VERILATOR FLAGS THIS LINE
if (RST == 1) begin
array[x] <= 0;
end
end
ra_r <= 0;
wa_r <= 0;
wr_r <= 0;
rd_r <= 0;
data_in_r <= 0;
end
else begin
ra_r <= ra;
wa_r <= wa;
wr_r <= wr;
rd_r <= rd;
data_in_r <= data_in;
if (wr_r) array[wa_r] <= data_in_r;
end
end
endmodule
// Local Variables:
// verilog-auto-inst-param-value: t
// End:
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module top (
input clk,
output [3:0] led,
inout out_a,
output [1:0] out_b
);
wire LD6, LD7, LD8, LD9;
wire inter_wire, inter_wire_2;
localparam BITS = 1;
localparam LOG2DELAY = 25;
reg [BITS+LOG2DELAY-1:0] counter = 0;
always @(posedge clk) begin
counter <= counter + 1;
end
assign led[1] = inter_wire;
assign inter_wire = inter_wire_2;
assign {LD9, LD8, LD7, LD6} = counter >> LOG2DELAY;
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_6 (
.I(LD6),
.O(led[0])
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_7 (
.I(LD7),
.O(inter_wire_2)
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_OUT (
.I(LD7),
.O(out_a)
);
bottom bottom_inst (
.I (LD8),
.O (led[2]),
.OB(out_b)
);
bottom_intermediate bottom_intermediate_inst (
.I(LD9),
.O(led[3])
);
endmodule
module bottom_intermediate (
input I,
output O
);
wire bottom_intermediate_wire;
assign O = bottom_intermediate_wire;
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_8 (
.I(I),
.O(bottom_intermediate_wire)
);
endmodule
module bottom (
input I,
output [1:0] OB,
output O
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_9 (
.I(I),
.O(O)
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_10 (
.I(I),
.O(OB[0])
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_11 (
.I(I),
.O(OB[1])
);
endmodule
|
module sgpr_comparator
(/*AUTOARG*/
// Outputs
result,
// Inputs
retired_operand_mask, retired_operand_addr, src1_gpr_info,
src4_gpr_info, dst1_gpr_info, src2_gpr_info, src3_gpr_info,
dst2_gpr_info
);
wire src1_cmp_en, src2_cmp_en, src3_cmp_en, src4_cmp_en,
dst1_cmp_en, dst2_cmp_en;
input [3:0] retired_operand_mask;
wire [3:0] src1_mask, src4_mask, dst1_mask;
wire [2:0] src2_mask, src3_mask, dst2_mask;
input [`SGPR_ADDR_LENGTH-1:0] retired_operand_addr;
input [13:0] src1_gpr_info, src4_gpr_info, dst1_gpr_info;
input [12:0] src2_gpr_info, src3_gpr_info, dst2_gpr_info;
output [`ISSUE_GPR_RD_BITS_LENGTH-1:0] result;
wire [3:0] src1_cmp_result, src4_cmp_result, dst1_cmp_result;
wire [1:0] src2_cmp_result, src3_cmp_result, dst2_cmp_result;
// Compare only valid sgprs
assign src1_cmp_en = get_valid_sgpr(src1_gpr_info[11:0]);
assign src2_cmp_en = get_valid_sgpr(src2_gpr_info[11:0]);
assign src3_cmp_en = get_valid_sgpr(src3_gpr_info[11:0]);
assign src4_cmp_en = get_valid_sgpr(src4_gpr_info[11:0]);
assign dst1_cmp_en = get_valid_sgpr(dst1_gpr_info[11:0]);
assign dst2_cmp_en = get_valid_sgpr(dst2_gpr_info[11:0]);
assign src1_mask = get_mask_4w(src1_gpr_info);
assign src2_mask = get_mask_2w(src2_gpr_info);
assign src3_mask = get_mask_2w(src3_gpr_info);
assign src4_mask = get_mask_4w(src4_gpr_info);
assign dst1_mask = get_mask_4w(dst1_gpr_info);
assign dst2_mask = get_mask_2w(dst2_gpr_info);
assign src1_cmp_result = sgpr_compare_operands_4w(src1_cmp_en, retired_operand_addr,
src1_gpr_info[`SGPR_ADDR_LENGTH-1:0],
retired_operand_mask,
src1_mask);
assign src2_cmp_result = sgpr_compare_operands_2w(src2_cmp_en, retired_operand_addr,
src2_gpr_info[`SGPR_ADDR_LENGTH-1:0],
retired_operand_mask,
src2_mask);
assign src3_cmp_result = sgpr_compare_operands_2w(src3_cmp_en, retired_operand_addr,
src3_gpr_info[`SGPR_ADDR_LENGTH-1:0],
retired_operand_mask,
src3_mask);
assign src4_cmp_result = sgpr_compare_operands_4w(src4_cmp_en, retired_operand_addr,
src4_gpr_info[`SGPR_ADDR_LENGTH-1:0],
retired_operand_mask,
src4_mask);
assign dst1_cmp_result = sgpr_compare_operands_4w(dst1_cmp_en, retired_operand_addr,
dst1_gpr_info[`SGPR_ADDR_LENGTH-1:0],
retired_operand_mask,
dst1_mask);
assign dst2_cmp_result = sgpr_compare_operands_2w(dst2_cmp_en, retired_operand_addr,
dst2_gpr_info[`SGPR_ADDR_LENGTH-1:0],
retired_operand_mask,
dst2_mask);
assign result = {src1_cmp_result, src2_cmp_result, src3_cmp_result,
src4_cmp_result, dst1_cmp_result, dst2_cmp_result};
// Function to verify if the operand is indeed a valid sgpr
function get_valid_sgpr;
input[11:0] sgpr_info;
begin
get_valid_sgpr
= (sgpr_info[`ISSUE_OP_VALID_H:`ISSUE_OP_VALID_SGPR_L] == `ISSUE_VALID_SGPR_ID)?
1'b1 : 1'b0;
end
endfunction
// Functions to generate masks
function [3:0] get_mask_4w;
input[13:0] sgpr_info;
begin
get_mask_4w
= (sgpr_info[`ISSUE_OP_4WORD_BIT]) ? 4'b1111 :
(sgpr_info[`ISSUE_OP_2WORD_BIT]) ? 4'b0011 :
4'b0001;
end
endfunction
function [1:0] get_mask_2w;
input[12:0] sgpr_info;
begin
get_mask_2w
= (sgpr_info[`ISSUE_OP_2WORD_BIT]) ? 4'b0011 :
4'b0001;
end
endfunction
// Functions that compare two operands
function [3:0] sgpr_compare_operands_4w;
input sb_operand_en;
input [`SGPR_ADDR_LENGTH-1:0] r_operand_info, sb_operand_info;
input [3:0] r_operand_mask, sb_operand_mask;
begin
sgpr_compare_operands_4w
= ( sb_operand_en == 1'b0 ) ? 4'b0000 :
( sb_operand_info+3 == r_operand_info ) ? sb_operand_mask & r_operand_mask<<3 :
( sb_operand_info+2 == r_operand_info ) ? sb_operand_mask & r_operand_mask<<2 :
( sb_operand_info+1 == r_operand_info ) ? sb_operand_mask & r_operand_mask<<1 :
( sb_operand_info == r_operand_info ) ? sb_operand_mask & r_operand_mask :
( sb_operand_info == r_operand_info+1 ) ? sb_operand_mask & r_operand_mask>>1 :
( sb_operand_info == r_operand_info+2 ) ? sb_operand_mask & r_operand_mask>>2 :
( sb_operand_info == r_operand_info+3 ) ? sb_operand_mask & r_operand_mask>>3 :
4'b0000;
end
endfunction
function [1:0] sgpr_compare_operands_2w;
input sb_operand_en;
input [`SGPR_ADDR_LENGTH-1:0] r_operand_info, sb_operand_info;
input [3:0] r_operand_mask;
input [1:0] sb_operand_mask;
begin
sgpr_compare_operands_2w
= ( sb_operand_en == 1'b0 )? 2'b00 :
( sb_operand_info+1 == r_operand_info ) ? (sb_operand_mask & {r_operand_mask[0],1'b0}) :
( sb_operand_info == r_operand_info ) ? (sb_operand_mask & r_operand_mask[1:0]) :
( sb_operand_info == r_operand_info+1 ) ? (sb_operand_mask & r_operand_mask[2:1]) :
( sb_operand_info == r_operand_info+2 ) ? sb_operand_mask & r_operand_mask[3:2] :
( sb_operand_info == r_operand_info+3 ) ? sb_operand_mask & {1'b0,r_operand_mask[3]} :
2'b00;
end
endfunction
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
// Life analysis checks
reg [15:0] life;
// Ding case
reg [7:0] din;
reg [15:0] fixin;
always @* begin
fixin = {din[7:0],din[7:0]};
case (din[1:0])
2'b00: begin
fixin = {fixin[14:0], 1'b1};
if (cyc==101) $display("Prevent ?: optimization a");
end
2'b01: begin
fixin = {fixin[13:0], 2'b11};
if (cyc==101) $display("Prevent ?: optimization b");
end
2'b10: begin
fixin = {fixin[12:0], 3'b111};
if (cyc==101) $display("Prevent ?: optimization c");
end
2'b11: begin
fixin = {fixin[11:0], 4'b1111};
if (cyc==101) $display("Prevent ?: optimization d");
end
endcase
end
always @ (posedge clk) begin
if (cyc!=0) begin
cyc<=cyc+1;
if (cyc==1) begin
life = 16'h8000; // Dropped
life = 16'h0010; // Used below
if (life != 16'h0010) $stop;
//
life = 16'h0020; // Used below
if ($time < 10000)
if (life != 16'h0020) $stop;
//
life = 16'h8000; // Dropped
if ($time > 100000) begin
if ($time != 0) $stop; // Prevent conversion to ?:
life = 16'h1030;
end
else
life = 16'h0030;
if (life != 16'h0030) $stop;
//
life = 16'h0040; // Not dropped, no else below
if ($time > 100000)
life = 16'h1040;
if (life != 16'h0040) $stop;
//
life = 16'h8000; // Dropped
if ($time > 100000) begin
life = 16'h1050;
if (life != 0) $stop; // Ignored, as set is first
end
else begin
if ($time > 100010)
life = 16'h1050;
else life = 16'h0050;
end
if (life != 16'h0050) $stop;
end
if (cyc==2) begin
din <= 8'haa;
end
if (cyc==3) begin
din <= 8'hfb;
if (fixin != 16'h5557) $stop;
end
if (cyc==4) begin
din <= 8'h5c;
if (fixin != 16'hbfbf) $stop;
end
if (cyc==5) begin
din <= 8'hed;
if (fixin != 16'hb8b9) $stop;
end
if (cyc==6) begin
if (fixin != 16'hb7b7) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
`timescale 1ns / 1ps
`include "Defintions.v"
module MiniAlu
(
input wire Clock,
input wire Reset,
output wire [7:0] oLed
);
wire [15:0] wIP,wIP_temp,wIP_return;
reg rWriteEnable,rBranchTaken,rReturn,rCall;
wire [27:0] wInstruction;
wire [3:0] wOperation;
reg [15:0] rResult;
wire [7:0] wSourceAddr0,wSourceAddr1,wDestination, wDestinationPrev;
wire [15:0] wSourceData0,wSourceData1,wSourceData0_RAM,wSourceData1_RAM,wResultPrev,wIPInitialValue,wDestinationJump,wImmediateValue;
wire wHazard0, wHazard1, wWriteEnablePrev, wIsImmediate,wPushAddr;
ROM InstructionRom
(
.iAddress( wIP ),
.oInstruction( wInstruction )
);
RAM_DUAL_READ_PORT DataRam
(
.Clock( Clock ),
.iWriteEnable( rWriteEnable ),
.iReadAddress0( wInstruction[7:0] ),
.iReadAddress1( wInstruction[15:8] ),
.iWriteAddress( wDestination ),
.iDataIn( rResult ),
.oDataOut0( wSourceData0_RAM ),
.oDataOut1( wSourceData1_RAM )
);
assign wDestinationJump = (rReturn) ? wIP_return : wDestination;
assign wIPInitialValue = (Reset) ? 8'b0 : wDestinationJump;
UPCOUNTER_POSEDGE IP
(
.Clock( Clock ),
.Reset( Reset | rBranchTaken ),
.Initial( wIPInitialValue + 16'd1 ),
.Enable( 1'b1 ),
.Q( wIP_temp )
);
assign wIP = (rBranchTaken) ? wIPInitialValue : wIP_temp;
FFD_POSEDGE_SYNCRONOUS_RESET # ( 4 ) FFD1
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wInstruction[27:24]),
.Q(wOperation)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFD2
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wInstruction[7:0]),
.Q(wSourceAddr0)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFD3
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wInstruction[15:8]),
.Q(wSourceAddr1)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFD4
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wInstruction[23:16]),
.Q(wDestination)
);
reg rFFLedEN;
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FF_LEDS
(
.Clock(Clock),
.Reset(Reset),
.Enable( rFFLedEN ),
.D( wSourceData1[7:0] ),
.Q( oLed )
);
assign wImmediateValue = {wSourceAddr1,wSourceAddr0};
/////////////////////////////////
// Data Hazards en el pipeline //
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFD41
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wDestination),
.Q(wDestinationPrev)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 16 ) FFDRES
(
.Clock(Clock),
.Reset(Reset),
.Enable(rWriteEnable),
.D(rResult),
.Q(wResultPrev)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFDWRITE
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D( {rWriteEnable} ),
.Q( {wWriteEnablePrev} )
);
assign wIsImmediate = wOperation[3] && wOperation[2];
assign wHazard0 = ((wDestinationPrev == wSourceAddr0) && wWriteEnablePrev && ~wIsImmediate ) ? 1'b1 : 1'b0;
assign wHazard1 = ((wDestinationPrev == wSourceAddr1) && wWriteEnablePrev && ~wIsImmediate ) ? 1'b1 : 1'b0;
assign wSourceData0 = (wHazard0) ? wResultPrev : wSourceData0_RAM;
assign wSourceData1 = (wHazard1) ? wResultPrev : wSourceData1_RAM;
// //
/////////////////////////////////
/////////////////////////////////
// CALL RET //
// assign wPushAddr = (wInstruction[27:24] == `CALL);
//assign wPushAddr = (wOperation == `CALL);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 16 ) FF_RET
(
.Clock(~Clock),
.Reset(Reset),
.Enable( rCall ),
.D( wIP_temp ),
.Q( wIP_return )
);
// //
/////////////////////////////////
always @ ( * )
begin
case (wOperation)
//-------------------------------------
`NOP:
begin
rFFLedEN <= 1'b0;
rBranchTaken <= 1'b0;
rWriteEnable <= 1'b0;
rResult <= 0;
rReturn <= 1'b0;
rCall <= 1'b0;
end
//-------------------------------------
`ADD:
begin
rFFLedEN <= 1'b0;
rBranchTaken <= 1'b0;
rWriteEnable <= 1'b1;
rResult <= wSourceData1 + wSourceData0;
rReturn <= 1'b0;
rCall <= 1'b0;
end
//-------------------------------------
`SUB:
begin
rFFLedEN <= 1'b0;
rBranchTaken <= 1'b0;
rWriteEnable <= 1'b1;
rResult <= wSourceData1 - wSourceData0;
rReturn <= 1'b0;
rCall <= 1'b0;
end
//-------------------------------------
`STO:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b1;
rBranchTaken <= 1'b0;
rResult <= wImmediateValue;
rReturn <= 1'b0;
rCall <= 1'b0;
end
//-------------------------------------
`BLE:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b0;
rResult <= 0;
if (wSourceData1 <= wSourceData0 )
rBranchTaken <= 1'b1;
else
rBranchTaken <= 1'b0;
rReturn <= 1'b0;
rCall <= 1'b0;
end
//-------------------------------------
`JMP:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b0;
rResult <= 0;
rBranchTaken <= 1'b1;
rReturn <= 1'b0;
rCall <= 1'b0;
end
//-------------------------------------
`CALL:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b0;
rResult <= 0;
rBranchTaken <= 1'b1;
rReturn <= 1'b0;
rCall <= 1'b1;
end
//-------------------------------------
`RET:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b0;
rResult <= 0;
rBranchTaken <= 1'b1;
rReturn <= 1'b1;
rCall <= 1'b0;
end
//-------------------------------------
`LED:
begin
rFFLedEN <= 1'b1;
rWriteEnable <= 1'b0;
rResult <= 0;
rBranchTaken <= 1'b0;
rReturn <= 1'b0;
rCall <= 1'b0;
end
//-------------------------------------
default:
begin
rFFLedEN <= 1'b1;
rWriteEnable <= 1'b0;
rResult <= 0;
rBranchTaken <= 1'b0;
rReturn <= 1'b0;
rCall <= 1'b0;
end
//-------------------------------------
endcase
end
endmodule
|
// CONFIG:
// NUM_COEFF = 22
// PIPLINED = 0
// WARNING: more than enough COEFFICIENTS in array (there are 26, and we only need 11)
module fir (
clk,
reset,
clk_ena,
i_valid,
i_in,
o_valid,
o_out
);
// Data Width
parameter dw = 18; //Data input/output bits
// Number of filter coefficients
parameter N = 22;
parameter N_UNIQ = 11; // ciel(N/2) assuming symmetric filter coefficients
//Number of extra valid cycles needed to align output (i.e. computation pipeline depth + input/output registers
localparam N_VALID_REGS = 23;
input clk;
input reset;
input clk_ena;
input i_valid;
input [dw-1:0] i_in; // signed
output o_valid;
output [dw-1:0] o_out; // signed
// Data Width dervied parameters
localparam dw_add_int = 18; //Internal adder precision bits
localparam dw_mult_int = 36; //Internal multiplier precision bits
localparam scale_factor = 17; //Multiplier normalization shift amount
// Number of extra registers in INPUT_PIPELINE_REG to prevent contention for CHAIN_END's chain adders
localparam N_INPUT_REGS = 22;
// Debug
// initial begin
// $display ("Data Width: %d", dw);
// $display ("Data Width Add Internal: %d", dw_add_int);
// $display ("Data Width Mult Internal: %d", dw_mult_int);
// $display ("Scale Factor: %d", scale_factor);
// end
reg [dw-1:0] COEFFICIENT_0;
reg [dw-1:0] COEFFICIENT_1;
reg [dw-1:0] COEFFICIENT_2;
reg [dw-1:0] COEFFICIENT_3;
reg [dw-1:0] COEFFICIENT_4;
reg [dw-1:0] COEFFICIENT_5;
reg [dw-1:0] COEFFICIENT_6;
reg [dw-1:0] COEFFICIENT_7;
reg [dw-1:0] COEFFICIENT_8;
reg [dw-1:0] COEFFICIENT_9;
reg [dw-1:0] COEFFICIENT_10;
always@(posedge clk) begin
COEFFICIENT_0 <= 18'd88;
COEFFICIENT_1 <= 18'd0;
COEFFICIENT_2 <= -18'd97;
COEFFICIENT_3 <= -18'd197;
COEFFICIENT_4 <= -18'd294;
COEFFICIENT_5 <= -18'd380;
COEFFICIENT_6 <= -18'd447;
COEFFICIENT_7 <= -18'd490;
COEFFICIENT_8 <= -18'd504;
COEFFICIENT_9 <= -18'd481;
COEFFICIENT_10 <= -18'd420;
end
////******************************************************
// *
// * Valid Delay Pipeline
// *
// *****************************************************
//Input valid signal is pipelined to become output valid signal
//Valid registers
reg [N_VALID_REGS-1:0] VALID_PIPELINE_REGS;
always@(posedge clk or posedge reset) begin
if(reset) begin
VALID_PIPELINE_REGS <= 0;
end else begin
if(clk_ena) begin
VALID_PIPELINE_REGS <= {VALID_PIPELINE_REGS[N_VALID_REGS-2:0], i_valid};
end else begin
VALID_PIPELINE_REGS <= VALID_PIPELINE_REGS;
end
end
end
////******************************************************
// *
// * Input Register Pipeline
// *
// *****************************************************
//Pipelined input values
//Input value registers
wire [dw-1:0] INPUT_PIPELINE_REG_0;
wire [dw-1:0] INPUT_PIPELINE_REG_1;
wire [dw-1:0] INPUT_PIPELINE_REG_2;
wire [dw-1:0] INPUT_PIPELINE_REG_3;
wire [dw-1:0] INPUT_PIPELINE_REG_4;
wire [dw-1:0] INPUT_PIPELINE_REG_5;
wire [dw-1:0] INPUT_PIPELINE_REG_6;
wire [dw-1:0] INPUT_PIPELINE_REG_7;
wire [dw-1:0] INPUT_PIPELINE_REG_8;
wire [dw-1:0] INPUT_PIPELINE_REG_9;
wire [dw-1:0] INPUT_PIPELINE_REG_10;
wire [dw-1:0] INPUT_PIPELINE_REG_11;
wire [dw-1:0] INPUT_PIPELINE_REG_12;
wire [dw-1:0] INPUT_PIPELINE_REG_13;
wire [dw-1:0] INPUT_PIPELINE_REG_14;
wire [dw-1:0] INPUT_PIPELINE_REG_15;
wire [dw-1:0] INPUT_PIPELINE_REG_16;
wire [dw-1:0] INPUT_PIPELINE_REG_17;
wire [dw-1:0] INPUT_PIPELINE_REG_18;
wire [dw-1:0] INPUT_PIPELINE_REG_19;
wire [dw-1:0] INPUT_PIPELINE_REG_20;
wire [dw-1:0] INPUT_PIPELINE_REG_21;
input_pipeline in_pipe(
.clk(clk), .clk_ena(clk_ena),
.in_stream(i_in),
.pipeline_reg_0(INPUT_PIPELINE_REG_0),
.pipeline_reg_1(INPUT_PIPELINE_REG_1),
.pipeline_reg_2(INPUT_PIPELINE_REG_2),
.pipeline_reg_3(INPUT_PIPELINE_REG_3),
.pipeline_reg_4(INPUT_PIPELINE_REG_4),
.pipeline_reg_5(INPUT_PIPELINE_REG_5),
.pipeline_reg_6(INPUT_PIPELINE_REG_6),
.pipeline_reg_7(INPUT_PIPELINE_REG_7),
.pipeline_reg_8(INPUT_PIPELINE_REG_8),
.pipeline_reg_9(INPUT_PIPELINE_REG_9),
.pipeline_reg_10(INPUT_PIPELINE_REG_10),
.pipeline_reg_11(INPUT_PIPELINE_REG_11),
.pipeline_reg_12(INPUT_PIPELINE_REG_12),
.pipeline_reg_13(INPUT_PIPELINE_REG_13),
.pipeline_reg_14(INPUT_PIPELINE_REG_14),
.pipeline_reg_15(INPUT_PIPELINE_REG_15),
.pipeline_reg_16(INPUT_PIPELINE_REG_16),
.pipeline_reg_17(INPUT_PIPELINE_REG_17),
.pipeline_reg_18(INPUT_PIPELINE_REG_18),
.pipeline_reg_19(INPUT_PIPELINE_REG_19),
.pipeline_reg_20(INPUT_PIPELINE_REG_20),
.pipeline_reg_21(INPUT_PIPELINE_REG_21),
.reset(reset) );
defparam in_pipe.WIDTH = 18; // = dw
////******************************************************
// *
// * Computation Pipeline
// *
// *****************************************************
// ************************* LEVEL 0 ************************* \\
wire [dw-1:0] L0_output_wires_0;
wire [dw-1:0] L0_output_wires_1;
wire [dw-1:0] L0_output_wires_2;
wire [dw-1:0] L0_output_wires_3;
wire [dw-1:0] L0_output_wires_4;
wire [dw-1:0] L0_output_wires_5;
wire [dw-1:0] L0_output_wires_6;
wire [dw-1:0] L0_output_wires_7;
wire [dw-1:0] L0_output_wires_8;
wire [dw-1:0] L0_output_wires_9;
wire [dw-1:0] L0_output_wires_10;
adder_with_1_reg L0_adder_0and21(
.dataa (INPUT_PIPELINE_REG_0),
.datab (INPUT_PIPELINE_REG_21),
.result(L0_output_wires_0)
);
adder_with_1_reg L0_adder_1and20(
.dataa (INPUT_PIPELINE_REG_1),
.datab (INPUT_PIPELINE_REG_20),
.result(L0_output_wires_1)
);
adder_with_1_reg L0_adder_2and19(
.dataa (INPUT_PIPELINE_REG_2),
.datab (INPUT_PIPELINE_REG_19),
.result(L0_output_wires_2)
);
adder_with_1_reg L0_adder_3and18(
.dataa (INPUT_PIPELINE_REG_3),
.datab (INPUT_PIPELINE_REG_18),
.result(L0_output_wires_3)
);
adder_with_1_reg L0_adder_4and17(
.dataa (INPUT_PIPELINE_REG_4),
.datab (INPUT_PIPELINE_REG_17),
.result(L0_output_wires_4)
);
adder_with_1_reg L0_adder_5and16(
.dataa (INPUT_PIPELINE_REG_5),
.datab (INPUT_PIPELINE_REG_16),
.result(L0_output_wires_5)
);
adder_with_1_reg L0_adder_6and15(
.dataa (INPUT_PIPELINE_REG_6),
.datab (INPUT_PIPELINE_REG_15),
.result(L0_output_wires_6)
);
adder_with_1_reg L0_adder_7and14(
.dataa (INPUT_PIPELINE_REG_7),
.datab (INPUT_PIPELINE_REG_14),
.result(L0_output_wires_7)
);
adder_with_1_reg L0_adder_8and13(
.dataa (INPUT_PIPELINE_REG_8),
.datab (INPUT_PIPELINE_REG_13),
.result(L0_output_wires_8)
);
adder_with_1_reg L0_adder_9and12(
.dataa (INPUT_PIPELINE_REG_9),
.datab (INPUT_PIPELINE_REG_12),
.result(L0_output_wires_9)
);
adder_with_1_reg L0_adder_10and11(
.dataa (INPUT_PIPELINE_REG_10),
.datab (INPUT_PIPELINE_REG_11),
.result(L0_output_wires_10)
);
// (11 main tree Adders)
// ************************* LEVEL 1 ************************* \\
// **************** Multipliers **************** \\
wire [dw-1:0] L1_mult_wires_0;
wire [dw-1:0] L1_mult_wires_1;
wire [dw-1:0] L1_mult_wires_2;
wire [dw-1:0] L1_mult_wires_3;
wire [dw-1:0] L1_mult_wires_4;
wire [dw-1:0] L1_mult_wires_5;
wire [dw-1:0] L1_mult_wires_6;
wire [dw-1:0] L1_mult_wires_7;
wire [dw-1:0] L1_mult_wires_8;
wire [dw-1:0] L1_mult_wires_9;
wire [dw-1:0] L1_mult_wires_10;
multiplier_with_reg L1_mul_0(
.dataa (L0_output_wires_0),
.datab (COEFFICIENT_0),
.result(L1_mult_wires_0)
);
multiplier_with_reg L1_mul_1(
.dataa (L0_output_wires_1),
.datab (COEFFICIENT_1),
.result(L1_mult_wires_1)
);
multiplier_with_reg L1_mul_2(
.dataa (L0_output_wires_2),
.datab (COEFFICIENT_2),
.result(L1_mult_wires_2)
);
multiplier_with_reg L1_mul_3(
.dataa (L0_output_wires_3),
.datab (COEFFICIENT_3),
.result(L1_mult_wires_3)
);
multiplier_with_reg L1_mul_4(
.dataa (L0_output_wires_4),
.datab (COEFFICIENT_4),
.result(L1_mult_wires_4)
);
multiplier_with_reg L1_mul_5(
.dataa (L0_output_wires_5),
.datab (COEFFICIENT_5),
.result(L1_mult_wires_5)
);
multiplier_with_reg L1_mul_6(
.dataa (L0_output_wires_6),
.datab (COEFFICIENT_6),
.result(L1_mult_wires_6)
);
multiplier_with_reg L1_mul_7(
.dataa (L0_output_wires_7),
.datab (COEFFICIENT_7),
.result(L1_mult_wires_7)
);
multiplier_with_reg L1_mul_8(
.dataa (L0_output_wires_8),
.datab (COEFFICIENT_8),
.result(L1_mult_wires_8)
);
multiplier_with_reg L1_mul_9(
.dataa (L0_output_wires_9),
.datab (COEFFICIENT_9),
.result(L1_mult_wires_9)
);
multiplier_with_reg L1_mul_10(
.dataa (L0_output_wires_10),
.datab (COEFFICIENT_10),
.result(L1_mult_wires_10)
);
// (11 Multipliers)
// **************** Adders **************** \\
wire [dw-1:0] L1_output_wires_0;
wire [dw-1:0] L1_output_wires_1;
wire [dw-1:0] L1_output_wires_2;
wire [dw-1:0] L1_output_wires_3;
wire [dw-1:0] L1_output_wires_4;
wire [dw-1:0] L1_output_wires_5;
adder_with_1_reg L1_adder_0and1(
.dataa (L1_mult_wires_0),
.datab (L1_mult_wires_1),
.result(L1_output_wires_0)
);
adder_with_1_reg L1_adder_2and3(
.dataa (L1_mult_wires_2),
.datab (L1_mult_wires_3),
.result(L1_output_wires_1)
);
adder_with_1_reg L1_adder_4and5(
.dataa (L1_mult_wires_4),
.datab (L1_mult_wires_5),
.result(L1_output_wires_2)
);
adder_with_1_reg L1_adder_6and7(
.dataa (L1_mult_wires_6),
.datab (L1_mult_wires_7),
.result(L1_output_wires_3)
);
adder_with_1_reg L1_adder_8and9(
.dataa (L1_mult_wires_8),
.datab (L1_mult_wires_9),
.result(L1_output_wires_4)
);
// (5 main tree Adders)
// ********* Byes ******** \\
one_register L1_byereg_for_10(
.dataa (L1_mult_wires_10),
.result(L1_output_wires_5)
);
// (1 byes)
// ************************* LEVEL 2 ************************* \\
wire [dw-1:0] L2_output_wires_0;
wire [dw-1:0] L2_output_wires_1;
wire [dw-1:0] L2_output_wires_2;
adder_with_1_reg L2_adder_0and1(
.dataa (L1_output_wires_0),
.datab (L1_output_wires_1),
.result(L2_output_wires_0)
);
adder_with_1_reg L2_adder_2and3(
.dataa (L1_output_wires_2),
.datab (L1_output_wires_3),
.result(L2_output_wires_1)
);
adder_with_1_reg L2_adder_4and5(
.dataa (L1_output_wires_4),
.datab (L1_output_wires_5),
.result(L2_output_wires_2)
);
// (3 main tree Adders)
// ************************* LEVEL 3 ************************* \\
wire [dw-1:0] L3_output_wires_0;
wire [dw-1:0] L3_output_wires_1;
adder_with_1_reg L3_adder_0and1(
.dataa (L2_output_wires_0),
.datab (L2_output_wires_1),
.result(L3_output_wires_0)
);
// (1 main tree Adders)
// ********* Byes ******** \\
one_register L3_byereg_for_2(
.dataa (L2_output_wires_2),
.result(L3_output_wires_1)
);
// (1 byes)
// ************************* LEVEL 4 ************************* \\
wire [dw-1:0] L4_output_wires_0;
adder_with_1_reg L4_adder_0and1(
.dataa (L3_output_wires_0),
.datab (L3_output_wires_1),
.result(L4_output_wires_0)
);
// (1 main tree Adders)
////******************************************************
// *
// * Output Logic
// *
// *****************************************************
//Actual outputs
reg [17:0] o_out;
always @(posedge clk) begin
if(clk_ena) begin
o_out <= L4_output_wires_0;
end
end
assign o_valid = VALID_PIPELINE_REGS[N_VALID_REGS-1];
endmodule
module input_pipeline (
clk,
clk_ena,
in_stream,
pipeline_reg_0,
pipeline_reg_1,
pipeline_reg_2,
pipeline_reg_3,
pipeline_reg_4,
pipeline_reg_5,
pipeline_reg_6,
pipeline_reg_7,
pipeline_reg_8,
pipeline_reg_9,
pipeline_reg_10,
pipeline_reg_11,
pipeline_reg_12,
pipeline_reg_13,
pipeline_reg_14,
pipeline_reg_15,
pipeline_reg_16,
pipeline_reg_17,
pipeline_reg_18,
pipeline_reg_19,
pipeline_reg_20,
pipeline_reg_21,
reset);
parameter WIDTH = 1;
//Input value registers
input clk;
input clk_ena;
input [WIDTH-1:0] in_stream;
output [WIDTH-1:0] pipeline_reg_0;
output [WIDTH-1:0] pipeline_reg_1;
output [WIDTH-1:0] pipeline_reg_2;
output [WIDTH-1:0] pipeline_reg_3;
output [WIDTH-1:0] pipeline_reg_4;
output [WIDTH-1:0] pipeline_reg_5;
output [WIDTH-1:0] pipeline_reg_6;
output [WIDTH-1:0] pipeline_reg_7;
output [WIDTH-1:0] pipeline_reg_8;
output [WIDTH-1:0] pipeline_reg_9;
output [WIDTH-1:0] pipeline_reg_10;
output [WIDTH-1:0] pipeline_reg_11;
output [WIDTH-1:0] pipeline_reg_12;
output [WIDTH-1:0] pipeline_reg_13;
output [WIDTH-1:0] pipeline_reg_14;
output [WIDTH-1:0] pipeline_reg_15;
output [WIDTH-1:0] pipeline_reg_16;
output [WIDTH-1:0] pipeline_reg_17;
output [WIDTH-1:0] pipeline_reg_18;
output [WIDTH-1:0] pipeline_reg_19;
output [WIDTH-1:0] pipeline_reg_20;
output [WIDTH-1:0] pipeline_reg_21;
reg [WIDTH-1:0] pipeline_reg_0;
reg [WIDTH-1:0] pipeline_reg_1;
reg [WIDTH-1:0] pipeline_reg_2;
reg [WIDTH-1:0] pipeline_reg_3;
reg [WIDTH-1:0] pipeline_reg_4;
reg [WIDTH-1:0] pipeline_reg_5;
reg [WIDTH-1:0] pipeline_reg_6;
reg [WIDTH-1:0] pipeline_reg_7;
reg [WIDTH-1:0] pipeline_reg_8;
reg [WIDTH-1:0] pipeline_reg_9;
reg [WIDTH-1:0] pipeline_reg_10;
reg [WIDTH-1:0] pipeline_reg_11;
reg [WIDTH-1:0] pipeline_reg_12;
reg [WIDTH-1:0] pipeline_reg_13;
reg [WIDTH-1:0] pipeline_reg_14;
reg [WIDTH-1:0] pipeline_reg_15;
reg [WIDTH-1:0] pipeline_reg_16;
reg [WIDTH-1:0] pipeline_reg_17;
reg [WIDTH-1:0] pipeline_reg_18;
reg [WIDTH-1:0] pipeline_reg_19;
reg [WIDTH-1:0] pipeline_reg_20;
reg [WIDTH-1:0] pipeline_reg_21;
input reset;
always@(posedge clk or posedge reset) begin
if(reset) begin
pipeline_reg_0 <= 0;
pipeline_reg_1 <= 0;
pipeline_reg_2 <= 0;
pipeline_reg_3 <= 0;
pipeline_reg_4 <= 0;
pipeline_reg_5 <= 0;
pipeline_reg_6 <= 0;
pipeline_reg_7 <= 0;
pipeline_reg_8 <= 0;
pipeline_reg_9 <= 0;
pipeline_reg_10 <= 0;
pipeline_reg_11 <= 0;
pipeline_reg_12 <= 0;
pipeline_reg_13 <= 0;
pipeline_reg_14 <= 0;
pipeline_reg_15 <= 0;
pipeline_reg_16 <= 0;
pipeline_reg_17 <= 0;
pipeline_reg_18 <= 0;
pipeline_reg_19 <= 0;
pipeline_reg_20 <= 0;
pipeline_reg_21 <= 0;
end else begin
if(clk_ena) begin
pipeline_reg_0 <= in_stream;
pipeline_reg_1 <= pipeline_reg_0;
pipeline_reg_2 <= pipeline_reg_1;
pipeline_reg_3 <= pipeline_reg_2;
pipeline_reg_4 <= pipeline_reg_3;
pipeline_reg_5 <= pipeline_reg_4;
pipeline_reg_6 <= pipeline_reg_5;
pipeline_reg_7 <= pipeline_reg_6;
pipeline_reg_8 <= pipeline_reg_7;
pipeline_reg_9 <= pipeline_reg_8;
pipeline_reg_10 <= pipeline_reg_9;
pipeline_reg_11 <= pipeline_reg_10;
pipeline_reg_12 <= pipeline_reg_11;
pipeline_reg_13 <= pipeline_reg_12;
pipeline_reg_14 <= pipeline_reg_13;
pipeline_reg_15 <= pipeline_reg_14;
pipeline_reg_16 <= pipeline_reg_15;
pipeline_reg_17 <= pipeline_reg_16;
pipeline_reg_18 <= pipeline_reg_17;
pipeline_reg_19 <= pipeline_reg_18;
pipeline_reg_20 <= pipeline_reg_19;
pipeline_reg_21 <= pipeline_reg_20;
end //else begin
//pipeline_reg_0 <= pipeline_reg_0;
//pipeline_reg_1 <= pipeline_reg_1;
//pipeline_reg_2 <= pipeline_reg_2;
//pipeline_reg_3 <= pipeline_reg_3;
//pipeline_reg_4 <= pipeline_reg_4;
//pipeline_reg_5 <= pipeline_reg_5;
//pipeline_reg_6 <= pipeline_reg_6;
//pipeline_reg_7 <= pipeline_reg_7;
//pipeline_reg_8 <= pipeline_reg_8;
//pipeline_reg_9 <= pipeline_reg_9;
//pipeline_reg_10 <= pipeline_reg_10;
//pipeline_reg_11 <= pipeline_reg_11;
//pipeline_reg_12 <= pipeline_reg_12;
//pipeline_reg_13 <= pipeline_reg_13;
//pipeline_reg_14 <= pipeline_reg_14;
//pipeline_reg_15 <= pipeline_reg_15;
//pipeline_reg_16 <= pipeline_reg_16;
//pipeline_reg_17 <= pipeline_reg_17;
//pipeline_reg_18 <= pipeline_reg_18;
//pipeline_reg_19 <= pipeline_reg_19;
//pipeline_reg_20 <= pipeline_reg_20;
//pipeline_reg_21 <= pipeline_reg_21;
//end
end
end
endmodule
module adder_with_1_reg (
dataa,
datab,
result);
input clk;
input clk_ena;
input [17:0] dataa;
input [17:0] datab;
output [17:0] result;
assign result = dataa + datab;
endmodule
module multiplier_with_reg (
dataa,
datab,
result);
input clk;
input clk_ena;
input [17:0] dataa;
input [17:0] datab;
output [17:0] result;
assign result = dataa * datab;
endmodule
module one_register (
dataa,
result);
input clk;
input clk_ena;
input [17:0] dataa;
output [17:0] result;
assign result = dataa;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2008 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [7:0] sel = crc[7:0];
wire [255+3:0] in = {crc[2:0],crc,crc,crc,crc};
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [3:0] out; // From test of Test.v
// End of automatics
/* Test AUTO_TEMPLATE (
.i\([0-9]+\) (in[\1 +:4]),
); */
Test test (/*AUTOINST*/
// Outputs
.out (out[3:0]),
// Inputs
.sel (sel[7:0]),
.i0 (in[0 +:4]), // Templated
.i1 (in[1 +:4]), // Templated
.i2 (in[2 +:4]), // Templated
.i3 (in[3 +:4]), // Templated
.i4 (in[4 +:4]), // Templated
.i5 (in[5 +:4]), // Templated
.i6 (in[6 +:4]), // Templated
.i7 (in[7 +:4]), // Templated
.i8 (in[8 +:4]), // Templated
.i9 (in[9 +:4]), // Templated
.i10 (in[10 +:4]), // Templated
.i11 (in[11 +:4]), // Templated
.i12 (in[12 +:4]), // Templated
.i13 (in[13 +:4]), // Templated
.i14 (in[14 +:4]), // Templated
.i15 (in[15 +:4]), // Templated
.i16 (in[16 +:4]), // Templated
.i17 (in[17 +:4]), // Templated
.i18 (in[18 +:4]), // Templated
.i19 (in[19 +:4]), // Templated
.i20 (in[20 +:4]), // Templated
.i21 (in[21 +:4]), // Templated
.i22 (in[22 +:4]), // Templated
.i23 (in[23 +:4]), // Templated
.i24 (in[24 +:4]), // Templated
.i25 (in[25 +:4]), // Templated
.i26 (in[26 +:4]), // Templated
.i27 (in[27 +:4]), // Templated
.i28 (in[28 +:4]), // Templated
.i29 (in[29 +:4]), // Templated
.i30 (in[30 +:4]), // Templated
.i31 (in[31 +:4]), // Templated
.i32 (in[32 +:4]), // Templated
.i33 (in[33 +:4]), // Templated
.i34 (in[34 +:4]), // Templated
.i35 (in[35 +:4]), // Templated
.i36 (in[36 +:4]), // Templated
.i37 (in[37 +:4]), // Templated
.i38 (in[38 +:4]), // Templated
.i39 (in[39 +:4]), // Templated
.i40 (in[40 +:4]), // Templated
.i41 (in[41 +:4]), // Templated
.i42 (in[42 +:4]), // Templated
.i43 (in[43 +:4]), // Templated
.i44 (in[44 +:4]), // Templated
.i45 (in[45 +:4]), // Templated
.i46 (in[46 +:4]), // Templated
.i47 (in[47 +:4]), // Templated
.i48 (in[48 +:4]), // Templated
.i49 (in[49 +:4]), // Templated
.i50 (in[50 +:4]), // Templated
.i51 (in[51 +:4]), // Templated
.i52 (in[52 +:4]), // Templated
.i53 (in[53 +:4]), // Templated
.i54 (in[54 +:4]), // Templated
.i55 (in[55 +:4]), // Templated
.i56 (in[56 +:4]), // Templated
.i57 (in[57 +:4]), // Templated
.i58 (in[58 +:4]), // Templated
.i59 (in[59 +:4]), // Templated
.i60 (in[60 +:4]), // Templated
.i61 (in[61 +:4]), // Templated
.i62 (in[62 +:4]), // Templated
.i63 (in[63 +:4]), // Templated
.i64 (in[64 +:4]), // Templated
.i65 (in[65 +:4]), // Templated
.i66 (in[66 +:4]), // Templated
.i67 (in[67 +:4]), // Templated
.i68 (in[68 +:4]), // Templated
.i69 (in[69 +:4]), // Templated
.i70 (in[70 +:4]), // Templated
.i71 (in[71 +:4]), // Templated
.i72 (in[72 +:4]), // Templated
.i73 (in[73 +:4]), // Templated
.i74 (in[74 +:4]), // Templated
.i75 (in[75 +:4]), // Templated
.i76 (in[76 +:4]), // Templated
.i77 (in[77 +:4]), // Templated
.i78 (in[78 +:4]), // Templated
.i79 (in[79 +:4]), // Templated
.i80 (in[80 +:4]), // Templated
.i81 (in[81 +:4]), // Templated
.i82 (in[82 +:4]), // Templated
.i83 (in[83 +:4]), // Templated
.i84 (in[84 +:4]), // Templated
.i85 (in[85 +:4]), // Templated
.i86 (in[86 +:4]), // Templated
.i87 (in[87 +:4]), // Templated
.i88 (in[88 +:4]), // Templated
.i89 (in[89 +:4]), // Templated
.i90 (in[90 +:4]), // Templated
.i91 (in[91 +:4]), // Templated
.i92 (in[92 +:4]), // Templated
.i93 (in[93 +:4]), // Templated
.i94 (in[94 +:4]), // Templated
.i95 (in[95 +:4]), // Templated
.i96 (in[96 +:4]), // Templated
.i97 (in[97 +:4]), // Templated
.i98 (in[98 +:4]), // Templated
.i99 (in[99 +:4]), // Templated
.i100 (in[100 +:4]), // Templated
.i101 (in[101 +:4]), // Templated
.i102 (in[102 +:4]), // Templated
.i103 (in[103 +:4]), // Templated
.i104 (in[104 +:4]), // Templated
.i105 (in[105 +:4]), // Templated
.i106 (in[106 +:4]), // Templated
.i107 (in[107 +:4]), // Templated
.i108 (in[108 +:4]), // Templated
.i109 (in[109 +:4]), // Templated
.i110 (in[110 +:4]), // Templated
.i111 (in[111 +:4]), // Templated
.i112 (in[112 +:4]), // Templated
.i113 (in[113 +:4]), // Templated
.i114 (in[114 +:4]), // Templated
.i115 (in[115 +:4]), // Templated
.i116 (in[116 +:4]), // Templated
.i117 (in[117 +:4]), // Templated
.i118 (in[118 +:4]), // Templated
.i119 (in[119 +:4]), // Templated
.i120 (in[120 +:4]), // Templated
.i121 (in[121 +:4]), // Templated
.i122 (in[122 +:4]), // Templated
.i123 (in[123 +:4]), // Templated
.i124 (in[124 +:4]), // Templated
.i125 (in[125 +:4]), // Templated
.i126 (in[126 +:4]), // Templated
.i127 (in[127 +:4]), // Templated
.i128 (in[128 +:4]), // Templated
.i129 (in[129 +:4]), // Templated
.i130 (in[130 +:4]), // Templated
.i131 (in[131 +:4]), // Templated
.i132 (in[132 +:4]), // Templated
.i133 (in[133 +:4]), // Templated
.i134 (in[134 +:4]), // Templated
.i135 (in[135 +:4]), // Templated
.i136 (in[136 +:4]), // Templated
.i137 (in[137 +:4]), // Templated
.i138 (in[138 +:4]), // Templated
.i139 (in[139 +:4]), // Templated
.i140 (in[140 +:4]), // Templated
.i141 (in[141 +:4]), // Templated
.i142 (in[142 +:4]), // Templated
.i143 (in[143 +:4]), // Templated
.i144 (in[144 +:4]), // Templated
.i145 (in[145 +:4]), // Templated
.i146 (in[146 +:4]), // Templated
.i147 (in[147 +:4]), // Templated
.i148 (in[148 +:4]), // Templated
.i149 (in[149 +:4]), // Templated
.i150 (in[150 +:4]), // Templated
.i151 (in[151 +:4]), // Templated
.i152 (in[152 +:4]), // Templated
.i153 (in[153 +:4]), // Templated
.i154 (in[154 +:4]), // Templated
.i155 (in[155 +:4]), // Templated
.i156 (in[156 +:4]), // Templated
.i157 (in[157 +:4]), // Templated
.i158 (in[158 +:4]), // Templated
.i159 (in[159 +:4]), // Templated
.i160 (in[160 +:4]), // Templated
.i161 (in[161 +:4]), // Templated
.i162 (in[162 +:4]), // Templated
.i163 (in[163 +:4]), // Templated
.i164 (in[164 +:4]), // Templated
.i165 (in[165 +:4]), // Templated
.i166 (in[166 +:4]), // Templated
.i167 (in[167 +:4]), // Templated
.i168 (in[168 +:4]), // Templated
.i169 (in[169 +:4]), // Templated
.i170 (in[170 +:4]), // Templated
.i171 (in[171 +:4]), // Templated
.i172 (in[172 +:4]), // Templated
.i173 (in[173 +:4]), // Templated
.i174 (in[174 +:4]), // Templated
.i175 (in[175 +:4]), // Templated
.i176 (in[176 +:4]), // Templated
.i177 (in[177 +:4]), // Templated
.i178 (in[178 +:4]), // Templated
.i179 (in[179 +:4]), // Templated
.i180 (in[180 +:4]), // Templated
.i181 (in[181 +:4]), // Templated
.i182 (in[182 +:4]), // Templated
.i183 (in[183 +:4]), // Templated
.i184 (in[184 +:4]), // Templated
.i185 (in[185 +:4]), // Templated
.i186 (in[186 +:4]), // Templated
.i187 (in[187 +:4]), // Templated
.i188 (in[188 +:4]), // Templated
.i189 (in[189 +:4]), // Templated
.i190 (in[190 +:4]), // Templated
.i191 (in[191 +:4]), // Templated
.i192 (in[192 +:4]), // Templated
.i193 (in[193 +:4]), // Templated
.i194 (in[194 +:4]), // Templated
.i195 (in[195 +:4]), // Templated
.i196 (in[196 +:4]), // Templated
.i197 (in[197 +:4]), // Templated
.i198 (in[198 +:4]), // Templated
.i199 (in[199 +:4]), // Templated
.i200 (in[200 +:4]), // Templated
.i201 (in[201 +:4]), // Templated
.i202 (in[202 +:4]), // Templated
.i203 (in[203 +:4]), // Templated
.i204 (in[204 +:4]), // Templated
.i205 (in[205 +:4]), // Templated
.i206 (in[206 +:4]), // Templated
.i207 (in[207 +:4]), // Templated
.i208 (in[208 +:4]), // Templated
.i209 (in[209 +:4]), // Templated
.i210 (in[210 +:4]), // Templated
.i211 (in[211 +:4]), // Templated
.i212 (in[212 +:4]), // Templated
.i213 (in[213 +:4]), // Templated
.i214 (in[214 +:4]), // Templated
.i215 (in[215 +:4]), // Templated
.i216 (in[216 +:4]), // Templated
.i217 (in[217 +:4]), // Templated
.i218 (in[218 +:4]), // Templated
.i219 (in[219 +:4]), // Templated
.i220 (in[220 +:4]), // Templated
.i221 (in[221 +:4]), // Templated
.i222 (in[222 +:4]), // Templated
.i223 (in[223 +:4]), // Templated
.i224 (in[224 +:4]), // Templated
.i225 (in[225 +:4]), // Templated
.i226 (in[226 +:4]), // Templated
.i227 (in[227 +:4]), // Templated
.i228 (in[228 +:4]), // Templated
.i229 (in[229 +:4]), // Templated
.i230 (in[230 +:4]), // Templated
.i231 (in[231 +:4]), // Templated
.i232 (in[232 +:4]), // Templated
.i233 (in[233 +:4]), // Templated
.i234 (in[234 +:4]), // Templated
.i235 (in[235 +:4]), // Templated
.i236 (in[236 +:4]), // Templated
.i237 (in[237 +:4]), // Templated
.i238 (in[238 +:4]), // Templated
.i239 (in[239 +:4]), // Templated
.i240 (in[240 +:4]), // Templated
.i241 (in[241 +:4]), // Templated
.i242 (in[242 +:4]), // Templated
.i243 (in[243 +:4]), // Templated
.i244 (in[244 +:4]), // Templated
.i245 (in[245 +:4]), // Templated
.i246 (in[246 +:4]), // Templated
.i247 (in[247 +:4]), // Templated
.i248 (in[248 +:4]), // Templated
.i249 (in[249 +:4]), // Templated
.i250 (in[250 +:4]), // Templated
.i251 (in[251 +:4]), // Templated
.i252 (in[252 +:4]), // Templated
.i253 (in[253 +:4]), // Templated
.i254 (in[254 +:4]), // Templated
.i255 (in[255 +:4])); // Templated
// Aggregate outputs into a single result vector
wire [63:0] result = {60'h0, out};
// What checksum will we end up with
`define EXPECTED_SUM 64'h36f3051d15caf07a
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test
( output wire [3:0] out,
input [7:0] sel,
input [3:0] i0, i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, i11, i12, i13, i14, i15, i16,
i17, i18, i19, i20, i21, i22, i23, i24, i25, i26, i27, i28, i29, i30, i31, i32, i33,
i34, i35, i36, i37, i38, i39, i40, i41, i42, i43, i44, i45, i46, i47, i48, i49, i50,
i51, i52, i53, i54, i55, i56, i57, i58, i59, i60, i61, i62, i63, i64, i65, i66, i67,
i68, i69, i70, i71, i72, i73, i74, i75, i76, i77, i78, i79, i80, i81, i82, i83, i84,
i85, i86, i87, i88, i89, i90, i91, i92, i93, i94, i95, i96, i97, i98, i99, i100, i101,
i102, i103, i104, i105, i106, i107, i108, i109, i110, i111, i112, i113, i114, i115,
i116, i117, i118, i119, i120, i121, i122, i123, i124, i125, i126, i127, i128, i129,
i130, i131, i132, i133, i134, i135, i136, i137, i138, i139, i140, i141, i142, i143,
i144, i145, i146, i147, i148, i149, i150, i151, i152, i153, i154, i155, i156, i157,
i158, i159, i160, i161, i162, i163, i164, i165, i166, i167, i168, i169, i170, i171,
i172, i173, i174, i175, i176, i177, i178, i179, i180, i181, i182, i183, i184, i185,
i186, i187, i188, i189, i190, i191, i192, i193, i194, i195, i196, i197, i198, i199,
i200, i201, i202, i203, i204, i205, i206, i207, i208, i209, i210, i211, i212, i213,
i214, i215, i216, i217, i218, i219, i220, i221, i222, i223, i224, i225, i226, i227,
i228, i229, i230, i231, i232, i233, i234, i235, i236, i237, i238, i239, i240, i241,
i242, i243, i244, i245, i246, i247, i248, i249, i250, i251, i252, i253, i254, i255
);
assign out
= (sel==8'h00) ? i0 : (sel==8'h01) ? i1 : (sel==8'h02) ? i2 : (sel==8'h03) ? i3
: (sel==8'h04) ? i4 : (sel==8'h05) ? i5 : (sel==8'h06) ? i6 : (sel==8'h07) ? i7
: (sel==8'h08) ? i8 : (sel==8'h09) ? i9 : (sel==8'h0a) ? i10 : (sel==8'h0b) ? i11
: (sel==8'h0c) ? i12 : (sel==8'h0d) ? i13 : (sel==8'h0e) ? i14 : (sel==8'h0f) ? i15
: (sel==8'h10) ? i16 : (sel==8'h11) ? i17 : (sel==8'h12) ? i18 : (sel==8'h13) ? i19
: (sel==8'h14) ? i20 : (sel==8'h15) ? i21 : (sel==8'h16) ? i22 : (sel==8'h17) ? i23
: (sel==8'h18) ? i24 : (sel==8'h19) ? i25 : (sel==8'h1a) ? i26 : (sel==8'h1b) ? i27
: (sel==8'h1c) ? i28 : (sel==8'h1d) ? i29 : (sel==8'h1e) ? i30 : (sel==8'h1f) ? i31
: (sel==8'h20) ? i32 : (sel==8'h21) ? i33 : (sel==8'h22) ? i34 : (sel==8'h23) ? i35
: (sel==8'h24) ? i36 : (sel==8'h25) ? i37 : (sel==8'h26) ? i38 : (sel==8'h27) ? i39
: (sel==8'h28) ? i40 : (sel==8'h29) ? i41 : (sel==8'h2a) ? i42 : (sel==8'h2b) ? i43
: (sel==8'h2c) ? i44 : (sel==8'h2d) ? i45 : (sel==8'h2e) ? i46 : (sel==8'h2f) ? i47
: (sel==8'h30) ? i48 : (sel==8'h31) ? i49 : (sel==8'h32) ? i50 : (sel==8'h33) ? i51
: (sel==8'h34) ? i52 : (sel==8'h35) ? i53 : (sel==8'h36) ? i54 : (sel==8'h37) ? i55
: (sel==8'h38) ? i56 : (sel==8'h39) ? i57 : (sel==8'h3a) ? i58 : (sel==8'h3b) ? i59
: (sel==8'h3c) ? i60 : (sel==8'h3d) ? i61 : (sel==8'h3e) ? i62 : (sel==8'h3f) ? i63
: (sel==8'h40) ? i64 : (sel==8'h41) ? i65 : (sel==8'h42) ? i66 : (sel==8'h43) ? i67
: (sel==8'h44) ? i68 : (sel==8'h45) ? i69 : (sel==8'h46) ? i70 : (sel==8'h47) ? i71
: (sel==8'h48) ? i72 : (sel==8'h49) ? i73 : (sel==8'h4a) ? i74 : (sel==8'h4b) ? i75
: (sel==8'h4c) ? i76 : (sel==8'h4d) ? i77 : (sel==8'h4e) ? i78 : (sel==8'h4f) ? i79
: (sel==8'h50) ? i80 : (sel==8'h51) ? i81 : (sel==8'h52) ? i82 : (sel==8'h53) ? i83
: (sel==8'h54) ? i84 : (sel==8'h55) ? i85 : (sel==8'h56) ? i86 : (sel==8'h57) ? i87
: (sel==8'h58) ? i88 : (sel==8'h59) ? i89 : (sel==8'h5a) ? i90 : (sel==8'h5b) ? i91
: (sel==8'h5c) ? i92 : (sel==8'h5d) ? i93 : (sel==8'h5e) ? i94 : (sel==8'h5f) ? i95
: (sel==8'h60) ? i96 : (sel==8'h61) ? i97 : (sel==8'h62) ? i98 : (sel==8'h63) ? i99
: (sel==8'h64) ? i100 : (sel==8'h65) ? i101 : (sel==8'h66) ? i102 : (sel==8'h67) ? i103
: (sel==8'h68) ? i104 : (sel==8'h69) ? i105 : (sel==8'h6a) ? i106 : (sel==8'h6b) ? i107
: (sel==8'h6c) ? i108 : (sel==8'h6d) ? i109 : (sel==8'h6e) ? i110 : (sel==8'h6f) ? i111
: (sel==8'h70) ? i112 : (sel==8'h71) ? i113 : (sel==8'h72) ? i114 : (sel==8'h73) ? i115
: (sel==8'h74) ? i116 : (sel==8'h75) ? i117 : (sel==8'h76) ? i118 : (sel==8'h77) ? i119
: (sel==8'h78) ? i120 : (sel==8'h79) ? i121 : (sel==8'h7a) ? i122 : (sel==8'h7b) ? i123
: (sel==8'h7c) ? i124 : (sel==8'h7d) ? i125 : (sel==8'h7e) ? i126 : (sel==8'h7f) ? i127
: (sel==8'h80) ? i128 : (sel==8'h81) ? i129 : (sel==8'h82) ? i130 : (sel==8'h83) ? i131
: (sel==8'h84) ? i132 : (sel==8'h85) ? i133 : (sel==8'h86) ? i134 : (sel==8'h87) ? i135
: (sel==8'h88) ? i136 : (sel==8'h89) ? i137 : (sel==8'h8a) ? i138 : (sel==8'h8b) ? i139
: (sel==8'h8c) ? i140 : (sel==8'h8d) ? i141 : (sel==8'h8e) ? i142 : (sel==8'h8f) ? i143
: (sel==8'h90) ? i144 : (sel==8'h91) ? i145 : (sel==8'h92) ? i146 : (sel==8'h93) ? i147
: (sel==8'h94) ? i148 : (sel==8'h95) ? i149 : (sel==8'h96) ? i150 : (sel==8'h98) ? i151
: (sel==8'h99) ? i152 : (sel==8'h9a) ? i153 : (sel==8'h9b) ? i154 : (sel==8'h9c) ? i155
: (sel==8'h9d) ? i156 : (sel==8'h9e) ? i157 : (sel==8'h9f) ? i158 : (sel==8'ha0) ? i159
: (sel==8'ha1) ? i160 : (sel==8'ha2) ? i161 : (sel==8'ha3) ? i162 : (sel==8'ha4) ? i163
: (sel==8'ha5) ? i164 : (sel==8'ha6) ? i165 : (sel==8'ha7) ? i166 : (sel==8'ha8) ? i167
: (sel==8'ha9) ? i168 : (sel==8'haa) ? i169 : (sel==8'hab) ? i170 : (sel==8'hac) ? i171
: (sel==8'had) ? i172 : (sel==8'hae) ? i173 : (sel==8'haf) ? i174 : (sel==8'hb0) ? i175
: (sel==8'hb1) ? i176 : (sel==8'hb2) ? i177 : (sel==8'hb3) ? i178 : (sel==8'hb4) ? i179
: (sel==8'hb5) ? i180 : (sel==8'hb6) ? i181 : (sel==8'hb7) ? i182 : (sel==8'hb8) ? i183
: (sel==8'hb9) ? i184 : (sel==8'hba) ? i185 : (sel==8'hbb) ? i186 : (sel==8'hbc) ? i187
: (sel==8'hbd) ? i188 : (sel==8'hbe) ? i189 : (sel==8'hbf) ? i190 : (sel==8'hc0) ? i191
: (sel==8'hc1) ? i192 : (sel==8'hc2) ? i193 : (sel==8'hc3) ? i194 : (sel==8'hc4) ? i195
: (sel==8'hc5) ? i196 : (sel==8'hc6) ? i197 : (sel==8'hc7) ? i198 : (sel==8'hc8) ? i199
: (sel==8'hc9) ? i200 : (sel==8'hca) ? i201 : (sel==8'hcb) ? i202 : (sel==8'hcc) ? i203
: (sel==8'hcd) ? i204 : (sel==8'hce) ? i205 : (sel==8'hcf) ? i206 : (sel==8'hd0) ? i207
: (sel==8'hd1) ? i208 : (sel==8'hd2) ? i209 : (sel==8'hd3) ? i210 : (sel==8'hd4) ? i211
: (sel==8'hd5) ? i212 : (sel==8'hd6) ? i213 : (sel==8'hd7) ? i214 : (sel==8'hd8) ? i215
: (sel==8'hd9) ? i216 : (sel==8'hda) ? i217 : (sel==8'hdb) ? i218 : (sel==8'hdc) ? i219
: (sel==8'hdd) ? i220 : (sel==8'hde) ? i221 : (sel==8'hdf) ? i222 : (sel==8'he0) ? i223
: (sel==8'he1) ? i224 : (sel==8'he2) ? i225 : (sel==8'he3) ? i226 : (sel==8'he4) ? i227
: (sel==8'he5) ? i228 : (sel==8'he6) ? i229 : (sel==8'he7) ? i230 : (sel==8'he8) ? i231
: (sel==8'he9) ? i232 : (sel==8'hea) ? i233 : (sel==8'heb) ? i234 : (sel==8'hec) ? i235
: (sel==8'hed) ? i236 : (sel==8'hee) ? i237 : (sel==8'hef) ? i238 : (sel==8'hf0) ? i239
: (sel==8'hf1) ? i240 : (sel==8'hf2) ? i241 : (sel==8'hf3) ? i242 : (sel==8'hf4) ? i243
: (sel==8'hf5) ? i244 : (sel==8'hf6) ? i245 : (sel==8'hf7) ? i246 : (sel==8'hf8) ? i247
: (sel==8'hf9) ? i248 : (sel==8'hfa) ? i249 : (sel==8'hfb) ? i250 : (sel==8'hfc) ? i251
: (sel==8'hfd) ? i252 : (sel==8'hfe) ? i253 : (sel==8'hff) ? i254 : i255;
endmodule
|
/*
* freq_gen_tb.v: Test bench for freq_gen.v
* author: Till Mahlburg
* year: 2019
* organization: Universität Leipzig
* license: ISC
*
*/
`timescale 1 ns / 1 ps
`ifndef WAIT_INTERVAL
`define WAIT_INTERVAL 1000
`endif
`ifndef M_1000
`define M_1000 1000
`endif
`ifndef D
`define D 1
`endif
`ifndef O_1000
`define O_1000 1000
`endif
module freq_gen_tb ();
reg RST;
reg PWRDWN;
reg period_stable;
reg [31:0] ref_period_length_1000;
reg clk;
wire out;
wire [31:0] out_period_length_1000;
/* resets the high counter module used for frequency checks */
wire [31:0] highs_counted;
integer pass_count;
integer fail_count;
/* adjust according to the number of test cases */
localparam total = 6;
freq_gen dut (
.M_1000(`M_1000),
.D(`D),
.O_1000(`O_1000),
.RST(RST),
.PWRDWN(PWRDWN),
.ref_period_1000(ref_period_length_1000),
.clk(clk),
.out(out),
.out_period_length_1000(out_period_length_1000),
.period_stable(period_stable));
high_counter high_counter (
.clk(out),
.rst(~period_stable),
.count(highs_counted));
initial begin
$dumpfile("freq_gen_tb.vcd");
$dumpvars(0, freq_gen_tb);
RST = 0;
PWRDWN = 0;
period_stable = 0;
clk = 0;
ref_period_length_1000 = 20 * 1000;
pass_count = 0;
fail_count = 0;
#10;
RST = 1;
#10;
if (out === 1'b0) begin
$display("PASSED: RST");
pass_count = pass_count + 1;
end else begin
$display("FAILED: RST");
fail_count = fail_count + 1;
end
period_stable = 1;
RST = 0;
#((ref_period_length_1000 / 1000.0) + 11);
if (out === 1'b1) begin
$display("PASSED: rising edge detection");
pass_count = pass_count + 1;
end else begin
$display("FAILED: rising edge detection");
fail_count = fail_count + 1;
end
#(`WAIT_INTERVAL - ((ref_period_length_1000 / 1000.0) + 11));
/* use 1.0 to calculate floating point numbers */
if ($floor(`WAIT_INTERVAL / highs_counted) == $floor((ref_period_length_1000 / 1000.0) * ((`D * (`O_1000 / 1000.0) * 1.0) / (`M_1000 / 1000.0)))) begin
$display("PASSED: ref period = 20");
pass_count = pass_count + 1;
end else begin
$display("FAILED: ref period = 20");
fail_count = fail_count + 1;
end
period_stable = 0;
ref_period_length_1000 = 10 * 1000;
#`WAIT_INTERVAL;
period_stable = 1;
#`WAIT_INTERVAL;
if ($floor(`WAIT_INTERVAL / highs_counted) == $floor((ref_period_length_1000 / 1000.0) * ((`D * (`O_1000 / 1000.0) * 1.0) / (`M_1000 / 1000.0)))) begin
$display("PASSED: ref period = 10");
pass_count = pass_count + 1;
end else begin
$display("FAILED: ref period = 10");
fail_count = fail_count + 1;
end
period_stable = 0;
ref_period_length_1000 = 5600;
#`WAIT_INTERVAL;
period_stable = 1;
#`WAIT_INTERVAL;
if ($floor(`WAIT_INTERVAL / highs_counted) == $floor((ref_period_length_1000 / 1000.0) * ((`D * (`O_1000 / 1000.0) * 1.0) / (`M_1000 / 1000.0)))) begin
$display("PASSED: ref period = 5.6");
pass_count = pass_count + 1;
end else begin
$display("FAILED: ref period = 5.6");
fail_count = fail_count + 1;
end
if ($floor((`WAIT_INTERVAL + (ref_period_length_1000 / 1000.0)) / highs_counted) == $floor(out_period_length_1000 / 1000.0)) begin
$display("PASSED: period length output");
pass_count = pass_count + 1;
end else begin
$display("FAILED: period length output");
fail_count = fail_count + 1;
end
if ((pass_count + fail_count) == total) begin
$display("PASSED: number of test cases");
pass_count = pass_count + 1;
end else begin
$display("FAILED: number of test cases");
fail_count = fail_count + 1;
end
$display("%0d/%0d PASSED", pass_count, (total + 1));
$finish;
end
always #((ref_period_length_1000 / 1000.0) / 2.0) clk <= ~clk;
endmodule
|
//date:2016/3/13
//engineer:ZhaiShaoMin
//module name: pipeline register between id and ex
module core_id_ex(//input
clk,
rst,
// inst_lo,
wb_reg_write,
wb_memtoreg,
mem_memread,
mem_memwrite,
mem_ll_mem,
mem_sc_mem,
regdst,
aluop,
alusrc,
regread1,
regread2,
sign_extend,
reg_rs,
reg_rt,
reg_rd,
//output
// ex_inst_lo,
ex_wb_reg_write,
ex_wb_memtoreg,
ex_mem_memread,
ex_mem_memwrite,
ex_mem_ll_mem,
ex_mem_sc_mem,
ex_regdst,
ex_aluop,
ex_alusrc,
ex_regread1,
ex_regread2,
ex_sign_extend,
ex_reg_rs,
ex_reg_rt,
ex_reg_rd);
//input
input clk;
input rst;
//input [15:0] inst_lo;
input wb_reg_write;
input wb_memtoreg;
input mem_memread;
input mem_memwrite;
input mem_ll_mem;
input mem_sc_mem;
input regdst;
input [1:0] aluop;
input alusrc;
input [31:0] regread1;
input [31:0] regread2;
input [31:0] sign_extend;
input [4:0] reg_rs;
input [4:0] reg_rt;
input [4:0] reg_rd;
//outpu
//output [15:0] ex_inst_lo;
output ex_wb_reg_write;
output ex_wb_memtoreg;
output ex_mem_memread;
output ex_mem_memwrite;
output ex_mem_ll_mem;
output ex_mem_sc_mem;
output ex_regdst;
output [1:0] ex_aluop;
output ex_alusrc;
output [31:0] ex_regread1;
output [31:0] ex_regread2;
output [31:0] ex_sign_extend;
output [4:0] ex_reg_rs;
output [4:0] ex_reg_rt;
output [4:0] ex_reg_rd;
//define regs
//reg [15:0] ex_inst_lo;
reg ex_wb_reg_write;
reg ex_wb_memtoreg;
reg ex_mem_memread;
reg ex_mem_memwrite;
reg ex_mem_ll_mem;
reg ex_mem_sc_mem;
reg ex_regdst;
reg [1:0] ex_aluop;
reg ex_alusrc;
reg [31:0] ex_regread1;
reg [31:0] ex_regread2;
reg [31:0] ex_sign_extend;
reg [4:0] ex_reg_rs;
reg [4:0] ex_reg_rt;
reg [4:0] ex_reg_rd;
always@(posedge clk)
begin
if(rst)
begin
// ex_inst_lo<=15'b000000000000000;
ex_wb_reg_write<=1'b0;
ex_wb_memtoreg<=1'b0;
ex_mem_memread<=1'b0;
ex_mem_memwrite<=1'b0;
ex_mem_ll_mem<=1'b0;
ex_mem_sc_mem<=1'b0;
ex_regdst<=1'b0;
ex_aluop<=2'b00;
ex_alusrc<=1'b0;
ex_regread1<=32'h0000;
ex_regread2<=32'h0000;
ex_sign_extend<=32'h0000;
ex_reg_rs<=5'b00000;
ex_reg_rt<=5'b00000;
ex_reg_rd<=5'b00000;
end
else
begin
// ex_inst_lo<=inst_lo;
ex_wb_reg_write<=wb_reg_write;
ex_wb_memtoreg<=wb_memtoreg;
ex_mem_memread<=mem_memread;
ex_mem_memwrite<=mem_memwrite;
ex_mem_ll_mem<=mem_ll_mem;
ex_mem_sc_mem<=mem_sc_mem;
ex_regdst<=regdst;
ex_aluop<=aluop;
ex_alusrc<=alusrc;
ex_regread1<=regread1;
ex_regread2<=regread2;
ex_sign_extend<=sign_extend;
ex_reg_rs<=reg_rs;
ex_reg_rt<=reg_rt;
ex_reg_rd<=reg_rd;
end
end
endmodule |
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate case/endcase w/ null_statement - no default
module main ();
reg error;
reg [2:0] val1,val2;
reg [2:0] result ;
always @( val1 or val2)
case (val1 & val2 )
3'b000,3'b001: result = 0;
3'b101: ;
3'b011: result = 1;
endcase
initial
begin
error = 0;
val1 = 3'b0;
val2 = 3'b0;
#1 if(result !==0)
begin
$display("FAILED case 3.8C - case (expr) lab1: ");
error = 1;
end
val1 = 3'b111;
val2 = 3'b011;
#1 if(result !==1)
begin
$display("FAILED case 3.8C - case (expr) lab2: ");
error = 1;
end
val2 = 3'b101; // Should activate null statement and get no action
#1 if(result !==1)
begin
$display("FAILED case 3.8C - case (expr) lab1: ");
error = 1;
end
if(error == 0)
$display("PASSED");
end
endmodule // main
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKBUF_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__CLKBUF_FUNCTIONAL_PP_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__clkbuf (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKBUF_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__EBUFN_BLACKBOX_V
`define SKY130_FD_SC_LS__EBUFN_BLACKBOX_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__ebufn (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__EBUFN_BLACKBOX_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Thu May 25 15:17:13 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_vga_pll_0_0/system_vga_pll_0_0_stub.v
// Design : system_vga_pll_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "vga_pll,Vivado 2016.4" *)
module system_vga_pll_0_0(clk_100, clk_50, clk_25, clk_12_5, clk_6_25)
/* synthesis syn_black_box black_box_pad_pin="clk_100,clk_50,clk_25,clk_12_5,clk_6_25" */;
input clk_100;
output clk_50;
output clk_25;
output clk_12_5;
output clk_6_25;
endmodule
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
//------------------------------------------------------------------------------
// SHARED CODE
//------------------------------------------------------------------------------
`ifdef OVL_SHARED_CODE
wire [width-1:0] dec_test_expr = test_expr - {{width-1{1'b0}},1'b1};
wire zoh_test_expr = ((test_expr & dec_test_expr) == {width{1'b0}});
wire valid_test_expr = ((test_expr ^ test_expr) == {width{1'b0}});
`endif
//------------------------------------------------------------------------------
// ASSERTION
//------------------------------------------------------------------------------
`ifdef OVL_ASSERT_ON
// 2-STATE
// =======
wire fire_2state_1;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
end
else begin
if (fire_2state_1) begin
ovl_error_t(`OVL_FIRE_2STATE,"Test expression contains more or less than 1 asserted bits");
end
end
end
assign fire_2state_1 = !zoh_test_expr || (test_expr == {width{1'b0}});
// X-CHECK
// =======
`ifdef OVL_XCHECK_OFF
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
`else
reg fire_xcheck_1;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
end
else begin
if (fire_xcheck_1) begin
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
end
end
end
always @ (valid_test_expr) begin
if (valid_test_expr) begin
fire_xcheck_1 = 1'b0;
end
else begin
fire_xcheck_1 = 1'b1;
end
end
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`endif // OVL_ASSERT_ON
//------------------------------------------------------------------------------
// COVERAGE
//------------------------------------------------------------------------------
`ifdef OVL_COVER_ON
// Auxiliary logic
reg [width-1:0] one_hots_checked;
reg [width-1:0] prev_one_hots_checked;
reg [width-1:0] prev_test_expr;
always @ (posedge clk) begin
prev_test_expr <= test_expr; // deliberately not reset
if (`OVL_RESET_SIGNAL == 1'b0) begin
one_hots_checked <= {width{1'b0}};
prev_one_hots_checked <= {width{1'b0}};
end
else begin
if (valid_test_expr && zoh_test_expr) begin
one_hots_checked <= one_hots_checked | test_expr;
end
prev_one_hots_checked <= one_hots_checked;
end
end
wire fire_cover_1, fire_cover_2;
always @ (posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
end
else begin
if (fire_cover_1) begin
ovl_cover_t("test_expr_change covered"); // sanity
end
if (fire_cover_2) begin
ovl_cover_t("all_one_hots_checked covered"); // corner
end
end
end
assign fire_cover_1 = ((OVL_COVER_SANITY_ON > 0) && (test_expr != prev_test_expr));
assign fire_cover_2 = ((OVL_COVER_CORNER_ON > 0) && (one_hots_checked == {width{1'b1}}) && (one_hots_checked != prev_one_hots_checked));
`endif // OVL_COVER_ON
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ba
//
// Generated
// by: wig
// on: Mon Oct 24 10:52:44 2005
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ba.v,v 1.1 2005/10/25 13:15:35 wig Exp $
// $Date: 2005/10/25 13:15:35 $
// $Log: ent_ba.v,v $
// Revision 1.1 2005/10/25 13:15:35 wig
// Testcase result update
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.62 2005/10/19 15:40:06 wig Exp
//
// Generator: mix_0.pl Revision: 1.38 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of ent_ba
//
// No `defines in this module
module ent_ba
//
// Generated module inst_ba
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of ent_ba
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CONB_1_V
`define SKY130_FD_SC_LP__CONB_1_V
/**
* conb: Constant value, low, high outputs.
*
* Verilog wrapper for conb with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__conb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__conb_1 (
HI ,
LO ,
VPWR,
VGND,
VPB ,
VNB
);
output HI ;
output LO ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__conb base (
.HI(HI),
.LO(LO),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__conb_1 (
HI,
LO
);
output HI;
output LO;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__conb base (
.HI(HI),
.LO(LO)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__CONB_1_V
|
/// date:2016/3/5 3/6 am: 10:57 done!
/// engineer:ZhaiShaoMIn
/// module function:because there are two kinds of uploadregs to
/// OUT_rep: inst_cache ,data_cache and memory, so we need to determine which can be writed into OUT_rep.
module arbiter_for_OUT_rep(//input
clk,
rst,
OUT_rep_rdy,
v_dc_rep,
v_mem_rep,
dc_rep_flit,
mem_rep_flit,
dc_rep_ctrl,
mem_rep_ctrl,
//output
ack_OUT_rep,
ack_dc_rep,
ack_mem_rep,
select // select 1/2
);
//input
input clk;
input rst;
input OUT_rep_rdy;
input v_dc_rep;
input v_mem_rep;
input [15:0] dc_rep_flit;
input [15:0] mem_rep_flit;
input [1:0] dc_rep_ctrl;
input [1:0] mem_rep_ctrl;
//output
output ack_OUT_rep;
output ack_dc_rep;
output ack_mem_rep;
output [1:0] select; // select 1/2
//parameter for fsm state
parameter arbiter_idle=3'b001;
parameter dc_uploading=3'b010;
parameter mem_uploading=3'b100;
//parameter of cmd
parameter nackrep_cmd=5'b10101;
parameter SCflurep_cmd=5'b11100;
reg [2:0] nstate;
reg [2:0] state;
reg priority1;
reg ack_OUT_rep;
reg ack_dc_rep;
reg ack_mem_rep;
reg update_priority;
reg [1:0] select;
/// nstate and output function
always@(*)
begin
nstate=state;
ack_OUT_rep=1'b0;
ack_dc_rep=1'b0;
ack_mem_rep=1'b0;
update_priority=1'b0;
select=2'b00;
case(state)
arbiter_idle:
begin
if({v_dc_rep,v_mem_rep}==2'b11)
begin
update_priority=1'b1;
if(priority1)
begin
nstate=dc_uploading;
end
else
begin
nstate=mem_uploading;
end
end
else if({v_dc_rep,v_mem_rep}==2'b01)
begin
nstate=mem_uploading;
end
else if({v_dc_rep,v_mem_rep}==2'b10)
begin
nstate=dc_uploading;
end
end
dc_uploading:
begin
if(OUT_rep_rdy)
begin
ack_OUT_rep=1'b1;
ack_dc_rep=1'b1;
select=2'b01;
if(dc_rep_ctrl==2'b11||dc_rep_ctrl==2'b01&&(dc_rep_flit[9:5]==SCflurep_cmd||dc_rep_flit[9:5]==nackrep_cmd))
begin
nstate=arbiter_idle;
end
end
end
mem_uploading:
begin
if(OUT_rep_rdy)
begin
ack_OUT_rep=1'b1;
ack_mem_rep=1'b1;
select=2'b10;
if(mem_rep_ctrl==2'b11||mem_rep_ctrl==2'b01&&(mem_rep_flit[9:5]==SCflurep_cmd||mem_rep_flit[9:5]==nackrep_cmd))
begin
nstate=arbiter_idle;
end
end
end
endcase
end
// fsm state reg
always@(posedge clk)
begin
if(rst)
state<=3'b001;
else
state<=nstate;
end
always@(posedge clk)
begin
if(rst)
priority1<=1'b0;
else if(update_priority)
priority1<=~priority1;
end
endmodule
|
(** * Equiv: Program Equivalence *)
Require Export Imp.
(** *** Some general advice for working on exercises:
- Most of the Coq proofs we ask you to do are similar to proofs
that we've provided. Before starting to work on the homework
problems, take the time to work through our proofs (both
informally, on paper, and in Coq) and make sure you understand
them in detail. This will save you a lot of time.
- The Coq proofs we're doing now are sufficiently complicated that
it is more or less impossible to complete them simply by random
experimentation or "following your nose." You need to start
with an idea about why the property is true and how the proof is
going to go. The best way to do this is to write out at least a
sketch of an informal proof on paper -- one that intuitively
convinces you of the truth of the theorem -- before starting to
work on the formal one. Alternately, grab a friend and try to
convince them that the theorem is true; then try to formalize
your explanation.
- Use automation to save work! Some of the proofs in this
chapter's exercises are pretty long if you try to write out all
the cases explicitly. *)
(* ####################################################### *)
(** * Behavioral Equivalence *)
(** In the last chapter, we investigated the correctness of a very
simple program transformation: the [optimize_0plus] function. The
programming language we were considering was the first version of
the language of arithmetic expressions -- with no variables -- so
in that setting it was very easy to define what it _means_ for a
program transformation to be correct: it should always yield a
program that evaluates to the same number as the original.
To go further and talk about the correctness of program
transformations in the full Imp language, we need to consider the
role of variables and state. *)
(* ####################################################### *)
(** ** Definitions *)
(** For [aexp]s and [bexp]s with variables, the definition we want is
clear. We say
that two [aexp]s or [bexp]s are _behaviorally equivalent_ if they
evaluate to the same result _in every state_. *)
Definition aequiv (a1 a2 : aexp) : Prop :=
forall (st:state),
aeval st a1 = aeval st a2.
Definition bequiv (b1 b2 : bexp) : Prop :=
forall (st:state),
beval st b1 = beval st b2.
(** For commands, the situation is a little more subtle. We can't
simply say "two commands are behaviorally equivalent if they
evaluate to the same ending state whenever they are started in the
same initial state," because some commands (in some starting
states) don't terminate in any final state at all! What we need
instead is this: two commands are behaviorally equivalent if, for
any given starting state, they either both diverge or both
terminate in the same final state. A compact way to express this
is "if the first one terminates in a particular state then so does
the second, and vice versa." *)
Definition cequiv (c1 c2 : com) : Prop :=
forall (st st' : state),
(c1 / st || st') <-> (c2 / st || st').
(** **** Exercise: 2 stars (equiv_classes) *)
(** Given the following programs, group together those that are
equivalent in [Imp]. Your answer should be given as a list of
lists, where each sub-list represents a group of equivalent
programs. For example, if you think programs (a) through (h) are
all equivalent to each other, but not to (i), your answer should
look like this:
[ [prog_a;prog_b;prog_c;prog_d;prog_e;prog_f;prog_g;prog_h] ;
[prog_i] ]
Write down your answer below in the definition of [equiv_classes]. *)
Definition prog_a : com :=
WHILE BNot (BLe (AId X) (ANum 0)) DO
X ::= APlus (AId X) (ANum 1)
END.
Definition prog_b : com :=
IFB BEq (AId X) (ANum 0) THEN
X ::= APlus (AId X) (ANum 1);;
Y ::= ANum 1
ELSE
Y ::= ANum 0
FI;;
X ::= AMinus (AId X) (AId Y);;
Y ::= ANum 0.
Definition prog_c : com :=
SKIP.
Definition prog_d : com :=
WHILE BNot (BEq (AId X) (ANum 0)) DO
X ::= APlus (AMult (AId X) (AId Y)) (ANum 1)
END.
Definition prog_e : com :=
Y ::= ANum 0.
Definition prog_f : com :=
Y ::= APlus (AId X) (ANum 1);;
WHILE BNot (BEq (AId X) (AId Y)) DO
Y ::= APlus (AId X) (ANum 1)
END.
Definition prog_g : com :=
WHILE BTrue DO
SKIP
END.
Definition prog_h : com :=
WHILE BNot (BEq (AId X) (AId X)) DO
X ::= APlus (AId X) (ANum 1)
END.
Definition prog_i : com :=
WHILE BNot (BEq (AId X) (AId Y)) DO
X ::= APlus (AId Y) (ANum 1)
END.
Definition equiv_classes : list (list com) :=
[ [prog_b;prog_e] ; (* Y ::= ANum 0. *)
[prog_f;prog_g] ; (* dead loop *)
[prog_c;prog_h] ; (* nothing *)
[prog_a]; [prog_d]; [prog_i]
].
(* GRADE_TEST 2: check_equiv_classes equiv_classes *)
(** [] *)
(* ####################################################### *)
(** ** Examples *)
(** Here are some simple examples of equivalences of arithmetic
and boolean expressions. *)
Theorem aequiv_example:
aequiv (AMinus (AId X) (AId X)) (ANum 0).
Proof.
intros st. simpl. omega.
Qed.
Theorem bequiv_example:
bequiv (BEq (AMinus (AId X) (AId X)) (ANum 0)) BTrue.
Proof.
intros st. unfold beval.
rewrite aequiv_example. reflexivity.
Qed.
(** For examples of command equivalence, let's start by looking at
some trivial program transformations involving [SKIP]: *)
Theorem skip_left: forall c,
cequiv
(SKIP;; c)
c.
Proof.
(* WORKED IN CLASS *)
intros c st st'.
split; intros H.
Case "->".
inversion H. subst.
inversion H2. subst.
assumption.
Case "<-".
apply E_Seq with st.
apply E_Skip.
assumption.
Qed.
(** **** Exercise: 2 stars (skip_right) *)
(** Prove that adding a SKIP after a command results in an equivalent
program *)
Theorem skip_right: forall c,
cequiv
(c;; SKIP)
c.
Proof.
intros c st st'.
split; intros H.
inversion H. subst.
inversion H5. subst.
assumption.
apply E_Seq with st'.
assumption.
apply E_Skip.
Qed.
(** [] *)
(** Similarly, here is a simple transformations that simplifies [IFB]
commands: *)
Theorem IFB_true_simple: forall c1 c2,
cequiv
(IFB BTrue THEN c1 ELSE c2 FI)
c1.
Proof.
intros c1 c2.
split; intros H.
Case "->".
inversion H; subst. assumption. inversion H5.
Case "<-".
apply E_IfTrue. reflexivity. assumption. Qed.
(** Of course, few programmers would be tempted to write a conditional
whose guard is literally [BTrue]. A more interesting case is when
the guard is _equivalent_ to true:
_Theorem_: If [b] is equivalent to [BTrue], then [IFB b THEN c1
ELSE c2 FI] is equivalent to [c1].
*)
(** *** *)
(**
_Proof_:
- ([->]) We must show, for all [st] and [st'], that if [IFB b
THEN c1 ELSE c2 FI / st || st'] then [c1 / st || st'].
Proceed by cases on the rules that could possibly have been
used to show [IFB b THEN c1 ELSE c2 FI / st || st'], namely
[E_IfTrue] and [E_IfFalse].
- Suppose the final rule rule in the derivation of [IFB b THEN
c1 ELSE c2 FI / st || st'] was [E_IfTrue]. We then have, by
the premises of [E_IfTrue], that [c1 / st || st']. This is
exactly what we set out to prove.
- On the other hand, suppose the final rule in the derivation
of [IFB b THEN c1 ELSE c2 FI / st || st'] was [E_IfFalse].
We then know that [beval st b = false] and [c2 / st || st'].
Recall that [b] is equivalent to [BTrue], i.e. forall [st],
[beval st b = beval st BTrue]. In particular, this means
that [beval st b = true], since [beval st BTrue = true]. But
this is a contradiction, since [E_IfFalse] requires that
[beval st b = false]. Thus, the final rule could not have
been [E_IfFalse].
- ([<-]) We must show, for all [st] and [st'], that if [c1 / st
|| st'] then [IFB b THEN c1 ELSE c2 FI / st || st'].
Since [b] is equivalent to [BTrue], we know that [beval st b] =
[beval st BTrue] = [true]. Together with the assumption that
[c1 / st || st'], we can apply [E_IfTrue] to derive [IFB b THEN
c1 ELSE c2 FI / st || st']. []
Here is the formal version of this proof: *)
Theorem IFB_true: forall b c1 c2,
bequiv b BTrue ->
cequiv
(IFB b THEN c1 ELSE c2 FI)
c1.
Proof.
intros b c1 c2 Hb.
split; intros H.
Case "->".
inversion H; subst.
SCase "b evaluates to true".
assumption.
SCase "b evaluates to false (contradiction)".
unfold bequiv in Hb. simpl in Hb.
rewrite Hb in H5.
inversion H5.
Case "<-".
apply E_IfTrue; try assumption.
unfold bequiv in Hb. simpl in Hb.
rewrite Hb. reflexivity. Qed.
(** **** Exercise: 2 stars (IFB_false) *)
Theorem IFB_false: forall b c1 c2,
bequiv b BFalse ->
cequiv
(IFB b THEN c1 ELSE c2 FI)
c2.
Proof.
intros b c1 c2 Hb.
split; intros H.
Case "->".
inversion H; subst.
unfold bequiv in Hb. simpl in Hb.
rewrite Hb in H5. inversion H5.
assumption.
Case "<-".
apply E_IfFalse.
unfold bequiv in Hb. simpl in Hb.
rewrite Hb. reflexivity.
assumption.
Qed.
(** [] *)
(** **** Exercise: 3 stars (swap_if_branches) *)
(** Show that we can swap the branches of an IF by negating its
condition *)
Theorem swap_if_branches: forall b e1 e2,
cequiv
(IFB b THEN e1 ELSE e2 FI)
(IFB BNot b THEN e2 ELSE e1 FI).
Proof.
intros b e1 e2.
split; intros H.
Case "->".
inversion H; subst.
apply E_IfFalse.
simpl. rewrite H5. reflexivity. assumption.
apply E_IfTrue.
simpl. rewrite H5. reflexivity. assumption.
Case "<-".
inversion H; subst.
apply E_IfFalse.
rewrite <-negb_involutive with (beval st b).
simpl in H5. rewrite H5. reflexivity. assumption.
apply E_IfTrue.
rewrite <-negb_involutive with (beval st b).
simpl in H5. rewrite H5. reflexivity. assumption.
Qed.
(** [] *)
(** *** *)
(** For [WHILE] loops, we can give a similar pair of theorems. A loop
whose guard is equivalent to [BFalse] is equivalent to [SKIP],
while a loop whose guard is equivalent to [BTrue] is equivalent to
[WHILE BTrue DO SKIP END] (or any other non-terminating program).
The first of these facts is easy. *)
Theorem WHILE_false : forall b c,
bequiv b BFalse ->
cequiv
(WHILE b DO c END)
SKIP.
Proof.
intros b c Hb. split; intros H.
Case "->".
inversion H; subst.
SCase "E_WhileEnd".
apply E_Skip.
SCase "E_WhileLoop".
rewrite Hb in H2. inversion H2.
Case "<-".
inversion H; subst.
apply E_WhileEnd.
rewrite Hb.
reflexivity. Qed.
(** **** Exercise: 2 stars, advanced, optional (WHILE_false_informal) *)
(** Write an informal proof of [WHILE_false].
(* TODO: informal proof... *)
(* FILL IN HERE *)
[]
*)
(** *** *)
(** To prove the second fact, we need an auxiliary lemma stating that
[WHILE] loops whose guards are equivalent to [BTrue] never
terminate:
_Lemma_: If [b] is equivalent to [BTrue], then it cannot be the
case that [(WHILE b DO c END) / st || st'].
_Proof_: Suppose that [(WHILE b DO c END) / st || st']. We show,
by induction on a derivation of [(WHILE b DO c END) / st || st'],
that this assumption leads to a contradiction.
- Suppose [(WHILE b DO c END) / st || st'] is proved using rule
[E_WhileEnd]. Then by assumption [beval st b = false]. But
this contradicts the assumption that [b] is equivalent to
[BTrue].
- Suppose [(WHILE b DO c END) / st || st'] is proved using rule
[E_WhileLoop]. Then we are given the induction hypothesis
that [(WHILE b DO c END) / st || st'] is contradictory, which
is exactly what we are trying to prove!
- Since these are the only rules that could have been used to
prove [(WHILE b DO c END) / st || st'], the other cases of
the induction are immediately contradictory. [] *)
Lemma WHILE_true_nonterm : forall b c st st',
bequiv b BTrue ->
~( (WHILE b DO c END) / st || st' ).
Proof.
(* WORKED IN CLASS *)
intros b c st st' Hb.
intros H.
remember (WHILE b DO c END) as cw eqn:Heqcw.
ceval_cases (induction H) Case;
(* Most rules don't apply, and we can rule them out
by inversion *)
inversion Heqcw; subst; clear Heqcw.
(* The two interesting cases are the ones for WHILE loops: *)
Case "E_WhileEnd". (* contradictory -- b is always true! *)
unfold bequiv in Hb.
(* [rewrite] is able to instantiate the quantifier in [st] *)
rewrite Hb in H. inversion H.
Case "E_WhileLoop". (* immediate from the IH *)
apply IHceval2. reflexivity. Qed.
(** **** Exercise: 2 stars, optional (WHILE_true_nonterm_informal) *)
(** Explain what the lemma [WHILE_true_nonterm] means in English.
(* TODO: in english ... *)
*)
(** [] *)
(** **** Exercise: 2 stars (WHILE_true) *)
(** Prove the following theorem. _Hint_: You'll want to use
[WHILE_true_nonterm] here. *)
Theorem WHILE_true: forall b c,
bequiv b BTrue ->
cequiv
(WHILE b DO c END)
(WHILE BTrue DO SKIP END).
Proof.
intros b c Hb st st'.
split; intro H.
Case "->".
apply (WHILE_true_nonterm b c st st') in Hb.
contradiction.
Case "<-".
apply ex_falso_quodlibet.
apply (WHILE_true_nonterm BTrue SKIP st st'). (* tricky *)
intro st''. reflexivity.
assumption.
Qed.
(** [] *)
Theorem loop_unrolling: forall b c,
cequiv
(WHILE b DO c END)
(IFB b THEN (c;; WHILE b DO c END) ELSE SKIP FI).
Proof.
(* WORKED IN CLASS *)
intros b c st st'.
split; intros Hce.
Case "->".
inversion Hce; subst.
SCase "loop doesn't run".
apply E_IfFalse. assumption. apply E_Skip.
SCase "loop runs".
apply E_IfTrue. assumption.
apply E_Seq with (st' := st'0). assumption. assumption.
Case "<-".
inversion Hce; subst.
SCase "loop runs".
inversion H5; subst.
apply E_WhileLoop with (st' := st'0).
assumption. assumption. assumption.
SCase "loop doesn't run".
inversion H5; subst. apply E_WhileEnd. assumption. Qed.
(** **** Exercise: 2 stars, optional (seq_assoc) *)
Theorem seq_assoc : forall c1 c2 c3,
cequiv ((c1;;c2);;c3) (c1;;(c2;;c3)).
Proof.
intros.
intros st st'.
split; intro H.
Case "->".
inversion H; subst.
inversion H2; subst.
apply E_Seq with (st' := st'1).
assumption.
apply E_Seq with (st' := st'0).
assumption. assumption.
Case "<-".
inversion H; subst.
inversion H5; subst.
apply E_Seq with (st' := st'1).
apply E_Seq with (st' := st'0).
assumption. assumption. assumption.
Qed.
(** [] *)
(** ** The Functional Equivalence Axiom *)
(** Finally, let's look at simple equivalences involving assignments.
For example, we might expect to be able to show that [X ::= AId X]
is equivalent to [SKIP]. However, when we try to show it, we get
stuck in an interesting way. *)
Theorem identity_assignment_first_try : forall (X:id),
cequiv (X ::= AId X) SKIP.
Proof.
intros. split; intro H.
Case "->".
inversion H; subst. simpl.
replace (update st X (st X)) with st.
constructor.
(* Stuck... *) Abort.
(** Here we're stuck. The goal looks reasonable, but in fact it is not
provable! If we look back at the set of lemmas we proved about
[update] in the last chapter, we can see that lemma [update_same]
almost does the job, but not quite: it says that the original and
updated states agree at all values, but this is not the same thing
as saying that they are [=] in Coq's sense! *)
(** What is going on here? Recall that our states are just
functions from identifiers to values. For Coq, functions are only
equal when their definitions are syntactically the same, modulo
simplification. (This is the only way we can legally apply the
[refl_equal] constructor of the inductively defined proposition
[eq]!) In practice, for functions built up by repeated uses of the
[update] operation, this means that two functions can be proven
equal only if they were constructed using the _same_ [update]
operations, applied in the same order. In the theorem above, the
sequence of updates on the first parameter [cequiv] is one longer
than for the second parameter, so it is no wonder that the
equality doesn't hold. *)
(** *** *)
(** This problem is actually quite general. If we try to prove other
simple facts, such as
cequiv (X ::= X + 1;;
X ::= X + 1)
(X ::= X + 2)
or
cequiv (X ::= 1;; Y ::= 2)
(y ::= 2;; X ::= 1)
we'll get stuck in the same way: we'll have two functions that
behave the same way on all inputs, but cannot be proven to be [eq]
to each other.
The reasoning principle we would like to use in these situations
is called _functional extensionality_:
forall x, f x = g x
-------------------
f = g
Although this principle is not derivable in Coq's built-in logic,
it is safe to add it as an additional _axiom_. *)
Axiom functional_extensionality : forall {X Y: Type} {f g : X -> Y},
(forall (x: X), f x = g x) -> f = g.
(** It can be shown that adding this axiom doesn't introduce any
inconsistencies into Coq. (In this way, it is similar to adding
one of the classical logic axioms, such as [excluded_middle].) *)
(** With the benefit of this axiom we can prove our theorem. *)
Theorem identity_assignment : forall (X:id),
cequiv
(X ::= AId X)
SKIP.
Proof.
intros. split; intro H.
Case "->".
inversion H; subst. simpl.
replace (update st X (st X)) with st.
constructor.
apply functional_extensionality. intro.
rewrite update_same; reflexivity.
Case "<-".
inversion H; subst.
assert (st' = (update st' X (st' X))).
apply functional_extensionality. intro.
rewrite update_same; reflexivity.
rewrite H0 at 2.
constructor. reflexivity.
Qed.
(** **** Exercise: 2 stars (assign_aequiv) *)
Check E_Ass.
(* E_Ass *)
(* : forall (st : state) (a1 : aexp) (n : nat) (x : id), *)
(* aeval st a1 = n -> (x ::= a1) / st || update st x n *)
Theorem assign_aequiv : forall X e,
aequiv (AId X) e ->
cequiv SKIP (X ::= e).
Proof.
intros.
intros st st'.
split; intro H0.
Case "->".
inversion H0; subst.
unfold aequiv in H. simpl in H.
assert (st' = update st' X (aeval st' e)).
apply functional_extensionality. intro.
rewrite <-(H st').
rewrite update_same; reflexivity.
rewrite H1 at 2.
constructor. reflexivity.
Case "<-".
inversion H0; subst.
assert (st = update st X (aeval st e)).
apply functional_extensionality. intro.
rewrite <-(H st).
rewrite update_same; reflexivity.
rewrite <-H1.
constructor.
Qed.
(** [] *)
(* ####################################################### *)
(** * Properties of Behavioral Equivalence *)
(** We now turn to developing some of the properties of the program
equivalences we have defined. *)
(* ####################################################### *)
(** ** Behavioral Equivalence is an Equivalence *)
(** First, we verify that the equivalences on [aexps], [bexps], and
[com]s really are _equivalences_ -- i.e., that they are reflexive,
symmetric, and transitive. The proofs are all easy. *)
Lemma refl_aequiv : forall (a : aexp), aequiv a a.
Proof.
intros a st. reflexivity. Qed.
Lemma sym_aequiv : forall (a1 a2 : aexp),
aequiv a1 a2 -> aequiv a2 a1.
Proof.
intros a1 a2 H. intros st. symmetry. apply H. Qed.
Lemma trans_aequiv : forall (a1 a2 a3 : aexp),
aequiv a1 a2 -> aequiv a2 a3 -> aequiv a1 a3.
Proof.
unfold aequiv. intros a1 a2 a3 H12 H23 st.
rewrite (H12 st). rewrite (H23 st). reflexivity. Qed.
Lemma refl_bequiv : forall (b : bexp), bequiv b b.
Proof.
unfold bequiv. intros b st. reflexivity. Qed.
Lemma sym_bequiv : forall (b1 b2 : bexp),
bequiv b1 b2 -> bequiv b2 b1.
Proof.
unfold bequiv. intros b1 b2 H. intros st. symmetry. apply H. Qed.
Lemma trans_bequiv : forall (b1 b2 b3 : bexp),
bequiv b1 b2 -> bequiv b2 b3 -> bequiv b1 b3.
Proof.
unfold bequiv. intros b1 b2 b3 H12 H23 st.
rewrite (H12 st). rewrite (H23 st). reflexivity. Qed.
Lemma refl_cequiv : forall (c : com), cequiv c c.
Proof.
unfold cequiv. intros c st st'. apply iff_refl. Qed.
Lemma sym_cequiv : forall (c1 c2 : com),
cequiv c1 c2 -> cequiv c2 c1.
Proof.
unfold cequiv. intros c1 c2 H st st'.
assert (c1 / st || st' <-> c2 / st || st') as H'.
SCase "Proof of assertion". apply H.
apply iff_sym. assumption.
Qed.
Lemma iff_trans : forall (P1 P2 P3 : Prop),
(P1 <-> P2) -> (P2 <-> P3) -> (P1 <-> P3).
Proof.
intros P1 P2 P3 H12 H23.
inversion H12. inversion H23.
split; intros A.
apply H1. apply H. apply A.
apply H0. apply H2. apply A. Qed.
Lemma trans_cequiv : forall (c1 c2 c3 : com),
cequiv c1 c2 -> cequiv c2 c3 -> cequiv c1 c3.
Proof.
unfold cequiv. intros c1 c2 c3 H12 H23 st st'.
apply iff_trans with (c2 / st || st'). apply H12. apply H23. Qed.
(* ######################################################## *)
(** ** Behavioral Equivalence is a Congruence *)
(** Less obviously, behavioral equivalence is also a _congruence_.
That is, the equivalence of two subprograms implies the
equivalence of the larger programs in which they are embedded:
aequiv a1 a1'
-----------------------------
cequiv (i ::= a1) (i ::= a1')
cequiv c1 c1'
cequiv c2 c2'
------------------------
cequiv (c1;;c2) (c1';;c2')
...and so on.
(Note that we are using the inference rule notation here not as
part of a definition, but simply to write down some valid
implications in a readable format. We prove these implications
below.) *)
(** We will see a concrete example of why these congruence
properties are important in the following section (in the proof of
[fold_constants_com_sound]), but the main idea is that they allow
us to replace a small part of a large program with an equivalent
small part and know that the whole large programs are equivalent
_without_ doing an explicit proof about the non-varying parts --
i.e., the "proof burden" of a small change to a large program is
proportional to the size of the change, not the program. *)
Theorem CAss_congruence : forall i a1 a1',
aequiv a1 a1' ->
cequiv (CAss i a1) (CAss i a1').
Proof.
intros i a1 a2 Heqv st st'.
split; intros Hceval.
Case "->".
inversion Hceval. subst. apply E_Ass.
rewrite Heqv. reflexivity.
Case "<-".
inversion Hceval. subst. apply E_Ass.
rewrite Heqv. reflexivity. Qed.
(** The congruence property for loops is a little more interesting,
since it requires induction.
_Theorem_: Equivalence is a congruence for [WHILE] -- that is, if
[b1] is equivalent to [b1'] and [c1] is equivalent to [c1'], then
[WHILE b1 DO c1 END] is equivalent to [WHILE b1' DO c1' END].
_Proof_: Suppose [b1] is equivalent to [b1'] and [c1] is
equivalent to [c1']. We must show, for every [st] and [st'], that
[WHILE b1 DO c1 END / st || st'] iff [WHILE b1' DO c1' END / st
|| st']. We consider the two directions separately.
- ([->]) We show that [WHILE b1 DO c1 END / st || st'] implies
[WHILE b1' DO c1' END / st || st'], by induction on a
derivation of [WHILE b1 DO c1 END / st || st']. The only
nontrivial cases are when the final rule in the derivation is
[E_WhileEnd] or [E_WhileLoop].
- [E_WhileEnd]: In this case, the form of the rule gives us
[beval st b1 = false] and [st = st']. But then, since
[b1] and [b1'] are equivalent, we have [beval st b1' =
false], and [E-WhileEnd] applies, giving us [WHILE b1' DO
c1' END / st || st'], as required.
- [E_WhileLoop]: The form of the rule now gives us [beval st
b1 = true], with [c1 / st || st'0] and [WHILE b1 DO c1
END / st'0 || st'] for some state [st'0], with the
induction hypothesis [WHILE b1' DO c1' END / st'0 ||
st'].
Since [c1] and [c1'] are equivalent, we know that [c1' /
st || st'0]. And since [b1] and [b1'] are equivalent, we
have [beval st b1' = true]. Now [E-WhileLoop] applies,
giving us [WHILE b1' DO c1' END / st || st'], as
required.
- ([<-]) Similar. [] *)
Theorem CWhile_congruence : forall b1 b1' c1 c1',
bequiv b1 b1' -> cequiv c1 c1' ->
cequiv (WHILE b1 DO c1 END) (WHILE b1' DO c1' END).
Proof.
(* WORKED IN CLASS *)
unfold bequiv,cequiv.
intros b1 b1' c1 c1' Hb1e Hc1e st st'.
split; intros Hce.
Case "->".
remember (WHILE b1 DO c1 END) as cwhile eqn:Heqcwhile.
induction Hce; inversion Heqcwhile; subst.
SCase "E_WhileEnd".
apply E_WhileEnd. rewrite <- Hb1e. apply H.
SCase "E_WhileLoop".
apply E_WhileLoop with (st' := st').
SSCase "show loop runs". rewrite <- Hb1e. apply H.
SSCase "body execution".
apply (Hc1e st st'). apply Hce1.
SSCase "subsequent loop execution".
apply IHHce2. reflexivity.
Case "<-".
remember (WHILE b1' DO c1' END) as c'while eqn:Heqc'while.
induction Hce; inversion Heqc'while; subst.
SCase "E_WhileEnd".
apply E_WhileEnd. rewrite -> Hb1e. apply H.
SCase "E_WhileLoop".
apply E_WhileLoop with (st' := st').
SSCase "show loop runs". rewrite -> Hb1e. apply H.
SSCase "body execution".
apply (Hc1e st st'). apply Hce1.
SSCase "subsequent loop execution".
apply IHHce2. reflexivity. Qed.
(** **** Exercise: 3 stars, optional (CSeq_congruence) *)
Theorem CSeq_congruence : forall c1 c1' c2 c2',
cequiv c1 c1' -> cequiv c2 c2' ->
cequiv (c1;;c2) (c1';;c2').
Proof.
intros.
split; intro H1.
Case "->".
inversion H1; subst.
apply E_Seq with st'0.
apply H. assumption.
apply H0. assumption.
Case "<-".
inversion H1; subst.
apply E_Seq with st'0.
apply H. assumption.
apply H0. assumption.
Qed.
(** [] *)
(** **** Exercise: 3 stars (CIf_congruence) *)
Theorem CIf_congruence : forall b b' c1 c1' c2 c2',
bequiv b b' -> cequiv c1 c1' -> cequiv c2 c2' ->
cequiv (IFB b THEN c1 ELSE c2 FI) (IFB b' THEN c1' ELSE c2' FI).
Proof.
intros.
split; intro H2.
Case "->".
destruct (beval st b') eqn:HE.
apply E_IfTrue. assumption.
rewrite <-H in HE. apply H0.
inversion H2; subst. assumption. rewrite HE in H8. inversion H8.
apply E_IfFalse. assumption.
rewrite <-H in HE. apply H1.
inversion H2; subst. rewrite HE in H8. inversion H8. assumption.
Case "<-".
inversion H2; subst.
apply E_IfTrue. rewrite <-H in H8. assumption.
apply H0. assumption.
apply E_IfFalse. rewrite <-H in H8. assumption.
apply H1. assumption.
Qed.
(** [] *)
(** *** *)
(** For example, here are two equivalent programs and a proof of their
equivalence... *)
Example congruence_example:
cequiv
(* Program 1: *)
(X ::= ANum 0;;
IFB (BEq (AId X) (ANum 0))
THEN
Y ::= ANum 0
ELSE
Y ::= ANum 42
FI)
(* Program 2: *)
(X ::= ANum 0;;
IFB (BEq (AId X) (ANum 0))
THEN
Y ::= AMinus (AId X) (AId X) (* <--- changed here *)
ELSE
Y ::= ANum 42
FI).
Proof.
apply CSeq_congruence.
apply refl_cequiv.
apply CIf_congruence.
apply refl_bequiv.
apply CAss_congruence. unfold aequiv. simpl.
symmetry. apply minus_diag.
apply refl_cequiv.
Qed.
(* ####################################################### *)
(** * Program Transformations *)
(** A _program transformation_ is a function that takes a program
as input and produces some variant of the program as its
output. Compiler optimizations such as constant folding are
a canonical example, but there are many others. *)
(** A program transformation is _sound_ if it preserves the
behavior of the original program.
We can define a notion of soundness for translations of
[aexp]s, [bexp]s, and [com]s. *)
Definition atrans_sound (atrans : aexp -> aexp) : Prop :=
forall (a : aexp),
aequiv a (atrans a).
Definition btrans_sound (btrans : bexp -> bexp) : Prop :=
forall (b : bexp),
bequiv b (btrans b).
Definition ctrans_sound (ctrans : com -> com) : Prop :=
forall (c : com),
cequiv c (ctrans c).
(* ######################################################## *)
(** ** The Constant-Folding Transformation *)
(** An expression is _constant_ when it contains no variable
references.
Constant folding is an optimization that finds constant
expressions and replaces them by their values. *)
Fixpoint fold_constants_aexp (a : aexp) : aexp :=
match a with
| ANum n => ANum n
| AId i => AId i
| APlus a1 a2 =>
match (fold_constants_aexp a1, fold_constants_aexp a2) with
| (ANum n1, ANum n2) => ANum (n1 + n2)
| (a1', a2') => APlus a1' a2'
end
| AMinus a1 a2 =>
match (fold_constants_aexp a1, fold_constants_aexp a2) with
| (ANum n1, ANum n2) => ANum (n1 - n2)
| (a1', a2') => AMinus a1' a2'
end
| AMult a1 a2 =>
match (fold_constants_aexp a1, fold_constants_aexp a2) with
| (ANum n1, ANum n2) => ANum (n1 * n2)
| (a1', a2') => AMult a1' a2'
end
end.
Example fold_aexp_ex1 :
fold_constants_aexp
(AMult (APlus (ANum 1) (ANum 2)) (AId X))
= AMult (ANum 3) (AId X).
Proof. reflexivity. Qed.
(** Note that this version of constant folding doesn't eliminate
trivial additions, etc. -- we are focusing attention on a single
optimization for the sake of simplicity. It is not hard to
incorporate other ways of simplifying expressions; the definitions
and proofs just get longer. *)
Example fold_aexp_ex2 :
fold_constants_aexp
(AMinus (AId X) (APlus (AMult (ANum 0) (ANum 6)) (AId Y)))
= AMinus (AId X) (APlus (ANum 0) (AId Y)).
Proof. reflexivity. Qed.
(** *** *)
(** Not only can we lift [fold_constants_aexp] to [bexp]s (in the
[BEq] and [BLe] cases), we can also find constant _boolean_
expressions and reduce them in-place. *)
Fixpoint fold_constants_bexp (b : bexp) : bexp :=
match b with
| BTrue => BTrue
| BFalse => BFalse
| BEq a1 a2 =>
match (fold_constants_aexp a1, fold_constants_aexp a2) with
| (ANum n1, ANum n2) => if beq_nat n1 n2 then BTrue else BFalse
| (a1', a2') => BEq a1' a2'
end
| BLe a1 a2 =>
match (fold_constants_aexp a1, fold_constants_aexp a2) with
| (ANum n1, ANum n2) => if ble_nat n1 n2 then BTrue else BFalse
| (a1', a2') => BLe a1' a2'
end
| BNot b1 =>
match (fold_constants_bexp b1) with
| BTrue => BFalse
| BFalse => BTrue
| b1' => BNot b1'
end
| BAnd b1 b2 =>
match (fold_constants_bexp b1, fold_constants_bexp b2) with
| (BTrue, BTrue) => BTrue
| (BTrue, BFalse) => BFalse
| (BFalse, BTrue) => BFalse
| (BFalse, BFalse) => BFalse
| (b1', b2') => BAnd b1' b2'
end
end.
Example fold_bexp_ex1 :
fold_constants_bexp (BAnd BTrue (BNot (BAnd BFalse BTrue)))
= BTrue.
Proof. reflexivity. Qed.
Example fold_bexp_ex2 :
fold_constants_bexp
(BAnd (BEq (AId X) (AId Y))
(BEq (ANum 0)
(AMinus (ANum 2) (APlus (ANum 1) (ANum 1)))))
= BAnd (BEq (AId X) (AId Y)) BTrue.
Proof. reflexivity. Qed.
(** *** *)
(** To fold constants in a command, we apply the appropriate folding
functions on all embedded expressions. *)
Fixpoint fold_constants_com (c : com) : com :=
match c with
| SKIP =>
SKIP
| i ::= a =>
CAss i (fold_constants_aexp a)
| c1 ;; c2 =>
(fold_constants_com c1) ;; (fold_constants_com c2)
| IFB b THEN c1 ELSE c2 FI =>
match fold_constants_bexp b with
| BTrue => fold_constants_com c1
| BFalse => fold_constants_com c2
| b' => IFB b' THEN fold_constants_com c1
ELSE fold_constants_com c2 FI
end
| WHILE b DO c END =>
match fold_constants_bexp b with
| BTrue => WHILE BTrue DO SKIP END
| BFalse => SKIP
| b' => WHILE b' DO (fold_constants_com c) END
end
end.
(** *** *)
Example fold_com_ex1 :
fold_constants_com
(* Original program: *)
(X ::= APlus (ANum 4) (ANum 5);;
Y ::= AMinus (AId X) (ANum 3);;
IFB BEq (AMinus (AId X) (AId Y)) (APlus (ANum 2) (ANum 4)) THEN
SKIP
ELSE
Y ::= ANum 0
FI;;
IFB BLe (ANum 0) (AMinus (ANum 4) (APlus (ANum 2) (ANum 1))) THEN
Y ::= ANum 0
ELSE
SKIP
FI;;
WHILE BEq (AId Y) (ANum 0) DO
X ::= APlus (AId X) (ANum 1)
END)
= (* After constant folding: *)
(X ::= ANum 9;;
Y ::= AMinus (AId X) (ANum 3);;
IFB BEq (AMinus (AId X) (AId Y)) (ANum 6) THEN
SKIP
ELSE
(Y ::= ANum 0)
FI;;
Y ::= ANum 0;;
WHILE BEq (AId Y) (ANum 0) DO
X ::= APlus (AId X) (ANum 1)
END).
Proof. reflexivity. Qed.
(* ################################################### *)
(** ** Soundness of Constant Folding *)
(** Now we need to show that what we've done is correct. *)
(** Here's the proof for arithmetic expressions: *)
Theorem fold_constants_aexp_sound :
atrans_sound fold_constants_aexp.
Proof.
unfold atrans_sound. intros a. unfold aequiv. intros st.
aexp_cases (induction a) Case; simpl;
(* ANum and AId follow immediately *)
try reflexivity;
(* APlus, AMinus, and AMult follow from the IH
and the observation that
aeval st (APlus a1 a2)
= ANum ((aeval st a1) + (aeval st a2))
= aeval st (ANum ((aeval st a1) + (aeval st a2)))
(and similarly for AMinus/minus and AMult/mult) *)
try (destruct (fold_constants_aexp a1);
destruct (fold_constants_aexp a2);
rewrite IHa1; rewrite IHa2; reflexivity). Qed.
(** **** Exercise: 3 stars, optional (fold_bexp_Eq_informal) *)
(** Here is an informal proof of the [BEq] case of the soundness
argument for boolean expression constant folding. Read it
carefully and compare it to the formal proof that follows. Then
fill in the [BLe] case of the formal proof (without looking at the
[BEq] case, if possible).
_Theorem_: The constant folding function for booleans,
[fold_constants_bexp], is sound.
_Proof_: We must show that [b] is equivalent to [fold_constants_bexp],
for all boolean expressions [b]. Proceed by induction on [b]. We
show just the case where [b] has the form [BEq a1 a2].
In this case, we must show
beval st (BEq a1 a2)
= beval st (fold_constants_bexp (BEq a1 a2)).
There are two cases to consider:
- First, suppose [fold_constants_aexp a1 = ANum n1] and
[fold_constants_aexp a2 = ANum n2] for some [n1] and [n2].
In this case, we have
fold_constants_bexp (BEq a1 a2)
= if beq_nat n1 n2 then BTrue else BFalse
and
beval st (BEq a1 a2)
= beq_nat (aeval st a1) (aeval st a2).
By the soundness of constant folding for arithmetic
expressions (Lemma [fold_constants_aexp_sound]), we know
aeval st a1
= aeval st (fold_constants_aexp a1)
= aeval st (ANum n1)
= n1
and
aeval st a2
= aeval st (fold_constants_aexp a2)
= aeval st (ANum n2)
= n2,
so
beval st (BEq a1 a2)
= beq_nat (aeval a1) (aeval a2)
= beq_nat n1 n2.
Also, it is easy to see (by considering the cases [n1 = n2] and
[n1 <> n2] separately) that
beval st (if beq_nat n1 n2 then BTrue else BFalse)
= if beq_nat n1 n2 then beval st BTrue else beval st BFalse
= if beq_nat n1 n2 then true else false
= beq_nat n1 n2.
So
beval st (BEq a1 a2)
= beq_nat n1 n2.
= beval st (if beq_nat n1 n2 then BTrue else BFalse),
]]
as required.
- Otherwise, one of [fold_constants_aexp a1] and
[fold_constants_aexp a2] is not a constant. In this case, we
must show
beval st (BEq a1 a2)
= beval st (BEq (fold_constants_aexp a1)
(fold_constants_aexp a2)),
which, by the definition of [beval], is the same as showing
beq_nat (aeval st a1) (aeval st a2)
= beq_nat (aeval st (fold_constants_aexp a1))
(aeval st (fold_constants_aexp a2)).
But the soundness of constant folding for arithmetic
expressions ([fold_constants_aexp_sound]) gives us
aeval st a1 = aeval st (fold_constants_aexp a1)
aeval st a2 = aeval st (fold_constants_aexp a2),
completing the case. []
*)
Theorem fold_constants_bexp_sound:
btrans_sound fold_constants_bexp.
Proof.
unfold btrans_sound. intros b. unfold bequiv. intros st.
bexp_cases (induction b) Case;
(* BTrue and BFalse are immediate *)
try reflexivity.
Case "BEq".
(* Doing induction when there are a lot of constructors makes
specifying variable names a chore, but Coq doesn't always
choose nice variable names. We can rename entries in the
context with the [rename] tactic: [rename a into a1] will
change [a] to [a1] in the current goal and context. *)
rename a into a1. rename a0 into a2. simpl.
remember (fold_constants_aexp a1) as a1' eqn:Heqa1'.
remember (fold_constants_aexp a2) as a2' eqn:Heqa2'.
replace (aeval st a1) with (aeval st a1') by
(subst a1'; rewrite <- fold_constants_aexp_sound; reflexivity).
replace (aeval st a2) with (aeval st a2') by
(subst a2'; rewrite <- fold_constants_aexp_sound; reflexivity).
destruct a1'; destruct a2'; try reflexivity.
(* The only interesting case is when both a1 and a2
become constants after folding *)
simpl. destruct (beq_nat n n0); reflexivity.
Case "BLe".
(* copied from BEq case *)
rename a into a1. rename a0 into a2. simpl.
remember (fold_constants_aexp a1) as a1' eqn:Heqa1'.
remember (fold_constants_aexp a2) as a2' eqn:Heqa2'.
replace (aeval st a1) with (aeval st a1') by
(subst a1'; rewrite <- fold_constants_aexp_sound; reflexivity).
replace (aeval st a2) with (aeval st a2') by
(subst a2'; rewrite <- fold_constants_aexp_sound; reflexivity).
destruct a1'; destruct a2'; try reflexivity.
simpl. destruct (ble_nat n n0); reflexivity.
Case "BNot".
simpl. remember (fold_constants_bexp b) as b' eqn:Heqb'.
rewrite IHb.
destruct b'; reflexivity.
Case "BAnd".
simpl.
remember (fold_constants_bexp b1) as b1' eqn:Heqb1'.
remember (fold_constants_bexp b2) as b2' eqn:Heqb2'.
rewrite IHb1. rewrite IHb2.
destruct b1'; destruct b2'; reflexivity. Qed.
(** [] *)
(** **** Exercise: 3 stars (fold_constants_com_sound) *)
(** Complete the [WHILE] case of the following proof. *)
Theorem fold_constants_com_sound :
ctrans_sound fold_constants_com.
Proof.
unfold ctrans_sound. intros c.
com_cases (induction c) Case; simpl.
Case "SKIP". apply refl_cequiv.
Case "::=". apply CAss_congruence. apply fold_constants_aexp_sound.
Case ";;". apply CSeq_congruence; assumption.
Case "IFB".
assert (bequiv b (fold_constants_bexp b)).
SCase "Pf of assertion". apply fold_constants_bexp_sound.
destruct (fold_constants_bexp b) eqn:Heqb;
(* If the optimization doesn't eliminate the if, then the result
is easy to prove from the IH and fold_constants_bexp_sound *)
try (apply CIf_congruence; assumption).
SCase "b always true".
apply trans_cequiv with c1; try assumption.
apply IFB_true; assumption.
SCase "b always false".
apply trans_cequiv with c2; try assumption.
apply IFB_false; assumption.
Case "WHILE".
assert (bequiv b (fold_constants_bexp b)).
apply fold_constants_bexp_sound.
destruct (fold_constants_bexp b) eqn:Heqb;
try (apply CWhile_congruence; assumption; assumption).
apply WHILE_true. assumption.
apply WHILE_false. assumption.
Qed.
(** [] *)
(* ########################################################## *)
(** *** Soundness of (0 + n) Elimination, Redux *)
(** **** Exercise: 4 stars, advanced, optional (optimize_0plus) *)
(** Recall the definition [optimize_0plus] from Imp.v:
Fixpoint optimize_0plus (e:aexp) : aexp :=
match e with
| ANum n =>
ANum n
| APlus (ANum 0) e2 =>
optimize_0plus e2
| APlus e1 e2 =>
APlus (optimize_0plus e1) (optimize_0plus e2)
| AMinus e1 e2 =>
AMinus (optimize_0plus e1) (optimize_0plus e2)
| AMult e1 e2 =>
AMult (optimize_0plus e1) (optimize_0plus e2)
end.
Note that this function is defined over the old [aexp]s,
without states.
Write a new version of this function that accounts for variables,
and analogous ones for [bexp]s and commands:
optimize_0plus_aexp
optimize_0plus_bexp
optimize_0plus_com
Prove that these three functions are sound, as we did for
[fold_constants_*]. (Make sure you use the congruence lemmas in
the proof of [optimize_0plus_com] -- otherwise it will be _long_!)
Then define an optimizer on commands that first folds
constants (using [fold_constants_com]) and then eliminates [0 + n]
terms (using [optimize_0plus_com]).
- Give a meaningful example of this optimizer's output.
- Prove that the optimizer is sound. (This part should be _very_
easy.) *)
Fixpoint optimize_0plus_aexp (a : aexp) : aexp :=
match a with
| ANum n => ANum n
| AId i => AId i
| APlus (ANum 0) a2 => optimize_0plus_aexp a2
| APlus a1 a2 =>
APlus (optimize_0plus_aexp a1) (optimize_0plus_aexp a2)
| AMinus a1 a2 =>
AMinus (optimize_0plus_aexp a1) (optimize_0plus_aexp a2)
| AMult a1 a2 =>
AMult (optimize_0plus_aexp a1) (optimize_0plus_aexp a2)
end.
Theorem optimize_0plus_aexp_sound :
atrans_sound optimize_0plus_aexp.
Proof.
unfold atrans_sound. intros a st.
aexp_cases (induction a) Case;
try reflexivity;
simpl; rewrite IHa1; rewrite IHa2;
destruct a1;
simpl; try(destruct n); reflexivity.
Qed.
Fixpoint optimize_0plus_bexp (b : bexp) : bexp :=
match b with
| BTrue => BTrue
| BFalse => BFalse
| BEq a1 a2 => BEq (optimize_0plus_aexp a1)
(optimize_0plus_aexp a2)
| BLe a1 a2 => BLe (optimize_0plus_aexp a1)
(optimize_0plus_aexp a2)
| BNot b => BNot (optimize_0plus_bexp b)
| BAnd b1 b2 => BAnd (optimize_0plus_bexp b1)
(optimize_0plus_bexp b2)
end.
Theorem optimize_0plus_bexp_sound :
btrans_sound optimize_0plus_bexp.
Proof.
unfold btrans_sound. unfold bequiv.
intros b st.
bexp_cases (induction b) Case; try reflexivity;
try (simpl;
rewrite (optimize_0plus_aexp_sound a);
rewrite (optimize_0plus_aexp_sound a0);
reflexivity).
simpl. rewrite IHb. reflexivity.
simpl. rewrite IHb1. rewrite IHb2. reflexivity.
Qed.
Fixpoint optimize_0plus_com (c : com) : com :=
match c with
| SKIP =>
SKIP
| i ::= a =>
CAss i (optimize_0plus_aexp a)
| c1 ;; c2 =>
(optimize_0plus_com c1) ;; (optimize_0plus_com c2)
| IFB b THEN c1 ELSE c2 FI =>
IFB (optimize_0plus_bexp b)
THEN (optimize_0plus_com c1)
ELSE (optimize_0plus_com c2)
FI
| WHILE b DO c END =>
WHILE (optimize_0plus_bexp b)
DO (optimize_0plus_com c) END
end.
Theorem optimize_0plus_com_sound :
ctrans_sound optimize_0plus_com.
Proof.
unfold ctrans_sound. intros c.
com_cases (induction c) Case.
Case "SKIP". apply refl_cequiv.
Case "::=".
apply CAss_congruence. apply optimize_0plus_aexp_sound.
Case ";;". apply CSeq_congruence; assumption.
Case "IFB".
apply CIf_congruence.
apply (optimize_0plus_bexp_sound b).
assumption. assumption.
Case "WHILE".
apply CWhile_congruence.
apply (optimize_0plus_bexp_sound b).
assumption.
Qed.
Function optimize2_com (c : com) : com :=
optimize_0plus_com (fold_constants_com c).
Theorem optimize2_com_sound :
ctrans_sound optimize2_com.
Proof.
unfold ctrans_sound.
unfold optimize2_com.
intros c.
apply trans_cequiv with (c2:=fold_constants_com c).
apply (fold_constants_com_sound c).
apply (optimize_0plus_com_sound (fold_constants_com c)).
Qed.
(** [] *)
(* ####################################################### *)
(** * Proving That Programs Are _Not_ Equivalent *)
(** Suppose that [c1] is a command of the form [X ::= a1;; Y ::= a2]
and [c2] is the command [X ::= a1;; Y ::= a2'], where [a2'] is
formed by substituting [a1] for all occurrences of [X] in [a2].
For example, [c1] and [c2] might be:
c1 = (X ::= 42 + 53;;
Y ::= Y + X)
c2 = (X ::= 42 + 53;;
Y ::= Y + (42 + 53))
Clearly, this _particular_ [c1] and [c2] are equivalent. Is this
true in general? *)
(** We will see in a moment that it is not, but it is worthwhile
to pause, now, and see if you can find a counter-example on your
own. *)
(** Here, formally, is the function that substitutes an arithmetic
expression for each occurrence of a given variable in another
expression: *)
Fixpoint subst_aexp (i : id) (u : aexp) (a : aexp) : aexp :=
match a with
| ANum n => ANum n
| AId i' => if eq_id_dec i i' then u else AId i'
| APlus a1 a2 => APlus (subst_aexp i u a1) (subst_aexp i u a2)
| AMinus a1 a2 => AMinus (subst_aexp i u a1) (subst_aexp i u a2)
| AMult a1 a2 => AMult (subst_aexp i u a1) (subst_aexp i u a2)
end.
Example subst_aexp_ex :
subst_aexp X (APlus (ANum 42) (ANum 53)) (APlus (AId Y) (AId X)) =
(APlus (AId Y) (APlus (ANum 42) (ANum 53))).
Proof. reflexivity. Qed.
(** And here is the property we are interested in, expressing the
claim that commands [c1] and [c2] as described above are
always equivalent. *)
Definition subst_equiv_property := forall i1 i2 a1 a2,
cequiv (i1 ::= a1;; i2 ::= a2)
(i1 ::= a1;; i2 ::= subst_aexp i1 a1 a2).
(** *** *)
(** Sadly, the property does _not_ always hold.
_Theorem_: It is not the case that, for all [i1], [i2], [a1],
and [a2],
cequiv (i1 ::= a1;; i2 ::= a2)
(i1 ::= a1;; i2 ::= subst_aexp i1 a1 a2).
]]
_Proof_: Suppose, for a contradiction, that for all [i1], [i2],
[a1], and [a2], we have
cequiv (i1 ::= a1;; i2 ::= a2)
(i1 ::= a1;; i2 ::= subst_aexp i1 a1 a2).
Consider the following program:
X ::= APlus (AId X) (ANum 1);; Y ::= AId X
Note that
(X ::= APlus (AId X) (ANum 1);; Y ::= AId X)
/ empty_state || st1,
where [st1 = { X |-> 1, Y |-> 1 }].
By our assumption, we know that
cequiv (X ::= APlus (AId X) (ANum 1);; Y ::= AId X)
(X ::= APlus (AId X) (ANum 1);; Y ::= APlus (AId X) (ANum 1))
so, by the definition of [cequiv], we have
(X ::= APlus (AId X) (ANum 1);; Y ::= APlus (AId X) (ANum 1))
/ empty_state || st1.
But we can also derive
(X ::= APlus (AId X) (ANum 1);; Y ::= APlus (AId X) (ANum 1))
/ empty_state || st2,
where [st2 = { X |-> 1, Y |-> 2 }]. Note that [st1 <> st2]; this
is a contradiction, since [ceval] is deterministic! [] *)
Theorem subst_inequiv :
~ subst_equiv_property.
Proof.
unfold subst_equiv_property.
intros Contra.
(* Here is the counterexample: assuming that [subst_equiv_property]
holds allows us to prove that these two programs are
equivalent... *)
remember (X ::= APlus (AId X) (ANum 1);;
Y ::= AId X)
as c1.
remember (X ::= APlus (AId X) (ANum 1);;
Y ::= APlus (AId X) (ANum 1))
as c2.
assert (cequiv c1 c2) by (subst; apply Contra).
(* ... allows us to show that the command [c2] can terminate
in two different final states:
st1 = {X |-> 1, Y |-> 1}
st2 = {X |-> 1, Y |-> 2}. *)
remember (update (update empty_state X 1) Y 1) as st1.
remember (update (update empty_state X 1) Y 2) as st2.
assert (H1: c1 / empty_state || st1);
assert (H2: c2 / empty_state || st2);
try (subst;
apply E_Seq with (st' := (update empty_state X 1));
apply E_Ass; reflexivity).
apply H in H1.
(* Finally, we use the fact that evaluation is deterministic
to obtain a contradiction. *)
assert (Hcontra: st1 = st2)
by (apply (ceval_deterministic c2 empty_state); assumption).
assert (Hcontra': st1 Y = st2 Y)
by (rewrite Hcontra; reflexivity).
subst. inversion Hcontra'. Qed.
(** **** Exercise: 4 stars, optional (better_subst_equiv) *)
(** The equivalence we had in mind above was not complete nonsense --
it was actually almost right. To make it correct, we just need to
exclude the case where the variable [X] occurs in the
right-hand-side of the first assignment statement. *)
Inductive var_not_used_in_aexp (X:id) : aexp -> Prop :=
| VNUNum: forall n, var_not_used_in_aexp X (ANum n)
| VNUId: forall Y, X <> Y -> var_not_used_in_aexp X (AId Y)
| VNUPlus: forall a1 a2,
var_not_used_in_aexp X a1 ->
var_not_used_in_aexp X a2 ->
var_not_used_in_aexp X (APlus a1 a2)
| VNUMinus: forall a1 a2,
var_not_used_in_aexp X a1 ->
var_not_used_in_aexp X a2 ->
var_not_used_in_aexp X (AMinus a1 a2)
| VNUMult: forall a1 a2,
var_not_used_in_aexp X a1 ->
var_not_used_in_aexp X a2 ->
var_not_used_in_aexp X (AMult a1 a2).
Lemma aeval_weakening : forall i st a ni,
var_not_used_in_aexp i a ->
aeval (update st i ni) a = aeval st a.
Proof.
intros.
induction H;
try reflexivity;
try (simpl; apply update_neq; assumption);
try (simpl;
rewrite IHvar_not_used_in_aexp1;
rewrite IHvar_not_used_in_aexp2;
reflexivity).
Qed.
(** Using [var_not_used_in_aexp], formalize and prove a correct verson
of [subst_equiv_property]. *)
(* ref: https://github.com/khibino/sfja-code/blob/master/Equiv.v#L1221 *)
Lemma better_subst_equiv_property : forall i1 i2 a1 a2,
var_not_used_in_aexp i1 a1 ->
cequiv (i1 ::= a1;; i2 ::= a2)
(i1 ::= a1;; i2 ::= subst_aexp i1 a1 a2).
Proof.
split.
Case "->".
intros.
inversion H0; subst.
apply E_Seq with st'0.
assumption.
inversion H3; subst.
inversion H6; subst.
apply E_Ass.
aexp_cases (induction a2) SCase.
SCase "ANum".
reflexivity.
SCase "AId".
simpl.
destruct (eq_id_dec i1 i).
SSCase "i1 = i".
subst. rewrite update_eq.
apply aeval_weakening. assumption.
SSCase "i1 <> i".
rewrite update_neq.
simpl. apply update_neq. assumption. assumption.
SCase "APlus".
simpl.
rewrite IHa2_1. rewrite IHa2_2. try reflexivity.
apply E_Seq with (st' := update st i1 (aeval st a1)).
apply E_Ass; reflexivity. apply E_Ass; reflexivity. apply E_Ass; reflexivity.
apply E_Seq with (st' := update st i1 (aeval st a1)).
apply E_Ass; reflexivity. apply E_Ass; reflexivity. apply E_Ass; reflexivity.
SCase "AMinus".
simpl. rewrite IHa2_1. rewrite IHa2_2. reflexivity.
apply E_Seq with (st' := update st i1 (aeval st a1)).
apply E_Ass; reflexivity. apply E_Ass; reflexivity. apply E_Ass; reflexivity.
apply E_Seq with (st' := update st i1 (aeval st a1)).
apply E_Ass; reflexivity. apply E_Ass; reflexivity. apply E_Ass; reflexivity.
SCase "AMult".
simpl. rewrite IHa2_1. rewrite IHa2_2. reflexivity.
apply E_Seq with (st' := update st i1 (aeval st a1)).
apply E_Ass; reflexivity. apply E_Ass; reflexivity. apply E_Ass; reflexivity.
apply E_Seq with (st' := update st i1 (aeval st a1)).
apply E_Ass; reflexivity. apply E_Ass; reflexivity. apply E_Ass; reflexivity.
Case "<-".
intro H0.
inversion H0; subst.
apply E_Seq with st'0.
assumption.
inversion H3; subst.
inversion H6; subst.
apply E_Ass. symmetry.
aexp_cases (induction a2) SCase.
SCase "ANum".
reflexivity.
SCase "AId".
simpl.
destruct (eq_id_dec i1 i).
SSCase "i1 = i".
subst. rewrite update_eq.
apply aeval_weakening. assumption.
SSCase "i1 <> i".
rewrite update_neq.
simpl. apply update_neq. assumption. assumption.
SCase "APlus".
simpl.
rewrite IHa2_1. rewrite IHa2_2. try reflexivity.
apply E_Seq with (st' := update st i1 (aeval st a1)).
apply E_Ass; reflexivity. apply E_Ass; reflexivity. apply E_Ass; reflexivity.
apply E_Seq with (st' := update st i1 (aeval st a1)).
apply E_Ass; reflexivity. apply E_Ass; reflexivity. apply E_Ass; reflexivity.
SCase "AMinus".
simpl. rewrite IHa2_1. rewrite IHa2_2. reflexivity.
apply E_Seq with (st' := update st i1 (aeval st a1)).
apply E_Ass; reflexivity. apply E_Ass; reflexivity. apply E_Ass; reflexivity.
apply E_Seq with (st' := update st i1 (aeval st a1)).
apply E_Ass; reflexivity. apply E_Ass; reflexivity. apply E_Ass; reflexivity.
SCase "AMult".
simpl. rewrite IHa2_1. rewrite IHa2_2. reflexivity.
apply E_Seq with (st' := update st i1 (aeval st a1)).
apply E_Ass; reflexivity. apply E_Ass; reflexivity. apply E_Ass; reflexivity.
apply E_Seq with (st' := update st i1 (aeval st a1)).
apply E_Ass; reflexivity. apply E_Ass; reflexivity. apply E_Ass; reflexivity.
Qed.
(** [] *)
(** **** Exercise: 3 stars, optional (inequiv_exercise) *)
(** Prove that an infinite loop is not equivalent to [SKIP] *)
Theorem inequiv_exercise:
~ cequiv (WHILE BTrue DO SKIP END) SKIP.
Proof.
intro contra.
unfold cequiv in contra.
remember (contra empty_state empty_state) as H. clear HeqH.
inversion H.
remember (E_Skip empty_state) as HS. clear HeqHS.
apply H1 in HS.
apply (WHILE_true_nonterm BTrue SKIP empty_state empty_state).
apply refl_bequiv. assumption.
Qed.
(** [] *)
(** * Extended exercise: Non-deterministic Imp *)
(** As we have seen (in theorem [ceval_deterministic] in the Imp
chapter), Imp's evaluation relation is deterministic. However,
_non_-determinism is an important part of the definition of many
real programming languages. For example, in many imperative
languages (such as C and its relatives), the order in which
function arguments are evaluated is unspecified. The program
fragment
x = 0;;
f(++x, x)
might call [f] with arguments [(1, 0)] or [(1, 1)], depending how
the compiler chooses to order things. This can be a little
confusing for programmers, but it gives the compiler writer useful
freedom.
In this exercise, we will extend Imp with a simple
non-deterministic command and study how this change affects
program equivalence. The new command has the syntax [HAVOC X],
where [X] is an identifier. The effect of executing [HAVOC X] is
to assign an _arbitrary_ number to the variable [X],
non-deterministically. For example, after executing the program:
HAVOC Y;;
Z ::= Y * 2
the value of [Y] can be any number, while the value of [Z] is
twice that of [Y] (so [Z] is always even). Note that we are not
saying anything about the _probabilities_ of the outcomes -- just
that there are (infinitely) many different outcomes that can
possibly happen after executing this non-deterministic code.
In a sense a variable on which we do [HAVOC] roughly corresponds
to an unitialized variable in the C programming language. After
the [HAVOC] the variable holds a fixed but arbitrary number. Most
sources of nondeterminism in language definitions are there
precisely because programmers don't care which choice is made (and
so it is good to leave it open to the compiler to choose whichever
will run faster).
We call this new language _Himp_ (``Imp extended with [HAVOC]''). *)
Module Himp.
(** To formalize the language, we first add a clause to the definition of
commands. *)
Inductive com : Type :=
| CSkip : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
| CHavoc : id -> com. (* <---- new *)
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";;"
| Case_aux c "IFB" | Case_aux c "WHILE" | Case_aux c "HAVOC" ].
Notation "'SKIP'" :=
CSkip.
Notation "X '::=' a" :=
(CAss X a) (at level 60).
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' e1 'THEN' e2 'ELSE' e3 'FI'" :=
(CIf e1 e2 e3) (at level 80, right associativity).
Notation "'HAVOC' l" := (CHavoc l) (at level 60).
(** **** Exercise: 2 stars (himp_ceval) *)
(** Now, we must extend the operational semantics. We have provided
a template for the [ceval] relation below, specifying the big-step
semantics. What rule(s) must be added to the definition of [ceval]
to formalize the behavior of the [HAVOC] command? *)
Reserved Notation "c1 '/' st '||' st'" (at level 40, st at level 39).
Inductive ceval : com -> state -> state -> Prop :=
| E_Skip : forall st : state, SKIP / st || st
| E_Ass : forall (st : state) (a1 : aexp) (n : nat) (X : id),
aeval st a1 = n -> (X ::= a1) / st || update st X n
| E_Seq : forall (c1 c2 : com) (st st' st'' : state),
c1 / st || st' -> c2 / st' || st'' -> (c1 ;; c2) / st || st''
| E_IfTrue : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = true ->
c1 / st || st' -> (IFB b1 THEN c1 ELSE c2 FI) / st || st'
| E_IfFalse : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = false ->
c2 / st || st' -> (IFB b1 THEN c1 ELSE c2 FI) / st || st'
| E_WhileEnd : forall (b1 : bexp) (st : state) (c1 : com),
beval st b1 = false -> (WHILE b1 DO c1 END) / st || st
| E_WhileLoop : forall (st st' st'' : state) (b1 : bexp) (c1 : com),
beval st b1 = true ->
c1 / st || st' ->
(WHILE b1 DO c1 END) / st' || st'' ->
(WHILE b1 DO c1 END) / st || st''
| E_Havoc : forall X st n,
(HAVOC X) / st || update st X n
where "c1 '/' st '||' st'" := (ceval c1 st st').
Tactic Notation "ceval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Skip" | Case_aux c "E_Ass" | Case_aux c "E_Seq"
| Case_aux c "E_IfTrue" | Case_aux c "E_IfFalse"
| Case_aux c "E_WhileEnd" | Case_aux c "E_WhileLoop"
| Case_aux c "E_Havoc"
].
(** As a sanity check, the following claims should be provable for
your definition: *)
Example havoc_example1 : (HAVOC X) / empty_state || update empty_state X 0.
Proof.
constructor. Qed.
Example havoc_example2 :
(SKIP;; HAVOC Z) / empty_state || update empty_state Z 42.
Proof.
apply E_Seq with empty_state.
constructor. constructor.
Qed.
(** [] *)
(** Finally, we repeat the definition of command equivalence from above: *)
Definition cequiv (c1 c2 : com) : Prop := forall st st' : state,
c1 / st || st' <-> c2 / st || st'.
(** This definition still makes perfect sense in the case of always
terminating programs, so let's apply it to prove some
non-deterministic programs equivalent or non-equivalent. *)
(** **** Exercise: 3 stars (havoc_swap) *)
(** Are the following two programs equivalent? *)
Definition pXY :=
HAVOC X;; HAVOC Y.
Definition pYX :=
HAVOC Y;; HAVOC X.
(** If you think they are equivalent, prove it. If you think they are
not, prove that. *)
Theorem pXY_cequiv_pYX :
cequiv pXY pYX \/ ~ cequiv pXY pYX.
Proof.
left.
unfold pXY. unfold pYX.
split; intro H.
Case "<-".
inversion H; subst.
inversion H2; subst.
inversion H5; subst.
destruct (eq_id_dec X Y).
rewrite e in *.
apply E_Seq with (update st Y n).
constructor. constructor.
apply E_Seq with (update st Y n0).
constructor.
assert (update (update st X n) Y n0 =
update (update st Y n0) X n).
apply functional_extensionality.
intro Z. apply update_permute. assumption.
rewrite H0.
constructor.
Case "->".
inversion H; subst.
inversion H2; subst.
inversion H5; subst.
destruct (eq_id_dec X Y).
rewrite e in *.
apply E_Seq with (update st Y n).
constructor. constructor.
apply E_Seq with (update st X n0).
constructor.
assert (update (update st Y n) X n0 =
update (update st X n0) Y n).
apply functional_extensionality.
intro Z. apply update_permute.
intro. apply n1. rewrite H0. reflexivity.
rewrite H0.
constructor.
Qed.
(** [] *)
(** **** Exercise: 4 stars, optional (havoc_copy) *)
(** Are the following two programs equivalent? *)
Definition ptwice :=
HAVOC X;; HAVOC Y.
Definition pcopy :=
HAVOC X;; Y ::= AId X.
(** If you think they are equivalent, then prove it. If you think they
are not, then prove that. (Hint: You may find the [assert] tactic
useful.) *)
Theorem ptwice_cequiv_pcopy :
cequiv ptwice pcopy \/ ~cequiv ptwice pcopy.
Proof.
right. unfold ptwice. unfold pcopy.
intro contra.
unfold cequiv in contra.
remember (contra empty_state
(update (update empty_state X 0) Y 1)).
inversion i. clear H0. clear Heqi. clear i.
assert ((HAVOC X;; HAVOC Y) / empty_state ||
update (update empty_state X 0) Y 1).
apply E_Seq with (update empty_state X 0); constructor.
apply H in H0. clear H.
inversion H0; subst.
inversion H2; subst.
inversion H5; subst.
simpl in H6.
unfold update at 3 in H6.
rewrite eq_id in H6.
destruct (beq_nat n 0) eqn:HE.
apply beq_nat_true in HE. subst.
assert (update (update empty_state X 0) Y 1 Y =
update (update empty_state X 0) Y 0 Y).
rewrite H6. reflexivity.
rewrite update_eq in H. rewrite update_eq in H. inversion H.
apply beq_nat_false in HE.
assert (update (update empty_state X n) Y n X =
update (update empty_state X 0) Y 1 X).
rewrite H6. reflexivity.
rewrite update_neq in H.
symmetry in H.
rewrite update_neq in H.
rewrite update_eq in H. rewrite update_eq in H.
rewrite <-H in HE. apply HE. reflexivity.
intro. inversion H1. intro. inversion H1.
Qed.
(** [] *)
(** The definition of program equivalence we are using here has some
subtle consequences on programs that may loop forever. What
[cequiv] says is that the set of possible _terminating_ outcomes
of two equivalent programs is the same. However, in a language
with non-determinism, like Himp, some programs always terminate,
some programs always diverge, and some programs can
non-deterministically terminate in some runs and diverge in
others. The final part of the following exercise illustrates this
phenomenon.
*)
(** **** Exercise: 5 stars, advanced (p1_p2_equiv) *)
(** Prove that p1 and p2 are equivalent. In this and the following
exercises, try to understand why the [cequiv] definition has the
behavior it has on these examples. *)
Definition p1 : com :=
WHILE (BNot (BEq (AId X) (ANum 0))) DO
HAVOC Y;;
X ::= APlus (AId X) (ANum 1)
END.
Definition p2 : com :=
WHILE (BNot (BEq (AId X) (ANum 0))) DO
SKIP
END.
(** Intuitively, the programs have the same termination
behavior: either they loop forever, or they terminate in the
same state they started in. We can capture the termination
behavior of p1 and p2 individually with these lemmas: *)
(* ref: https://github.com/timjb/software-foundations/blob/master/Equiv.v#L1674 *)
Lemma p1_may_diverge : forall st st', st X <> 0 ->
~ p1 / st || st'.
Proof.
intros.
intro E.
remember p1 as p1. (* critical *)
ceval_cases (induction E) Case;
inversion Heqp1; subst.
Case "E_WhileEnd".
simpl in H0.
apply negb_false_iff in H0.
apply beq_nat_true in H0.
contradiction.
Case "E_WhileLoop".
apply IHE2.
inversion E1; subst.
inversion H3; subst.
inversion H6; subst.
simpl. unfold update. simpl. omega.
assumption.
Qed.
Lemma p2_may_diverge : forall st st', st X <> 0 ->
~ p2 / st || st'.
Proof.
intros. intro E.
remember p2 as p2.
ceval_cases (induction E) Case;
inversion Heqp2; subst.
Case "E_WhileEnd".
simpl in H0.
apply negb_false_iff in H0.
apply beq_nat_true in H0.
contradiction.
Case "E_WhileLoop".
apply IHE2.
inversion E1; subst.
simpl in H0.
apply negb_true_iff in H0.
apply beq_nat_false in H0.
assumption. assumption.
Qed.
(** You should use these lemmas to prove that p1 and p2 are actually
equivalent. *)
Theorem p1_p2_equiv : cequiv p1 p2.
Proof.
split; intro H.
Case "->".
destruct (st X) eqn:HX.
SCase "st X = 0".
inversion H; subst.
SSCase "E_WhileEnd".
apply E_WhileEnd. assumption. (* tricky *)
SSCase "E_WhileLoop".
simpl in H2. rewrite HX in H2. simpl in H2. inversion H2.
SCase "st X = S n".
assert (st X <> 0). rewrite HX; omega.
apply p1_may_diverge with (st:=st) (st':=st') in H0.
contradiction.
Case "<-".
destruct (st X) eqn:HX.
SCase "st X = 0".
inversion H; subst.
SSCase "E_WhileEnd".
apply E_WhileEnd. assumption.
SSCase "E_WhileLoop".
simpl in H2. rewrite HX in H2. simpl in H2. inversion H2.
SCase "st X = S n".
assert (st X <> 0). rewrite HX; omega.
apply p2_may_diverge with (st:=st) (st':=st') in H0.
contradiction.
Qed.
(** [] *)
(** **** Exercise: 4 stars, advanced (p3_p4_inquiv) *)
(** Prove that the following programs are _not_ equivalent. *)
Definition p3 : com :=
Z ::= ANum 1;;
WHILE (BNot (BEq (AId X) (ANum 0))) DO
HAVOC X;;
HAVOC Z
END.
Definition p4 : com :=
X ::= (ANum 0);;
Z ::= (ANum 1).
Theorem p3_p4_inequiv : ~ cequiv p3 p4.
Proof.
intro contra.
unfold cequiv in contra.
remember (contra (update empty_state X 1)
(update (update (update (update empty_state X 1) Z 1) X 0) Z 0)).
inversion i. clear contra Heqi i H0.
(* show p3 can do it *)
assert (p3 / update empty_state X 1 || (update (update (update (update empty_state X 1) Z 1) X 0) Z 0)).
apply E_Seq with (update (update empty_state X 1) Z 1).
apply E_Ass; reflexivity.
apply E_WhileLoop with (update (update (update (update empty_state X 1) Z 1) X 0) Z 0). reflexivity.
apply E_Seq with (update (update (update empty_state X 1) Z 1) X 0); apply E_Havoc.
apply E_WhileEnd; reflexivity.
(* show p4 cannot do it *)
apply H in H0. clear H.
inversion H0; subst.
inversion H2; subst.
inversion H5; subst.
simpl in H6.
assert ((update (update (update empty_state X 1) X 0) Z 1) Z = 1) by reflexivity.
rewrite H6 in H.
rewrite update_eq in H.
inversion H.
Qed.
(** [] *)
(** **** Exercise: 5 stars, advanced, optional (p5_p6_equiv) *)
Definition p5 : com :=
WHILE (BNot (BEq (AId X) (ANum 1))) DO
HAVOC X
END.
Definition p6 : com :=
X ::= ANum 1.
Theorem p5_fact_X :
forall st st', p5 / st || st' -> st' X = 1.
Proof.
intros.
remember p5 as p5.
ceval_cases (induction H) Case; inversion Heqp5; subst.
Case "E_WhileEnd".
simpl in H.
apply negb_false_iff in H.
apply beq_nat_true in H.
assumption.
Case "E_WhileLoop".
apply IHceval2.
assumption.
Qed.
Theorem p5_fact_others :
forall st st' Y,
X <> Y -> p5 / st || st' -> st Y = st' Y.
Proof.
intros.
remember p5 as p5.
ceval_cases (induction H0) Case; inversion Heqp5; subst.
reflexivity.
inversion H0_; subst.
rewrite update_neq in IHceval2.
apply IHceval2. assumption.
assumption.
Qed.
Theorem p5_p6_equiv : cequiv p5 p6.
Proof.
split; intro H.
Case "->".
assert (st' = update st X 1).
apply functional_extensionality.
intro Y. destruct (eq_id_dec X Y).
subst. rewrite update_eq.
apply p5_fact_X in H. assumption.
rewrite update_neq.
apply (p5_fact_others st st' Y) in H.
symmetry. assumption. assumption. assumption.
rewrite H0. apply E_Ass. reflexivity.
Case "<-".
inversion H; subst. simpl in *.
destruct (beq_nat (st X) 1) eqn:HX.
SCase "st X = 1".
apply beq_nat_true in HX.
assert (st = update st X 1).
rewrite <-HX.
apply functional_extensionality.
intro Y. destruct (eq_id_dec X Y).
subst. rewrite update_eq. reflexivity.
rewrite update_neq. reflexivity. assumption.
rewrite <-H0.
apply E_WhileEnd.
simpl. rewrite HX. reflexivity.
SCase "st X <> 1".
apply beq_nat_false in HX.
apply E_WhileLoop with (update st X 1).
simpl.
apply negb_true_iff.
rewrite false_beq_nat. reflexivity. assumption.
apply E_Havoc.
apply E_WhileEnd.
reflexivity.
Qed.
(** [] *)
End Himp.
(* ####################################################### *)
(** * Doing Without Extensionality (Optional) *)
(** Purists might object to using the [functional_extensionality]
axiom. In general, it can be quite dangerous to add axioms,
particularly several at once (as they may be mutually
inconsistent). In fact, [functional_extensionality] and
[excluded_middle] can both be assumed without any problems, but
some Coq users prefer to avoid such "heavyweight" general
techniques, and instead craft solutions for specific problems that
stay within Coq's standard logic.
For our particular problem here, rather than extending the
definition of equality to do what we want on functions
representing states, we could instead give an explicit notion of
_equivalence_ on states. For example: *)
Definition stequiv (st1 st2 : state) : Prop :=
forall (X:id), st1 X = st2 X.
Notation "st1 '~' st2" := (stequiv st1 st2) (at level 30).
(** It is easy to prove that [stequiv] is an _equivalence_ (i.e., it
is reflexive, symmetric, and transitive), so it partitions the set
of all states into equivalence classes. *)
(** **** Exercise: 1 star, optional (stequiv_refl) *)
Lemma stequiv_refl : forall (st : state),
st ~ st.
Proof.
unfold stequiv. intros. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 1 star, optional (stequiv_sym) *)
Lemma stequiv_sym : forall (st1 st2 : state),
st1 ~ st2 ->
st2 ~ st1.
Proof.
unfold stequiv. intros. symmetry. apply H.
Qed.
(** [] *)
(** **** Exercise: 1 star, optional (stequiv_trans) *)
Lemma stequiv_trans : forall (st1 st2 st3 : state),
st1 ~ st2 ->
st2 ~ st3 ->
st1 ~ st3.
Proof.
unfold stequiv. intros. rewrite H. rewrite H0. reflexivity.
Qed.
(** [] *)
(** Another useful fact... *)
(** **** Exercise: 1 star, optional (stequiv_update) *)
Lemma stequiv_update : forall (st1 st2 : state),
st1 ~ st2 ->
forall (X:id) (n:nat),
update st1 X n ~ update st2 X n.
Proof.
unfold stequiv. intros. unfold update.
destruct (eq_id_dec X X0) eqn:HX.
reflexivity. apply H.
Qed.
(** [] *)
(** It is then straightforward to show that [aeval] and [beval] behave
uniformly on all members of an equivalence class: *)
(** **** Exercise: 2 stars, optional (stequiv_aeval) *)
Lemma stequiv_aeval : forall (st1 st2 : state),
st1 ~ st2 ->
forall (a:aexp), aeval st1 a = aeval st2 a.
Proof.
intros.
aexp_cases (induction a) Case.
reflexivity.
simpl. rewrite H. reflexivity.
simpl. rewrite IHa1. rewrite IHa2. reflexivity.
simpl. rewrite IHa1. rewrite IHa2. reflexivity.
simpl. rewrite IHa1. rewrite IHa2. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 2 stars, optional (stequiv_beval) *)
Lemma stequiv_beval : forall (st1 st2 : state),
st1 ~ st2 ->
forall (b:bexp), beval st1 b = beval st2 b.
Proof.
intros.
bexp_cases (induction b) Case.
reflexivity. reflexivity.
simpl.
rewrite (stequiv_aeval st1 st2). rewrite (stequiv_aeval st1 st2).
reflexivity.
assumption. assumption.
simpl.
rewrite (stequiv_aeval st1 st2). rewrite (stequiv_aeval st1 st2).
reflexivity.
assumption. assumption.
simpl. rewrite IHb. reflexivity.
simpl. rewrite IHb1. rewrite IHb2. reflexivity.
Qed.
(** [] *)
(** We can also characterize the behavior of [ceval] on equivalent
states (this result is a bit more complicated to write down
because [ceval] is a relation). *)
Lemma stequiv_ceval: forall (st1 st2 : state),
st1 ~ st2 ->
forall (c: com) (st1': state),
(c / st1 || st1') ->
exists st2' : state,
((c / st2 || st2') /\ st1' ~ st2').
Proof.
intros st1 st2 STEQV c st1' CEV1. generalize dependent st2.
induction CEV1; intros st2 STEQV.
Case "SKIP".
exists st2. split.
constructor.
assumption.
Case ":=".
exists (update st2 x n). split.
constructor. rewrite <- H. symmetry. apply stequiv_aeval.
assumption. apply stequiv_update. assumption.
Case ";".
destruct (IHCEV1_1 st2 STEQV) as [st2' [P1 EQV1]].
destruct (IHCEV1_2 st2' EQV1) as [st2'' [P2 EQV2]].
exists st2''. split.
apply E_Seq with st2'; assumption.
assumption.
Case "IfTrue".
destruct (IHCEV1 st2 STEQV) as [st2' [P EQV]].
exists st2'. split.
apply E_IfTrue. rewrite <- H. symmetry. apply stequiv_beval.
assumption. assumption. assumption.
Case "IfFalse".
destruct (IHCEV1 st2 STEQV) as [st2' [P EQV]].
exists st2'. split.
apply E_IfFalse. rewrite <- H. symmetry. apply stequiv_beval.
assumption. assumption. assumption.
Case "WhileEnd".
exists st2. split.
apply E_WhileEnd. rewrite <- H. symmetry. apply stequiv_beval.
assumption. assumption.
Case "WhileLoop".
destruct (IHCEV1_1 st2 STEQV) as [st2' [P1 EQV1]].
destruct (IHCEV1_2 st2' EQV1) as [st2'' [P2 EQV2]].
exists st2''. split.
apply E_WhileLoop with st2'. rewrite <- H. symmetry.
apply stequiv_beval. assumption. assumption. assumption.
assumption.
Qed.
(** Now we need to redefine [cequiv] to use [~] instead of [=]. It is
not completely trivial to do this in a way that keeps the
definition simple and symmetric, but here is one approach (thanks
to Andrew McCreight). We first define a looser variant of [||]
that "folds in" the notion of equivalence. *)
Reserved Notation "c1 '/' st '||'' st'" (at level 40, st at level 39).
Inductive ceval' : com -> state -> state -> Prop :=
| E_equiv : forall c st st' st'',
c / st || st' ->
st' ~ st'' ->
c / st ||' st''
where "c1 '/' st '||'' st'" := (ceval' c1 st st').
(** Now the revised definition of [cequiv'] looks familiar: *)
Definition cequiv' (c1 c2 : com) : Prop :=
forall (st st' : state),
(c1 / st ||' st') <-> (c2 / st ||' st').
(** A sanity check shows that the original notion of command
equivalence is at least as strong as this new one. (The converse
is not true, naturally.) *)
Lemma cequiv__cequiv' : forall (c1 c2: com),
cequiv c1 c2 -> cequiv' c1 c2.
Proof.
unfold cequiv, cequiv'; split; intros.
inversion H0 ; subst. apply E_equiv with st'0.
apply (H st st'0); assumption. assumption.
inversion H0 ; subst. apply E_equiv with st'0.
apply (H st st'0). assumption. assumption.
Qed.
(** **** Exercise: 2 stars, optional (identity_assignment') *)
(** Finally, here is our example once more... (You can complete the
proof.) *)
Example identity_assignment' :
cequiv' SKIP (X ::= AId X).
Proof.
unfold cequiv'. intros. split; intros.
Case "->".
inversion H; subst; clear H. inversion H0; subst.
apply E_equiv with (update st'0 X (st'0 X)).
constructor. reflexivity. apply stequiv_trans with st'0.
unfold stequiv. intros. apply update_same.
reflexivity. assumption.
Case "<-".
inversion H; subst.
inversion H0; subst.
simpl in *.
apply E_equiv with st.
constructor.
unfold stequiv. intro Y. rewrite <-H1.
rewrite update_same; reflexivity.
Qed.
(** [] *)
(** On the whole, this explicit equivalence approach is considerably
harder to work with than relying on functional
extensionality. (Coq does have an advanced mechanism called
"setoids" that makes working with equivalences somewhat easier, by
allowing them to be registered with the system so that standard
rewriting tactics work for them almost as well as for equalities.)
But it is worth knowing about, because it applies even in
situations where the equivalence in question is _not_ over
functions. For example, if we chose to represent state mappings
as binary search trees, we would need to use an explicit
equivalence of this kind. *)
(* ####################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 4 stars, optional (for_while_equiv) *)
(** This exercise extends the optional [add_for_loop] exercise from
Imp.v, where you were asked to extend the language of commands
with C-style [for] loops. Prove that the command:
for (c1 ; b ; c2) {
c3
}
is equivalent to:
c1 ;
WHILE b DO
c3 ;
c2
END
*)
(* TODO: lazy *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 3 stars, optional (swap_noninterfering_assignments) *)
(* Hint: You'll need [functional_extensionality] *)
Theorem swap_noninterfering_assignments: forall l1 l2 a1 a2,
l1 <> l2 ->
var_not_used_in_aexp l1 a2 ->
var_not_used_in_aexp l2 a1 ->
cequiv
(l1 ::= a1;; l2 ::= a2)
(l2 ::= a2;; l1 ::= a1).
Proof.
unfold cequiv. intros.
(* important theorem *)
assert (update (update st l1 (aeval st a1)) l2
(aeval (update st l1 (aeval st a1)) a2) =
update (update st l2 (aeval st a2)) l1
(aeval (update st l2 (aeval st a2)) a1)).
assert (aeval (update st l1 (aeval st a1)) a2 = aeval st a2) by (apply aeval_weakening; assumption).
assert (aeval (update st l2 (aeval st a2)) a1 = aeval st a1) by (apply aeval_weakening; assumption).
rewrite H2. rewrite H3.
apply functional_extensionality.
intro l3.
destruct (eq_id_dec l1 l3) eqn:H13;
destruct (eq_id_dec l2 l3) eqn:H23.
SCase "l1 = l3, l2 = l3".
rewrite e in H; rewrite e0 in H;
apply ex_falso_quodlibet; apply H; reflexivity.
SCase "l1 = l3, l2 <> l3".
subst. rewrite update_neq. rewrite update_eq.
rewrite update_eq. reflexivity. assumption.
SCase "l1 <> l3, l2 = l3".
subst. rewrite update_eq. rewrite update_neq.
rewrite update_eq. reflexivity. assumption.
SCase "l1 <> l3, l2 <> l3".
repeat rewrite update_neq;
try reflexivity; assumption.
(* got it *)
split; intro E.
Case "->".
inversion E; subst.
inversion H5; subst.
inversion H8; subst.
rewrite H2.
apply E_Seq with (update st l2 (aeval st a2));
constructor; reflexivity.
Case "<-".
inversion E; subst.
inversion H5; subst.
inversion H8; subst.
rewrite <-H2.
apply E_Seq with (update st l1 (aeval st a1));
constructor; reflexivity.
Qed.
(** [] *)
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_rx_dma # (
parameter P_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36,
parameter C_M_AXI_DATA_WIDTH = 64
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input [2:0] pcie_max_read_req_size,
input pcie_rx_cmd_wr_en,
input [33:0] pcie_rx_cmd_wr_data,
output pcie_rx_cmd_full_n,
output tx_dma_mrd_req,
output [7:0] tx_dma_mrd_tag,
output [11:2] tx_dma_mrd_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_dma_mrd_addr,
input tx_dma_mrd_req_ack,
input [7:0] cpld_dma_fifo_tag,
input [P_PCIE_DATA_WIDTH-1:0] cpld_dma_fifo_wr_data,
input cpld_dma_fifo_wr_en,
input cpld_dma_fifo_tag_last,
input dma_bus_clk,
input dma_bus_rst_n,
input pcie_rx_fifo_rd_en,
output [C_M_AXI_DATA_WIDTH-1:0] pcie_rx_fifo_rd_data,
input pcie_rx_fifo_free_en,
input [9:4] pcie_rx_fifo_free_len,
output pcie_rx_fifo_empty_n
);
wire w_pcie_rx_cmd_rd_en;
wire [33:0] w_pcie_rx_cmd_rd_data;
wire w_pcie_rx_cmd_empty_n;
wire w_pcie_tag_alloc;
wire [7:0] w_pcie_alloc_tag;
wire [9:4] w_pcie_tag_alloc_len;
wire w_pcie_tag_full_n;
wire w_pcie_rx_fifo_full_n;
wire w_fifo_wr_en;
wire [8:0] w_fifo_wr_addr;
wire [127:0] w_fifo_wr_data;
wire [9:0] w_rear_full_addr;
wire [9:0] w_rear_addr;
pcie_rx_cmd_fifo
pcie_rx_cmd_fifo_inst0
(
.clk (pcie_user_clk),
.rst_n (pcie_user_rst_n),
.wr_en (pcie_rx_cmd_wr_en),
.wr_data (pcie_rx_cmd_wr_data),
.full_n (pcie_rx_cmd_full_n),
.rd_en (w_pcie_rx_cmd_rd_en),
.rd_data (w_pcie_rx_cmd_rd_data),
.empty_n (w_pcie_rx_cmd_empty_n)
);
pcie_rx_fifo
pcie_rx_fifo_inst0
(
.wr_clk (pcie_user_clk),
.wr_rst_n (pcie_user_rst_n),
.wr_en (w_fifo_wr_en),
.wr_addr (w_fifo_wr_addr),
.wr_data (w_fifo_wr_data),
.rear_full_addr (w_rear_full_addr),
.rear_addr (w_rear_addr),
.alloc_len (w_pcie_tag_alloc_len),
.full_n (w_pcie_rx_fifo_full_n),
.rd_clk (dma_bus_clk),
.rd_rst_n (pcie_user_rst_n),
.rd_en (pcie_rx_fifo_rd_en),
.rd_data (pcie_rx_fifo_rd_data),
.free_en (pcie_rx_fifo_free_en),
.free_len (pcie_rx_fifo_free_len),
.empty_n (pcie_rx_fifo_empty_n)
);
pcie_rx_tag
pcie_rx_tag_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_tag_alloc (w_pcie_tag_alloc),
.pcie_alloc_tag (w_pcie_alloc_tag),
.pcie_tag_alloc_len (w_pcie_tag_alloc_len),
.pcie_tag_full_n (w_pcie_tag_full_n),
.cpld_fifo_tag (cpld_dma_fifo_tag),
.cpld_fifo_wr_data (cpld_dma_fifo_wr_data),
.cpld_fifo_wr_en (cpld_dma_fifo_wr_en),
.cpld_fifo_tag_last (cpld_dma_fifo_tag_last),
.fifo_wr_en (w_fifo_wr_en),
.fifo_wr_addr (w_fifo_wr_addr),
.fifo_wr_data (w_fifo_wr_data),
.rear_full_addr (w_rear_full_addr),
.rear_addr (w_rear_addr)
);
pcie_rx_req # (
.P_PCIE_DATA_WIDTH (P_PCIE_DATA_WIDTH),
.C_PCIE_ADDR_WIDTH (C_PCIE_ADDR_WIDTH)
)
pcie_rx_req_inst0(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_max_read_req_size (pcie_max_read_req_size),
.pcie_rx_cmd_rd_en (w_pcie_rx_cmd_rd_en),
.pcie_rx_cmd_rd_data (w_pcie_rx_cmd_rd_data),
.pcie_rx_cmd_empty_n (w_pcie_rx_cmd_empty_n),
.pcie_tag_alloc (w_pcie_tag_alloc),
.pcie_alloc_tag (w_pcie_alloc_tag),
.pcie_tag_alloc_len (w_pcie_tag_alloc_len),
.pcie_tag_full_n (w_pcie_tag_full_n),
.pcie_rx_fifo_full_n (w_pcie_rx_fifo_full_n),
.tx_dma_mrd_req (tx_dma_mrd_req),
.tx_dma_mrd_tag (tx_dma_mrd_tag),
.tx_dma_mrd_len (tx_dma_mrd_len),
.tx_dma_mrd_addr (tx_dma_mrd_addr),
.tx_dma_mrd_req_ack (tx_dma_mrd_req_ack)
);
endmodule |
// $Id: rtr_flags_mux.v 5188 2012-08-30 00:31:31Z dub $
/*
Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// module for extracting the flags for a given port and packet class
//==============================================================================
module rtr_flags_mux
(sel_mc, route_op, route_orc, flags_op_opc, flags);
`include "c_functions.v"
`include "c_constants.v"
//---------------------------------------------------------------------------
// parameters
//---------------------------------------------------------------------------
// number of message classes (e.g. request, reply)
parameter num_message_classes = 2;
// number of resource classes (e.g. minimal, adaptive)
parameter num_resource_classes = 2;
// number of input and output ports on router
parameter num_ports = 5;
// width of flags
parameter width = 1;
//---------------------------------------------------------------------------
// derived parameters
//---------------------------------------------------------------------------
// total number of packet classes
localparam num_packet_classes = num_message_classes * num_resource_classes;
//---------------------------------------------------------------------------
// interface
//---------------------------------------------------------------------------
// current message class
input [0:num_message_classes-1] sel_mc;
// destination port
input [0:num_ports-1] route_op;
// destination resource class
input [0:num_resource_classes-1] route_orc;
// bit field of output VC flags of interest
input [0:num_ports*num_packet_classes*width-1] flags_op_opc;
// subset of bits that we are interested in
output [0:width-1] flags;
wire [0:width-1] flags;
//---------------------------------------------------------------------------
// implementation
//---------------------------------------------------------------------------
wire [0:num_packet_classes*width-1] flags_opc;
c_select_1ofn
#(.num_ports(num_ports),
.width(num_packet_classes*width))
flags_opc_sel
(.select(route_op),
.data_in(flags_op_opc),
.data_out(flags_opc));
wire [0:num_resource_classes*width-1] flags_orc;
c_select_1ofn
#(.num_ports(num_message_classes),
.width(num_resource_classes*width))
flags_orc_sel
(.select(sel_mc),
.data_in(flags_opc),
.data_out(flags_orc));
c_select_1ofn
#(.num_ports(num_resource_classes),
.width(width))
flags_sel
(.select(route_orc),
.data_in(flags_orc),
.data_out(flags));
endmodule
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_CPU_test_bench (
// inputs:
A_bstatus_reg,
A_cmp_result,
A_ctrl_exception,
A_ctrl_ld_non_bypass,
A_dst_regnum,
A_en,
A_estatus_reg,
A_ienable_reg,
A_ipending_reg,
A_iw,
A_mem_byte_en,
A_op_hbreak,
A_op_intr,
A_pcb,
A_st_data,
A_status_reg,
A_valid,
A_wr_data_unfiltered,
A_wr_dst_reg,
E_add_br_to_taken_history_unfiltered,
E_logic_result,
E_valid,
M_bht_ptr_unfiltered,
M_bht_wr_data_unfiltered,
M_bht_wr_en_unfiltered,
M_mem_baddr,
M_target_pcb,
M_valid,
W_dst_regnum,
W_iw,
W_iw_op,
W_iw_opx,
W_pcb,
W_valid,
W_vinst,
W_wr_dst_reg,
clk,
d_address,
d_byteenable,
d_read,
d_write,
i_address,
i_read,
i_readdatavalid,
reset_n,
// outputs:
A_wr_data_filtered,
E_add_br_to_taken_history_filtered,
E_src1_eq_src2,
M_bht_ptr_filtered,
M_bht_wr_data_filtered,
M_bht_wr_en_filtered,
test_has_ended
)
;
output [ 31: 0] A_wr_data_filtered;
output E_add_br_to_taken_history_filtered;
output E_src1_eq_src2;
output [ 7: 0] M_bht_ptr_filtered;
output [ 1: 0] M_bht_wr_data_filtered;
output M_bht_wr_en_filtered;
output test_has_ended;
input [ 31: 0] A_bstatus_reg;
input A_cmp_result;
input A_ctrl_exception;
input A_ctrl_ld_non_bypass;
input [ 4: 0] A_dst_regnum;
input A_en;
input [ 31: 0] A_estatus_reg;
input [ 31: 0] A_ienable_reg;
input [ 31: 0] A_ipending_reg;
input [ 31: 0] A_iw;
input [ 3: 0] A_mem_byte_en;
input A_op_hbreak;
input A_op_intr;
input [ 27: 0] A_pcb;
input [ 31: 0] A_st_data;
input [ 31: 0] A_status_reg;
input A_valid;
input [ 31: 0] A_wr_data_unfiltered;
input A_wr_dst_reg;
input E_add_br_to_taken_history_unfiltered;
input [ 31: 0] E_logic_result;
input E_valid;
input [ 7: 0] M_bht_ptr_unfiltered;
input [ 1: 0] M_bht_wr_data_unfiltered;
input M_bht_wr_en_unfiltered;
input [ 27: 0] M_mem_baddr;
input [ 27: 0] M_target_pcb;
input M_valid;
input [ 4: 0] W_dst_regnum;
input [ 31: 0] W_iw;
input [ 5: 0] W_iw_op;
input [ 5: 0] W_iw_opx;
input [ 27: 0] W_pcb;
input W_valid;
input [ 55: 0] W_vinst;
input W_wr_dst_reg;
input clk;
input [ 27: 0] d_address;
input [ 3: 0] d_byteenable;
input d_read;
input d_write;
input [ 27: 0] i_address;
input i_read;
input i_readdatavalid;
input reset_n;
reg [ 27: 0] A_mem_baddr;
reg [ 27: 0] A_target_pcb;
wire [ 31: 0] A_wr_data_filtered;
wire A_wr_data_unfiltered_0_is_x;
wire A_wr_data_unfiltered_10_is_x;
wire A_wr_data_unfiltered_11_is_x;
wire A_wr_data_unfiltered_12_is_x;
wire A_wr_data_unfiltered_13_is_x;
wire A_wr_data_unfiltered_14_is_x;
wire A_wr_data_unfiltered_15_is_x;
wire A_wr_data_unfiltered_16_is_x;
wire A_wr_data_unfiltered_17_is_x;
wire A_wr_data_unfiltered_18_is_x;
wire A_wr_data_unfiltered_19_is_x;
wire A_wr_data_unfiltered_1_is_x;
wire A_wr_data_unfiltered_20_is_x;
wire A_wr_data_unfiltered_21_is_x;
wire A_wr_data_unfiltered_22_is_x;
wire A_wr_data_unfiltered_23_is_x;
wire A_wr_data_unfiltered_24_is_x;
wire A_wr_data_unfiltered_25_is_x;
wire A_wr_data_unfiltered_26_is_x;
wire A_wr_data_unfiltered_27_is_x;
wire A_wr_data_unfiltered_28_is_x;
wire A_wr_data_unfiltered_29_is_x;
wire A_wr_data_unfiltered_2_is_x;
wire A_wr_data_unfiltered_30_is_x;
wire A_wr_data_unfiltered_31_is_x;
wire A_wr_data_unfiltered_3_is_x;
wire A_wr_data_unfiltered_4_is_x;
wire A_wr_data_unfiltered_5_is_x;
wire A_wr_data_unfiltered_6_is_x;
wire A_wr_data_unfiltered_7_is_x;
wire A_wr_data_unfiltered_8_is_x;
wire A_wr_data_unfiltered_9_is_x;
wire E_add_br_to_taken_history_filtered;
wire E_src1_eq_src2;
wire [ 7: 0] M_bht_ptr_filtered;
wire [ 1: 0] M_bht_wr_data_filtered;
wire M_bht_wr_en_filtered;
wire W_op_add;
wire W_op_addi;
wire W_op_and;
wire W_op_andhi;
wire W_op_andi;
wire W_op_beq;
wire W_op_bge;
wire W_op_bgeu;
wire W_op_blt;
wire W_op_bltu;
wire W_op_bne;
wire W_op_br;
wire W_op_break;
wire W_op_bret;
wire W_op_call;
wire W_op_callr;
wire W_op_cmpeq;
wire W_op_cmpeqi;
wire W_op_cmpge;
wire W_op_cmpgei;
wire W_op_cmpgeu;
wire W_op_cmpgeui;
wire W_op_cmplt;
wire W_op_cmplti;
wire W_op_cmpltu;
wire W_op_cmpltui;
wire W_op_cmpne;
wire W_op_cmpnei;
wire W_op_crst;
wire W_op_custom;
wire W_op_div;
wire W_op_divu;
wire W_op_eret;
wire W_op_flushd;
wire W_op_flushda;
wire W_op_flushi;
wire W_op_flushp;
wire W_op_hbreak;
wire W_op_initd;
wire W_op_initda;
wire W_op_initi;
wire W_op_intr;
wire W_op_jmp;
wire W_op_jmpi;
wire W_op_ldb;
wire W_op_ldbio;
wire W_op_ldbu;
wire W_op_ldbuio;
wire W_op_ldh;
wire W_op_ldhio;
wire W_op_ldhu;
wire W_op_ldhuio;
wire W_op_ldl;
wire W_op_ldw;
wire W_op_ldwio;
wire W_op_mul;
wire W_op_muli;
wire W_op_mulxss;
wire W_op_mulxsu;
wire W_op_mulxuu;
wire W_op_nextpc;
wire W_op_nor;
wire W_op_opx;
wire W_op_or;
wire W_op_orhi;
wire W_op_ori;
wire W_op_rdctl;
wire W_op_rdprs;
wire W_op_ret;
wire W_op_rol;
wire W_op_roli;
wire W_op_ror;
wire W_op_rsv02;
wire W_op_rsv09;
wire W_op_rsv10;
wire W_op_rsv17;
wire W_op_rsv18;
wire W_op_rsv25;
wire W_op_rsv26;
wire W_op_rsv33;
wire W_op_rsv34;
wire W_op_rsv41;
wire W_op_rsv42;
wire W_op_rsv49;
wire W_op_rsv57;
wire W_op_rsv61;
wire W_op_rsv62;
wire W_op_rsv63;
wire W_op_rsvx00;
wire W_op_rsvx10;
wire W_op_rsvx15;
wire W_op_rsvx17;
wire W_op_rsvx21;
wire W_op_rsvx25;
wire W_op_rsvx33;
wire W_op_rsvx34;
wire W_op_rsvx35;
wire W_op_rsvx42;
wire W_op_rsvx43;
wire W_op_rsvx44;
wire W_op_rsvx47;
wire W_op_rsvx50;
wire W_op_rsvx51;
wire W_op_rsvx55;
wire W_op_rsvx56;
wire W_op_rsvx60;
wire W_op_rsvx63;
wire W_op_sll;
wire W_op_slli;
wire W_op_sra;
wire W_op_srai;
wire W_op_srl;
wire W_op_srli;
wire W_op_stb;
wire W_op_stbio;
wire W_op_stc;
wire W_op_sth;
wire W_op_sthio;
wire W_op_stw;
wire W_op_stwio;
wire W_op_sub;
wire W_op_sync;
wire W_op_trap;
wire W_op_wrctl;
wire W_op_wrprs;
wire W_op_xor;
wire W_op_xorhi;
wire W_op_xori;
wire test_has_ended;
assign W_op_call = W_iw_op == 0;
assign W_op_jmpi = W_iw_op == 1;
assign W_op_ldbu = W_iw_op == 3;
assign W_op_addi = W_iw_op == 4;
assign W_op_stb = W_iw_op == 5;
assign W_op_br = W_iw_op == 6;
assign W_op_ldb = W_iw_op == 7;
assign W_op_cmpgei = W_iw_op == 8;
assign W_op_ldhu = W_iw_op == 11;
assign W_op_andi = W_iw_op == 12;
assign W_op_sth = W_iw_op == 13;
assign W_op_bge = W_iw_op == 14;
assign W_op_ldh = W_iw_op == 15;
assign W_op_cmplti = W_iw_op == 16;
assign W_op_initda = W_iw_op == 19;
assign W_op_ori = W_iw_op == 20;
assign W_op_stw = W_iw_op == 21;
assign W_op_blt = W_iw_op == 22;
assign W_op_ldw = W_iw_op == 23;
assign W_op_cmpnei = W_iw_op == 24;
assign W_op_flushda = W_iw_op == 27;
assign W_op_xori = W_iw_op == 28;
assign W_op_stc = W_iw_op == 29;
assign W_op_bne = W_iw_op == 30;
assign W_op_ldl = W_iw_op == 31;
assign W_op_cmpeqi = W_iw_op == 32;
assign W_op_ldbuio = W_iw_op == 35;
assign W_op_muli = W_iw_op == 36;
assign W_op_stbio = W_iw_op == 37;
assign W_op_beq = W_iw_op == 38;
assign W_op_ldbio = W_iw_op == 39;
assign W_op_cmpgeui = W_iw_op == 40;
assign W_op_ldhuio = W_iw_op == 43;
assign W_op_andhi = W_iw_op == 44;
assign W_op_sthio = W_iw_op == 45;
assign W_op_bgeu = W_iw_op == 46;
assign W_op_ldhio = W_iw_op == 47;
assign W_op_cmpltui = W_iw_op == 48;
assign W_op_initd = W_iw_op == 51;
assign W_op_orhi = W_iw_op == 52;
assign W_op_stwio = W_iw_op == 53;
assign W_op_bltu = W_iw_op == 54;
assign W_op_ldwio = W_iw_op == 55;
assign W_op_rdprs = W_iw_op == 56;
assign W_op_flushd = W_iw_op == 59;
assign W_op_xorhi = W_iw_op == 60;
assign W_op_rsv02 = W_iw_op == 2;
assign W_op_rsv09 = W_iw_op == 9;
assign W_op_rsv10 = W_iw_op == 10;
assign W_op_rsv17 = W_iw_op == 17;
assign W_op_rsv18 = W_iw_op == 18;
assign W_op_rsv25 = W_iw_op == 25;
assign W_op_rsv26 = W_iw_op == 26;
assign W_op_rsv33 = W_iw_op == 33;
assign W_op_rsv34 = W_iw_op == 34;
assign W_op_rsv41 = W_iw_op == 41;
assign W_op_rsv42 = W_iw_op == 42;
assign W_op_rsv49 = W_iw_op == 49;
assign W_op_rsv57 = W_iw_op == 57;
assign W_op_rsv61 = W_iw_op == 61;
assign W_op_rsv62 = W_iw_op == 62;
assign W_op_rsv63 = W_iw_op == 63;
assign W_op_eret = W_op_opx & (W_iw_opx == 1);
assign W_op_roli = W_op_opx & (W_iw_opx == 2);
assign W_op_rol = W_op_opx & (W_iw_opx == 3);
assign W_op_flushp = W_op_opx & (W_iw_opx == 4);
assign W_op_ret = W_op_opx & (W_iw_opx == 5);
assign W_op_nor = W_op_opx & (W_iw_opx == 6);
assign W_op_mulxuu = W_op_opx & (W_iw_opx == 7);
assign W_op_cmpge = W_op_opx & (W_iw_opx == 8);
assign W_op_bret = W_op_opx & (W_iw_opx == 9);
assign W_op_ror = W_op_opx & (W_iw_opx == 11);
assign W_op_flushi = W_op_opx & (W_iw_opx == 12);
assign W_op_jmp = W_op_opx & (W_iw_opx == 13);
assign W_op_and = W_op_opx & (W_iw_opx == 14);
assign W_op_cmplt = W_op_opx & (W_iw_opx == 16);
assign W_op_slli = W_op_opx & (W_iw_opx == 18);
assign W_op_sll = W_op_opx & (W_iw_opx == 19);
assign W_op_wrprs = W_op_opx & (W_iw_opx == 20);
assign W_op_or = W_op_opx & (W_iw_opx == 22);
assign W_op_mulxsu = W_op_opx & (W_iw_opx == 23);
assign W_op_cmpne = W_op_opx & (W_iw_opx == 24);
assign W_op_srli = W_op_opx & (W_iw_opx == 26);
assign W_op_srl = W_op_opx & (W_iw_opx == 27);
assign W_op_nextpc = W_op_opx & (W_iw_opx == 28);
assign W_op_callr = W_op_opx & (W_iw_opx == 29);
assign W_op_xor = W_op_opx & (W_iw_opx == 30);
assign W_op_mulxss = W_op_opx & (W_iw_opx == 31);
assign W_op_cmpeq = W_op_opx & (W_iw_opx == 32);
assign W_op_divu = W_op_opx & (W_iw_opx == 36);
assign W_op_div = W_op_opx & (W_iw_opx == 37);
assign W_op_rdctl = W_op_opx & (W_iw_opx == 38);
assign W_op_mul = W_op_opx & (W_iw_opx == 39);
assign W_op_cmpgeu = W_op_opx & (W_iw_opx == 40);
assign W_op_initi = W_op_opx & (W_iw_opx == 41);
assign W_op_trap = W_op_opx & (W_iw_opx == 45);
assign W_op_wrctl = W_op_opx & (W_iw_opx == 46);
assign W_op_cmpltu = W_op_opx & (W_iw_opx == 48);
assign W_op_add = W_op_opx & (W_iw_opx == 49);
assign W_op_break = W_op_opx & (W_iw_opx == 52);
assign W_op_hbreak = W_op_opx & (W_iw_opx == 53);
assign W_op_sync = W_op_opx & (W_iw_opx == 54);
assign W_op_sub = W_op_opx & (W_iw_opx == 57);
assign W_op_srai = W_op_opx & (W_iw_opx == 58);
assign W_op_sra = W_op_opx & (W_iw_opx == 59);
assign W_op_intr = W_op_opx & (W_iw_opx == 61);
assign W_op_crst = W_op_opx & (W_iw_opx == 62);
assign W_op_rsvx00 = W_op_opx & (W_iw_opx == 0);
assign W_op_rsvx10 = W_op_opx & (W_iw_opx == 10);
assign W_op_rsvx15 = W_op_opx & (W_iw_opx == 15);
assign W_op_rsvx17 = W_op_opx & (W_iw_opx == 17);
assign W_op_rsvx21 = W_op_opx & (W_iw_opx == 21);
assign W_op_rsvx25 = W_op_opx & (W_iw_opx == 25);
assign W_op_rsvx33 = W_op_opx & (W_iw_opx == 33);
assign W_op_rsvx34 = W_op_opx & (W_iw_opx == 34);
assign W_op_rsvx35 = W_op_opx & (W_iw_opx == 35);
assign W_op_rsvx42 = W_op_opx & (W_iw_opx == 42);
assign W_op_rsvx43 = W_op_opx & (W_iw_opx == 43);
assign W_op_rsvx44 = W_op_opx & (W_iw_opx == 44);
assign W_op_rsvx47 = W_op_opx & (W_iw_opx == 47);
assign W_op_rsvx50 = W_op_opx & (W_iw_opx == 50);
assign W_op_rsvx51 = W_op_opx & (W_iw_opx == 51);
assign W_op_rsvx55 = W_op_opx & (W_iw_opx == 55);
assign W_op_rsvx56 = W_op_opx & (W_iw_opx == 56);
assign W_op_rsvx60 = W_op_opx & (W_iw_opx == 60);
assign W_op_rsvx63 = W_op_opx & (W_iw_opx == 63);
assign W_op_opx = W_iw_op == 58;
assign W_op_custom = W_iw_op == 50;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
A_target_pcb <= 0;
else if (A_en)
A_target_pcb <= M_target_pcb;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
A_mem_baddr <= 0;
else if (A_en)
A_mem_baddr <= M_mem_baddr;
end
assign E_src1_eq_src2 = E_logic_result == 0;
//Propagating 'X' data bits
assign E_add_br_to_taken_history_filtered = E_add_br_to_taken_history_unfiltered;
//Propagating 'X' data bits
assign M_bht_wr_en_filtered = M_bht_wr_en_unfiltered;
//Propagating 'X' data bits
assign M_bht_wr_data_filtered = M_bht_wr_data_unfiltered;
//Propagating 'X' data bits
assign M_bht_ptr_filtered = M_bht_ptr_unfiltered;
assign test_has_ended = 1'b0;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//Clearing 'X' data bits
assign A_wr_data_unfiltered_0_is_x = ^(A_wr_data_unfiltered[0]) === 1'bx;
assign A_wr_data_filtered[0] = (A_wr_data_unfiltered_0_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[0];
assign A_wr_data_unfiltered_1_is_x = ^(A_wr_data_unfiltered[1]) === 1'bx;
assign A_wr_data_filtered[1] = (A_wr_data_unfiltered_1_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[1];
assign A_wr_data_unfiltered_2_is_x = ^(A_wr_data_unfiltered[2]) === 1'bx;
assign A_wr_data_filtered[2] = (A_wr_data_unfiltered_2_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[2];
assign A_wr_data_unfiltered_3_is_x = ^(A_wr_data_unfiltered[3]) === 1'bx;
assign A_wr_data_filtered[3] = (A_wr_data_unfiltered_3_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[3];
assign A_wr_data_unfiltered_4_is_x = ^(A_wr_data_unfiltered[4]) === 1'bx;
assign A_wr_data_filtered[4] = (A_wr_data_unfiltered_4_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[4];
assign A_wr_data_unfiltered_5_is_x = ^(A_wr_data_unfiltered[5]) === 1'bx;
assign A_wr_data_filtered[5] = (A_wr_data_unfiltered_5_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[5];
assign A_wr_data_unfiltered_6_is_x = ^(A_wr_data_unfiltered[6]) === 1'bx;
assign A_wr_data_filtered[6] = (A_wr_data_unfiltered_6_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[6];
assign A_wr_data_unfiltered_7_is_x = ^(A_wr_data_unfiltered[7]) === 1'bx;
assign A_wr_data_filtered[7] = (A_wr_data_unfiltered_7_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[7];
assign A_wr_data_unfiltered_8_is_x = ^(A_wr_data_unfiltered[8]) === 1'bx;
assign A_wr_data_filtered[8] = (A_wr_data_unfiltered_8_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[8];
assign A_wr_data_unfiltered_9_is_x = ^(A_wr_data_unfiltered[9]) === 1'bx;
assign A_wr_data_filtered[9] = (A_wr_data_unfiltered_9_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[9];
assign A_wr_data_unfiltered_10_is_x = ^(A_wr_data_unfiltered[10]) === 1'bx;
assign A_wr_data_filtered[10] = (A_wr_data_unfiltered_10_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[10];
assign A_wr_data_unfiltered_11_is_x = ^(A_wr_data_unfiltered[11]) === 1'bx;
assign A_wr_data_filtered[11] = (A_wr_data_unfiltered_11_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[11];
assign A_wr_data_unfiltered_12_is_x = ^(A_wr_data_unfiltered[12]) === 1'bx;
assign A_wr_data_filtered[12] = (A_wr_data_unfiltered_12_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[12];
assign A_wr_data_unfiltered_13_is_x = ^(A_wr_data_unfiltered[13]) === 1'bx;
assign A_wr_data_filtered[13] = (A_wr_data_unfiltered_13_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[13];
assign A_wr_data_unfiltered_14_is_x = ^(A_wr_data_unfiltered[14]) === 1'bx;
assign A_wr_data_filtered[14] = (A_wr_data_unfiltered_14_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[14];
assign A_wr_data_unfiltered_15_is_x = ^(A_wr_data_unfiltered[15]) === 1'bx;
assign A_wr_data_filtered[15] = (A_wr_data_unfiltered_15_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[15];
assign A_wr_data_unfiltered_16_is_x = ^(A_wr_data_unfiltered[16]) === 1'bx;
assign A_wr_data_filtered[16] = (A_wr_data_unfiltered_16_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[16];
assign A_wr_data_unfiltered_17_is_x = ^(A_wr_data_unfiltered[17]) === 1'bx;
assign A_wr_data_filtered[17] = (A_wr_data_unfiltered_17_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[17];
assign A_wr_data_unfiltered_18_is_x = ^(A_wr_data_unfiltered[18]) === 1'bx;
assign A_wr_data_filtered[18] = (A_wr_data_unfiltered_18_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[18];
assign A_wr_data_unfiltered_19_is_x = ^(A_wr_data_unfiltered[19]) === 1'bx;
assign A_wr_data_filtered[19] = (A_wr_data_unfiltered_19_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[19];
assign A_wr_data_unfiltered_20_is_x = ^(A_wr_data_unfiltered[20]) === 1'bx;
assign A_wr_data_filtered[20] = (A_wr_data_unfiltered_20_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[20];
assign A_wr_data_unfiltered_21_is_x = ^(A_wr_data_unfiltered[21]) === 1'bx;
assign A_wr_data_filtered[21] = (A_wr_data_unfiltered_21_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[21];
assign A_wr_data_unfiltered_22_is_x = ^(A_wr_data_unfiltered[22]) === 1'bx;
assign A_wr_data_filtered[22] = (A_wr_data_unfiltered_22_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[22];
assign A_wr_data_unfiltered_23_is_x = ^(A_wr_data_unfiltered[23]) === 1'bx;
assign A_wr_data_filtered[23] = (A_wr_data_unfiltered_23_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[23];
assign A_wr_data_unfiltered_24_is_x = ^(A_wr_data_unfiltered[24]) === 1'bx;
assign A_wr_data_filtered[24] = (A_wr_data_unfiltered_24_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[24];
assign A_wr_data_unfiltered_25_is_x = ^(A_wr_data_unfiltered[25]) === 1'bx;
assign A_wr_data_filtered[25] = (A_wr_data_unfiltered_25_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[25];
assign A_wr_data_unfiltered_26_is_x = ^(A_wr_data_unfiltered[26]) === 1'bx;
assign A_wr_data_filtered[26] = (A_wr_data_unfiltered_26_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[26];
assign A_wr_data_unfiltered_27_is_x = ^(A_wr_data_unfiltered[27]) === 1'bx;
assign A_wr_data_filtered[27] = (A_wr_data_unfiltered_27_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[27];
assign A_wr_data_unfiltered_28_is_x = ^(A_wr_data_unfiltered[28]) === 1'bx;
assign A_wr_data_filtered[28] = (A_wr_data_unfiltered_28_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[28];
assign A_wr_data_unfiltered_29_is_x = ^(A_wr_data_unfiltered[29]) === 1'bx;
assign A_wr_data_filtered[29] = (A_wr_data_unfiltered_29_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[29];
assign A_wr_data_unfiltered_30_is_x = ^(A_wr_data_unfiltered[30]) === 1'bx;
assign A_wr_data_filtered[30] = (A_wr_data_unfiltered_30_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[30];
assign A_wr_data_unfiltered_31_is_x = ^(A_wr_data_unfiltered[31]) === 1'bx;
assign A_wr_data_filtered[31] = (A_wr_data_unfiltered_31_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[31];
always @(posedge clk)
begin
if (reset_n)
if (^(W_wr_dst_reg) === 1'bx)
begin
$write("%0d ns: ERROR: nios_system_CPU_test_bench/W_wr_dst_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_wr_dst_reg)
if (^(W_dst_regnum) === 1'bx)
begin
$write("%0d ns: ERROR: nios_system_CPU_test_bench/W_dst_regnum is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(W_valid) === 1'bx)
begin
$write("%0d ns: ERROR: nios_system_CPU_test_bench/W_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid)
if (^(W_pcb) === 1'bx)
begin
$write("%0d ns: ERROR: nios_system_CPU_test_bench/W_pcb is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid)
if (^(W_iw) === 1'bx)
begin
$write("%0d ns: ERROR: nios_system_CPU_test_bench/W_iw is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(A_en) === 1'bx)
begin
$write("%0d ns: ERROR: nios_system_CPU_test_bench/A_en is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(E_valid) === 1'bx)
begin
$write("%0d ns: ERROR: nios_system_CPU_test_bench/E_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(M_valid) === 1'bx)
begin
$write("%0d ns: ERROR: nios_system_CPU_test_bench/M_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(A_valid) === 1'bx)
begin
$write("%0d ns: ERROR: nios_system_CPU_test_bench/A_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (A_valid & A_en & A_wr_dst_reg)
if (^(A_wr_data_unfiltered) === 1'bx)
begin
$write("%0d ns: WARNING: nios_system_CPU_test_bench/A_wr_data_unfiltered is 'x'\n", $time);
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(A_status_reg) === 1'bx)
begin
$write("%0d ns: ERROR: nios_system_CPU_test_bench/A_status_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(A_estatus_reg) === 1'bx)
begin
$write("%0d ns: ERROR: nios_system_CPU_test_bench/A_estatus_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(A_bstatus_reg) === 1'bx)
begin
$write("%0d ns: ERROR: nios_system_CPU_test_bench/A_bstatus_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(i_read) === 1'bx)
begin
$write("%0d ns: ERROR: nios_system_CPU_test_bench/i_read is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (i_read)
if (^(i_address) === 1'bx)
begin
$write("%0d ns: ERROR: nios_system_CPU_test_bench/i_address is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(i_readdatavalid) === 1'bx)
begin
$write("%0d ns: ERROR: nios_system_CPU_test_bench/i_readdatavalid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(d_write) === 1'bx)
begin
$write("%0d ns: ERROR: nios_system_CPU_test_bench/d_write is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (d_write)
if (^(d_byteenable) === 1'bx)
begin
$write("%0d ns: ERROR: nios_system_CPU_test_bench/d_byteenable is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (d_write | d_read)
if (^(d_address) === 1'bx)
begin
$write("%0d ns: ERROR: nios_system_CPU_test_bench/d_address is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(d_read) === 1'bx)
begin
$write("%0d ns: ERROR: nios_system_CPU_test_bench/d_read is 'x'\n", $time);
$stop;
end
end
reg [31:0] trace_handle; // for $fopen
initial
begin
trace_handle = $fopen("nios_system_CPU.tr");
$fwrite(trace_handle, "version 3\nnumThreads 1\n");
end
always @(posedge clk)
begin
if ((~reset_n || (A_valid & A_en)) && ~test_has_ended)
$fwrite(trace_handle, "%0d ns: %0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h\n", $time, ~reset_n, A_pcb, 0, A_op_intr, A_op_hbreak, A_iw, ~(A_op_intr | A_op_hbreak), A_wr_dst_reg, A_dst_regnum, 0, A_wr_data_filtered, A_mem_baddr, A_st_data, A_mem_byte_en, A_cmp_result, A_target_pcb, A_status_reg, A_estatus_reg, A_bstatus_reg, A_ienable_reg, A_ipending_reg, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, A_ctrl_exception ? 1 : 0, 0, 0, 0, 0);
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
//
// assign A_wr_data_filtered = A_wr_data_unfiltered;
//
//synthesis read_comments_as_HDL off
endmodule
|
module digit_state_machine(
input clk,
input reset_n,
input [3:0] units,
input [3:0] tens,
input [3:0] hundreds,
input [3:0] thousands,
output reg [2:0] digit_select,
output reg [3:0] data,
output reg decimal_point
);
reg [1:0] state;
reg [1:0] state_n;
parameter S0 = 2'b00;
parameter S1 = 2'b01;
parameter S2 = 2'b10;
parameter S3 = 2'b11;
always @ (posedge clk, negedge reset_n)
begin
if(!reset_n)
state <= S0;
else
state <= state_n;
end
always @ (*)
begin
case(state)
S0: state_n = S1;
S1: state_n = S2;
S2: state_n = S3;
S3: state_n = S0;
default: state_n = S0;
endcase
end
always @ (*)
begin
case(state)
S0: begin
decimal_point = 1;
digit_select = 3'b000;
data = units;
end
S1: begin
decimal_point = 1;
digit_select = 3'b001;
data = tens;
end
S2: begin
decimal_point = 1;
digit_select = 3'b011;
data = hundreds;
end
S3: begin
decimal_point = 0;
digit_select = 3'b100;
data = thousands;
end
endcase
end
endmodule |
/*
* Simple GPIO module with configurable bus width
*
* First 32 bit word is the GPIO I/O reg
* Second 32 bit word is the direction register
* If the bus width is less than 32 bits MSB registers are undefined.
*
* Set direction bit to '1' to output corresponding data bit.
*
* Register mapping:
*
* adr 0-3:
* gpio data
* adr 4-7:
* gpio dir
*/
module wb_gpio
#(
parameter n_bits = 32 // bus width, range 1:32
)
(
input wb_clk,
input wb_rst,
input [2:2] wb_adr_i,
input [n_bits-1:0] wb_dat_i,
input wb_we_i,
input wb_cyc_i,
input wb_stb_i,
input [2:0] wb_cti_i,
input [1:0] wb_bte_i,
output reg [n_bits-1:0] wb_dat_o,
output reg wb_ack_o,
output wb_err_o,
output wb_rty_o,
input [n_bits-1:0] gpio_i,
output reg [n_bits-1:0] gpio_o,
output reg [n_bits-1:0] gpio_dir_o
);
// GPIO dir register
always @(posedge wb_clk)
if (wb_rst)
gpio_dir_o <= 0; // All set to in at reset
else if (wb_cyc_i & wb_stb_i & wb_we_i) begin
if (wb_adr_i[2] == 1)
gpio_dir_o <= wb_dat_i[n_bits-1:0];
end
// GPIO data out register
always @(posedge wb_clk)
if (wb_rst)
gpio_o <= 0;
else if (wb_cyc_i & wb_stb_i & wb_we_i) begin
if (wb_adr_i[2] == 0)
gpio_o <= wb_dat_i[n_bits-1:0];
end
// Register the gpio in signal
reg [n_bits-1:0] gpio_i_ff;
always @(posedge wb_clk) begin
// Synchronize gpio_i
// single ff because the second ff only adds enable logic and clk freq is low
gpio_i_ff <= gpio_i;
// Data regs
if (wb_adr_i[2] == 0)
wb_dat_o <= gpio_i_ff;
// Direction regs
if (wb_adr_i[2] == 1)
wb_dat_o <= gpio_dir_o;
end
// Ack generation
always @(posedge wb_clk)
if (wb_rst)
wb_ack_o <= 0;
else if (wb_ack_o)
wb_ack_o <= 0;
else if (wb_cyc_i & wb_stb_i & !wb_ack_o)
wb_ack_o <= 1;
assign wb_err_o = 0;
assign wb_rty_o = 0;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/10/2016 04:46:19 PM
// Design Name:
// Module Name: exp_operation
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Exp_Operation
#(parameter EW = 8) //Exponent Width
(
input wire clk, //system clock
input wire rst, //reset of the module
input wire load_a_i,
input wire load_b_i,
input wire [EW-1:0] Data_A_i,
input wire [EW-1:0] Data_B_i,
input wire Add_Subt_i,
///////////////////////////////////////////////////////////////////77
output wire [EW-1:0] Data_Result_o,
output wire Overflow_flag_o,
output wire Underflow_flag_o
);
//wire [EW-1:0] Data_B;
wire [EW:0] Data_S;
/////////////////////////////////////////7
//genvar j;
//for (j=0; j<EW; j=j+1)begin
// assign Data_B[j] = PreData_B_i[j] ^ Add_Subt_i;
//end
/////////////////////////////////////////
add_sub_carry_out #(.W(EW)) exp_add_subt(
.op_mode (Add_Subt_i),
.Data_A (Data_A_i),
.Data_B (Data_B_i),
.Data_S (Data_S)
);
//assign Overflow_flag_o = 1'b0;
//assign Underflow_flag_o = 1'b0;
Comparators #(.W_Exp(EW+1)) array_comparators(
.exp(Data_S),
.overflow(Overflow_flag),
.underflow(Underflow_flag)
);
RegisterAdd #(.W(EW)) exp_result(
.clk (clk),
.rst (rst),
.load (load_a_i),
.D (Data_S[EW-1:0]),
.Q (Data_Result_o)
);
RegisterAdd #(.W(1)) Overflow (
.clk(clk),
.rst(rst),
.load(load_a_i),
.D(Overflow_flag),
.Q(Overflow_flag_o)
);
RegisterAdd #(.W(1)) Underflow (
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Underflow_flag),
.Q(Underflow_flag_o)
);
endmodule
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2015 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
Require Setoid.
Require Import PeanoNat Le Gt Minus Bool Lt.
Set Implicit Arguments.
(* Set Universe Polymorphism. *)
(******************************************************************)
(** * Basics: definition of polymorphic lists and some operations *)
(******************************************************************)
(** The definition of [list] is now in [Init/Datatypes],
as well as the definitions of [length] and [app] *)
Open Scope list_scope.
(** Standard notations for lists.
In a special module to avoid conflicts. *)
Module ListNotations.
Notation " [ ] " := nil (format "[ ]") : list_scope.
Notation " [ x ] " := (cons x nil) : list_scope.
Notation " [ x ; .. ; y ] " := (cons x .. (cons y nil) ..) : list_scope.
End ListNotations.
Import ListNotations.
Section Lists.
Variable A : Type.
(** Head and tail *)
Definition hd (default:A) (l:list A) :=
match l with
| [] => default
| x :: _ => x
end.
Definition hd_error (l:list A) :=
match l with
| [] => None
| x :: _ => Some x
end.
Definition tl (l:list A) :=
match l with
| [] => nil
| a :: m => m
end.
(** The [In] predicate *)
Fixpoint In (a:A) (l:list A) : Prop :=
match l with
| [] => False
| b :: m => b = a \/ In a m
end.
End Lists.
Section Facts.
Variable A : Type.
(** *** Genereric facts *)
(** Discrimination *)
Theorem nil_cons : forall (x:A) (l:list A), [] <> x :: l.
Proof.
intros; discriminate.
Qed.
(** Destruction *)
Theorem destruct_list : forall l : list A, {x:A & {tl:list A | l = x::tl}}+{l = []}.
Proof.
induction l as [|a tail].
right; reflexivity.
left; exists a, tail; reflexivity.
Qed.
Lemma hd_error_tl_repr : forall l (a:A) r,
hd_error l = Some a /\ tl l = r <-> l = a :: r.
Proof. destruct l as [|x xs].
- unfold hd_error, tl; intros a r. split; firstorder discriminate.
- intros. simpl. split.
* intros (H1, H2). inversion H1. rewrite H2. reflexivity.
* inversion 1. subst. auto.
Qed.
Lemma hd_error_some_nil : forall l (a:A), hd_error l = Some a -> l <> nil.
Proof. unfold hd_error. destruct l; now discriminate. Qed.
Theorem length_zero_iff_nil (l : list A):
length l = 0 <-> l=[].
Proof.
split; [now destruct l | now intros ->].
Qed.
(** *** Head and tail *)
Theorem hd_error_nil : hd_error (@nil A) = None.
Proof.
simpl; reflexivity.
Qed.
Theorem hd_error_cons : forall (l : list A) (x : A), hd_error (x::l) = Some x.
Proof.
intros; simpl; reflexivity.
Qed.
(************************)
(** *** Facts about [In] *)
(************************)
(** Characterization of [In] *)
Theorem in_eq : forall (a:A) (l:list A), In a (a :: l).
Proof.
simpl; auto.
Qed.
Theorem in_cons : forall (a b:A) (l:list A), In b l -> In b (a :: l).
Proof.
simpl; auto.
Qed.
Theorem not_in_cons (x a : A) (l : list A):
~ In x (a::l) <-> x<>a /\ ~ In x l.
Proof.
simpl. intuition.
Qed.
Theorem in_nil : forall a:A, ~ In a [].
Proof.
unfold not; intros a H; inversion_clear H.
Qed.
Theorem in_split : forall x (l:list A), In x l -> exists l1 l2, l = l1++x::l2.
Proof.
induction l; simpl; destruct 1.
subst a; auto.
exists [], l; auto.
destruct (IHl H) as (l1,(l2,H0)).
exists (a::l1), l2; simpl. apply f_equal. auto.
Qed.
(** Inversion *)
Lemma in_inv : forall (a b:A) (l:list A), In b (a :: l) -> a = b \/ In b l.
Proof.
intros a b l H; inversion_clear H; auto.
Qed.
(** Decidability of [In] *)
Theorem in_dec :
(forall x y:A, {x = y} + {x <> y}) ->
forall (a:A) (l:list A), {In a l} + {~ In a l}.
Proof.
intro H; induction l as [| a0 l IHl].
right; apply in_nil.
destruct (H a0 a); simpl; auto.
destruct IHl; simpl; auto.
right; unfold not; intros [Hc1| Hc2]; auto.
Defined.
(**************************)
(** *** Facts about [app] *)
(**************************)
(** Discrimination *)
Theorem app_cons_not_nil : forall (x y:list A) (a:A), [] <> x ++ a :: y.
Proof.
unfold not.
destruct x as [| a l]; simpl; intros.
discriminate H.
discriminate H.
Qed.
(** Concat with [nil] *)
Theorem app_nil_l : forall l:list A, [] ++ l = l.
Proof.
reflexivity.
Qed.
Theorem app_nil_r : forall l:list A, l ++ [] = l.
Proof.
induction l; simpl; f_equal; auto.
Qed.
(* begin hide *)
(* Deprecated *)
Theorem app_nil_end : forall (l:list A), l = l ++ [].
Proof. symmetry; apply app_nil_r. Qed.
(* end hide *)
(** [app] is associative *)
Theorem app_assoc : forall l m n:list A, l ++ m ++ n = (l ++ m) ++ n.
Proof.
intros l m n; induction l; simpl; f_equal; auto.
Qed.
(* begin hide *)
(* Deprecated *)
Theorem app_assoc_reverse : forall l m n:list A, (l ++ m) ++ n = l ++ m ++ n.
Proof.
auto using app_assoc.
Qed.
Hint Resolve app_assoc_reverse.
(* end hide *)
(** [app] commutes with [cons] *)
Theorem app_comm_cons : forall (x y:list A) (a:A), a :: (x ++ y) = (a :: x) ++ y.
Proof.
auto.
Qed.
(** Facts deduced from the result of a concatenation *)
Theorem app_eq_nil : forall l l':list A, l ++ l' = [] -> l = [] /\ l' = [].
Proof.
destruct l as [| x l]; destruct l' as [| y l']; simpl; auto.
intro; discriminate.
intros H; discriminate H.
Qed.
Theorem app_eq_unit :
forall (x y:list A) (a:A),
x ++ y = [a] -> x = [] /\ y = [a] \/ x = [a] /\ y = [].
Proof.
destruct x as [| a l]; [ destruct y as [| a l] | destruct y as [| a0 l0] ];
simpl.
intros a H; discriminate H.
left; split; auto.
right; split; auto.
generalize H.
generalize (app_nil_r l); intros E.
rewrite -> E; auto.
intros.
injection H.
intro.
assert ([] = l ++ a0 :: l0) by auto.
apply app_cons_not_nil in H1 as [].
Qed.
Lemma app_inj_tail :
forall (x y:list A) (a b:A), x ++ [a] = y ++ [b] -> x = y /\ a = b.
Proof.
induction x as [| x l IHl];
[ destruct y as [| a l] | destruct y as [| a l0] ];
simpl; auto.
- intros a b H.
injection H.
auto.
- intros a0 b H.
injection H as H1 H0.
apply app_cons_not_nil in H0 as [].
- intros a b H.
injection H as H1 H0.
assert ([] = l ++ [a]) by auto.
apply app_cons_not_nil in H as [].
- intros a0 b H.
injection H as <- H0.
destruct (IHl l0 a0 b H0) as (<-,<-).
split; auto.
Qed.
(** Compatibility with other operations *)
Lemma app_length : forall l l' : list A, length (l++l') = length l + length l'.
Proof.
induction l; simpl; auto.
Qed.
Lemma in_app_or : forall (l m:list A) (a:A), In a (l ++ m) -> In a l \/ In a m.
Proof.
intros l m a.
elim l; simpl; auto.
intros a0 y H H0.
now_show ((a0 = a \/ In a y) \/ In a m).
elim H0; auto.
intro H1.
now_show ((a0 = a \/ In a y) \/ In a m).
elim (H H1); auto.
Qed.
Lemma in_or_app : forall (l m:list A) (a:A), In a l \/ In a m -> In a (l ++ m).
Proof.
intros l m a.
elim l; simpl; intro H.
now_show (In a m).
elim H; auto; intro H0.
now_show (In a m).
elim H0. (* subProof completed *)
intros y H0 H1.
now_show (H = a \/ In a (y ++ m)).
elim H1; auto 4.
intro H2.
now_show (H = a \/ In a (y ++ m)).
elim H2; auto.
Qed.
Lemma in_app_iff : forall l l' (a:A), In a (l++l') <-> In a l \/ In a l'.
Proof.
split; auto using in_app_or, in_or_app.
Qed.
Lemma app_inv_head:
forall l l1 l2 : list A, l ++ l1 = l ++ l2 -> l1 = l2.
Proof.
induction l; simpl; auto; injection 1; auto.
Qed.
Lemma app_inv_tail:
forall l l1 l2 : list A, l1 ++ l = l2 ++ l -> l1 = l2.
Proof.
intros l l1 l2; revert l1 l2 l.
induction l1 as [ | x1 l1]; destruct l2 as [ | x2 l2];
simpl; auto; intros l H.
absurd (length (x2 :: l2 ++ l) <= length l).
simpl; rewrite app_length; auto with arith.
rewrite <- H; auto with arith.
absurd (length (x1 :: l1 ++ l) <= length l).
simpl; rewrite app_length; auto with arith.
rewrite H; auto with arith.
injection H; clear H; intros; f_equal; eauto.
Qed.
End Facts.
Hint Resolve app_assoc app_assoc_reverse: datatypes v62.
Hint Resolve app_comm_cons app_cons_not_nil: datatypes v62.
Hint Immediate app_eq_nil: datatypes v62.
Hint Resolve app_eq_unit app_inj_tail: datatypes v62.
Hint Resolve in_eq in_cons in_inv in_nil in_app_or in_or_app: datatypes v62.
(*******************************************)
(** * Operations on the elements of a list *)
(*******************************************)
Section Elts.
Variable A : Type.
(*****************************)
(** ** Nth element of a list *)
(*****************************)
Fixpoint nth (n:nat) (l:list A) (default:A) {struct l} : A :=
match n, l with
| O, x :: l' => x
| O, other => default
| S m, [] => default
| S m, x :: t => nth m t default
end.
Fixpoint nth_ok (n:nat) (l:list A) (default:A) {struct l} : bool :=
match n, l with
| O, x :: l' => true
| O, other => false
| S m, [] => false
| S m, x :: t => nth_ok m t default
end.
Lemma nth_in_or_default :
forall (n:nat) (l:list A) (d:A), {In (nth n l d) l} + {nth n l d = d}.
Proof.
intros n l d; revert n; induction l.
- right; destruct n; trivial.
- intros [|n]; simpl.
* left; auto.
* destruct (IHl n); auto.
Qed.
Lemma nth_S_cons :
forall (n:nat) (l:list A) (d a:A),
In (nth n l d) l -> In (nth (S n) (a :: l) d) (a :: l).
Proof.
simpl; auto.
Qed.
Fixpoint nth_error (l:list A) (n:nat) {struct n} : option A :=
match n, l with
| O, x :: _ => Some x
| S n, _ :: l => nth_error l n
| _, _ => None
end.
Definition nth_default (default:A) (l:list A) (n:nat) : A :=
match nth_error l n with
| Some x => x
| None => default
end.
Lemma nth_default_eq :
forall n l (d:A), nth_default d l n = nth n l d.
Proof.
unfold nth_default; induction n; intros [ | ] ?; simpl; auto.
Qed.
(** Results about [nth] *)
Lemma nth_In :
forall (n:nat) (l:list A) (d:A), n < length l -> In (nth n l d) l.
Proof.
unfold lt; induction n as [| n hn]; simpl.
- destruct l; simpl; [ inversion 2 | auto ].
- destruct l as [| a l hl]; simpl.
* inversion 2.
* intros d ie; right; apply hn; auto with arith.
Qed.
Lemma In_nth l x d : In x l ->
exists n, n < length l /\ nth n l d = x.
Proof.
induction l as [|a l IH].
- easy.
- intros [H|H].
* subst; exists 0; simpl; auto with arith.
* destruct (IH H) as (n & Hn & Hn').
exists (S n); simpl; auto with arith.
Qed.
Lemma nth_overflow : forall l n d, length l <= n -> nth n l d = d.
Proof.
induction l; destruct n; simpl; intros; auto.
- inversion H.
- apply IHl; auto with arith.
Qed.
Lemma nth_indep :
forall l n d d', n < length l -> nth n l d = nth n l d'.
Proof.
induction l.
- inversion 1.
- intros [|n] d d'; simpl; auto with arith.
Qed.
Lemma app_nth1 :
forall l l' d n, n < length l -> nth n (l++l') d = nth n l d.
Proof.
induction l.
- inversion 1.
- intros l' d [|n]; simpl; auto with arith.
Qed.
Lemma app_nth2 :
forall l l' d n, n >= length l -> nth n (l++l') d = nth (n-length l) l' d.
Proof.
induction l; intros l' d [|n]; auto.
- inversion 1.
- intros; simpl; rewrite IHl; auto with arith.
Qed.
Lemma nth_split n l d : n < length l ->
exists l1, exists l2, l = l1 ++ nth n l d :: l2 /\ length l1 = n.
Proof.
revert l.
induction n as [|n IH]; intros [|a l] H; try easy.
- exists nil; exists l; now simpl.
- destruct (IH l) as (l1 & l2 & Hl & Hl1); auto with arith.
exists (a::l1); exists l2; simpl; split; now f_equal.
Qed.
(** Results about [nth_error] *)
Lemma nth_error_In l n x : nth_error l n = Some x -> In x l.
Proof.
revert n. induction l as [|a l IH]; intros [|n]; simpl; try easy.
- injection 1; auto.
- eauto.
Qed.
Lemma In_nth_error l x : In x l -> exists n, nth_error l n = Some x.
Proof.
induction l as [|a l IH].
- easy.
- intros [H|H].
* subst; exists 0; simpl; auto with arith.
* destruct (IH H) as (n,Hn).
exists (S n); simpl; auto with arith.
Qed.
Lemma nth_error_None l n : nth_error l n = None <-> length l <= n.
Proof.
revert n. induction l; destruct n; simpl.
- split; auto.
- split; auto with arith.
- split; now auto with arith.
- rewrite IHl; split; auto with arith.
Qed.
Lemma nth_error_Some l n : nth_error l n <> None <-> n < length l.
Proof.
revert n. induction l; destruct n; simpl.
- split; [now destruct 1 | inversion 1].
- split; [now destruct 1 | inversion 1].
- split; now auto with arith.
- rewrite IHl; split; auto with arith.
Qed.
Lemma nth_error_split l n a : nth_error l n = Some a ->
exists l1, exists l2, l = l1 ++ a :: l2 /\ length l1 = n.
Proof.
revert l.
induction n as [|n IH]; intros [|x l] H; simpl in *; try easy.
- exists nil; exists l. injection H; clear H; intros; now subst.
- destruct (IH _ H) as (l1 & l2 & H1 & H2).
exists (x::l1); exists l2; simpl; split; now f_equal.
Qed.
Lemma nth_error_app1 l l' n : n < length l ->
nth_error (l++l') n = nth_error l n.
Proof.
revert l.
induction n; intros [|a l] H; auto; try solve [inversion H].
simpl in *. apply IHn. auto with arith.
Qed.
Lemma nth_error_app2 l l' n : length l <= n ->
nth_error (l++l') n = nth_error l' (n-length l).
Proof.
revert l.
induction n; intros [|a l] H; auto; try solve [inversion H].
simpl in *. apply IHn. auto with arith.
Qed.
(*****************)
(** ** Remove *)
(*****************)
Hypothesis eq_dec : forall x y : A, {x = y}+{x <> y}.
Fixpoint remove (x : A) (l : list A) : list A :=
match l with
| [] => []
| y::tl => if (eq_dec x y) then remove x tl else y::(remove x tl)
end.
Theorem remove_In : forall (l : list A) (x : A), ~ In x (remove x l).
Proof.
induction l as [|x l]; auto.
intro y; simpl; destruct (eq_dec y x) as [yeqx | yneqx].
apply IHl.
unfold not; intro HF; simpl in HF; destruct HF; auto.
apply (IHl y); assumption.
Qed.
(******************************)
(** ** Last element of a list *)
(******************************)
(** [last l d] returns the last element of the list [l],
or the default value [d] if [l] is empty. *)
Fixpoint last (l:list A) (d:A) : A :=
match l with
| [] => d
| [a] => a
| a :: l => last l d
end.
(** [removelast l] remove the last element of [l] *)
Fixpoint removelast (l:list A) : list A :=
match l with
| [] => []
| [a] => []
| a :: l => a :: removelast l
end.
Lemma app_removelast_last :
forall l d, l <> [] -> l = removelast l ++ [last l d].
Proof.
induction l.
destruct 1; auto.
intros d _.
destruct l; auto.
pattern (a0::l) at 1; rewrite IHl with d; auto; discriminate.
Qed.
Lemma exists_last :
forall l, l <> [] -> { l' : (list A) & { a : A | l = l' ++ [a]}}.
Proof.
induction l.
destruct 1; auto.
intros _.
destruct l.
exists [], a; auto.
destruct IHl as [l' (a',H)]; try discriminate.
rewrite H.
exists (a::l'), a'; auto.
Qed.
Lemma removelast_app :
forall l l', l' <> [] -> removelast (l++l') = l ++ removelast l'.
Proof.
induction l.
simpl; auto.
simpl; intros.
assert (l++l' <> []).
destruct l.
simpl; auto.
simpl; discriminate.
specialize (IHl l' H).
destruct (l++l'); [elim H0; auto|f_equal; auto].
Qed.
(****************************************)
(** ** Counting occurences of a element *)
(****************************************)
Fixpoint count_occ (l : list A) (x : A) : nat :=
match l with
| [] => 0
| y :: tl =>
let n := count_occ tl x in
if eq_dec y x then S n else n
end.
(** Compatibility of count_occ with operations on list *)
Theorem count_occ_In l x : In x l <-> count_occ l x > 0.
Proof.
induction l as [|y l]; simpl.
- split; [destruct 1 | apply gt_irrefl].
- destruct eq_dec as [->|Hneq]; rewrite IHl; intuition.
Qed.
Theorem count_occ_not_In l x : ~ In x l <-> count_occ l x = 0.
Proof.
rewrite count_occ_In. unfold gt. now rewrite Nat.nlt_ge, Nat.le_0_r.
Qed.
Lemma count_occ_nil x : count_occ [] x = 0.
Proof.
reflexivity.
Qed.
Theorem count_occ_inv_nil l :
(forall x:A, count_occ l x = 0) <-> l = [].
Proof.
split.
- induction l as [|x l]; trivial.
intros H. specialize (H x). simpl in H.
destruct eq_dec as [_|NEQ]; [discriminate|now elim NEQ].
- now intros ->.
Qed.
Lemma count_occ_cons_eq l x y :
x = y -> count_occ (x::l) y = S (count_occ l y).
Proof.
intros H. simpl. now destruct (eq_dec x y).
Qed.
Lemma count_occ_cons_neq l x y :
x <> y -> count_occ (x::l) y = count_occ l y.
Proof.
intros H. simpl. now destruct (eq_dec x y).
Qed.
End Elts.
(*******************************)
(** * Manipulating whole lists *)
(*******************************)
Section ListOps.
Variable A : Type.
(*************************)
(** ** Reverse *)
(*************************)
Fixpoint rev (l:list A) : list A :=
match l with
| [] => []
| x :: l' => rev l' ++ [x]
end.
Lemma rev_app_distr : forall x y:list A, rev (x ++ y) = rev y ++ rev x.
Proof.
induction x as [| a l IHl].
destruct y as [| a l].
simpl.
auto.
simpl.
rewrite app_nil_r; auto.
intro y.
simpl.
rewrite (IHl y).
rewrite app_assoc; trivial.
Qed.
Remark rev_unit : forall (l:list A) (a:A), rev (l ++ [a]) = a :: rev l.
Proof.
intros.
apply (rev_app_distr l [a]); simpl; auto.
Qed.
Lemma rev_involutive : forall l:list A, rev (rev l) = l.
Proof.
induction l as [| a l IHl].
simpl; auto.
simpl.
rewrite (rev_unit (rev l) a).
rewrite IHl; auto.
Qed.
(** Compatibility with other operations *)
Lemma in_rev : forall l x, In x l <-> In x (rev l).
Proof.
induction l.
simpl; intuition.
intros.
simpl.
intuition.
subst.
apply in_or_app; right; simpl; auto.
apply in_or_app; left; firstorder.
destruct (in_app_or _ _ _ H); firstorder.
Qed.
Lemma rev_length : forall l, length (rev l) = length l.
Proof.
induction l;simpl; auto.
rewrite app_length.
rewrite IHl.
simpl.
elim (length l); simpl; auto.
Qed.
Lemma rev_nth : forall l d n, n < length l ->
nth n (rev l) d = nth (length l - S n) l d.
Proof.
induction l.
intros; inversion H.
intros.
simpl in H.
simpl (rev (a :: l)).
simpl (length (a :: l) - S n).
inversion H.
rewrite <- minus_n_n; simpl.
rewrite <- rev_length.
rewrite app_nth2; auto.
rewrite <- minus_n_n; auto.
rewrite app_nth1; auto.
rewrite (minus_plus_simpl_l_reverse (length l) n 1).
replace (1 + length l) with (S (length l)); auto with arith.
rewrite <- minus_Sn_m; auto with arith.
apply IHl ; auto with arith.
rewrite rev_length; auto.
Qed.
(** An alternative tail-recursive definition for reverse *)
Fixpoint rev_append (l l': list A) : list A :=
match l with
| [] => l'
| a::l => rev_append l (a::l')
end.
Definition rev' l : list A := rev_append l [].
Lemma rev_append_rev : forall l l', rev_append l l' = rev l ++ l'.
Proof.
induction l; simpl; auto; intros.
rewrite <- app_assoc; firstorder.
Qed.
Lemma rev_alt : forall l, rev l = rev_append l [].
Proof.
intros; rewrite rev_append_rev.
rewrite app_nil_r; trivial.
Qed.
(*********************************************)
(** Reverse Induction Principle on Lists *)
(*********************************************)
Section Reverse_Induction.
Lemma rev_list_ind :
forall P:list A-> Prop,
P [] ->
(forall (a:A) (l:list A), P (rev l) -> P (rev (a :: l))) ->
forall l:list A, P (rev l).
Proof.
induction l; auto.
Qed.
Theorem rev_ind :
forall P:list A -> Prop,
P [] ->
(forall (x:A) (l:list A), P l -> P (l ++ [x])) -> forall l:list A, P l.
Proof.
intros.
generalize (rev_involutive l).
intros E; rewrite <- E.
apply (rev_list_ind P).
auto.
simpl.
intros.
apply (H0 a (rev l0)).
auto.
Qed.
End Reverse_Induction.
(*************************)
(** ** Concatenation *)
(*************************)
Fixpoint concat (l : list (list A)) : list A :=
match l with
| nil => nil
| cons x l => x ++ concat l
end.
Lemma concat_nil : concat nil = nil.
Proof.
reflexivity.
Qed.
Lemma concat_cons : forall x l, concat (cons x l) = x ++ concat l.
Proof.
reflexivity.
Qed.
Lemma concat_app : forall l1 l2, concat (l1 ++ l2) = concat l1 ++ concat l2.
Proof.
intros l1; induction l1 as [|x l1 IH]; intros l2; simpl.
+ reflexivity.
+ rewrite IH; apply app_assoc.
Qed.
(***********************************)
(** ** Decidable equality on lists *)
(***********************************)
Hypothesis eq_dec : forall (x y : A), {x = y}+{x <> y}.
Lemma list_eq_dec : forall l l':list A, {l = l'} + {l <> l'}.
Proof. decide equality. Defined.
End ListOps.
(***************************************************)
(** * Applying functions to the elements of a list *)
(***************************************************)
(************)
(** ** Map *)
(************)
Section Map.
Variables (A : Type) (B : Type).
Variable f : A -> B.
Fixpoint map (l:list A) : list B :=
match l with
| [] => []
| a :: t => (f a) :: (map t)
end.
Lemma map_cons (x:A)(l:list A) : map (x::l) = (f x) :: (map l).
Proof.
reflexivity.
Qed.
Lemma in_map :
forall (l:list A) (x:A), In x l -> In (f x) (map l).
Proof.
induction l; firstorder (subst; auto).
Qed.
Lemma in_map_iff : forall l y, In y (map l) <-> exists x, f x = y /\ In x l.
Proof.
induction l; firstorder (subst; auto).
Qed.
Lemma map_length : forall l, length (map l) = length l.
Proof.
induction l; simpl; auto.
Qed.
Lemma map_nth : forall l d n,
nth n (map l) (f d) = f (nth n l d).
Proof.
induction l; simpl map; destruct n; firstorder.
Qed.
Lemma map_nth_error : forall n l d,
nth_error l n = Some d -> nth_error (map l) n = Some (f d).
Proof.
induction n; intros [ | ] ? Heq; simpl in *; inversion Heq; auto.
Qed.
Lemma map_app : forall l l',
map (l++l') = (map l)++(map l').
Proof.
induction l; simpl; auto.
intros; rewrite IHl; auto.
Qed.
Lemma map_rev : forall l, map (rev l) = rev (map l).
Proof.
induction l; simpl; auto.
rewrite map_app.
rewrite IHl; auto.
Qed.
Lemma map_eq_nil : forall l, map l = [] -> l = [].
Proof.
destruct l; simpl; reflexivity || discriminate.
Qed.
(** [map] and count of occurrences *)
Hypothesis decA: forall x1 x2 : A, {x1 = x2} + {x1 <> x2}.
Hypothesis decB: forall y1 y2 : B, {y1 = y2} + {y1 <> y2}.
Hypothesis Hfinjective: forall x1 x2: A, (f x1) = (f x2) -> x1 = x2.
Theorem count_occ_map x l:
count_occ decA l x = count_occ decB (map l) (f x).
Proof.
revert x. induction l as [| a l' Hrec]; intro x; simpl.
- reflexivity.
- specialize (Hrec x).
destruct (decA a x) as [H1|H1], (decB (f a) (f x)) as [H2|H2].
* rewrite Hrec. reflexivity.
* contradiction H2. rewrite H1. reflexivity.
* specialize (Hfinjective H2). contradiction H1.
* assumption.
Qed.
(** [flat_map] *)
Definition flat_map (f:A -> list B) :=
fix flat_map (l:list A) : list B :=
match l with
| nil => nil
| cons x t => (f x)++(flat_map t)
end.
Lemma in_flat_map : forall (f:A->list B)(l:list A)(y:B),
In y (flat_map f l) <-> exists x, In x l /\ In y (f x).
Proof using A B.
induction l; simpl; split; intros.
contradiction.
destruct H as (x,(H,_)); contradiction.
destruct (in_app_or _ _ _ H).
exists a; auto.
destruct (IHl y) as (H1,_); destruct (H1 H0) as (x,(H2,H3)).
exists x; auto.
apply in_or_app.
destruct H as (x,(H0,H1)); destruct H0.
subst; auto.
right; destruct (IHl y) as (_,H2); apply H2.
exists x; auto.
Qed.
End Map.
Lemma flat_map_concat_map : forall A B (f : A -> list B) l,
flat_map f l = concat (map f l).
Proof.
intros A B f l; induction l as [|x l IH]; simpl.
+ reflexivity.
+ rewrite IH; reflexivity.
Qed.
Lemma concat_map : forall A B (f : A -> B) l, map f (concat l) = concat (map (map f) l).
Proof.
intros A B f l; induction l as [|x l IH]; simpl.
+ reflexivity.
+ rewrite map_app, IH; reflexivity.
Qed.
Lemma map_id : forall (A :Type) (l : list A),
map (fun x => x) l = l.
Proof.
induction l; simpl; auto; rewrite IHl; auto.
Qed.
Lemma map_map : forall (A B C:Type)(f:A->B)(g:B->C) l,
map g (map f l) = map (fun x => g (f x)) l.
Proof.
induction l; simpl; auto.
rewrite IHl; auto.
Qed.
Lemma map_ext_in :
forall (A B : Type)(f g:A->B) l, (forall a, In a l -> f a = g a) -> map f l = map g l.
Proof.
induction l; simpl; auto.
intros; rewrite H by intuition; rewrite IHl; auto.
Qed.
Lemma map_ext :
forall (A B : Type)(f g:A->B), (forall a, f a = g a) -> forall l, map f l = map g l.
Proof.
intros; apply map_ext_in; auto.
Qed.
(************************************)
(** Left-to-right iterator on lists *)
(************************************)
Section Fold_Left_Recursor.
Variables (A : Type) (B : Type).
Variable f : A -> B -> A.
Fixpoint fold_left (l:list B) (a0:A) : A :=
match l with
| nil => a0
| cons b t => fold_left t (f a0 b)
end.
Lemma fold_left_app : forall (l l':list B)(i:A),
fold_left (l++l') i = fold_left l' (fold_left l i).
Proof.
induction l.
simpl; auto.
intros.
simpl.
auto.
Qed.
End Fold_Left_Recursor.
Lemma fold_left_length :
forall (A:Type)(l:list A), fold_left (fun x _ => S x) l 0 = length l.
Proof.
intros A l.
enough (H : forall n, fold_left (fun x _ => S x) l n = n + length l) by exact (H 0).
induction l; simpl; auto.
intros; rewrite IHl.
simpl; auto with arith.
Qed.
(************************************)
(** Right-to-left iterator on lists *)
(************************************)
Section Fold_Right_Recursor.
Variables (A : Type) (B : Type).
Variable f : B -> A -> A.
Variable a0 : A.
Fixpoint fold_right (l:list B) : A :=
match l with
| nil => a0
| cons b t => f b (fold_right t)
end.
End Fold_Right_Recursor.
Lemma fold_right_app : forall (A B:Type)(f:A->B->B) l l' i,
fold_right f i (l++l') = fold_right f (fold_right f i l') l.
Proof.
induction l.
simpl; auto.
simpl; intros.
f_equal; auto.
Qed.
Lemma fold_left_rev_right : forall (A B:Type)(f:A->B->B) l i,
fold_right f i (rev l) = fold_left (fun x y => f y x) l i.
Proof.
induction l.
simpl; auto.
intros.
simpl.
rewrite fold_right_app; simpl; auto.
Qed.
Theorem fold_symmetric :
forall (A : Type) (f : A -> A -> A),
(forall x y z : A, f x (f y z) = f (f x y) z) ->
forall (a0 : A), (forall y : A, f a0 y = f y a0) ->
forall (l : list A), fold_left f l a0 = fold_right f a0 l.
Proof.
intros A f assoc a0 comma0 l.
induction l as [ | a1 l ]; [ simpl; reflexivity | ].
simpl. rewrite <- IHl. clear IHl. revert a1. induction l; [ auto | ].
simpl. intro. rewrite <- assoc. rewrite IHl. rewrite IHl. auto.
Qed.
(** [(list_power x y)] is [y^x], or the set of sequences of elts of [y]
indexed by elts of [x], sorted in lexicographic order. *)
Fixpoint list_power (A B:Type)(l:list A) (l':list B) :
list (list (A * B)) :=
match l with
| nil => cons nil nil
| cons x t =>
flat_map (fun f:list (A * B) => map (fun y:B => cons (x, y) f) l')
(list_power t l')
end.
(*************************************)
(** ** Boolean operations over lists *)
(*************************************)
Section Bool.
Variable A : Type.
Variable f : A -> bool.
(** find whether a boolean function can be satisfied by an
elements of the list. *)
Fixpoint existsb (l:list A) : bool :=
match l with
| nil => false
| a::l => f a || existsb l
end.
Lemma existsb_exists :
forall l, existsb l = true <-> exists x, In x l /\ f x = true.
Proof.
induction l; simpl; intuition.
inversion H.
firstorder.
destruct (orb_prop _ _ H1); firstorder.
firstorder.
subst.
rewrite H2; auto.
Qed.
Lemma existsb_nth : forall l n d, n < length l ->
existsb l = false -> f (nth n l d) = false.
Proof.
induction l.
inversion 1.
simpl; intros.
destruct (orb_false_elim _ _ H0); clear H0; auto.
destruct n ; auto.
rewrite IHl; auto with arith.
Qed.
Lemma existsb_app : forall l1 l2,
existsb (l1++l2) = existsb l1 || existsb l2.
Proof.
induction l1; intros l2; simpl.
solve[auto].
case (f a); simpl; solve[auto].
Qed.
(** find whether a boolean function is satisfied by
all the elements of a list. *)
Fixpoint forallb (l:list A) : bool :=
match l with
| nil => true
| a::l => f a && forallb l
end.
Lemma forallb_forall :
forall l, forallb l = true <-> (forall x, In x l -> f x = true).
Proof.
induction l; simpl; intuition.
destruct (andb_prop _ _ H1).
congruence.
destruct (andb_prop _ _ H1); auto.
assert (forallb l = true).
apply H0; intuition.
rewrite H1; auto.
Qed.
Lemma forallb_app :
forall l1 l2, forallb (l1++l2) = forallb l1 && forallb l2.
Proof.
induction l1; simpl.
solve[auto].
case (f a); simpl; solve[auto].
Qed.
(** [filter] *)
Fixpoint filter (l:list A) : list A :=
match l with
| nil => nil
| x :: l => if f x then x::(filter l) else filter l
end.
Lemma filter_In : forall x l, In x (filter l) <-> In x l /\ f x = true.
Proof.
induction l; simpl.
intuition.
intros.
case_eq (f a); intros; simpl; intuition congruence.
Qed.
(** [find] *)
Fixpoint find (l:list A) : option A :=
match l with
| nil => None
| x :: tl => if f x then Some x else find tl
end.
Lemma find_some l x : find l = Some x -> In x l /\ f x = true.
Proof.
induction l as [|a l IH]; simpl; [easy| ].
case_eq (f a); intros Ha Eq.
* injection Eq as ->; auto.
* destruct (IH Eq); auto.
Qed.
Lemma find_none l : find l = None -> forall x, In x l -> f x = false.
Proof.
induction l as [|a l IH]; simpl; [easy|].
case_eq (f a); intros Ha Eq x IN; [easy|].
destruct IN as [<-|IN]; auto.
Qed.
(** [partition] *)
Fixpoint partition (l:list A) : list A * list A :=
match l with
| nil => (nil, nil)
| x :: tl => let (g,d) := partition tl in
if f x then (x::g,d) else (g,x::d)
end.
Theorem partition_cons1 a l l1 l2:
partition l = (l1, l2) ->
f a = true ->
partition (a::l) = (a::l1, l2).
Proof.
simpl. now intros -> ->.
Qed.
Theorem partition_cons2 a l l1 l2:
partition l = (l1, l2) ->
f a=false ->
partition (a::l) = (l1, a::l2).
Proof.
simpl. now intros -> ->.
Qed.
Theorem partition_length l l1 l2:
partition l = (l1, l2) ->
length l = length l1 + length l2.
Proof.
revert l1 l2. induction l as [ | a l' Hrec]; intros l1 l2.
- now intros [= <- <- ].
- simpl. destruct (f a), (partition l') as (left, right);
intros [= <- <- ]; simpl; rewrite (Hrec left right); auto.
Qed.
Theorem partition_inv_nil (l : list A):
partition l = ([], []) <-> l = [].
Proof.
split.
- destruct l as [|a l' _].
* intuition.
* simpl. destruct (f a), (partition l'); now intros [= -> ->].
- now intros ->.
Qed.
Theorem elements_in_partition l l1 l2:
partition l = (l1, l2) ->
forall x:A, In x l <-> In x l1 \/ In x l2.
Proof.
revert l1 l2. induction l as [| a l' Hrec]; simpl; intros l1 l2 Eq x.
- injection Eq as <- <-. tauto.
- destruct (partition l') as (left, right).
specialize (Hrec left right eq_refl x).
destruct (f a); injection Eq as <- <-; simpl; tauto.
Qed.
End Bool.
(******************************************************)
(** ** Operations on lists of pairs or lists of lists *)
(******************************************************)
Section ListPairs.
Variables (A : Type) (B : Type).
(** [split] derives two lists from a list of pairs *)
Fixpoint split (l:list (A*B)) : list A * list B :=
match l with
| [] => ([], [])
| (x,y) :: tl => let (left,right) := split tl in (x::left, y::right)
end.
Lemma in_split_l : forall (l:list (A*B))(p:A*B),
In p l -> In (fst p) (fst (split l)).
Proof.
induction l; simpl; intros; auto.
destruct p; destruct a; destruct (split l); simpl in *.
destruct H.
injection H; auto.
right; apply (IHl (a0,b) H).
Qed.
Lemma in_split_r : forall (l:list (A*B))(p:A*B),
In p l -> In (snd p) (snd (split l)).
Proof.
induction l; simpl; intros; auto.
destruct p; destruct a; destruct (split l); simpl in *.
destruct H.
injection H; auto.
right; apply (IHl (a0,b) H).
Qed.
Lemma split_nth : forall (l:list (A*B))(n:nat)(d:A*B),
nth n l d = (nth n (fst (split l)) (fst d), nth n (snd (split l)) (snd d)).
Proof.
induction l.
destruct n; destruct d; simpl; auto.
destruct n; destruct d; simpl; auto.
destruct a; destruct (split l); simpl; auto.
destruct a; destruct (split l); simpl in *; auto.
apply IHl.
Qed.
Lemma split_length_l : forall (l:list (A*B)),
length (fst (split l)) = length l.
Proof.
induction l; simpl; auto.
destruct a; destruct (split l); simpl; auto.
Qed.
Lemma split_length_r : forall (l:list (A*B)),
length (snd (split l)) = length l.
Proof.
induction l; simpl; auto.
destruct a; destruct (split l); simpl; auto.
Qed.
(** [combine] is the opposite of [split].
Lists given to [combine] are meant to be of same length.
If not, [combine] stops on the shorter list *)
Fixpoint combine (l : list A) (l' : list B) : list (A*B) :=
match l,l' with
| x::tl, y::tl' => (x,y)::(combine tl tl')
| _, _ => nil
end.
Lemma split_combine : forall (l: list (A*B)),
let (l1,l2) := split l in combine l1 l2 = l.
Proof.
induction l.
simpl; auto.
destruct a; simpl.
destruct (split l); simpl in *.
f_equal; auto.
Qed.
Lemma combine_split : forall (l:list A)(l':list B), length l = length l' ->
split (combine l l') = (l,l').
Proof.
induction l; destruct l'; simpl; intros; auto; try discriminate.
injection H; clear H; intros.
rewrite IHl; auto.
Qed.
Lemma in_combine_l : forall (l:list A)(l':list B)(x:A)(y:B),
In (x,y) (combine l l') -> In x l.
Proof.
induction l.
simpl; auto.
destruct l'; simpl; auto; intros.
contradiction.
destruct H.
injection H; auto.
right; apply IHl with l' y; auto.
Qed.
Lemma in_combine_r : forall (l:list A)(l':list B)(x:A)(y:B),
In (x,y) (combine l l') -> In y l'.
Proof.
induction l.
simpl; intros; contradiction.
destruct l'; simpl; auto; intros.
destruct H.
injection H; auto.
right; apply IHl with x; auto.
Qed.
Lemma combine_length : forall (l:list A)(l':list B),
length (combine l l') = min (length l) (length l').
Proof.
induction l.
simpl; auto.
destruct l'; simpl; auto.
Qed.
Lemma combine_nth : forall (l:list A)(l':list B)(n:nat)(x:A)(y:B),
length l = length l' ->
nth n (combine l l') (x,y) = (nth n l x, nth n l' y).
Proof.
induction l; destruct l'; intros; try discriminate.
destruct n; simpl; auto.
destruct n; simpl in *; auto.
Qed.
(** [list_prod] has the same signature as [combine], but unlike
[combine], it adds every possible pairs, not only those at the
same position. *)
Fixpoint list_prod (l:list A) (l':list B) :
list (A * B) :=
match l with
| nil => nil
| cons x t => (map (fun y:B => (x, y)) l')++(list_prod t l')
end.
Lemma in_prod_aux :
forall (x:A) (y:B) (l:list B),
In y l -> In (x, y) (map (fun y0:B => (x, y0)) l).
Proof.
induction l;
[ simpl; auto
| simpl; destruct 1 as [H1| ];
[ left; rewrite H1; trivial | right; auto ] ].
Qed.
Lemma in_prod :
forall (l:list A) (l':list B) (x:A) (y:B),
In x l -> In y l' -> In (x, y) (list_prod l l').
Proof.
induction l;
[ simpl; tauto
| simpl; intros; apply in_or_app; destruct H;
[ left; rewrite H; apply in_prod_aux; assumption | right; auto ] ].
Qed.
Lemma in_prod_iff :
forall (l:list A)(l':list B)(x:A)(y:B),
In (x,y) (list_prod l l') <-> In x l /\ In y l'.
Proof.
split; [ | intros; apply in_prod; intuition ].
induction l; simpl; intros.
intuition.
destruct (in_app_or _ _ _ H); clear H.
destruct (in_map_iff (fun y : B => (a, y)) l' (x,y)) as (H1,_).
destruct (H1 H0) as (z,(H2,H3)); clear H0 H1.
injection H2; clear H2; intros; subst; intuition.
intuition.
Qed.
Lemma prod_length : forall (l:list A)(l':list B),
length (list_prod l l') = (length l) * (length l').
Proof.
induction l; simpl; auto.
intros.
rewrite app_length.
rewrite map_length.
auto.
Qed.
End ListPairs.
(*****************************************)
(** * Miscellaneous operations on lists *)
(*****************************************)
(******************************)
(** ** Length order of lists *)
(******************************)
Section length_order.
Variable A : Type.
Definition lel (l m:list A) := length l <= length m.
Variables a b : A.
Variables l m n : list A.
Lemma lel_refl : lel l l.
Proof.
unfold lel; auto with arith.
Qed.
Lemma lel_trans : lel l m -> lel m n -> lel l n.
Proof.
unfold lel; intros.
now_show (length l <= length n).
apply le_trans with (length m); auto with arith.
Qed.
Lemma lel_cons_cons : lel l m -> lel (a :: l) (b :: m).
Proof.
unfold lel; simpl; auto with arith.
Qed.
Lemma lel_cons : lel l m -> lel l (b :: m).
Proof.
unfold lel; simpl; auto with arith.
Qed.
Lemma lel_tail : lel (a :: l) (b :: m) -> lel l m.
Proof.
unfold lel; simpl; auto with arith.
Qed.
Lemma lel_nil : forall l':list A, lel l' nil -> nil = l'.
Proof.
intro l'; elim l'; auto with arith.
intros a' y H H0.
now_show (nil = a' :: y).
absurd (S (length y) <= 0); auto with arith.
Qed.
End length_order.
Hint Resolve lel_refl lel_cons_cons lel_cons lel_nil lel_nil nil_cons:
datatypes v62.
(******************************)
(** ** Set inclusion on list *)
(******************************)
Section SetIncl.
Variable A : Type.
Definition incl (l m:list A) := forall a:A, In a l -> In a m.
Hint Unfold incl.
Lemma incl_refl : forall l:list A, incl l l.
Proof.
auto.
Qed.
Hint Resolve incl_refl.
Lemma incl_tl : forall (a:A) (l m:list A), incl l m -> incl l (a :: m).
Proof.
auto with datatypes.
Qed.
Hint Immediate incl_tl.
Lemma incl_tran : forall l m n:list A, incl l m -> incl m n -> incl l n.
Proof.
auto.
Qed.
Lemma incl_appl : forall l m n:list A, incl l n -> incl l (n ++ m).
Proof.
auto with datatypes.
Qed.
Hint Immediate incl_appl.
Lemma incl_appr : forall l m n:list A, incl l n -> incl l (m ++ n).
Proof.
auto with datatypes.
Qed.
Hint Immediate incl_appr.
Lemma incl_cons :
forall (a:A) (l m:list A), In a m -> incl l m -> incl (a :: l) m.
Proof.
unfold incl; simpl; intros a l m H H0 a0 H1.
now_show (In a0 m).
elim H1.
now_show (a = a0 -> In a0 m).
elim H1; auto; intro H2.
now_show (a = a0 -> In a0 m).
elim H2; auto. (* solves subgoal *)
now_show (In a0 l -> In a0 m).
auto.
Qed.
Hint Resolve incl_cons.
Lemma incl_app : forall l m n:list A, incl l n -> incl m n -> incl (l ++ m) n.
Proof.
unfold incl; simpl; intros l m n H H0 a H1.
now_show (In a n).
elim (in_app_or _ _ _ H1); auto.
Qed.
Hint Resolve incl_app.
End SetIncl.
Hint Resolve incl_refl incl_tl incl_tran incl_appl incl_appr incl_cons
incl_app: datatypes v62.
(**************************************)
(** * Cutting a list at some position *)
(**************************************)
Section Cutting.
Variable A : Type.
Fixpoint firstn (n:nat)(l:list A) : list A :=
match n with
| 0 => nil
| S n => match l with
| nil => nil
| a::l => a::(firstn n l)
end
end.
Lemma firstn_nil n: firstn n [] = [].
Proof. induction n; now simpl. Qed.
Lemma firstn_cons n a l: firstn (S n) (a::l) = a :: (firstn n l).
Proof. now simpl. Qed.
Lemma firstn_all l: firstn (length l) l = l.
Proof. induction l as [| ? ? H]; simpl; [reflexivity | now rewrite H]. Qed.
Lemma firstn_all2 n: forall (l:list A), (length l) <= n -> firstn n l = l.
Proof. induction n as [|k iHk].
- intro. inversion 1 as [H1|?].
rewrite (length_zero_iff_nil l) in H1. subst. now simpl.
- destruct l as [|x xs]; simpl.
* now reflexivity.
* simpl. intro H. apply Peano.le_S_n in H. f_equal. apply iHk, H.
Qed.
Lemma firstn_O l: firstn 0 l = [].
Proof. now simpl. Qed.
Lemma firstn_le_length n: forall l:list A, length (firstn n l) <= n.
Proof.
induction n as [|k iHk]; simpl; [auto | destruct l as [|x xs]; simpl].
- auto with arith.
- apply Peano.le_n_S, iHk.
Qed.
Lemma firstn_length_le: forall l:list A, forall n:nat,
n <= length l -> length (firstn n l) = n.
Proof. induction l as [|x xs Hrec].
- simpl. intros n H. apply le_n_0_eq in H. rewrite <- H. now simpl.
- destruct n.
* now simpl.
* simpl. intro H. apply le_S_n in H. now rewrite (Hrec n H).
Qed.
Lemma firstn_app n:
forall l1 l2,
firstn n (l1 ++ l2) = (firstn n l1) ++ (firstn (n - length l1) l2).
Proof. induction n as [|k iHk]; intros l1 l2.
- now simpl.
- destruct l1 as [|x xs].
* unfold firstn at 2, length. now rewrite 2!app_nil_l, <- minus_n_O.
* rewrite <- app_comm_cons. simpl. f_equal. apply iHk.
Qed.
Lemma firstn_app_2 n:
forall l1 l2,
firstn ((length l1) + n) (l1 ++ l2) = l1 ++ firstn n l2.
Proof. induction n as [| k iHk];intros l1 l2.
- unfold firstn at 2. rewrite <- plus_n_O, app_nil_r.
rewrite firstn_app. rewrite <- minus_diag_reverse.
unfold firstn at 2. rewrite app_nil_r. apply firstn_all.
- destruct l2 as [|x xs].
* simpl. rewrite app_nil_r. apply firstn_all2. auto with arith.
* rewrite firstn_app. assert (H0 : (length l1 + S k - length l1) = S k).
auto with arith.
rewrite H0, firstn_all2; [reflexivity | auto with arith].
Qed.
Lemma firstn_firstn:
forall l:list A,
forall i j : nat,
firstn i (firstn j l) = firstn (min i j) l.
Proof. induction l as [|x xs Hl].
- intros. simpl. now rewrite ?firstn_nil.
- destruct i.
* intro. now simpl.
* destruct j.
+ now simpl.
+ simpl. f_equal. apply Hl.
Qed.
Fixpoint skipn (n:nat)(l:list A) : list A :=
match n with
| 0 => l
| S n => match l with
| nil => nil
| a::l => skipn n l
end
end.
Lemma firstn_skipn : forall n l, firstn n l ++ skipn n l = l.
Proof.
induction n.
simpl; auto.
destruct l; simpl; auto.
f_equal; auto.
Qed.
Lemma firstn_length : forall n l, length (firstn n l) = min n (length l).
Proof.
induction n; destruct l; simpl; auto.
Qed.
Lemma removelast_firstn : forall n l, n < length l ->
removelast (firstn (S n) l) = firstn n l.
Proof.
induction n; destruct l.
simpl; auto.
simpl; auto.
simpl; auto.
intros.
simpl in H.
change (firstn (S (S n)) (a::l)) with ((a::nil)++firstn (S n) l).
change (firstn (S n) (a::l)) with (a::firstn n l).
rewrite removelast_app.
rewrite IHn; auto with arith.
clear IHn; destruct l; simpl in *; try discriminate.
inversion_clear H.
inversion_clear H0.
Qed.
Lemma firstn_removelast : forall n l, n < length l ->
firstn n (removelast l) = firstn n l.
Proof.
induction n; destruct l.
simpl; auto.
simpl; auto.
simpl; auto.
intros.
simpl in H.
change (removelast (a :: l)) with (removelast ((a::nil)++l)).
rewrite removelast_app.
simpl; f_equal; auto with arith.
intro H0; rewrite H0 in H; inversion_clear H; inversion_clear H1.
Qed.
End Cutting.
(**********************************************************************)
(** ** Predicate for List addition/removal (no need for decidability) *)
(**********************************************************************)
Section Add.
Variable A : Type.
(* [Add a l l'] means that [l'] is exactly [l], with [a] added
once somewhere *)
Inductive Add (a:A) : list A -> list A -> Prop :=
| Add_head l : Add a l (a::l)
| Add_cons x l l' : Add a l l' -> Add a (x::l) (x::l').
Lemma Add_app a l1 l2 : Add a (l1++l2) (l1++a::l2).
Proof.
induction l1; simpl; now constructor.
Qed.
Lemma Add_split a l l' :
Add a l l' -> exists l1 l2, l = l1++l2 /\ l' = l1++a::l2.
Proof.
induction 1.
- exists nil; exists l; split; trivial.
- destruct IHAdd as (l1 & l2 & Hl & Hl').
exists (x::l1); exists l2; split; simpl; f_equal; trivial.
Qed.
Lemma Add_in a l l' : Add a l l' ->
forall x, In x l' <-> In x (a::l).
Proof.
induction 1; intros; simpl in *; rewrite ?IHAdd; tauto.
Qed.
Lemma Add_length a l l' : Add a l l' -> length l' = S (length l).
Proof.
induction 1; simpl; auto with arith.
Qed.
Lemma Add_inv a l : In a l -> exists l', Add a l' l.
Proof.
intro Ha. destruct (in_split _ _ Ha) as (l1 & l2 & ->).
exists (l1 ++ l2). apply Add_app.
Qed.
Lemma incl_Add_inv a l u v :
~In a l -> incl (a::l) v -> Add a u v -> incl l u.
Proof.
intros Ha H AD y Hy.
assert (Hy' : In y (a::u)).
{ rewrite <- (Add_in AD). apply H; simpl; auto. }
destruct Hy'; [ subst; now elim Ha | trivial ].
Qed.
End Add.
(********************************)
(** ** Lists without redundancy *)
(********************************)
Section ReDun.
Variable A : Type.
Inductive NoDup : list A -> Prop :=
| NoDup_nil : NoDup nil
| NoDup_cons : forall x l, ~ In x l -> NoDup l -> NoDup (x::l).
Lemma NoDup_Add a l l' : Add a l l' -> (NoDup l' <-> NoDup l /\ ~In a l).
Proof.
induction 1 as [l|x l l' AD IH].
- split; [ inversion_clear 1; now split | now constructor ].
- split.
+ inversion_clear 1. rewrite IH in *. rewrite (Add_in AD) in *.
simpl in *; split; try constructor; intuition.
+ intros (N,IN). inversion_clear N. constructor.
* rewrite (Add_in AD); simpl in *; intuition.
* apply IH. split; trivial. simpl in *; intuition.
Qed.
Lemma NoDup_remove l l' a :
NoDup (l++a::l') -> NoDup (l++l') /\ ~In a (l++l').
Proof.
apply NoDup_Add. apply Add_app.
Qed.
Lemma NoDup_remove_1 l l' a : NoDup (l++a::l') -> NoDup (l++l').
Proof.
intros. now apply NoDup_remove with a.
Qed.
Lemma NoDup_remove_2 l l' a : NoDup (l++a::l') -> ~In a (l++l').
Proof.
intros. now apply NoDup_remove.
Qed.
Theorem NoDup_cons_iff a l:
NoDup (a::l) <-> ~ In a l /\ NoDup l.
Proof.
split.
+ inversion_clear 1. now split.
+ now constructor.
Qed.
(** Effective computation of a list without duplicates *)
Hypothesis decA: forall x y : A, {x = y} + {x <> y}.
Fixpoint nodup (l : list A) : list A :=
match l with
| [] => []
| x::xs => if in_dec decA x xs then nodup xs else x::(nodup xs)
end.
Lemma nodup_In l x : In x (nodup l) <-> In x l.
Proof.
induction l as [|a l' Hrec]; simpl.
- reflexivity.
- destruct (in_dec decA a l'); simpl; rewrite Hrec.
* intuition; now subst.
* reflexivity.
Qed.
Lemma NoDup_nodup l: NoDup (nodup l).
Proof.
induction l as [|a l' Hrec]; simpl.
- constructor.
- destruct (in_dec decA a l'); simpl.
* assumption.
* constructor; [ now rewrite nodup_In | assumption].
Qed.
Lemma nodup_inv k l a : nodup k = a :: l -> ~ In a l.
Proof.
intros H.
assert (H' : NoDup (a::l)).
{ rewrite <- H. apply NoDup_nodup. }
now inversion_clear H'.
Qed.
Theorem NoDup_count_occ l:
NoDup l <-> (forall x:A, count_occ decA l x <= 1).
Proof.
induction l as [| a l' Hrec].
- simpl; split; auto. constructor.
- rewrite NoDup_cons_iff, Hrec, (count_occ_not_In decA). clear Hrec. split.
+ intros (Ha, H) x. simpl. destruct (decA a x); auto.
subst; now rewrite Ha.
+ split.
* specialize (H a). rewrite count_occ_cons_eq in H; trivial.
now inversion H.
* intros x. specialize (H x). simpl in *. destruct (decA a x); auto.
now apply Nat.lt_le_incl.
Qed.
Theorem NoDup_count_occ' l:
NoDup l <-> (forall x:A, In x l -> count_occ decA l x = 1).
Proof.
rewrite NoDup_count_occ.
setoid_rewrite (count_occ_In decA). unfold gt, lt in *.
split; intros H x; specialize (H x);
set (n := count_occ decA l x) in *; clearbody n.
(* the rest would be solved by omega if we had it here... *)
- now apply Nat.le_antisymm.
- destruct (Nat.le_gt_cases 1 n); trivial.
+ rewrite H; trivial.
+ now apply Nat.lt_le_incl.
Qed.
(** Alternative characterisations of being without duplicates,
thanks to [nth_error] and [nth] *)
Lemma NoDup_nth_error l :
NoDup l <->
(forall i j, i<length l -> nth_error l i = nth_error l j -> i = j).
Proof.
split.
{ intros H; induction H as [|a l Hal Hl IH]; intros i j Hi E.
- inversion Hi.
- destruct i, j; simpl in *; auto.
* elim Hal. eapply nth_error_In; eauto.
* elim Hal. eapply nth_error_In; eauto.
* f_equal. apply IH; auto with arith. }
{ induction l as [|a l]; intros H; constructor.
* intro Ha. apply In_nth_error in Ha. destruct Ha as (n,Hn).
assert (n < length l) by (now rewrite <- nth_error_Some, Hn).
specialize (H 0 (S n)). simpl in H. discriminate H; auto with arith.
* apply IHl.
intros i j Hi E. apply eq_add_S, H; simpl; auto with arith. }
Qed.
Lemma NoDup_nth l d :
NoDup l <->
(forall i j, i<length l -> j<length l ->
nth i l d = nth j l d -> i = j).
Proof.
split.
{ intros H; induction H as [|a l Hal Hl IH]; intros i j Hi Hj E.
- inversion Hi.
- destruct i, j; simpl in *; auto.
* elim Hal. subst a. apply nth_In; auto with arith.
* elim Hal. subst a. apply nth_In; auto with arith.
* f_equal. apply IH; auto with arith. }
{ induction l as [|a l]; intros H; constructor.
* intro Ha. eapply In_nth in Ha. destruct Ha as (n & Hn & Hn').
specialize (H 0 (S n)). simpl in H. discriminate H; eauto with arith.
* apply IHl.
intros i j Hi Hj E. apply eq_add_S, H; simpl; auto with arith. }
Qed.
(** Having [NoDup] hypotheses bring more precise facts about [incl]. *)
Lemma NoDup_incl_length l l' :
NoDup l -> incl l l' -> length l <= length l'.
Proof.
intros N. revert l'. induction N as [|a l Hal N IH]; simpl.
- auto with arith.
- intros l' H.
destruct (Add_inv a l') as (l'', AD). { apply H; simpl; auto. }
rewrite (Add_length AD). apply le_n_S. apply IH.
now apply incl_Add_inv with a l'.
Qed.
Lemma NoDup_length_incl l l' :
NoDup l -> length l' <= length l -> incl l l' -> incl l' l.
Proof.
intros N. revert l'. induction N as [|a l Hal N IH].
- destruct l'; easy.
- intros l' E H x Hx.
destruct (Add_inv a l') as (l'', AD). { apply H; simpl; auto. }
rewrite (Add_in AD) in Hx. simpl in Hx.
destruct Hx as [Hx|Hx]; [left; trivial|right].
revert x Hx. apply (IH l''); trivial.
* apply le_S_n. now rewrite <- (Add_length AD).
* now apply incl_Add_inv with a l'.
Qed.
End ReDun.
(** NoDup and map *)
(** NB: the reciprocal result holds only for injective functions,
see FinFun.v *)
Lemma NoDup_map_inv A B (f:A->B) l : NoDup (map f l) -> NoDup l.
Proof.
induction l; simpl; inversion_clear 1; subst; constructor; auto.
intro H. now apply (in_map f) in H.
Qed.
(***********************************)
(** ** Sequence of natural numbers *)
(***********************************)
Section NatSeq.
(** [seq] computes the sequence of [len] contiguous integers
that starts at [start]. For instance, [seq 2 3] is [2::3::4::nil]. *)
Fixpoint seq (start len:nat) : list nat :=
match len with
| 0 => nil
| S len => start :: seq (S start) len
end.
Lemma seq_length : forall len start, length (seq start len) = len.
Proof.
induction len; simpl; auto.
Qed.
Lemma seq_nth : forall len start n d,
n < len -> nth n (seq start len) d = start+n.
Proof.
induction len; intros.
inversion H.
simpl seq.
destruct n; simpl.
auto with arith.
rewrite IHlen;simpl; auto with arith.
Qed.
Lemma seq_shift : forall len start,
map S (seq start len) = seq (S start) len.
Proof.
induction len; simpl; auto.
intros.
rewrite IHlen.
auto with arith.
Qed.
Lemma in_seq len start n :
In n (seq start len) <-> start <= n < start+len.
Proof.
revert start. induction len; simpl; intros.
- rewrite <- plus_n_O. split;[easy|].
intros (H,H'). apply (Lt.lt_irrefl _ (Lt.le_lt_trans _ _ _ H H')).
- rewrite IHlen, <- plus_n_Sm; simpl; split.
* intros [H|H]; subst; intuition auto with arith.
* intros (H,H'). destruct (Lt.le_lt_or_eq _ _ H); intuition.
Qed.
Lemma seq_NoDup len start : NoDup (seq start len).
Proof.
revert start; induction len; simpl; constructor; trivial.
rewrite in_seq. intros (H,_). apply (Lt.lt_irrefl _ H).
Qed.
End NatSeq.
Section Exists_Forall.
(** * Existential and universal predicates over lists *)
Variable A:Type.
Section One_predicate.
Variable P:A->Prop.
Inductive Exists : list A -> Prop :=
| Exists_cons_hd : forall x l, P x -> Exists (x::l)
| Exists_cons_tl : forall x l, Exists l -> Exists (x::l).
Hint Constructors Exists.
Lemma Exists_exists (l:list A) :
Exists l <-> (exists x, In x l /\ P x).
Proof.
split.
- induction 1; firstorder.
- induction l; firstorder; subst; auto.
Qed.
Lemma Exists_nil : Exists nil <-> False.
Proof. split; inversion 1. Qed.
Lemma Exists_cons x l:
Exists (x::l) <-> P x \/ Exists l.
Proof. split; inversion 1; auto. Qed.
Lemma Exists_dec l:
(forall x:A, {P x} + { ~ P x }) ->
{Exists l} + {~ Exists l}.
Proof.
intro Pdec. induction l as [|a l' Hrec].
- right. now rewrite Exists_nil.
- destruct Hrec as [Hl'|Hl'].
* left. now apply Exists_cons_tl.
* destruct (Pdec a) as [Ha|Ha].
+ left. now apply Exists_cons_hd.
+ right. now inversion_clear 1.
Qed.
Inductive Forall : list A -> Prop :=
| Forall_nil : Forall nil
| Forall_cons : forall x l, P x -> Forall l -> Forall (x::l).
Hint Constructors Forall.
Lemma Forall_forall (l:list A):
Forall l <-> (forall x, In x l -> P x).
Proof.
split.
- induction 1; firstorder; subst; auto.
- induction l; firstorder.
Qed.
Lemma Forall_inv : forall (a:A) l, Forall (a :: l) -> P a.
Proof.
intros; inversion H; trivial.
Qed.
Lemma Forall_rect : forall (Q : list A -> Type),
Q [] -> (forall b l, P b -> Q (b :: l)) -> forall l, Forall l -> Q l.
Proof.
intros Q H H'; induction l; intro; [|eapply H', Forall_inv]; eassumption.
Qed.
Lemma Forall_dec :
(forall x:A, {P x} + { ~ P x }) ->
forall l:list A, {Forall l} + {~ Forall l}.
Proof.
intro Pdec. induction l as [|a l' Hrec].
- left. apply Forall_nil.
- destruct Hrec as [Hl'|Hl'].
+ destruct (Pdec a) as [Ha|Ha].
* left. now apply Forall_cons.
* right. now inversion_clear 1.
+ right. now inversion_clear 1.
Qed.
End One_predicate.
Lemma Forall_Exists_neg (P:A->Prop)(l:list A) :
Forall (fun x => ~ P x) l <-> ~(Exists P l).
Proof.
rewrite Forall_forall, Exists_exists. firstorder.
Qed.
Lemma Exists_Forall_neg (P:A->Prop)(l:list A) :
(forall x, P x \/ ~P x) ->
Exists (fun x => ~ P x) l <-> ~(Forall P l).
Proof.
intro Dec.
split.
- rewrite Forall_forall, Exists_exists; firstorder.
- intros NF.
induction l as [|a l IH].
+ destruct NF. constructor.
+ destruct (Dec a) as [Ha|Ha].
* apply Exists_cons_tl, IH. contradict NF. now constructor.
* now apply Exists_cons_hd.
Qed.
Lemma Forall_Exists_dec (P:A->Prop) :
(forall x:A, {P x} + { ~ P x }) ->
forall l:list A,
{Forall P l} + {Exists (fun x => ~ P x) l}.
Proof.
intros Pdec l.
destruct (Forall_dec P Pdec l); [left|right]; trivial.
apply Exists_Forall_neg; trivial.
intro x. destruct (Pdec x); [now left|now right].
Qed.
Lemma Forall_impl : forall (P Q : A -> Prop), (forall a, P a -> Q a) ->
forall l, Forall P l -> Forall Q l.
Proof.
intros P Q H l. rewrite !Forall_forall. firstorder.
Qed.
End Exists_Forall.
Hint Constructors Exists.
Hint Constructors Forall.
Section Forall2.
(** [Forall2]: stating that elements of two lists are pairwise related. *)
Variables A B : Type.
Variable R : A -> B -> Prop.
Inductive Forall2 : list A -> list B -> Prop :=
| Forall2_nil : Forall2 [] []
| Forall2_cons : forall x y l l',
R x y -> Forall2 l l' -> Forall2 (x::l) (y::l').
Hint Constructors Forall2.
Theorem Forall2_refl : Forall2 [] [].
Proof. intros; apply Forall2_nil. Qed.
Theorem Forall2_app_inv_l : forall l1 l2 l',
Forall2 (l1 ++ l2) l' ->
exists l1' l2', Forall2 l1 l1' /\ Forall2 l2 l2' /\ l' = l1' ++ l2'.
Proof.
induction l1; intros.
exists [], l'; auto.
simpl in H; inversion H; subst; clear H.
apply IHl1 in H4 as (l1' & l2' & Hl1 & Hl2 & ->).
exists (y::l1'), l2'; simpl; auto.
Qed.
Theorem Forall2_app_inv_r : forall l1' l2' l,
Forall2 l (l1' ++ l2') ->
exists l1 l2, Forall2 l1 l1' /\ Forall2 l2 l2' /\ l = l1 ++ l2.
Proof.
induction l1'; intros.
exists [], l; auto.
simpl in H; inversion H; subst; clear H.
apply IHl1' in H4 as (l1 & l2 & Hl1 & Hl2 & ->).
exists (x::l1), l2; simpl; auto.
Qed.
Theorem Forall2_app : forall l1 l2 l1' l2',
Forall2 l1 l1' -> Forall2 l2 l2' -> Forall2 (l1 ++ l2) (l1' ++ l2').
Proof.
intros. induction l1 in l1', H, H0 |- *; inversion H; subst; simpl; auto.
Qed.
End Forall2.
Hint Constructors Forall2.
Section ForallPairs.
(** [ForallPairs] : specifies that a certain relation should
always hold when inspecting all possible pairs of elements of a list. *)
Variable A : Type.
Variable R : A -> A -> Prop.
Definition ForallPairs l :=
forall a b, In a l -> In b l -> R a b.
(** [ForallOrdPairs] : we still check a relation over all pairs
of elements of a list, but now the order of elements matters. *)
Inductive ForallOrdPairs : list A -> Prop :=
| FOP_nil : ForallOrdPairs nil
| FOP_cons : forall a l,
Forall (R a) l -> ForallOrdPairs l -> ForallOrdPairs (a::l).
Hint Constructors ForallOrdPairs.
Lemma ForallOrdPairs_In : forall l,
ForallOrdPairs l ->
forall x y, In x l -> In y l -> x=y \/ R x y \/ R y x.
Proof.
induction 1.
inversion 1.
simpl; destruct 1; destruct 1; subst; auto.
right; left. apply -> Forall_forall; eauto.
right; right. apply -> Forall_forall; eauto.
Qed.
(** [ForallPairs] implies [ForallOrdPairs]. The reverse implication is true
only when [R] is symmetric and reflexive. *)
Lemma ForallPairs_ForallOrdPairs l: ForallPairs l -> ForallOrdPairs l.
Proof.
induction l; auto. intros H.
constructor.
apply <- Forall_forall. intros; apply H; simpl; auto.
apply IHl. red; intros; apply H; simpl; auto.
Qed.
Lemma ForallOrdPairs_ForallPairs :
(forall x, R x x) ->
(forall x y, R x y -> R y x) ->
forall l, ForallOrdPairs l -> ForallPairs l.
Proof.
intros Refl Sym l Hl x y Hx Hy.
destruct (ForallOrdPairs_In Hl _ _ Hx Hy); subst; intuition.
Qed.
End ForallPairs.
(** * Inversion of predicates over lists based on head symbol *)
Ltac is_list_constr c :=
match c with
| nil => idtac
| (_::_) => idtac
| _ => fail
end.
Ltac invlist f :=
match goal with
| H:f ?l |- _ => is_list_constr l; inversion_clear H; invlist f
| H:f _ ?l |- _ => is_list_constr l; inversion_clear H; invlist f
| H:f _ _ ?l |- _ => is_list_constr l; inversion_clear H; invlist f
| H:f _ _ _ ?l |- _ => is_list_constr l; inversion_clear H; invlist f
| H:f _ _ _ _ ?l |- _ => is_list_constr l; inversion_clear H; invlist f
| _ => idtac
end.
(** * Exporting hints and tactics *)
Hint Rewrite
rev_involutive (* rev (rev l) = l *)
rev_unit (* rev (l ++ a :: nil) = a :: rev l *)
map_nth (* nth n (map f l) (f d) = f (nth n l d) *)
map_length (* length (map f l) = length l *)
seq_length (* length (seq start len) = len *)
app_length (* length (l ++ l') = length l + length l' *)
rev_length (* length (rev l) = length l *)
app_nil_r (* l ++ nil = l *)
: list.
Ltac simpl_list := autorewrite with list.
Ltac ssimpl_list := autorewrite with list using simpl.
(* begin hide *)
(* Compatibility notations after the migration of [list] to [Datatypes] *)
Notation list := list (only parsing).
Notation list_rect := list_rect (only parsing).
Notation list_rec := list_rec (only parsing).
Notation list_ind := list_ind (only parsing).
Notation nil := nil (only parsing).
Notation cons := cons (only parsing).
Notation length := length (only parsing).
Notation app := app (only parsing).
(* Compatibility Names *)
Notation tail := tl (only parsing).
Notation head := hd_error (only parsing).
Notation head_nil := hd_error_nil (only parsing).
Notation head_cons := hd_error_cons (only parsing).
Notation ass_app := app_assoc (only parsing).
Notation app_ass := app_assoc_reverse (only parsing).
Notation In_split := in_split (only parsing).
Notation In_rev := in_rev (only parsing).
Notation In_dec := in_dec (only parsing).
Notation distr_rev := rev_app_distr (only parsing).
Notation rev_acc := rev_append (only parsing).
Notation rev_acc_rev := rev_append_rev (only parsing).
Notation AllS := Forall (only parsing). (* was formerly in TheoryList *)
Hint Resolve app_nil_end : datatypes v62.
(* end hide *)
Section Repeat.
Variable A : Type.
Fixpoint repeat (x : A) (n: nat ) :=
match n with
| O => []
| S k => x::(repeat x k)
end.
Theorem repeat_length x n:
length (repeat x n) = n.
Proof.
induction n as [| k Hrec]; simpl; rewrite ?Hrec; reflexivity.
Qed.
Theorem repeat_spec n x y:
In y (repeat x n) -> y=x.
Proof.
induction n as [|k Hrec]; simpl; destruct 1; auto.
Qed.
End Repeat.
(* Unset Universe Polymorphism. *)
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [7:0] crc;
genvar g;
wire [7:0] out_p1;
wire [15:0] out_p2;
wire [7:0] out_p3;
wire [7:0] out_p4;
paramed #(.WIDTH(8), .MODE(0)) p1 (.in(crc), .out(out_p1));
paramed #(.WIDTH(16), .MODE(1)) p2 (.in({crc,crc}), .out(out_p2));
paramed #(.WIDTH(8), .MODE(2)) p3 (.in(crc), .out(out_p3));
gencase #(.MODE(3)) p4 (.in(crc), .out(out_p4));
wire [7:0] out_ef;
enflop #(.WIDTH(8)) enf (.a(crc), .q(out_ef), .oe_e1(1'b1), .clk(clk));
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d crc=%b %x %x %x %x %x\n",$time, cyc, crc, out_p1, out_p2, out_p3, out_p4, out_ef);
cyc <= cyc + 1;
crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}};
if (cyc==0) begin
// Setup
crc <= 8'hed;
end
else if (cyc==1) begin
end
else if (cyc==3) begin
if (out_p1 !== 8'h2d) $stop;
if (out_p2 !== 16'h2d2d) $stop;
if (out_p3 !== 8'h78) $stop;
if (out_p4 !== 8'h44) $stop;
if (out_ef !== 8'hda) $stop;
end
else if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module gencase (/*AUTOARG*/
// Outputs
out,
// Inputs
in
);
parameter MODE = 0;
input [7:0] in;
output [7:0] out;
generate // : genblk1
begin
case (MODE)
2: mbuf mc [7:0] (.q(out[7:0]), .a({in[5:0],in[7:6]}));
default: mbuf mc [7:0] (.q(out[7:0]), .a({in[3:0],in[3:0]}));
endcase
end
endgenerate
endmodule
module paramed (/*AUTOARG*/
// Outputs
out,
// Inputs
in
);
parameter WIDTH = 1;
parameter MODE = 0;
input [WIDTH-1:0] in;
output [WIDTH-1:0] out;
generate
if (MODE==0) initial $write("Mode=0\n");
// No else
endgenerate
`ifndef NC // for(genvar) unsupported
`ifndef ATSIM // for(genvar) unsupported
generate
// Empty loop body, local genvar
for (genvar j=0; j<3; j=j+1) begin end
// Ditto to make sure j has new scope
for (genvar j=0; j<5; j=j+1) begin end
endgenerate
`endif
`endif
generate
endgenerate
genvar i;
generate
if (MODE==0) begin
// Flip bitorder, direct assign method
for (i=0; i<WIDTH; i=i+1) begin
assign out[i] = in[WIDTH-i-1];
end
end
else if (MODE==1) begin
// Flip using instantiation
for (i=0; i<WIDTH; i=i+1) begin
integer from = WIDTH-i-1;
if (i==0) begin // Test if's within a for
mbuf m0 (.q(out[i]), .a(in[from]));
end
else begin
mbuf ma (.q(out[i]), .a(in[from]));
end
end
end
else begin
for (i=0; i<WIDTH; i=i+1) begin
mbuf ma (.q(out[i]), .a(in[i^1]));
end
end
endgenerate
endmodule
module mbuf (
input a,
output q
);
assign q = a;
endmodule
module enflop (clk, oe_e1, a,q);
parameter WIDTH=1;
input clk;
input oe_e1;
input [WIDTH-1:0] a;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] oe_r;
reg [WIDTH-1:0] q_r;
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : datapath_bits
enflop_one enflop_one
(.clk (clk),
.d (a[i]),
.q_r (q_r[i]));
always @(posedge clk) oe_r[i] <= oe_e1;
assign q[i] = oe_r[i] ? q_r[i] : 1'bx;
end
endgenerate
endmodule
module enflop_one (
input clk,
input d,
output reg q_r
);
always @(posedge clk) q_r <= d;
endmodule
|