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// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2020 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t(/*AUTOARG*/
// Inputs
clk
);
input clk;
int cyc = 0;
// Test loop
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc == 10) begin
$strobe("[%0t] cyc=%0d", $time, cyc);
$strobe("[%0t] cyc=%0d also", $time, cyc);
end
else if (cyc == 17) begin
$strobeb(cyc, "b");
end
else if (cyc == 18) begin
$strobeh(cyc, "h");
end
else if (cyc == 19) begin
$strobeo(cyc, "o");
end
else if (cyc == 22) begin
$strobe("[%0t] cyc=%0d new-strobe", $time, cyc);
end
else if (cyc == 24) begin
$monitoroff;
end
else if (cyc == 26) begin
$monitoron;
end
else if (cyc == 30) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
// d_KES_PE_ELU_MINodr.v for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Jinwoo Jeong <[email protected]>
// Ilyong Jung <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Jinwoo Jeong <[email protected]>
// Ilyong Jung <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: BCH Page Decoder
// Module Name: d_KES_PE_ELU_MINodr
// File Name: d_KES_PE_ELU_MINodr.v
//
// Version: v1.1.1-256B_T14
//
// Description:
// - Processing Element: Error Locator Update module, minimum order
// - for binary version of inversion-less Berlekamp-Massey algorithm (iBM.b)
// - for data area
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.1.1
// - minor modification for releasing
//
// * v1.1.0
// - change state machine: divide states
// - insert additional registers
// - improve frequency characteristic
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`include "d_KES_parameters.vh"
`timescale 1ns / 1ps
module d_KES_PE_ELU_MINodr // error locate update module: minimum order
(
input wire i_clk,
input wire i_RESET_KES,
input wire i_stop_dec,
input wire i_EXECUTE_PE_ELU,
input wire [`D_KES_GF_ORDER-1:0] i_delta_2im2,
output reg [`D_KES_GF_ORDER-1:0] o_v_2i_X,
output reg o_v_2i_X_deg_chk_bit,
output reg [`D_KES_GF_ORDER-1:0] o_k_2i_X
);
parameter [11:0] D_KES_VALUE_ZERO = 12'b0000_0000_0000;
parameter [11:0] D_KES_VALUE_ONE = 12'b0000_0000_0001;
// FSM parameters
parameter PE_ELU_RST = 2'b01; // reset
parameter PE_ELU_OUT = 2'b10; // output buffer update
// variable declaration
reg [1:0] r_cur_state;
reg [1:0] r_nxt_state;
wire [`D_KES_GF_ORDER-1:0] w_v_2ip2_X_term_A;
wire [`D_KES_GF_ORDER-1:0] w_v_2ip2_X;
wire [`D_KES_GF_ORDER-1:0] w_k_2ip2_X;
// update current state to next state
always @ (posedge i_clk)
begin
if ((i_RESET_KES) || (i_stop_dec)) begin
r_cur_state <= PE_ELU_RST;
end else begin
r_cur_state <= r_nxt_state;
end
end
// decide next state
always @ ( * )
begin
case (r_cur_state)
PE_ELU_RST: begin
r_nxt_state <= (i_EXECUTE_PE_ELU)? (PE_ELU_OUT):(PE_ELU_RST);
end
PE_ELU_OUT: begin
r_nxt_state <= PE_ELU_RST;
end
default: begin
r_nxt_state <= PE_ELU_RST;
end
endcase
end
// state behaviour
always @ (posedge i_clk)
begin
if ((i_RESET_KES) || (i_stop_dec)) begin // initializing
o_v_2i_X[`D_KES_GF_ORDER-1:0] <= D_KES_VALUE_ONE[`D_KES_GF_ORDER-1:0];
o_v_2i_X_deg_chk_bit <= 1;
o_k_2i_X[`D_KES_GF_ORDER-1:0] <= D_KES_VALUE_ONE[`D_KES_GF_ORDER-1:0];
end
else begin
case (r_nxt_state)
PE_ELU_RST: begin // hold original data
o_v_2i_X[`D_KES_GF_ORDER-1:0] <= o_v_2i_X[`D_KES_GF_ORDER-1:0];
o_v_2i_X_deg_chk_bit <= o_v_2i_X_deg_chk_bit;
o_k_2i_X[`D_KES_GF_ORDER-1:0] <= o_k_2i_X[`D_KES_GF_ORDER-1:0];
end
PE_ELU_OUT: begin // output update only
o_v_2i_X[`D_KES_GF_ORDER-1:0] <= w_v_2ip2_X[`D_KES_GF_ORDER-1:0];
o_v_2i_X_deg_chk_bit <= |(w_v_2ip2_X[`D_KES_GF_ORDER-1:0]);
o_k_2i_X[`D_KES_GF_ORDER-1:0] <= w_k_2ip2_X[`D_KES_GF_ORDER-1:0];
end
default: begin
o_v_2i_X[`D_KES_GF_ORDER-1:0] <= o_v_2i_X[`D_KES_GF_ORDER-1:0];
o_v_2i_X_deg_chk_bit <= o_v_2i_X_deg_chk_bit;
o_k_2i_X[`D_KES_GF_ORDER-1:0] <= o_k_2i_X[`D_KES_GF_ORDER-1:0];
end
endcase
end
end
d_parallel_FFM_gate_GF12 d_delta_2im2_FFM_v_2i_X (
.i_poly_form_A (i_delta_2im2[`D_KES_GF_ORDER-1:0]),
.i_poly_form_B (o_v_2i_X[`D_KES_GF_ORDER-1:0]),
.o_poly_form_result(w_v_2ip2_X_term_A[`D_KES_GF_ORDER-1:0]));
assign w_v_2ip2_X[`D_KES_GF_ORDER-1:0] = w_v_2ip2_X_term_A[`D_KES_GF_ORDER-1:0];
assign w_k_2ip2_X[`D_KES_GF_ORDER-1:0] = D_KES_VALUE_ZERO[`D_KES_GF_ORDER-1:0];
endmodule
|
/*!
btcminer -- BTCMiner for ZTEX USB-FPGA Modules: HDL code: hash pipelines
Copyright (C) 2011 ZTEX GmbH
http://www.ztex.de
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License version 3 as
published by the Free Software Foundation.
This program is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, see http://www.gnu.org/licenses/.
!*/
`define IDX(x) (((x)+1)*(32)-1):((x)*(32))
`define E0(x) ( {{x}[1:0],{x}[31:2]} ^ {{x}[12:0],{x}[31:13]} ^ {{x}[21:0],{x}[31:22]} )
`define E1(x) ( {{x}[5:0],{x}[31:6]} ^ {{x}[10:0],{x}[31:11]} ^ {{x}[24:0],{x}[31:25]} )
`define CH(x,y,z) ( (z) ^ ((x) & ((y) ^ (z))) )
`define MAJ(x,y,z) ( ((x) & (y)) | ((z) & ((x) | (y))) )
`define S0(x) ( { {x}[6:4] ^ {x}[17:15], {{x}[3:0], {x}[31:7]} ^ {{x}[14:0],{x}[31:18]} ^ {x}[31:3] } )
`define S1(x) ( { {x}[16:7] ^ {x}[18:9], {{x}[6:0], {x}[31:17]} ^ {{x}[8:0],{x}[31:19]} ^ {x}[31:10] } )
module sha256_pipe2_base ( clk, i_state, i_data, out );
parameter STAGES = 64;
input clk;
input [255:0] i_state;
input [511:0] i_data;
output [255:0] out;
localparam Ks = {
32'h428a2f98, 32'h71374491, 32'hb5c0fbcf, 32'he9b5dba5,
32'h3956c25b, 32'h59f111f1, 32'h923f82a4, 32'hab1c5ed5,
32'hd807aa98, 32'h12835b01, 32'h243185be, 32'h550c7dc3,
32'h72be5d74, 32'h80deb1fe, 32'h9bdc06a7, 32'hc19bf174,
32'he49b69c1, 32'hefbe4786, 32'h0fc19dc6, 32'h240ca1cc,
32'h2de92c6f, 32'h4a7484aa, 32'h5cb0a9dc, 32'h76f988da,
32'h983e5152, 32'ha831c66d, 32'hb00327c8, 32'hbf597fc7,
32'hc6e00bf3, 32'hd5a79147, 32'h06ca6351, 32'h14292967,
32'h27b70a85, 32'h2e1b2138, 32'h4d2c6dfc, 32'h53380d13,
32'h650a7354, 32'h766a0abb, 32'h81c2c92e, 32'h92722c85,
32'ha2bfe8a1, 32'ha81a664b, 32'hc24b8b70, 32'hc76c51a3,
32'hd192e819, 32'hd6990624, 32'hf40e3585, 32'h106aa070,
32'h19a4c116, 32'h1e376c08, 32'h2748774c, 32'h34b0bcb5,
32'h391c0cb3, 32'h4ed8aa4a, 32'h5b9cca4f, 32'h682e6ff3,
32'h748f82ee, 32'h78a5636f, 32'h84c87814, 32'h8cc70208,
32'h90befffa, 32'ha4506ceb, 32'hbef9a3f7, 32'hc67178f2
};
genvar i;
generate
for (i = 0; i <= STAGES; i = i + 1) begin : S
reg [511:0] data;
reg [223:0] state;
reg [31:0] t1_p1;
if(i == 0)
begin
always @ (posedge clk)
begin
data <= i_data;
state <= i_state[223:0];
t1_p1 <= i_state[`IDX(7)] + i_data[`IDX(0)] + Ks[`IDX(63)];
end
end else
begin
reg [511:0] data_buf;
reg [223:0] state_buf;
reg [31:0] data15_p1, data15_p2, data15_p3, t1;
always @ (posedge clk)
begin
data_buf <= S[i-1].data;
data[479:0] <= data_buf[511:32];
data15_p1 <= `S1( S[i-1].data[`IDX(15)] ); // 3
data15_p2 <= data15_p1; // 1
data15_p3 <= ( ( i == 1 ) ? `S1( S[i-1].data[`IDX(14)] ) : S[i-1].data15_p2 ) + S[i-1].data[`IDX(9)] + S[i-1].data[`IDX(0)]; // 3
data[`IDX(15)] <= `S0( data_buf[`IDX(1)] ) + data15_p3; // 4
state_buf <= S[i-1].state; // 2
t1 <= `CH( S[i-1].state[`IDX(4)], S[i-1].state[`IDX(5)], S[i-1].state[`IDX(6)] ) + `E1( S[i-1].state[`IDX(4)] ) + S[i-1].t1_p1; // 6
state[`IDX(0)] <= `MAJ( state_buf[`IDX(0)], state_buf[`IDX(1)], state_buf[`IDX(2)] ) + `E0( state_buf[`IDX(0)] ) + t1; // 7
state[`IDX(1)] <= state_buf[`IDX(0)]; // 1
state[`IDX(2)] <= state_buf[`IDX(1)]; // 1
state[`IDX(3)] <= state_buf[`IDX(2)]; // 1
state[`IDX(4)] <= state_buf[`IDX(3)] + t1; // 2
state[`IDX(5)] <= state_buf[`IDX(4)]; // 1
state[`IDX(6)] <= state_buf[`IDX(5)]; // 1
t1_p1 <= state_buf[`IDX(6)] + data_buf[`IDX(1)] + Ks[`IDX((127-i) & 63)]; // 2
end
end
end
endgenerate
reg [31:0] state7, state7_buf;
always @ (posedge clk)
begin
state7_buf <= S[STAGES-1].state[`IDX(6)];
state7 <= state7_buf;
end
assign out[223:0] = S[STAGES].state;
assign out[255:224] = state7;
endmodule
module sha256_pipe130 ( clk, state, state2, data, hash );
input clk;
input [255:0] state, state2;
input [511:0] data;
output reg [255:0] hash;
wire [255:0] out;
sha256_pipe2_base #( .STAGES(64) ) P (
.clk(clk),
.i_state(state),
.i_data(data),
.out(out)
);
always @ (posedge clk)
begin
hash[`IDX(0)] <= state2[`IDX(0)] + out[`IDX(0)];
hash[`IDX(1)] <= state2[`IDX(1)] + out[`IDX(1)];
hash[`IDX(2)] <= state2[`IDX(2)] + out[`IDX(2)];
hash[`IDX(3)] <= state2[`IDX(3)] + out[`IDX(3)];
hash[`IDX(4)] <= state2[`IDX(4)] + out[`IDX(4)];
hash[`IDX(5)] <= state2[`IDX(5)] + out[`IDX(5)];
hash[`IDX(6)] <= state2[`IDX(6)] + out[`IDX(6)];
hash[`IDX(7)] <= state2[`IDX(7)] + out[`IDX(7)];
end
endmodule
module sha256_pipe123 ( clk, data, hash );
parameter state = 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
input clk;
input [511:0] data;
output [31:0] hash;
wire [255:0] out;
sha256_pipe2_base #( .STAGES(61) ) P (
.clk(clk),
.i_state(state),
.i_data(data),
.out(out)
);
assign hash = out[`IDX(4)];
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : arb_select.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Based on granta_r and grantc_r, this module selects a
// row and column command from the request information
// provided by the bank machines.
//
// Depending on address mode configuration, nCL and nCWL, a column
// command pipeline of up to three states will be created.
`timescale 1 ps / 1 ps
module mig_7series_v2_3_arb_select #
(
parameter TCQ = 100,
parameter EVEN_CWL_2T_MODE = "OFF",
parameter ADDR_CMD_MODE = "1T",
parameter BANK_VECT_INDX = 11,
parameter BANK_WIDTH = 3,
parameter BURST_MODE = "8",
parameter CS_WIDTH = 4,
parameter CL = 5,
parameter CWL = 5,
parameter DATA_BUF_ADDR_VECT_INDX = 31,
parameter DATA_BUF_ADDR_WIDTH = 8,
parameter DRAM_TYPE = "DDR3",
parameter EARLY_WR_DATA_ADDR = "OFF",
parameter ECC = "OFF",
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2,
parameter nCS_PER_RANK = 1,
parameter CKE_ODT_AUX = "FALSE",
parameter nSLOTS = 2,
parameter RANKS = 1,
parameter RANK_VECT_INDX = 15,
parameter RANK_WIDTH = 2,
parameter ROW_VECT_INDX = 63,
parameter ROW_WIDTH = 16,
parameter RTT_NOM = "40",
parameter RTT_WR = "120",
parameter SLOT_0_CONFIG = 8'b0000_0101,
parameter SLOT_1_CONFIG = 8'b0000_1010
)
(
// Outputs
output wire col_periodic_rd,
output wire [RANK_WIDTH-1:0] col_ra,
output wire [BANK_WIDTH-1:0] col_ba,
output wire [ROW_WIDTH-1:0] col_a,
output wire col_rmw,
output wire col_rd_wr,
output wire col_size,
output wire [ROW_WIDTH-1:0] col_row,
output wire [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr,
output wire [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr,
output wire [nCK_PER_CLK-1:0] mc_ras_n,
output wire [nCK_PER_CLK-1:0] mc_cas_n,
output wire [nCK_PER_CLK-1:0] mc_we_n,
output wire [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address,
output wire [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank,
output wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n,
output wire [1:0] mc_odt,
output wire [nCK_PER_CLK-1:0] mc_cke,
output wire [3:0] mc_aux_out0,
output wire [3:0] mc_aux_out1,
output [2:0] mc_cmd,
output wire [5:0] mc_data_offset,
output wire [5:0] mc_data_offset_1,
output wire [5:0] mc_data_offset_2,
output wire [1:0] mc_cas_slot,
output wire [RANK_WIDTH-1:0] rnk_config,
// Inputs
input clk,
input rst,
input init_calib_complete,
input [RANK_VECT_INDX:0] req_rank_r,
input [BANK_VECT_INDX:0] req_bank_r,
input [nBANK_MACHS-1:0] req_ras,
input [nBANK_MACHS-1:0] req_cas,
input [nBANK_MACHS-1:0] req_wr_r,
input [nBANK_MACHS-1:0] grant_row_r,
input [nBANK_MACHS-1:0] grant_pre_r,
input [ROW_VECT_INDX:0] row_addr,
input [nBANK_MACHS-1:0] row_cmd_wr,
input insert_maint_r1,
input maint_zq_r,
input maint_sre_r,
input maint_srx_r,
input [RANK_WIDTH-1:0] maint_rank_r,
input [nBANK_MACHS-1:0] req_periodic_rd_r,
input [nBANK_MACHS-1:0] req_size_r,
input [nBANK_MACHS-1:0] rd_wr_r,
input [ROW_VECT_INDX:0] req_row_r,
input [ROW_VECT_INDX:0] col_addr,
input [DATA_BUF_ADDR_VECT_INDX:0] req_data_buf_addr_r,
input [nBANK_MACHS-1:0] grant_col_r,
input [nBANK_MACHS-1:0] grant_col_wr,
input [6*RANKS-1:0] calib_rddata_offset,
input [6*RANKS-1:0] calib_rddata_offset_1,
input [6*RANKS-1:0] calib_rddata_offset_2,
input [5:0] col_channel_offset,
input [nBANK_MACHS-1:0] grant_config_r,
input rnk_config_strobe,
input [7:0] slot_0_present,
input [7:0] slot_1_present,
input send_cmd0_row,
input send_cmd0_col,
input send_cmd1_row,
input send_cmd1_col,
input send_cmd2_row,
input send_cmd2_col,
input send_cmd2_pre,
input send_cmd3_col,
input sent_col,
input cs_en0,
input cs_en1,
input cs_en2,
input cs_en3
);
localparam OUT_CMD_WIDTH = RANK_WIDTH + BANK_WIDTH + ROW_WIDTH + 1 + 1 + 1;
reg col_rd_wr_ns;
reg col_rd_wr_r = 1'b0;
reg [OUT_CMD_WIDTH-1:0] col_cmd_r = {OUT_CMD_WIDTH {1'b0}};
reg [OUT_CMD_WIDTH-1:0] row_cmd_r = {OUT_CMD_WIDTH {1'b0}};
// calib_rd_data_offset for currently targeted rank
reg [5:0] rank_rddata_offset_0;
reg [5:0] rank_rddata_offset_1;
reg [5:0] rank_rddata_offset_2;
// Toggle CKE[0] when entering and exiting self-refresh, disable CKE[1]
assign mc_aux_out0[0] = (maint_sre_r || maint_srx_r) & insert_maint_r1;
assign mc_aux_out0[2] = 1'b0;
reg cke_r;
reg cke_ns;
generate
if(CKE_ODT_AUX == "FALSE")begin
always @(posedge clk)
begin
if (rst)
cke_r = 1'b1;
else
cke_r = cke_ns;
end
always @(*)
begin
cke_ns = 1'b1;
if (maint_sre_r & insert_maint_r1)
cke_ns = 1'b0;
else if (cke_r==1'b0)
begin
if (maint_srx_r & insert_maint_r1)
cke_ns = 1'b1;
else
cke_ns = 1'b0;
end
end
end
endgenerate
// Disable ODT & CKE toggle enable high bits
assign mc_aux_out1 = 4'b0;
// implement PHY command word
assign mc_cmd[0] = sent_col;
assign mc_cmd[1] = EVEN_CWL_2T_MODE == "ON" ?
sent_col && col_rd_wr_r :
sent_col && col_rd_wr_ns;
assign mc_cmd[2] = ~sent_col;
// generate calib_rd_data_offset for current rank - only use rank 0 values for now
always @(calib_rddata_offset or calib_rddata_offset_1 or calib_rddata_offset_2) begin
rank_rddata_offset_0 = calib_rddata_offset[5:0];
rank_rddata_offset_1 = calib_rddata_offset_1[5:0];
rank_rddata_offset_2 = calib_rddata_offset_2[5:0];
end
// generate data offset
generate
if(EVEN_CWL_2T_MODE == "ON") begin : gen_mc_data_offset_even_cwl_2t
assign mc_data_offset = ~sent_col ?
6'b0 :
col_rd_wr_r ?
rank_rddata_offset_0 + col_channel_offset :
nCK_PER_CLK == 2 ?
CWL - 2 + col_channel_offset :
// nCK_PER_CLK == 4
CWL + 2 + col_channel_offset;
assign mc_data_offset_1 = ~sent_col ?
6'b0 :
col_rd_wr_r ?
rank_rddata_offset_1 + col_channel_offset :
nCK_PER_CLK == 2 ?
CWL - 2 + col_channel_offset :
// nCK_PER_CLK == 4
CWL + 2 + col_channel_offset;
assign mc_data_offset_2 = ~sent_col ?
6'b0 :
col_rd_wr_r ?
rank_rddata_offset_2 + col_channel_offset :
nCK_PER_CLK == 2 ?
CWL - 2 + col_channel_offset :
// nCK_PER_CLK == 4
CWL + 2 + col_channel_offset;
end
else begin : gen_mc_data_offset_not_even_cwl_2t
assign mc_data_offset = ~sent_col ?
6'b0 :
col_rd_wr_ns ?
rank_rddata_offset_0 + col_channel_offset :
nCK_PER_CLK == 2 ?
CWL - 2 + col_channel_offset :
// nCK_PER_CLK == 4
CWL + 2 + col_channel_offset;
assign mc_data_offset_1 = ~sent_col ?
6'b0 :
col_rd_wr_ns ?
rank_rddata_offset_1 + col_channel_offset :
nCK_PER_CLK == 2 ?
CWL - 2 + col_channel_offset :
// nCK_PER_CLK == 4
CWL + 2 + col_channel_offset;
assign mc_data_offset_2 = ~sent_col ?
6'b0 :
col_rd_wr_ns ?
rank_rddata_offset_2 + col_channel_offset :
nCK_PER_CLK == 2 ?
CWL - 2 + col_channel_offset :
// nCK_PER_CLK == 4
CWL + 2 + col_channel_offset;
end
endgenerate
assign mc_cas_slot = col_channel_offset[1:0];
// Based on arbitration results, select the row and column commands.
integer i;
reg [OUT_CMD_WIDTH-1:0] row_cmd_ns;
generate
begin : row_mux
wire [OUT_CMD_WIDTH-1:0] maint_cmd =
{maint_rank_r, // maintenance rank
row_cmd_r[15+:(BANK_WIDTH+ROW_WIDTH-11)],
// bank plus upper address bits
1'b0, // A10 = 0 for ZQCS
row_cmd_r[3+:10], // address bits [9:0]
// ZQ, SRX or SRE/REFRESH
(maint_zq_r ? 3'b110 : maint_srx_r ? 3'b111 : 3'b001)
};
always @(/*AS*/grant_row_r or insert_maint_r1 or maint_cmd
or req_bank_r or req_cas or req_rank_r or req_ras
or row_addr or row_cmd_r or row_cmd_wr or rst)
begin
row_cmd_ns = rst
? {RANK_WIDTH{1'b0}}
: insert_maint_r1
? maint_cmd
: row_cmd_r;
for (i=0; i<nBANK_MACHS; i=i+1)
if (grant_row_r[i])
row_cmd_ns = {req_rank_r[(RANK_WIDTH*i)+:RANK_WIDTH],
req_bank_r[(BANK_WIDTH*i)+:BANK_WIDTH],
row_addr[(ROW_WIDTH*i)+:ROW_WIDTH],
req_ras[i],
req_cas[i],
row_cmd_wr[i]};
end
if (ADDR_CMD_MODE == "2T" && nCK_PER_CLK == 2)
always @(posedge clk) row_cmd_r <= #TCQ row_cmd_ns;
end // row_mux
endgenerate
reg [OUT_CMD_WIDTH-1:0] pre_cmd_ns;
generate
if((nCK_PER_CLK == 4) && (ADDR_CMD_MODE != "2T")) begin : pre_mux
reg [OUT_CMD_WIDTH-1:0] pre_cmd_r = {OUT_CMD_WIDTH {1'b0}};
always @(/*AS*/grant_pre_r or req_bank_r or req_cas or req_rank_r or req_ras
or row_addr or pre_cmd_r or row_cmd_wr or rst)
begin
pre_cmd_ns = rst
? {RANK_WIDTH{1'b0}}
: pre_cmd_r;
for (i=0; i<nBANK_MACHS; i=i+1)
if (grant_pre_r[i])
pre_cmd_ns = {req_rank_r[(RANK_WIDTH*i)+:RANK_WIDTH],
req_bank_r[(BANK_WIDTH*i)+:BANK_WIDTH],
row_addr[(ROW_WIDTH*i)+:ROW_WIDTH],
req_ras[i],
req_cas[i],
row_cmd_wr[i]};
end
end // pre_mux
endgenerate
reg [OUT_CMD_WIDTH-1:0] col_cmd_ns;
generate
begin : col_mux
reg col_periodic_rd_ns;
reg col_periodic_rd_r;
reg col_rmw_ns;
reg col_rmw_r;
reg col_size_ns;
reg col_size_r;
reg [ROW_WIDTH-1:0] col_row_ns;
reg [ROW_WIDTH-1:0] col_row_r;
reg [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr_ns;
reg [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr_r;
always @(col_addr or col_cmd_r or col_data_buf_addr_r
or col_periodic_rd_r or col_rmw_r or col_row_r
or col_size_r or grant_col_r or rd_wr_r or req_bank_r
or req_data_buf_addr_r or req_periodic_rd_r
or req_rank_r or req_row_r or req_size_r or req_wr_r
or rst or col_rd_wr_r)
begin
col_periodic_rd_ns = ~rst && col_periodic_rd_r;
col_cmd_ns = {(rst ? {RANK_WIDTH{1'b0}}
: col_cmd_r[(OUT_CMD_WIDTH-1)-:RANK_WIDTH]),
((rst && ECC != "OFF")
? {OUT_CMD_WIDTH-3-RANK_WIDTH{1'b0}}
: col_cmd_r[3+:(OUT_CMD_WIDTH-3-RANK_WIDTH)]),
(rst ? 3'b0 : col_cmd_r[2:0])};
col_rmw_ns = col_rmw_r;
col_size_ns = rst ? 1'b0 : col_size_r;
col_row_ns = col_row_r;
col_rd_wr_ns = col_rd_wr_r;
col_data_buf_addr_ns = col_data_buf_addr_r;
for (i=0; i<nBANK_MACHS; i=i+1)
if (grant_col_r[i]) begin
col_periodic_rd_ns = req_periodic_rd_r[i];
col_cmd_ns = {req_rank_r[(RANK_WIDTH*i)+:RANK_WIDTH],
req_bank_r[(BANK_WIDTH*i)+:BANK_WIDTH],
col_addr[(ROW_WIDTH*i)+:ROW_WIDTH],
1'b1,
1'b0,
rd_wr_r[i]};
col_rmw_ns = req_wr_r[i] && rd_wr_r[i];
col_size_ns = req_size_r[i];
col_row_ns = req_row_r[(ROW_WIDTH*i)+:ROW_WIDTH];
col_rd_wr_ns = rd_wr_r[i];
col_data_buf_addr_ns =
req_data_buf_addr_r[(DATA_BUF_ADDR_WIDTH*i)+:DATA_BUF_ADDR_WIDTH];
end
end // always @ (...
if (EARLY_WR_DATA_ADDR == "OFF") begin : early_wr_data_addr_off
assign col_wr_data_buf_addr = col_data_buf_addr_ns;
end
else begin : early_wr_data_addr_on
reg [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr_ns;
reg [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr_r;
always @(/*AS*/col_wr_data_buf_addr_r or grant_col_wr
or req_data_buf_addr_r) begin
col_wr_data_buf_addr_ns = col_wr_data_buf_addr_r;
for (i=0; i<nBANK_MACHS; i=i+1)
if (grant_col_wr[i])
col_wr_data_buf_addr_ns =
req_data_buf_addr_r[(DATA_BUF_ADDR_WIDTH*i)+:DATA_BUF_ADDR_WIDTH];
end
always @(posedge clk) col_wr_data_buf_addr_r <=
#TCQ col_wr_data_buf_addr_ns;
assign col_wr_data_buf_addr = col_wr_data_buf_addr_ns;
end
always @(posedge clk) col_periodic_rd_r <= #TCQ col_periodic_rd_ns;
always @(posedge clk) col_rmw_r <= #TCQ col_rmw_ns;
always @(posedge clk) col_size_r <= #TCQ col_size_ns;
always @(posedge clk) col_data_buf_addr_r <=
#TCQ col_data_buf_addr_ns;
if (ECC != "OFF" || EVEN_CWL_2T_MODE == "ON") begin
always @(posedge clk) col_cmd_r <= #TCQ col_cmd_ns;
always @(posedge clk) col_row_r <= #TCQ col_row_ns;
end
always @(posedge clk) col_rd_wr_r <= #TCQ col_rd_wr_ns;
if(EVEN_CWL_2T_MODE == "ON") begin
assign col_periodic_rd = col_periodic_rd_r;
assign col_ra = col_cmd_r[3+ROW_WIDTH+BANK_WIDTH+:RANK_WIDTH];
assign col_ba = col_cmd_r[3+ROW_WIDTH+:BANK_WIDTH];
assign col_a = col_cmd_r[3+:ROW_WIDTH];
assign col_rmw = col_rmw_r;
assign col_rd_wr = col_rd_wr_r;
assign col_size = col_size_r;
assign col_row = col_row_r;
assign col_data_buf_addr = col_data_buf_addr_r;
end
else begin
assign col_periodic_rd = col_periodic_rd_ns;
assign col_ra = col_cmd_ns[3+ROW_WIDTH+BANK_WIDTH+:RANK_WIDTH];
assign col_ba = col_cmd_ns[3+ROW_WIDTH+:BANK_WIDTH];
assign col_a = col_cmd_ns[3+:ROW_WIDTH];
assign col_rmw = col_rmw_ns;
assign col_rd_wr = col_rd_wr_ns;
assign col_size = col_size_ns;
assign col_row = col_row_ns;
assign col_data_buf_addr = col_data_buf_addr_ns;
end
end // col_mux
endgenerate
reg [OUT_CMD_WIDTH-1:0] cmd0 = {OUT_CMD_WIDTH{1'b1}};
reg cke0;
always @(send_cmd0_row or send_cmd0_col or row_cmd_ns or row_cmd_r or col_cmd_ns or col_cmd_r or cke_ns or cke_r ) begin
cmd0 = {OUT_CMD_WIDTH{1'b1}};
if (send_cmd0_row) cmd0 = row_cmd_ns;
if (send_cmd0_row && EVEN_CWL_2T_MODE == "ON" && nCK_PER_CLK == 2) cmd0 = row_cmd_r;
if (send_cmd0_col) cmd0 = col_cmd_ns;
if (send_cmd0_col && EVEN_CWL_2T_MODE == "ON") cmd0 = col_cmd_r;
if (send_cmd0_row) cke0 = cke_ns;
else cke0 = cke_r ;
end
reg [OUT_CMD_WIDTH-1:0] cmd1 = {OUT_CMD_WIDTH{1'b1}};
generate
if ((nCK_PER_CLK == 2) || (nCK_PER_CLK == 4))
always @(send_cmd1_row or send_cmd1_col or row_cmd_ns or col_cmd_ns or pre_cmd_ns) begin
cmd1 = {OUT_CMD_WIDTH{1'b1}};
if (send_cmd1_row) cmd1 = row_cmd_ns;
if (send_cmd1_col) cmd1 = col_cmd_ns;
end
endgenerate
reg [OUT_CMD_WIDTH-1:0] cmd2 = {OUT_CMD_WIDTH{1'b1}};
reg [OUT_CMD_WIDTH-1:0] cmd3 = {OUT_CMD_WIDTH{1'b1}};
generate
if (nCK_PER_CLK == 4)
always @(send_cmd2_row or send_cmd2_col or send_cmd2_pre or send_cmd3_col or row_cmd_ns or col_cmd_ns or pre_cmd_ns) begin
cmd2 = {OUT_CMD_WIDTH{1'b1}};
cmd3 = {OUT_CMD_WIDTH{1'b1}};
if (send_cmd2_row) cmd2 = row_cmd_ns;
if (send_cmd2_col) cmd2 = col_cmd_ns;
if (send_cmd2_pre) cmd2 = pre_cmd_ns;
if (send_cmd3_col) cmd3 = col_cmd_ns;
end
endgenerate
// Output command bus 0.
wire [RANK_WIDTH-1:0] ra0;
// assign address
assign {ra0, mc_bank[BANK_WIDTH-1:0], mc_address[ROW_WIDTH-1:0], mc_ras_n[0], mc_cas_n[0], mc_we_n[0]} = cmd0;
// Output command bus 1.
wire [RANK_WIDTH-1:0] ra1;
// assign address
assign {ra1, mc_bank[2*BANK_WIDTH-1:BANK_WIDTH], mc_address[2*ROW_WIDTH-1:ROW_WIDTH], mc_ras_n[1], mc_cas_n[1], mc_we_n[1]} = cmd1;
wire [RANK_WIDTH-1:0] ra2;
wire [RANK_WIDTH-1:0] ra3;
generate
if(nCK_PER_CLK == 4) begin
// Output command bus 2.
// assign address
assign {ra2, mc_bank[3*BANK_WIDTH-1:2*BANK_WIDTH], mc_address[3*ROW_WIDTH-1:2*ROW_WIDTH], mc_ras_n[2], mc_cas_n[2], mc_we_n[2]} = cmd2;
// Output command bus 3.
// assign address
assign {ra3, mc_bank[4*BANK_WIDTH-1:3*BANK_WIDTH], mc_address[4*ROW_WIDTH-1:3*ROW_WIDTH], mc_ras_n[3], mc_cas_n[3], mc_we_n[3]} =
cmd3;
end
endgenerate
generate
if(CKE_ODT_AUX == "FALSE")begin
assign mc_cke[0] = cke0;
assign mc_cke[1] = cke_ns;
if(nCK_PER_CLK == 4) begin
assign mc_cke[2] = cke_ns;
assign mc_cke[3] = cke_ns;
end
end
endgenerate
// Output cs busses.
localparam ONE = {nCS_PER_RANK{1'b1}};
wire [(CS_WIDTH*nCS_PER_RANK)-1:0] cs_one_hot =
{{CS_WIDTH{1'b0}},ONE};
assign mc_cs_n[CS_WIDTH*nCS_PER_RANK -1 :0 ] =
{(~(cs_one_hot << (nCS_PER_RANK*ra0)) | {CS_WIDTH*nCS_PER_RANK{~cs_en0}})};
assign mc_cs_n[2*CS_WIDTH*nCS_PER_RANK -1 : CS_WIDTH*nCS_PER_RANK ] =
{(~(cs_one_hot << (nCS_PER_RANK*ra1)) | {CS_WIDTH*nCS_PER_RANK{~cs_en1}})};
generate
if(nCK_PER_CLK == 4) begin
assign mc_cs_n[3*CS_WIDTH*nCS_PER_RANK -1 :2*CS_WIDTH*nCS_PER_RANK ] =
{(~(cs_one_hot << (nCS_PER_RANK*ra2)) | {CS_WIDTH*nCS_PER_RANK{~cs_en2}})};
assign mc_cs_n[4*CS_WIDTH*nCS_PER_RANK -1 :3*CS_WIDTH*nCS_PER_RANK ] =
{(~(cs_one_hot << (nCS_PER_RANK*ra3)) | {CS_WIDTH*nCS_PER_RANK{~cs_en3}})};
end
endgenerate
// Output rnk_config info.
reg [RANK_WIDTH-1:0] rnk_config_ns;
reg [RANK_WIDTH-1:0] rnk_config_r;
always @(/*AS*/grant_config_r
or rnk_config_r or rnk_config_strobe or req_rank_r or rst) begin
if (rst) rnk_config_ns = {RANK_WIDTH{1'b0}};
else begin
rnk_config_ns = rnk_config_r;
if (rnk_config_strobe)
for (i=0; i<nBANK_MACHS; i=i+1)
if (grant_config_r[i]) rnk_config_ns = req_rank_r[(RANK_WIDTH*i)+:RANK_WIDTH];
end
end
always @(posedge clk) rnk_config_r <= #TCQ rnk_config_ns;
assign rnk_config = rnk_config_ns;
// Generate ODT signals.
wire [CS_WIDTH-1:0] col_ra_one_hot = cs_one_hot << col_ra;
wire slot_0_select = (nSLOTS == 1) ? |(col_ra_one_hot & slot_0_present)
: (slot_0_present[2] & slot_0_present[0]) ?
|(col_ra_one_hot[CS_WIDTH-1:0] & {slot_0_present[2],
slot_0_present[0]}) : (slot_0_present[0])?
col_ra_one_hot[0] : 1'b0;
wire slot_0_read = EVEN_CWL_2T_MODE == "ON" ?
slot_0_select && col_rd_wr_r :
slot_0_select && col_rd_wr_ns;
wire slot_0_write = EVEN_CWL_2T_MODE == "ON" ?
slot_0_select && ~col_rd_wr_r :
slot_0_select && ~col_rd_wr_ns;
reg [1:0] slot_1_population = 2'b0;
reg[1:0] slot_0_population;
always @(/*AS*/slot_0_present) begin
slot_0_population = 2'b0;
for (i=0; i<8; i=i+1)
if (~slot_0_population[1])
if (slot_0_present[i] == 1'b1) slot_0_population =
slot_0_population + 2'b1;
end
// ODT on in slot 0 for writes to slot 0 (and R/W to slot 1 for DDR3)
wire slot_0_odt = (DRAM_TYPE == "DDR3") ? ~slot_0_read : slot_0_write;
assign mc_aux_out0[1] = slot_0_odt & sent_col; // Only send for COL cmds
generate
if (nSLOTS > 1) begin : slot_1_configured
wire slot_1_select = (slot_1_present[3] & slot_1_present[1])?
|({col_ra_one_hot[slot_0_population+1],
col_ra_one_hot[slot_0_population]}) :
(slot_1_present[1]) ? col_ra_one_hot[slot_0_population] :1'b0;
wire slot_1_read = EVEN_CWL_2T_MODE == "ON" ?
slot_1_select && col_rd_wr_r :
slot_1_select && col_rd_wr_ns;
wire slot_1_write = EVEN_CWL_2T_MODE == "ON" ?
slot_1_select && ~col_rd_wr_r :
slot_1_select && ~col_rd_wr_ns;
// ODT on in slot 1 for writes to slot 1 (and R/W to slot 0 for DDR3)
wire slot_1_odt = (DRAM_TYPE == "DDR3") ? ~slot_1_read : slot_1_write;
assign mc_aux_out0[3] = slot_1_odt & sent_col; // Only send for COL cmds
end // if (nSLOTS > 1)
else begin
// Disable slot 1 ODT when not present
assign mc_aux_out0[3] = 1'b0;
end // else: !if(nSLOTS > 1)
endgenerate
generate
if(CKE_ODT_AUX == "FALSE")begin
reg[1:0] mc_aux_out_r ;
reg[1:0] mc_aux_out_r_1 ;
reg[1:0] mc_aux_out_r_2 ;
always@(posedge clk) begin
mc_aux_out_r[0] <= #TCQ mc_aux_out0[1] ;
mc_aux_out_r[1] <= #TCQ mc_aux_out0[3] ;
mc_aux_out_r_1 <= #TCQ mc_aux_out_r ;
mc_aux_out_r_2 <= #TCQ mc_aux_out_r_1 ;
end
if((nCK_PER_CLK == 4) && (nSLOTS > 1 )) begin:odt_high_time_4_1_dslot
assign mc_odt[0] = mc_aux_out0[1] | mc_aux_out_r[0] | mc_aux_out_r_1[0];
assign mc_odt[1] = mc_aux_out0[3] | mc_aux_out_r[1] | mc_aux_out_r_1[1];
end else if(nCK_PER_CLK == 4) begin:odt_high_time_4_1
assign mc_odt[0] = mc_aux_out0[1] | mc_aux_out_r[0] ;
assign mc_odt[1] = mc_aux_out0[3] | mc_aux_out_r[1] ;
end else if(nCK_PER_CLK == 2) begin:odt_high_time_2_1
assign mc_odt[0] = mc_aux_out0[1] | mc_aux_out_r[0] | mc_aux_out_r_1[0] | mc_aux_out_r_2[0] ;
assign mc_odt[1] = mc_aux_out0[3] | mc_aux_out_r[1] | mc_aux_out_r_1[1] | mc_aux_out_r_2[1] ;
end
end
endgenerate
endmodule
|
//-----------------------------------------------------------------------------
//-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
//--
//-- This file contains confidential and proprietary information
//-- of Xilinx, Inc. and is protected under U.S. and
//-- international copyright and other intellectual property
//-- laws.
//--
//-- DISCLAIMER
//-- This disclaimer is not a license and does not grant any
//-- rights to the materials distributed herewith. Except as
//-- otherwise provided in a valid license issued to you by
//-- Xilinx, and to the maximum extent permitted by applicable
//-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
//-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
//-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
//-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
//-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
//-- (2) Xilinx shall not be liable (whether in contract or tort,
//-- including negligence, or under any other theory of
//-- liability) for any loss or damage of any kind or nature
//-- related to, arising under or in connection with these
//-- materials, including for any direct, or any indirect,
//-- special, incidental, or consequential loss or damage
//-- (including loss of data, profits, goodwill, or any type of
//-- loss or damage suffered as a result of any action brought
//-- by a third party) even if such damage or loss was
//-- reasonably foreseeable or Xilinx had been advised of the
//-- possibility of the same.
//--
//-- CRITICAL APPLICATIONS
//-- Xilinx products are not designed or intended to be fail-
//-- safe, or for use in any application requiring fail-safe
//-- performance, such as life-support or safety devices or
//-- systems, Class III medical devices, nuclear facilities,
//-- applications related to the deployment of airbags, or any
//-- other applications that could lead to death, personal
//-- injury, or severe property or environmental damage
//-- (individually and collectively, "Critical
//-- Applications"). Customer assumes the sole risk and
//-- liability of any use of Xilinx products in Critical
//-- Applications, subject only to applicable laws and
//-- regulations governing limitations on product liability.
//--
//-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
//-- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: ACP Transaction Checker
//
// Check for optimized ACP transactions and flag if they are broken.
//
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// atc
// aw_atc
// w_atc
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
module processing_system7_v5_5_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of all ADDR signals on SI and MI side of checker.
// Range: 32.
parameter integer C_AXI_DATA_WIDTH = 64,
// Width of all DATA signals on SI and MI side of checker.
// Range: 64.
parameter integer C_AXI_AWUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_AXI_ARUSER_WIDTH = 1,
// Width of ARUSER signals.
// Range: >= 1.
parameter integer C_AXI_WUSER_WIDTH = 1,
// Width of WUSER signals.
// Range: >= 1.
parameter integer C_AXI_RUSER_WIDTH = 1,
// Width of RUSER signals.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1
// Width of BUSER signals.
// Range: >= 1.
)
(
// Global Signals
input wire ACLK,
input wire ARESETN,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
input wire [4-1:0] S_AXI_AWLEN,
input wire [3-1:0] S_AXI_AWSIZE,
input wire [2-1:0] S_AXI_AWBURST,
input wire [2-1:0] S_AXI_AWLOCK,
input wire [4-1:0] S_AXI_AWCACHE,
input wire [3-1:0] S_AXI_AWPROT,
input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
// Slave Interface Write Data Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID,
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output wire [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
input wire [4-1:0] S_AXI_ARLEN,
input wire [3-1:0] S_AXI_ARSIZE,
input wire [2-1:0] S_AXI_ARBURST,
input wire [2-1:0] S_AXI_ARLOCK,
input wire [4-1:0] S_AXI_ARCACHE,
input wire [3-1:0] S_AXI_ARPROT,
input wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [2-1:0] S_AXI_RRESP,
output wire S_AXI_RLAST,
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
output wire [4-1:0] M_AXI_AWLEN,
output wire [3-1:0] M_AXI_AWSIZE,
output wire [2-1:0] M_AXI_AWBURST,
output wire [2-1:0] M_AXI_AWLOCK,
output wire [4-1:0] M_AXI_AWCACHE,
output wire [3-1:0] M_AXI_AWPROT,
output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER,
output wire M_AXI_AWVALID,
input wire M_AXI_AWREADY,
// Master Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Master Interface Read Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
output wire [4-1:0] M_AXI_ARLEN,
output wire [3-1:0] M_AXI_ARSIZE,
output wire [2-1:0] M_AXI_ARBURST,
output wire [2-1:0] M_AXI_ARLOCK,
output wire [4-1:0] M_AXI_ARCACHE,
output wire [3-1:0] M_AXI_ARPROT,
output wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER,
output wire M_AXI_ARVALID,
input wire M_AXI_ARREADY,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID,
input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RLAST,
input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY,
output wire ERROR_TRIGGER,
output wire [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
localparam C_FIFO_DEPTH_LOG = 4;
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Internal reset.
reg ARESET;
// AW->W command queue signals.
wire cmd_w_valid;
wire cmd_w_check;
wire [C_AXI_ID_WIDTH-1:0] cmd_w_id;
wire cmd_w_ready;
// W->B command queue signals.
wire cmd_b_push;
wire cmd_b_error;
wire [C_AXI_ID_WIDTH-1:0] cmd_b_id;
wire cmd_b_full;
wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr;
wire cmd_b_ready;
/////////////////////////////////////////////////////////////////////////////
// Handle Internal Reset
/////////////////////////////////////////////////////////////////////////////
always @ (posedge ACLK) begin
ARESET <= !ARESETN;
end
/////////////////////////////////////////////////////////////////////////////
// Handle Write Channels (AW/W/B)
/////////////////////////////////////////////////////////////////////////////
// Write Address Channel.
processing_system7_v5_5_aw_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_addr_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (Out)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Address Ports
.S_AXI_AWID (S_AXI_AWID),
.S_AXI_AWADDR (S_AXI_AWADDR),
.S_AXI_AWLEN (S_AXI_AWLEN),
.S_AXI_AWSIZE (S_AXI_AWSIZE),
.S_AXI_AWBURST (S_AXI_AWBURST),
.S_AXI_AWLOCK (S_AXI_AWLOCK),
.S_AXI_AWCACHE (S_AXI_AWCACHE),
.S_AXI_AWPROT (S_AXI_AWPROT),
.S_AXI_AWUSER (S_AXI_AWUSER),
.S_AXI_AWVALID (S_AXI_AWVALID),
.S_AXI_AWREADY (S_AXI_AWREADY),
// Master Interface Write Address Port
.M_AXI_AWID (M_AXI_AWID),
.M_AXI_AWADDR (M_AXI_AWADDR),
.M_AXI_AWLEN (M_AXI_AWLEN),
.M_AXI_AWSIZE (M_AXI_AWSIZE),
.M_AXI_AWBURST (M_AXI_AWBURST),
.M_AXI_AWLOCK (M_AXI_AWLOCK),
.M_AXI_AWCACHE (M_AXI_AWCACHE),
.M_AXI_AWPROT (M_AXI_AWPROT),
.M_AXI_AWUSER (M_AXI_AWUSER),
.M_AXI_AWVALID (M_AXI_AWVALID),
.M_AXI_AWREADY (M_AXI_AWREADY)
);
// Write Data channel.
processing_system7_v5_5_w_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH)
) write_data_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
// Command Interface (Out)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
// Slave Interface Write Data Ports
.S_AXI_WID (S_AXI_WID),
.S_AXI_WDATA (S_AXI_WDATA),
.S_AXI_WSTRB (S_AXI_WSTRB),
.S_AXI_WLAST (S_AXI_WLAST),
.S_AXI_WUSER (S_AXI_WUSER),
.S_AXI_WVALID (S_AXI_WVALID),
.S_AXI_WREADY (S_AXI_WREADY),
// Master Interface Write Data Ports
.M_AXI_WID (M_AXI_WID),
.M_AXI_WDATA (M_AXI_WDATA),
.M_AXI_WSTRB (M_AXI_WSTRB),
.M_AXI_WLAST (M_AXI_WLAST),
.M_AXI_WUSER (M_AXI_WUSER),
.M_AXI_WVALID (M_AXI_WVALID),
.M_AXI_WREADY (M_AXI_WREADY)
);
// Write Response channel.
processing_system7_v5_5_b_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_response_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Response Ports
.S_AXI_BID (S_AXI_BID),
.S_AXI_BRESP (S_AXI_BRESP),
.S_AXI_BUSER (S_AXI_BUSER),
.S_AXI_BVALID (S_AXI_BVALID),
.S_AXI_BREADY (S_AXI_BREADY),
// Master Interface Write Response Ports
.M_AXI_BID (M_AXI_BID),
.M_AXI_BRESP (M_AXI_BRESP),
.M_AXI_BUSER (M_AXI_BUSER),
.M_AXI_BVALID (M_AXI_BVALID),
.M_AXI_BREADY (M_AXI_BREADY),
// Trigger detection
.ERROR_TRIGGER (ERROR_TRIGGER),
.ERROR_TRANSACTION_ID (ERROR_TRANSACTION_ID)
);
/////////////////////////////////////////////////////////////////////////////
// Handle Read Channels (AR/R)
/////////////////////////////////////////////////////////////////////////////
// Read Address Port
assign M_AXI_ARID = S_AXI_ARID;
assign M_AXI_ARADDR = S_AXI_ARADDR;
assign M_AXI_ARLEN = S_AXI_ARLEN;
assign M_AXI_ARSIZE = S_AXI_ARSIZE;
assign M_AXI_ARBURST = S_AXI_ARBURST;
assign M_AXI_ARLOCK = S_AXI_ARLOCK;
assign M_AXI_ARCACHE = S_AXI_ARCACHE;
assign M_AXI_ARPROT = S_AXI_ARPROT;
assign M_AXI_ARUSER = S_AXI_ARUSER;
assign M_AXI_ARVALID = S_AXI_ARVALID;
assign S_AXI_ARREADY = M_AXI_ARREADY;
// Read Data Port
assign S_AXI_RID = M_AXI_RID;
assign S_AXI_RDATA = M_AXI_RDATA;
assign S_AXI_RRESP = M_AXI_RRESP;
assign S_AXI_RLAST = M_AXI_RLAST;
assign S_AXI_RUSER = M_AXI_RUSER;
assign S_AXI_RVALID = M_AXI_RVALID;
assign M_AXI_RREADY = S_AXI_RREADY;
endmodule
`default_nettype wire
|
// hps_sdram.v
// This file was auto-generated from altera_mem_if_hps_emif_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 13.1.1 166 at 2014.04.26.23:18:03
`timescale 1 ps / 1 ps
module hps_sdram (
input wire pll_ref_clk, // pll_ref_clk.clk
input wire global_reset_n, // global_reset.reset_n
input wire soft_reset_n, // soft_reset.reset_n
output wire [14:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire [0:0] mem_ck, // .mem_ck
output wire [0:0] mem_ck_n, // .mem_ck_n
output wire [0:0] mem_cke, // .mem_cke
output wire [0:0] mem_cs_n, // .mem_cs_n
output wire [3:0] mem_dm, // .mem_dm
output wire [0:0] mem_ras_n, // .mem_ras_n
output wire [0:0] mem_cas_n, // .mem_cas_n
output wire [0:0] mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [31:0] mem_dq, // .mem_dq
inout wire [3:0] mem_dqs, // .mem_dqs
inout wire [3:0] mem_dqs_n, // .mem_dqs_n
output wire [0:0] mem_odt, // .mem_odt
input wire oct_rzqin // oct.rzqin
);
wire pll_afi_clk_clk; // pll:afi_clk -> [c0:afi_clk, p0:afi_clk]
wire pll_afi_half_clk_clk; // pll:afi_half_clk -> [c0:afi_half_clk, p0:afi_half_clk]
wire [3:0] p0_afi_afi_wlat; // p0:afi_wlat -> c0:afi_wlat
wire [0:0] p0_afi_afi_rdata_valid; // p0:afi_rdata_valid -> c0:afi_rdata_valid
wire p0_afi_afi_cal_success; // p0:afi_cal_success -> c0:afi_cal_success
wire [4:0] p0_afi_afi_rlat; // p0:afi_rlat -> c0:afi_rlat
wire [79:0] p0_afi_afi_rdata; // p0:afi_rdata -> c0:afi_rdata
wire p0_afi_afi_cal_fail; // p0:afi_cal_fail -> c0:afi_cal_fail
wire p0_afi_reset_reset; // p0:afi_reset_n -> c0:afi_reset_n
wire [1:0] c0_afi_afi_cs_n; // c0:afi_cs_n -> p0:afi_cs_n
wire [1:0] c0_afi_afi_cke; // c0:afi_cke -> p0:afi_cke
wire [0:0] c0_afi_afi_ras_n; // c0:afi_ras_n -> p0:afi_ras_n
wire [0:0] c0_afi_afi_mem_clk_disable; // c0:afi_mem_clk_disable -> p0:afi_mem_clk_disable
wire [9:0] c0_afi_afi_dm; // c0:afi_dm -> p0:afi_dm
wire [1:0] c0_afi_afi_odt; // c0:afi_odt -> p0:afi_odt
wire [19:0] c0_afi_afi_addr; // c0:afi_addr -> p0:afi_addr
wire [4:0] c0_afi_afi_rdata_en_full; // c0:afi_rdata_en_full -> p0:afi_rdata_en_full
wire [0:0] c0_afi_afi_we_n; // c0:afi_we_n -> p0:afi_we_n
wire [2:0] c0_afi_afi_ba; // c0:afi_ba -> p0:afi_ba
wire [79:0] c0_afi_afi_wdata; // c0:afi_wdata -> p0:afi_wdata
wire [4:0] c0_afi_afi_rdata_en; // c0:afi_rdata_en -> p0:afi_rdata_en
wire [0:0] c0_afi_afi_rst_n; // c0:afi_rst_n -> p0:afi_rst_n
wire [0:0] c0_afi_afi_cas_n; // c0:afi_cas_n -> p0:afi_cas_n
wire [4:0] c0_afi_afi_wdata_valid; // c0:afi_wdata_valid -> p0:afi_wdata_valid
wire [4:0] c0_afi_afi_dqs_burst; // c0:afi_dqs_burst -> p0:afi_dqs_burst
wire [7:0] c0_hard_phy_cfg_cfg_addlat; // c0:cfg_addlat -> p0:cfg_addlat
wire [7:0] c0_hard_phy_cfg_cfg_rowaddrwidth; // c0:cfg_rowaddrwidth -> p0:cfg_rowaddrwidth
wire [7:0] c0_hard_phy_cfg_cfg_csaddrwidth; // c0:cfg_csaddrwidth -> p0:cfg_csaddrwidth
wire [7:0] c0_hard_phy_cfg_cfg_devicewidth; // c0:cfg_devicewidth -> p0:cfg_devicewidth
wire [7:0] c0_hard_phy_cfg_cfg_interfacewidth; // c0:cfg_interfacewidth -> p0:cfg_interfacewidth
wire [7:0] c0_hard_phy_cfg_cfg_tcl; // c0:cfg_tcl -> p0:cfg_tcl
wire [7:0] c0_hard_phy_cfg_cfg_coladdrwidth; // c0:cfg_coladdrwidth -> p0:cfg_coladdrwidth
wire [15:0] c0_hard_phy_cfg_cfg_trefi; // c0:cfg_trefi -> p0:cfg_trefi
wire [23:0] c0_hard_phy_cfg_cfg_dramconfig; // c0:cfg_dramconfig -> p0:cfg_dramconfig
wire [7:0] c0_hard_phy_cfg_cfg_caswrlat; // c0:cfg_caswrlat -> p0:cfg_caswrlat
wire [7:0] c0_hard_phy_cfg_cfg_trfc; // c0:cfg_trfc -> p0:cfg_trfc
wire [7:0] c0_hard_phy_cfg_cfg_bankaddrwidth; // c0:cfg_bankaddrwidth -> p0:cfg_bankaddrwidth
wire [7:0] c0_hard_phy_cfg_cfg_twr; // c0:cfg_twr -> p0:cfg_twr
wire [7:0] c0_hard_phy_cfg_cfg_tmrd; // c0:cfg_tmrd -> p0:cfg_tmrd
wire p0_ctl_clk_clk; // p0:ctl_clk -> c0:ctl_clk
wire p0_ctl_reset_reset; // p0:ctl_reset_n -> c0:ctl_reset_n
wire p0_io_int_io_intaficalsuccess; // p0:io_intaficalsuccess -> c0:io_intaficalsuccess
wire p0_io_int_io_intaficalfail; // p0:io_intaficalfail -> c0:io_intaficalfail
wire [15:0] oct_oct_sharing_parallelterminationcontrol; // oct:parallelterminationcontrol -> p0:parallelterminationcontrol
wire [15:0] oct_oct_sharing_seriesterminationcontrol; // oct:seriesterminationcontrol -> p0:seriesterminationcontrol
wire pll_pll_sharing_pll_mem_phy_clk; // pll:pll_mem_phy_clk -> p0:pll_mem_phy_clk
wire pll_pll_sharing_pll_avl_clk; // pll:pll_avl_clk -> p0:pll_avl_clk
wire pll_pll_sharing_pll_avl_phy_clk; // pll:pll_avl_phy_clk -> p0:pll_avl_phy_clk
wire pll_pll_sharing_afi_phy_clk; // pll:afi_phy_clk -> p0:afi_phy_clk
wire pll_pll_sharing_pll_config_clk; // pll:pll_config_clk -> p0:pll_config_clk
wire pll_pll_sharing_pll_addr_cmd_clk; // pll:pll_addr_cmd_clk -> p0:pll_addr_cmd_clk
wire pll_pll_sharing_pll_mem_clk; // pll:pll_mem_clk -> p0:pll_mem_clk
wire pll_pll_sharing_pll_locked; // pll:pll_locked -> p0:pll_locked
wire pll_pll_sharing_pll_write_clk_pre_phy_clk; // pll:pll_write_clk_pre_phy_clk -> p0:pll_write_clk_pre_phy_clk
wire pll_pll_sharing_pll_write_clk; // pll:pll_write_clk -> p0:pll_write_clk
wire p0_dll_clk_clk; // p0:dll_clk -> dll:clk
wire p0_dll_sharing_dll_pll_locked; // p0:dll_pll_locked -> dll:dll_pll_locked
wire [6:0] dll_dll_sharing_dll_delayctrl; // dll:dll_delayctrl -> p0:dll_delayctrl
hps_sdram_pll pll (
.global_reset_n (global_reset_n), // global_reset.reset_n
.pll_ref_clk (pll_ref_clk), // pll_ref_clk.clk
.afi_clk (pll_afi_clk_clk), // afi_clk.clk
.afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk
.pll_mem_clk (pll_pll_sharing_pll_mem_clk), // pll_sharing.pll_mem_clk
.pll_write_clk (pll_pll_sharing_pll_write_clk), // .pll_write_clk
.pll_locked (pll_pll_sharing_pll_locked), // .pll_locked
.pll_write_clk_pre_phy_clk (pll_pll_sharing_pll_write_clk_pre_phy_clk), // .pll_write_clk_pre_phy_clk
.pll_addr_cmd_clk (pll_pll_sharing_pll_addr_cmd_clk), // .pll_addr_cmd_clk
.pll_avl_clk (pll_pll_sharing_pll_avl_clk), // .pll_avl_clk
.pll_config_clk (pll_pll_sharing_pll_config_clk), // .pll_config_clk
.pll_mem_phy_clk (pll_pll_sharing_pll_mem_phy_clk), // .pll_mem_phy_clk
.afi_phy_clk (pll_pll_sharing_afi_phy_clk), // .afi_phy_clk
.pll_avl_phy_clk (pll_pll_sharing_pll_avl_phy_clk) // .pll_avl_phy_clk
);
hps_sdram_p0 p0 (
.global_reset_n (global_reset_n), // global_reset.reset_n
.soft_reset_n (soft_reset_n), // soft_reset.reset_n
.afi_reset_n (p0_afi_reset_reset), // afi_reset.reset_n
.afi_reset_export_n (), // afi_reset_export.reset_n
.ctl_reset_n (p0_ctl_reset_reset), // ctl_reset.reset_n
.afi_clk (pll_afi_clk_clk), // afi_clk.clk
.afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk
.ctl_clk (p0_ctl_clk_clk), // ctl_clk.clk
.avl_clk (), // avl_clk.clk
.avl_reset_n (), // avl_reset.reset_n
.scc_clk (), // scc_clk.clk
.scc_reset_n (), // scc_reset.reset_n
.avl_address (), // avl.address
.avl_write (), // .write
.avl_writedata (), // .writedata
.avl_read (), // .read
.avl_readdata (), // .readdata
.avl_waitrequest (), // .waitrequest
.dll_clk (p0_dll_clk_clk), // dll_clk.clk
.afi_addr (c0_afi_afi_addr), // afi.afi_addr
.afi_ba (c0_afi_afi_ba), // .afi_ba
.afi_cke (c0_afi_afi_cke), // .afi_cke
.afi_cs_n (c0_afi_afi_cs_n), // .afi_cs_n
.afi_ras_n (c0_afi_afi_ras_n), // .afi_ras_n
.afi_we_n (c0_afi_afi_we_n), // .afi_we_n
.afi_cas_n (c0_afi_afi_cas_n), // .afi_cas_n
.afi_rst_n (c0_afi_afi_rst_n), // .afi_rst_n
.afi_odt (c0_afi_afi_odt), // .afi_odt
.afi_dqs_burst (c0_afi_afi_dqs_burst), // .afi_dqs_burst
.afi_wdata_valid (c0_afi_afi_wdata_valid), // .afi_wdata_valid
.afi_wdata (c0_afi_afi_wdata), // .afi_wdata
.afi_dm (c0_afi_afi_dm), // .afi_dm
.afi_rdata (p0_afi_afi_rdata), // .afi_rdata
.afi_rdata_en (c0_afi_afi_rdata_en), // .afi_rdata_en
.afi_rdata_en_full (c0_afi_afi_rdata_en_full), // .afi_rdata_en_full
.afi_rdata_valid (p0_afi_afi_rdata_valid), // .afi_rdata_valid
.afi_wlat (p0_afi_afi_wlat), // .afi_wlat
.afi_rlat (p0_afi_afi_rlat), // .afi_rlat
.afi_cal_success (p0_afi_afi_cal_success), // .afi_cal_success
.afi_cal_fail (p0_afi_afi_cal_fail), // .afi_cal_fail
.scc_data (), // scc.scc_data
.scc_dqs_ena (), // .scc_dqs_ena
.scc_dqs_io_ena (), // .scc_dqs_io_ena
.scc_dq_ena (), // .scc_dq_ena
.scc_dm_ena (), // .scc_dm_ena
.capture_strobe_tracking (), // .capture_strobe_tracking
.scc_upd (), // .scc_upd
.cfg_addlat (c0_hard_phy_cfg_cfg_addlat), // hard_phy_cfg.cfg_addlat
.cfg_bankaddrwidth (c0_hard_phy_cfg_cfg_bankaddrwidth), // .cfg_bankaddrwidth
.cfg_caswrlat (c0_hard_phy_cfg_cfg_caswrlat), // .cfg_caswrlat
.cfg_coladdrwidth (c0_hard_phy_cfg_cfg_coladdrwidth), // .cfg_coladdrwidth
.cfg_csaddrwidth (c0_hard_phy_cfg_cfg_csaddrwidth), // .cfg_csaddrwidth
.cfg_devicewidth (c0_hard_phy_cfg_cfg_devicewidth), // .cfg_devicewidth
.cfg_dramconfig (c0_hard_phy_cfg_cfg_dramconfig), // .cfg_dramconfig
.cfg_interfacewidth (c0_hard_phy_cfg_cfg_interfacewidth), // .cfg_interfacewidth
.cfg_rowaddrwidth (c0_hard_phy_cfg_cfg_rowaddrwidth), // .cfg_rowaddrwidth
.cfg_tcl (c0_hard_phy_cfg_cfg_tcl), // .cfg_tcl
.cfg_tmrd (c0_hard_phy_cfg_cfg_tmrd), // .cfg_tmrd
.cfg_trefi (c0_hard_phy_cfg_cfg_trefi), // .cfg_trefi
.cfg_trfc (c0_hard_phy_cfg_cfg_trfc), // .cfg_trfc
.cfg_twr (c0_hard_phy_cfg_cfg_twr), // .cfg_twr
.afi_mem_clk_disable (c0_afi_afi_mem_clk_disable), // afi_mem_clk_disable.afi_mem_clk_disable
.pll_mem_clk (pll_pll_sharing_pll_mem_clk), // pll_sharing.pll_mem_clk
.pll_write_clk (pll_pll_sharing_pll_write_clk), // .pll_write_clk
.pll_locked (pll_pll_sharing_pll_locked), // .pll_locked
.pll_write_clk_pre_phy_clk (pll_pll_sharing_pll_write_clk_pre_phy_clk), // .pll_write_clk_pre_phy_clk
.pll_addr_cmd_clk (pll_pll_sharing_pll_addr_cmd_clk), // .pll_addr_cmd_clk
.pll_avl_clk (pll_pll_sharing_pll_avl_clk), // .pll_avl_clk
.pll_config_clk (pll_pll_sharing_pll_config_clk), // .pll_config_clk
.pll_mem_phy_clk (pll_pll_sharing_pll_mem_phy_clk), // .pll_mem_phy_clk
.afi_phy_clk (pll_pll_sharing_afi_phy_clk), // .afi_phy_clk
.pll_avl_phy_clk (pll_pll_sharing_pll_avl_phy_clk), // .pll_avl_phy_clk
.dll_pll_locked (p0_dll_sharing_dll_pll_locked), // dll_sharing.dll_pll_locked
.dll_delayctrl (dll_dll_sharing_dll_delayctrl), // .dll_delayctrl
.seriesterminationcontrol (oct_oct_sharing_seriesterminationcontrol), // oct_sharing.seriesterminationcontrol
.parallelterminationcontrol (oct_oct_sharing_parallelterminationcontrol), // .parallelterminationcontrol
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_dm (mem_dm), // .mem_dm
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.io_intaficalfail (p0_io_int_io_intaficalfail), // io_int.io_intaficalfail
.io_intaficalsuccess (p0_io_int_io_intaficalsuccess), // .io_intaficalsuccess
.csr_soft_reset_req (1'b0), // (terminated)
.io_intaddrdout (64'b0000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.io_intbadout (12'b000000000000), // (terminated)
.io_intcasndout (4'b0000), // (terminated)
.io_intckdout (4'b0000), // (terminated)
.io_intckedout (8'b00000000), // (terminated)
.io_intckndout (4'b0000), // (terminated)
.io_intcsndout (8'b00000000), // (terminated)
.io_intdmdout (20'b00000000000000000000), // (terminated)
.io_intdqdin (), // (terminated)
.io_intdqdout (180'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.io_intdqoe (90'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.io_intdqsbdout (20'b00000000000000000000), // (terminated)
.io_intdqsboe (10'b0000000000), // (terminated)
.io_intdqsdout (20'b00000000000000000000), // (terminated)
.io_intdqslogicdqsena (10'b0000000000), // (terminated)
.io_intdqslogicfiforeset (5'b00000), // (terminated)
.io_intdqslogicincrdataen (10'b0000000000), // (terminated)
.io_intdqslogicincwrptr (10'b0000000000), // (terminated)
.io_intdqslogicoct (10'b0000000000), // (terminated)
.io_intdqslogicrdatavalid (), // (terminated)
.io_intdqslogicreadlatency (25'b0000000000000000000000000), // (terminated)
.io_intdqsoe (10'b0000000000), // (terminated)
.io_intodtdout (8'b00000000), // (terminated)
.io_intrasndout (4'b0000), // (terminated)
.io_intresetndout (4'b0000), // (terminated)
.io_intwendout (4'b0000), // (terminated)
.io_intafirlat (), // (terminated)
.io_intafiwlat () // (terminated)
);
altera_mem_if_hhp_qseq_synth_top #(
.MEM_IF_DM_WIDTH (4),
.MEM_IF_DQS_WIDTH (4),
.MEM_IF_CS_WIDTH (1),
.MEM_IF_DQ_WIDTH (32)
) seq (
);
altera_mem_if_hard_memory_controller_top_cyclonev #(
.MEM_IF_DQS_WIDTH (4),
.MEM_IF_CS_WIDTH (1),
.MEM_IF_CHIP_BITS (1),
.MEM_IF_CLK_PAIR_COUNT (1),
.CSR_ADDR_WIDTH (10),
.CSR_DATA_WIDTH (8),
.CSR_BE_WIDTH (1),
.AVL_ADDR_WIDTH (27),
.AVL_DATA_WIDTH (64),
.AVL_SIZE_WIDTH (3),
.AVL_DATA_WIDTH_PORT_0 (1),
.AVL_ADDR_WIDTH_PORT_0 (1),
.AVL_NUM_SYMBOLS_PORT_0 (1),
.LSB_WFIFO_PORT_0 (5),
.MSB_WFIFO_PORT_0 (5),
.LSB_RFIFO_PORT_0 (5),
.MSB_RFIFO_PORT_0 (5),
.AVL_DATA_WIDTH_PORT_1 (1),
.AVL_ADDR_WIDTH_PORT_1 (1),
.AVL_NUM_SYMBOLS_PORT_1 (1),
.LSB_WFIFO_PORT_1 (5),
.MSB_WFIFO_PORT_1 (5),
.LSB_RFIFO_PORT_1 (5),
.MSB_RFIFO_PORT_1 (5),
.AVL_DATA_WIDTH_PORT_2 (1),
.AVL_ADDR_WIDTH_PORT_2 (1),
.AVL_NUM_SYMBOLS_PORT_2 (1),
.LSB_WFIFO_PORT_2 (5),
.MSB_WFIFO_PORT_2 (5),
.LSB_RFIFO_PORT_2 (5),
.MSB_RFIFO_PORT_2 (5),
.AVL_DATA_WIDTH_PORT_3 (1),
.AVL_ADDR_WIDTH_PORT_3 (1),
.AVL_NUM_SYMBOLS_PORT_3 (1),
.LSB_WFIFO_PORT_3 (5),
.MSB_WFIFO_PORT_3 (5),
.LSB_RFIFO_PORT_3 (5),
.MSB_RFIFO_PORT_3 (5),
.AVL_DATA_WIDTH_PORT_4 (1),
.AVL_ADDR_WIDTH_PORT_4 (1),
.AVL_NUM_SYMBOLS_PORT_4 (1),
.LSB_WFIFO_PORT_4 (5),
.MSB_WFIFO_PORT_4 (5),
.LSB_RFIFO_PORT_4 (5),
.MSB_RFIFO_PORT_4 (5),
.AVL_DATA_WIDTH_PORT_5 (1),
.AVL_ADDR_WIDTH_PORT_5 (1),
.AVL_NUM_SYMBOLS_PORT_5 (1),
.LSB_WFIFO_PORT_5 (5),
.MSB_WFIFO_PORT_5 (5),
.LSB_RFIFO_PORT_5 (5),
.MSB_RFIFO_PORT_5 (5),
.ENUM_ATTR_COUNTER_ONE_RESET ("DISABLED"),
.ENUM_ATTR_COUNTER_ZERO_RESET ("DISABLED"),
.ENUM_ATTR_STATIC_CONFIG_VALID ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_0 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_1 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_2 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_3 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_4 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_5 ("DISABLED"),
.ENUM_CAL_REQ ("DISABLED"),
.ENUM_CFG_BURST_LENGTH ("BL_8"),
.ENUM_CFG_INTERFACE_WIDTH ("DWIDTH_32"),
.ENUM_CFG_SELF_RFSH_EXIT_CYCLES ("SELF_RFSH_EXIT_CYCLES_512"),
.ENUM_CFG_STARVE_LIMIT ("STARVE_LIMIT_10"),
.ENUM_CFG_TYPE ("DDR3"),
.ENUM_CLOCK_OFF_0 ("DISABLED"),
.ENUM_CLOCK_OFF_1 ("DISABLED"),
.ENUM_CLOCK_OFF_2 ("DISABLED"),
.ENUM_CLOCK_OFF_3 ("DISABLED"),
.ENUM_CLOCK_OFF_4 ("DISABLED"),
.ENUM_CLOCK_OFF_5 ("DISABLED"),
.ENUM_CLR_INTR ("NO_CLR_INTR"),
.ENUM_CMD_PORT_IN_USE_0 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_1 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_2 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_3 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_4 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_5 ("FALSE"),
.ENUM_CPORT0_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT0_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT0_TYPE ("DISABLE"),
.ENUM_CPORT0_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT1_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT1_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT1_TYPE ("DISABLE"),
.ENUM_CPORT1_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT2_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT2_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT2_TYPE ("DISABLE"),
.ENUM_CPORT2_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT3_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT3_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT3_TYPE ("DISABLE"),
.ENUM_CPORT3_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT4_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT4_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT4_TYPE ("DISABLE"),
.ENUM_CPORT4_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT5_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT5_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT5_TYPE ("DISABLE"),
.ENUM_CPORT5_WFIFO_MAP ("FIFO_0"),
.ENUM_CTL_ADDR_ORDER ("CHIP_ROW_BANK_COL"),
.ENUM_CTL_ECC_ENABLED ("CTL_ECC_DISABLED"),
.ENUM_CTL_ECC_RMW_ENABLED ("CTL_ECC_RMW_DISABLED"),
.ENUM_CTL_REGDIMM_ENABLED ("REGDIMM_DISABLED"),
.ENUM_CTL_USR_REFRESH ("CTL_USR_REFRESH_DISABLED"),
.ENUM_CTRL_WIDTH ("DATA_WIDTH_64_BIT"),
.ENUM_DELAY_BONDING ("BONDING_LATENCY_0"),
.ENUM_DFX_BYPASS_ENABLE ("DFX_BYPASS_DISABLED"),
.ENUM_DISABLE_MERGING ("MERGING_ENABLED"),
.ENUM_ECC_DQ_WIDTH ("ECC_DQ_WIDTH_0"),
.ENUM_ENABLE_ATPG ("DISABLED"),
.ENUM_ENABLE_BONDING_0 ("DISABLED"),
.ENUM_ENABLE_BONDING_1 ("DISABLED"),
.ENUM_ENABLE_BONDING_2 ("DISABLED"),
.ENUM_ENABLE_BONDING_3 ("DISABLED"),
.ENUM_ENABLE_BONDING_4 ("DISABLED"),
.ENUM_ENABLE_BONDING_5 ("DISABLED"),
.ENUM_ENABLE_BONDING_WRAPBACK ("DISABLED"),
.ENUM_ENABLE_DQS_TRACKING ("ENABLED"),
.ENUM_ENABLE_ECC_CODE_OVERWRITES ("DISABLED"),
.ENUM_ENABLE_FAST_EXIT_PPD ("DISABLED"),
.ENUM_ENABLE_INTR ("DISABLED"),
.ENUM_ENABLE_NO_DM ("DISABLED"),
.ENUM_ENABLE_PIPELINEGLOBAL ("DISABLED"),
.ENUM_GANGED_ARF ("DISABLED"),
.ENUM_GEN_DBE ("GEN_DBE_DISABLED"),
.ENUM_GEN_SBE ("GEN_SBE_DISABLED"),
.ENUM_INC_SYNC ("FIFO_SET_2"),
.ENUM_LOCAL_IF_CS_WIDTH ("ADDR_WIDTH_0"),
.ENUM_MASK_CORR_DROPPED_INTR ("DISABLED"),
.ENUM_MASK_DBE_INTR ("DISABLED"),
.ENUM_MASK_SBE_INTR ("DISABLED"),
.ENUM_MEM_IF_AL ("AL_0"),
.ENUM_MEM_IF_BANKADDR_WIDTH ("ADDR_WIDTH_3"),
.ENUM_MEM_IF_BURSTLENGTH ("MEM_IF_BURSTLENGTH_8"),
.ENUM_MEM_IF_COLADDR_WIDTH ("ADDR_WIDTH_10"),
.ENUM_MEM_IF_CS_PER_RANK ("MEM_IF_CS_PER_RANK_1"),
.ENUM_MEM_IF_CS_WIDTH ("MEM_IF_CS_WIDTH_1"),
.ENUM_MEM_IF_DQ_PER_CHIP ("MEM_IF_DQ_PER_CHIP_8"),
.ENUM_MEM_IF_DQS_WIDTH ("DQS_WIDTH_4"),
.ENUM_MEM_IF_DWIDTH ("MEM_IF_DWIDTH_32"),
.ENUM_MEM_IF_MEMTYPE ("DDR3_SDRAM"),
.ENUM_MEM_IF_ROWADDR_WIDTH ("ADDR_WIDTH_15"),
.ENUM_MEM_IF_SPEEDBIN ("DDR3_1600_8_8_8"),
.ENUM_MEM_IF_TCCD ("TCCD_4"),
.ENUM_MEM_IF_TCL ("TCL_11"),
.ENUM_MEM_IF_TCWL ("TCWL_8"),
.ENUM_MEM_IF_TFAW ("TFAW_12"),
.ENUM_MEM_IF_TMRD ("TMRD_4"),
.ENUM_MEM_IF_TRAS ("TRAS_14"),
.ENUM_MEM_IF_TRC ("TRC_20"),
.ENUM_MEM_IF_TRCD ("TRCD_6"),
.ENUM_MEM_IF_TRP ("TRP_6"),
.ENUM_MEM_IF_TRRD ("TRRD_3"),
.ENUM_MEM_IF_TRTP ("TRTP_3"),
.ENUM_MEM_IF_TWR ("TWR_6"),
.ENUM_MEM_IF_TWTR ("TWTR_4"),
.ENUM_MMR_CFG_MEM_BL ("MP_BL_8"),
.ENUM_OUTPUT_REGD ("DISABLED"),
.ENUM_PDN_EXIT_CYCLES ("SLOW_EXIT"),
.ENUM_PORT0_WIDTH ("PORT_32_BIT"),
.ENUM_PORT1_WIDTH ("PORT_32_BIT"),
.ENUM_PORT2_WIDTH ("PORT_32_BIT"),
.ENUM_PORT3_WIDTH ("PORT_32_BIT"),
.ENUM_PORT4_WIDTH ("PORT_32_BIT"),
.ENUM_PORT5_WIDTH ("PORT_32_BIT"),
.ENUM_PRIORITY_0_0 ("WEIGHT_0"),
.ENUM_PRIORITY_0_1 ("WEIGHT_0"),
.ENUM_PRIORITY_0_2 ("WEIGHT_0"),
.ENUM_PRIORITY_0_3 ("WEIGHT_0"),
.ENUM_PRIORITY_0_4 ("WEIGHT_0"),
.ENUM_PRIORITY_0_5 ("WEIGHT_0"),
.ENUM_PRIORITY_1_0 ("WEIGHT_0"),
.ENUM_PRIORITY_1_1 ("WEIGHT_0"),
.ENUM_PRIORITY_1_2 ("WEIGHT_0"),
.ENUM_PRIORITY_1_3 ("WEIGHT_0"),
.ENUM_PRIORITY_1_4 ("WEIGHT_0"),
.ENUM_PRIORITY_1_5 ("WEIGHT_0"),
.ENUM_PRIORITY_2_0 ("WEIGHT_0"),
.ENUM_PRIORITY_2_1 ("WEIGHT_0"),
.ENUM_PRIORITY_2_2 ("WEIGHT_0"),
.ENUM_PRIORITY_2_3 ("WEIGHT_0"),
.ENUM_PRIORITY_2_4 ("WEIGHT_0"),
.ENUM_PRIORITY_2_5 ("WEIGHT_0"),
.ENUM_PRIORITY_3_0 ("WEIGHT_0"),
.ENUM_PRIORITY_3_1 ("WEIGHT_0"),
.ENUM_PRIORITY_3_2 ("WEIGHT_0"),
.ENUM_PRIORITY_3_3 ("WEIGHT_0"),
.ENUM_PRIORITY_3_4 ("WEIGHT_0"),
.ENUM_PRIORITY_3_5 ("WEIGHT_0"),
.ENUM_PRIORITY_4_0 ("WEIGHT_0"),
.ENUM_PRIORITY_4_1 ("WEIGHT_0"),
.ENUM_PRIORITY_4_2 ("WEIGHT_0"),
.ENUM_PRIORITY_4_3 ("WEIGHT_0"),
.ENUM_PRIORITY_4_4 ("WEIGHT_0"),
.ENUM_PRIORITY_4_5 ("WEIGHT_0"),
.ENUM_PRIORITY_5_0 ("WEIGHT_0"),
.ENUM_PRIORITY_5_1 ("WEIGHT_0"),
.ENUM_PRIORITY_5_2 ("WEIGHT_0"),
.ENUM_PRIORITY_5_3 ("WEIGHT_0"),
.ENUM_PRIORITY_5_4 ("WEIGHT_0"),
.ENUM_PRIORITY_5_5 ("WEIGHT_0"),
.ENUM_PRIORITY_6_0 ("WEIGHT_0"),
.ENUM_PRIORITY_6_1 ("WEIGHT_0"),
.ENUM_PRIORITY_6_2 ("WEIGHT_0"),
.ENUM_PRIORITY_6_3 ("WEIGHT_0"),
.ENUM_PRIORITY_6_4 ("WEIGHT_0"),
.ENUM_PRIORITY_6_5 ("WEIGHT_0"),
.ENUM_PRIORITY_7_0 ("WEIGHT_0"),
.ENUM_PRIORITY_7_1 ("WEIGHT_0"),
.ENUM_PRIORITY_7_2 ("WEIGHT_0"),
.ENUM_PRIORITY_7_3 ("WEIGHT_0"),
.ENUM_PRIORITY_7_4 ("WEIGHT_0"),
.ENUM_PRIORITY_7_5 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_0 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_1 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_2 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_3 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_4 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_5 ("WEIGHT_0"),
.ENUM_RCFG_USER_PRIORITY_0 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_1 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_2 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_3 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_4 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_5 ("PRIORITY_1"),
.ENUM_RD_DWIDTH_0 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_1 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_2 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_3 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_4 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_5 ("DWIDTH_0"),
.ENUM_RD_FIFO_IN_USE_0 ("FALSE"),
.ENUM_RD_FIFO_IN_USE_1 ("FALSE"),
.ENUM_RD_FIFO_IN_USE_2 ("FALSE"),
.ENUM_RD_FIFO_IN_USE_3 ("FALSE"),
.ENUM_RD_PORT_INFO_0 ("USE_NO"),
.ENUM_RD_PORT_INFO_1 ("USE_NO"),
.ENUM_RD_PORT_INFO_2 ("USE_NO"),
.ENUM_RD_PORT_INFO_3 ("USE_NO"),
.ENUM_RD_PORT_INFO_4 ("USE_NO"),
.ENUM_RD_PORT_INFO_5 ("USE_NO"),
.ENUM_READ_ODT_CHIP ("ODT_DISABLED"),
.ENUM_REORDER_DATA ("DATA_REORDERING"),
.ENUM_RFIFO0_CPORT_MAP ("CMD_PORT_0"),
.ENUM_RFIFO1_CPORT_MAP ("CMD_PORT_0"),
.ENUM_RFIFO2_CPORT_MAP ("CMD_PORT_0"),
.ENUM_RFIFO3_CPORT_MAP ("CMD_PORT_0"),
.ENUM_SINGLE_READY_0 ("CONCATENATE_RDY"),
.ENUM_SINGLE_READY_1 ("CONCATENATE_RDY"),
.ENUM_SINGLE_READY_2 ("CONCATENATE_RDY"),
.ENUM_SINGLE_READY_3 ("CONCATENATE_RDY"),
.ENUM_STATIC_WEIGHT_0 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_1 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_2 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_3 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_4 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_5 ("WEIGHT_0"),
.ENUM_SYNC_MODE_0 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_1 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_2 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_3 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_4 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_5 ("ASYNCHRONOUS"),
.ENUM_TEST_MODE ("NORMAL_MODE"),
.ENUM_THLD_JAR1_0 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_1 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_2 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_3 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_4 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_5 ("THRESHOLD_32"),
.ENUM_THLD_JAR2_0 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_1 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_2 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_3 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_4 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_5 ("THRESHOLD_16"),
.ENUM_USE_ALMOST_EMPTY_0 ("EMPTY"),
.ENUM_USE_ALMOST_EMPTY_1 ("EMPTY"),
.ENUM_USE_ALMOST_EMPTY_2 ("EMPTY"),
.ENUM_USE_ALMOST_EMPTY_3 ("EMPTY"),
.ENUM_USER_ECC_EN ("DISABLE"),
.ENUM_USER_PRIORITY_0 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_1 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_2 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_3 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_4 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_5 ("PRIORITY_1"),
.ENUM_WFIFO0_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO0_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WFIFO1_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO1_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WFIFO2_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO2_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WFIFO3_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO3_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WR_DWIDTH_0 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_1 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_2 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_3 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_4 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_5 ("DWIDTH_0"),
.ENUM_WR_FIFO_IN_USE_0 ("FALSE"),
.ENUM_WR_FIFO_IN_USE_1 ("FALSE"),
.ENUM_WR_FIFO_IN_USE_2 ("FALSE"),
.ENUM_WR_FIFO_IN_USE_3 ("FALSE"),
.ENUM_WR_PORT_INFO_0 ("USE_NO"),
.ENUM_WR_PORT_INFO_1 ("USE_NO"),
.ENUM_WR_PORT_INFO_2 ("USE_NO"),
.ENUM_WR_PORT_INFO_3 ("USE_NO"),
.ENUM_WR_PORT_INFO_4 ("USE_NO"),
.ENUM_WR_PORT_INFO_5 ("USE_NO"),
.ENUM_WRITE_ODT_CHIP ("WRITE_CHIP0_ODT0_CHIP1"),
.INTG_MEM_AUTO_PD_CYCLES (0),
.INTG_CYC_TO_RLD_JARS_0 (1),
.INTG_CYC_TO_RLD_JARS_1 (1),
.INTG_CYC_TO_RLD_JARS_2 (1),
.INTG_CYC_TO_RLD_JARS_3 (1),
.INTG_CYC_TO_RLD_JARS_4 (1),
.INTG_CYC_TO_RLD_JARS_5 (1),
.INTG_EXTRA_CTL_CLK_ACT_TO_ACT (0),
.INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK (0),
.INTG_EXTRA_CTL_CLK_ACT_TO_PCH (0),
.INTG_EXTRA_CTL_CLK_ACT_TO_RDWR (0),
.INTG_EXTRA_CTL_CLK_ARF_PERIOD (0),
.INTG_EXTRA_CTL_CLK_ARF_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT (0),
.INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_PCH_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_PDN_PERIOD (0),
.INTG_EXTRA_CTL_CLK_PDN_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_RD_TO_PCH (0),
.INTG_EXTRA_CTL_CLK_RD_TO_RD (0),
.INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP (0),
.INTG_EXTRA_CTL_CLK_RD_TO_WR (2),
.INTG_EXTRA_CTL_CLK_RD_TO_WR_BC (2),
.INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP (2),
.INTG_EXTRA_CTL_CLK_SRF_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL (0),
.INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_WR_TO_PCH (0),
.INTG_EXTRA_CTL_CLK_WR_TO_RD (3),
.INTG_EXTRA_CTL_CLK_WR_TO_RD_BC (3),
.INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP (3),
.INTG_EXTRA_CTL_CLK_WR_TO_WR (0),
.INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP (0),
.INTG_MEM_IF_TREFI (3120),
.INTG_MEM_IF_TRFC (104),
.INTG_RCFG_SUM_WT_PRIORITY_0 (0),
.INTG_RCFG_SUM_WT_PRIORITY_1 (0),
.INTG_RCFG_SUM_WT_PRIORITY_2 (0),
.INTG_RCFG_SUM_WT_PRIORITY_3 (0),
.INTG_RCFG_SUM_WT_PRIORITY_4 (0),
.INTG_RCFG_SUM_WT_PRIORITY_5 (0),
.INTG_RCFG_SUM_WT_PRIORITY_6 (0),
.INTG_RCFG_SUM_WT_PRIORITY_7 (0),
.INTG_SUM_WT_PRIORITY_0 (0),
.INTG_SUM_WT_PRIORITY_1 (0),
.INTG_SUM_WT_PRIORITY_2 (0),
.INTG_SUM_WT_PRIORITY_3 (0),
.INTG_SUM_WT_PRIORITY_4 (0),
.INTG_SUM_WT_PRIORITY_5 (0),
.INTG_SUM_WT_PRIORITY_6 (0),
.INTG_SUM_WT_PRIORITY_7 (0),
.INTG_POWER_SAVING_EXIT_CYCLES (5),
.INTG_MEM_CLK_ENTRY_CYCLES (10),
.ENUM_ENABLE_BURST_INTERRUPT ("DISABLED"),
.ENUM_ENABLE_BURST_TERMINATE ("DISABLED"),
.AFI_RATE_RATIO (1),
.AFI_ADDR_WIDTH (15),
.AFI_BANKADDR_WIDTH (3),
.AFI_CONTROL_WIDTH (1),
.AFI_CS_WIDTH (1),
.AFI_DM_WIDTH (8),
.AFI_DQ_WIDTH (64),
.AFI_ODT_WIDTH (1),
.AFI_WRITE_DQS_WIDTH (4),
.AFI_RLAT_WIDTH (6),
.AFI_WLAT_WIDTH (6),
.HARD_PHY (1)
) c0 (
.afi_clk (pll_afi_clk_clk), // afi_clk.clk
.afi_reset_n (p0_afi_reset_reset), // afi_reset.reset_n
.ctl_reset_n (p0_ctl_reset_reset), // ctl_reset.reset_n
.afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk
.ctl_clk (p0_ctl_clk_clk), // ctl_clk.clk
.local_init_done (), // status.local_init_done
.local_cal_success (), // .local_cal_success
.local_cal_fail (), // .local_cal_fail
.afi_addr (c0_afi_afi_addr), // afi.afi_addr
.afi_ba (c0_afi_afi_ba), // .afi_ba
.afi_cke (c0_afi_afi_cke), // .afi_cke
.afi_cs_n (c0_afi_afi_cs_n), // .afi_cs_n
.afi_ras_n (c0_afi_afi_ras_n), // .afi_ras_n
.afi_we_n (c0_afi_afi_we_n), // .afi_we_n
.afi_cas_n (c0_afi_afi_cas_n), // .afi_cas_n
.afi_rst_n (c0_afi_afi_rst_n), // .afi_rst_n
.afi_odt (c0_afi_afi_odt), // .afi_odt
.afi_mem_clk_disable (c0_afi_afi_mem_clk_disable), // .afi_mem_clk_disable
.afi_init_req (), // .afi_init_req
.afi_cal_req (), // .afi_cal_req
.afi_seq_busy (), // .afi_seq_busy
.afi_ctl_refresh_done (), // .afi_ctl_refresh_done
.afi_ctl_long_idle (), // .afi_ctl_long_idle
.afi_dqs_burst (c0_afi_afi_dqs_burst), // .afi_dqs_burst
.afi_wdata_valid (c0_afi_afi_wdata_valid), // .afi_wdata_valid
.afi_wdata (c0_afi_afi_wdata), // .afi_wdata
.afi_dm (c0_afi_afi_dm), // .afi_dm
.afi_rdata (p0_afi_afi_rdata), // .afi_rdata
.afi_rdata_en (c0_afi_afi_rdata_en), // .afi_rdata_en
.afi_rdata_en_full (c0_afi_afi_rdata_en_full), // .afi_rdata_en_full
.afi_rdata_valid (p0_afi_afi_rdata_valid), // .afi_rdata_valid
.afi_wlat (p0_afi_afi_wlat), // .afi_wlat
.afi_rlat (p0_afi_afi_rlat), // .afi_rlat
.afi_cal_success (p0_afi_afi_cal_success), // .afi_cal_success
.afi_cal_fail (p0_afi_afi_cal_fail), // .afi_cal_fail
.cfg_addlat (c0_hard_phy_cfg_cfg_addlat), // hard_phy_cfg.cfg_addlat
.cfg_bankaddrwidth (c0_hard_phy_cfg_cfg_bankaddrwidth), // .cfg_bankaddrwidth
.cfg_caswrlat (c0_hard_phy_cfg_cfg_caswrlat), // .cfg_caswrlat
.cfg_coladdrwidth (c0_hard_phy_cfg_cfg_coladdrwidth), // .cfg_coladdrwidth
.cfg_csaddrwidth (c0_hard_phy_cfg_cfg_csaddrwidth), // .cfg_csaddrwidth
.cfg_devicewidth (c0_hard_phy_cfg_cfg_devicewidth), // .cfg_devicewidth
.cfg_dramconfig (c0_hard_phy_cfg_cfg_dramconfig), // .cfg_dramconfig
.cfg_interfacewidth (c0_hard_phy_cfg_cfg_interfacewidth), // .cfg_interfacewidth
.cfg_rowaddrwidth (c0_hard_phy_cfg_cfg_rowaddrwidth), // .cfg_rowaddrwidth
.cfg_tcl (c0_hard_phy_cfg_cfg_tcl), // .cfg_tcl
.cfg_tmrd (c0_hard_phy_cfg_cfg_tmrd), // .cfg_tmrd
.cfg_trefi (c0_hard_phy_cfg_cfg_trefi), // .cfg_trefi
.cfg_trfc (c0_hard_phy_cfg_cfg_trfc), // .cfg_trfc
.cfg_twr (c0_hard_phy_cfg_cfg_twr), // .cfg_twr
.io_intaficalfail (p0_io_int_io_intaficalfail), // io_int.io_intaficalfail
.io_intaficalsuccess (p0_io_int_io_intaficalsuccess), // .io_intaficalsuccess
.mp_cmd_clk_0 (1'b0), // (terminated)
.mp_cmd_reset_n_0 (1'b1), // (terminated)
.mp_cmd_clk_1 (1'b0), // (terminated)
.mp_cmd_reset_n_1 (1'b1), // (terminated)
.mp_cmd_clk_2 (1'b0), // (terminated)
.mp_cmd_reset_n_2 (1'b1), // (terminated)
.mp_cmd_clk_3 (1'b0), // (terminated)
.mp_cmd_reset_n_3 (1'b1), // (terminated)
.mp_cmd_clk_4 (1'b0), // (terminated)
.mp_cmd_reset_n_4 (1'b1), // (terminated)
.mp_cmd_clk_5 (1'b0), // (terminated)
.mp_cmd_reset_n_5 (1'b1), // (terminated)
.mp_rfifo_clk_0 (1'b0), // (terminated)
.mp_rfifo_reset_n_0 (1'b1), // (terminated)
.mp_wfifo_clk_0 (1'b0), // (terminated)
.mp_wfifo_reset_n_0 (1'b1), // (terminated)
.mp_rfifo_clk_1 (1'b0), // (terminated)
.mp_rfifo_reset_n_1 (1'b1), // (terminated)
.mp_wfifo_clk_1 (1'b0), // (terminated)
.mp_wfifo_reset_n_1 (1'b1), // (terminated)
.mp_rfifo_clk_2 (1'b0), // (terminated)
.mp_rfifo_reset_n_2 (1'b1), // (terminated)
.mp_wfifo_clk_2 (1'b0), // (terminated)
.mp_wfifo_reset_n_2 (1'b1), // (terminated)
.mp_rfifo_clk_3 (1'b0), // (terminated)
.mp_rfifo_reset_n_3 (1'b1), // (terminated)
.mp_wfifo_clk_3 (1'b0), // (terminated)
.mp_wfifo_reset_n_3 (1'b1), // (terminated)
.csr_clk (1'b0), // (terminated)
.csr_reset_n (1'b1), // (terminated)
.avl_ready_0 (), // (terminated)
.avl_burstbegin_0 (1'b0), // (terminated)
.avl_addr_0 (1'b0), // (terminated)
.avl_rdata_valid_0 (), // (terminated)
.avl_rdata_0 (), // (terminated)
.avl_wdata_0 (1'b0), // (terminated)
.avl_be_0 (1'b0), // (terminated)
.avl_read_req_0 (1'b0), // (terminated)
.avl_write_req_0 (1'b0), // (terminated)
.avl_size_0 (3'b000), // (terminated)
.avl_ready_1 (), // (terminated)
.avl_burstbegin_1 (1'b0), // (terminated)
.avl_addr_1 (1'b0), // (terminated)
.avl_rdata_valid_1 (), // (terminated)
.avl_rdata_1 (), // (terminated)
.avl_wdata_1 (1'b0), // (terminated)
.avl_be_1 (1'b0), // (terminated)
.avl_read_req_1 (1'b0), // (terminated)
.avl_write_req_1 (1'b0), // (terminated)
.avl_size_1 (3'b000), // (terminated)
.avl_ready_2 (), // (terminated)
.avl_burstbegin_2 (1'b0), // (terminated)
.avl_addr_2 (1'b0), // (terminated)
.avl_rdata_valid_2 (), // (terminated)
.avl_rdata_2 (), // (terminated)
.avl_wdata_2 (1'b0), // (terminated)
.avl_be_2 (1'b0), // (terminated)
.avl_read_req_2 (1'b0), // (terminated)
.avl_write_req_2 (1'b0), // (terminated)
.avl_size_2 (3'b000), // (terminated)
.avl_ready_3 (), // (terminated)
.avl_burstbegin_3 (1'b0), // (terminated)
.avl_addr_3 (1'b0), // (terminated)
.avl_rdata_valid_3 (), // (terminated)
.avl_rdata_3 (), // (terminated)
.avl_wdata_3 (1'b0), // (terminated)
.avl_be_3 (1'b0), // (terminated)
.avl_read_req_3 (1'b0), // (terminated)
.avl_write_req_3 (1'b0), // (terminated)
.avl_size_3 (3'b000), // (terminated)
.avl_ready_4 (), // (terminated)
.avl_burstbegin_4 (1'b0), // (terminated)
.avl_addr_4 (1'b0), // (terminated)
.avl_rdata_valid_4 (), // (terminated)
.avl_rdata_4 (), // (terminated)
.avl_wdata_4 (1'b0), // (terminated)
.avl_be_4 (1'b0), // (terminated)
.avl_read_req_4 (1'b0), // (terminated)
.avl_write_req_4 (1'b0), // (terminated)
.avl_size_4 (3'b000), // (terminated)
.avl_ready_5 (), // (terminated)
.avl_burstbegin_5 (1'b0), // (terminated)
.avl_addr_5 (1'b0), // (terminated)
.avl_rdata_valid_5 (), // (terminated)
.avl_rdata_5 (), // (terminated)
.avl_wdata_5 (1'b0), // (terminated)
.avl_be_5 (1'b0), // (terminated)
.avl_read_req_5 (1'b0), // (terminated)
.avl_write_req_5 (1'b0), // (terminated)
.avl_size_5 (3'b000), // (terminated)
.csr_write_req (1'b0), // (terminated)
.csr_read_req (1'b0), // (terminated)
.csr_waitrequest (), // (terminated)
.csr_addr (10'b0000000000), // (terminated)
.csr_be (1'b0), // (terminated)
.csr_wdata (8'b00000000), // (terminated)
.csr_rdata (), // (terminated)
.csr_rdata_valid (), // (terminated)
.local_multicast (1'b0), // (terminated)
.local_refresh_req (1'b0), // (terminated)
.local_refresh_chip (1'b0), // (terminated)
.local_refresh_ack (), // (terminated)
.local_self_rfsh_req (1'b0), // (terminated)
.local_self_rfsh_chip (1'b0), // (terminated)
.local_self_rfsh_ack (), // (terminated)
.local_deep_powerdn_req (1'b0), // (terminated)
.local_deep_powerdn_chip (1'b0), // (terminated)
.local_deep_powerdn_ack (), // (terminated)
.local_powerdn_ack (), // (terminated)
.local_priority (1'b0), // (terminated)
.bonding_in_1 (4'b0000), // (terminated)
.bonding_in_2 (6'b000000), // (terminated)
.bonding_in_3 (6'b000000), // (terminated)
.bonding_out_1 (), // (terminated)
.bonding_out_2 (), // (terminated)
.bonding_out_3 () // (terminated)
);
altera_mem_if_oct_cyclonev #(
.OCT_TERM_CONTROL_WIDTH (16)
) oct (
.oct_rzqin (oct_rzqin), // oct.rzqin
.seriesterminationcontrol (oct_oct_sharing_seriesterminationcontrol), // oct_sharing.seriesterminationcontrol
.parallelterminationcontrol (oct_oct_sharing_parallelterminationcontrol) // .parallelterminationcontrol
);
altera_mem_if_dll_cyclonev #(
.DLL_DELAY_CTRL_WIDTH (7),
.DLL_OFFSET_CTRL_WIDTH (6),
.DELAY_BUFFER_MODE ("HIGH"),
.DELAY_CHAIN_LENGTH (8),
.DLL_INPUT_FREQUENCY_PS_STR ("2500 ps")
) dll (
.clk (p0_dll_clk_clk), // clk.clk
.dll_pll_locked (p0_dll_sharing_dll_pll_locked), // dll_sharing.dll_pll_locked
.dll_delayctrl (dll_dll_sharing_dll_delayctrl) // .dll_delayctrl
);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2013.
// SPDX-License-Identifier: CC0-1.0
module t
(
input logic clk,
input logic daten,
input logic [8:0] datval,
output logic signed [3:0][3:0][35:0] datao
);
logic signed [3:0][3:0][3:0][8:0] datat;
genvar i;
generate
for (i=0; i<4; i++)begin
testio dut(.clk(clk), .arr3d_in(datat[i]), .arr2d_out(datao[i]));
end
endgenerate
genvar j;
generate
for (i=0; i<4; i++) begin
for (j=0; j<4; j++) begin
always_comb datat[i][j][0] = daten ? 9'h0 : datval;
always_comb datat[i][j][1] = daten ? 9'h1 : datval;
always_comb datat[i][j][2] = daten ? 9'h2 : datval;
always_comb datat[i][j][3] = daten ? 9'h3 : datval;
end
end
endgenerate
endmodule
module testio
(
input clk,
input logic signed [3:0] [3:0] [8:0] arr3d_in,
output logic signed [3:0] [35:0] arr2d_out
);
logic signed [3:0] [35:0] ar2d_out_pre;
always_comb ar2d_out_pre[0][35:0] = {arr3d_in[0][0][8:0], arr3d_in[0][1][8:0], arr3d_in[0][2][8:0], arr3d_in[0][3][8:0]};
always_comb ar2d_out_pre[0][35:0] = {arr3d_in[0][0][8:0], arr3d_in[0][1][8:0], arr3d_in[0][2][8:0], arr3d_in[0][3][8:0]};
always_comb ar2d_out_pre[0][35:0] = {arr3d_in[0][0][8:0], arr3d_in[0][1][8:0], arr3d_in[0][2][8:0], arr3d_in[0][3][8:0]};
always_comb ar2d_out_pre[0][35:0] = {arr3d_in[0][0][8:0], arr3d_in[0][1][8:0], arr3d_in[0][2][8:0], arr3d_in[0][3][8:0]};
always_ff @(posedge clk) begin
if (clk)
arr2d_out <= ar2d_out_pre;
end
endmodule
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module SOC_NIOS_II_jtag_debug_module_wrapper (
// inputs:
MonDReg,
break_readreg,
clk,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
// outputs:
jdo,
jrst_n,
st_ready_test_idle,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a,
take_no_action_tracemem_a
)
;
output [ 37: 0] jdo;
output jrst_n;
output st_ready_test_idle;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_action_tracemem_a;
output take_action_tracemem_b;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
output take_no_action_tracemem_a;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input clk;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
wire [ 37: 0] jdo;
wire jrst_n;
wire [ 37: 0] sr;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire vji_cdr;
wire [ 1: 0] vji_ir_in;
wire [ 1: 0] vji_ir_out;
wire vji_rti;
wire vji_sdr;
wire vji_tck;
wire vji_tdi;
wire vji_tdo;
wire vji_udr;
wire vji_uir;
//Change the sld_virtual_jtag_basic's defparams to
//switch between a regular Nios II or an internally embedded Nios II.
//For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34.
//For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135.
SOC_NIOS_II_jtag_debug_module_tck the_SOC_NIOS_II_jtag_debug_module_tck
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.ir_in (vji_ir_in),
.ir_out (vji_ir_out),
.jrst_n (jrst_n),
.jtag_state_rti (vji_rti),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.sr (sr),
.st_ready_test_idle (st_ready_test_idle),
.tck (vji_tck),
.tdi (vji_tdi),
.tdo (vji_tdo),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1),
.vs_cdr (vji_cdr),
.vs_sdr (vji_sdr),
.vs_uir (vji_uir)
);
SOC_NIOS_II_jtag_debug_module_sysclk the_SOC_NIOS_II_jtag_debug_module_sysclk
(
.clk (clk),
.ir_in (vji_ir_in),
.jdo (jdo),
.sr (sr),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_action_tracemem_a (take_action_tracemem_a),
.take_action_tracemem_b (take_action_tracemem_b),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.take_no_action_tracemem_a (take_no_action_tracemem_a),
.vs_udr (vji_udr),
.vs_uir (vji_uir)
);
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign vji_tck = 1'b0;
assign vji_tdi = 1'b0;
assign vji_sdr = 1'b0;
assign vji_cdr = 1'b0;
assign vji_rti = 1'b0;
assign vji_uir = 1'b0;
assign vji_udr = 1'b0;
assign vji_ir_in = 2'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// sld_virtual_jtag_basic SOC_NIOS_II_jtag_debug_module_phy
// (
// .ir_in (vji_ir_in),
// .ir_out (vji_ir_out),
// .jtag_state_rti (vji_rti),
// .tck (vji_tck),
// .tdi (vji_tdi),
// .tdo (vji_tdo),
// .virtual_state_cdr (vji_cdr),
// .virtual_state_sdr (vji_sdr),
// .virtual_state_udr (vji_udr),
// .virtual_state_uir (vji_uir)
// );
//
// defparam SOC_NIOS_II_jtag_debug_module_phy.sld_auto_instance_index = "YES",
// SOC_NIOS_II_jtag_debug_module_phy.sld_instance_index = 0,
// SOC_NIOS_II_jtag_debug_module_phy.sld_ir_width = 2,
// SOC_NIOS_II_jtag_debug_module_phy.sld_mfg_id = 70,
// SOC_NIOS_II_jtag_debug_module_phy.sld_sim_action = "",
// SOC_NIOS_II_jtag_debug_module_phy.sld_sim_n_scan = 0,
// SOC_NIOS_II_jtag_debug_module_phy.sld_sim_total_length = 0,
// SOC_NIOS_II_jtag_debug_module_phy.sld_type_id = 34,
// SOC_NIOS_II_jtag_debug_module_phy.sld_version = 3;
//
//synthesis read_comments_as_HDL off
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: ddr_phy_v4_0_phy_ocd_cntlr.v
// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose: Steps through the major sections of the output clock
// delay algorithm. Enabling various subblocks at the right time.
//
// Steps through each byte of the interface.
//
// Implements both the simple and complex data pattern.
//
// for each byte in interface
// begin
// Limit
// Scan - which includes DQS centering
// Precharge
// end
// set _wrlvl and _done equal to one
//
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v4_0_ddr_phy_ocd_cntlr #
(parameter TCQ = 100,
parameter DQS_CNT_WIDTH = 3,
parameter DQS_WIDTH = 8)
(/*AUTOARG*/
// Outputs
wrlvl_final, complex_wrlvl_final, oclk_init_delay_done,
ocd_prech_req, lim_start, complex_oclkdelay_calib_done,
oclkdelay_calib_done, phy_rddata_en_1, phy_rddata_en_2,
phy_rddata_en_3, ocd_cntlr2stg2_dec, oclkdelay_calib_cnt,
reset_scan,
// Inputs
clk, rst, prech_done, oclkdelay_calib_start,
complex_oclkdelay_calib_start, lim_done, phy_rddata_en,
po_counter_read_val, po_rdy, scan_done
);
localparam ONE = 1;
input clk;
input rst;
output wrlvl_final, complex_wrlvl_final;
reg wrlvl_final_ns, wrlvl_final_r, complex_wrlvl_final_ns, complex_wrlvl_final_r;
always @(posedge clk) wrlvl_final_r <= #TCQ wrlvl_final_ns;
always @(posedge clk) complex_wrlvl_final_r <= #TCQ complex_wrlvl_final_ns;
assign wrlvl_final = wrlvl_final_r;
assign complex_wrlvl_final = complex_wrlvl_final_r;
// Completed initial delay increment
output oclk_init_delay_done; // may not need this... maybe for fast cal mode.
assign oclk_init_delay_done = 1'b1;
// Precharge done status from ddr_phy_init
input prech_done;
reg ocd_prech_req_ns, ocd_prech_req_r;
always @(posedge clk) ocd_prech_req_r <= #TCQ ocd_prech_req_ns;
output ocd_prech_req;
assign ocd_prech_req = ocd_prech_req_r;
input oclkdelay_calib_start, complex_oclkdelay_calib_start;
input lim_done;
reg lim_start_ns, lim_start_r;
always @(posedge clk) lim_start_r <= #TCQ lim_start_ns;
output lim_start;
assign lim_start = lim_start_r;
reg complex_oclkdelay_calib_done_ns, complex_oclkdelay_calib_done_r;
always @(posedge clk) complex_oclkdelay_calib_done_r <= #TCQ complex_oclkdelay_calib_done_ns;
output complex_oclkdelay_calib_done;
assign complex_oclkdelay_calib_done = complex_oclkdelay_calib_done_r;
reg oclkdelay_calib_done_ns, oclkdelay_calib_done_r;
always @(posedge clk) oclkdelay_calib_done_r <= #TCQ oclkdelay_calib_done_ns;
output oclkdelay_calib_done;
assign oclkdelay_calib_done = oclkdelay_calib_done_r;
input phy_rddata_en;
reg prde_r1, prde_r2;
always @(posedge clk) prde_r1 <= #TCQ phy_rddata_en;
always @(posedge clk) prde_r2 <= #TCQ prde_r1;
wire prde = complex_oclkdelay_calib_start ? prde_r2 : phy_rddata_en;
reg phy_rddata_en_r1, phy_rddata_en_r2, phy_rddata_en_r3;
always @(posedge clk) phy_rddata_en_r1 <= #TCQ prde;
always @(posedge clk) phy_rddata_en_r2 <= #TCQ phy_rddata_en_r1;
always @(posedge clk) phy_rddata_en_r3 <= #TCQ phy_rddata_en_r2;
output phy_rddata_en_1, phy_rddata_en_2, phy_rddata_en_3;
assign phy_rddata_en_1 = phy_rddata_en_r1;
assign phy_rddata_en_2 = phy_rddata_en_r2;
assign phy_rddata_en_3 = phy_rddata_en_r3;
input [8:0] po_counter_read_val;
reg ocd_cntlr2stg2_dec_r;
output ocd_cntlr2stg2_dec;
assign ocd_cntlr2stg2_dec = ocd_cntlr2stg2_dec_r;
input po_rdy;
reg [3:0] po_rd_wait_ns, po_rd_wait_r;
always @(posedge clk) po_rd_wait_r <= #TCQ po_rd_wait_ns;
reg [DQS_CNT_WIDTH-1:0] byte_ns, byte_r;
always @(posedge clk) byte_r <= #TCQ byte_ns;
output [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt;
assign oclkdelay_calib_cnt = {1'b0, byte_r};
reg reset_scan_ns, reset_scan_r;
always @(posedge clk) reset_scan_r <= #TCQ reset_scan_ns;
output reset_scan;
assign reset_scan = reset_scan_r;
input scan_done;
reg [2:0] sm_ns, sm_r;
always @(posedge clk) sm_r <= #TCQ sm_ns;
// Primary state machine.
always @(*) begin
// Default next state assignments.
byte_ns = byte_r;
complex_wrlvl_final_ns = complex_wrlvl_final_r;
lim_start_ns = lim_start_r;
oclkdelay_calib_done_ns = oclkdelay_calib_done_r;
complex_oclkdelay_calib_done_ns = complex_oclkdelay_calib_done_r;
ocd_cntlr2stg2_dec_r = 1'b0;
po_rd_wait_ns = po_rd_wait_r;
if (|po_rd_wait_r) po_rd_wait_ns = po_rd_wait_r - 4'b1;
reset_scan_ns = reset_scan_r;
wrlvl_final_ns = wrlvl_final_r;
sm_ns = sm_r;
ocd_prech_req_ns= 1'b0;
if (rst == 1'b1) begin
// RESET next states
complex_oclkdelay_calib_done_ns = 1'b0;
complex_wrlvl_final_ns = 1'b0;
sm_ns = /*AK("READY")*/3'd0;
lim_start_ns = 1'b0;
oclkdelay_calib_done_ns = 1'b0;
reset_scan_ns = 1'b1;
wrlvl_final_ns = 1'b0;
end else
// State based actions and next states.
case (sm_r)
/*AL("READY")*/3'd0: begin
byte_ns = {DQS_CNT_WIDTH{1'b0}};
if (oclkdelay_calib_start && ~oclkdelay_calib_done_r ||
complex_oclkdelay_calib_start && ~complex_oclkdelay_calib_done_r)
begin
sm_ns = /*AK("LIMIT_START")*/3'd1;
lim_start_ns = 1'b1;
end
end
/*AL("LIMIT_START")*/3'd1:
sm_ns = /*AK("LIMIT_WAIT")*/3'd2;
/*AL("LIMIT_WAIT")*/3'd2:begin
if (lim_done) begin
lim_start_ns = 1'b0;
sm_ns = /*AK("SCAN")*/3'd3;
reset_scan_ns = 1'b0;
end
end
/*AL("SCAN")*/3'd3:begin
if (scan_done) begin
reset_scan_ns = 1'b1;
sm_ns = /*AK("COMPUTE")*/3'd4;
end
end
/*AL("COMPUTE")*/3'd4:begin
sm_ns = /*AK("PRECHARGE")*/3'd5;
ocd_prech_req_ns = 1'b1;
end
/*AL("PRECHARGE")*/3'd5:begin
if (prech_done) sm_ns = /*AK("DONE")*/3'd6;
end
/*AL("DONE")*/3'd6:begin
byte_ns = byte_r + ONE[DQS_CNT_WIDTH-1:0];
if ({1'b0, byte_r} == DQS_WIDTH[DQS_CNT_WIDTH:0] - ONE[DQS_WIDTH:0]) begin
byte_ns = {DQS_CNT_WIDTH{1'b0}};
po_rd_wait_ns = 4'd8;
sm_ns = /*AK("STG2_2_ZERO")*/3'd7;
end else begin
sm_ns = /*AK("LIMIT_START")*/3'd1;
lim_start_ns = 1'b1;
end
end
/*AL("STG2_2_ZERO")*/3'd7:
if (~|po_rd_wait_r && po_rdy)
if (|po_counter_read_val[5:0]) ocd_cntlr2stg2_dec_r = 1'b1;
else begin
if ({1'b0, byte_r} == DQS_WIDTH[DQS_CNT_WIDTH:0] - ONE[DQS_WIDTH:0]) begin
sm_ns = /*AK("READY")*/3'd0;
oclkdelay_calib_done_ns= 1'b1;
wrlvl_final_ns = 1'b1;
if (complex_oclkdelay_calib_start) begin
complex_oclkdelay_calib_done_ns = 1'b1;
complex_wrlvl_final_ns = 1'b1;
end
end else begin
byte_ns = byte_r + ONE[DQS_CNT_WIDTH-1:0];
po_rd_wait_ns = 4'd8;
end
end // else: !if(|po_counter_read_val[5:0])
endcase // case (sm_r)
end // always @ begin
endmodule // mig_7series_v4_0_ddr_phy_ocd_cntlr
// Local Variables:
// verilog-autolabel-prefix: "3'd"
// End:
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// This is a single sample interpolator.
module cf_ddsv_intp_1 (
// data_s0 = delayed(data_a);
// data_s1 = scale_a * data_a + scale_b * data_b;
clk,
data_a,
data_b,
scale_a,
scale_b,
data_s0,
data_s1);
// data_s0 = delayed(data_a);
// data_s1 = scale_a * data_a + scale_b * data_b;
input clk;
input [15:0] data_a;
input [15:0] data_b;
input [15:0] scale_a;
input [15:0] scale_b;
output [15:0] data_s0;
output [15:0] data_s1;
reg [15:0] data_a_delay = 'd0;
reg [15:0] data_p = 'd0;
reg [15:0] data_s0 = 'd0;
reg [15:0] data_s1 = 'd0;
wire [15:0] data_a_p_s;
wire [15:0] data_b_p_s;
wire [15:0] data_a_delay_s;
// output registers (sum of products)
always @(posedge clk) begin
data_a_delay <= data_a_delay_s;
data_p <= data_a_p_s + data_b_p_s;
data_s0 <= data_a_delay;
data_s1 <= data_p;
end
// product term 1, scale_a * data_a;
cf_muls #(.DELAY_DATA_WIDTH(16)) i_mul_a (
.clk (clk),
.data_a (data_a),
.data_b (scale_a),
.data_p (data_a_p_s),
.ddata_in (data_a),
.ddata_out (data_a_delay_s));
// product term 2, scale_b * data_b;
cf_muls #(.DELAY_DATA_WIDTH(1)) i_mul_b (
.clk (clk),
.data_a (data_b),
.data_b (scale_b),
.data_p (data_b_p_s),
.ddata_in (1'b0),
.ddata_out ());
endmodule
// ***************************************************************************
// ***************************************************************************
|
/*
Copyright 2010 David Fritz, Brian Gordon, Wira Mulia
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
fritz
generic 8kb block ram. taken from the xilinx xst style guide for generating inferred rams.
*/
module inferred_ram(clka, clkb, ena, enb, wea, addra, addrb, dia, doa, dob);
input clka, clkb;
input wea;
input ena, enb;
input [10:0] addra, addrb;
input [31:0] dia;
output reg [31:0] doa, dob;
reg [31:0] RAM [2047:0];
always @(posedge clka) begin
if (ena) begin
if (wea) begin
RAM[addra] <= dia;
$display("RAM: %x written to %x", dia, addra);
end
doa <= RAM[addra];
end
end
always @(posedge clkb) begin
if (enb) begin
dob <= RAM[addrb];
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09.10.2016 17:20:34
// Design Name:
// Module Name: fifo_testbench
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module fifo_testbench
(
input wire enable,
input wire clear,
output wire fifo_ready,
input wire push_clock,
input wire pop_clock,
input wire [7 : 0] in_data,
output wire [7 : 0] out_data,
output wire popped_last,
output wire pushed_last
);
//
fifo #(.FIFO_SIZE(3), .DATA_WIDTH(8)) simple_fifo (.enable(enable), .clear(clear), .fifo_ready(fifo_ready),
.push_clock(push_clock), .pop_clock(pop_clock),
.in_data(in_data), .out_data(out_data),
.popped_last(popped_last), .pushed_last(pushed_last));
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: rxc_engine_classic.v
// Version: 1.0
// Verilog Standard: Verilog-2001
// Description: The RXC Engine (Ultrascale) takes a single stream of
// AXI packets and provides the completion packets on the RXC Interface.
// This Engine is capable of operating at "line rate".
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "trellis.vh"
`include "ultrascale.vh"
module rxc_engine_ultrascale
#(parameter C_PCI_DATA_WIDTH = 128,
parameter C_RX_PIPELINE_DEPTH=10,
// Number of data pipeline registers for metadata and data stages
parameter C_RX_META_STAGES = 0,
parameter C_RX_DATA_STAGES = 1)
(// Interface: Clocks
input CLK,
// Interface: Resets
input RST_BUS, // Replacement for generic RST_IN
input RST_LOGIC, // Addition for RIFFA_RST
output DONE_RXC_RST,
// Interface: RC
input M_AXIS_RC_TVALID,
input M_AXIS_RC_TLAST,
input [C_PCI_DATA_WIDTH-1:0] M_AXIS_RC_TDATA,
input [(C_PCI_DATA_WIDTH/32)-1:0] M_AXIS_RC_TKEEP,
input [`SIG_RC_TUSER_W-1:0] M_AXIS_RC_TUSER,
output M_AXIS_RC_TREADY,
// Interface: RXC Engine
output [C_PCI_DATA_WIDTH-1:0] RXC_DATA,
output RXC_DATA_VALID,
output [(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_WORD_ENABLE,
output RXC_DATA_START_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_START_OFFSET,
output RXC_DATA_END_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_END_OFFSET,
output [`SIG_LBE_W-1:0] RXC_META_LDWBE,
output [`SIG_FBE_W-1:0] RXC_META_FDWBE,
output [`SIG_TAG_W-1:0] RXC_META_TAG,
output [`SIG_LOWADDR_W-1:0] RXC_META_ADDR,
output [`SIG_TYPE_W-1:0] RXC_META_TYPE,
output [`SIG_LEN_W-1:0] RXC_META_LENGTH,
output [`SIG_BYTECNT_W-1:0] RXC_META_BYTES_REMAINING,
output [`SIG_CPLID_W-1:0] RXC_META_COMPLETER_ID,
output RXC_META_EP
);
// Width of the Byte Enable Shift register
localparam C_RX_BE_W = (`SIG_FBE_W + `SIG_LBE_W);
localparam C_RX_INPUT_STAGES = 0;
localparam C_RX_OUTPUT_STAGES = 2; // Should always be at least one
localparam C_RX_COMPUTATION_STAGES = 1;
localparam C_TOTAL_STAGES = C_RX_COMPUTATION_STAGES + C_RX_OUTPUT_STAGES + C_RX_INPUT_STAGES;
// CYCLE = LOW ORDER BIT (INDEX) / C_PCI_DATA_WIDTH
localparam C_RX_METADW0_CYCLE = (`UPKT_RXC_METADW0_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
localparam C_RX_METADW1_CYCLE = (`UPKT_RXC_METADW1_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
localparam C_RX_METADW2_CYCLE = (`UPKT_RXC_METADW2_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
localparam C_RX_PAYLOAD_CYCLE = (`UPKT_RXC_PAYLOAD_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
localparam C_RX_BE_CYCLE = C_RX_INPUT_STAGES; // Available on the first cycle (as per the spec)
localparam C_RX_METADW0_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`UPKT_RXC_METADW0_I%C_PCI_DATA_WIDTH);
localparam C_RX_METADW1_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`UPKT_RXC_METADW1_I%C_PCI_DATA_WIDTH);
localparam C_RX_METADW2_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`UPKT_RXC_METADW2_I%C_PCI_DATA_WIDTH);
localparam C_RX_BE_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES;
// Mask width of the calculated SOF/EOF fields
localparam C_OFFSET_WIDTH = clog2(C_PCI_DATA_WIDTH/32);
wire wMAxisRcSop;
wire wMAxisRcTlast;
wire [C_RX_PIPELINE_DEPTH:0] wRxSrSop;
wire [C_RX_PIPELINE_DEPTH:0] wRxSrEop;
wire [C_RX_PIPELINE_DEPTH:0] wRxSrDataValid;
wire [(C_RX_PIPELINE_DEPTH+1)*C_RX_BE_W-1:0] wRxSrBe;
wire [(C_RX_PIPELINE_DEPTH+1)*C_PCI_DATA_WIDTH-1:0] wRxSrData;
wire wRxcDataValid;
wire wRxcDataReady; // Pinned High
wire [(C_PCI_DATA_WIDTH/32)-1:0] wRxcDataWordEnable;
wire wRxcDataEndFlag;
wire [clog2(C_PCI_DATA_WIDTH/32)-1:0] wRxcDataEndOffset;
wire wRxcDataStartFlag;
wire [clog2(C_PCI_DATA_WIDTH/32)-1:0] wRxcDataStartOffset;
wire [`SIG_BYTECNT_W-1:0] wRxcMetaBytesRemaining;
wire [`SIG_CPLID_W-1:0] wRxcMetaCompleterId;
wire [`UPKT_RXC_MAXHDR_W-1:0] wRxcHdr;
wire [`SIG_TYPE_W-1:0] wRxcType;
wire [`SIG_BARDECODE_W-1:0] wRxcBarDecoded;
wire [`UPKT_RXC_MAXHDR_W-1:0] wHdr;
wire [`SIG_TYPE_W-1:0] wType;
wire wHasPayload;
wire _wEndFlag;
wire wEndFlag;
wire wEndFlagLastCycle;
wire [clog2(C_PCI_DATA_WIDTH/32)-1:0] wEndOffset;
wire [(C_PCI_DATA_WIDTH/32)-1:0] wEndMask;
wire _wStartFlag;
wire wStartFlag;
wire [1:0] wStartFlags;
wire [clog2(C_PCI_DATA_WIDTH/32)-1:0] wStartOffset;
wire [(C_PCI_DATA_WIDTH/32)-1:0] wStartMask;
wire [C_OFFSET_WIDTH-1:0] wOffsetMask;
reg rValid,_rValid;
reg rRST;
assign DONE_RXC_RST = ~rRST;
assign wMAxisRcSop = M_AXIS_RC_TUSER[`UPKT_RC_TUSER_SOP_I];
assign wMAxisRcTlast = M_AXIS_RC_TLAST;
// We assert the end flag on the last cycle of a packet, however on single
// cycle packets we need to check that there wasn't an end flag last cycle
// (because wStartFlag will take priority when setting rValid) so we can
// deassert rValid if necessary.
assign wEndFlag = wRxSrEop[C_RX_INPUT_STAGES + C_RX_COMPUTATION_STAGES];
assign wEndFlagLastCycle = wRxSrEop[C_RX_INPUT_STAGES + C_RX_COMPUTATION_STAGES + 1];
/* verilator lint_off WIDTH */
assign wStartOffset = 3;
assign wEndOffset = wHdr[`UPKT_RXC_LENGTH_I +: C_OFFSET_WIDTH] + ((`UPKT_RXC_MAXHDR_W-32)/32);
/* verilator lint_on WIDTH */
// Output assignments. See the header file derived from the user
// guide for indices.
assign RXC_META_LENGTH = wRxcHdr[`UPKT_RXC_LENGTH_I+:`SIG_LEN_W];
//assign RXC_META_ATTR = wRxcHdr[`UPKT_RXC_ATTR_R];
//assign RXC_META_TC = wRxcHdr[`UPKT_RXC_TC_R];
assign RXC_META_TAG = wRxcHdr[`UPKT_RXC_TAG_R];
assign RXC_META_FDWBE = 0;// TODO: Remove (use addr)
assign RXC_META_LDWBE = 0;// TODO: Remove (use addr)
assign RXC_META_ADDR = wRxcHdr[(`UPKT_RXC_ADDRLOW_I) +: `SIG_LOWADDR_W];
assign RXC_DATA_START_FLAG = wRxcDataStartFlag;
assign RXC_DATA_START_OFFSET = {C_PCI_DATA_WIDTH > 64, 1'b1};
assign RXC_DATA_END_FLAG = wRxcDataEndFlag;
assign RXC_DATA_END_OFFSET = wRxcDataEndOffset;
assign RXC_DATA_VALID = wRxcDataValid;
assign RXC_DATA = wRxSrData[(C_TOTAL_STAGES)*C_PCI_DATA_WIDTH +: C_PCI_DATA_WIDTH];
assign RXC_META_TYPE = wRxcType;
assign RXC_META_BYTES_REMAINING = wRxcHdr[`UPKT_RXC_BYTECNT_I +: `SIG_BYTECNT_W];
assign RXC_META_COMPLETER_ID = wRxcHdr[`UPKT_RXC_CPLID_R];
assign RXC_META_EP = wRxcHdr[`UPKT_RXC_EP_R];
assign M_AXIS_RC_TREADY = 1'b1;
assign _wEndFlag = wRxSrEop[C_RX_INPUT_STAGES];
assign wEndFlag = wRxSrEop[C_RX_INPUT_STAGES+1];
assign _wStartFlag = wStartFlags != 0;
assign wType = (wHasPayload)? `TRLS_CPL_WD: `TRLS_CPL_ND;
generate
if(C_PCI_DATA_WIDTH == 64) begin
assign wStartFlags[0] = 0;
assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES + 1];
//assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES + 1] & wRxSrEop[C_RX_INPUT_STAGES]; // No Payload
end else if (C_PCI_DATA_WIDTH == 128) begin
assign wStartFlags[1] = 0;
assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES];
end else begin // 256
assign wStartFlags[1] = 0;
assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES];
end // else: !if(C_PCI_DATA_WIDTH == 128)
endgenerate
always @(*) begin
_rValid = rValid;
if(_wStartFlag) begin
_rValid = 1'b1;
end else if (wEndFlag) begin
_rValid = 1'b0;
end
end
always @(posedge CLK) begin
if(rRST) begin
rValid <= 1'b0;
end else begin
rValid <= _rValid;
end
end
always @(posedge CLK) begin
rRST <= RST_BUS | RST_LOGIC;
end
register
#(// Parameters
.C_WIDTH (1),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
start_flag_register
(// Outputs
.RD_DATA (wStartFlag),
// Inputs
.WR_DATA (_wStartFlag),
.WR_EN (1),
.RST_IN (0),
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(// Parameters
.C_WIDTH (32),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
meta_DW2_register
(// Outputs
.RD_DATA (wHdr[95:64]),
// Inputs
.WR_DATA (wRxSrData[C_RX_METADW2_INDEX +: 32]),
.WR_EN (wRxSrSop[C_RX_METADW2_CYCLE]),
.RST_IN (0),
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(// Parameters
.C_WIDTH (32 + 1),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
meta_DW1_register
(// Outputs
.RD_DATA ({wHdr[63:32],wHasPayload}),
// Inputs
.WR_DATA ({wRxSrData[C_RX_METADW1_INDEX +: 32],
wRxSrData[C_RX_METADW1_INDEX +: `UPKT_LEN_W] != 0}),
.WR_EN (wRxSrSop[C_RX_METADW1_CYCLE]),
.RST_IN (0),
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(// Parameters
.C_WIDTH (32),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
metadata_DW0_register
(// Outputs
.RD_DATA (wHdr[31:0]),
// Inputs
.WR_DATA (wRxSrData[C_RX_METADW0_INDEX +: 32]),
.WR_EN (wRxSrSop[C_RX_METADW0_CYCLE]),
.RST_IN (0),
/*AUTOINST*/
// Inputs
.CLK (CLK));
// Shift register for input data with output taps for each delayed
// cycle.
shiftreg
#(// Parameters
.C_DEPTH (C_RX_PIPELINE_DEPTH),
.C_WIDTH (C_PCI_DATA_WIDTH),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
data_shiftreg_inst
(// Outputs
.RD_DATA (wRxSrData),
// Inputs
.WR_DATA (M_AXIS_RC_TDATA),
.RST_IN (0),
/*AUTOINST*/
// Inputs
.CLK (CLK));
// Start Flag Shift Register. Data enables are derived from the
// taps on this shift register.
shiftreg
#(// Parameters
.C_DEPTH (C_RX_PIPELINE_DEPTH),
.C_WIDTH (1'b1),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
sop_shiftreg_inst
(// Outputs
.RD_DATA (wRxSrSop),
// Inputs
.WR_DATA (wMAxisRcSop & M_AXIS_RC_TVALID),
.RST_IN (0),
/*AUTOINST*/
// Inputs
.CLK (CLK));
// End Flag Shift Register.
shiftreg
#(// Parameters
.C_DEPTH (C_RX_PIPELINE_DEPTH),
.C_WIDTH (1'b1),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
eop_shiftreg_inst
(// Outputs
.RD_DATA (wRxSrEop),
// Inputs
.WR_DATA (wMAxisRcTlast),
.RST_IN (0),
/*AUTOINST*/
// Inputs
.CLK (CLK));
// Data Valid Shift Register. Data enables are derived from the
// taps on this shift register.
shiftreg
#(// Parameters
.C_DEPTH (C_RX_PIPELINE_DEPTH),
.C_WIDTH (1),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
valid_shiftreg_inst
(// Outputs
.RD_DATA (wRxSrDataValid),
// Inputs
.WR_DATA (M_AXIS_RC_TVALID),
.RST_IN (rRST),
/*AUTOINST*/
// Inputs
.CLK (CLK));
assign wStartMask = {C_PCI_DATA_WIDTH/32{1'b1}} << ({C_OFFSET_WIDTH{wStartFlag}}& wStartOffset[C_OFFSET_WIDTH-1:0]);
offset_to_mask
#(// Parameters
.C_MASK_SWAP (0),
.C_MASK_WIDTH (C_PCI_DATA_WIDTH/32)
/*AUTOINSTPARAM*/)
o2m_ef
(// Outputs
.MASK (wEndMask),
// Inputs
.OFFSET_ENABLE (wEndFlag),
.OFFSET (wEndOffset)
/*AUTOINST*/);
generate
if(C_RX_OUTPUT_STAGES == 0) begin
assign RXC_DATA_WORD_ENABLE = {wEndMask & wStartMask} & {C_PCI_DATA_WIDTH/32{~rValid | ~wHasPayload}};
end else begin
register
#(// Parameters
.C_WIDTH (C_PCI_DATA_WIDTH/32),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
dw_enable
(// Outputs
.RD_DATA (wRxcDataWordEnable),
// Inputs
.RST_IN (~rValid | ~wHasPayload),
.WR_DATA (wEndMask & wStartMask),
.WR_EN (1),
/*AUTOINST*/
// Inputs
.CLK (CLK));
pipeline
#(
// Parameters
.C_DEPTH (C_RX_OUTPUT_STAGES-1),
.C_WIDTH (C_PCI_DATA_WIDTH/32),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
dw_pipeline
(// Outputs
.WR_DATA_READY (), // Pinned to 1
.RD_DATA (RXC_DATA_WORD_ENABLE),
.RD_DATA_VALID (),
// Inputs
.WR_DATA (wRxcDataWordEnable),
.WR_DATA_VALID (1),
.RD_DATA_READY (1'b1),
.RST_IN (0),
/*AUTOINST*/
// Inputs
.CLK (CLK));
end
endgenerate
// Shift register for input data with output taps for each delayed
// cycle.
pipeline
#(
// Parameters
.C_DEPTH (C_RX_OUTPUT_STAGES),
.C_WIDTH (`UPKT_RXC_MAXHDR_W +
2*(1 + clog2(C_PCI_DATA_WIDTH/32))+`SIG_TYPE_W),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
output_pipeline
(
// Outputs
.WR_DATA_READY (), // Pinned to 1
.RD_DATA ({wRxcHdr, wRxcDataStartFlag,
wRxcDataStartOffset,wRxcDataEndFlag,
wRxcDataEndOffset,wRxcType}),
.RD_DATA_VALID (wRxcDataValid),
// Inputs
.WR_DATA ({wHdr,wStartFlag,
wStartOffset[C_OFFSET_WIDTH-1:0],
wEndFlag,wEndOffset[C_OFFSET_WIDTH-1:0],wType}),
.WR_DATA_VALID (rValid),
.RD_DATA_READY (1'b1),
.RST_IN (rRST),
/*AUTOINST*/
// Inputs
.CLK (CLK));
endmodule
// Local Variables:
// verilog-library-directories:("." "../../../common/")
// End:
|
// only used for synthesis
`include "~/ee577b/syn/src/control.h"
module umult8(reg_A, reg_B, result, ctrl_ww);
// INPUTS
input [0:127] reg_A, reg_B;
input [0:1] ctrl_ww;
// OUTPUTS
output [0:127] result;
// REGISTERS
reg [0:15] p_pdt8a, p_pdt8a2;
reg [0:15] p_pdt8b, p_pdt8b2;
reg [0:15] p_pdt8c, p_pdt8c2;
reg [0:15] p_pdt8d, p_pdt8d2;
reg [0:15] p_pdt8e, p_pdt8e2;
reg [0:15] p_pdt8f, p_pdt8f2;
reg [0:15] p_pdt8g, p_pdt8g2;
reg [0:15] p_pdt8h, p_pdt8h2;
reg [0:31] p_pdt16a, p_pdt16a2;
reg [0:31] p_pdt16b, p_pdt16b2;
reg [0:31] p_pdt16c, p_pdt16c2;
reg [0:31] p_pdt16d, p_pdt16d2;
reg [0:127] p_pdt;
reg [0:127] result;
// INTEGERS (contols for loops)
integer i;
always @ (reg_A or reg_B or ctrl_ww)
begin
// reg_B
// x reg_A
// -------
// result
p_pdt8a=16'b0;
p_pdt8a2=16'b0;
p_pdt8b=16'b0;
p_pdt8b2=16'b0;
p_pdt8c=16'b0;
p_pdt8c2=16'b0;
p_pdt8d=16'b0;
p_pdt8d2=16'b0;
p_pdt8e=16'b0;
p_pdt8e2=16'b0;
p_pdt8f=16'b0;
p_pdt8f2=16'b0;
p_pdt8g=16'b0;
p_pdt8g2=16'b0;
p_pdt8h=16'b0;
p_pdt8h2=16'b0;
p_pdt16a=32'b0;
p_pdt16a2=32'b0;
p_pdt16b=32'b0;
p_pdt16b2=32'b0;
p_pdt16c=32'b0;
p_pdt16c2=32'b0;
p_pdt16d=32'b0;
p_pdt16d2=32'b0;
p_pdt=128'b0;
case(ctrl_ww)
(`w8+2'b1):
begin
// 1st even byte
// extend operand B
p_pdt8a2={{8{1'b0}},reg_B[0+(16*0):7+(16*0)]};
// extend operand A
p_pdt8a={{8{1'b0}},reg_A[0+(16*0):7+(16*0)]};
// i loops through each bit to compute sum of partial products
for (i=15; i>7; i=i-1)
p_pdt[0+(16*0):15+(16*0)]=p_pdt[0+(16*0):15+(16*0)]
+ (p_pdt8a[i]?(p_pdt8a2<<(8'd15-i)):16'b0);
// 2nd even byte
// extend operand B
p_pdt8b2={{8{1'b0}},reg_B[0+(16*1):7+(16*1)]};
// extend operand A
p_pdt8b={{8{1'b0}},reg_A[0+(16*1):7+(16*1)]};
// i loops through each bit to compute sum of partial products
for (i=15; i>7; i=i-1)
p_pdt[0+(16*1):15+(16*1)]=p_pdt[0+(16*1):15+(16*1)]
+ (p_pdt8b[i]?(p_pdt8b2<<(8'd15-i)):16'b0);
// 3rd even byte
// extend operand B
p_pdt8c2={{8{1'b0}},reg_B[0+(16*2):7+(16*2)]};
// extend operand A
p_pdt8c={{8{1'b0}},reg_A[0+(16*2):7+(16*2)]};
// i loops through each bit to compute sum of partial products
for (i=15; i>7; i=i-1)
p_pdt[0+(16*2):15+(16*2)]=p_pdt[0+(16*2):15+(16*2)]
+ (p_pdt8c[i]?(p_pdt8c2<<(8'd15-i)):16'b0);
// 4th even byte
// extend operand B
p_pdt8d2={{8{1'b0}},reg_B[0+(16*3):7+(16*3)]};
// extend operand A
p_pdt8d={{8{1'b0}},reg_A[0+(16*3):7+(16*3)]};
// i loops through each bit to compute sum of partial products
for (i=15; i>7; i=i-1)
p_pdt[0+(16*3):15+(16*3)]=p_pdt[0+(16*3):15+(16*3)]
+ (p_pdt8d[i]?(p_pdt8d2<<(8'd15-i)):16'b0);
// 5th even byte
// extend operand B
p_pdt8e2={{8{1'b0}},reg_B[0+(16*4):7+(16*4)]};
// extend operand A
p_pdt8e={{8{1'b0}},reg_A[0+(16*4):7+(16*4)]};
// i loops through each bit to compute sum of partial products
for (i=15; i>7; i=i-1)
p_pdt[0+(16*4):15+(16*4)]=p_pdt[0+(16*4):15+(16*4)]
+ (p_pdt8e[i]?(p_pdt8e2<<(8'd15-i)):16'b0);
// 6th even byte
// extend operand B
p_pdt8f2={{8{1'b0}},reg_B[0+(16*5):7+(16*5)]};
// extend operand A
p_pdt8f={{8{1'b0}},reg_A[0+(16*5):7+(16*5)]};
// i loops through each bit to compute sum of partial products
for (i=15; i>7; i=i-1)
p_pdt[0+(16*5):15+(16*5)]=p_pdt[0+(16*5):15+(16*5)]
+ (p_pdt8f[i]?(p_pdt8f2<<(8'd15-i)):16'b0);
// 7th even byte
// extend operand B
p_pdt8g2={{8{1'b0}},reg_B[0+(16*6):7+(16*6)]};
// extend operand A
p_pdt8g={{8{1'b0}},reg_A[0+(16*6):7+(16*6)]};
// i loops through each bit to compute sum of partial products
for (i=15; i>7; i=i-1)
p_pdt[0+(16*6):15+(16*6)]=p_pdt[0+(16*6):15+(16*6)]
+ (p_pdt8g[i]?(p_pdt8g2<<(8'd15-i)):16'b0);
// 8th even byte
// extend operand B
p_pdt8h2={{8{1'b0}},reg_B[0+(16*7):7+(16*7)]};
// extend operand A
p_pdt8h={{8{1'b0}},reg_A[0+(16*7):7+(16*7)]};
// i loops through each bit to compute sum of partial products
for (i=15; i>7; i=i-1)
p_pdt[0+(16*7):15+(16*7)]=p_pdt[0+(16*7):15+(16*7)]
+ (p_pdt8h[i]?(p_pdt8h2<<(8'd15-i)):16'b0);
result<=p_pdt;
end // case (`w8+2'b1)
(`w16+2'b1):
begin
// 1st word
// extend operand B
p_pdt16a2={{16{1'b0}},reg_B[0+(32*0):15+(32*0)]};
// extend operand A
p_pdt16a={{16{1'b0}},reg_A[0+(32*0):15+(32*0)]};
// i loops through each bit to compute sum due to partial products
for (i=31; i>15; i=i-1)
p_pdt[0+(32*0):31+(32*0)]=p_pdt[0+(32*0):31+(32*0)]
+ (p_pdt16a[i]?(p_pdt16a2<<(8'd31-i)):32'b0);
// 2nd word
// extend operand B
p_pdt16b2={{16{1'b0}},reg_B[0+(32*1):15+(32*1)]};
// extend operand A
p_pdt16b={{16{1'b0}},reg_A[0+(32*1):15+(32*1)]};
// i loops through each bit to compute sum due to partial products
for (i=31; i>15; i=i-1)
p_pdt[0+(32*1):31+(32*1)]=p_pdt[0+(32*1):31+(32*1)]
+ (p_pdt16b[i]?(p_pdt16b2<<(8'd31-i)):32'b0);
// 3rd word
// extend operand B
p_pdt16c2={{16{1'b0}},reg_B[0+(32*2):15+(32*2)]};
// extend operand A
p_pdt16c={{16{1'b0}},reg_A[0+(32*2):15+(32*2)]};
// i loops through each bit to compute sum due to partial products
for (i=31; i>15; i=i-1)
p_pdt[0+(32*2):31+(32*2)]=p_pdt[0+(32*2):31+(32*2)]
+ (p_pdt16c[i]?(p_pdt16c2<<(8'd31-i)):32'b0);
// 4th word
// extend operand B
p_pdt16d2={{16{1'b0}},reg_B[0+(32*3):15+(32*3)]};
// extend operand A
p_pdt16d={{16{1'b0}},reg_A[0+(32*3):15+(32*3)]};
// i loops through each bit to compute sum due to partial products
for (i=31; i>15; i=i-1)
p_pdt[0+(32*3):31+(32*3)]=p_pdt[0+(32*3):31+(32*3)]
+ (p_pdt16d[i]?(p_pdt16d2<<(8'd31-i)):32'b0);
result<=p_pdt;
end // case (`w16+2'b1)
default:
begin
result<=128'd0;
end
endcase // case(ctrl_ww)
end
endmodule
/*
// extend operand B
p8b_0={{8{1'b0}},reg_B[0:7]};
// extend operand A
p8a_0={{8{1'b0}},reg_A[0:7]};
// compute sum due to partial products
// not using for loop
// pt=pt+(p8a_0[15]?(p8b_0):16'b0);
// pt=pt+(p8a_0[14]?(p8b_0<<8'd1):16'b0);
// pt=pt+(p8a_0[13]?(p8b_0<<8'd2):16'b0);
// pt=pt+(p8a_0[12]?(p8b_0<<8'd3):16'b0);
// pt=pt+(p8a_0[11]?(p8b_0<<8'd4):16'b0);
// pt=pt+(p8a_0[10]?(p8b_0<<8'd5):16'b0);
// pt=pt+(p8a_0[9]?(p8b_0<<8'd6):16'b0);
// pt=pt+(p8a_0[8]?(p8b_0<<8'd7):16'b0);
// same computation as above, but using for loop
for (i=15; i>7; i=i-1)
begin
pt=pt+(p8a_0[i]?(p8b_0<<(8'd15-i)):16'b0);
end
// store sum as result
result<=pt;
end
*/
|
module ALU
#(
parameter DATA_WIDTH = 32
)(
input [DATA_WIDTH - 1:0] channel_A, channel_B,
output reg [DATA_WIDTH - 1:0] operation_result,
input [3:0] control,
input previous_specreg_carry,
output reg Negative_ALU_flag, Zero_ALU_flag,
output reg Carry_ALU_flag, oVerflow_ALU_flag
);
// Declaration section
wire [DATA_WIDTH - 1:0] channel_B_negative;
wire most_significant_bit, local_overflow, channel_A_msb, channel_B_msb;
reg use_negative_B;
// OVERFLOW Flag calculation
assign most_significant_bit = operation_result[DATA_WIDTH - 1];
assign channel_A_msb = channel_A[DATA_WIDTH -1];
assign channel_B_negative = - channel_B;
assign channel_B_msb = use_negative_B ? channel_B_negative[DATA_WIDTH - 1] :
channel_B[DATA_WIDTH -1];
assign local_overflow = most_significant_bit ? !(channel_A_msb || channel_B_msb) :
channel_A_msb && channel_B_msb;
// ALU Implementation
always @ ( * ) begin
// Default values that might be overriden
Negative_ALU_flag = 0;
Carry_ALU_flag = 0;
oVerflow_ALU_flag = 0;
use_negative_B = 0;
operation_result = 0;
// Controlled operations
case (control)
1: // ADD + previous_specreg_carry
begin
{Carry_ALU_flag, operation_result} = channel_A + channel_B + previous_specreg_carry;
oVerflow_ALU_flag = local_overflow;
Negative_ALU_flag = most_significant_bit;
Zero_ALU_flag = (operation_result == 0);
end
2: // ADD
begin
{Carry_ALU_flag, operation_result} = channel_A + channel_B;
oVerflow_ALU_flag = local_overflow;
Negative_ALU_flag = most_significant_bit;
Zero_ALU_flag = (operation_result == 0);
end
3: // AND
begin
operation_result = channel_A & channel_B;
Negative_ALU_flag = most_significant_bit;
Zero_ALU_flag = (operation_result == 0);
end
4: // BIC
begin
operation_result = channel_A & (~channel_B);
Negative_ALU_flag = most_significant_bit;
Zero_ALU_flag = (operation_result == 0);
end
5: // SUB or CMP
begin
use_negative_B = 1;
{Carry_ALU_flag, operation_result} = channel_A + channel_B_negative;
oVerflow_ALU_flag = local_overflow;
Negative_ALU_flag = most_significant_bit;
Zero_ALU_flag = (operation_result == 0);
end
6: // NEG
begin
{Carry_ALU_flag, operation_result} = - channel_A;
oVerflow_ALU_flag = local_overflow;
Negative_ALU_flag = most_significant_bit;
Zero_ALU_flag = (operation_result == 0);
end
7: // OR
begin
operation_result = channel_A | channel_B;
Negative_ALU_flag = most_significant_bit;
Zero_ALU_flag = (operation_result == 0);
end
8: // SBC
begin
{Carry_ALU_flag, operation_result} = channel_A - channel_B - ~previous_specreg_carry;
oVerflow_ALU_flag = local_overflow;
Negative_ALU_flag = most_significant_bit;
Zero_ALU_flag = (operation_result == 0);
end
9: // MULTIPLY
begin
operation_result = channel_A * channel_B;
Negative_ALU_flag = most_significant_bit;
Zero_ALU_flag = (operation_result == 0);
end
10: // DIV
begin
oVerflow_ALU_flag = (channel_B == 0);
operation_result = (oVerflow_ALU_flag) ? 0 : channel_A / channel_B;
Zero_ALU_flag = (operation_result == 0);
end
11: // MOD
begin
oVerflow_ALU_flag = (channel_B == 0);
operation_result = (oVerflow_ALU_flag) ? 0 : channel_A % channel_B;
Zero_ALU_flag = (operation_result == 0);
end
12: // BarrelShifter
begin
operation_result = channel_B;
Zero_ALU_flag = (operation_result == 0);
end
13: // XOR
begin
operation_result = channel_A ^ channel_B;
Negative_ALU_flag = most_significant_bit;
Zero_ALU_flag = (operation_result == 0);
end
14: // LOGICAL AND
begin
operation_result = channel_A && channel_B;
Negative_ALU_flag = most_significant_bit;
Zero_ALU_flag = (operation_result == 0);
end
15: // Paste Special Register
begin
Negative_ALU_flag = channel_A[3];
Zero_ALU_flag = channel_A[2];
Carry_ALU_flag = channel_A[1];
oVerflow_ALU_flag = channel_A[0];
end
default: // channel_A is OUTPUT
begin
operation_result = channel_A;
Negative_ALU_flag = most_significant_bit;
Zero_ALU_flag = (operation_result == 0);
end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUFKAPWR_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__BUFKAPWR_PP_BLACKBOX_V
/**
* bufkapwr: Buffer on keep-alive power rail.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__bufkapwr (
X ,
A ,
VPWR ,
VGND ,
KAPWR,
VPB ,
VNB
);
output X ;
input A ;
input VPWR ;
input VGND ;
input KAPWR;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUFKAPWR_PP_BLACKBOX_V
|
// 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9
// 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0
//----------------------------------------------------------------------------------------
//
// The MIT License (MIT)
// Copyright (c) 2016 Enrique Sedano ([email protected])
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this
// software and associated documentation files (the "Software"), to deal in the Software
// without restriction, including without limitation the rights to use, copy, modify,
// merge, publish, distribute, sublicense, and/or sell copies of the Software, and to
// permit persons to whom the Software is furnished to do so, subject to the following
// conditions:
//
// The above copyright notice and this permission notice shall be included in all copies
// or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
// PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
// CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
// OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
//
//----------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------
//
// This module is a member of
// ____ __
// _ __/ __ \__ ______/ /_ __
// | | / / /_/ / / / / __ / / / /
// | |/ / _, _/ /_/ / /_/ / /_/ /
// |___/_/ |_|\__,_/\__,_/\__, /
// /____/ v 0.0 - Development
//
// Module: ctrl_top.v
// Version: 1.0
// Description:
// Control unit. Implements the state machine that controls vRudy.
//----------------------------------------------------------------------------------------
module ctrl_top (
//------------------------------
// Top level control signals
//------------------------------
input wire clk,
input wire rst_n,
//------------------------------
// Control inputs
//------------------------------
input wire [1:0] ir,
input wire cond,
//------------------------------
// Control outputs
//------------------------------
output reg ld_ra,
output reg ld_ir,
output reg ld_pc,
output reg ld_rat,
output reg ld_rz,
output reg ld_rn,
output reg pc_at,
output reg [1:0] crf,
output reg erd,
output reg rw,
output reg operate
);
localparam S_FETCH = 3'b000;
localparam S_DECO = 3'b001;
localparam S_LOAD = 3'b010;
localparam S_STORE = 3'b011;
localparam S_ARIT = 3'b100;
localparam S_BRANCH = 3'b101;
// State of the control unit
reg [2:0] state;
reg [2:0] n_state;
//----------------------------------------
// State update
//----------------------------------------
always @(posedge clk, negedge rst_n)
begin
if (rst_n == 1'b0)
state <= S_FETCH;
else
state <= n_state;
end
//----------------------------------------
// Next state and output signals selection
//----------------------------------------
always @(*)
begin
//------------------------------
// Default assignments
//------------------------------
n_state = state;
ld_ra = 1'b0;
ld_ir = 1'b0;
ld_pc = 1'b0;
ld_rat = 1'b0;
ld_rz = 1'b0;
ld_rn = 1'b0;
pc_at = 1'b0;
crf = 2'b00;
erd = 1'b0;
rw = 1'b0;
operate = 1'b0;
//------------------------------
// Values selection
//------------------------------
case (state)
S_FETCH:
begin
n_state = S_DECO;
ld_ir = 1'b1;
ld_pc = 1'b1;
end
S_DECO:
begin
case (ir)
2'b00:
n_state = S_LOAD;
2'b01:
n_state = S_STORE;
2'b10:
if (cond == 1'b0)
n_state = S_FETCH;
else
n_state = S_BRANCH;
2'b11:
n_state = S_ARIT;
endcase
ld_ra = 1'b1;
ld_rat = 1'b1;
crf = 1'b1;
end
S_LOAD:
begin
n_state = S_FETCH;
ld_rz = 1'b1;
ld_rn = 1'b1;
pc_at = 1'b1;
erd = 1'b1;
end
S_STORE:
begin
n_state = S_FETCH;
pc_at = 1'b1;
rw = 1'b1;
end
S_ARIT:
begin
n_state = S_DECO;
ld_ir = 1'b1;
ld_pc = 1'b1;
ld_rz = 1'b1;
ld_rn = 1'b1;
crf = 2'b10;
erd = 1'b1;
operate = 1'b1;
end
S_BRANCH:
begin
n_state = S_DECO;
ld_ir = 1'b1;
ld_pc = 1'b1;
pc_at = 1'b1;
end
endcase
end
endmodule
//----------------------------------------------------------------------------------------
// Trivia: The different versions of the code (except for v 0.0 - Development) will be
// named after notable venues in the Bay Area thrash metal scene. Wikipedia only lists
// seven of those, but I don't really expect to have many more versions than that.
//----------------------------------------------------------------------------------------
// 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9
// 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0
|
//----------------------------------------------------------------------------
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: DE4Gen2x8If128.v
// Version:
// Verilog Standard: Verilog-2001
// Description: Top level module for RIFFA 2.2 reference design for the
// the Altera Stratix IV IP Compiler for PCI Express
// module and the Terasic DE4 Development Board.
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`include "functions.vh"
`include "riffa.vh"
`include "altera.vh"
`timescale 1ps / 1ps
module DE4Gen2x8If128
#(// Number of RIFFA Channels
parameter C_NUM_CHNL = 1,
// Number of PCIe Lanes
parameter C_NUM_LANES = 8,
// Settings from Quartus IP Library
parameter C_PCI_DATA_WIDTH = 128,
parameter C_MAX_PAYLOAD_BYTES = 256,
parameter C_LOG_NUM_TAGS = 5
)
(
input OSC_50_BANK2,
input OSC_50_BANK3,
input OSC_50_BANK4,
input OSC_50_BANK5,
input OSC_50_BANK6,
input PCIE_RESET_N,
input PCIE_REFCLK,
input [C_NUM_LANES-1:0] PCIE_RX_IN,
output [C_NUM_LANES-1:0] PCIE_TX_OUT,
output [7:0] LED
);
// ----------PLL Signals----------
wire clk50;
wire clk125;
wire clk250;
wire locked;
wire inclk0;
// ----------PCIe Core Signals----------
// ----------PCIe Clocks----------
wire pld_clk;
wire reconfig_clk;
wire core_clk_out;
wire fixedclk_serdes;
wire refclk;
wire rc_pll_locked;
wire cal_blk_clk;
// ----------PCIe Resets----------
wire pll_powerdown;
wire reset_status;
wire crst;
wire npor;
wire srst;
wire gxb_powerdown;
// ----------PCIe Transaction layer configuration ----------
wire [ 3: 0] tl_cfg_add;
wire [ 31: 0] tl_cfg_ctl;
wire tl_cfg_ctl_wr;
wire [ 52: 0] tl_cfg_sts;
wire tl_cfg_sts_wr;
wire [ 19: 0] ko_cpl_spc_vc0;
// ----------PCIe Interrupt Interface----------
wire app_int_ack;
wire app_msi_ack;
wire app_int_sts;
wire app_msi_req;
// ----------PCIe Status Signals----------
wire hotrst_exit;
wire l2_exit;
wire dlup_exit;
wire [3:0] lane_act;
wire [4:0] ltssm;
wire pme_to_sr;
wire suc_spd_neg;
// ----------PCIe RX Interface----------
wire rx_st_mask0;
wire [ 7: 0] rx_st_bardec0;
wire [ 15: 0] rx_st_be0;
wire [0:0] rx_st_sop0;
wire [0:0] rx_st_eop0;
wire [0:0] rx_st_err0;
wire [0:0] rx_st_valid0;
wire [0:0] rx_st_empty0;
wire rx_st_ready0;
wire [C_PCI_DATA_WIDTH-1:0] rx_st_data0;
// ----------PCIe TX Interface----------
wire [0:0] tx_st_sop0;
wire [0:0] tx_st_eop0;
wire [0:0] tx_st_err0;
wire [0:0] tx_st_valid0;
wire [0:0] tx_st_empty0;
wire tx_st_ready0;
wire [C_PCI_DATA_WIDTH-1:0] tx_st_data0;
// ----------ALTGX Signals----------
wire busy;
wire busy_altgxb_reconfig;
wire [33:0] reconfig_fromgxb;
wire [3:0] reconfig_togxb;
// ----------Resets ----------
reg [4:0] rPCIRstCtr=0,_rPCIRstCtr=0;
reg [2:0] rRstSync=0,_rRstSync=0;
wire wSyncRst;
always @(*) begin
_rRstSync = {rRstSync[1:0], ~npor};
_rPCIRstCtr = rPCIRstCtr;
if (rRstSync[2]) begin
_rPCIRstCtr = 0;
end else if (~rPCIRstCtr[4]) begin
_rPCIRstCtr = rPCIRstCtr + 1;
end
end
always @(posedge pld_clk) begin
rRstSync <= _rRstSync;
rPCIRstCtr <= _rPCIRstCtr;
end
assign wSyncRst = ~ rPCIRstCtr[4];
assign srst = wSyncRst;
assign crst = wSyncRst;
// ----------PLL assignments----------
assign inclk0 = OSC_50_BANK2;
assign fixedclk_serdes = clk125;
assign reconfig_clk = clk50;
// ----------PCIe Resets----------
assign npor = PCIE_RESET_N;
assign gxb_powerdown = ~ npor;
assign pll_powerdown = ~ npor;
// ----------PCIe Clocks / PLLs----------
assign refclk = PCIE_REFCLK;
assign pld_clk = core_clk_out;
assign cal_blk_clk = reconfig_clk;
// ----------ALTGX----------
assign busy = busy_altgxb_reconfig;
// -------------------- BEGIN ALTERA IP INSTANTIATION --------------------
ALTPLL50I50O125O250O ALTPLL50I50O125O250O_inst
(
// Outputs
.c0 (clk50),
.c1 (clk125),
.c2 (clk250),
.locked (locked),
// Inputs
.inclk0 (inclk0));
ALTGXPCIeGen2x8
altgx_inst
(
// Outputs
.busy (busy),
.reconfig_togxb (reconfig_togxb[3:0]),
// Inputs
.reconfig_clk (reconfig_clk),
.reconfig_fromgxb (reconfig_fromgxb[33:0]));
PCIeGen2x8If128
pcie_inst
(
// Outputs
.app_int_ack (app_int_ack),
.app_msi_ack (app_msi_ack),
.core_clk_out (core_clk_out),
.hotrst_exit (hotrst_exit),
.l2_exit (l2_exit),
.dlup_exit (dlup_exit),
.lane_act (lane_act[3:0]),
.ltssm (ltssm[4:0]),
.rc_pll_locked (rc_pll_locked),
.reconfig_fromgxb (reconfig_fromgxb[33:0]),
.reset_status (reset_status),
.rx_st_bardec0 (rx_st_bardec0[7:0]),
.rx_st_be0 (rx_st_be0[7:0]),
.rx_st_data0 (rx_st_data0[C_PCI_DATA_WIDTH-1:0]),
.rx_st_eop0 (rx_st_eop0),
.rx_st_err0 (rx_st_err0),
.rx_st_sop0 (rx_st_sop0),
.rx_st_empty0 (rx_st_empty0),
.rx_st_valid0 (rx_st_valid0),
.suc_spd_neg (suc_spd_neg),// Gen 2 successful
.tl_cfg_add (tl_cfg_add[3:0]),
.tl_cfg_ctl (tl_cfg_ctl[31:0]),
.tl_cfg_ctl_wr (tl_cfg_ctl_wr),
.tl_cfg_sts (tl_cfg_sts[52:0]),
.tl_cfg_sts_wr (tl_cfg_sts_wr),
.ko_cpl_spc_vc0 (ko_cpl_spc_vc0),
.tx_out0 (PCIE_TX_OUT[0]),
.tx_out1 (PCIE_TX_OUT[1]),
.tx_out2 (PCIE_TX_OUT[2]),
.tx_out3 (PCIE_TX_OUT[3]),
.tx_out4 (PCIE_TX_OUT[4]),
.tx_out5 (PCIE_TX_OUT[5]),
.tx_out6 (PCIE_TX_OUT[6]),
.tx_out7 (PCIE_TX_OUT[7]),
.tx_st_ready0 (tx_st_ready0),
// Inputs
.app_int_sts (app_int_sts),
.app_msi_req (app_msi_req),
.busy_altgxb_reconfig (busy_altgxb_reconfig),
.cal_blk_clk (cal_blk_clk),
.crst (crst),
.fixedclk_serdes (fixedclk_serdes),
.gxb_powerdown (gxb_powerdown),
.pll_powerdown (pll_powerdown),
.npor (npor),
.pld_clk (pld_clk),
.reconfig_clk (reconfig_clk),
.reconfig_togxb (reconfig_togxb[3:0]),
.refclk (refclk),
.rx_in0 (PCIE_RX_IN[0]),
.rx_in1 (PCIE_RX_IN[1]),
.rx_in2 (PCIE_RX_IN[2]),
.rx_in3 (PCIE_RX_IN[3]),
.rx_in4 (PCIE_RX_IN[4]),
.rx_in5 (PCIE_RX_IN[5]),
.rx_in6 (PCIE_RX_IN[6]),
.rx_in7 (PCIE_RX_IN[7]),
.rx_st_ready0 (rx_st_ready0),
.srst (srst),
.tx_st_data0 (tx_st_data0[C_PCI_DATA_WIDTH-1:0]),
.tx_st_eop0 (tx_st_eop0),
.tx_st_err0 (1'b0),
.tx_st_sop0 (tx_st_sop0),
.tx_st_empty0 (tx_st_empty0),
.tx_st_valid0 (tx_st_valid0));
// -------------------- END ALTERA IP INSTANTIATION --------------------
// -------------------- BEGIN RIFFA INSTANTAION --------------------
// ----------RIFFA channel interface----------
wire [C_NUM_CHNL-1:0] chnl_rx_clk;
wire [C_NUM_CHNL-1:0] chnl_rx;
wire [C_NUM_CHNL-1:0] chnl_rx_ack;
wire [C_NUM_CHNL-1:0] chnl_rx_last;
wire [(C_NUM_CHNL*32)-1:0] chnl_rx_len;
wire [(C_NUM_CHNL*31)-1:0] chnl_rx_off;
wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_rx_data;
wire [C_NUM_CHNL-1:0] chnl_rx_data_valid;
wire [C_NUM_CHNL-1:0] chnl_rx_data_ren;
wire [C_NUM_CHNL-1:0] chnl_tx_clk;
wire [C_NUM_CHNL-1:0] chnl_tx;
wire [C_NUM_CHNL-1:0] chnl_tx_ack;
wire [C_NUM_CHNL-1:0] chnl_tx_last;
wire [(C_NUM_CHNL*32)-1:0] chnl_tx_len;
wire [(C_NUM_CHNL*31)-1:0] chnl_tx_off;
wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_tx_data;
wire [C_NUM_CHNL-1:0] chnl_tx_data_valid;
wire [C_NUM_CHNL-1:0] chnl_tx_data_ren;
wire chnl_reset;
wire chnl_clk;
wire rst_out;
assign chnl_clk = pld_clk;
assign chnl_reset = rst_out;
riffa_wrapper_de4
#(/*AUTOINSTPARAM*/
// Parameters
.C_LOG_NUM_TAGS (C_LOG_NUM_TAGS),
.C_NUM_CHNL (C_NUM_CHNL),
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_MAX_PAYLOAD_BYTES (C_MAX_PAYLOAD_BYTES))
riffa
(
// Outputs
.RX_ST_READY (rx_st_ready0),
.TX_ST_DATA (tx_st_data0[C_PCI_DATA_WIDTH-1:0]),
.TX_ST_VALID (tx_st_valid0[0:0]),
.TX_ST_EOP (tx_st_eop0[0:0]),
.TX_ST_SOP (tx_st_sop0[0:0]),
.TX_ST_EMPTY (tx_st_empty0[0:0]),
.APP_MSI_REQ (app_msi_req),
.RST_OUT (rst_out),
.CHNL_RX (chnl_rx[C_NUM_CHNL-1:0]),
.CHNL_RX_LAST (chnl_rx_last[C_NUM_CHNL-1:0]),
.CHNL_RX_LEN (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
.CHNL_RX_OFF (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
.CHNL_RX_DATA (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_RX_DATA_VALID (chnl_rx_data_valid[C_NUM_CHNL-1:0]),
.CHNL_TX_ACK (chnl_tx_ack[C_NUM_CHNL-1:0]),
.CHNL_TX_DATA_REN (chnl_tx_data_ren[C_NUM_CHNL-1:0]),
// Inputs
.RX_ST_DATA (rx_st_data0[C_PCI_DATA_WIDTH-1:0]),
.RX_ST_EOP (rx_st_eop0[0:0]),
.RX_ST_SOP (rx_st_sop0[0:0]),
.RX_ST_VALID (rx_st_valid0[0:0]),
.RX_ST_EMPTY (rx_st_empty0[0:0]),
.TX_ST_READY (tx_st_ready0),
.TL_CFG_CTL (tl_cfg_ctl[`SIG_CFG_CTL_W-1:0]),
.TL_CFG_ADD (tl_cfg_add[`SIG_CFG_ADD_W-1:0]),
.TL_CFG_STS (tl_cfg_sts[`SIG_CFG_STS_W-1:0]),
.KO_CPL_SPC_HEADER (ko_cpl_spc_vc0[7:0]),
.KO_CPL_SPC_DATA (ko_cpl_spc_vc0[19:8]),
.APP_MSI_ACK (app_msi_ack),
.PLD_CLK (pld_clk),
.RESET_STATUS (reset_status),
.CHNL_RX_CLK (chnl_rx_clk[C_NUM_CHNL-1:0]),
.CHNL_RX_ACK (chnl_rx_ack[C_NUM_CHNL-1:0]),
.CHNL_RX_DATA_REN (chnl_rx_data_ren[C_NUM_CHNL-1:0]),
.CHNL_TX_CLK (chnl_tx_clk[C_NUM_CHNL-1:0]),
.CHNL_TX (chnl_tx[C_NUM_CHNL-1:0]),
.CHNL_TX_LAST (chnl_tx_last[C_NUM_CHNL-1:0]),
.CHNL_TX_LEN (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
.CHNL_TX_OFF (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
.CHNL_TX_DATA (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_TX_DATA_VALID (chnl_tx_data_valid[C_NUM_CHNL-1:0]));
// -------------------- END RIFFA INSTANTAION --------------------
// -------------------- BEGIN USER CODE --------------------
genvar i;
generate
for (i = 0; i < C_NUM_CHNL; i = i + 1) begin : test_channels
// Instantiate and assign modules to RIFFA channels. Users should
// replace the chnl_tester instantiation with their own core.
chnl_tester
#(
.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)
)
chnl_tester_i
(
.CLK(chnl_clk),
.RST(chnl_reset), // chnl_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[i]),
.CHNL_RX(chnl_rx[i]),
.CHNL_RX_ACK(chnl_rx_ack[i]),
.CHNL_RX_LAST(chnl_rx_last[i]),
.CHNL_RX_LEN(chnl_rx_len[`SIG_CHNL_LENGTH_W*i +:`SIG_CHNL_LENGTH_W]),
.CHNL_RX_OFF(chnl_rx_off[`SIG_CHNL_OFFSET_W*i +:`SIG_CHNL_OFFSET_W]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*i +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[i]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[i]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[i]),
.CHNL_TX(chnl_tx[i]),
.CHNL_TX_ACK(chnl_tx_ack[i]),
.CHNL_TX_LAST(chnl_tx_last[i]),
.CHNL_TX_LEN(chnl_tx_len[`SIG_CHNL_LENGTH_W*i +:`SIG_CHNL_LENGTH_W]),
.CHNL_TX_OFF(chnl_tx_off[`SIG_CHNL_OFFSET_W*i +:`SIG_CHNL_OFFSET_W]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*i +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[i]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[i])
);
end
endgenerate
// -------------------- END USER CODE --------------------
endmodule // DE4Gen2x8If128
|
// Check the various variable bit selects (LSB > MSB).
module top;
parameter [-4:-1] ap = 4'h1;
parameter [-4:-1] bp = 4'he;
parameter [-3:0] cp = 4'h1;
parameter [-3:0] dp = 4'he;
reg passed;
wire [-4:-1] a = 4'h1;
wire [-4:-1] b = 4'he;
wire [0:0] s0 = 0;
wire [1:0] s1 = 0;
wire [2:0] s2 = 0;
reg [-4:-1] ar = 4'h1;
reg [-4:-1] br = 4'he;
wire [-3:0] c = 4'h1;
wire [-3:0] d = 4'he;
wire [0:0] s3 = 0;
wire [1:0] s4 = 0;
reg [-3:0] cr = 4'h1;
reg [-3:0] dr = 4'he;
wire res_a0 = a[s0];
wire res_b0 = b[s0];
wire res_a1 = a[s1];
wire res_b1 = b[s1];
wire res_a2 = a[s2];
wire res_b2 = b[s2];
wire res_c3 = c[s3];
wire res_d3 = d[s3];
wire res_c4 = c[s4];
wire res_d4 = d[s4];
reg [-4:-1] res_ab;
reg [-3:0] res_cd;
initial begin
#1;
passed = 1'b1;
// Check procedural R-value variable bit selects of a net.
$display("a[s0]: %b", a[s0]);
if (a[s0] !== 1'bx) begin
$display("Failed a[s0], expected 1'bx, got %b", a[s0]);
passed = 1'b0;
end
$display("b[s0]: %b", b[s0]);
if (b[s0] !== 1'bx) begin
$display("Failed b[s0], expected 1'bx, got %b", b[s0]);
passed = 1'b0;
end
$display("a[s1]: %b", a[s1]);
if (a[s1] !== 1'bx) begin
$display("Failed a[s1], expected 1'bx, got %b", a[s1]);
passed = 1'b0;
end
$display("b[s1]: %b", b[s1]);
if (b[s1] !== 1'bx) begin
$display("Failed b[s1], expected 1'bx, got %b", b[s1]);
passed = 1'b0;
end
$display("a[s2]: %b", a[s2]);
if (a[s2] !== 1'bx) begin
$display("Failed a[s2], expected 1'bx, got %b", a[s2]);
passed = 1'b0;
end
$display("b[s2]: %b", b[s2]);
if (b[s2] !== 1'bx) begin
$display("Failed b[s2], expected 1'bx, got %b", b[s2]);
passed = 1'b0;
end
$display("c[s3]: %b", c[s3]);
if (c[s3] !== 1'b1) begin
$display("Failed c[s3], expected 1'b1, got %b", c[s3]);
passed = 1'b0;
end
$display("d[s3]: %b", d[s3]);
if (d[s3] !== 1'b0) begin
$display("Failed d[s3], expected 1'b0, got %b", d[s3]);
passed = 1'b0;
end
$display("c[s4]: %b", c[s4]);
if (c[s4] !== 1'b1) begin
$display("Failed c[s4], expected 1'b1, got %b", c[s4]);
passed = 1'b0;
end
$display("d[s4]: %b", d[s4]);
if (d[s4] !== 1'b0) begin
$display("Failed d[s4], expected 1'b0, got %b", d[s4]);
passed = 1'b0;
end
// Check procedural R-value variable bit selects of a parameter.
$display("ap[s0]: %b", ap[s0]);
if (ap[s0] !== 1'bx) begin
$display("Failed ap[s0], expected 1'bx, got %b", ap[s0]);
passed = 1'b0;
end
$display("bp[s0]: %b", bp[s0]);
if (bp[s0] !== 1'bx) begin
$display("Failed bp[s0], expected 1'bx, got %b", bp[s0]);
passed = 1'b0;
end
$display("ap[s1]: %b", ap[s1]);
if (ap[s1] !== 1'bx) begin
$display("Failed ap[s1], expected 1'bx, got %b", ap[s1]);
passed = 1'b0;
end
$display("bp[s1]: %b", bp[s1]);
if (bp[s1] !== 1'bx) begin
$display("Failed bp[s1], expected 1'bx, got %b", bp[s1]);
passed = 1'b0;
end
$display("ap[s2]: %b", ap[s2]);
if (ap[s2] !== 1'bx) begin
$display("Failed ap[s2], expected 1'bx, got %b", ap[s2]);
passed = 1'b0;
end
$display("bp[s2]: %b", bp[s2]);
if (bp[s2] !== 1'bx) begin
$display("Failed bp[s2], expected 1'bx, got %b", bp[s2]);
passed = 1'b0;
end
$display("cp[s3]: %b", cp[s3]);
if (cp[s3] !== 1'b1) begin
$display("Failed cp[s3], expected 1'b1, got %b", cp[s3]);
passed = 1'b0;
end
$display("dp[s3]: %b", dp[s3]);
if (dp[s3] !== 1'b0) begin
$display("Failed dp[s3], expected 1'b0, got %b", dp[s3]);
passed = 1'b0;
end
$display("cp[s4]: %b", cp[s4]);
if (cp[s4] !== 1'b1) begin
$display("Failed cp[s4], expected 1'b1, got %b", cp[s4]);
passed = 1'b0;
end
$display("dp[s4]: %b", dp[s4]);
if (dp[s4] !== 1'b0) begin
$display("Failed dp[s4], expected 1'b0, got %b", dp[s4]);
passed = 1'b0;
end
// Check procedural R-value variable bit selects of a reg.
$display("ar[s0]: %b", ar[s0]);
if (ar[s0] !== 1'bx) begin
$display("Failed ar[s0], expected 1'bx, got %b", ar[s0]);
passed = 1'b0;
end
$display("br[s0]: %b", br[s0]);
if (br[s0] !== 1'bx) begin
$display("Failed br[s0], expected 1'bx, got %b", br[s0]);
passed = 1'b0;
end
$display("ar[s1]: %b", ar[s1]);
if (ar[s1] !== 1'bx) begin
$display("Failed ar[s1], expected 1'bx, got %b", ar[s1]);
passed = 1'b0;
end
$display("br[s1]: %b", br[s1]);
if (br[s1] !== 1'bx) begin
$display("Failed br[s1], expected 1'bx, got %b", br[s1]);
passed = 1'b0;
end
$display("ar[s2]: %b", ar[s2]);
if (ar[s2] !== 1'bx) begin
$display("Failed ar[s2], expected 1'bx, got %b", ar[s2]);
passed = 1'b0;
end
$display("br[s2]: %b", br[s2]);
if (br[s2] !== 1'bx) begin
$display("Failed br[s2], expected 1'bx, got %b", br[s2]);
passed = 1'b0;
end
$display("cr[s3]: %b", cr[s3]);
if (cr[s3] !== 1'b1) begin
$display("Failed cr[s3], expected 1'b1, got %b", cr[s3]);
passed = 1'b0;
end
$display("dr[s3]: %b", dr[s3]);
if (dr[s3] !== 1'b0) begin
$display("Failed dr[s3], expected 1'b0, got %b", dr[s3]);
passed = 1'b0;
end
$display("cr[s4]: %b", cr[s4]);
if (cr[s4] !== 1'b1) begin
$display("Failed cr[s4], expected 1'b1, got %b", cr[s4]);
passed = 1'b0;
end
$display("dr[s4]: %b", dr[s4]);
if (dr[s4] !== 1'b0) begin
$display("Failed dr[s4], expected 1'b0, got %b", dr[s4]);
passed = 1'b0;
end
// Check continuous assignment R-value variable bit selects.
if (res_a0 !== 1'bx) begin
$display("Failed res_a0, expected 1'bx, got %b", res_a0);
passed = 1'b0;
end
if (res_b0 !== 1'bx) begin
$display("Failed res_b0, expected 1'bx, got %b", res_b0);
passed = 1'b0;
end
if (res_a1 !== 1'bx) begin
$display("Failed res_a1, expected 1'bx, got %b", res_a1);
passed = 1'b0;
end
if (res_b1 !== 1'bx) begin
$display("Failed res_b1, expected 1'bx, got %b", res_b1);
passed = 1'b0;
end
if (res_a2 !== 1'bx) begin
$display("Failed res_a2, expected 1'bx, got %b", res_a2);
passed = 1'b0;
end
if (res_b2 !== 1'bx) begin
$display("Failed res_b2, expected 1'bx, got %b", res_b2);
passed = 1'b0;
end
if (res_c3 !== 1'b1) begin
$display("Failed res_c3, expected 1'b1, got %b", res_c3);
passed = 1'b0;
end
if (res_d3 !== 1'b0) begin
$display("Failed res_d3, expected 1'b0, got %b", res_d3);
passed = 1'b0;
end
if (res_c4 !== 1'b1) begin
$display("Failed res_c4, expected 1'b1, got %b", res_c4);
passed = 1'b0;
end
if (res_d4 !== 1'b0) begin
$display("Failed res_d4, expected 1'b0, got %b", res_d4);
passed = 1'b0;
end
// Check procedural L-value variable bit selects.
res_ab = 4'bxxxx;
res_ab[s0] = 1'b0;
if (res_ab !== 4'bxxxx) begin
$display("Failed res_ab[s0], expected 4'bxxxx, got %b", res_ab);
passed = 1'b0;
end
res_ab = 4'bxxxx;
res_ab[s1] = 1'b0;
if (res_ab !== 4'bxxxx) begin
$display("Failed res_ab[s1], expected 4'bxxxx, got %b", res_ab);
passed = 1'b0;
end
res_ab = 4'bxxxx;
res_ab[s2] = 1'b0;
if (res_ab !== 4'bxxxx) begin
$display("Failed res_ab[s2], expected 4'bxxxx, got %b", res_ab);
passed = 1'b0;
end
res_cd = 4'bxxxx;
res_cd[s3] = 1'b0;
if (res_cd !== 4'bxxx0) begin
$display("Failed res_cd[s3], expected 4'bxxx0, got %b", res_cd);
passed = 1'b0;
end
res_cd = 4'bxxxx;
res_cd[s4] = 1'b0;
if (res_cd !== 4'bxxx0) begin
$display("Failed res_cd[s4], expected 4'bxxx0, got %b", res_cd);
passed = 1'b0;
end
if (passed) $display("Compare tests passed");
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// Top module for HIGHT Crypto Core ////
//// ////
//// This file is part of the HIGHT Crypto Core project ////
//// http://github.com/OpenSoCPlus/hight_crypto_core ////
//// http://www.opencores.org/project,hight ////
//// ////
//// Description ////
//// __description__ ////
//// ////
//// Author(s): ////
//// - JoonSoo Ha, [email protected] ////
//// - Younjoo Kim, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors, OpenSoCPlus and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
module HIGHT_CORE_TOP(
rstn ,
clk ,
i_mk_rdy ,
i_mk ,
i_post_rdy ,
i_op ,
i_text_val ,
i_text_in ,
o_text_done ,
o_text_out ,
o_rdy
);
//=====================================
//
// PARAMETERS
//
//=====================================
//=====================================
//
// I/O PORTS
//
//=====================================
input rstn ;
input clk ;
input i_mk_rdy ;
input[127:0] i_mk ;
input i_post_rdy ;
input i_op ;
input i_text_val ;
input[63:0] i_text_in ;
output o_text_done ;
output[63:0] o_text_out ;
output o_rdy ;
//=====================================
//
// REGISTERS
//
//=====================================
//=====================================
//
// WIRES
//
//=====================================
wire[31:0] w_rnd_key ;
wire[2:0] w_xf_sel ;
wire w_rf_final ;
wire w_key_sel ;
wire[4:0] w_rnd_idx ;
wire w_wf_post_pre ;
//=====================================
//
// MAIN
//
//=====================================
// CYPTO_PATH instance
CRYPTO_PATH u_CRYPTO_PATH(
.rstn ( rstn ) ,
.clk ( clk ) ,
.i_op ( i_op ) ,
.i_wrsk ( w_rnd_key ) ,
.i_text_in ( i_text_in ) ,
.i_xf_sel ( w_xf_sel ) ,
.i_rf_final ( w_rf_final ) ,
.o_text_out ( o_text_out )
);
// KEY_SCHED instance
KEY_SCHED u_KEY_SCHED(
.rstn ( rstn ) ,
.clk ( clk ) ,
.i_mk ( i_mk ) ,
.i_op ( i_op ) ,
.i_key_sel ( w_key_sel ) ,
.i_rnd_idx ( w_rnd_idx ) ,
.i_wf_post_pre ( w_wf_post_pre ) ,
.o_rnd_key ( w_rnd_key )
);
// CONTROL instance
CONTROL u_CONTROL(
.rstn ( rstn ) ,
.clk ( clk ) ,
.i_mk_rdy ( i_mk_rdy ) ,
.i_post_rdy ( i_post_rdy ) ,
.i_text_val ( i_text_val ) ,
.o_rdy ( o_rdy ) ,
.o_text_done ( o_text_done ) ,
.o_xf_sel ( w_xf_sel ) ,
.o_rf_final ( w_rf_final ) ,
.o_key_sel ( w_key_sel ) ,
.o_rnd_idx ( w_rnd_idx ) ,
.o_wf_post_pre ( w_wf_post_pre )
);
endmodule
|
module mux_40xPARAMb_to_1xPARAMb(
out,
in,
select );
parameter WORD_WIDTH = 12;
input[40*WORD_WIDTH-1:0] in;
input[5:0] select;
output[WORD_WIDTH-1:0] out;
reg[WORD_WIDTH-1:0] out;
always @(in or select) begin
casex(select)
6'h00: out = in[1*WORD_WIDTH-1:0*WORD_WIDTH];
6'h01: out = in[2*WORD_WIDTH-1:1*WORD_WIDTH];
6'h02: out = in[3*WORD_WIDTH-1:2*WORD_WIDTH];
6'h03: out = in[4*WORD_WIDTH-1:3*WORD_WIDTH];
6'h04: out = in[5*WORD_WIDTH-1:4*WORD_WIDTH];
6'h05: out = in[6*WORD_WIDTH-1:5*WORD_WIDTH];
6'h06: out = in[7*WORD_WIDTH-1:6*WORD_WIDTH];
6'h07: out = in[8*WORD_WIDTH-1:7*WORD_WIDTH];
6'h08: out = in[9*WORD_WIDTH-1:8*WORD_WIDTH];
6'h09: out = in[10*WORD_WIDTH-1:9*WORD_WIDTH];
6'h0a: out = in[11*WORD_WIDTH-1:10*WORD_WIDTH];
6'h0b: out = in[12*WORD_WIDTH-1:11*WORD_WIDTH];
6'h0c: out = in[13*WORD_WIDTH-1:12*WORD_WIDTH];
6'h0d: out = in[14*WORD_WIDTH-1:13*WORD_WIDTH];
6'h0e: out = in[15*WORD_WIDTH-1:14*WORD_WIDTH];
6'h0f: out = in[16*WORD_WIDTH-1:15*WORD_WIDTH];
6'h10: out = in[17*WORD_WIDTH-1:16*WORD_WIDTH];
6'h11: out = in[18*WORD_WIDTH-1:17*WORD_WIDTH];
6'h12: out = in[19*WORD_WIDTH-1:18*WORD_WIDTH];
6'h13: out = in[20*WORD_WIDTH-1:19*WORD_WIDTH];
6'h14: out = in[21*WORD_WIDTH-1:20*WORD_WIDTH];
6'h15: out = in[22*WORD_WIDTH-1:21*WORD_WIDTH];
6'h16: out = in[23*WORD_WIDTH-1:22*WORD_WIDTH];
6'h17: out = in[24*WORD_WIDTH-1:23*WORD_WIDTH];
6'h18: out = in[25*WORD_WIDTH-1:24*WORD_WIDTH];
6'h19: out = in[26*WORD_WIDTH-1:25*WORD_WIDTH];
6'h1a: out = in[27*WORD_WIDTH-1:26*WORD_WIDTH];
6'h1b: out = in[28*WORD_WIDTH-1:27*WORD_WIDTH];
6'h1c: out = in[29*WORD_WIDTH-1:28*WORD_WIDTH];
6'h1d: out = in[30*WORD_WIDTH-1:29*WORD_WIDTH];
6'h1e: out = in[31*WORD_WIDTH-1:30*WORD_WIDTH];
6'h1f: out = in[32*WORD_WIDTH-1:31*WORD_WIDTH];
6'h20: out = in[33*WORD_WIDTH-1:32*WORD_WIDTH];
6'h21: out = in[34*WORD_WIDTH-1:33*WORD_WIDTH];
6'h22: out = in[35*WORD_WIDTH-1:34*WORD_WIDTH];
6'h23: out = in[36*WORD_WIDTH-1:35*WORD_WIDTH];
6'h24: out = in[37*WORD_WIDTH-1:36*WORD_WIDTH];
6'h25: out = in[38*WORD_WIDTH-1:37*WORD_WIDTH];
6'h26: out = in[39*WORD_WIDTH-1:38*WORD_WIDTH];
6'h27: out = in[40*WORD_WIDTH-1:39*WORD_WIDTH];
default: out = {(WORD_WIDTH){1'bX}};
endcase
end
endmodule
|
//`include"DataPath.v"
//`include"Controller.v"
module CPU(input clk,rst);
wire[1:0] stackContrl,pcContrl;
wire[5:0] cntrlInstruc;
DataPath dp(clk,rst,RdOrR2,AluOrMem,RFWE,MWE,stackContrl,pcContrl,Zero,Cout,cntrlInstruc);
Controller cntrl(clk,rst,RdOrR2,AluOrMem,RFWE,MWE,stackContrl,pcContrl,Zero,Cout,cntrlInstruc);
endmodule
module CPUTB();
initial begin
$dumpfile("CPUTB.vcd");
$dumpvars;
end
//integer outfile,regFile;
integer i,ramOut;
reg clk,rst;
parameter delta = 10;
initial begin clk = 0; forever #delta clk = ~clk; end
CPU UUT(clk,rst);
initial begin
ramOut = $fopen("ramModified.bin") | 1;
//regFile = $fopen("regsOut.bin") | 1;
rst=0;
#1 rst=1;
#(1+delta) rst=0;
for(i=0;i<500;i=i+1)
begin
//#(2*delta) $fdisplay(regFile, "%8d,%8d,%8d,%8d,%8d,%8d,%8d,%8d,%4d",UUT.dp.RF.registers[0],UUT.dp.RF.registers[1],UUT.dp.RF.registers[2],UUT.dp.RF.registers[3],UUT.dp.RF.registers[4],UUT.dp.RF.registers[5],UUT.dp.RF.registers[6],UUT.dp.RF.registers[7],UUT.dp.Alu.Zero);
#(2*delta) $display("%8d,%8d,%8d,%8d,%8d,%8d,%8d,%8d",UUT.dp.RF.registers[0],UUT.dp.RF.registers[1],UUT.dp.RF.registers[2],UUT.dp.RF.registers[3],UUT.dp.RF.registers[4],UUT.dp.RF.registers[5],UUT.dp.RF.registers[6],UUT.dp.RF.registers[7]);
end
for(i=0;i<256;i=i+1)
begin
$fdisplay(ramOut, "%8b", UUT.dp.Mem.data[i]);
end
$finish;
end
endmodule
|
(** * Subtyping_J :サブタイプ *)
(* * Subtyping *)
(* $Date: 2011-05-07 21:28:52 -0400 (Sat, 07 May 2011) $ *)
Require Export MoreStlc_J.
(* ###################################################### *)
(* * Concepts *)
(** * 概念 *)
(* We now turn to the study of _subtyping_, perhaps the most
characteristic feature of the static type systems used by many
recently designed programming languages. *)
(** さて、サブタイプ(_subtyping_)の学習に入ります。
サブタイプはおそらく、近年設計されたプログラミング言語で使われる静的型システムの最も特徴的な機能です。
*)
(* ###################################################### *)
(* ** A Motivating Example *)
(** ** 動機付けのための例 *)
(* In the simply typed lamdba-calculus with records, the term
<<
(\r:{y:Nat}. (r.y)+1) {x=10,y=11}
>>
is not typable: it involves an application of a function that wants
a one-field record to an argument that actually provides two
fields, while the [T_App] rule demands that the domain type of the
function being applied must match the type of the argument
precisely.
But this is silly: we're passing the function a _better_ argument
than it needs! The only thing the body of the function can
possibly do with its record argument [r] is project the field [y]
from it: nothing else is allowed by the type. So the presence or
absence of an extra [x] field should make no difference at all.
So, intuitively, it seems that this function should be applicable
to any record value that has at least a [y] field.
Looking at the same thing from another point of view, a record with
more fields is "at least as good in any context" as one with just a
subset of these fields, in the sense that any value belonging to
the longer record type can be used _safely_ in any context
expecting the shorter record type. If the context expects
something with the shorter type but we actually give it something
with the longer type, nothing bad will happen (formally, the
program will not get stuck).
The general principle at work here is called _subtyping_. We say
that "[S] is a subtype of [T]", informally written [S <: T], if a
value of type [S] can safely be used in any context where a value
of type [T] is expected. The idea of subtyping applies not only to
records, but to all of the type constructors in the language --
functions, pairs, etc. *)
(** レコードを持つ単純型付きラムダ計算では、項
<<
(\r:{y:Nat}. (r.y)+1) {x=10,y=11}
>>
は型付けできません。なぜなら、
これはフィールドが1つのレコードを引数としてとる関数に2つのフィールドを持つレコードが与えられている部分を含んでいて、
一方、[T_App]規則は関数の定義域の型は引数の型に完全に一致することを要求するからです。
しかしこれは馬鹿らしいことです。
実際には関数に、必要とされるものより良い引数を与えているのです!
この関数の本体がレコード引数[r]に対して行うことができることはおそらく、
そのフィールド[y]を射影することだけです。型から許されることは他にはありません。
すると、他に[x]フィールドが存在するか否かは何の違いもないはずです。
これから、直観的に、
この関数は少なくとも[y]フィールドは持つ任意のレコード値に適用可能であるべきと思われます。
同じことを別の観点から見ると、より豊かなフィールドを持つレコードは、
そのサブセットのフィールドだけを持つレコードと
「任意のコンテキストで少なくとも同等の良さである」と言えるでしょう。
より長い(多いフィールドを持つ)レコード型の任意の値は、
より短かいレコード型が求められるコンテキストで「安全に」(_safely_)使えるという意味においてです。
コンテキストがより短かい型のものを求めているときに、より長い型のものを与えた場合、
何も悪いことは起こらないでしょう(形式的には、プログラムは行き詰まることはないでしょう)。
ここではたらいている一般原理はサブタイプ(付け)(_subtyping_)と呼ばれます。
型[T]の値が求められている任意のコンテキストで型[S]の値が安全に使えるとき、
「[S]は[T]のサブタイプである」と言い、非形式的に [S <: T] と書きます。
サブタイプの概念はレコードだけではなく、関数、対、など言語のすべての型コンストラクタに適用されます。
*)
(* ** Subtyping and Object-Oriented Languages *)
(** ** サブタイプとオブジェクト指向言語 *)
(* Subtyping plays a fundamental role in many programming
languages -- in particular, it is closely related to the notion of
_subclassing_ in object-oriented languages.
An _object_ (in Java, C[#], etc.) can be thought of as a record,
some of whose fields are functions ("methods") and some of whose
fields are data values ("fields" or "instance variables").
Invoking a method [m] of an object [o] on some arguments [a1..an]
consists of projecting out the [m] field of [o] and applying it to
[a1..an].
The type of an object can be given as either a _class_ or an
_interface_. Both of these provide a description of which methods
and which data fields the object offers.
Classes and interfaces are related by the _subclass_ and
_subinterface_ relations. An object belonging to a subclass (or
subinterface) is required to provide all the methods and fields of
one belonging to a superclass (or superinterface), plus possibly
some more.
The fact that an object from a subclass (or sub-interface) can be
used in place of one from a superclass (or super-interface) provides
a degree of flexibility that is is extremely handy for organizing
complex libraries. For example, a graphical user interface
toolkit like Java's Swing framework might define an abstract
interface [Component] that collects together the common fields and
methods of all objects having a graphical representation that can
be displayed on the screen and that can interact with the user.
Examples of such object would include the buttons, checkboxes, and
scrollbars of a typical GUI. A method that relies only on this
common interface can now be applied to any of these objects.
Of course, real object-oriented languages include many other
features besides these. Fields can be updated. Fields and
methods can be declared [private]. Classes also give _code_ that
is used when constructing objects and implementing their methods,
and the code in subclasses cooperate with code in superclasses via
_inheritance_. Classes can have static methods and fields,
initializers, etc., etc.
To keep things simple here, we won't deal with any of these
issues -- in fact, we won't even talk any more about objects or
classes. (There is a lot of discussion in Types and Programming
Languages, if you are interested.) Instead, we'll study the core
concepts behind the subclass / subinterface relation in the
simplified setting of the STLC. *)
(** サブタイプは多くのプログラミング言語で重要な役割を演じます。
特に、オブジェクト指向言語のサブクラス(_subclassing_)の概念と近い関係にあります。
(JavaやC[#]等の)オブジェクトはレコードと考えることができます。
いくつかのフィールドは関数(「メソッド」)で、いくつかのフィールドはデータ値
(「フィールド」または「インスタンス変数」)です。
オブジェクト[o]のメソッド[m]を引数[a1..an]のもとで呼ぶことは、
[o]から[m]フィールドを射影として抽出して、それを[a1..an]に適用することです。
オブジェクトの型はクラス(_class_)またはインターフェース(_interface_)
として与えることができます。
この両者はどちらも、どのメソッドとどのデータフィールドをオブジェクトが提供するかを記述します。
クラスやインターフェースは、サブクラス(_subclass_)関係やサブインターフェース
(_subinterface_)関係で関係づけられます。
サブクラス(またはサブインターフェース)に属するオブジェクトには、スーパークラス
(またはスーパーインターフェース)
に属するオブジェクトのメソッドとフィールドのすべての提供することが求められ、
おそらくそれに加えてさらにいくつかのものを提供します。
サブクラス(またはサブインターフェース)のオブジェクトをスーパークラス(またはスーパーインターフェース)
のオブジェクトの場所で使えるという事実は、
複雑なライブラリの構築にきわめて便利なほどの柔軟性を提供します。
例えば、Javaの Swing
フレームワークのようなグラフィカルユーザーインターフェースツールキットは、
スクリーンに表示できユーザとインタラクションできるグラフィカルな表現を持つすべてのオブジェクトに共通のフィールドとメソッドを集めた、抽象インターフェース[Component]を定義するでしょう。
そのようなオブジェクトの例としては、典型的なGUIのボタン、チェックボックス、スクロールバーなどがあります。
この共通インターフェースのみに依存するメソッドは任意のそれらのオブジェクトに適用できます。
もちろん、実際のオブジェクト指向言語はこれらに加えてたくさんの他の機能を持っています。
フィールドは更新できます。フィールドとメソッドは[private]と宣言できます。
クラスはまた、
オブジェクトを構成しそのメソッドをインプリメントするのに使われる「コード」を与えます。
そしてサブクラスのコードは「継承」を通じてスーパークラスのコードと協調します。
クラスは、静的なメソッドやフィールド、イニシャライザ、等々を持つことができます。
ものごとを単純なまま進めるために、これらの問題を扱うことはしません。
実際、これ以上オブジェクトやクラスについて話すことはありません。
(もし興味があるなら、 Types and Programming Languages にたくさんの議論があります。)
その代わり、STLCの単純化された設定のもとで、
サブクラス/サブインターフェース関係の背後にある核となる概念について学習します。 *)
(* ** The Subsumption Rule *)
(** ** 包摂規則 *)
(* Our goal for this chapter is to add subtyping to the simply typed
lambda-calculus (with products). This involves two steps:
- Defining a binary _subtype relation_ between types.
- Enriching the typing relation to take subtyping into account.
The second step is actually very simple. We add just a single rule
to the typing relation -- the so-called _rule of subsumption_:
[[[
Gamma |- t : S S <: T
------------------------- (T_Sub)
Gamma |- t : T
]]]
This rule says, intuitively, that we can "forget" some of the
information that we know about a term. *)
(** この章のゴールは(直積を持つ)単純型付きラムダ計算にサブタイプを追加することです。
これは2つのステップから成ります:
- 型の間の二項サブタイプ関係(_subtype relation_)を定義します。
- 型付け関係をサブタイプを考慮した形に拡張します。
2つ目のステップは実際はとても単純です。型付け関係にただ1つの規則だけを追加します。
その規則は、包摂規則(_rule of subsumption_)と呼ばれます:
[[
Gamma |- t : S S <: T
------------------------- (T_Sub)
Gamma |- t : T
]]
この規則は、直観的には、項について知っている情報のいくらかを「忘れる」ことができると言っています。 *)
(* For example, we may know that [t] is a record with two
fields (e.g., [S = {x:A->A, y:B->B}]], but choose to forget about
one of the fields ([T = {y:B->B}]) so that we can pass [t] to a
function that expects just a single-field record. *)
(** 例えば、[t]が2つのフィールドを持つレコード(例えば、[S = {x:A->A, y:B->B}])で、
フィールドの1つを忘れることにした([T = {y:B->B}])とします。
すると[t]を、1フィールドのレコードを引数としてとる関数に渡すことができるようになります。 *)
(* ** The Subtype Relation *)
(** ** サブタイプ関係 *)
(* The first step -- the definition of the relation [S <: T] -- is
where all the action is. Let's look at each of the clauses of its
definition. *)
(** 最初のステップ、関係 [S <: T] の定義にすべてのアクションがあります。
定義のそれぞれを見てみましょう。 *)
(* *** Products *)
(** *** 直積型 *)
(** 最初に、直積型です。ある一つの対が他の対より「良い」とは、
それぞれの成分が他の対の対応するものより良いことです。
[[
S1 <: T1 S2 <: T2
-------------------- (S_Prod)
S1*S2 <: T1*T2
]]
*)
(* *** Arrows *)
(** *** 関数型 *)
(* Suppose we have two functions [f] and [g] with these types:
<<
f : C -> {x:A,y:B}
g : (C->{y:B}) -> D
>>
That is, [f] is a function that yields a record of type
[{x:A,y:B}], and [g] is a higher-order function that expects
its (function) argument to yield a record of type [{y:B}]. (And
suppose, even though we haven't yet discussed subtyping for
records, that [{x:A,y:B}] is a subtype of [{y:B}]) Then the
application [g f] is safe even though their types do not match up
precisely, because the only thing [g] can do with [f] is to apply
it to some argument (of type [C]); the result will actually be a
two-field record, while [g] will be expecting only a record with a
single field, but this is safe because the only thing [g] can then
do is to project out the single field that it knows about, and
this will certainly be among the two fields that are present.
This example suggests that the subtyping rule for arrow types
should say that two arrow types are in the subtype relation if
their results are:
[[[
S2 <: T2
---------------- (S_Arrow2)
S1->S2 <: S1->T2
]]]
We can generalize this to allow the arguments of the two arrow
types to be in the subtype relation as well:
[[[
T1 <: S1 S2 <: T2
-------------------- (S_Arrow)
S1->S2 <: T1->T2
]]]
Notice, here, that the argument types are subtypes "the other way
round": in order to conclude that [S1->S2] to be a subtype of
[T1->T2], it must be the case that [T1] is a subtype of [S1]. The
arrow constructor is said to be _contravariant_ in its first
argument and _covariant_ in its second.
The intuition is that, if we have a function [f] of type [S1->S2],
then we know that [f] accepts elements of type [S1]; clearly, [f]
will also accept elements of any subtype [T1] of [S1]. The type of
[f] also tells us that it returns elements of type [S2]; we can
also view these results belonging to any supertype [T2] of
[S2]. That is, any function [f] of type [S1->S2] can also be viewed
as having type [T1->T2]. *)
(** 次の型を持つ2つの関数[f]と[g]があるとします：
<<
f : C -> {x:A,y:B}
g : (C->{y:B}) -> D
>>
つまり、[f]は型[{x:A,y:B}]のレコードを引数とする関数であり、
[g]は引数として、型[{y:B}]のレコードを引数とする関数をとる高階関数です。
(そして、レコードのサブタイプについてはまだ議論していませんが、
[{x:A,y:B}] は [{y:B}] のサブタイプであるとします。)
すると、関数適用 [g f] は、両者の型が正確に一致しないにもかかわらず安全です。
なぜなら、[g]が[f]について行うことができるのは、
[f]を(型[C]の)ある引数に適用することだけだからです。
その結果は実際には2フィールドのレコードになります。
ここで[g]が期待するのは1つのフィールドを持つレコードだけです。
しかしこれは安全です。なぜなら[g]がすることができるのは、
わかっている1つのフィールドを射影することだけで、
それは存在する2つのフィールドの1つだからです。
この例から、関数型のサブタイプ規則が以下のようになるべきということが導かれます。
2つの関数型がサブタイプ関係にあるのは、その結果が次の条件のときです:
[[
S2 <: T2
---------------- (S_Arrow2)
S1->S2 <: S1->T2
]]
これを一般化して、2つの関数型のサブタイプ関係を、引数の条件を含めた形にすることが、同様にできます:
[[
T1 <: S1 S2 <: T2
-------------------- (S_Arrow)
S1->S2 <: T1->T2
]]
ここで注意するのは、引数の型はサブタイプ関係が逆向きになることです。
[S1->S2] が [T1->T2] のサブタイプであると結論するためには、
[T1]が[S1]のサブタイプでなければなりません。
関数型のコンストラクタは最初の引数について反変(_contravariant_)であり、
二番目の引数について共変(_covariant_)であると言います。
直観的には、型[S1->S2]の関数[f]があるとき、[f]は型[S1]の要素を引数にとることがわかります。
明らかに[f]は[S1]の任意のサブタイプ[T1]の要素をとることもできます。
[f]の型は同時に[f]が型[S2]の要素を返すことも示しています。
この値が[S2]の任意のスーパータイプ[T2]に属することも見ることができます。
つまり、型[S1->S2]の任意の関数[f]は、型[T1->T2]を持つと見ることもできるということです。 *)
(* *** Top *)
(** *** Top *)
(* It is natural to give the subtype relation a maximal element -- a
type that lies above every other type and is inhabited by
all (well-typed) values. We do this by adding to the language one
new type constant, called [Top], together with a subtyping rule
that places it above every other type in the subtype relation:
[[[
-------- (S_Top)
S <: Top
]]]
The [Top] type is an analog of the [Object] type in Java and C[#]. *)
(** サブタイプ関係の最大要素を定めることは自然です。他のすべての型のスーパータイプであり、
すべての(型付けできる)値が属する型です。このために言語に新しい一つの型定数[Top]を追加し、
[Top]をサブタイプ関係の他のすべての型のスーパータイプとするサブタイプ規則を定めます:
[[
-------- (S_Top)
S <: Top
]]
[Top]型はJavaやC[#]における[Object]型に対応するものです。 *)
(* *** Structural Rules *)
(** *** 構造規則 *)
(* To finish off the subtype relation, we add two "structural rules"
that are independent of any particular type constructor: a rule of
_transitivity_, which says intuitively that, if [S] is better than
[U] and [U] is better than [T], then [S] is better than [T]...
[[[
S <: U U <: T
---------------- (S_Trans)
S <: T
]]]
... and a rule of _reflexivity_, since any type [T] is always just
as good as itself:
[[[
------ (S_Refl)
T <: T
]]]
*)
(** サブタイプ関係の最後に、2つの「構造規則」("structural rules")を追加します。
これらは特定の型コンストラクタからは独立したものです。
推移律(rule of _transitivity_)は、直観的には、
[S]が[U]よりも良く、[U]が[T]よりも良ければ、[S]は[T]よりも良いというものです...
[[
S <: U U <: T
---------------- (S_Trans)
S <: T
]]
... そして反射律(rule of _reflexivity_)は、
任意の型はそれ自身と同じ良さを持つというものです。
[[
------ (S_Refl)
T <: T
]]
*)
(* *** Records *)
(** *** レコード *)
(* What about subtyping for record types?
The basic intuition about subtyping for record types is that it is
always safe to use a "bigger" record in place of a "smaller" one.
That is, given a record type, adding extra fields will always
result in a subtype. If some code is expecting a record with
fields [x] and [y], it is perfectly safe for it to receive a record
with fields [x], [y], and [z]; the [z] field will simply be ignored.
For example,
<<
{x:Nat,y:Bool} <: {x:Nat}
{x:Nat} <: {}
>>
This is known as "width subtyping" for records.
We can also create a subtype of a record type by replacing the type
of one of its fields with a subtype. If some code is expecting a
record with a field [x] of type [T], it will be happy with a record
having a field [x] of type [S] as long as [S] is a subtype of
[T]. For example,
<<
{a:{x:Nat}} <: {a:{}}
>>
This is known as "depth subtyping".
Finally, although the fields of a record type are written in a
particular order, the order does not really matter. For example,
<<
{x:Nat,y:Bool} <: {y:Bool,x:Nat}
>>
This is known as "permutation subtyping".
We could try formalizing these requirements in a single subtyping
rule for records as follows:
[[[
for each jk in j1..jn,
exists ip in i1..im, such that
jk=ip and Sp <: Tk
---------------------------------- (S_Rcd)
{i1:S1...im:Sm} <: {j1:T1...jn:Tn}
]]]
That is, the record on the left should have all the field labels of
the one on the right (and possibly more), while the types of the
common fields should be in the subtype relation. However, This rule
is rather heavy and hard to read. If we like, we can decompose it
into three simpler rules, which can be combined using [S_Trans] to
achieve all the same effects.
First, adding fields to the end of a record type gives a subtype:
[[[
n > m
--------------------------------- (S_RcdWidth)
{i1:T1...in:Tn} <: {i1:T1...im:Tm}
]]]
We can use [S_RcdWidth] to drop later fields of a multi-field
record while keeping earlier fields, showing for example that
[{y:B, x:A} <: {y:B}].
Second, we can apply subtyping inside the components of a compound
record type:
[[[
S1 <: T1 ... Sn <: Tn
---------------------------------- (S_RcdDepth)
{i1:S1...in:Sn} <: {i1:T1...in:Tn}
]]]
For example, we can use [S_RcdDepth] and [S_RcdWidth] together to
show that [{y:{z:B}, x:A} <: {y:{}}].
Third, we need to be able to reorder fields. The example we
originally had in mind was [{x:A,y:B} <: {y:B}]. We
haven't quite achieved this yet: using just [S_RcdDepth] and
[S_RcdWidth] we can only drop fields from the _end_ of a record
type. So we need:
[[[
{i1:S1...in:Sn} is a permutation of {i1:T1...in:Tn}
--------------------------------------------------- (S_RcdPerm)
{i1:S1...in:Sn} <: {i1:T1...in:Tn}
]]]
Further examples:
- [{x:A,y:B}] <: [{y:B,x:A}].
- [{}->{j:A} <: {k:B}->Top]
- [Top->{k:A,j:B} <: C->{j:B}]
*)
(** レコード型のサブタイプは何でしょうか？
レコード型のサブタイプについての基本的直観は、
「より小さな」レコードの場所で「より大きな」レコードを使うことは常に安全だということです。
つまり、レコード型があるとき、さらにフィールドを追加したものは常にサブタイプになるということです。
もしあるコードがフィールド[x]と[y]を持つレコードを期待していたとき、
レコード[x]、[y]、[z]を持つレコードを受けとることは完璧に安全です。
[z]フィールドは単に無視されるだけでしょう。
例えば次の通りです。
<<
{x:Nat,y:Bool} <: {x:Nat}
{x:Nat} <: {}
>>
これはレコードの"width subtyping"(幅サブタイプ)として知られます。
レコードの1つのフィールドの型をそのサブタイプで置き換えることでも、
レコードのサブタイプを作ることができます。
もしあるコードが型[T]のフィールド[x]を持つレコードを待っていたとき、
型[S]が型[T]のサブタイプである限りは、
型[S]のフィールド[x]を持つレコードが来ることはハッピーです。
例えば次の通りです。
<<
{a:{x:Nat}} <: {a:{}}
>>
これは"depth subtyping"(深さサブタイプ)として知られています。
最後に、レコードのフィールドは特定の順番で記述されますが、その順番は実際には問題ではありません。
例えば次の通りです。
<<
{x:Nat,y:Bool} <: {y:Bool,x:Nat}
>>
これは"permutation subtyping"(順列サブタイプ)として知られています。
これらをレコードについての単一のサブタイプ規則に形式化することをやってみましょう。
次の通りです:
[[
for each jk in j1..jn,
exists ip in i1..im, such that
jk=ip and Sp <: Tk
---------------------------------- (S_Rcd)
{i1:S1...im:Sm} <: {j1:T1...jn:Tn}
]]
つまり、左のレコードは(少なくとも)右のレコードのフィールドラベルをすべて持ち、
両者で共通するフィールドはサブタイプ関係になければならない、ということです。
しかしながら、この規則はかなり重くて読むのがたいへんです。
ここでは、3つのより簡単な規則に分解します。この3つは[S_Trans]を使うことで結合することができ、
同じ作用をすることができます。
最初に、レコード型の最後にフィールドを追加したものはサブタイプになります:
[[
n > m
--------------------------------- (S_RcdWidth)
{i1:T1...in:Tn} <: {i1:T1...im:Tm}
]]
[S_RcdWidth]を使うと、複数のフィールドを持つレコードについて、
前方のフィールドを残したまま後方のフィールドを落とすことができます。
この規則で例えば [{y:B, x:A} <: {y:B}] が示されます。
二つ目に、レコード型の構成要素の内部にサブタイプ規則を適用できます:
[[
S1 <: T1 ... Sn <: Tn
---------------------------------- (S_RcdDepth)
{i1:S1...in:Sn} <: {i1:T1...in:Tn}
]]
例えば [S_RcdDepth]と[S_RcdWidth]を両方使って [{y:{z:B}, x:A} <: {y:{}}]
を示すことができます。
三つ目に、フィールドの並べ替えを可能にする必要があります。
念頭に置いてきた例は [{x:A,y:B} <: {y:B}] でした。
これはまだ達成されていませんでした。
[S_RcdDepth]と[S_RcdWidth]だけでは、レコード型の「後」からフィールドを落とすことしかできません。
これから次の規則が必要です:
[[
{i1:S1...in:Sn} is a permutation of {i1:T1...in:Tn}
--------------------------------------------------- (S_RcdPerm)
{i1:S1...in:Sn} <: {i1:T1...in:Tn}
]]
さらなる例です:
- [{x:A,y:B}] <: [{y:B,x:A}].
- [{}->{j:A} <: {k:B}->Top]
- [Top->{k:A,j:B} <: C->{j:B}]
*)
(* It is worth noting that real languages may choose not to adopt
all of these subtyping rules. For example, in Java:
- A subclass may not change the argument or result types of a
method of its superclass (i.e., no depth subtyping or no arrow
subtyping, depending how you look at it).
- Each class has just one superclass ("single inheritance" of
classes)
- Each class member (field or method) can be assigned a single
index, adding new indices "on the right" as more members are
added in subclasses (i.e., no permutation for classes)
- A class may implement multiple interfaces -- so-called "multiple
inheritance" of interfaces (i.e., permutation is allowed for
interfaces). *)
(** なお、実際の言語ではこれらのサブタイプ規則のすべてを採用しているとは限らないことは、
注記しておくべきでしょう。例えばJavaでは:
- サブクラスではスーパークラスのメソッドの引数または結果の型を変えることはできません
(つまり、depth subtypingまたは関数型サブタイプのいずれかができないということです。
どちらかは見方によります)。
- それぞれのクラスは(直上の)スーパークラスを1つだけ持ちます(クラスの「単一継承」
("single inheritance")です)。
- 各クラスのメンバー(フィールドまたはメソッド)は1つだけインデックスを持ち、
サブクラスでメンバーが追加されるたびに新しいインデックスが「右に」追加されます
(つまり、クラスには並び換えがありません)。
- クラスは複数のインターフェースをインプリメントできます。これは
インターフェースの「多重継承」("multiple inheritance")と呼ばれます
(つまり、インターフェースには並び換えがあります)。 *)
(* *** Records, via Products and Top (optional) *)
(** *** 直積と Top によるレコード (optional) *)
(* Exactly how we formalize all this depends on how we are choosing
to formalize records and their types. If we are treating them as
part of the core language, then we need to write down subtyping
rules for them. The file [RecordSub.v] shows how this extension
works.
On the other hand, if we are treating them as a derived form that
is desugared in the parser, then we shouldn't need any new rules:
we should just check that the existing rules for subtyping product
and [Unit] types give rise to reasonable rules for record
subtyping via this encoding. To do this, we just need to make one
small change to the encoding described earlier: instead of using
[Unit] as the base case in the encoding of tuples and the "don't
care" placeholder in the encoding of records, we use [Top]. So:
<<
{a:Nat, b:Nat} ----> {Nat,Nat} i.e. (Nat,(Nat,Top))
{c:Nat, a:Nat} ----> {Nat,Top,Nat} i.e. (Nat,(Top,(Nat,Top)))
>>
The encoding of record values doesn't change at all. It is
easy (and instructive) to check that the subtyping rules above are
validated by the encoding. For the rest of this chapter, we'll
follow this approach. *)
(** これらすべてをどのように形式化するかは、レコードとその型をどのように形式化するかに、
まさに依存しています。もしこれらを核言語の一部として扱うならば、
そのためのサブタイプ規則を書き下す必要があります。
ファイル[RecordSub_J.v]で、この拡張がどのようにはたらくかを示します。
一方、もしそれらをパーサで展開される派生形として扱うならば、新しい規則は何も必要ありません。
直積と[Unit]型のサブタイプについての既存の規則が、
このエンコードによるレコードのサブタイプに関する妥当な規則になっているかをチェックすれば良いだけです。
このために、前述のエンコードをわずかに変更する必要があります。
組のエンコードのベースケースおよびレコードのエンコードの "don't care" プレースホルダとして、
[Unit]の代わりに[Top]を使います。
すると:
<<
{a:Nat, b:Nat} ----> {Nat,Nat} つまり (Nat,(Nat,Top))
{c:Nat, a:Nat} ----> {Nat,Top,Nat} つまり (Nat,(Top,(Nat,Top)))
>>
レコード値のエンコードは何も変更しません。
このエンコードで上述のサブタイプ規則が成立することをチェックするのは容易です
(そしてタメになります)。この章の残りでは、このアプローチを追求します。 *)
(* ###################################################### *)
(* * Core definitions *)
(** * 中核部の定義 *)
(* We've already sketched the significant extensions that we'll need
to make to the STLC: (1) add the subtype relation and (2) extend
the typing relation with the rule of subsumption. To make
everything work smoothly, we'll also implement some technical
improvements to the presentation from the last chapter. The rest
of the definitions -- in particular, the syntax and operational
semantics of the language -- are identical to what we saw in the
last chapter. Let's first do the identical bits. *)
(** STLCに必要となる重要な拡張を既に概観してきました:
(1)サブタイプ関係を追加し、(2)型関係に包摂規則を拡張することです。
すべてがスムースにいくように、前の章の表現にいくらかの技術的改善を行います。
定義の残りは -- 特に言語の構文と操作的意味は -- 前の章で見たものと同じです。
最初に同じ部分をやってみましょう。 *)
(* ################################### *)
(* *** Syntax *)
(** *** 構文 *)
(* Just for the sake of more interesting examples, we'll make one
more very small extension to the pure STLC: an arbitrary set of
additional _base types_ like [String], [Person], [Window], etc.
We won't bother adding any constants belonging to these types or
any operators on them, but we could easily do so. *)
(** よりおもしろい例のために、純粋STLCに非常に小さな拡張を行います。
[String]、[Person]、[Window]等のような、任意の「基本型」の集合を追加します。
これらの型の定数を追加したり、その型の上の操作を追加したりすることをわざわざやりませんが、
そうすることは簡単です。 *)
(* In the rest of the chapter, we formalize just base types,
booleans, arrow types, [Unit], and [Top], leaving product types as
an exercise. *)
(** この章の残りでは、基本型、ブール型、関数型、[Unit]と[Top]のみ形式化し、
直積型は練習問題にします。 *)
Inductive ty : Type :=
| ty_Top : ty
| ty_Bool : ty
| ty_base : id -> ty
| ty_arrow : ty -> ty -> ty
| ty_Unit : ty
.
Tactic Notation "ty_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ty_Top" | Case_aux c "ty_Bool"
| Case_aux c "ty_base" | Case_aux c "ty_arrow"
| Case_aux c "ty_Unit" |
].
Inductive tm : Type :=
| tm_var : id -> tm
| tm_app : tm -> tm -> tm
| tm_abs : id -> ty -> tm -> tm
| tm_true : tm
| tm_false : tm
| tm_if : tm -> tm -> tm -> tm
| tm_unit : tm
.
Tactic Notation "tm_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "tm_var" | Case_aux c "tm_app"
| Case_aux c "tm_abs" | Case_aux c "tm_true"
| Case_aux c "tm_false" | Case_aux c "tm_if"
| Case_aux c "tm_unit"
].
(* ################################### *)
(* *** Substitution *)
(** *** 包摂 *)
(* The definition of substitution remains the same as for the
ordinary STLC. *)
(** 包摂の定義は、いつものSTLCと同様です。 *)
Fixpoint subst (s:tm) (x:id) (t:tm) : tm :=
match t with
| tm_var y =>
if beq_id x y then s else t
| tm_abs y T t1 =>
tm_abs y T (if beq_id x y then t1 else (subst s x t1))
| tm_app t1 t2 =>
tm_app (subst s x t1) (subst s x t2)
| tm_true =>
tm_true
| tm_false =>
tm_false
| tm_if t1 t2 t3 =>
tm_if (subst s x t1) (subst s x t2) (subst s x t3)
| tm_unit =>
tm_unit
end.
(* ################################### *)
(* *** Reduction *)
(** *** 簡約 *)
(* Likewise the definitions of the [value] property and the [step]
relation. *)
(** [value](値)の定義や[step]関係の定義と同様です。 *)
Inductive value : tm -> Prop :=
| v_abs : forall x T t,
value (tm_abs x T t)
| t_true :
value tm_true
| t_false :
value tm_false
| v_unit :
value tm_unit
.
Hint Constructors value.
Reserved Notation "t1 '==>' t2" (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_AppAbs : forall x T t12 v2,
value v2 ->
(tm_app (tm_abs x T t12) v2) ==> (subst v2 x t12)
| ST_App1 : forall t1 t1' t2,
t1 ==> t1' ->
(tm_app t1 t2) ==> (tm_app t1' t2)
| ST_App2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
(tm_app v1 t2) ==> (tm_app v1 t2')
| ST_IfTrue : forall t1 t2,
(tm_if tm_true t1 t2) ==> t1
| ST_IfFalse : forall t1 t2,
(tm_if tm_false t1 t2) ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
(tm_if t1 t2 t3) ==> (tm_if t1' t2 t3)
where "t1 '==>' t2" := (step t1 t2).
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_AppAbs" | Case_aux c "ST_App1"
| Case_aux c "ST_App2" | Case_aux c "ST_IfTrue"
| Case_aux c "ST_IfFalse" | Case_aux c "ST_If"
].
Hint Constructors step.
(* ###################################################################### *)
(* * Subtyping *)
(** * サブタイプ *)
(* Now we come to the interesting part. We begin by defining
the subtyping relation and developing some of its important
technical properties. *)
(** さて、おもしろい所にやって来ました。サブタイプ関係の定義から始め、その重要な技術的性質を調べます。 *)
(* ################################### *)
(* ** Definition *)
(** ** 定義 *)
(* The definition of subtyping is just what we sketched in the
motivating discussion. *)
(** サブタイプの定義は、動機付けの議論のところで概観した通りです。 *)
Inductive subtype : ty -> ty -> Prop :=
| S_Refl : forall T,
subtype T T
| S_Trans : forall S U T,
subtype S U ->
subtype U T ->
subtype S T
| S_Top : forall S,
subtype S ty_Top
| S_Arrow : forall S1 S2 T1 T2,
subtype T1 S1 ->
subtype S2 T2 ->
subtype (ty_arrow S1 S2) (ty_arrow T1 T2)
.
(* Note that we don't need any special rules for base types: they are
automatically subtypes of themselves (by [S_Refl]) and [Top] (by
[S_Top]), and that's all we want. *)
(** なお、基本型については特別な規則は何ら必要ありません。
基本型は自動的に([S_Refl]より)自分自身のサブタイプであり、
([S_Top]より)[Top]のサブタイプでもあります。そしてこれが必要な全てです。 *)
Hint Constructors subtype.
Tactic Notation "subtype_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "S_Refl" | Case_aux c "S_Trans"
| Case_aux c "S_Top" | Case_aux c "S_Arrow"
].
(* ############################################### *)
(* ** Subtyping Examples and Exercises *)
(** ** サブタイプの例と練習問題 *)
Module Examples.
Notation x := (Id 0).
Notation y := (Id 1).
Notation z := (Id 2).
Notation A := (ty_base (Id 6)).
Notation B := (ty_base (Id 7)).
Notation C := (ty_base (Id 8)).
Notation String := (ty_base (Id 9)).
Notation Float := (ty_base (Id 10)).
Notation Integer := (ty_base (Id 11)).
(* **** Exercise: 2 stars, optional (subtyping judgements) *)
(** **** 練習問題: ★★, optional (subtyping judgements) *)
(* (Do this exercise after you have added product types to the
language, at least up to this point in the file).
Using the encoding of records into pairs, define pair types
representing the record types
[[
Person := { name : String }
Student := { name : String ;
gpa : Float }
Employee := { name : String ;
ssn : Integer }
]]
*)
(** (この練習問題は、少なくともファイルのここまでに、直積型を言語に追加した後で行ってください。)
レコードを対でエンコードするときに、以下のレコード型を表す直積型を定義しなさい。
[[
Person := { name : String }
Student := { name : String ;
gpa : Float }
Employee := { name : String ;
ssn : Integer }
]]
*)
Definition Person : ty :=
(* FILL IN HERE *) admit.
Definition Student : ty :=
(* FILL IN HERE *) admit.
Definition Employee : ty :=
(* FILL IN HERE *) admit.
Example sub_student_person :
subtype Student Person.
Proof.
(* FILL IN HERE *) Admitted.
Example sub_employee_person :
subtype Employee Person.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
Example subtyping_example_0 :
subtype (ty_arrow C Person)
(ty_arrow C ty_Top).
(* C->Person <: C->Top *)
Proof.
apply S_Arrow.
apply S_Refl. auto.
Qed.
(* The following facts are mostly easy to prove in Coq. To get
full benefit from the exercises, make sure you also
understand how to prove them on paper! *)
(** 以下の事実のほとんどは、Coqで証明するのは簡単です。
練習問題の効果を十分に得るために、
どうやって証明するか自分が理解していることを紙に証明を書いて確認しなさい。 *)
(* **** Exercise: 1 star, optional (subtyping_example_1) *)
(** **** 練習問題: ★, optional (subtyping_example_1) *)
Example subtyping_example_1 :
subtype (ty_arrow ty_Top Student)
(ty_arrow (ty_arrow C C) Person).
(* Top->Student <: (C->C)->Person *)
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
(* **** Exercise: 1 star, optional (subtyping_example_2) *)
(** **** 練習問題: ★, optional (subtyping_example_2) *)
Example subtyping_example_2 :
subtype (ty_arrow ty_Top Person)
(ty_arrow Person ty_Top).
(* Top->Person <: Person->Top *)
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
End Examples.
(* **** Exercise: 1 star, optional (subtype_instances_tf_1) *)
(** **** 練習問題: ★, optional (subtype_instances_tf_1) *)
(* Suppose we have types [S], [T], [U], and [V] with [S <: T]
and [U <: V]. Which of the following subtyping assertions
are then true? Write _true_ or _false_ after each one.
(Note that [A], [B], and [C] are base types.)
- [T->S <: T->S]
- [Top->U <: S->Top]
- [(C->C) -> (A*B) <: (C->C) -> (Top*B)]
- [T->T->U <: S->S->V]
- [(T->T)->U <: (S->S)->V]
- [((T->S)->T)->U <: ((S->T)->S)->V]
- [S*V <: T*U]
[]
*)
(** 型[S]、[T]、[U]、[V]があり [S <: T] かつ [U <: V] とします。
このとき以下のサブタイプ関係の主張のうち、正しいものはどれでしょうか？
それぞれの後に「真」または「偽」と書きなさい。
(ここで、[A]、[B]、[C]は基本型とします。)
- [T->S <: T->S]
- [Top->U <: S->Top]
- [(C->C) -> (A*B) <: (C->C) -> (Top*B)]
- [T->T->U <: S->S->V]
- [(T->T)->U <: (S->S)->V]
- [((T->S)->T)->U <: ((S->T)->S)->V]
- [S*V <: T*U]
[]
*)
(* **** Exercise: 1 star (subtype_instances_tf_2) *)
(** **** 練習問題: ★ (subtype_instances_tf_2) *)
(* Which of the following statements are true? Write TRUE or FALSE
after each one.
[[
forall S T,
S <: T ->
S->S <: T->T
forall S T,
S <: A->A ->
exists T,
S = T->T /\ T <: A
forall S T1 T1,
S <: T1 -> T2 ->
exists S1 S2,
S = S1 -> S2 /\ T1 <: S1 /\ S2 <: T2
exists S,
S <: S->S
exists S,
S->S <: S
forall S T2 T2,
S <: T1*T2 ->
exists S1 S2,
S = S1*S2 /\ S1 <: T1 /\ S2 <: T2
]]
[] *)
(** 以下の主張のうち正しいものはどれでしょうか？
それぞれについて「真」または「偽」と書きなさい。
[[
forall S T,
S <: T ->
S->S <: T->T
forall S T,
S <: A->A ->
exists T,
S = T->T /\ T <: A
forall S T1 T1,
S <: T1 -> T2 ->
exists S1 S2,
S = S1 -> S2 /\ T1 <: S1 /\ S2 <: T2
exists S,
S <: S->S
exists S,
S->S <: S
forall S T2 T2,
S <: T1*T2 ->
exists S1 S2,
S = S1*S2 /\ S1 <: T1 /\ S2 <: T2
]]
[] *)
(* **** Exercise: 1 star (subtype_concepts_tf) *)
(** **** 練習問題: ★ (subtype_concepts_tf) *)
(* Which of the following statements are true, and which are false?
- There exists a type that is a supertype of every other type.
- There exists a type that is a subtype of every other type.
- There exists a pair type that is a supertype of every other
pair type.
- There exists a pair type that is a subtype of every other
pair type.
- There exists an arrow type that is a supertype of every other
arrow type.
- There exists an arrow type that is a subtype of every other
arrow type.
- There is an infinite descending chain of distinct types in the
subtype relation---that is, an infinite sequence of types
[S0], [S1], etc., such that all the [Si]'s are different and
each [S(i+1)] is a subtype of [Si].
- There is an infinite _ascending_ chain of distinct types in
the subtype relation---that is, an infinite sequence of types
[S0], [S1], etc., such that all the [Si]'s are different and
each [S(i+1)] is a supertype of [Si].
[]
*)
(** 以下のうち真であるものはどれで、偽であるものはどれでしょうか？
- 他のすべての型のスーパータイプである型がある。
- 他のすべての型のサブタイプである型がある。
- 他のすべての対型のスーパータイプである対型がある。
- 他のすべての対型のサブタイプである対型がある。
- 他のすべての関数型のスーパータイプである関数型がある。
- 他のすべての関数型のサブタイプである関数型がある。
- サブタイプ関係による、同一型を含まない無限降鎖(infinite descending chain)がある。
つまり型の無限列[S0]、[S1]、... があり、すべての[Si]は異なり、
そして各[S(i+1)]は[S(i)]のサブタイプである。
- サブタイプ関係による、同一型を含まない無限昇鎖(infinite _ascending_ chain)がある。
つまり型の無限列[S0]、[S1]、... があり、すべての[Si]は異なり、
そして各[S(i+1)]は[S(i)]のスーパータイプである。
[]
*)
(* **** Exercise: 2 stars (proper_subtypes) *)
(** **** 練習問題: ★★ (proper_subtypes) *)
(* Is the following statement true or false? Briefly explain your
answer.
[[
forall T,
~(exists n, T = ty_base n) ->
exists S,
S <: T /\ S <> T
]]
[]
*)
(** 次の主張は真でしょうか偽でしょうか？自分の答えを簡単に説明しなさい。
[[
forall T,
~(exists n, T = ty_base n) ->
exists S,
S <: T /\ S <> T
]]
[]
*)
(* **** Exercise: 2 stars (small_large_1) *)
(** **** 練習問題: ★★ (small_large_1) *)
(*
- What is the _smallest_ type [T] ("smallest" in the subtype
relation) that makes the following assertion true?
[[
empty |- (\p:T*Top. p.fst) ((\z:A.z), unit) : A->A
]]
- What is the _largest_ type [T] that makes the same assertion true?
[]
*)
(**
- 次の表明を真にする最小の型[T]は何でしょうか？
(ここで「最小」とはサブタイプ関係においてです。)
[[
empty |- (\p:T*Top. p.fst) ((\z:A.z), unit) : A->A
]]
- 同じ表明を真にする最大の型[T]は何でしょうか？
[]
*)
(* **** Exercise: 2 stars (small_large_2) *)
(** **** 練習問題: ★★ (small_large_2) *)
(*
- What is the _smallest_ type [T] that makes the following
assertion true?
[[
empty |- (\p:(A->A * B->B). p) ((\z:A.z), (\z:B.z)) : T
]]
- What is the _largest_ type [T] that makes the same assertion true?
[]
*)
(**
- 次の表明を真にする最小の型[T]は何でしょうか？
[[
empty |- (\p:(A->A * B->B). p) ((\z:A.z), (\z:B.z)) : T
]]
- 同じ表明を真にする最大の型[T]は何でしょうか？
[]
*)
(* **** Exercise: 2 stars, optional (small_large_3) *)
(** **** 練習問題: ★★, optional (small_large_3) *)
(*
- What is the _smallest_ type [T] that makes the following
assertion true?
[[
a:A |- (\p:(A*T). (p.snd) (p.fst)) (a , \z:A.z) : A
]]
- What is the _largest_ type [T] that makes the same assertion true?
[]
*)
(**
- 次の表明を真にする最小の型[T]は何でしょうか？
[[
a:A |- (\p:(A*T). (p.snd) (p.fst)) (a , \z:A.z) : A
]]
- 同じ表明を真にする最大の型[T]は何でしょうか？
[]
*)
(* **** Exercise: 2 stars (small_large_4) *)
(** **** 練習問題: ★★ (small_large_4) *)
(*
- What is the _smallest_ type [T] that makes the following
assertion true?
[[
exists S,
empty |- (\p:(A*T). (p.snd) (p.fst)) : S
]]
- What is the _largest_ type [T] that makes the same
assertion true?
[]
*)
(**
- 次の表明を真にする最小の型[T]は何でしょうか？
[[
exists S,
empty |- (\p:(A*T). (p.snd) (p.fst)) : S
]]
- 同じ表明を真にする最大の型[T]は何でしょうか？
[]
*)
(* **** Exercise: 2 stars (smallest_1) *)
(** **** 練習問題: ★★ (smallest_1) *)
(* What is the _smallest_ type [T] that makes the following
assertion true?
[[
exists S, exists t,
empty |- (\x:T. x x) t : S
]]
[]
*)
(** 次の表明を真にする最小の型[T]は何でしょうか？
[[
exists S, exists t,
empty |- (\x:T. x x) t : S
]]
[]
*)
(* **** Exercise: 2 stars (smallest_2) *)
(** **** 練習問題: ★★ (smallest_2) *)
(* What is the _smallest_ type [T] that makes the following
assertion true?
[[
empty |- (\x:Top. x) ((\z:A.z) , (\z:B.z)) : T
]]
[]
*)
(** 次の表明を真にする最小の型[T]は何でしょうか？
[[
empty |- (\x:Top. x) ((\z:A.z) , (\z:B.z)) : T
]]
[]
*)
(* **** Exercise: 3 stars, optional (count_supertypes) *)
(** **** 練習問題: ★★★, optional (count_supertypes) *)
(* How many supertypes does the record type [{x:A, y:C->C}] have? That is,
how many different types [T] are there such that [{x:A, y:C->C} <:
T]? (We consider two types to be different if they are written
differently, even if each is a subtype of the other. For example,
[{x:A,y:B}] and [{y:B,x:A}] are different.)
[]
*)
(** レコード型 [{x:A, y:C->C}] はいくつのスーパータイプを持つでしょうか？
つまり、いくつの異なる型[T]が [{x:A, y:C->C} <: T] を満たすでしょうか?
(ここで、2つの型が異なるとは、その記述が異なることとします。
たとえ両者が相互にサブタイプであってもです。
例えば、[{x:A,y:B}] と [{y:B,x:A}] は異なります。)
[]
*)
(* ###################################################################### *)
(* * Typing *)
(** * 型付け *)
(* The only change to the typing relation is the addition of the rule
of subsumption, [T_Sub]. *)
(** 型付け関係の変更は、包摂規則 [T_Sub] の追加だけです。 *)
Definition context := id -> (option ty).
Definition empty : context := (fun _ => None).
Definition extend (Gamma : context) (x:id) (T : ty) :=
fun x' => if beq_id x x' then Some T else Gamma x'.
Inductive has_type : context -> tm -> ty -> Prop :=
(* Same as before *)
| T_Var : forall Gamma x T,
Gamma x = Some T ->
has_type Gamma (tm_var x) T
| T_Abs : forall Gamma x T11 T12 t12,
has_type (extend Gamma x T11) t12 T12 ->
has_type Gamma (tm_abs x T11 t12) (ty_arrow T11 T12)
| T_App : forall T1 T2 Gamma t1 t2,
has_type Gamma t1 (ty_arrow T1 T2) ->
has_type Gamma t2 T1 ->
has_type Gamma (tm_app t1 t2) T2
| T_True : forall Gamma,
has_type Gamma tm_true ty_Bool
| T_False : forall Gamma,
has_type Gamma tm_false ty_Bool
| T_If : forall t1 t2 t3 T Gamma,
has_type Gamma t1 ty_Bool ->
has_type Gamma t2 T ->
has_type Gamma t3 T ->
has_type Gamma (tm_if t1 t2 t3) T
| T_Unit : forall Gamma,
has_type Gamma tm_unit ty_Unit
(* New rule of subsumption *)
| T_Sub : forall Gamma t S T,
has_type Gamma t S ->
subtype S T ->
has_type Gamma t T.
Hint Constructors has_type.
Tactic Notation "has_type_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "T_Var" | Case_aux c "T_Abs"
| Case_aux c "T_App" | Case_aux c "T_True"
| Case_aux c "T_False" | Case_aux c "T_If"
| Case_aux c "T_Unit"
| Case_aux c "T_Sub" ].
(* ############################################### *)
(* ** Typing examples *)
(** ** 型付けの例 *)
Module Examples2.
Import Examples.
(* Do the following exercises after you have added product types to
the language. For each informal typing judgement, write it as a
formal statement in Coq and prove it. *)
(** 以下の練習問題は言語に直積を追加した後に行いなさい。
それぞれの非形式的な型付けジャッジメントについて、Coqで形式的主張を記述し、
それを証明しなさい。 *)
(* **** Exercise: 1 star, optional (typing_example_0) *)
(** **** 練習問題: ★, optional (typing_example_0) *)
(* empty |- ((\z:A.z), (\z:B.z)) : (A->A * B->B) *)
(* FILL IN HERE *)
(** [] *)
(* **** Exercise: 2 stars, optional (typing_example_1) *)
(** **** 練習問題: ★★, optional (typing_example_1) *)
(* empty |- (\x:(Top * B->B). x.snd) ((\z:A.z), (\z:B.z)) : B->B *)
(* FILL IN HERE *)
(** [] *)
(* **** Exercise: 2 stars, optional (typing_example_2) *)
(** **** 練習問題: ★★, optional (typing_example_2) *)
(* empty |- (\z:(C->C)->(Top * B->B). (z (\x:C.x)).snd)
(\z:C->C. ((\z:A.z), (\z:B.z)))
: B->B *)
(* FILL IN HERE *)
(** [] *)
End Examples2.
(* ###################################################################### *)
(* * Properties *)
(** * 性質 *)
(* The fundamental properties of the system that we want to check are
the same as always: progress and preservation. Unlike the
extension of the STLC with references, we don't need to change the
_statements_ of these properties to take subtyping into account.
However, their proofs do become a little bit more involved. *)
(** チェックしたいシステムの根本的性質はいつもと同じく、進行と保存です。
STLCに参照を拡張したものとは違い、サブタイプを考慮しても、これらの主張を変化させる必要はありません。
ただし、それらの証明はもうちょっと複雑になります。 *)
(* ###################################################################### *)
(* ** Inversion Lemmas for Subtyping *)
(** ** サブタイプの反転補題(Inversion Lemmas) *)
(* Before we look at the properties of the typing relation, we need
to record a couple of critical structural properties of the subtype
relation:
- [Bool] is the only subtype of [Bool]
- every subtype of an arrow type _is_ an arrow type. *)
(** 型付け関係の性質を見る前に、サブタイプ関係の2つの重要な構造的性質を記しておかなければなりません:
- [Bool]は[Bool]の唯一のサブタイプです
- 関数型のすべてのサブタイプは関数型です *)
(* These are called _inversion lemmas_ because they play the same
role in later proofs as the built-in [inversion] tactic: given a
hypothesis that there exists a derivation of some subtyping
statement [S <: T] and some constraints on the shape of [S] and/or
[T], each one reasons about what this derivation must look like to
tell us something further about the shapes of [S] and [T] and the
existence of subtype relations between their parts. *)
(** これらは反転補題(_inversion lemmas_)と呼ばれます。これは、後の証明でもともとの
[inversion]タクティックと同じ役目をするためです。
つまり、サブタイプ関係の主張 [S <: T] の導出が存在するという仮定と、
[S]や[T]の形についてのいくつかの制約が与えられたとき、
それぞれの補題は、[S]と[T]の形、および両者の構成要素間のサブタイプ関係の存在について、
より多くのことが言えるためには、
[S <: T] の導出がどういう形でなければならないかを提示するからです。 *)
(* **** Exercise: 2 stars, optional (sub_inversion_Bool) *)
(** **** 練習問題: ★★, optional (sub_inversion_Bool) *)
Lemma sub_inversion_Bool : forall U,
subtype U ty_Bool ->
U = ty_Bool.
Proof with auto.
intros U Hs.
remember ty_Bool as V.
(* FILL IN HERE *) Admitted.
(* **** Exercise: 3 stars, optional (sub_inversion_arrow) *)
(** **** 練習問題: ★★★, optional (sub_inversion_arrow) *)
Lemma sub_inversion_arrow : forall U V1 V2,
subtype U (ty_arrow V1 V2) ->
exists U1, exists U2,
U = (ty_arrow U1 U2) /\ (subtype V1 U1) /\ (subtype U2 V2).
Proof with eauto.
intros U V1 V2 Hs.
remember (ty_arrow V1 V2) as V.
generalize dependent V2. generalize dependent V1.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ########################################## *)
(* ** Canonical Forms *)
(** ** 正準形(Canonical Forms) *)
(* We'll see first that the proof of the progress theorem doesn't
change too much -- we just need one small refinement. When we're
considering the case where the term in question is an application
[t1 t2] where both [t1] and [t2] are values, we need to know that
[t1] has the _form_ of a lambda-abstraction, so that we can apply
the [ST_AppAbs] reduction rule. In the ordinary STLC, this is
obvious: we know that [t1] has a function type [T11->T12], and
there is only one rule that can be used to give a function type to
a value -- rule [T_Abs] -- and the form of the conclusion of this
rule forces [t1] to be an abstraction.
In the STLC with subtyping, this reasoning doesn't quite work
because there's another rule that can be used to show that a value
has a function type: subsumption. Fortunately, this possibility
doesn't change things much: if the last rule used to show [Gamma
|- t1 : T11->T12] is subsumption, then there is some
_sub_-derivation whose subject is also [t1], and we can reason by
induction until we finally bottom out at a use of [T_Abs].
This bit of reasoning is packaged up in the following lemma, which
tells us the possible "canonical forms" (i.e. values) of function
type. *)
(** 最初に、進行定理の証明はそれほど変わらないことを見ます。
1つだけ小さなリファインメントが必要です。
問題となる項が関数適用 [t1 t2] で[t1]と[t2]が両方とも値の場合を考えるとき、
[t1]がラムダ抽象の形をしており、
そのため[ST_AppAbs]簡約規則が適用できることを確認する必要があります。
もともとのSTLCでは、これは明らかです。
[t1]が関数型[T11->T12]を持ち、また、関数型の値を与える規則が1つだけ、
つまり規則[T_Abs]だけであり、そしてこの規則の結論部の形から、
[t1]は関数型にならざるを得ない、ということがわかります。
サブタイプを持つSTLCにおいては、この推論はそのままうまく行くわけではありません。
その理由は、値が関数型を持つことを示すのに使える規則がもう1つあるからです。
包摂規則です。幸い、このことが大きな違いをもたらすことはありません。
もし [Gamma |- t1 : T11->T12] を示すのに使われた最後の規則が包摂規則だった場合、
導出のその前の部分で、同様に[t1]が主部(項の部分)である導出があり、
帰納法により一番最初には[T_Abs]が使われたことが推論できるからです。
推論のこの部分は次の補題にまとめられています。この補題は、関数型の可能な正準形
("canonical forms"、つまり値)を示します。 *)
(* **** Exercise: 3 stars, optional (canonical_forms_of_arrow_types) *)
(** **** 練習問題: ★★★, optional (canonical_forms_of_arrow_types) *)
Lemma canonical_forms_of_arrow_types : forall Gamma s T1 T2,
has_type Gamma s (ty_arrow T1 T2) ->
value s ->
exists x, exists S1, exists s2,
s = tm_abs x S1 s2.
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
(* Similarly, the canonical forms of type [Bool] are the constants
[true] and [false]. *)
(** 同様に、型[Bool]の正準形は定数[true]と[false]です。 *)
Lemma canonical_forms_of_Bool : forall Gamma s,
has_type Gamma s ty_Bool ->
value s ->
(s = tm_true \/ s = tm_false).
Proof with eauto.
intros Gamma s Hty Hv.
remember ty_Bool as T.
has_type_cases (induction Hty) Case; try solve by inversion...
Case "T_Sub".
subst. apply sub_inversion_Bool in H. subst...
Qed.
(* ########################################## *)
(* ** Progress *)
(** ** 進行 *)
(* The proof of progress proceeds like the one for the pure
STLC, except that in several places we invoke canonical forms
lemmas... *)
(** 進行性の証明は純粋なSTLCとほぼ同様に進みます。ただ何箇所かで正準形補題を使うことを除けば...
*)
(* _Theorem_ (Progress): For any term [t] and type [T], if [empty |-
t : T] then [t] is a value or [t ==> t'] for some term [t'].
_Proof_: Let [t] and [T] be given, with [empty |- t : T]. Proceed
by induction on the typing derivation.
The cases for [T_Abs], [T_Unit], [T_True] and [T_False] are
immediate because abstractions, [unit], [true], and [false] are
already values. The [T_Var] case is vacuous because variables
cannot be typed in the empty context. The remaining cases are
more interesting:
- If the last step in the typing derivation uses rule [T_App],
then there are terms [t1] [t2] and types [T1] and [T2] such that
[t = t1 t2], [T = T2], [empty |- t1 : T1 -> T2], and [empty |-
t2 : T1]. Moreover, by the induction hypothesis, either [t1] is
a value or it steps, and either [t2] is a value or it steps.
There are three possibilities to consider:
- Suppose [t1 ==> t1'] for some term [t1']. Then [t1 t2 ==> t1' t2]
by [ST_App1].
- Suppose [t1] is a value and [t2 ==> t2'] for some term [t2'].
Then [t1 t2 ==> t1 t2'] by rule [ST_App2] because [t1] is a
value.
- Finally, suppose [t1] and [t2] are both values. By Lemma
[canonical_forms_for_arrow_types], we know that [t1] has the
form [\x:S1.s2] for some [x], [S1], and [s2]. But then
[(\x:S1.s2) t2 ==> [t2/x]s2] by [ST_AppAbs], since [t2] is a
value.
- If the final step of the derivation uses rule [T_If], then there
are terms [t1], [t2], and [t3] such that [t = if t1 then t2 else
t3], with [empty |- t1 : Bool] and with [empty |- t2 : T] and
[empty |- t3 : T]. Moreover, by the induction hypothesis,
either [t1] is a value or it steps.
- If [t1] is a value, then by the canonical forms lemma for
booleans, either [t1 = true] or [t1 = false]. In either
case, [t] can step, using rule [ST_IfTrue] or [ST_IfFalse].
- If [t1] can step, then so can [t], by rule [ST_If].
- If the final step of the derivation is by [T_Sub], then there is
a type [S] such that [S <: T] and [empty |- t : S]. The desired
result is exactly the induction hypothesis for the typing
subderivation.
*)
(** 「定理」(進行): 任意の項[t]と型[T]について、
もし [empty |- t : T] ならば[t]は値であるか、ある項[t']について [t ==> t'] である。
「証明」:[t]と[T]が与えられ、[empty |- t : T] とする。
型付けの導出についての帰納法で進める。
(最後の規則が)[T_Abs]、[T_Unit]、[T_True]、[T_False]のいずれかの場合は、
自明である。なぜなら、関数抽象、[unit]、[true]、[false]は既に値だからである。
[T_Var]であることはありえない。なぜなら、変数は空コンテキストで型付けできないからである。
残るのはより興味深い場合である:
- 型付け導出の最後のステップで規則[T_App]が使われた場合、
項[t1]、[t2]と型[T1]、[T2]が存在して [t = t1 t2]、[T = T2]、
[empty |- t1 : T1 -> T2]、[empty |- t2 : T1] となる。
さらに帰納法の仮定から、[t1]は値であるかステップを進めることができ、
[t2]も値であるかステップを進めることができる。
このとき、3つの場合がある:
- ある項 [t1'] について [t1 ==> t1'] とする。このとき[ST_App1]より
[t1 t2 ==> t1' t2] である。
- [t1]が値であり、ある項[t2']について [t2 ==> t2'] とする。
このとき規則[ST_App2]より [t1 t2 ==> t1 t2'] となる。なぜなら
[t1]が値だからである。
- 最後に[t1]と[t2]がどちらも値とする。補題[canonical_forms_for_arrow_types]
より、[t1]はある[x]、[S1]、[s2]について[\x:S1.s2]という形である。
しかしすると[t2]が値であることから、
[ST_AppAbs]より [(\x:S1.s2) t2 ==> [t2/x]s2] となる。
- 導出の最後のステップで規則[T_If]が使われた場合、項[t1]、[t2]、[t3]があって
[t = if t1 then t2 else t3] となり、
[empty |- t1 : Bool] かつ [empty |- t2 : T] かつ [empty |- t3 : T] である。
さらに、帰納法の仮定より[t1]は値であるかステップを進めることができる。
- もし[t1]が値ならば、ブール値についての正準形補題より [t1 = true] または
[t1 = false] である。どちらの場合でも、規則[ST_IfTrue]または[ST_IfFalse]
を使うことによって[t]はステップを進めることができる。
- もし[t1]がステップを進めることができるならば、
規則[ST_If]より[t]もまたステップを進めることができる。
- 導出の最後のステップが規則[T_Sub]による場合、型[S]があって [S <: T] かつ
[empty |- t : S] となっている。
求める結果は型付け導出の帰納法の仮定そのものである。
*)
Theorem progress : forall t T,
has_type empty t T ->
value t \/ exists t', t ==> t'.
Proof with eauto.
intros t T Ht.
remember empty as Gamma.
revert HeqGamma.
has_type_cases (induction Ht) Case;
intros HeqGamma; subst...
Case "T_Var".
inversion H.
Case "T_App".
right.
destruct IHHt1; subst...
SCase "t1 is a value".
destruct IHHt2; subst...
SSCase "t2 is a value".
destruct (canonical_forms_of_arrow_types empty t1 T1 T2)
as [x [S1 [t12 Heqt1]]]...
subst. exists (subst t2 x t12)...
SSCase "t2 steps".
destruct H0 as [t2' Hstp]. exists (tm_app t1 t2')...
SCase "t1 steps".
destruct H as [t1' Hstp]. exists (tm_app t1' t2)...
Case "T_If".
right.
destruct IHHt1.
SCase "t1 is a value"...
assert (t1 = tm_true \/ t1 = tm_false)
by (eapply canonical_forms_of_Bool; eauto).
inversion H0; subst...
destruct H. rename x into t1'. eauto.
Qed.
(* ########################################## *)
(* ** Inversion Lemmas for Typing *)
(** ** 型付けの反転補題 *)
(* The proof of the preservation theorem also becomes a little more
complex with the addition of subtyping. The reason is that, as
with the "inversion lemmas for subtyping" above, there are a
number of facts about the typing relation that are "obvious from
the definition" in the pure STLC (and hence can be obtained
directly from the [inversion] tactic) but that require real proofs
in the presence of subtyping because there are multiple ways to
derive the same [has_type] statement.
The following "inversion lemma" tells us that, if we have a
derivation of some typing statement [Gamma |- \x:S1.t2 : T] whose
subject is an abstraction, then there must be some subderivation
giving a type to the body [t2]. *)
(** 保存定理の証明はサブタイプを追加したことでやはり少し複雑になります。
その理由は、上述の「サブタイプの反転補題」と同様に、純粋なSTLCでは「定義から自明」
であった(したがって[inversion]タクティックからすぐに得られた)のに、
サブタイプがあることで本当の証明が必要になった、
型付け関係についてのいくつもの事実があるからです。
サブタイプがある場合、同じ[has_type]の主張を導出するのに複数の方法があるのです。
以下の「反転補題」("inversion lemma")は、
もし、関数抽象の型付け主張 [Gamma |- \x:S1.t2 : T]
の導出があるならば、その導出の中に本体[t2]の型を与える部分が含まれている、
ということを言うものです。 *)
(* _Lemma_: If [Gamma |- \x:S1.t2 : T], then there is a type [S2]
such that [Gamma, x:S1 |- t2 : S2] and [S1 -> S2 <: T].
(Notice that the lemma does _not_ say, "then [T] itself is an arrow
type" -- this is tempting, but false!)
_Proof_: Let [Gamma], [x], [S1], [t2] and [T] be given as
described. Proceed by induction on the derivation of [Gamma |-
\x:S1.t2 : T]. Cases [T_Var], [T_App], are vacuous as those
rules cannot be used to give a type to a syntactic abstraction.
- If the last step of the derivation is a use of [T_Abs] then
there is a type [T12] such that [T = S1 -> T12] and [Gamma,
x:S1 |- t2 : T12]. Picking [T12] for [S2] gives us what we
need: [S1 -> T12 <: S1 -> T12] follows from [S_Refl].
- If the last step of the derivation is a use of [T_Sub] then
there is a type [S] such that [S <: T] and [Gamma |- \x:S1.t2 :
S]. The IH for the typing subderivation tell us that there is
some type [S2] with [S1 -> S2 <: S] and [Gamma, x:S1 |- t2 :
S2]. Picking type [S2] gives us what we need, since [S1 -> S2
<: T] then follows by [S_Trans]. *)
(** 「補題」: もし [Gamma |- \x:S1.t2 : T] ならば、
型[S2]が存在して [Gamma, x:S1 |- t2 : S2] かつ [S1 -> S2 <: T] となる。
(この補題は「[T]はそれ自身が関数型である」とは言っていないことに注意します。
そうしたいところですが、それは成立しません!)
「証明」:[Gamma]、[x]、[S1]、[t2]、[T]を補題の主張に記述された通りとする。
[Gamma |- \x:S1.t2 : T] の導出についての帰納法で証明する。
[T_Var]と[T_App]の場合はあり得ない。
これらは構文的に関数抽象の形の項に型を与えることはできないからである。
- 導出の最後のステップ使われた規則が[T_Abs]の場合、型[T12]が存在して
[T = S1 -> T12] かつ [Gamma,x:S1 |- t2 : T12] である。
[S2]として[T12]をとると、[S_Refl]より [S1 -> T12 <: S1 -> T12] となり、
求める性質が成立する。
- 導出の最後のステップ使われた規則が[T_Sub]の場合、型[S]が存在して
[S <: T] かつ [Gamma |- \x:S1.t2 : S] となる。
型付け導出の帰納仮定より、型[S2]が存在して
[S1 -> S2 <: S] かつ [Gamma, x:S1 |- t2 : S2] である。
この[S2]を採用すれば、
[S1 -> S2 <: T] であるから[S_Trans]より求める性質が成立する。 *)
Lemma typing_inversion_abs : forall Gamma x S1 t2 T,
has_type Gamma (tm_abs x S1 t2) T ->
(exists S2, subtype (ty_arrow S1 S2) T
/\ has_type (extend Gamma x S1) t2 S2).
Proof with eauto.
intros Gamma x S1 t2 T H.
remember (tm_abs x S1 t2) as t.
has_type_cases (induction H) Case;
inversion Heqt; subst; intros; try solve by inversion.
Case "T_Abs".
exists T12...
Case "T_Sub".
destruct IHhas_type as [S2 [Hsub Hty]]...
Qed.
(* Similarly... *)
(** 同様に... *)
Lemma typing_inversion_var : forall Gamma x T,
has_type Gamma (tm_var x) T ->
exists S,
Gamma x = Some S /\ subtype S T.
Proof with eauto.
intros Gamma x T Hty.
remember (tm_var x) as t.
has_type_cases (induction Hty) Case; intros;
inversion Heqt; subst; try solve by inversion.
Case "T_Var".
exists T...
Case "T_Sub".
destruct IHHty as [U [Hctx HsubU]]... Qed.
Lemma typing_inversion_app : forall Gamma t1 t2 T2,
has_type Gamma (tm_app t1 t2) T2 ->
exists T1,
has_type Gamma t1 (ty_arrow T1 T2) /\
has_type Gamma t2 T1.
Proof with eauto.
intros Gamma t1 t2 T2 Hty.
remember (tm_app t1 t2) as t.
has_type_cases (induction Hty) Case; intros;
inversion Heqt; subst; try solve by inversion.
Case "T_App".
exists T1...
Case "T_Sub".
destruct IHHty as [U1 [Hty1 Hty2]]...
Qed.
Lemma typing_inversion_true : forall Gamma T,
has_type Gamma tm_true T ->
subtype ty_Bool T.
Proof with eauto.
intros Gamma T Htyp. remember tm_true as tu.
has_type_cases (induction Htyp) Case;
inversion Heqtu; subst; intros...
Qed.
Lemma typing_inversion_false : forall Gamma T,
has_type Gamma tm_false T ->
subtype ty_Bool T.
Proof with eauto.
intros Gamma T Htyp. remember tm_false as tu.
has_type_cases (induction Htyp) Case;
inversion Heqtu; subst; intros...
Qed.
Lemma typing_inversion_if : forall Gamma t1 t2 t3 T,
has_type Gamma (tm_if t1 t2 t3) T ->
has_type Gamma t1 ty_Bool
/\ has_type Gamma t2 T
/\ has_type Gamma t3 T.
Proof with eauto.
intros Gamma t1 t2 t3 T Hty.
remember (tm_if t1 t2 t3) as t.
has_type_cases (induction Hty) Case; intros;
inversion Heqt; subst; try solve by inversion.
Case "T_If".
auto.
Case "T_Sub".
destruct (IHHty H0) as [H1 [H2 H3]]...
Qed.
Lemma typing_inversion_unit : forall Gamma T,
has_type Gamma tm_unit T ->
subtype ty_Unit T.
Proof with eauto.
intros Gamma T Htyp. remember tm_unit as tu.
has_type_cases (induction Htyp) Case;
inversion Heqtu; subst; intros...
Qed.
(* The inversion lemmas for typing and for subtyping between arrow
types can be packaged up as a useful "combination lemma" telling
us exactly what we'll actually require below. *)
(** 型付けについての反転補題と関数型の間のサブタイプの反転補題は「結合補題」
("combination lemma")としてまとめることができます。
この補題は以下で実際に必要になるものを示します。 *)
Lemma abs_arrow : forall x S1 s2 T1 T2,
has_type empty (tm_abs x S1 s2) (ty_arrow T1 T2) ->
subtype T1 S1
/\ has_type (extend empty x S1) s2 T2.
Proof with eauto.
intros x S1 s2 T1 T2 Hty.
apply typing_inversion_abs in Hty.
destruct Hty as [S2 [Hsub Hty]].
apply sub_inversion_arrow in Hsub.
destruct Hsub as [U1 [U2 [Heq [Hsub1 Hsub2]]]].
inversion Heq; subst... Qed.
(* ########################################## *)
(* ** Context Invariance *)
(** ** コンテキスト不変性 *)
(* The context invariance lemma follows the same pattern as in the
pure STLC. *)
(** コンテキスト不変性補題は、純粋のSTLCと同じパターンをとります。 *)
Inductive appears_free_in : id -> tm -> Prop :=
| afi_var : forall x,
appears_free_in x (tm_var x)
| afi_app1 : forall x t1 t2,
appears_free_in x t1 -> appears_free_in x (tm_app t1 t2)
| afi_app2 : forall x t1 t2,
appears_free_in x t2 -> appears_free_in x (tm_app t1 t2)
| afi_abs : forall x y T11 t12,
y <> x ->
appears_free_in x t12 ->
appears_free_in x (tm_abs y T11 t12)
| afi_if1 : forall x t1 t2 t3,
appears_free_in x t1 ->
appears_free_in x (tm_if t1 t2 t3)
| afi_if2 : forall x t1 t2 t3,
appears_free_in x t2 ->
appears_free_in x (tm_if t1 t2 t3)
| afi_if3 : forall x t1 t2 t3,
appears_free_in x t3 ->
appears_free_in x (tm_if t1 t2 t3)
.
Hint Constructors appears_free_in.
Lemma context_invariance : forall Gamma Gamma' t S,
has_type Gamma t S ->
(forall x, appears_free_in x t -> Gamma x = Gamma' x) ->
has_type Gamma' t S.
Proof with eauto.
intros. generalize dependent Gamma'.
has_type_cases (induction H) Case;
intros Gamma' Heqv...
Case "T_Var".
apply T_Var... rewrite <- Heqv...
Case "T_Abs".
apply T_Abs... apply IHhas_type. intros x0 Hafi.
unfold extend. remember (beq_id x x0) as e.
destruct e...
Case "T_App".
apply T_App with T1...
Case "T_If".
apply T_If...
Qed.
Lemma free_in_context : forall x t T Gamma,
appears_free_in x t ->
has_type Gamma t T ->
exists T', Gamma x = Some T'.
Proof with eauto.
intros x t T Gamma Hafi Htyp.
has_type_cases (induction Htyp) Case;
subst; inversion Hafi; subst...
Case "T_Abs".
destruct (IHHtyp H4) as [T Hctx]. exists T.
unfold extend in Hctx. apply not_eq_beq_id_false in H2.
rewrite H2 in Hctx... Qed.
(* ########################################## *)
(* ** Substitution *)
(** ** 置換 *)
(* The _substitution lemma_ is proved along the same lines as for the
pure STLC. The only significant change is that there are several
places where, instead of the built-in [inversion] tactic, we use
the inversion lemmas that we proved above to extract structural
information from assumptions about the well-typedness of
subterms. *)
(** 置換補題(_substitution lemma_)は純粋なSTLCと同じ流れで証明されます。
唯一の大きな変更点は、いくつかの場所で、
部分項が型を持つことについての仮定から構造的情報を抽出するために、
Coqの[inversion]タクティックを使う代わりに上で証明した反転補題を使うことです。 *)
Lemma substitution_preserves_typing : forall Gamma x U v t S,
has_type (extend Gamma x U) t S ->
has_type empty v U ->
has_type Gamma (subst v x t) S.
Proof with eauto.
intros Gamma x U v t S Htypt Htypv.
generalize dependent S. generalize dependent Gamma.
tm_cases (induction t) Case; intros; simpl.
Case "tm_var".
rename i into y.
destruct (typing_inversion_var _ _ _ Htypt)
as [T [Hctx Hsub]].
unfold extend in Hctx.
remember (beq_id x y) as e. destruct e...
SCase "x=y".
apply beq_id_eq in Heqe. subst.
inversion Hctx; subst. clear Hctx.
apply context_invariance with empty...
intros x Hcontra.
destruct (free_in_context _ _ S empty Hcontra)
as [T' HT']...
inversion HT'.
Case "tm_app".
destruct (typing_inversion_app _ _ _ _ Htypt)
as [T1 [Htypt1 Htypt2]].
eapply T_App...
Case "tm_abs".
rename i into y. rename t into T1.
destruct (typing_inversion_abs _ _ _ _ _ Htypt)
as [T2 [Hsub Htypt2]].
apply T_Sub with (ty_arrow T1 T2)... apply T_Abs...
remember (beq_id x y) as e. destruct e.
SCase "x=y".
eapply context_invariance...
apply beq_id_eq in Heqe. subst.
intros x Hafi. unfold extend.
destruct (beq_id y x)...
SCase "x<>y".
apply IHt. eapply context_invariance...
intros z Hafi. unfold extend.
remember (beq_id y z) as e0. destruct e0...
apply beq_id_eq in Heqe0. subst.
rewrite <- Heqe...
Case "tm_true".
assert (subtype ty_Bool S)
by apply (typing_inversion_true _ _ Htypt)...
Case "tm_false".
assert (subtype ty_Bool S)
by apply (typing_inversion_false _ _ Htypt)...
Case "tm_if".
assert (has_type (extend Gamma x U) t1 ty_Bool
/\ has_type (extend Gamma x U) t2 S
/\ has_type (extend Gamma x U) t3 S)
by apply (typing_inversion_if _ _ _ _ _ Htypt).
destruct H as [H1 [H2 H3]].
apply IHt1 in H1. apply IHt2 in H2. apply IHt3 in H3.
auto.
Case "tm_unit".
assert (subtype ty_Unit S)
by apply (typing_inversion_unit _ _ Htypt)...
Qed.
(* ########################################## *)
(* ** Preservation *)
(** ** 保存 *)
(* The proof of preservation now proceeds pretty much as in earlier
chapters, using the substitution lemma at the appropriate point
and again using inversion lemmas from above to extract structural
information from typing assumptions. *)
(** (型の)保存の証明は以前の章とほとんど同じです。適切な場所で置換補題を使い、
型付け仮定から構造的情報を抽出するために上述の反転補題をまた使います。
*)
(* _Theorem_ (Preservation): If [t], [t'] are terms and [T] is a type
such that [empty |- t : T] and [t ==> t'], then [empty |- t' :
T].
_Proof_: Let [t] and [T] be given such that [empty |- t : T]. We
go by induction on the structure of this typing derivation,
leaving [t'] general. The cases [T_Abs], [T_Unit], [T_True], and
[T_False] cases are vacuous because abstractions and constants
don't step. Case [T_Var] is vacuous as well, since the context is
empty.
- If the final step of the derivation is by [T_App], then there
are terms [t1] [t2] and types [T1] [T2] such that [t = t1 t2],
[T = T2], [empty |- t1 : T1 -> T2] and [empty |- t2 : T1].
By inspection of the definition of the step relation, there are
three ways [t1 t2] can step. Cases [ST_App1] and [ST_App2]
follow immediately by the induction hypotheses for the typing
subderivations and a use of [T_App].
Suppose instead [t1 t2] steps by [ST_AppAbs]. Then [t1 =
\x:S.t12] for some type [S] and term [t12], and [t' =
[t2/x]t12].
By lemma [abs_arrow], we have [T1 <: S] and [x:S1 |- s2 : T2].
It then follows by the substitution lemma
([substitution_preserves_typing]) that [empty |- [t2/x]
t12 : T2] as desired.
- If the final step of the derivation uses rule [T_If], then
there are terms [t1], [t2], and [t3] such that [t = if t1 then
t2 else t3], with [empty |- t1 : Bool] and with [empty |- t2 :
T] and [empty |- t3 : T]. Moreover, by the induction
hypothesis, if [t1] steps to [t1'] then [empty |- t1' : Bool].
There are three cases to consider, depending on which rule was
used to show [t ==> t'].
- If [t ==> t'] by rule [ST_If], then [t' = if t1' then t2
else t3] with [t1 ==> t1']. By the induction hypothesis,
[empty |- t1' : Bool], and so [empty |- t' : T] by [T_If].
- If [t ==> t'] by rule [ST_IfTrue] or [ST_IfFalse], then
either [t' = t2] or [t' = t3], and [empty |- t' : T]
follows by assumption.
- If the final step of the derivation is by [T_Sub], then there
is a type [S] such that [S <: T] and [empty |- t : S]. The
result is immediate by the induction hypothesis for the typing
subderivation and an application of [T_Sub]. [] *)
(** 「定理」(保存)： [t]、[t']が項で[T]が型であり、[empty |- t : T] かつ [t ==> t']
ならば、[empty |- t' : T] である。
「証明」:[t] と [T] が [empty |- t : T] であるとする。
証明は、[t']を特化しないまま型付け導出の構造に関する帰納法で進める。
(最後の規則が)[T_Abs]、[T_Unit]、[T_True]、[T_False]の場合は考えなくて良い。
なぜなら関数抽象と定数はステップを進めないからである。
[T_Var]も考えなくて良い。なぜならコンテキストが空だからである。
- もし導出の最後のステップの規則が[T_App]ならば、
項[t1] [t2] と型 [T1] [T2] が存在して、[t = t1 t2]、[T = T2]、
[empty |- t1 : T1 -> T2]、[empty |- t2 : T1] である。
ステップ関係の定義から、[t1 t2] がステップする方法は3通りである。
[ST_App1]と[ST_App2]の場合、
型付け導出の帰納仮定と[T_App]より求める結果がすぐに得られる。
[t1 t2] のステップが [ST_AppAbs] によるとする。
するとある型[S]と項[t12]について [t1 = \x:S.t12] であり、かつ
[t' = [t2/x]t12] である。
補題[abs_arrow]より、[T1 <: S] かつ [x:S1 |- s2 : T2] となる。
すると置換補題([substitution_preserves_typing])より、
[empty |- [t2/x]t12 : T2] となるがこれが求める結果である。
- もし導出の最後のステップで使う規則が[T_If]ならば、
項[t1]、[t2]、[t3]が存在して [t = if t1 then t2 else t3] かつ
[empty |- t1 : Bool] かつ [empty |- t2 : T] かつ [empty |- t3 : T]
となる。さらに帰納法の仮定より、もし[t1]がステップして[t1']に進むならば
[empty |- t1' : Bool] である。
[t ==> t'] を示すために使われた規則によって、3つの場合がある。
- [t ==> t'] が規則[ST_If]による場合、
[t' = if t1' then t2 else t3] かつ [t1 ==> t1'] となる。
帰納法の仮定より [empty |- t1' : Bool] となり、
これから[T_If]より [empty |- t' : T] となる。
- [t ==> t'] が規則[ST_IfTrue]または[ST_IfFalse]による場合、
[t' = t2] または [t' = t3] であり、仮定から [empty |- t' : T]
となる。
- もし導出の最後のステップで使う規則が[T_Sub]ならば、
型[S]が存在して [S <: T] かつ [empty |- t : S] となる。
型付け導出についての帰納法の仮定と[T_Sub]の適用から結果がすぐに得られる。 [] *)
Theorem preservation : forall t t' T,
has_type empty t T ->
t ==> t' ->
has_type empty t' T.
Proof with eauto.
intros t t' T HT.
remember empty as Gamma. generalize dependent HeqGamma.
generalize dependent t'.
has_type_cases (induction HT) Case;
intros t' HeqGamma HE; subst; inversion HE; subst...
Case "T_App".
inversion HE; subst...
SCase "ST_AppAbs".
destruct (abs_arrow _ _ _ _ _ HT1) as [HA1 HA2].
apply substitution_preserves_typing with T...
Qed.
(* ###################################################### *)
(* ** Exercises on Typing *)
(** ** 型付けの練習問題 *)
(* **** Exercise: 2 stars (variations) *)
(** **** 練習問題: ★★ (variations) *)
(* Each part of this problem suggests a different way of
changing the definition of the STLC with Unit and
subtyping. (These changes are not cumulative: each part
starts from the original language.) In each part, list which
properties (Progress, Preservation, both, or neither) become
false. If a property becomes false, give a counterexample.
- Suppose we add the following typing rule:
[[[
Gamma |- t : S1->S2
S1 <: T1 T1 <: S1 S2 <: T2
----------------------------------- (T_Funny1)
Gamma |- t : T1->T2
]]]
- Suppose we add the following reduction rule:
[[[
------------------ (ST_Funny21)
unit ==> (\x:Top. x)
]]]
- Suppose we add the following subtyping rule:
[[[
-------------- (S_Funny3)
Unit <: Top->Top
]]]
- Suppose we add the following subtyping rule:
[[[
-------------- (S_Funny4)
Top->Top <: Unit
]]]
- Suppose we add the following evaluation rule:
[[[
----------------- (ST_Funny5)
(unit t) ==> (t unit)
]]]
- Suppose we add the same evaluation rule _and_ a new typing rule:
[[[
----------------- (ST_Funny5)
(unit t) ==> (t unit)
---------------------- (T_Funny6)
empty |- Unit : Top->Top
]]]
- Suppose we _change_ the arrow subtyping rule to:
[[[
S1 <: T1 S2 <: T2
----------------------- (S_Arrow')
S1->S2 <: T1->T2
]]]
[]
*)
(** この問題の各部分は、Unitとサブタイプを持つSTLCの定義を変更する別々の方法を導きます。
(これらの変更は累積的ではありません。各部分はいずれも元々の言語から始まります。)
各部分について、(進行、保存の)性質のうち偽になるものをリストアップしなさい。
偽になる性質について、反例を示しなさい。
- 次の型付け規則を追加する:
[[
Gamma |- t : S1->S2
S1 <: T1 T1 <: S1 S2 <: T2
----------------------------------- (T_Funny1)
Gamma |- t : T1->T2
]]
- 次の簡約規則を追加する:
[[
------------------ (ST_Funny21)
unit ==> (\x:Top. x)
]]
- 次のサブタイプ規則を追加する:
[[
-------------- (S_Funny3)
Unit <: Top->Top
]]
- 次のサブタイプ規則を追加する:
[[
-------------- (S_Funny4)
Top->Top <: Unit
]]
- 次の評価規則を追加する:
[[
----------------- (ST_Funny5)
(unit t) ==> (t unit)
]]
- 上と同じ評価規則と新たな型付け規則を追加する:
[[
----------------- (ST_Funny5)
(unit t) ==> (t unit)
---------------------- (T_Funny6)
empty |- Unit : Top->Top
]]
- 関数型のサブタイプ規則を次のものに変更する:
[[
S1 <: T1 S2 <: T2
----------------------- (S_Arrow')
S1->S2 <: T1->T2
]]
[]
*)
(* ###################################################################### *)
(* * Exercise: Adding Products *)
(** * 練習問題: 直積の追加 *)
(* **** Exercise: 4 stars, optional (products) *)
(** **** 練習問題: ★★★★, optional (products) *)
(* Adding pairs, projections, and product types to the system we have
defined is a relatively straightforward matter. Carry out this
extension:
- Add constructors for pairs, first and second projections, and
product types to the definitions of [ty] and [tm]. (Don't
forget to add corresponding cases to [ty_cases] and [tm_cases].)
- Extend the well-formedness relation in the obvious way.
- Extend the operational semantics with the same reduction rules
as in the last chapter.
- Extend the subtyping relation with this rule:
[[[
S1 <: T1 S2 <: T2
--------------------- (Sub_Prod)
S1 * S2 <: T1 * T2
]]]
- Extend the typing relation with the same rules for pairs and
projections as in the last chapter.
- Extend the proofs of progress, preservation, and all their
supporting lemmas to deal with the new constructs. (You'll also
need to add some completely new lemmas.) []
*)
(** 定義したシステムに対、射影、直積型を追加することは比較的簡単な問題です。
次の拡張を行いなさい:
- [ty]と[tm]の定義に、対のコンストラクタ、第1射影、第2射影、直積型を追加しなさい。
([ty_cases]と[tm_cases]に対応する場合を追加することを忘れないこと。)
- 自明な方法で、well-formedness 関係を拡張しなさい。
- 操作的意味に前の章と同様の簡約規則を拡張しなさい。
- サブタイプ関係に次の規則を拡張しなさい:
[[
S1 <: T1 S2 <: T2
--------------------- (Sub_Prod)
S1 * S2 <: T1 * T2
]]
- 型付け関係に、前の章と同様の、対と射影の規則を拡張しなさい。
- 進行および保存の証明、およびそのための補題を、
新しい構成要素を扱うように拡張しなさい。
(完全に新しいある補題を追加する必要もあるでしょう。) []
*)
|
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_b2s_aw_channel #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of ID signals.
// Range: >= 1.
parameter integer C_ID_WIDTH = 4,
// Width of AxADDR
// Range: 32.
parameter integer C_AXI_ADDR_WIDTH = 32
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// AXI Slave Interface
// Slave Interface System Signals
input wire clk ,
input wire reset ,
// Slave Interface Write Address Ports
input wire [C_ID_WIDTH-1:0] s_awid ,
input wire [C_AXI_ADDR_WIDTH-1:0] s_awaddr ,
input wire [7:0] s_awlen ,
input wire [2:0] s_awsize ,
input wire [1:0] s_awburst ,
input wire s_awvalid ,
output wire s_awready ,
output wire m_awvalid ,
output wire [C_AXI_ADDR_WIDTH-1:0] m_awaddr ,
input wire m_awready ,
// Connections to/from axi_protocol_converter_v2_1_b2s_b_channel module
output wire b_push ,
output wire [C_ID_WIDTH-1:0] b_awid ,
output wire [7:0] b_awlen ,
input wire b_full
);
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
wire next ;
wire next_pending ;
wire a_push;
wire incr_burst;
reg [C_ID_WIDTH-1:0] s_awid_r;
reg [7:0] s_awlen_r;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// Translate the AXI transaction to the MC transaction(s)
axi_protocol_converter_v2_1_b2s_cmd_translator #
(
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH )
)
cmd_translator_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.s_axaddr ( s_awaddr ) ,
.s_axlen ( s_awlen ) ,
.s_axsize ( s_awsize ) ,
.s_axburst ( s_awburst ) ,
.s_axhandshake ( s_awvalid & a_push ) ,
.m_axaddr ( m_awaddr ) ,
.incr_burst ( incr_burst ) ,
.next ( next ) ,
.next_pending ( next_pending )
);
axi_protocol_converter_v2_1_b2s_wr_cmd_fsm aw_cmd_fsm_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.s_awready ( s_awready ) ,
.s_awvalid ( s_awvalid ) ,
.m_awvalid ( m_awvalid ) ,
.m_awready ( m_awready ) ,
.next ( next ) ,
.next_pending ( next_pending ) ,
.b_push ( b_push ) ,
.b_full ( b_full ) ,
.a_push ( a_push )
);
assign b_awid = s_awid_r;
assign b_awlen = s_awlen_r;
always @(posedge clk) begin
s_awid_r <= s_awid ;
s_awlen_r <= s_awlen ;
end
endmodule
`default_nettype wire
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Thu May 25 21:06:44 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_ov7670_vga_0_0/system_ov7670_vga_0_0_stub.v
// Design : system_ov7670_vga_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "ov7670_vga,Vivado 2016.4" *)
module system_ov7670_vga_0_0(clk_x2, active, data, rgb)
/* synthesis syn_black_box black_box_pad_pin="clk_x2,active,data[7:0],rgb[15:0]" */;
input clk_x2;
input active;
input [7:0]data;
output [15:0]rgb;
endmodule
|
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: one_new2.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module one_new2 (
address,
clock,
q);
input [9:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../newnums2/one_new2.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../newnums2/one_new2.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL one_new2.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL one_new2.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL one_new2.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL one_new2.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL one_new2_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL one_new2_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
module test(input wire load, in,
output reg out1, out2);
(* ivl_combinational *)
always @* begin
out1 = 0;
if (load) begin
out1 = in;
out2 = in;
end else begin
out2 = ~in;
end
end
endmodule // test
module test_bench;
reg load;
reg val;
wire out1, out2;
test DUT(.load(load), .in(val), .out1(out1), .out2(out2));
(* ivl_synthesis_off *)
initial begin
val = 0;
load = 1;
#1 ;
if (out1 !== 0 || out2 !== 0) begin
$display("FAILED -- load=%b, val=%b, out1=%b, out2=%b", load, val, out1, out2);
$finish;
end
val = 1;
#1 ;
if (out1 !== 1 || out2 !== 1) begin
$display("FAILED -- load=%b, val=%b, out1=%b, out2=%b", load, val, out1, out2);
$finish;
end
load = 0;
#1 ;
if (out1 !== 0 || out2 !== 0) begin
$display("FAILED -- load=%b, val=%b, out1=%b, out2=%b", load, val, out1, out2);
$finish;
end
val = 0;
#1 ;
if (out1 !== 0 || out2 !== 1) begin
$display("FAILED -- load=%b, val=%b, out1=%b, out2=%b", load, val, out1, out2);
$finish;
end
$display("PASSED");
end // initial begin
endmodule // test_bench
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:04:14 06/30/2012
// Design Name:
// Module Name: MIO_BUS
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module MIO_BUS(input clk,
input rst,
input[3:0]BTN,
input[15:0]SW,
input mem_w,
input[31:0]Cpu_data2bus, //data from CPU
input[31:0]addr_bus,
input[31:0]ram_data_out,
input[15:0]led_out,
input[31:0]counter_out,
input counter0_out,
input counter1_out,
input counter2_out,
output reg[31:0]Cpu_data4bus, //write to CPU
output reg[31:0]ram_data_in, //from CPU write to Memory
output reg[9:0]ram_addr, //Memory Address signals
output reg data_ram_we,
output reg GPIOf0000000_we,
output reg GPIOe0000000_we,
output reg counter_we,
output reg[31:0]Peripheral_in
);
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : PCIeGen2x8If128_pcie2_top.v
// Version : 3.2
//--------------------------------------------------------------------------------
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module PCIeGen2x8If128_pcie2_top # (
parameter c_component_name ="pcie_7x_v3_2_1",
parameter dev_port_type ="0000",
parameter c_dev_port_type ="0",
parameter c_header_type ="00",
parameter c_upstream_facing ="TRUE",
parameter max_lnk_wdt = "000100",
parameter max_lnk_spd = "1",
parameter c_gen1 = 1'b0,
parameter c_int_width = 64,
parameter pci_exp_int_freq = 2,
parameter c_pcie_fast_config = 0,
parameter bar_0 = "FFFFFF80",
parameter bar_1 = "00000000",
parameter bar_2 = "00000000",
parameter bar_3 = "00000000",
parameter bar_4 = "00000000",
parameter bar_5 = "00000000",
parameter xrom_bar = "00000000",
parameter cost_table = 1,
parameter ven_id = "10EE",
parameter dev_id = "7028",
parameter rev_id = "00",
parameter subsys_ven_id = "10EE",
parameter subsys_id = "0007",
parameter class_code = "058000",
parameter cardbus_cis_ptr = "00000000",
parameter cap_ver = "2",
parameter c_pcie_cap_slot_implemented = "FALSE",
parameter mps = "010",
parameter cmps = "2",
parameter ext_tag_fld_sup = "FALSE",
parameter c_dev_control_ext_tag_default = "FALSE",
parameter phantm_func_sup = "00",
parameter c_phantom_functions = "0",
parameter ep_l0s_accpt_lat = "000",
parameter c_ep_l0s_accpt_lat = "0",
parameter ep_l1_accpt_lat = "111",
parameter c_ep_l1_accpt_lat = "7",
parameter c_cpl_timeout_disable_sup = "FALSE",
parameter c_cpl_timeout_range = "0010",
parameter c_cpl_timeout_ranges_sup = "2",
parameter c_buf_opt_bma = "TRUE",
parameter c_perf_level_high = "TRUE",
parameter c_tx_last_tlp = "29",
parameter c_rx_ram_limit = "7FF",
parameter c_fc_ph = "32",
parameter c_fc_pd = "437",
parameter c_fc_nph = "12",
parameter c_fc_npd = "24",
parameter c_fc_cplh = "36",
parameter c_fc_cpld = "461",
parameter c_cpl_inf = "TRUE",
parameter c_cpl_infinite = "TRUE",
parameter c_surprise_dn_err_cap = "FALSE",
parameter c_dll_lnk_actv_cap = "FALSE",
parameter c_lnk_bndwdt_notif = "FALSE",
parameter c_external_clocking = "TRUE",
parameter c_trgt_lnk_spd = "0",
parameter c_hw_auton_spd_disable = "FALSE",
parameter c_de_emph = "FALSE",
parameter slot_clk = "TRUE",
parameter c_rcb = "0",
parameter c_root_cap_crs = "FALSE",
parameter c_slot_cap_attn_butn = "FALSE",
parameter c_slot_cap_attn_ind = "FALSE",
parameter c_slot_cap_pwr_ctrl = "FALSE",
parameter c_slot_cap_pwr_ind = "FALSE",
parameter c_slot_cap_hotplug_surprise = "FALSE",
parameter c_slot_cap_hotplug_cap = "FALSE",
parameter c_slot_cap_mrl = "FALSE",
parameter c_slot_cap_elec_interlock = "FALSE",
parameter c_slot_cap_no_cmd_comp_sup = "FALSE",
parameter c_slot_cap_pwr_limit_value = "0",
parameter c_slot_cap_pwr_limit_scale = "0",
parameter c_slot_cap_physical_slot_num = "0",
parameter intx = "TRUE",
parameter int_pin = "1",
parameter c_msi_cap_on = "TRUE",
parameter c_pm_cap_next_ptr = "48",
parameter c_msi_64b_addr = "TRUE",
parameter c_msi = "0",
parameter c_msi_mult_msg_extn = "0",
parameter c_msi_per_vctr_mask_cap = "FALSE",
parameter c_msix_cap_on = "FALSE",
parameter c_msix_next_ptr = "00",
parameter c_pcie_cap_next_ptr = "00",
parameter c_msix_table_size = "000",
parameter c_msix_table_offset = "0",
parameter c_msix_table_bir = "0",
parameter c_msix_pba_offset = "0",
parameter c_msix_pba_bir = "0",
parameter dsi = "0",
parameter c_dsi_bool = "FALSE",
parameter d1_sup = "0",
parameter c_d1_support = "FALSE",
parameter d2_sup = "0",
parameter c_d2_support = "FALSE",
parameter pme_sup = "0F",
parameter c_pme_support = "0F",
parameter no_soft_rst = "TRUE",
parameter pwr_con_d0_state = "00",
parameter con_scl_fctr_d0_state = "0",
parameter pwr_con_d1_state = "00",
parameter con_scl_fctr_d1_state = "0",
parameter pwr_con_d2_state = "00",
parameter con_scl_fctr_d2_state = "0",
parameter pwr_con_d3_state = "00",
parameter con_scl_fctr_d3_state = "0",
parameter pwr_dis_d0_state = "00",
parameter dis_scl_fctr_d0_state = "0",
parameter pwr_dis_d1_state = "00",
parameter dis_scl_fctr_d1_state = "0",
parameter pwr_dis_d2_state = "00",
parameter dis_scl_fctr_d2_state = "0",
parameter pwr_dis_d3_state = "00",
parameter dis_scl_fctr_d3_state = "0",
parameter c_dsn_cap_enabled = "TRUE",
parameter c_dsn_base_ptr = "100",
parameter c_vc_cap_enabled = "FALSE",
parameter c_vc_base_ptr = "000",
parameter c_vc_cap_reject_snoop = "FALSE",
parameter c_vsec_cap_enabled = "FALSE",
parameter c_vsec_base_ptr = "000",
parameter c_vsec_next_ptr = "000",
parameter c_dsn_next_ptr = "000",
parameter c_vc_next_ptr = "000",
parameter c_pci_cfg_space_addr = "3F",
parameter c_ext_pci_cfg_space_addr = "3FF",
parameter c_last_cfg_dw = "10C",
parameter c_enable_msg_route = "00000000000",
parameter bram_lat = "0",
parameter c_rx_raddr_lat = "0",
parameter c_rx_rdata_lat = "2",
parameter c_rx_write_lat = "0",
parameter c_tx_raddr_lat = "0",
parameter c_tx_rdata_lat = "2",
parameter c_tx_write_lat = "0",
parameter c_ll_ack_timeout_enable = "FALSE",
parameter c_ll_ack_timeout_function = "0",
parameter c_ll_ack_timeout = "0000",
parameter c_ll_replay_timeout_enable = "FALSE",
parameter c_ll_replay_timeout_func = "1",
parameter c_ll_replay_timeout = "0000",
parameter c_dis_lane_reverse = "TRUE",
parameter c_upconfig_capable = "TRUE",
parameter c_disable_scrambling = "FALSE",
parameter c_disable_tx_aspm_l0s = "0",
parameter c_rev_gt_order = "FALSE",
parameter c_pcie_dbg_ports = "FALSE",
parameter pci_exp_ref_freq = "0",
parameter c_xlnx_ref_board = "NONE",
parameter c_pcie_blk_locn = "0",
parameter c_ur_atomic = "FALSE",
parameter c_dev_cap2_atomicop32_completer_supported = "FALSE",
parameter c_dev_cap2_atomicop64_completer_supported = "FALSE",
parameter c_dev_cap2_cas128_completer_supported = "FALSE",
parameter c_dev_cap2_tph_completer_supported = "00",
parameter c_dev_cap2_ari_forwarding_supported = "FALSE",
parameter c_dev_cap2_atomicop_routing_supported = "FALSE",
parameter c_link_cap_aspm_optionality = "FALSE",
parameter c_aer_cap_on = "FALSE",
parameter c_aer_base_ptr = "000",
parameter c_aer_cap_nextptr = "000",
parameter c_aer_cap_ecrc_check_capable = "FALSE",
parameter c_aer_cap_multiheader = "FALSE",
parameter c_aer_cap_permit_rooterr_update = "FALSE",
parameter c_rbar_cap_on = "FALSE",
parameter c_rbar_base_ptr = "000",
parameter c_rbar_cap_nextptr = "000",
parameter c_rbar_num = "0",
parameter c_rbar_cap_sup0 = "00001",
parameter c_rbar_cap_index0 = "0",
parameter c_rbar_cap_control_encodedbar0 = "00",
parameter c_rbar_cap_sup1 = "00001",
parameter c_rbar_cap_index1 = "0",
parameter c_rbar_cap_control_encodedbar1 = "00",
parameter c_rbar_cap_sup2 = "00001",
parameter c_rbar_cap_index2 = "0",
parameter c_rbar_cap_control_encodedbar2 = "00",
parameter c_rbar_cap_sup3 = "00001",
parameter c_rbar_cap_index3 = "0",
parameter c_rbar_cap_control_encodedbar3 = "00",
parameter c_rbar_cap_sup4 = "00001",
parameter c_rbar_cap_index4 = "0",
parameter c_rbar_cap_control_encodedbar4 = "00",
parameter c_rbar_cap_sup5 = "00001",
parameter c_rbar_cap_index5 = "0",
parameter c_rbar_cap_control_encodedbar5 = "00",
parameter c_recrc_check = "0",
parameter c_recrc_check_trim = "FALSE",
parameter c_disable_rx_poisoned_resp = "FALSE",
parameter c_trn_np_fc = "TRUE",
parameter c_ur_inv_req = "TRUE",
parameter c_ur_prs_response = "TRUE",
parameter c_silicon_rev = "1",
parameter c_aer_cap_optional_err_support = "000000",
parameter PIPE_SIM = "FALSE",
parameter PCIE_EXT_CLK = "TRUE",
parameter PCIE_EXT_GT_COMMON = "FALSE",
parameter EXT_CH_GT_DRP = "TRUE",
parameter TRANSCEIVER_CTRL_STATUS_PORTS = "FALSE",
parameter SHARED_LOGIC_IN_CORE = "FALSE",
parameter PL_INTERFACE = "TRUE",
parameter CFG_MGMT_IF = "TRUE",
parameter CFG_CTL_IF = "TRUE",
parameter CFG_STATUS_IF = "TRUE",
parameter RCV_MSG_IF = "TRUE",
parameter CFG_FC_IF = "TRUE" ,
parameter ERR_REPORTING_IF = "TRUE",
parameter c_aer_cap_ecrc_gen_capable = "FALSE",
parameter EXT_PIPE_INTERFACE = "FALSE",
parameter EXT_STARTUP_PRIMITIVE = "FALSE",
parameter integer LINK_CAP_MAX_LINK_WIDTH = 6'h8,
parameter integer C_DATA_WIDTH = 64,
parameter integer KEEP_WIDTH = C_DATA_WIDTH / 8,
parameter PCIE_ASYNC_EN = "FALSE"
)
(
//----------------------------------------------------------------------------------------------------------------//
// 1. PCI Express (pci_exp) Interface //
//----------------------------------------------------------------------------------------------------------------//
// Tx
output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_txn,
output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_txp,
// Rx
input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_rxn,
input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_rxp,
//----------------------------------------------------------------------------------------------------------------//
// 2. Clock & GT COMMON Sharing Interface //
//----------------------------------------------------------------------------------------------------------------//
// Shared Logic Internal
output int_pclk_out_slave,
output int_pipe_rxusrclk_out,
output [(LINK_CAP_MAX_LINK_WIDTH-1):0] int_rxoutclk_out,
output int_dclk_out,
output int_userclk1_out,
output int_userclk2_out,
output int_oobclk_out,
output int_mmcm_lock_out,
output [1:0] int_qplllock_out,
output [1:0] int_qplloutclk_out,
output [1:0] int_qplloutrefclk_out,
input [(LINK_CAP_MAX_LINK_WIDTH-1):0] int_pclk_sel_slave,
// Shared Logic External - Clocks
input pipe_pclk_in,
input pipe_rxusrclk_in,
input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pipe_rxoutclk_in,
input pipe_dclk_in,
input pipe_userclk1_in,
input pipe_userclk2_in,
input pipe_oobclk_in,
input pipe_mmcm_lock_in,
output pipe_txoutclk_out,
output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pipe_rxoutclk_out,
output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pipe_pclk_sel_out,
output pipe_gen3_out,
// Shared Logic External - GT COMMON
input [11:0] qpll_drp_crscode,
input [17:0] qpll_drp_fsm,
input [1:0] qpll_drp_done,
input [1:0] qpll_drp_reset,
input [1:0] qpll_qplllock,
input [1:0] qpll_qplloutclk,
input [1:0] qpll_qplloutrefclk,
output qpll_qplld,
output [1:0] qpll_qpllreset,
output qpll_drp_clk,
output qpll_drp_rst_n,
output qpll_drp_ovrd,
output qpll_drp_gen3,
output qpll_drp_start,
//----------------------------------------------------------------------------------------------------------------//
// 3. AXI-S Interface //
//----------------------------------------------------------------------------------------------------------------//
// Common
output user_clk_out,
output user_reset_out,
output user_lnk_up,
output user_app_rdy,
// AXI TX
//-----------
output [5:0] tx_buf_av,
output tx_err_drop,
output tx_cfg_req,
input [C_DATA_WIDTH-1:0] s_axis_tx_tdata,
input s_axis_tx_tvalid,
output s_axis_tx_tready,
input [KEEP_WIDTH-1:0] s_axis_tx_tkeep,
input s_axis_tx_tlast,
input [3:0] s_axis_tx_tuser,
input tx_cfg_gnt,
// AXI RX
//-----------
output [C_DATA_WIDTH-1:0] m_axis_rx_tdata,
output m_axis_rx_tvalid,
input m_axis_rx_tready,
output [KEEP_WIDTH-1:0] m_axis_rx_tkeep,
output m_axis_rx_tlast,
output [21:0] m_axis_rx_tuser,
input rx_np_ok,
input rx_np_req,
// Flow Control
output [11:0] fc_cpld,
output [7:0] fc_cplh,
output [11:0] fc_npd,
output [7:0] fc_nph,
output [11:0] fc_pd,
output [7:0] fc_ph,
input [2:0] fc_sel,
//----------------------------------------------------------------------------------------------------------------//
// 4. Configuration (CFG) Interface //
//----------------------------------------------------------------------------------------------------------------//
//------------------------------------------------//
// EP and RP //
//------------------------------------------------//
output [31:0] cfg_mgmt_do,
output cfg_mgmt_rd_wr_done,
output [15:0] cfg_status,
output [15:0] cfg_command,
output [15:0] cfg_dstatus,
output [15:0] cfg_dcommand,
output [15:0] cfg_lstatus,
output [15:0] cfg_lcommand,
output [15:0] cfg_dcommand2,
output [2:0] cfg_pcie_link_state,
output cfg_pmcsr_pme_en,
output [1:0] cfg_pmcsr_powerstate,
output cfg_pmcsr_pme_status,
output cfg_received_func_lvl_rst,
// Management Interface
input [31:0] cfg_mgmt_di,
input [3:0] cfg_mgmt_byte_en,
input [9:0] cfg_mgmt_dwaddr,
input cfg_mgmt_wr_en,
input cfg_mgmt_rd_en,
input cfg_mgmt_wr_readonly,
// Error Reporting Interface
input cfg_err_ecrc,
input cfg_err_ur,
input cfg_err_cpl_timeout,
input cfg_err_cpl_unexpect,
input cfg_err_cpl_abort,
input cfg_err_posted,
input cfg_err_cor,
input cfg_err_atomic_egress_blocked,
input cfg_err_internal_cor,
input cfg_err_malformed,
input cfg_err_mc_blocked,
input cfg_err_poisoned,
input cfg_err_norecovery,
input [47:0] cfg_err_tlp_cpl_header,
output cfg_err_cpl_rdy,
input cfg_err_locked,
input cfg_err_acs,
input cfg_err_internal_uncor,
input cfg_trn_pending,
input cfg_pm_halt_aspm_l0s,
input cfg_pm_halt_aspm_l1,
input cfg_pm_force_state_en,
input [1:0] cfg_pm_force_state,
input [63:0] cfg_dsn,
output cfg_msg_received,
output [15:0] cfg_msg_data,
//------------------------------------------------//
// EP Only //
//------------------------------------------------//
// Interrupt Interface Signals
input cfg_interrupt,
output cfg_interrupt_rdy,
input cfg_interrupt_assert,
input [7:0] cfg_interrupt_di,
output [7:0] cfg_interrupt_do,
output [2:0] cfg_interrupt_mmenable,
output cfg_interrupt_msienable,
output cfg_interrupt_msixenable,
output cfg_interrupt_msixfm,
input cfg_interrupt_stat,
input [4:0] cfg_pciecap_interrupt_msgnum,
output cfg_to_turnoff,
input cfg_turnoff_ok,
output [7:0] cfg_bus_number,
output [4:0] cfg_device_number,
output [2:0] cfg_function_number,
input cfg_pm_wake,
output cfg_msg_received_pm_as_nak,
output cfg_msg_received_setslotpowerlimit,
//------------------------------------------------//
// RP Only //
//------------------------------------------------//
input cfg_pm_send_pme_to,
input [7:0] cfg_ds_bus_number,
input [4:0] cfg_ds_device_number,
input [2:0] cfg_ds_function_number,
input cfg_mgmt_wr_rw1c_as_rw,
output cfg_bridge_serr_en,
output cfg_slot_control_electromech_il_ctl_pulse,
output cfg_root_control_syserr_corr_err_en,
output cfg_root_control_syserr_non_fatal_err_en,
output cfg_root_control_syserr_fatal_err_en,
output cfg_root_control_pme_int_en,
output cfg_aer_rooterr_corr_err_reporting_en,
output cfg_aer_rooterr_non_fatal_err_reporting_en,
output cfg_aer_rooterr_fatal_err_reporting_en,
output cfg_aer_rooterr_corr_err_received,
output cfg_aer_rooterr_non_fatal_err_received,
output cfg_aer_rooterr_fatal_err_received,
output cfg_msg_received_err_cor,
output cfg_msg_received_err_non_fatal,
output cfg_msg_received_err_fatal,
output cfg_msg_received_pm_pme,
output cfg_msg_received_pme_to_ack,
output cfg_msg_received_assert_int_a,
output cfg_msg_received_assert_int_b,
output cfg_msg_received_assert_int_c,
output cfg_msg_received_assert_int_d,
output cfg_msg_received_deassert_int_a,
output cfg_msg_received_deassert_int_b,
output cfg_msg_received_deassert_int_c,
output cfg_msg_received_deassert_int_d,
//----------------------------------------------------------------------------------------------------------------//
// 5. Physical Layer Control and Status (PL) Interface //
//----------------------------------------------------------------------------------------------------------------//
//------------------------------------------------//
// EP and RP //
//------------------------------------------------//
input [1:0] pl_directed_link_change,
input [1:0] pl_directed_link_width,
input pl_directed_link_speed,
input pl_directed_link_auton,
input pl_upstream_prefer_deemph,
output pl_sel_lnk_rate,
output [1:0] pl_sel_lnk_width,
output [5:0] pl_ltssm_state,
output [1:0] pl_lane_reversal_mode,
output pl_phy_lnk_up,
output [2:0] pl_tx_pm_state,
output [1:0] pl_rx_pm_state,
output pl_link_upcfg_cap,
output pl_link_gen2_cap,
output pl_link_partner_gen2_supported,
output [2:0] pl_initial_link_width,
output pl_directed_change_done,
//------------------------------------------------//
// EP Only //
//------------------------------------------------//
output pl_received_hot_rst,
//------------------------------------------------//
// RP Only //
//------------------------------------------------//
input pl_transmit_hot_rst,
input pl_downstream_deemph_source,
//----------------------------------------------------------------------------------------------------------------//
// 6. AER interface //
//----------------------------------------------------------------------------------------------------------------//
input [127:0] cfg_err_aer_headerlog,
input [4:0] cfg_aer_interrupt_msgnum,
output cfg_err_aer_headerlog_set,
output cfg_aer_ecrc_check_en,
output cfg_aer_ecrc_gen_en,
//----------------------------------------------------------------------------------------------------------------//
// 7. VC interface //
//----------------------------------------------------------------------------------------------------------------//
output [6:0] cfg_vc_tcvc_map,
//----------------------------------------------------------------------------------------------------------------//
// 8. PCIe DRP (PCIe DRP) Interface //
//----------------------------------------------------------------------------------------------------------------//
input pcie_drp_clk,
input pcie_drp_en,
input pcie_drp_we,
input [8:0] pcie_drp_addr,
input [15:0] pcie_drp_di,
output pcie_drp_rdy,
output [15:0] pcie_drp_do,
//----------------------------------------------------------------------------------------------------------------//
// PCIe Fast Config: STARTUP primitive Interface - only used in Tandem configurations //
//----------------------------------------------------------------------------------------------------------------//
// This input should be used when the startup block is generated exteranl to the PCI Express Core
input startup_eos_in, // 1-bit input: This signal should be driven by the EOS output of the STARTUP primitive.
// These inputs and outputs may be use when the startup block is generated internal to the PCI Express Core.
output wire startup_cfgclk, // 1-bit output: Configuration main clock output
output wire startup_cfgmclk, // 1-bit output: Configuration internal oscillator clock output
output wire startup_eos, // 1-bit output: Active high output signal indicating the End Of Startup
output wire startup_preq, // 1-bit output: PROGRAM request to fabric output
input wire startup_clk, // 1-bit input: User start-up clock input
input wire startup_gsr, // 1-bit input: Global Set/Reset input (GSR cannot be used for the port name)
input wire startup_gts, // 1-bit input: Global 3-state input (GTS cannot be used for the port name)
input wire startup_keyclearb, // 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM)
input wire startup_pack, // 1-bit input: PROGRAM acknowledge input
input wire startup_usrcclko, // 1-bit input: User CCLK input
input wire startup_usrcclkts, // 1-bit input: User CCLK 3-state enable input
input wire startup_usrdoneo, // 1-bit input: User DONE pin output control
input wire startup_usrdonets, // 1-bit input: User DONE 3-state enable output
//----------------------------------------------------------------------------------------------------------------//
// PCIe Fast Config: ICAP primitive Interface - only used in Tandem PCIe configuration //
//----------------------------------------------------------------------------------------------------------------//
input wire icap_clk,
input wire icap_csib,
input wire icap_rdwrb,
input wire [31:0] icap_i,
output wire [31:0] icap_o,
input [ 2:0] pipe_txprbssel,
input [ 2:0] pipe_rxprbssel,
input pipe_txprbsforceerr,
input pipe_rxprbscntreset,
input [ 2:0] pipe_loopback,
output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_rxprbserr,
input [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_txinhibit,
output [4:0] pipe_rst_fsm,
output [11:0] pipe_qrst_fsm,
output [(LINK_CAP_MAX_LINK_WIDTH*5)-1:0] pipe_rate_fsm,
output [(LINK_CAP_MAX_LINK_WIDTH*6)-1:0] pipe_sync_fsm_tx,
output [(LINK_CAP_MAX_LINK_WIDTH*7)-1:0] pipe_sync_fsm_rx,
output [(LINK_CAP_MAX_LINK_WIDTH*7)-1:0] pipe_drp_fsm,
output pipe_rst_idle,
output pipe_qrst_idle,
output pipe_rate_idle,
output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_eyescandataerror,
output [(LINK_CAP_MAX_LINK_WIDTH*3)-1:0] pipe_rxstatus,
output [(LINK_CAP_MAX_LINK_WIDTH*15)-1:0] pipe_dmonitorout,
output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_cpll_lock,
output [(LINK_CAP_MAX_LINK_WIDTH-1)>>2:0] pipe_qpll_lock,
output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_rxpmaresetdone,
output [(LINK_CAP_MAX_LINK_WIDTH*3)-1:0] pipe_rxbufstatus,
output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_txphaligndone,
output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_txphinitdone,
output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_txdlysresetdone,
output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_rxphaligndone,
output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_rxdlysresetdone,
output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_rxsyncdone,
output [(LINK_CAP_MAX_LINK_WIDTH*8)-1:0] pipe_rxdisperr,
output [(LINK_CAP_MAX_LINK_WIDTH*8)-1:0] pipe_rxnotintable,
output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_rxcommadet,
output [LINK_CAP_MAX_LINK_WIDTH-1:0] gt_ch_drp_rdy,
output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_0,
output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_1,
output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_2,
output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_3,
output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_4,
output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_5,
output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_6,
output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_7,
output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_8,
output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_9,
output [31:0] pipe_debug,
//--------------Channel DRP---------------------------------
output ext_ch_gt_drpclk,
input [(LINK_CAP_MAX_LINK_WIDTH*9)-1:0] ext_ch_gt_drpaddr,
input [LINK_CAP_MAX_LINK_WIDTH-1:0] ext_ch_gt_drpen,
input [(LINK_CAP_MAX_LINK_WIDTH*16)-1:0] ext_ch_gt_drpdi,
input [LINK_CAP_MAX_LINK_WIDTH-1:0] ext_ch_gt_drpwe,
output [(LINK_CAP_MAX_LINK_WIDTH*16)-1:0] ext_ch_gt_drpdo,
output [LINK_CAP_MAX_LINK_WIDTH-1:0] ext_ch_gt_drprdy,
//----------------------------------------------------------------------------------------------------------------//
// PIPE PORTS to TOP Level For PIPE SIMULATION with 3rd Party IP/BFM/Xilinx BFM
//----------------------------------------------------------------------------------------------------------------//
input wire [ 3:0] common_commands_in,
input wire [24:0] pipe_rx_0_sigs,
input wire [24:0] pipe_rx_1_sigs,
input wire [24:0] pipe_rx_2_sigs,
input wire [24:0] pipe_rx_3_sigs,
input wire [24:0] pipe_rx_4_sigs,
input wire [24:0] pipe_rx_5_sigs,
input wire [24:0] pipe_rx_6_sigs,
input wire [24:0] pipe_rx_7_sigs,
output wire [11:0] common_commands_out,
output wire [22:0] pipe_tx_0_sigs,
output wire [22:0] pipe_tx_1_sigs,
output wire [22:0] pipe_tx_2_sigs,
output wire [22:0] pipe_tx_3_sigs,
output wire [22:0] pipe_tx_4_sigs,
output wire [22:0] pipe_tx_5_sigs,
output wire [22:0] pipe_tx_6_sigs,
output wire [22:0] pipe_tx_7_sigs,
//----------------------------------------------------------------------------------------------------------------//
input wire pipe_mmcm_rst_n, // Async | Async
input wire sys_clk,
input wire sys_rst_n
);
PCIeGen2x8If128_core_top # (
.LINK_CAP_MAX_LINK_WIDTH (LINK_CAP_MAX_LINK_WIDTH),
.C_DATA_WIDTH (C_DATA_WIDTH),
.KEEP_WIDTH (KEEP_WIDTH)
) inst
(
.pci_exp_txn(pci_exp_txn),
.pci_exp_txp(pci_exp_txp),
.pci_exp_rxn(pci_exp_rxn),
.pci_exp_rxp(pci_exp_rxp),
.int_pclk_out_slave(int_pclk_out_slave),
.int_pipe_rxusrclk_out(int_pipe_rxusrclk_out),
.int_rxoutclk_out(int_rxoutclk_out),
.int_dclk_out(int_dclk_out),
.int_userclk1_out(int_userclk1_out),
.int_mmcm_lock_out(int_mmcm_lock_out),
.int_userclk2_out(int_userclk2_out),
.int_oobclk_out(int_oobclk_out),
.int_qplllock_out(int_qplllock_out),
.int_qplloutclk_out(int_qplloutclk_out),
.int_qplloutrefclk_out(int_qplloutrefclk_out),
.int_pclk_sel_slave(int_pclk_sel_slave),
.pipe_pclk_in(pipe_pclk_in),
.pipe_rxusrclk_in(pipe_rxusrclk_in),
.pipe_rxoutclk_in(pipe_rxoutclk_in),
.pipe_dclk_in(pipe_dclk_in),
.pipe_userclk1_in(pipe_userclk1_in),
.pipe_userclk2_in(pipe_userclk2_in),
.pipe_oobclk_in(pipe_oobclk_in),
.pipe_mmcm_lock_in(pipe_mmcm_lock_in),
.pipe_txoutclk_out(pipe_txoutclk_out),
.pipe_rxoutclk_out(pipe_rxoutclk_out),
.pipe_pclk_sel_out(pipe_pclk_sel_out),
.pipe_gen3_out(pipe_gen3_out),
.user_clk_out(user_clk_out),
.user_reset_out(user_reset_out),
.user_lnk_up(user_lnk_up),
.user_app_rdy(user_app_rdy),
.tx_buf_av(tx_buf_av),
.tx_err_drop(tx_err_drop),
.tx_cfg_req(tx_cfg_req),
.s_axis_tx_tready(s_axis_tx_tready),
.s_axis_tx_tdata(s_axis_tx_tdata),
.s_axis_tx_tkeep(s_axis_tx_tkeep),
.s_axis_tx_tuser(s_axis_tx_tuser),
.s_axis_tx_tlast(s_axis_tx_tlast),
.s_axis_tx_tvalid(s_axis_tx_tvalid),
.tx_cfg_gnt(tx_cfg_gnt),
.m_axis_rx_tdata(m_axis_rx_tdata),
.m_axis_rx_tkeep(m_axis_rx_tkeep),
.m_axis_rx_tlast(m_axis_rx_tlast),
.m_axis_rx_tvalid(m_axis_rx_tvalid),
.m_axis_rx_tready(m_axis_rx_tready),
.m_axis_rx_tuser(m_axis_rx_tuser),
.rx_np_ok(rx_np_ok),
.rx_np_req(rx_np_req),
.fc_cpld(fc_cpld),
.fc_cplh(fc_cplh),
.fc_npd(fc_npd),
.fc_nph(fc_nph),
.fc_pd(fc_pd),
.fc_ph(fc_ph),
.fc_sel(fc_sel),
.cfg_status(cfg_status),
.cfg_command(cfg_command),
.cfg_dstatus(cfg_dstatus),
.cfg_dcommand(cfg_dcommand),
.cfg_lstatus(cfg_lstatus),
.cfg_lcommand(cfg_lcommand),
.cfg_dcommand2(cfg_dcommand2),
.cfg_pcie_link_state(cfg_pcie_link_state),
.cfg_pmcsr_pme_en(cfg_pmcsr_pme_en),
.cfg_pmcsr_powerstate(cfg_pmcsr_powerstate),
.cfg_pmcsr_pme_status(cfg_pmcsr_pme_status),
.cfg_received_func_lvl_rst(cfg_received_func_lvl_rst),
.cfg_mgmt_do(cfg_mgmt_do),
.cfg_mgmt_rd_wr_done(cfg_mgmt_rd_wr_done),
.cfg_mgmt_di(cfg_mgmt_di),
.cfg_mgmt_byte_en(cfg_mgmt_byte_en),
.cfg_mgmt_dwaddr(cfg_mgmt_dwaddr),
.cfg_mgmt_wr_en(cfg_mgmt_wr_en),
.cfg_mgmt_rd_en(cfg_mgmt_rd_en),
.cfg_mgmt_wr_readonly(cfg_mgmt_wr_readonly),
.cfg_err_ecrc(cfg_err_ecrc),
.cfg_err_ur(cfg_err_ur),
.cfg_err_cpl_timeout(cfg_err_cpl_timeout),
.cfg_err_cpl_unexpect(cfg_err_cpl_unexpect),
.cfg_err_cpl_abort(cfg_err_cpl_abort),
.cfg_err_posted(cfg_err_posted),
.cfg_err_cor(cfg_err_cor),
.cfg_err_atomic_egress_blocked(cfg_err_atomic_egress_blocked),
.cfg_err_internal_cor(cfg_err_internal_cor),
.cfg_err_malformed(cfg_err_malformed),
.cfg_err_mc_blocked(cfg_err_mc_blocked),
.cfg_err_poisoned(cfg_err_poisoned),
.cfg_err_norecovery(cfg_err_norecovery),
.cfg_err_tlp_cpl_header(cfg_err_tlp_cpl_header),
.cfg_err_cpl_rdy(cfg_err_cpl_rdy),
.cfg_err_locked(cfg_err_locked),
.cfg_err_acs(cfg_err_acs),
.cfg_err_internal_uncor(cfg_err_internal_uncor),
.cfg_trn_pending(cfg_trn_pending),
.cfg_pm_halt_aspm_l0s(cfg_pm_halt_aspm_l0s),
.cfg_pm_halt_aspm_l1(cfg_pm_halt_aspm_l1),
.cfg_pm_force_state_en(cfg_pm_force_state_en),
.cfg_pm_force_state(cfg_pm_force_state),
.cfg_dsn(cfg_dsn),
.cfg_msg_received(cfg_msg_received),
.cfg_msg_data(cfg_msg_data),
.cfg_interrupt(cfg_interrupt),
.cfg_interrupt_rdy(cfg_interrupt_rdy),
.cfg_interrupt_assert(cfg_interrupt_assert),
.cfg_interrupt_di(cfg_interrupt_di),
.cfg_interrupt_do(cfg_interrupt_do),
.cfg_interrupt_mmenable(cfg_interrupt_mmenable),
.cfg_interrupt_msienable(cfg_interrupt_msienable),
.cfg_interrupt_msixenable(cfg_interrupt_msixenable),
.cfg_interrupt_msixfm(cfg_interrupt_msixfm),
.cfg_interrupt_stat(cfg_interrupt_stat),
.cfg_pciecap_interrupt_msgnum(cfg_pciecap_interrupt_msgnum),
.cfg_to_turnoff(cfg_to_turnoff),
.cfg_turnoff_ok(cfg_turnoff_ok),
.cfg_bus_number(cfg_bus_number),
.cfg_device_number(cfg_device_number),
.cfg_function_number(cfg_function_number),
.cfg_pm_wake(cfg_pm_wake),
.cfg_msg_received_setslotpowerlimit(cfg_msg_received_setslotpowerlimit),
.cfg_pm_send_pme_to(cfg_pm_send_pme_to),
.cfg_ds_bus_number(cfg_ds_bus_number),
.cfg_ds_device_number(cfg_ds_device_number),
.cfg_ds_function_number(cfg_ds_function_number),
.cfg_mgmt_wr_rw1c_as_rw(cfg_mgmt_wr_rw1c_as_rw),
.cfg_bridge_serr_en(cfg_bridge_serr_en),
.cfg_slot_control_electromech_il_ctl_pulse(cfg_slot_control_electromech_il_ctl_pulse),
.cfg_root_control_syserr_corr_err_en(cfg_root_control_syserr_corr_err_en),
.cfg_root_control_syserr_non_fatal_err_en(cfg_root_control_syserr_non_fatal_err_en),
.cfg_root_control_syserr_fatal_err_en(cfg_root_control_syserr_fatal_err_en),
.cfg_root_control_pme_int_en(cfg_root_control_pme_int_en),
.cfg_aer_rooterr_corr_err_reporting_en(cfg_aer_rooterr_corr_err_reporting_en),
.cfg_aer_rooterr_non_fatal_err_reporting_en(cfg_aer_rooterr_non_fatal_err_reporting_en),
.cfg_aer_rooterr_fatal_err_reporting_en(cfg_aer_rooterr_fatal_err_reporting_en),
.cfg_aer_rooterr_corr_err_received(cfg_aer_rooterr_corr_err_received),
.cfg_aer_rooterr_non_fatal_err_received(cfg_aer_rooterr_non_fatal_err_received),
.cfg_aer_rooterr_fatal_err_received(cfg_aer_rooterr_fatal_err_received),
.cfg_msg_received_err_cor(cfg_msg_received_err_cor),
.cfg_msg_received_err_non_fatal(cfg_msg_received_err_non_fatal),
.cfg_msg_received_err_fatal(cfg_msg_received_err_fatal),
.cfg_msg_received_pm_as_nak(cfg_msg_received_pm_as_nak),
.cfg_msg_received_pm_pme(cfg_msg_received_pm_pme),
.cfg_msg_received_pme_to_ack(cfg_msg_received_pme_to_ack),
.cfg_msg_received_assert_int_a(cfg_msg_received_assert_int_a),
.cfg_msg_received_assert_int_b(cfg_msg_received_assert_int_b),
.cfg_msg_received_assert_int_c(cfg_msg_received_assert_int_c),
.cfg_msg_received_assert_int_d(cfg_msg_received_assert_int_d),
.cfg_msg_received_deassert_int_a(cfg_msg_received_deassert_int_a),
.cfg_msg_received_deassert_int_b(cfg_msg_received_deassert_int_b),
.cfg_msg_received_deassert_int_c(cfg_msg_received_deassert_int_c),
.cfg_msg_received_deassert_int_d(cfg_msg_received_deassert_int_d),
.pl_directed_link_change(pl_directed_link_change),
.pl_directed_link_width(pl_directed_link_width),
.pl_directed_link_speed(pl_directed_link_speed),
.pl_directed_link_auton(pl_directed_link_auton),
.pl_upstream_prefer_deemph(pl_upstream_prefer_deemph),
.pl_sel_lnk_rate(pl_sel_lnk_rate),
.pl_sel_lnk_width(pl_sel_lnk_width),
.pl_ltssm_state(pl_ltssm_state),
.pl_lane_reversal_mode(pl_lane_reversal_mode),
.pl_phy_lnk_up(pl_phy_lnk_up),
.pl_tx_pm_state(pl_tx_pm_state),
.pl_rx_pm_state(pl_rx_pm_state),
.pl_link_upcfg_cap(pl_link_upcfg_cap),
.pl_link_gen2_cap(pl_link_gen2_cap),
.pl_link_partner_gen2_supported(pl_link_partner_gen2_supported),
.pl_initial_link_width(pl_initial_link_width),
.pl_directed_change_done(pl_directed_change_done),
.pl_received_hot_rst(pl_received_hot_rst),
.pl_transmit_hot_rst(pl_transmit_hot_rst),
.pl_downstream_deemph_source(pl_downstream_deemph_source),
.cfg_err_aer_headerlog(cfg_err_aer_headerlog),
.cfg_aer_interrupt_msgnum(cfg_aer_interrupt_msgnum),
.cfg_err_aer_headerlog_set(cfg_err_aer_headerlog_set),
.cfg_aer_ecrc_check_en(cfg_aer_ecrc_check_en),
.cfg_aer_ecrc_gen_en(cfg_aer_ecrc_gen_en),
.cfg_vc_tcvc_map(cfg_vc_tcvc_map),
.pcie_drp_clk(pcie_drp_clk),
.pcie_drp_en(pcie_drp_en),
.pcie_drp_we(pcie_drp_we),
.pcie_drp_addr(pcie_drp_addr),
.pcie_drp_di(pcie_drp_di),
.pcie_drp_rdy(pcie_drp_rdy),
.pcie_drp_do(pcie_drp_do),
// STARTUP primitive interface - Can only be used with Tandem Configurations
// This input should be used when the startup block is generated exteranl to the PCI Express Core
.startup_eos_in(startup_eos_in), // 1-bit input: This signal should be driven by the EOS output of the STARTUP primitive.
// These inputs and outputs may be use when the startup block is generated internal to the PCI Express Core.
.startup_cfgclk(startup_cfgclk), // 1-bit output: Configuration main clock output
.startup_cfgmclk(startup_cfgmclk), // 1-bit output: Configuration internal oscillator clock output
.startup_eos(startup_eos), // 1-bit output: Active high output signal indicating the End Of Startup.
.startup_preq(startup_preq), // 1-bit output: PROGRAM request to fabric output
.startup_clk(startup_clk), // 1-bit input: User start-up clock input
.startup_gsr(startup_gsr), // 1-bit input: Global Set/Reset input (GSR cannot be used for the port name)
.startup_gts(startup_gts), // 1-bit input: Global 3-state input (GTS cannot be used for the port name)
.startup_keyclearb(startup_keyclearb), // 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM)
.startup_pack(startup_pack), // 1-bit input: PROGRAM acknowledge input
.startup_usrcclko(startup_usrcclko), // 1-bit input: User CCLK input
.startup_usrcclkts(startup_usrcclkts), // 1-bit input: User CCLK 3-state enable input
.startup_usrdoneo(startup_usrdoneo), // 1-bit input: User DONE pin output control
.startup_usrdonets(startup_usrdonets), // 1-bit input: User DONE 3-state enable output
// ICAP primitive interface - Can only be used with Tandem PCIe Configuration
.icap_clk(icap_clk),
.icap_csib(icap_csib),
.icap_rdwrb(icap_rdwrb),
.icap_i(icap_i),
.icap_o(icap_o),
//External GT COMMON Ports
.qpll_drp_crscode ( qpll_drp_crscode ),
.qpll_drp_fsm ( qpll_drp_fsm ),
.qpll_drp_done ( qpll_drp_done ),
.qpll_drp_reset ( qpll_drp_reset ),
.qpll_qplllock ( qpll_qplllock ),
.qpll_qplloutclk ( qpll_qplloutclk ),
.qpll_qplloutrefclk ( qpll_qplloutrefclk ),
.qpll_qplld ( qpll_qplld ),
.qpll_qpllreset ( qpll_qpllreset ),
.qpll_drp_clk ( qpll_drp_clk ),
.qpll_drp_rst_n ( qpll_drp_rst_n ),
.qpll_drp_ovrd ( qpll_drp_ovrd ),
.qpll_drp_gen3 ( qpll_drp_gen3),
.qpll_drp_start ( qpll_drp_start ),
//------------TRANSCEIVER DEBUG-----------------------------------
//Drive these inputs to 0s
.ext_ch_gt_drpclk (ext_ch_gt_drpclk),
.ext_ch_gt_drpaddr (ext_ch_gt_drpaddr),
.ext_ch_gt_drpen (ext_ch_gt_drpen),
.ext_ch_gt_drpdi (ext_ch_gt_drpdi),
.ext_ch_gt_drpwe (ext_ch_gt_drpwe),
.ext_ch_gt_drpdo (ext_ch_gt_drpdo),
.ext_ch_gt_drprdy (ext_ch_gt_drprdy ),
.pipe_txprbssel (pipe_txprbssel),
.pipe_rxprbssel (pipe_rxprbssel),
.pipe_txprbsforceerr (pipe_txprbsforceerr),
.pipe_rxprbscntreset (pipe_rxprbscntreset),
.pipe_loopback (pipe_loopback ),
.pipe_rxprbserr (pipe_rxprbserr),
.pipe_txinhibit (pipe_txinhibit),
.pipe_rst_fsm (pipe_rst_fsm),
.pipe_qrst_fsm (pipe_qrst_fsm),
.pipe_rate_fsm (pipe_rate_fsm),
.pipe_sync_fsm_tx (pipe_sync_fsm_tx),
.pipe_sync_fsm_rx (pipe_sync_fsm_rx),
.pipe_drp_fsm (pipe_drp_fsm),
.pipe_rst_idle (pipe_rst_idle),
.pipe_qrst_idle (pipe_qrst_idle),
.pipe_rate_idle (pipe_rate_idle),
.pipe_eyescandataerror (pipe_eyescandataerror),
.pipe_rxstatus (pipe_rxstatus),
.pipe_dmonitorout (pipe_dmonitorout),
.pipe_cpll_lock ( pipe_cpll_lock ),
.pipe_qpll_lock ( pipe_qpll_lock ),
.pipe_rxpmaresetdone ( pipe_rxpmaresetdone ),
.pipe_rxbufstatus ( pipe_rxbufstatus ),
.pipe_txphaligndone ( pipe_txphaligndone ),
.pipe_txphinitdone ( pipe_txphinitdone ),
.pipe_txdlysresetdone ( pipe_txdlysresetdone ),
.pipe_rxphaligndone ( pipe_rxphaligndone ),
.pipe_rxdlysresetdone ( pipe_rxdlysresetdone ),
.pipe_rxsyncdone ( pipe_rxsyncdone ),
.pipe_rxdisperr ( pipe_rxdisperr ),
.pipe_rxnotintable ( pipe_rxnotintable ),
.pipe_rxcommadet ( pipe_rxcommadet ),
//---------- CHANNEL DRP --------------------------------
.gt_ch_drp_rdy (gt_ch_drp_rdy),
.pipe_debug_0 (pipe_debug_0),
.pipe_debug_1 (pipe_debug_1),
.pipe_debug_2 (pipe_debug_2),
.pipe_debug_3 (pipe_debug_3),
.pipe_debug_4 (pipe_debug_4),
.pipe_debug_5 (pipe_debug_5),
.pipe_debug_6 (pipe_debug_6),
.pipe_debug_7 (pipe_debug_7),
.pipe_debug_8 (pipe_debug_8),
.pipe_debug_9 (pipe_debug_9),
.pipe_debug (pipe_debug),
.common_commands_in ( common_commands_in ),
.pipe_rx_0_sigs ( pipe_rx_0_sigs ),
.pipe_rx_1_sigs ( pipe_rx_1_sigs ),
.pipe_rx_2_sigs ( pipe_rx_2_sigs ),
.pipe_rx_3_sigs ( pipe_rx_3_sigs ),
.pipe_rx_4_sigs ( pipe_rx_4_sigs ),
.pipe_rx_5_sigs ( pipe_rx_5_sigs ),
.pipe_rx_6_sigs ( pipe_rx_6_sigs ),
.pipe_rx_7_sigs ( pipe_rx_7_sigs ),
.common_commands_out ( common_commands_out ),
.pipe_tx_0_sigs ( pipe_tx_0_sigs ),
.pipe_tx_1_sigs ( pipe_tx_1_sigs ),
.pipe_tx_2_sigs ( pipe_tx_2_sigs ),
.pipe_tx_3_sigs ( pipe_tx_3_sigs ),
.pipe_tx_4_sigs ( pipe_tx_4_sigs ),
.pipe_tx_5_sigs ( pipe_tx_5_sigs ),
.pipe_tx_6_sigs ( pipe_tx_6_sigs ),
.pipe_tx_7_sigs ( pipe_tx_7_sigs ),
.pipe_mmcm_rst_n (pipe_mmcm_rst_n), // Async | Async
.sys_clk (sys_clk),
.sys_rst_n (sys_rst_n)
);
endmodule
|
`timescale 1 ns / 1 ps
module rp_dac #
(
)
(
input dac_clk_1x ,
input dac_clk_2x ,
input dac_clk_2p ,
input dac_locked ,
// DAC IC
output [ 14-1: 0] dac_dat_o , //!< DAC IC combined data
output dac_wrt_o , //!< DAC IC write enable
output dac_sel_o , //!< DAC IC channel select
output dac_clk_o , //!< DAC IC clock
output dac_rst_o , //!< DAC IC reset
input [ 14-1: 0] dac_dat_a_i , //!< DAC CHA data
input [ 14-1: 0] dac_dat_b_i //!< DAC CHB data
);
reg dac_rst ;
reg [14-1: 0] dac_dat_a ;
reg [14-1: 0] dac_dat_b ;
// output registers + signed to unsigned (also to negative slope)
always @(posedge dac_clk_1x) begin
dac_dat_a <= {dac_dat_a_i[14-1], ~dac_dat_a_i[14-2:0]};
dac_dat_b <= {dac_dat_b_i[14-1], ~dac_dat_b_i[14-2:0]};
dac_rst <= !dac_locked;
end
ODDR oddr_dac_clk (.Q(dac_clk_o), .D1(1'b0 ), .D2(1'b1 ), .C(dac_clk_2p), .CE(1'b1), .R(1'b0 ), .S(1'b0));
ODDR oddr_dac_wrt (.Q(dac_wrt_o), .D1(1'b0 ), .D2(1'b1 ), .C(dac_clk_2x), .CE(1'b1), .R(1'b0 ), .S(1'b0));
ODDR oddr_dac_sel (.Q(dac_sel_o), .D1(1'b1 ), .D2(1'b0 ), .C(dac_clk_1x), .CE(1'b1), .R(dac_rst), .S(1'b0));
ODDR oddr_dac_rst (.Q(dac_rst_o), .D1(dac_rst ), .D2(dac_rst ), .C(dac_clk_1x), .CE(1'b1), .R(1'b0 ), .S(1'b0));
ODDR oddr_dac_dat [14-1:0] (.Q(dac_dat_o), .D1(dac_dat_b), .D2(dac_dat_a), .C(dac_clk_1x), .CE(1'b1), .R(dac_rst), .S(1'b0));
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 06.10.2017 09:04:37
// Design Name:
// Module Name: bankregister_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module bankregister_tb;
reg [5:0] RegLe1;
reg [5:0] RegLe2;
reg [5:0] RegEscr;
reg EscrReg;
reg clk;
reg [31:0] datain;
wire [31:0] data1;
wire [31:0] data2;
reg reset;
bankregister uut(
.RegLe1(RegLe1),
.RegLe2(RegLe2),
.RegEscr(RegEscr),
.EscrReg(EscrReg),
.clk(clk),
.datain(datain),
.data1(data1),
.data2(data2),
.reset(reset)
);
always
begin
clk = 1'b1;
#50;
clk = 1'b0;
#50;
end
initial begin
reset = 1'b1;
#100;
reset = 1'b0;
RegLe1 = 6'b000000;
RegLe2 = 6'b000001;
RegEscr = 6'b000000;
EscrReg = 1'b0;
datain = 32'b00000000_00000000_00000000_00000000;
#100;
RegLe1 = 6'b000000;
RegLe2 = 6'b000001;
RegEscr = 6'b000010;
EscrReg = 1'b1;
datain = 32'b00000000_00000000_00000000_10000101;
#100;
RegLe1 = 6'b000010;
RegLe2 = 6'b000001;
RegEscr = 6'b000000;
EscrReg = 1'b0;
datain = 32'b00000000_00000000_00000000_00000001;
#100;
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// tx_queue.v. Derived from NetFPGA project.
// vim:set shiftwidth=3 softtabstop=3 expandtab:
// $Id: tx_queue.v 2080 2007-08-02 17:19:29Z grg $
//
// Module: tx_queue.v
// Project: NF2.1
// Description: Instantiates the speed matching FIFO that accepts
// packets from the core and sends it to the MAC
//
// On the read side is the 125/12.5/1.25MHz MAC clock which reads
// data 9 bits wide from the fifo (bit 8 is EOP).
//
///////////////////////////////////////////////////////////////////////////////
module tx_queue
#(
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = DATA_WIDTH/8,
parameter ENABLE_HEADER = 1,
parameter STAGE_NUMBER = 'hff,
parameter AXI_DATA_WIDTH = 32,
parameter AXI_KEEP_WIDTH = AXI_DATA_WIDTH/8
)
(input [DATA_WIDTH-1:0] in_data,
input [CTRL_WIDTH-1:0] in_ctrl,
input in_wr,
output in_rdy,
// --- MAC side signals (m_tx_axis_aclk domain)
input m_tx_axis_aclk,
output reg m_tx_axis_tvalid,
output [AXI_DATA_WIDTH - 1 : 0] m_tx_axis_tdata,
output reg m_tx_axis_tlast,
output reg [AXI_KEEP_WIDTH - 1 : 0] m_tx_axis_tkeep,
input m_tx_axis_tready,
// --- Register interface
//input tx_queue_en,
// output tx_pkt_sent,
output reg tx_pkt_stored,
output reg [11:0] tx_pkt_byte_cnt,
output reg tx_pkt_byte_cnt_vld,
output reg [9:0] tx_pkt_word_cnt,
// --- Misc
input reset,
input clk
);
// ------------ Internal Params --------
//state machine states (one-hot)
localparam IDLE = 1;
localparam WAIT_FOR_READY = 2;
localparam WAIT_FOR_EOP = 4;
localparam INPUT_IDLE = 1;
localparam INPUT_PKTS = 2;
// Number of packets waiting:
//
// 4096 / 64 = 64 = 2**6
//
// so, need 7 bits to represent the number of packets waiting
localparam NUM_PKTS_WAITING_WIDTH = 7;
// ------------- Regs/ wires -----------
wire [DATA_WIDTH+CTRL_WIDTH - 1 : 0] tx_fifo_din;
wire [AXI_DATA_WIDTH - 1 : 0] tx_fifo_out_data;
wire [AXI_KEEP_WIDTH - 1 : 0] tx_fifo_out_ctrl;
reg tx_fifo_rd_en;
wire tx_fifo_empty;
wire tx_fifo_almost_full;
reg reset_txclk;
reg pkt_sent_txclk; // pulses when a packet has been removed
reg [4:0] tx_mac_state_nxt, tx_mac_state;
reg m_tx_axis_tvalid_nxt;
reg tx_queue_en_txclk;
//reg tx_queue_en_sync;
reg [NUM_PKTS_WAITING_WIDTH-1:0] txf_num_pkts_waiting;
wire txf_pkts_avail;
reg [4:0] tx_input_state, tx_input_state_nxt;
reg tx_fifo_wr_en;
reg need_clear_padding;
assign in_rdy = ~tx_fifo_almost_full;
//--------------------------------------------------------------
// synchronize
//--------------------------------------------------------------
// extend reset over to MAC domain
reg reset_long;
// synthesis attribute ASYNC_REG of reset_long is TRUE ;
always @(posedge clk) begin
if (reset) reset_long <= 1;
else if (reset_txclk) reset_long <= 0;
end
always @(posedge m_tx_axis_aclk) reset_txclk <= reset_long;
//---------------------------------------------------------------
// packet fifo input and output logic
//---------------------------------------------------------------
assign tx_fifo_din = {in_ctrl[7:4], in_data[63:32],in_ctrl[3:0], in_data[31:0]};
txfifo_512x72_to_36 gmac_tx_fifo
(
.din (tx_fifo_din),
.wr_en (tx_fifo_wr_en),
.wr_clk (clk),
.dout ({tx_fifo_out_ctrl,tx_fifo_out_data}),
.rd_en (tx_fifo_rd_en),
.rd_clk (m_tx_axis_aclk),
.empty (tx_fifo_empty),
.full (),
.almost_full(tx_fifo_almost_full),
.rst (reset)
);
/* small_fifo #(.WIDTH(DATA_WIDTH+CTRL_WIDTH),.MAX_DEPTH_BITS(3))
input_fifo
( .din ({in_ctrl, in_data}), // Data in
.wr_en (tx_fifo_wr_en), // Write enable
.rd_en (tx_fifo_rd_en), // Read the next word
.dout ({tx_fifo_out_ctrl, tx_fifo_out_data}),
.full (),
.prog_full (),
.nearly_full (tx_fifo_almost_full),
.empty (tx_fifo_empty),
.reset (reset),
.clk (clk)
);
fifo_72_to_36 #(.WIDTH(DATA_WIDTH+CTRL_WIDTH),.MAX_DEPTH_BITS(10))
fifo_72_to_36
( .din (tx_fifo_din), // Data in
.wr_en (tx_fifo_wr_en), // Write enable
.rd_en (tx_fifo_rd_en), // Read the next word
.dout ({tx_fifo_out_ctrl, tx_fifo_out_data}),
.full (),
.prog_full (tx_fifo_almost_full),
.nearly_full (),
.empty (tx_fifo_empty),
.reset (reset),
.clk (clk)
);*/
// Reorder the output: AXI-S uses little endian, the User Data Path uses big endian
generate
genvar k;
for(k=0; k<AXI_KEEP_WIDTH; k=k+1) begin: reorder_endianness
assign m_tx_axis_tdata[8*k+:8] = tx_fifo_out_data[AXI_DATA_WIDTH-8-8*k+:8];
end
endgenerate
//----------------------------------------------------------
//input state machine.
//Following is in core clock domain (62MHz/125 MHz)
//----------------------------------------------------------
always @(*)begin
tx_fifo_wr_en = 0;
tx_pkt_stored = 0;
tx_pkt_byte_cnt = 0;
tx_pkt_byte_cnt_vld = 0;
tx_pkt_word_cnt = 0;
tx_input_state_nxt = tx_input_state;
case (tx_input_state)
INPUT_IDLE: begin
if(in_wr && in_ctrl == STAGE_NUMBER)begin
tx_pkt_byte_cnt = in_data[`IOQ_BYTE_LEN_POS +: 16];
tx_pkt_word_cnt = in_data[`IOQ_WORD_LEN_POS +: 16];
tx_pkt_byte_cnt_vld = 1'b1;
end
else if(in_wr && in_ctrl == 0)begin //just ignore other module header
tx_fifo_wr_en = 1'b1;
tx_input_state_nxt = INPUT_PKTS;
end
end
INPUT_PKTS: begin
if(in_wr)begin
tx_fifo_wr_en = 1'b1;
if(|in_ctrl) begin
//tx_pkt_stored = 1'b1;
tx_input_state_nxt = INPUT_IDLE;
end
end
end
endcase
end
always @(posedge clk) begin
if(reset) begin
tx_input_state <= INPUT_IDLE;
end
else tx_input_state <= tx_input_state_nxt;
end
//---------------------------------------------------------------
//output state machine
// Following is in MAC clock domain (125MHz/12.5Mhz/1.25Mhz)
//---------------------------------------------------------------
// sync the enable signal from the core to the tx clock domains
/*always @(posedge m_tx_axis_aclk) begin
if(reset_txclk) begin
tx_queue_en_sync <= 0;
tx_queue_en_txclk <= 0;
end
else begin
tx_queue_en_sync <= tx_queue_en;
tx_queue_en_txclk <= tx_queue_en_sync;
end
end*/
always @* begin
tx_mac_state_nxt = tx_mac_state;
tx_fifo_rd_en = 1'b0;
m_tx_axis_tvalid_nxt = 1'b0;
pkt_sent_txclk = 1'b0;
case (tx_mac_state)
IDLE: if ( !tx_fifo_empty ) begin //txf_pkts_avail &
tx_fifo_rd_en = 1; // this will make DOUT of FIFO valid after the NEXT clock
m_tx_axis_tvalid_nxt = 1;
tx_mac_state_nxt = WAIT_FOR_READY;
end
WAIT_FOR_READY:begin
m_tx_axis_tvalid_nxt = 1;
if(!tx_fifo_empty && m_tx_axis_tready)begin
tx_fifo_rd_en = 1;
tx_mac_state_nxt = WAIT_FOR_EOP;
end
end
WAIT_FOR_EOP: begin
m_tx_axis_tvalid_nxt = 1;
if(|tx_fifo_out_ctrl) begin
pkt_sent_txclk = 1;
m_tx_axis_tvalid_nxt = 0;
tx_mac_state_nxt = IDLE;
if (need_clear_padding) begin // the last data byte was the last of the word so we are done.
tx_fifo_rd_en = 1;
end
else tx_fifo_rd_en = 0;
end
else if(!tx_fifo_empty && m_tx_axis_tready)begin // Not EOP - keep reading!
tx_fifo_rd_en = 1;
//m_tx_axis_tvalid_nxt = 1;
end
end
endcase
end
always @(*)begin
if(tx_mac_state == WAIT_FOR_READY || tx_mac_state == WAIT_FOR_EOP)begin
case (tx_fifo_out_ctrl)
4'b1000: begin
m_tx_axis_tkeep = 4'b0001;
m_tx_axis_tlast = 1'b1;
end
4'b0100: begin
m_tx_axis_tkeep = 4'b0011;
m_tx_axis_tlast = 1'b1;
end
4'b0010: begin
m_tx_axis_tkeep = 4'b0111;
m_tx_axis_tlast = 1'b1;
end
4'b0001: begin
m_tx_axis_tkeep = 4'b1111;
m_tx_axis_tlast = 1'b1;
end
default: begin
m_tx_axis_tlast = 1'b0;
m_tx_axis_tkeep = 4'b1111;
end
endcase
end
else begin
m_tx_axis_tkeep = 1'b0;
m_tx_axis_tlast = 1'b0;
end
end
// update sequential elements
always @(posedge m_tx_axis_aclk) begin
if (reset_txclk) begin
tx_mac_state <= IDLE;
m_tx_axis_tvalid <= 0;
need_clear_padding <= 0;
end
else begin
tx_mac_state <= tx_mac_state_nxt;
m_tx_axis_tvalid <= m_tx_axis_tvalid_nxt;
if(tx_fifo_rd_en) need_clear_padding <= !need_clear_padding;
end
end // always @ (posedge m_tx_axis_aclk)
//-------------------------------------------------------------------
// stats
//-------------------------------------------------------------------
/* these modules move pulses from one clk domain to the other */
/* pulse_synchronizer tx_pkt_stored_sync
(.pulse_in_clkA (tx_pkt_stored),
.clkA (clk),
.pulse_out_clkB(pkt_stored_txclk),
.clkB (m_tx_axis_aclk),
.reset_clkA (reset),
.reset_clkB (reset_txclk));
pulse_synchronizer tx_pkt_sent_sync
(.pulse_in_clkA (pkt_sent_txclk),
.clkA (m_tx_axis_aclk),
.pulse_out_clkB(tx_pkt_sent),
.clkB (clk),
.reset_clkA (reset_txclk),
.reset_clkB (reset));
//stats
always @(posedge m_tx_axis_aclk) begin
if (reset_txclk) begin
txf_num_pkts_waiting <= 'h0;
end
else begin
case ({pkt_sent_txclk, pkt_stored_txclk})
2'b01 : txf_num_pkts_waiting <= txf_num_pkts_waiting + 1;
2'b10 : txf_num_pkts_waiting <= txf_num_pkts_waiting - 1;
default: begin end
endcase
end
end // always @ (posedge m_tx_axis_aclk)
assign txf_pkts_avail = (txf_num_pkts_waiting != 'h0);*/
endmodule // tx_queue
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLYGATE4SD3_BLACKBOX_V
`define SKY130_FD_SC_MS__DLYGATE4SD3_BLACKBOX_V
/**
* dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dlygate4sd3 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLYGATE4SD3_BLACKBOX_V
|
//--------------------------------------------------------------------------------
// trigger.vhd
//
// Copyright (C) 2006 Michael Poppitz
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
//
//--------------------------------------------------------------------------------
//
// Details: http://www.sump.org/projects/analyzer/
//
// Complex 4 stage 32 channel trigger.
//
// All commands are passed on to the stages. This file only maintains
// the global trigger level and it outputs the run condition if it is set
// by any of the stages.
//
//--------------------------------------------------------------------------------
//
// 12/29/2010 - Ian Davis (IED) - Verilog version, changed to use LUT based
// masked comparisons, and other cleanups created - mygizmos.org
//
`timescale 1ns/100ps
module trigger #(
parameter integer DW = 32
)(
// system signals
input wire clk,
input wire rst,
// configuration/control signals
input wire [3:0] wrMask, // Write trigger mask register
input wire [3:0] wrValue, // Write trigger value register
input wire [3:0] wrConfig, // Write trigger config register
input wire [31:0] config_data, // Data to write into trigger config regs
input wire arm,
input wire demux_mode,
// input stream
input wire sti_valid,
input wire [DW-1:0] sti_data, // Channel data...
// status
output reg capture, // Store captured data in fifo.
output wire run // Tell controller when trigger hit.
);
reg [1:0] levelReg = 2'b00;
// if any of the stages set run, then capturing starts...
wire [3:0] stageRun;
assign run = |stageRun;
//
// IED - Shift register initialization handler...
//
// Much more space efficient in FPGA to compare this way.
//
// Instead of four seperate 32-bit value, 32-bit mask, and 32-bit comparison
// functions & all manner of flops & interconnect, each stage uses LUT table
// lookups instead.
//
// Each LUT RAM evaluates 4-bits of input. The RAM is programmed to
// evaluate the original masked compare function, and is serially downloaded
// by the following verilog.
//
//
// Background:
// ----------
// The original function was:
// hit = ((data[31:0] ^ value[31:0]) & mask[31:0])==0;
//
//
// The following table shows the result for a single bit:
// data value mask hit
// x x 0 1
// 0 0 1 1
// 0 1 1 0
// 1 0 1 0
// 1 1 1 1
//
// If a mask bit is zero, it always matches. If one, then
// the result of comparing data & value matters. If data &
// value match, the XOR function results in zero. So if either
// the mask is zero, or the input matches value, you get a hit.
//
//
// New code
// --------
// To evaluate the data, each address of the LUT RAM's evalutes:
// What hit value should result assuming my address as input?
//
// In other words, LUT for data[3:0] stores the following at given addresses:
// LUT address 0 stores result of: (4'h0 ^ value[3:0]) & mask[3:0])==0
// LUT address 1 stores result of: (4'h1 ^ value[3:0]) & mask[3:0])==0
// LUT address 2 stores result of: (4'h2 ^ value[3:0]) & mask[3:0])==0
// LUT address 3 stores result of: (4'h3 ^ value[3:0]) & mask[3:0])==0
// LUT address 4 stores result of: (4'h4 ^ value[3:0]) & mask[3:0])==0
// etc...
//
// The LUT for data[7:4] stores the following:
// LUT address 0 stores result of: (4'h0 ^ value[7:4]) & mask[7:4])==0
// LUT address 1 stores result of: (4'h1 ^ value[7:4]) & mask[7:4])==0
// LUT address 2 stores result of: (4'h2 ^ value[7:4]) & mask[7:4])==0
// LUT address 3 stores result of: (4'h3 ^ value[7:4]) & mask[7:4])==0
// LUT address 4 stores result of: (4'h4 ^ value[7:4]) & mask[7:4])==0
// etc...
//
// Eight LUT's are needed to evalute all 32-bits of data, so the
// following verilog computes the LUT RAM data for all simultaneously.
//
//
// Result:
// ------
// It functionally does exactly the same thing as before. Just uses
// less FPGA. Only requirement is the Client software on your PC issue
// the value & mask's for each trigger stage in pairs.
//
reg [DW-1:0] maskRegister;
reg [DW-1:0] valueRegister;
reg [3:0] wrcount = 0;
reg [3:0] wrenb = 4'b0;
wire [7:0] wrdata;
always @ (posedge clk)
begin
maskRegister <= (|wrMask ) ? config_data : maskRegister;
valueRegister <= (|wrValue) ? config_data : valueRegister;
end
always @ (posedge clk, posedge rst)
if (rst) begin
wrcount <= 0;
wrenb <= 4'h0;
end else begin
// Do 16 writes when value register written...
if (|wrenb) begin
wrcount <= wrcount + 'b1;
if (&wrcount) wrenb <= 4'h0;
end else begin
wrcount <= 0;
wrenb <= wrenb | wrValue;
end
end
// Compute data for the 8 target LUT's...
assign wrdata = {
~|((~wrcount^valueRegister[31:28])&maskRegister[31:28]),
~|((~wrcount^valueRegister[27:24])&maskRegister[27:24]),
~|((~wrcount^valueRegister[23:20])&maskRegister[23:20]),
~|((~wrcount^valueRegister[19:16])&maskRegister[19:16]),
~|((~wrcount^valueRegister[15:12])&maskRegister[15:12]),
~|((~wrcount^valueRegister[11: 8])&maskRegister[11: 8]),
~|((~wrcount^valueRegister[7 : 4])&maskRegister[ 7: 4]),
~|((~wrcount^valueRegister[3 : 0])&maskRegister[ 3: 0])
};
//
// Instantiate stages...
//
wire [3:0] stageMatch;
stage stage [3:0] (
// system signals
.clk (clk),
.rst (rst),
// input stream
.dataIn (sti_data),
.validIn (sti_valid),
//.wrMask (wrMask),
//.wrValue (wrValue),
.wrenb (wrenb),
.din (wrdata),
.wrConfig (wrConfig),
.config_data(config_data),
.arm (arm),
.level (levelReg),
.demux_mode (demux_mode),
.run (stageRun),
.match (stageMatch)
);
//
// Increase level on match (on any level?!)...
//
always @(posedge clk, posedge rst)
begin : P2
if (rst) begin
capture <= 1'b0;
levelReg <= 2'b00;
end else begin
capture <= arm | capture;
if (|stageMatch) levelReg <= levelReg + 'b1;
end
end
endmodule
|
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_dbg_i2c.v
//
// *Module Description:
// Debug I2C Slave communication interface
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev: 103 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_defines.v"
`endif
module omsp_dbg_i2c (
// OUTPUTs
dbg_addr, // Debug register address
dbg_din, // Debug register data input
dbg_i2c_sda_out, // Debug interface: I2C SDA OUT
dbg_rd, // Debug register data read
dbg_wr, // Debug register data write
// INPUTs
dbg_clk, // Debug unit clock
dbg_dout, // Debug register data output
dbg_i2c_addr, // Debug interface: I2C ADDRESS
dbg_i2c_broadcast, // Debug interface: I2C Broadcast Address (for multicore systems)
dbg_i2c_scl, // Debug interface: I2C SCL
dbg_i2c_sda_in, // Debug interface: I2C SDA IN
dbg_rst, // Debug unit reset
mem_burst, // Burst on going
mem_burst_end, // End TX/RX burst
mem_burst_rd, // Start TX burst
mem_burst_wr, // Start RX burst
mem_bw // Burst byte width
);
// OUTPUTs
//=========
output [5:0] dbg_addr; // Debug register address
output [15:0] dbg_din; // Debug register data input
output dbg_i2c_sda_out; // Debug interface: I2C SDA OUT
output dbg_rd; // Debug register data read
output dbg_wr; // Debug register data write
// INPUTs
//=========
input dbg_clk; // Debug unit clock
input [15:0] dbg_dout; // Debug register data output
input [6:0] dbg_i2c_addr; // Debug interface: I2C ADDRESS
input [6:0] dbg_i2c_broadcast; // Debug interface: I2C Broadcast Address (for multicore systems)
input dbg_i2c_scl; // Debug interface: I2C SCL
input dbg_i2c_sda_in; // Debug interface: I2C SDA IN
input dbg_rst; // Debug unit reset
input mem_burst; // Burst on going
input mem_burst_end; // End TX/RX burst
input mem_burst_rd; // Start TX burst
input mem_burst_wr; // Start RX burst
input mem_bw; // Burst byte width
//=============================================================================
// 1) I2C RECEIVE LINE SYNCHRONIZTION & FILTERING
//=============================================================================
// Synchronize SCL/SDA inputs
//--------------------------------
wire scl_sync_n;
omsp_sync_cell sync_cell_i2c_scl (
.data_out (scl_sync_n),
.data_in (~dbg_i2c_scl),
.clk (dbg_clk),
.rst (dbg_rst)
);
wire scl_sync = ~scl_sync_n;
wire sda_in_sync_n;
omsp_sync_cell sync_cell_i2c_sda (
.data_out (sda_in_sync_n),
.data_in (~dbg_i2c_sda_in),
.clk (dbg_clk),
.rst (dbg_rst)
);
wire sda_in_sync = ~sda_in_sync_n;
// SCL/SDA input buffers
//--------------------------------
reg [1:0] scl_buf;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) scl_buf <= 2'h3;
else scl_buf <= {scl_buf[0], scl_sync};
reg [1:0] sda_in_buf;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) sda_in_buf <= 2'h3;
else sda_in_buf <= {sda_in_buf[0], sda_in_sync};
// SCL/SDA Majority decision
//------------------------------
wire scl = (scl_sync & scl_buf[0]) |
(scl_sync & scl_buf[1]) |
(scl_buf[0] & scl_buf[1]);
wire sda_in = (sda_in_sync & sda_in_buf[0]) |
(sda_in_sync & sda_in_buf[1]) |
(sda_in_buf[0] & sda_in_buf[1]);
// SCL/SDA Edge detection
//------------------------------
// SDA Edge detection
reg sda_in_dly;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) sda_in_dly <= 1'b1;
else sda_in_dly <= sda_in;
wire sda_in_fe = sda_in_dly & ~sda_in;
wire sda_in_re = ~sda_in_dly & sda_in;
wire sda_in_edge = sda_in_dly ^ sda_in;
// SCL Edge detection
reg scl_dly;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) scl_dly <= 1'b1;
else scl_dly <= scl;
wire scl_fe = scl_dly & ~scl;
wire scl_re = ~scl_dly & scl;
wire scl_edge = scl_dly ^ scl;
// Delayed SCL Rising-Edge for SDA data sampling
reg [1:0] scl_re_dly;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) scl_re_dly <= 2'b00;
else scl_re_dly <= {scl_re_dly[0], scl_re};
wire scl_sample = scl_re_dly[1];
//=============================================================================
// 2) I2C START & STOP CONDITION DETECTION
//=============================================================================
//-----------------
// Start condition
//-----------------
wire start_detect = sda_in_fe & scl;
//-----------------
// Stop condition
//-----------------
wire stop_detect = sda_in_re & scl;
//-----------------
// I2C Slave Active
//-----------------
// The I2C logic will be activated whenever a start condition
// is detected and will be disactivated if the slave address
// doesn't match or if a stop condition is detected.
wire i2c_addr_not_valid;
reg i2c_active_seq;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) i2c_active_seq <= 1'b0;
else if (start_detect) i2c_active_seq <= 1'b1;
else if (stop_detect || i2c_addr_not_valid) i2c_active_seq <= 1'b0;
wire i2c_active = i2c_active_seq & ~stop_detect;
wire i2c_init = ~i2c_active | start_detect;
//=============================================================================
// 3) I2C STATE MACHINE
//=============================================================================
// State register/wires
reg [2:0] i2c_state;
reg [2:0] i2c_state_nxt;
// Utility signals
reg [8:0] shift_buf;
wire shift_rx_done;
wire shift_tx_done;
reg dbg_rd;
// State machine definition
parameter RX_ADDR = 3'h0;
parameter RX_ADDR_ACK = 3'h1;
parameter RX_DATA = 3'h2;
parameter RX_DATA_ACK = 3'h3;
parameter TX_DATA = 3'h4;
parameter TX_DATA_ACK = 3'h5;
// State transition
always @(i2c_state or i2c_init or shift_rx_done or i2c_addr_not_valid or shift_tx_done or scl_fe or shift_buf or sda_in)
case (i2c_state)
RX_ADDR : i2c_state_nxt = i2c_init ? RX_ADDR :
~shift_rx_done ? RX_ADDR :
i2c_addr_not_valid ? RX_ADDR :
RX_ADDR_ACK;
RX_ADDR_ACK : i2c_state_nxt = i2c_init ? RX_ADDR :
~scl_fe ? RX_ADDR_ACK :
shift_buf[0] ? TX_DATA :
RX_DATA;
RX_DATA : i2c_state_nxt = i2c_init ? RX_ADDR :
~shift_rx_done ? RX_DATA :
RX_DATA_ACK;
RX_DATA_ACK : i2c_state_nxt = i2c_init ? RX_ADDR :
~scl_fe ? RX_DATA_ACK :
RX_DATA;
TX_DATA : i2c_state_nxt = i2c_init ? RX_ADDR :
~shift_tx_done ? TX_DATA :
TX_DATA_ACK;
TX_DATA_ACK : i2c_state_nxt = i2c_init ? RX_ADDR :
~scl_fe ? TX_DATA_ACK :
~sda_in ? TX_DATA :
RX_ADDR;
// pragma coverage off
default : i2c_state_nxt = RX_ADDR;
// pragma coverage on
endcase
// State machine
always @(posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) i2c_state <= RX_ADDR;
else i2c_state <= i2c_state_nxt;
//=============================================================================
// 4) I2C SHIFT REGISTER (FOR RECEIVING & TRANSMITING)
//=============================================================================
wire shift_rx_en = ((i2c_state==RX_ADDR) | (i2c_state ==RX_DATA) | (i2c_state ==RX_DATA_ACK));
wire shift_tx_en = (i2c_state ==TX_DATA) | (i2c_state ==TX_DATA_ACK);
wire shift_tx_en_pre = (i2c_state_nxt==TX_DATA) | (i2c_state_nxt==TX_DATA_ACK);
assign shift_rx_done = shift_rx_en & scl_fe & shift_buf[8];
assign shift_tx_done = shift_tx_en & scl_fe & (shift_buf==9'h100);
wire shift_buf_rx_init = i2c_init | ((i2c_state==RX_ADDR_ACK) & scl_fe & ~shift_buf[0]) |
((i2c_state==RX_DATA_ACK) & scl_fe);
wire shift_buf_rx_en = shift_rx_en & scl_sample;
wire shift_buf_tx_init = ((i2c_state==RX_ADDR_ACK) & scl_re & shift_buf[0]) |
((i2c_state==TX_DATA_ACK) & scl_re);
wire shift_buf_tx_en = shift_tx_en_pre & scl_fe & (shift_buf!=9'h100);
wire [7:0] shift_tx_val;
wire [8:0] shift_buf_nxt = shift_buf_rx_init ? 9'h001 : // RX Init
shift_buf_tx_init ? {shift_tx_val, 1'b1} : // TX Init
shift_buf_rx_en ? {shift_buf[7:0], sda_in} : // RX Shift
shift_buf_tx_en ? {shift_buf[7:0], 1'b0} : // TX Shift
shift_buf[8:0]; // Hold
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) shift_buf <= 9'h001;
else shift_buf <= shift_buf_nxt;
// Detect when the received I2C device address is not valid
assign i2c_addr_not_valid = (i2c_state == RX_ADDR) && shift_rx_done && (
`ifdef DBG_I2C_BROADCAST
(shift_buf[7:1] != dbg_i2c_broadcast[6:0]) &&
`endif
(shift_buf[7:1] != dbg_i2c_addr[6:0]));
`ifdef DBG_I2C_BROADCAST
`else
wire [6:0] UNUSED_dbg_i2c_broadcast = dbg_i2c_broadcast;
`endif
// Utility signals
wire shift_rx_data_done = shift_rx_done & (i2c_state==RX_DATA);
wire shift_tx_data_done = shift_tx_done;
//=============================================================================
// 5) I2C TRANSMIT BUFFER
//=============================================================================
reg dbg_i2c_sda_out;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) dbg_i2c_sda_out <= 1'b1;
else if (scl_fe) dbg_i2c_sda_out <= ~((i2c_state_nxt==RX_ADDR_ACK) ||
(i2c_state_nxt==RX_DATA_ACK) ||
(shift_buf_tx_en & ~shift_buf[8]));
//=============================================================================
// 6) DEBUG INTERFACE STATE MACHINE
//=============================================================================
// State register/wires
reg [2:0] dbg_state;
reg [2:0] dbg_state_nxt;
// Utility signals
reg dbg_bw;
// State machine definition
parameter RX_CMD = 3'h0;
parameter RX_BYTE_LO = 3'h1;
parameter RX_BYTE_HI = 3'h2;
parameter TX_BYTE_LO = 3'h3;
parameter TX_BYTE_HI = 3'h4;
// State transition
always @(dbg_state or shift_rx_data_done or shift_tx_data_done or shift_buf or dbg_bw or
mem_burst_wr or mem_burst_rd or mem_burst or mem_burst_end or mem_bw)
case (dbg_state)
RX_CMD : dbg_state_nxt = mem_burst_wr ? RX_BYTE_LO :
mem_burst_rd ? TX_BYTE_LO :
~shift_rx_data_done ? RX_CMD :
shift_buf[7] ? RX_BYTE_LO :
TX_BYTE_LO;
RX_BYTE_LO : dbg_state_nxt = (mem_burst & mem_burst_end) ? RX_CMD :
~shift_rx_data_done ? RX_BYTE_LO :
(mem_burst & ~mem_burst_end) ?
(mem_bw ? RX_BYTE_LO :
RX_BYTE_HI) :
dbg_bw ? RX_CMD :
RX_BYTE_HI;
RX_BYTE_HI : dbg_state_nxt = ~shift_rx_data_done ? RX_BYTE_HI :
(mem_burst & ~mem_burst_end) ? RX_BYTE_LO :
RX_CMD;
TX_BYTE_LO : dbg_state_nxt = ~shift_tx_data_done ? TX_BYTE_LO :
( mem_burst & mem_bw) ? TX_BYTE_LO :
( mem_burst & ~mem_bw) ? TX_BYTE_HI :
~dbg_bw ? TX_BYTE_HI :
RX_CMD;
TX_BYTE_HI : dbg_state_nxt = ~shift_tx_data_done ? TX_BYTE_HI :
mem_burst ? TX_BYTE_LO :
RX_CMD;
// pragma coverage off
default : dbg_state_nxt = RX_CMD;
// pragma coverage on
endcase
// State machine
always @(posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) dbg_state <= RX_CMD;
else dbg_state <= dbg_state_nxt;
// Utility signals
wire cmd_valid = (dbg_state==RX_CMD) & shift_rx_data_done;
wire rx_lo_valid = (dbg_state==RX_BYTE_LO) & shift_rx_data_done;
wire rx_hi_valid = (dbg_state==RX_BYTE_HI) & shift_rx_data_done;
//=============================================================================
// 7) REGISTER READ/WRITE ACCESS
//=============================================================================
parameter MEM_DATA = 6'h06;
// Debug register address & bit width
reg [5:0] dbg_addr;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst)
begin
dbg_bw <= 1'b0;
dbg_addr <= 6'h00;
end
else if (cmd_valid)
begin
dbg_bw <= shift_buf[6];
dbg_addr <= shift_buf[5:0];
end
else if (mem_burst)
begin
dbg_bw <= mem_bw;
dbg_addr <= MEM_DATA;
end
// Debug register data input
reg [7:0] dbg_din_lo;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) dbg_din_lo <= 8'h00;
else if (rx_lo_valid) dbg_din_lo <= shift_buf[7:0];
reg [7:0] dbg_din_hi;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) dbg_din_hi <= 8'h00;
else if (rx_lo_valid) dbg_din_hi <= 8'h00;
else if (rx_hi_valid) dbg_din_hi <= shift_buf[7:0];
assign dbg_din = {dbg_din_hi, dbg_din_lo};
// Debug register data write command
reg dbg_wr;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) dbg_wr <= 1'b0;
else dbg_wr <= (mem_burst & mem_bw) ? rx_lo_valid :
(mem_burst & ~mem_bw) ? rx_hi_valid :
dbg_bw ? rx_lo_valid :
rx_hi_valid;
// Debug register data read command
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) dbg_rd <= 1'b0;
else dbg_rd <= (mem_burst & mem_bw) ? (shift_tx_data_done & (dbg_state==TX_BYTE_LO)) :
(mem_burst & ~mem_bw) ? (shift_tx_data_done & (dbg_state==TX_BYTE_HI)) :
cmd_valid ? ~shift_buf[7] :
1'b0;
// Debug register data read value
assign shift_tx_val = (dbg_state==TX_BYTE_HI) ? dbg_dout[15:8] :
dbg_dout[7:0];
endmodule
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_undefines.v"
`endif
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.1
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
module tri_intersect_fsub_32ns_32ns_32_9_full_dsp
#(parameter
ID = 0,
NUM_STAGE = 9,
din0_WIDTH = 32,
din1_WIDTH = 32,
dout_WIDTH = 32
)(
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [31:0] a_tdata;
wire b_tvalid;
wire [31:0] b_tdata;
wire r_tvalid;
wire [31:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
//------------------------Instantiation------------------
tri_intersect_ap_fsub_7_full_dsp_32 tri_intersect_ap_fsub_7_full_dsp_32_u (
.aclk ( aclk ),
.aclken ( aclken ),
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.s_axis_b_tvalid ( b_tvalid ),
.s_axis_b_tdata ( b_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1==='bx ? 'b0 : din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1==='bx ? 'b0 : din1_buf1;
assign dout = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
endmodule
|
(** * Imp: Simple Imperative Programs *)
(** In this chapter, we take a more serious look at how to use Coq to
study other things. Our case study is a _simple imperative
programming language_ called Imp, embodying a tiny core fragment
of conventional mainstream languages such as C and Java. Here is
a familiar mathematical function written in Imp.
Z ::= X;;
Y ::= 1;;
WHILE ~(Z = 0) DO
Y ::= Y * Z;;
Z ::= Z - 1
END
*)
(** We concentrate here on defining the _syntax_ and _semantics_ of
Imp; later chapters in _Programming Language Foundations_
(_Software Foundations_, volume 2) develop a theory of
_program equivalence_ and introduce _Hoare Logic_, a widely
used logic for reasoning about imperative programs. *)
Set Warnings "-notation-overridden,-parsing".
From Coq Require Import Bool.Bool.
From Coq Require Import Init.Nat.
From Coq Require Import Arith.Arith.
From Coq Require Import Arith.EqNat.
From Coq Require Import omega.Omega.
From Coq Require Import Lists.List.
From Coq Require Import Strings.String.
Import ListNotations.
From PLF Require Import Maps.
(* ################################################################# *)
(** * Arithmetic and Boolean Expressions *)
(** We'll present Imp in three parts: first a core language of
_arithmetic and boolean expressions_, then an extension of these
expressions with _variables_, and finally a language of _commands_
including assignment, conditions, sequencing, and loops. *)
(* ================================================================= *)
(** ** Syntax *)
Module AExp.
(** These two definitions specify the _abstract syntax_ of
arithmetic and boolean expressions. *)
Inductive aexp : Type :=
| ANum (n : nat)
| APlus (a1 a2 : aexp)
| AMinus (a1 a2 : aexp)
| AMult (a1 a2 : aexp).
Inductive bexp : Type :=
| BTrue
| BFalse
| BEq (a1 a2 : aexp)
| BLe (a1 a2 : aexp)
| BNot (b : bexp)
| BAnd (b1 b2 : bexp).
(** In this chapter, we'll mostly elide the translation from the
concrete syntax that a programmer would actually write to these
abstract syntax trees -- the process that, for example, would
translate the string ["1 + 2 * 3"] to the AST
APlus (ANum 1) (AMult (ANum 2) (ANum 3)).
The optional chapter [ImpParser] develops a simple lexical
analyzer and parser that can perform this translation. You do
_not_ need to understand that chapter to understand this one, but
if you haven't already taken a course where these techniques are
covered (e.g., a compilers course) you may want to skim it. *)
(** For comparison, here's a conventional BNF (Backus-Naur Form)
grammar defining the same abstract syntax:
a ::= nat
| a + a
| a - a
| a * a
b ::= true
| false
| a = a
| a <= a
| ~ b
| b && b
*)
(** Compared to the Coq version above...
- The BNF is more informal -- for example, it gives some
suggestions about the surface syntax of expressions (like the
fact that the addition operation is written with an infix
[+]) while leaving other aspects of lexical analysis and
parsing (like the relative precedence of [+], [-], and
[*], the use of parens to group subexpressions, etc.)
unspecified. Some additional information -- and human
intelligence -- would be required to turn this description
into a formal definition, e.g., for implementing a compiler.
The Coq version consistently omits all this information and
concentrates on the abstract syntax only.
- Conversely, the BNF version is lighter and easier to read.
Its informality makes it flexible, a big advantage in
situations like discussions at the blackboard, where
conveying general ideas is more important than getting every
detail nailed down precisely.
Indeed, there are dozens of BNF-like notations and people
switch freely among them, usually without bothering to say
which kind of BNF they're using because there is no need to:
a rough-and-ready informal understanding is all that's
important.
It's good to be comfortable with both sorts of notations: informal
ones for communicating between humans and formal ones for carrying
out implementations and proofs. *)
(* ================================================================= *)
(** ** Evaluation *)
(** _Evaluating_ an arithmetic expression produces a number. *)
Fixpoint aeval (a : aexp) : nat :=
match a with
| ANum n => n
| APlus a1 a2 => (aeval a1) + (aeval a2)
| AMinus a1 a2 => (aeval a1) - (aeval a2)
| AMult a1 a2 => (aeval a1) * (aeval a2)
end.
Example test_aeval1:
aeval (APlus (ANum 2) (ANum 2)) = 4.
Proof. reflexivity. Qed.
(** Similarly, evaluating a boolean expression yields a boolean. *)
Fixpoint beval (b : bexp) : bool :=
match b with
| BTrue => true
| BFalse => false
| BEq a1 a2 => (aeval a1) =? (aeval a2)
| BLe a1 a2 => (aeval a1) <=? (aeval a2)
| BNot b1 => negb (beval b1)
| BAnd b1 b2 => andb (beval b1) (beval b2)
end.
(* ================================================================= *)
(** ** Optimization *)
(** We haven't defined very much yet, but we can already get
some mileage out of the definitions. Suppose we define a function
that takes an arithmetic expression and slightly simplifies it,
changing every occurrence of [0 + e] (i.e., [(APlus (ANum 0) e])
into just [e]. *)
Fixpoint optimize_0plus (a:aexp) : aexp :=
match a with
| ANum n => ANum n
| APlus (ANum 0) e2 => optimize_0plus e2
| APlus e1 e2 => APlus (optimize_0plus e1) (optimize_0plus e2)
| AMinus e1 e2 => AMinus (optimize_0plus e1) (optimize_0plus e2)
| AMult e1 e2 => AMult (optimize_0plus e1) (optimize_0plus e2)
end.
(** To make sure our optimization is doing the right thing we
can test it on some examples and see if the output looks OK. *)
Example test_optimize_0plus:
optimize_0plus (APlus (ANum 2)
(APlus (ANum 0)
(APlus (ANum 0) (ANum 1))))
= APlus (ANum 2) (ANum 1).
Proof. reflexivity. Qed.
(** But if we want to be sure the optimization is correct --
i.e., that evaluating an optimized expression gives the same
result as the original -- we should prove it. *)
Theorem optimize_0plus_sound: forall a,
aeval (optimize_0plus a) = aeval a.
Proof.
intros a. induction a.
- (* ANum *) reflexivity.
- (* APlus *) destruct a1 eqn:Ea1.
+ (* a1 = ANum n *) destruct n eqn:En.
* (* n = 0 *) simpl. apply IHa2.
* (* n <> 0 *) simpl. rewrite IHa2. reflexivity.
+ (* a1 = APlus a1_1 a1_2 *)
simpl. simpl in IHa1. rewrite IHa1.
rewrite IHa2. reflexivity.
+ (* a1 = AMinus a1_1 a1_2 *)
simpl. simpl in IHa1. rewrite IHa1.
rewrite IHa2. reflexivity.
+ (* a1 = AMult a1_1 a1_2 *)
simpl. simpl in IHa1. rewrite IHa1.
rewrite IHa2. reflexivity.
- (* AMinus *)
simpl. rewrite IHa1. rewrite IHa2. reflexivity.
- (* AMult *)
simpl. rewrite IHa1. rewrite IHa2. reflexivity. Qed.
(* ################################################################# *)
(** * Coq Automation *)
(** The amount of repetition in this last proof is a little
annoying. And if either the language of arithmetic expressions or
the optimization being proved sound were significantly more
complex, it would start to be a real problem.
So far, we've been doing all our proofs using just a small handful
of Coq's tactics and completely ignoring its powerful facilities
for constructing parts of proofs automatically. This section
introduces some of these facilities, and we will see more over the
next several chapters. Getting used to them will take some
energy -- Coq's automation is a power tool -- but it will allow us
to scale up our efforts to more complex definitions and more
interesting properties without becoming overwhelmed by boring,
repetitive, low-level details. *)
(* ================================================================= *)
(** ** Tacticals *)
(** _Tacticals_ is Coq's term for tactics that take other tactics as
arguments -- "higher-order tactics," if you will. *)
(* ----------------------------------------------------------------- *)
(** *** The [try] Tactical *)
(** If [T] is a tactic, then [try T] is a tactic that is just like [T]
except that, if [T] fails, [try T] _successfully_ does nothing at
all (rather than failing). *)
Theorem silly1 : forall ae, aeval ae = aeval ae.
Proof. try reflexivity. (* This just does [reflexivity]. *) Qed.
Theorem silly2 : forall (P : Prop), P -> P.
Proof.
intros P HP.
try reflexivity. (* Just [reflexivity] would have failed. *)
apply HP. (* We can still finish the proof in some other way. *)
Qed.
(** There is no real reason to use [try] in completely manual
proofs like these, but it is very useful for doing automated
proofs in conjunction with the [;] tactical, which we show
next. *)
(* ----------------------------------------------------------------- *)
(** *** The [;] Tactical (Simple Form) *)
(** In its most common form, the [;] tactical takes two tactics as
arguments. The compound tactic [T;T'] first performs [T] and then
performs [T'] on _each subgoal_ generated by [T]. *)
(** For example, consider the following trivial lemma: *)
Lemma foo : forall n, 0 <=? n = true.
Proof.
intros.
destruct n.
(* Leaves two subgoals, which are discharged identically... *)
- (* n=0 *) simpl. reflexivity.
- (* n=Sn' *) simpl. reflexivity.
Qed.
(** We can simplify this proof using the [;] tactical: *)
Lemma foo' : forall n, 0 <=? n = true.
Proof.
intros.
(* [destruct] the current goal *)
destruct n;
(* then [simpl] each resulting subgoal *)
simpl;
(* and do [reflexivity] on each resulting subgoal *)
reflexivity.
Qed.
(** Using [try] and [;] together, we can get rid of the repetition in
the proof that was bothering us a little while ago. *)
Theorem optimize_0plus_sound': forall a,
aeval (optimize_0plus a) = aeval a.
Proof.
intros a.
induction a;
(* Most cases follow directly by the IH... *)
try (simpl; rewrite IHa1; rewrite IHa2; reflexivity).
(* ... but the remaining cases -- ANum and APlus --
are different: *)
- (* ANum *) reflexivity.
- (* APlus *)
destruct a1 eqn:Ea1;
(* Again, most cases follow directly by the IH: *)
try (simpl; simpl in IHa1; rewrite IHa1;
rewrite IHa2; reflexivity).
(* The interesting case, on which the [try...]
does nothing, is when [e1 = ANum n]. In this
case, we have to destruct [n] (to see whether
the optimization applies) and rewrite with the
induction hypothesis. *)
+ (* a1 = ANum n *) destruct n eqn:En;
simpl; rewrite IHa2; reflexivity. Qed.
(** Coq experts often use this "[...; try... ]" idiom after a tactic
like [induction] to take care of many similar cases all at once.
Naturally, this practice has an analog in informal proofs. For
example, here is an informal proof of the optimization theorem
that matches the structure of the formal one:
_Theorem_: For all arithmetic expressions [a],
aeval (optimize_0plus a) = aeval a.
_Proof_: By induction on [a]. Most cases follow directly from the
IH. The remaining cases are as follows:
- Suppose [a = ANum n] for some [n]. We must show
aeval (optimize_0plus (ANum n)) = aeval (ANum n).
This is immediate from the definition of [optimize_0plus].
- Suppose [a = APlus a1 a2] for some [a1] and [a2]. We must
show
aeval (optimize_0plus (APlus a1 a2)) = aeval (APlus a1 a2).
Consider the possible forms of [a1]. For most of them,
[optimize_0plus] simply calls itself recursively for the
subexpressions and rebuilds a new expression of the same form
as [a1]; in these cases, the result follows directly from the
IH.
The interesting case is when [a1 = ANum n] for some [n]. If
[n = 0], then
optimize_0plus (APlus a1 a2) = optimize_0plus a2
and the IH for [a2] is exactly what we need. On the other
hand, if [n = S n'] for some [n'], then again [optimize_0plus]
simply calls itself recursively, and the result follows from
the IH. [] *)
(** However, this proof can still be improved: the first case (for
[a = ANum n]) is very trivial -- even more trivial than the cases
that we said simply followed from the IH -- yet we have chosen to
write it out in full. It would be better and clearer to drop it
and just say, at the top, "Most cases are either immediate or
direct from the IH. The only interesting case is the one for
[APlus]..." We can make the same improvement in our formal proof
too. Here's how it looks: *)
Theorem optimize_0plus_sound'': forall a,
aeval (optimize_0plus a) = aeval a.
Proof.
intros a.
induction a;
(* Most cases follow directly by the IH *)
try (simpl; rewrite IHa1; rewrite IHa2; reflexivity);
(* ... or are immediate by definition *)
try reflexivity.
(* The interesting case is when a = APlus a1 a2. *)
- (* APlus *)
destruct a1; try (simpl; simpl in IHa1; rewrite IHa1;
rewrite IHa2; reflexivity).
+ (* a1 = ANum n *) destruct n;
simpl; rewrite IHa2; reflexivity. Qed.
(* ----------------------------------------------------------------- *)
(** *** The [;] Tactical (General Form) *)
(** The [;] tactical also has a more general form than the simple
[T;T'] we've seen above. If [T], [T1], ..., [Tn] are tactics,
then
T; [T1 | T2 | ... | Tn]
is a tactic that first performs [T] and then performs [T1] on the
first subgoal generated by [T], performs [T2] on the second
subgoal, etc.
So [T;T'] is just special notation for the case when all of the
[Ti]'s are the same tactic; i.e., [T;T'] is shorthand for:
T; [T' | T' | ... | T']
*)
(* ----------------------------------------------------------------- *)
(** *** The [repeat] Tactical *)
(** The [repeat] tactical takes another tactic and keeps applying this
tactic until it fails. Here is an example showing that [10] is in
a long list using repeat. *)
Theorem In10 : In 10 [1;2;3;4;5;6;7;8;9;10].
Proof.
repeat (try (left; reflexivity); right).
Qed.
(** The tactic [repeat T] never fails: if the tactic [T] doesn't apply
to the original goal, then repeat still succeeds without changing
the original goal (i.e., it repeats zero times). *)
Theorem In10' : In 10 [1;2;3;4;5;6;7;8;9;10].
Proof.
repeat (left; reflexivity).
repeat (right; try (left; reflexivity)).
Qed.
(** The tactic [repeat T] also does not have any upper bound on the
number of times it applies [T]. If [T] is a tactic that always
succeeds, then repeat [T] will loop forever (e.g., [repeat simpl]
loops, since [simpl] always succeeds). While evaluation in Coq's
term language, Gallina, is guaranteed to terminate, tactic
evaluation is not! This does not affect Coq's logical
consistency, however, since the job of [repeat] and other tactics
is to guide Coq in constructing proofs; if the construction
process diverges (i.e., it does not terminate), this simply means
that we have failed to construct a proof, not that we have
constructed a wrong one. *)
(** **** Exercise: 3 stars, standard (optimize_0plus_b_sound)
Since the [optimize_0plus] transformation doesn't change the value
of [aexp]s, we should be able to apply it to all the [aexp]s that
appear in a [bexp] without changing the [bexp]'s value. Write a
function that performs this transformation on [bexp]s and prove
it is sound. Use the tacticals we've just seen to make the proof
as elegant as possible. *)
Fixpoint optimize_0plus_b (b : bexp) : bexp
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
Theorem optimize_0plus_b_sound : forall b,
beval (optimize_0plus_b b) = beval b.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 4 stars, standard, optional (optimize)
_Design exercise_: The optimization implemented by our
[optimize_0plus] function is only one of many possible
optimizations on arithmetic and boolean expressions. Write a more
sophisticated optimizer and prove it correct. (You will probably
find it easiest to start small -- add just a single, simple
optimization and its correctness proof -- and build up to
something more interesting incrementially.) *)
(* FILL IN HERE
[] *)
(* ================================================================= *)
(** ** Defining New Tactic Notations *)
(** Coq also provides several ways of "programming" tactic
scripts.
- The [Tactic Notation] idiom illustrated below gives a handy way
to define "shorthand tactics" that bundle several tactics into a
single command.
- For more sophisticated programming, Coq offers a built-in
language called [Ltac] with primitives that can examine and
modify the proof state. The details are a bit too complicated
to get into here (and it is generally agreed that [Ltac] is not
the most beautiful part of Coq's design!), but they can be found
in the reference manual and other books on Coq, and there are
many examples of [Ltac] definitions in the Coq standard library
that you can use as examples.
- There is also an OCaml API, which can be used to build tactics
that access Coq's internal structures at a lower level, but this
is seldom worth the trouble for ordinary Coq users.
The [Tactic Notation] mechanism is the easiest to come to grips
with, and it offers plenty of power for many purposes. Here's an
example. *)
Tactic Notation "simpl_and_try" tactic(c) :=
simpl;
try c.
(** This defines a new tactical called [simpl_and_try] that takes one
tactic [c] as an argument and is defined to be equivalent to the
tactic [simpl; try c]. Now writing "[simpl_and_try reflexivity.]"
in a proof will be the same as writing "[simpl; try reflexivity.]" *)
(* ================================================================= *)
(** ** The [omega] Tactic *)
(** The [omega] tactic implements a decision procedure for a subset of
first-order logic called _Presburger arithmetic_. It is based on
the Omega algorithm invented by William Pugh [Pugh 1991] (in Bib.v).
If the goal is a universally quantified formula made out of
- numeric constants, addition ([+] and [S]), subtraction ([-]
and [pred]), and multiplication by constants (this is what
makes it Presburger arithmetic),
- equality ([=] and [<>]) and ordering ([<=]), and
- the logical connectives [/\], [\/], [~], and [->],
then invoking [omega] will either solve the goal or fail, meaning
that the goal is actually false. (If the goal is _not_ of this
form, [omega] will also fail.) *)
Example silly_presburger_example : forall m n o p,
m + n <= n + o /\ o + 3 = p + 3 ->
m <= p.
Proof.
intros. omega.
Qed.
(** (Note the [From Coq Require Import omega.Omega.] at the top of
the file.) *)
(* ================================================================= *)
(** ** A Few More Handy Tactics *)
(** Finally, here are some miscellaneous tactics that you may find
convenient.
- [clear H]: Delete hypothesis [H] from the context.
- [subst x]: For a variable [x], find an assumption [x = e] or
[e = x] in the context, replace [x] with [e] throughout the
context and current goal, and clear the assumption.
- [subst]: Substitute away _all_ assumptions of the form [x = e]
or [e = x] (where [x] is a variable).
- [rename... into...]: Change the name of a hypothesis in the
proof context. For example, if the context includes a variable
named [x], then [rename x into y] will change all occurrences
of [x] to [y].
- [assumption]: Try to find a hypothesis [H] in the context that
exactly matches the goal; if one is found, behave like [apply
H].
- [contradiction]: Try to find a hypothesis [H] in the current
context that is logically equivalent to [False]. If one is
found, solve the goal.
- [constructor]: Try to find a constructor [c] (from some
[Inductive] definition in the current environment) that can be
applied to solve the current goal. If one is found, behave
like [apply c].
We'll see examples of all of these as we go along. *)
(* ################################################################# *)
(** * Evaluation as a Relation *)
(** We have presented [aeval] and [beval] as functions defined by
[Fixpoint]s. Another way to think about evaluation -- one that we
will see is often more flexible -- is as a _relation_ between
expressions and their values. This leads naturally to [Inductive]
definitions like the following one for arithmetic expressions... *)
Module aevalR_first_try.
Inductive aevalR : aexp -> nat -> Prop :=
| E_ANum n :
aevalR (ANum n) n
| E_APlus (e1 e2: aexp) (n1 n2: nat) :
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (APlus e1 e2) (n1 + n2)
| E_AMinus (e1 e2: aexp) (n1 n2: nat) :
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (AMinus e1 e2) (n1 - n2)
| E_AMult (e1 e2: aexp) (n1 n2: nat) :
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (AMult e1 e2) (n1 * n2).
Module TooHardToRead.
(* A small notational aside. We would previously have written the
definition of [aevalR] like this, with explicit names for the
hypotheses in each case: *)
Inductive aevalR : aexp -> nat -> Prop :=
| E_ANum n :
aevalR (ANum n) n
| E_APlus (e1 e2: aexp) (n1 n2: nat)
(H1 : aevalR e1 n1)
(H2 : aevalR e2 n2) :
aevalR (APlus e1 e2) (n1 + n2)
| E_AMinus (e1 e2: aexp) (n1 n2: nat)
(H1 : aevalR e1 n1)
(H2 : aevalR e2 n2) :
aevalR (AMinus e1 e2) (n1 - n2)
| E_AMult (e1 e2: aexp) (n1 n2: nat)
(H1 : aevalR e1 n1)
(H2 : aevalR e2 n2) :
aevalR (AMult e1 e2) (n1 * n2).
(** Instead, we've chosen to leave the hypotheses anonymous, just
giving their types. This style gives us less control over the
names that Coq chooses during proofs involving [aevalR], but it
makes the definition itself quite a bit lighter. *)
End TooHardToRead.
(** It will be convenient to have an infix notation for
[aevalR]. We'll write [e \\ n] to mean that arithmetic expression
[e] evaluates to value [n]. *)
Notation "e '\\' n"
:= (aevalR e n)
(at level 50, left associativity)
: type_scope.
End aevalR_first_try.
(** In fact, Coq provides a way to use this notation in the
definition of [aevalR] itself. This reduces confusion by avoiding
situations where we're working on a proof involving statements in
the form [e \\ n] but we have to refer back to a definition
written using the form [aevalR e n].
We do this by first "reserving" the notation, then giving the
definition together with a declaration of what the notation
means. *)
Reserved Notation "e '\\' n" (at level 90, left associativity).
Inductive aevalR : aexp -> nat -> Prop :=
| E_ANum (n : nat) :
(ANum n) \\ n
| E_APlus (e1 e2 : aexp) (n1 n2 : nat) :
(e1 \\ n1) -> (e2 \\ n2) -> (APlus e1 e2) \\ (n1 + n2)
| E_AMinus (e1 e2 : aexp) (n1 n2 : nat) :
(e1 \\ n1) -> (e2 \\ n2) -> (AMinus e1 e2) \\ (n1 - n2)
| E_AMult (e1 e2 : aexp) (n1 n2 : nat) :
(e1 \\ n1) -> (e2 \\ n2) -> (AMult e1 e2) \\ (n1 * n2)
where "e '\\' n" := (aevalR e n) : type_scope.
(* ================================================================= *)
(** ** Inference Rule Notation *)
(** In informal discussions, it is convenient to write the rules
for [aevalR] and similar relations in the more readable graphical
form of _inference rules_, where the premises above the line
justify the conclusion below the line (we have already seen them
in the [IndProp] chapter). *)
(** For example, the constructor [E_APlus]...
| E_APlus : forall (e1 e2: aexp) (n1 n2: nat),
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (APlus e1 e2) (n1 + n2)
...would be written like this as an inference rule:
e1 \\ n1
e2 \\ n2
-------------------- (E_APlus)
APlus e1 e2 \\ n1+n2
*)
(** Formally, there is nothing deep about inference rules: they
are just implications. You can read the rule name on the right as
the name of the constructor and read each of the linebreaks
between the premises above the line (as well as the line itself)
as [->]. All the variables mentioned in the rule ([e1], [n1],
etc.) are implicitly bound by universal quantifiers at the
beginning. (Such variables are often called _metavariables_ to
distinguish them from the variables of the language we are
defining. At the moment, our arithmetic expressions don't include
variables, but we'll soon be adding them.) The whole collection
of rules is understood as being wrapped in an [Inductive]
declaration. In informal prose, this is either elided or else
indicated by saying something like "Let [aevalR] be the smallest
relation closed under the following rules...". *)
(** For example, [\\] is the smallest relation closed under these
rules:
----------- (E_ANum)
ANum n \\ n
e1 \\ n1
e2 \\ n2
-------------------- (E_APlus)
APlus e1 e2 \\ n1+n2
e1 \\ n1
e2 \\ n2
--------------------- (E_AMinus)
AMinus e1 e2 \\ n1-n2
e1 \\ n1
e2 \\ n2
-------------------- (E_AMult)
AMult e1 e2 \\ n1*n2
*)
(** **** Exercise: 1 star, standard, optional (beval_rules)
Here, again, is the Coq definition of the [beval] function:
Fixpoint beval (e : bexp) : bool :=
match e with
| BTrue => true
| BFalse => false
| BEq a1 a2 => (aeval a1) =? (aeval a2)
| BLe a1 a2 => (aeval a1) <=? (aeval a2)
| BNot b1 => negb (beval b1)
| BAnd b1 b2 => andb (beval b1) (beval b2)
end.
Write out a corresponding definition of boolean evaluation as a
relation (in inference rule notation). *)
(* FILL IN HERE *)
(* Do not modify the following line: *)
Definition manual_grade_for_beval_rules : option (nat*string) := None.
(** [] *)
(* ================================================================= *)
(** ** Equivalence of the Definitions *)
(** It is straightforward to prove that the relational and functional
definitions of evaluation agree: *)
Theorem aeval_iff_aevalR : forall a n,
(a \\ n) <-> aeval a = n.
Proof.
split.
- (* -> *)
intros H.
induction H; simpl.
+ (* E_ANum *)
reflexivity.
+ (* E_APlus *)
rewrite IHaevalR1. rewrite IHaevalR2. reflexivity.
+ (* E_AMinus *)
rewrite IHaevalR1. rewrite IHaevalR2. reflexivity.
+ (* E_AMult *)
rewrite IHaevalR1. rewrite IHaevalR2. reflexivity.
- (* <- *)
generalize dependent n.
induction a;
simpl; intros; subst.
+ (* ANum *)
apply E_ANum.
+ (* APlus *)
apply E_APlus.
apply IHa1. reflexivity.
apply IHa2. reflexivity.
+ (* AMinus *)
apply E_AMinus.
apply IHa1. reflexivity.
apply IHa2. reflexivity.
+ (* AMult *)
apply E_AMult.
apply IHa1. reflexivity.
apply IHa2. reflexivity.
Qed.
(** We can make the proof quite a bit shorter by making more
use of tacticals. *)
Theorem aeval_iff_aevalR' : forall a n,
(a \\ n) <-> aeval a = n.
Proof.
(* WORKED IN CLASS *)
split.
- (* -> *)
intros H; induction H; subst; reflexivity.
- (* <- *)
generalize dependent n.
induction a; simpl; intros; subst; constructor;
try apply IHa1; try apply IHa2; reflexivity.
Qed.
(** **** Exercise: 3 stars, standard (bevalR)
Write a relation [bevalR] in the same style as
[aevalR], and prove that it is equivalent to [beval]. *)
Inductive bevalR: bexp -> bool -> Prop :=
(* FILL IN HERE *)
.
Lemma beval_iff_bevalR : forall b bv,
bevalR b bv <-> beval b = bv.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
End AExp.
(* ================================================================= *)
(** ** Computational vs. Relational Definitions *)
(** For the definitions of evaluation for arithmetic and boolean
expressions, the choice of whether to use functional or relational
definitions is mainly a matter of taste: either way works.
However, there are circumstances where relational definitions of
evaluation work much better than functional ones. *)
Module aevalR_division.
(** For example, suppose that we wanted to extend the arithmetic
operations with division: *)
Inductive aexp : Type :=
| ANum (n : nat)
| APlus (a1 a2 : aexp)
| AMinus (a1 a2 : aexp)
| AMult (a1 a2 : aexp)
| ADiv (a1 a2 : aexp). (* <--- NEW *)
(** Extending the definition of [aeval] to handle this new operation
would not be straightforward (what should we return as the result
of [ADiv (ANum 5) (ANum 0)]?). But extending [aevalR] is
straightforward. *)
Reserved Notation "e '\\' n"
(at level 90, left associativity).
Inductive aevalR : aexp -> nat -> Prop :=
| E_ANum (n : nat) :
(ANum n) \\ n
| E_APlus (a1 a2 : aexp) (n1 n2 : nat) :
(a1 \\ n1) -> (a2 \\ n2) -> (APlus a1 a2) \\ (n1 + n2)
| E_AMinus (a1 a2 : aexp) (n1 n2 : nat) :
(a1 \\ n1) -> (a2 \\ n2) -> (AMinus a1 a2) \\ (n1 - n2)
| E_AMult (a1 a2 : aexp) (n1 n2 : nat) :
(a1 \\ n1) -> (a2 \\ n2) -> (AMult a1 a2) \\ (n1 * n2)
| E_ADiv (a1 a2 : aexp) (n1 n2 n3 : nat) :
(a1 \\ n1) -> (a2 \\ n2) -> (n2 > 0) ->
(mult n2 n3 = n1) -> (ADiv a1 a2) \\ n3
where "a '\\' n" := (aevalR a n) : type_scope.
End aevalR_division.
Module aevalR_extended.
(** Or suppose that we want to extend the arithmetic operations by a
nondeterministic number generator [any] that, when evaluated, may
yield any number. (Note that this is not the same as making a
_probabilistic_ choice among all possible numbers -- we're not
specifying any particular probability distribution for the
results, just saying what results are _possible_.) *)
Reserved Notation "e '\\' n" (at level 90, left associativity).
Inductive aexp : Type :=
| AAny (* <--- NEW *)
| ANum (n : nat)
| APlus (a1 a2 : aexp)
| AMinus (a1 a2 : aexp)
| AMult (a1 a2 : aexp).
(** Again, extending [aeval] would be tricky, since now evaluation is
_not_ a deterministic function from expressions to numbers, but
extending [aevalR] is no problem... *)
Inductive aevalR : aexp -> nat -> Prop :=
| E_Any (n : nat) :
AAny \\ n (* <--- NEW *)
| E_ANum (n : nat) :
(ANum n) \\ n
| E_APlus (a1 a2 : aexp) (n1 n2 : nat) :
(a1 \\ n1) -> (a2 \\ n2) -> (APlus a1 a2) \\ (n1 + n2)
| E_AMinus (a1 a2 : aexp) (n1 n2 : nat) :
(a1 \\ n1) -> (a2 \\ n2) -> (AMinus a1 a2) \\ (n1 - n2)
| E_AMult (a1 a2 : aexp) (n1 n2 : nat) :
(a1 \\ n1) -> (a2 \\ n2) -> (AMult a1 a2) \\ (n1 * n2)
where "a '\\' n" := (aevalR a n) : type_scope.
End aevalR_extended.
(** At this point you maybe wondering: which style should I use by
default? In the examples we've just seen, relational definitions
turned out to be more useful than functional ones. For situations
like these, where the thing being defined is not easy to express
as a function, or indeed where it is _not_ a function, there is no
real choice. But what about when both styles are workable?
One point in favor of relational definitions is that they can be
more elegant and easier to understand.
Another is that Coq automatically generates nice inversion and
induction principles from [Inductive] definitions. *)
(** On the other hand, functional definitions can often be more
convenient:
- Functions are by definition deterministic and defined on all
arguments; for a relation we have to show these properties
explicitly if we need them.
- With functions we can also take advantage of Coq's computation
mechanism to simplify expressions during proofs.
Furthermore, functions can be directly "extracted" from Gallina to
executable code in OCaml or Haskell. *)
(** Ultimately, the choice often comes down to either the specifics of
a particular situation or simply a question of taste. Indeed, in
large Coq developments it is common to see a definition given in
_both_ functional and relational styles, plus a lemma stating that
the two coincide, allowing further proofs to switch from one point
of view to the other at will. *)
(* ################################################################# *)
(** * Expressions With Variables *)
(** Back to defining Imp. The next thing we need to do is to enrich
our arithmetic and boolean expressions with variables. To keep
things simple, we'll assume that all variables are global and that
they only hold numbers. *)
(* ================================================================= *)
(** ** States *)
(** Since we'll want to look variables up to find out their current
values, we'll reuse maps from the [Maps] chapter, and
[string]s will be used to represent variables in Imp.
A _machine state_ (or just _state_) represents the current values
of _all_ variables at some point in the execution of a program. *)
(** For simplicity, we assume that the state is defined for
_all_ variables, even though any given program is only going to
mention a finite number of them. The state captures all of the
information stored in memory. For Imp programs, because each
variable stores a natural number, we can represent the state as a
mapping from strings to [nat], and will use [0] as default value
in the store. For more complex programming languages, the state
might have more structure. *)
Definition state := total_map nat.
(* ================================================================= *)
(** ** Syntax *)
(** We can add variables to the arithmetic expressions we had before by
simply adding one more constructor: *)
Inductive aexp : Type :=
| ANum (n : nat)
| AId (x : string) (* <--- NEW *)
| APlus (a1 a2 : aexp)
| AMinus (a1 a2 : aexp)
| AMult (a1 a2 : aexp).
(** Defining a few variable names as notational shorthands will make
examples easier to read: *)
Definition W : string := "W".
Definition X : string := "X".
Definition Y : string := "Y".
Definition Z : string := "Z".
(** (This convention for naming program variables ([X], [Y],
[Z]) clashes a bit with our earlier use of uppercase letters for
types. Since we're not using polymorphism heavily in the chapters
developed to Imp, this overloading should not cause confusion.) *)
(** The definition of [bexp]s is unchanged (except that it now refers
to the new [aexp]s): *)
Inductive bexp : Type :=
| BTrue
| BFalse
| BEq (a1 a2 : aexp)
| BLe (a1 a2 : aexp)
| BNot (b : bexp)
| BAnd (b1 b2 : bexp).
(* ================================================================= *)
(** ** Notations *)
(** To make Imp programs easier to read and write, we introduce some
notations and implicit coercions.
You do not need to understand exactly what these declarations do.
Briefly, though, the [Coercion] declaration in Coq stipulates that
a function (or constructor) can be implicitly used by the type
system to coerce a value of the input type to a value of the
output type. For instance, the coercion declaration for [AId]
allows us to use plain strings when an [aexp] is expected; the
string will implicitly be wrapped with [AId]. *)
(** The notations below are declared in specific _notation scopes_, in
order to avoid conflicts with other interpretations of the same
symbols. Again, it is not necessary to understand the details,
but it is important to recognize that we are defining _new_
interpretations for some familiar operators like [+], [-], [*],
[=], [<=], etc. *)
Coercion AId : string >-> aexp.
Coercion ANum : nat >-> aexp.
Definition bool_to_bexp (b : bool) : bexp :=
if b then BTrue else BFalse.
Coercion bool_to_bexp : bool >-> bexp.
Bind Scope imp_scope with aexp.
Bind Scope imp_scope with bexp.
Delimit Scope imp_scope with imp.
Notation "x + y" := (APlus x y) (at level 50, left associativity) : imp_scope.
Notation "x - y" := (AMinus x y) (at level 50, left associativity) : imp_scope.
Notation "x * y" := (AMult x y) (at level 40, left associativity) : imp_scope.
Notation "x <= y" := (BLe x y) (at level 70, no associativity) : imp_scope.
Notation "x = y" := (BEq x y) (at level 70, no associativity) : imp_scope.
Notation "x && y" := (BAnd x y) (at level 40, left associativity) : imp_scope.
Notation "'~' b" := (BNot b) (at level 75, right associativity) : imp_scope.
(** We can now write [3 + (X * 2)] instead of [APlus 3 (AMult X 2)],
and [true && ~(X <= 4)] instead of [BAnd true (BNot (BLe X 4))]. *)
Definition example_aexp := (3 + (X * 2))%imp : aexp.
Definition example_bexp := (true && ~(X <= 4))%imp : bexp.
(** One downside of these coercions is that they can make it a little
harder for humans to calculate the types of expressions. If you
get confused, try doing [Set Printing Coercions] to see exactly
what is going on. *)
Set Printing Coercions.
Print example_bexp.
(* ===> example_bexp = bool_to_bexp true && ~ (AId X <= ANum 4) *)
Unset Printing Coercions.
(* ================================================================= *)
(** ** Evaluation *)
(** The arith and boolean evaluators are extended to handle
variables in the obvious way, taking a state as an extra
argument: *)
Fixpoint aeval (st : state) (a : aexp) : nat :=
match a with
| ANum n => n
| AId x => st x (* <--- NEW *)
| APlus a1 a2 => (aeval st a1) + (aeval st a2)
| AMinus a1 a2 => (aeval st a1) - (aeval st a2)
| AMult a1 a2 => (aeval st a1) * (aeval st a2)
end.
Fixpoint beval (st : state) (b : bexp) : bool :=
match b with
| BTrue => true
| BFalse => false
| BEq a1 a2 => (aeval st a1) =? (aeval st a2)
| BLe a1 a2 => (aeval st a1) <=? (aeval st a2)
| BNot b1 => negb (beval st b1)
| BAnd b1 b2 => andb (beval st b1) (beval st b2)
end.
(** We specialize our notation for total maps to the specific case of
states, i.e. using [(_ !-> 0)] as empty state. *)
Definition empty_st := (_ !-> 0).
(** Now we can add a notation for a "singleton state" with just one
variable bound to a value. *)
Notation "a '!->' x" := (t_update empty_st a x) (at level 100).
Example aexp1 :
aeval (X !-> 5) (3 + (X * 2))%imp
= 13.
Proof. reflexivity. Qed.
Example bexp1 :
beval (X !-> 5) (true && ~(X <= 4))%imp
= true.
Proof. reflexivity. Qed.
(* ################################################################# *)
(** * Commands *)
(** Now we are ready define the syntax and behavior of Imp
_commands_ (sometimes called _statements_). *)
(* ================================================================= *)
(** ** Syntax *)
(** Informally, commands [c] are described by the following BNF
grammar.
c ::= SKIP | x ::= a | c ;; c | TEST b THEN c ELSE c FI
| WHILE b DO c END
(We choose this slightly awkward concrete syntax for the
sake of being able to define Imp syntax using Coq's notation
mechanism. In particular, we use [TEST] to avoid conflicting with
the [if] and [IF] notations from the standard library.)
For example, here's factorial in Imp:
Z ::= X;;
Y ::= 1;;
WHILE ~(Z = 0) DO
Y ::= Y * Z;;
Z ::= Z - 1
END
When this command terminates, the variable [Y] will contain the
factorial of the initial value of [X]. *)
(** Here is the formal definition of the abstract syntax of
commands: *)
Inductive com : Type :=
| CSkip
| CAss (x : string) (a : aexp)
| CSeq (c1 c2 : com)
| CIf (b : bexp) (c1 c2 : com)
| CWhile (b : bexp) (c : com).
(** As for expressions, we can use a few [Notation] declarations to
make reading and writing Imp programs more convenient. *)
Bind Scope imp_scope with com.
Notation "'SKIP'" :=
CSkip : imp_scope.
Notation "x '::=' a" :=
(CAss x a) (at level 60) : imp_scope.
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity) : imp_scope.
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity) : imp_scope.
Notation "'TEST' c1 'THEN' c2 'ELSE' c3 'FI'" :=
(CIf c1 c2 c3) (at level 80, right associativity) : imp_scope.
(** For example, here is the factorial function again, written as a
formal definition to Coq: *)
Definition fact_in_coq : com :=
(Z ::= X;;
Y ::= 1;;
WHILE ~(Z = 0) DO
Y ::= Y * Z;;
Z ::= Z - 1
END)%imp.
(* ================================================================= *)
(** ** Desugaring notations *)
(** Coq offers a rich set of features to manage the increasing
complexity of the objects we work with, such as coercions
and notations. However, their heavy usage can make for quite
overwhelming syntax. It is often instructive to "turn off"
those features to get a more elementary picture of things,
using the following commands:
- [Unset Printing Notations] (undo with [Set Printing Notations])
- [Set Printing Coercions] (undo with [Unset Printing Coercions])
- [Set Printing All] (undo with [Unset Printing All])
These commands can also be used in the middle of a proof,
to elaborate the current goal and context.
*)
Unset Printing Notations.
Print fact_in_coq.
(* ===>
fact_in_coq =
CSeq (CAss Z X)
(CSeq (CAss Y (S O))
(CWhile (BNot (BEq Z O))
(CSeq (CAss Y (AMult Y Z))
(CAss Z (AMinus Z (S O))))))
: com *)
Set Printing Notations.
Set Printing Coercions.
Print fact_in_coq.
(* ===>
fact_in_coq =
(Z ::= AId X;;
Y ::= ANum 1;;
WHILE ~ (AId Z = ANum 0) DO
Y ::= AId Y * AId Z;;
Z ::= AId Z - ANum 1
END)%imp
: com *)
Unset Printing Coercions.
(* ================================================================= *)
(** ** The [Locate] command *)
(* ----------------------------------------------------------------- *)
(** *** Finding notations *)
(** When faced with unknown notation, use [Locate] with a _string_
containing one of its symbols to see its possible
interpretations. *)
Locate "&&".
(* ===>
Notation "x && y" := andb x y : bool_scope (default interpretation) *)
Locate ";;".
(* ===>
Notation "c1 ;; c2" := CSeq c1 c2 : imp_scope (default interpretation) *)
Locate "WHILE".
(* ===>
Notation "'WHILE' b 'DO' c 'END'" := CWhile b c : imp_scope
(default interpretation) *)
(* ----------------------------------------------------------------- *)
(** *** Finding identifiers *)
(** When used with an identifier, the command [Locate] prints
the full path to every value in scope with the same name.
This is useful to troubleshoot problems due to variable
shadowing. *)
Locate aexp.
(* ===>
Inductive Top.aexp
Inductive Top.AExp.aexp
(shorter name to refer to it in current context is AExp.aexp)
Inductive Top.aevalR_division.aexp
(shorter name to refer to it in current context is aevalR_division.aexp)
Inductive Top.aevalR_extended.aexp
(shorter name to refer to it in current context is aevalR_extended.aexp)
*)
(* ================================================================= *)
(** ** More Examples *)
(** Assignment: *)
Definition plus2 : com :=
X ::= X + 2.
Definition XtimesYinZ : com :=
Z ::= X * Y.
Definition subtract_slowly_body : com :=
Z ::= Z - 1 ;;
X ::= X - 1.
(* ----------------------------------------------------------------- *)
(** *** Loops *)
Definition subtract_slowly : com :=
(WHILE ~(X = 0) DO
subtract_slowly_body
END)%imp.
Definition subtract_3_from_5_slowly : com :=
X ::= 3 ;;
Z ::= 5 ;;
subtract_slowly.
(* ----------------------------------------------------------------- *)
(** *** An infinite loop: *)
Definition loop : com :=
WHILE true DO
SKIP
END.
(* ################################################################# *)
(** * Evaluating Commands *)
(** Next we need to define what it means to evaluate an Imp command.
The fact that [WHILE] loops don't necessarily terminate makes
defining an evaluation function tricky... *)
(* ================================================================= *)
(** ** Evaluation as a Function (Failed Attempt) *)
(** Here's an attempt at defining an evaluation function for commands,
omitting the [WHILE] case. *)
(** The following declaration is needed to be able to use the
notations in match patterns. *)
Open Scope imp_scope.
Fixpoint ceval_fun_no_while (st : state) (c : com)
: state :=
match c with
| SKIP =>
st
| x ::= a1 =>
(x !-> (aeval st a1) ; st)
| c1 ;; c2 =>
let st' := ceval_fun_no_while st c1 in
ceval_fun_no_while st' c2
| TEST b THEN c1 ELSE c2 FI =>
if (beval st b)
then ceval_fun_no_while st c1
else ceval_fun_no_while st c2
| WHILE b DO c END =>
st (* bogus *)
end.
Close Scope imp_scope.
(** In a traditional functional programming language like OCaml or
Haskell we could add the [WHILE] case as follows:
Fixpoint ceval_fun (st : state) (c : com) : state :=
match c with
...
| WHILE b DO c END =>
if (beval st b)
then ceval_fun st (c ;; WHILE b DO c END)
else st
end.
Coq doesn't accept such a definition ("Error: Cannot guess
decreasing argument of fix") because the function we want to
define is not guaranteed to terminate. Indeed, it _doesn't_ always
terminate: for example, the full version of the [ceval_fun]
function applied to the [loop] program above would never
terminate. Since Coq is not just a functional programming
language but also a consistent logic, any potentially
non-terminating function needs to be rejected. Here is
an (invalid!) program showing what would go wrong if Coq
allowed non-terminating recursive functions:
Fixpoint loop_false (n : nat) : False := loop_false n.
That is, propositions like [False] would become provable
([loop_false 0] would be a proof of [False]), which
would be a disaster for Coq's logical consistency.
Thus, because it doesn't terminate on all inputs,
of [ceval_fun] cannot be written in Coq -- at least not without
additional tricks and workarounds (see chapter [ImpCEvalFun]
if you're curious about what those might be). *)
(* ================================================================= *)
(** ** Evaluation as a Relation *)
(** Here's a better way: define [ceval] as a _relation_ rather than a
_function_ -- i.e., define it in [Prop] instead of [Type], as we
did for [aevalR] above. *)
(** This is an important change. Besides freeing us from awkward
workarounds, it gives us a lot more flexibility in the definition.
For example, if we add nondeterministic features like [any] to the
language, we want the definition of evaluation to be
nondeterministic -- i.e., not only will it not be total, it will
not even be a function! *)
(** We'll use the notation [st =[ c ]=> st'] for the [ceval] relation:
[st =[ c ]=> st'] means that executing program [c] in a starting
state [st] results in an ending state [st']. This can be
pronounced "[c] takes state [st] to [st']". *)
(* ----------------------------------------------------------------- *)
(** *** Operational Semantics *)
(** Here is an informal definition of evaluation, presented as inference
rules for readability:
----------------- (E_Skip)
st =[ SKIP ]=> st
aeval st a1 = n
-------------------------------- (E_Ass)
st =[ x := a1 ]=> (x !-> n ; st)
st =[ c1 ]=> st'
st' =[ c2 ]=> st''
--------------------- (E_Seq)
st =[ c1;;c2 ]=> st''
beval st b1 = true
st =[ c1 ]=> st'
--------------------------------------- (E_IfTrue)
st =[ TEST b1 THEN c1 ELSE c2 FI ]=> st'
beval st b1 = false
st =[ c2 ]=> st'
--------------------------------------- (E_IfFalse)
st =[ TEST b1 THEN c1 ELSE c2 FI ]=> st'
beval st b = false
----------------------------- (E_WhileFalse)
st =[ WHILE b DO c END ]=> st
beval st b = true
st =[ c ]=> st'
st' =[ WHILE b DO c END ]=> st''
-------------------------------- (E_WhileTrue)
st =[ WHILE b DO c END ]=> st''
*)
(** Here is the formal definition. Make sure you understand
how it corresponds to the inference rules. *)
Reserved Notation "st '=[' c ']=>' st'"
(at level 40).
Inductive ceval : com -> state -> state -> Prop :=
| E_Skip : forall st,
st =[ SKIP ]=> st
| E_Ass : forall st a1 n x,
aeval st a1 = n ->
st =[ x ::= a1 ]=> (x !-> n ; st)
| E_Seq : forall c1 c2 st st' st'',
st =[ c1 ]=> st' ->
st' =[ c2 ]=> st'' ->
st =[ c1 ;; c2 ]=> st''
| E_IfTrue : forall st st' b c1 c2,
beval st b = true ->
st =[ c1 ]=> st' ->
st =[ TEST b THEN c1 ELSE c2 FI ]=> st'
| E_IfFalse : forall st st' b c1 c2,
beval st b = false ->
st =[ c2 ]=> st' ->
st =[ TEST b THEN c1 ELSE c2 FI ]=> st'
| E_WhileFalse : forall b st c,
beval st b = false ->
st =[ WHILE b DO c END ]=> st
| E_WhileTrue : forall st st' st'' b c,
beval st b = true ->
st =[ c ]=> st' ->
st' =[ WHILE b DO c END ]=> st'' ->
st =[ WHILE b DO c END ]=> st''
where "st =[ c ]=> st'" := (ceval c st st').
(** The cost of defining evaluation as a relation instead of a
function is that we now need to construct _proofs_ that some
program evaluates to some result state, rather than just letting
Coq's computation mechanism do it for us. *)
Example ceval_example1:
empty_st =[
X ::= 2;;
TEST X <= 1
THEN Y ::= 3
ELSE Z ::= 4
FI
]=> (Z !-> 4 ; X !-> 2).
Proof.
(* We must supply the intermediate state *)
apply E_Seq with (X !-> 2).
- (* assignment command *)
apply E_Ass. reflexivity.
- (* if command *)
apply E_IfFalse.
reflexivity.
apply E_Ass. reflexivity.
Qed.
(** **** Exercise: 2 stars, standard (ceval_example2) *)
Example ceval_example2:
empty_st =[
X ::= 0;; Y ::= 1;; Z ::= 2
]=> (Z !-> 2 ; Y !-> 1 ; X !-> 0).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, standard, optional (pup_to_n)
Write an Imp program that sums the numbers from [1] to
[X] (inclusive: [1 + 2 + ... + X]) in the variable [Y].
Prove that this program executes as intended for [X] = [2]
(this is trickier than you might expect). *)
Definition pup_to_n : com
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
Theorem pup_to_2_ceval :
(X !-> 2) =[
pup_to_n
]=> (X !-> 0 ; Y !-> 3 ; X !-> 1 ; Y !-> 2 ; Y !-> 0 ; X !-> 2).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ================================================================= *)
(** ** Determinism of Evaluation *)
(** Changing from a computational to a relational definition of
evaluation is a good move because it frees us from the artificial
requirement that evaluation should be a total function. But it
also raises a question: Is the second definition of evaluation
really a partial function? Or is it possible that, beginning from
the same state [st], we could evaluate some command [c] in
different ways to reach two different output states [st'] and
[st'']?
In fact, this cannot happen: [ceval] _is_ a partial function: *)
Theorem ceval_deterministic: forall c st st1 st2,
st =[ c ]=> st1 ->
st =[ c ]=> st2 ->
st1 = st2.
Proof.
intros c st st1 st2 E1 E2.
generalize dependent st2.
induction E1;
intros st2 E2; inversion E2; subst.
- (* E_Skip *) reflexivity.
- (* E_Ass *) reflexivity.
- (* E_Seq *)
assert (st' = st'0) as EQ1.
{ (* Proof of assertion *) apply IHE1_1; assumption. }
subst st'0.
apply IHE1_2. assumption.
- (* E_IfTrue, b1 evaluates to true *)
apply IHE1. assumption.
- (* E_IfTrue, b1 evaluates to false (contradiction) *)
rewrite H in H5. discriminate H5.
- (* E_IfFalse, b1 evaluates to true (contradiction) *)
rewrite H in H5. discriminate H5.
- (* E_IfFalse, b1 evaluates to false *)
apply IHE1. assumption.
- (* E_WhileFalse, b1 evaluates to false *)
reflexivity.
- (* E_WhileFalse, b1 evaluates to true (contradiction) *)
rewrite H in H2. discriminate H2.
- (* E_WhileTrue, b1 evaluates to false (contradiction) *)
rewrite H in H4. discriminate H4.
- (* E_WhileTrue, b1 evaluates to true *)
assert (st' = st'0) as EQ1.
{ (* Proof of assertion *) apply IHE1_1; assumption. }
subst st'0.
apply IHE1_2. assumption. Qed.
(* ################################################################# *)
(** * Reasoning About Imp Programs *)
(** We'll get deeper into more systematic and powerful techniques for
reasoning about Imp programs in _Programming Language
Foundations_, but we can get some distance just working with the
bare definitions. This section explores some examples. *)
Theorem plus2_spec : forall st n st',
st X = n ->
st =[ plus2 ]=> st' ->
st' X = n + 2.
Proof.
intros st n st' HX Heval.
(** Inverting [Heval] essentially forces Coq to expand one step of
the [ceval] computation -- in this case revealing that [st']
must be [st] extended with the new value of [X], since [plus2]
is an assignment. *)
inversion Heval. subst. clear Heval. simpl.
apply t_update_eq. Qed.
(** **** Exercise: 3 stars, standard, recommended (XtimesYinZ_spec)
State and prove a specification of [XtimesYinZ]. *)
(* FILL IN HERE *)
(* Do not modify the following line: *)
Definition manual_grade_for_XtimesYinZ_spec : option (nat*string) := None.
(** [] *)
(** **** Exercise: 3 stars, standard, recommended (loop_never_stops) *)
Theorem loop_never_stops : forall st st',
~(st =[ loop ]=> st').
Proof.
intros st st' contra. unfold loop in contra.
remember (WHILE true DO SKIP END)%imp as loopdef
eqn:Heqloopdef.
(** Proceed by induction on the assumed derivation showing that
[loopdef] terminates. Most of the cases are immediately
contradictory (and so can be solved in one step with
[discriminate]). *)
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, standard (no_whiles_eqv)
Consider the following function: *)
Open Scope imp_scope.
Fixpoint no_whiles (c : com) : bool :=
match c with
| SKIP =>
true
| _ ::= _ =>
true
| c1 ;; c2 =>
andb (no_whiles c1) (no_whiles c2)
| TEST _ THEN ct ELSE cf FI =>
andb (no_whiles ct) (no_whiles cf)
| WHILE _ DO _ END =>
false
end.
Close Scope imp_scope.
(** This predicate yields [true] just on programs that have no while
loops. Using [Inductive], write a property [no_whilesR] such that
[no_whilesR c] is provable exactly when [c] is a program with no
while loops. Then prove its equivalence with [no_whiles]. *)
Inductive no_whilesR: com -> Prop :=
(* FILL IN HERE *)
.
Theorem no_whiles_eqv:
forall c, no_whiles c = true <-> no_whilesR c.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 4 stars, standard (no_whiles_terminating)
Imp programs that don't involve while loops always terminate.
State and prove a theorem [no_whiles_terminating] that says this.
Use either [no_whiles] or [no_whilesR], as you prefer. *)
(* FILL IN HERE *)
(* Do not modify the following line: *)
Definition manual_grade_for_no_whiles_terminating : option (nat*string) := None.
(** [] *)
(* ################################################################# *)
(** * Additional Exercises *)
(** **** Exercise: 3 stars, standard (stack_compiler)
Old HP Calculators, programming languages like Forth and Postscript,
and abstract machines like the Java Virtual Machine all evaluate
arithmetic expressions using a _stack_. For instance, the expression
(2*3)+(3*(4-2))
would be written as
2 3 * 3 4 2 - * +
and evaluated like this (where we show the program being evaluated
on the right and the contents of the stack on the left):
[ ] | 2 3 * 3 4 2 - * +
[2] | 3 * 3 4 2 - * +
[3, 2] | * 3 4 2 - * +
[6] | 3 4 2 - * +
[3, 6] | 4 2 - * +
[4, 3, 6] | 2 - * +
[2, 4, 3, 6] | - * +
[2, 3, 6] | * +
[6, 6] | +
[12] |
The goal of this exercise is to write a small compiler that
translates [aexp]s into stack machine instructions.
The instruction set for our stack language will consist of the
following instructions:
- [SPush n]: Push the number [n] on the stack.
- [SLoad x]: Load the identifier [x] from the store and push it
on the stack
- [SPlus]: Pop the two top numbers from the stack, add them, and
push the result onto the stack.
- [SMinus]: Similar, but subtract.
- [SMult]: Similar, but multiply. *)
Inductive sinstr : Type :=
| SPush (n : nat)
| SLoad (x : string)
| SPlus
| SMinus
| SMult.
(** Write a function to evaluate programs in the stack language. It
should take as input a state, a stack represented as a list of
numbers (top stack item is the head of the list), and a program
represented as a list of instructions, and it should return the
stack after executing the program. Test your function on the
examples below.
Note that the specification leaves unspecified what to do when
encountering an [SPlus], [SMinus], or [SMult] instruction if the
stack contains less than two elements. In a sense, it is
immaterial what we do, since our compiler will never emit such a
malformed program. *)
Fixpoint s_execute (st : state) (stack : list nat)
(prog : list sinstr)
: list nat
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
Example s_execute1 :
s_execute empty_st []
[SPush 5; SPush 3; SPush 1; SMinus]
= [2; 5].
(* FILL IN HERE *) Admitted.
Example s_execute2 :
s_execute (X !-> 3) [3;4]
[SPush 4; SLoad X; SMult; SPlus]
= [15; 4].
(* FILL IN HERE *) Admitted.
(** Next, write a function that compiles an [aexp] into a stack
machine program. The effect of running the program should be the
same as pushing the value of the expression on the stack. *)
Fixpoint s_compile (e : aexp) : list sinstr
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
(** After you've defined [s_compile], prove the following to test
that it works. *)
Example s_compile1 :
s_compile (X - (2 * Y))%imp
= [SLoad X; SPush 2; SLoad Y; SMult; SMinus].
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 4 stars, advanced (stack_compiler_correct)
Now we'll prove the correctness of the compiler implemented in the
previous exercise. Remember that the specification left
unspecified what to do when encountering an [SPlus], [SMinus], or
[SMult] instruction if the stack contains less than two
elements. (In order to make your correctness proof easier you
might find it helpful to go back and change your implementation!)
Prove the following theorem. You will need to start by stating a
more general lemma to get a usable induction hypothesis; the main
theorem will then be a simple corollary of this lemma. *)
Theorem s_compile_correct : forall (st : state) (e : aexp),
s_execute st [] (s_compile e) = [ aeval st e ].
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, standard, optional (short_circuit)
Most modern programming languages use a "short-circuit" evaluation
rule for boolean [and]: to evaluate [BAnd b1 b2], first evaluate
[b1]. If it evaluates to [false], then the entire [BAnd]
expression evaluates to [false] immediately, without evaluating
[b2]. Otherwise, [b2] is evaluated to determine the result of the
[BAnd] expression.
Write an alternate version of [beval] that performs short-circuit
evaluation of [BAnd] in this manner, and prove that it is
equivalent to [beval]. (N.b. This is only true because expression
evaluation in Imp is rather simple. In a bigger language where
evaluating an expression might diverge, the short-circuiting [BAnd]
would _not_ be equivalent to the original, since it would make more
programs terminate.) *)
(* FILL IN HERE
[] *)
Module BreakImp.
(** **** Exercise: 4 stars, advanced (break_imp)
Imperative languages like C and Java often include a [break] or
similar statement for interrupting the execution of loops. In this
exercise we consider how to add [break] to Imp. First, we need to
enrich the language of commands with an additional case. *)
Inductive com : Type :=
| CSkip
| CBreak (* <--- NEW *)
| CAss (x : string) (a : aexp)
| CSeq (c1 c2 : com)
| CIf (b : bexp) (c1 c2 : com)
| CWhile (b : bexp) (c : com).
Notation "'SKIP'" :=
CSkip.
Notation "'BREAK'" :=
CBreak.
Notation "x '::=' a" :=
(CAss x a) (at level 60).
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'TEST' c1 'THEN' c2 'ELSE' c3 'FI'" :=
(CIf c1 c2 c3) (at level 80, right associativity).
(** Next, we need to define the behavior of [BREAK]. Informally,
whenever [BREAK] is executed in a sequence of commands, it stops
the execution of that sequence and signals that the innermost
enclosing loop should terminate. (If there aren't any
enclosing loops, then the whole program simply terminates.) The
final state should be the same as the one in which the [BREAK]
statement was executed.
One important point is what to do when there are multiple loops
enclosing a given [BREAK]. In those cases, [BREAK] should only
terminate the _innermost_ loop. Thus, after executing the
following...
X ::= 0;;
Y ::= 1;;
WHILE ~(0 = Y) DO
WHILE true DO
BREAK
END;;
X ::= 1;;
Y ::= Y - 1
END
... the value of [X] should be [1], and not [0].
One way of expressing this behavior is to add another parameter to
the evaluation relation that specifies whether evaluation of a
command executes a [BREAK] statement: *)
Inductive result : Type :=
| SContinue
| SBreak.
Reserved Notation "st '=[' c ']=>' st' '/' s"
(at level 40, st' at next level).
(** Intuitively, [st =[ c ]=> st' / s] means that, if [c] is started in
state [st], then it terminates in state [st'] and either signals
that the innermost surrounding loop (or the whole program) should
exit immediately ([s = SBreak]) or that execution should continue
normally ([s = SContinue]).
The definition of the "[st =[ c ]=> st' / s]" relation is very
similar to the one we gave above for the regular evaluation
relation ([st =[ c ]=> st']) -- we just need to handle the
termination signals appropriately:
- If the command is [SKIP], then the state doesn't change and
execution of any enclosing loop can continue normally.
- If the command is [BREAK], the state stays unchanged but we
signal a [SBreak].
- If the command is an assignment, then we update the binding for
that variable in the state accordingly and signal that execution
can continue normally.
- If the command is of the form [TEST b THEN c1 ELSE c2 FI], then
the state is updated as in the original semantics of Imp, except
that we also propagate the signal from the execution of
whichever branch was taken.
- If the command is a sequence [c1 ;; c2], we first execute
[c1]. If this yields a [SBreak], we skip the execution of [c2]
and propagate the [SBreak] signal to the surrounding context;
the resulting state is the same as the one obtained by
executing [c1] alone. Otherwise, we execute [c2] on the state
obtained after executing [c1], and propagate the signal
generated there.
- Finally, for a loop of the form [WHILE b DO c END], the
semantics is almost the same as before. The only difference is
that, when [b] evaluates to true, we execute [c] and check the
signal that it raises. If that signal is [SContinue], then the
execution proceeds as in the original semantics. Otherwise, we
stop the execution of the loop, and the resulting state is the
same as the one resulting from the execution of the current
iteration. In either case, since [BREAK] only terminates the
innermost loop, [WHILE] signals [SContinue]. *)
(** Based on the above description, complete the definition of the
[ceval] relation. *)
Inductive ceval : com -> state -> result -> state -> Prop :=
| E_Skip : forall st,
st =[ CSkip ]=> st / SContinue
(* FILL IN HERE *)
where "st '=[' c ']=>' st' '/' s" := (ceval c st s st').
(** Now prove the following properties of your definition of [ceval]: *)
Theorem break_ignore : forall c st st' s,
st =[ BREAK;; c ]=> st' / s ->
st = st'.
Proof.
(* FILL IN HERE *) Admitted.
Theorem while_continue : forall b c st st' s,
st =[ WHILE b DO c END ]=> st' / s ->
s = SContinue.
Proof.
(* FILL IN HERE *) Admitted.
Theorem while_stops_on_break : forall b c st st',
beval st b = true ->
st =[ c ]=> st' / SBreak ->
st =[ WHILE b DO c END ]=> st' / SContinue.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, advanced, optional (while_break_true) *)
Theorem while_break_true : forall b c st st',
st =[ WHILE b DO c END ]=> st' / SContinue ->
beval st' b = true ->
exists st'', st'' =[ c ]=> st' / SBreak.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 4 stars, advanced, optional (ceval_deterministic) *)
Theorem ceval_deterministic: forall (c:com) st st1 st2 s1 s2,
st =[ c ]=> st1 / s1 ->
st =[ c ]=> st2 / s2 ->
st1 = st2 /\ s1 = s2.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
End BreakImp.
(** **** Exercise: 4 stars, standard, optional (add_for_loop)
Add C-style [for] loops to the language of commands, update the
[ceval] definition to define the semantics of [for] loops, and add
cases for [for] loops as needed so that all the proofs in this
file are accepted by Coq.
A [for] loop should be parameterized by (a) a statement executed
initially, (b) a test that is run on each iteration of the loop to
determine whether the loop should continue, (c) a statement
executed at the end of each loop iteration, and (d) a statement
that makes up the body of the loop. (You don't need to worry
about making up a concrete Notation for [for] loops, but feel free
to play with this too if you like.) *)
(* FILL IN HERE
[] *)
(* Fri Feb 8 06:31:30 EST 2019 *)
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// DUC block
module duc(input clock,
input reset,
input enable,
input [3:0] rate1,
input [3:0] rate2,
output strobe,
input [31:0] freq,
input [15:0] i_in,
input [15:0] q_in,
output [15:0] i_out,
output [15:0] q_out
);
parameter bw = 16;
parameter zw = 16;
wire [15:0] i_interp_out, q_interp_out;
wire [31:0] phase;
wire strobe1, strobe2;
reg [3:0] strobe_ctr1,strobe_ctr2;
always @(posedge clock)
if(reset | ~enable)
strobe_ctr2 <= #1 4'd0;
else if(strobe2)
strobe_ctr2 <= #1 4'd0;
else
strobe_ctr2 <= #1 strobe_ctr2 + 4'd1;
always @(posedge clock)
if(reset | ~enable)
strobe_ctr1 <= #1 4'd0;
else if(strobe1)
strobe_ctr1 <= #1 4'd0;
else if(strobe2)
strobe_ctr1 <= #1 strobe_ctr1 + 4'd1;
assign strobe2 = enable & ( strobe_ctr2 == rate2 );
assign strobe1 = strobe2 & ( strobe_ctr1 == rate1 );
assign strobe = strobe1;
function [2:0] log_ceil;
input [3:0] val;
log_ceil = val[3] ? 3'd4 : val[2] ? 3'd3 : val[1] ? 3'd2 : 3'd1;
endfunction
wire [2:0] shift1 = log_ceil(rate1);
wire [2:0] shift2 = log_ceil(rate2);
cordic #(.bitwidth(bw),.zwidth(zw),.stages(16))
cordic(.clock(clock), .reset(reset), .enable(enable),
.xi(i_interp_out), .yi(q_interp_out), .zi(phase[31:32-zw]),
.xo(i_out), .yo(q_out), .zo() );
cic_interp_2stage #(.bw(bw),.N(4))
interp_i(.clock(clock),.reset(reset),.enable(enable),
.strobe1(strobe1),.strobe2(strobe2),.strobe3(1'b1),.shift1(shift1),.shift2(shift2),
.signal_in(i_in),.signal_out(i_interp_out));
cic_interp_2stage #(.bw(bw),.N(4))
interp_q(.clock(clock),.reset(reset),.enable(enable),
.strobe1(strobe1),.strobe2(strobe2),.strobe3(1'b1),.shift1(shift1),.shift2(shift2),
.signal_in(q_in),.signal_out(q_interp_out));
phase_acc #(.resolution(32))
nco (.clk(clock),.reset(reset),.enable(enable),
.freq(freq),.phase(phase));
endmodule
|
// (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
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// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
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// (individually and collectively, "Critical
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// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
////////////////////////////////////////////////////////////
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// axis_infrastructure_v1_1_0_util_aclken_converter
//
//--------------------------------------------------------------------------
`ifndef AXIS_INFRASTRUCTURE_V1_0_UTIL_ACLKEN_CONVERTER_V
`define AXIS_INFRASTRUCTURE_V1_0_UTIL_ACLKEN_CONVERTER_V
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axis_infrastructure_v1_1_0_util_aclken_converter # (
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_PAYLOAD_WIDTH = 32,
parameter integer C_S_ACLKEN_CAN_TOGGLE = 1,
parameter integer C_M_ACLKEN_CAN_TOGGLE = 1
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// Slave side
input wire ACLK,
input wire ARESETN,
input wire S_ACLKEN,
input wire [C_PAYLOAD_WIDTH-1:0] S_PAYLOAD,
input wire S_VALID,
output wire S_READY,
// Master side
input wire M_ACLKEN,
output wire [C_PAYLOAD_WIDTH-1:0] M_PAYLOAD,
output wire M_VALID,
input wire M_READY
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
// State machine states
localparam SM_NOT_READY = 3'b000;
localparam SM_EMPTY = 3'b001;
localparam SM_R0_NOT_READY = 3'b010;
localparam SM_R0 = 3'b011;
localparam SM_R1 = 3'b100;
localparam SM_FULL = 3'b110;
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
wire s_aclken_i;
wire m_aclken_i;
reg areset;
reg [2:0] state;
// r0 is the output register
reg [C_PAYLOAD_WIDTH-1:0] r0;
wire load_r0;
wire load_r0_from_r1;
// r1 is the overflow register
reg [C_PAYLOAD_WIDTH-1:0] r1;
wire load_r1;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
assign s_aclken_i = C_S_ACLKEN_CAN_TOGGLE ? S_ACLKEN : 1'b1;
assign m_aclken_i = C_M_ACLKEN_CAN_TOGGLE ? M_ACLKEN : 1'b1;
always @(posedge ACLK) begin
areset <= ~ARESETN;
end
// Valid/Ready outputs encoded into state machine.
assign S_READY = state[0];
assign M_VALID = state[1];
// State machine: Controls outputs and hold register state info
always @(posedge ACLK) begin
if (areset) begin
state <= SM_NOT_READY;
end
else begin
case (state)
// De-assert s_ready, de-assert m_valid, R0 unoccupied, R1 unoccupied
SM_NOT_READY: begin
if (s_aclken_i) begin
state <= SM_EMPTY;
end
else begin
state <= state;
end
end
// Assert s_ready, de-assert m_valid, R0 unoccupied, R1 unoccupied
SM_EMPTY: begin
if (s_aclken_i & S_VALID & m_aclken_i) begin
state <= SM_R0;
end
else if (s_aclken_i & S_VALID & ~m_aclken_i) begin
state <= SM_R1;
end
else begin
state <= state;
end
end
// Assert s_ready, Assert m_valid, R0 occupied, R1 unoccupied
SM_R0: begin
if ((m_aclken_i & M_READY) & ~(s_aclken_i & S_VALID)) begin
state <= SM_EMPTY;
end
else if (~(m_aclken_i & M_READY) & (s_aclken_i & S_VALID)) begin
state <= SM_FULL;
end
else begin
state <= state;
end
end
// De-assert s_ready, Assert m_valid, R0 occupied, R1 unoccupied
SM_R0_NOT_READY: begin
if (s_aclken_i & m_aclken_i & M_READY) begin
state <= SM_EMPTY;
end
else if (~s_aclken_i & m_aclken_i & M_READY) begin
state <= SM_NOT_READY;
end
else if (s_aclken_i) begin
state <= SM_R0;
end
else begin
state <= state;
end
end
// De-assert s_ready, De-assert m_valid, R0 unoccupied, R1 occupied
SM_R1: begin
if (~s_aclken_i & m_aclken_i) begin
state <= SM_R0_NOT_READY;
end
else if (s_aclken_i & m_aclken_i) begin
state <= SM_R0;
end
else begin
state <= state;
end
end
// De-assert s_ready, De-assert m_valid, R0 occupied, R1 occupied
SM_FULL: begin
if (~s_aclken_i & m_aclken_i & M_READY) begin
state <= SM_R0_NOT_READY;
end
else if (s_aclken_i & m_aclken_i & M_READY) begin
state <= SM_R0;
end
else begin
state <= state;
end
end
default: begin
state <= SM_NOT_READY;
end
endcase
end
end
assign M_PAYLOAD = r0;
always @(posedge ACLK) begin
if (m_aclken_i) begin
r0 <= ~load_r0 ? r0 :
load_r0_from_r1 ? r1 :
S_PAYLOAD ;
end
end
assign load_r0 = (state == SM_EMPTY)
| (state == SM_R1)
| ((state == SM_R0) & M_READY)
| ((state == SM_FULL) & M_READY);
assign load_r0_from_r1 = (state == SM_R1) | (state == SM_FULL);
always @(posedge ACLK) begin
r1 <= ~load_r1 ? r1 : S_PAYLOAD;
end
assign load_r1 = (state == SM_EMPTY) | (state == SM_R0);
endmodule // axis_infrastructure_v1_1_0_util_aclken_converter
`default_nettype wire
`endif
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O21AI_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__O21AI_BEHAVIORAL_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__o21ai (
Y ,
A1,
A2,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y, B1, or0_out );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O21AI_BEHAVIORAL_V |
//i2s_mem_controllerv
/*
Distributed under the MIT license.
Copyright (c) 2011 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
`include "project_defines.v"
`timescale 1 ns/1 ps
module i2s_mem_controller (
input rst,
input clk,
//control
input enable,
input post_fifo_wave_en,
//clock divider
input i2s_clock,
//memory interface
output [23:0] wfifo_size,
output [1:0] wfifo_ready,
input [1:0] wfifo_activate,
input wfifo_strobe,
input [31:0] wfifo_data,
//i2s writer
input audio_data_request,
output reg audio_data_ack,
output reg [23:0] audio_data,
output reg audio_lr_bit
);
//registers/wires
//input side
wire starved;
//output side
reg read_strobe = 0;
wire read_ready;
reg read_activate = 0;
wire [23:0] read_size;
wire [31:0] read_data;
//i2s writer interface
reg [23:0] read_count = 0;
reg [3:0] state = 0;
//waveform
reg [31:0] write_count = 0;
reg [7:0] test_pre_pos = 0;
wire [7:0] test_pre_wavelength;
wire [15:0] test_pre_value;
reg [31:0] test_pre_data;
reg test_pre_write_strobe;
wire [31:0] fifo_data;
wire fifo_write_strobe;
reg [7:0] test_pos = 0;
wire [7:0] test_wavelength;
wire [15:0] test_value;
//parameters
parameter READ_STROBE = 4'h0;
parameter DELAY = 4'h1;
parameter READ = 4'h2;
//generate a Ping Pong FIFO to cross the clock domain
ppfifo #(
.DATA_WIDTH(32),
`ifndef SIMULATION
.ADDRESS_WIDTH(12)
//.ADDRESS_WIDTH(4)
`else
.ADDRESS_WIDTH(2)
`endif
)ping_pong (
.reset (rst || !enable ),
//write
.write_clock (clk ),
.write_ready (wfifo_ready ),
.write_activate (wfifo_activate ),
.write_fifo_size (wfifo_size ),
.write_strobe (wfifo_strobe ),
.write_data (wfifo_data ),
//.starved (starved ),
//read
.read_clock (i2s_clock ),
.read_strobe (read_strobe ),
.read_ready (read_ready ),
.read_activate (read_activate ),
.read_count (read_size ),
.read_data (read_data )
);
waveform wave_post (
.clk(clk),
.rst(rst),
.wavelength(test_wavelength),
.pos(test_pos),
.value(test_value)
);
//asynchronous logic
//prepare the data for the i2s writer
`ifdef SIMULATION
always @(posedge i2s_clock or posedge rst) begin
`else
always @(posedge i2s_clock) begin
`endif
read_strobe <= 0;
if (rst) begin
audio_data_ack <= 0;
audio_data <= 0;
audio_lr_bit <= 0;
read_count <= 0;
read_activate <= 0;
state <= READ_STROBE;
test_pos <= 0;
end
else if (enable) begin
//got an ack from the writer
if (~audio_data_request && audio_data_ack) begin
//de-assert the ack
audio_data_ack <= 0;
end
if (post_fifo_wave_en) begin
if (audio_data_request && ~audio_data_ack) begin
audio_lr_bit <= ~audio_lr_bit;
if (test_pos >= test_wavelength - 1) begin
test_pos <= 0;
end
else begin
test_pos <= test_pos + 1;
end
audio_data <= {test_value, 8'h0};
audio_data_ack <= 1;
end
end
else begin
if (read_ready && !read_activate) begin
read_count <= 0;
read_activate <= 1;
end
else if (read_activate) begin
if (read_count < read_size) begin
if (audio_data_request && !audio_data_ack) begin
audio_data <= read_data[23:0];
audio_lr_bit <= read_data[31];
audio_data_ack<= 1;
read_count <= read_count + 1;
read_strobe <= 1;
end
end
else begin
read_activate <= 0;
end
end
end
end
end
endmodule
|
// megafunction wizard: %Altera PLL v14.0%
// GENERATION: XML
// video720.v
// Generated using ACDS version 14.0 200 at 2018.03.18.20:41:24
`timescale 1 ps / 1 ps
module video720 (
input wire refclk, // refclk.clk
input wire rst, // reset.reset
output wire outclk_0 // outclk0.clk
);
video720_0002 video720_inst (
.refclk (refclk), // refclk.clk
.rst (rst), // reset.reset
.outclk_0 (outclk_0), // outclk0.clk
.locked () // (terminated)
);
endmodule
// Retrieval info: <?xml version="1.0"?>
//<!--
// Generated by Altera MegaWizard Launcher Utility version 1.0
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2018 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
//-->
// Retrieval info: <instance entity-name="altera_pll" version="14.0" >
// Retrieval info: <generic name="debug_print_output" value="false" />
// Retrieval info: <generic name="debug_use_rbc_taf_method" value="false" />
// Retrieval info: <generic name="device_family" value="Cyclone V" />
// Retrieval info: <generic name="device" value="Unknown" />
// Retrieval info: <generic name="gui_device_speed_grade" value="1" />
// Retrieval info: <generic name="gui_pll_mode" value="Fractional-N PLL" />
// Retrieval info: <generic name="gui_reference_clock_frequency" value="50.0" />
// Retrieval info: <generic name="gui_channel_spacing" value="0.0" />
// Retrieval info: <generic name="gui_operation_mode" value="direct" />
// Retrieval info: <generic name="gui_feedback_clock" value="Global Clock" />
// Retrieval info: <generic name="gui_fractional_cout" value="32" />
// Retrieval info: <generic name="gui_dsm_out_sel" value="1st_order" />
// Retrieval info: <generic name="gui_use_locked" value="false" />
// Retrieval info: <generic name="gui_en_adv_params" value="false" />
// Retrieval info: <generic name="gui_number_of_clocks" value="1" />
// Retrieval info: <generic name="gui_multiply_factor" value="1" />
// Retrieval info: <generic name="gui_frac_multiply_factor" value="1" />
// Retrieval info: <generic name="gui_divide_factor_n" value="1" />
// Retrieval info: <generic name="gui_cascade_counter0" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency0" value="74.25" />
// Retrieval info: <generic name="gui_divide_factor_c0" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units0" value="ps" />
// Retrieval info: <generic name="gui_phase_shift0" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg0" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift0" value="0" />
// Retrieval info: <generic name="gui_duty_cycle0" value="50" />
// Retrieval info: <generic name="gui_cascade_counter1" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency1" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c1" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency1" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units1" value="ps" />
// Retrieval info: <generic name="gui_phase_shift1" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg1" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift1" value="0" />
// Retrieval info: <generic name="gui_duty_cycle1" value="50" />
// Retrieval info: <generic name="gui_cascade_counter2" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency2" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c2" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency2" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units2" value="ps" />
// Retrieval info: <generic name="gui_phase_shift2" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg2" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift2" value="0" />
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// Retrieval info: <generic name="gui_cascade_counter3" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency3" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c3" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency3" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units3" value="ps" />
// Retrieval info: <generic name="gui_phase_shift3" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg3" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift3" value="0" />
// Retrieval info: <generic name="gui_duty_cycle3" value="50" />
// Retrieval info: <generic name="gui_cascade_counter4" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency4" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c4" value="1" />
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// Retrieval info: <generic name="gui_ps_units4" value="ps" />
// Retrieval info: <generic name="gui_phase_shift4" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg4" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift4" value="0" />
// Retrieval info: <generic name="gui_duty_cycle4" value="50" />
// Retrieval info: <generic name="gui_cascade_counter5" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency5" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c5" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency5" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units5" value="ps" />
// Retrieval info: <generic name="gui_phase_shift5" value="0" />
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// Retrieval info: <generic name="gui_ps_units6" value="ps" />
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// Retrieval info: <generic name="gui_actual_phase_shift6" value="0" />
// Retrieval info: <generic name="gui_duty_cycle6" value="50" />
// Retrieval info: <generic name="gui_cascade_counter7" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency7" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c7" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency7" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units7" value="ps" />
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// Retrieval info: <generic name="gui_output_clock_frequency10" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c10" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency10" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units10" value="ps" />
// Retrieval info: <generic name="gui_phase_shift10" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg10" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift10" value="0" />
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// Retrieval info: <generic name="gui_ps_units11" value="ps" />
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// Retrieval info: <generic name="gui_ps_units12" value="ps" />
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// Retrieval info: <generic name="gui_dps_dir" value="Positive" />
// Retrieval info: <generic name="gui_refclk_switch" value="false" />
// Retrieval info: <generic name="gui_refclk1_frequency" value="100.0" />
// Retrieval info: <generic name="gui_switchover_mode" value="Automatic Switchover" />
// Retrieval info: <generic name="gui_switchover_delay" value="0" />
// Retrieval info: <generic name="gui_active_clk" value="false" />
// Retrieval info: <generic name="gui_clk_bad" value="false" />
// Retrieval info: <generic name="gui_enable_cascade_out" value="false" />
// Retrieval info: <generic name="gui_cascade_outclk_index" value="0" />
// Retrieval info: <generic name="gui_enable_cascade_in" value="false" />
// Retrieval info: <generic name="gui_pll_cascading_mode" value="Create an adjpllin signal to connect with an upstream PLL" />
// Retrieval info: <generic name="AUTO_REFCLK_CLOCK_RATE" value="-1" />
// Retrieval info: </instance>
// IPFS_FILES : video720.vo
// RELATED_FILES: video720.v, video720_0002.v
|
// ============================================================================
// Copyright (c) 2012 by Terasic Technologies Inc.
// ============================================================================
//
// Permission:
//
// Terasic grants permission to use and modify this code for use
// in synthesis for all Terasic Development Boards and Altera Development
// Kits made by Terasic. Other use of this code, including the selling
// ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Terasic provides no warranty regarding the use
// or functionality of this code.
//
// ============================================================================
//
// Terasic Technologies Inc
// 9F., No.176, Sec.2, Gongdao 5th Rd, East Dist, Hsinchu City, 30070. Taiwan
//
//
//
// web: http://www.terasic.com/
// email: [email protected]
//
// ============================================================================
//
// Major Functions: DE2_115_Default
//
// ============================================================================
//
// Revision History :
// ============================================================================
// Ver :| Author :| Mod. Date :| Changes Made:
// V1.1 :| HdHuang :| 05/12/10 :| Initial Revision
// V2.0 :| Eko :| 05/23/12 :| version 11.1
// ============================================================================
// Modified by Alan Ehret to output grayscale video
module DE2_115_TV
(
//////// CLOCK //////////
CLOCK_50,
// CLOCK2_50,
// CLOCK3_50,
ENETCLK_25,
//////// LED //////////
LEDG,
// LEDR,
//////// KEY //////////
KEY,
//////// I2C for Audio and Tv-Decode //////////
I2C_SCLK,
I2C_SDAT,
//////// TV Decoder //////////
TD_CLK27,
TD_DATA,
TD_HS,
TD_RESET_N,
TD_VS,
///////// VGA CTRL and OUTPUT /////////
VGA_R,
VGA_G,
VGA_B,
VGA_BLANK_N,
VGA_CLK,
VGA_HS,
VGA_SYNC_N,
VGA_VS
);
//===========================================================================
// PARAMETER declarations
//===========================================================================
parameter LINEWIDTH = 640;
//===========================================================================
// PORT declarations
//===========================================================================
//////////// CLOCK //////////
input CLOCK_50;
input ENETCLK_25;
//////////// LED //////////
output [8:0] LEDG;
//output [17:0] LEDR;
//////////// KEY //////////
input [3:0] KEY;
//////////// I2C for Audio and Tv-Decode //////////
output I2C_SCLK;
inout I2C_SDAT;
//////////// TV Decoder 1 //////////
input TD_CLK27;
input [7:0] TD_DATA;
input TD_HS;
output TD_RESET_N;
input TD_VS;
//////////// VGA CTRL / OUTPUT //////////
output [7:0] VGA_R, VGA_G, VGA_B;
output VGA_BLANK_N, VGA_HS, VGA_VS, VGA_SYNC_N, VGA_CLK;
///////////////////////////////////////////////////////////////////
//=============================================================================
// REG/WIRE declarations
//=============================================================================
wire CPU_CLK;
wire CPU_RESET;
wire CLK_18_4;
wire CLK_25;
// For ITU-R 656 Decoder
wire [15:0] YCbCr;
wire [9:0] TV_X, TV_Y;
wire TV_DVAL;
// For Delay Timer
wire TD_Stable;
wire DLY0;
wire DLY1;
wire DLY2;
// For Down Sample
wire [3:0] Remain;
wire [9:0] Quotient;
wire mDVAL;
wire NTSC;
wire PAL;
// for Frame Buffer and VGA
wire CLOCK_PX;
wire [7:0] q_a, q_b;
wire [18:0] addr_b;
reg[18:0] addr_a;
// for image processing
wire[7:0] im_processed;
// for ui
wire [9:0] obj_x, obj_y;
//reg [9:0] obj_x, obj_y;
//=============================================================================
// Structural coding
//=============================================================================
//////// Alan's Stuff ///////
//assign LEDG = {1'b1, YCbCr[15:8]};
// PLL for VGA
//pll25_175 vga(CLOCK_50, VGA_CLK);
//pll25_175 main(CLOCK_50, CLOCK_PX);
test vga(CLOCK_50, VGA_CLK);
test main(CLOCK_50, CLOCK_PX);
VGA_Ctrl ( // Host Side
.iRed(q_b),
.iGreen(q_b),
.iBlue(q_b),
// oCurrent_X(),
// oCurrent_Y,
.oAddress(addr_b),
// oRequest,
// VGA Side
.oVGA_R(VGA_R),
.oVGA_G(VGA_G),
.oVGA_B(VGA_B),
.oVGA_HS(VGA_HS),
.oVGA_VS(VGA_VS),
.oVGA_SYNC(VGA_SYNC_N),
.oVGA_BLANK(VGA_BLANK_N),
// oVGA_CLOCK(VGA_CL),
// Control Signal
.iCLK(VGA_CLK),
.iRST_N(1'b1/*KEY[0]*/) );
// User input
user_input ui(
.CLOCK(CLOCK_50),
.RESET(1'b1),
.KEY(KEY),
.OBJ_X(obj_x),
.OBJ_Y(obj_y)
);
// Image Processing
image_processing im(
.CLOCK_50(TD_CLK27/*CLOCK_50*/),
.RESET(1'b1/*KEY[0]*/),
.IM_DATA(YCbCr[15:8]),
.OBJ_X(obj_x),
.OBJ_Y(obj_y),
.FB_ADDR(addr_a),
.FB_DATA(im_processed),
);
// reg [28:0] count;
//always@(posedge TD_CLK27) begin
// count <= count + 29'd1;
// if(count == 29'd0)
// if (obj_x > 10'd150)
// obj_x <= 10'd50;
// else
// obj_x <= obj_x + 10'd1;
// if (obj_y > 10'd150)
// obj_y <= 10'd50;
// else
// obj_y <= obj_y + 10'd1;
//end
//
// Frame buffer
frame_buffer fb(
.address_a(/*addr_a*/TV_X + (TV_Y *640)),
.address_b(addr_b),
.data_a(/*c[9:2]*//*YCbCr[15:8]*/im_processed),
.data_b(8'hff),
.inclock(TD_CLK27),
.outclock(CLOCK_PX/*ENETCLK_25*/),
.wren_a(TV_DVAL),
.wren_b(1'd0),// b is the vga port, will never write
.q_a(LEDG[7:0]),
.q_b(q_b)
);
//// VGA Controll and output
//vga_sram vga_fb(.CLOCK_PX(CLOCK_PX/*ENETCLK_25*/),// this was a seperate pll previously
// .rst(KEY[0]),
// .VGA_R(VGA_R),
// .VGA_G(VGA_G),
// .VGA_B(VGA_B),
// .VGA_HS(VGA_HS),
// .VGA_VS(VGA_VS),
// .VGA_SYNC(VGA_SYNC_N),
// .VGA_BLANK(VGA_BLANK_N),
// .FB_ADDR(addr_b),
// .fb_data(q_b),
// .we_nIN(1'd1)// always display
// );
// reg fb_fill_en;
// reg [9:0] c;
// always@(posedge CLOCK_50 or negedge KEY[0]) begin
// if (KEY[0] == 1'b0) begin
// addr_a <= 19'd0;
// c <= 9'd0;
// fb_fill_en <= 1'b1;
// end else begin
// addr_a <= addr_a + 19'd1;
// if(addr_a > 640*480)
// fb_fill_en <= 1'b0;
// if(c< 640)
// c <= c+1;
// else
// c <= 0;
// end
// end
// Turn On TV Decoder
assign TD_RESET_N = 1'b1;
parameter FB_SIZE = 640*480;
parameter NES_RES = 640*500;
always@(posedge TV_DVAL /*or negedge KEY[0]*/) begin
// if(KEY[0] == 1'b0)
// addr_a <= 19'd0;
// else
if(TD_VS == 1'b0 || addr_a >= NES_RES)
addr_a <= 19'd0;
else
addr_a <= addr_a + 19'd1;
end
//assign wren_a = TV_DVAL;
//assign data_b = 8'hff;
// TV Decoder Stable Check
TD_Detect u2 ( .oTD_Stable(TD_Stable),
.oNTSC(NTSC),
.oPAL(PAL),
.iTD_VS(TD_VS),
.iTD_HS(TD_HS),
.iRST_N(1'b1/*KEY[0]*/) );
// Reset Delay Timer
Reset_Delay u3 ( .iCLK(CLOCK_50),
.iRST(TD_Stable),
.oRST_0(DLY0),
.oRST_1(DLY1),
.oRST_2(DLY2));
// ITU-R 656 to YUV 4:2:2
ITU_656_Decoder u4 ( // TV Decoder Input
.iTD_DATA(TD_DATA),
// Position Output
.oTV_X(TV_X),
.oTV_Y(TV_Y),
// YUV 4:2:2 Output
.oYCbCr(YCbCr),
.oDVAL(TV_DVAL),
// Control Signals
.iSwap_CbCr(Quotient[0]),
.iSkip(Remain==4'h0),
.iRST_N(DLY1),
.iCLK_27(TD_CLK27) );
// For Down Sample 720 to 640
DIV u5 ( .aclr(!DLY0),
.clock(TD_CLK27),
.denom(4'h9),
.numer(TV_X),
.quotient(Quotient),
.remain(Remain));
// Audio CODEC and video decoder setting
I2C_AV_Config u1 ( // Host Side
.iCLK(CLOCK_50),
.iRST_N(1'b1/*KEY[0]*/),
// I2C Side
.I2C_SCLK(I2C_SCLK),
.I2C_SDAT(I2C_SDAT) );
endmodule
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_arb_hp0_1.v
*
* Date : 2012-11
*
* Description : Module that arbitrates between RD/WR requests from 2 ports.
* Used for modelling the Top_Interconnect switch.
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_5_arb_hp0_1(
sw_clk,
rstn,
w_qos_hp0,
r_qos_hp0,
w_qos_hp1,
r_qos_hp1,
wr_ack_ddr_hp0,
wr_data_hp0,
wr_addr_hp0,
wr_bytes_hp0,
wr_dv_ddr_hp0,
rd_req_ddr_hp0,
rd_addr_hp0,
rd_bytes_hp0,
rd_data_ddr_hp0,
rd_dv_ddr_hp0,
wr_ack_ddr_hp1,
wr_data_hp1,
wr_addr_hp1,
wr_bytes_hp1,
wr_dv_ddr_hp1,
rd_req_ddr_hp1,
rd_addr_hp1,
rd_bytes_hp1,
rd_data_ddr_hp1,
rd_dv_ddr_hp1,
ddr_wr_ack,
ddr_wr_dv,
ddr_rd_req,
ddr_rd_dv,
ddr_rd_qos,
ddr_wr_qos,
ddr_wr_addr,
ddr_wr_data,
ddr_wr_bytes,
ddr_rd_addr,
ddr_rd_data,
ddr_rd_bytes
);
`include "processing_system7_bfm_v2_0_5_local_params.v"
input sw_clk;
input rstn;
input [axi_qos_width-1:0] w_qos_hp0;
input [axi_qos_width-1:0] r_qos_hp0;
input [axi_qos_width-1:0] w_qos_hp1;
input [axi_qos_width-1:0] r_qos_hp1;
input [axi_qos_width-1:0] ddr_rd_qos;
input [axi_qos_width-1:0] ddr_wr_qos;
output wr_ack_ddr_hp0;
input [max_burst_bits-1:0] wr_data_hp0;
input [addr_width-1:0] wr_addr_hp0;
input [max_burst_bytes_width:0] wr_bytes_hp0;
output wr_dv_ddr_hp0;
input rd_req_ddr_hp0;
input [addr_width-1:0] rd_addr_hp0;
input [max_burst_bytes_width:0] rd_bytes_hp0;
output [max_burst_bits-1:0] rd_data_ddr_hp0;
output rd_dv_ddr_hp0;
output wr_ack_ddr_hp1;
input [max_burst_bits-1:0] wr_data_hp1;
input [addr_width-1:0] wr_addr_hp1;
input [max_burst_bytes_width:0] wr_bytes_hp1;
output wr_dv_ddr_hp1;
input rd_req_ddr_hp1;
input [addr_width-1:0] rd_addr_hp1;
input [max_burst_bytes_width:0] rd_bytes_hp1;
output [max_burst_bits-1:0] rd_data_ddr_hp1;
output rd_dv_ddr_hp1;
input ddr_wr_ack;
output ddr_wr_dv;
output [addr_width-1:0]ddr_wr_addr;
output [max_burst_bits-1:0]ddr_wr_data;
output [max_burst_bytes_width:0]ddr_wr_bytes;
input ddr_rd_dv;
input [max_burst_bits-1:0] ddr_rd_data;
output ddr_rd_req;
output [addr_width-1:0] ddr_rd_addr;
output [max_burst_bytes_width:0] ddr_rd_bytes;
processing_system7_bfm_v2_0_5_arb_wr ddr_hp_wr(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(w_qos_hp0),
.qos2(w_qos_hp1),
.prt_dv1(wr_dv_ddr_hp0),
.prt_dv2(wr_dv_ddr_hp1),
.prt_data1(wr_data_hp0),
.prt_data2(wr_data_hp1),
.prt_addr1(wr_addr_hp0),
.prt_addr2(wr_addr_hp1),
.prt_bytes1(wr_bytes_hp0),
.prt_bytes2(wr_bytes_hp1),
.prt_ack1(wr_ack_ddr_hp0),
.prt_ack2(wr_ack_ddr_hp1),
.prt_req(ddr_wr_dv),
.prt_qos(ddr_wr_qos),
.prt_data(ddr_wr_data),
.prt_addr(ddr_wr_addr),
.prt_bytes(ddr_wr_bytes),
.prt_ack(ddr_wr_ack)
);
processing_system7_bfm_v2_0_5_arb_rd ddr_hp_rd(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(r_qos_hp0),
.qos2(r_qos_hp1),
.prt_req1(rd_req_ddr_hp0),
.prt_req2(rd_req_ddr_hp1),
.prt_data1(rd_data_ddr_hp0),
.prt_data2(rd_data_ddr_hp1),
.prt_addr1(rd_addr_hp0),
.prt_addr2(rd_addr_hp1),
.prt_bytes1(rd_bytes_hp0),
.prt_bytes2(rd_bytes_hp1),
.prt_dv1(rd_dv_ddr_hp0),
.prt_dv2(rd_dv_ddr_hp1),
.prt_qos(ddr_rd_qos),
.prt_req(ddr_rd_req),
.prt_data(ddr_rd_data),
.prt_addr(ddr_rd_addr),
.prt_bytes(ddr_rd_bytes),
.prt_dv(ddr_rd_dv)
);
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// Top level module for in-order coalesced memory access.
//
// Properties - Coalesced: Yes, Ordered: Yes, Hazard-Safe: Yes, Pipelined: Yes
// (see lsu_top.v for details)
//
// Description: Requests are submitted as soon as possible to memory, stalled
// requests are coalesced with neighbouring requests if they
// access the same page of memory.
// Basic coalesced read unit:
// Accept read requests on the upstream interface. Requests are sent to
// the avalon bus as soon as they are recieved. If the avalon bus is
// stalling, requests to the same global-memory word are coalesced into
// a single request to improve efficiency.
//
// The request FIFO stores the byte-address to select the appropriate word
// out of the response data as well as an extra bit to indicate if the
// request is coalesced with the previous request or if a new request was
// made. The output port looks ahead to the next pending request to
// determine whether the current response data can be thrown away or
// must be kept to service the next coalesced request.
module lsu_basic_coalesced_read
(
clk, reset, o_stall, i_valid, i_address, i_stall, o_valid, o_readdata,
o_active, //Debugging signal
avm_address, avm_read, avm_readdata, avm_waitrequest, avm_byteenable,
avm_readdatavalid
);
/*************
* Parameters *
*************/
parameter AWIDTH=32; // Address width (32-bits for Avalon)
parameter WIDTH_BYTES=4; // Width of the memory access (bytes)
parameter MWIDTH_BYTES=32; // Width of the global memory bus (bytes)
parameter ALIGNMENT_ABITS=2; // Request address alignment (address bits)
parameter KERNEL_SIDE_MEM_LATENCY=32; // Determines the max number of live requests.
// Derived parameters
localparam WIDTH=8*WIDTH_BYTES;
localparam MWIDTH=8*MWIDTH_BYTES;
localparam BYTE_SELECT_BITS=$clog2(MWIDTH_BYTES);
localparam SEGMENT_SELECT_BITS=BYTE_SELECT_BITS-ALIGNMENT_ABITS;
localparam PAGE_SELECT_BITS=AWIDTH-BYTE_SELECT_BITS;
// Constants
localparam REQUEST_FIFO_DEPTH=2*KERNEL_SIDE_MEM_LATENCY;
/********
* Ports *
********/
// Standard global signals
input clk;
input reset;
// Upstream interface
output o_stall;
input i_valid;
input [AWIDTH-1:0] i_address;
// Downstream interface
input i_stall;
output o_valid;
output [WIDTH-1:0] o_readdata;
output o_active;
// Avalon interface
output [AWIDTH-1:0] avm_address;
output avm_read;
input [MWIDTH-1:0] avm_readdata;
input avm_waitrequest;
output [MWIDTH_BYTES-1:0] avm_byteenable;
input avm_readdatavalid;
/***************
* Architecture *
***************/
wire [PAGE_SELECT_BITS-1:0] page_addr;
wire [SEGMENT_SELECT_BITS:0] rf_data_in;
wire [BYTE_SELECT_BITS-1:0] byte_addr;
wire next_new_page;
wire c_stall;
wire c_new_page;
wire [PAGE_SELECT_BITS-1:0] c_req_addr;
wire c_req_valid;
wire rf_full;
wire rf_valid;
wire [SEGMENT_SELECT_BITS:0] rf_data;
wire rf_next_valid;
wire [SEGMENT_SELECT_BITS:0] rf_next_data;
wire rf_stall_in;
wire rm_stall;
wire rm_valid;
wire rm_active;
wire [MWIDTH-1:0] rm_data;
wire rm_stall_in;
// Coalescer - Groups subsequent requests together if they are compatible and
// the avalon bus is stalled.
assign page_addr = i_address[AWIDTH-1:BYTE_SELECT_BITS];
basic_coalescer #(
.PAGE_ADDR_WIDTH(PAGE_SELECT_BITS),
.TIMEOUT(MWIDTH/WIDTH)
) coalescer (
.clk(clk),
.reset(reset),
.i_page_addr(page_addr),
.i_valid(i_valid && !rf_full),
.o_stall(c_stall),
.o_new_page(c_new_page),
.o_req_addr(c_req_addr),
.o_req_valid(c_req_valid),
.i_stall(rm_stall)
);
// Response FIFO - Buffers the requests so they can be extracted from the
// wider memory bus. Stores the segment address to extract the requested
// word from the response data, and a bit indicating if the request comes
// from a new page.
generate if(SEGMENT_SELECT_BITS > 0)
begin
wire [SEGMENT_SELECT_BITS-1:0] segment_addr;
assign segment_addr = i_address[BYTE_SELECT_BITS-1:ALIGNMENT_ABITS];
assign rf_data_in = {c_new_page, segment_addr};
assign byte_addr = (rf_data[SEGMENT_SELECT_BITS-1:0] << ALIGNMENT_ABITS);
end
else
begin
assign rf_data_in = c_new_page;
assign byte_addr = {BYTE_SELECT_BITS{1'b0}};
end
endgenerate
lookahead_fifo #(
.WIDTH( SEGMENT_SELECT_BITS + 1 ),
.DEPTH( REQUEST_FIFO_DEPTH )
) request_fifo (
.clk(clk),
.reset(reset),
.i_data( rf_data_in ),
.i_valid( i_valid && !c_stall ),
.o_full(rf_full),
.i_stall(rf_stall_in),
.o_valid(rf_valid),
.o_data(rf_data),
.o_next_valid(rf_next_valid),
.o_next_data(rf_next_data)
);
// Read master - Handles pipelined read transactions through MM-Avalon.
lsu_pipelined_read #(
.AWIDTH( AWIDTH ),
.WIDTH_BYTES( MWIDTH_BYTES ),
.MWIDTH_BYTES( MWIDTH_BYTES ),
.ALIGNMENT_ABITS( BYTE_SELECT_BITS ),
.KERNEL_SIDE_MEM_LATENCY( KERNEL_SIDE_MEM_LATENCY ),
.USEOUTPUTFIFO(1),
.USEINPUTFIFO( 1 ), // Add the latency adjusting input fifos
.PIPELINE_INPUT( 1 ) // Let's add a pipline input to the input side just to help with Fmax
) read_master (
.clk(clk),
.reset(reset),
.o_stall(rm_stall),
.i_valid(c_req_valid),
.i_address({c_req_addr, {BYTE_SELECT_BITS{1'b0}}}),
.i_stall(rm_stall_in),
.o_valid(rm_valid),
.o_active(rm_active),
.o_readdata(rm_data),
.avm_address(avm_address),
.avm_read(avm_read),
.avm_readdata(avm_readdata),
.avm_waitrequest(avm_waitrequest),
.avm_byteenable(avm_byteenable),
.avm_readdatavalid(avm_readdatavalid)
);
// Control logic
// Highest bit of rf_next_data indicates whether this is a new avalon request
// (new page) or was coalesced into the previous request.
assign next_new_page = rf_next_data[SEGMENT_SELECT_BITS];
assign rm_stall_in = (!next_new_page && rf_next_valid) || rf_stall_in;
assign rf_stall_in = i_stall || !rm_valid;
// Output MUX
assign o_readdata = rm_data[8*byte_addr +: WIDTH];
// External control signals
assign o_stall = c_stall || rf_full;
assign o_valid = rm_valid && rf_valid;
assign o_active=rf_valid | rm_active;
endmodule
/******************************************************************************/
// Basic coalesced write unit:
// Accept write requests on the upstream interface. The avalon spec does
// not allow a request to change while it is being stalled, so the current
// request is registered in an output register stage and not modified.
// Subsequent requests are coalesced together as long as the output register
// stage is occupied (i.e. the avalon bus is stalling).
//
// TODO: The byte enable format is not actually compliant with the
// Avalon spec. Essentially we should not enable non-adjacent words in a write
// request. This is OK for the DDR Memory Controller as it accepts our
// non-compliant format. This needs to be investigated further.
module lsu_basic_coalesced_write
(
clk, reset, o_stall, i_valid, i_address, i_writedata, i_stall, o_valid, i_byteenable,
o_active, //Debugging signal
avm_address, avm_write, avm_writeack, avm_writedata, avm_byteenable, avm_waitrequest
);
/*************
* Parameters *
*************/
parameter AWIDTH=32; // Address width (32-bits for Avalon)
parameter WIDTH_BYTES=4; // Width of the memory access (bytes)
parameter MWIDTH_BYTES=32; // Width of the global memory bus (bytes)
parameter ALIGNMENT_ABITS=2; // Request address alignment (address bits)
parameter KERNEL_SIDE_MEM_LATENCY=32; // Memory latency in cycles
parameter USE_BYTE_EN;
// Derived parameters
localparam WIDTH=8*WIDTH_BYTES;
localparam MWIDTH=8*MWIDTH_BYTES;
localparam BYTE_SELECT_BITS=$clog2(MWIDTH_BYTES);
localparam SEGMENT_SELECT_BITS=BYTE_SELECT_BITS-ALIGNMENT_ABITS;
localparam PAGE_SELECT_BITS=AWIDTH-BYTE_SELECT_BITS;
localparam NUM_SEGMENTS=2**SEGMENT_SELECT_BITS;
localparam SEGMENT_WIDTH=8*(2**ALIGNMENT_ABITS);
localparam SEGMENT_WIDTH_BYTES=(2**ALIGNMENT_ABITS);
// Constants
localparam COUNTER_WIDTH=8; // Determines the max writes 'in-flight'
/********
* Ports *
********/
// Standard global signals
input clk;
input reset;
// Upstream interface
output o_stall;
input i_valid;
input [AWIDTH-1:0] i_address;
input [WIDTH-1:0] i_writedata;
// Downstream interface
input i_stall;
output o_valid;
output o_active;
// Avalon interface
output [AWIDTH-1:0] avm_address;
output avm_write;
input avm_writeack;
output [MWIDTH-1:0] avm_writedata;
output [MWIDTH_BYTES-1:0] avm_byteenable;
input avm_waitrequest;
input [WIDTH_BYTES-1:0] i_byteenable;
/***************
* Architecture *
***************/
wire input_accepted;
wire output_acknowledged;
wire write_accepted;
wire [PAGE_SELECT_BITS-1:0] page_addr;
wire c_new_page;
wire [PAGE_SELECT_BITS-1:0] c_req_addr;
wire c_req_valid;
wire c_stall;
reg [COUNTER_WIDTH-1:0] occ_counter;
reg [COUNTER_WIDTH-1:0] ack_counter;
reg [COUNTER_WIDTH-1:0] next_counter;
reg [COUNTER_WIDTH-1:0] or_next_counter;
wire [COUNTER_WIDTH-1:0] rf_count;
wire rf_read;
wire rf_empty;
wire rf_full;
reg [MWIDTH-1:0] wm_writedata;
reg [MWIDTH_BYTES-1:0] wm_byteenable;
reg [MWIDTH-1:0] wm_wide_wdata;
reg [MWIDTH_BYTES-1:0] wm_wide_be;
reg [MWIDTH-1:0] wm_wide_bite;
wire or_ready;
reg or_write;
reg [AWIDTH-1:0] or_address;
reg [MWIDTH-1:0] or_writedata;
reg [MWIDTH_BYTES-1:0] or_byteenable;
wire oc_full;
// Output register stage to store the next request
assign or_ready = !or_write || !avm_waitrequest;
always@(posedge clk or posedge reset)
begin
if(reset)
begin
or_write <= 1'b0;
or_address <= {AWIDTH{1'b0}};
or_writedata <= {MWIDTH{1'b0}};
or_byteenable <= {MWIDTH_BYTES{1'b0}};
or_next_counter <= {COUNTER_WIDTH{1'b0}};
end
else
begin
if(or_ready)
begin
or_write <= c_req_valid;
or_address <= (c_req_addr << BYTE_SELECT_BITS);
or_writedata <= wm_writedata;
or_byteenable <= wm_byteenable;
or_next_counter <= next_counter;
end
end
end
assign avm_address = or_address;
assign avm_write = or_write;
assign avm_writedata = or_writedata;
assign avm_byteenable = or_byteenable;
// The address components
assign page_addr = i_address[AWIDTH-1:BYTE_SELECT_BITS];
// Coalescer - Groups subsequent requests together if they are compatible
// and the output register stage is stalled
basic_coalescer #(
.PAGE_ADDR_WIDTH(PAGE_SELECT_BITS),
.TIMEOUT(MWIDTH/WIDTH)
) coalescer (
.clk(clk),
.reset(reset),
.i_page_addr(page_addr),
.i_valid(i_valid && !oc_full),
.o_stall(c_stall),
.o_new_page(c_new_page),
.o_req_addr(c_req_addr),
.o_req_valid(c_req_valid),
.i_stall(!or_ready)
);
// Writedata MUX
generate if( SEGMENT_SELECT_BITS > 0 )
begin
wire [SEGMENT_SELECT_BITS-1:0] segment_select;
assign segment_select = i_address[BYTE_SELECT_BITS-1:ALIGNMENT_ABITS];
always@(*)
begin
wm_wide_wdata = {MWIDTH{1'bx}};
wm_wide_wdata[segment_select*SEGMENT_WIDTH +: WIDTH] = i_writedata;
wm_wide_be = {MWIDTH_BYTES{1'b0}};
wm_wide_be[segment_select*SEGMENT_WIDTH_BYTES +: WIDTH_BYTES] = USE_BYTE_EN ? i_byteenable : {WIDTH_BYTES{1'b1}};
wm_wide_bite = {MWIDTH{1'b0}};
wm_wide_bite[segment_select*SEGMENT_WIDTH +: WIDTH] = {WIDTH{1'b1}};
end
end
else
begin
always@(*)
begin
wm_wide_wdata = {MWIDTH{1'bx}};
wm_wide_wdata[0 +: WIDTH] = i_writedata;
wm_wide_be = {MWIDTH_BYTES{1'b0}};
wm_wide_be[0 +: WIDTH_BYTES] = USE_BYTE_EN ? i_byteenable : {WIDTH_BYTES{1'b1}} ;
wm_wide_bite = {MWIDTH{1'b0}};
wm_wide_bite[0 +: WIDTH] = {WIDTH{1'b1}};
end
end
endgenerate
// Track the current write burst data - coalesce writes together until the
// output registers are ready for a new request.
always@(posedge clk or posedge reset)
begin
if(reset)
begin
wm_writedata <= {MWIDTH{1'b0}};
wm_byteenable <= {MWIDTH_BYTES{1'b0}};
end
else
begin
if(c_new_page)
begin
wm_writedata <= wm_wide_wdata;
wm_byteenable <= wm_wide_be;
end
else if(input_accepted)
begin
wm_writedata <= (wm_wide_wdata & wm_wide_bite) | (wm_writedata & ~wm_wide_bite);
wm_byteenable <= wm_wide_be | wm_byteenable;
end
end
end
// Write size tracker - track the number of threads represented by each pending write request
acl_ll_fifo #(
.WIDTH(COUNTER_WIDTH),
.DEPTH(KERNEL_SIDE_MEM_LATENCY+1)
) req_fifo (
.clk(clk),
.reset(reset),
.data_in( or_next_counter ),
.data_out( rf_count ),
.write( write_accepted && (!rf_empty || !avm_writeack) ),
.read( rf_read ),
.empty( rf_empty ),
.full( rf_full )
);
assign rf_read = avm_writeack && !rf_empty;
// Occupancy counter - track the number of successfully transmitted writes
// and the number of writes pending in the next request.
// occ_counter - the total occupancy (in threads) of the unit
// next_counter - the number of threads coalesced into the next transfer
// ack_counter - the number of pending threads with write completion acknowledged
assign input_accepted = i_valid && !o_stall;
assign write_accepted = avm_write && !avm_waitrequest;
assign output_acknowledged = o_valid && !i_stall;
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
begin
occ_counter <= {COUNTER_WIDTH{1'b0}};
ack_counter <= {COUNTER_WIDTH{1'b0}};
next_counter <= {COUNTER_WIDTH{1'b0}};
end
else
begin
occ_counter <= occ_counter + input_accepted - output_acknowledged;
next_counter <= input_accepted + ((c_req_valid & or_ready) ? {COUNTER_WIDTH{1'b0}} : next_counter);
ack_counter <= ack_counter + ({COUNTER_WIDTH{avm_writeack}} & ( rf_empty ? or_next_counter : rf_count )) - output_acknowledged;
end
end
assign oc_full = (occ_counter == {COUNTER_WIDTH{1'b1}});
// Pipeline control signals
assign o_stall = oc_full || c_stall || rf_full;
assign o_valid = (ack_counter > {COUNTER_WIDTH{1'b0}});
assign o_active = (occ_counter != {COUNTER_WIDTH{1'b0}});
endmodule
/******************************************************************************/
/* RESPONSE FIFO */
// lookahead_fifo - A simple sc_fifo instantiation with an additional
// shift-register stage at the end to provide access to the next two data
// items.
module lookahead_fifo
(
clk, reset, i_data, i_valid, o_full, i_stall, o_valid, o_data,
o_next_valid, o_next_data
);
parameter WIDTH=32;
parameter DEPTH=32;
input clk;
input reset;
input [WIDTH-1:0] i_data;
input i_valid;
output o_full;
input i_stall;
output reg o_valid;
output reg [WIDTH-1:0] o_data;
output o_next_valid;
output [WIDTH-1:0] o_next_data;
wire sr_ready;
// Fifo
acl_data_fifo #(
.DATA_WIDTH(WIDTH),
.DEPTH(DEPTH),
.IMPL("ram_plus_reg")
) req_fifo (
.clock(clk),
.resetn(!reset),
.data_in( i_data ),
.data_out( o_next_data ),
.valid_in( i_valid ),
.valid_out( o_next_valid ),
.stall_in( !sr_ready ),
.stall_out( o_full )
);
// Shift-reg
assign sr_ready = !o_valid || !i_stall;
always@(posedge clk or posedge reset)
begin
if(reset)
begin
o_data <= {WIDTH{1'b0}};
o_valid <= 1'b0;
end
else
begin
o_valid <= sr_ready ? o_next_valid : o_valid;
o_data <= sr_ready ? o_next_data : o_data;
end
end
endmodule
/* BASIC COALESCING MODULE */
// basic_coalescer - Accept new inputs as long as the unit is not stalled,
// or the new request can be coalesced with the pending (stalled) request.
module basic_coalescer
(
clk, reset, i_page_addr, i_valid, o_stall, o_new_page, o_req_addr,
o_req_valid, i_stall
);
parameter PAGE_ADDR_WIDTH=32;
parameter TIMEOUT=8; // power of 2
input clk;
input reset;
input [PAGE_ADDR_WIDTH-1:0] i_page_addr;
input i_valid;
output o_stall;
output o_new_page;
output [PAGE_ADDR_WIDTH-1:0] o_req_addr;
output o_req_valid;
input i_stall;
reg [PAGE_ADDR_WIDTH-1:0] page_addr;
reg valid;
wire ready;
wire waiting;
wire match;
wire timeout;
reg [$clog2(TIMEOUT):0] timeout_counter;
assign timeout = timeout_counter[$clog2(TIMEOUT)];
// Internal signal logic
assign match = (i_page_addr == page_addr);
assign ready = !valid || !(i_stall || waiting);
assign waiting = !timeout && (!i_valid || match);
always@(posedge clk or posedge reset)
begin
if(reset)
begin
page_addr <= {PAGE_ADDR_WIDTH{1'b0}};
valid <= 1'b0;
timeout_counter <= '0;
end
else
begin
page_addr <= ready ? i_page_addr : page_addr;
valid <= ready ? i_valid : valid;
if( i_valid )
timeout_counter <= 'd1;
else if( valid && !timeout )
timeout_counter <= timeout_counter + 'd1;
end
end
// Outputs
assign o_stall = i_valid && !match && !ready;
assign o_new_page = ready;
assign o_req_addr = page_addr;
assign o_req_valid = valid && !waiting;
endmodule
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_intr_rd_mem.v
*
* Date : 2012-11
*
* Description : Mimics interconnect for Reads between AFI and DDRC/OCM
*
*****************************************************************************/
module processing_system7_bfm_v2_0_intr_rd_mem(
sw_clk,
rstn,
full,
empty,
req,
invalid_rd_req,
rd_info,
RD_DATA_OCM,
RD_DATA_DDR,
RD_DATA_VALID_OCM,
RD_DATA_VALID_DDR
);
`include "processing_system7_bfm_v2_0_local_params.v"
input sw_clk, rstn;
output full, empty;
input RD_DATA_VALID_DDR, RD_DATA_VALID_OCM;
input [max_burst_bits-1:0] RD_DATA_DDR, RD_DATA_OCM;
input req, invalid_rd_req;
input [rd_info_bits-1:0] rd_info;
reg [intr_cnt_width-1:0] wr_ptr = 0, rd_ptr = 0;
reg [rd_afi_fifo_bits-1:0] rd_fifo [0:intr_max_outstanding-1]; // Data, addr, size, burst, len, RID, RRESP, valid bytes
wire full, empty;
assign empty = (wr_ptr === rd_ptr)?1'b1: 1'b0;
assign full = ((wr_ptr[intr_cnt_width-1]!== rd_ptr[intr_cnt_width-1]) && (wr_ptr[intr_cnt_width-2:0] === rd_ptr[intr_cnt_width-2:0]))?1'b1 :1'b0;
/* read from the fifo */
task read_mem;
output [rd_afi_fifo_bits-1:0] data;
begin
data = rd_fifo[rd_ptr[intr_cnt_width-1:0]];
if(rd_ptr[intr_cnt_width-2:0] === intr_max_outstanding-1)
rd_ptr[intr_cnt_width-2:0] = 0;
else
rd_ptr = rd_ptr + 1;
end
endtask
reg state;
reg invalid_rd;
/* write in the fifo */
always@(negedge rstn or posedge sw_clk)
begin
if(!rstn) begin
wr_ptr <= 0;
rd_ptr <= 0;
state <= 0;
invalid_rd <= 0;
end else begin
case (state)
0 : begin
state <= 0;
invalid_rd <= 0;
if(req)begin
state <= 1;
invalid_rd <= invalid_rd_req;
end
end
1 : begin
state <= 1;
if(RD_DATA_VALID_OCM | RD_DATA_VALID_DDR | invalid_rd) begin
if(RD_DATA_VALID_DDR)
rd_fifo[wr_ptr[intr_cnt_width-2:0]] <= {RD_DATA_DDR,rd_info};
else if(RD_DATA_VALID_OCM)
rd_fifo[wr_ptr[intr_cnt_width-2:0]] <= {RD_DATA_OCM,rd_info};
else
rd_fifo[wr_ptr[intr_cnt_width-2:0]] <= rd_info;
if(wr_ptr[intr_cnt_width-2:0] === intr_max_outstanding-1)
wr_ptr[intr_cnt_width-2:0] <= 0;
else
wr_ptr <= wr_ptr + 1;
state <= 0;
invalid_rd <= 0;
end
end
endcase
end
end
endmodule
|
// megafunction wizard: %ALTFP_CONVERT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTFP_CONVERT
// ============================================================
// File Name: acl_fp_fptosi_double.v
// Megafunction Name(s):
// ALTFP_CONVERT
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.0 Build 157 04/27/2011 SJ Full Version
// ************************************************************
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altfp_convert CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix IV" OPERATION="FLOAT2INT" ROUNDING="TO_NEAREST" WIDTH_DATA=64 WIDTH_EXP_INPUT=11 WIDTH_EXP_OUTPUT=8 WIDTH_INT=33 WIDTH_MAN_INPUT=52 WIDTH_MAN_OUTPUT=23 WIDTH_RESULT=33 clk_en clock dataa result
//VERSION_BEGIN 11.0 cbx_altbarrel_shift 2011:04:27:21:09:05:SJ cbx_altfp_convert 2011:04:27:21:09:05:SJ cbx_altpriority_encoder 2011:04:27:21:09:05:SJ cbx_altsyncram 2011:04:27:21:09:05:SJ cbx_cycloneii 2011:04:27:21:09:05:SJ cbx_lpm_abs 2011:04:27:21:09:05:SJ cbx_lpm_add_sub 2011:04:27:21:09:05:SJ cbx_lpm_compare 2011:04:27:21:09:05:SJ cbx_lpm_decode 2011:04:27:21:09:05:SJ cbx_lpm_divide 2011:04:27:21:09:05:SJ cbx_lpm_mux 2011:04:27:21:09:05:SJ cbx_mgl 2011:04:27:21:10:09:SJ cbx_stratix 2011:04:27:21:09:05:SJ cbx_stratixii 2011:04:27:21:09:05:SJ cbx_stratixiii 2011:04:27:21:09:05:SJ cbx_stratixv 2011:04:27:21:09:05:SJ cbx_util_mgl 2011:04:27:21:09:05:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//altbarrel_shift CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix IV" PIPELINE=2 SHIFTDIR="LEFT" SHIFTTYPE="LOGICAL" WIDTH=84 WIDTHDIST=7 aclr clk_en clock data distance result
//VERSION_BEGIN 11.0 cbx_altbarrel_shift 2011:04:27:21:09:05:SJ cbx_mgl 2011:04:27:21:10:09:SJ VERSION_END
//synthesis_resources = reg 173
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_fptosi_double_altbarrel_shift_3tf
(
aclr,
clk_en,
clock,
data,
distance,
result) ;
input aclr;
input clk_en;
input clock;
input [83:0] data;
input [6:0] distance;
output [83:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clk_en;
tri0 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [1:0] dir_pipe;
reg [83:0] sbit_piper1d;
reg [83:0] sbit_piper2d;
reg sel_pipec4r1d;
reg sel_pipec5r1d;
reg sel_pipec6r1d;
wire [7:0] dir_w;
wire direction_w;
wire [63:0] pad_w;
wire [671:0] sbit_w;
wire [6:0] sel_w;
wire [587:0] smux_w;
// synopsys translate_off
initial
dir_pipe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) dir_pipe <= 2'b0;
else if (clk_en == 1'b1) dir_pipe <= {dir_w[6], dir_w[3]};
// synopsys translate_off
initial
sbit_piper1d = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sbit_piper1d <= 84'b0;
else if (clk_en == 1'b1) sbit_piper1d <= smux_w[335:252];
// synopsys translate_off
initial
sbit_piper2d = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sbit_piper2d <= 84'b0;
else if (clk_en == 1'b1) sbit_piper2d <= smux_w[587:504];
// synopsys translate_off
initial
sel_pipec4r1d = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sel_pipec4r1d <= 1'b0;
else if (clk_en == 1'b1) sel_pipec4r1d <= distance[4];
// synopsys translate_off
initial
sel_pipec5r1d = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sel_pipec5r1d <= 1'b0;
else if (clk_en == 1'b1) sel_pipec5r1d <= distance[5];
// synopsys translate_off
initial
sel_pipec6r1d = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sel_pipec6r1d <= 1'b0;
else if (clk_en == 1'b1) sel_pipec6r1d <= distance[6];
assign
dir_w = {dir_pipe[1], dir_w[5:4], dir_pipe[0], dir_w[2:0], direction_w},
direction_w = 1'b0,
pad_w = {64{1'b0}},
result = sbit_w[671:588],
sbit_w = {sbit_piper2d, smux_w[503:336], sbit_piper1d, smux_w[251:0], data},
sel_w = {sel_pipec6r1d, sel_pipec5r1d, sel_pipec4r1d, distance[3:0]},
smux_w = {((({84{(sel_w[6] & (~ dir_w[6]))}} & {sbit_w[523:504], pad_w[63:0]}) | ({84{(sel_w[6] & dir_w[6])}} & {pad_w[63:0], sbit_w[587:568]})) | ({84{(~ sel_w[6])}} & sbit_w[587:504])), ((({84{(sel_w[5] & (~ dir_w[5]))}} & {sbit_w[471:420], pad_w[31:0]}) | ({84{(sel_w[5] & dir_w[5])}} & {pad_w[31:0], sbit_w[503:452]})) | ({84{(~ sel_w[5])}} & sbit_w[503:420])), ((({84{(sel_w[4] & (~ dir_w[4]))}} & {sbit_w[403:336], pad_w[15:0]}) | ({84{(sel_w[4] & dir_w[4])}} & {pad_w[15:0], sbit_w[419:352]})) | ({84{(~ sel_w[4])}} & sbit_w[419:336])), ((({84{(sel_w[3] & (~ dir_w[3]))}} & {sbit_w[327:252], pad_w[7:0]}) | ({84{(sel_w[3] & dir_w[3])}} & {pad_w[7:0], sbit_w[335:260]})) | ({84{(~ sel_w[3])}} & sbit_w[335:252])), ((({84{(sel_w[2] & (~ dir_w[2]))}} & {sbit_w[247:168], pad_w[3:0]}) | ({84{(sel_w[2] & dir_w[2])}} & {pad_w[3:0], sbit_w[251:172]})) | ({84{(~ sel_w[2])}} & sbit_w[251:168])), ((({84{(sel_w[1] & (~ dir_w[1]))}} & {sbit_w[165:84], pad_w[1:0]}) | ({84{(sel_w[1] & dir_w[1])}} & {pad_w[1:0], sbit_w[167:86]})) | ({84{(~ sel_w[1])}} & sbit_w[167:84])), ((({84{(sel_w[0] & (~ dir_w[0]))}} & {sbit_w[82:0], pad_w[0]}) | ({84{(sel_w[0] & dir_w[0])}} & {pad_w[0], sbit_w[83:1]})) | ({84{(~ sel_w[0])}} & sbit_w[83:0]))};
endmodule //acl_fp_fptosi_double_altbarrel_shift_3tf
//synthesis_resources = lpm_add_sub 5 lpm_compare 4 reg 406
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_fptosi_double_altfp_convert_hkn
(
clk_en,
clock,
dataa,
result) ;
input clk_en;
input clock;
input [63:0] dataa;
output [32:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clk_en;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [83:0] wire_altbarrel_shift6_result;
reg [6:0] added_power2_reg;
reg below_lower_limit1_reg1;
reg below_lower_limit1_reg2;
reg below_lower_limit1_reg3;
reg below_lower_limit2_reg1;
reg below_lower_limit2_reg2;
reg below_lower_limit2_reg3;
reg below_lower_limit2_reg4;
reg [63:0] dataa_reg;
reg equal_upper_limit_reg1;
reg equal_upper_limit_reg2;
reg equal_upper_limit_reg3;
reg exceed_upper_limit_reg1;
reg exceed_upper_limit_reg2;
reg exceed_upper_limit_reg3;
reg exceed_upper_limit_reg4;
reg exp_and_reg1;
reg exp_and_reg2;
reg exp_and_reg3;
reg exp_and_reg4;
reg exp_or_reg1;
reg exp_or_reg2;
reg exp_or_reg3;
reg exp_or_reg4;
reg int_or1_reg1;
reg int_or2_reg1;
reg int_or_reg2;
reg int_or_reg3;
reg [32:0] integer_result_reg;
reg [31:0] integer_rounded_reg;
reg lowest_int_sel_reg;
reg man_or1_reg1;
reg man_or2_reg1;
reg man_or_reg2;
reg man_or_reg3;
reg man_or_reg4;
reg [51:0] mantissa_input_reg;
reg max_shift_exceeder_reg;
reg max_shift_reg;
reg [6:0] power2_value_reg;
reg sign_input_reg1;
reg sign_input_reg2;
reg sign_input_reg3;
reg sign_input_reg4;
wire [10:0] wire_add_sub4_result;
wire [6:0] wire_add_sub5_result;
wire wire_add_sub7_cout;
wire [31:0] wire_add_sub7_result;
wire wire_add_sub8_cout;
wire [15:0] wire_add_sub8_result;
wire [15:0] wire_add_sub9_result;
wire wire_cmpr1_aeb;
wire wire_cmpr1_agb;
wire wire_cmpr2_aeb;
wire wire_cmpr3_alb;
wire wire_max_shift_compare_agb;
wire aclr;
wire add_1_cout_w;
wire add_1_w;
wire [32:0] all_zeroes_w;
wire [83:0] barrel_mantissa_input;
wire [30:0] barrel_zero_padding_w;
wire below_limit_exceeders;
wire [32:0] below_limit_integer;
wire below_lower_limit1_w;
wire below_lower_limit2_w;
wire [10:0] bias_value_less_1_w;
wire [10:0] bias_value_w;
wire [10:0] const_bias_value_add_width_res_w;
wire denormal_input_w;
wire equal_upper_limit_w;
wire exceed_limit_exceeders;
wire [32:0] exceed_limit_integer;
wire exceed_upper_limit_w;
wire [10:0] exp_and;
wire exp_and_w;
wire [10:0] exp_bus;
wire [10:0] exp_or;
wire exp_or_w;
wire [10:0] exponent_input;
wire guard_bit_w;
wire [52:0] implied_mantissa_input;
wire infinity_input_w;
wire [32:0] infinity_value_w;
wire int_or1_w;
wire int_or2_w;
wire [32:0] integer_output;
wire [31:0] integer_post_round;
wire [31:0] integer_pre_round;
wire [32:0] integer_result;
wire [31:0] integer_rounded;
wire [31:0] integer_rounded_tmp;
wire [31:0] integer_tmp_output;
wire [15:0] inv_add_1_adder1_w;
wire [15:0] inv_add_1_adder2_w;
wire [31:0] inv_integer;
wire [83:0] lbarrel_shift_result_w;
wire [31:0] lbarrel_shift_w;
wire lower_limit_selector;
wire lowest_integer_selector;
wire [31:0] lowest_integer_value;
wire [25:0] man_bus1;
wire [25:0] man_bus2;
wire [25:0] man_or1;
wire man_or1_w;
wire [25:0] man_or2;
wire man_or2_w;
wire man_or_w;
wire [51:0] mantissa_input;
wire max_shift_reg_w;
wire [6:0] max_shift_w;
wire more_than_max_shift_w;
wire nan_input_w;
wire [32:0] neg_infi_w;
wire [10:0] padded_exponent_input;
wire [32:0] pos_infi_w;
wire [6:0] power2_value_w;
wire [32:0] result_w;
wire round_bit_w;
wire sign_input;
wire sign_input_w;
wire [31:0] signed_integer;
wire sticky_bit_w;
wire [50:0] sticky_bus;
wire [50:0] sticky_or;
wire [31:0] unsigned_integer;
wire upper_limit_w;
wire zero_input_w;
acl_fp_fptosi_double_altbarrel_shift_3tf altbarrel_shift6
(
.aclr(aclr),
.clk_en(clk_en),
.clock(clock),
.data(barrel_mantissa_input),
.distance(power2_value_reg),
.result(wire_altbarrel_shift6_result));
// synopsys translate_off
initial
added_power2_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) added_power2_reg <= 7'b0;
else if (clk_en == 1'b1) added_power2_reg <= wire_add_sub5_result;
// synopsys translate_off
initial
below_lower_limit1_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) below_lower_limit1_reg1 <= 1'b0;
else if (clk_en == 1'b1) below_lower_limit1_reg1 <= below_lower_limit1_w;
// synopsys translate_off
initial
below_lower_limit1_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) below_lower_limit1_reg2 <= 1'b0;
else if (clk_en == 1'b1) below_lower_limit1_reg2 <= below_lower_limit1_reg1;
// synopsys translate_off
initial
below_lower_limit1_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) below_lower_limit1_reg3 <= 1'b0;
else if (clk_en == 1'b1) below_lower_limit1_reg3 <= below_lower_limit1_reg2;
// synopsys translate_off
initial
below_lower_limit2_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) below_lower_limit2_reg1 <= 1'b0;
else if (clk_en == 1'b1) below_lower_limit2_reg1 <= below_lower_limit2_w;
// synopsys translate_off
initial
below_lower_limit2_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) below_lower_limit2_reg2 <= 1'b0;
else if (clk_en == 1'b1) below_lower_limit2_reg2 <= below_lower_limit2_reg1;
// synopsys translate_off
initial
below_lower_limit2_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) below_lower_limit2_reg3 <= 1'b0;
else if (clk_en == 1'b1) below_lower_limit2_reg3 <= below_lower_limit2_reg2;
// synopsys translate_off
initial
below_lower_limit2_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) below_lower_limit2_reg4 <= 1'b0;
else if (clk_en == 1'b1) below_lower_limit2_reg4 <= below_lower_limit2_reg3;
// synopsys translate_off
initial
dataa_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) dataa_reg <= 64'b0;
else if (clk_en == 1'b1) dataa_reg <= dataa;
// synopsys translate_off
initial
equal_upper_limit_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) equal_upper_limit_reg1 <= 1'b0;
else if (clk_en == 1'b1) equal_upper_limit_reg1 <= equal_upper_limit_w;
// synopsys translate_off
initial
equal_upper_limit_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) equal_upper_limit_reg2 <= 1'b0;
else if (clk_en == 1'b1) equal_upper_limit_reg2 <= equal_upper_limit_reg1;
// synopsys translate_off
initial
equal_upper_limit_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) equal_upper_limit_reg3 <= 1'b0;
else if (clk_en == 1'b1) equal_upper_limit_reg3 <= equal_upper_limit_reg2;
// synopsys translate_off
initial
exceed_upper_limit_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exceed_upper_limit_reg1 <= 1'b0;
else if (clk_en == 1'b1) exceed_upper_limit_reg1 <= exceed_upper_limit_w;
// synopsys translate_off
initial
exceed_upper_limit_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exceed_upper_limit_reg2 <= 1'b0;
else if (clk_en == 1'b1) exceed_upper_limit_reg2 <= exceed_upper_limit_reg1;
// synopsys translate_off
initial
exceed_upper_limit_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exceed_upper_limit_reg3 <= 1'b0;
else if (clk_en == 1'b1) exceed_upper_limit_reg3 <= exceed_upper_limit_reg2;
// synopsys translate_off
initial
exceed_upper_limit_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exceed_upper_limit_reg4 <= 1'b0;
else if (clk_en == 1'b1) exceed_upper_limit_reg4 <= upper_limit_w;
// synopsys translate_off
initial
exp_and_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_and_reg1 <= 1'b0;
else if (clk_en == 1'b1) exp_and_reg1 <= exp_and_w;
// synopsys translate_off
initial
exp_and_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_and_reg2 <= 1'b0;
else if (clk_en == 1'b1) exp_and_reg2 <= exp_and_reg1;
// synopsys translate_off
initial
exp_and_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_and_reg3 <= 1'b0;
else if (clk_en == 1'b1) exp_and_reg3 <= exp_and_reg2;
// synopsys translate_off
initial
exp_and_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_and_reg4 <= 1'b0;
else if (clk_en == 1'b1) exp_and_reg4 <= exp_and_reg3;
// synopsys translate_off
initial
exp_or_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_or_reg1 <= 1'b0;
else if (clk_en == 1'b1) exp_or_reg1 <= exp_or_w;
// synopsys translate_off
initial
exp_or_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_or_reg2 <= 1'b0;
else if (clk_en == 1'b1) exp_or_reg2 <= exp_or_reg1;
// synopsys translate_off
initial
exp_or_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_or_reg3 <= 1'b0;
else if (clk_en == 1'b1) exp_or_reg3 <= exp_or_reg2;
// synopsys translate_off
initial
exp_or_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_or_reg4 <= 1'b0;
else if (clk_en == 1'b1) exp_or_reg4 <= exp_or_reg3;
// synopsys translate_off
initial
int_or1_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) int_or1_reg1 <= 1'b0;
else if (clk_en == 1'b1) int_or1_reg1 <= int_or1_w;
// synopsys translate_off
initial
int_or2_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) int_or2_reg1 <= 1'b0;
else if (clk_en == 1'b1) int_or2_reg1 <= int_or2_w;
// synopsys translate_off
initial
int_or_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) int_or_reg2 <= 1'b0;
else if (clk_en == 1'b1) int_or_reg2 <= (int_or1_reg1 | int_or2_reg1);
// synopsys translate_off
initial
int_or_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) int_or_reg3 <= 1'b0;
else if (clk_en == 1'b1) int_or_reg3 <= int_or_reg2;
// synopsys translate_off
initial
integer_result_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) integer_result_reg <= 33'b0;
else if (clk_en == 1'b1) integer_result_reg <= integer_result;
// synopsys translate_off
initial
integer_rounded_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) integer_rounded_reg <= 32'b0;
else if (clk_en == 1'b1) integer_rounded_reg <= integer_rounded;
// synopsys translate_off
initial
lowest_int_sel_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lowest_int_sel_reg <= 1'b0;
else if (clk_en == 1'b1) lowest_int_sel_reg <= lowest_integer_selector;
// synopsys translate_off
initial
man_or1_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_or1_reg1 <= 1'b0;
else if (clk_en == 1'b1) man_or1_reg1 <= man_or1_w;
// synopsys translate_off
initial
man_or2_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_or2_reg1 <= 1'b0;
else if (clk_en == 1'b1) man_or2_reg1 <= man_or2_w;
// synopsys translate_off
initial
man_or_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_or_reg2 <= 1'b0;
else if (clk_en == 1'b1) man_or_reg2 <= man_or_w;
// synopsys translate_off
initial
man_or_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_or_reg3 <= 1'b0;
else if (clk_en == 1'b1) man_or_reg3 <= man_or_reg2;
// synopsys translate_off
initial
man_or_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_or_reg4 <= 1'b0;
else if (clk_en == 1'b1) man_or_reg4 <= man_or_reg3;
// synopsys translate_off
initial
mantissa_input_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) mantissa_input_reg <= 52'b0;
else if (clk_en == 1'b1) mantissa_input_reg <= mantissa_input;
// synopsys translate_off
initial
max_shift_exceeder_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) max_shift_exceeder_reg <= 1'b0;
else if (clk_en == 1'b1) max_shift_exceeder_reg <= more_than_max_shift_w;
// synopsys translate_off
initial
max_shift_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) max_shift_reg <= 1'b0;
else if (clk_en == 1'b1) max_shift_reg <= wire_max_shift_compare_agb;
// synopsys translate_off
initial
power2_value_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) power2_value_reg <= 7'b0;
else if (clk_en == 1'b1) power2_value_reg <= power2_value_w;
// synopsys translate_off
initial
sign_input_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_input_reg1 <= 1'b0;
else if (clk_en == 1'b1) sign_input_reg1 <= sign_input;
// synopsys translate_off
initial
sign_input_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_input_reg2 <= 1'b0;
else if (clk_en == 1'b1) sign_input_reg2 <= sign_input_reg1;
// synopsys translate_off
initial
sign_input_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_input_reg3 <= 1'b0;
else if (clk_en == 1'b1) sign_input_reg3 <= sign_input_reg2;
// synopsys translate_off
initial
sign_input_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_input_reg4 <= 1'b0;
else if (clk_en == 1'b1) sign_input_reg4 <= sign_input_reg3;
lpm_add_sub add_sub4
(
.cout(),
.dataa(exponent_input),
.datab(bias_value_w),
.overflow(),
.result(wire_add_sub4_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub4.lpm_direction = "SUB",
add_sub4.lpm_width = 11,
add_sub4.lpm_type = "lpm_add_sub",
add_sub4.lpm_hint = "ONE_INPUT_IS_CONSTANT=YES";
lpm_add_sub add_sub5
(
.cout(),
.dataa(power2_value_reg),
.datab(7'b0000001),
.overflow(),
.result(wire_add_sub5_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub5.lpm_direction = "ADD",
add_sub5.lpm_width = 7,
add_sub5.lpm_type = "lpm_add_sub",
add_sub5.lpm_hint = "ONE_INPUT_IS_CONSTANT=YES";
lpm_add_sub add_sub7
(
.cout(wire_add_sub7_cout),
.dataa(integer_pre_round),
.datab(32'b00000000000000000000000000000001),
.overflow(),
.result(wire_add_sub7_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub7.lpm_direction = "ADD",
add_sub7.lpm_width = 32,
add_sub7.lpm_type = "lpm_add_sub",
add_sub7.lpm_hint = "ONE_INPUT_IS_CONSTANT=YES";
lpm_add_sub add_sub8
(
.cout(wire_add_sub8_cout),
.dataa(inv_integer[15:0]),
.datab(16'b0000000000000001),
.overflow(),
.result(wire_add_sub8_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub8.lpm_direction = "ADD",
add_sub8.lpm_width = 16,
add_sub8.lpm_type = "lpm_add_sub",
add_sub8.lpm_hint = "ONE_INPUT_IS_CONSTANT=YES";
lpm_add_sub add_sub9
(
.cout(),
.dataa(inv_integer[31:16]),
.datab(16'b0000000000000001),
.overflow(),
.result(wire_add_sub9_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub9.lpm_direction = "ADD",
add_sub9.lpm_width = 16,
add_sub9.lpm_type = "lpm_add_sub",
add_sub9.lpm_hint = "ONE_INPUT_IS_CONSTANT=YES";
lpm_compare cmpr1
(
.aeb(wire_cmpr1_aeb),
.agb(wire_cmpr1_agb),
.ageb(),
.alb(),
.aleb(),
.aneb(),
.dataa(padded_exponent_input),
.datab(const_bias_value_add_width_res_w)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cmpr1.lpm_representation = "UNSIGNED",
cmpr1.lpm_width = 11,
cmpr1.lpm_type = "lpm_compare";
lpm_compare cmpr2
(
.aeb(wire_cmpr2_aeb),
.agb(),
.ageb(),
.alb(),
.aleb(),
.aneb(),
.dataa(exponent_input),
.datab(bias_value_less_1_w)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cmpr2.lpm_representation = "UNSIGNED",
cmpr2.lpm_width = 11,
cmpr2.lpm_type = "lpm_compare";
lpm_compare cmpr3
(
.aeb(),
.agb(),
.ageb(),
.alb(wire_cmpr3_alb),
.aleb(),
.aneb(),
.dataa(exponent_input),
.datab(bias_value_w)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cmpr3.lpm_representation = "UNSIGNED",
cmpr3.lpm_width = 11,
cmpr3.lpm_type = "lpm_compare";
lpm_compare max_shift_compare
(
.aeb(),
.agb(wire_max_shift_compare_agb),
.ageb(),
.alb(),
.aleb(),
.aneb(),
.dataa(added_power2_reg),
.datab(max_shift_w)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
max_shift_compare.lpm_representation = "UNSIGNED",
max_shift_compare.lpm_width = 7,
max_shift_compare.lpm_type = "lpm_compare";
assign
aclr = 1'b0,
add_1_cout_w = ((wire_add_sub7_cout & add_1_w) & (~ sign_input_reg3)),
add_1_w = ((((~ guard_bit_w) & round_bit_w) & sticky_bit_w) | (guard_bit_w & round_bit_w)),
all_zeroes_w = {1'b0, {32{1'b0}}},
barrel_mantissa_input = {barrel_zero_padding_w, implied_mantissa_input},
barrel_zero_padding_w = {31{1'b0}},
below_limit_exceeders = (((denormal_input_w | zero_input_w) | lower_limit_selector) | nan_input_w),
below_limit_integer = (({33{(~ below_limit_exceeders)}} & integer_output) | ({33{below_limit_exceeders}} & all_zeroes_w)),
below_lower_limit1_w = wire_cmpr2_aeb,
below_lower_limit2_w = wire_cmpr3_alb,
bias_value_less_1_w = 11'b01111111110,
bias_value_w = 11'b01111111111,
const_bias_value_add_width_res_w = 11'b10000011111,
denormal_input_w = ((~ exp_or_reg4) & man_or_reg4),
equal_upper_limit_w = wire_cmpr1_aeb,
exceed_limit_exceeders = (((infinity_input_w | max_shift_exceeder_reg) | exceed_upper_limit_reg4) & (~ nan_input_w)),
exceed_limit_integer = (({33{(~ exceed_limit_exceeders)}} & below_limit_integer) | ({33{exceed_limit_exceeders}} & infinity_value_w)),
exceed_upper_limit_w = wire_cmpr1_agb,
exp_and = {(exp_and[9] & exp_bus[10]), (exp_and[8] & exp_bus[9]), (exp_and[7] & exp_bus[8]), (exp_and[6] & exp_bus[7]), (exp_and[5] & exp_bus[6]), (exp_and[4] & exp_bus[5]), (exp_and[3] & exp_bus[4]), (exp_and[2] & exp_bus[3]), (exp_and[1] & exp_bus[2]), (exp_and[0] & exp_bus[1]), exp_bus[0]},
exp_and_w = exp_and[10],
exp_bus = exponent_input,
exp_or = {(exp_or[9] | exp_bus[10]), (exp_or[8] | exp_bus[9]), (exp_or[7] | exp_bus[8]), (exp_or[6] | exp_bus[7]), (exp_or[5] | exp_bus[6]), (exp_or[4] | exp_bus[5]), (exp_or[3] | exp_bus[4]), (exp_or[2] | exp_bus[3]), (exp_or[1] | exp_bus[2]), (exp_or[0] | exp_bus[1]), exp_bus[0]},
exp_or_w = exp_or[10],
exponent_input = dataa_reg[62:52],
guard_bit_w = wire_altbarrel_shift6_result[52],
implied_mantissa_input = {1'b1, mantissa_input_reg},
infinity_input_w = (exp_and_reg4 & (~ man_or_reg4)),
infinity_value_w = (({33{(~ sign_input_w)}} & pos_infi_w) | ({33{sign_input_w}} & neg_infi_w)),
int_or1_w = man_or2[0],
int_or2_w = man_or1[20],
integer_output = {sign_input_w, integer_tmp_output},
integer_post_round = wire_add_sub7_result,
integer_pre_round = lbarrel_shift_w,
integer_result = exceed_limit_integer,
integer_rounded = (({32{(~ lowest_integer_selector)}} & integer_rounded_tmp) | ({32{lowest_integer_selector}} & lowest_integer_value)),
integer_rounded_tmp = (({32{(~ add_1_w)}} & integer_pre_round) | ({32{add_1_w}} & integer_post_round)),
integer_tmp_output = (({32{(~ sign_input_w)}} & unsigned_integer) | ({32{sign_input_w}} & signed_integer)),
inv_add_1_adder1_w = wire_add_sub8_result,
inv_add_1_adder2_w = (({16{(~ wire_add_sub8_cout)}} & inv_integer[31:16]) | ({16{wire_add_sub8_cout}} & wire_add_sub9_result)),
inv_integer = (~ integer_rounded_reg),
lbarrel_shift_result_w = wire_altbarrel_shift6_result,
lbarrel_shift_w = lbarrel_shift_result_w[83:52],
lower_limit_selector = (((below_lower_limit2_reg4 & (~ zero_input_w)) & (~ denormal_input_w)) & (~ lowest_int_sel_reg)),
lowest_integer_selector = (below_lower_limit1_reg3 & man_or_reg3),
lowest_integer_value = {barrel_zero_padding_w, 1'b1},
man_bus1 = mantissa_input[25:0],
man_bus2 = mantissa_input[51:26],
man_or1 = {man_bus1[25], (man_or1[25] | man_bus1[24]), (man_or1[24] | man_bus1[23]), (man_or1[23] | man_bus1[22]), (man_or1[22] | man_bus1[21]), (man_or1[21] | man_bus1[20]), (man_or1[20] | man_bus1[19]), (man_or1[19] | man_bus1[18]), (man_or1[18] | man_bus1[17]), (man_or1[17] | man_bus1[16]), (man_or1[16] | man_bus1[15]), (man_or1[15] | man_bus1[14]), (man_or1[14] | man_bus1[13]), (man_or1[13] | man_bus1[12]), (man_or1[12] | man_bus1[11]), (man_or1[11] | man_bus1[10]), (man_or1[10] | man_bus1[9]), (man_or1[9] | man_bus1[8]), (man_or1[8] | man_bus1[7]), (man_or1[7] | man_bus1[6]), (man_or1[6] | man_bus1[5]), (man_or1[5] | man_bus1[4]), (man_or1[4] | man_bus1[3]), (man_or1[3] | man_bus1[2]), (man_or1[2] | man_bus1[1]), (man_or1[1] | man_bus1[0])},
man_or1_w = man_or1[0],
man_or2 = {man_bus2[25], (man_or2[25] | man_bus2[24]), (man_or2[24] | man_bus2[23]), (man_or2[23] | man_bus2[22]), (man_or2[22] | man_bus2[21]), (man_or2[21] | man_bus2[20]), (man_or2[20] | man_bus2[19]), (man_or2[19] | man_bus2[18]), (man_or2[18] | man_bus2[17]), (man_or2[17] | man_bus2[16]), (man_or2[16] | man_bus2[15]), (man_or2[15] | man_bus2[14]), (man_or2[14] | man_bus2[13]), (man_or2[13] | man_bus2[12]), (man_or2[12] | man_bus2[11]), (man_or2[11] | man_bus2[10]), (man_or2[10] | man_bus2[9]), (man_or2[9] | man_bus2[8]), (man_or2[8] | man_bus2[7]), (man_or2[7] | man_bus2[6]), (man_or2[6] | man_bus2[5]), (man_or2[5] | man_bus2[4]), (man_or2[4] | man_bus2[3]), (man_or2[3] | man_bus2[2]), (man_or2[2] | man_bus2[1]), (man_or2[1] | man_bus2[0])},
man_or2_w = man_or2[0],
man_or_w = (man_or1_reg1 | man_or2_reg1),
mantissa_input = dataa_reg[51:0],
max_shift_reg_w = max_shift_reg,
max_shift_w = 7'b0011111,
more_than_max_shift_w = ((max_shift_reg_w & add_1_cout_w) & (~ below_lower_limit2_reg3)),
nan_input_w = (exp_and_reg4 & man_or_reg4),
neg_infi_w = {1'b1, {32{1'b0}}},
padded_exponent_input = exponent_input,
pos_infi_w = {1'b0, {32{1'b1}}},
power2_value_w = wire_add_sub4_result[6:0],
result = result_w,
result_w = integer_result_reg,
round_bit_w = wire_altbarrel_shift6_result[51],
sign_input = dataa_reg[63],
sign_input_w = sign_input_reg4,
signed_integer = {inv_add_1_adder2_w, inv_add_1_adder1_w},
sticky_bit_w = sticky_or[50],
sticky_bus = wire_altbarrel_shift6_result[50:0],
sticky_or = {(sticky_or[49] | sticky_bus[50]), (sticky_or[48] | sticky_bus[49]), (sticky_or[47] | sticky_bus[48]), (sticky_or[46] | sticky_bus[47]), (sticky_or[45] | sticky_bus[46]), (sticky_or[44] | sticky_bus[45]), (sticky_or[43] | sticky_bus[44]), (sticky_or[42] | sticky_bus[43]), (sticky_or[41] | sticky_bus[42]), (sticky_or[40] | sticky_bus[41]), (sticky_or[39] | sticky_bus[40]), (sticky_or[38] | sticky_bus[39]), (sticky_or[37] | sticky_bus[38]), (sticky_or[36] | sticky_bus[37]), (sticky_or[35] | sticky_bus[36]), (sticky_or[34] | sticky_bus[35]), (sticky_or[33] | sticky_bus[34]), (sticky_or[32] | sticky_bus[33]), (sticky_or[31] | sticky_bus[32]), (sticky_or[30] | sticky_bus[31]), (sticky_or[29] | sticky_bus[30]), (sticky_or[28] | sticky_bus[29]), (sticky_or[27] | sticky_bus[28]), (sticky_or[26] | sticky_bus[27]), (sticky_or[25] | sticky_bus[26]), (sticky_or[24] | sticky_bus[25]), (sticky_or[23] | sticky_bus[24]), (sticky_or[22] | sticky_bus[23]), (sticky_or[21] | sticky_bus[22]), (sticky_or[20] | sticky_bus[21]), (sticky_or[19] | sticky_bus[20]), (sticky_or[18] | sticky_bus[19]), (sticky_or[17] | sticky_bus[18]), (sticky_or[16] | sticky_bus[17]), (sticky_or[15] | sticky_bus[16]), (sticky_or[14] | sticky_bus[15]), (sticky_or[13] | sticky_bus[14]), (sticky_or[12] | sticky_bus[13]), (sticky_or[11] | sticky_bus[12]), (sticky_or[10] | sticky_bus[11]), (sticky_or[9] | sticky_bus[10]), (sticky_or[8] | sticky_bus[9]), (sticky_or[7] | sticky_bus[8]), (sticky_or[6] | sticky_bus[7]), (sticky_or[5] | sticky_bus[6]), (sticky_or[4] | sticky_bus[5]), (sticky_or[3] | sticky_bus[4]), (sticky_or[2] | sticky_bus[3]), (sticky_or[1] | sticky_bus[2]), (sticky_or[0] | sticky_bus[1]), sticky_bus[0]},
unsigned_integer = integer_rounded_reg,
upper_limit_w = (((~ sign_input_reg3) & (exceed_upper_limit_reg3 | equal_upper_limit_reg3)) | (sign_input_reg3 & (exceed_upper_limit_reg3 | (equal_upper_limit_reg3 & (int_or_reg3 | add_1_w))))),
zero_input_w = ((~ exp_or_reg4) & (~ man_or_reg4));
endmodule //acl_fp_fptosi_double_altfp_convert_hkn
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acl_fp_fptosi_double (
enable,
clock,
dataa,
result);
input enable;
input clock;
input [63:0] dataa;
output [32:0] result;
wire [32:0] sub_wire0;
wire [32:0] result = sub_wire0[32:0];
acl_fp_fptosi_double_altfp_convert_hkn acl_fp_fptosi_double_altfp_convert_hkn_component (
.clk_en (enable),
.clock (clock),
.dataa (dataa),
.result (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altfp_convert"
// Retrieval info: CONSTANT: OPERATION STRING "FLOAT2INT"
// Retrieval info: CONSTANT: ROUNDING STRING "TO_NEAREST"
// Retrieval info: CONSTANT: WIDTH_DATA NUMERIC "64"
// Retrieval info: CONSTANT: WIDTH_EXP_INPUT NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_EXP_OUTPUT NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_INT NUMERIC "33"
// Retrieval info: CONSTANT: WIDTH_MAN_INPUT NUMERIC "52"
// Retrieval info: CONSTANT: WIDTH_MAN_OUTPUT NUMERIC "23"
// Retrieval info: CONSTANT: WIDTH_RESULT NUMERIC "33"
// Retrieval info: USED_PORT: clk_en 0 0 0 0 INPUT NODEFVAL "clk_en"
// Retrieval info: CONNECT: @clk_en 0 0 0 0 clk_en 0 0 0 0
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: USED_PORT: dataa 0 0 64 0 INPUT NODEFVAL "dataa[63..0]"
// Retrieval info: CONNECT: @dataa 0 0 64 0 dataa 0 0 64 0
// Retrieval info: USED_PORT: result 0 0 33 0 OUTPUT NODEFVAL "result[32..0]"
// Retrieval info: CONNECT: result 0 0 33 0 @result 0 0 33 0
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_fptosi_double.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_fptosi_double.qip TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_fptosi_double.bsf FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_fptosi_double_inst.v FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_fptosi_double_bb.v FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_fptosi_double.inc FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_fptosi_double.cmp FALSE TRUE
// Retrieval info: LIB_FILE: lpm
|
// -- (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Register Slice
// Generic single-channel AXI pipeline register on forward and/or reverse signal path
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// axic_sync_clock_converter
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_clock_converter_v2_1_axic_sync_clock_converter # (
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter C_FAMILY = "virtex6",
parameter integer C_PAYLOAD_WIDTH = 32,
parameter integer C_S_ACLK_RATIO = 1,
parameter integer C_M_ACLK_RATIO = 1 ,
parameter integer C_MODE = 0 // 0 = light-weight (1-deep); 1 = fully-pipelined (2-deep)
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire SAMPLE_CYCLE_EARLY,
input wire SAMPLE_CYCLE,
// Slave side
input wire S_ACLK,
input wire S_ARESETN,
input wire [C_PAYLOAD_WIDTH-1:0] S_PAYLOAD,
input wire S_VALID,
output wire S_READY,
// Master side
input wire M_ACLK,
input wire M_ARESETN,
output wire [C_PAYLOAD_WIDTH-1:0] M_PAYLOAD,
output wire M_VALID,
input wire M_READY
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam [1:0] ZERO = 2'b10;
localparam [1:0] ONE = 2'b11;
localparam [1:0] TWO = 2'b01;
localparam [1:0] INIT = 2'b00;
localparam integer P_LIGHT_WT = 0;
localparam integer P_FULLY_REG = 1;
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
generate
if (C_S_ACLK_RATIO == C_M_ACLK_RATIO) begin : gen_passthru
assign M_PAYLOAD = S_PAYLOAD;
assign M_VALID = S_VALID;
assign S_READY = M_READY;
end else begin : gen_sync_clock_converter
wire s_sample_cycle;
wire s_sample_cycle_early;
wire m_sample_cycle;
wire m_sample_cycle_early;
wire slow_aclk;
wire slow_areset;
wire s_areset_r;
wire m_areset_r;
reg s_tready_r;
wire s_tready_ns;
reg m_tvalid_r;
wire m_tvalid_ns;
reg [C_PAYLOAD_WIDTH-1:0] m_tpayload_r;
reg [C_PAYLOAD_WIDTH-1:0] m_tstorage_r;
wire [C_PAYLOAD_WIDTH-1:0] m_tpayload_ns;
wire [C_PAYLOAD_WIDTH-1:0] m_tstorage_ns;
reg m_tready_hold;
wire m_tready_sample;
wire load_tpayload;
wire load_tstorage;
wire load_tpayload_from_tstorage;
reg [1:0] state;
reg [1:0] next_state;
reg s_aresetn_r = 1'b0; // Reset delay register
always @(posedge S_ACLK) begin
if (~S_ARESETN | ~M_ARESETN) begin
s_aresetn_r <= 1'b0;
end else begin
s_aresetn_r <= S_ARESETN & M_ARESETN;
end
end
assign s_areset_r = ~s_aresetn_r;
reg m_aresetn_r = 1'b0; // Reset delay register
always @(posedge M_ACLK) begin
if (~S_ARESETN | ~M_ARESETN) begin
m_aresetn_r <= 1'b0;
end else begin
m_aresetn_r <= S_ARESETN & M_ARESETN;
end
end
assign m_areset_r = ~m_aresetn_r;
if (C_S_ACLK_RATIO > C_M_ACLK_RATIO) begin : gen_slowclk_mi
assign slow_aclk = M_ACLK;
end else begin : gen_slowclk_si
assign slow_aclk = S_ACLK;
end
assign slow_areset = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? m_areset_r : s_areset_r;
assign s_sample_cycle_early = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? SAMPLE_CYCLE_EARLY : 1'b1;
assign s_sample_cycle = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? SAMPLE_CYCLE : 1'b1;
assign m_sample_cycle_early = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? 1'b1 : SAMPLE_CYCLE_EARLY;
assign m_sample_cycle = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? 1'b1 : SAMPLE_CYCLE;
// Output flop for S_READY, value is encoded into state machine.
assign s_tready_ns = (C_S_ACLK_RATIO > C_M_ACLK_RATIO) ? state[1] & (state != INIT) : next_state[1];
always @(posedge S_ACLK) begin
if (s_areset_r) begin
s_tready_r <= 1'b0;
end
else begin
s_tready_r <= s_sample_cycle_early ? s_tready_ns : 1'b0;
end
end
assign S_READY = s_tready_r;
// Output flop for M_VALID
assign m_tvalid_ns = next_state[0];
always @(posedge M_ACLK) begin
if (m_areset_r) begin
m_tvalid_r <= 1'b0;
end
else begin
m_tvalid_r <= m_sample_cycle ? m_tvalid_ns : m_tvalid_r & ~M_READY;
end
end
assign M_VALID = m_tvalid_r;
// Hold register for M_READY when M_ACLK is fast.
always @(posedge M_ACLK) begin
if (m_areset_r) begin
m_tready_hold <= 1'b0;
end
else begin
m_tready_hold <= m_sample_cycle ? 1'b0 : m_tready_sample;
end
end
assign m_tready_sample = (M_READY ) | m_tready_hold;
// Output/storage flops for PAYLOAD
assign m_tpayload_ns = ~load_tpayload ? m_tpayload_r :
load_tpayload_from_tstorage ? m_tstorage_r :
S_PAYLOAD;
assign m_tstorage_ns = C_MODE ? (load_tstorage ? S_PAYLOAD : m_tstorage_r) : 0;
always @(posedge slow_aclk) begin
m_tpayload_r <= m_tpayload_ns;
m_tstorage_r <= C_MODE ? m_tstorage_ns : 0;
end
assign M_PAYLOAD = m_tpayload_r;
// load logic
assign load_tstorage = C_MODE && (state != TWO);
assign load_tpayload = m_tready_sample || (state == ZERO);
assign load_tpayload_from_tstorage = C_MODE && (state == TWO) && m_tready_sample;
// State machine
always @(posedge slow_aclk) begin
state <= next_state;
end
always @* begin
if (slow_areset) begin
next_state = INIT;
end else begin
case (state)
INIT: begin
next_state = ZERO;
end
// No transaction stored locally
ZERO: begin
if (S_VALID) begin
next_state = C_MODE ? ONE : TWO; // Push from empty
end
else begin
next_state = ZERO;
end
end
// One transaction stored locally
ONE: begin
if (C_MODE == 0) begin
next_state = TWO; // State ONE is inaccessible when C_MODE=0
end
else if (m_tready_sample & ~S_VALID) begin
next_state = ZERO; // Read out one so move to ZERO
end
else if (~m_tready_sample & S_VALID) begin
next_state = TWO; // Got another one so move to TWO
end
else begin
next_state = ONE;
end
end
// Storage registers full
TWO: begin
if (m_tready_sample) begin
next_state = C_MODE ? ONE : ZERO; // Pop from full
end
else begin
next_state = TWO;
end
end
endcase // case (state)
end
end
end // gen_sync_clock_converter
endgenerate
endmodule
`default_nettype wire
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: AxiLite Slave Conversion
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// axilite_conv
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_axilite_conv #
(
parameter C_FAMILY = "virtex6",
parameter integer C_AXI_ID_WIDTH = 1,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_WRITE = 1,
parameter integer C_AXI_SUPPORTS_READ = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1
)
(
// System Signals
input wire ACLK,
input wire ARESETN,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
input wire [3-1:0] S_AXI_AWPROT,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
// Slave Interface Write Data Ports
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output wire [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER, // Constant =0
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
input wire [3-1:0] S_AXI_ARPROT,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [2-1:0] S_AXI_RRESP,
output wire S_AXI_RLAST, // Constant =1
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER, // Constant =0
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
// Master Interface Write Address Port
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
output wire [3-1:0] M_AXI_AWPROT,
output wire M_AXI_AWVALID,
input wire M_AXI_AWREADY,
// Master Interface Write Data Ports
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY,
// Master Interface Write Response Ports
input wire [2-1:0] M_AXI_BRESP,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Master Interface Read Address Port
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
output wire [3-1:0] M_AXI_ARPROT,
output wire M_AXI_ARVALID,
input wire M_AXI_ARREADY,
// Master Interface Read Data Ports
input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY
);
wire s_awvalid_i;
wire s_arvalid_i;
wire [C_AXI_ADDR_WIDTH-1:0] m_axaddr;
// Arbiter
reg read_active;
reg write_active;
reg busy;
wire read_req;
wire write_req;
wire read_complete;
wire write_complete;
reg [1:0] areset_d; // Reset delay register
always @(posedge ACLK) begin
areset_d <= {areset_d[0], ~ARESETN};
end
assign s_awvalid_i = S_AXI_AWVALID & (C_AXI_SUPPORTS_WRITE != 0);
assign s_arvalid_i = S_AXI_ARVALID & (C_AXI_SUPPORTS_READ != 0);
assign read_req = s_arvalid_i & ~busy & ~|areset_d & ~write_active;
assign write_req = s_awvalid_i & ~busy & ~|areset_d & ((~read_active & ~s_arvalid_i) | write_active);
assign read_complete = M_AXI_RVALID & S_AXI_RREADY;
assign write_complete = M_AXI_BVALID & S_AXI_BREADY;
always @(posedge ACLK) begin : arbiter_read_ff
if (|areset_d)
read_active <= 1'b0;
else if (read_complete)
read_active <= 1'b0;
else if (read_req)
read_active <= 1'b1;
end
always @(posedge ACLK) begin : arbiter_write_ff
if (|areset_d)
write_active <= 1'b0;
else if (write_complete)
write_active <= 1'b0;
else if (write_req)
write_active <= 1'b1;
end
always @(posedge ACLK) begin : arbiter_busy_ff
if (|areset_d)
busy <= 1'b0;
else if (read_complete | write_complete)
busy <= 1'b0;
else if ((write_req & M_AXI_AWREADY) | (read_req & M_AXI_ARREADY))
busy <= 1'b1;
end
assign M_AXI_ARVALID = read_req;
assign S_AXI_ARREADY = M_AXI_ARREADY & read_req;
assign M_AXI_AWVALID = write_req;
assign S_AXI_AWREADY = M_AXI_AWREADY & write_req;
assign M_AXI_RREADY = S_AXI_RREADY & read_active;
assign S_AXI_RVALID = M_AXI_RVALID & read_active;
assign M_AXI_BREADY = S_AXI_BREADY & write_active;
assign S_AXI_BVALID = M_AXI_BVALID & write_active;
// Address multiplexer
assign m_axaddr = (read_req | (C_AXI_SUPPORTS_WRITE == 0)) ? S_AXI_ARADDR : S_AXI_AWADDR;
// Id multiplexer and flip-flop
reg [C_AXI_ID_WIDTH-1:0] s_axid;
always @(posedge ACLK) begin : axid
if (read_req) s_axid <= S_AXI_ARID;
else if (write_req) s_axid <= S_AXI_AWID;
end
assign S_AXI_BID = s_axid;
assign S_AXI_RID = s_axid;
assign M_AXI_AWADDR = m_axaddr;
assign M_AXI_ARADDR = m_axaddr;
// Feed-through signals
assign S_AXI_WREADY = M_AXI_WREADY & ~|areset_d;
assign S_AXI_BRESP = M_AXI_BRESP;
assign S_AXI_RDATA = M_AXI_RDATA;
assign S_AXI_RRESP = M_AXI_RRESP;
assign S_AXI_RLAST = 1'b1;
assign S_AXI_BUSER = {C_AXI_BUSER_WIDTH{1'b0}};
assign S_AXI_RUSER = {C_AXI_RUSER_WIDTH{1'b0}};
assign M_AXI_AWPROT = S_AXI_AWPROT;
assign M_AXI_WVALID = S_AXI_WVALID & ~|areset_d;
assign M_AXI_WDATA = S_AXI_WDATA;
assign M_AXI_WSTRB = S_AXI_WSTRB;
assign M_AXI_ARPROT = S_AXI_ARPROT;
endmodule
|
// -- (c) Copyright 2012 -2013 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: axi_protocol_converter.v
//
// Description:
// This module is a bank of AXI4-Lite and AXI3 protocol converters for a vectored AXI interface.
// The interface of this module consists of a vectored slave and master interface
// which are each concatenations of upper-level AXI pathways,
// plus various vectored parameters.
// This module instantiates a set of individual protocol converter modules.
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_axi_protocol_converter #(
parameter C_FAMILY = "virtex6",
parameter integer C_M_AXI_PROTOCOL = 0,
parameter integer C_S_AXI_PROTOCOL = 0,
parameter integer C_IGNORE_ID = 0,
// 0 = RID/BID are stored by axilite_conv.
// 1 = RID/BID have already been stored in an upstream device, like SASD crossbar.
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_WRITE = 1,
parameter integer C_AXI_SUPPORTS_READ = 1,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
// 1 = Propagate all USER signals, 0 = Dont propagate.
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_TRANSLATION_MODE = 1
// 0 (Unprotected) = Disable all error checking; master is well-behaved.
// 1 (Protection) = Detect SI transaction violations, but perform no splitting.
// AXI4 -> AXI3 must be <= 16 beats; AXI4/3 -> AXI4LITE must be single.
// 2 (Conversion) = Include transaction splitting logic
) (
// Global Signals
input wire aclk,
input wire aresetn,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input wire [((C_S_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,
input wire [3-1:0] s_axi_awsize,
input wire [2-1:0] s_axi_awburst,
input wire [((C_S_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,
input wire [4-1:0] s_axi_awcache,
input wire [3-1:0] s_axi_awprot,
input wire [4-1:0] s_axi_awregion,
input wire [4-1:0] s_axi_awqos,
input wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
input wire s_axi_awvalid,
output wire s_axi_awready,
// Slave Interface Write Data Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_wid,
input wire [C_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input wire s_axi_wlast,
input wire [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
input wire s_axi_wvalid,
output wire s_axi_wready,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output wire [2-1:0] s_axi_bresp,
output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
output wire s_axi_bvalid,
input wire s_axi_bready,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input wire [((C_S_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,
input wire [3-1:0] s_axi_arsize,
input wire [2-1:0] s_axi_arburst,
input wire [((C_S_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,
input wire [4-1:0] s_axi_arcache,
input wire [3-1:0] s_axi_arprot,
input wire [4-1:0] s_axi_arregion,
input wire [4-1:0] s_axi_arqos,
input wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
input wire s_axi_arvalid,
output wire s_axi_arready,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output wire [C_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output wire [2-1:0] s_axi_rresp,
output wire s_axi_rlast,
output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
output wire s_axi_rvalid,
input wire s_axi_rready,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [((C_M_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [((C_M_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
output wire m_axi_awvalid,
input wire m_axi_awready,
// Master Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
output wire m_axi_wvalid,
input wire m_axi_wready,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [2-1:0] m_axi_bresp,
input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
input wire m_axi_bvalid,
output wire m_axi_bready,
// Master Interface Read Address Port
output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [((C_M_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [((C_M_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
output wire m_axi_arvalid,
input wire m_axi_arready,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
input wire m_axi_rvalid,
output wire m_axi_rready
);
localparam P_AXI4 = 32'h0;
localparam P_AXI3 = 32'h1;
localparam P_AXILITE = 32'h2;
localparam P_AXILITE_SIZE = (C_AXI_DATA_WIDTH == 32) ? 3'b010 : 3'b011;
localparam P_INCR = 2'b01;
localparam P_DECERR = 2'b11;
localparam P_SLVERR = 2'b10;
localparam integer P_PROTECTION = 1;
localparam integer P_CONVERSION = 2;
wire s_awvalid_i;
wire s_arvalid_i;
wire s_wvalid_i ;
wire s_bready_i ;
wire s_rready_i ;
wire s_awready_i;
wire s_wready_i;
wire s_bvalid_i;
wire [C_AXI_ID_WIDTH-1:0] s_bid_i;
wire [1:0] s_bresp_i;
wire [C_AXI_BUSER_WIDTH-1:0] s_buser_i;
wire s_arready_i;
wire s_rvalid_i;
wire [C_AXI_ID_WIDTH-1:0] s_rid_i;
wire [1:0] s_rresp_i;
wire [C_AXI_RUSER_WIDTH-1:0] s_ruser_i;
wire [C_AXI_DATA_WIDTH-1:0] s_rdata_i;
wire s_rlast_i;
generate
if ((C_M_AXI_PROTOCOL == P_AXILITE) || (C_S_AXI_PROTOCOL == P_AXILITE)) begin : gen_axilite
assign m_axi_awid = 0;
assign m_axi_awlen = 0;
assign m_axi_awsize = P_AXILITE_SIZE;
assign m_axi_awburst = P_INCR;
assign m_axi_awlock = 0;
assign m_axi_awcache = 0;
assign m_axi_awregion = 0;
assign m_axi_awqos = 0;
assign m_axi_awuser = 0;
assign m_axi_wid = 0;
assign m_axi_wlast = 1'b1;
assign m_axi_wuser = 0;
assign m_axi_arid = 0;
assign m_axi_arlen = 0;
assign m_axi_arsize = P_AXILITE_SIZE;
assign m_axi_arburst = P_INCR;
assign m_axi_arlock = 0;
assign m_axi_arcache = 0;
assign m_axi_arregion = 0;
assign m_axi_arqos = 0;
assign m_axi_aruser = 0;
if (((C_IGNORE_ID == 1) && (C_TRANSLATION_MODE != P_CONVERSION)) || (C_S_AXI_PROTOCOL == P_AXILITE)) begin : gen_axilite_passthru
assign m_axi_awaddr = s_axi_awaddr;
assign m_axi_awprot = s_axi_awprot;
assign m_axi_awvalid = s_awvalid_i;
assign s_awready_i = m_axi_awready;
assign m_axi_wdata = s_axi_wdata;
assign m_axi_wstrb = s_axi_wstrb;
assign m_axi_wvalid = s_wvalid_i;
assign s_wready_i = m_axi_wready;
assign s_bid_i = 0;
assign s_bresp_i = m_axi_bresp;
assign s_buser_i = 0;
assign s_bvalid_i = m_axi_bvalid;
assign m_axi_bready = s_bready_i;
assign m_axi_araddr = s_axi_araddr;
assign m_axi_arprot = s_axi_arprot;
assign m_axi_arvalid = s_arvalid_i;
assign s_arready_i = m_axi_arready;
assign s_rid_i = 0;
assign s_rdata_i = m_axi_rdata;
assign s_rresp_i = m_axi_rresp;
assign s_rlast_i = 1'b1;
assign s_ruser_i = 0;
assign s_rvalid_i = m_axi_rvalid;
assign m_axi_rready = s_rready_i;
end else if (C_TRANSLATION_MODE == P_CONVERSION) begin : gen_b2s_conv
assign s_buser_i = {C_AXI_BUSER_WIDTH{1'b0}};
assign s_ruser_i = {C_AXI_RUSER_WIDTH{1'b0}};
axi_protocol_converter_v2_1_b2s #(
.C_S_AXI_PROTOCOL (C_S_AXI_PROTOCOL),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_SUPPORTS_WRITE (C_AXI_SUPPORTS_WRITE),
.C_AXI_SUPPORTS_READ (C_AXI_SUPPORTS_READ)
) axilite_b2s (
.aresetn (aresetn),
.aclk (aclk),
.s_axi_awid (s_axi_awid),
.s_axi_awaddr (s_axi_awaddr),
.s_axi_awlen (s_axi_awlen),
.s_axi_awsize (s_axi_awsize),
.s_axi_awburst (s_axi_awburst),
.s_axi_awprot (s_axi_awprot),
.s_axi_awvalid (s_awvalid_i),
.s_axi_awready (s_awready_i),
.s_axi_wdata (s_axi_wdata),
.s_axi_wstrb (s_axi_wstrb),
.s_axi_wlast (s_axi_wlast),
.s_axi_wvalid (s_wvalid_i),
.s_axi_wready (s_wready_i),
.s_axi_bid (s_bid_i),
.s_axi_bresp (s_bresp_i),
.s_axi_bvalid (s_bvalid_i),
.s_axi_bready (s_bready_i),
.s_axi_arid (s_axi_arid),
.s_axi_araddr (s_axi_araddr),
.s_axi_arlen (s_axi_arlen),
.s_axi_arsize (s_axi_arsize),
.s_axi_arburst (s_axi_arburst),
.s_axi_arprot (s_axi_arprot),
.s_axi_arvalid (s_arvalid_i),
.s_axi_arready (s_arready_i),
.s_axi_rid (s_rid_i),
.s_axi_rdata (s_rdata_i),
.s_axi_rresp (s_rresp_i),
.s_axi_rlast (s_rlast_i),
.s_axi_rvalid (s_rvalid_i),
.s_axi_rready (s_rready_i),
.m_axi_awaddr (m_axi_awaddr),
.m_axi_awprot (m_axi_awprot),
.m_axi_awvalid (m_axi_awvalid),
.m_axi_awready (m_axi_awready),
.m_axi_wdata (m_axi_wdata),
.m_axi_wstrb (m_axi_wstrb),
.m_axi_wvalid (m_axi_wvalid),
.m_axi_wready (m_axi_wready),
.m_axi_bresp (m_axi_bresp),
.m_axi_bvalid (m_axi_bvalid),
.m_axi_bready (m_axi_bready),
.m_axi_araddr (m_axi_araddr),
.m_axi_arprot (m_axi_arprot),
.m_axi_arvalid (m_axi_arvalid),
.m_axi_arready (m_axi_arready),
.m_axi_rdata (m_axi_rdata),
.m_axi_rresp (m_axi_rresp),
.m_axi_rvalid (m_axi_rvalid),
.m_axi_rready (m_axi_rready)
);
end else begin : gen_axilite_conv
axi_protocol_converter_v2_1_axilite_conv #(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_SUPPORTS_WRITE (C_AXI_SUPPORTS_WRITE),
.C_AXI_SUPPORTS_READ (C_AXI_SUPPORTS_READ),
.C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH)
) axilite_conv_inst (
.ARESETN (aresetn),
.ACLK (aclk),
.S_AXI_AWID (s_axi_awid),
.S_AXI_AWADDR (s_axi_awaddr),
.S_AXI_AWPROT (s_axi_awprot),
.S_AXI_AWVALID (s_awvalid_i),
.S_AXI_AWREADY (s_awready_i),
.S_AXI_WDATA (s_axi_wdata),
.S_AXI_WSTRB (s_axi_wstrb),
.S_AXI_WVALID (s_wvalid_i),
.S_AXI_WREADY (s_wready_i),
.S_AXI_BID (s_bid_i),
.S_AXI_BRESP (s_bresp_i),
.S_AXI_BUSER (s_buser_i),
.S_AXI_BVALID (s_bvalid_i),
.S_AXI_BREADY (s_bready_i),
.S_AXI_ARID (s_axi_arid),
.S_AXI_ARADDR (s_axi_araddr),
.S_AXI_ARPROT (s_axi_arprot),
.S_AXI_ARVALID (s_arvalid_i),
.S_AXI_ARREADY (s_arready_i),
.S_AXI_RID (s_rid_i),
.S_AXI_RDATA (s_rdata_i),
.S_AXI_RRESP (s_rresp_i),
.S_AXI_RLAST (s_rlast_i),
.S_AXI_RUSER (s_ruser_i),
.S_AXI_RVALID (s_rvalid_i),
.S_AXI_RREADY (s_rready_i),
.M_AXI_AWADDR (m_axi_awaddr),
.M_AXI_AWPROT (m_axi_awprot),
.M_AXI_AWVALID (m_axi_awvalid),
.M_AXI_AWREADY (m_axi_awready),
.M_AXI_WDATA (m_axi_wdata),
.M_AXI_WSTRB (m_axi_wstrb),
.M_AXI_WVALID (m_axi_wvalid),
.M_AXI_WREADY (m_axi_wready),
.M_AXI_BRESP (m_axi_bresp),
.M_AXI_BVALID (m_axi_bvalid),
.M_AXI_BREADY (m_axi_bready),
.M_AXI_ARADDR (m_axi_araddr),
.M_AXI_ARPROT (m_axi_arprot),
.M_AXI_ARVALID (m_axi_arvalid),
.M_AXI_ARREADY (m_axi_arready),
.M_AXI_RDATA (m_axi_rdata),
.M_AXI_RRESP (m_axi_rresp),
.M_AXI_RVALID (m_axi_rvalid),
.M_AXI_RREADY (m_axi_rready)
);
end
end else if ((C_M_AXI_PROTOCOL == P_AXI3) && (C_S_AXI_PROTOCOL == P_AXI4)) begin : gen_axi4_axi3
axi_protocol_converter_v2_1_axi3_conv #(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS),
.C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),
.C_AXI_ARUSER_WIDTH (C_AXI_ARUSER_WIDTH),
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH),
.C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_AXI_SUPPORTS_WRITE (C_AXI_SUPPORTS_WRITE),
.C_AXI_SUPPORTS_READ (C_AXI_SUPPORTS_READ),
.C_SUPPORT_SPLITTING ((C_TRANSLATION_MODE == P_CONVERSION) ? 1 : 0)
) axi3_conv_inst (
.ARESETN (aresetn),
.ACLK (aclk),
.S_AXI_AWID (s_axi_awid),
.S_AXI_AWADDR (s_axi_awaddr),
.S_AXI_AWLEN (s_axi_awlen),
.S_AXI_AWSIZE (s_axi_awsize),
.S_AXI_AWBURST (s_axi_awburst),
.S_AXI_AWLOCK (s_axi_awlock),
.S_AXI_AWCACHE (s_axi_awcache),
.S_AXI_AWPROT (s_axi_awprot),
.S_AXI_AWQOS (s_axi_awqos),
.S_AXI_AWUSER (s_axi_awuser),
.S_AXI_AWVALID (s_awvalid_i),
.S_AXI_AWREADY (s_awready_i),
.S_AXI_WDATA (s_axi_wdata),
.S_AXI_WSTRB (s_axi_wstrb),
.S_AXI_WLAST (s_axi_wlast),
.S_AXI_WUSER (s_axi_wuser),
.S_AXI_WVALID (s_wvalid_i),
.S_AXI_WREADY (s_wready_i),
.S_AXI_BID (s_bid_i),
.S_AXI_BRESP (s_bresp_i),
.S_AXI_BUSER (s_buser_i),
.S_AXI_BVALID (s_bvalid_i),
.S_AXI_BREADY (s_bready_i),
.S_AXI_ARID (s_axi_arid),
.S_AXI_ARADDR (s_axi_araddr),
.S_AXI_ARLEN (s_axi_arlen),
.S_AXI_ARSIZE (s_axi_arsize),
.S_AXI_ARBURST (s_axi_arburst),
.S_AXI_ARLOCK (s_axi_arlock),
.S_AXI_ARCACHE (s_axi_arcache),
.S_AXI_ARPROT (s_axi_arprot),
.S_AXI_ARQOS (s_axi_arqos),
.S_AXI_ARUSER (s_axi_aruser),
.S_AXI_ARVALID (s_arvalid_i),
.S_AXI_ARREADY (s_arready_i),
.S_AXI_RID (s_rid_i),
.S_AXI_RDATA (s_rdata_i),
.S_AXI_RRESP (s_rresp_i),
.S_AXI_RLAST (s_rlast_i),
.S_AXI_RUSER (s_ruser_i),
.S_AXI_RVALID (s_rvalid_i),
.S_AXI_RREADY (s_rready_i),
.M_AXI_AWID (m_axi_awid),
.M_AXI_AWADDR (m_axi_awaddr),
.M_AXI_AWLEN (m_axi_awlen),
.M_AXI_AWSIZE (m_axi_awsize),
.M_AXI_AWBURST (m_axi_awburst),
.M_AXI_AWLOCK (m_axi_awlock),
.M_AXI_AWCACHE (m_axi_awcache),
.M_AXI_AWPROT (m_axi_awprot),
.M_AXI_AWQOS (m_axi_awqos),
.M_AXI_AWUSER (m_axi_awuser),
.M_AXI_AWVALID (m_axi_awvalid),
.M_AXI_AWREADY (m_axi_awready),
.M_AXI_WID (m_axi_wid),
.M_AXI_WDATA (m_axi_wdata),
.M_AXI_WSTRB (m_axi_wstrb),
.M_AXI_WLAST (m_axi_wlast),
.M_AXI_WUSER (m_axi_wuser),
.M_AXI_WVALID (m_axi_wvalid),
.M_AXI_WREADY (m_axi_wready),
.M_AXI_BID (m_axi_bid),
.M_AXI_BRESP (m_axi_bresp),
.M_AXI_BUSER (m_axi_buser),
.M_AXI_BVALID (m_axi_bvalid),
.M_AXI_BREADY (m_axi_bready),
.M_AXI_ARID (m_axi_arid),
.M_AXI_ARADDR (m_axi_araddr),
.M_AXI_ARLEN (m_axi_arlen),
.M_AXI_ARSIZE (m_axi_arsize),
.M_AXI_ARBURST (m_axi_arburst),
.M_AXI_ARLOCK (m_axi_arlock),
.M_AXI_ARCACHE (m_axi_arcache),
.M_AXI_ARPROT (m_axi_arprot),
.M_AXI_ARQOS (m_axi_arqos),
.M_AXI_ARUSER (m_axi_aruser),
.M_AXI_ARVALID (m_axi_arvalid),
.M_AXI_ARREADY (m_axi_arready),
.M_AXI_RID (m_axi_rid),
.M_AXI_RDATA (m_axi_rdata),
.M_AXI_RRESP (m_axi_rresp),
.M_AXI_RLAST (m_axi_rlast),
.M_AXI_RUSER (m_axi_ruser),
.M_AXI_RVALID (m_axi_rvalid),
.M_AXI_RREADY (m_axi_rready)
);
assign m_axi_awregion = 0;
assign m_axi_arregion = 0;
end else if ((C_S_AXI_PROTOCOL == P_AXI3) && (C_M_AXI_PROTOCOL == P_AXI4)) begin : gen_axi3_axi4
assign m_axi_awid = s_axi_awid;
assign m_axi_awaddr = s_axi_awaddr;
assign m_axi_awlen = {4'h0, s_axi_awlen[3:0]};
assign m_axi_awsize = s_axi_awsize;
assign m_axi_awburst = s_axi_awburst;
assign m_axi_awlock = s_axi_awlock[0];
assign m_axi_awcache = s_axi_awcache;
assign m_axi_awprot = s_axi_awprot;
assign m_axi_awregion = 4'h0;
assign m_axi_awqos = s_axi_awqos;
assign m_axi_awuser = s_axi_awuser;
assign m_axi_awvalid = s_awvalid_i;
assign s_awready_i = m_axi_awready;
assign m_axi_wid = {C_AXI_ID_WIDTH{1'b0}} ;
assign m_axi_wdata = s_axi_wdata;
assign m_axi_wstrb = s_axi_wstrb;
assign m_axi_wlast = s_axi_wlast;
assign m_axi_wuser = s_axi_wuser;
assign m_axi_wvalid = s_wvalid_i;
assign s_wready_i = m_axi_wready;
assign s_bid_i = m_axi_bid;
assign s_bresp_i = m_axi_bresp;
assign s_buser_i = m_axi_buser;
assign s_bvalid_i = m_axi_bvalid;
assign m_axi_bready = s_bready_i;
assign m_axi_arid = s_axi_arid;
assign m_axi_araddr = s_axi_araddr;
assign m_axi_arlen = {4'h0, s_axi_arlen[3:0]};
assign m_axi_arsize = s_axi_arsize;
assign m_axi_arburst = s_axi_arburst;
assign m_axi_arlock = s_axi_arlock[0];
assign m_axi_arcache = s_axi_arcache;
assign m_axi_arprot = s_axi_arprot;
assign m_axi_arregion = 4'h0;
assign m_axi_arqos = s_axi_arqos;
assign m_axi_aruser = s_axi_aruser;
assign m_axi_arvalid = s_arvalid_i;
assign s_arready_i = m_axi_arready;
assign s_rid_i = m_axi_rid;
assign s_rdata_i = m_axi_rdata;
assign s_rresp_i = m_axi_rresp;
assign s_rlast_i = m_axi_rlast;
assign s_ruser_i = m_axi_ruser;
assign s_rvalid_i = m_axi_rvalid;
assign m_axi_rready = s_rready_i;
end else begin :gen_no_conv
assign m_axi_awid = s_axi_awid;
assign m_axi_awaddr = s_axi_awaddr;
assign m_axi_awlen = s_axi_awlen;
assign m_axi_awsize = s_axi_awsize;
assign m_axi_awburst = s_axi_awburst;
assign m_axi_awlock = s_axi_awlock;
assign m_axi_awcache = s_axi_awcache;
assign m_axi_awprot = s_axi_awprot;
assign m_axi_awregion = s_axi_awregion;
assign m_axi_awqos = s_axi_awqos;
assign m_axi_awuser = s_axi_awuser;
assign m_axi_awvalid = s_awvalid_i;
assign s_awready_i = m_axi_awready;
assign m_axi_wid = s_axi_wid;
assign m_axi_wdata = s_axi_wdata;
assign m_axi_wstrb = s_axi_wstrb;
assign m_axi_wlast = s_axi_wlast;
assign m_axi_wuser = s_axi_wuser;
assign m_axi_wvalid = s_wvalid_i;
assign s_wready_i = m_axi_wready;
assign s_bid_i = m_axi_bid;
assign s_bresp_i = m_axi_bresp;
assign s_buser_i = m_axi_buser;
assign s_bvalid_i = m_axi_bvalid;
assign m_axi_bready = s_bready_i;
assign m_axi_arid = s_axi_arid;
assign m_axi_araddr = s_axi_araddr;
assign m_axi_arlen = s_axi_arlen;
assign m_axi_arsize = s_axi_arsize;
assign m_axi_arburst = s_axi_arburst;
assign m_axi_arlock = s_axi_arlock;
assign m_axi_arcache = s_axi_arcache;
assign m_axi_arprot = s_axi_arprot;
assign m_axi_arregion = s_axi_arregion;
assign m_axi_arqos = s_axi_arqos;
assign m_axi_aruser = s_axi_aruser;
assign m_axi_arvalid = s_arvalid_i;
assign s_arready_i = m_axi_arready;
assign s_rid_i = m_axi_rid;
assign s_rdata_i = m_axi_rdata;
assign s_rresp_i = m_axi_rresp;
assign s_rlast_i = m_axi_rlast;
assign s_ruser_i = m_axi_ruser;
assign s_rvalid_i = m_axi_rvalid;
assign m_axi_rready = s_rready_i;
end
if ((C_TRANSLATION_MODE == P_PROTECTION) &&
(((C_S_AXI_PROTOCOL != P_AXILITE) && (C_M_AXI_PROTOCOL == P_AXILITE)) ||
((C_S_AXI_PROTOCOL == P_AXI4) && (C_M_AXI_PROTOCOL == P_AXI3)))) begin : gen_err_detect
wire e_awvalid;
reg e_awvalid_r;
wire e_arvalid;
reg e_arvalid_r;
wire e_wvalid;
wire e_bvalid;
wire e_rvalid;
reg e_awready;
reg e_arready;
wire e_wready;
reg [C_AXI_ID_WIDTH-1:0] e_awid;
reg [C_AXI_ID_WIDTH-1:0] e_arid;
reg [8-1:0] e_arlen;
wire [C_AXI_ID_WIDTH-1:0] e_bid;
wire [C_AXI_ID_WIDTH-1:0] e_rid;
wire e_rlast;
wire w_err;
wire r_err;
wire busy_aw;
wire busy_w;
wire busy_ar;
wire aw_push;
wire aw_pop;
wire w_pop;
wire ar_push;
wire ar_pop;
reg s_awvalid_pending;
reg s_awvalid_en;
reg s_arvalid_en;
reg s_awready_en;
reg s_arready_en;
reg [4:0] aw_cnt;
reg [4:0] ar_cnt;
reg [4:0] w_cnt;
reg w_borrow;
reg err_busy_w;
reg err_busy_r;
assign w_err = (C_M_AXI_PROTOCOL == P_AXILITE) ? (s_axi_awlen != 0) : ((s_axi_awlen>>4) != 0);
assign r_err = (C_M_AXI_PROTOCOL == P_AXILITE) ? (s_axi_arlen != 0) : ((s_axi_arlen>>4) != 0);
assign s_awvalid_i = s_axi_awvalid & s_awvalid_en & ~w_err;
assign e_awvalid = e_awvalid_r & ~busy_aw & ~busy_w;
assign s_arvalid_i = s_axi_arvalid & s_arvalid_en & ~r_err;
assign e_arvalid = e_arvalid_r & ~busy_ar ;
assign s_wvalid_i = s_axi_wvalid & (busy_w | (s_awvalid_pending & ~w_borrow));
assign e_wvalid = s_axi_wvalid & err_busy_w;
assign s_bready_i = s_axi_bready & busy_aw;
assign s_rready_i = s_axi_rready & busy_ar;
assign s_axi_awready = (s_awready_i & s_awready_en) | e_awready;
assign s_axi_wready = (s_wready_i & (busy_w | (s_awvalid_pending & ~w_borrow))) | e_wready;
assign s_axi_bvalid = (s_bvalid_i & busy_aw) | e_bvalid;
assign s_axi_bid = err_busy_w ? e_bid : s_bid_i;
assign s_axi_bresp = err_busy_w ? P_SLVERR : s_bresp_i;
assign s_axi_buser = err_busy_w ? {C_AXI_BUSER_WIDTH{1'b0}} : s_buser_i;
assign s_axi_arready = (s_arready_i & s_arready_en) | e_arready;
assign s_axi_rvalid = (s_rvalid_i & busy_ar) | e_rvalid;
assign s_axi_rid = err_busy_r ? e_rid : s_rid_i;
assign s_axi_rresp = err_busy_r ? P_SLVERR : s_rresp_i;
assign s_axi_ruser = err_busy_r ? {C_AXI_RUSER_WIDTH{1'b0}} : s_ruser_i;
assign s_axi_rdata = err_busy_r ? {C_AXI_DATA_WIDTH{1'b0}} : s_rdata_i;
assign s_axi_rlast = err_busy_r ? e_rlast : s_rlast_i;
assign busy_aw = (aw_cnt != 0);
assign busy_w = (w_cnt != 0);
assign busy_ar = (ar_cnt != 0);
assign aw_push = s_awvalid_i & s_awready_i & s_awready_en;
assign aw_pop = s_bvalid_i & s_bready_i;
assign w_pop = s_wvalid_i & s_wready_i & s_axi_wlast;
assign ar_push = s_arvalid_i & s_arready_i & s_arready_en;
assign ar_pop = s_rvalid_i & s_rready_i & s_rlast_i;
always @(posedge aclk) begin
if (~aresetn) begin
s_awvalid_en <= 1'b0;
s_arvalid_en <= 1'b0;
s_awready_en <= 1'b0;
s_arready_en <= 1'b0;
e_awvalid_r <= 1'b0;
e_arvalid_r <= 1'b0;
e_awready <= 1'b0;
e_arready <= 1'b0;
aw_cnt <= 0;
w_cnt <= 0;
ar_cnt <= 0;
err_busy_w <= 1'b0;
err_busy_r <= 1'b0;
w_borrow <= 1'b0;
s_awvalid_pending <= 1'b0;
end else begin
e_awready <= 1'b0; // One-cycle pulse
if (e_bvalid & s_axi_bready) begin
s_awvalid_en <= 1'b1;
s_awready_en <= 1'b1;
err_busy_w <= 1'b0;
end else if (e_awvalid) begin
e_awvalid_r <= 1'b0;
err_busy_w <= 1'b1;
end else if (s_axi_awvalid & w_err & ~e_awvalid_r & ~err_busy_w) begin
e_awvalid_r <= 1'b1;
e_awready <= ~(s_awready_i & s_awvalid_en); // 1-cycle pulse if awready not already asserted
s_awvalid_en <= 1'b0;
s_awready_en <= 1'b0;
end else if ((&aw_cnt) | (&w_cnt) | aw_push) begin
s_awvalid_en <= 1'b0;
s_awready_en <= 1'b0;
end else if (~err_busy_w & ~e_awvalid_r & ~(s_axi_awvalid & w_err)) begin
s_awvalid_en <= 1'b1;
s_awready_en <= 1'b1;
end
if (aw_push & ~aw_pop) begin
aw_cnt <= aw_cnt + 1;
end else if (~aw_push & aw_pop & (|aw_cnt)) begin
aw_cnt <= aw_cnt - 1;
end
if (aw_push) begin
if (~w_pop & ~w_borrow) begin
w_cnt <= w_cnt + 1;
end
w_borrow <= 1'b0;
end else if (~aw_push & w_pop) begin
if (|w_cnt) begin
w_cnt <= w_cnt - 1;
end else begin
w_borrow <= 1'b1;
end
end
s_awvalid_pending <= s_awvalid_i & ~s_awready_i;
e_arready <= 1'b0; // One-cycle pulse
if (e_rvalid & s_axi_rready & e_rlast) begin
s_arvalid_en <= 1'b1;
s_arready_en <= 1'b1;
err_busy_r <= 1'b0;
end else if (e_arvalid) begin
e_arvalid_r <= 1'b0;
err_busy_r <= 1'b1;
end else if (s_axi_arvalid & r_err & ~e_arvalid_r & ~err_busy_r) begin
e_arvalid_r <= 1'b1;
e_arready <= ~(s_arready_i & s_arvalid_en); // 1-cycle pulse if arready not already asserted
s_arvalid_en <= 1'b0;
s_arready_en <= 1'b0;
end else if ((&ar_cnt) | ar_push) begin
s_arvalid_en <= 1'b0;
s_arready_en <= 1'b0;
end else if (~err_busy_r & ~e_arvalid_r & ~(s_axi_arvalid & r_err)) begin
s_arvalid_en <= 1'b1;
s_arready_en <= 1'b1;
end
if (ar_push & ~ar_pop) begin
ar_cnt <= ar_cnt + 1;
end else if (~ar_push & ar_pop & (|ar_cnt)) begin
ar_cnt <= ar_cnt - 1;
end
end
end
always @(posedge aclk) begin
if (s_axi_awvalid & ~err_busy_w & ~e_awvalid_r ) begin
e_awid <= s_axi_awid;
end
if (s_axi_arvalid & ~err_busy_r & ~e_arvalid_r ) begin
e_arid <= s_axi_arid;
e_arlen <= s_axi_arlen;
end
end
axi_protocol_converter_v2_1_decerr_slave #
(
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_AXI_PROTOCOL (C_S_AXI_PROTOCOL),
.C_RESP (P_SLVERR),
.C_IGNORE_ID (C_IGNORE_ID)
)
decerr_slave_inst
(
.ACLK (aclk),
.ARESETN (aresetn),
.S_AXI_AWID (e_awid),
.S_AXI_AWVALID (e_awvalid),
.S_AXI_AWREADY (),
.S_AXI_WLAST (s_axi_wlast),
.S_AXI_WVALID (e_wvalid),
.S_AXI_WREADY (e_wready),
.S_AXI_BID (e_bid),
.S_AXI_BRESP (),
.S_AXI_BUSER (),
.S_AXI_BVALID (e_bvalid),
.S_AXI_BREADY (s_axi_bready),
.S_AXI_ARID (e_arid),
.S_AXI_ARLEN (e_arlen),
.S_AXI_ARVALID (e_arvalid),
.S_AXI_ARREADY (),
.S_AXI_RID (e_rid),
.S_AXI_RDATA (),
.S_AXI_RRESP (),
.S_AXI_RUSER (),
.S_AXI_RLAST (e_rlast),
.S_AXI_RVALID (e_rvalid),
.S_AXI_RREADY (s_axi_rready)
);
end else begin : gen_no_err_detect
assign s_awvalid_i = s_axi_awvalid;
assign s_arvalid_i = s_axi_arvalid;
assign s_wvalid_i = s_axi_wvalid;
assign s_bready_i = s_axi_bready;
assign s_rready_i = s_axi_rready;
assign s_axi_awready = s_awready_i;
assign s_axi_wready = s_wready_i;
assign s_axi_bvalid = s_bvalid_i;
assign s_axi_bid = s_bid_i;
assign s_axi_bresp = s_bresp_i;
assign s_axi_buser = s_buser_i;
assign s_axi_arready = s_arready_i;
assign s_axi_rvalid = s_rvalid_i;
assign s_axi_rid = s_rid_i;
assign s_axi_rresp = s_rresp_i;
assign s_axi_ruser = s_ruser_i;
assign s_axi_rdata = s_rdata_i;
assign s_axi_rlast = s_rlast_i;
end // gen_err_detect
endgenerate
endmodule
`default_nettype wire
|
//////////////////////////////////////////////////////////////////
// //
// Register Bank for Amber Core //
// //
// This file is part of the Amber project //
// http://www.opencores.org/project,amber //
// //
// Description //
// Contains 37 32-bit registers, 16 of which are visible //
// ina any one operating mode. Registers use real flipflops, //
// rather than SRAM. This makes sense for an FPGA //
// implementation, where flipflops are plentiful. //
// //
// Author(s): //
// - Conor Santifort, [email protected] //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2010 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
module a23_register_bank (
input i_clk,
input i_fetch_stall,
input [1:0] i_mode_idec, // user, supervisor, irq_idec, firq_idec etc.
// Used for register writes
input [1:0] i_mode_exec, // 1 periods delayed from i_mode_idec
// Used for register reads
input [3:0] i_mode_rds_exec, // Use one-hot version specifically for rds,
// includes i_user_mode_regs_store
input i_user_mode_regs_load,
input i_firq_not_user_mode,
input [3:0] i_rm_sel,
input [3:0] i_rds_sel,
input [3:0] i_rn_sel,
input i_pc_wen,
input [14:0] i_reg_bank_wen,
input [23:0] i_pc, // program counter [25:2]
input [31:0] i_reg,
input [3:0] i_status_bits_flags,
input i_status_bits_irq_mask,
input i_status_bits_firq_mask,
output [31:0] o_rm,
output reg [31:0] o_rs,
output reg [31:0] o_rd,
output [31:0] o_rn,
output [31:0] o_pc
);
`include "a23_localparams.v"
`include "a23_functions.v"
// User Mode Registers
reg [31:0] r0 = 32'hdead_beef;
reg [31:0] r1 = 32'hdead_beef;
reg [31:0] r2 = 32'hdead_beef;
reg [31:0] r3 = 32'hdead_beef;
reg [31:0] r4 = 32'hdead_beef;
reg [31:0] r5 = 32'hdead_beef;
reg [31:0] r6 = 32'hdead_beef;
reg [31:0] r7 = 32'hdead_beef;
reg [31:0] r8 = 32'hdead_beef;
reg [31:0] r9 = 32'hdead_beef;
reg [31:0] r10 = 32'hdead_beef;
reg [31:0] r11 = 32'hdead_beef;
reg [31:0] r12 = 32'hdead_beef;
reg [31:0] r13 = 32'hdead_beef;
reg [31:0] r14 = 32'hdead_beef;
reg [23:0] r15 = 24'hc0_ffee;
wire [31:0] r0_out;
wire [31:0] r1_out;
wire [31:0] r2_out;
wire [31:0] r3_out;
wire [31:0] r4_out;
wire [31:0] r5_out;
wire [31:0] r6_out;
wire [31:0] r7_out;
wire [31:0] r8_out;
wire [31:0] r9_out;
wire [31:0] r10_out;
wire [31:0] r11_out;
wire [31:0] r12_out;
wire [31:0] r13_out;
wire [31:0] r14_out;
wire [31:0] r15_out_rm;
wire [31:0] r15_out_rm_nxt;
wire [31:0] r15_out_rn;
wire [31:0] r8_rds;
wire [31:0] r9_rds;
wire [31:0] r10_rds;
wire [31:0] r11_rds;
wire [31:0] r12_rds;
wire [31:0] r13_rds;
wire [31:0] r14_rds;
// Supervisor Mode Registers
reg [31:0] r13_svc = 32'hdead_beef;
reg [31:0] r14_svc = 32'hdead_beef;
// Interrupt Mode Registers
reg [31:0] r13_irq = 32'hdead_beef;
reg [31:0] r14_irq = 32'hdead_beef;
// Fast Interrupt Mode Registers
reg [31:0] r8_firq = 32'hdead_beef;
reg [31:0] r9_firq = 32'hdead_beef;
reg [31:0] r10_firq = 32'hdead_beef;
reg [31:0] r11_firq = 32'hdead_beef;
reg [31:0] r12_firq = 32'hdead_beef;
reg [31:0] r13_firq = 32'hdead_beef;
reg [31:0] r14_firq = 32'hdead_beef;
wire usr_exec;
wire svc_exec;
wire irq_exec;
wire firq_exec;
wire usr_idec;
wire svc_idec;
wire irq_idec;
wire firq_idec;
// Write Enables from execute stage
assign usr_idec = i_user_mode_regs_load || i_mode_idec == USR;
assign svc_idec = !i_user_mode_regs_load && i_mode_idec == SVC;
assign irq_idec = !i_user_mode_regs_load && i_mode_idec == IRQ;
// pre-encoded in decode stage to speed up long path
assign firq_idec = i_firq_not_user_mode;
// Read Enables from stage 1 (fetch)
assign usr_exec = i_mode_exec == USR;
assign svc_exec = i_mode_exec == SVC;
assign irq_exec = i_mode_exec == IRQ;
assign firq_exec = i_mode_exec == FIRQ;
// ========================================================
// Register Update
// ========================================================
always @ ( posedge i_clk )
if (!i_fetch_stall)
begin
r0 <= i_reg_bank_wen[0 ] ? i_reg : r0;
r1 <= i_reg_bank_wen[1 ] ? i_reg : r1;
r2 <= i_reg_bank_wen[2 ] ? i_reg : r2;
r3 <= i_reg_bank_wen[3 ] ? i_reg : r3;
r4 <= i_reg_bank_wen[4 ] ? i_reg : r4;
r5 <= i_reg_bank_wen[5 ] ? i_reg : r5;
r6 <= i_reg_bank_wen[6 ] ? i_reg : r6;
r7 <= i_reg_bank_wen[7 ] ? i_reg : r7;
r8 <= (i_reg_bank_wen[8 ] && !firq_idec) ? i_reg : r8;
r9 <= (i_reg_bank_wen[9 ] && !firq_idec) ? i_reg : r9;
r10 <= (i_reg_bank_wen[10] && !firq_idec) ? i_reg : r10;
r11 <= (i_reg_bank_wen[11] && !firq_idec) ? i_reg : r11;
r12 <= (i_reg_bank_wen[12] && !firq_idec) ? i_reg : r12;
r8_firq <= (i_reg_bank_wen[8 ] && firq_idec) ? i_reg : r8_firq;
r9_firq <= (i_reg_bank_wen[9 ] && firq_idec) ? i_reg : r9_firq;
r10_firq <= (i_reg_bank_wen[10] && firq_idec) ? i_reg : r10_firq;
r11_firq <= (i_reg_bank_wen[11] && firq_idec) ? i_reg : r11_firq;
r12_firq <= (i_reg_bank_wen[12] && firq_idec) ? i_reg : r12_firq;
r13 <= (i_reg_bank_wen[13] && usr_idec) ? i_reg : r13;
r14 <= (i_reg_bank_wen[14] && usr_idec) ? i_reg : r14;
r13_svc <= (i_reg_bank_wen[13] && svc_idec) ? i_reg : r13_svc;
r14_svc <= (i_reg_bank_wen[14] && svc_idec) ? i_reg : r14_svc;
r13_irq <= (i_reg_bank_wen[13] && irq_idec) ? i_reg : r13_irq;
r14_irq <= (i_reg_bank_wen[14] && irq_idec) ? i_reg : r14_irq;
r13_firq <= (i_reg_bank_wen[13] && firq_idec) ? i_reg : r13_firq;
r14_firq <= (i_reg_bank_wen[14] && firq_idec) ? i_reg : r14_firq;
r15 <= i_pc_wen ? i_pc : r15;
end
// ========================================================
// Register Read based on Mode
// ========================================================
assign r0_out = r0;
assign r1_out = r1;
assign r2_out = r2;
assign r3_out = r3;
assign r4_out = r4;
assign r5_out = r5;
assign r6_out = r6;
assign r7_out = r7;
assign r8_out = firq_exec ? r8_firq : r8;
assign r9_out = firq_exec ? r9_firq : r9;
assign r10_out = firq_exec ? r10_firq : r10;
assign r11_out = firq_exec ? r11_firq : r11;
assign r12_out = firq_exec ? r12_firq : r12;
assign r13_out = usr_exec ? r13 :
svc_exec ? r13_svc :
irq_exec ? r13_irq :
r13_firq ;
assign r14_out = usr_exec ? r14 :
svc_exec ? r14_svc :
irq_exec ? r14_irq :
r14_firq ;
assign r15_out_rm = { i_status_bits_flags,
i_status_bits_irq_mask,
i_status_bits_firq_mask,
r15,
i_mode_exec};
assign r15_out_rm_nxt = { i_status_bits_flags,
i_status_bits_irq_mask,
i_status_bits_firq_mask,
i_pc,
i_mode_exec};
assign r15_out_rn = {6'd0, r15, 2'd0};
// rds outputs
assign r8_rds = i_mode_rds_exec[OH_FIRQ] ? r8_firq : r8;
assign r9_rds = i_mode_rds_exec[OH_FIRQ] ? r9_firq : r9;
assign r10_rds = i_mode_rds_exec[OH_FIRQ] ? r10_firq : r10;
assign r11_rds = i_mode_rds_exec[OH_FIRQ] ? r11_firq : r11;
assign r12_rds = i_mode_rds_exec[OH_FIRQ] ? r12_firq : r12;
assign r13_rds = i_mode_rds_exec[OH_USR] ? r13 :
i_mode_rds_exec[OH_SVC] ? r13_svc :
i_mode_rds_exec[OH_IRQ] ? r13_irq :
r13_firq ;
assign r14_rds = i_mode_rds_exec[OH_USR] ? r14 :
i_mode_rds_exec[OH_SVC] ? r14_svc :
i_mode_rds_exec[OH_IRQ] ? r14_irq :
r14_firq ;
// ========================================================
// Program Counter out
// ========================================================
assign o_pc = r15_out_rn;
// ========================================================
// Rm Selector
// ========================================================
assign o_rm = i_rm_sel == 4'd0 ? r0_out :
i_rm_sel == 4'd1 ? r1_out :
i_rm_sel == 4'd2 ? r2_out :
i_rm_sel == 4'd3 ? r3_out :
i_rm_sel == 4'd4 ? r4_out :
i_rm_sel == 4'd5 ? r5_out :
i_rm_sel == 4'd6 ? r6_out :
i_rm_sel == 4'd7 ? r7_out :
i_rm_sel == 4'd8 ? r8_out :
i_rm_sel == 4'd9 ? r9_out :
i_rm_sel == 4'd10 ? r10_out :
i_rm_sel == 4'd11 ? r11_out :
i_rm_sel == 4'd12 ? r12_out :
i_rm_sel == 4'd13 ? r13_out :
i_rm_sel == 4'd14 ? r14_out :
r15_out_rm ;
// ========================================================
// Rds Selector
// ========================================================
always @*
case (i_rds_sel)
4'd0 : o_rs = r0_out ;
4'd1 : o_rs = r1_out ;
4'd2 : o_rs = r2_out ;
4'd3 : o_rs = r3_out ;
4'd4 : o_rs = r4_out ;
4'd5 : o_rs = r5_out ;
4'd6 : o_rs = r6_out ;
4'd7 : o_rs = r7_out ;
4'd8 : o_rs = r8_rds ;
4'd9 : o_rs = r9_rds ;
4'd10 : o_rs = r10_rds ;
4'd11 : o_rs = r11_rds ;
4'd12 : o_rs = r12_rds ;
4'd13 : o_rs = r13_rds ;
4'd14 : o_rs = r14_rds ;
default: o_rs = r15_out_rn ;
endcase
// ========================================================
// Rd Selector
// ========================================================
always @*
case (i_rds_sel)
4'd0 : o_rd = r0_out ;
4'd1 : o_rd = r1_out ;
4'd2 : o_rd = r2_out ;
4'd3 : o_rd = r3_out ;
4'd4 : o_rd = r4_out ;
4'd5 : o_rd = r5_out ;
4'd6 : o_rd = r6_out ;
4'd7 : o_rd = r7_out ;
4'd8 : o_rd = r8_rds ;
4'd9 : o_rd = r9_rds ;
4'd10 : o_rd = r10_rds ;
4'd11 : o_rd = r11_rds ;
4'd12 : o_rd = r12_rds ;
4'd13 : o_rd = r13_rds ;
4'd14 : o_rd = r14_rds ;
default: o_rd = r15_out_rm_nxt ;
endcase
// ========================================================
// Rn Selector
// ========================================================
assign o_rn = i_rn_sel == 4'd0 ? r0_out :
i_rn_sel == 4'd1 ? r1_out :
i_rn_sel == 4'd2 ? r2_out :
i_rn_sel == 4'd3 ? r3_out :
i_rn_sel == 4'd4 ? r4_out :
i_rn_sel == 4'd5 ? r5_out :
i_rn_sel == 4'd6 ? r6_out :
i_rn_sel == 4'd7 ? r7_out :
i_rn_sel == 4'd8 ? r8_out :
i_rn_sel == 4'd9 ? r9_out :
i_rn_sel == 4'd10 ? r10_out :
i_rn_sel == 4'd11 ? r11_out :
i_rn_sel == 4'd12 ? r12_out :
i_rn_sel == 4'd13 ? r13_out :
i_rn_sel == 4'd14 ? r14_out :
r15_out_rn ;
endmodule
|
module data_packet_fifo
( input reset,
input clock,
input [31:0]ram_data_in,
input write_enable,
output reg have_space,
output reg [31:0]ram_data_out,
output reg pkt_waiting,
output reg isfull,
output reg [1:0]usb_ram_packet_out,
output reg [1:0]usb_ram_packet_in,
input read_enable,
input pkt_complete,
input skip_packet) ;
/* Some parameters for usage later on */
parameter DATA_WIDTH = 32 ;
parameter PKT_DEPTH = 128 ;
parameter NUM_PACKETS = 4 ;
/* Create the RAM here */
reg [DATA_WIDTH-1:0] usb_ram [PKT_DEPTH*NUM_PACKETS-1:0] ;
/* Create the address signals */
reg [6:0] usb_ram_offset_out ;
//reg [1:0] usb_ram_packet_out ;
reg [6:0] usb_ram_offset_in ;
//reg [1:0] usb_ram_packet_in ;
wire [6-2+NUM_PACKETS:0] usb_ram_aout ;
wire [6-2+NUM_PACKETS:0] usb_ram_ain ;
//reg isfull;
assign usb_ram_aout = {usb_ram_packet_out, usb_ram_offset_out} ;
assign usb_ram_ain = {usb_ram_packet_in, usb_ram_offset_in} ;
// Check if there is one full packet to process
always @(usb_ram_ain, usb_ram_aout, isfull)
begin
if (usb_ram_ain == usb_ram_aout)
pkt_waiting <= isfull ;
else if (usb_ram_ain > usb_ram_aout)
pkt_waiting <= (usb_ram_ain - usb_ram_aout) >= PKT_DEPTH;
else
pkt_waiting <= (usb_ram_ain + 10'b1000000000 - usb_ram_aout) >= PKT_DEPTH;
end
// Check if there is room
always @(usb_ram_ain, usb_ram_aout, isfull)
begin
if (usb_ram_ain == usb_ram_aout)
have_space <= ~isfull;
else if (usb_ram_ain > usb_ram_aout)
have_space <= ((usb_ram_ain - usb_ram_aout) <= PKT_DEPTH * (NUM_PACKETS - 1))? 1'b1 : 1'b0;
else
have_space <= (usb_ram_aout - usb_ram_ain) >= PKT_DEPTH;
end
/* RAM Writing/Reading process */
always @(posedge clock)
begin
if( write_enable )
begin
usb_ram[usb_ram_ain] <= ram_data_in ;
end
ram_data_out <= usb_ram[usb_ram_aout] ;
end
/* RAM Write/Read Address process */
always @(posedge clock)
begin
if( reset )
begin
usb_ram_packet_out <= 0 ;
usb_ram_offset_out <= 0 ;
usb_ram_offset_in <= 0 ;
usb_ram_packet_in <= 0 ;
isfull <= 0;
end
else
begin
if( skip_packet )
begin
usb_ram_packet_out <= usb_ram_packet_out + 1 ;
usb_ram_offset_out <= 0 ;
isfull <= 0;
end
else if(read_enable)
begin
if( usb_ram_offset_out == 7'b1111111 )
begin
isfull <= 0 ;
usb_ram_offset_out <= 0 ;
usb_ram_packet_out <= usb_ram_packet_out + 1 ;
end
else
usb_ram_offset_out <= usb_ram_offset_out + 1 ;
end
if( pkt_complete )
begin
usb_ram_packet_in <= usb_ram_packet_in + 1 ;
usb_ram_offset_in <= 0 ;
if ((usb_ram_packet_in + 2'b1) == usb_ram_packet_out)
isfull <= 1 ;
end
else if( write_enable )
begin
if (usb_ram_offset_in == 7'b1111111)
usb_ram_offset_in <= 7'b1111111 ;
else
usb_ram_offset_in <= usb_ram_offset_in + 1 ;
end
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: University of Southern California
// Engineer: Matthew Pohlmann
//
// Create Date: 20:53:49 11/14/2013
// Design Name:
// Module Name: text_editor_top
// Project Name: ee201_final_text_editor
// Target Devices: Nexys-3, Spartan-6
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module text_editor_top(
MemOE, MemWR, RamCS, FlashCS, QuadSpiFlashCS, // Disable the three memory chips
ClkPort, // the 100 MHz incoming clock signal
BtnC, // the middle button used as Reset
Ld7, Ld6, Ld5, Ld4, Ld3, Ld2, Ld1, Ld0,
An3, An2, An1, An0, // 4 anodes
Ca, Cb, Cc, Cd, Ce, Cf, Cg, // 7 cathodes
Dp, // Dot Point Cathode on SSDs
PS2KeyboardData, // PS2 Keyboard data bus
PS2KeyboardClk, // PS2 Keyboard data clock
vga_h_sync, // VGA Output Horizontal Sync signal
vga_v_sync, // VGA Output Vertical Sync signal
vga_r, // Red value for current scanning pixel
vga_g, // Green value for current scanning pixel
vga_b // Blue value for current scanning pixel
);
/************************************************************************
* INPUTS *
************************************************************************/
input ClkPort;
input BtnC;
/************************************************************************
* BIDIRECTIONALS *
************************************************************************/
inout PS2KeyboardData, PS2KeyboardClk;
/************************************************************************
* OUTPUTS *
************************************************************************/
output MemOE, MemWR, RamCS, FlashCS, QuadSpiFlashCS;
output Ld7, Ld6, Ld5, Ld4, Ld3, Ld2, Ld1, Ld0;
output Cg, Cf, Ce, Cd, Cc, Cb, Ca, Dp;
output An0, An1, An2, An3;
output vga_h_sync, vga_v_sync, vga_r, vga_g, vga_b;
/************************************************************************
* LOCAL SIGNALS *
************************************************************************/
wire Reset, ClkPort;
wire board_clk, sys_clk, PS2_clk, VGA_clk, cursor_clk;
wire [1:0] ssdscan_clk;
reg [26:0] DIV_CLK;
reg [3:0] SSD;
wire [3:0] SSD3, SSD2, SSD1, SSD0;
reg [7:0] SSD_CATHODES;
wire [7:0] KeyData;
wire KeyReleased;
reg [7:0] CurrentKey;
reg [8:0] document_pointer;
reg [8:0] write_location;
reg write_to_RAM;
wire [7:0] RAM_data;
wire [9:0] read_address;
reg vga_r, vga_g, vga_b;
assign { Ld7, Ld6, Ld5, Ld4, Ld3, Ld2, Ld1, Ld0 } = document_pointer[7:0];
assign Reset = BtnC;
// Disable the three memories so that they do not interfere with the rest of the design.
assign {MemOE, MemWR, RamCS, FlashCS, QuadSpiFlashCS} = 5'b11111;
/************************************************************************
* CLOCK DIVISION *
************************************************************************/
BUFGP BUFGP1 (board_clk, ClkPort);
// Our clock is too fast (100MHz) for SSD scanning
// create a series of slower "divided" clocks
// each successive bit is 1/2 frequency
always @(posedge board_clk, posedge Reset) begin
if (Reset)
DIV_CLK <= 0;
else
DIV_CLK <= DIV_CLK + 1'b1;
end
assign sys_clk = board_clk; // 100 MHz
assign PS2_clk = DIV_CLK[0]; // 50 MHz
assign VGA_clk = DIV_CLK[1]; // 25 MHz
assign cursor_clk = DIV_CLK[26]; // .75 Hz
/************************************************************************
* VGA Control *
************************************************************************/
parameter RAM_size = 10'd512; // Size of the RAM
parameter write_area = RAM_size - 10'd2; // Allowable write area in the RAM (last location used as a null location)
parameter char_dim = 10'd16; // Dimension of a character (16x16 bits)
parameter char_scale_i = 10'd2; // Initial character scale
parameter row_length_i = 10'd18; // Initial length of a row (number of columns)
parameter col_length_i = 10'd29; // Initial length of a column (number of rows)
reg [9:0] char_scale;
reg [9:0] row_length;
reg [9:0] col_length;
reg [9:0] scroll;
reg text_red;
reg text_green;
reg text_blue;
wire inDisplayArea;
wire [9:0] CounterX;
wire [9:0] CounterY;
wire [9:0] CounterXDiv;
wire [9:0] CounterYDiv;
assign CounterXDiv = CounterX / char_scale;
assign CounterYDiv = CounterY / char_scale;
wire shouldDraw;
assign shouldDraw = CounterXDiv < char_dim * row_length && CounterYDiv < char_dim * col_length;
wire [0:255] relativePixel;
assign relativePixel = CounterXDiv % char_dim + CounterYDiv % char_dim * char_dim;
wire drawCursor;
assign drawCursor = read_address == document_pointer && Cursor[relativePixel] && cursor_clk;
assign read_address = (CounterXDiv / char_dim + CounterYDiv / char_dim * row_length + scroll * row_length) < RAM_size - 1'b1 ?
(CounterXDiv / char_dim + CounterYDiv / char_dim * row_length + scroll * row_length) :
RAM_size - 1'b1;
hvsync_generator vgaSyncGen(
// Inputs
.clk(VGA_clk),
.reset(Reset),
// Outputs
.vga_h_sync(vga_h_sync),
.vga_v_sync(vga_v_sync),
.inDisplayArea(inDisplayArea),
.CounterX(CounterX),
.CounterY(CounterY)
);
always @(posedge VGA_clk) begin
vga_r <= Red & inDisplayArea;
vga_g <= Green & inDisplayArea;
vga_b <= Blue & inDisplayArea;
end
wire Red = shouldDraw && ((~drawCursor && text_red && toDraw[relativePixel]) || (drawCursor && !text_red) || (drawCursor && text_red && text_green && text_blue));
wire Blue = shouldDraw && ((~drawCursor && text_blue && toDraw[relativePixel]) || (drawCursor && !text_blue));
wire Green = shouldDraw && ((~drawCursor && text_green && toDraw[relativePixel]) || (drawCursor && !text_green));
wire [0:255] toDraw;
assign toDraw = RAM_data == 8'h70 ? Block :
RAM_data == 8'h49 ? Period :
RAM_data == 8'h41 ? Comma :
RAM_data == 8'h52 ? Apost :
RAM_data == 8'h16 ? ExlPnt :
RAM_data == 8'h1C ? A :
RAM_data == 8'h32 ? B :
RAM_data == 8'h21 ? C :
RAM_data == 8'h23 ? D :
RAM_data == 8'h24 ? E :
RAM_data == 8'h2B ? F :
RAM_data == 8'h34 ? G :
RAM_data == 8'h33 ? H :
RAM_data == 8'h43 ? I :
RAM_data == 8'h3B ? J :
RAM_data == 8'h42 ? K :
RAM_data == 8'h4B ? L :
RAM_data == 8'h3A ? M :
RAM_data == 8'h31 ? N :
RAM_data == 8'h44 ? O :
RAM_data == 8'h4D ? P :
RAM_data == 8'h15 ? Q :
RAM_data == 8'h2D ? R :
RAM_data == 8'h1B ? S :
RAM_data == 8'h2C ? T :
RAM_data == 8'h3C ? U :
RAM_data == 8'h2A ? V :
RAM_data == 8'h1D ? W :
RAM_data == 8'h22 ? X :
RAM_data == 8'h35 ? Y :
RAM_data == 8'h1A ? Z :
256'd0;
parameter [0:255] Cursor = 256'hC000C000C000C000C000C000C000C000C000C000C000C000C000C000C000C000;
parameter [0:255] Block = 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF;
parameter [0:255] Period = 256'h0000000000000000000000000000000000000000000000000000E000E000E000;
parameter [0:255] Comma = 256'h000000000000000000000000000000000000000000000000000070007000E000;
parameter [0:255] Apost = 256'h070007000E000000000000000000000000000000000000000000000000000000;
parameter [0:255] ExlPnt = 256'hF000F000F000F000F000F000F000F000F000F000F00000000000F000F000F000;
parameter [0:255] A = 256'h00001FE03870387070387038E01CE01CE01CFFFCFFFCE01CE01CE01CE01CE01C;
parameter [0:255] B = 256'h0000FFC0FFF0F078F03CF03CF038FFE0FFE0F038F03CF03CF03CF07CFFF8FFE0;
parameter [0:255] C = 256'h00001FF07FFCF81EF01EE000E000E000E000E000E000E000E01EF01E7FFC1FF0;
parameter [0:255] D = 256'h0000FFE0FFF8F03CF01CF00EF00EF00EF00EF00EF00EF00EF01CF03CFFF8FFE0;
parameter [0:255] E = 256'h0000FFFEFFFEE000E000E000E000FFFEFFFEE000E000E000E000E000FFFEFFFE;
parameter [0:255] F = 256'h0000FFFEFFFEF000F000F000F000FFFEFFFEF000F000F000F000F000F000F000;
parameter [0:255] G = 256'h00003FF07FF8F01EE00EC000C000C000C000C07EC07EC00EC00EF01E7FF83FF0;
parameter [0:255] H = 256'h0000E00EE00EE00EE00EE00EE00EFFFEFFFEE00EE00EE00EE00EE00EE00EE00E;
parameter [0:255] I = 256'h0000FFFCFFFC07800780078007800780078007800780078007800780FFFCFFFC;
parameter [0:255] J = 256'h00003FFC3FFC001C001C001C001C001C001C001CE01CE01CE01CF03C7FF83FF0;
parameter [0:255] K = 256'h0000E00EE00EE01CE038E070E0E0FFC0FFC0E0E0E070E038E01CE00EE00EE00E;
parameter [0:255] L = 256'h0000E000E000E000E000E000E000E000E000E000E000E000E000E000FFFCFFFC;
parameter [0:255] M = 256'h0000F87CFCFCFCFCECDCEFDCE79CE31CE01CE01CE01CE01CE01CE01CE01CE01C;
parameter [0:255] N = 256'h0000F81CF81CEC1CEC1CE61CE61CE31CE31CE31CE19CE19CE0DCE0DCE07CE07C;
parameter [0:255] O = 256'h00003FF07878E01CE01CE01CE01CE01CE01CE01CE01CE01CE01CF03C78783FF0;
parameter [0:255] P = 256'h0000FFC0FFF8F07CF03CF03CF03CF07CFFF8FFC0F000F000F000F000F000F000;
parameter [0:255] Q = 256'h00003FF07878E01CE01CE01CE01CE01CE01CE01CE01CE01CE01CF03C787C0FDE;
parameter [0:255] R = 256'h0000FFF0FFFCF01EF01EF01EF01EFFF0FFC0F0F0F078F03CF03CF01EF01EF01E;
parameter [0:255] S = 256'h00000FF03FFCE01EE00EE00EF0007FF01FFC001EE00EE00EF00E781E3FFC07F8;
parameter [0:255] T = 256'h0000FFFEFFFE0380038003800380038003800380038003800380038003800380;
parameter [0:255] U = 256'h0000E00EE00EE00EE00EE00EE00EE00EE00EE00EE00EE00EE00EE00E783C1FF0;
parameter [0:255] V = 256'h0000E00EF01EF01E783C783C3C783C783C781EF01EF00FE00FE007C003800100;
parameter [0:255] W = 256'h0000E01CE01CE01CE01CE01CE01CE01CE01CE31CE79CEFDCECDCFCFCFCFCF87C;
parameter [0:255] X = 256'h0000F01EF01E78783CF03CF01FE00FC007800FC01FE03CF03CF07878F03CF03C;
parameter [0:255] Y = 256'h0000E00EE00E701C781C3C780FE007C003800380038003800380038003800380;
parameter [0:255] Z = 256'h0000FFFEFFFE001E003C007800F001E003C00F001E003C007800F000FFFEFFFE;
/************************************************************************
* PS2 KEYBOARD *
************************************************************************/
text_editor_keyboard_controller KeyBoard(
// Inputs
.sys_Clk(sys_clk),
.PS2_Clk(PS2_clk),
.Reset(Reset),
// Bidirectionals
.PS2KeyboardData(PS2KeyboardData),
.PS2KeyboardClk(PS2KeyboardClk),
// Outputs
.KeyData(KeyData),
.KeyReleased(KeyReleased)
);
/************************************************************************
* TEXT RAM *
************************************************************************/
text_editor_RAM RAM(
// Inputs
.clk(sys_clk),
.Reset(Reset),
.write(write_to_RAM),
.write_address(write_location),
.write_data(CurrentKey),
.read_address(read_address[8:0]),
// Outputs
.read_data(RAM_data)
);
/************************************************************************
* STATE MACHINE *
************************************************************************/
reg [1:0] state;
localparam
INI = 2'b00,
GETKEY = 2'b01,
EDIT = 2'b10,
WRITE = 2'b11,
UNK = 2'bXX;
always @ (posedge sys_clk, posedge Reset) begin: STATE_MACHINE
if (Reset) begin
CurrentKey <= 8'hXX;
document_pointer <= 9'bXXXXXXXXX;
write_location <= 9'bXXXXXXXXX;
write_to_RAM <= 1'bX;
char_scale <= 10'bXXXXXXXXXX;
row_length <= 10'bXXXXXXXXXX;
col_length <= 10'bXXXXXXXXXX;
scroll <= 10'bXXXXXXXXXX;
text_red <= 1'bX;
text_green <= 1'bX;
text_blue <= 1'bX;
state <= INI;
end else begin
case (state)
INI: begin
state <= GETKEY;
CurrentKey <= 8'h29; // SPACE
write_to_RAM <= 1'b0;
document_pointer <= 10'd0;
write_location <= 10'd0;
char_scale <= char_scale_i;
row_length <= row_length_i;
col_length <= col_length_i;
scroll <= 10'd0;
text_red <= 1'b0;
text_green <= 1'b1;
text_blue <= 1'b0;
end
GETKEY: begin
if (KeyReleased) begin
state <= EDIT;
end
CurrentKey <= KeyData;
case(char_scale)
2'd1: begin row_length <= 10'd36; col_length <= 10'd15; end
2'd2: begin row_length <= 10'd18; col_length <= 10'd29; end
2'd3: begin row_length <= 10'd12; col_length <= 10'd43; end
default: begin row_length <= 10'd18; col_length <= 10'd29; end
endcase
end
EDIT: begin
state <= WRITE;
write_to_RAM <= 1'b1;
write_location <= document_pointer;
case (CurrentKey)
8'h66: begin // BACKSPACE
if (document_pointer > 10'd0) begin
document_pointer <= document_pointer - 1'b1;
write_location <= document_pointer - 1'b1;
end
CurrentKey <= 8'h29; // SPACE
end
8'h6B: begin // LEFT ARROW
write_to_RAM <= 1'b0;
if (document_pointer > 10'd0) begin
document_pointer <= document_pointer - 1'b1;
end
end
8'h74: begin // RIGHT ARROW
write_to_RAM <= 1'b0;
if (document_pointer < write_area) begin
document_pointer <= document_pointer + 1'b1;
end
end
8'h75: begin // UP ARROW
write_to_RAM <= 1'b0;
if (document_pointer >= row_length) begin
document_pointer <= document_pointer - row_length;
end
end
8'h72: begin // DOWN ARROW
write_to_RAM <= 1'b0;
if (document_pointer <= write_area - row_length) begin
document_pointer <= document_pointer + row_length;
end
end
8'h79: begin // + KEYPAD
write_to_RAM <= 1'b0;
if (char_scale < 10'd3) begin
char_scale <= char_scale + 1'b1;
end
end
8'h7B: begin // - KEYPAD
write_to_RAM <= 1'b0;
if (char_scale > 10'd1) begin
char_scale <= char_scale - 1'b1;
end
end
8'h7D: begin // PG UP
write_to_RAM <= 1'b0;
if (scroll < col_length - 2'd2) begin
scroll <= scroll + 1'b1;
end
end
8'h7A: begin // PG DOWN
write_to_RAM <= 1'b0;
if (scroll > 10'd0) begin
scroll <= scroll - 1'b1;
end
end
8'h05: begin // F1 (Red color)
write_to_RAM <= 1'b0;
text_red <= ~text_red;
if (text_red && !text_blue) begin
text_green <= 1'b1;
end
end
8'h06: begin // F2 (Green color)
write_to_RAM <= 1'b0;
text_green <= ~text_green;
if (text_green && !text_blue && !text_red) begin
text_green <= 1'b1;
end
end
8'h04: begin // F3 (Blue color)
write_to_RAM <= 1'b0;
text_blue <= ~text_blue;
if (text_blue && !text_red) begin
text_green <= 1'b1;
end
end
8'h71: begin // DELETE KEY
CurrentKey <= 8'h29; // SPACE
end
default: begin
if (document_pointer < write_area) begin
document_pointer <= document_pointer + 1'b1;
end
end
endcase
end
WRITE: begin
state <= GETKEY;
write_to_RAM <= 1'b0;
end
default: begin
state <= UNK;
end
endcase
end
end
/************************************************************************
* SSD OUTPUT *
************************************************************************/
assign SSD3 = 0;
assign SSD2 = 0;
assign SSD1 = KeyData[7:4];
assign SSD0 = KeyData[3:0];
assign ssdscan_clk = DIV_CLK[19:18];
assign An3 = 1; //!(~(ssdscan_clk[1]) && ~(ssdscan_clk[0])); // when ssdscan_clk = 00 **Used for debugging, disabled in final project**
assign An2 = 1; //!(~(ssdscan_clk[1]) && (ssdscan_clk[0])); // when ssdscan_clk = 01 **Used for debugging, disabled in final project**
assign An1 = !((ssdscan_clk[1]) && ~(ssdscan_clk[0])); // when ssdscan_clk = 10
assign An0 = !((ssdscan_clk[1]) && (ssdscan_clk[0])); // when ssdscan_clk = 11
always @ (ssdscan_clk, SSD0, SSD1, SSD2, SSD3) begin: SSD_SCAN_OUT
case (ssdscan_clk)
2'b00: SSD = SSD3;
2'b01: SSD = SSD2;
2'b10: SSD = SSD1;
2'b11: SSD = SSD0;
endcase
end
// and finally convert SSD_num to ssd
// We convert the output of our 4-bit 4x1 mux
assign {Ca, Cb, Cc, Cd, Ce, Cf, Cg, Dp} = {SSD_CATHODES};
// Following is Hex-to-SSD conversion
always @ (SSD)
begin : HEX_TO_SSD
case (SSD)
4'b0000: SSD_CATHODES = 8'b00000011; // 0
4'b0001: SSD_CATHODES = 8'b10011111; // 1
4'b0010: SSD_CATHODES = 8'b00100101; // 2
4'b0011: SSD_CATHODES = 8'b00001101; // 3
4'b0100: SSD_CATHODES = 8'b10011001; // 4
4'b0101: SSD_CATHODES = 8'b01001001; // 5
4'b0110: SSD_CATHODES = 8'b01000001; // 6
4'b0111: SSD_CATHODES = 8'b00011111; // 7
4'b1000: SSD_CATHODES = 8'b00000001; // 8
4'b1001: SSD_CATHODES = 8'b00001001; // 9
4'b1010: SSD_CATHODES = 8'b00010001; // A
4'b1011: SSD_CATHODES = 8'b11000001; // B
4'b1100: SSD_CATHODES = 8'b01100011; // C
4'b1101: SSD_CATHODES = 8'b10000101; // D
4'b1110: SSD_CATHODES = 8'b01100001; // E
4'b1111: SSD_CATHODES = 8'b01110001; // F
default: SSD_CATHODES = 8'bXXXXXXXX; // default is not needed as we covered all cases
endcase
end
endmodule
|
// ============================================================================
// Copyright (c) 2010
// ============================================================================
//
// Permission:
//
//
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods.
// ============================================================================
//
// ReConfigurable Computing Group
//
// web: http://www.ecs.umass.edu/ece/tessier/rcg/
//
//
// ============================================================================
// Major Functions/Design Description:
//
//
//
// ============================================================================
// Revision History:
// ============================================================================
// Ver.: |Author: |Mod. Date: |Changes Made:
// V1.0 |RCG |05/10/2011 |
// ============================================================================
//include "NF_2.1_defines.v"
//include "registers.v"
//include "reg_defines_reference_router.v"
`include "../command_defines.v"
module op_lut_process_sm
#(parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = DATA_WIDTH/8,
parameter NUM_QUEUES = 8,
parameter NUM_QUEUES_WIDTH = log2(NUM_QUEUES),
parameter STAGE_NUM = 4,
parameter IOQ_STAGE_NUM = 8'hff)
(// --- interface to input fifo - fallthrough
input in_fifo_vld,
input [DATA_WIDTH-1:0] in_fifo_data,
input [CTRL_WIDTH-1:0] in_fifo_ctrl,
output reg in_fifo_rd_en,
// --- interface to eth_parser
input is_arp_pkt,
input is_ip_pkt,
input is_for_us,
input is_broadcast,
input eth_parser_info_vld,
input [NUM_QUEUES_WIDTH-1:0] mac_dst_port_num,
// --- interface to ip_arp
input [47:0] next_hop_mac,
input [NUM_QUEUES-1:0] output_port,
input arp_lookup_hit, // indicates if the next hop mac is correct
input lpm_lookup_hit, // indicates if the route to the destination IP was found
input arp_mac_vld, // indicates the lookup is done
// --- interface to op_lut_hdr_parser
input is_from_cpu,
input [NUM_QUEUES-1:0] to_cpu_output_port, // where to send pkts this pkt if it has to go to the CPU
input [NUM_QUEUES-1:0] from_cpu_output_port, // where to send this pkt if it is coming from the CPU
input is_from_cpu_vld,
input [NUM_QUEUES_WIDTH-1:0] input_port_num,
// --- interface to IP_checksum
input ip_checksum_vld,
input ip_checksum_is_good,
input ip_hdr_has_options,
input [15:0] ip_new_checksum, // new checksum assuming decremented TTL
input ip_ttl_is_good,
input [7:0] ip_new_ttl,
// --- input to dest_ip_filter
input dest_ip_hit,
input dest_ip_filter_vld,
// -- connected to all preprocess blocks
output reg rd_preprocess_info,
// --- interface to next module
output reg out_wr,
output reg [DATA_WIDTH-1:0] out_data,
output reg [CTRL_WIDTH-1:0] out_ctrl, // new checksum assuming decremented TTL
input out_rdy,
// --- interface to registers
output reg pkt_sent_from_cpu, // pulsed: we've sent a pkt from the CPU
output reg pkt_sent_to_cpu_options_ver, // pulsed: we've sent a pkt to the CPU coz it has options/bad version
output reg pkt_sent_to_cpu_bad_ttl, // pulsed: sent a pkt to the CPU coz the TTL is 1 or 0
output reg pkt_sent_to_cpu_dest_ip_hit, // pulsed: sent a pkt to the CPU coz it has hit in the destination ip filter list
output reg pkt_forwarded , // pulsed: forwarded pkt to the destination port
output reg pkt_dropped_checksum, // pulsed: dropped pkt coz bad checksum
output reg pkt_sent_to_cpu_non_ip, // pulsed: sent pkt to cpu coz it's not IP
output reg pkt_sent_to_cpu_arp_miss, // pulsed: sent pkt to cpu coz we didn't find arp entry for next hop ip
output reg pkt_sent_to_cpu_lpm_miss, // pulsed: sent pkt to cpu coz we didn't find lpm entry for destination ip
output reg pkt_dropped_wrong_dst_mac, // pulsed: dropped pkt not destined to us
input [47:0] mac_0, // address of rx queue 0
input [47:0] mac_1, // address of rx queue 1
input [47:0] mac_2, // address of rx queue 2
input [47:0] mac_3, // address of rx queue 3
// -- avalon interface to access ethernet rx buffer (Deepak)
input [ 9: 0] address,
output [ 31: 0] readdata,
input [ 3: 0] byteenable,
input chipselect,
input write,
input [ 31: 0] writedata,
//i/f b/w op_lut_process_sm.v and RX EXT FIFO
output reg [63:0] rx_ext_update_data,
input rx_ext_update_0_full,
output rx_ext_update_0_wrreq,
input rx_ext_update_1_full,
output rx_ext_update_1_wrreq,
input rx_ext_update_2_full,
output rx_ext_update_2_wrreq,
input rx_ext_update_3_full,
output rx_ext_update_3_wrreq,
input rx_ext_update_4_full,
output rx_ext_update_4_wrreq,
input rx_ext_update_5_full,
output rx_ext_update_5_wrreq,
input rx_ext_update_6_full,
output rx_ext_update_6_wrreq,
input rx_ext_update_7_full,
output rx_ext_update_7_wrreq,
output reg start_update,
output reg flush_ddr,
output reg check_terminate,
output reg flush_data,
output reg start_load,
output reg compute_system_reset,
//write interface to DDR (used by load data function)
output reg [63:0] dram_fifo_writedata,
output reg dram_fifo_write,
input dram_fifo_full,
input [7:0] proc_bit_mask,
// misc
input reset,
input clk
);
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
//------------------- Internal parameters -----------------------
localparam NUM_STATES = 10;
localparam WAIT_PREPROCESS_RDY = 1;
localparam MOVE_MODULE_HDRS = 2;
localparam SEND_SRC_MAC_LO = 4;
localparam SEND_IP_TTL = 8;
localparam SEND_IP_CHECKSUM = 16;
localparam MOVE_UDP = 32;
localparam INTERPRET_COMMAND = 64;
localparam LOAD_KEY_VALUE = 128;
localparam ACCUM_KEY_VALUE = 256;
localparam DROP_PKT = 512;
//---------------------- Wires and regs -------------------------
wire preprocess_vld;
reg [NUM_STATES-1:0] state;
reg [NUM_STATES-1:0] state_next;
reg [DATA_WIDTH-1:0] out_data_next;
reg [CTRL_WIDTH-1:0] out_ctrl_next;
reg out_wr_next;
reg ctrl_prev_is_0;
wire eop;
reg [47:0] src_mac_sel;
reg [NUM_QUEUES-1:0] dst_port;
reg [NUM_QUEUES-1:0] dst_port_next;
reg to_from_cpu;
reg to_from_cpu_next;
reg [63:0] rx_ext_update_data_next;
reg [7:0] rx_ext_update_wrreq, rx_ext_update_wrreq_next;
wire [7:0] rx_ext_update_full;
reg [1:0] command, command_next;
reg start_update_next;
reg flush_ddr_next;
reg start_load_next;
reg check_terminate_next;
reg flush_data_next;
wire is_safe_to_write_packet;
reg compute_system_reset_next;
reg [63:0] dram_fifo_writedata_next;
reg dram_fifo_write_next;
reg [4:0] rx_ext_fifo_sel, rx_ext_fifo_sel_next;
wire [4:0] next_external_fifo;
reg [31:0] packet_rcv /*synthesis noprune*/;
reg [31:0] packet_rcv_next /*synthesis noprune*/;
assign rx_ext_update_0_wrreq = rx_ext_update_wrreq[0];
assign rx_ext_update_1_wrreq = rx_ext_update_wrreq[1];
assign rx_ext_update_2_wrreq = rx_ext_update_wrreq[2];
assign rx_ext_update_3_wrreq = rx_ext_update_wrreq[3];
assign rx_ext_update_4_wrreq = rx_ext_update_wrreq[4];
assign rx_ext_update_5_wrreq = rx_ext_update_wrreq[5];
assign rx_ext_update_6_wrreq = rx_ext_update_wrreq[6];
assign rx_ext_update_7_wrreq = rx_ext_update_wrreq[7];
assign rx_ext_update_full[0] = rx_ext_update_0_full;
assign rx_ext_update_full[1] = rx_ext_update_1_full;
assign rx_ext_update_full[2] = rx_ext_update_2_full;
assign rx_ext_update_full[3] = rx_ext_update_3_full;
assign rx_ext_update_full[4] = rx_ext_update_4_full;
assign rx_ext_update_full[5] = rx_ext_update_5_full;
assign rx_ext_update_full[6] = rx_ext_update_6_full;
assign rx_ext_update_full[7] = rx_ext_update_7_full;
reg [3:0] ext_start;
always@(*) begin
case(proc_bit_mask) //ext_start represents bit position in proc_mask
8'h00: ext_start = 0;
8'h01: ext_start = 1;
8'h03: ext_start = 2;
8'h07: ext_start = 3;
8'h0f: ext_start = 4;
8'h1f: ext_start = 5;
8'h3f: ext_start = 6;
8'h7f: ext_start = 7;
8'hff: ext_start = 0; //Illegal - should never happen!
default: ext_start = 0;
endcase
end
localparam INVALID=0;
localparam LOAD=1;
localparam ACCUMULATE=2;
//-------------------------- Logic ------------------------------
assign preprocess_vld = eth_parser_info_vld & ip_checksum_vld;
assign eop = (ctrl_prev_is_0 && (in_fifo_ctrl!=0));
/* select the src mac address to write in the forwarded pkt */
always @(*) begin
case(output_port)
'h1: src_mac_sel = mac_0;
'h4: src_mac_sel = mac_1;
'h10: src_mac_sel = mac_2;
'h40: src_mac_sel = mac_3;
default: src_mac_sel = mac_0;
endcase // case(output_port)
end
/* Modify the packet's hdrs and add the module hdr */
always @(*) begin
rd_preprocess_info = 0;
state_next = state;
in_fifo_rd_en = 0;
pkt_dropped_wrong_dst_mac = 0;
rx_ext_update_data_next = rx_ext_update_data;
rx_ext_update_wrreq_next = 1'b0;
command_next = command;
//start_update_next = 1'b0;
start_update_next = start_update;
flush_ddr_next = 1'b0;
start_load_next = start_load;
check_terminate_next = 1'b0;
flush_data_next = 1'b0;
dram_fifo_writedata_next = dram_fifo_writedata;
dram_fifo_write_next = 1'b0;
compute_system_reset_next = 1'b0;
rx_ext_fifo_sel_next = rx_ext_fifo_sel;
packet_rcv_next = packet_rcv;
case(state)
WAIT_PREPROCESS_RDY: begin
if(preprocess_vld) begin
//if(is_for_us && is_ip_pkt && ip_checksum_is_good) begin
if(is_for_us && is_ip_pkt) begin //skip checksum for now
state_next = MOVE_MODULE_HDRS;
packet_rcv_next = packet_rcv+1;
end // else: !if(ip_hdr_has_options | !ip_ttl_is_good)
else begin
pkt_dropped_wrong_dst_mac = 1;
rd_preprocess_info = 1;
in_fifo_rd_en = 1;
state_next = DROP_PKT;
end
end
end // case: WAIT_PREPROCESS_RDY
MOVE_MODULE_HDRS: begin
if(in_fifo_vld) begin
in_fifo_rd_en = 1;
if(in_fifo_ctrl==0) begin
state_next = SEND_SRC_MAC_LO;
end
end
end // case: MOVE_MODULE_HDRS
SEND_SRC_MAC_LO: begin
if(in_fifo_vld) begin
in_fifo_rd_en = 1;
state_next = SEND_IP_TTL;
end
end
SEND_IP_TTL: begin
if(in_fifo_vld) begin
in_fifo_rd_en = 1;
state_next = SEND_IP_CHECKSUM;
end
end
SEND_IP_CHECKSUM: begin
if(in_fifo_vld) begin
in_fifo_rd_en = 1;
rd_preprocess_info = 1;
state_next = MOVE_UDP;
end
end
MOVE_UDP: begin
if(in_fifo_vld) begin
in_fifo_rd_en = 1;
state_next = INTERPRET_COMMAND;
end
end
INTERPRET_COMMAND: begin
if(in_fifo_vld) begin
in_fifo_rd_en = 1;
//interpret command here TODO
if(in_fifo_data[47:40]==`START_LOAD) begin
start_load_next = 1'b1;
state_next = DROP_PKT;
end
else if(in_fifo_data[47:40]==`LOAD_DATA) begin
state_next = LOAD_KEY_VALUE;
end
else if(in_fifo_data[47:40]==`END_LOAD) begin
start_load_next = 1'b0;
compute_system_reset_next = 1'b1; //reset the compute system
state_next = DROP_PKT;
end
else if(in_fifo_data[47:40]==`FPGA_TO_WORKER_PUT_REQUEST) begin //updates from FPGA workers to this FPGA
state_next = ACCUM_KEY_VALUE;
end
else if(in_fifo_data[47:40]==`WORKER_TO_FPGA_PUT_REQUEST) begin //updaets from CPU workers to this FPGA
state_next = ACCUM_KEY_VALUE;
end
else if(in_fifo_data[47:40]==`START_UPDATE) begin
start_update_next = 1'b1;
state_next = DROP_PKT;
end
else if(in_fifo_data[47:40]==`END_UPDATE) begin
start_update_next = 1'b0;
state_next = DROP_PKT;
end
else if(in_fifo_data[47:40]==`START_CHECK_TERMINATE) begin
check_terminate_next = 1'b1;
state_next = DROP_PKT;
end
else if(in_fifo_data[47:40]==`START_FLUSH_DATA) begin
flush_ddr_next = 1'b1;
state_next = DROP_PKT;
end
else begin
state_next = DROP_PKT;
end
end //end if(in_fifo)
end
LOAD_KEY_VALUE: begin //FIX THIS
if(in_fifo_vld && (!dram_fifo_full)) begin
dram_fifo_writedata_next = in_fifo_data[63:0];
dram_fifo_write_next = 1'b1;
state_next = (eop)?WAIT_PREPROCESS_RDY:LOAD_KEY_VALUE;
in_fifo_rd_en = (eop)?0:1;
end
end
ACCUM_KEY_VALUE: begin
if(in_fifo_vld) begin
//Make sure key!=0 AND val!=0
//If rx fifo is full, simply DROP packets - dont head-of-line
//block the packets
if((|in_fifo_data)&&(!rx_ext_update_full[rx_ext_fifo_sel])) begin
rx_ext_update_data_next = in_fifo_data[63:0];
rx_ext_update_wrreq_next[rx_ext_fifo_sel] = 1'b1;
rx_ext_fifo_sel_next = ((rx_ext_fifo_sel+1)==8)?ext_start:(rx_ext_fifo_sel+1);
end
in_fifo_rd_en = 1'b1;
if(eop) begin
state_next = WAIT_PREPROCESS_RDY;
end
else begin
//state_next = DROP_PKT;
state_next = ACCUM_KEY_VALUE;
end
end
end
DROP_PKT: begin
if(in_fifo_vld) begin
in_fifo_rd_en = 1;
if(eop) begin
state_next = WAIT_PREPROCESS_RDY;
end
end
end
endcase // case(state)
end // always @ (*)
always @(posedge clk or posedge reset) begin
if(reset) begin
state <= WAIT_PREPROCESS_RDY;
ctrl_prev_is_0 <= 0;
rx_ext_update_data <= 0;
rx_ext_update_wrreq <= 0;
start_update <= 0;
start_load <= 0;
check_terminate <= 0;
flush_ddr <= 0;
dram_fifo_writedata <= 0;
dram_fifo_write <= 0;
compute_system_reset <= 0;
rx_ext_fifo_sel <= 0;
packet_rcv <= 0;
end
else begin
state <= state_next;
ctrl_prev_is_0 <= in_fifo_rd_en ? (in_fifo_ctrl==0) : ctrl_prev_is_0;
rx_ext_update_data <= rx_ext_update_data_next;
rx_ext_update_wrreq <= rx_ext_update_wrreq_next;
start_update <= start_update_next;
start_load <= start_load_next;
check_terminate <= check_terminate_next;
flush_ddr <= flush_ddr_next;
dram_fifo_writedata <= dram_fifo_writedata_next;
dram_fifo_write <= dram_fifo_write_next;
compute_system_reset <= compute_system_reset_next;
rx_ext_fifo_sel <= (rx_ext_fifo_sel_next<ext_start)?ext_start:rx_ext_fifo_sel_next;
packet_rcv <= packet_rcv_next;
end // else: !if(reset)
end // always @ (posedge clk)
endmodule // op_lut_process_sm
|
// -----------------------------------------------------------
// Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
// use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any
// output files any of the foregoing (including device programming or
// simulation files), and any associated documentation or information are
// expressly subject to the terms and conditions of the Altera Program
// License Subscription Agreement or other applicable license agreement,
// including, without limitation, that your use is for the sole purpose
// of programming logic devices manufactured by Altera and sold by Altera
// or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// Description: Single clock Avalon-ST FIFO.
// -----------------------------------------------------------
`timescale 1 ns / 1 ns
//altera message_off 10036
module altera_avalon_sc_fifo
#(
// --------------------------------------------------
// Parameters
// --------------------------------------------------
parameter SYMBOLS_PER_BEAT = 1,
parameter BITS_PER_SYMBOL = 8,
parameter FIFO_DEPTH = 16,
parameter CHANNEL_WIDTH = 0,
parameter ERROR_WIDTH = 0,
parameter USE_PACKETS = 0,
parameter USE_FILL_LEVEL = 0,
parameter USE_STORE_FORWARD = 0,
parameter USE_ALMOST_FULL_IF = 0,
parameter USE_ALMOST_EMPTY_IF = 0,
// --------------------------------------------------
// Empty latency is defined as the number of cycles
// required for a write to deassert the empty flag.
// For example, a latency of 1 means that the empty
// flag is deasserted on the cycle after a write.
//
// Another way to think of it is the latency for a
// write to propagate to the output.
//
// An empty latency of 0 implies lookahead, which is
// only implemented for the register-based FIFO.
// --------------------------------------------------
parameter EMPTY_LATENCY = 3,
parameter USE_MEMORY_BLOCKS = 1,
// --------------------------------------------------
// Internal Parameters
// --------------------------------------------------
parameter DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
)
(
// --------------------------------------------------
// Ports
// --------------------------------------------------
input clk,
input reset,
input [DATA_WIDTH-1: 0] in_data,
input in_valid,
input in_startofpacket,
input in_endofpacket,
input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] in_empty,
input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] in_error,
input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] in_channel,
output in_ready,
output [DATA_WIDTH-1 : 0] out_data,
output reg out_valid,
output out_startofpacket,
output out_endofpacket,
output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] out_empty,
output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] out_error,
output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel,
input out_ready,
input [(USE_STORE_FORWARD ? 2 : 1) : 0] csr_address,
input csr_write,
input csr_read,
input [31 : 0] csr_writedata,
output reg [31 : 0] csr_readdata,
output wire almost_full_data,
output wire almost_empty_data
);
// --------------------------------------------------
// Local Parameters
// --------------------------------------------------
localparam ADDR_WIDTH = log2ceil(FIFO_DEPTH);
localparam DEPTH = FIFO_DEPTH;
localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH;
localparam PAYLOAD_WIDTH = (USE_PACKETS == 1) ?
2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH:
DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH;
// --------------------------------------------------
// Internal Signals
// --------------------------------------------------
genvar i;
reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0];
reg [ADDR_WIDTH-1 : 0] wr_ptr;
reg [ADDR_WIDTH-1 : 0] rd_ptr;
reg [DEPTH-1 : 0] mem_used;
wire [ADDR_WIDTH-1 : 0] next_wr_ptr;
wire [ADDR_WIDTH-1 : 0] next_rd_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr;
wire [ADDR_WIDTH-1 : 0] mem_rd_ptr;
wire read;
wire write;
reg empty;
reg next_empty;
reg full;
reg next_full;
wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals;
wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals;
wire [PAYLOAD_WIDTH-1 : 0] in_payload;
reg [PAYLOAD_WIDTH-1 : 0] internal_out_payload;
reg [PAYLOAD_WIDTH-1 : 0] out_payload;
reg internal_out_valid;
wire internal_out_ready;
reg [ADDR_WIDTH : 0] fifo_fill_level;
reg [ADDR_WIDTH : 0] fill_level;
reg [ADDR_WIDTH-1 : 0] sop_ptr = 0;
wire [ADDR_WIDTH-1 : 0] curr_sop_ptr;
reg [23:0] almost_full_threshold;
reg [23:0] almost_empty_threshold;
reg [23:0] cut_through_threshold;
reg [15:0] pkt_cnt;
reg drop_on_error_en;
reg error_in_pkt;
reg pkt_has_started;
reg sop_has_left_fifo;
reg fifo_too_small_r;
reg pkt_cnt_eq_zero;
reg pkt_cnt_eq_one;
wire wait_for_threshold;
reg pkt_mode;
wire wait_for_pkt;
wire ok_to_forward;
wire in_pkt_eop_arrive;
wire out_pkt_leave;
wire in_pkt_start;
wire in_pkt_error;
wire drop_on_error;
wire fifo_too_small;
wire out_pkt_sop_leave;
wire [31:0] max_fifo_size;
reg fifo_fill_level_lt_cut_through_threshold;
// --------------------------------------------------
// Define Payload
//
// Icky part where we decide which signals form the
// payload to the FIFO with generate blocks.
// --------------------------------------------------
generate
if (EMPTY_WIDTH > 0) begin : gen_blk1
assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty};
assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals;
end
else begin : gen_blk1_else
assign out_empty = in_error;
assign in_packet_signals = {in_startofpacket, in_endofpacket};
assign {out_startofpacket, out_endofpacket} = out_packet_signals;
end
endgenerate
generate
if (USE_PACKETS) begin : gen_blk2
if (ERROR_WIDTH > 0) begin : gen_blk3
if (CHANNEL_WIDTH > 0) begin : gen_blk4
assign in_payload = {in_packet_signals, in_data, in_error, in_channel};
assign {out_packet_signals, out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk4_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data, in_error};
assign {out_packet_signals, out_data, out_error} = out_payload;
end
end
else begin : gen_blk3_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk5
assign in_payload = {in_packet_signals, in_data, in_channel};
assign {out_packet_signals, out_data, out_channel} = out_payload;
end
else begin : gen_blk5_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data};
assign {out_packet_signals, out_data} = out_payload;
end
end
end
else begin : gen_blk2_else
assign out_packet_signals = 0;
if (ERROR_WIDTH > 0) begin : gen_blk6
if (CHANNEL_WIDTH > 0) begin : gen_blk7
assign in_payload = {in_data, in_error, in_channel};
assign {out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk7_else
assign out_channel = in_channel;
assign in_payload = {in_data, in_error};
assign {out_data, out_error} = out_payload;
end
end
else begin : gen_blk6_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk8
assign in_payload = {in_data, in_channel};
assign {out_data, out_channel} = out_payload;
end
else begin : gen_blk8_else
assign out_channel = in_channel;
assign in_payload = in_data;
assign out_data = out_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Memory-based FIFO storage
//
// To allow a ready latency of 0, the read index is
// obtained from the next read pointer and memory
// outputs are unregistered.
//
// If the empty latency is 1, we infer bypass logic
// around the memory so writes propagate to the
// outputs on the next cycle.
//
// Do not change the way this is coded: Quartus needs
// a perfect match to the template, and any attempt to
// refactor the two always blocks into one will break
// memory inference.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk9
if (EMPTY_LATENCY == 1) begin : gen_blk10
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] = in_payload;
internal_out_payload = mem[mem_rd_ptr];
end
end else begin : gen_blk10_else
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] <= in_payload;
internal_out_payload <= mem[mem_rd_ptr];
end
end
assign mem_rd_ptr = next_rd_ptr;
end else begin : gen_blk9_else
// --------------------------------------------------
// Register-based FIFO storage
//
// Uses a shift register as the storage element. Each
// shift register slot has a bit which indicates if
// the slot is occupied (credit to Sam H for the idea).
// The occupancy bits are contiguous and start from the
// lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep
// FIFO.
//
// Each slot is enabled during a read or when it
// is unoccupied. New data is always written to every
// going-to-be-empty slot (we keep track of which ones
// are actually useful with the occupancy bits). On a
// read we shift occupied slots.
//
// The exception is the last slot, which always gets
// new data when it is unoccupied.
// --------------------------------------------------
for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg
always @(posedge clk or posedge reset) begin
if (reset) begin
mem[i] <= 0;
end
else if (read || !mem_used[i]) begin
if (!mem_used[i+1])
mem[i] <= in_payload;
else
mem[i] <= mem[i+1];
end
end
end
always @(posedge clk, posedge reset) begin
if (reset) begin
mem[DEPTH-1] <= 0;
end
else begin
if (DEPTH == 1) begin
if (write)
mem[DEPTH-1] <= in_payload;
end
else if (!mem_used[DEPTH-1])
mem[DEPTH-1] <= in_payload;
end
end
end
endgenerate
assign read = internal_out_ready && internal_out_valid && ok_to_forward;
assign write = in_ready && in_valid;
// --------------------------------------------------
// Pointer Management
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk11
assign incremented_wr_ptr = wr_ptr + 1'b1;
assign incremented_rd_ptr = rd_ptr + 1'b1;
assign next_wr_ptr = drop_on_error ? curr_sop_ptr : write ? incremented_wr_ptr : wr_ptr;
assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr;
always @(posedge clk or posedge reset) begin
if (reset) begin
wr_ptr <= 0;
rd_ptr <= 0;
end
else begin
wr_ptr <= next_wr_ptr;
rd_ptr <= next_rd_ptr;
end
end
end else begin : gen_blk11_else
// --------------------------------------------------
// Shift Register Occupancy Bits
//
// Consider a 4-deep FIFO with 2 entries: 0011
// On a read and write, do not modify the bits.
// On a write, left-shift the bits to get 0111.
// On a read, right-shift the bits to get 0001.
//
// Also, on a write we set bit0 (the head), while
// clearing the tail on a read.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[0] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[0] <= 1;
else if (read) begin
if (DEPTH > 1)
mem_used[0] <= mem_used[1];
else
mem_used[0] <= 0;
end
end
end
end
if (DEPTH > 1) begin : gen_blk12
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[DEPTH-1] <= 0;
end
else begin
if (write ^ read) begin
mem_used[DEPTH-1] <= 0;
if (write)
mem_used[DEPTH-1] <= mem_used[DEPTH-2];
end
end
end
end
for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic
always @(posedge clk, posedge reset) begin
if (reset) begin
mem_used[i] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[i] <= mem_used[i-1];
else if (read)
mem_used[i] <= mem_used[i+1];
end
end
end
end
end
endgenerate
// --------------------------------------------------
// Memory FIFO Status Management
//
// Generates the full and empty signals from the
// pointers. The FIFO is full when the next write
// pointer will be equal to the read pointer after
// a write. Reading from a FIFO clears full.
//
// The FIFO is empty when the next read pointer will
// be equal to the write pointer after a read. Writing
// to a FIFO clears empty.
//
// A simultaneous read and write must not change any of
// the empty or full flags unless there is a drop on error event.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk13
always @* begin
next_full = full;
next_empty = empty;
if (read && !write) begin
next_full = 1'b0;
if (incremented_rd_ptr == wr_ptr)
next_empty = 1'b1;
end
if (write && !read) begin
if (!drop_on_error)
next_empty = 1'b0;
else if (curr_sop_ptr == rd_ptr) // drop on error and only 1 pkt in fifo
next_empty = 1'b1;
if (incremented_wr_ptr == rd_ptr && !drop_on_error)
next_full = 1'b1;
end
if (write && read && drop_on_error) begin
if (curr_sop_ptr == next_rd_ptr)
next_empty = 1'b1;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
empty <= 1;
full <= 0;
end
else begin
empty <= next_empty;
full <= next_full;
end
end
end else begin : gen_blk13_else
// --------------------------------------------------
// Register FIFO Status Management
//
// Full when the tail occupancy bit is 1. Empty when
// the head occupancy bit is 0.
// --------------------------------------------------
always @* begin
full = mem_used[DEPTH-1];
empty = !mem_used[0];
// ------------------------------------------
// For a single slot FIFO, reading clears the
// full status immediately.
// ------------------------------------------
if (DEPTH == 1)
full = mem_used[0] && !read;
internal_out_payload = mem[0];
// ------------------------------------------
// Writes clear empty immediately for lookahead modes.
// Note that we use in_valid instead of write to avoid
// combinational loops (in lookahead mode, qualifying
// with in_ready is meaningless).
//
// In a 1-deep FIFO, a possible combinational loop runs
// from write -> out_valid -> out_ready -> write
// ------------------------------------------
if (EMPTY_LATENCY == 0) begin
empty = !mem_used[0] && !in_valid;
if (!mem_used[0] && in_valid)
internal_out_payload = in_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Avalon-ST Signals
//
// The in_ready signal is straightforward.
//
// To match memory latency when empty latency > 1,
// out_valid assertions must be delayed by one clock
// cycle.
//
// Note: out_valid deassertions must not be delayed or
// the FIFO will underflow.
// --------------------------------------------------
assign in_ready = !full;
assign internal_out_ready = out_ready || !out_valid;
generate if (EMPTY_LATENCY > 1) begin : gen_blk14
always @(posedge clk or posedge reset) begin
if (reset)
internal_out_valid <= 0;
else begin
internal_out_valid <= !empty & ok_to_forward & ~drop_on_error;
if (read) begin
if (incremented_rd_ptr == wr_ptr)
internal_out_valid <= 1'b0;
end
end
end
end else begin : gen_blk14_else
always @* begin
internal_out_valid = !empty & ok_to_forward;
end
end
endgenerate
// --------------------------------------------------
// Single Output Pipeline Stage
//
// This output pipeline stage is enabled if the FIFO's
// empty latency is set to 3 (default). It is disabled
// for all other allowed latencies.
//
// Reason: The memory outputs are unregistered, so we have to
// register the output or fmax will drop if combinatorial
// logic is present on the output datapath.
//
// Q: The Avalon-ST spec says that I have to register my outputs
// But isn't the memory counted as a register?
// A: The path from the address lookup to the memory output is
// slow. Registering the memory outputs is a good idea.
//
// The registers get packed into the memory by the fitter
// which means minimal resources are consumed (the result
// is a altsyncram with registered outputs, available on
// all modern Altera devices).
//
// This output stage acts as an extra slot in the FIFO,
// and complicates the fill level.
// --------------------------------------------------
generate if (EMPTY_LATENCY == 3) begin : gen_blk15
always @(posedge clk or posedge reset) begin
if (reset) begin
out_valid <= 0;
out_payload <= 0;
end
else begin
if (internal_out_ready) begin
out_valid <= internal_out_valid & ok_to_forward;
out_payload <= internal_out_payload;
end
end
end
end
else begin : gen_blk15_else
always @* begin
out_valid = internal_out_valid;
out_payload = internal_out_payload;
end
end
endgenerate
// --------------------------------------------------
// Fill Level
//
// The fill level is calculated from the next write
// and read pointers to avoid unnecessary latency
// and logic.
//
// However, if the store-and-forward mode of the FIFO
// is enabled, the fill level is an up-down counter
// for fmax optimization reasons.
//
// If the output pipeline is enabled, the fill level
// must account for it, or we'll always be off by one.
// This may, or may not be important depending on the
// application.
//
// For now, we'll always calculate the exact fill level
// at the cost of an extra adder when the output stage
// is enabled.
// --------------------------------------------------
generate if (USE_FILL_LEVEL) begin : gen_blk16
wire [31:0] depth32;
assign depth32 = DEPTH;
if (USE_STORE_FORWARD) begin
reg [ADDR_WIDTH : 0] curr_packet_len_less_one;
// --------------------------------------------------
// We only drop on endofpacket. As long as we don't add to the fill
// level on the dropped endofpacket cycle, we can simply subtract
// (packet length - 1) from the fill level for dropped packets.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
curr_packet_len_less_one <= 0;
end else begin
if (write) begin
curr_packet_len_less_one <= curr_packet_len_less_one + 1'b1;
if (in_endofpacket)
curr_packet_len_less_one <= 0;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
fifo_fill_level <= 0;
end else if (drop_on_error) begin
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one;
if (read)
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one - 1'b1;
end else if (write && !read) begin
fifo_fill_level <= fifo_fill_level + 1'b1;
end else if (read && !write) begin
fifo_fill_level <= fifo_fill_level - 1'b1;
end
end
end else begin
always @(posedge clk or posedge reset) begin
if (reset)
fifo_fill_level <= 0;
else if (next_full & !drop_on_error)
fifo_fill_level <= depth32[ADDR_WIDTH:0];
else begin
fifo_fill_level[ADDR_WIDTH] <= 1'b0;
fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr;
end
end
end
always @* begin
fill_level = fifo_fill_level;
if (EMPTY_LATENCY == 3)
fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid};
end
end
else begin : gen_blk16_else
always @* begin
fill_level = 0;
end
end
endgenerate
generate if (USE_ALMOST_FULL_IF) begin : gen_blk17
assign almost_full_data = (fill_level >= almost_full_threshold);
end
else
assign almost_full_data = 0;
endgenerate
generate if (USE_ALMOST_EMPTY_IF) begin : gen_blk18
assign almost_empty_data = (fill_level <= almost_empty_threshold);
end
else
assign almost_empty_data = 0;
endgenerate
// --------------------------------------------------
// Avalon-MM Status & Control Connection Point
//
// Register map:
//
// | Addr | RW | 31 - 0 |
// | 0 | R | Fill level |
//
// The registering of this connection point means
// that there is a cycle of latency between
// reads/writes and the updating of the fill level.
// --------------------------------------------------
generate if (USE_STORE_FORWARD) begin : gen_blk19
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
cut_through_threshold <= 0;
drop_on_error_en <= 0;
csr_readdata <= 0;
pkt_mode <= 1'b1;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 5)
csr_readdata <= {31'b0, drop_on_error_en};
else if (csr_address == 4)
csr_readdata <= {8'b0, cut_through_threshold};
else if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b101)
drop_on_error_en <= csr_writedata[0];
else if(csr_address == 3'b100) begin
cut_through_threshold <= csr_writedata[23:0];
pkt_mode <= (csr_writedata[23:0] == 0);
end
else if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin : gen_blk19_else1
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
csr_readdata <= 0;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else begin : gen_blk19_else2
always @(posedge clk or posedge reset) begin
if (reset) begin
csr_readdata <= 0;
end
else if (csr_read) begin
csr_readdata <= 0;
if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
end
end
endgenerate
// --------------------------------------------------
// Store and forward logic
// --------------------------------------------------
// if the fifo gets full before the entire packet or the
// cut-threshold condition is met then start sending out
// data in order to avoid dead-lock situation
generate if (USE_STORE_FORWARD) begin : gen_blk20
assign wait_for_threshold = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ;
assign wait_for_pkt = pkt_cnt_eq_zero | (pkt_cnt_eq_one & out_pkt_leave);
assign ok_to_forward = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) :
~wait_for_threshold) | fifo_too_small_r;
assign in_pkt_eop_arrive = in_valid & in_ready & in_endofpacket;
assign in_pkt_start = in_valid & in_ready & in_startofpacket;
assign in_pkt_error = in_valid & in_ready & |in_error;
assign out_pkt_sop_leave = out_valid & out_ready & out_startofpacket;
assign out_pkt_leave = out_valid & out_ready & out_endofpacket;
assign fifo_too_small = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready;
// count packets coming and going into the fifo
always @(posedge clk or posedge reset) begin
if (reset) begin
pkt_cnt <= 0;
pkt_has_started <= 0;
sop_has_left_fifo <= 0;
fifo_too_small_r <= 0;
pkt_cnt_eq_zero <= 1'b1;
pkt_cnt_eq_one <= 1'b0;
fifo_fill_level_lt_cut_through_threshold <= 1'b1;
end
else begin
fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold;
fifo_too_small_r <= fifo_too_small;
if( in_pkt_eop_arrive )
sop_has_left_fifo <= 1'b0;
else if (out_pkt_sop_leave & pkt_cnt_eq_zero )
sop_has_left_fifo <= 1'b1;
if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin
pkt_cnt <= pkt_cnt + 1'b1;
pkt_cnt_eq_zero <= 0;
if (pkt_cnt == 0)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin
pkt_cnt <= pkt_cnt - 1'b1;
if (pkt_cnt == 1)
pkt_cnt_eq_zero <= 1'b1;
else
pkt_cnt_eq_zero <= 1'b0;
if (pkt_cnt == 2)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
if (in_pkt_start)
pkt_has_started <= 1'b1;
else if (in_pkt_eop_arrive)
pkt_has_started <= 1'b0;
end
end
// drop on error logic
always @(posedge clk or posedge reset) begin
if (reset) begin
sop_ptr <= 0;
error_in_pkt <= 0;
end
else begin
// save the location of the SOP
if ( in_pkt_start )
sop_ptr <= wr_ptr;
// remember if error in pkt
// log error only if packet has already started
if (in_pkt_eop_arrive)
error_in_pkt <= 1'b0;
else if ( in_pkt_error & (pkt_has_started | in_pkt_start))
error_in_pkt <= 1'b1;
end
end
assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive &
~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero);
assign curr_sop_ptr = (write && in_startofpacket && in_endofpacket) ? wr_ptr : sop_ptr;
end
else begin : gen_blk20_else
assign ok_to_forward = 1'b1;
assign drop_on_error = 1'b0;
if (ADDR_WIDTH <= 1)
assign curr_sop_ptr = 1'b0;
else
assign curr_sop_ptr = {ADDR_WIDTH - 1 { 1'b0 }};
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value
// --------------------------------------------------
function integer log2ceil;
input integer val;
reg[31:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i[30:0] << 1;
end
end
endfunction
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
// d_CS_evaluation_matrices.v for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Jinwoo Jeong <[email protected]>
// Ilyong Jung <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Jinwoo Jeong <[email protected]>
// Ilyong Jung <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: BCH Page Decoder
// Module Name: d_CS_shortening_matrix_alpha_to***, d_CS_evaluation_matrix_slot_***_alpha_to_***
// File Name: d_CS_evaluation_matrices.v
//
// Version: v1.0.1-256B_T14
//
// Description:
// - shortening matrix for BCH decoder: Chien search (CS)
// - evaluation matrix for BCH decoder: Chien search (CS)
// - for data area
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.1
// - minor modification for releasing
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`include "d_CS_parameters.vh"
`timescale 1ns / 1ps
/////////////////////////////////////////////
////////// GENERATED BY C PROGRAMA //////////
/////
///
// This file was generated by C program.
// total: 14
///
/////
////////// GENERATED BY C PROGRAMA //////////
/////////////////////////////////////////////
module d_CS_shortening_matrix_alpha_to_001(i_in, o_out); // shortened by alpha_to_1879, 1879
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[0] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[10] ^ i_in[11];
assign o_out[1] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[11];
assign o_out[2] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7];
assign o_out[3] = i_in[0] ^ i_in[1] ^ i_in[4] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10] ^ i_in[11];
assign o_out[4] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[5] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[6] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[7] = i_in[0] ^ i_in[5] ^ i_in[6] ^ i_in[7];
assign o_out[8] = i_in[0] ^ i_in[1] ^ i_in[6] ^ i_in[7] ^ i_in[8];
assign o_out[9] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[7] ^ i_in[8] ^ i_in[9];
assign o_out[10] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[11] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[9] ^ i_in[10] ^ i_in[11];
endmodule
module d_CS_shortening_matrix_alpha_to_002(i_in, o_out); // shortened by alpha_to_1879, 3758
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[2] ^ i_in[5] ^ i_in[7];
assign o_out[1] = i_in[0] ^ i_in[3] ^ i_in[6] ^ i_in[8];
assign o_out[2] = i_in[1] ^ i_in[4] ^ i_in[7] ^ i_in[9];
assign o_out[3] = i_in[7] ^ i_in[8] ^ i_in[10];
assign o_out[4] = i_in[2] ^ i_in[5] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[5] = i_in[3] ^ i_in[6] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[6] = i_in[4] ^ i_in[7] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[7] = i_in[0] ^ i_in[2] ^ i_in[7] ^ i_in[8] ^ i_in[10] ^ i_in[11];
assign o_out[8] = i_in[1] ^ i_in[3] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[9] = i_in[2] ^ i_in[4] ^ i_in[9] ^ i_in[10];
assign o_out[10] = i_in[0] ^ i_in[3] ^ i_in[5] ^ i_in[10] ^ i_in[11];
assign o_out[11] = i_in[1] ^ i_in[4] ^ i_in[6] ^ i_in[11];
endmodule
module d_CS_shortening_matrix_alpha_to_003(i_in, o_out); // shortened by alpha_to_1879, 1542
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[0] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[1] = i_in[0] ^ i_in[1] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[2] = i_in[1] ^ i_in[2] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[3] = i_in[0] ^ i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[9] ^ i_in[10];
assign o_out[4] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[9];
assign o_out[5] = i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[9] ^ i_in[10];
assign o_out[6] = i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10] ^ i_in[11];
assign o_out[7] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[10];
assign o_out[8] = i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[11];
assign o_out[9] = i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9];
assign o_out[10] = i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[11] = i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
endmodule
module d_CS_shortening_matrix_alpha_to_004(i_in, o_out); // shortened by alpha_to_1879, 3421
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[11];
assign o_out[1] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[7];
assign o_out[2] = i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[8];
assign o_out[3] = i_in[1] ^ i_in[2] ^ i_in[5] ^ i_in[7] ^ i_in[9] ^ i_in[11];
assign o_out[4] = i_in[0] ^ i_in[1] ^ i_in[4] ^ i_in[8] ^ i_in[10] ^ i_in[11];
assign o_out[5] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[5] ^ i_in[9] ^ i_in[11];
assign o_out[6] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[6] ^ i_in[10];
assign o_out[7] = i_in[1] ^ i_in[6] ^ i_in[7];
assign o_out[8] = i_in[0] ^ i_in[2] ^ i_in[7] ^ i_in[8];
assign o_out[9] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[8] ^ i_in[9];
assign o_out[10] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[9] ^ i_in[10];
assign o_out[11] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[10] ^ i_in[11];
endmodule
module d_CS_shortening_matrix_alpha_to_005(i_in, o_out); // shortened by alpha_to_1879, 1205
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[0] ^ i_in[3] ^ i_in[7] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[1] = i_in[1] ^ i_in[4] ^ i_in[8] ^ i_in[10] ^ i_in[11];
assign o_out[2] = i_in[0] ^ i_in[2] ^ i_in[5] ^ i_in[9] ^ i_in[11];
assign o_out[3] = i_in[0] ^ i_in[1] ^ i_in[6] ^ i_in[7] ^ i_in[9] ^ i_in[11];
assign o_out[4] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[5] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[9] ^ i_in[10];
assign o_out[6] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[10] ^ i_in[11];
assign o_out[7] = i_in[2] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[9] ^ i_in[10];
assign o_out[8] = i_in[3] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10] ^ i_in[11];
assign o_out[9] = i_in[0] ^ i_in[4] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[10] = i_in[1] ^ i_in[5] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[11] = i_in[2] ^ i_in[6] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
endmodule
module d_CS_shortening_matrix_alpha_to_006(i_in, o_out); // shortened by alpha_to_1879, 3084
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[1] = i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[2] = i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[3] = i_in[4] ^ i_in[6] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[4] = i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[8] ^ i_in[10];
assign o_out[5] = i_in[0] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[9] ^ i_in[11];
assign o_out[6] = i_in[1] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[10];
assign o_out[7] = i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[9];
assign o_out[8] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[10];
assign o_out[9] = i_in[0] ^ i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[11];
assign o_out[10] = i_in[1] ^ i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[9];
assign o_out[11] = i_in[2] ^ i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10];
endmodule
module d_CS_shortening_matrix_alpha_to_007(i_in, o_out); // shortened by alpha_to_1879, 868
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[9] ^ i_in[11];
assign o_out[1] = i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[10];
assign o_out[2] = i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[3] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[4] = i_in[0] ^ i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[8] ^ i_in[9];
assign o_out[5] = i_in[1] ^ i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[6] = i_in[2] ^ i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[7] = i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[6] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[8] = i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[7] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[9] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[8] ^ i_in[10] ^ i_in[11];
assign o_out[10] = i_in[0] ^ i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[9] ^ i_in[11];
assign o_out[11] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[10];
endmodule
module d_CS_shortening_matrix_alpha_to_008(i_in, o_out); // shortened by alpha_to_1879, 2747
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[0] ^ i_in[3] ^ i_in[6] ^ i_in[9] ^ i_in[10];
assign o_out[1] = i_in[1] ^ i_in[4] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[2] = i_in[0] ^ i_in[2] ^ i_in[5] ^ i_in[8] ^ i_in[11];
assign o_out[3] = i_in[0] ^ i_in[1] ^ i_in[10];
assign o_out[4] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[5] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[6] = i_in[0] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[8] ^ i_in[11];
assign o_out[7] = i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[10];
assign o_out[8] = i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[11];
assign o_out[9] = i_in[0] ^ i_in[3] ^ i_in[6] ^ i_in[7];
assign o_out[10] = i_in[1] ^ i_in[4] ^ i_in[7] ^ i_in[8];
assign o_out[11] = i_in[2] ^ i_in[5] ^ i_in[8] ^ i_in[9];
endmodule
module d_CS_shortening_matrix_alpha_to_009(i_in, o_out); // shortened by alpha_to_1879, 531
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[3] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[1] = i_in[4] ^ i_in[9] ^ i_in[10];
assign o_out[2] = i_in[5] ^ i_in[10] ^ i_in[11];
assign o_out[3] = i_in[0] ^ i_in[3] ^ i_in[6] ^ i_in[8] ^ i_in[9];
assign o_out[4] = i_in[1] ^ i_in[3] ^ i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[10] ^ i_in[11];
assign o_out[5] = i_in[2] ^ i_in[4] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[6] = i_in[3] ^ i_in[5] ^ i_in[6] ^ i_in[9] ^ i_in[10];
assign o_out[7] = i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[8] = i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[9] = i_in[0] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[10] = i_in[1] ^ i_in[6] ^ i_in[7] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[11] = i_in[2] ^ i_in[7] ^ i_in[8] ^ i_in[10] ^ i_in[11];
endmodule
module d_CS_shortening_matrix_alpha_to_010(i_in, o_out); // shortened by alpha_to_1879, 2410
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[0] ^ i_in[3] ^ i_in[7] ^ i_in[8];
assign o_out[1] = i_in[0] ^ i_in[1] ^ i_in[4] ^ i_in[8] ^ i_in[9];
assign o_out[2] = i_in[1] ^ i_in[2] ^ i_in[5] ^ i_in[9] ^ i_in[10];
assign o_out[3] = i_in[2] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10] ^ i_in[11];
assign o_out[4] = i_in[9] ^ i_in[11];
assign o_out[5] = i_in[0] ^ i_in[10];
assign o_out[6] = i_in[1] ^ i_in[11];
assign o_out[7] = i_in[2] ^ i_in[3] ^ i_in[7] ^ i_in[8];
assign o_out[8] = i_in[3] ^ i_in[4] ^ i_in[8] ^ i_in[9];
assign o_out[9] = i_in[0] ^ i_in[4] ^ i_in[5] ^ i_in[9] ^ i_in[10];
assign o_out[10] = i_in[1] ^ i_in[5] ^ i_in[6] ^ i_in[10] ^ i_in[11];
assign o_out[11] = i_in[2] ^ i_in[6] ^ i_in[7] ^ i_in[11];
endmodule
module d_CS_shortening_matrix_alpha_to_011(i_in, o_out); // shortened by alpha_to_1879, 194
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[2] ^ i_in[3] ^ i_in[6] ^ i_in[7];
assign o_out[1] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[7] ^ i_in[8];
assign o_out[2] = i_in[0] ^ i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[8] ^ i_in[9];
assign o_out[3] = i_in[1] ^ i_in[3] ^ i_in[5] ^ i_in[7] ^ i_in[9] ^ i_in[10];
assign o_out[4] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[10] ^ i_in[11];
assign o_out[5] = i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[6] = i_in[0] ^ i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[9] ^ i_in[10];
assign o_out[7] = i_in[1] ^ i_in[2] ^ i_in[10] ^ i_in[11];
assign o_out[8] = i_in[2] ^ i_in[3] ^ i_in[11];
assign o_out[9] = i_in[0] ^ i_in[3] ^ i_in[4];
assign o_out[10] = i_in[0] ^ i_in[1] ^ i_in[4] ^ i_in[5];
assign o_out[11] = i_in[1] ^ i_in[2] ^ i_in[5] ^ i_in[6];
endmodule
module d_CS_shortening_matrix_alpha_to_012(i_in, o_out); // shortened by alpha_to_1879, 2073
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[5] ^ i_in[7] ^ i_in[8] ^ i_in[9];
assign o_out[1] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[6] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[2] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[7] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[3] = i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[4] = i_in[1] ^ i_in[2] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[5] = i_in[0] ^ i_in[2] ^ i_in[3] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[6] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[4] ^ i_in[8] ^ i_in[11];
assign o_out[7] = i_in[0] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[7] ^ i_in[8];
assign o_out[8] = i_in[1] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[8] ^ i_in[9];
assign o_out[9] = i_in[0] ^ i_in[2] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[9] ^ i_in[10];
assign o_out[10] = i_in[1] ^ i_in[3] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[11] = i_in[0] ^ i_in[2] ^ i_in[4] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[11];
endmodule
module d_CS_shortening_matrix_alpha_to_013(i_in, o_out); // shortened by alpha_to_1879, 3952
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[10];
assign o_out[1] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[11];
assign o_out[2] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4];
assign o_out[3] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[10];
assign o_out[4] = i_in[2] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[10] ^ i_in[11];
assign o_out[5] = i_in[0] ^ i_in[3] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[11];
assign o_out[6] = i_in[0] ^ i_in[1] ^ i_in[4] ^ i_in[6] ^ i_in[7] ^ i_in[8];
assign o_out[7] = i_in[5] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[8] = i_in[6] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[9] = i_in[7] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[10] = i_in[0] ^ i_in[8] ^ i_in[10] ^ i_in[11];
assign o_out[11] = i_in[0] ^ i_in[1] ^ i_in[9] ^ i_in[11];
endmodule
module d_CS_shortening_matrix_alpha_to_014(i_in, o_out); // shortened by alpha_to_1879, 1736
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[8] ^ i_in[9];
assign o_out[1] = i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[2] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[3] = i_in[0] ^ i_in[2] ^ i_in[3] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[4] = i_in[2] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[5] = i_in[3] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[6] = i_in[0] ^ i_in[4] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[7] = i_in[0] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[7] ^ i_in[9] ^ i_in[11];
assign o_out[8] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[8] ^ i_in[10];
assign o_out[9] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[9] ^ i_in[11];
assign o_out[10] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[10];
assign o_out[11] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[11];
endmodule
/////////////////////////////////////////////
////////// GENERATED BY C PROGRAMA //////////
/////
///
// This file was generated by C program.
// total: 112
///
/////
////////// GENERATED BY C PROGRAMA //////////
/////////////////////////////////////////////
module d_CS_evaluation_matrix_slot_001_alpha_to_001(i_in, o_out); // evaluated by alpha_to_1, 1
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[11];
assign o_out[1] = i_in[0];
assign o_out[2] = i_in[1];
assign o_out[3] = i_in[2] ^ i_in[11];
assign o_out[4] = i_in[3] ^ i_in[11];
assign o_out[5] = i_in[4];
assign o_out[6] = i_in[5];
assign o_out[7] = i_in[6] ^ i_in[11];
assign o_out[8] = i_in[7];
assign o_out[9] = i_in[8];
assign o_out[10] = i_in[9];
assign o_out[11] = i_in[10];
endmodule
module d_CS_evaluation_matrix_slot_001_alpha_to_002(i_in, o_out); // evaluated by alpha_to_1, 2
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[10];
assign o_out[1] = i_in[11];
assign o_out[2] = i_in[0];
assign o_out[3] = i_in[1] ^ i_in[10];
assign o_out[4] = i_in[2] ^ i_in[10] ^ i_in[11];
assign o_out[5] = i_in[3] ^ i_in[11];
assign o_out[6] = i_in[4];
assign o_out[7] = i_in[5] ^ i_in[10];
assign o_out[8] = i_in[6] ^ i_in[11];
assign o_out[9] = i_in[7];
assign o_out[10] = i_in[8];
assign o_out[11] = i_in[9];
endmodule
module d_CS_evaluation_matrix_slot_001_alpha_to_003(i_in, o_out); // evaluated by alpha_to_1, 3
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[9];
assign o_out[1] = i_in[10];
assign o_out[2] = i_in[11];
assign o_out[3] = i_in[0] ^ i_in[9];
assign o_out[4] = i_in[1] ^ i_in[9] ^ i_in[10];
assign o_out[5] = i_in[2] ^ i_in[10] ^ i_in[11];
assign o_out[6] = i_in[3] ^ i_in[11];
assign o_out[7] = i_in[4] ^ i_in[9];
assign o_out[8] = i_in[5] ^ i_in[10];
assign o_out[9] = i_in[6] ^ i_in[11];
assign o_out[10] = i_in[7];
assign o_out[11] = i_in[8];
endmodule
module d_CS_evaluation_matrix_slot_001_alpha_to_004(i_in, o_out); // evaluated by alpha_to_1, 4
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[8];
assign o_out[1] = i_in[9];
assign o_out[2] = i_in[10];
assign o_out[3] = i_in[8] ^ i_in[11];
assign o_out[4] = i_in[0] ^ i_in[8] ^ i_in[9];
assign o_out[5] = i_in[1] ^ i_in[9] ^ i_in[10];
assign o_out[6] = i_in[2] ^ i_in[10] ^ i_in[11];
assign o_out[7] = i_in[3] ^ i_in[8] ^ i_in[11];
assign o_out[8] = i_in[4] ^ i_in[9];
assign o_out[9] = i_in[5] ^ i_in[10];
assign o_out[10] = i_in[6] ^ i_in[11];
assign o_out[11] = i_in[7];
endmodule
module d_CS_evaluation_matrix_slot_001_alpha_to_005(i_in, o_out); // evaluated by alpha_to_1, 5
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[7];
assign o_out[1] = i_in[8];
assign o_out[2] = i_in[9];
assign o_out[3] = i_in[7] ^ i_in[10];
assign o_out[4] = i_in[7] ^ i_in[8] ^ i_in[11];
assign o_out[5] = i_in[0] ^ i_in[8] ^ i_in[9];
assign o_out[6] = i_in[1] ^ i_in[9] ^ i_in[10];
assign o_out[7] = i_in[2] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[8] = i_in[3] ^ i_in[8] ^ i_in[11];
assign o_out[9] = i_in[4] ^ i_in[9];
assign o_out[10] = i_in[5] ^ i_in[10];
assign o_out[11] = i_in[6] ^ i_in[11];
endmodule
module d_CS_evaluation_matrix_slot_001_alpha_to_006(i_in, o_out); // evaluated by alpha_to_1, 6
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[6] ^ i_in[11];
assign o_out[1] = i_in[7];
assign o_out[2] = i_in[8];
assign o_out[3] = i_in[6] ^ i_in[9] ^ i_in[11];
assign o_out[4] = i_in[6] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[5] = i_in[7] ^ i_in[8] ^ i_in[11];
assign o_out[6] = i_in[0] ^ i_in[8] ^ i_in[9];
assign o_out[7] = i_in[1] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[8] = i_in[2] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[9] = i_in[3] ^ i_in[8] ^ i_in[11];
assign o_out[10] = i_in[4] ^ i_in[9];
assign o_out[11] = i_in[5] ^ i_in[10];
endmodule
module d_CS_evaluation_matrix_slot_001_alpha_to_007(i_in, o_out); // evaluated by alpha_to_1, 7
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[5] ^ i_in[10];
assign o_out[1] = i_in[6] ^ i_in[11];
assign o_out[2] = i_in[7];
assign o_out[3] = i_in[5] ^ i_in[8] ^ i_in[10];
assign o_out[4] = i_in[5] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[5] = i_in[6] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[6] = i_in[7] ^ i_in[8] ^ i_in[11];
assign o_out[7] = i_in[0] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[8] = i_in[1] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[9] = i_in[2] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[10] = i_in[3] ^ i_in[8] ^ i_in[11];
assign o_out[11] = i_in[4] ^ i_in[9];
endmodule
module d_CS_evaluation_matrix_slot_001_alpha_to_008(i_in, o_out); // evaluated by alpha_to_1, 8
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[4] ^ i_in[9];
assign o_out[1] = i_in[5] ^ i_in[10];
assign o_out[2] = i_in[6] ^ i_in[11];
assign o_out[3] = i_in[4] ^ i_in[7] ^ i_in[9];
assign o_out[4] = i_in[4] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[5] = i_in[5] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[6] = i_in[6] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[7] = i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[8] = i_in[0] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[9] = i_in[1] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[10] = i_in[2] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[11] = i_in[3] ^ i_in[8] ^ i_in[11];
endmodule
module d_CS_evaluation_matrix_slot_001_alpha_to_009(i_in, o_out); // evaluated by alpha_to_1, 9
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[3] ^ i_in[8] ^ i_in[11];
assign o_out[1] = i_in[4] ^ i_in[9];
assign o_out[2] = i_in[5] ^ i_in[10];
assign o_out[3] = i_in[3] ^ i_in[6] ^ i_in[8];
assign o_out[4] = i_in[3] ^ i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[5] = i_in[4] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[6] = i_in[5] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[7] = i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10];
assign o_out[8] = i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[9] = i_in[0] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[10] = i_in[1] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[11] = i_in[2] ^ i_in[7] ^ i_in[10] ^ i_in[11];
endmodule
module d_CS_evaluation_matrix_slot_001_alpha_to_010(i_in, o_out); // evaluated by alpha_to_1, 10
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[2] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[1] = i_in[3] ^ i_in[8] ^ i_in[11];
assign o_out[2] = i_in[4] ^ i_in[9];
assign o_out[3] = i_in[2] ^ i_in[5] ^ i_in[7] ^ i_in[11];
assign o_out[4] = i_in[2] ^ i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10] ^ i_in[11];
assign o_out[5] = i_in[3] ^ i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[6] = i_in[4] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[7] = i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[9];
assign o_out[8] = i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10];
assign o_out[9] = i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[10] = i_in[0] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[11] = i_in[1] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
endmodule
module d_CS_evaluation_matrix_slot_001_alpha_to_011(i_in, o_out); // evaluated by alpha_to_1, 11
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[1] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[1] = i_in[2] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[2] = i_in[3] ^ i_in[8] ^ i_in[11];
assign o_out[3] = i_in[1] ^ i_in[4] ^ i_in[6] ^ i_in[10] ^ i_in[11];
assign o_out[4] = i_in[1] ^ i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[9] ^ i_in[10];
assign o_out[5] = i_in[2] ^ i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10] ^ i_in[11];
assign o_out[6] = i_in[3] ^ i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[7] = i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[11];
assign o_out[8] = i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[9];
assign o_out[9] = i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10];
assign o_out[10] = i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[11] = i_in[0] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[10];
endmodule
module d_CS_evaluation_matrix_slot_001_alpha_to_012(i_in, o_out); // evaluated by alpha_to_1, 12
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[0] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[1] = i_in[1] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[2] = i_in[2] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[3] = i_in[0] ^ i_in[3] ^ i_in[5] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[4] = i_in[0] ^ i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[5] = i_in[1] ^ i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[9] ^ i_in[10];
assign o_out[6] = i_in[2] ^ i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10] ^ i_in[11];
assign o_out[7] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[8] = i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[11];
assign o_out[9] = i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[9];
assign o_out[10] = i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10];
assign o_out[11] = i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
endmodule
module d_CS_evaluation_matrix_slot_001_alpha_to_013(i_in, o_out); // evaluated by alpha_to_1, 13
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[1] = i_in[0] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[2] = i_in[1] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[3] = i_in[2] ^ i_in[4] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[4] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[8] ^ i_in[10];
assign o_out[5] = i_in[0] ^ i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[6] = i_in[1] ^ i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[9] ^ i_in[10];
assign o_out[7] = i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[9] ^ i_in[10];
assign o_out[8] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[9] = i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[11];
assign o_out[10] = i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[9];
assign o_out[11] = i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10];
endmodule
module d_CS_evaluation_matrix_slot_001_alpha_to_014(i_in, o_out); // evaluated by alpha_to_1, 14
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10];
assign o_out[1] = i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[2] = i_in[0] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[3] = i_in[1] ^ i_in[3] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[4] = i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[7] ^ i_in[9];
assign o_out[5] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[8] ^ i_in[10];
assign o_out[6] = i_in[0] ^ i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[7] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[8] ^ i_in[9];
assign o_out[8] = i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[9] ^ i_in[10];
assign o_out[9] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[10] = i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[11];
assign o_out[11] = i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[9];
endmodule
module d_CS_evaluation_matrix_slot_002_alpha_to_001(i_in, o_out); // evaluated by alpha_to_2, 2
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[10];
assign o_out[1] = i_in[11];
assign o_out[2] = i_in[0];
assign o_out[3] = i_in[1] ^ i_in[10];
assign o_out[4] = i_in[2] ^ i_in[10] ^ i_in[11];
assign o_out[5] = i_in[3] ^ i_in[11];
assign o_out[6] = i_in[4];
assign o_out[7] = i_in[5] ^ i_in[10];
assign o_out[8] = i_in[6] ^ i_in[11];
assign o_out[9] = i_in[7];
assign o_out[10] = i_in[8];
assign o_out[11] = i_in[9];
endmodule
module d_CS_evaluation_matrix_slot_002_alpha_to_002(i_in, o_out); // evaluated by alpha_to_2, 4
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[8];
assign o_out[1] = i_in[9];
assign o_out[2] = i_in[10];
assign o_out[3] = i_in[8] ^ i_in[11];
assign o_out[4] = i_in[0] ^ i_in[8] ^ i_in[9];
assign o_out[5] = i_in[1] ^ i_in[9] ^ i_in[10];
assign o_out[6] = i_in[2] ^ i_in[10] ^ i_in[11];
assign o_out[7] = i_in[3] ^ i_in[8] ^ i_in[11];
assign o_out[8] = i_in[4] ^ i_in[9];
assign o_out[9] = i_in[5] ^ i_in[10];
assign o_out[10] = i_in[6] ^ i_in[11];
assign o_out[11] = i_in[7];
endmodule
module d_CS_evaluation_matrix_slot_002_alpha_to_003(i_in, o_out); // evaluated by alpha_to_2, 6
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[6] ^ i_in[11];
assign o_out[1] = i_in[7];
assign o_out[2] = i_in[8];
assign o_out[3] = i_in[6] ^ i_in[9] ^ i_in[11];
assign o_out[4] = i_in[6] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[5] = i_in[7] ^ i_in[8] ^ i_in[11];
assign o_out[6] = i_in[0] ^ i_in[8] ^ i_in[9];
assign o_out[7] = i_in[1] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[8] = i_in[2] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[9] = i_in[3] ^ i_in[8] ^ i_in[11];
assign o_out[10] = i_in[4] ^ i_in[9];
assign o_out[11] = i_in[5] ^ i_in[10];
endmodule
module d_CS_evaluation_matrix_slot_002_alpha_to_004(i_in, o_out); // evaluated by alpha_to_2, 8
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[4] ^ i_in[9];
assign o_out[1] = i_in[5] ^ i_in[10];
assign o_out[2] = i_in[6] ^ i_in[11];
assign o_out[3] = i_in[4] ^ i_in[7] ^ i_in[9];
assign o_out[4] = i_in[4] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[5] = i_in[5] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[6] = i_in[6] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[7] = i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[8] = i_in[0] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[9] = i_in[1] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[10] = i_in[2] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[11] = i_in[3] ^ i_in[8] ^ i_in[11];
endmodule
module d_CS_evaluation_matrix_slot_002_alpha_to_005(i_in, o_out); // evaluated by alpha_to_2, 10
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[2] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[1] = i_in[3] ^ i_in[8] ^ i_in[11];
assign o_out[2] = i_in[4] ^ i_in[9];
assign o_out[3] = i_in[2] ^ i_in[5] ^ i_in[7] ^ i_in[11];
assign o_out[4] = i_in[2] ^ i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10] ^ i_in[11];
assign o_out[5] = i_in[3] ^ i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[6] = i_in[4] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[7] = i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[9];
assign o_out[8] = i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10];
assign o_out[9] = i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[10] = i_in[0] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[11] = i_in[1] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
endmodule
module d_CS_evaluation_matrix_slot_002_alpha_to_006(i_in, o_out); // evaluated by alpha_to_2, 12
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[0] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[1] = i_in[1] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[2] = i_in[2] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[3] = i_in[0] ^ i_in[3] ^ i_in[5] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[4] = i_in[0] ^ i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[5] = i_in[1] ^ i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[9] ^ i_in[10];
assign o_out[6] = i_in[2] ^ i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10] ^ i_in[11];
assign o_out[7] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[8] = i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[11];
assign o_out[9] = i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[9];
assign o_out[10] = i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10];
assign o_out[11] = i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
endmodule
module d_CS_evaluation_matrix_slot_002_alpha_to_007(i_in, o_out); // evaluated by alpha_to_2, 14
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10];
assign o_out[1] = i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[2] = i_in[0] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[3] = i_in[1] ^ i_in[3] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[4] = i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[7] ^ i_in[9];
assign o_out[5] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[8] ^ i_in[10];
assign o_out[6] = i_in[0] ^ i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[7] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[8] ^ i_in[9];
assign o_out[8] = i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[9] ^ i_in[10];
assign o_out[9] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[10] = i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[11];
assign o_out[11] = i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[9];
endmodule
module d_CS_evaluation_matrix_slot_002_alpha_to_008(i_in, o_out); // evaluated by alpha_to_2, 16
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[11];
assign o_out[1] = i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[9];
assign o_out[2] = i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10];
assign o_out[3] = i_in[1] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[9];
assign o_out[4] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[5] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[11];
assign o_out[6] = i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[7] ^ i_in[9];
assign o_out[7] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[8] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[11];
assign o_out[9] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[8] ^ i_in[9];
assign o_out[10] = i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[9] ^ i_in[10];
assign o_out[11] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[10] ^ i_in[11];
endmodule
module d_CS_evaluation_matrix_slot_002_alpha_to_009(i_in, o_out); // evaluated by alpha_to_2, 18
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[9] ^ i_in[10];
assign o_out[1] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[2] = i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[11];
assign o_out[3] = i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[10];
assign o_out[4] = i_in[0] ^ i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[5] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[6] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[7] = i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[8] = i_in[0] ^ i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[9] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[10] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[11];
assign o_out[11] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[8] ^ i_in[9];
endmodule
module d_CS_evaluation_matrix_slot_002_alpha_to_010(i_in, o_out); // evaluated by alpha_to_2, 20
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[11];
assign o_out[1] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[8] ^ i_in[9];
assign o_out[2] = i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[9] ^ i_in[10];
assign o_out[3] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[8] ^ i_in[10];
assign o_out[4] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9];
assign o_out[5] = i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[6] = i_in[0] ^ i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[7] = i_in[2] ^ i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[8] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[9] = i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[10] = i_in[0] ^ i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[11] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[10] ^ i_in[11];
endmodule
module d_CS_evaluation_matrix_slot_002_alpha_to_011(i_in, o_out); // evaluated by alpha_to_2, 22
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[0] ^ i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[1] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[2] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[11];
assign o_out[3] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[6] ^ i_in[8] ^ i_in[10] ^ i_in[11];
assign o_out[4] = i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[10];
assign o_out[5] = i_in[0] ^ i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[11];
assign o_out[6] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9];
assign o_out[7] = i_in[0] ^ i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[11];
assign o_out[8] = i_in[1] ^ i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9];
assign o_out[9] = i_in[2] ^ i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[10] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[11] = i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
endmodule
module d_CS_evaluation_matrix_slot_002_alpha_to_012(i_in, o_out); // evaluated by alpha_to_2, 24
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[1] = i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[2] = i_in[0] ^ i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[3] = i_in[1] ^ i_in[4] ^ i_in[6] ^ i_in[8] ^ i_in[9];
assign o_out[4] = i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[8] ^ i_in[11];
assign o_out[5] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[9];
assign o_out[6] = i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[10];
assign o_out[7] = i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[9] ^ i_in[10];
assign o_out[8] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[9] = i_in[0] ^ i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[11];
assign o_out[10] = i_in[1] ^ i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9];
assign o_out[11] = i_in[2] ^ i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10];
endmodule
module d_CS_evaluation_matrix_slot_002_alpha_to_013(i_in, o_out); // evaluated by alpha_to_2, 26
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[1] ^ i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9];
assign o_out[1] = i_in[2] ^ i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[2] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[3] = i_in[2] ^ i_in[4] ^ i_in[6] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[4] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[6] ^ i_in[9] ^ i_in[11];
assign o_out[5] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[7] ^ i_in[10];
assign o_out[6] = i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[8] ^ i_in[11];
assign o_out[7] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[7] ^ i_in[8];
assign o_out[8] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[8] ^ i_in[9];
assign o_out[9] = i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[9] ^ i_in[10];
assign o_out[10] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[11] = i_in[0] ^ i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[11];
endmodule
module d_CS_evaluation_matrix_slot_002_alpha_to_014(i_in, o_out); // evaluated by alpha_to_2, 28
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[1] = i_in[0] ^ i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[11];
assign o_out[2] = i_in[1] ^ i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9];
assign o_out[3] = i_in[0] ^ i_in[2] ^ i_in[4] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[4] = i_in[0] ^ i_in[1] ^ i_in[4] ^ i_in[7] ^ i_in[9] ^ i_in[11];
assign o_out[5] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[5] ^ i_in[8] ^ i_in[10];
assign o_out[6] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[6] ^ i_in[9] ^ i_in[11];
assign o_out[7] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[11];
assign o_out[8] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[6] ^ i_in[7];
assign o_out[9] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[7] ^ i_in[8];
assign o_out[10] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[8] ^ i_in[9];
assign o_out[11] = i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[9] ^ i_in[10];
endmodule
module d_CS_evaluation_matrix_slot_003_alpha_to_001(i_in, o_out); // evaluated by alpha_to_3, 3
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[9];
assign o_out[1] = i_in[10];
assign o_out[2] = i_in[11];
assign o_out[3] = i_in[0] ^ i_in[9];
assign o_out[4] = i_in[1] ^ i_in[9] ^ i_in[10];
assign o_out[5] = i_in[2] ^ i_in[10] ^ i_in[11];
assign o_out[6] = i_in[3] ^ i_in[11];
assign o_out[7] = i_in[4] ^ i_in[9];
assign o_out[8] = i_in[5] ^ i_in[10];
assign o_out[9] = i_in[6] ^ i_in[11];
assign o_out[10] = i_in[7];
assign o_out[11] = i_in[8];
endmodule
module d_CS_evaluation_matrix_slot_003_alpha_to_002(i_in, o_out); // evaluated by alpha_to_3, 6
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[6] ^ i_in[11];
assign o_out[1] = i_in[7];
assign o_out[2] = i_in[8];
assign o_out[3] = i_in[6] ^ i_in[9] ^ i_in[11];
assign o_out[4] = i_in[6] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[5] = i_in[7] ^ i_in[8] ^ i_in[11];
assign o_out[6] = i_in[0] ^ i_in[8] ^ i_in[9];
assign o_out[7] = i_in[1] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[8] = i_in[2] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[9] = i_in[3] ^ i_in[8] ^ i_in[11];
assign o_out[10] = i_in[4] ^ i_in[9];
assign o_out[11] = i_in[5] ^ i_in[10];
endmodule
module d_CS_evaluation_matrix_slot_003_alpha_to_003(i_in, o_out); // evaluated by alpha_to_3, 9
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[3] ^ i_in[8] ^ i_in[11];
assign o_out[1] = i_in[4] ^ i_in[9];
assign o_out[2] = i_in[5] ^ i_in[10];
assign o_out[3] = i_in[3] ^ i_in[6] ^ i_in[8];
assign o_out[4] = i_in[3] ^ i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[5] = i_in[4] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[6] = i_in[5] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[7] = i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10];
assign o_out[8] = i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[9] = i_in[0] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[10] = i_in[1] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[11] = i_in[2] ^ i_in[7] ^ i_in[10] ^ i_in[11];
endmodule
module d_CS_evaluation_matrix_slot_003_alpha_to_004(i_in, o_out); // evaluated by alpha_to_3, 12
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[0] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[1] = i_in[1] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[2] = i_in[2] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[3] = i_in[0] ^ i_in[3] ^ i_in[5] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[4] = i_in[0] ^ i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[5] = i_in[1] ^ i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[9] ^ i_in[10];
assign o_out[6] = i_in[2] ^ i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10] ^ i_in[11];
assign o_out[7] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[8] = i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[11];
assign o_out[9] = i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[9];
assign o_out[10] = i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10];
assign o_out[11] = i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
endmodule
module d_CS_evaluation_matrix_slot_003_alpha_to_005(i_in, o_out); // evaluated by alpha_to_3, 15
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[9];
assign o_out[1] = i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10];
assign o_out[2] = i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[3] = i_in[0] ^ i_in[2] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10];
assign o_out[4] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[11];
assign o_out[5] = i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[7] ^ i_in[9];
assign o_out[6] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[8] ^ i_in[10];
assign o_out[7] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[11];
assign o_out[8] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[8] ^ i_in[9];
assign o_out[9] = i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[9] ^ i_in[10];
assign o_out[10] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[11] = i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[11];
endmodule
module d_CS_evaluation_matrix_slot_003_alpha_to_006(i_in, o_out); // evaluated by alpha_to_3, 18
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[9] ^ i_in[10];
assign o_out[1] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[2] = i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[11];
assign o_out[3] = i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[10];
assign o_out[4] = i_in[0] ^ i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[5] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[6] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[7] = i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[8] = i_in[0] ^ i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[9] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[10] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[11];
assign o_out[11] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[8] ^ i_in[9];
endmodule
module d_CS_evaluation_matrix_slot_003_alpha_to_007(i_in, o_out); // evaluated by alpha_to_3, 21
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[1] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[11];
assign o_out[2] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[8] ^ i_in[9];
assign o_out[3] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[7] ^ i_in[9] ^ i_in[11];
assign o_out[4] = i_in[0] ^ i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[11];
assign o_out[5] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9];
assign o_out[6] = i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[7] = i_in[1] ^ i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9];
assign o_out[8] = i_in[2] ^ i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[9] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[10] = i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[11] = i_in[0] ^ i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
endmodule
module d_CS_evaluation_matrix_slot_003_alpha_to_008(i_in, o_out); // evaluated by alpha_to_3, 24
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[1] = i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[2] = i_in[0] ^ i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[3] = i_in[1] ^ i_in[4] ^ i_in[6] ^ i_in[8] ^ i_in[9];
assign o_out[4] = i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[8] ^ i_in[11];
assign o_out[5] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[9];
assign o_out[6] = i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[10];
assign o_out[7] = i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[9] ^ i_in[10];
assign o_out[8] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[9] = i_in[0] ^ i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[11];
assign o_out[10] = i_in[1] ^ i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9];
assign o_out[11] = i_in[2] ^ i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10];
endmodule
module d_CS_evaluation_matrix_slot_003_alpha_to_009(i_in, o_out); // evaluated by alpha_to_3, 27
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[0] ^ i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[11];
assign o_out[1] = i_in[1] ^ i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9];
assign o_out[2] = i_in[2] ^ i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[3] = i_in[1] ^ i_in[3] ^ i_in[5] ^ i_in[6] ^ i_in[9] ^ i_in[10];
assign o_out[4] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[5] ^ i_in[8] ^ i_in[10];
assign o_out[5] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[6] ^ i_in[9] ^ i_in[11];
assign o_out[6] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[7] ^ i_in[10];
assign o_out[7] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[6] ^ i_in[7];
assign o_out[8] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[7] ^ i_in[8];
assign o_out[9] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[8] ^ i_in[9];
assign o_out[10] = i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[9] ^ i_in[10];
assign o_out[11] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[10] ^ i_in[11];
endmodule
module d_CS_evaluation_matrix_slot_003_alpha_to_010(i_in, o_out); // evaluated by alpha_to_3, 30
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[8] ^ i_in[9];
assign o_out[1] = i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[9] ^ i_in[10];
assign o_out[2] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[3] = i_in[0] ^ i_in[2] ^ i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[9] ^ i_in[11];
assign o_out[4] = i_in[2] ^ i_in[5] ^ i_in[7] ^ i_in[9] ^ i_in[10];
assign o_out[5] = i_in[0] ^ i_in[3] ^ i_in[6] ^ i_in[8] ^ i_in[10] ^ i_in[11];
assign o_out[6] = i_in[0] ^ i_in[1] ^ i_in[4] ^ i_in[7] ^ i_in[9] ^ i_in[11];
assign o_out[7] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[9] ^ i_in[10];
assign o_out[8] = i_in[0] ^ i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[10] ^ i_in[11];
assign o_out[9] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[11];
assign o_out[10] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[6] ^ i_in[7];
assign o_out[11] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[7] ^ i_in[8];
endmodule
module d_CS_evaluation_matrix_slot_003_alpha_to_011(i_in, o_out); // evaluated by alpha_to_3, 33
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[11];
assign o_out[1] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[6] ^ i_in[7];
assign o_out[2] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[7] ^ i_in[8];
assign o_out[3] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[4] = i_in[2] ^ i_in[4] ^ i_in[6] ^ i_in[7] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[5] = i_in[0] ^ i_in[3] ^ i_in[5] ^ i_in[7] ^ i_in[8] ^ i_in[10] ^ i_in[11];
assign o_out[6] = i_in[1] ^ i_in[4] ^ i_in[6] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[7] = i_in[0] ^ i_in[1] ^ i_in[6] ^ i_in[7] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[8] = i_in[1] ^ i_in[2] ^ i_in[7] ^ i_in[8] ^ i_in[10] ^ i_in[11];
assign o_out[9] = i_in[2] ^ i_in[3] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[10] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[9] ^ i_in[10];
assign o_out[11] = i_in[0] ^ i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[10] ^ i_in[11];
endmodule
module d_CS_evaluation_matrix_slot_003_alpha_to_012(i_in, o_out); // evaluated by alpha_to_3, 36
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[2] ^ i_in[3] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[1] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[9] ^ i_in[10];
assign o_out[2] = i_in[0] ^ i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[10] ^ i_in[11];
assign o_out[3] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[9];
assign o_out[4] = i_in[1] ^ i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10] ^ i_in[11];
assign o_out[5] = i_in[0] ^ i_in[2] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[6] = i_in[1] ^ i_in[3] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[7] = i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10];
assign o_out[8] = i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[9] = i_in[0] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[10] = i_in[0] ^ i_in[1] ^ i_in[6] ^ i_in[7] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[11] = i_in[1] ^ i_in[2] ^ i_in[7] ^ i_in[8] ^ i_in[10] ^ i_in[11];
endmodule
module d_CS_evaluation_matrix_slot_003_alpha_to_013(i_in, o_out); // evaluated by alpha_to_3, 39
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[0] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[1] = i_in[0] ^ i_in[1] ^ i_in[6] ^ i_in[7] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[2] = i_in[1] ^ i_in[2] ^ i_in[7] ^ i_in[8] ^ i_in[10] ^ i_in[11];
assign o_out[3] = i_in[0] ^ i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[6] ^ i_in[10] ^ i_in[11];
assign o_out[4] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[5] = i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[6] = i_in[0] ^ i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[7] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[9] ^ i_in[11];
assign o_out[8] = i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[10];
assign o_out[9] = i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[9] ^ i_in[11];
assign o_out[10] = i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10];
assign o_out[11] = i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
endmodule
module d_CS_evaluation_matrix_slot_003_alpha_to_014(i_in, o_out); // evaluated by alpha_to_3, 42
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[9] ^ i_in[11];
assign o_out[1] = i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10];
assign o_out[2] = i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[3] = i_in[0] ^ i_in[2] ^ i_in[3] ^ i_in[7] ^ i_in[8] ^ i_in[10] ^ i_in[11];
assign o_out[4] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8];
assign o_out[5] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9];
assign o_out[6] = i_in[0] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[7] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[6] ^ i_in[8] ^ i_in[10];
assign o_out[8] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[7] ^ i_in[9] ^ i_in[11];
assign o_out[9] = i_in[0] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[8] ^ i_in[10];
assign o_out[10] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[9] ^ i_in[11];
assign o_out[11] = i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[10];
endmodule
module d_CS_evaluation_matrix_slot_004_alpha_to_001(i_in, o_out); // evaluated by alpha_to_4, 4
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[8];
assign o_out[1] = i_in[9];
assign o_out[2] = i_in[10];
assign o_out[3] = i_in[8] ^ i_in[11];
assign o_out[4] = i_in[0] ^ i_in[8] ^ i_in[9];
assign o_out[5] = i_in[1] ^ i_in[9] ^ i_in[10];
assign o_out[6] = i_in[2] ^ i_in[10] ^ i_in[11];
assign o_out[7] = i_in[3] ^ i_in[8] ^ i_in[11];
assign o_out[8] = i_in[4] ^ i_in[9];
assign o_out[9] = i_in[5] ^ i_in[10];
assign o_out[10] = i_in[6] ^ i_in[11];
assign o_out[11] = i_in[7];
endmodule
module d_CS_evaluation_matrix_slot_004_alpha_to_002(i_in, o_out); // evaluated by alpha_to_4, 8
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[4] ^ i_in[9];
assign o_out[1] = i_in[5] ^ i_in[10];
assign o_out[2] = i_in[6] ^ i_in[11];
assign o_out[3] = i_in[4] ^ i_in[7] ^ i_in[9];
assign o_out[4] = i_in[4] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[5] = i_in[5] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[6] = i_in[6] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[7] = i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[8] = i_in[0] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[9] = i_in[1] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[10] = i_in[2] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[11] = i_in[3] ^ i_in[8] ^ i_in[11];
endmodule
module d_CS_evaluation_matrix_slot_004_alpha_to_003(i_in, o_out); // evaluated by alpha_to_4, 12
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[0] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[1] = i_in[1] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[2] = i_in[2] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[3] = i_in[0] ^ i_in[3] ^ i_in[5] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[4] = i_in[0] ^ i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[5] = i_in[1] ^ i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[9] ^ i_in[10];
assign o_out[6] = i_in[2] ^ i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10] ^ i_in[11];
assign o_out[7] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[8] = i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[11];
assign o_out[9] = i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[9];
assign o_out[10] = i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10];
assign o_out[11] = i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
endmodule
module d_CS_evaluation_matrix_slot_004_alpha_to_004(i_in, o_out); // evaluated by alpha_to_4, 16
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[11];
assign o_out[1] = i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[9];
assign o_out[2] = i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10];
assign o_out[3] = i_in[1] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[9];
assign o_out[4] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[5] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[11];
assign o_out[6] = i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[7] ^ i_in[9];
assign o_out[7] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[8] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[11];
assign o_out[9] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[8] ^ i_in[9];
assign o_out[10] = i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[9] ^ i_in[10];
assign o_out[11] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[10] ^ i_in[11];
endmodule
module d_CS_evaluation_matrix_slot_004_alpha_to_005(i_in, o_out); // evaluated by alpha_to_4, 20
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[11];
assign o_out[1] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[8] ^ i_in[9];
assign o_out[2] = i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[9] ^ i_in[10];
assign o_out[3] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[8] ^ i_in[10];
assign o_out[4] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9];
assign o_out[5] = i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[6] = i_in[0] ^ i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[7] = i_in[2] ^ i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[8] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[9] = i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[10] = i_in[0] ^ i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[11] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[10] ^ i_in[11];
endmodule
module d_CS_evaluation_matrix_slot_004_alpha_to_006(i_in, o_out); // evaluated by alpha_to_4, 24
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[1] = i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[2] = i_in[0] ^ i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[3] = i_in[1] ^ i_in[4] ^ i_in[6] ^ i_in[8] ^ i_in[9];
assign o_out[4] = i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[8] ^ i_in[11];
assign o_out[5] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[9];
assign o_out[6] = i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[10];
assign o_out[7] = i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[9] ^ i_in[10];
assign o_out[8] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[9] = i_in[0] ^ i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[11];
assign o_out[10] = i_in[1] ^ i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9];
assign o_out[11] = i_in[2] ^ i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10];
endmodule
module d_CS_evaluation_matrix_slot_004_alpha_to_007(i_in, o_out); // evaluated by alpha_to_4, 28
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[1] = i_in[0] ^ i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[11];
assign o_out[2] = i_in[1] ^ i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9];
assign o_out[3] = i_in[0] ^ i_in[2] ^ i_in[4] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[4] = i_in[0] ^ i_in[1] ^ i_in[4] ^ i_in[7] ^ i_in[9] ^ i_in[11];
assign o_out[5] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[5] ^ i_in[8] ^ i_in[10];
assign o_out[6] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[6] ^ i_in[9] ^ i_in[11];
assign o_out[7] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[11];
assign o_out[8] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[6] ^ i_in[7];
assign o_out[9] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[7] ^ i_in[8];
assign o_out[10] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[8] ^ i_in[9];
assign o_out[11] = i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[9] ^ i_in[10];
endmodule
module d_CS_evaluation_matrix_slot_004_alpha_to_008(i_in, o_out); // evaluated by alpha_to_4, 32
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[6] ^ i_in[7];
assign o_out[1] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[7] ^ i_in[8];
assign o_out[2] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[8] ^ i_in[9];
assign o_out[3] = i_in[0] ^ i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[9] ^ i_in[10];
assign o_out[4] = i_in[0] ^ i_in[3] ^ i_in[5] ^ i_in[7] ^ i_in[8] ^ i_in[10] ^ i_in[11];
assign o_out[5] = i_in[1] ^ i_in[4] ^ i_in[6] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[6] = i_in[2] ^ i_in[5] ^ i_in[7] ^ i_in[9] ^ i_in[10];
assign o_out[7] = i_in[1] ^ i_in[2] ^ i_in[7] ^ i_in[8] ^ i_in[10] ^ i_in[11];
assign o_out[8] = i_in[2] ^ i_in[3] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[9] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[9] ^ i_in[10];
assign o_out[10] = i_in[0] ^ i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[10] ^ i_in[11];
assign o_out[11] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[11];
endmodule
module d_CS_evaluation_matrix_slot_004_alpha_to_009(i_in, o_out); // evaluated by alpha_to_4, 36
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[2] ^ i_in[3] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[1] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[9] ^ i_in[10];
assign o_out[2] = i_in[0] ^ i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[10] ^ i_in[11];
assign o_out[3] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[9];
assign o_out[4] = i_in[1] ^ i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10] ^ i_in[11];
assign o_out[5] = i_in[0] ^ i_in[2] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[6] = i_in[1] ^ i_in[3] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[7] = i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10];
assign o_out[8] = i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[9] = i_in[0] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[10] = i_in[0] ^ i_in[1] ^ i_in[6] ^ i_in[7] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[11] = i_in[1] ^ i_in[2] ^ i_in[7] ^ i_in[8] ^ i_in[10] ^ i_in[11];
endmodule
module d_CS_evaluation_matrix_slot_004_alpha_to_010(i_in, o_out); // evaluated by alpha_to_4, 40
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[1] = i_in[0] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[2] = i_in[0] ^ i_in[1] ^ i_in[6] ^ i_in[7] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[3] = i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[5] ^ i_in[9] ^ i_in[10];
assign o_out[4] = i_in[0] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[5] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[6] = i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[7] = i_in[0] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[8] ^ i_in[10];
assign o_out[8] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[9] ^ i_in[11];
assign o_out[9] = i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[10];
assign o_out[10] = i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[9] ^ i_in[11];
assign o_out[11] = i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10];
endmodule
module d_CS_evaluation_matrix_slot_004_alpha_to_011(i_in, o_out); // evaluated by alpha_to_4, 44
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[9] ^ i_in[11];
assign o_out[1] = i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[10];
assign o_out[2] = i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[9] ^ i_in[11];
assign o_out[3] = i_in[0] ^ i_in[1] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[4] = i_in[0] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[10];
assign o_out[5] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[11];
assign o_out[6] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8];
assign o_out[7] = i_in[0] ^ i_in[2] ^ i_in[4] ^ i_in[6] ^ i_in[8] ^ i_in[11];
assign o_out[8] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[5] ^ i_in[7] ^ i_in[9];
assign o_out[9] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[6] ^ i_in[8] ^ i_in[10];
assign o_out[10] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[7] ^ i_in[9] ^ i_in[11];
assign o_out[11] = i_in[0] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[8] ^ i_in[10];
endmodule
module d_CS_evaluation_matrix_slot_004_alpha_to_012(i_in, o_out); // evaluated by alpha_to_4, 48
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[5] ^ i_in[7] ^ i_in[9];
assign o_out[1] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[6] ^ i_in[8] ^ i_in[10];
assign o_out[2] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[7] ^ i_in[9] ^ i_in[11];
assign o_out[3] = i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[4] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[6] ^ i_in[8] ^ i_in[10] ^ i_in[11];
assign o_out[5] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[7] ^ i_in[9] ^ i_in[11];
assign o_out[6] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[8] ^ i_in[10];
assign o_out[7] = i_in[0] ^ i_in[2] ^ i_in[4] ^ i_in[7] ^ i_in[11];
assign o_out[8] = i_in[1] ^ i_in[3] ^ i_in[5] ^ i_in[8];
assign o_out[9] = i_in[0] ^ i_in[2] ^ i_in[4] ^ i_in[6] ^ i_in[9];
assign o_out[10] = i_in[1] ^ i_in[3] ^ i_in[5] ^ i_in[7] ^ i_in[10];
assign o_out[11] = i_in[0] ^ i_in[2] ^ i_in[4] ^ i_in[6] ^ i_in[8] ^ i_in[11];
endmodule
module d_CS_evaluation_matrix_slot_004_alpha_to_013(i_in, o_out); // evaluated by alpha_to_4, 52
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[1] ^ i_in[3] ^ i_in[5] ^ i_in[8];
assign o_out[1] = i_in[0] ^ i_in[2] ^ i_in[4] ^ i_in[6] ^ i_in[9];
assign o_out[2] = i_in[1] ^ i_in[3] ^ i_in[5] ^ i_in[7] ^ i_in[10];
assign o_out[3] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[11];
assign o_out[4] = i_in[2] ^ i_in[4] ^ i_in[6] ^ i_in[7] ^ i_in[8];
assign o_out[5] = i_in[3] ^ i_in[5] ^ i_in[7] ^ i_in[8] ^ i_in[9];
assign o_out[6] = i_in[0] ^ i_in[4] ^ i_in[6] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[7] = i_in[0] ^ i_in[3] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[8] = i_in[1] ^ i_in[4] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[9] = i_in[0] ^ i_in[2] ^ i_in[5] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[10] = i_in[1] ^ i_in[3] ^ i_in[6] ^ i_in[10] ^ i_in[11];
assign o_out[11] = i_in[0] ^ i_in[2] ^ i_in[4] ^ i_in[7] ^ i_in[11];
endmodule
module d_CS_evaluation_matrix_slot_004_alpha_to_014(i_in, o_out); // evaluated by alpha_to_4, 56
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[1] ^ i_in[4] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[1] = i_in[0] ^ i_in[2] ^ i_in[5] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[2] = i_in[1] ^ i_in[3] ^ i_in[6] ^ i_in[10] ^ i_in[11];
assign o_out[3] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[4] = i_in[0] ^ i_in[2] ^ i_in[3] ^ i_in[4];
assign o_out[5] = i_in[1] ^ i_in[3] ^ i_in[4] ^ i_in[5];
assign o_out[6] = i_in[0] ^ i_in[2] ^ i_in[4] ^ i_in[5] ^ i_in[6];
assign o_out[7] = i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[8] = i_in[0] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[9] = i_in[1] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[10] = i_in[2] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[11] = i_in[0] ^ i_in[3] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
endmodule
module d_CS_evaluation_matrix_slot_005_alpha_to_001(i_in, o_out); // evaluated by alpha_to_5, 5
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[7];
assign o_out[1] = i_in[8];
assign o_out[2] = i_in[9];
assign o_out[3] = i_in[7] ^ i_in[10];
assign o_out[4] = i_in[7] ^ i_in[8] ^ i_in[11];
assign o_out[5] = i_in[0] ^ i_in[8] ^ i_in[9];
assign o_out[6] = i_in[1] ^ i_in[9] ^ i_in[10];
assign o_out[7] = i_in[2] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[8] = i_in[3] ^ i_in[8] ^ i_in[11];
assign o_out[9] = i_in[4] ^ i_in[9];
assign o_out[10] = i_in[5] ^ i_in[10];
assign o_out[11] = i_in[6] ^ i_in[11];
endmodule
module d_CS_evaluation_matrix_slot_005_alpha_to_002(i_in, o_out); // evaluated by alpha_to_5, 10
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[2] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[1] = i_in[3] ^ i_in[8] ^ i_in[11];
assign o_out[2] = i_in[4] ^ i_in[9];
assign o_out[3] = i_in[2] ^ i_in[5] ^ i_in[7] ^ i_in[11];
assign o_out[4] = i_in[2] ^ i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10] ^ i_in[11];
assign o_out[5] = i_in[3] ^ i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[6] = i_in[4] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[7] = i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[9];
assign o_out[8] = i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10];
assign o_out[9] = i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[10] = i_in[0] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[11] = i_in[1] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
endmodule
module d_CS_evaluation_matrix_slot_005_alpha_to_003(i_in, o_out); // evaluated by alpha_to_5, 15
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[9];
assign o_out[1] = i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10];
assign o_out[2] = i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[3] = i_in[0] ^ i_in[2] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10];
assign o_out[4] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[11];
assign o_out[5] = i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[7] ^ i_in[9];
assign o_out[6] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[8] ^ i_in[10];
assign o_out[7] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[11];
assign o_out[8] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[8] ^ i_in[9];
assign o_out[9] = i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[9] ^ i_in[10];
assign o_out[10] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[11] = i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[11];
endmodule
module d_CS_evaluation_matrix_slot_005_alpha_to_004(i_in, o_out); // evaluated by alpha_to_5, 20
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[11];
assign o_out[1] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[8] ^ i_in[9];
assign o_out[2] = i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[9] ^ i_in[10];
assign o_out[3] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[8] ^ i_in[10];
assign o_out[4] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9];
assign o_out[5] = i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[6] = i_in[0] ^ i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[7] = i_in[2] ^ i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[8] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[9] = i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[10] = i_in[0] ^ i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[11] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[10] ^ i_in[11];
endmodule
module d_CS_evaluation_matrix_slot_005_alpha_to_005(i_in, o_out); // evaluated by alpha_to_5, 25
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[2] ^ i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[1] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[2] = i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[3] = i_in[0] ^ i_in[3] ^ i_in[5] ^ i_in[7] ^ i_in[8] ^ i_in[11];
assign o_out[4] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[7] ^ i_in[10];
assign o_out[5] = i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[8] ^ i_in[11];
assign o_out[6] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[9];
assign o_out[7] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[8] ^ i_in[9];
assign o_out[8] = i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[9] ^ i_in[10];
assign o_out[9] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[10] = i_in[0] ^ i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[11];
assign o_out[11] = i_in[1] ^ i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9];
endmodule
module d_CS_evaluation_matrix_slot_005_alpha_to_006(i_in, o_out); // evaluated by alpha_to_5, 30
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[8] ^ i_in[9];
assign o_out[1] = i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[9] ^ i_in[10];
assign o_out[2] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[3] = i_in[0] ^ i_in[2] ^ i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[9] ^ i_in[11];
assign o_out[4] = i_in[2] ^ i_in[5] ^ i_in[7] ^ i_in[9] ^ i_in[10];
assign o_out[5] = i_in[0] ^ i_in[3] ^ i_in[6] ^ i_in[8] ^ i_in[10] ^ i_in[11];
assign o_out[6] = i_in[0] ^ i_in[1] ^ i_in[4] ^ i_in[7] ^ i_in[9] ^ i_in[11];
assign o_out[7] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[9] ^ i_in[10];
assign o_out[8] = i_in[0] ^ i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[10] ^ i_in[11];
assign o_out[9] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[11];
assign o_out[10] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[6] ^ i_in[7];
assign o_out[11] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[7] ^ i_in[8];
endmodule
module d_CS_evaluation_matrix_slot_005_alpha_to_007(i_in, o_out); // evaluated by alpha_to_5, 35
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[9] ^ i_in[10];
assign o_out[1] = i_in[0] ^ i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[10] ^ i_in[11];
assign o_out[2] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[11];
assign o_out[3] = i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[6] ^ i_in[7] ^ i_in[9] ^ i_in[10];
assign o_out[4] = i_in[0] ^ i_in[2] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[5] = i_in[1] ^ i_in[3] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[6] = i_in[2] ^ i_in[4] ^ i_in[6] ^ i_in[7] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[7] = i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[8] = i_in[0] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[9] = i_in[0] ^ i_in[1] ^ i_in[6] ^ i_in[7] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[10] = i_in[1] ^ i_in[2] ^ i_in[7] ^ i_in[8] ^ i_in[10] ^ i_in[11];
assign o_out[11] = i_in[2] ^ i_in[3] ^ i_in[8] ^ i_in[9] ^ i_in[11];
endmodule
module d_CS_evaluation_matrix_slot_005_alpha_to_008(i_in, o_out); // evaluated by alpha_to_5, 40
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[1] = i_in[0] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[2] = i_in[0] ^ i_in[1] ^ i_in[6] ^ i_in[7] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[3] = i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[5] ^ i_in[9] ^ i_in[10];
assign o_out[4] = i_in[0] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[5] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[6] = i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[7] = i_in[0] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[8] ^ i_in[10];
assign o_out[8] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[9] ^ i_in[11];
assign o_out[9] = i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[10];
assign o_out[10] = i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[9] ^ i_in[11];
assign o_out[11] = i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10];
endmodule
module d_CS_evaluation_matrix_slot_005_alpha_to_009(i_in, o_out); // evaluated by alpha_to_5, 45
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[0] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[8] ^ i_in[10];
assign o_out[1] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[9] ^ i_in[11];
assign o_out[2] = i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[10];
assign o_out[3] = i_in[0] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[4] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[9] ^ i_in[11];
assign o_out[5] = i_in[0] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[10];
assign o_out[6] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[11];
assign o_out[7] = i_in[1] ^ i_in[3] ^ i_in[5] ^ i_in[7] ^ i_in[10];
assign o_out[8] = i_in[0] ^ i_in[2] ^ i_in[4] ^ i_in[6] ^ i_in[8] ^ i_in[11];
assign o_out[9] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[5] ^ i_in[7] ^ i_in[9];
assign o_out[10] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[6] ^ i_in[8] ^ i_in[10];
assign o_out[11] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[7] ^ i_in[9] ^ i_in[11];
endmodule
module d_CS_evaluation_matrix_slot_005_alpha_to_010(i_in, o_out); // evaluated by alpha_to_5, 50
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[1] ^ i_in[3] ^ i_in[5] ^ i_in[7] ^ i_in[10];
assign o_out[1] = i_in[0] ^ i_in[2] ^ i_in[4] ^ i_in[6] ^ i_in[8] ^ i_in[11];
assign o_out[2] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[5] ^ i_in[7] ^ i_in[9];
assign o_out[3] = i_in[0] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8];
assign o_out[4] = i_in[0] ^ i_in[4] ^ i_in[6] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[5] = i_in[0] ^ i_in[1] ^ i_in[5] ^ i_in[7] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[6] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[6] ^ i_in[8] ^ i_in[10] ^ i_in[11];
assign o_out[7] = i_in[0] ^ i_in[2] ^ i_in[5] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[8] = i_in[1] ^ i_in[3] ^ i_in[6] ^ i_in[10] ^ i_in[11];
assign o_out[9] = i_in[0] ^ i_in[2] ^ i_in[4] ^ i_in[7] ^ i_in[11];
assign o_out[10] = i_in[1] ^ i_in[3] ^ i_in[5] ^ i_in[8];
assign o_out[11] = i_in[0] ^ i_in[2] ^ i_in[4] ^ i_in[6] ^ i_in[9];
endmodule
module d_CS_evaluation_matrix_slot_005_alpha_to_011(i_in, o_out); // evaluated by alpha_to_5, 55
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[0] ^ i_in[2] ^ i_in[5] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[1] = i_in[1] ^ i_in[3] ^ i_in[6] ^ i_in[10] ^ i_in[11];
assign o_out[2] = i_in[0] ^ i_in[2] ^ i_in[4] ^ i_in[7] ^ i_in[11];
assign o_out[3] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[4] = i_in[1] ^ i_in[3] ^ i_in[4] ^ i_in[5];
assign o_out[5] = i_in[0] ^ i_in[2] ^ i_in[4] ^ i_in[5] ^ i_in[6];
assign o_out[6] = i_in[1] ^ i_in[3] ^ i_in[5] ^ i_in[6] ^ i_in[7];
assign o_out[7] = i_in[0] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[8] = i_in[1] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[9] = i_in[2] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[10] = i_in[0] ^ i_in[3] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[11] = i_in[1] ^ i_in[4] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
endmodule
module d_CS_evaluation_matrix_slot_005_alpha_to_012(i_in, o_out); // evaluated by alpha_to_5, 60
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[0] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[1] = i_in[1] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[2] = i_in[2] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[3] = i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6];
assign o_out[4] = i_in[0] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[5] = i_in[0] ^ i_in[1] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[6] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[10] ^ i_in[11];
assign o_out[7] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[8] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[9] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[10] = i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[11] = i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
endmodule
module d_CS_evaluation_matrix_slot_005_alpha_to_013(i_in, o_out); // evaluated by alpha_to_5, 65
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[1] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[2] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[3] = i_in[0] ^ i_in[1] ^ i_in[11];
assign o_out[4] = i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[5] = i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[6] = i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[7] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[11];
assign o_out[8] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6];
assign o_out[9] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7];
assign o_out[10] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8];
assign o_out[11] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9];
endmodule
module d_CS_evaluation_matrix_slot_005_alpha_to_014(i_in, o_out); // evaluated by alpha_to_5, 70
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[11];
assign o_out[1] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6];
assign o_out[2] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7];
assign o_out[3] = i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[11];
assign o_out[4] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[5] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[6] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[7] = i_in[0] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10];
assign o_out[8] = i_in[0] ^ i_in[1] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[9] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[10] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[11] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[10] ^ i_in[11];
endmodule
module d_CS_evaluation_matrix_slot_006_alpha_to_001(i_in, o_out); // evaluated by alpha_to_6, 6
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[6] ^ i_in[11];
assign o_out[1] = i_in[7];
assign o_out[2] = i_in[8];
assign o_out[3] = i_in[6] ^ i_in[9] ^ i_in[11];
assign o_out[4] = i_in[6] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[5] = i_in[7] ^ i_in[8] ^ i_in[11];
assign o_out[6] = i_in[0] ^ i_in[8] ^ i_in[9];
assign o_out[7] = i_in[1] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[8] = i_in[2] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[9] = i_in[3] ^ i_in[8] ^ i_in[11];
assign o_out[10] = i_in[4] ^ i_in[9];
assign o_out[11] = i_in[5] ^ i_in[10];
endmodule
module d_CS_evaluation_matrix_slot_006_alpha_to_002(i_in, o_out); // evaluated by alpha_to_6, 12
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[0] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[1] = i_in[1] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[2] = i_in[2] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[3] = i_in[0] ^ i_in[3] ^ i_in[5] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[4] = i_in[0] ^ i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[5] = i_in[1] ^ i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[9] ^ i_in[10];
assign o_out[6] = i_in[2] ^ i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10] ^ i_in[11];
assign o_out[7] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[8] = i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[11];
assign o_out[9] = i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[9];
assign o_out[10] = i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10];
assign o_out[11] = i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
endmodule
module d_CS_evaluation_matrix_slot_006_alpha_to_003(i_in, o_out); // evaluated by alpha_to_6, 18
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[9] ^ i_in[10];
assign o_out[1] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[2] = i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[11];
assign o_out[3] = i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[10];
assign o_out[4] = i_in[0] ^ i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[5] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[6] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[7] = i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[8] = i_in[0] ^ i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[9] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[10] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[11];
assign o_out[11] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[8] ^ i_in[9];
endmodule
module d_CS_evaluation_matrix_slot_006_alpha_to_004(i_in, o_out); // evaluated by alpha_to_6, 24
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[1] = i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[2] = i_in[0] ^ i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[3] = i_in[1] ^ i_in[4] ^ i_in[6] ^ i_in[8] ^ i_in[9];
assign o_out[4] = i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[8] ^ i_in[11];
assign o_out[5] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[9];
assign o_out[6] = i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[10];
assign o_out[7] = i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[9] ^ i_in[10];
assign o_out[8] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[9] = i_in[0] ^ i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[11];
assign o_out[10] = i_in[1] ^ i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9];
assign o_out[11] = i_in[2] ^ i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10];
endmodule
module d_CS_evaluation_matrix_slot_006_alpha_to_005(i_in, o_out); // evaluated by alpha_to_6, 30
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[8] ^ i_in[9];
assign o_out[1] = i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[9] ^ i_in[10];
assign o_out[2] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[3] = i_in[0] ^ i_in[2] ^ i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[9] ^ i_in[11];
assign o_out[4] = i_in[2] ^ i_in[5] ^ i_in[7] ^ i_in[9] ^ i_in[10];
assign o_out[5] = i_in[0] ^ i_in[3] ^ i_in[6] ^ i_in[8] ^ i_in[10] ^ i_in[11];
assign o_out[6] = i_in[0] ^ i_in[1] ^ i_in[4] ^ i_in[7] ^ i_in[9] ^ i_in[11];
assign o_out[7] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[9] ^ i_in[10];
assign o_out[8] = i_in[0] ^ i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[10] ^ i_in[11];
assign o_out[9] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[11];
assign o_out[10] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[6] ^ i_in[7];
assign o_out[11] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[7] ^ i_in[8];
endmodule
module d_CS_evaluation_matrix_slot_006_alpha_to_006(i_in, o_out); // evaluated by alpha_to_6, 36
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[2] ^ i_in[3] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[1] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[9] ^ i_in[10];
assign o_out[2] = i_in[0] ^ i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[10] ^ i_in[11];
assign o_out[3] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[9];
assign o_out[4] = i_in[1] ^ i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10] ^ i_in[11];
assign o_out[5] = i_in[0] ^ i_in[2] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[6] = i_in[1] ^ i_in[3] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[7] = i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10];
assign o_out[8] = i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[9] = i_in[0] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[10] = i_in[0] ^ i_in[1] ^ i_in[6] ^ i_in[7] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[11] = i_in[1] ^ i_in[2] ^ i_in[7] ^ i_in[8] ^ i_in[10] ^ i_in[11];
endmodule
module d_CS_evaluation_matrix_slot_006_alpha_to_007(i_in, o_out); // evaluated by alpha_to_6, 42
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[9] ^ i_in[11];
assign o_out[1] = i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10];
assign o_out[2] = i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[3] = i_in[0] ^ i_in[2] ^ i_in[3] ^ i_in[7] ^ i_in[8] ^ i_in[10] ^ i_in[11];
assign o_out[4] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8];
assign o_out[5] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9];
assign o_out[6] = i_in[0] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[7] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[6] ^ i_in[8] ^ i_in[10];
assign o_out[8] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[7] ^ i_in[9] ^ i_in[11];
assign o_out[9] = i_in[0] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[8] ^ i_in[10];
assign o_out[10] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[9] ^ i_in[11];
assign o_out[11] = i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[10];
endmodule
module d_CS_evaluation_matrix_slot_006_alpha_to_008(i_in, o_out); // evaluated by alpha_to_6, 48
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[5] ^ i_in[7] ^ i_in[9];
assign o_out[1] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[6] ^ i_in[8] ^ i_in[10];
assign o_out[2] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[7] ^ i_in[9] ^ i_in[11];
assign o_out[3] = i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[4] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[6] ^ i_in[8] ^ i_in[10] ^ i_in[11];
assign o_out[5] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[7] ^ i_in[9] ^ i_in[11];
assign o_out[6] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[8] ^ i_in[10];
assign o_out[7] = i_in[0] ^ i_in[2] ^ i_in[4] ^ i_in[7] ^ i_in[11];
assign o_out[8] = i_in[1] ^ i_in[3] ^ i_in[5] ^ i_in[8];
assign o_out[9] = i_in[0] ^ i_in[2] ^ i_in[4] ^ i_in[6] ^ i_in[9];
assign o_out[10] = i_in[1] ^ i_in[3] ^ i_in[5] ^ i_in[7] ^ i_in[10];
assign o_out[11] = i_in[0] ^ i_in[2] ^ i_in[4] ^ i_in[6] ^ i_in[8] ^ i_in[11];
endmodule
module d_CS_evaluation_matrix_slot_006_alpha_to_009(i_in, o_out); // evaluated by alpha_to_6, 54
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[1] ^ i_in[3] ^ i_in[6] ^ i_in[10] ^ i_in[11];
assign o_out[1] = i_in[0] ^ i_in[2] ^ i_in[4] ^ i_in[7] ^ i_in[11];
assign o_out[2] = i_in[1] ^ i_in[3] ^ i_in[5] ^ i_in[8];
assign o_out[3] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[4] = i_in[0] ^ i_in[2] ^ i_in[4] ^ i_in[5] ^ i_in[6];
assign o_out[5] = i_in[1] ^ i_in[3] ^ i_in[5] ^ i_in[6] ^ i_in[7];
assign o_out[6] = i_in[2] ^ i_in[4] ^ i_in[6] ^ i_in[7] ^ i_in[8];
assign o_out[7] = i_in[1] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[8] = i_in[2] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[9] = i_in[0] ^ i_in[3] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[10] = i_in[1] ^ i_in[4] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[11] = i_in[0] ^ i_in[2] ^ i_in[5] ^ i_in[9] ^ i_in[10] ^ i_in[11];
endmodule
module d_CS_evaluation_matrix_slot_006_alpha_to_010(i_in, o_out); // evaluated by alpha_to_6, 60
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[0] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[1] = i_in[1] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[2] = i_in[2] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[3] = i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6];
assign o_out[4] = i_in[0] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[5] = i_in[0] ^ i_in[1] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[6] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[10] ^ i_in[11];
assign o_out[7] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[8] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[9] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[10] = i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[11] = i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
endmodule
module d_CS_evaluation_matrix_slot_006_alpha_to_011(i_in, o_out); // evaluated by alpha_to_6, 66
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9];
assign o_out[1] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[2] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[3] = i_in[0] ^ i_in[10] ^ i_in[11];
assign o_out[4] = i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[5] = i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[6] = i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[7] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[10] ^ i_in[11];
assign o_out[8] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[11];
assign o_out[9] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6];
assign o_out[10] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7];
assign o_out[11] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8];
endmodule
module d_CS_evaluation_matrix_slot_006_alpha_to_012(i_in, o_out); // evaluated by alpha_to_6, 72
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[1] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[10] ^ i_in[11];
assign o_out[2] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[11];
assign o_out[3] = i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[4] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[9];
assign o_out[5] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10];
assign o_out[6] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[7] = i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[11];
assign o_out[8] = i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[9];
assign o_out[9] = i_in[0] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10];
assign o_out[10] = i_in[0] ^ i_in[1] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[11] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[8] ^ i_in[9] ^ i_in[10];
endmodule
module d_CS_evaluation_matrix_slot_006_alpha_to_013(i_in, o_out); // evaluated by alpha_to_6, 78
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[1] = i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[11];
assign o_out[2] = i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[9];
assign o_out[3] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[11];
assign o_out[4] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[5] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[6] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[8] ^ i_in[11];
assign o_out[7] = i_in[0] ^ i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[8] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10] ^ i_in[11];
assign o_out[9] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[10] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[11] = i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
endmodule
module d_CS_evaluation_matrix_slot_006_alpha_to_014(i_in, o_out); // evaluated by alpha_to_6, 84
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[1] = i_in[0] ^ i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[2] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10] ^ i_in[11];
assign o_out[3] = i_in[0] ^ i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[4] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[5] = i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[10] ^ i_in[11];
assign o_out[6] = i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[9] ^ i_in[11];
assign o_out[7] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[9];
assign o_out[8] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[10];
assign o_out[9] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[9] ^ i_in[11];
assign o_out[10] = i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10];
assign o_out[11] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
endmodule
module d_CS_evaluation_matrix_slot_007_alpha_to_001(i_in, o_out); // evaluated by alpha_to_7, 7
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[5] ^ i_in[10];
assign o_out[1] = i_in[6] ^ i_in[11];
assign o_out[2] = i_in[7];
assign o_out[3] = i_in[5] ^ i_in[8] ^ i_in[10];
assign o_out[4] = i_in[5] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[5] = i_in[6] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[6] = i_in[7] ^ i_in[8] ^ i_in[11];
assign o_out[7] = i_in[0] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[8] = i_in[1] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[9] = i_in[2] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[10] = i_in[3] ^ i_in[8] ^ i_in[11];
assign o_out[11] = i_in[4] ^ i_in[9];
endmodule
module d_CS_evaluation_matrix_slot_007_alpha_to_002(i_in, o_out); // evaluated by alpha_to_7, 14
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10];
assign o_out[1] = i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[2] = i_in[0] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[3] = i_in[1] ^ i_in[3] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[4] = i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[7] ^ i_in[9];
assign o_out[5] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[8] ^ i_in[10];
assign o_out[6] = i_in[0] ^ i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[7] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[8] ^ i_in[9];
assign o_out[8] = i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[9] ^ i_in[10];
assign o_out[9] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[10] = i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[11];
assign o_out[11] = i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[9];
endmodule
module d_CS_evaluation_matrix_slot_007_alpha_to_003(i_in, o_out); // evaluated by alpha_to_7, 21
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[1] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[11];
assign o_out[2] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[8] ^ i_in[9];
assign o_out[3] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[7] ^ i_in[9] ^ i_in[11];
assign o_out[4] = i_in[0] ^ i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[11];
assign o_out[5] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9];
assign o_out[6] = i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[7] = i_in[1] ^ i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9];
assign o_out[8] = i_in[2] ^ i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[9] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[10] = i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[11] = i_in[0] ^ i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
endmodule
module d_CS_evaluation_matrix_slot_007_alpha_to_004(i_in, o_out); // evaluated by alpha_to_7, 28
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[1] = i_in[0] ^ i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[11];
assign o_out[2] = i_in[1] ^ i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9];
assign o_out[3] = i_in[0] ^ i_in[2] ^ i_in[4] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[4] = i_in[0] ^ i_in[1] ^ i_in[4] ^ i_in[7] ^ i_in[9] ^ i_in[11];
assign o_out[5] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[5] ^ i_in[8] ^ i_in[10];
assign o_out[6] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[6] ^ i_in[9] ^ i_in[11];
assign o_out[7] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[11];
assign o_out[8] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[6] ^ i_in[7];
assign o_out[9] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[7] ^ i_in[8];
assign o_out[10] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[8] ^ i_in[9];
assign o_out[11] = i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[9] ^ i_in[10];
endmodule
module d_CS_evaluation_matrix_slot_007_alpha_to_005(i_in, o_out); // evaluated by alpha_to_7, 35
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[9] ^ i_in[10];
assign o_out[1] = i_in[0] ^ i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[10] ^ i_in[11];
assign o_out[2] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[11];
assign o_out[3] = i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[6] ^ i_in[7] ^ i_in[9] ^ i_in[10];
assign o_out[4] = i_in[0] ^ i_in[2] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[5] = i_in[1] ^ i_in[3] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[6] = i_in[2] ^ i_in[4] ^ i_in[6] ^ i_in[7] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[7] = i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[8] = i_in[0] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[9] = i_in[0] ^ i_in[1] ^ i_in[6] ^ i_in[7] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[10] = i_in[1] ^ i_in[2] ^ i_in[7] ^ i_in[8] ^ i_in[10] ^ i_in[11];
assign o_out[11] = i_in[2] ^ i_in[3] ^ i_in[8] ^ i_in[9] ^ i_in[11];
endmodule
module d_CS_evaluation_matrix_slot_007_alpha_to_006(i_in, o_out); // evaluated by alpha_to_7, 42
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[9] ^ i_in[11];
assign o_out[1] = i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10];
assign o_out[2] = i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[3] = i_in[0] ^ i_in[2] ^ i_in[3] ^ i_in[7] ^ i_in[8] ^ i_in[10] ^ i_in[11];
assign o_out[4] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8];
assign o_out[5] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9];
assign o_out[6] = i_in[0] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[7] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[6] ^ i_in[8] ^ i_in[10];
assign o_out[8] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[7] ^ i_in[9] ^ i_in[11];
assign o_out[9] = i_in[0] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[8] ^ i_in[10];
assign o_out[10] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[9] ^ i_in[11];
assign o_out[11] = i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[10];
endmodule
module d_CS_evaluation_matrix_slot_007_alpha_to_007(i_in, o_out); // evaluated by alpha_to_7, 49
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[0] ^ i_in[2] ^ i_in[4] ^ i_in[6] ^ i_in[8] ^ i_in[11];
assign o_out[1] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[5] ^ i_in[7] ^ i_in[9];
assign o_out[2] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[6] ^ i_in[8] ^ i_in[10];
assign o_out[3] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9];
assign o_out[4] = i_in[0] ^ i_in[1] ^ i_in[5] ^ i_in[7] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[5] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[6] ^ i_in[8] ^ i_in[10] ^ i_in[11];
assign o_out[6] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[7] ^ i_in[9] ^ i_in[11];
assign o_out[7] = i_in[1] ^ i_in[3] ^ i_in[6] ^ i_in[10] ^ i_in[11];
assign o_out[8] = i_in[0] ^ i_in[2] ^ i_in[4] ^ i_in[7] ^ i_in[11];
assign o_out[9] = i_in[1] ^ i_in[3] ^ i_in[5] ^ i_in[8];
assign o_out[10] = i_in[0] ^ i_in[2] ^ i_in[4] ^ i_in[6] ^ i_in[9];
assign o_out[11] = i_in[1] ^ i_in[3] ^ i_in[5] ^ i_in[7] ^ i_in[10];
endmodule
module d_CS_evaluation_matrix_slot_007_alpha_to_008(i_in, o_out); // evaluated by alpha_to_7, 56
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[1] ^ i_in[4] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[1] = i_in[0] ^ i_in[2] ^ i_in[5] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[2] = i_in[1] ^ i_in[3] ^ i_in[6] ^ i_in[10] ^ i_in[11];
assign o_out[3] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[4] = i_in[0] ^ i_in[2] ^ i_in[3] ^ i_in[4];
assign o_out[5] = i_in[1] ^ i_in[3] ^ i_in[4] ^ i_in[5];
assign o_out[6] = i_in[0] ^ i_in[2] ^ i_in[4] ^ i_in[5] ^ i_in[6];
assign o_out[7] = i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[8] = i_in[0] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[9] = i_in[1] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[10] = i_in[2] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[11] = i_in[0] ^ i_in[3] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
endmodule
module d_CS_evaluation_matrix_slot_007_alpha_to_009(i_in, o_out); // evaluated by alpha_to_7, 63
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[1] = i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[2] = i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[3] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3];
assign o_out[4] = i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[5] = i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[6] = i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[7] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7];
assign o_out[8] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8];
assign o_out[9] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9];
assign o_out[10] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[11] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
endmodule
module d_CS_evaluation_matrix_slot_007_alpha_to_010(i_in, o_out); // evaluated by alpha_to_7, 70
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[11];
assign o_out[1] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6];
assign o_out[2] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7];
assign o_out[3] = i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[11];
assign o_out[4] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[5] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[6] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[7] = i_in[0] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10];
assign o_out[8] = i_in[0] ^ i_in[1] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[9] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[10] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[11] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[10] ^ i_in[11];
endmodule
module d_CS_evaluation_matrix_slot_007_alpha_to_011(i_in, o_out); // evaluated by alpha_to_7, 77
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[11];
assign o_out[1] = i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[9];
assign o_out[2] = i_in[0] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10];
assign o_out[3] = i_in[0] ^ i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[9];
assign o_out[4] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[5] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[8] ^ i_in[11];
assign o_out[6] = i_in[0] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[9];
assign o_out[7] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10] ^ i_in[11];
assign o_out[8] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[9] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[10] = i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[11] = i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[10] ^ i_in[11];
endmodule
module d_CS_evaluation_matrix_slot_007_alpha_to_012(i_in, o_out); // evaluated by alpha_to_7, 84
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[1] = i_in[0] ^ i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[2] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10] ^ i_in[11];
assign o_out[3] = i_in[0] ^ i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[4] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[5] = i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[10] ^ i_in[11];
assign o_out[6] = i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[9] ^ i_in[11];
assign o_out[7] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[9];
assign o_out[8] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[10];
assign o_out[9] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[9] ^ i_in[11];
assign o_out[10] = i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10];
assign o_out[11] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
endmodule
module d_CS_evaluation_matrix_slot_007_alpha_to_013(i_in, o_out); // evaluated by alpha_to_7, 91
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[7] ^ i_in[11];
assign o_out[1] = i_in[0] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[8];
assign o_out[2] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[9];
assign o_out[3] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10] ^ i_in[11];
assign o_out[4] = i_in[0] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[8] ^ i_in[9];
assign o_out[5] = i_in[1] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[9] ^ i_in[10];
assign o_out[6] = i_in[0] ^ i_in[2] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[10] ^ i_in[11];
assign o_out[7] = i_in[0] ^ i_in[2] ^ i_in[6];
assign o_out[8] = i_in[1] ^ i_in[3] ^ i_in[7];
assign o_out[9] = i_in[0] ^ i_in[2] ^ i_in[4] ^ i_in[8];
assign o_out[10] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[5] ^ i_in[9];
assign o_out[11] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[6] ^ i_in[10];
endmodule
module d_CS_evaluation_matrix_slot_007_alpha_to_014(i_in, o_out); // evaluated by alpha_to_7, 98
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[0] ^ i_in[4] ^ i_in[10];
assign o_out[1] = i_in[1] ^ i_in[5] ^ i_in[11];
assign o_out[2] = i_in[0] ^ i_in[2] ^ i_in[6];
assign o_out[3] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[4] ^ i_in[7] ^ i_in[10];
assign o_out[4] = i_in[1] ^ i_in[2] ^ i_in[5] ^ i_in[8] ^ i_in[10] ^ i_in[11];
assign o_out[5] = i_in[2] ^ i_in[3] ^ i_in[6] ^ i_in[9] ^ i_in[11];
assign o_out[6] = i_in[3] ^ i_in[4] ^ i_in[7] ^ i_in[10];
assign o_out[7] = i_in[5] ^ i_in[8] ^ i_in[10] ^ i_in[11];
assign o_out[8] = i_in[0] ^ i_in[6] ^ i_in[9] ^ i_in[11];
assign o_out[9] = i_in[1] ^ i_in[7] ^ i_in[10];
assign o_out[10] = i_in[2] ^ i_in[8] ^ i_in[11];
assign o_out[11] = i_in[3] ^ i_in[9];
endmodule
module d_CS_evaluation_matrix_slot_008_alpha_to_001(i_in, o_out); // evaluated by alpha_to_8, 8
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[4] ^ i_in[9];
assign o_out[1] = i_in[5] ^ i_in[10];
assign o_out[2] = i_in[6] ^ i_in[11];
assign o_out[3] = i_in[4] ^ i_in[7] ^ i_in[9];
assign o_out[4] = i_in[4] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[5] = i_in[5] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[6] = i_in[6] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[7] = i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[8] = i_in[0] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[9] = i_in[1] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[10] = i_in[2] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[11] = i_in[3] ^ i_in[8] ^ i_in[11];
endmodule
module d_CS_evaluation_matrix_slot_008_alpha_to_002(i_in, o_out); // evaluated by alpha_to_8, 16
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[11];
assign o_out[1] = i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[9];
assign o_out[2] = i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10];
assign o_out[3] = i_in[1] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[9];
assign o_out[4] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[5] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[11];
assign o_out[6] = i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[7] ^ i_in[9];
assign o_out[7] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[8] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[11];
assign o_out[9] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[8] ^ i_in[9];
assign o_out[10] = i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[9] ^ i_in[10];
assign o_out[11] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[10] ^ i_in[11];
endmodule
module d_CS_evaluation_matrix_slot_008_alpha_to_003(i_in, o_out); // evaluated by alpha_to_8, 24
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[1] = i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[2] = i_in[0] ^ i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[3] = i_in[1] ^ i_in[4] ^ i_in[6] ^ i_in[8] ^ i_in[9];
assign o_out[4] = i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[8] ^ i_in[11];
assign o_out[5] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[9];
assign o_out[6] = i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[10];
assign o_out[7] = i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[9] ^ i_in[10];
assign o_out[8] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[9] = i_in[0] ^ i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[11];
assign o_out[10] = i_in[1] ^ i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9];
assign o_out[11] = i_in[2] ^ i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10];
endmodule
module d_CS_evaluation_matrix_slot_008_alpha_to_004(i_in, o_out); // evaluated by alpha_to_8, 32
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[6] ^ i_in[7];
assign o_out[1] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[7] ^ i_in[8];
assign o_out[2] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[8] ^ i_in[9];
assign o_out[3] = i_in[0] ^ i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[9] ^ i_in[10];
assign o_out[4] = i_in[0] ^ i_in[3] ^ i_in[5] ^ i_in[7] ^ i_in[8] ^ i_in[10] ^ i_in[11];
assign o_out[5] = i_in[1] ^ i_in[4] ^ i_in[6] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[6] = i_in[2] ^ i_in[5] ^ i_in[7] ^ i_in[9] ^ i_in[10];
assign o_out[7] = i_in[1] ^ i_in[2] ^ i_in[7] ^ i_in[8] ^ i_in[10] ^ i_in[11];
assign o_out[8] = i_in[2] ^ i_in[3] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[9] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[9] ^ i_in[10];
assign o_out[10] = i_in[0] ^ i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[10] ^ i_in[11];
assign o_out[11] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[11];
endmodule
module d_CS_evaluation_matrix_slot_008_alpha_to_005(i_in, o_out); // evaluated by alpha_to_8, 40
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[1] = i_in[0] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[2] = i_in[0] ^ i_in[1] ^ i_in[6] ^ i_in[7] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[3] = i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[5] ^ i_in[9] ^ i_in[10];
assign o_out[4] = i_in[0] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[5] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[6] = i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[7] = i_in[0] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[8] ^ i_in[10];
assign o_out[8] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[9] ^ i_in[11];
assign o_out[9] = i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[10];
assign o_out[10] = i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[9] ^ i_in[11];
assign o_out[11] = i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10];
endmodule
module d_CS_evaluation_matrix_slot_008_alpha_to_006(i_in, o_out); // evaluated by alpha_to_8, 48
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[5] ^ i_in[7] ^ i_in[9];
assign o_out[1] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[6] ^ i_in[8] ^ i_in[10];
assign o_out[2] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[7] ^ i_in[9] ^ i_in[11];
assign o_out[3] = i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[4] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[6] ^ i_in[8] ^ i_in[10] ^ i_in[11];
assign o_out[5] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[7] ^ i_in[9] ^ i_in[11];
assign o_out[6] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[8] ^ i_in[10];
assign o_out[7] = i_in[0] ^ i_in[2] ^ i_in[4] ^ i_in[7] ^ i_in[11];
assign o_out[8] = i_in[1] ^ i_in[3] ^ i_in[5] ^ i_in[8];
assign o_out[9] = i_in[0] ^ i_in[2] ^ i_in[4] ^ i_in[6] ^ i_in[9];
assign o_out[10] = i_in[1] ^ i_in[3] ^ i_in[5] ^ i_in[7] ^ i_in[10];
assign o_out[11] = i_in[0] ^ i_in[2] ^ i_in[4] ^ i_in[6] ^ i_in[8] ^ i_in[11];
endmodule
module d_CS_evaluation_matrix_slot_008_alpha_to_007(i_in, o_out); // evaluated by alpha_to_8, 56
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[1] ^ i_in[4] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[1] = i_in[0] ^ i_in[2] ^ i_in[5] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[2] = i_in[1] ^ i_in[3] ^ i_in[6] ^ i_in[10] ^ i_in[11];
assign o_out[3] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[4] = i_in[0] ^ i_in[2] ^ i_in[3] ^ i_in[4];
assign o_out[5] = i_in[1] ^ i_in[3] ^ i_in[4] ^ i_in[5];
assign o_out[6] = i_in[0] ^ i_in[2] ^ i_in[4] ^ i_in[5] ^ i_in[6];
assign o_out[7] = i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[8] = i_in[0] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[9] = i_in[1] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[10] = i_in[2] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[11] = i_in[0] ^ i_in[3] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
endmodule
module d_CS_evaluation_matrix_slot_008_alpha_to_008(i_in, o_out); // evaluated by alpha_to_8, 64
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[1] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[2] = i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[3] = i_in[0] ^ i_in[1] ^ i_in[2];
assign o_out[4] = i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[5] = i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[6] = i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[7] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6];
assign o_out[8] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7];
assign o_out[9] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8];
assign o_out[10] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9];
assign o_out[11] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[10];
endmodule
module d_CS_evaluation_matrix_slot_008_alpha_to_009(i_in, o_out); // evaluated by alpha_to_8, 72
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[1] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[10] ^ i_in[11];
assign o_out[2] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[11];
assign o_out[3] = i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[4] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[9];
assign o_out[5] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10];
assign o_out[6] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[7] = i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[11];
assign o_out[8] = i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[9];
assign o_out[9] = i_in[0] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10];
assign o_out[10] = i_in[0] ^ i_in[1] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[11] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[8] ^ i_in[9] ^ i_in[10];
endmodule
module d_CS_evaluation_matrix_slot_008_alpha_to_010(i_in, o_out); // evaluated by alpha_to_8, 80
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[1] = i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[2] = i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[3] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[4] = i_in[1] ^ i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[5] = i_in[0] ^ i_in[2] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[6] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[7] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
assign o_out[8] = i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[9] ^ i_in[10];
assign o_out[9] = i_in[0] ^ i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[10] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10] ^ i_in[11];
assign o_out[11] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[9] ^ i_in[11];
endmodule
module d_CS_evaluation_matrix_slot_008_alpha_to_011(i_in, o_out); // evaluated by alpha_to_8, 88
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[10];
assign o_out[1] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[9] ^ i_in[11];
assign o_out[2] = i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[7] ^ i_in[8] ^ i_in[10];
assign o_out[3] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[4] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[5] ^ i_in[6] ^ i_in[7] ^ i_in[11];
assign o_out[5] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[6] ^ i_in[7] ^ i_in[8];
assign o_out[6] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[7] ^ i_in[8] ^ i_in[9];
assign o_out[7] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[5] ^ i_in[9];
assign o_out[8] = i_in[0] ^ i_in[1] ^ i_in[2] ^ i_in[4] ^ i_in[6] ^ i_in[10];
assign o_out[9] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[7] ^ i_in[11];
assign o_out[10] = i_in[0] ^ i_in[2] ^ i_in[3] ^ i_in[4] ^ i_in[6] ^ i_in[8];
assign o_out[11] = i_in[0] ^ i_in[1] ^ i_in[3] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[9];
endmodule
module d_CS_evaluation_matrix_slot_008_alpha_to_012(i_in, o_out); // evaluated by alpha_to_8, 96
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[0] ^ i_in[2] ^ i_in[6];
assign o_out[1] = i_in[1] ^ i_in[3] ^ i_in[7];
assign o_out[2] = i_in[0] ^ i_in[2] ^ i_in[4] ^ i_in[8];
assign o_out[3] = i_in[1] ^ i_in[2] ^ i_in[3] ^ i_in[5] ^ i_in[6] ^ i_in[9];
assign o_out[4] = i_in[3] ^ i_in[4] ^ i_in[7] ^ i_in[10];
assign o_out[5] = i_in[0] ^ i_in[4] ^ i_in[5] ^ i_in[8] ^ i_in[11];
assign o_out[6] = i_in[0] ^ i_in[1] ^ i_in[5] ^ i_in[6] ^ i_in[9];
assign o_out[7] = i_in[1] ^ i_in[7] ^ i_in[10];
assign o_out[8] = i_in[2] ^ i_in[8] ^ i_in[11];
assign o_out[9] = i_in[3] ^ i_in[9];
assign o_out[10] = i_in[0] ^ i_in[4] ^ i_in[10];
assign o_out[11] = i_in[1] ^ i_in[5] ^ i_in[11];
endmodule
module d_CS_evaluation_matrix_slot_008_alpha_to_013(i_in, o_out); // evaluated by alpha_to_8, 104
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[4] ^ i_in[7] ^ i_in[9] ^ i_in[10];
assign o_out[1] = i_in[5] ^ i_in[8] ^ i_in[10] ^ i_in[11];
assign o_out[2] = i_in[0] ^ i_in[6] ^ i_in[9] ^ i_in[11];
assign o_out[3] = i_in[1] ^ i_in[4] ^ i_in[9];
assign o_out[4] = i_in[2] ^ i_in[4] ^ i_in[5] ^ i_in[7] ^ i_in[9];
assign o_out[5] = i_in[0] ^ i_in[3] ^ i_in[5] ^ i_in[6] ^ i_in[8] ^ i_in[10];
assign o_out[6] = i_in[1] ^ i_in[4] ^ i_in[6] ^ i_in[7] ^ i_in[9] ^ i_in[11];
assign o_out[7] = i_in[2] ^ i_in[4] ^ i_in[5] ^ i_in[8] ^ i_in[9];
assign o_out[8] = i_in[0] ^ i_in[3] ^ i_in[5] ^ i_in[6] ^ i_in[9] ^ i_in[10];
assign o_out[9] = i_in[1] ^ i_in[4] ^ i_in[6] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[10] = i_in[2] ^ i_in[5] ^ i_in[7] ^ i_in[8] ^ i_in[11];
assign o_out[11] = i_in[3] ^ i_in[6] ^ i_in[8] ^ i_in[9];
endmodule
module d_CS_evaluation_matrix_slot_008_alpha_to_014(i_in, o_out); // evaluated by alpha_to_8, 112
input wire [`D_CS_GF_ORDER-1:0] i_in;
output wire [`D_CS_GF_ORDER-1:0] o_out;
assign o_out[0] = i_in[1] ^ i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[9] ^ i_in[10] ^ i_in[11];
assign o_out[1] = i_in[0] ^ i_in[2] ^ i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[10] ^ i_in[11];
assign o_out[2] = i_in[1] ^ i_in[3] ^ i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[11];
assign o_out[3] = i_in[1] ^ i_in[4] ^ i_in[6] ^ i_in[8] ^ i_in[10] ^ i_in[11];
assign o_out[4] = i_in[1] ^ i_in[6] ^ i_in[7] ^ i_in[10];
assign o_out[5] = i_in[0] ^ i_in[2] ^ i_in[7] ^ i_in[8] ^ i_in[11];
assign o_out[6] = i_in[1] ^ i_in[3] ^ i_in[8] ^ i_in[9];
assign o_out[7] = i_in[0] ^ i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[6] ^ i_in[11];
assign o_out[8] = i_in[1] ^ i_in[2] ^ i_in[5] ^ i_in[6] ^ i_in[7];
assign o_out[9] = i_in[2] ^ i_in[3] ^ i_in[6] ^ i_in[7] ^ i_in[8];
assign o_out[10] = i_in[0] ^ i_in[3] ^ i_in[4] ^ i_in[7] ^ i_in[8] ^ i_in[9];
assign o_out[11] = i_in[0] ^ i_in[1] ^ i_in[4] ^ i_in[5] ^ i_in[8] ^ i_in[9] ^ i_in[10];
endmodule
|
/*
* Copyright (c) 1999 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*/
// This example describes a 16x1 RAM that can be synthesized into
// a CLB ram in a Xilinx FPGA.
module ram16x1 (q, d, a, we, wclk);
output q;
input d;
input [3:0] a;
input we;
input wclk;
reg mem[15:0];
assign q = mem[a];
always @(posedge wclk) if (we) mem[a] = d;
endmodule /* ram16x1 */
module main;
wire q;
reg d;
reg [3:0] a;
reg we, wclk;
ram16x1 r1 (q, d, a, we, wclk);
initial begin
$monitor("q = %b", q);
d = 0;
wclk = 0;
a = 5;
we = 1;
#1 wclk = 1;
#1 wclk = 0;
end
endmodule /* main */
|
/*!
btcminer -- BTCMiner for ZTEX USB-FPGA Modules: HDL code for ZTEX USB-FPGA Module 1.15b (one double hash pipe)
Copyright (C) 2011-2012 ZTEX GmbH
http://www.ztex.de
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License version 3 as
published by the Free Software Foundation.
This program is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, see http://www.gnu.org/licenses/.
!*/
module ztex_ufm1_15d3 (fxclk_in, reset, clk_reset, pll_stop, dcm_progclk, dcm_progdata, dcm_progen, rd_clk, wr_clk, wr_start, read, write);
input fxclk_in, reset, clk_reset, pll_stop, dcm_progclk, dcm_progdata, dcm_progen, rd_clk, wr_clk, wr_start;
input [7:0] read;
output [7:0] write;
reg [3:0] rd_clk_b, wr_clk_b;
reg wr_start_b1, wr_start_b2, reset_buf;
reg dcm_progclk_buf, dcm_progdata_buf, dcm_progen_buf;
reg [4:0] wr_delay;
reg [351:0] inbuf, inbuf_tmp;
reg [95:0] outbuf;
reg [7:0] read_buf, write_buf;
wire fxclk, clk, dcm_clk, pll_fb, pll_clk0, dcm_locked, pll_reset;
wire [2:1] dcm_status;
wire [31:0] golden_nonce, nonce2, hash2;
miner253 m (
.clk(clk),
.reset(reset_buf),
.midstate(inbuf[351:96]),
.data(inbuf[95:0]),
.golden_nonce(golden_nonce),
.nonce2(nonce2),
.hash2(hash2)
);
BUFG bufg_fxclk (
.I(fxclk_in),
.O(fxclk)
);
BUFG bufg_clk (
.I(pll_clk0),
.O(clk)
);
DCM_CLKGEN #(
.CLKFX_DIVIDE(4.0),
.CLKFX_MULTIPLY(32),
.CLKFXDV_DIVIDE(2),
.CLKIN_PERIOD(20.8333)
)
dcm0 (
.CLKIN(fxclk),
.CLKFXDV(dcm_clk),
.FREEZEDCM(1'b0),
.PROGCLK(dcm_progclk_buf),
.PROGDATA(dcm_progdata_buf),
.PROGEN(dcm_progen_buf),
.LOCKED(dcm_locked),
.STATUS(dcm_status),
.RST(clk_reset)
);
PLL_BASE #(
.BANDWIDTH("LOW"),
.CLKFBOUT_MULT(4),
.CLKOUT0_DIVIDE(4),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLK_FEEDBACK("CLKFBOUT"),
.COMPENSATION("INTERNAL"),
.DIVCLK_DIVIDE(1),
.REF_JITTER(0.10),
.RESET_ON_LOSS_OF_LOCK("FALSE")
)
pll0 (
.CLKFBOUT(pll_fb),
.CLKOUT0(pll_clk0),
.CLKFBIN(pll_fb),
.CLKIN(dcm_clk),
.RST(pll_reset)
);
assign write = write_buf;
assign pll_reset = pll_stop | ~dcm_locked | clk_reset | dcm_status[2];
always @ (posedge clk)
begin
if ( (rd_clk_b[3] == rd_clk_b[2]) && (rd_clk_b[2] == rd_clk_b[1]) && (rd_clk_b[1] != rd_clk_b[0]) )
begin
inbuf_tmp[351:344] <= read_buf;
inbuf_tmp[343:0] <= inbuf_tmp[351:8];
end;
inbuf <= inbuf_tmp; // due to TIG's
if ( wr_start_b1 && wr_start_b2 )
begin
wr_delay <= 5'd0;
end else
begin
wr_delay[0] <= 1'b1;
wr_delay[4:1] <= wr_delay[3:0];
end
if ( ! wr_delay[4] )
begin
outbuf <= { hash2, nonce2, golden_nonce };
end else
begin
if ( (wr_clk_b[3] == wr_clk_b[2]) && (wr_clk_b[2] == wr_clk_b[1]) && (wr_clk_b[1] != wr_clk_b[0]) )
outbuf[87:0] <= outbuf[95:8];
end
read_buf <= read;
write_buf <= outbuf[7:0];
rd_clk_b[0] <= rd_clk;
rd_clk_b[3:1] <= rd_clk_b[2:0];
wr_clk_b[0] <= wr_clk;
wr_clk_b[3:1] <= wr_clk_b[2:0];
wr_start_b1 <= wr_start;
wr_start_b2 <= wr_start_b1;
reset_buf <= reset;
end
always @ (posedge fxclk)
begin
dcm_progclk_buf <= dcm_progclk;
dcm_progdata_buf <= dcm_progdata;
dcm_progen_buf <= dcm_progen;
end
endmodule
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: TX_PLL.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 15.1.0 Build 185 10/21/2015 SJ Lite Edition
// ************************************************************
//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus Prime License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module TX_PLL (
areset,
inclk0,
c0,
locked);
input areset;
input inclk0;
output c0;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [4:0] sub_wire0;
wire sub_wire2;
wire [0:0] sub_wire5 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire locked = sub_wire2;
wire sub_wire3 = inclk0;
wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
altpll altpll_component (
.areset (areset),
.inclk (sub_wire4),
.clk (sub_wire0),
.locked (sub_wire2),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 15625,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 576,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Cyclone IV E",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=TX_PLL",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "1.843200"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "1.84320000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "TX_PLL.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "15625"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "576"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL TX_PLL.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL TX_PLL.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL TX_PLL.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL TX_PLL.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL TX_PLL.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL TX_PLL_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL TX_PLL_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
module FswArbiter (/*AUTOARG*/) ;
// ========================
// Include parameter File
// ========================
parameter DMAO = 0;
`include "chip_fsw_spec_param.v"
// ===============
// Physical Pins
// ===============
input sclk; // Fabric switch clock
input lreset_l;
input csr_insert_idle;
input csr_arb_enable;
input [3:0] csr_bypass3_enable;
input [3:0] csr_bypass2_enable;
input [3:0] csr_bypass1_enable;
input csr_xb_ecc_enable;
output [3:0] xb_ecc_error_dbit;
output [3:0] xb_ecc_error_1bit;
output insert_idle_ack;
output [2:0] bp_performance_count;
input xb0_obx_ReqPst_s2a;
input [3:0] xb0_obx_NextVc_s2a;
input [1:0] xb0_obx_NextPort_s2a;
input [3:0] xb0_obx_NextXbe_s2a;
input [3:0] xb0_obx_NextXbe_s3a;
input [71:0] xb0_obx_OutDat_s4a;
output obx_xb0_GntPst_s3a;
output obx_xb0_GntByp_s3a;
input xb0_obx_ReqBypS3_s2a;
input xb0_obx_ReqBypS2_s2a;
input xb1_obx_ReqPst_s2a;
input [3:0] xb1_obx_NextVc_s2a;
input [1:0] xb1_obx_NextPort_s2a;
input [3:0] xb1_obx_NextXbe_s2a;
input [3:0] xb1_obx_NextXbe_s3a;
input [71:0] xb1_obx_OutDat_s4a;
output obx_xb1_GntPst_s3a;
output obx_xb1_GntByp_s3a;
input xb1_obx_ReqBypS3_s2a;
input xb1_obx_ReqBypS2_s2a;
input xb2_obx_ReqPst_s2a;
input [3:0] xb2_obx_NextVc_s2a;
input [1:0] xb2_obx_NextPort_s2a;
input [3:0] xb2_obx_NextXbe_s2a;
input [3:0] xb2_obx_NextXbe_s3a;
input [71:0] xb2_obx_OutDat_s4a;
output obx_xb2_GntPst_s3a;
output obx_xb2_GntByp_s3a;
input xb2_obx_ReqBypS3_s2a;
input xb2_obx_ReqBypS2_s2a;
input xb3_obx_ReqPst_s2a;
input [3:0] xb3_obx_NextVc_s2a;
input [1:0] xb3_obx_NextPort_s2a;
input [3:0] xb3_obx_NextXbe_s2a;
input [3:0] xb3_obx_NextXbe_s3a;
input [71:0] xb3_obx_OutDat_s4a;
output obx_xb3_GntPst_s3a;
output obx_xb3_GntByp_s3a;
input xb3_obx_ReqBypS3_s2a;
input xb3_obx_ReqBypS2_s2a;
input ib0_obx_PortSel_s1a;
input [63:0] ib0_obx_InDat_s1a;
input [1:0] ib0_obx_NextPort_s1a;
input [3:0] ib0_obx_NextVc_s1a;
input ib1_obx_PortSel_s1a;
input [63:0] ib1_obx_InDat_s1a;
input [1:0] ib1_obx_NextPort_s1a;
input [3:0] ib1_obx_NextVc_s1a;
input ib2_obx_PortSel_s1a;
input [63:0] ib2_obx_InDat_s1a;
input [1:0] ib2_obx_NextPort_s1a;
input [3:0] ib2_obx_NextVc_s1a;
input ib3_obx_PortSel_s1a;
input [63:0] ib3_obx_InDat_s1a;
input [1:0] ib3_obx_NextPort_s1a;
input [3:0] ib3_obx_NextVc_s1a;
input rp_is_full;
input rp_in_progress;
input [15:0] rp_arb_poolmask;
input [63:0] rp_arb_bufbusy_mask;
output xbx_grant_cycle;
output bp1_grant_cycle;
output set_arbitration_enable_d1;
output [63:0] reset_ackbuf;
output [63:0] wait_for_ack;
output [63:0] ice9_databus;
// =============================
// Auto Wires/Regs
// =============================
/*AUTOWIRE*/
/*AUTOREG*/
/* FswBypassArbiter AUTO_TEMPLATE (
// Outputs
.bp_grant3 (bp@_grant3),
.bp_grant2 (bp@_grant2),
.bp_grant1 (bp@_grant1),
.bp_grant0 (bp@_grant0),
.bp_grant_cycle (bp@_grant_cycle),
.bp_grant_cycle_d1 (bp@_grant_cycle_d1),
.bp_grant_cycle_d2 (bp@_grant_cycle_d2),
.bp_next_winner (bp@_next_winner[1:0]),
.bp_next_winner_d1 (bp@_next_winner_d1[1:0]),
.bp_next_winner_d2 (bp@_next_winner_d2[1:0]),
.bp_nextxbe (bp@_nextxbe[3:0]),
.bp_nextxbe_d1 (bp@_nextxbe_d1[3:0]),
.bp_nextxbe_d2 (bp@_nextxbe_d2[3:0]),
.bp_hold_wait_vector (bp@_hold_wait_vector[5:0]),
.bp_hold_wait_vector_d1 (bp@_hold_wait_vector_d1[5:0]),
.bp_select (bp@_select),
.bp_select_d1 (bp@_select_d1),
.bp_select_d2 (bp@_select_d2),
.bp_header (bp@_header),
.bp_header_d1 (bp@_header_d1),
.bp_header_d2 (bp@_header_d2),
// Inputs
.lreset_l (bp@_lreset_l),
.bp_arb_enable (bp@_arb_enable),
.sop3 (sop3 & xbx_bp3_enable_3),
.sop2 (sop2 & xbx_bp3_enable_2),
.sop1 (sop1 & xbx_bp3_enable_1),
.sop0 (sop0 & xbx_bp3_enable_0),
); */
FswBypassArbiter bp3 (/*AUTOINST*/);
/* FswBypassArbiter AUTO_TEMPLATE (
// Outputs
.bp_grant3 (bp@_grant3),
.bp_grant2 (bp@_grant2),
.bp_grant1 (bp@_grant1),
.bp_grant0 (bp@_grant0),
.bp_grant_cycle (bp@_grant_cycle),
.bp_grant_cycle_d1 (bp@_grant_cycle_d1),
.bp_grant_cycle_d2 (bp@_grant_cycle_d2),
.bp_next_winner (bp@_next_winner[1:0]),
.bp_next_winner_d1 (bp@_next_winner_d1[1:0]),
.bp_next_winner_d2 (bp@_next_winner_d2[1:0]),
.bp_nextxbe (bp@_nextxbe[3:0]),
.bp_nextxbe_d1 (bp@_nextxbe_d1[3:0]),
.bp_nextxbe_d2 (bp@_nextxbe_d2[3:0]),
.bp_hold_wait_vector (bp@_hold_wait_vector[5:0]),
.bp_hold_wait_vector_d1 (bp@_hold_wait_vector_d1[5:0]),
.bp_select (bp@_select),
.bp_select_d1 (bp@_select_d1),
.bp_select_d2 (bp@_select_d2),
.bp_header (bp@_header),
.bp_header_d1 (bp@_header_d1),
.bp_header_d2 (bp@_header_d2),
// Inputs
.lreset_l (bp@_lreset_l),
.bp_arb_enable (bp@_arb_enable),
.sop3 (sop3 & xbx_bp2_enable_3),
.sop2 (sop2 & xbx_bp2_enable_2),
.sop1 (sop1 & xbx_bp2_enable_1),
.sop0 (sop0 & xbx_bp2_enable_0),
); */
FswBypassArbiter bp2 (/*AUTOINST*/);
/* FswBypassArbiter AUTO_TEMPLATE (
// Outputs
.bp_grant3 (bp@_grant3),
.bp_grant2 (bp@_grant2),
.bp_grant1 (bp@_grant1),
.bp_grant0 (bp@_grant0),
.bp_grant_cycle (bp@_grant_cycle),
.bp_grant_cycle_d1 (bp@_grant_cycle_d1),
.bp_grant_cycle_d2 (bp@_grant_cycle_d2),
.bp_next_winner (bp@_next_winner[1:0]),
.bp_next_winner_d1 (bp@_next_winner_d1[1:0]),
.bp_next_winner_d2 (bp@_next_winner_d2[1:0]),
.bp_nextxbe (bp@_nextxbe[3:0]),
.bp_nextxbe_d1 (bp@_nextxbe_d1[3:0]),
.bp_nextxbe_d2 (bp@_nextxbe_d2[3:0]),
.bp_hold_wait_vector (bp@_hold_wait_vector[5:0]),
.bp_hold_wait_vector_d1 (bp@_hold_wait_vector_d1[5:0]),
.bp_select (bp@_select),
.bp_select_d1 (bp@_select_d1),
.bp_select_d2 (bp@_select_d2),
.bp_header (bp@_header),
.bp_header_d1 (bp@_header_d1),
.bp_header_d2 (bp@_header_d2),
// Inputs
.lreset_l (bp@_lreset_l),
.bp_arb_enable (bp@_arb_enable),
.sop3 (sop3 & csr_bp1_enable_3),
.sop2 (sop2 & csr_bp1_enable_2),
.sop1 (sop1 & csr_bp1_enable_1),
.sop0 (sop0 & csr_bp1_enable_0),
); */
FswBypassArbiter bp1 (/*AUTOINST*/);
// =======================================
// Coverage
// =======================================
// psl default clock = negedge sclk;
generate if (DMAO == 0)
begin
// psl cover {lreset_l & (bp1_grant0 |bp1_grant1 |bp1_grant2 |bp1_grant3 )} report "FswPerfRtl::byp1Taken";
// psl cover {lreset_l & (bp2_grant0 |bp2_grant1 |bp2_grant2 |bp2_grant3)} report "FswPerfRtl::byp2Taken";
// psl cover {lreset_l & (bp3_grant0 |bp3_grant1 |bp3_grant2 |bp3_grant3)} report "FswPerfRtl::byp3Taken";
end
endgenerate
// ================
// Unused signals
// ================
// lint_checking SCX_UNUSED off
wire _unused_ok = &{1'b0,
bp_select,
bp3_hold_wait_vector,
bp2_hold_wait_vector_d1,
bp1_hold_wait_vector_d1,
bp3_header,
bp3_header_d1,
bp3_select,
bp3_select_d1,
bp3_next_winner[1:0],
bp3_next_winner_d1[1:0],
bp3_nextxbe[3:0],
bp3_nextxbe_d1[3:0],
bp2_grant_cycle_d2,
bp2_header,
bp2_header_d2,
bp2_select,
bp2_select_d2,
bp2_next_winner[1:0],
bp2_next_winner_d2[1:0],
bp2_nextxbe[3:0],
bp2_nextxbe_d2[3:0],
bp1_header_d1,
bp1_header_d2,
bp1_select_d1,
bp1_select_d2,
bp1_next_winner_d1[1:0],
bp1_next_winner_d2[1:0],
bp1_nextxbe_d1[3:0],
bp1_nextxbe_d2[3:0],
xb0_obx_NextXbe_s3a, // This is unused signal now.
xb1_obx_NextXbe_s3a,
xb2_obx_NextXbe_s3a,
xb3_obx_NextXbe_s3a,
syn64,
dataout64,
1'b0
};
// lint_checking SCX_UNUSED on
endmodule
module FswBypassArbiter (/*AUTOARG*/) ;
input lreset_l;
input sclk;
input bp_arb_enable;
output bp_grant3;
output bp_grant2;
output bp_grant1;
output bp_grant0;
output bp_grant_cycle;
output bp_grant_cycle_d1;
output bp_grant_cycle_d2;
output [1:0] bp_next_winner;
output [1:0] bp_next_winner_d1;
output [1:0] bp_next_winner_d2;
output [3:0] bp_nextxbe;
output [3:0] bp_nextxbe_d1;
output [3:0] bp_nextxbe_d2;
output [5:0] bp_hold_wait_vector;
output [5:0] bp_hold_wait_vector_d1;
output bp_header;
output bp_header_d1;
output bp_header_d2;
output bp_select;
output bp_select_d1;
output bp_select_d2;
input sop3;
input [63:0] sop3_data;
input [5:0] sop3_bpcontext;
input sop2;
input [63:0] sop2_data;
input [5:0] sop2_bpcontext;
input sop1;
input [63:0] sop1_data;
input [5:0] sop1_bpcontext;
input sop0;
input [63:0] sop0_data;
input [5:0] sop0_bpcontext;
input [15:0] poolmask;
input [63:0] bufbusy_mask;
endmodule
|
// This is a component of pluto_servo, a PWM servo driver and quadrature
// counter for emc2
// Copyright 2006 Jeff Epler <[email protected]>
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
module wdt(clk, ena, cnt, out);
input clk, ena, cnt;
output out;
reg [6:0] timer;
wire timer_top = (timer == 7'd127);
reg internal_enable;
wire out = internal_enable && timer_top;
always @(posedge clk) begin
if(ena) begin
internal_enable <= 1;
timer <= 0;
end else if(cnt && !timer_top) timer <= timer + 7'd1;
end
endmodule
|
//
// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
//
//
//
//
// Ports:
// Name I/O size props
// mv_read O 32
// mav_write O 32
// CLK I 1 clock
// RST_N I 1 reset
// mav_write_misa I 28
// mav_write_wordxl I 32
// EN_reset I 1
// EN_mav_write I 1
//
// Combinational paths from inputs to outputs:
// (mav_write_misa, mav_write_wordxl) -> mav_write
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkCSR_MIE(CLK,
RST_N,
EN_reset,
mv_read,
mav_write_misa,
mav_write_wordxl,
EN_mav_write,
mav_write);
input CLK;
input RST_N;
// action method reset
input EN_reset;
// value method mv_read
output [31 : 0] mv_read;
// actionvalue method mav_write
input [27 : 0] mav_write_misa;
input [31 : 0] mav_write_wordxl;
input EN_mav_write;
output [31 : 0] mav_write;
// signals for module outputs
wire [31 : 0] mav_write, mv_read;
// register rg_mie
reg [11 : 0] rg_mie;
wire [11 : 0] rg_mie$D_IN;
wire rg_mie$EN;
// rule scheduling signals
wire CAN_FIRE_mav_write,
CAN_FIRE_reset,
WILL_FIRE_mav_write,
WILL_FIRE_reset;
// remaining internal signals
wire [11 : 0] mie__h88;
wire seie__h119, ssie__h113, stie__h116, ueie__h118, usie__h112, utie__h115;
// action method reset
assign CAN_FIRE_reset = 1'd1 ;
assign WILL_FIRE_reset = EN_reset ;
// value method mv_read
assign mv_read = { 20'd0, rg_mie } ;
// actionvalue method mav_write
assign mav_write = { 20'd0, mie__h88 } ;
assign CAN_FIRE_mav_write = 1'd1 ;
assign WILL_FIRE_mav_write = EN_mav_write ;
// register rg_mie
assign rg_mie$D_IN = EN_mav_write ? mie__h88 : 12'd0 ;
assign rg_mie$EN = EN_mav_write || EN_reset ;
// remaining internal signals
assign mie__h88 =
{ mav_write_wordxl[11],
1'b0,
seie__h119,
ueie__h118,
mav_write_wordxl[7],
1'b0,
stie__h116,
utie__h115,
mav_write_wordxl[3],
1'b0,
ssie__h113,
usie__h112 } ;
assign seie__h119 = mav_write_misa[18] && mav_write_wordxl[9] ;
assign ssie__h113 = mav_write_misa[18] && mav_write_wordxl[1] ;
assign stie__h116 = mav_write_misa[18] && mav_write_wordxl[5] ;
assign ueie__h118 = mav_write_misa[13] && mav_write_wordxl[8] ;
assign usie__h112 = mav_write_misa[13] && mav_write_wordxl[0] ;
assign utie__h115 = mav_write_misa[13] && mav_write_wordxl[4] ;
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
rg_mie <= `BSV_ASSIGNMENT_DELAY 12'd0;
end
else
begin
if (rg_mie$EN) rg_mie <= `BSV_ASSIGNMENT_DELAY rg_mie$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
rg_mie = 12'hAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkCSR_MIE
|
/**
* This is written by Zhiyang Ong
* for EE577b Extra Credit Homework , Question 2
*
* Behavioral model for the large XOR gate
*/
module large_xor (a,b,out);
// Output vector
output reg [14:0] out;
// Input vector
input [14:0] a;
// Another input vector
input [15:1] b;
// Declare "reg" signals...
//reg [3:0] in_bar;
// Declare "wire" signals...
// Defining constants: parameter [name_of_constant] = value;
always @(*)
begin
out[0]=a[0]^b[1];
out[1]=a[1]^b[2];
out[2]=a[2]^b[3];
out[3]=a[3]^b[4];
out[4]=a[4]^b[5];
out[5]=a[5]^b[6];
out[6]=a[6]^b[7];
out[7]=a[7]^b[8];
out[8]=a[8]^b[9];
out[9]=a[9]^b[10];
out[10]=a[10]^b[11];
out[11]=a[11]^b[12];
out[12]=a[12]^b[13];
out[13]=a[13]^b[14];
out[14]=a[14]^b[15];
end
endmodule
module parity_stripper (in,out);
// Output vector
output reg [10:0] out;
// Input vector
input [14:0] in;
// Declare "reg" signals...
//reg [3:0] in_bar;
// Declare "wire" signals...
// Defining constants: parameter [name_of_constant] = value;
always @(*)
begin
out[0]=in[2];
out[1]=in[4];
out[2]=in[5];
out[3]=in[6];
out[4]=in[8];
out[5]=in[9];
out[6]=in[10];
out[7]=in[11];
out[8]=in[12];
out[9]=in[13];
out[10]=in[14];
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INPUTISO0N_TB_V
`define SKY130_FD_SC_LP__INPUTISO0N_TB_V
/**
* inputiso0n: Input isolator with inverted enable.
*
* X = (A & SLEEP_B)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__inputiso0n.v"
module top();
// Inputs are registered
reg A;
reg SLEEP_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
SLEEP_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 SLEEP_B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 SLEEP_B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 SLEEP_B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 SLEEP_B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 SLEEP_B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_lp__inputiso0n dut (.A(A), .SLEEP_B(SLEEP_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__INPUTISO0N_TB_V
|
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: nto1_mux.v
//
// Description: N:1 MUX based on either binary-encoded or one-hot select input
// One-hot mode does not protect against multiple active SEL_ONEHOT inputs.
// Note: All port signals changed to all-upper-case (w.r.t. prior version).
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_nto1_mux #
(
parameter integer C_RATIO = 1, // Range: >=1
parameter integer C_SEL_WIDTH = 1, // Range: >=1; recommended: ceil_log2(C_RATIO)
parameter integer C_DATAOUT_WIDTH = 1, // Range: >=1
parameter integer C_ONEHOT = 0 // Values: 0 = binary-encoded (use SEL); 1 = one-hot (use SEL_ONEHOT)
)
(
input wire [C_RATIO-1:0] SEL_ONEHOT, // One-hot generic_baseblocks_v2_1_mux select (only used if C_ONEHOT=1)
input wire [C_SEL_WIDTH-1:0] SEL, // Binary-encoded generic_baseblocks_v2_1_mux select (only used if C_ONEHOT=0)
input wire [C_RATIO*C_DATAOUT_WIDTH-1:0] IN, // Data input array (num_selections x data_width)
output wire [C_DATAOUT_WIDTH-1:0] OUT // Data output vector
);
wire [C_DATAOUT_WIDTH*C_RATIO-1:0] carry;
genvar i;
generate
if (C_ONEHOT == 0) begin : gen_encoded
assign carry[C_DATAOUT_WIDTH-1:0] = {C_DATAOUT_WIDTH{(SEL==0)?1'b1:1'b0}} & IN[C_DATAOUT_WIDTH-1:0];
for (i=1;i<C_RATIO;i=i+1) begin : gen_carrychain_enc
assign carry[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH] =
carry[i*C_DATAOUT_WIDTH-1:(i-1)*C_DATAOUT_WIDTH] |
{C_DATAOUT_WIDTH{(SEL==i)?1'b1:1'b0}} & IN[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH];
end
end else begin : gen_onehot
assign carry[C_DATAOUT_WIDTH-1:0] = {C_DATAOUT_WIDTH{SEL_ONEHOT[0]}} & IN[C_DATAOUT_WIDTH-1:0];
for (i=1;i<C_RATIO;i=i+1) begin : gen_carrychain_hot
assign carry[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH] =
carry[i*C_DATAOUT_WIDTH-1:(i-1)*C_DATAOUT_WIDTH] |
{C_DATAOUT_WIDTH{SEL_ONEHOT[i]}} & IN[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH];
end
end
endgenerate
assign OUT = carry[C_DATAOUT_WIDTH*C_RATIO-1:
C_DATAOUT_WIDTH*(C_RATIO-1)];
endmodule
`default_nettype wire
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:module_ref:linescanner_image_capture_unit:1.0
// IP Revision: 1
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module image_processing_2d_design_linescanner_image_capture_unit_0_1 (
enable,
data,
rst_cvc,
rst_cds,
sample,
end_adc,
lval,
pixel_clock,
main_clock_source,
main_clock,
n_reset,
load_pulse,
pixel_data,
pixel_captured
);
input wire enable;
input wire [7 : 0] data;
output wire rst_cvc;
output wire rst_cds;
output wire sample;
input wire end_adc;
input wire lval;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 pixel_clock CLK" *)
input wire pixel_clock;
input wire main_clock_source;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 main_clock CLK" *)
output wire main_clock;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 n_reset RST" *)
input wire n_reset;
output wire load_pulse;
output wire [7 : 0] pixel_data;
output wire pixel_captured;
linescanner_image_capture_unit inst (
.enable(enable),
.data(data),
.rst_cvc(rst_cvc),
.rst_cds(rst_cds),
.sample(sample),
.end_adc(end_adc),
.lval(lval),
.pixel_clock(pixel_clock),
.main_clock_source(main_clock_source),
.main_clock(main_clock),
.n_reset(n_reset),
.load_pulse(load_pulse),
.pixel_data(pixel_data),
.pixel_captured(pixel_captured)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__XNOR3_1_V
`define SKY130_FD_SC_LS__XNOR3_1_V
/**
* xnor3: 3-input exclusive NOR.
*
* Verilog wrapper for xnor3 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__xnor3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__xnor3_1 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__xnor3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__xnor3_1 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__xnor3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__XNOR3_1_V
|
`timescale 1ps / 1ps
`define SB_DFF_INIT initial Q = 0;
// `define SB_DFF_INIT
`ifndef NO_ICE40_DEFAULT_ASSIGNMENTS
`define ICE40_DEFAULT_ASSIGNMENT_V(v) = v
`define ICE40_DEFAULT_ASSIGNMENT_0 = 1'b0
`define ICE40_DEFAULT_ASSIGNMENT_1 = 1'b1
`else
`define ICE40_DEFAULT_ASSIGNMENT_V(v)
`define ICE40_DEFAULT_ASSIGNMENT_0
`define ICE40_DEFAULT_ASSIGNMENT_1
`endif
// SiliconBlue IO Cells
module SB_IO (
inout PACKAGE_PIN,
input LATCH_INPUT_VALUE,
input CLOCK_ENABLE `ICE40_DEFAULT_ASSIGNMENT_1,
input INPUT_CLK,
input OUTPUT_CLK,
input OUTPUT_ENABLE,
input D_OUT_0,
input D_OUT_1,
output D_IN_0,
output D_IN_1
);
parameter [5:0] PIN_TYPE = 6'b000000;
parameter [0:0] PULLUP = 1'b0;
parameter [0:0] NEG_TRIGGER = 1'b0;
parameter IO_STANDARD = "SB_LVCMOS";
`ifndef BLACKBOX
reg dout, din_0, din_1;
reg din_q_0, din_q_1;
reg dout_q_0, dout_q_1;
reg outena_q;
// IO tile generates a constant 1'b1 internally if global_cen is not connected
wire clken_pulled = CLOCK_ENABLE || CLOCK_ENABLE === 1'bz;
reg clken_pulled_ri;
reg clken_pulled_ro;
generate if (!NEG_TRIGGER) begin
always @(posedge INPUT_CLK) clken_pulled_ri <= clken_pulled;
always @(posedge INPUT_CLK) if (clken_pulled) din_q_0 <= PACKAGE_PIN;
always @(negedge INPUT_CLK) if (clken_pulled_ri) din_q_1 <= PACKAGE_PIN;
always @(posedge OUTPUT_CLK) clken_pulled_ro <= clken_pulled;
always @(posedge OUTPUT_CLK) if (clken_pulled) dout_q_0 <= D_OUT_0;
always @(negedge OUTPUT_CLK) if (clken_pulled_ro) dout_q_1 <= D_OUT_1;
always @(posedge OUTPUT_CLK) if (clken_pulled) outena_q <= OUTPUT_ENABLE;
end else begin
always @(negedge INPUT_CLK) clken_pulled_ri <= clken_pulled;
always @(negedge INPUT_CLK) if (clken_pulled) din_q_0 <= PACKAGE_PIN;
always @(posedge INPUT_CLK) if (clken_pulled_ri) din_q_1 <= PACKAGE_PIN;
always @(negedge OUTPUT_CLK) clken_pulled_ro <= clken_pulled;
always @(negedge OUTPUT_CLK) if (clken_pulled) dout_q_0 <= D_OUT_0;
always @(posedge OUTPUT_CLK) if (clken_pulled_ro) dout_q_1 <= D_OUT_1;
always @(negedge OUTPUT_CLK) if (clken_pulled) outena_q <= OUTPUT_ENABLE;
end endgenerate
always @* begin
if (!PIN_TYPE[1] || !LATCH_INPUT_VALUE)
din_0 = PIN_TYPE[0] ? PACKAGE_PIN : din_q_0;
din_1 = din_q_1;
end
// work around simulation glitches on dout in DDR mode
reg outclk_delayed_1;
reg outclk_delayed_2;
always @* outclk_delayed_1 <= OUTPUT_CLK;
always @* outclk_delayed_2 <= outclk_delayed_1;
always @* begin
if (PIN_TYPE[3])
dout = PIN_TYPE[2] ? !dout_q_0 : D_OUT_0;
else
dout = (outclk_delayed_2 ^ NEG_TRIGGER) || PIN_TYPE[2] ? dout_q_0 : dout_q_1;
end
assign D_IN_0 = din_0, D_IN_1 = din_1;
generate
if (PIN_TYPE[5:4] == 2'b01) assign PACKAGE_PIN = dout;
if (PIN_TYPE[5:4] == 2'b10) assign PACKAGE_PIN = OUTPUT_ENABLE ? dout : 1'bz;
if (PIN_TYPE[5:4] == 2'b11) assign PACKAGE_PIN = outena_q ? dout : 1'bz;
endgenerate
`endif
`ifdef TIMING
specify
(INPUT_CLK => D_IN_0) = (0:0:0, 0:0:0);
(INPUT_CLK => D_IN_1) = (0:0:0, 0:0:0);
(PACKAGE_PIN => D_IN_0) = (0:0:0, 0:0:0);
(OUTPUT_CLK => PACKAGE_PIN) = (0:0:0, 0:0:0);
(D_OUT_0 => PACKAGE_PIN) = (0:0:0, 0:0:0);
(OUTPUT_ENABLE => PACKAGE_PIN) = (0:0:0, 0:0:0);
$setuphold(posedge OUTPUT_CLK, posedge D_OUT_0, 0:0:0, 0:0:0);
$setuphold(posedge OUTPUT_CLK, negedge D_OUT_0, 0:0:0, 0:0:0);
$setuphold(negedge OUTPUT_CLK, posedge D_OUT_1, 0:0:0, 0:0:0);
$setuphold(negedge OUTPUT_CLK, negedge D_OUT_1, 0:0:0, 0:0:0);
$setuphold(negedge OUTPUT_CLK, posedge D_OUT_0, 0:0:0, 0:0:0);
$setuphold(negedge OUTPUT_CLK, negedge D_OUT_0, 0:0:0, 0:0:0);
$setuphold(posedge OUTPUT_CLK, posedge D_OUT_1, 0:0:0, 0:0:0);
$setuphold(posedge OUTPUT_CLK, negedge D_OUT_1, 0:0:0, 0:0:0);
$setuphold(posedge INPUT_CLK, posedge CLOCK_ENABLE, 0:0:0, 0:0:0);
$setuphold(posedge INPUT_CLK, negedge CLOCK_ENABLE, 0:0:0, 0:0:0);
$setuphold(posedge OUTPUT_CLK, posedge CLOCK_ENABLE, 0:0:0, 0:0:0);
$setuphold(posedge OUTPUT_CLK, negedge CLOCK_ENABLE, 0:0:0, 0:0:0);
$setuphold(posedge INPUT_CLK, posedge PACKAGE_PIN, 0:0:0, 0:0:0);
$setuphold(posedge INPUT_CLK, negedge PACKAGE_PIN, 0:0:0, 0:0:0);
$setuphold(negedge INPUT_CLK, posedge PACKAGE_PIN, 0:0:0, 0:0:0);
$setuphold(negedge INPUT_CLK, negedge PACKAGE_PIN, 0:0:0, 0:0:0);
$setuphold(posedge OUTPUT_CLK, posedge OUTPUT_ENABLE, 0:0:0, 0:0:0);
$setuphold(posedge OUTPUT_CLK, negedge OUTPUT_ENABLE, 0:0:0, 0:0:0);
$setuphold(negedge OUTPUT_CLK, posedge OUTPUT_ENABLE, 0:0:0, 0:0:0);
$setuphold(negedge OUTPUT_CLK, negedge OUTPUT_ENABLE, 0:0:0, 0:0:0);
endspecify
`endif
endmodule
module SB_GB_IO (
inout PACKAGE_PIN,
output GLOBAL_BUFFER_OUTPUT,
input LATCH_INPUT_VALUE,
input CLOCK_ENABLE `ICE40_DEFAULT_ASSIGNMENT_1,
input INPUT_CLK,
input OUTPUT_CLK,
input OUTPUT_ENABLE,
input D_OUT_0,
input D_OUT_1,
output D_IN_0,
output D_IN_1
);
parameter [5:0] PIN_TYPE = 6'b000000;
parameter [0:0] PULLUP = 1'b0;
parameter [0:0] NEG_TRIGGER = 1'b0;
parameter IO_STANDARD = "SB_LVCMOS";
assign GLOBAL_BUFFER_OUTPUT = PACKAGE_PIN;
SB_IO #(
.PIN_TYPE(PIN_TYPE),
.PULLUP(PULLUP),
.NEG_TRIGGER(NEG_TRIGGER),
.IO_STANDARD(IO_STANDARD)
) IO (
.PACKAGE_PIN(PACKAGE_PIN),
.LATCH_INPUT_VALUE(LATCH_INPUT_VALUE),
.CLOCK_ENABLE(CLOCK_ENABLE),
.INPUT_CLK(INPUT_CLK),
.OUTPUT_CLK(OUTPUT_CLK),
.OUTPUT_ENABLE(OUTPUT_ENABLE),
.D_OUT_0(D_OUT_0),
.D_OUT_1(D_OUT_1),
.D_IN_0(D_IN_0),
.D_IN_1(D_IN_1)
);
endmodule
module SB_GB (
input USER_SIGNAL_TO_GLOBAL_BUFFER,
output GLOBAL_BUFFER_OUTPUT
);
assign GLOBAL_BUFFER_OUTPUT = USER_SIGNAL_TO_GLOBAL_BUFFER;
`ifdef TIMING
specify
(USER_SIGNAL_TO_GLOBAL_BUFFER => GLOBAL_BUFFER_OUTPUT) = (0:0:0, 0:0:0);
endspecify
`endif
endmodule
// SiliconBlue Logic Cells
(* abc9_lut=1, lib_whitebox *)
module SB_LUT4 (
output O,
input I0 `ICE40_DEFAULT_ASSIGNMENT_0,
input I1 `ICE40_DEFAULT_ASSIGNMENT_0,
input I2 `ICE40_DEFAULT_ASSIGNMENT_0,
input I3 `ICE40_DEFAULT_ASSIGNMENT_0
);
parameter [15:0] LUT_INIT = 0;
wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
wire [3:0] s2 = I2 ? s3[ 7:4] : s3[3:0];
wire [1:0] s1 = I1 ? s2[ 3:2] : s2[1:0];
assign O = I0 ? s1[1] : s1[0];
`ifdef ICE40_HX
specify
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L80
(I0 => O) = (449, 386);
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L83
(I1 => O) = (400, 379);
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L86
(I2 => O) = (379, 351);
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L88
(I3 => O) = (316, 288);
endspecify
`endif
`ifdef ICE40_LP
specify
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L80
(I0 => O) = (662, 569);
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L83
(I1 => O) = (589, 558);
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L86
(I2 => O) = (558, 517);
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L88
(I3 => O) = (465, 423);
endspecify
`endif
`ifdef ICE40_U
specify
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L92
(I0 => O) = (1245, 1285);
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L95
(I1 => O) = (1179, 1232);
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L98
(I2 => O) = (1179, 1205);
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L100
(I3 => O) = (861, 874);
endspecify
`endif
endmodule
(* lib_whitebox *)
module SB_CARRY (output CO, input I0, I1, CI);
assign CO = (I0 && I1) || ((I0 || I1) && CI);
`ifdef ICE40_HX
specify
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L79
(CI => CO) = (126, 105);
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L82
(I0 => CO) = (259, 245);
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L85
(I1 => CO) = (231, 133);
endspecify
`endif
`ifdef ICE40_LP
specify
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L79
(CI => CO) = (186, 155);
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L82
(I0 => CO) = (382, 362);
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L85
(I1 => CO) = (341, 196);
endspecify
`endif
`ifdef ICE40_U
specify
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L91
(CI => CO) = (278, 278);
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L94
(I0 => CO) = (675, 662);
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L97
(I1 => CO) = (609, 358);
endspecify
`endif
endmodule
// Positive Edge SiliconBlue FF Cells
(* abc9_flop, lib_whitebox *)
module SB_DFF (
output reg Q,
input C, D
);
`SB_DFF_INIT
always @(posedge C)
Q <= D;
`ifdef ICE40_HX
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
// minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
$setup(D, posedge C, 470 - 449);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
(posedge C => (Q : D)) = 540;
endspecify
`endif
`ifdef ICE40_LP
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
// minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
$setup(D, posedge C, 693 - 662);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
(posedge C => (Q : D)) = 796;
endspecify
`endif
`ifdef ICE40_U
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
// minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
$setup(D, posedge C, /*1232 - 1285*/ 0); // Negative times not currently supported
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
(posedge C => (Q : D)) = 1391;
endspecify
`endif
endmodule
(* abc9_flop, lib_whitebox *)
module SB_DFFE (
output reg Q,
input C, E `ICE40_DEFAULT_ASSIGNMENT_1, D
);
`SB_DFF_INIT
always @(posedge C)
if (E)
Q <= D;
`ifdef ICE40_HX
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
// minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
$setup(D, posedge C &&& E, 470 - 449);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
$setup(E, posedge C, 0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
if (E) (posedge C => (Q : D)) = 540;
endspecify
`endif
`ifdef ICE40_LP
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
// minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
$setup(D, posedge C &&& E, 693 - 662);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L73
$setup(E, posedge C, 0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
if (E) (posedge C => (Q : D)) = 796;
endspecify
`endif
`ifdef ICE40_U
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
// minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
$setup(D, posedge C &&& E, /*1232 - 1285*/ 0); // Negative times not currently supported
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L86
$setup(E, posedge C, 0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
if (E) (posedge C => (Q : D)) = 1391;
endspecify
`endif
endmodule
(* abc9_flop, lib_whitebox *)
module SB_DFFSR (
output reg Q,
input C, R, D
);
`SB_DFF_INIT
always @(posedge C)
if (R)
Q <= 0;
else
Q <= D;
`ifdef ICE40_HX
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
// minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
$setup(D, posedge C, 470 - 449);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L78
$setup(R, posedge C, 203);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
if ( R) (posedge C => (Q : 1'b0)) = 540;
if (!R) (posedge C => (Q : D)) = 540;
endspecify
`endif
`ifdef ICE40_LP
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
// minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
$setup(D, posedge C, 693 - 662);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L78
$setup(R, posedge C, 299);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
if ( R) (posedge C => (Q : 1'b0)) = 796;
if (!R) (posedge C => (Q : D)) = 796;
endspecify
`endif
`ifdef ICE40_U
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
// minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
$setup(D, posedge C, /*1232 - 1285*/ 0); // Negative times not currently supported
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L90
$setup(R, posedge C, 530);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
if ( R) (posedge C => (Q : 1'b0)) = 1391;
if (!R) (posedge C => (Q : D)) = 1391;
endspecify
`endif
endmodule
(* abc9_box, lib_whitebox *)
module SB_DFFR (
output reg Q,
input C, R, D
);
`SB_DFF_INIT
always @(posedge C, posedge R)
if (R)
Q <= 0;
else
Q <= D;
`ifdef ICE40_HX
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
// minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
$setup(D, posedge C, 470 - 449);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L63
$setup(negedge R, posedge C, 160);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L91
`ifndef YOSYS
(posedge R => (Q : 1'b0)) = 599;
`else
if (R) (R => Q) = 599; // Technically, this should be an edge sensitive path
// but for facilitating a bypass box, let's pretend it's
// a simple path
`endif
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
if (!R) (posedge C => (Q : D)) = 540;
endspecify
`endif
`ifdef ICE40_LP
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
// minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
$setup(D, posedge C, 693 - 662);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L63
$setup(negedge R, posedge C, 235);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L91
`ifndef YOSYS
(posedge R => (Q : 1'b0)) = 883;
`else
if (R) (R => Q) = 883; // Technically, this should be an edge sensitive path
// but for facilitating a bypass box, let's pretend it's
// a simple path
`endif
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
if (!R) (posedge C => (Q : D)) = 796;
endspecify
`endif
`ifdef ICE40_U
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
// minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
$setup(D, posedge C, /*1232 - 1285*/ 0); // Negative times not currently supported
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L75
$setup(negedge R, posedge C, 424);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L103
`ifndef YOSYS
(posedge R => (Q : 1'b0)) = 1589;
`else
if (R) (R => Q) = 1589; // Technically, this should be an edge sensitive path
// but for facilitating a bypass box, let's pretend it's
// a simple path
`endif
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
if (!R) (posedge C => (Q : D)) = 1391;
endspecify
`endif
endmodule
(* abc9_flop, lib_whitebox *)
module SB_DFFSS (
output reg Q,
input C, S, D
);
`SB_DFF_INIT
always @(posedge C)
if (S)
Q <= 1;
else
Q <= D;
`ifdef ICE40_HX
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
// minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
$setup(D, posedge C, 470 - 449);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L78
$setup(S, posedge C, 203);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
if ( S) (posedge C => (Q : 1'b1)) = 540;
if (!S) (posedge C => (Q : D)) = 540;
endspecify
`endif
`ifdef ICE40_LP
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
// minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
$setup(D, posedge C, 693 - 662);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L78
$setup(S, posedge C, 299);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
if ( S) (posedge C => (Q : 1'b1)) = 796;
if (!S) (posedge C => (Q : D)) = 796;
endspecify
`endif
`ifdef ICE40_U
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
// minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
$setup(D, posedge C, /*1232 - 1285*/ 0); // Negative times not currently supported
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L90
$setup(S, posedge C, 530);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
if ( S) (posedge C => (Q : 1'b1)) = 1391;
if (!S) (posedge C => (Q : D)) = 1391;
endspecify
`endif
endmodule
(* abc9_box, lib_whitebox *)
module SB_DFFS (
output reg Q,
input C, S, D
);
`SB_DFF_INIT
always @(posedge C, posedge S)
if (S)
Q <= 1;
else
Q <= D;
`ifdef ICE40_HX
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
// minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
$setup(D, posedge C, 470 - 449);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L63
$setup(negedge S, posedge C, 160);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L91
`ifndef YOSYS
(posedge S => (Q : 1'b1)) = 599;
`else
if (S) (S => Q) = 599; // Technically, this should be an edge sensitive path
// but for facilitating a bypass box, let's pretend it's
// a simple path
`endif
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
if (!S) (posedge C => (Q : D)) = 540;
endspecify
`endif
`ifdef ICE40_LP
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
// minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
$setup(D, posedge C, 693 - 662);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L63
$setup(negedge S, posedge C, 235);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L91
`ifndef YOSYS
(posedge S => (Q : 1'b1)) = 883;
`else
if (S) (S => Q) = 883; // Technically, this should be an edge sensitive path
// but for facilitating a bypass box, let's pretend it's
// a simple path
`endif
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
if (!S) (posedge C => (Q : D)) = 796;
endspecify
`endif
`ifdef ICE40_U
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
// minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
$setup(D, posedge C, /*1232 - 1285*/ 0); // Negative times not currently supported
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L75
$setup(negedge S, posedge C, 424);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L103
`ifndef YOSYS
(posedge S => (Q : 1'b1)) = 1589;
`else
if (S) (S => Q) = 1589; // Technically, this should be an edge sensitive path
// but for facilitating a bypass box, let's pretend it's
// a simple path
`endif
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
if (!S) (posedge C => (Q : D)) = 1391;
endspecify
`endif
endmodule
(* abc9_flop, lib_whitebox *)
module SB_DFFESR (
output reg Q,
input C, E `ICE40_DEFAULT_ASSIGNMENT_1, R, D
);
`SB_DFF_INIT
always @(posedge C)
if (E) begin
if (R)
Q <= 0;
else
Q <= D;
end
`ifdef ICE40_HX
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
// minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
$setup(D, posedge C &&& E && !R, 470 - 449);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
$setup(E, posedge C, 0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L78
$setup(R, posedge C &&& E, 203);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
if (E && R) (posedge C => (Q : 1'b0)) = 540;
if (E && !R) (posedge C => (Q : D)) = 540;
endspecify
`endif
`ifdef ICE40_LP
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
// minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
$setup(D, posedge C &&& E && !R, 693 - 662);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L73
$setup(E, posedge C, 0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L78
$setup(R, posedge C &&& E, 299);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
if (E && R) (posedge C => (Q : 1'b0)) = 796;
if (E && !R) (posedge C => (Q : D)) = 796;
endspecify
`endif
`ifdef ICE40_U
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
// minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
$setup(D, posedge C &&& E, /*1232 - 1285*/ 0); // Negative times not currently supported
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L86
$setup(E, posedge C, 0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L90
$setup(R, posedge C &&& E, 530);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
if (E && R) (posedge C => (Q : 1'b0)) = 1391;
if (E && !R) (posedge C => (Q : D)) = 1391;
endspecify
`endif
endmodule
(* abc9_box, lib_whitebox *)
module SB_DFFER (
output reg Q,
input C, E `ICE40_DEFAULT_ASSIGNMENT_1, R, D
);
`SB_DFF_INIT
always @(posedge C, posedge R)
if (R)
Q <= 0;
else if (E)
Q <= D;
`ifdef ICE40_HX
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
// minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
$setup(D, posedge C &&& E, 470 - 449);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
$setup(E, posedge C, 0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L63
$setup(negedge R, posedge C, 160);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L91
`ifndef YOSYS
(posedge R => (Q : 1'b0)) = 599;
`else
if (R) (R => Q) = 599; // Technically, this should be an edge sensitive path
// but for facilitating a bypass box, let's pretend it's
// a simple path
`endif
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
if (E && !R) (posedge C => (Q : D)) = 540;
endspecify
`endif
`ifdef ICE40_LP
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
// minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
$setup(D, posedge C &&& E, 693 - 662);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L73
$setup(E, posedge C, 0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L63
$setup(negedge R, posedge C, 235);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L91
`ifndef YOSYS
(posedge R => (Q : 1'b0)) = 883;
`else
if (R) (R => Q) = 883; // Technically, this should be an edge sensitive path
// but for facilitating a bypass box, let's pretend it's
// a simple path
`endif
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
if (E && !R) (posedge C => (Q : D)) = 796;
endspecify
`endif
`ifdef ICE40_U
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
// minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
$setup(D, posedge C &&& E, /*1232 - 1285*/ 0); // Negative times not currently supported
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L86
$setup(E, posedge C, 0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L75
$setup(negedge R, posedge C, 424);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L103
`ifndef YOSYS
(posedge R => (Q : 1'b0)) = 1589;
`else
if (R) (R => Q) = 1589; // Technically, this should be an edge sensitive path
// but for facilitating a bypass box, let's pretend it's
// a simple path
`endif
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
if (E && !R) (posedge C => (Q : D)) = 1391;
endspecify
`endif
endmodule
(* abc9_flop, lib_whitebox *)
module SB_DFFESS (
output reg Q,
input C, E `ICE40_DEFAULT_ASSIGNMENT_1, S, D
);
`SB_DFF_INIT
always @(posedge C)
if (E) begin
if (S)
Q <= 1;
else
Q <= D;
end
`ifdef ICE40_HX
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
// minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
$setup(D, posedge C &&& E && !S, 470 - 449);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
$setup(E, posedge C, 0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L78
$setup(S, posedge C &&& E, 203);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
if (E && S) (posedge C => (Q : 1'b1)) = 540;
if (E && !S) (posedge C => (Q : D)) = 540;
endspecify
`endif
`ifdef ICE40_LP
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
// minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
$setup(D, posedge C &&& E && !S, 693 - 662);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L73
$setup(E, posedge C, 0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L78
$setup(S, posedge C &&& E, 299);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
if (E && S) (posedge C => (Q : 1'b1)) = 796;
if (E && !S) (posedge C => (Q : D)) = 796;
endspecify
`endif
`ifdef ICE40_U
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
// minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
$setup(D, posedge C &&& E, /*1232 - 1285*/ 0); // Negative times not currently supported
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L86
$setup(E, posedge C, 0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L90
$setup(S, posedge C &&& E, 530);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
if (E && S) (posedge C => (Q : 1'b1)) = 1391;
if (E && !S) (posedge C => (Q : D)) = 1391;
endspecify
`endif
endmodule
(* abc9_box, lib_whitebox *)
module SB_DFFES (
output reg Q,
input C, E `ICE40_DEFAULT_ASSIGNMENT_1, S, D
);
`SB_DFF_INIT
always @(posedge C, posedge S)
if (S)
Q <= 1;
else if (E)
Q <= D;
`ifdef ICE40_HX
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
// minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
$setup(D, posedge C &&& E, 470 - 449);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
$setup(E, posedge C, 0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L63
$setup(posedge S, posedge C, 160);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L91
`ifndef YOSYS
(posedge S => (Q : 1'b1)) = 599;
`else
if (S) (S => Q) = 599; // Technically, this should be an edge sensitive path
// but for facilitating a bypass box, let's pretend it's
// a simple path
`endif
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
if (E && !S) (posedge C => (Q : D)) = 540;
endspecify
`endif
`ifdef ICE40_LP
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
// minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
$setup(D, posedge C &&& E, 693 - 662);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L73
$setup(E, posedge C, 0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L63
$setup(posedge S, posedge C, 235);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L91
`ifndef YOSYS
(posedge S => (Q : 1'b1)) = 883;
`else
if (S) (S => Q) = 883; // Technically, this should be an edge sensitive path
// but for facilitating a bypass box, let's pretend it's
// a simple path
`endif
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
if (E && !S) (posedge C => (Q : D)) = 796;
endspecify
`endif
`ifdef ICE40_U
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
// minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
$setup(D, posedge C &&& E, /*1232 - 1285*/ 0); // Negative times not currently supported
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L86
$setup(E, posedge C, 0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L75
$setup(posedge S, posedge C, 424);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L103
`ifndef YOSYS
(posedge S => (Q : 1'b1)) = 1589;
`else
if (S) (S => Q) = 1589; // Technically, this should be an edge sensitive path
// but for facilitating a bypass box, let's pretend it's
// a simple path
`endif
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
if (E && !S) (posedge C => (Q : D)) = 1391;
endspecify
`endif
endmodule
// Negative Edge SiliconBlue FF Cells
(* abc9_flop, lib_whitebox *)
module SB_DFFN (
output reg Q,
input C, D
);
`SB_DFF_INIT
always @(negedge C)
Q <= D;
`ifdef ICE40_HX
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
// minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
$setup(D, negedge C, 470 - 449);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
(negedge C => (Q : D)) = 540;
endspecify
`endif
`ifdef ICE40_LP
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
// minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
$setup(D, negedge C, 693 - 662);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
(negedge C => (Q : D)) = 796;
endspecify
`endif
`ifdef ICE40_U
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
// minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
$setup(D, negedge C, /*1232 - 1285*/ 0); // Negative times not currently supported
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
(negedge C => (Q : D)) = 1391;
endspecify
`endif
endmodule
(* abc9_flop, lib_whitebox *)
module SB_DFFNE (
output reg Q,
input C, E `ICE40_DEFAULT_ASSIGNMENT_1, D
);
`SB_DFF_INIT
always @(negedge C)
if (E)
Q <= D;
`ifdef ICE40_HX
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
// minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
$setup(D, negedge C &&& E, 470 - 449);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
$setup(E, negedge C, 0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
if (E) (negedge C => (Q : D)) = 540;
endspecify
`endif
`ifdef ICE40_LP
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
// minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
$setup(D, negedge C &&& E, 693 - 662);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L73
$setup(E, negedge C, 0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
if (E) (negedge C => (Q : D)) = 796;
endspecify
`endif
`ifdef ICE40_U
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
// minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
$setup(D, negedge C &&& E, /*1232 - 1285*/ 0); // Negative times not currently supported
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L86
$setup(E, negedge C, 0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
if (E) (negedge C => (Q : D)) = 1391;
endspecify
`endif
endmodule
(* abc9_flop, lib_whitebox *)
module SB_DFFNSR (
output reg Q,
input C, R, D
);
`SB_DFF_INIT
always @(negedge C)
if (R)
Q <= 0;
else
Q <= D;
`ifdef ICE40_HX
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
// minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
$setup(D, negedge C, 470 - 449);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
$setup(R, negedge C, 203);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
if ( R) (negedge C => (Q : 1'b0)) = 540;
if (!R) (negedge C => (Q : D)) = 540;
endspecify
`endif
`ifdef ICE40_LP
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
// minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
$setup(D, negedge C, 693 - 662);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L78
$setup(R, negedge C, 299);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
if ( R) (negedge C => (Q : 1'b0)) = 796;
if (!R) (negedge C => (Q : D)) = 796;
endspecify
`endif
`ifdef ICE40_U
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
// minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
$setup(D, negedge C, /*1232 - 1285*/ 0); // Negative times not currently supported
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L90
$setup(R, negedge C, 530);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
if ( R) (negedge C => (Q : 1'b0)) = 1391;
if (!R) (negedge C => (Q : D)) = 1391;
endspecify
`endif
endmodule
(* abc9_flop, lib_whitebox *)
module SB_DFFNR (
output reg Q,
input C, R, D
);
`SB_DFF_INIT
always @(negedge C, posedge R)
if (R)
Q <= 0;
else
Q <= D;
`ifdef ICE40_HX
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
// minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
$setup(D, negedge C, 470 - 449);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L63
$setup(negedge R, negedge C, 160);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L91
`ifndef YOSYS
(posedge R => (Q : 1'b0)) = 599;
`else
if (R) (R => Q) = 599; // Technically, this should be an edge sensitive path
// but for facilitating a bypass box, let's pretend it's
// a simple path
`endif
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
if (!R) (negedge C => (Q : D)) = 540;
endspecify
`endif
`ifdef ICE40_LP
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
// minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
$setup(D, negedge C, 693 - 662);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L63
$setup(negedge R, negedge C, 235);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L91
`ifndef YOSYS
(posedge R => (Q : 1'b0)) = 883;
`else
if (R) (R => Q) = 883; // Technically, this should be an edge sensitive path
// but for facilitating a bypass box, let's pretend it's
// a simple path
`endif
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
if (!R) (negedge C => (Q : D)) = 796;
endspecify
`endif
`ifdef ICE40_U
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
// minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
$setup(D, negedge C, /*1232 - 1285*/ 0); // Negative times not currently supported
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L75
$setup(negedge R, negedge C, 424);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L103
`ifndef YOSYS
(posedge R => (Q : 1'b0)) = 1589;
`else
if (R) (R => Q) = 1589; // Technically, this should be an edge sensitive path
// but for facilitating a bypass box, let's pretend it's
// a simple path
`endif
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
if (!R) (negedge C => (Q : D)) = 1391;
endspecify
`endif
endmodule
(* abc9_flop, lib_whitebox *)
module SB_DFFNSS (
output reg Q,
input C, S, D
);
`SB_DFF_INIT
always @(negedge C)
if (S)
Q <= 1;
else
Q <= D;
`ifdef ICE40_HX
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
// minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
$setup(D, negedge C, 470 - 449);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
$setup(S, negedge C, 203);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
if ( S) (negedge C => (Q : 1'b1)) = 540;
if (!S) (negedge C => (Q : D)) = 540;
endspecify
`endif
`ifdef ICE40_LP
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
// minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
$setup(D, negedge C, 693 - 662);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L78
$setup(S, negedge C, 299);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
if ( S) (negedge C => (Q : 1'b1)) = 796;
if (!S) (negedge C => (Q : D)) = 796;
endspecify
`endif
`ifdef ICE40_U
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
// minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
$setup(D, negedge C, /*1232 - 1285*/ 0); // Negative times not currently supported
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L90
$setup(S, negedge C, 530);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
if ( S) (negedge C => (Q : 1'b1)) = 1391;
if (!S) (negedge C => (Q : D)) = 1391;
endspecify
`endif
endmodule
(* abc9_box, lib_whitebox *)
module SB_DFFNS (
output reg Q,
input C, S, D
);
`SB_DFF_INIT
always @(negedge C, posedge S)
if (S)
Q <= 1;
else
Q <= D;
`ifdef ICE40_HX
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
// minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
$setup(D, negedge C, 470 - 449);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L63
$setup(negedge S, negedge C, 160);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L91
`ifndef YOSYS
(posedge S => (Q : 1'b1)) = 599;
`else
if (S) (S => Q) = 599; // Technically, this should be an edge sensitive path
// but for facilitating a bypass box, let's pretend it's
// a simple path
`endif
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
if (!S) (negedge C => (Q : D)) = 540;
endspecify
`endif
`ifdef ICE40_LP
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
// minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
$setup(D, negedge C, 693 - 662);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L63
$setup(negedge S, negedge C, 235);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L91
`ifndef YOSYS
(posedge S => (Q : 1'b1)) = 883;
`else
if (S) (S => Q) = 883; // Technically, this should be an edge sensitive path
// but for facilitating a bypass box, let's pretend it's
// a simple path
`endif
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
if (!S) (negedge C => (Q : D)) = 796;
endspecify
`endif
`ifdef ICE40_U
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
// minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
$setup(D, negedge C, /*1232 - 1285*/ 0); // Negative times not currently supported
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L75
$setup(negedge S, negedge C, 424);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L103
`ifndef YOSYS
(posedge S => (Q : 1'b1)) = 1589;
`else
if (S) (S => Q) = 1589; // Technically, this should be an edge sensitive path
// but for facilitating a bypass box, let's pretend it's
// a simple path
`endif
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
if (!S) (negedge C => (Q : D)) = 1391;
endspecify
`endif
endmodule
(* abc9_flop, lib_whitebox *)
module SB_DFFNESR (
output reg Q,
input C, E `ICE40_DEFAULT_ASSIGNMENT_1, R, D
);
`SB_DFF_INIT
always @(negedge C)
if (E) begin
if (R)
Q <= 0;
else
Q <= D;
end
`ifdef ICE40_HX
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
// minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
$setup(D, negedge C &&& E && !R, 470 - 449);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
$setup(E, negedge C, 0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L78
$setup(R, negedge C &&& E, 203);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
if (E && R) (negedge C => (Q : 1'b0)) = 540;
if (E && !R) (negedge C => (Q : D)) = 540;
endspecify
`endif
`ifdef ICE40_LP
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
// minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
$setup(D, negedge C &&& E && !R, 693 - 662);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L73
$setup(E, negedge C, 0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L78
$setup(R, negedge C &&& E, 299);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
if (E && R) (negedge C => (Q : 1'b0)) = 796;
if (E && !R) (negedge C => (Q : D)) = 796;
endspecify
`endif
`ifdef ICE40_U
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
// minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
$setup(D, negedge C &&& E, /*1232 - 1285*/ 0); // Negative times not currently supported
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L86
$setup(E, negedge C, 0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L90
$setup(R, negedge C &&& E, 530);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
if (E && R) (negedge C => (Q : 1'b0)) = 1391;
if (E && !R) (negedge C => (Q : D)) = 1391;
endspecify
`endif
endmodule
(* abc9_box, lib_whitebox *)
module SB_DFFNER (
output reg Q,
input C, E `ICE40_DEFAULT_ASSIGNMENT_1, R, D
);
`SB_DFF_INIT
always @(negedge C, posedge R)
if (R)
Q <= 0;
else if (E)
Q <= D;
`ifdef ICE40_HX
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
// minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
$setup(D, negedge C &&& E, 470 - 449);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
$setup(E, negedge C, 0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L63
$setup(R, negedge C, 2160);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L91
`ifndef YOSYS
(posedge R => (Q : 1'b0)) = 599;
`else
if (R) (R => Q) = 599; // Technically, this should be an edge sensitive path
// but for facilitating a bypass box, let's pretend it's
// a simple path
`endif
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
if (E && !R) (negedge C => (Q : D)) = 540;
endspecify
`endif
`ifdef ICE40_LP
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
// minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
$setup(D, negedge C &&& E, 693 - 662);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L73
$setup(E, negedge C, 0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L63
$setup(R, negedge C, 235);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L91
`ifndef YOSYS
(posedge R => (Q : 1'b0)) = 883;
`else
if (R) (R => Q) = 883; // Technically, this should be an edge sensitive path
// but for facilitating a bypass box, let's pretend it's
// a simple path
`endif
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
if (E && !R) (negedge C => (Q : D)) = 796;
endspecify
`endif
`ifdef ICE40_U
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
// minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
$setup(D, negedge C &&& E, /*1232 - 1285*/ 0); // Negative times not currently supported
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L86
$setup(E, negedge C, 0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L75
$setup(negedge R, negedge C, 424);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L103
`ifndef YOSYS
(posedge R => (Q : 1'b0)) = 1589;
`else
if (R) (R => Q) = 1589; // Technically, this should be an edge sensitive path
// but for facilitating a bypass box, let's pretend it's
// a simple path
`endif
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
if (E && !R) (negedge C => (Q : D)) = 1391;
endspecify
`endif
endmodule
(* abc9_flop, lib_whitebox *)
module SB_DFFNESS (
output reg Q,
input C, E `ICE40_DEFAULT_ASSIGNMENT_1, S, D
);
`SB_DFF_INIT
always @(negedge C)
if (E) begin
if (S)
Q <= 1;
else
Q <= D;
end
`ifdef ICE40_HX
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
// minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
$setup(D, negedge C &&& E && !S, 470 - 449);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
$setup(E, negedge C, 0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L78
$setup(S, negedge C &&& E, 203);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
if (E && S) (negedge C => (Q : 1'b1)) = 540;
if (E && !S) (negedge C => (Q : D)) = 540;
endspecify
`endif
`ifdef ICE40_LP
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
// minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
$setup(D, negedge C &&& E && !S, 693 - 662);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L73
$setup(E, negedge C, 0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L78
$setup(S, negedge C &&& E, 299);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
if (E && S) (negedge C => (Q : 1'b1)) = 796;
if (E && !S) (negedge C => (Q : D)) = 796;
endspecify
`endif
`ifdef ICE40_U
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
// minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
$setup(D, negedge C &&& E, /*1232 - 1285*/ 0); // Negative times not currently supported
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L86
$setup(E, negedge C, 0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L90
$setup(S, negedge C &&& E, 530);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
if (E && S) (negedge C => (Q : 1'b1)) = 1391;
if (E && !S) (negedge C => (Q : D)) = 1391;
endspecify
`endif
endmodule
(* abc9_box, lib_whitebox *)
module SB_DFFNES (
output reg Q,
input C, E `ICE40_DEFAULT_ASSIGNMENT_1, S, D
);
`SB_DFF_INIT
always @(negedge C, posedge S)
if (S)
Q <= 1;
else if (E)
Q <= D;
`ifdef ICE40_HX
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
// minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
$setup(D, negedge C &&& E, 470 - 449);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
$setup(E, negedge C, 0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L63
$setup(negedge S, negedge C, 160);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L91
`ifndef YOSYS
(posedge S => (Q : 1'b1)) = 599;
`else
if (S) (S => Q) = 599; // Technically, this should be an edge sensitive path
// but for facilitating a bypass box, let's pretend it's
// a simple path
`endif
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
if (E && !S) (negedge C => (Q : D)) = 540;
endspecify
`endif
`ifdef ICE40_LP
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
// minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
$setup(D, negedge C &&& E, 693 - 662);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L73
$setup(E, negedge C, 0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L63
$setup(negedge S, negedge C, 235);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L91
`ifndef YOSYS
(posedge S => (Q : 1'b1)) = 883;
`else
if (S) (S => Q) = 883; // Technically, this should be an edge sensitive path
// but for facilitating a bypass box, let's pretend it's
// a simple path
`endif
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
if (E && !S) (negedge C => (Q : D)) = 796;
endspecify
`endif
`ifdef ICE40_U
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
// minus https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
$setup(D, negedge C &&& E, /*1232 - 1285*/ 0); // Negative times not currently supported
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L86
$setup(E, negedge C, 0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L75
$setup(negedge S, negedge C, 424);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L103
`ifndef YOSYS
(posedge S => (Q : 1'b1)) = 1589;
`else
if (S) (S => Q) = 1589; // Technically, this should be an edge sensitive path
// but for facilitating a bypass box, let's pretend it's
// a simple path
`endif
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
if (E && !S) (negedge C => (Q : D)) = 1391;
endspecify
`endif
endmodule
// SiliconBlue RAM Cells
module SB_RAM40_4K (
output [15:0] RDATA,
input RCLK,
input RCLKE `ICE40_DEFAULT_ASSIGNMENT_1,
input RE `ICE40_DEFAULT_ASSIGNMENT_0,
input [10:0] RADDR,
input WCLK,
input WCLKE `ICE40_DEFAULT_ASSIGNMENT_1,
input WE `ICE40_DEFAULT_ASSIGNMENT_0,
input [10:0] WADDR,
input [15:0] MASK `ICE40_DEFAULT_ASSIGNMENT_V(16'h 0000),
input [15:0] WDATA
);
// MODE 0: 256 x 16
// MODE 1: 512 x 8
// MODE 2: 1024 x 4
// MODE 3: 2048 x 2
parameter WRITE_MODE = 0;
parameter READ_MODE = 0;
parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_FILE = "";
`ifndef BLACKBOX
wire [15:0] WMASK_I;
wire [15:0] RMASK_I;
reg [15:0] RDATA_I;
wire [15:0] WDATA_I;
generate
case (WRITE_MODE)
0: assign WMASK_I = MASK;
1: assign WMASK_I = WADDR[ 8] == 0 ? 16'b 1010_1010_1010_1010 :
WADDR[ 8] == 1 ? 16'b 0101_0101_0101_0101 : 16'bx;
2: assign WMASK_I = WADDR[ 9:8] == 0 ? 16'b 1110_1110_1110_1110 :
WADDR[ 9:8] == 1 ? 16'b 1101_1101_1101_1101 :
WADDR[ 9:8] == 2 ? 16'b 1011_1011_1011_1011 :
WADDR[ 9:8] == 3 ? 16'b 0111_0111_0111_0111 : 16'bx;
3: assign WMASK_I = WADDR[10:8] == 0 ? 16'b 1111_1110_1111_1110 :
WADDR[10:8] == 1 ? 16'b 1111_1101_1111_1101 :
WADDR[10:8] == 2 ? 16'b 1111_1011_1111_1011 :
WADDR[10:8] == 3 ? 16'b 1111_0111_1111_0111 :
WADDR[10:8] == 4 ? 16'b 1110_1111_1110_1111 :
WADDR[10:8] == 5 ? 16'b 1101_1111_1101_1111 :
WADDR[10:8] == 6 ? 16'b 1011_1111_1011_1111 :
WADDR[10:8] == 7 ? 16'b 0111_1111_0111_1111 : 16'bx;
endcase
case (READ_MODE)
0: assign RMASK_I = 16'b 0000_0000_0000_0000;
1: assign RMASK_I = RADDR[ 8] == 0 ? 16'b 1010_1010_1010_1010 :
RADDR[ 8] == 1 ? 16'b 0101_0101_0101_0101 : 16'bx;
2: assign RMASK_I = RADDR[ 9:8] == 0 ? 16'b 1110_1110_1110_1110 :
RADDR[ 9:8] == 1 ? 16'b 1101_1101_1101_1101 :
RADDR[ 9:8] == 2 ? 16'b 1011_1011_1011_1011 :
RADDR[ 9:8] == 3 ? 16'b 0111_0111_0111_0111 : 16'bx;
3: assign RMASK_I = RADDR[10:8] == 0 ? 16'b 1111_1110_1111_1110 :
RADDR[10:8] == 1 ? 16'b 1111_1101_1111_1101 :
RADDR[10:8] == 2 ? 16'b 1111_1011_1111_1011 :
RADDR[10:8] == 3 ? 16'b 1111_0111_1111_0111 :
RADDR[10:8] == 4 ? 16'b 1110_1111_1110_1111 :
RADDR[10:8] == 5 ? 16'b 1101_1111_1101_1111 :
RADDR[10:8] == 6 ? 16'b 1011_1111_1011_1111 :
RADDR[10:8] == 7 ? 16'b 0111_1111_0111_1111 : 16'bx;
endcase
case (WRITE_MODE)
0: assign WDATA_I = WDATA;
1: assign WDATA_I = {WDATA[14], WDATA[14], WDATA[12], WDATA[12],
WDATA[10], WDATA[10], WDATA[ 8], WDATA[ 8],
WDATA[ 6], WDATA[ 6], WDATA[ 4], WDATA[ 4],
WDATA[ 2], WDATA[ 2], WDATA[ 0], WDATA[ 0]};
2: assign WDATA_I = {WDATA[13], WDATA[13], WDATA[13], WDATA[13],
WDATA[ 9], WDATA[ 9], WDATA[ 9], WDATA[ 9],
WDATA[ 5], WDATA[ 5], WDATA[ 5], WDATA[ 5],
WDATA[ 1], WDATA[ 1], WDATA[ 1], WDATA[ 1]};
3: assign WDATA_I = {WDATA[11], WDATA[11], WDATA[11], WDATA[11],
WDATA[11], WDATA[11], WDATA[11], WDATA[11],
WDATA[ 3], WDATA[ 3], WDATA[ 3], WDATA[ 3],
WDATA[ 3], WDATA[ 3], WDATA[ 3], WDATA[ 3]};
endcase
case (READ_MODE)
0: assign RDATA = RDATA_I;
1: assign RDATA = {1'b0, |RDATA_I[15:14], 1'b0, |RDATA_I[13:12], 1'b0, |RDATA_I[11:10], 1'b0, |RDATA_I[ 9: 8],
1'b0, |RDATA_I[ 7: 6], 1'b0, |RDATA_I[ 5: 4], 1'b0, |RDATA_I[ 3: 2], 1'b0, |RDATA_I[ 1: 0]};
2: assign RDATA = {2'b0, |RDATA_I[15:12], 3'b0, |RDATA_I[11: 8], 3'b0, |RDATA_I[ 7: 4], 3'b0, |RDATA_I[ 3: 0], 1'b0};
3: assign RDATA = {4'b0, |RDATA_I[15: 8], 7'b0, |RDATA_I[ 7: 0], 3'b0};
endcase
endgenerate
integer i;
reg [15:0] memory [0:255];
initial begin
if (INIT_FILE != "")
$readmemh(INIT_FILE, memory);
else
for (i=0; i<16; i=i+1) begin
memory[ 0*16 + i] = INIT_0[16*i +: 16];
memory[ 1*16 + i] = INIT_1[16*i +: 16];
memory[ 2*16 + i] = INIT_2[16*i +: 16];
memory[ 3*16 + i] = INIT_3[16*i +: 16];
memory[ 4*16 + i] = INIT_4[16*i +: 16];
memory[ 5*16 + i] = INIT_5[16*i +: 16];
memory[ 6*16 + i] = INIT_6[16*i +: 16];
memory[ 7*16 + i] = INIT_7[16*i +: 16];
memory[ 8*16 + i] = INIT_8[16*i +: 16];
memory[ 9*16 + i] = INIT_9[16*i +: 16];
memory[10*16 + i] = INIT_A[16*i +: 16];
memory[11*16 + i] = INIT_B[16*i +: 16];
memory[12*16 + i] = INIT_C[16*i +: 16];
memory[13*16 + i] = INIT_D[16*i +: 16];
memory[14*16 + i] = INIT_E[16*i +: 16];
memory[15*16 + i] = INIT_F[16*i +: 16];
end
end
always @(posedge WCLK) begin
if (WE && WCLKE) begin
if (!WMASK_I[ 0]) memory[WADDR[7:0]][ 0] <= WDATA_I[ 0];
if (!WMASK_I[ 1]) memory[WADDR[7:0]][ 1] <= WDATA_I[ 1];
if (!WMASK_I[ 2]) memory[WADDR[7:0]][ 2] <= WDATA_I[ 2];
if (!WMASK_I[ 3]) memory[WADDR[7:0]][ 3] <= WDATA_I[ 3];
if (!WMASK_I[ 4]) memory[WADDR[7:0]][ 4] <= WDATA_I[ 4];
if (!WMASK_I[ 5]) memory[WADDR[7:0]][ 5] <= WDATA_I[ 5];
if (!WMASK_I[ 6]) memory[WADDR[7:0]][ 6] <= WDATA_I[ 6];
if (!WMASK_I[ 7]) memory[WADDR[7:0]][ 7] <= WDATA_I[ 7];
if (!WMASK_I[ 8]) memory[WADDR[7:0]][ 8] <= WDATA_I[ 8];
if (!WMASK_I[ 9]) memory[WADDR[7:0]][ 9] <= WDATA_I[ 9];
if (!WMASK_I[10]) memory[WADDR[7:0]][10] <= WDATA_I[10];
if (!WMASK_I[11]) memory[WADDR[7:0]][11] <= WDATA_I[11];
if (!WMASK_I[12]) memory[WADDR[7:0]][12] <= WDATA_I[12];
if (!WMASK_I[13]) memory[WADDR[7:0]][13] <= WDATA_I[13];
if (!WMASK_I[14]) memory[WADDR[7:0]][14] <= WDATA_I[14];
if (!WMASK_I[15]) memory[WADDR[7:0]][15] <= WDATA_I[15];
end
end
always @(posedge RCLK) begin
if (RE && RCLKE) begin
RDATA_I <= memory[RADDR[7:0]] & ~RMASK_I;
end
end
`endif
`ifdef ICE40_HX
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L343-L358
$setup(MASK, posedge WCLK &&& WE && WCLKE, 274);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L359-L369
$setup(RADDR, posedge RCLK &&& RE && RCLKE, 203);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L370
$setup(RCLKE, posedge RCLK, 267);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L371
$setup(RE, posedge RCLK, 98);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L372-L382
$setup(WADDR, posedge WCLK &&& WE && WCLKE, 224);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L383
$setup(WCLKE, posedge WCLK, 267);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L384-L399
$setup(WDATA, posedge WCLK &&& WE && WCLKE, 161);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L400
$setup(WE, posedge WCLK, 133);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
(posedge RCLK => (RDATA : 16'bx)) = 2146;
endspecify
`endif
`ifdef ICE40_LP
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L343-L358
$setup(MASK, posedge WCLK &&& WE && WCLKE, 403);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L359-L369
$setup(RADDR, posedge RCLK &&& RE && RCLKE, 300);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L370
$setup(RCLKE, posedge RCLK, 393);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L371
$setup(RE, posedge RCLK, 145);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L372-L382
$setup(WADDR, posedge WCLK &&& WE && WCLKE, 331);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L383
$setup(WCLKE, posedge WCLK, 393);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L384-L399
$setup(WDATA, posedge WCLK &&& WE && WCLKE, 238);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L400
$setup(WE, posedge WCLK, 196);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
(posedge RCLK => (RDATA : 16'bx)) = 3163;
endspecify
`endif
`ifdef ICE40_U
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12968-12983
$setup(MASK, posedge WCLK &&& WE && WCLKE, 517);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12984-12994
$setup(RADDR, posedge RCLK &&& RE && RCLKE, 384);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12995
$setup(RCLKE, posedge RCLK, 503);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12996
$setup(RE, posedge RCLK, 185);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12997-13007
$setup(WADDR, posedge WCLK &&& WE && WCLKE, 424);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13008
$setup(WCLKE, posedge WCLK, 503);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13009-13024
$setup(WDATA, posedge WCLK &&& WE && WCLKE, 305);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13025
$setup(WE, posedge WCLK, 252);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
(posedge RCLK => (RDATA : 16'bx)) = 1179;
endspecify
`endif
endmodule
module SB_RAM40_4KNR (
output [15:0] RDATA,
input RCLKN,
input RCLKE `ICE40_DEFAULT_ASSIGNMENT_1,
input RE `ICE40_DEFAULT_ASSIGNMENT_0,
input [10:0] RADDR,
input WCLK,
input WCLKE `ICE40_DEFAULT_ASSIGNMENT_1,
input WE `ICE40_DEFAULT_ASSIGNMENT_0,
input [10:0] WADDR,
input [15:0] MASK `ICE40_DEFAULT_ASSIGNMENT_V(16'h 0000),
input [15:0] WDATA
);
parameter WRITE_MODE = 0;
parameter READ_MODE = 0;
parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_FILE = "";
SB_RAM40_4K #(
.WRITE_MODE(WRITE_MODE),
.READ_MODE (READ_MODE ),
.INIT_0 (INIT_0 ),
.INIT_1 (INIT_1 ),
.INIT_2 (INIT_2 ),
.INIT_3 (INIT_3 ),
.INIT_4 (INIT_4 ),
.INIT_5 (INIT_5 ),
.INIT_6 (INIT_6 ),
.INIT_7 (INIT_7 ),
.INIT_8 (INIT_8 ),
.INIT_9 (INIT_9 ),
.INIT_A (INIT_A ),
.INIT_B (INIT_B ),
.INIT_C (INIT_C ),
.INIT_D (INIT_D ),
.INIT_E (INIT_E ),
.INIT_F (INIT_F ),
.INIT_FILE (INIT_FILE )
) RAM (
.RDATA(RDATA),
.RCLK (~RCLKN),
.RCLKE(RCLKE),
.RE (RE ),
.RADDR(RADDR),
.WCLK (WCLK ),
.WCLKE(WCLKE),
.WE (WE ),
.WADDR(WADDR),
.MASK (MASK ),
.WDATA(WDATA)
);
`ifdef ICE40_HX
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L343-L358
$setup(MASK, posedge WCLK &&& WE && WCLKE, 274);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L359-L369
$setup(RADDR, posedge RCLKN &&& RE && RCLKE, 203);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L370
$setup(RCLKE, posedge RCLKN, 267);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L371
$setup(RE, posedge RCLKN, 98);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L372-L382
$setup(WADDR, posedge WCLK &&& WE && WCLKE, 224);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L383
$setup(WCLKE, posedge WCLK, 267);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L384-L399
$setup(WDATA, posedge WCLK &&& WE && WCLKE, 161);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L400
$setup(WE, posedge WCLK, 133);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
(posedge RCLKN => (RDATA : 16'bx)) = 2146;
endspecify
`endif
`ifdef ICE40_LP
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L343-L358
$setup(MASK, posedge WCLK &&& WE && WCLKE, 403);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L359-L369
$setup(RADDR, posedge RCLKN &&& RE && RCLKE, 300);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L370
$setup(RCLKE, posedge RCLKN, 393);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L371
$setup(RE, posedge RCLKN, 145);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L372-L382
$setup(WADDR, posedge WCLK &&& WE && WCLKE, 331);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L383
$setup(WCLKE, posedge WCLK, 393);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L384-L399
$setup(WDATA, posedge WCLK &&& WE && WCLKE, 238);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L400
$setup(WE, posedge WCLK, 196);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
(posedge RCLKN => (RDATA : 16'bx)) = 3163;
endspecify
`endif
`ifdef ICE40_U
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12968-12983
$setup(MASK, posedge WCLK &&& WE && WCLKE, 517);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12984-12994
$setup(RADDR, posedge RCLKN &&& RE && RCLKE, 384);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12995
$setup(RCLKE, posedge RCLKN, 503);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12996
$setup(RE, posedge RCLKN, 185);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12997-13007
$setup(WADDR, posedge WCLK &&& WE && WCLKE, 424);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13008
$setup(WCLKE, posedge WCLK, 503);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13009-13024
$setup(WDATA, posedge WCLK &&& WE && WCLKE, 305);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13025
$setup(WE, posedge WCLK, 252);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
(posedge RCLKN => (RDATA : 16'bx)) = 1179;
endspecify
`endif
endmodule
module SB_RAM40_4KNW (
output [15:0] RDATA,
input RCLK,
input RCLKE `ICE40_DEFAULT_ASSIGNMENT_1,
input RE `ICE40_DEFAULT_ASSIGNMENT_0,
input [10:0] RADDR,
input WCLKN,
input WCLKE `ICE40_DEFAULT_ASSIGNMENT_1,
input WE `ICE40_DEFAULT_ASSIGNMENT_0,
input [10:0] WADDR,
input [15:0] MASK `ICE40_DEFAULT_ASSIGNMENT_V(16'h 0000),
input [15:0] WDATA
);
parameter WRITE_MODE = 0;
parameter READ_MODE = 0;
parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_FILE = "";
SB_RAM40_4K #(
.WRITE_MODE(WRITE_MODE),
.READ_MODE (READ_MODE ),
.INIT_0 (INIT_0 ),
.INIT_1 (INIT_1 ),
.INIT_2 (INIT_2 ),
.INIT_3 (INIT_3 ),
.INIT_4 (INIT_4 ),
.INIT_5 (INIT_5 ),
.INIT_6 (INIT_6 ),
.INIT_7 (INIT_7 ),
.INIT_8 (INIT_8 ),
.INIT_9 (INIT_9 ),
.INIT_A (INIT_A ),
.INIT_B (INIT_B ),
.INIT_C (INIT_C ),
.INIT_D (INIT_D ),
.INIT_E (INIT_E ),
.INIT_F (INIT_F ),
.INIT_FILE (INIT_FILE )
) RAM (
.RDATA(RDATA),
.RCLK (RCLK ),
.RCLKE(RCLKE),
.RE (RE ),
.RADDR(RADDR),
.WCLK (~WCLKN),
.WCLKE(WCLKE),
.WE (WE ),
.WADDR(WADDR),
.MASK (MASK ),
.WDATA(WDATA)
);
`ifdef ICE40_HX
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L343-L358
$setup(MASK, posedge WCLKN &&& WE && WCLKE, 274);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L359-L369
$setup(RADDR, posedge RCLK &&& RE && RCLKE, 203);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L370
$setup(RCLKE, posedge RCLK, 267);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L371
$setup(RE, posedge RCLK, 98);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L372-L382
$setup(WADDR, posedge WCLKN &&& WE && WCLKE, 224);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L383
$setup(WCLKE, posedge WCLKN, 267);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L384-L399
$setup(WDATA, posedge WCLKN &&& WE && WCLKE, 161);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L400
$setup(WE, posedge WCLKN, 133);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
(posedge RCLK => (RDATA : 16'bx)) = 2146;
endspecify
`endif
`ifdef ICE40_LP
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L343-L358
$setup(MASK, posedge WCLKN &&& WE && WCLKE, 403);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L359-L369
$setup(RADDR, posedge RCLK &&& RE && RCLKE, 300);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L370
$setup(RCLKE, posedge RCLK, 393);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L371
$setup(RE, posedge RCLK, 145);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L372-L382
$setup(WADDR, posedge WCLKN &&& WE && WCLKE, 331);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L383
$setup(WCLKE, posedge WCLKN, 393);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L384-L399
$setup(WDATA, posedge WCLKN &&& WE && WCLKE, 238);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L400
$setup(WE, posedge WCLKN, 196);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
(posedge RCLK => (RDATA : 16'bx)) = 3163;
endspecify
`endif
`ifdef ICE40_U
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12968-12983
$setup(MASK, posedge WCLKN &&& WE && WCLKE, 517);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12984-12994
$setup(RADDR, posedge RCLK &&& RE && RCLKE, 384);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12995
$setup(RCLKE, posedge RCLK, 503);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12996
$setup(RE, posedge RCLK, 185);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12997-13007
$setup(WADDR, posedge WCLKN &&& WE && WCLKE, 424);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13008
$setup(WCLKE, posedge WCLKN, 503);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13009-13024
$setup(WDATA, posedge WCLKN &&& WE && WCLKE, 305);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13025
$setup(WE, posedge WCLKN, 252);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
(posedge RCLK => (RDATA : 16'bx)) = 1179;
endspecify
`endif
endmodule
module SB_RAM40_4KNRNW (
output [15:0] RDATA,
input RCLKN,
input RCLKE `ICE40_DEFAULT_ASSIGNMENT_1,
input RE `ICE40_DEFAULT_ASSIGNMENT_0,
input [10:0] RADDR,
input WCLKN,
input WCLKE `ICE40_DEFAULT_ASSIGNMENT_1,
input WE `ICE40_DEFAULT_ASSIGNMENT_0,
input [10:0] WADDR,
input [15:0] MASK `ICE40_DEFAULT_ASSIGNMENT_V(16'h 0000),
input [15:0] WDATA
);
parameter WRITE_MODE = 0;
parameter READ_MODE = 0;
parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_FILE = "";
SB_RAM40_4K #(
.WRITE_MODE(WRITE_MODE),
.READ_MODE (READ_MODE ),
.INIT_0 (INIT_0 ),
.INIT_1 (INIT_1 ),
.INIT_2 (INIT_2 ),
.INIT_3 (INIT_3 ),
.INIT_4 (INIT_4 ),
.INIT_5 (INIT_5 ),
.INIT_6 (INIT_6 ),
.INIT_7 (INIT_7 ),
.INIT_8 (INIT_8 ),
.INIT_9 (INIT_9 ),
.INIT_A (INIT_A ),
.INIT_B (INIT_B ),
.INIT_C (INIT_C ),
.INIT_D (INIT_D ),
.INIT_E (INIT_E ),
.INIT_F (INIT_F ),
.INIT_FILE (INIT_FILE )
) RAM (
.RDATA(RDATA),
.RCLK (~RCLKN),
.RCLKE(RCLKE),
.RE (RE ),
.RADDR(RADDR),
.WCLK (~WCLKN),
.WCLKE(WCLKE),
.WE (WE ),
.WADDR(WADDR),
.MASK (MASK ),
.WDATA(WDATA)
);
`ifdef ICE40_HX
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L343-L358
$setup(MASK, posedge WCLKN &&& WE && WCLKE, 274);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L359-L369
$setup(RADDR, posedge RCLKN &&& RE && RCLKE, 203);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L370
$setup(RCLKE, posedge RCLKN, 267);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L371
$setup(RE, posedge RCLKN, 98);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L372-L382
$setup(WADDR, posedge WCLKN &&& WE && WCLKE, 224);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L383
$setup(WCLKE, posedge WCLKN, 267);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L384-L399
$setup(WDATA, posedge WCLKN &&& WE && WCLKE, 161);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L400
$setup(WE, posedge WCLKN, 133);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
(posedge RCLKN => (RDATA : 16'bx)) = 2146;
endspecify
`endif
`ifdef ICE40_LP
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L343-L358
$setup(MASK, posedge WCLKN &&& WE && WCLKE, 403);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L359-L369
$setup(RADDR, posedge RCLKN &&& RE && RCLKE, 300);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L370
$setup(RCLKE, posedge RCLKN, 393);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L371
$setup(RE, posedge RCLKN, 145);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L372-L382
$setup(WADDR, posedge WCLKN &&& WE && WCLKE, 331);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L383
$setup(WCLKE, posedge WCLKN, 393);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L384-L399
$setup(WDATA, posedge WCLKN &&& WE && WCLKE, 238);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L400
$setup(WE, posedge WCLKN, 196);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
(posedge RCLKN => (RDATA : 16'bx)) = 3163;
endspecify
`endif
`ifdef ICE40_U
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12968-12983
$setup(MASK, posedge WCLKN &&& WE && WCLKE, 517);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12984-12994
$setup(RADDR, posedge RCLKN &&& RE && RCLKE, 384);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12995
$setup(RCLKE, posedge RCLKN, 503);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12996
$setup(RE, posedge RCLKN, 185);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12997-13007
$setup(WADDR, posedge WCLKN &&& WE && WCLKE, 424);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13008
$setup(WCLKE, posedge WCLKN, 503);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13009-13024
$setup(WDATA, posedge WCLKN &&& WE && WCLKE, 305);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13025
$setup(WE, posedge WCLKN, 252);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
(posedge RCLKN => (RDATA : 16'bx)) = 1179;
endspecify
`endif
endmodule
// Packed IceStorm Logic Cells
module ICESTORM_LC (
input I0, I1, I2, I3, CIN, CLK, CEN, SR,
output LO,
output O,
output COUT
);
parameter [15:0] LUT_INIT = 0;
parameter [0:0] NEG_CLK = 0;
parameter [0:0] CARRY_ENABLE = 0;
parameter [0:0] DFF_ENABLE = 0;
parameter [0:0] SET_NORESET = 0;
parameter [0:0] ASYNC_SR = 0;
parameter [0:0] CIN_CONST = 0;
parameter [0:0] CIN_SET = 0;
wire I0_pd = (I0 === 1'bz) ? 1'b0 : I0;
wire I1_pd = (I1 === 1'bz) ? 1'b0 : I1;
wire I2_pd = (I2 === 1'bz) ? 1'b0 : I2;
wire I3_pd = (I3 === 1'bz) ? 1'b0 : I3;
wire SR_pd = (SR === 1'bz) ? 1'b0 : SR;
wire CEN_pu = (CEN === 1'bz) ? 1'b1 : CEN;
wire mux_cin = CIN_CONST ? CIN_SET : CIN;
assign COUT = CARRY_ENABLE ? (I1_pd && I2_pd) || ((I1_pd || I2_pd) && mux_cin) : 1'bx;
wire [7:0] lut_s3 = I3_pd ? LUT_INIT[15:8] : LUT_INIT[7:0];
wire [3:0] lut_s2 = I2_pd ? lut_s3[ 7:4] : lut_s3[3:0];
wire [1:0] lut_s1 = I1_pd ? lut_s2[ 3:2] : lut_s2[1:0];
wire lut_o = I0_pd ? lut_s1[ 1] : lut_s1[ 0];
assign LO = lut_o;
wire polarized_clk;
assign polarized_clk = CLK ^ NEG_CLK;
reg o_reg = 1'b0;
always @(posedge polarized_clk)
if (CEN_pu)
o_reg <= SR_pd ? SET_NORESET : lut_o;
reg o_reg_async = 1'b0;
always @(posedge polarized_clk, posedge SR_pd)
if (SR_pd)
o_reg_async <= SET_NORESET;
else if (CEN_pu)
o_reg_async <= lut_o;
assign O = DFF_ENABLE ? ASYNC_SR ? o_reg_async : o_reg : lut_o;
`ifdef TIMING
specify
(I0 => O) = (0:0:0, 0:0:0);
(I1 => O) = (0:0:0, 0:0:0);
(I2 => O) = (0:0:0, 0:0:0);
(I3 => O) = (0:0:0, 0:0:0);
(I0 => LO) = (0:0:0, 0:0:0);
(I1 => LO) = (0:0:0, 0:0:0);
(I2 => LO) = (0:0:0, 0:0:0);
(I3 => LO) = (0:0:0, 0:0:0);
(I1 => COUT) = (0:0:0, 0:0:0);
(I2 => COUT) = (0:0:0, 0:0:0);
(CIN => COUT) = (0:0:0, 0:0:0);
(CLK => O) = (0:0:0, 0:0:0);
(SR => O) = (0:0:0, 0:0:0);
$setuphold(posedge CLK, posedge I0, 0:0:0, 0:0:0);
$setuphold(posedge CLK, negedge I0, 0:0:0, 0:0:0);
$setuphold(negedge CLK, posedge I0, 0:0:0, 0:0:0);
$setuphold(negedge CLK, negedge I0, 0:0:0, 0:0:0);
$setuphold(posedge CLK, posedge I1, 0:0:0, 0:0:0);
$setuphold(posedge CLK, negedge I1, 0:0:0, 0:0:0);
$setuphold(negedge CLK, posedge I1, 0:0:0, 0:0:0);
$setuphold(negedge CLK, negedge I1, 0:0:0, 0:0:0);
$setuphold(posedge CLK, posedge I2, 0:0:0, 0:0:0);
$setuphold(posedge CLK, negedge I2, 0:0:0, 0:0:0);
$setuphold(negedge CLK, posedge I2, 0:0:0, 0:0:0);
$setuphold(negedge CLK, negedge I2, 0:0:0, 0:0:0);
$setuphold(posedge CLK, posedge I3, 0:0:0, 0:0:0);
$setuphold(posedge CLK, negedge I3, 0:0:0, 0:0:0);
$setuphold(negedge CLK, posedge I3, 0:0:0, 0:0:0);
$setuphold(negedge CLK, negedge I3, 0:0:0, 0:0:0);
$setuphold(posedge CLK, posedge CEN, 0:0:0, 0:0:0);
$setuphold(posedge CLK, negedge CEN, 0:0:0, 0:0:0);
$setuphold(negedge CLK, posedge CEN, 0:0:0, 0:0:0);
$setuphold(negedge CLK, negedge CEN, 0:0:0, 0:0:0);
$setuphold(posedge CLK, posedge SR, 0:0:0, 0:0:0);
$setuphold(posedge CLK, negedge SR, 0:0:0, 0:0:0);
$setuphold(negedge CLK, posedge SR, 0:0:0, 0:0:0);
$setuphold(negedge CLK, negedge SR, 0:0:0, 0:0:0);
endspecify
`endif
`ifdef ICE40_HX
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L79
(CIN => COUT) = (101:112:126, 85:94:105);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
(I0 => O) = (361:399:449, 310:343:386);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L81
(I0 => LO) = (293:324:365, 310:343:386);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L82
(I1 => COUT) = (209:231:259, 197:218:245);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L83
(I1 => O) = (321:355:400, 304:337:379);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L84
(I1 => LO) = (259:287:323, 304:337:379);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L85
(I2 => COUT) = (186:206:231, 107:118:133);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L86
(I2 => O) = (304:337:379, 282:312:351);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L87
(I2 => LO) = (254:281:316, 231:256:288);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L88
(I3 => O) = (254:281:316, 231:256:288);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L89
(I3 => LO) = (214:237:267, 220:243:274);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
(posedge CLK => (O : 1'bx)) = (434:480:540, 434:480:540);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L91-L92
(SR => O) = (482:535:599, 482:533:599);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
$setuphold(posedge CLK, posedge I0, 378:418:470, 0:0:0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L68
$setuphold(posedge CLK, negedge I0, 321:355:400, 0:0:0);
$setuphold(negedge CLK, posedge I0, 378:418:470, 0:0:0);
$setuphold(negedge CLK, negedge I0, 321:355:400, 0:0:0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L75
$setuphold(posedge CLK, posedge I1, 321:355:400, 0:0:0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L69
$setuphold(posedge CLK, negedge I1, 304:337:379, 0:0:0);
$setuphold(negedge CLK, posedge I1, 321:355:400, 0:0:0);
$setuphold(negedge CLK, negedge I1, 304:337:379, 0:0:0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L76
$setuphold(posedge CLK, posedge I2, 299:330:372, 0:0:0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L70
$setuphold(posedge CLK, negedge I2, 259:287:323, 0:0:0);
$setuphold(negedge CLK, posedge I2, 299:330:372, 0:0:0);
$setuphold(negedge CLK, negedge I2, 259:287:323, 0:0:0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L77
$setuphold(posedge CLK, posedge I3, 220:243:274, 0:0:0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L71
$setuphold(posedge CLK, negedge I3, 175:183:217, 0:0:0);
$setuphold(negedge CLK, posedge I3, 220:243:274, 0:0:0);
$setuphold(negedge CLK, negedge I3, 175:183:217, 0:0:0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
$setuphold(posedge CLK, negedge CEN, 0:0:0, 0:0:0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L67
$setuphold(posedge CLK, posedge CEN, 0:0:0, 0:0:0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L78
$setuphold(posedge CLK, posedge SR, 163:181:203, 0:0:0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L72
$setuphold(posedge CLK, negedge SR, 113:125:140, 0:0:0);
$setuphold(negedge CLK, posedge SR, 163:181:203, 0:0:0);
$setuphold(negedge CLK, negedge SR, 113:125:140, 0:0:0);
endspecify
`endif
`ifdef ICE40_LP
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L79
(CIN => COUT) = (118:153:186, 98:128:155);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
(I0 => O) = (419:545:662, 360:468:569);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L81
(I0 => LO) = (340:442:538, 360:468:569);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L82
(I1 => COUT) = (242:315:382, 229:298:362);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L83
(I1 => O) = (372:485:589, 353:459:558);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L84
(I1 => LO) = (301:391:475, 353:459:558);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L85
(I2 => COUT) = (216:281:341, 124:162:196);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
(I2 => O) = (353:459:558, 327:425:517);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L87
(I2 => LO) = (288:374:455, 321:417:507);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L88
(I3 => O) = (294:383:465, 268:349:424);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L89
(I3 => LO) = (249:323:393, 255:332:403);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
(posedge CLK => (O : 1'bx)) = (504:655:796, 504:655:796);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L91-L92
(SR => O) = (559:726:883, 559:726:883);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
$setuphold(posedge CLK, posedge I0, 438:570:693, 0:0:0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L68
$setuphold(posedge CLK, negedge I0, 373:485:589, 0:0:0);
$setuphold(negedge CLK, posedge I0, 438:570:693, 0:0:0);
$setuphold(negedge CLK, negedge I0, 373:485:589, 0:0:0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L75
$setuphold(posedge CLK, posedge I1, 373:485:589, 0:0:0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L69
$setuphold(posedge CLK, negedge I1, 353:459:558, 0:0:0);
$setuphold(negedge CLK, posedge I1, 373:485:589, 0:0:0);
$setuphold(negedge CLK, negedge I1, 353:459:558, 0:0:0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L76
$setuphold(posedge CLK, posedge I2, 347:451:548, 0:0:0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L70
$setuphold(posedge CLK, negedge I2, 301:391:475, 0:0:0);
$setuphold(negedge CLK, posedge I2, 347:451:548, 0:0:0);
$setuphold(negedge CLK, negedge I2, 301:391:475, 0:0:0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L77
$setuphold(posedge CLK, posedge I3, 255:332:403, 0:0:0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L71
$setuphold(posedge CLK, negedge I3, 203:264:320, 0:0:0);
$setuphold(negedge CLK, posedge I3, 255:332:403, 0:0:0);
$setuphold(negedge CLK, negedge I3, 203:264:320, 0:0:0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L73
$setuphold(posedge CLK, negedge CEN, 0:0:0, 0:0:0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L67
$setuphold(posedge CLK, posedge CEN, 0:0:0, 0:0:0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L78
$setuphold(posedge CLK, posedge SR, 190:247:300, 0:0:0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L72
$setuphold(posedge CLK, negedge SR, 131:170:207, 0:0:0);
$setuphold(negedge CLK, posedge SR, 190:247:300, 0:0:0);
$setuphold(negedge CLK, negedge SR, 131:170:207, 0:0:0);
endspecify
`endif
`ifdef ICE40_U
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L91
(CIN => COUT) = (103:181:278, 103:181:278);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L92
(I0 => O) = (462:808:1255, 477:834:1285);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L93
(I0 => LO) = (315:550:848, 334:585:901);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L94
(I1 => COUT) = (251:438:675, 246:430:662);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L95
(I1 => O) = (438:765:1179, 457:799:1232);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L96
(I1 => LO) = (275:481:742, 329:576:887);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L97
(I2 => COUT) = (226:395:609, 133:232:358);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L98
(I2 => O) = (438:765:1179, 447:782:1205);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L99
(I2 => LO) = (261:456:702, 290:507:781);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L100
(I3 => O) = (320:559:861, 226:370:874);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L101
(I3 => LO) = (216:378:583, 226:395:609);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
(posedge CLK => (O : 1'bx)) = (516:903:1391, 516:903:1391);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L103-104
(SR => O) = (420:734:1131, 590:1032:1589);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L86
$setuphold(posedge CLK, posedge I0, 457:799:1232, 0:0:0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L80
$setuphold(posedge CLK, negedge I0, 393:688:1060, 0:0:0);
$setuphold(negedge CLK, posedge I0, 457:799:1232, 0:0:0);
$setuphold(negedge CLK, negedge I0, 393:688:1060, 0:0:0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L87
$setuphold(posedge CLK, posedge I1, 393:688:1060, 0:0:0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L81
$setuphold(posedge CLK, negedge I1, 373:653:1007, 0:0:0);
$setuphold(negedge CLK, posedge I1, 393:688:1060, 0:0:0);
$setuphold(negedge CLK, negedge I1, 373:653:1007, 0:0:0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L88
$setuphold(posedge CLK, posedge I2, 364:636:980, 0:0:0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L82
$setuphold(posedge CLK, negedge I2, 320:559:861, 0:0:0);
$setuphold(negedge CLK, posedge I2, 364:636:980, 0:0:0);
$setuphold(negedge CLK, negedge I2, 320:559:861, 0:0:0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L89
$setuphold(posedge CLK, posedge I3, 279:473:728, 0:0:0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L83
$setuphold(posedge CLK, negedge I3, 216:378:583, 0:0:0);
$setuphold(negedge CLK, posedge I3, 279:473:728, 0:0:0);
$setuphold(negedge CLK, negedge I3, 216:378:583, 0:0:0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L85
$setuphold(posedge CLK, negedge CEN, 0:0:0, 0:0:0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L79
$setuphold(posedge CLK, posedge CEN, 0:0:0, 0:0:0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L90
$setuphold(posedge CLK, posedge SR, 197:344:530, 0:0:0);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L84
$setuphold(posedge CLK, negedge SR, 143:249:384, 0:0:0);
$setuphold(negedge CLK, posedge SR, 197:344:530, 0:0:0);
$setuphold(negedge CLK, negedge SR, 131:170:207, 0:0:0);
endspecify
`endif
endmodule
// SiliconBlue PLL Cells
(* blackbox *)
module SB_PLL40_CORE (
input REFERENCECLK,
output PLLOUTCORE,
output PLLOUTGLOBAL,
input EXTFEEDBACK,
input [7:0] DYNAMICDELAY,
output LOCK,
input BYPASS,
input RESETB,
input LATCHINPUTVALUE,
output SDO,
input SDI,
input SCLK
);
parameter FEEDBACK_PATH = "SIMPLE";
parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
parameter SHIFTREG_DIV_MODE = 1'b0;
parameter FDA_FEEDBACK = 4'b0000;
parameter FDA_RELATIVE = 4'b0000;
parameter PLLOUT_SELECT = "GENCLK";
parameter DIVR = 4'b0000;
parameter DIVF = 7'b0000000;
parameter DIVQ = 3'b000;
parameter FILTER_RANGE = 3'b000;
parameter ENABLE_ICEGATE = 1'b0;
parameter TEST_MODE = 1'b0;
parameter EXTERNAL_DIVIDE_FACTOR = 1;
endmodule
(* blackbox *)
module SB_PLL40_PAD (
input PACKAGEPIN,
output PLLOUTCORE,
output PLLOUTGLOBAL,
input EXTFEEDBACK,
input [7:0] DYNAMICDELAY,
output LOCK,
input BYPASS,
input RESETB,
input LATCHINPUTVALUE,
output SDO,
input SDI,
input SCLK
);
parameter FEEDBACK_PATH = "SIMPLE";
parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
parameter SHIFTREG_DIV_MODE = 1'b0;
parameter FDA_FEEDBACK = 4'b0000;
parameter FDA_RELATIVE = 4'b0000;
parameter PLLOUT_SELECT = "GENCLK";
parameter DIVR = 4'b0000;
parameter DIVF = 7'b0000000;
parameter DIVQ = 3'b000;
parameter FILTER_RANGE = 3'b000;
parameter ENABLE_ICEGATE = 1'b0;
parameter TEST_MODE = 1'b0;
parameter EXTERNAL_DIVIDE_FACTOR = 1;
endmodule
(* blackbox *)
module SB_PLL40_2_PAD (
input PACKAGEPIN,
output PLLOUTCOREA,
output PLLOUTGLOBALA,
output PLLOUTCOREB,
output PLLOUTGLOBALB,
input EXTFEEDBACK,
input [7:0] DYNAMICDELAY,
output LOCK,
input BYPASS,
input RESETB,
input LATCHINPUTVALUE,
output SDO,
input SDI,
input SCLK
);
parameter FEEDBACK_PATH = "SIMPLE";
parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
parameter SHIFTREG_DIV_MODE = 1'b0;
parameter FDA_FEEDBACK = 4'b0000;
parameter FDA_RELATIVE = 4'b0000;
parameter PLLOUT_SELECT_PORTB = "GENCLK";
parameter DIVR = 4'b0000;
parameter DIVF = 7'b0000000;
parameter DIVQ = 3'b000;
parameter FILTER_RANGE = 3'b000;
parameter ENABLE_ICEGATE_PORTA = 1'b0;
parameter ENABLE_ICEGATE_PORTB = 1'b0;
parameter TEST_MODE = 1'b0;
parameter EXTERNAL_DIVIDE_FACTOR = 1;
endmodule
(* blackbox *)
module SB_PLL40_2F_CORE (
input REFERENCECLK,
output PLLOUTCOREA,
output PLLOUTGLOBALA,
output PLLOUTCOREB,
output PLLOUTGLOBALB,
input EXTFEEDBACK,
input [7:0] DYNAMICDELAY,
output LOCK,
input BYPASS,
input RESETB,
input LATCHINPUTVALUE,
output SDO,
input SDI,
input SCLK
);
parameter FEEDBACK_PATH = "SIMPLE";
parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
parameter SHIFTREG_DIV_MODE = 1'b0;
parameter FDA_FEEDBACK = 4'b0000;
parameter FDA_RELATIVE = 4'b0000;
parameter PLLOUT_SELECT_PORTA = "GENCLK";
parameter PLLOUT_SELECT_PORTB = "GENCLK";
parameter DIVR = 4'b0000;
parameter DIVF = 7'b0000000;
parameter DIVQ = 3'b000;
parameter FILTER_RANGE = 3'b000;
parameter ENABLE_ICEGATE_PORTA = 1'b0;
parameter ENABLE_ICEGATE_PORTB = 1'b0;
parameter TEST_MODE = 1'b0;
parameter EXTERNAL_DIVIDE_FACTOR = 1;
endmodule
(* blackbox *)
module SB_PLL40_2F_PAD (
input PACKAGEPIN,
output PLLOUTCOREA,
output PLLOUTGLOBALA,
output PLLOUTCOREB,
output PLLOUTGLOBALB,
input EXTFEEDBACK,
input [7:0] DYNAMICDELAY,
output LOCK,
input BYPASS,
input RESETB,
input LATCHINPUTVALUE,
output SDO,
input SDI,
input SCLK
);
parameter FEEDBACK_PATH = "SIMPLE";
parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
parameter SHIFTREG_DIV_MODE = 2'b00;
parameter FDA_FEEDBACK = 4'b0000;
parameter FDA_RELATIVE = 4'b0000;
parameter PLLOUT_SELECT_PORTA = "GENCLK";
parameter PLLOUT_SELECT_PORTB = "GENCLK";
parameter DIVR = 4'b0000;
parameter DIVF = 7'b0000000;
parameter DIVQ = 3'b000;
parameter FILTER_RANGE = 3'b000;
parameter ENABLE_ICEGATE_PORTA = 1'b0;
parameter ENABLE_ICEGATE_PORTB = 1'b0;
parameter TEST_MODE = 1'b0;
parameter EXTERNAL_DIVIDE_FACTOR = 1;
endmodule
// SiliconBlue Device Configuration Cells
(* blackbox, keep *)
module SB_WARMBOOT (
input BOOT,
input S1,
input S0
);
endmodule
module SB_SPRAM256KA (
input [13:0] ADDRESS,
input [15:0] DATAIN,
input [3:0] MASKWREN,
input WREN, CHIPSELECT, CLOCK, STANDBY, SLEEP, POWEROFF,
output reg [15:0] DATAOUT
);
`ifndef BLACKBOX
`ifndef EQUIV
reg [15:0] mem [0:16383];
wire off = SLEEP || !POWEROFF;
integer i;
always @(negedge POWEROFF) begin
for (i = 0; i <= 16383; i = i+1)
mem[i] = 16'bx;
end
always @(posedge CLOCK, posedge off) begin
if (off) begin
DATAOUT <= 0;
end else
if (STANDBY) begin
DATAOUT <= 16'bx;
end else
if (CHIPSELECT) begin
if (!WREN) begin
DATAOUT <= mem[ADDRESS];
end else begin
if (MASKWREN[0]) mem[ADDRESS][ 3: 0] <= DATAIN[ 3: 0];
if (MASKWREN[1]) mem[ADDRESS][ 7: 4] <= DATAIN[ 7: 4];
if (MASKWREN[2]) mem[ADDRESS][11: 8] <= DATAIN[11: 8];
if (MASKWREN[3]) mem[ADDRESS][15:12] <= DATAIN[15:12];
DATAOUT <= 16'bx;
end
end
end
`endif
`endif
`ifdef ICE40_U
specify
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13169-L13182
$setup(posedge ADDRESS, posedge CLOCK, 268);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13183
$setup(CHIPSELECT, posedge CLOCK, 404);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13184-L13199
$setup(DATAIN, posedge CLOCK, 143);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13200-L13203
$setup(MASKWREN, posedge CLOCK, 143);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13167
//$setup(negedge SLEEP, posedge CLOCK, 41505);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13167
//$setup(negedge STANDBY, posedge CLOCK, 1715);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13206
$setup(WREN, posedge CLOCK, 289);
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13207-L13222
(posedge CLOCK => (DATAOUT : 16'bx)) = 1821;
// https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13223-L13238
(posedge SLEEP => (DATAOUT : 16'b0)) = 1099;
endspecify
`endif
endmodule
(* blackbox *)
module SB_HFOSC(
input TRIM0,
input TRIM1,
input TRIM2,
input TRIM3,
input TRIM4,
input TRIM5,
input TRIM6,
input TRIM7,
input TRIM8,
input TRIM9,
input CLKHFPU,
input CLKHFEN,
output CLKHF
);
parameter TRIM_EN = "0b0";
parameter CLKHF_DIV = "0b00";
endmodule
(* blackbox *)
module SB_LFOSC(
input CLKLFPU,
input CLKLFEN,
output CLKLF
);
endmodule
(* blackbox *)
module SB_RGBA_DRV(
input CURREN,
input RGBLEDEN,
input RGB0PWM,
input RGB1PWM,
input RGB2PWM,
output RGB0,
output RGB1,
output RGB2
);
parameter CURRENT_MODE = "0b0";
parameter RGB0_CURRENT = "0b000000";
parameter RGB1_CURRENT = "0b000000";
parameter RGB2_CURRENT = "0b000000";
endmodule
(* blackbox *)
module SB_LED_DRV_CUR(
input EN,
output LEDPU
);
endmodule
(* blackbox *)
module SB_RGB_DRV(
input RGBLEDEN,
input RGB0PWM,
input RGB1PWM,
input RGB2PWM,
input RGBPU,
output RGB0,
output RGB1,
output RGB2
);
parameter CURRENT_MODE = "0b0";
parameter RGB0_CURRENT = "0b000000";
parameter RGB1_CURRENT = "0b000000";
parameter RGB2_CURRENT = "0b000000";
endmodule
(* blackbox *)
module SB_I2C(
input SBCLKI,
input SBRWI,
input SBSTBI,
input SBADRI7,
input SBADRI6,
input SBADRI5,
input SBADRI4,
input SBADRI3,
input SBADRI2,
input SBADRI1,
input SBADRI0,
input SBDATI7,
input SBDATI6,
input SBDATI5,
input SBDATI4,
input SBDATI3,
input SBDATI2,
input SBDATI1,
input SBDATI0,
input SCLI,
input SDAI,
output SBDATO7,
output SBDATO6,
output SBDATO5,
output SBDATO4,
output SBDATO3,
output SBDATO2,
output SBDATO1,
output SBDATO0,
output SBACKO,
output I2CIRQ,
output I2CWKUP,
output SCLO, //inout in the SB verilog library, but output in the VHDL and PDF libs and seemingly in the HW itself
output SCLOE,
output SDAO,
output SDAOE
);
parameter I2C_SLAVE_INIT_ADDR = "0b1111100001";
parameter BUS_ADDR74 = "0b0001";
endmodule
(* blackbox *)
module SB_SPI (
input SBCLKI,
input SBRWI,
input SBSTBI,
input SBADRI7,
input SBADRI6,
input SBADRI5,
input SBADRI4,
input SBADRI3,
input SBADRI2,
input SBADRI1,
input SBADRI0,
input SBDATI7,
input SBDATI6,
input SBDATI5,
input SBDATI4,
input SBDATI3,
input SBDATI2,
input SBDATI1,
input SBDATI0,
input MI,
input SI,
input SCKI,
input SCSNI,
output SBDATO7,
output SBDATO6,
output SBDATO5,
output SBDATO4,
output SBDATO3,
output SBDATO2,
output SBDATO1,
output SBDATO0,
output SBACKO,
output SPIIRQ,
output SPIWKUP,
output SO,
output SOE,
output MO,
output MOE,
output SCKO, //inout in the SB verilog library, but output in the VHDL and PDF libs and seemingly in the HW itself
output SCKOE,
output MCSNO3,
output MCSNO2,
output MCSNO1,
output MCSNO0,
output MCSNOE3,
output MCSNOE2,
output MCSNOE1,
output MCSNOE0
);
parameter BUS_ADDR74 = "0b0000";
endmodule
(* blackbox *)
module SB_LEDDA_IP(
input LEDDCS,
input LEDDCLK,
input LEDDDAT7,
input LEDDDAT6,
input LEDDDAT5,
input LEDDDAT4,
input LEDDDAT3,
input LEDDDAT2,
input LEDDDAT1,
input LEDDDAT0,
input LEDDADDR3,
input LEDDADDR2,
input LEDDADDR1,
input LEDDADDR0,
input LEDDDEN,
input LEDDEXE,
input LEDDRST,
output PWMOUT0,
output PWMOUT1,
output PWMOUT2,
output LEDDON
);
endmodule
(* blackbox *)
module SB_FILTER_50NS(
input FILTERIN,
output FILTEROUT
);
endmodule
module SB_IO_I3C (
inout PACKAGE_PIN,
input LATCH_INPUT_VALUE,
input CLOCK_ENABLE,
input INPUT_CLK,
input OUTPUT_CLK,
input OUTPUT_ENABLE,
input D_OUT_0,
input D_OUT_1,
output D_IN_0,
output D_IN_1,
input PU_ENB,
input WEAK_PU_ENB
);
parameter [5:0] PIN_TYPE = 6'b000000;
parameter [0:0] PULLUP = 1'b0;
parameter [0:0] WEAK_PULLUP = 1'b0;
parameter [0:0] NEG_TRIGGER = 1'b0;
parameter IO_STANDARD = "SB_LVCMOS";
`ifndef BLACKBOX
reg dout, din_0, din_1;
reg din_q_0, din_q_1;
reg dout_q_0, dout_q_1;
reg outena_q;
generate if (!NEG_TRIGGER) begin
always @(posedge INPUT_CLK) if (CLOCK_ENABLE) din_q_0 <= PACKAGE_PIN;
always @(negedge INPUT_CLK) if (CLOCK_ENABLE) din_q_1 <= PACKAGE_PIN;
always @(posedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_0 <= D_OUT_0;
always @(negedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_1 <= D_OUT_1;
always @(posedge OUTPUT_CLK) if (CLOCK_ENABLE) outena_q <= OUTPUT_ENABLE;
end else begin
always @(negedge INPUT_CLK) if (CLOCK_ENABLE) din_q_0 <= PACKAGE_PIN;
always @(posedge INPUT_CLK) if (CLOCK_ENABLE) din_q_1 <= PACKAGE_PIN;
always @(negedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_0 <= D_OUT_0;
always @(posedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_1 <= D_OUT_1;
always @(negedge OUTPUT_CLK) if (CLOCK_ENABLE) outena_q <= OUTPUT_ENABLE;
end endgenerate
always @* begin
if (!PIN_TYPE[1] || !LATCH_INPUT_VALUE)
din_0 = PIN_TYPE[0] ? PACKAGE_PIN : din_q_0;
din_1 = din_q_1;
end
// work around simulation glitches on dout in DDR mode
reg outclk_delayed_1;
reg outclk_delayed_2;
always @* outclk_delayed_1 <= OUTPUT_CLK;
always @* outclk_delayed_2 <= outclk_delayed_1;
always @* begin
if (PIN_TYPE[3])
dout = PIN_TYPE[2] ? !dout_q_0 : D_OUT_0;
else
dout = (outclk_delayed_2 ^ NEG_TRIGGER) || PIN_TYPE[2] ? dout_q_0 : dout_q_1;
end
assign D_IN_0 = din_0, D_IN_1 = din_1;
generate
if (PIN_TYPE[5:4] == 2'b01) assign PACKAGE_PIN = dout;
if (PIN_TYPE[5:4] == 2'b10) assign PACKAGE_PIN = OUTPUT_ENABLE ? dout : 1'bz;
if (PIN_TYPE[5:4] == 2'b11) assign PACKAGE_PIN = outena_q ? dout : 1'bz;
endgenerate
`endif
endmodule
module SB_IO_OD (
inout PACKAGEPIN,
input LATCHINPUTVALUE,
input CLOCKENABLE,
input INPUTCLK,
input OUTPUTCLK,
input OUTPUTENABLE,
input DOUT1,
input DOUT0,
output DIN1,
output DIN0
);
parameter [5:0] PIN_TYPE = 6'b000000;
parameter [0:0] NEG_TRIGGER = 1'b0;
`ifndef BLACKBOX
reg dout, din_0, din_1;
reg din_q_0, din_q_1;
reg dout_q_0, dout_q_1;
reg outena_q;
generate if (!NEG_TRIGGER) begin
always @(posedge INPUTCLK) if (CLOCKENABLE) din_q_0 <= PACKAGEPIN;
always @(negedge INPUTCLK) if (CLOCKENABLE) din_q_1 <= PACKAGEPIN;
always @(posedge OUTPUTCLK) if (CLOCKENABLE) dout_q_0 <= DOUT0;
always @(negedge OUTPUTCLK) if (CLOCKENABLE) dout_q_1 <= DOUT1;
always @(posedge OUTPUTCLK) if (CLOCKENABLE) outena_q <= OUTPUTENABLE;
end else begin
always @(negedge INPUTCLK) if (CLOCKENABLE) din_q_0 <= PACKAGEPIN;
always @(posedge INPUTCLK) if (CLOCKENABLE) din_q_1 <= PACKAGEPIN;
always @(negedge OUTPUTCLK) if (CLOCKENABLE) dout_q_0 <= DOUT0;
always @(posedge OUTPUTCLK) if (CLOCKENABLE) dout_q_1 <= DOUT1;
always @(negedge OUTPUTCLK) if (CLOCKENABLE) outena_q <= OUTPUTENABLE;
end endgenerate
always @* begin
if (!PIN_TYPE[1] || !LATCHINPUTVALUE)
din_0 = PIN_TYPE[0] ? PACKAGEPIN : din_q_0;
din_1 = din_q_1;
end
// work around simulation glitches on dout in DDR mode
reg outclk_delayed_1;
reg outclk_delayed_2;
always @* outclk_delayed_1 <= OUTPUTCLK;
always @* outclk_delayed_2 <= outclk_delayed_1;
always @* begin
if (PIN_TYPE[3])
dout = PIN_TYPE[2] ? !dout_q_0 : DOUT0;
else
dout = (outclk_delayed_2 ^ NEG_TRIGGER) || PIN_TYPE[2] ? dout_q_0 : dout_q_1;
end
assign DIN0 = din_0, DIN1 = din_1;
generate
if (PIN_TYPE[5:4] == 2'b01) assign PACKAGEPIN = dout ? 1'bz : 1'b0;
if (PIN_TYPE[5:4] == 2'b10) assign PACKAGEPIN = OUTPUTENABLE ? (dout ? 1'bz : 1'b0) : 1'bz;
if (PIN_TYPE[5:4] == 2'b11) assign PACKAGEPIN = outena_q ? (dout ? 1'bz : 1'b0) : 1'bz;
endgenerate
`endif
endmodule
//(* abc9_box, lib_whitebox *) // TODO
module SB_MAC16 (
input CLK, CE,
input [15:0] C, A, B, D,
input AHOLD, BHOLD, CHOLD, DHOLD,
input IRSTTOP, IRSTBOT,
input ORSTTOP, ORSTBOT,
input OLOADTOP, OLOADBOT,
input ADDSUBTOP, ADDSUBBOT,
input OHOLDTOP, OHOLDBOT,
input CI, ACCUMCI, SIGNEXTIN,
output [31:0] O,
output CO, ACCUMCO, SIGNEXTOUT
);
parameter [0:0] NEG_TRIGGER = 0;
parameter [0:0] C_REG = 0;
parameter [0:0] A_REG = 0;
parameter [0:0] B_REG = 0;
parameter [0:0] D_REG = 0;
parameter [0:0] TOP_8x8_MULT_REG = 0;
parameter [0:0] BOT_8x8_MULT_REG = 0;
parameter [0:0] PIPELINE_16x16_MULT_REG1 = 0;
parameter [0:0] PIPELINE_16x16_MULT_REG2 = 0;
parameter [1:0] TOPOUTPUT_SELECT = 0;
parameter [1:0] TOPADDSUB_LOWERINPUT = 0;
parameter [0:0] TOPADDSUB_UPPERINPUT = 0;
parameter [1:0] TOPADDSUB_CARRYSELECT = 0;
parameter [1:0] BOTOUTPUT_SELECT = 0;
parameter [1:0] BOTADDSUB_LOWERINPUT = 0;
parameter [0:0] BOTADDSUB_UPPERINPUT = 0;
parameter [1:0] BOTADDSUB_CARRYSELECT = 0;
parameter [0:0] MODE_8x8 = 0;
parameter [0:0] A_SIGNED = 0;
parameter [0:0] B_SIGNED = 0;
wire clock = CLK ^ NEG_TRIGGER;
// internal wires, compare Figure on page 133 of ICE Technology Library 3.0 and Fig 2 on page 2 of Lattice TN1295-DSP
// http://www.latticesemi.com/~/media/LatticeSemi/Documents/TechnicalBriefs/SBTICETechnologyLibrary201608.pdf
// https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/AD/DSPFunctionUsageGuideforICE40Devices.ashx
wire [15:0] iA, iB, iC, iD;
wire [15:0] iF, iJ, iK, iG;
wire [31:0] iL, iH;
wire [15:0] iW, iX, iP, iQ;
wire [15:0] iY, iZ, iR, iS;
wire HCI, LCI, LCO;
// Regs C and A
reg [15:0] rC, rA;
always @(posedge clock, posedge IRSTTOP) begin
if (IRSTTOP) begin
rC <= 0;
rA <= 0;
end else if (CE) begin
if (!CHOLD) rC <= C;
if (!AHOLD) rA <= A;
end
end
assign iC = C_REG ? rC : C;
assign iA = A_REG ? rA : A;
// Regs B and D
reg [15:0] rB, rD;
always @(posedge clock, posedge IRSTBOT) begin
if (IRSTBOT) begin
rB <= 0;
rD <= 0;
end else if (CE) begin
if (!BHOLD) rB <= B;
if (!DHOLD) rD <= D;
end
end
assign iB = B_REG ? rB : B;
assign iD = D_REG ? rD : D;
// Multiplier Stage
wire [15:0] p_Ah_Bh, p_Al_Bh, p_Ah_Bl, p_Al_Bl;
wire [15:0] Ah, Al, Bh, Bl;
assign Ah = {A_SIGNED ? {8{iA[15]}} : 8'b0, iA[15: 8]};
assign Al = {A_SIGNED && MODE_8x8 ? {8{iA[ 7]}} : 8'b0, iA[ 7: 0]};
assign Bh = {B_SIGNED ? {8{iB[15]}} : 8'b0, iB[15: 8]};
assign Bl = {B_SIGNED && MODE_8x8 ? {8{iB[ 7]}} : 8'b0, iB[ 7: 0]};
assign p_Ah_Bh = Ah * Bh; // F
assign p_Al_Bh = {8'b0, Al[7:0]} * Bh; // J
assign p_Ah_Bl = Ah * {8'b0, Bl[7:0]}; // K
assign p_Al_Bl = Al * Bl; // G
// Regs F and J
reg [15:0] rF, rJ;
always @(posedge clock, posedge IRSTTOP) begin
if (IRSTTOP) begin
rF <= 0;
rJ <= 0;
end else if (CE) begin
rF <= p_Ah_Bh;
if (!MODE_8x8) rJ <= p_Al_Bh;
end
end
assign iF = TOP_8x8_MULT_REG ? rF : p_Ah_Bh;
assign iJ = PIPELINE_16x16_MULT_REG1 ? rJ : p_Al_Bh;
// Regs K and G
reg [15:0] rK, rG;
always @(posedge clock, posedge IRSTBOT) begin
if (IRSTBOT) begin
rK <= 0;
rG <= 0;
end else if (CE) begin
if (!MODE_8x8) rK <= p_Ah_Bl;
rG <= p_Al_Bl;
end
end
assign iK = PIPELINE_16x16_MULT_REG1 ? rK : p_Ah_Bl;
assign iG = BOT_8x8_MULT_REG ? rG : p_Al_Bl;
// Adder Stage
wire [23:0] iK_e = {A_SIGNED ? {8{iK[15]}} : 8'b0, iK};
wire [23:0] iJ_e = {B_SIGNED ? {8{iJ[15]}} : 8'b0, iJ};
assign iL = iG + (iK_e << 8) + (iJ_e << 8) + (iF << 16);
// Reg H
reg [31:0] rH;
always @(posedge clock, posedge IRSTBOT) begin
if (IRSTBOT) begin
rH <= 0;
end else if (CE) begin
if (!MODE_8x8) rH <= iL;
end
end
assign iH = PIPELINE_16x16_MULT_REG2 ? rH : iL;
// Hi Output Stage
wire [15:0] XW, Oh;
reg [15:0] rQ;
assign iW = TOPADDSUB_UPPERINPUT ? iC : iQ;
assign iX = (TOPADDSUB_LOWERINPUT == 0) ? iA : (TOPADDSUB_LOWERINPUT == 1) ? iF : (TOPADDSUB_LOWERINPUT == 2) ? iH[31:16] : {16{iZ[15]}};
assign {ACCUMCO, XW} = iX + (iW ^ {16{ADDSUBTOP}}) + HCI;
assign CO = ACCUMCO ^ ADDSUBTOP;
assign iP = OLOADTOP ? iC : XW ^ {16{ADDSUBTOP}};
always @(posedge clock, posedge ORSTTOP) begin
if (ORSTTOP) begin
rQ <= 0;
end else if (CE) begin
if (!OHOLDTOP) rQ <= iP;
end
end
assign iQ = rQ;
assign Oh = (TOPOUTPUT_SELECT == 0) ? iP : (TOPOUTPUT_SELECT == 1) ? iQ : (TOPOUTPUT_SELECT == 2) ? iF : iH[31:16];
assign HCI = (TOPADDSUB_CARRYSELECT == 0) ? 1'b0 : (TOPADDSUB_CARRYSELECT == 1) ? 1'b1 : (TOPADDSUB_CARRYSELECT == 2) ? LCO : LCO ^ ADDSUBBOT;
assign SIGNEXTOUT = iX[15];
// Lo Output Stage
wire [15:0] YZ, Ol;
reg [15:0] rS;
assign iY = BOTADDSUB_UPPERINPUT ? iD : iS;
assign iZ = (BOTADDSUB_LOWERINPUT == 0) ? iB : (BOTADDSUB_LOWERINPUT == 1) ? iG : (BOTADDSUB_LOWERINPUT == 2) ? iH[15:0] : {16{SIGNEXTIN}};
assign {LCO, YZ} = iZ + (iY ^ {16{ADDSUBBOT}}) + LCI;
assign iR = OLOADBOT ? iD : YZ ^ {16{ADDSUBBOT}};
always @(posedge clock, posedge ORSTBOT) begin
if (ORSTBOT) begin
rS <= 0;
end else if (CE) begin
if (!OHOLDBOT) rS <= iR;
end
end
assign iS = rS;
assign Ol = (BOTOUTPUT_SELECT == 0) ? iR : (BOTOUTPUT_SELECT == 1) ? iS : (BOTOUTPUT_SELECT == 2) ? iG : iH[15:0];
assign LCI = (BOTADDSUB_CARRYSELECT == 0) ? 1'b0 : (BOTADDSUB_CARRYSELECT == 1) ? 1'b1 : (BOTADDSUB_CARRYSELECT == 2) ? ACCUMCI : CI;
assign O = {Oh, Ol};
endmodule
// Post-place-and-route RAM model
module ICESTORM_RAM(
output RDATA_15, RDATA_14, RDATA_13, RDATA_12, RDATA_11, RDATA_10, RDATA_9, RDATA_8, RDATA_7, RDATA_6, RDATA_5, RDATA_4, RDATA_3, RDATA_2, RDATA_1, RDATA_0,
input RCLK, RCLKE, RE,
input RADDR_10, RADDR_9, RADDR_8, RADDR_7, RADDR_6, RADDR_5, RADDR_4, RADDR_3, RADDR_2, RADDR_1, RADDR_0,
input WCLK, WCLKE, WE,
input WADDR_10, WADDR_9, WADDR_8, WADDR_7, WADDR_6, WADDR_5, WADDR_4, WADDR_3, WADDR_2, WADDR_1, WADDR_0,
input MASK_15, MASK_14, MASK_13, MASK_12, MASK_11, MASK_10, MASK_9, MASK_8, MASK_7, MASK_6, MASK_5, MASK_4, MASK_3, MASK_2, MASK_1, MASK_0,
input WDATA_15, WDATA_14, WDATA_13, WDATA_12, WDATA_11, WDATA_10, WDATA_9, WDATA_8, WDATA_7, WDATA_6, WDATA_5, WDATA_4, WDATA_3, WDATA_2, WDATA_1, WDATA_0
);
parameter WRITE_MODE = 0;
parameter READ_MODE = 0;
parameter NEG_CLK_R = 1'b0;
parameter NEG_CLK_W = 1'b0;
parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
// Pull-down and pull-up functions
function pd;
input x;
begin
pd = (x === 1'bz) ? 1'b0 : x;
end
endfunction
function pu;
input x;
begin
pu = (x === 1'bz) ? 1'b1 : x;
end
endfunction
SB_RAM40_4K #(
.WRITE_MODE(WRITE_MODE),
.READ_MODE (READ_MODE ),
.INIT_0 (INIT_0 ),
.INIT_1 (INIT_1 ),
.INIT_2 (INIT_2 ),
.INIT_3 (INIT_3 ),
.INIT_4 (INIT_4 ),
.INIT_5 (INIT_5 ),
.INIT_6 (INIT_6 ),
.INIT_7 (INIT_7 ),
.INIT_8 (INIT_8 ),
.INIT_9 (INIT_9 ),
.INIT_A (INIT_A ),
.INIT_B (INIT_B ),
.INIT_C (INIT_C ),
.INIT_D (INIT_D ),
.INIT_E (INIT_E ),
.INIT_F (INIT_F )
) RAM (
.RDATA({RDATA_15, RDATA_14, RDATA_13, RDATA_12, RDATA_11, RDATA_10, RDATA_9, RDATA_8, RDATA_7, RDATA_6, RDATA_5, RDATA_4, RDATA_3, RDATA_2, RDATA_1, RDATA_0}),
.RCLK (pd(RCLK) ^ NEG_CLK_R),
.RCLKE(pu(RCLKE)),
.RE (pd(RE)),
.RADDR({pd(RADDR_10), pd(RADDR_9), pd(RADDR_8), pd(RADDR_7), pd(RADDR_6), pd(RADDR_5), pd(RADDR_4), pd(RADDR_3), pd(RADDR_2), pd(RADDR_1), pd(RADDR_0)}),
.WCLK (pd(WCLK) ^ NEG_CLK_W),
.WCLKE(pu(WCLKE)),
.WE (pd(WE)),
.WADDR({pd(WADDR_10), pd(WADDR_9), pd(WADDR_8), pd(WADDR_7), pd(WADDR_6), pd(WADDR_5), pd(WADDR_4), pd(WADDR_3), pd(WADDR_2), pd(WADDR_1), pd(WADDR_0)}),
.MASK ({pd(MASK_15), pd(MASK_14), pd(MASK_13), pd(MASK_12), pd(MASK_11), pd(MASK_10), pd(MASK_9), pd(MASK_8),
pd(MASK_7), pd(MASK_6), pd(MASK_5), pd(MASK_4), pd(MASK_3), pd(MASK_2), pd(MASK_1), pd(MASK_0)}),
.WDATA({pd(WDATA_15), pd(WDATA_14), pd(WDATA_13), pd(WDATA_12), pd(WDATA_11), pd(WDATA_10), pd(WDATA_9), pd(WDATA_8),
pd(WDATA_7), pd(WDATA_6), pd(WDATA_5), pd(WDATA_4), pd(WDATA_3), pd(WDATA_2), pd(WDATA_1), pd(WDATA_0)})
);
`ifdef TIMING
specify
(RCLK => RDATA_15) = (0:0:0, 0:0:0);
(RCLK => RDATA_14) = (0:0:0, 0:0:0);
(RCLK => RDATA_13) = (0:0:0, 0:0:0);
(RCLK => RDATA_12) = (0:0:0, 0:0:0);
(RCLK => RDATA_11) = (0:0:0, 0:0:0);
(RCLK => RDATA_10) = (0:0:0, 0:0:0);
(RCLK => RDATA_9) = (0:0:0, 0:0:0);
(RCLK => RDATA_8) = (0:0:0, 0:0:0);
(RCLK => RDATA_7) = (0:0:0, 0:0:0);
(RCLK => RDATA_6) = (0:0:0, 0:0:0);
(RCLK => RDATA_5) = (0:0:0, 0:0:0);
(RCLK => RDATA_4) = (0:0:0, 0:0:0);
(RCLK => RDATA_3) = (0:0:0, 0:0:0);
(RCLK => RDATA_2) = (0:0:0, 0:0:0);
(RCLK => RDATA_1) = (0:0:0, 0:0:0);
(RCLK => RDATA_0) = (0:0:0, 0:0:0);
$setuphold(posedge RCLK, posedge RCLKE, 0:0:0, 0:0:0);
$setuphold(posedge RCLK, negedge RCLKE, 0:0:0, 0:0:0);
$setuphold(negedge RCLK, posedge RCLKE, 0:0:0, 0:0:0);
$setuphold(negedge RCLK, negedge RCLKE, 0:0:0, 0:0:0);
$setuphold(posedge RCLK, posedge RE, 0:0:0, 0:0:0);
$setuphold(posedge RCLK, negedge RE, 0:0:0, 0:0:0);
$setuphold(negedge RCLK, posedge RE, 0:0:0, 0:0:0);
$setuphold(negedge RCLK, negedge RE, 0:0:0, 0:0:0);
$setuphold(posedge RCLK, posedge RADDR_10, 0:0:0, 0:0:0);
$setuphold(posedge RCLK, negedge RADDR_10, 0:0:0, 0:0:0);
$setuphold(negedge RCLK, posedge RADDR_10, 0:0:0, 0:0:0);
$setuphold(negedge RCLK, negedge RADDR_10, 0:0:0, 0:0:0);
$setuphold(posedge RCLK, posedge RADDR_9, 0:0:0, 0:0:0);
$setuphold(posedge RCLK, negedge RADDR_9, 0:0:0, 0:0:0);
$setuphold(negedge RCLK, posedge RADDR_9, 0:0:0, 0:0:0);
$setuphold(negedge RCLK, negedge RADDR_9, 0:0:0, 0:0:0);
$setuphold(posedge RCLK, posedge RADDR_8, 0:0:0, 0:0:0);
$setuphold(posedge RCLK, negedge RADDR_8, 0:0:0, 0:0:0);
$setuphold(negedge RCLK, posedge RADDR_8, 0:0:0, 0:0:0);
$setuphold(negedge RCLK, negedge RADDR_8, 0:0:0, 0:0:0);
$setuphold(posedge RCLK, posedge RADDR_7, 0:0:0, 0:0:0);
$setuphold(posedge RCLK, negedge RADDR_7, 0:0:0, 0:0:0);
$setuphold(negedge RCLK, posedge RADDR_7, 0:0:0, 0:0:0);
$setuphold(negedge RCLK, negedge RADDR_7, 0:0:0, 0:0:0);
$setuphold(posedge RCLK, posedge RADDR_6, 0:0:0, 0:0:0);
$setuphold(posedge RCLK, negedge RADDR_6, 0:0:0, 0:0:0);
$setuphold(negedge RCLK, posedge RADDR_6, 0:0:0, 0:0:0);
$setuphold(negedge RCLK, negedge RADDR_6, 0:0:0, 0:0:0);
$setuphold(posedge RCLK, posedge RADDR_5, 0:0:0, 0:0:0);
$setuphold(posedge RCLK, negedge RADDR_5, 0:0:0, 0:0:0);
$setuphold(negedge RCLK, posedge RADDR_5, 0:0:0, 0:0:0);
$setuphold(negedge RCLK, negedge RADDR_5, 0:0:0, 0:0:0);
$setuphold(posedge RCLK, posedge RADDR_4, 0:0:0, 0:0:0);
$setuphold(posedge RCLK, negedge RADDR_4, 0:0:0, 0:0:0);
$setuphold(negedge RCLK, posedge RADDR_4, 0:0:0, 0:0:0);
$setuphold(negedge RCLK, negedge RADDR_4, 0:0:0, 0:0:0);
$setuphold(posedge RCLK, posedge RADDR_3, 0:0:0, 0:0:0);
$setuphold(posedge RCLK, negedge RADDR_3, 0:0:0, 0:0:0);
$setuphold(negedge RCLK, posedge RADDR_3, 0:0:0, 0:0:0);
$setuphold(negedge RCLK, negedge RADDR_3, 0:0:0, 0:0:0);
$setuphold(posedge RCLK, posedge RADDR_2, 0:0:0, 0:0:0);
$setuphold(posedge RCLK, negedge RADDR_2, 0:0:0, 0:0:0);
$setuphold(negedge RCLK, posedge RADDR_2, 0:0:0, 0:0:0);
$setuphold(negedge RCLK, negedge RADDR_2, 0:0:0, 0:0:0);
$setuphold(posedge RCLK, posedge RADDR_1, 0:0:0, 0:0:0);
$setuphold(posedge RCLK, negedge RADDR_1, 0:0:0, 0:0:0);
$setuphold(negedge RCLK, posedge RADDR_1, 0:0:0, 0:0:0);
$setuphold(negedge RCLK, negedge RADDR_1, 0:0:0, 0:0:0);
$setuphold(posedge RCLK, posedge RADDR_0, 0:0:0, 0:0:0);
$setuphold(posedge RCLK, negedge RADDR_0, 0:0:0, 0:0:0);
$setuphold(negedge RCLK, posedge RADDR_0, 0:0:0, 0:0:0);
$setuphold(negedge RCLK, negedge RADDR_0, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, posedge WCLKE, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, negedge WCLKE, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, posedge WCLKE, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, negedge WCLKE, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, posedge WE, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, negedge WE, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, posedge WE, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, negedge WE, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, posedge WADDR_10, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, negedge WADDR_10, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, posedge WADDR_10, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, negedge WADDR_10, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, posedge WADDR_9, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, negedge WADDR_9, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, posedge WADDR_9, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, negedge WADDR_9, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, posedge WADDR_8, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, negedge WADDR_8, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, posedge WADDR_8, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, negedge WADDR_8, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, posedge WADDR_7, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, negedge WADDR_7, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, posedge WADDR_7, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, negedge WADDR_7, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, posedge WADDR_6, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, negedge WADDR_6, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, posedge WADDR_6, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, negedge WADDR_6, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, posedge WADDR_5, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, negedge WADDR_5, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, posedge WADDR_5, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, negedge WADDR_5, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, posedge WADDR_4, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, negedge WADDR_4, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, posedge WADDR_4, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, negedge WADDR_4, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, posedge WADDR_3, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, negedge WADDR_3, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, posedge WADDR_3, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, negedge WADDR_3, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, posedge WADDR_2, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, negedge WADDR_2, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, posedge WADDR_2, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, negedge WADDR_2, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, posedge WADDR_1, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, negedge WADDR_1, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, posedge WADDR_1, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, negedge WADDR_1, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, posedge WADDR_0, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, negedge WADDR_0, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, posedge WADDR_0, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, negedge WADDR_0, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, posedge MASK_15, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, negedge MASK_15, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, posedge MASK_15, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, negedge MASK_15, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, posedge MASK_14, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, negedge MASK_14, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, posedge MASK_14, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, negedge MASK_14, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, posedge MASK_13, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, negedge MASK_13, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, posedge MASK_13, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, negedge MASK_13, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, posedge MASK_12, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, negedge MASK_12, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, posedge MASK_12, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, negedge MASK_12, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, posedge MASK_11, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, negedge MASK_11, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, posedge MASK_11, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, negedge MASK_11, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, posedge MASK_10, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, negedge MASK_10, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, posedge MASK_10, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, negedge MASK_10, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, posedge MASK_9, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, negedge MASK_9, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, posedge MASK_9, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, negedge MASK_9, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, posedge MASK_8, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, negedge MASK_8, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, posedge MASK_8, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, negedge MASK_8, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, posedge MASK_7, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, negedge MASK_7, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, posedge MASK_7, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, negedge MASK_7, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, posedge MASK_6, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, negedge MASK_6, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, posedge MASK_6, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, negedge MASK_6, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, posedge MASK_5, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, negedge MASK_5, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, posedge MASK_5, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, negedge MASK_5, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, posedge MASK_4, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, negedge MASK_4, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, posedge MASK_4, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, negedge MASK_4, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, posedge MASK_3, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, negedge MASK_3, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, posedge MASK_3, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, negedge MASK_3, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, posedge MASK_2, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, negedge MASK_2, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, posedge MASK_2, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, negedge MASK_2, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, posedge MASK_1, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, negedge MASK_1, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, posedge MASK_1, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, negedge MASK_1, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, posedge MASK_0, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, negedge MASK_0, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, posedge MASK_0, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, negedge MASK_0, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, posedge WDATA_15, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, negedge WDATA_15, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, posedge WDATA_15, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, negedge WDATA_15, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, posedge WDATA_14, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, negedge WDATA_14, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, posedge WDATA_14, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, negedge WDATA_14, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, posedge WDATA_13, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, negedge WDATA_13, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, posedge WDATA_13, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, negedge WDATA_13, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, posedge WDATA_12, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, negedge WDATA_12, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, posedge WDATA_12, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, negedge WDATA_12, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, posedge WDATA_11, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, negedge WDATA_11, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, posedge WDATA_11, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, negedge WDATA_11, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, posedge WDATA_10, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, negedge WDATA_10, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, posedge WDATA_10, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, negedge WDATA_10, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, posedge WDATA_9, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, negedge WDATA_9, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, posedge WDATA_9, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, negedge WDATA_9, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, posedge WDATA_8, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, negedge WDATA_8, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, posedge WDATA_8, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, negedge WDATA_8, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, posedge WDATA_7, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, negedge WDATA_7, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, posedge WDATA_7, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, negedge WDATA_7, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, posedge WDATA_6, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, negedge WDATA_6, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, posedge WDATA_6, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, negedge WDATA_6, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, posedge WDATA_5, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, negedge WDATA_5, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, posedge WDATA_5, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, negedge WDATA_5, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, posedge WDATA_4, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, negedge WDATA_4, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, posedge WDATA_4, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, negedge WDATA_4, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, posedge WDATA_3, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, negedge WDATA_3, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, posedge WDATA_3, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, negedge WDATA_3, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, posedge WDATA_2, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, negedge WDATA_2, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, posedge WDATA_2, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, negedge WDATA_2, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, posedge WDATA_1, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, negedge WDATA_1, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, posedge WDATA_1, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, negedge WDATA_1, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, posedge WDATA_0, 0:0:0, 0:0:0);
$setuphold(posedge WCLK, negedge WDATA_0, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, posedge WDATA_0, 0:0:0, 0:0:0);
$setuphold(negedge WCLK, negedge WDATA_0, 0:0:0, 0:0:0);
endspecify
`endif
endmodule
|
(* -*- coding: utf-8 -*- *)
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2016 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(** * Euclidean Division *)
(** Initial Contribution by Claude Marché and Xavier Urbain *)
Require Export ZArith_base.
Require Import Zbool Omega ZArithRing Zcomplements Setoid Morphisms.
Local Open Scope Z_scope.
(** The definition of the division is now in [BinIntDef], the initial
specifications and properties are in [BinInt]. *)
Notation Zdiv_eucl_POS := Z.pos_div_eucl (compat "8.3").
Notation Zdiv_eucl := Z.div_eucl (compat "8.3").
Notation Zdiv := Z.div (compat "8.3").
Notation Zmod := Z.modulo (compat "8.3").
Notation Zdiv_eucl_eq := Z.div_eucl_eq (compat "8.3").
Notation Z_div_mod_eq_full := Z.div_mod (compat "8.3").
Notation Zmod_POS_bound := Z.pos_div_eucl_bound (compat "8.3").
Notation Zmod_pos_bound := Z.mod_pos_bound (compat "8.3").
Notation Zmod_neg_bound := Z.mod_neg_bound (compat "8.3").
(** * Main division theorems *)
(** NB: many things are stated twice for compatibility reasons *)
Lemma Z_div_mod_POS :
forall b:Z,
b > 0 ->
forall a:positive,
let (q, r) := Z.pos_div_eucl a b in Zpos a = b * q + r /\ 0 <= r < b.
Proof.
intros b Hb a. Z.swap_greater.
generalize (Z.pos_div_eucl_eq a b Hb) (Z.pos_div_eucl_bound a b Hb).
destruct Z.pos_div_eucl. rewrite Z.mul_comm. auto.
Qed.
Theorem Z_div_mod a b :
b > 0 ->
let (q, r) := Z.div_eucl a b in a = b * q + r /\ 0 <= r < b.
Proof.
Z.swap_greater. intros Hb.
assert (Hb' : b<>0) by (now destruct b).
generalize (Z.div_eucl_eq a b Hb') (Z.mod_pos_bound a b Hb).
unfold Z.modulo. destruct Z.div_eucl. auto.
Qed.
(** For stating the fully general result, let's give a short name
to the condition on the remainder. *)
Definition Remainder r b := 0 <= r < b \/ b < r <= 0.
(** Another equivalent formulation: *)
Definition Remainder_alt r b := Z.abs r < Z.abs b /\ Z.sgn r <> - Z.sgn b.
(* In the last formulation, [ Z.sgn r <> - Z.sgn b ] is less nice than saying
[ Z.sgn r = Z.sgn b ], but at least it works even when [r] is null. *)
Lemma Remainder_equiv : forall r b, Remainder r b <-> Remainder_alt r b.
Proof.
intros; unfold Remainder, Remainder_alt; omega with *.
Qed.
Hint Unfold Remainder.
(** Now comes the fully general result about Euclidean division. *)
Theorem Z_div_mod_full a b :
b <> 0 ->
let (q, r) := Z.div_eucl a b in a = b * q + r /\ Remainder r b.
Proof.
intros Hb.
generalize (Z.div_eucl_eq a b Hb)
(Z.mod_pos_bound a b) (Z.mod_neg_bound a b).
unfold Z.modulo. destruct Z.div_eucl as (q,r).
intros EQ POS NEG.
split; auto.
red; destruct b.
now destruct Hb. left; now apply POS. right; now apply NEG.
Qed.
(** The same results as before, stated separately in terms of Z.div and Z.modulo *)
Lemma Z_mod_remainder a b : b<>0 -> Remainder (a mod b) b.
Proof.
unfold Z.modulo; intros Hb; generalize (Z_div_mod_full a b Hb); auto.
destruct Z.div_eucl; tauto.
Qed.
Lemma Z_mod_lt a b : b > 0 -> 0 <= a mod b < b.
Proof (fun Hb => Z.mod_pos_bound a b (Z.gt_lt _ _ Hb)).
Lemma Z_mod_neg a b : b < 0 -> b < a mod b <= 0.
Proof (Z.mod_neg_bound a b).
Lemma Z_div_mod_eq a b : b > 0 -> a = b*(a/b) + (a mod b).
Proof.
intros Hb; apply Z.div_mod; auto with zarith.
Qed.
Lemma Zmod_eq_full a b : b<>0 -> a mod b = a - (a/b)*b.
Proof. intros. rewrite Z.mul_comm. now apply Z.mod_eq. Qed.
Lemma Zmod_eq a b : b>0 -> a mod b = a - (a/b)*b.
Proof. intros. apply Zmod_eq_full. now destruct b. Qed.
(** Existence theorem *)
Theorem Zdiv_eucl_exist : forall (b:Z)(Hb:b>0)(a:Z),
{qr : Z * Z | let (q, r) := qr in a = b * q + r /\ 0 <= r < b}.
Proof.
intros b Hb a.
exists (Z.div_eucl a b).
exact (Z_div_mod a b Hb).
Qed.
Arguments Zdiv_eucl_exist : default implicits.
(** Uniqueness theorems *)
Theorem Zdiv_mod_unique b q1 q2 r1 r2 :
0 <= r1 < Z.abs b -> 0 <= r2 < Z.abs b ->
b*q1+r1 = b*q2+r2 -> q1=q2 /\ r1=r2.
Proof.
intros Hr1 Hr2 H. rewrite <- (Z.abs_sgn b), <- !Z.mul_assoc in H.
destruct (Z.div_mod_unique (Z.abs b) (Z.sgn b * q1) (Z.sgn b * q2) r1 r2); auto.
split; trivial.
apply Z.mul_cancel_l with (Z.sgn b); trivial.
rewrite Z.sgn_null_iff, <- Z.abs_0_iff. destruct Hr1; Z.order.
Qed.
Theorem Zdiv_mod_unique_2 :
forall b q1 q2 r1 r2:Z,
Remainder r1 b -> Remainder r2 b ->
b*q1+r1 = b*q2+r2 -> q1=q2 /\ r1=r2.
Proof Z.div_mod_unique.
Theorem Zdiv_unique_full:
forall a b q r, Remainder r b ->
a = b*q + r -> q = a/b.
Proof Z.div_unique.
Theorem Zdiv_unique:
forall a b q r, 0 <= r < b ->
a = b*q + r -> q = a/b.
Proof. intros; eapply Zdiv_unique_full; eauto. Qed.
Theorem Zmod_unique_full:
forall a b q r, Remainder r b ->
a = b*q + r -> r = a mod b.
Proof Z.mod_unique.
Theorem Zmod_unique:
forall a b q r, 0 <= r < b ->
a = b*q + r -> r = a mod b.
Proof. intros; eapply Zmod_unique_full; eauto. Qed.
(** * Basic values of divisions and modulo. *)
Lemma Zmod_0_l: forall a, 0 mod a = 0.
Proof.
destruct a; simpl; auto.
Qed.
Lemma Zmod_0_r: forall a, a mod 0 = 0.
Proof.
destruct a; simpl; auto.
Qed.
Lemma Zdiv_0_l: forall a, 0/a = 0.
Proof.
destruct a; simpl; auto.
Qed.
Lemma Zdiv_0_r: forall a, a/0 = 0.
Proof.
destruct a; simpl; auto.
Qed.
Ltac zero_or_not a :=
destruct (Z.eq_dec a 0);
[subst; rewrite ?Zmod_0_l, ?Zdiv_0_l, ?Zmod_0_r, ?Zdiv_0_r;
auto with zarith|].
Lemma Zmod_1_r: forall a, a mod 1 = 0.
Proof. intros. zero_or_not a. apply Z.mod_1_r. Qed.
Lemma Zdiv_1_r: forall a, a/1 = a.
Proof. intros. zero_or_not a. apply Z.div_1_r. Qed.
Hint Resolve Zmod_0_l Zmod_0_r Zdiv_0_l Zdiv_0_r Zdiv_1_r Zmod_1_r
: zarith.
Lemma Zdiv_1_l: forall a, 1 < a -> 1/a = 0.
Proof Z.div_1_l.
Lemma Zmod_1_l: forall a, 1 < a -> 1 mod a = 1.
Proof Z.mod_1_l.
Lemma Z_div_same_full : forall a:Z, a<>0 -> a/a = 1.
Proof Z.div_same.
Lemma Z_mod_same_full : forall a, a mod a = 0.
Proof. intros. zero_or_not a. apply Z.mod_same; auto. Qed.
Lemma Z_mod_mult : forall a b, (a*b) mod b = 0.
Proof. intros. zero_or_not b. apply Z.mod_mul. auto. Qed.
Lemma Z_div_mult_full : forall a b:Z, b <> 0 -> (a*b)/b = a.
Proof Z.div_mul.
(** * Order results about Z.modulo and Z.div *)
(* Division of positive numbers is positive. *)
Lemma Z_div_pos: forall a b, b > 0 -> 0 <= a -> 0 <= a/b.
Proof. intros. apply Z.div_pos; auto with zarith. Qed.
Lemma Z_div_ge0: forall a b, b > 0 -> a >= 0 -> a/b >=0.
Proof.
intros; generalize (Z_div_pos a b H); auto with zarith.
Qed.
(** As soon as the divisor is greater or equal than 2,
the division is strictly decreasing. *)
Lemma Z_div_lt : forall a b:Z, b >= 2 -> a > 0 -> a/b < a.
Proof. intros. apply Z.div_lt; auto with zarith. Qed.
(** A division of a small number by a bigger one yields zero. *)
Theorem Zdiv_small: forall a b, 0 <= a < b -> a/b = 0.
Proof Z.div_small.
(** Same situation, in term of modulo: *)
Theorem Zmod_small: forall a n, 0 <= a < n -> a mod n = a.
Proof Z.mod_small.
(** [Z.ge] is compatible with a positive division. *)
Lemma Z_div_ge : forall a b c:Z, c > 0 -> a >= b -> a/c >= b/c.
Proof. intros. apply Z.le_ge. apply Z.div_le_mono; auto with zarith. Qed.
(** Same, with [Z.le]. *)
Lemma Z_div_le : forall a b c:Z, c > 0 -> a <= b -> a/c <= b/c.
Proof. intros. apply Z.div_le_mono; auto with zarith. Qed.
(** With our choice of division, rounding of (a/b) is always done toward bottom: *)
Lemma Z_mult_div_ge : forall a b:Z, b > 0 -> b*(a/b) <= a.
Proof. intros. apply Z.mul_div_le; auto with zarith. Qed.
Lemma Z_mult_div_ge_neg : forall a b:Z, b < 0 -> b*(a/b) >= a.
Proof. intros. apply Z.le_ge. apply Z.mul_div_ge; auto with zarith. Qed.
(** The previous inequalities are exact iff the modulo is zero. *)
Lemma Z_div_exact_full_1 : forall a b:Z, a = b*(a/b) -> a mod b = 0.
Proof. intros a b. zero_or_not b. rewrite Z.div_exact; auto. Qed.
Lemma Z_div_exact_full_2 : forall a b:Z, b <> 0 -> a mod b = 0 -> a = b*(a/b).
Proof. intros; rewrite Z.div_exact; auto. Qed.
(** A modulo cannot grow beyond its starting point. *)
Theorem Zmod_le: forall a b, 0 < b -> 0 <= a -> a mod b <= a.
Proof. intros. apply Z.mod_le; auto. Qed.
(** Some additional inequalities about Z.div. *)
Theorem Zdiv_lt_upper_bound:
forall a b q, 0 < b -> a < q*b -> a/b < q.
Proof. intros a b q; rewrite Z.mul_comm; apply Z.div_lt_upper_bound. Qed.
Theorem Zdiv_le_upper_bound:
forall a b q, 0 < b -> a <= q*b -> a/b <= q.
Proof. intros a b q; rewrite Z.mul_comm; apply Z.div_le_upper_bound. Qed.
Theorem Zdiv_le_lower_bound:
forall a b q, 0 < b -> q*b <= a -> q <= a/b.
Proof. intros a b q; rewrite Z.mul_comm; apply Z.div_le_lower_bound. Qed.
(** A division of respect opposite monotonicity for the divisor *)
Lemma Zdiv_le_compat_l: forall p q r, 0 <= p -> 0 < q < r ->
p / r <= p / q.
Proof. intros; apply Z.div_le_compat_l; auto with zarith. Qed.
Theorem Zdiv_sgn: forall a b,
0 <= Z.sgn (a/b) * Z.sgn a * Z.sgn b.
Proof.
destruct a as [ |a|a]; destruct b as [ |b|b]; simpl; auto with zarith;
generalize (Z.div_pos (Zpos a) (Zpos b)); unfold Z.div, Z.div_eucl;
destruct Z.pos_div_eucl as (q,r); destruct r; omega with *.
Qed.
(** * Relations between usual operations and Z.modulo and Z.div *)
Lemma Z_mod_plus_full : forall a b c:Z, (a + b * c) mod c = a mod c.
Proof. intros. zero_or_not c. apply Z.mod_add; auto. Qed.
Lemma Z_div_plus_full : forall a b c:Z, c <> 0 -> (a + b * c) / c = a / c + b.
Proof Z.div_add.
Theorem Z_div_plus_full_l: forall a b c : Z, b <> 0 -> (a * b + c) / b = a + c / b.
Proof Z.div_add_l.
(** [Z.opp] and [Z.div], [Z.modulo].
Due to the choice of convention for our Euclidean division,
some of the relations about [Z.opp] and divisions are rather complex. *)
Lemma Zdiv_opp_opp : forall a b:Z, (-a)/(-b) = a/b.
Proof. intros. zero_or_not b. apply Z.div_opp_opp; auto. Qed.
Lemma Zmod_opp_opp : forall a b:Z, (-a) mod (-b) = - (a mod b).
Proof. intros. zero_or_not b. apply Z.mod_opp_opp; auto. Qed.
Lemma Z_mod_zero_opp_full : forall a b:Z, a mod b = 0 -> (-a) mod b = 0.
Proof. intros. zero_or_not b. apply Z.mod_opp_l_z; auto. Qed.
Lemma Z_mod_nz_opp_full : forall a b:Z, a mod b <> 0 ->
(-a) mod b = b - (a mod b).
Proof. intros. zero_or_not b. apply Z.mod_opp_l_nz; auto. Qed.
Lemma Z_mod_zero_opp_r : forall a b:Z, a mod b = 0 -> a mod (-b) = 0.
Proof. intros. zero_or_not b. apply Z.mod_opp_r_z; auto. Qed.
Lemma Z_mod_nz_opp_r : forall a b:Z, a mod b <> 0 ->
a mod (-b) = (a mod b) - b.
Proof. intros. zero_or_not b. apply Z.mod_opp_r_nz; auto. Qed.
Lemma Z_div_zero_opp_full : forall a b:Z, a mod b = 0 -> (-a)/b = -(a/b).
Proof. intros. zero_or_not b. apply Z.div_opp_l_z; auto. Qed.
Lemma Z_div_nz_opp_full : forall a b:Z, a mod b <> 0 ->
(-a)/b = -(a/b)-1.
Proof. intros a b. zero_or_not b. intros; rewrite Z.div_opp_l_nz; auto. Qed.
Lemma Z_div_zero_opp_r : forall a b:Z, a mod b = 0 -> a/(-b) = -(a/b).
Proof. intros. zero_or_not b. apply Z.div_opp_r_z; auto. Qed.
Lemma Z_div_nz_opp_r : forall a b:Z, a mod b <> 0 ->
a/(-b) = -(a/b)-1.
Proof. intros a b. zero_or_not b. intros; rewrite Z.div_opp_r_nz; auto. Qed.
(** Cancellations. *)
Lemma Zdiv_mult_cancel_r : forall a b c:Z,
c <> 0 -> (a*c)/(b*c) = a/b.
Proof. intros. zero_or_not b. apply Z.div_mul_cancel_r; auto. Qed.
Lemma Zdiv_mult_cancel_l : forall a b c:Z,
c<>0 -> (c*a)/(c*b) = a/b.
Proof.
intros. rewrite (Z.mul_comm c b); zero_or_not b.
rewrite (Z.mul_comm b c). apply Z.div_mul_cancel_l; auto.
Qed.
Lemma Zmult_mod_distr_l: forall a b c,
(c*a) mod (c*b) = c * (a mod b).
Proof.
intros. zero_or_not c. rewrite (Z.mul_comm c b); zero_or_not b.
rewrite (Z.mul_comm b c). apply Z.mul_mod_distr_l; auto.
Qed.
Lemma Zmult_mod_distr_r: forall a b c,
(a*c) mod (b*c) = (a mod b) * c.
Proof.
intros. zero_or_not b. rewrite (Z.mul_comm b c); zero_or_not c.
rewrite (Z.mul_comm c b). apply Z.mul_mod_distr_r; auto.
Qed.
(** Operations modulo. *)
Theorem Zmod_mod: forall a n, (a mod n) mod n = a mod n.
Proof. intros. zero_or_not n. apply Z.mod_mod; auto. Qed.
Theorem Zmult_mod: forall a b n,
(a * b) mod n = ((a mod n) * (b mod n)) mod n.
Proof. intros. zero_or_not n. apply Z.mul_mod; auto. Qed.
Theorem Zplus_mod: forall a b n,
(a + b) mod n = (a mod n + b mod n) mod n.
Proof. intros. zero_or_not n. apply Z.add_mod; auto. Qed.
Theorem Zminus_mod: forall a b n,
(a - b) mod n = (a mod n - b mod n) mod n.
Proof.
intros.
replace (a - b) with (a + (-1) * b); auto with zarith.
replace (a mod n - b mod n) with (a mod n + (-1) * (b mod n)); auto with zarith.
rewrite Zplus_mod.
rewrite Zmult_mod.
rewrite Zplus_mod with (b:=(-1) * (b mod n)).
rewrite Zmult_mod.
rewrite Zmult_mod with (b:= b mod n).
repeat rewrite Zmod_mod; auto.
Qed.
Lemma Zplus_mod_idemp_l: forall a b n, (a mod n + b) mod n = (a + b) mod n.
Proof.
intros; rewrite Zplus_mod, Zmod_mod, <- Zplus_mod; auto.
Qed.
Lemma Zplus_mod_idemp_r: forall a b n, (b + a mod n) mod n = (b + a) mod n.
Proof.
intros; rewrite Zplus_mod, Zmod_mod, <- Zplus_mod; auto.
Qed.
Lemma Zminus_mod_idemp_l: forall a b n, (a mod n - b) mod n = (a - b) mod n.
Proof.
intros; rewrite Zminus_mod, Zmod_mod, <- Zminus_mod; auto.
Qed.
Lemma Zminus_mod_idemp_r: forall a b n, (a - b mod n) mod n = (a - b) mod n.
Proof.
intros; rewrite Zminus_mod, Zmod_mod, <- Zminus_mod; auto.
Qed.
Lemma Zmult_mod_idemp_l: forall a b n, (a mod n * b) mod n = (a * b) mod n.
Proof.
intros; rewrite Zmult_mod, Zmod_mod, <- Zmult_mod; auto.
Qed.
Lemma Zmult_mod_idemp_r: forall a b n, (b * (a mod n)) mod n = (b * a) mod n.
Proof.
intros; rewrite Zmult_mod, Zmod_mod, <- Zmult_mod; auto.
Qed.
(** For a specific number N, equality modulo N is hence a nice setoid
equivalence, compatible with [+], [-] and [*]. *)
Section EqualityModulo.
Variable N:Z.
Definition eqm a b := (a mod N = b mod N).
Infix "==" := eqm (at level 70).
Lemma eqm_refl : forall a, a == a.
Proof. unfold eqm; auto. Qed.
Lemma eqm_sym : forall a b, a == b -> b == a.
Proof. unfold eqm; auto. Qed.
Lemma eqm_trans : forall a b c,
a == b -> b == c -> a == c.
Proof. unfold eqm; eauto with *. Qed.
Instance eqm_setoid : Equivalence eqm.
Proof.
constructor; [exact eqm_refl | exact eqm_sym | exact eqm_trans].
Qed.
Instance Zplus_eqm : Proper (eqm ==> eqm ==> eqm) Z.add.
Proof.
unfold eqm; repeat red; intros. rewrite Zplus_mod, H, H0, <- Zplus_mod; auto.
Qed.
Instance Zminus_eqm : Proper (eqm ==> eqm ==> eqm) Z.sub.
Proof.
unfold eqm; repeat red; intros. rewrite Zminus_mod, H, H0, <- Zminus_mod; auto.
Qed.
Instance Zmult_eqm : Proper (eqm ==> eqm ==> eqm) Z.mul.
Proof.
unfold eqm; repeat red; intros. rewrite Zmult_mod, H, H0, <- Zmult_mod; auto.
Qed.
Instance Zopp_eqm : Proper (eqm ==> eqm) Z.opp.
Proof.
intros x y H. change ((-x)==(-y)) with ((0-x)==(0-y)). now rewrite H.
Qed.
Lemma Zmod_eqm : forall a, (a mod N) == a.
Proof.
intros; exact (Zmod_mod a N).
Qed.
(* NB: Z.modulo and Z.div are not morphisms with respect to eqm.
For instance, let (==) be (eqm 2). Then we have (3 == 1) but:
~ (3 mod 3 == 1 mod 3)
~ (1 mod 3 == 1 mod 1)
~ (3/3 == 1/3)
~ (1/3 == 1/1)
*)
End EqualityModulo.
Lemma Zdiv_Zdiv : forall a b c, 0<=b -> 0<=c -> (a/b)/c = a/(b*c).
Proof.
intros. zero_or_not b. rewrite Z.mul_comm. zero_or_not c.
rewrite Z.mul_comm. apply Z.div_div; auto with zarith.
Qed.
(** Unfortunately, the previous result isn't always true on negative numbers.
For instance: 3/(-2)/(-2) = 1 <> 0 = 3 / (-2*-2) *)
(** A last inequality: *)
Theorem Zdiv_mult_le:
forall a b c, 0<=a -> 0<=b -> 0<=c -> c*(a/b) <= (c*a)/b.
Proof.
intros. zero_or_not b. apply Z.div_mul_le; auto with zarith. Qed.
(** Z.modulo is related to divisibility (see more in Znumtheory) *)
Lemma Zmod_divides : forall a b, b<>0 ->
(a mod b = 0 <-> exists c, a = b*c).
Proof.
intros. rewrite Z.mod_divide; trivial.
split; intros (c,Hc); exists c; subst; auto with zarith.
Qed.
(** Particular case : dividing by 2 is related with parity *)
Lemma Zdiv2_div : forall a, Z.div2 a = a/2.
Proof Z.div2_div.
Lemma Zmod_odd : forall a, a mod 2 = if Z.odd a then 1 else 0.
Proof.
intros a. now rewrite <- Z.bit0_odd, <- Z.bit0_mod.
Qed.
Lemma Zmod_even : forall a, a mod 2 = if Z.even a then 0 else 1.
Proof.
intros a. rewrite Zmod_odd, Zodd_even_bool. now destruct Z.even.
Qed.
Lemma Zodd_mod : forall a, Z.odd a = Zeq_bool (a mod 2) 1.
Proof.
intros a. rewrite Zmod_odd. now destruct Z.odd.
Qed.
Lemma Zeven_mod : forall a, Z.even a = Zeq_bool (a mod 2) 0.
Proof.
intros a. rewrite Zmod_even. now destruct Z.even.
Qed.
(** * Compatibility *)
(** Weaker results kept only for compatibility *)
Lemma Z_mod_same : forall a, a > 0 -> a mod a = 0.
Proof.
intros; apply Z_mod_same_full.
Qed.
Lemma Z_div_same : forall a, a > 0 -> a/a = 1.
Proof.
intros; apply Z_div_same_full; auto with zarith.
Qed.
Lemma Z_div_plus : forall a b c:Z, c > 0 -> (a + b * c) / c = a / c + b.
Proof.
intros; apply Z_div_plus_full; auto with zarith.
Qed.
Lemma Z_div_mult : forall a b:Z, b > 0 -> (a*b)/b = a.
Proof.
intros; apply Z_div_mult_full; auto with zarith.
Qed.
Lemma Z_mod_plus : forall a b c:Z, c > 0 -> (a + b * c) mod c = a mod c.
Proof.
intros; apply Z_mod_plus_full; auto with zarith.
Qed.
Lemma Z_div_exact_1 : forall a b:Z, b > 0 -> a = b*(a/b) -> a mod b = 0.
Proof.
intros; apply Z_div_exact_full_1; auto with zarith.
Qed.
Lemma Z_div_exact_2 : forall a b:Z, b > 0 -> a mod b = 0 -> a = b*(a/b).
Proof.
intros; apply Z_div_exact_full_2; auto with zarith.
Qed.
Lemma Z_mod_zero_opp : forall a b:Z, b > 0 -> a mod b = 0 -> (-a) mod b = 0.
Proof.
intros; apply Z_mod_zero_opp_full; auto with zarith.
Qed.
(** * A direct way to compute Z.modulo *)
Fixpoint Zmod_POS (a : positive) (b : Z) : Z :=
match a with
| xI a' =>
let r := Zmod_POS a' b in
let r' := (2 * r + 1) in
if r' <? b then r' else (r' - b)
| xO a' =>
let r := Zmod_POS a' b in
let r' := (2 * r) in
if r' <? b then r' else (r' - b)
| xH => if 2 <=? b then 1 else 0
end.
Definition Zmod' a b :=
match a with
| Z0 => 0
| Zpos a' =>
match b with
| Z0 => 0
| Zpos _ => Zmod_POS a' b
| Zneg b' =>
let r := Zmod_POS a' (Zpos b') in
match r with Z0 => 0 | _ => b + r end
end
| Zneg a' =>
match b with
| Z0 => 0
| Zpos _ =>
let r := Zmod_POS a' b in
match r with Z0 => 0 | _ => b - r end
| Zneg b' => - (Zmod_POS a' (Zpos b'))
end
end.
Theorem Zmod_POS_correct a b : Zmod_POS a b = snd (Z.pos_div_eucl a b).
Proof.
induction a as [a IH|a IH| ]; simpl; rewrite ?IH.
destruct (Z.pos_div_eucl a b) as (p,q); simpl;
case Z.ltb_spec; reflexivity.
destruct (Z.pos_div_eucl a b) as (p,q); simpl;
case Z.ltb_spec; reflexivity.
case Z.leb_spec; trivial.
Qed.
Theorem Zmod'_correct: forall a b, Zmod' a b = a mod b.
Proof.
intros a b; unfold Z.modulo; case a; simpl; auto.
intros p; case b; simpl; auto.
intros p1; refine (Zmod_POS_correct _ _); auto.
intros p1; rewrite Zmod_POS_correct; auto.
case (Z.pos_div_eucl p (Zpos p1)); simpl; intros z1 z2; case z2; auto.
intros p; case b; simpl; auto.
intros p1; rewrite Zmod_POS_correct; auto.
case (Z.pos_div_eucl p (Zpos p1)); simpl; intros z1 z2; case z2; auto.
intros p1; rewrite Zmod_POS_correct; simpl; auto.
case (Z.pos_div_eucl p (Zpos p1)); auto.
Qed.
(** Another convention is possible for division by negative numbers:
* quotient is always the biggest integer smaller than or equal to a/b
* remainder is hence always positive or null. *)
Theorem Zdiv_eucl_extended :
forall b:Z,
b <> 0 ->
forall a:Z,
{qr : Z * Z | let (q, r) := qr in a = b * q + r /\ 0 <= r < Z.abs b}.
Proof.
intros b Hb a.
destruct (Z_le_gt_dec 0 b) as [Hb'|Hb'].
- assert (Hb'' : b > 0) by omega.
rewrite Z.abs_eq; [ apply Zdiv_eucl_exist; assumption | assumption ].
- assert (Hb'' : - b > 0) by omega.
destruct (Zdiv_eucl_exist Hb'' a) as ((q,r),[]).
exists (- q, r).
split.
+ rewrite <- Z.mul_opp_comm; assumption.
+ rewrite Z.abs_neq; [ assumption | omega ].
Qed.
Arguments Zdiv_eucl_extended : default implicits.
(** * Division and modulo in Z agree with same in nat: *)
Require Import PeanoNat.
Lemma div_Zdiv (n m: nat): m <> O ->
Z.of_nat (n / m) = Z.of_nat n / Z.of_nat m.
Proof.
intros.
apply (Zdiv_unique _ _ _ (Z.of_nat (n mod m))).
split. auto with zarith.
now apply inj_lt, Nat.mod_upper_bound.
rewrite <- Nat2Z.inj_mul, <- Nat2Z.inj_add.
now apply inj_eq, Nat.div_mod.
Qed.
Lemma mod_Zmod (n m: nat): m <> O ->
Z.of_nat (n mod m) = (Z.of_nat n) mod (Z.of_nat m).
Proof.
intros.
apply (Zmod_unique _ _ (Z.of_nat n / Z.of_nat m)).
split. auto with zarith.
now apply inj_lt, Nat.mod_upper_bound.
rewrite <- div_Zdiv, <- Nat2Z.inj_mul, <- Nat2Z.inj_add by trivial.
now apply inj_eq, Nat.div_mod.
Qed.
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: clock.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 16.0.0 Build 211 04/27/2016 SJ Lite Edition
// ************************************************************
//Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus Prime License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module clock (
inclk0,
c0);
input inclk0;
output c0;
wire [4:0] sub_wire0;
wire [0:0] sub_wire4 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire sub_wire2 = inclk0;
wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
altpll altpll_component (
.inclk (sub_wire3),
.clk (sub_wire0),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.locked (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 5,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 2,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Cyclone IV E",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=clock",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_UNUSED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "20.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "20.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "clock.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "5"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: GEN_FILE: TYPE_NORMAL clock.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL clock.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL clock.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clock.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clock.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL clock_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clock_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A211O_TB_V
`define SKY130_FD_SC_HS__A211O_TB_V
/**
* a211o: 2-input AND into first input of 3-input OR.
*
* X = ((A1 & A2) | B1 | C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a211o.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg C1;
reg VPWR;
reg VGND;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 C1 = 1'b0;
#100 VGND = 1'b0;
#120 VPWR = 1'b0;
#140 A1 = 1'b1;
#160 A2 = 1'b1;
#180 B1 = 1'b1;
#200 C1 = 1'b1;
#220 VGND = 1'b1;
#240 VPWR = 1'b1;
#260 A1 = 1'b0;
#280 A2 = 1'b0;
#300 B1 = 1'b0;
#320 C1 = 1'b0;
#340 VGND = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VGND = 1'b1;
#420 C1 = 1'b1;
#440 B1 = 1'b1;
#460 A2 = 1'b1;
#480 A1 = 1'b1;
#500 VPWR = 1'bx;
#520 VGND = 1'bx;
#540 C1 = 1'bx;
#560 B1 = 1'bx;
#580 A2 = 1'bx;
#600 A1 = 1'bx;
end
sky130_fd_sc_hs__a211o dut (.A1(A1), .A2(A2), .B1(B1), .C1(C1), .VPWR(VPWR), .VGND(VGND), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A211O_TB_V
|
//
// fixed for 9.1 jan 21 2010 cruben
//
//`include "timescale.v"
`include "i2c_master_defines.v"
module i2c_opencores
(
wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o,
wb_we_i, wb_stb_i, /*wb_cyc_i,*/ wb_ack_o, wb_inta_o,
scl_pad_io, sda_pad_io
);
// Common bus signals
input wb_clk_i; // WISHBONE clock
input wb_rst_i; // WISHBONE reset
// Slave signals
input [2:0] wb_adr_i; // WISHBONE address input
input [7:0] wb_dat_i; // WISHBONE data input
output [7:0] wb_dat_o; // WISHBONE data output
input wb_we_i; // WISHBONE write enable input
input wb_stb_i; // WISHBONE strobe input
//input wb_cyc_i; // WISHBONE cycle input
output wb_ack_o; // WISHBONE acknowledge output
output wb_inta_o; // WISHBONE interrupt output
// I2C signals
inout scl_pad_io; // I2C clock io
inout sda_pad_io; // I2C data io
wire wb_cyc_i; // WISHBONE cycle input
// Wire tri-state scl/sda
wire scl_pad_i;
wire scl_pad_o;
wire scl_pad_io;
wire scl_padoen_o;
assign wb_cyc_i = wb_stb_i;
assign scl_pad_i = scl_pad_io;
assign scl_pad_io = scl_padoen_o ? 1'bZ : scl_pad_o;
wire sda_pad_i;
wire sda_pad_o;
wire sda_pad_io;
wire sda_padoen_o;
assign sda_pad_i = sda_pad_io;
assign sda_pad_io = sda_padoen_o ? 1'bZ : sda_pad_o;
// Avalon doesn't have an asynchronous reset
// set it to be inactive and just use synchronous reset
// reset level is a parameter, 0 is the default (active-low reset)
wire arst_i;
assign arst_i = 1'b1;
// Connect the top level I2C core
i2c_master_top i2c_master_top_inst
(
.wb_clk_i(wb_clk_i), .wb_rst_i(wb_rst_i), .arst_i(arst_i),
.wb_adr_i(wb_adr_i), .wb_dat_i(wb_dat_i), .wb_dat_o(wb_dat_o),
.wb_we_i(wb_we_i), .wb_stb_i(wb_stb_i), .wb_cyc_i(wb_cyc_i),
.wb_ack_o(wb_ack_o), .wb_inta_o(wb_inta_o),
.scl_pad_i(scl_pad_i), .scl_pad_o(scl_pad_o), .scl_padoen_o(scl_padoen_o),
.sda_pad_i(sda_pad_i), .sda_pad_o(sda_pad_o), .sda_padoen_o(sda_padoen_o)
);
endmodule
|
// -*- Mode: Verilog -*-
// Filename : system_controller.v
// Description : Prototype System Controller for SPI FPGA
// Author : Philip Tracton
// Created On : Fri Jul 8 20:54:44 2016
// Last Modified By: Philip Tracton
// Last Modified On: Fri Jul 8 20:54:44 2016
// Update Count : 0
// Status : Unknown, Use with caution!
module system_controller (/*AUTOARG*/
// Outputs
clk, rst, nrst,
// Inputs
clk_i, rst_i
) ;
input wire clk_i;
input wire rst_i;
output wire clk;
output wire rst;
output wire nrst;
`ifdef XILINX
//
// Input buffer the clk pin
//
wire clk_ibuf;
IBUF xclk_ibufg(.I(clk_i), .O(clk_ibuf));
`else
assign clk = clk_i;
reg [4:0] reset_count =0;
assign rst = |reset_count;
assign nrst = ~rst;
always @(posedge clk_i or posedge rst_i)
if (rst_i) begin
reset_count <= 1;
end else begin
if (reset_count)
reset_count <= reset_count + 1;
end
`endif
endmodule // system_controller
|
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: wdata_mux.v
//
// Description:
// Contains MI-side write command queue.
// SI-slot index selected by AW arbiter is pushed onto queue when S_AVALID transfer is received.
// Queue is popped when WLAST data beat is transferred.
// W-channel input from SI-slot selected by queue output is transferred to MI-side output .
//--------------------------------------------------------------------------
//
// Structure:
// wdata_mux
// axic_reg_srl_fifo
// mux_enc
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_8_wdata_mux #
(
parameter C_FAMILY = "none", // FPGA Family.
parameter integer C_WMESG_WIDTH = 1, // Width of W-channel payload.
parameter integer C_NUM_SLAVE_SLOTS = 1, // Number of S_* ports.
parameter integer C_SELECT_WIDTH = 1, // Width of ASELECT.
parameter integer C_FIFO_DEPTH_LOG = 0 // Queue depth = 2**C_FIFO_DEPTH_LOG.
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Slave Data Ports
input wire [C_NUM_SLAVE_SLOTS*C_WMESG_WIDTH-1:0] S_WMESG,
input wire [C_NUM_SLAVE_SLOTS-1:0] S_WLAST,
input wire [C_NUM_SLAVE_SLOTS-1:0] S_WVALID,
output wire [C_NUM_SLAVE_SLOTS-1:0] S_WREADY,
// Master Data Ports
output wire [C_WMESG_WIDTH-1:0] M_WMESG,
output wire M_WLAST,
output wire M_WVALID,
input wire M_WREADY,
// Write Command Ports
input wire [C_SELECT_WIDTH-1:0] S_ASELECT, // SI-slot index from AW arbiter
input wire S_AVALID,
output wire S_AREADY
);
localparam integer P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG <= 5) ? C_FIFO_DEPTH_LOG : 5; // Max depth = 32
// Decode select input to 1-hot
function [C_NUM_SLAVE_SLOTS-1:0] f_decoder (
input [C_SELECT_WIDTH-1:0] sel
);
integer i;
begin
for (i=0; i<C_NUM_SLAVE_SLOTS; i=i+1) begin
f_decoder[i] = (sel == i);
end
end
endfunction
wire m_valid_i;
wire m_last_i;
wire [C_NUM_SLAVE_SLOTS-1:0] m_select_hot;
wire [C_SELECT_WIDTH-1:0] m_select_enc;
wire m_avalid;
wire m_aready;
generate
if (C_NUM_SLAVE_SLOTS>1) begin : gen_wmux
// SI-side write command queue
axi_data_fifo_v2_1_6_axic_reg_srl_fifo #
(
.C_FAMILY (C_FAMILY),
.C_FIFO_WIDTH (C_SELECT_WIDTH),
.C_FIFO_DEPTH_LOG (P_FIFO_DEPTH_LOG),
.C_USE_FULL (0)
)
wmux_aw_fifo
(
.ACLK (ACLK),
.ARESET (ARESET),
.S_MESG (S_ASELECT),
.S_VALID (S_AVALID),
.S_READY (S_AREADY),
.M_MESG (m_select_enc),
.M_VALID (m_avalid),
.M_READY (m_aready)
);
assign m_select_hot = f_decoder(m_select_enc);
// Instantiate MUX
generic_baseblocks_v2_1_0_mux_enc #
(
.C_FAMILY ("rtl"),
.C_RATIO (C_NUM_SLAVE_SLOTS),
.C_SEL_WIDTH (C_SELECT_WIDTH),
.C_DATA_WIDTH (C_WMESG_WIDTH)
) mux_w
(
.S (m_select_enc),
.A (S_WMESG),
.O (M_WMESG),
.OE (1'b1)
);
assign m_last_i = |(S_WLAST & m_select_hot);
assign m_valid_i = |(S_WVALID & m_select_hot);
assign m_aready = m_valid_i & m_avalid & m_last_i & M_WREADY;
assign M_WLAST = m_last_i;
assign M_WVALID = m_valid_i & m_avalid;
assign S_WREADY = m_select_hot & {C_NUM_SLAVE_SLOTS{m_avalid & M_WREADY}};
end else begin : gen_no_wmux
assign S_AREADY = 1'b1;
assign M_WVALID = S_WVALID;
assign S_WREADY = M_WREADY;
assign M_WLAST = S_WLAST;
assign M_WMESG = S_WMESG;
end
endgenerate
endmodule
`default_nettype wire
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
(* CORE_GENERATION_INFO="vectoradd,hls_ip_2017_4,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=2.552000,HLS_SYN_LAT=65,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=10,HLS_SYN_LUT=149}" *)
module vectoradd (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
ap_ready,
in0,
in0_ap_vld,
in0_ap_ack,
in1,
in1_ap_vld,
in1_ap_ack,
out_r,
out_r_ap_vld,
out_r_ap_ack
);
parameter ap_ST_fsm_state1 = 2'd1;
parameter ap_ST_fsm_state2 = 2'd2;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
output ap_ready;
input [31:0] in0;
input in0_ap_vld;
output in0_ap_ack;
input [31:0] in1;
input in1_ap_vld;
output in1_ap_ack;
output [31:0] out_r;
output out_r_ap_vld;
input out_r_ap_ack;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg in0_ap_ack;
reg in1_ap_ack;
reg out_r_ap_vld;
(* fsm_encoding = "none" *) reg [1:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg in0_blk_n;
wire ap_CS_fsm_state2;
wire [0:0] exitcond_fu_64_p2;
reg in1_blk_n;
reg out_r_blk_n;
wire [6:0] i_1_fu_70_p2;
reg ap_block_state2;
reg ap_sig_ioackin_out_r_ap_ack;
reg ap_block_state2_io;
reg [6:0] i_reg_53;
reg ap_reg_ioackin_out_r_ap_ack;
reg [1:0] ap_NS_fsm;
reg ap_condition_100;
reg ap_condition_57;
// power-on initialization
initial begin
#0 ap_CS_fsm = 2'd1;
#0 ap_reg_ioackin_out_r_ap_ack = 1'b0;
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_reg_ioackin_out_r_ap_ack <= 1'b0;
end else begin
if (((exitcond_fu_64_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
if ((1'b1 == ap_condition_57)) begin
ap_reg_ioackin_out_r_ap_ack <= 1'b0;
end else if ((1'b1 == ap_condition_100)) begin
ap_reg_ioackin_out_r_ap_ack <= 1'b1;
end
end
end
end
always @ (posedge ap_clk) begin
if ((~((1'b1 == ap_block_state2_io) | ((exitcond_fu_64_p2 == 1'd0) & (in1_ap_vld == 1'b0)) | ((exitcond_fu_64_p2 == 1'd0) & (in0_ap_vld == 1'b0))) & (exitcond_fu_64_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
i_reg_53 <= i_1_fu_70_p2;
end else if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
i_reg_53 <= 7'd0;
end
end
always @ (*) begin
if ((~((1'b1 == ap_block_state2_io) | ((exitcond_fu_64_p2 == 1'd0) & (in1_ap_vld == 1'b0)) | ((exitcond_fu_64_p2 == 1'd0) & (in0_ap_vld == 1'b0))) & (exitcond_fu_64_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
ap_done = 1'b1;
end else begin
ap_done = 1'b0;
end
end
always @ (*) begin
if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @ (*) begin
if ((~((1'b1 == ap_block_state2_io) | ((exitcond_fu_64_p2 == 1'd0) & (in1_ap_vld == 1'b0)) | ((exitcond_fu_64_p2 == 1'd0) & (in0_ap_vld == 1'b0))) & (exitcond_fu_64_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @ (*) begin
if ((ap_reg_ioackin_out_r_ap_ack == 1'b0)) begin
ap_sig_ioackin_out_r_ap_ack = out_r_ap_ack;
end else begin
ap_sig_ioackin_out_r_ap_ack = 1'b1;
end
end
always @ (*) begin
if ((~((1'b1 == ap_block_state2_io) | ((exitcond_fu_64_p2 == 1'd0) & (in1_ap_vld == 1'b0)) | ((exitcond_fu_64_p2 == 1'd0) & (in0_ap_vld == 1'b0))) & (exitcond_fu_64_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
in0_ap_ack = 1'b1;
end else begin
in0_ap_ack = 1'b0;
end
end
always @ (*) begin
if (((exitcond_fu_64_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
in0_blk_n = in0_ap_vld;
end else begin
in0_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((1'b1 == ap_block_state2_io) | ((exitcond_fu_64_p2 == 1'd0) & (in1_ap_vld == 1'b0)) | ((exitcond_fu_64_p2 == 1'd0) & (in0_ap_vld == 1'b0))) & (exitcond_fu_64_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
in1_ap_ack = 1'b1;
end else begin
in1_ap_ack = 1'b0;
end
end
always @ (*) begin
if (((exitcond_fu_64_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
in1_blk_n = in1_ap_vld;
end else begin
in1_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~(((exitcond_fu_64_p2 == 1'd0) & (in1_ap_vld == 1'b0)) | ((exitcond_fu_64_p2 == 1'd0) & (in0_ap_vld == 1'b0))) & (exitcond_fu_64_p2 == 1'd0) & (ap_reg_ioackin_out_r_ap_ack == 1'b0) & (1'b1 == ap_CS_fsm_state2))) begin
out_r_ap_vld = 1'b1;
end else begin
out_r_ap_vld = 1'b0;
end
end
always @ (*) begin
if (((exitcond_fu_64_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
out_r_blk_n = out_r_ap_ack;
end else begin
out_r_blk_n = 1'b1;
end
end
always @ (*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1 : begin
if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
ap_NS_fsm = ap_ST_fsm_state2;
end else begin
ap_NS_fsm = ap_ST_fsm_state1;
end
end
ap_ST_fsm_state2 : begin
if ((~((1'b1 == ap_block_state2_io) | ((exitcond_fu_64_p2 == 1'd0) & (in1_ap_vld == 1'b0)) | ((exitcond_fu_64_p2 == 1'd0) & (in0_ap_vld == 1'b0))) & (exitcond_fu_64_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
ap_NS_fsm = ap_ST_fsm_state1;
end else if ((~((1'b1 == ap_block_state2_io) | ((exitcond_fu_64_p2 == 1'd0) & (in1_ap_vld == 1'b0)) | ((exitcond_fu_64_p2 == 1'd0) & (in0_ap_vld == 1'b0))) & (exitcond_fu_64_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
ap_NS_fsm = ap_ST_fsm_state2;
end else begin
ap_NS_fsm = ap_ST_fsm_state2;
end
end
default : begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];
always @ (*) begin
ap_block_state2 = (((exitcond_fu_64_p2 == 1'd0) & (in1_ap_vld == 1'b0)) | ((exitcond_fu_64_p2 == 1'd0) & (in0_ap_vld == 1'b0)));
end
always @ (*) begin
ap_block_state2_io = ((exitcond_fu_64_p2 == 1'd0) & (ap_sig_ioackin_out_r_ap_ack == 1'b0));
end
always @ (*) begin
ap_condition_100 = (~(((exitcond_fu_64_p2 == 1'd0) & (in1_ap_vld == 1'b0)) | ((exitcond_fu_64_p2 == 1'd0) & (in0_ap_vld == 1'b0))) & (out_r_ap_ack == 1'b1));
end
always @ (*) begin
ap_condition_57 = ~((1'b1 == ap_block_state2_io) | ((exitcond_fu_64_p2 == 1'd0) & (in1_ap_vld == 1'b0)) | ((exitcond_fu_64_p2 == 1'd0) & (in0_ap_vld == 1'b0)));
end
assign exitcond_fu_64_p2 = ((i_reg_53 == 7'd64) ? 1'b1 : 1'b0);
assign i_1_fu_70_p2 = (i_reg_53 + 7'd1);
assign out_r = (in0 + in1);
endmodule //vectoradd
|
// (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
// IP Revision: 17
(* X_CORE_INFO = "axi_protocol_converter_v2_1_17_axi_protocol_converter,Vivado 2018.2" *)
(* CHECK_LICENSE_TYPE = "gcd_block_design_auto_pc_1,axi_protocol_converter_v2_1_17_axi_protocol_converter,{}" *)
(* CORE_GENERATION_INFO = "gcd_block_design_auto_pc_1,axi_protocol_converter_v2_1_17_axi_protocol_converter,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_protocol_converter,x_ipVersion=2.1,x_ipCoreRevision=17,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_M_AXI_PROTOCOL=2,C_S_AXI_PROTOCOL=1,C_IGNORE_ID=0,C_AXI_ID_WIDTH=12,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_A\
XI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_TRANSLATION_MODE=2}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module gcd_block_design_auto_pc_1 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN gcd_block_design_processing_system7_0_2_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, TYPE INTERCONNECT" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [11 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [3 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [1 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
input wire [11 : 0] s_axi_wid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [11 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [11 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [3 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [1 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [11 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN gcd_block_design_processing_system7_0_2_FCLK_CLK0, NUM_READ_\
THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN gcd_block_design_processing_system7_0_2_FCLK_CLK0, NUM_REA\
D_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_protocol_converter_v2_1_17_axi_protocol_converter #(
.C_FAMILY("zynq"),
.C_M_AXI_PROTOCOL(2),
.C_S_AXI_PROTOCOL(1),
.C_IGNORE_ID(0),
.C_AXI_ID_WIDTH(12),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_TRANSLATION_MODE(2)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(4'H0),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(s_axi_wid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(4'H0),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(12'H000),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(12'H000),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(1'H1),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
//
// SDW - Int type declaration/validation
//
// D: Assign a 16 bit vector to an int and observe the 0 extension.
// D: Assign a 32 bit vector to an int and observer same value.
// D: Add -1 + 1. Add 0 and -1...and observer correct values.
module main();
reg [15:0] a;
reg [31:0] b;
integer result;
integer int_a;
integer int_b;
initial // Excitation block
begin
a = 0;
b = 0;
result = 0;
# 5; // Assign a shorter value
a = 16'h1234; // should see 0 extension in result
result = a;
# 5; // Assign a 32 bit vector
b = 32'h12345678 ;
result = b;
# 5; // Validate sum basic integer arithmetic
int_a = -1 ; // pun intended!
int_b = 1;
result = int_a + int_b;
# 5;
int_a = 0;
int_b = -1;
result = int_a + int_b;
end
initial // Validation block
begin
#1 ;
#5 ;
if(result != 32'h00001234)
begin
$display("FAILED - Bit extend wrong\n");
$finish ;
end
#5 ;
if(result != 32'h12345678)
begin
$display("FAILED - 32 bit assign wrong\n");
$finish ;
end
#5 ;
if(result != 32'h00000000)
begin
$display("FAILED - -1 + 1 = %h\n",result);
$finish ;
end
#5 ;
if(result != 32'hffffffff)
begin
$display("FAILED - 0 - 1 = %h\n",result);
$finish ;
end
$display("PASSED\n");
$finish ;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_FUNCTIONAL_V
/**
* lsbufhv2lv_simple: Level shifting buffer, High Voltage to Low
* Voltage, simple (hv devices in inverters on lv
* power rail).
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__lsbufhv2lv_simple (
X,
A
);
// Module ports
output X;
input A;
// Name Output Other arguments
buf buf0 (X , A );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_FUNCTIONAL_V |
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: fifo_1kx16.v
// Megafunction Name(s):
// scfifo
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module fifo_1kx16 (
aclr,
clock,
data,
rdreq,
wrreq,
almost_empty,
empty,
full,
q,
usedw);
input aclr;
input clock;
input [15:0] data;
input rdreq;
input wrreq;
output almost_empty;
output empty;
output full;
output [15:0] q;
output [9:0] usedw;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "1"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "504"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "1024"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "16"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: ALMOST_EMPTY_VALUE NUMERIC "504"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
// Retrieval info: USED_PORT: almost_empty 0 0 0 0 OUTPUT NODEFVAL almost_empty
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: usedw 0 0 10 0 OUTPUT NODEFVAL usedw[9..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: usedw 0 0 10 0 @usedw 0 0 10 0
// Retrieval info: CONNECT: almost_empty 0 0 0 0 @almost_empty 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_wave*.jpg FALSE
|
/*
* Copyright (c) 2002 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module foo;
reg [2:0] cond;
reg test;
initial begin
cond = 0;
test = cond ? 1'b1 : 1'b0;
if (test !== 1'b0) begin
$display("FAILED -- cond=%b, test=%b", cond, test);
$finish;
end
cond = 1;
test = cond ? 1'b1 : 1'b0;
if (test !== 1) begin
$display("FAILED -- cond=%b, test=%b", cond, test);
$finish;
end
cond = 2;
test = cond ? 1'b1 : 1'b0;
if (test !== 1) begin
$display("FAILED -- cond=%b, test=%b", cond, test);
$finish;
end
$display("PASSED");
end // initial begin
endmodule
|
//altera message_off 10230 10036
//For tCL = 3 and tCWL = 2 rdwr_data_tmg block output must be registered in order to support ODT
`timescale 1 ps / 1 ps
module alt_mem_ddrx_ddr2_odt_gen
# ( parameter
CFG_DWIDTH_RATIO = 2,
CFG_PORT_WIDTH_ADD_LAT = 3,
CFG_PORT_WIDTH_OUTPUT_REGD = 1,
CFG_PORT_WIDTH_TCL = 4
)
(
ctl_clk,
ctl_reset_n,
cfg_tcl,
cfg_add_lat,
cfg_burst_length,
cfg_output_regd,
bg_do_write,
bg_do_read,
int_odt_l,
int_odt_h
);
//=================================================================================================//
// Local parameter definition //
//=================================================================================================//
localparam integer CFG_TCL_PIPE_LENGTH = 2**CFG_PORT_WIDTH_TCL; // okay to size this to 4 since max latency in DDR2 is 7+6=13
localparam CFG_TAOND = 2;
localparam CFG_TAOFD = 2.5;
//=================================================================================================//
// input/output declaration //
//=================================================================================================//
input ctl_clk;
input ctl_reset_n;
input [CFG_PORT_WIDTH_TCL-1:0] cfg_tcl;
input [CFG_PORT_WIDTH_ADD_LAT-1:0] cfg_add_lat;
input [4:0] cfg_burst_length;
input [CFG_PORT_WIDTH_OUTPUT_REGD-1:0] cfg_output_regd;
input bg_do_write;
input bg_do_read;
output int_odt_l;
output int_odt_h;
//=================================================================================================//
// reg/wire declaration //
//=================================================================================================//
wire bg_do_write;
wire bg_do_read;
reg [1:0] regd_output;
reg [CFG_PORT_WIDTH_TCL-1:0] int_tcwl_unreg;
reg [CFG_PORT_WIDTH_TCL-1:0] int_tcwl;
reg int_tcwl_even;
reg int_tcwl_odd;
reg [CFG_PORT_WIDTH_TCL-1:0] write_latency;
reg [CFG_PORT_WIDTH_TCL-1:0] read_latency;
wire int_odt_l;
wire int_odt_h;
reg reg_odt_l;
reg reg_odt_h;
reg combi_odt_l;
reg combi_odt_h;
reg [1:0] offset_code;
reg start_odt_write;
reg start_odt_read;
reg [CFG_TCL_PIPE_LENGTH-1:0] do_write_pipe;
reg [CFG_TCL_PIPE_LENGTH-1:0] do_read_pipe;
reg [3:0] doing_write_count;
reg [3:0] doing_read_count;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
regd_output <= 0;
end
else
begin
if (cfg_output_regd)
regd_output <= (CFG_DWIDTH_RATIO / 2);
else
regd_output <= 2'd0;
end
end
always @ (*)
begin
int_tcwl_unreg = cfg_tcl + cfg_add_lat + regd_output - 1'b1;
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
int_tcwl <= 0;
else
int_tcwl <= int_tcwl_unreg;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_tcwl_even <= 1'b0;
int_tcwl_odd <= 1'b0;
end
else
begin
if (int_tcwl % 2 == 0)
begin
int_tcwl_even <= 1'b1;
int_tcwl_odd <= 1'b0;
end
else
begin
int_tcwl_even <= 1'b0;
int_tcwl_odd <= 1'b1;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
write_latency <= 0;
read_latency <= 0;
end
else
begin
write_latency <= (int_tcwl - 4) / (CFG_DWIDTH_RATIO / 2);
read_latency <= (int_tcwl - 3) / (CFG_DWIDTH_RATIO / 2);
end
end
//=================================================================================================//
// Delay ODT signal to match READ DQ/DQS //
//=================================================================================================//
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
do_read_pipe <= 0;
else
if (bg_do_read)
do_read_pipe <= {do_read_pipe[CFG_TCL_PIPE_LENGTH-2:0],bg_do_read};
else
do_read_pipe <= {do_read_pipe[CFG_TCL_PIPE_LENGTH-2:0],1'b0};
end
always @(*)
begin
if (int_tcwl < 3)
start_odt_read = bg_do_read;
else
start_odt_read = do_read_pipe[read_latency];
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin doing_read_count <= 0; end
else
begin
if (start_odt_read)
begin
if ((cfg_burst_length / CFG_DWIDTH_RATIO) > 1)
doing_read_count <= 1;
else
doing_read_count <= 0;
end
else if (doing_read_count >= ((cfg_burst_length / CFG_DWIDTH_RATIO) - 1))
begin
doing_read_count <= 0;
end
else if (doing_read_count > 0)
begin
doing_read_count <= doing_read_count + 1'b1;
end
end
end
//=================================================================================================//
// Delay ODT signal to match WRITE DQ/DQS //
//=================================================================================================//
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
do_write_pipe <= 0;
else
if (bg_do_write)
do_write_pipe <= {do_write_pipe[CFG_TCL_PIPE_LENGTH-2:0],bg_do_write};
else
do_write_pipe <= {do_write_pipe[CFG_TCL_PIPE_LENGTH-2:0],1'b0};
end
always @(*)
begin
if (int_tcwl < 4)
start_odt_write = bg_do_write;
else
start_odt_write = do_write_pipe[write_latency];
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
doing_write_count <= 0;
else
if (start_odt_write)
begin
if ((cfg_burst_length / CFG_DWIDTH_RATIO) > 1)
doing_write_count <= 1;
else
doing_write_count <= 0;
end
else if (doing_write_count >= ((cfg_burst_length / CFG_DWIDTH_RATIO) - 1))
begin
doing_write_count <= 0;
end
else if (doing_write_count > 0)
begin
doing_write_count <= doing_write_count + 1'b1;
end
end
//=================================================================================================//
// ODT signal generation block //
//=================================================================================================//
always @ (*)
begin
if (CFG_DWIDTH_RATIO == 2) // full rate
begin
if (start_odt_write || start_odt_read)
begin
combi_odt_h = 1'b1;
combi_odt_l = 1'b1;
end
else
begin
combi_odt_h = 1'b0;
combi_odt_l = 1'b0;
end
end
else // half and quarter rate
begin
if (int_tcwl_even)
begin
if (start_odt_write)
begin
combi_odt_h = 1'b1;
combi_odt_l = 1'b1;
end
else if (start_odt_read)
begin
combi_odt_h = 1'b1;
combi_odt_l = 1'b0;
end
else
begin
combi_odt_h = 1'b0;
combi_odt_l = 1'b0;
end
end
else
begin
if (start_odt_write)
begin
combi_odt_h = 1'b1;
combi_odt_l = 1'b0;
end
else if (start_odt_read)
begin
combi_odt_h = 1'b1;
combi_odt_l = 1'b1;
end
else
begin
combi_odt_h = 1'b0;
combi_odt_l = 1'b0;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
reg_odt_h <= 1'b0;
reg_odt_l <= 1'b0;
end
else
begin
if (CFG_DWIDTH_RATIO == 2) // full rate
begin
if (start_odt_write || start_odt_read)
begin
reg_odt_h <= 1'b1;
reg_odt_l <= 1'b1;
end
else if (doing_write_count > 0 || doing_read_count > 0)
begin
reg_odt_h <= 1'b1;
reg_odt_l <= 1'b1;
end
else
begin
reg_odt_h <= 1'b0;
reg_odt_l <= 1'b0;
end
end
else // half and quarter rate
begin
if (start_odt_write)
begin
if ((cfg_burst_length / CFG_DWIDTH_RATIO) > 1)
begin
reg_odt_h <= 1'b1;
reg_odt_l <= 1'b1;
end
else
begin
if (int_tcwl_even)
begin
reg_odt_h <= 1'b0;
reg_odt_l <= 1'b1;
end
else
begin
reg_odt_h <= 1'b1;
reg_odt_l <= 1'b1;
end
end
end
else if (start_odt_read)
begin
if ((cfg_burst_length / CFG_DWIDTH_RATIO) > 1)
begin
reg_odt_h <= 1'b1;
reg_odt_l <= 1'b1;
end
else
begin
if (int_tcwl_odd)
begin
reg_odt_h <= 1'b0;
reg_odt_l <= 1'b1;
end
else
begin
reg_odt_h <= 1'b1;
reg_odt_l <= 1'b1;
end
end
end
else if (doing_write_count > 0)
begin
if (doing_write_count < ((cfg_burst_length / CFG_DWIDTH_RATIO) - 1))
begin
reg_odt_h <= 1'b1;
reg_odt_l <= 1'b1;
end
else
begin
if (int_tcwl_even)
begin
reg_odt_h <= 1'b0;
reg_odt_l <= 1'b1;
end
else
begin
reg_odt_h <= 1'b1;
reg_odt_l <= 1'b1;
end
end
end
else if (doing_read_count > 0)
begin
if (doing_read_count < ((cfg_burst_length / CFG_DWIDTH_RATIO) - 1))
begin
reg_odt_h <= 1'b1;
reg_odt_l <= 1'b1;
end
else
begin
if (int_tcwl_odd)
begin
reg_odt_h <= 1'b0;
reg_odt_l <= 1'b1;
end
else
begin
reg_odt_h <= 1'b1;
reg_odt_l <= 1'b1;
end
end
end
else
begin
reg_odt_h <= 1'b0;
reg_odt_l <= 1'b0;
end
end
end
end
generate
if (CFG_DWIDTH_RATIO == 2) // full rate
begin
assign int_odt_h = combi_odt_h | reg_odt_h;
assign int_odt_l = combi_odt_h | reg_odt_h;
end
else if (CFG_DWIDTH_RATIO == 4) // half rate
begin
assign int_odt_h = combi_odt_h | reg_odt_h;
assign int_odt_l = combi_odt_l | reg_odt_l;
end
else if (CFG_DWIDTH_RATIO == 8) // quarter rate
begin
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:38:56 06/14/2016
// Design Name:
// Module Name: LZD_16bit
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module LZD_16bit( in, out, valid
);
input [15:0]in;
output reg [3:0]out;
output reg valid;
wire v1,v2;
wire [2:0]l1, l2;
initial
begin
out<=4'b0000;
valid<=0;
end
LZD_8bit d5( .in(in[7:0]), .out(l1), .valid(v1));
LZD_8bit d6( .in(in[15:8]), .out(l2), .valid(v2));
always@(in,v1,v2,l1,l2)
begin
if(v2==0&&v1==1)
begin
out<={{~v2},{l1}} ;
end
/*
here l1, l2 are 3 bits each and v1,v2 are 1bit
when v2=0
eg- 0000_0000_0010_0100
v2=0,l2=3'b000, v1=1, l1=3'b010
out= {{1},{010}}= {1010}=10 there are 10 leading zeros in 0000_0000_0010_0100
*/
else if( v2==0&&v1==0)
begin
out<=0;
end
else
begin
out<={{~v2},{l2}};
end
/*eg- 0000_0100_0010_0100
v2=0,l2=3'b101, v1=1, l1=3'b010
out= {{1},{101}}= {0101}=5 there are 5 leading zeros in 0000_0100_0010_0100
*/
valid<= v1|v2 ; /* valid = in[15]|in[14]|in[13]|in[12]|in[11]|in[10]|in[9]|in[8]
|in[7]|in[6]|in[5]|in[4]|in[3]|in[2]|in[1]|in[0]*/
end
endmodule
|
// megafunction wizard: %ALTFP_SQRT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altfp_sqrt
// ============================================================
// File Name: fp_sqrt.v
// Megafunction Name(s):
// altfp_sqrt
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.1.0 Build 186 12/03/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
//altfp_sqrt CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone V" PIPELINE=28 ROUNDING="TO_NEAREST" WIDTH_EXP=8 WIDTH_MAN=23 clock data result
//VERSION_BEGIN 14.1 cbx_altfp_sqrt 2014:12:03:18:16:05:SJ cbx_cycloneii 2014:12:03:18:16:05:SJ cbx_lpm_add_sub 2014:12:03:18:16:05:SJ cbx_mgl 2014:12:03:20:51:57:SJ cbx_stratix 2014:12:03:18:16:05:SJ cbx_stratixii 2014:12:03:18:16:05:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//alt_sqrt_block CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone V" PIPELINE=28 WIDTH_SQRT=25 aclr clken clock rad root_result
//VERSION_BEGIN 14.1 cbx_altfp_sqrt 2014:12:03:18:16:05:SJ cbx_cycloneii 2014:12:03:18:16:05:SJ cbx_lpm_add_sub 2014:12:03:18:16:05:SJ cbx_mgl 2014:12:03:20:51:57:SJ cbx_stratix 2014:12:03:18:16:05:SJ cbx_stratixii 2014:12:03:18:16:05:SJ VERSION_END
//synthesis_resources = lpm_add_sub 25 reg 1034
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fp_sqrt_alt_sqrt_block_rcb
(
aclr,
clken,
clock,
rad,
root_result) ;
input aclr;
input clken;
input clock;
input [25:0] rad;
output [24:0] root_result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [23:0] q_ff0c;
reg [23:0] q_ff10c;
reg [23:0] q_ff11c;
reg [23:0] q_ff12c;
reg [23:0] q_ff13c;
reg [23:0] q_ff14c;
reg [23:0] q_ff15c;
reg [23:0] q_ff16c;
reg [23:0] q_ff17c;
reg [23:0] q_ff18c;
reg [23:0] q_ff19c;
reg [23:0] q_ff1c;
reg [23:0] q_ff20c;
reg [23:0] q_ff21c;
reg [23:0] q_ff22c;
reg [23:0] q_ff23c;
reg [23:0] q_ff2c;
reg [23:0] q_ff3c;
reg [23:0] q_ff4c;
reg [23:0] q_ff5c;
reg [23:0] q_ff6c;
reg [23:0] q_ff7c;
reg [23:0] q_ff8c;
reg [23:0] q_ff9c;
reg [25:0] rad_ff0c;
reg [15:0] rad_ff10c;
reg [14:0] rad_ff11c;
reg [13:0] rad_ff12c;
reg [12:0] rad_ff13c;
reg [13:0] rad_ff14c;
reg [14:0] rad_ff15c;
reg [15:0] rad_ff16c;
reg [16:0] rad_ff17c;
reg [17:0] rad_ff18c;
reg [18:0] rad_ff19c;
reg [24:0] rad_ff1c;
reg [19:0] rad_ff20c;
reg [20:0] rad_ff21c;
reg [21:0] rad_ff22c;
reg [22:0] rad_ff23c;
reg [23:0] rad_ff2c;
reg [22:0] rad_ff3c;
reg [21:0] rad_ff4c;
reg [20:0] rad_ff5c;
reg [19:0] rad_ff6c;
reg [18:0] rad_ff7c;
reg [17:0] rad_ff8c;
reg [16:0] rad_ff9c;
wire [8:0] wire_add_sub10_result;
wire [9:0] wire_add_sub11_result;
wire [10:0] wire_add_sub12_result;
wire [11:0] wire_add_sub13_result;
wire [12:0] wire_add_sub14_result;
wire [13:0] wire_add_sub15_result;
wire [13:0] wire_add_sub16_result;
wire [12:0] wire_add_sub17_result;
wire [13:0] wire_add_sub18_result;
wire [14:0] wire_add_sub19_result;
wire [15:0] wire_add_sub20_result;
wire [16:0] wire_add_sub21_result;
wire [17:0] wire_add_sub22_result;
wire [18:0] wire_add_sub23_result;
wire [19:0] wire_add_sub24_result;
wire [20:0] wire_add_sub25_result;
wire [21:0] wire_add_sub26_result;
wire [22:0] wire_add_sub27_result;
wire [23:0] wire_add_sub28_result;
wire [2:0] wire_add_sub4_result;
wire [3:0] wire_add_sub5_result;
wire [4:0] wire_add_sub6_result;
wire [5:0] wire_add_sub7_result;
wire [6:0] wire_add_sub8_result;
wire [7:0] wire_add_sub9_result;
wire [26:0] addnode_w0c;
wire [26:0] addnode_w10c;
wire [26:0] addnode_w11c;
wire [26:0] addnode_w12c;
wire [26:0] addnode_w13c;
wire [26:0] addnode_w14c;
wire [26:0] addnode_w15c;
wire [26:0] addnode_w16c;
wire [26:0] addnode_w17c;
wire [26:0] addnode_w18c;
wire [26:0] addnode_w19c;
wire [26:0] addnode_w1c;
wire [26:0] addnode_w20c;
wire [26:0] addnode_w21c;
wire [26:0] addnode_w22c;
wire [26:0] addnode_w23c;
wire [26:0] addnode_w24c;
wire [26:0] addnode_w2c;
wire [26:0] addnode_w3c;
wire [26:0] addnode_w4c;
wire [26:0] addnode_w5c;
wire [26:0] addnode_w6c;
wire [26:0] addnode_w7c;
wire [26:0] addnode_w8c;
wire [26:0] addnode_w9c;
wire [2:0] qlevel_w0c;
wire [12:0] qlevel_w10c;
wire [13:0] qlevel_w11c;
wire [14:0] qlevel_w12c;
wire [15:0] qlevel_w13c;
wire [16:0] qlevel_w14c;
wire [17:0] qlevel_w15c;
wire [18:0] qlevel_w16c;
wire [19:0] qlevel_w17c;
wire [20:0] qlevel_w18c;
wire [21:0] qlevel_w19c;
wire [3:0] qlevel_w1c;
wire [22:0] qlevel_w20c;
wire [23:0] qlevel_w21c;
wire [24:0] qlevel_w22c;
wire [25:0] qlevel_w23c;
wire [26:0] qlevel_w24c;
wire [4:0] qlevel_w2c;
wire [5:0] qlevel_w3c;
wire [6:0] qlevel_w4c;
wire [7:0] qlevel_w5c;
wire [8:0] qlevel_w6c;
wire [9:0] qlevel_w7c;
wire [10:0] qlevel_w8c;
wire [11:0] qlevel_w9c;
wire [26:0] slevel_w0c;
wire [26:0] slevel_w10c;
wire [26:0] slevel_w11c;
wire [26:0] slevel_w12c;
wire [26:0] slevel_w13c;
wire [26:0] slevel_w14c;
wire [26:0] slevel_w15c;
wire [26:0] slevel_w16c;
wire [26:0] slevel_w17c;
wire [26:0] slevel_w18c;
wire [26:0] slevel_w19c;
wire [26:0] slevel_w1c;
wire [26:0] slevel_w20c;
wire [26:0] slevel_w21c;
wire [26:0] slevel_w22c;
wire [26:0] slevel_w23c;
wire [26:0] slevel_w24c;
wire [26:0] slevel_w2c;
wire [26:0] slevel_w3c;
wire [26:0] slevel_w4c;
wire [26:0] slevel_w5c;
wire [26:0] slevel_w6c;
wire [26:0] slevel_w7c;
wire [26:0] slevel_w8c;
wire [26:0] slevel_w9c;
// synopsys translate_off
initial
q_ff0c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff0c <= 24'b0;
else if (clken == 1'b1) q_ff0c <= {q_ff0c[22:0], (~ addnode_w24c[26])};
// synopsys translate_off
initial
q_ff10c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff10c <= 24'b0;
else if (clken == 1'b1) q_ff10c <= {q_ff10c[22:0], (~ addnode_w14c[26])};
// synopsys translate_off
initial
q_ff11c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff11c <= 24'b0;
else if (clken == 1'b1) q_ff11c <= {q_ff11c[22:0], (~ addnode_w13c[26])};
// synopsys translate_off
initial
q_ff12c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff12c <= 24'b0;
else if (clken == 1'b1) q_ff12c <= {q_ff12c[22:0], (~ addnode_w12c[26])};
// synopsys translate_off
initial
q_ff13c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff13c <= 24'b0;
else if (clken == 1'b1) q_ff13c <= {q_ff13c[22:0], (~ addnode_w11c[26])};
// synopsys translate_off
initial
q_ff14c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff14c <= 24'b0;
else if (clken == 1'b1) q_ff14c <= {q_ff14c[22:0], (~ addnode_w10c[26])};
// synopsys translate_off
initial
q_ff15c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff15c <= 24'b0;
else if (clken == 1'b1) q_ff15c <= {q_ff15c[22:0], (~ addnode_w9c[26])};
// synopsys translate_off
initial
q_ff16c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff16c <= 24'b0;
else if (clken == 1'b1) q_ff16c <= {q_ff16c[22:0], (~ addnode_w8c[26])};
// synopsys translate_off
initial
q_ff17c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff17c <= 24'b0;
else if (clken == 1'b1) q_ff17c <= {q_ff17c[22:0], (~ addnode_w7c[26])};
// synopsys translate_off
initial
q_ff18c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff18c <= 24'b0;
else if (clken == 1'b1) q_ff18c <= {q_ff18c[22:0], (~ addnode_w6c[26])};
// synopsys translate_off
initial
q_ff19c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff19c <= 24'b0;
else if (clken == 1'b1) q_ff19c <= {q_ff19c[22:0], (~ addnode_w5c[26])};
// synopsys translate_off
initial
q_ff1c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff1c <= 24'b0;
else if (clken == 1'b1) q_ff1c <= {q_ff1c[22:0], (~ addnode_w23c[26])};
// synopsys translate_off
initial
q_ff20c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff20c <= 24'b0;
else if (clken == 1'b1) q_ff20c <= {q_ff20c[22:0], (~ addnode_w4c[26])};
// synopsys translate_off
initial
q_ff21c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff21c <= 24'b0;
else if (clken == 1'b1) q_ff21c <= {q_ff21c[22:0], (~ addnode_w3c[26])};
// synopsys translate_off
initial
q_ff22c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff22c <= 24'b0;
else if (clken == 1'b1) q_ff22c <= {q_ff22c[22:0], (~ addnode_w2c[26])};
// synopsys translate_off
initial
q_ff23c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff23c <= 24'b0;
else if (clken == 1'b1) q_ff23c <= {q_ff23c[22:0], (~ addnode_w1c[26])};
// synopsys translate_off
initial
q_ff2c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff2c <= 24'b0;
else if (clken == 1'b1) q_ff2c <= {q_ff2c[22:0], (~ addnode_w22c[26])};
// synopsys translate_off
initial
q_ff3c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff3c <= 24'b0;
else if (clken == 1'b1) q_ff3c <= {q_ff3c[22:0], (~ addnode_w21c[26])};
// synopsys translate_off
initial
q_ff4c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff4c <= 24'b0;
else if (clken == 1'b1) q_ff4c <= {q_ff4c[22:0], (~ addnode_w20c[26])};
// synopsys translate_off
initial
q_ff5c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff5c <= 24'b0;
else if (clken == 1'b1) q_ff5c <= {q_ff5c[22:0], (~ addnode_w19c[26])};
// synopsys translate_off
initial
q_ff6c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff6c <= 24'b0;
else if (clken == 1'b1) q_ff6c <= {q_ff6c[22:0], (~ addnode_w18c[26])};
// synopsys translate_off
initial
q_ff7c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff7c <= 24'b0;
else if (clken == 1'b1) q_ff7c <= {q_ff7c[22:0], (~ addnode_w17c[26])};
// synopsys translate_off
initial
q_ff8c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff8c <= 24'b0;
else if (clken == 1'b1) q_ff8c <= {q_ff8c[22:0], (~ addnode_w16c[26])};
// synopsys translate_off
initial
q_ff9c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff9c <= 24'b0;
else if (clken == 1'b1) q_ff9c <= {q_ff9c[22:0], (~ addnode_w15c[26])};
// synopsys translate_off
initial
rad_ff0c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff0c <= 26'b0;
else if (clken == 1'b1) rad_ff0c <= addnode_w0c[26:1];
// synopsys translate_off
initial
rad_ff10c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff10c <= 16'b0;
else if (clken == 1'b1) rad_ff10c <= addnode_w10c[26:11];
// synopsys translate_off
initial
rad_ff11c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff11c <= 15'b0;
else if (clken == 1'b1) rad_ff11c <= addnode_w11c[26:12];
// synopsys translate_off
initial
rad_ff12c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff12c <= 14'b0;
else if (clken == 1'b1) rad_ff12c <= addnode_w12c[26:13];
// synopsys translate_off
initial
rad_ff13c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff13c <= 13'b0;
else if (clken == 1'b1) rad_ff13c <= addnode_w13c[26:14];
// synopsys translate_off
initial
rad_ff14c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff14c <= 14'b0;
else if (clken == 1'b1) rad_ff14c <= addnode_w14c[26:13];
// synopsys translate_off
initial
rad_ff15c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff15c <= 15'b0;
else if (clken == 1'b1) rad_ff15c <= addnode_w15c[26:12];
// synopsys translate_off
initial
rad_ff16c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff16c <= 16'b0;
else if (clken == 1'b1) rad_ff16c <= addnode_w16c[26:11];
// synopsys translate_off
initial
rad_ff17c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff17c <= 17'b0;
else if (clken == 1'b1) rad_ff17c <= addnode_w17c[26:10];
// synopsys translate_off
initial
rad_ff18c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff18c <= 18'b0;
else if (clken == 1'b1) rad_ff18c <= addnode_w18c[26:9];
// synopsys translate_off
initial
rad_ff19c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff19c <= 19'b0;
else if (clken == 1'b1) rad_ff19c <= addnode_w19c[26:8];
// synopsys translate_off
initial
rad_ff1c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff1c <= 25'b0;
else if (clken == 1'b1) rad_ff1c <= addnode_w1c[26:2];
// synopsys translate_off
initial
rad_ff20c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff20c <= 20'b0;
else if (clken == 1'b1) rad_ff20c <= addnode_w20c[26:7];
// synopsys translate_off
initial
rad_ff21c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff21c <= 21'b0;
else if (clken == 1'b1) rad_ff21c <= addnode_w21c[26:6];
// synopsys translate_off
initial
rad_ff22c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff22c <= 22'b0;
else if (clken == 1'b1) rad_ff22c <= addnode_w22c[26:5];
// synopsys translate_off
initial
rad_ff23c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff23c <= 23'b0;
else if (clken == 1'b1) rad_ff23c <= addnode_w23c[26:4];
// synopsys translate_off
initial
rad_ff2c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff2c <= 24'b0;
else if (clken == 1'b1) rad_ff2c <= addnode_w2c[26:3];
// synopsys translate_off
initial
rad_ff3c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff3c <= 23'b0;
else if (clken == 1'b1) rad_ff3c <= addnode_w3c[26:4];
// synopsys translate_off
initial
rad_ff4c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff4c <= 22'b0;
else if (clken == 1'b1) rad_ff4c <= addnode_w4c[26:5];
// synopsys translate_off
initial
rad_ff5c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff5c <= 21'b0;
else if (clken == 1'b1) rad_ff5c <= addnode_w5c[26:6];
// synopsys translate_off
initial
rad_ff6c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff6c <= 20'b0;
else if (clken == 1'b1) rad_ff6c <= addnode_w6c[26:7];
// synopsys translate_off
initial
rad_ff7c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff7c <= 19'b0;
else if (clken == 1'b1) rad_ff7c <= addnode_w7c[26:8];
// synopsys translate_off
initial
rad_ff8c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff8c <= 18'b0;
else if (clken == 1'b1) rad_ff8c <= addnode_w8c[26:9];
// synopsys translate_off
initial
rad_ff9c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff9c <= 17'b0;
else if (clken == 1'b1) rad_ff9c <= addnode_w9c[26:10];
lpm_add_sub add_sub10
(
.cout(),
.dataa({slevel_w6c[26:18]}),
.datab({(({7{(~ rad_ff5c[20])}} & (~ qlevel_w6c[8:2])) | ({7{rad_ff5c[20]}} & qlevel_w6c[8:2])), qlevel_w6c[1:0]}),
.overflow(),
.result(wire_add_sub10_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub10.lpm_direction = "ADD",
add_sub10.lpm_pipeline = 0,
add_sub10.lpm_width = 9,
add_sub10.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub11
(
.cout(),
.dataa({slevel_w7c[26:17]}),
.datab({(({8{(~ rad_ff6c[19])}} & (~ qlevel_w7c[9:2])) | ({8{rad_ff6c[19]}} & qlevel_w7c[9:2])), qlevel_w7c[1:0]}),
.overflow(),
.result(wire_add_sub11_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub11.lpm_direction = "ADD",
add_sub11.lpm_pipeline = 0,
add_sub11.lpm_width = 10,
add_sub11.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub12
(
.cout(),
.dataa({slevel_w8c[26:16]}),
.datab({(({9{(~ rad_ff7c[18])}} & (~ qlevel_w8c[10:2])) | ({9{rad_ff7c[18]}} & qlevel_w8c[10:2])), qlevel_w8c[1:0]}),
.overflow(),
.result(wire_add_sub12_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub12.lpm_direction = "ADD",
add_sub12.lpm_pipeline = 0,
add_sub12.lpm_width = 11,
add_sub12.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub13
(
.cout(),
.dataa({slevel_w9c[26:15]}),
.datab({(({10{(~ rad_ff8c[17])}} & (~ qlevel_w9c[11:2])) | ({10{rad_ff8c[17]}} & qlevel_w9c[11:2])), qlevel_w9c[1:0]}),
.overflow(),
.result(wire_add_sub13_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub13.lpm_direction = "ADD",
add_sub13.lpm_pipeline = 0,
add_sub13.lpm_width = 12,
add_sub13.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub14
(
.cout(),
.dataa({slevel_w10c[26:14]}),
.datab({(({11{(~ rad_ff9c[16])}} & (~ qlevel_w10c[12:2])) | ({11{rad_ff9c[16]}} & qlevel_w10c[12:2])), qlevel_w10c[1:0]}),
.overflow(),
.result(wire_add_sub14_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub14.lpm_direction = "ADD",
add_sub14.lpm_pipeline = 0,
add_sub14.lpm_width = 13,
add_sub14.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub15
(
.cout(),
.dataa({slevel_w11c[26:13]}),
.datab({(({12{(~ rad_ff10c[15])}} & (~ qlevel_w11c[13:2])) | ({12{rad_ff10c[15]}} & qlevel_w11c[13:2])), qlevel_w11c[1:0]}),
.overflow(),
.result(wire_add_sub15_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub15.lpm_direction = "ADD",
add_sub15.lpm_pipeline = 0,
add_sub15.lpm_width = 14,
add_sub15.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub16
(
.cout(),
.dataa({slevel_w12c[26:13]}),
.datab({(({13{(~ rad_ff11c[14])}} & (~ qlevel_w12c[14:2])) | ({13{rad_ff11c[14]}} & qlevel_w12c[14:2])), qlevel_w12c[1]}),
.overflow(),
.result(wire_add_sub16_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub16.lpm_direction = "ADD",
add_sub16.lpm_pipeline = 0,
add_sub16.lpm_width = 14,
add_sub16.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub17
(
.cout(),
.dataa({slevel_w13c[26:14]}),
.datab({(({13{(~ rad_ff12c[13])}} & (~ qlevel_w13c[15:3])) | ({13{rad_ff12c[13]}} & qlevel_w13c[15:3]))}),
.overflow(),
.result(wire_add_sub17_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub17.lpm_direction = "ADD",
add_sub17.lpm_pipeline = 0,
add_sub17.lpm_width = 13,
add_sub17.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub18
(
.cout(),
.dataa({slevel_w14c[26:13]}),
.datab({(({14{(~ rad_ff13c[12])}} & (~ qlevel_w14c[16:3])) | ({14{rad_ff13c[12]}} & qlevel_w14c[16:3]))}),
.overflow(),
.result(wire_add_sub18_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub18.lpm_direction = "ADD",
add_sub18.lpm_pipeline = 0,
add_sub18.lpm_width = 14,
add_sub18.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub19
(
.cout(),
.dataa({slevel_w15c[26:12]}),
.datab({(({15{(~ rad_ff14c[13])}} & (~ qlevel_w15c[17:3])) | ({15{rad_ff14c[13]}} & qlevel_w15c[17:3]))}),
.overflow(),
.result(wire_add_sub19_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub19.lpm_direction = "ADD",
add_sub19.lpm_pipeline = 0,
add_sub19.lpm_width = 15,
add_sub19.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub20
(
.cout(),
.dataa({slevel_w16c[26:11]}),
.datab({(({16{(~ rad_ff15c[14])}} & (~ qlevel_w16c[18:3])) | ({16{rad_ff15c[14]}} & qlevel_w16c[18:3]))}),
.overflow(),
.result(wire_add_sub20_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub20.lpm_direction = "ADD",
add_sub20.lpm_pipeline = 0,
add_sub20.lpm_width = 16,
add_sub20.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub21
(
.cout(),
.dataa({slevel_w17c[26:10]}),
.datab({(({17{(~ rad_ff16c[15])}} & (~ qlevel_w17c[19:3])) | ({17{rad_ff16c[15]}} & qlevel_w17c[19:3]))}),
.overflow(),
.result(wire_add_sub21_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub21.lpm_direction = "ADD",
add_sub21.lpm_pipeline = 0,
add_sub21.lpm_width = 17,
add_sub21.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub22
(
.cout(),
.dataa({slevel_w18c[26:9]}),
.datab({(({18{(~ rad_ff17c[16])}} & (~ qlevel_w18c[20:3])) | ({18{rad_ff17c[16]}} & qlevel_w18c[20:3]))}),
.overflow(),
.result(wire_add_sub22_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub22.lpm_direction = "ADD",
add_sub22.lpm_pipeline = 0,
add_sub22.lpm_width = 18,
add_sub22.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub23
(
.cout(),
.dataa({slevel_w19c[26:8]}),
.datab({(({19{(~ rad_ff18c[17])}} & (~ qlevel_w19c[21:3])) | ({19{rad_ff18c[17]}} & qlevel_w19c[21:3]))}),
.overflow(),
.result(wire_add_sub23_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub23.lpm_direction = "ADD",
add_sub23.lpm_pipeline = 0,
add_sub23.lpm_width = 19,
add_sub23.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub24
(
.cout(),
.dataa({slevel_w20c[26:7]}),
.datab({(({20{(~ rad_ff19c[18])}} & (~ qlevel_w20c[22:3])) | ({20{rad_ff19c[18]}} & qlevel_w20c[22:3]))}),
.overflow(),
.result(wire_add_sub24_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub24.lpm_direction = "ADD",
add_sub24.lpm_pipeline = 0,
add_sub24.lpm_width = 20,
add_sub24.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub25
(
.cout(),
.dataa({slevel_w21c[26:6]}),
.datab({(({21{(~ rad_ff20c[19])}} & (~ qlevel_w21c[23:3])) | ({21{rad_ff20c[19]}} & qlevel_w21c[23:3]))}),
.overflow(),
.result(wire_add_sub25_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub25.lpm_direction = "ADD",
add_sub25.lpm_pipeline = 0,
add_sub25.lpm_width = 21,
add_sub25.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub26
(
.cout(),
.dataa({slevel_w22c[26:5]}),
.datab({(({22{(~ rad_ff21c[20])}} & (~ qlevel_w22c[24:3])) | ({22{rad_ff21c[20]}} & qlevel_w22c[24:3]))}),
.overflow(),
.result(wire_add_sub26_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub26.lpm_direction = "ADD",
add_sub26.lpm_pipeline = 0,
add_sub26.lpm_width = 22,
add_sub26.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub27
(
.cout(),
.dataa({slevel_w23c[26:4]}),
.datab({(({23{(~ rad_ff22c[21])}} & (~ qlevel_w23c[25:3])) | ({23{rad_ff22c[21]}} & qlevel_w23c[25:3]))}),
.overflow(),
.result(wire_add_sub27_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub27.lpm_direction = "ADD",
add_sub27.lpm_pipeline = 0,
add_sub27.lpm_width = 23,
add_sub27.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub28
(
.cout(),
.dataa({slevel_w24c[26:3]}),
.datab({qlevel_w24c[26:25], (({22{(~ rad_ff23c[22])}} & (~ qlevel_w24c[24:3])) | ({22{rad_ff23c[22]}} & qlevel_w24c[24:3]))}),
.overflow(),
.result(wire_add_sub28_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub28.lpm_direction = "ADD",
add_sub28.lpm_pipeline = 0,
add_sub28.lpm_width = 24,
add_sub28.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub4
(
.cout(),
.dataa({slevel_w0c[26:24]}),
.datab({qlevel_w0c[2:0]}),
.overflow(),
.result(wire_add_sub4_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub4.lpm_direction = "ADD",
add_sub4.lpm_pipeline = 0,
add_sub4.lpm_width = 3,
add_sub4.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub5
(
.cout(),
.dataa({slevel_w1c[26:23]}),
.datab({qlevel_w1c[3:0]}),
.overflow(),
.result(wire_add_sub5_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub5.lpm_direction = "ADD",
add_sub5.lpm_pipeline = 0,
add_sub5.lpm_width = 4,
add_sub5.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub6
(
.cout(),
.dataa({slevel_w2c[26:22]}),
.datab({(({3{(~ rad_ff1c[24])}} & (~ qlevel_w2c[4:2])) | ({3{rad_ff1c[24]}} & qlevel_w2c[4:2])), qlevel_w2c[1:0]}),
.overflow(),
.result(wire_add_sub6_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub6.lpm_direction = "ADD",
add_sub6.lpm_pipeline = 0,
add_sub6.lpm_width = 5,
add_sub6.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub7
(
.cout(),
.dataa({slevel_w3c[26:21]}),
.datab({(({4{(~ rad_ff2c[23])}} & (~ qlevel_w3c[5:2])) | ({4{rad_ff2c[23]}} & qlevel_w3c[5:2])), qlevel_w3c[1:0]}),
.overflow(),
.result(wire_add_sub7_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub7.lpm_direction = "ADD",
add_sub7.lpm_pipeline = 0,
add_sub7.lpm_width = 6,
add_sub7.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub8
(
.cout(),
.dataa({slevel_w4c[26:20]}),
.datab({(({5{(~ rad_ff3c[22])}} & (~ qlevel_w4c[6:2])) | ({5{rad_ff3c[22]}} & qlevel_w4c[6:2])), qlevel_w4c[1:0]}),
.overflow(),
.result(wire_add_sub8_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub8.lpm_direction = "ADD",
add_sub8.lpm_pipeline = 0,
add_sub8.lpm_width = 7,
add_sub8.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub9
(
.cout(),
.dataa({slevel_w5c[26:19]}),
.datab({(({6{(~ rad_ff4c[21])}} & (~ qlevel_w5c[7:2])) | ({6{rad_ff4c[21]}} & qlevel_w5c[7:2])), qlevel_w5c[1:0]}),
.overflow(),
.result(wire_add_sub9_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub9.lpm_direction = "ADD",
add_sub9.lpm_pipeline = 0,
add_sub9.lpm_width = 8,
add_sub9.lpm_type = "lpm_add_sub";
assign
addnode_w0c = {wire_add_sub4_result[2:0], slevel_w0c[23:0]},
addnode_w10c = {wire_add_sub14_result[12:0], slevel_w10c[13:0]},
addnode_w11c = {wire_add_sub15_result[13:0], slevel_w11c[12:0]},
addnode_w12c = {wire_add_sub16_result[13:0], qlevel_w12c[0], slevel_w12c[11:0]},
addnode_w13c = {wire_add_sub17_result[12:0], 1'b1, qlevel_w13c[1:0], slevel_w13c[10:0]},
addnode_w14c = {wire_add_sub18_result[13:0], 1'b1, qlevel_w14c[1:0], slevel_w14c[9:0]},
addnode_w15c = {wire_add_sub19_result[14:0], 1'b1, qlevel_w15c[1:0], slevel_w15c[8:0]},
addnode_w16c = {wire_add_sub20_result[15:0], 1'b1, qlevel_w16c[1:0], slevel_w16c[7:0]},
addnode_w17c = {wire_add_sub21_result[16:0], 1'b1, qlevel_w17c[1:0], slevel_w17c[6:0]},
addnode_w18c = {wire_add_sub22_result[17:0], 1'b1, qlevel_w18c[1:0], slevel_w18c[5:0]},
addnode_w19c = {wire_add_sub23_result[18:0], 1'b1, qlevel_w19c[1:0], slevel_w19c[4:0]},
addnode_w1c = {wire_add_sub5_result[3:0], slevel_w1c[22:0]},
addnode_w20c = {wire_add_sub24_result[19:0], 1'b1, qlevel_w20c[1:0], slevel_w20c[3:0]},
addnode_w21c = {wire_add_sub25_result[20:0], 1'b1, qlevel_w21c[1:0], slevel_w21c[2:0]},
addnode_w22c = {wire_add_sub26_result[21:0], 1'b1, qlevel_w22c[1:0], slevel_w22c[1:0]},
addnode_w23c = {wire_add_sub27_result[22:0], 1'b1, qlevel_w23c[1:0], slevel_w23c[0]},
addnode_w24c = {wire_add_sub28_result[23:0], 1'b1, qlevel_w24c[1:0]},
addnode_w2c = {wire_add_sub6_result[4:0], slevel_w2c[21:0]},
addnode_w3c = {wire_add_sub7_result[5:0], slevel_w3c[20:0]},
addnode_w4c = {wire_add_sub8_result[6:0], slevel_w4c[19:0]},
addnode_w5c = {wire_add_sub9_result[7:0], slevel_w5c[18:0]},
addnode_w6c = {wire_add_sub10_result[8:0], slevel_w6c[17:0]},
addnode_w7c = {wire_add_sub11_result[9:0], slevel_w7c[16:0]},
addnode_w8c = {wire_add_sub12_result[10:0], slevel_w8c[15:0]},
addnode_w9c = {wire_add_sub13_result[11:0], slevel_w9c[14:0]},
qlevel_w0c = {3{1'b1}},
qlevel_w10c = {1'b0, 1'b1, q_ff23c[8], q_ff22c[7], q_ff21c[6], q_ff20c[5], q_ff19c[4], q_ff18c[3], q_ff17c[2], q_ff16c[1], q_ff15c[0], {2{1'b1}}},
qlevel_w11c = {1'b0, 1'b1, q_ff23c[9], q_ff22c[8], q_ff21c[7], q_ff20c[6], q_ff19c[5], q_ff18c[4], q_ff17c[3], q_ff16c[2], q_ff15c[1], q_ff14c[0], {2{1'b1}}},
qlevel_w12c = {1'b0, 1'b1, q_ff23c[10], q_ff22c[9], q_ff21c[8], q_ff20c[7], q_ff19c[6], q_ff18c[5], q_ff17c[4], q_ff16c[3], q_ff15c[2], q_ff14c[1], q_ff13c[0], {2{1'b1}}},
qlevel_w13c = {1'b0, 1'b1, q_ff23c[11], q_ff22c[10], q_ff21c[9], q_ff20c[8], q_ff19c[7], q_ff18c[6], q_ff17c[5], q_ff16c[4], q_ff15c[3], q_ff14c[2], q_ff13c[1], q_ff12c[0], {2{1'b1}}},
qlevel_w14c = {1'b0, 1'b1, q_ff23c[12], q_ff22c[11], q_ff21c[10], q_ff20c[9], q_ff19c[8], q_ff18c[7], q_ff17c[6], q_ff16c[5], q_ff15c[4], q_ff14c[3], q_ff13c[2], q_ff12c[1], q_ff11c[0], {2{1'b1}}},
qlevel_w15c = {1'b0, 1'b1, q_ff23c[13], q_ff22c[12], q_ff21c[11], q_ff20c[10], q_ff19c[9], q_ff18c[8], q_ff17c[7], q_ff16c[6], q_ff15c[5], q_ff14c[4], q_ff13c[3], q_ff12c[2], q_ff11c[1], q_ff10c[0], {2{1'b1}}},
qlevel_w16c = {1'b0, 1'b1, q_ff23c[14], q_ff22c[13], q_ff21c[12], q_ff20c[11], q_ff19c[10], q_ff18c[9], q_ff17c[8], q_ff16c[7], q_ff15c[6], q_ff14c[5], q_ff13c[4], q_ff12c[3], q_ff11c[2], q_ff10c[1], q_ff9c[0], {2{1'b1}}},
qlevel_w17c = {1'b0, 1'b1, q_ff23c[15], q_ff22c[14], q_ff21c[13], q_ff20c[12], q_ff19c[11], q_ff18c[10], q_ff17c[9], q_ff16c[8], q_ff15c[7], q_ff14c[6], q_ff13c[5], q_ff12c[4], q_ff11c[3], q_ff10c[2], q_ff9c[1], q_ff8c[0], {2{1'b1}}},
qlevel_w18c = {1'b0, 1'b1, q_ff23c[16], q_ff22c[15], q_ff21c[14], q_ff20c[13], q_ff19c[12], q_ff18c[11], q_ff17c[10], q_ff16c[9], q_ff15c[8], q_ff14c[7], q_ff13c[6], q_ff12c[5], q_ff11c[4], q_ff10c[3], q_ff9c[2], q_ff8c[1], q_ff7c[0], {2{1'b1}}},
qlevel_w19c = {1'b0, 1'b1, q_ff23c[17], q_ff22c[16], q_ff21c[15], q_ff20c[14], q_ff19c[13], q_ff18c[12], q_ff17c[11], q_ff16c[10], q_ff15c[9], q_ff14c[8], q_ff13c[7], q_ff12c[6], q_ff11c[5], q_ff10c[4], q_ff9c[3], q_ff8c[2], q_ff7c[1], q_ff6c[0], {2{1'b1}}},
qlevel_w1c = {1'b1, 1'b0, {2{1'b1}}},
qlevel_w20c = {1'b0, 1'b1, q_ff23c[18], q_ff22c[17], q_ff21c[16], q_ff20c[15], q_ff19c[14], q_ff18c[13], q_ff17c[12], q_ff16c[11], q_ff15c[10], q_ff14c[9], q_ff13c[8], q_ff12c[7], q_ff11c[6], q_ff10c[5], q_ff9c[4], q_ff8c[3], q_ff7c[2], q_ff6c[1], q_ff5c[0], {2{1'b1}}},
qlevel_w21c = {1'b0, 1'b1, q_ff23c[19], q_ff22c[18], q_ff21c[17], q_ff20c[16], q_ff19c[15], q_ff18c[14], q_ff17c[13], q_ff16c[12], q_ff15c[11], q_ff14c[10], q_ff13c[9], q_ff12c[8], q_ff11c[7], q_ff10c[6], q_ff9c[5], q_ff8c[4], q_ff7c[3], q_ff6c[2], q_ff5c[1], q_ff4c[0], {2{1'b1}}},
qlevel_w22c = {1'b0, 1'b1, q_ff23c[20], q_ff22c[19], q_ff21c[18], q_ff20c[17], q_ff19c[16], q_ff18c[15], q_ff17c[14], q_ff16c[13], q_ff15c[12], q_ff14c[11], q_ff13c[10], q_ff12c[9], q_ff11c[8], q_ff10c[7], q_ff9c[6], q_ff8c[5], q_ff7c[4], q_ff6c[3], q_ff5c[2], q_ff4c[1], q_ff3c[0], {2{1'b1}}},
qlevel_w23c = {1'b0, 1'b1, q_ff23c[21], q_ff22c[20], q_ff21c[19], q_ff20c[18], q_ff19c[17], q_ff18c[16], q_ff17c[15], q_ff16c[14], q_ff15c[13], q_ff14c[12], q_ff13c[11], q_ff12c[10], q_ff11c[9], q_ff10c[8], q_ff9c[7], q_ff8c[6], q_ff7c[5], q_ff6c[4], q_ff5c[3], q_ff4c[2], q_ff3c[1], q_ff2c[0], {2{1'b1}}},
qlevel_w24c = {(~ rad_ff23c[22]), rad_ff23c[22], q_ff23c[22], q_ff22c[21], q_ff21c[20], q_ff20c[19], q_ff19c[18], q_ff18c[17], q_ff17c[16], q_ff16c[15], q_ff15c[14], q_ff14c[13], q_ff13c[12], q_ff12c[11], q_ff11c[10], q_ff10c[9], q_ff9c[8], q_ff8c[7], q_ff7c[6], q_ff6c[5], q_ff5c[4], q_ff4c[3], q_ff3c[2], q_ff2c[1], q_ff1c[0], {2{1'b1}}},
qlevel_w2c = {1'b0, 1'b1, q_ff23c[0], {2{1'b1}}},
qlevel_w3c = {1'b0, 1'b1, q_ff23c[1], q_ff22c[0], {2{1'b1}}},
qlevel_w4c = {1'b0, 1'b1, q_ff23c[2], q_ff22c[1], q_ff21c[0], {2{1'b1}}},
qlevel_w5c = {1'b0, 1'b1, q_ff23c[3], q_ff22c[2], q_ff21c[1], q_ff20c[0], {2{1'b1}}},
qlevel_w6c = {1'b0, 1'b1, q_ff23c[4], q_ff22c[3], q_ff21c[2], q_ff20c[1], q_ff19c[0], {2{1'b1}}},
qlevel_w7c = {1'b0, 1'b1, q_ff23c[5], q_ff22c[4], q_ff21c[3], q_ff20c[2], q_ff19c[1], q_ff18c[0], {2{1'b1}}},
qlevel_w8c = {1'b0, 1'b1, q_ff23c[6], q_ff22c[5], q_ff21c[4], q_ff20c[3], q_ff19c[2], q_ff18c[1], q_ff17c[0], {2{1'b1}}},
qlevel_w9c = {1'b0, 1'b1, q_ff23c[7], q_ff22c[6], q_ff21c[5], q_ff20c[4], q_ff19c[3], q_ff18c[2], q_ff17c[1], q_ff16c[0], {2{1'b1}}},
root_result = {1'b1, q_ff23c[23], q_ff22c[22], q_ff21c[21], q_ff20c[20], q_ff19c[19], q_ff18c[18], q_ff17c[17], q_ff16c[16], q_ff15c[15], q_ff14c[14], q_ff13c[13], q_ff12c[12], q_ff11c[11], q_ff10c[10], q_ff9c[9], q_ff8c[8], q_ff7c[7], q_ff6c[6], q_ff5c[5], q_ff4c[4], q_ff3c[3], q_ff2c[2], q_ff1c[1], q_ff0c[0]},
slevel_w0c = {1'b0, rad},
slevel_w10c = {rad_ff9c[15:0], {11{1'b0}}},
slevel_w11c = {rad_ff10c[14:0], {12{1'b0}}},
slevel_w12c = {rad_ff11c[13:0], {13{1'b0}}},
slevel_w13c = {rad_ff12c[12:0], 1'b1, {13{1'b0}}},
slevel_w14c = {rad_ff13c[11:0], {3{1'b1}}, {12{1'b0}}},
slevel_w15c = {rad_ff14c[12:0], {3{1'b1}}, {11{1'b0}}},
slevel_w16c = {rad_ff15c[13:0], {3{1'b1}}, {10{1'b0}}},
slevel_w17c = {rad_ff16c[14:0], {3{1'b1}}, {9{1'b0}}},
slevel_w18c = {rad_ff17c[15:0], {3{1'b1}}, {8{1'b0}}},
slevel_w19c = {rad_ff18c[16:0], {3{1'b1}}, {7{1'b0}}},
slevel_w1c = {rad_ff0c[24:0], {2{1'b0}}},
slevel_w20c = {rad_ff19c[17:0], {3{1'b1}}, {6{1'b0}}},
slevel_w21c = {rad_ff20c[18:0], {3{1'b1}}, {5{1'b0}}},
slevel_w22c = {rad_ff21c[19:0], {3{1'b1}}, {4{1'b0}}},
slevel_w23c = {rad_ff22c[20:0], {3{1'b1}}, {3{1'b0}}},
slevel_w24c = {rad_ff23c[21:0], {3{1'b1}}, {2{1'b0}}},
slevel_w2c = {rad_ff1c[23:0], {3{1'b0}}},
slevel_w3c = {rad_ff2c[22:0], {4{1'b0}}},
slevel_w4c = {rad_ff3c[21:0], {5{1'b0}}},
slevel_w5c = {rad_ff4c[20:0], {6{1'b0}}},
slevel_w6c = {rad_ff5c[19:0], {7{1'b0}}},
slevel_w7c = {rad_ff6c[18:0], {8{1'b0}}},
slevel_w8c = {rad_ff7c[17:0], {9{1'b0}}},
slevel_w9c = {rad_ff8c[16:0], {10{1'b0}}};
endmodule //fp_sqrt_alt_sqrt_block_rcb
//synthesis_resources = lpm_add_sub 27 reg 1433
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fp_sqrt_altfp_sqrt_4jc
(
clock,
data,
result) ;
input clock;
input [31:0] data;
output [31:0] result;
wire [24:0] wire_alt_sqrt_block2_root_result;
reg exp_all_one_ff;
reg [7:0] exp_ff1;
reg [7:0] exp_ff20c;
reg [7:0] exp_ff210c;
reg [7:0] exp_ff211c;
reg [7:0] exp_ff212c;
reg [7:0] exp_ff213c;
reg [7:0] exp_ff214c;
reg [7:0] exp_ff215c;
reg [7:0] exp_ff216c;
reg [7:0] exp_ff217c;
reg [7:0] exp_ff218c;
reg [7:0] exp_ff219c;
reg [7:0] exp_ff21c;
reg [7:0] exp_ff220c;
reg [7:0] exp_ff221c;
reg [7:0] exp_ff222c;
reg [7:0] exp_ff223c;
reg [7:0] exp_ff224c;
reg [7:0] exp_ff22c;
reg [7:0] exp_ff23c;
reg [7:0] exp_ff24c;
reg [7:0] exp_ff25c;
reg [7:0] exp_ff26c;
reg [7:0] exp_ff27c;
reg [7:0] exp_ff28c;
reg [7:0] exp_ff29c;
reg [7:0] exp_in_ff;
reg exp_not_zero_ff;
reg [7:0] exp_result_ff;
reg [0:0] infinity_ff0;
reg [0:0] infinity_ff1;
reg [0:0] infinity_ff2;
reg [0:0] infinity_ff3;
reg [0:0] infinity_ff4;
reg [0:0] infinity_ff5;
reg [0:0] infinity_ff6;
reg [0:0] infinity_ff7;
reg [0:0] infinity_ff8;
reg [0:0] infinity_ff9;
reg [0:0] infinity_ff10;
reg [0:0] infinity_ff11;
reg [0:0] infinity_ff12;
reg [0:0] infinity_ff13;
reg [0:0] infinity_ff14;
reg [0:0] infinity_ff15;
reg [0:0] infinity_ff16;
reg [0:0] infinity_ff17;
reg [0:0] infinity_ff18;
reg [0:0] infinity_ff19;
reg [0:0] infinity_ff20;
reg [0:0] infinity_ff21;
reg [0:0] infinity_ff22;
reg [0:0] infinity_ff23;
reg [0:0] infinity_ff24;
reg [22:0] man_in_ff;
reg man_not_zero_ff;
reg [22:0] man_result_ff;
reg [22:0] man_rounding_ff;
reg [0:0] nan_man_ff0;
reg [0:0] nan_man_ff1;
reg [0:0] nan_man_ff2;
reg [0:0] nan_man_ff3;
reg [0:0] nan_man_ff4;
reg [0:0] nan_man_ff5;
reg [0:0] nan_man_ff6;
reg [0:0] nan_man_ff7;
reg [0:0] nan_man_ff8;
reg [0:0] nan_man_ff9;
reg [0:0] nan_man_ff10;
reg [0:0] nan_man_ff11;
reg [0:0] nan_man_ff12;
reg [0:0] nan_man_ff13;
reg [0:0] nan_man_ff14;
reg [0:0] nan_man_ff15;
reg [0:0] nan_man_ff16;
reg [0:0] nan_man_ff17;
reg [0:0] nan_man_ff18;
reg [0:0] nan_man_ff19;
reg [0:0] nan_man_ff20;
reg [0:0] nan_man_ff21;
reg [0:0] nan_man_ff22;
reg [0:0] nan_man_ff23;
reg [0:0] nan_man_ff24;
reg [0:0] sign_node_ff0;
reg [0:0] sign_node_ff1;
reg [0:0] sign_node_ff2;
reg [0:0] sign_node_ff3;
reg [0:0] sign_node_ff4;
reg [0:0] sign_node_ff5;
reg [0:0] sign_node_ff6;
reg [0:0] sign_node_ff7;
reg [0:0] sign_node_ff8;
reg [0:0] sign_node_ff9;
reg [0:0] sign_node_ff10;
reg [0:0] sign_node_ff11;
reg [0:0] sign_node_ff12;
reg [0:0] sign_node_ff13;
reg [0:0] sign_node_ff14;
reg [0:0] sign_node_ff15;
reg [0:0] sign_node_ff16;
reg [0:0] sign_node_ff17;
reg [0:0] sign_node_ff18;
reg [0:0] sign_node_ff19;
reg [0:0] sign_node_ff20;
reg [0:0] sign_node_ff21;
reg [0:0] sign_node_ff22;
reg [0:0] sign_node_ff23;
reg [0:0] sign_node_ff24;
reg [0:0] sign_node_ff25;
reg [0:0] sign_node_ff26;
reg [0:0] sign_node_ff27;
reg [0:0] zero_exp_ff0;
reg [0:0] zero_exp_ff1;
reg [0:0] zero_exp_ff2;
reg [0:0] zero_exp_ff3;
reg [0:0] zero_exp_ff4;
reg [0:0] zero_exp_ff5;
reg [0:0] zero_exp_ff6;
reg [0:0] zero_exp_ff7;
reg [0:0] zero_exp_ff8;
reg [0:0] zero_exp_ff9;
reg [0:0] zero_exp_ff10;
reg [0:0] zero_exp_ff11;
reg [0:0] zero_exp_ff12;
reg [0:0] zero_exp_ff13;
reg [0:0] zero_exp_ff14;
reg [0:0] zero_exp_ff15;
reg [0:0] zero_exp_ff16;
reg [0:0] zero_exp_ff17;
reg [0:0] zero_exp_ff18;
reg [0:0] zero_exp_ff19;
reg [0:0] zero_exp_ff20;
reg [0:0] zero_exp_ff21;
reg [0:0] zero_exp_ff22;
reg [0:0] zero_exp_ff23;
reg [0:0] zero_exp_ff24;
wire [8:0] wire_add_sub1_result;
wire [22:0] wire_add_sub3_result;
wire aclr;
wire [7:0] bias;
wire clk_en;
wire [7:0] exp_all_one_w;
wire [7:0] exp_div_w;
wire [7:0] exp_ff2_w;
wire [7:0] exp_not_zero_w;
wire infinitycondition_w;
wire [22:0] man_not_zero_w;
wire [24:0] man_root_result_w;
wire nancondition_w;
wire preadjust_w;
wire [25:0] radicand_w;
wire roundbit_w;
fp_sqrt_alt_sqrt_block_rcb alt_sqrt_block2
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.rad(radicand_w),
.root_result(wire_alt_sqrt_block2_root_result));
// synopsys translate_off
initial
exp_all_one_ff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_all_one_ff <= 1'b0;
else if (clk_en == 1'b1) exp_all_one_ff <= exp_all_one_w[7];
// synopsys translate_off
initial
exp_ff1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff1 <= 8'b0;
else if (clk_en == 1'b1) exp_ff1 <= exp_div_w;
// synopsys translate_off
initial
exp_ff20c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff20c <= 8'b0;
else if (clk_en == 1'b1) exp_ff20c <= exp_ff1;
// synopsys translate_off
initial
exp_ff210c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff210c <= 8'b0;
else if (clk_en == 1'b1) exp_ff210c <= exp_ff29c;
// synopsys translate_off
initial
exp_ff211c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff211c <= 8'b0;
else if (clk_en == 1'b1) exp_ff211c <= exp_ff210c;
// synopsys translate_off
initial
exp_ff212c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff212c <= 8'b0;
else if (clk_en == 1'b1) exp_ff212c <= exp_ff211c;
// synopsys translate_off
initial
exp_ff213c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff213c <= 8'b0;
else if (clk_en == 1'b1) exp_ff213c <= exp_ff212c;
// synopsys translate_off
initial
exp_ff214c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff214c <= 8'b0;
else if (clk_en == 1'b1) exp_ff214c <= exp_ff213c;
// synopsys translate_off
initial
exp_ff215c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff215c <= 8'b0;
else if (clk_en == 1'b1) exp_ff215c <= exp_ff214c;
// synopsys translate_off
initial
exp_ff216c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff216c <= 8'b0;
else if (clk_en == 1'b1) exp_ff216c <= exp_ff215c;
// synopsys translate_off
initial
exp_ff217c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff217c <= 8'b0;
else if (clk_en == 1'b1) exp_ff217c <= exp_ff216c;
// synopsys translate_off
initial
exp_ff218c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff218c <= 8'b0;
else if (clk_en == 1'b1) exp_ff218c <= exp_ff217c;
// synopsys translate_off
initial
exp_ff219c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff219c <= 8'b0;
else if (clk_en == 1'b1) exp_ff219c <= exp_ff218c;
// synopsys translate_off
initial
exp_ff21c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff21c <= 8'b0;
else if (clk_en == 1'b1) exp_ff21c <= exp_ff20c;
// synopsys translate_off
initial
exp_ff220c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff220c <= 8'b0;
else if (clk_en == 1'b1) exp_ff220c <= exp_ff219c;
// synopsys translate_off
initial
exp_ff221c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff221c <= 8'b0;
else if (clk_en == 1'b1) exp_ff221c <= exp_ff220c;
// synopsys translate_off
initial
exp_ff222c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff222c <= 8'b0;
else if (clk_en == 1'b1) exp_ff222c <= exp_ff221c;
// synopsys translate_off
initial
exp_ff223c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff223c <= 8'b0;
else if (clk_en == 1'b1) exp_ff223c <= exp_ff222c;
// synopsys translate_off
initial
exp_ff224c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff224c <= 8'b0;
else if (clk_en == 1'b1) exp_ff224c <= exp_ff223c;
// synopsys translate_off
initial
exp_ff22c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff22c <= 8'b0;
else if (clk_en == 1'b1) exp_ff22c <= exp_ff21c;
// synopsys translate_off
initial
exp_ff23c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff23c <= 8'b0;
else if (clk_en == 1'b1) exp_ff23c <= exp_ff22c;
// synopsys translate_off
initial
exp_ff24c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff24c <= 8'b0;
else if (clk_en == 1'b1) exp_ff24c <= exp_ff23c;
// synopsys translate_off
initial
exp_ff25c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff25c <= 8'b0;
else if (clk_en == 1'b1) exp_ff25c <= exp_ff24c;
// synopsys translate_off
initial
exp_ff26c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff26c <= 8'b0;
else if (clk_en == 1'b1) exp_ff26c <= exp_ff25c;
// synopsys translate_off
initial
exp_ff27c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff27c <= 8'b0;
else if (clk_en == 1'b1) exp_ff27c <= exp_ff26c;
// synopsys translate_off
initial
exp_ff28c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff28c <= 8'b0;
else if (clk_en == 1'b1) exp_ff28c <= exp_ff27c;
// synopsys translate_off
initial
exp_ff29c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff29c <= 8'b0;
else if (clk_en == 1'b1) exp_ff29c <= exp_ff28c;
// synopsys translate_off
initial
exp_in_ff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_in_ff <= 8'b0;
else if (clk_en == 1'b1) exp_in_ff <= data[30:23];
// synopsys translate_off
initial
exp_not_zero_ff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_not_zero_ff <= 1'b0;
else if (clk_en == 1'b1) exp_not_zero_ff <= exp_not_zero_w[7];
// synopsys translate_off
initial
exp_result_ff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_ff <= 8'b0;
else if (clk_en == 1'b1) exp_result_ff <= (((exp_ff2_w & {8{zero_exp_ff24[0:0]}}) | {8{nan_man_ff24[0:0]}}) | {8{infinity_ff24[0:0]}});
// synopsys translate_off
initial
infinity_ff0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff0 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff0 <= (infinitycondition_w & (~ sign_node_ff1[0:0]));
// synopsys translate_off
initial
infinity_ff1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff1 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff1 <= infinity_ff0[0:0];
// synopsys translate_off
initial
infinity_ff2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff2 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff2 <= infinity_ff1[0:0];
// synopsys translate_off
initial
infinity_ff3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff3 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff3 <= infinity_ff2[0:0];
// synopsys translate_off
initial
infinity_ff4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff4 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff4 <= infinity_ff3[0:0];
// synopsys translate_off
initial
infinity_ff5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff5 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff5 <= infinity_ff4[0:0];
// synopsys translate_off
initial
infinity_ff6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff6 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff6 <= infinity_ff5[0:0];
// synopsys translate_off
initial
infinity_ff7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff7 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff7 <= infinity_ff6[0:0];
// synopsys translate_off
initial
infinity_ff8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff8 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff8 <= infinity_ff7[0:0];
// synopsys translate_off
initial
infinity_ff9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff9 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff9 <= infinity_ff8[0:0];
// synopsys translate_off
initial
infinity_ff10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff10 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff10 <= infinity_ff9[0:0];
// synopsys translate_off
initial
infinity_ff11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff11 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff11 <= infinity_ff10[0:0];
// synopsys translate_off
initial
infinity_ff12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff12 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff12 <= infinity_ff11[0:0];
// synopsys translate_off
initial
infinity_ff13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff13 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff13 <= infinity_ff12[0:0];
// synopsys translate_off
initial
infinity_ff14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff14 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff14 <= infinity_ff13[0:0];
// synopsys translate_off
initial
infinity_ff15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff15 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff15 <= infinity_ff14[0:0];
// synopsys translate_off
initial
infinity_ff16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff16 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff16 <= infinity_ff15[0:0];
// synopsys translate_off
initial
infinity_ff17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff17 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff17 <= infinity_ff16[0:0];
// synopsys translate_off
initial
infinity_ff18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff18 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff18 <= infinity_ff17[0:0];
// synopsys translate_off
initial
infinity_ff19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff19 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff19 <= infinity_ff18[0:0];
// synopsys translate_off
initial
infinity_ff20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff20 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff20 <= infinity_ff19[0:0];
// synopsys translate_off
initial
infinity_ff21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff21 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff21 <= infinity_ff20[0:0];
// synopsys translate_off
initial
infinity_ff22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff22 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff22 <= infinity_ff21[0:0];
// synopsys translate_off
initial
infinity_ff23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff23 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff23 <= infinity_ff22[0:0];
// synopsys translate_off
initial
infinity_ff24 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff24 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff24 <= infinity_ff23[0:0];
// synopsys translate_off
initial
man_in_ff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_in_ff <= 23'b0;
else if (clk_en == 1'b1) man_in_ff <= data[22:0];
// synopsys translate_off
initial
man_not_zero_ff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_not_zero_ff <= 1'b0;
else if (clk_en == 1'b1) man_not_zero_ff <= man_not_zero_w[22];
// synopsys translate_off
initial
man_result_ff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_result_ff <= 23'b0;
else if (clk_en == 1'b1) man_result_ff <= ((man_rounding_ff & {23{zero_exp_ff24[0:0]}}) | {23{nan_man_ff24[0:0]}});
// synopsys translate_off
initial
man_rounding_ff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_rounding_ff <= 23'b0;
else if (clk_en == 1'b1) man_rounding_ff <= wire_add_sub3_result;
// synopsys translate_off
initial
nan_man_ff0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff0 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff0 <= nancondition_w;
// synopsys translate_off
initial
nan_man_ff1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff1 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff1 <= nan_man_ff0[0:0];
// synopsys translate_off
initial
nan_man_ff2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff2 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff2 <= nan_man_ff1[0:0];
// synopsys translate_off
initial
nan_man_ff3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff3 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff3 <= nan_man_ff2[0:0];
// synopsys translate_off
initial
nan_man_ff4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff4 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff4 <= nan_man_ff3[0:0];
// synopsys translate_off
initial
nan_man_ff5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff5 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff5 <= nan_man_ff4[0:0];
// synopsys translate_off
initial
nan_man_ff6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff6 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff6 <= nan_man_ff5[0:0];
// synopsys translate_off
initial
nan_man_ff7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff7 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff7 <= nan_man_ff6[0:0];
// synopsys translate_off
initial
nan_man_ff8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff8 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff8 <= nan_man_ff7[0:0];
// synopsys translate_off
initial
nan_man_ff9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff9 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff9 <= nan_man_ff8[0:0];
// synopsys translate_off
initial
nan_man_ff10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff10 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff10 <= nan_man_ff9[0:0];
// synopsys translate_off
initial
nan_man_ff11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff11 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff11 <= nan_man_ff10[0:0];
// synopsys translate_off
initial
nan_man_ff12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff12 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff12 <= nan_man_ff11[0:0];
// synopsys translate_off
initial
nan_man_ff13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff13 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff13 <= nan_man_ff12[0:0];
// synopsys translate_off
initial
nan_man_ff14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff14 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff14 <= nan_man_ff13[0:0];
// synopsys translate_off
initial
nan_man_ff15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff15 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff15 <= nan_man_ff14[0:0];
// synopsys translate_off
initial
nan_man_ff16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff16 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff16 <= nan_man_ff15[0:0];
// synopsys translate_off
initial
nan_man_ff17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff17 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff17 <= nan_man_ff16[0:0];
// synopsys translate_off
initial
nan_man_ff18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff18 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff18 <= nan_man_ff17[0:0];
// synopsys translate_off
initial
nan_man_ff19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff19 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff19 <= nan_man_ff18[0:0];
// synopsys translate_off
initial
nan_man_ff20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff20 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff20 <= nan_man_ff19[0:0];
// synopsys translate_off
initial
nan_man_ff21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff21 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff21 <= nan_man_ff20[0:0];
// synopsys translate_off
initial
nan_man_ff22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff22 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff22 <= nan_man_ff21[0:0];
// synopsys translate_off
initial
nan_man_ff23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff23 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff23 <= nan_man_ff22[0:0];
// synopsys translate_off
initial
nan_man_ff24 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff24 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff24 <= nan_man_ff23[0:0];
// synopsys translate_off
initial
sign_node_ff0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff0 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff0 <= data[31];
// synopsys translate_off
initial
sign_node_ff1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff1 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff1 <= sign_node_ff0[0:0];
// synopsys translate_off
initial
sign_node_ff2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff2 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff2 <= sign_node_ff1[0:0];
// synopsys translate_off
initial
sign_node_ff3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff3 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff3 <= sign_node_ff2[0:0];
// synopsys translate_off
initial
sign_node_ff4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff4 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff4 <= sign_node_ff3[0:0];
// synopsys translate_off
initial
sign_node_ff5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff5 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff5 <= sign_node_ff4[0:0];
// synopsys translate_off
initial
sign_node_ff6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff6 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff6 <= sign_node_ff5[0:0];
// synopsys translate_off
initial
sign_node_ff7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff7 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff7 <= sign_node_ff6[0:0];
// synopsys translate_off
initial
sign_node_ff8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff8 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff8 <= sign_node_ff7[0:0];
// synopsys translate_off
initial
sign_node_ff9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff9 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff9 <= sign_node_ff8[0:0];
// synopsys translate_off
initial
sign_node_ff10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff10 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff10 <= sign_node_ff9[0:0];
// synopsys translate_off
initial
sign_node_ff11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff11 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff11 <= sign_node_ff10[0:0];
// synopsys translate_off
initial
sign_node_ff12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff12 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff12 <= sign_node_ff11[0:0];
// synopsys translate_off
initial
sign_node_ff13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff13 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff13 <= sign_node_ff12[0:0];
// synopsys translate_off
initial
sign_node_ff14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff14 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff14 <= sign_node_ff13[0:0];
// synopsys translate_off
initial
sign_node_ff15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff15 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff15 <= sign_node_ff14[0:0];
// synopsys translate_off
initial
sign_node_ff16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff16 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff16 <= sign_node_ff15[0:0];
// synopsys translate_off
initial
sign_node_ff17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff17 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff17 <= sign_node_ff16[0:0];
// synopsys translate_off
initial
sign_node_ff18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff18 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff18 <= sign_node_ff17[0:0];
// synopsys translate_off
initial
sign_node_ff19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff19 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff19 <= sign_node_ff18[0:0];
// synopsys translate_off
initial
sign_node_ff20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff20 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff20 <= sign_node_ff19[0:0];
// synopsys translate_off
initial
sign_node_ff21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff21 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff21 <= sign_node_ff20[0:0];
// synopsys translate_off
initial
sign_node_ff22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff22 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff22 <= sign_node_ff21[0:0];
// synopsys translate_off
initial
sign_node_ff23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff23 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff23 <= sign_node_ff22[0:0];
// synopsys translate_off
initial
sign_node_ff24 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff24 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff24 <= sign_node_ff23[0:0];
// synopsys translate_off
initial
sign_node_ff25 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff25 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff25 <= sign_node_ff24[0:0];
// synopsys translate_off
initial
sign_node_ff26 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff26 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff26 <= sign_node_ff25[0:0];
// synopsys translate_off
initial
sign_node_ff27 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff27 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff27 <= sign_node_ff26[0:0];
// synopsys translate_off
initial
zero_exp_ff0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff0 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff0 <= exp_not_zero_ff;
// synopsys translate_off
initial
zero_exp_ff1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff1 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff1 <= zero_exp_ff0[0:0];
// synopsys translate_off
initial
zero_exp_ff2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff2 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff2 <= zero_exp_ff1[0:0];
// synopsys translate_off
initial
zero_exp_ff3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff3 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff3 <= zero_exp_ff2[0:0];
// synopsys translate_off
initial
zero_exp_ff4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff4 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff4 <= zero_exp_ff3[0:0];
// synopsys translate_off
initial
zero_exp_ff5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff5 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff5 <= zero_exp_ff4[0:0];
// synopsys translate_off
initial
zero_exp_ff6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff6 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff6 <= zero_exp_ff5[0:0];
// synopsys translate_off
initial
zero_exp_ff7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff7 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff7 <= zero_exp_ff6[0:0];
// synopsys translate_off
initial
zero_exp_ff8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff8 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff8 <= zero_exp_ff7[0:0];
// synopsys translate_off
initial
zero_exp_ff9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff9 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff9 <= zero_exp_ff8[0:0];
// synopsys translate_off
initial
zero_exp_ff10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff10 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff10 <= zero_exp_ff9[0:0];
// synopsys translate_off
initial
zero_exp_ff11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff11 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff11 <= zero_exp_ff10[0:0];
// synopsys translate_off
initial
zero_exp_ff12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff12 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff12 <= zero_exp_ff11[0:0];
// synopsys translate_off
initial
zero_exp_ff13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff13 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff13 <= zero_exp_ff12[0:0];
// synopsys translate_off
initial
zero_exp_ff14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff14 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff14 <= zero_exp_ff13[0:0];
// synopsys translate_off
initial
zero_exp_ff15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff15 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff15 <= zero_exp_ff14[0:0];
// synopsys translate_off
initial
zero_exp_ff16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff16 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff16 <= zero_exp_ff15[0:0];
// synopsys translate_off
initial
zero_exp_ff17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff17 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff17 <= zero_exp_ff16[0:0];
// synopsys translate_off
initial
zero_exp_ff18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff18 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff18 <= zero_exp_ff17[0:0];
// synopsys translate_off
initial
zero_exp_ff19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff19 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff19 <= zero_exp_ff18[0:0];
// synopsys translate_off
initial
zero_exp_ff20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff20 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff20 <= zero_exp_ff19[0:0];
// synopsys translate_off
initial
zero_exp_ff21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff21 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff21 <= zero_exp_ff20[0:0];
// synopsys translate_off
initial
zero_exp_ff22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff22 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff22 <= zero_exp_ff21[0:0];
// synopsys translate_off
initial
zero_exp_ff23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff23 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff23 <= zero_exp_ff22[0:0];
// synopsys translate_off
initial
zero_exp_ff24 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff24 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff24 <= zero_exp_ff23[0:0];
lpm_add_sub add_sub1
(
.cout(),
.dataa({1'b0, exp_in_ff}),
.datab({1'b0, bias}),
.overflow(),
.result(wire_add_sub1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub1.lpm_direction = "ADD",
add_sub1.lpm_pipeline = 0,
add_sub1.lpm_width = 9,
add_sub1.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub3
(
.cout(),
.dataa(man_root_result_w[23:1]),
.datab({{22{1'b0}}, roundbit_w}),
.overflow(),
.result(wire_add_sub3_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub3.lpm_direction = "ADD",
add_sub3.lpm_pipeline = 0,
add_sub3.lpm_width = 23,
add_sub3.lpm_type = "lpm_add_sub";
assign
aclr = 1'b0,
bias = {1'b0, {7{1'b1}}},
clk_en = 1'b1,
exp_all_one_w = {(exp_in_ff[7] & exp_all_one_w[6]), (exp_in_ff[6] & exp_all_one_w[5]), (exp_in_ff[5] & exp_all_one_w[4]), (exp_in_ff[4] & exp_all_one_w[3]), (exp_in_ff[3] & exp_all_one_w[2]), (exp_in_ff[2] & exp_all_one_w[1]), (exp_in_ff[1] & exp_all_one_w[0]), exp_in_ff[0]},
exp_div_w = {wire_add_sub1_result[8:1]},
exp_ff2_w = exp_ff224c,
exp_not_zero_w = {(exp_in_ff[7] | exp_not_zero_w[6]), (exp_in_ff[6] | exp_not_zero_w[5]), (exp_in_ff[5] | exp_not_zero_w[4]), (exp_in_ff[4] | exp_not_zero_w[3]), (exp_in_ff[3] | exp_not_zero_w[2]), (exp_in_ff[2] | exp_not_zero_w[1]), (exp_in_ff[1] | exp_not_zero_w[0]), exp_in_ff[0]},
infinitycondition_w = ((~ man_not_zero_ff) & exp_all_one_ff),
man_not_zero_w = {(man_in_ff[22] | man_not_zero_w[21]), (man_in_ff[21] | man_not_zero_w[20]), (man_in_ff[20] | man_not_zero_w[19]), (man_in_ff[19] | man_not_zero_w[18]), (man_in_ff[18] | man_not_zero_w[17]), (man_in_ff[17] | man_not_zero_w[16]), (man_in_ff[16] | man_not_zero_w[15]), (man_in_ff[15] | man_not_zero_w[14]), (man_in_ff[14] | man_not_zero_w[13]), (man_in_ff[13] | man_not_zero_w[12]), (man_in_ff[12] | man_not_zero_w[11]), (man_in_ff[11] | man_not_zero_w[10]), (man_in_ff[10] | man_not_zero_w[9]), (man_in_ff[9] | man_not_zero_w[8]), (man_in_ff[8] | man_not_zero_w[7]), (man_in_ff[7] | man_not_zero_w[6]), (man_in_ff[6] | man_not_zero_w[5]), (man_in_ff[5] | man_not_zero_w[4]), (man_in_ff[4] | man_not_zero_w[3]), (man_in_ff[3] | man_not_zero_w[2]), (man_in_ff[2] | man_not_zero_w[1]), (man_in_ff[1] | man_not_zero_w[0]), man_in_ff[0]},
man_root_result_w = wire_alt_sqrt_block2_root_result,
nancondition_w = ((sign_node_ff1[0:0] & exp_not_zero_ff) | (exp_all_one_ff & man_not_zero_ff)),
preadjust_w = exp_in_ff[0],
radicand_w = {(~ preadjust_w), (preadjust_w | (man_in_ff[22] & (~ preadjust_w))), ((man_in_ff[22:1] & {22{preadjust_w}}) | (man_in_ff[21:0] & {22{(~ preadjust_w)}})), (man_in_ff[0] & preadjust_w), 1'b0},
result = {sign_node_ff27[0:0], exp_result_ff, man_result_ff},
roundbit_w = wire_alt_sqrt_block2_root_result[0];
endmodule //fp_sqrt_altfp_sqrt_4jc
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fp_sqrt (
clock,
data,
result);
input clock;
input [31:0] data;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
fp_sqrt_altfp_sqrt_4jc fp_sqrt_altfp_sqrt_4jc_component (
.clock (clock),
.data (data),
.result (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: FPM_FORMAT NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: PIPELINE NUMERIC "28"
// Retrieval info: CONSTANT: ROUNDING STRING "TO_NEAREST"
// Retrieval info: CONSTANT: WIDTH_EXP NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_MAN NUMERIC "23"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL fp_sqrt.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fp_sqrt.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fp_sqrt.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fp_sqrt.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fp_sqrt_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fp_sqrt_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
// (C) 2001-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/14.0/ip/avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_base.v $
// $Revision: #1 $
// $Date: 2014/02/16 $
// $Author: swbranch $
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_pipeline_base (
clk,
reset,
in_ready,
in_valid,
in_data,
out_ready,
out_valid,
out_data
);
parameter SYMBOLS_PER_BEAT = 1;
parameter BITS_PER_SYMBOL = 8;
parameter PIPELINE_READY = 1;
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
input clk;
input reset;
output in_ready;
input in_valid;
input [DATA_WIDTH-1:0] in_data;
input out_ready;
output out_valid;
output [DATA_WIDTH-1:0] out_data;
reg full0;
reg full1;
reg [DATA_WIDTH-1:0] data0;
reg [DATA_WIDTH-1:0] data1;
assign out_valid = full1;
assign out_data = data1;
generate if (PIPELINE_READY == 1)
begin : REGISTERED_READY_PLINE
assign in_ready = !full0;
always @(posedge clk, posedge reset) begin
if (reset) begin
data0 <= {DATA_WIDTH{1'b0}};
data1 <= {DATA_WIDTH{1'b0}};
end else begin
// ----------------------------
// always load the second slot if we can
// ----------------------------
if (~full0)
data0 <= in_data;
// ----------------------------
// first slot is loaded either from the second,
// or with new data
// ----------------------------
if (~full1 || (out_ready && out_valid)) begin
if (full0)
data1 <= data0;
else
data1 <= in_data;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
full0 <= 1'b0;
full1 <= 1'b0;
end else begin
// no data in pipeline
if (~full0 & ~full1) begin
if (in_valid) begin
full1 <= 1'b1;
end
end // ~f1 & ~f0
// one datum in pipeline
if (full1 & ~full0) begin
if (in_valid & ~out_ready) begin
full0 <= 1'b1;
end
// back to empty
if (~in_valid & out_ready) begin
full1 <= 1'b0;
end
end // f1 & ~f0
// two data in pipeline
if (full1 & full0) begin
// go back to one datum state
if (out_ready) begin
full0 <= 1'b0;
end
end // end go back to one datum stage
end
end
end
else
begin : UNREGISTERED_READY_PLINE
// in_ready will be a pass through of the out_ready signal as it is not registered
assign in_ready = (~full1) | out_ready;
always @(posedge clk or posedge reset) begin
if (reset) begin
data1 <= 'b0;
full1 <= 1'b0;
end
else begin
if (in_ready) begin
data1 <= in_data;
full1 <= in_valid;
end
end
end
end
endgenerate
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2006 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc = 0;
reg [63:0] crc;
integer i;
reg [63:0] mem [7:0];
always @ (posedge clk) begin
if (cyc==1) begin
for (i=0; i<8; i=i+1) begin
mem[i] <= 64'h0;
end
end
else begin
mem[0] <= crc;
for (i=1; i<8; i=i+1) begin
mem[i] <= mem[i-1];
end
end
end
wire [63:0] outData = mem[7];
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d crc=%b q=%x\n", $time, cyc, crc, outData);
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc==90) begin
if (outData != 64'h1265e3bddcd9bc27) $stop;
end
else if (cyc==91) begin
if (outData != 64'h24cbc77bb9b3784e) $stop;
end
else if (cyc==92) begin
end
else if (cyc==93) begin
end
else if (cyc==94) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
`timescale 1ns / 1ps
/*
* Simple Brainfuck CPU in Verilog.
* Copyright (C) 2011 Sergey Gridasov <[email protected]>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module TestConsole (
input CLK,
input RESET,
input [7:0] IN,
output [7:0] OUT,
output RDA,
input ACK,
input WR,
output RDY
);
reg [3:0] SELREG;
assign OUT = 8'h41 + SELREG;
assign RDA = 1'b1;
assign RDY = 1'b1;
always @ (posedge CLK)
begin
if(RESET)
SELREG <= 8'h00;
else
begin
if(WR)
$write("%c", IN);
if(ACK)
SELREG <= SELREG + 1;
end
end
endmodule
module CPUTest;
// Inputs
reg CLK;
reg RESET;
wire [7:0] CIN;
wire CRDA;
wire CRDY;
// Outputs
wire [7:0] COUT;
wire CACK;
wire CWR;
TestConsole console (
.CLK(CLK),
.RESET(RESET),
.IN(COUT),
.OUT(CIN),
.RDA(CRDA),
.ACK(CACK),
.WR(CWR),
.RDY(CRDY)
);
// Instantiate the Unit Under Test (UUT)
BrainfuckWrapper #(
.IA_WIDTH(12)
) uut (
.CLK(CLK),
.RESET(RESET),
.CIN(CIN),
.COUT(COUT),
.CRDA(CRDA),
.CACK(CACK),
.CWR(CWR),
.CRDY(CRDY)
);
initial begin
// Initialize Inputs
CLK = 1'b1;
RESET = 1'b1;
// Wait 100 ns for global reset to finish
#100;
RESET = 1'b0;
#100;
end
always
#20 CLK <= ~CLK;
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////
//
// This file is part of Descrypt Ztex Bruteforcer
// Copyright (C) 2014 Alexey Osipov <giftsungiv3n at gmail dot com>
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
////////////////////////////////////////////////////////////////////////
module SP_block_test;
// Inputs
reg [47:0] Din;
// Outputs
wire [31:0] P_S;
// Instantiate the Unit Under Test (UUT)
SP_block uut (
.Din(Din),
.P_S(P_S)
);
initial begin
// Initialize Inputs
Din = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
Din = 48'b011000010001011110111010100001100110010100100111;
#100;
if(!(P_S == 32'b00100011010010101010100110111011)) $finish;
end
endmodule
|
/****************************************
Branch
for MIST32 Processor
Takahiro Ito @cpu_labs
****************************************/
`include "core.h"
`default_nettype none
module execute_branch(
input wire [31:0] iDATA_0,
input wire [31:0] iDATA_1,
input wire [31:0] iPC,
input wire [4:0] iFLAG,
input wire [3:0] iCC,
input wire [4:0] iCMD,
output wire [31:0] oBRANCH_ADDR,
output wire oJUMP_VALID,
output wire oNOT_JUMP_VALID,
output wire oIB_VALID,
output wire oIDTS_VALID,
output wire oHALT_VALID
);
assign oBRANCH_ADDR = func_branch_addr(
iCMD,
iPC,
iDATA_1
);
function [31:0] func_branch_addr;
input [4:0] func_cmd;
input [31:0] func_pc;
input [31:0] func_source1;
begin
case(func_cmd)
`EXE_BRANCH_BUR:
begin
func_branch_addr = func_source1 + func_pc;
end
`EXE_BRANCH_BR:
begin
func_branch_addr = func_source1 + func_pc;
end
`EXE_BRANCH_B:
begin
func_branch_addr = func_source1;
end
`EXE_BRANCH_INTB:
begin
func_branch_addr = 32'h0;
end
`EXE_BRANCH_IDTS:
begin
func_branch_addr = func_pc + 32'h0000004;
end
default:
begin
func_branch_addr = 32'h0;
end
endcase
end
endfunction
assign oJUMP_VALID = (iCMD != `EXE_BRANCH_INTB && iCMD != `EXE_BRANCH_IDTS)? func_ex_branch_check(iCC, iFLAG) : 1'b0;
assign oNOT_JUMP_VALID = (iCMD != `EXE_BRANCH_INTB && iCMD != `EXE_BRANCH_IDTS)? !func_ex_branch_check(iCC, iFLAG) : 1'b0;
assign oIB_VALID = (iCMD == `EXE_BRANCH_INTB)? 1'b1 : 1'b0;
assign oIDTS_VALID = (iCMD == `EXE_BRANCH_IDTS)? 1'b1 : 1'b0;
assign oHALT_VALID = (iCMD == `EXE_BRANCH_HALT)? 1'b1 : 1'b0;
function func_ex_branch_check;
input [3:0] func_ex_branch_check_cc;
input [4:0] func_ex_branch_check_flag;
begin
case(func_ex_branch_check_cc)
`CC_AL : func_ex_branch_check = 1'b1;
`CC_EQ :
begin
if(func_ex_branch_check_flag[`FLAGS_ZF])begin
func_ex_branch_check = 1'b1;
end
else begin
func_ex_branch_check = 1'b0;
end
end
`CC_NEQ :
begin
if(!func_ex_branch_check_flag[`FLAGS_ZF])begin
func_ex_branch_check = 1'b1;
end
else begin
func_ex_branch_check = 1'b0;
end
end
`CC_MI :
begin
func_ex_branch_check = func_ex_branch_check_flag[`FLAGS_SF];
end
`CC_PL :
begin
func_ex_branch_check = !func_ex_branch_check_flag[`FLAGS_SF];
end
`CC_EN :
begin
if(!func_ex_branch_check_flag[`FLAGS_PF])begin
func_ex_branch_check = 1'b1;
end
else begin
func_ex_branch_check = 1'b0;
end
end
`CC_ON :
begin
if(func_ex_branch_check_flag[`FLAGS_PF])begin
func_ex_branch_check = 1'b1;
end
else begin
func_ex_branch_check = 1'b0;
end
end
`CC_OVF :
begin
if(func_ex_branch_check_flag[`FLAGS_OF])begin
func_ex_branch_check = 1'b1;
end
else begin
func_ex_branch_check = 1'b0;
end
end
`CC_UEO :
begin
func_ex_branch_check = func_ex_branch_check_flag[`FLAGS_CF];
end
`CC_UU :
begin
func_ex_branch_check = !func_ex_branch_check_flag[`FLAGS_CF];
end
`CC_UO :
begin
func_ex_branch_check = func_ex_branch_check_flag[`FLAGS_CF] && !func_ex_branch_check_flag[`FLAGS_ZF];
end
`CC_UEU :
begin
func_ex_branch_check = !func_ex_branch_check_flag[`FLAGS_CF] || func_ex_branch_check_flag[`FLAGS_ZF];
end
`CC_SEO :
begin
func_ex_branch_check = (func_ex_branch_check_flag[`FLAGS_SF] && func_ex_branch_check_flag[`FLAGS_OF]) || (!func_ex_branch_check_flag[`FLAGS_SF] && !func_ex_branch_check_flag[`FLAGS_OF]);
end
`CC_SU :
begin
func_ex_branch_check = (func_ex_branch_check_flag[`FLAGS_SF] && !func_ex_branch_check_flag[`FLAGS_OF]) || (!func_ex_branch_check_flag[`FLAGS_SF] && func_ex_branch_check_flag[`FLAGS_OF]);
end
`CC_SO :
begin
func_ex_branch_check = !((func_ex_branch_check_flag[`FLAGS_SF] ^ func_ex_branch_check_flag[`FLAGS_OF]) || func_ex_branch_check_flag[`FLAGS_ZF]);
end
`CC_SEU :
begin
func_ex_branch_check = (func_ex_branch_check_flag[`FLAGS_SF] ^ func_ex_branch_check_flag[`FLAGS_OF]) || func_ex_branch_check_flag[`FLAGS_ZF];
end
default : func_ex_branch_check = 1'b1;
endcase
end
endfunction
endmodule
`default_nettype wire
|
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module hps_sdram_p0_altdqdqs (
core_clock_in,
reset_n_core_clock_in,
fr_clock_in,
hr_clock_in,
write_strobe_clock_in,
write_strobe,
strobe_ena_hr_clock_in,
capture_strobe_tracking,
read_write_data_io,
write_oe_in,
strobe_io,
output_strobe_ena,
strobe_n_io,
oct_ena_in,
read_data_out,
capture_strobe_out,
write_data_in,
extra_write_data_in,
extra_write_data_out,
parallelterminationcontrol_in,
seriesterminationcontrol_in,
config_data_in,
config_update,
config_dqs_ena,
config_io_ena,
config_extra_io_ena,
config_dqs_io_ena,
config_clock_in,
lfifo_rdata_en,
lfifo_rdata_en_full,
lfifo_rd_latency,
lfifo_reset_n,
lfifo_rdata_valid,
vfifo_qvld,
vfifo_inc_wr_ptr,
vfifo_reset_n,
rfifo_reset_n,
dll_delayctrl_in
);
input [7-1:0] dll_delayctrl_in;
input core_clock_in;
input reset_n_core_clock_in;
input fr_clock_in;
input hr_clock_in;
input write_strobe_clock_in;
input [3:0] write_strobe;
input strobe_ena_hr_clock_in;
output capture_strobe_tracking;
inout [8-1:0] read_write_data_io;
input [2*8-1:0] write_oe_in;
inout strobe_io;
input [2-1:0] output_strobe_ena;
inout strobe_n_io;
input [2-1:0] oct_ena_in;
output [2 * 2 * 8-1:0] read_data_out;
output capture_strobe_out;
input [2 * 2 * 8-1:0] write_data_in;
input [2 * 2 * 1-1:0] extra_write_data_in;
output [1-1:0] extra_write_data_out;
input [16-1:0] parallelterminationcontrol_in;
input [16-1:0] seriesterminationcontrol_in;
input config_data_in;
input config_update;
input config_dqs_ena;
input [8-1:0] config_io_ena;
input [1-1:0] config_extra_io_ena;
input config_dqs_io_ena;
input config_clock_in;
input [2-1:0] lfifo_rdata_en;
input [2-1:0] lfifo_rdata_en_full;
input [4:0] lfifo_rd_latency;
input lfifo_reset_n;
output lfifo_rdata_valid;
input [2-1:0] vfifo_qvld;
input [2-1:0] vfifo_inc_wr_ptr;
input vfifo_reset_n;
input rfifo_reset_n;
parameter ALTERA_ALTDQ_DQS2_FAST_SIM_MODEL = "";
altdq_dqs2_acv_connect_to_hard_phy_cyclonev altdq_dqs2_inst (
.core_clock_in( core_clock_in),
.reset_n_core_clock_in (reset_n_core_clock_in),
.fr_clock_in( fr_clock_in),
.hr_clock_in( hr_clock_in),
.write_strobe_clock_in (write_strobe_clock_in),
.write_strobe(write_strobe),
.strobe_ena_hr_clock_in( strobe_ena_hr_clock_in),
.capture_strobe_tracking (capture_strobe_tracking),
.read_write_data_io( read_write_data_io),
.write_oe_in( write_oe_in),
.strobe_io( strobe_io),
.output_strobe_ena( output_strobe_ena),
.strobe_n_io( strobe_n_io),
.oct_ena_in( oct_ena_in),
.read_data_out( read_data_out),
.capture_strobe_out( capture_strobe_out),
.write_data_in( write_data_in),
.extra_write_data_in( extra_write_data_in),
.extra_write_data_out( extra_write_data_out),
.parallelterminationcontrol_in( parallelterminationcontrol_in),
.seriesterminationcontrol_in( seriesterminationcontrol_in),
.config_data_in( config_data_in),
.config_update( config_update),
.config_dqs_ena( config_dqs_ena),
.config_io_ena( config_io_ena),
.config_extra_io_ena( config_extra_io_ena),
.config_dqs_io_ena( config_dqs_io_ena),
.config_clock_in( config_clock_in),
.lfifo_rdata_en(lfifo_rdata_en),
.lfifo_rdata_en_full(lfifo_rdata_en_full),
.lfifo_rd_latency(lfifo_rd_latency),
.lfifo_reset_n(lfifo_reset_n),
.lfifo_rdata_valid(lfifo_rdata_valid),
.vfifo_qvld(vfifo_qvld),
.vfifo_inc_wr_ptr(vfifo_inc_wr_ptr),
.vfifo_reset_n(vfifo_reset_n),
.rfifo_reset_n(rfifo_reset_n),
.dll_delayctrl_in(dll_delayctrl_in)
);
defparam altdq_dqs2_inst.PIN_WIDTH = 8;
defparam altdq_dqs2_inst.PIN_TYPE = "bidir";
defparam altdq_dqs2_inst.USE_INPUT_PHASE_ALIGNMENT = "false";
defparam altdq_dqs2_inst.USE_OUTPUT_PHASE_ALIGNMENT = "false";
defparam altdq_dqs2_inst.USE_LDC_AS_LOW_SKEW_CLOCK = "false";
defparam altdq_dqs2_inst.USE_HALF_RATE_INPUT = "false";
defparam altdq_dqs2_inst.USE_HALF_RATE_OUTPUT = "true";
defparam altdq_dqs2_inst.DIFFERENTIAL_CAPTURE_STROBE = "true";
defparam altdq_dqs2_inst.SEPARATE_CAPTURE_STROBE = "false";
defparam altdq_dqs2_inst.INPUT_FREQ = 400.0;
defparam altdq_dqs2_inst.INPUT_FREQ_PS = "2500 ps";
defparam altdq_dqs2_inst.DELAY_CHAIN_BUFFER_MODE = "high";
defparam altdq_dqs2_inst.DQS_PHASE_SETTING = 0;
defparam altdq_dqs2_inst.DQS_PHASE_SHIFT = 0;
defparam altdq_dqs2_inst.DQS_ENABLE_PHASE_SETTING = 3;
defparam altdq_dqs2_inst.USE_DYNAMIC_CONFIG = "true";
defparam altdq_dqs2_inst.INVERT_CAPTURE_STROBE = "true";
defparam altdq_dqs2_inst.SWAP_CAPTURE_STROBE_POLARITY = "false";
defparam altdq_dqs2_inst.USE_TERMINATION_CONTROL = "true";
defparam altdq_dqs2_inst.USE_DQS_ENABLE = "true";
defparam altdq_dqs2_inst.USE_OUTPUT_STROBE = "true";
defparam altdq_dqs2_inst.USE_OUTPUT_STROBE_RESET = "false";
defparam altdq_dqs2_inst.DIFFERENTIAL_OUTPUT_STROBE = "true";
defparam altdq_dqs2_inst.USE_BIDIR_STROBE = "true";
defparam altdq_dqs2_inst.REVERSE_READ_WORDS = "false";
defparam altdq_dqs2_inst.EXTRA_OUTPUT_WIDTH = 1;
defparam altdq_dqs2_inst.DYNAMIC_MODE = "dynamic";
defparam altdq_dqs2_inst.OCT_SERIES_TERM_CONTROL_WIDTH = 16;
defparam altdq_dqs2_inst.OCT_PARALLEL_TERM_CONTROL_WIDTH = 16;
defparam altdq_dqs2_inst.DLL_WIDTH = 7;
defparam altdq_dqs2_inst.USE_DATA_OE_FOR_OCT = "false";
defparam altdq_dqs2_inst.DQS_ENABLE_WIDTH = 1;
defparam altdq_dqs2_inst.USE_OCT_ENA_IN_FOR_OCT = "true";
defparam altdq_dqs2_inst.PREAMBLE_TYPE = "high";
defparam altdq_dqs2_inst.EMIF_UNALIGNED_PREAMBLE_SUPPORT = "false";
defparam altdq_dqs2_inst.USE_OFFSET_CTRL = "false";
defparam altdq_dqs2_inst.HR_DDIO_OUT_HAS_THREE_REGS = "false";
defparam altdq_dqs2_inst.DQS_ENABLE_PHASECTRL = "true";
defparam altdq_dqs2_inst.USE_2X_FF = "false";
defparam altdq_dqs2_inst.DLL_USE_2X_CLK = "false";
defparam altdq_dqs2_inst.USE_DQS_TRACKING = "true";
defparam altdq_dqs2_inst.USE_HARD_FIFOS = "true";
defparam altdq_dqs2_inst.USE_DQSIN_FOR_VFIFO_READ = "false";
defparam altdq_dqs2_inst.CALIBRATION_SUPPORT = "false";
defparam altdq_dqs2_inst.NATURAL_ALIGNMENT = "true";
defparam altdq_dqs2_inst.SEPERATE_LDC_FOR_WRITE_STROBE = "false";
defparam altdq_dqs2_inst.HHP_HPS = "true";
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFSTP_BLACKBOX_V
`define SKY130_FD_SC_HS__DFSTP_BLACKBOX_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dfstp (
CLK ,
D ,
Q ,
SET_B
);
input CLK ;
input D ;
output Q ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFSTP_BLACKBOX_V
|
module alu_datapath(clk, alu_data, opcode_value, store_a, store_b, start, alu_done, result, overflow_def);
parameter DATA_WIDTH = 8;
input clk;
input alu_data;
input opcode_value;
input store_a;
input store_b;
input start;
output alu_done;
output result;
output overflow_def;
reg overflow_def;
wire clk;
wire [DATA_WIDTH-1:0] alu_data;
wire [1:0] opcode_value;
wire store_a;
wire store_b;
wire start;
reg alu_done;
reg start_def;
reg [DATA_WIDTH-1:0] result;
parameter ON = 1'b1;
parameter OFF = 1'b0;
parameter ADD = 2'b00;
parameter SUB = 2'b01;
parameter PAR = 2'b10;
parameter COMP = 2'b11;
reg [DATA_WIDTH-1:0] buf_a;
reg [DATA_WIDTH-1:0] buf_b;
wire done;
reg [DATA_WIDTH-1:0] add_a;
reg [DATA_WIDTH-1:0] add_b;
wire [DATA_WIDTH-1:0] add_sum;
reg add_carry_in;
wire add_overflow;
reg [DATA_WIDTH-1:0] sub_a;
reg [DATA_WIDTH-1:0] sub_b;
wire [DATA_WIDTH-1:0] sub_diff;
reg sub_borrow_in;
wire sub_borrow_out;
reg [DATA_WIDTH-1:0] par_a;
reg [DATA_WIDTH-1:0] par_b;
wire [DATA_WIDTH-1:0] par_parity;
reg [DATA_WIDTH-1:0] comp_a;
reg [DATA_WIDTH-1:0] comp_b;
wire [DATA_WIDTH-1:0] comp_comp;
always @(posedge clk or store_a or store_b or start)
begin
if(store_a)
begin
buf_a = alu_data;
end
else if(store_b)
begin
buf_b = alu_data;
end
else if(start)
begin
case(opcode_value)
ADD:
begin
add_a = buf_a;
add_b = buf_b;
add_carry_in = 1'b0;
start_def = 1'b1;
end
SUB:
begin
sub_a = buf_a;
sub_b = buf_b;
sub_borrow_in = 1'b0;
start_def = 1'b1;
end
PAR:
begin
par_a = buf_a;
par_b = buf_b;
start_def = 1'b1;
end
COMP:
begin
comp_a = buf_a;
comp_b = buf_b;
start_def = 1'b1;
end
endcase
end
end
always @(posedge clk or done)
begin
if(done)
begin
case(opcode_value)
ADD:
begin
result = add_sum;
overflow_def = add_overflow;
alu_done = ON;
end
SUB:
begin
result = sub_diff;
overflow_def = sub_borrow_out;
alu_done = ON;
end
PAR:
begin
result = par_parity;
alu_done = ON;
overflow_def = OFF;
end
COMP:
begin
result = comp_a ^~ comp_b;
alu_done = ON;
overflow_def = OFF;
end
endcase
end
else
begin
result = 0;
overflow_def = 0;
alu_done = OFF;
end
end
byte_adder #(DATA_WIDTH) adder_ex(
.byte_a(add_a),
.byte_b(add_b),
.byte_carry_in(add_carry_in),
.byte_sum(add_sum),
.byte_overflow(add_overflow),
.start(start_def),
.done(done)
);
byte_subtractor #(DATA_WIDTH) subtractor_ex(
.byte_a(sub_a),
.byte_b(sub_b),
.byte_borrow_in(sub_borrow_in),
.byte_diff(sub_diff),
.byte_borrow_out(sub_borrow_out),
.start(start_def),
.done(done)
);
byte_parity #(DATA_WIDTH) parity_ex(
.byte_a(par_a),
.byte_b(par_b),
.byte_parity(par_parity),
.start(start_def),
.done(done)
);
byte_comp #(DATA_WIDTH) comp_ex(
.byte_a(comp_a),
.byte_b(comp_b),
.byte_comp(comp_comp),
.start(start_def),
.done(done)
);
endmodule
|
// -*- Mode: Verilog -*-
// Filename : wb_daq_slave_registers.v
// Description : WB Data Acquisition Slave Registers
// Author : Philip Tracton
// Created On : Tue Dec 15 20:52:45 2015
// Last Modified By: Philip Tracton
// Last Modified On: Tue Dec 15 20:52:45 2015
// Update Count : 0
// Status : Unknown, Use with caution!
`include "wb_daq_slave_registers_include.vh"
module wb_daq_slave_registers (/*AUTOARG*/
// Outputs
wb_dat_o, wb_ack_o, wb_err_o, wb_rty_o, daq_control_reg,
daq_channel0_address_reg, daq_channel1_address_reg,
daq_channel2_address_reg, daq_channel3_address_reg,
daq_channel0_control_reg, daq_channel1_control_reg,
daq_channel2_control_reg, daq_channel3_control_reg, interrupt,
// Inputs
wb_clk, wb_rst, wb_adr_i, wb_dat_i, wb_sel_i, wb_we_i, wb_cyc_i,
wb_stb_i, wb_cti_i, wb_bte_i, daq_channel0_status_reg,
daq_channel1_status_reg, daq_channel2_status_reg,
daq_channel3_status_reg
) ;
parameter dw = 32;
parameter aw = 8;
parameter DEBUG = 0;
input wb_clk;
input wb_rst;
input [aw-1:0] wb_adr_i;
input [dw-1:0] wb_dat_i;
input [3:0] wb_sel_i;
input wb_we_i;
input wb_cyc_i;
input wb_stb_i;
input [2:0] wb_cti_i;
input [1:0] wb_bte_i;
output reg [dw-1:0] wb_dat_o;
output reg wb_ack_o;
output reg wb_err_o;
output reg wb_rty_o;
output reg [dw-1:0] daq_control_reg;
output reg [dw-1:0] daq_channel0_address_reg;
output reg [dw-1:0] daq_channel1_address_reg;
output reg [dw-1:0] daq_channel2_address_reg;
output reg [dw-1:0] daq_channel3_address_reg;
output reg [dw-1:0] daq_channel0_control_reg;
output reg [dw-1:0] daq_channel1_control_reg;
output reg [dw-1:0] daq_channel2_control_reg;
output reg [dw-1:0] daq_channel3_control_reg;
input wire [dw-1:0] daq_channel0_status_reg;
input wire [dw-1:0] daq_channel1_status_reg;
input wire [dw-1:0] daq_channel2_status_reg;
input wire [dw-1:0] daq_channel3_status_reg;
output reg interrupt = 0;
/* -----\/----- EXCLUDED -----\/-----
assign wb_ack_o = wb_cyc_i & wb_stb_i;
assign wb_err_o = 0;
assign wb_rty_o = 0;
-----/\----- EXCLUDED -----/\----- */
always @(posedge wb_clk)
if (wb_rst) begin
wb_ack_o <= 1'b0;
wb_err_o <= 1'b0;
wb_rty_o <= 1'b0;
end else begin
if (wb_cyc_i & wb_stb_i) begin
wb_ack_o <= 1;
end else begin
wb_ack_o <= 0;
end
end // else: !if(wb_rst)
//
// Register Write Logic
//
always @(posedge wb_clk)
if (wb_rst) begin
daq_control_reg <= 0;
daq_channel0_address_reg <= 0;
daq_channel1_address_reg <= 0;
daq_channel2_address_reg <= 0;
daq_channel3_address_reg <= 0;
daq_channel0_control_reg <= 32'h0000_000C;
daq_channel1_control_reg <= 32'h0000_000C;
daq_channel2_control_reg <= 32'h0000_000C;
daq_channel3_control_reg <= 32'h0000_000C;
end else begin
if (wb_cyc_i & wb_stb_i & wb_we_i) begin
case (wb_adr_i[7:0])
`DAQ_CONTROL_REG_OFFSET:begin
daq_control_reg[7:0] <= wb_sel_i[0] ? wb_dat_i[7:0] : daq_control_reg[7:0];
daq_control_reg[15:8] <= wb_sel_i[1] ? wb_dat_i[15:8] : daq_control_reg[15:8];
daq_control_reg[23:16] <= wb_sel_i[2] ? wb_dat_i[23:16] : daq_control_reg[23:16];
daq_control_reg[31:24] <= wb_sel_i[3] ? wb_dat_i[31:24] : daq_control_reg[31:24];
end
`DAQ_CHANNEL0_ADDRESS_OFFSET: begin
daq_channel0_address_reg[7:0] <= wb_sel_i[0] ? wb_dat_i[7:0] : daq_channel0_address_reg[7:0];
daq_channel0_address_reg[15:8] <= wb_sel_i[1] ? wb_dat_i[15:8] : daq_channel0_address_reg[15:8];
daq_channel0_address_reg[23:16] <= wb_sel_i[2] ? wb_dat_i[23:16] : daq_channel0_address_reg[23:16];
daq_channel0_address_reg[31:24] <= wb_sel_i[3] ? wb_dat_i[31:24] : daq_channel0_address_reg[31:24];
end
`DAQ_CHANNEL0_CONTROL_OFFSET: begin
daq_channel0_control_reg[7:0] <= wb_sel_i[0] ? wb_dat_i[7:0] : daq_channel0_control_reg[7:0];
daq_channel0_control_reg[15:8] <= wb_sel_i[1] ? wb_dat_i[15:8] : daq_channel0_control_reg[15:8];
daq_channel0_control_reg[23:16] <= wb_sel_i[2] ? wb_dat_i[23:16] : daq_channel0_control_reg[23:16];
daq_channel0_control_reg[31:24] <= wb_sel_i[3] ? wb_dat_i[31:24] : daq_channel0_control_reg[31:24];
end
`DAQ_CHANNEL1_ADDRESS_OFFSET: begin
daq_channel1_address_reg[7:0] <= wb_sel_i[0] ? wb_dat_i[7:0] : daq_channel1_address_reg[7:0];
daq_channel1_address_reg[15:8] <= wb_sel_i[1] ? wb_dat_i[15:8] : daq_channel1_address_reg[15:8];
daq_channel1_address_reg[23:16] <= wb_sel_i[2] ? wb_dat_i[23:16] : daq_channel1_address_reg[23:16];
daq_channel1_address_reg[31:24] <= wb_sel_i[3] ? wb_dat_i[31:24] : daq_channel1_address_reg[31:24];
end
`DAQ_CHANNEL1_CONTROL_OFFSET: begin
daq_channel1_control_reg[7:0] <= wb_sel_i[0] ? wb_dat_i[7:0] : daq_channel1_control_reg[7:0];
daq_channel1_control_reg[15:8] <= wb_sel_i[1] ? wb_dat_i[15:8] : daq_channel1_control_reg[15:8];
daq_channel1_control_reg[23:16] <= wb_sel_i[2] ? wb_dat_i[23:16] : daq_channel1_control_reg[23:16];
daq_channel1_control_reg[31:24] <= wb_sel_i[3] ? wb_dat_i[31:24] : daq_channel1_control_reg[31:24];
end
`DAQ_CHANNEL2_ADDRESS_OFFSET: begin
daq_channel2_address_reg[7:0] <= wb_sel_i[0] ? wb_dat_i[7:0] : daq_channel2_address_reg[7:0];
daq_channel2_address_reg[15:8] <= wb_sel_i[1] ? wb_dat_i[15:8] : daq_channel2_address_reg[15:8];
daq_channel2_address_reg[23:16] <= wb_sel_i[2] ? wb_dat_i[23:16] : daq_channel2_address_reg[23:16];
daq_channel2_address_reg[31:24] <= wb_sel_i[3] ? wb_dat_i[31:24] : daq_channel2_address_reg[31:24];
end
`DAQ_CHANNEL2_CONTROL_OFFSET: begin
daq_channel2_control_reg[7:0] <= wb_sel_i[0] ? wb_dat_i[7:0] : daq_channel2_control_reg[7:0];
daq_channel2_control_reg[15:8] <= wb_sel_i[1] ? wb_dat_i[15:8] : daq_channel2_control_reg[15:8];
daq_channel2_control_reg[23:16] <= wb_sel_i[2] ? wb_dat_i[23:16] : daq_channel2_control_reg[23:16];
daq_channel2_control_reg[31:24] <= wb_sel_i[3] ? wb_dat_i[31:24] : daq_channel2_control_reg[31:24];
end
`DAQ_CHANNEL3_ADDRESS_OFFSET: begin
daq_channel3_address_reg[7:0] <= wb_sel_i[0] ? wb_dat_i[7:0] : daq_channel3_address_reg[7:0];
daq_channel3_address_reg[15:8] <= wb_sel_i[1] ? wb_dat_i[15:8] : daq_channel3_address_reg[15:8];
daq_channel3_address_reg[23:16] <= wb_sel_i[2] ? wb_dat_i[23:16] : daq_channel3_address_reg[23:16];
daq_channel3_address_reg[31:24] <= wb_sel_i[3] ? wb_dat_i[31:24] : daq_channel3_address_reg[31:24];
end
`DAQ_CHANNEL3_CONTROL_OFFSET: begin
daq_channel3_control_reg[7:0] <= wb_sel_i[0] ? wb_dat_i[7:0] : daq_channel3_control_reg[7:0];
daq_channel3_control_reg[15:8] <= wb_sel_i[1] ? wb_dat_i[15:8] : daq_channel3_control_reg[15:8];
daq_channel3_control_reg[23:16] <= wb_sel_i[2] ? wb_dat_i[23:16] : daq_channel3_control_reg[23:16];
daq_channel3_control_reg[31:24] <= wb_sel_i[3] ? wb_dat_i[31:24] : daq_channel3_control_reg[31:24];
end
endcase // case (wb_adr_i)
end // if (wb_cyc_i & wb_stb_i & wb_we_i)
end // else: !if(wb_rst)
//
// Register Read Logic
//
always @(posedge wb_clk)
if (wb_rst) begin
wb_dat_o <= 32'b0;
end else begin
if (wb_cyc_i & wb_stb_i & ~wb_we_i) begin
case (wb_adr_i[7:0])
`DAQ_CONTROL_REG_OFFSET : wb_dat_o <= daq_control_reg;
`DAQ_CHANNEL0_ADDRESS_OFFSET : wb_dat_o <= daq_channel0_address_reg;
`DAQ_CHANNEL1_ADDRESS_OFFSET : wb_dat_o <= daq_channel1_address_reg;
`DAQ_CHANNEL2_ADDRESS_OFFSET : wb_dat_o <= daq_channel2_address_reg;
`DAQ_CHANNEL3_ADDRESS_OFFSET : wb_dat_o <= daq_channel3_address_reg;
`DAQ_CHANNEL0_CONTROL_OFFSET : wb_dat_o <= daq_channel0_control_reg;
`DAQ_CHANNEL1_CONTROL_OFFSET : wb_dat_o <= daq_channel1_control_reg;
`DAQ_CHANNEL2_CONTROL_OFFSET : wb_dat_o <= daq_channel2_control_reg;
`DAQ_CHANNEL3_CONTROL_OFFSET : wb_dat_o <= daq_channel3_control_reg;
`DAQ_CHANNEL0_STATUS_OFFSET : wb_dat_o <= daq_channel0_status_reg;
`DAQ_CHANNEL1_STATUS_OFFSET : wb_dat_o <= daq_channel1_status_reg;
`DAQ_CHANNEL2_STATUS_OFFSET : wb_dat_o <= daq_channel2_status_reg;
`DAQ_CHANNEL3_STATUS_OFFSET : wb_dat_o <= daq_channel3_status_reg;
default: wb_dat_o <= 0;
endcase // case (wb_adr_i[3:0])
end
end // else: !if(wb_rst)
endmodule // wb_daq_slave_registers
|
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// synthesis verilog_input_version verilog_2001
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
//-----------------------------------------------------------------------------
// Title : PCI Express Reference Design Example Application
// Project : PCI Express MegaCore function
//-----------------------------------------------------------------------------
// File : altpcierd_cdma_ast_tx_64.v
// Author : Altera Corporation
//-----------------------------------------------------------------------------
// Description :
// This module construct of the Avalon Streaming transmit port for the
// chaining DMA application DATA/Descriptor signals.
//-----------------------------------------------------------------------------
// Copyright (c) 2009 Altera Corporation. All rights reserved. Altera products are
// protected under numerous U.S. and foreign patents, maskwork rights, copyrights and
// other intellectual property laws.
//
// This reference design file, and your use thereof, is subject to and governed by
// the terms and conditions of the applicable Altera Reference Design License Agreement.
// By using this reference design file, you indicate your acceptance of such terms and
// conditions between you and Altera Corporation. In the event that you do not agree with
// such terms and conditions, you may not use the reference design file. Please promptly
// destroy any copies you have made.
//
// This reference design file being provided on an "as-is" basis and as an accommodation
// and therefore all warranties, representations or guarantees of any kind
// (whether express, implied or statutory) including, without limitation, warranties of
// merchantability, non-infringement, or fitness for a particular purpose, are
// specifically disclaimed. By making this reference design file available, Altera
// expressly does not recommend, suggest or require that this reference design file be
// used in combination with any other product not provided by Altera.
//-----------------------------------------------------------------------------
module altpcierd_cdma_ast_tx_64 #(
parameter TX_PIPE_REQ=0,
parameter INTENDED_DEVICE_FAMILY="Cyclone IV GX",
parameter ECRC_FORWARD_GENER=0
)(
input clk_in,
input srst,
input tx_stream_ready0,
output [132:0] txdata,
output tx_stream_valid0,
//transmit section channel 0
input tx_req0 ,
output tx_ack0 ,
input [127:0] tx_desc0,
output reg tx_ws0 ,
input tx_err0 ,
input tx_dv0 ,
input tx_dfr0 ,
input[127:0] tx_data0,
output tx_fifo_empty);
localparam TXFIFO_WIDTH=133;
localparam TXFIFO_DEPTH=32;
localparam TXFIFO_WIDTHU=5;
wire[132:0] txdata_int;
wire[132:0] txdata_ecrc;
wire txfifo_rdreq_int;
wire txfifo_rdreq_ecrc;
reg tx_stream_valid0_int;
wire tx_stream_valid0_ecrc;
wire tx_req_p0;
reg tx_req_next;
wire [127:0] txdata_with_payload;
reg tx_err;
wire tx_sop_0;
wire tx_empty ;
reg tx_sop_1;
wire tx_eop_1;
wire tx_eop_3dwh_1dwp_nonaligned;
reg tx_eop_ndword;
reg [132:0] txfifo_d;
reg txfifo_wrreq;
wire [132:0] txfifo_q;
wire txfifo_empty;
wire txfifo_full;
wire txfifo_rdreq;
wire [TXFIFO_WIDTHU-1:0] txfifo_usedw;
wire txfifo_wrreq_with_payload;
wire ctrltx_nopayload;
reg ctrltx_nopayload_reg;
wire ctrltx_3dw;
reg ctrltx_3dw_reg;
wire ctrltx_qword_aligned;
reg ctrltx_qword_aligned_reg;
wire [9:0] ctrltx_tx_length;
reg [9:0] ctrltx_tx_length_reg;
reg txfifo_almostfull;
reg tx_req_int;
reg ctrltx_4dw_or_aligned_reg;
reg ctrltx_3dw_and_nonaligned_reg;
// ECRC
wire[1:0] user_sop;
wire[1:0] user_eop;
wire[127:0] user_data;
wire user_rd_req;
reg user_valid;
wire [75:0] ecrc_stream_data0_0;
wire [75:0] ecrc_stream_data0_1;
reg[132:0] txfifo_q_pipe;
reg output_stage_full;
wire debug_3dw_aligned_dataless;
wire debug_3dw_nonaligned_dataless;
wire debug_4dw_aligned_dataless;
wire debug_4dw_nonaligned_dataless;
wire debug_3dw_aligned_withdata;
wire debug_3dw_nonaligned_withdata;
wire debug_4dw_aligned_withdata;
wire debug_4dw_nonaligned_withdata;
//---------------------------------
// debug monitors
assign debug_3dw_aligned_dataless = (tx_ack0==1'b1) & (tx_desc0[126:125]==2'b00) & (tx_desc0[34]==1'b0);
assign debug_3dw_nonaligned_dataless = (tx_ack0==1'b1) & (tx_desc0[126:125]==2'b00) & (tx_desc0[34]==1'b1);
assign debug_3dw_aligned_withdata = (tx_ack0==1'b1) & (tx_desc0[126:125]==2'b10) & (tx_desc0[34]==1'b0);
assign debug_3dw_nonaligned_withdata = (tx_ack0==1'b1) & (tx_desc0[126:125]==2'b10) & (tx_desc0[34]==1'b1);
assign debug_4dw_aligned_dataless = (tx_ack0==1'b1) & (tx_desc0[126:125]==2'b01) & (tx_desc0[2]==1'b0);
assign debug_4dw_nonaligned_dataless = (tx_ack0==1'b1) & (tx_desc0[126:125]==2'b01) & (tx_desc0[2]==1'b1);
assign debug_4dw_aligned_withdata = (tx_ack0==1'b1) & (tx_desc0[126:125]==2'b11) & (tx_desc0[2]==1'b0);
assign debug_4dw_nonaligned_withdata = (tx_ack0==1'b1) & (tx_desc0[126:125]==2'b11) & (tx_desc0[2]==1'b1);
//-----------------------------------
assign tx_fifo_empty = txfifo_empty;
assign tx_ack0 = (txfifo_almostfull==0) ? tx_req_int:1'b0;
always @ (posedge clk_in) begin
if (srst==1'b1) begin
tx_req_int <= 1'b0;
txfifo_almostfull <= 1'b0;
end
else begin
if (tx_ack0==1'b1)
tx_req_int <= 1'b0;
else if (tx_req0==1'b1)
tx_req_int <= 1'b1;
else
tx_req_int <= tx_req_int;
if ((txfifo_usedw>(TXFIFO_DEPTH/2)) & (txfifo_empty==1'b0))
txfifo_almostfull <=1'b1;
else
txfifo_almostfull <=1'b0;
end
end
always @ (posedge clk_in) begin
if (srst==1'b1) begin
ctrltx_4dw_or_aligned_reg <= 1'b0;
ctrltx_3dw_and_nonaligned_reg <= 1'b0;
end
else begin
ctrltx_4dw_or_aligned_reg <= ((ctrltx_3dw==1'b0) || (ctrltx_qword_aligned==1'b1)); // becomes valid on 2nd phase of tx_req
ctrltx_3dw_and_nonaligned_reg <= ((ctrltx_3dw==1'b1) && (ctrltx_qword_aligned==1'b0)); // becomes valid on 2nd phase of tx_req
end
end
always @(*) begin
if ((txfifo_almostfull==1'b1) ||
((tx_req_int==1'b1) &
(ctrltx_4dw_or_aligned_reg==1'b1))) // hold off on accepting data until desc is written, if header is 4DW or address is QWaligned
tx_ws0 =1'b1;
else
tx_ws0 = 1'b0;
end
//////////////////////////////////////////////////////////////////////
// tx_fifo
scfifo # (
.add_ram_output_register ("ON") ,
.intended_device_family (INTENDED_DEVICE_FAMILY),
.lpm_numwords (TXFIFO_DEPTH),
.lpm_showahead ("OFF") ,
.lpm_type ("scfifo") ,
.lpm_width (TXFIFO_WIDTH) ,
.lpm_widthu (TXFIFO_WIDTHU),
.overflow_checking ("ON") ,
.underflow_checking ("ON") ,
.use_eab ("ON")
)
tx_data_fifo_128 (
.clock (clk_in),
.sclr (srst ),
// RX push TAGs into TAG_FIFO
.data (txfifo_d),
.wrreq (txfifo_wrreq),
// TX pop TAGs from TAG_FIFO
.rdreq (txfifo_rdreq),
.q (txfifo_q),
.empty (txfifo_empty),
.full (txfifo_full ),
.usedw (txfifo_usedw)
// synopsys translate_off
,
.aclr (),
.almost_empty (),
.almost_full ()
// synopsys translate_on
);
/////////////////////////////////////////////////////////////
// TX Streaming ECRC mux
// Selects between sending output tx Stream with ECRC or
// an output tx Stream without ECRC
// Streaming output - ECRC mux
assign txdata = (ECRC_FORWARD_GENER==1) ? txdata_ecrc : txdata_int;
assign tx_stream_valid0 = (ECRC_FORWARD_GENER==1) ? tx_stream_valid0_ecrc : tx_stream_valid0_int;
// Data Fifo read control - ECRC mux
assign txfifo_rdreq = (ECRC_FORWARD_GENER==1) ? txfifo_rdreq_ecrc : txfifo_rdreq_int;
///////////////////////////////////////////////////////
// Streaming output data & Fifo rd control without ECRC
assign txdata_int[132:0] = txfifo_q_pipe[132:0];
assign txfifo_rdreq_int = ((tx_stream_ready0==1'b1)&&(txfifo_empty==1'b0))?1'b1:1'b0;
// tx_stream_valid output signal used when ECRC forwarding is NOT enabled
always @(posedge clk_in) begin
if (srst==1'b1) begin
tx_stream_valid0_int <=1'b0;
output_stage_full <= 1'b0;
end
else begin
if (tx_stream_ready0==1'b0) begin
tx_stream_valid0_int <= 1'b0;
output_stage_full <= output_stage_full;
end
else begin
output_stage_full <= ~txfifo_empty;
if (output_stage_full)
tx_stream_valid0_int <= 1'b1;
else
tx_stream_valid0_int <= 1'b0;
end
end
end
always @ (posedge clk_in) begin
if (tx_stream_ready0==1'b1) begin
txfifo_q_pipe <= txfifo_q;
end
else begin
txfifo_q_pipe <= txfifo_q_pipe;
end
end
////////////////////////////////////////////////////////////////////////
// ECRC Generator
// Appends ECRC field to end of txdata pulled from tx_data_fifo_128
assign user_sop[0] = txfifo_q[131];
assign user_sop[1] = 1'b0;
assign user_eop[0] = txfifo_q[130];
assign user_eop[1] = txfifo_q[128];
assign user_data = txfifo_q[127:0];
always @ (posedge clk_in) begin
if (srst==1'b1) begin
user_valid <= 1'b0;
end
else begin
if ((user_rd_req==1'b1) & (txfifo_empty==1'b0))
user_valid <= 1'b1;
else if (user_rd_req==1'b1)
user_valid <= 1'b0;
else
user_valid <= user_valid; // hold valid until 'acked' by rdreq
end
end
assign txdata_ecrc[127:64] = ecrc_stream_data0_0[63:0];
assign txdata_ecrc[130] = ecrc_stream_data0_0[73];
assign txdata_ecrc[131] = ecrc_stream_data0_0[72];
assign txdata_ecrc[132] = 1'b0;
assign txdata_ecrc[128] = ecrc_stream_data0_1[73];
assign txdata_ecrc[129] = ecrc_stream_data0_1[72];
assign txdata_ecrc[63:0] = ecrc_stream_data0_1[63:0];
assign txfifo_rdreq_ecrc = ((user_rd_req==1'b1)&&(txfifo_empty==1'b0))?1'b1:1'b0;
generate begin
if (ECRC_FORWARD_GENER==1) begin
altpcierd_cdma_ecrc_gen #(.AVALON_ST_128(0))
cdma_ecrc_gen (
.clk(clk_in),
.rstn(~srst),
.user_rd_req(user_rd_req),
.user_sop(user_sop[0]),
.user_eop(user_eop),
.user_data(user_data),
.user_valid(user_valid),
.tx_stream_ready0(tx_stream_ready0),
.tx_stream_data0_0(ecrc_stream_data0_0),
.tx_stream_data0_1(ecrc_stream_data0_1),
.tx_stream_valid0(tx_stream_valid0_ecrc));
end
end
endgenerate
///////////////////////////////////////////
//------------------------------------------------------------
// Constructing TSDATA from Desc/ Data, tx_dv, tx_dfr
//------------------------------------------------------------
// txdata[132] tx_err0
// txdata[131] tx_sop0
// txdata[130] tx_eop0
// txdata[129] tx_sop1
// txdata[128] tx_eop1
//
// Header | Aligned | Un-aligned
// | | 3 Dwords | 4 Dwords
// txdata[127:96] H0 | D0 | - -> D1 | -> D3
// txdata[95:64 ] H1 | D1 | - -> D2 | D0 -> D4
// txdata[63:32 ] H2 | D2 | - -> D3 | D1 -> D5
// txdata[31:0 ] H4 | D3 | D0 -> D4 | D2 -> D6
assign tx_req_p0 = ((tx_req0==1'b1) && (tx_req_next==1'b0)) ? 1'b1 : 1'b0;
assign ctrltx_nopayload = (tx_req_p0==1'b1) ? ((tx_dfr0==1'b0)?1'b1: 1'b0) : ctrltx_nopayload_reg;
assign ctrltx_3dw = (tx_req_p0==1'b1) ? ((tx_desc0[125]==1'b0)? 1'b1: 1'b0) : ctrltx_3dw_reg;
assign ctrltx_tx_length = (tx_req_p0==1'b1) ? ((tx_desc0[126]==1'b1) ?
tx_desc0[105:96] : 0) : ctrltx_tx_length_reg; // Length only applies if there is a payld
assign ctrltx_qword_aligned = (tx_req_p0 ==1'b1) ? // entire tx_desc should be avail on first tx_req phase
(((ctrltx_3dw==1'b1) && (tx_desc0[34:32]==0))||
((ctrltx_3dw==1'b0) && (tx_desc0[2:0 ]==0))) : ctrltx_qword_aligned_reg;
always @(posedge clk_in) begin
if (srst==1'b1) begin
tx_req_next <= 1'b0;
ctrltx_nopayload_reg <= 1'b0;
ctrltx_3dw_reg <= 1'b0;
ctrltx_qword_aligned_reg <= 1'b0;
ctrltx_tx_length_reg <= 0;
end
else begin
tx_req_next <= tx_req0;
ctrltx_nopayload_reg <= ctrltx_nopayload;
ctrltx_3dw_reg <= ctrltx_3dw;
ctrltx_qword_aligned_reg <= ctrltx_qword_aligned;
ctrltx_tx_length_reg <= ctrltx_tx_length;
end
end
always @(posedge clk_in) begin
tx_err <= tx_err0;
end
// TX FIFO inputs - pipelined
always @(posedge clk_in) begin
txfifo_d <= {tx_err, tx_sop_0, tx_empty, tx_sop_1, tx_eop_1, txdata_with_payload};
txfifo_wrreq <= txfifo_wrreq_with_payload;
tx_sop_1 <= 1'b0;
end
assign txfifo_wrreq_with_payload = ( (tx_req_p0==1'b1 )|| (tx_ack0==1'b1) || // 2 descriptor phases
(tx_eop_1==1'b1)||
((tx_dv0==1'b1) & (tx_ws0==1'b0))) ?1'b1:1'b0;
assign tx_sop_0 = (tx_req_p0==1'b1); // first cycle of descriptor
assign tx_eop_3dwh_1dwp_nonaligned = (
(tx_ack0==1'b1)&&
// (ctrltx_3dw==1'b1)&&(ctrltx_qword_aligned==1'b0)&&
(ctrltx_3dw_and_nonaligned_reg==1'b1) && // use registered version for performance. only evaluated on tx_ack0 cycle (i.e. 2nd phase of tx_req)
(ctrltx_tx_length==1)) ? 1'b1:1'b0;
assign tx_eop_1 = ((tx_eop_3dwh_1dwp_nonaligned==1'b1)|| ((ctrltx_nopayload_reg==1'b1) & (tx_ack0==1'b1)) || // account for 4DW dataless
(tx_eop_ndword==1'b1))?1'b1:1'b0;
/* Generate Streaming EOP and Data fields
3DW
Stream
H0H1 H2-- D1D0 --D2 Aligned, odd DWs (Data & Eop is delayed)
H0H1 H2-- D1D0 D3D2 Aligned, even DWs (Data & Eop is delayed)
H0H1 H2D0 D2D1 NonAligned, odd DWs
H0H1 H2D0 --D1 NonAligned, even DWs
Desc/Data
H0H1 H2
D1D0 --D2 Aligned, odd DWs
D1D0 D3D2 Aligned, even DWs
D0 D2D1 NonAligned, odd DWs
D0 --D1 NonAligned, even DWs
*/
// Streaming EOP
always @(*) begin
if ((tx_dfr0==1'b0)&&(tx_dv0==1'b1) & (tx_ws0==1'b0)) begin // assert eop when last data phase is accepted
if ((ctrltx_qword_aligned==1'b1) || (ctrltx_3dw==1'b0)) // if aligned, or 4DW header, data is always deferred to cycle after descriptor phase 2
tx_eop_ndword <=1'b1;
else if (ctrltx_tx_length>1) // if not aligned adn 3DW header, and there were atleast 2 DWs
tx_eop_ndword <=1'b1;
else
tx_eop_ndword <=1'b0; // if not aligned, and there was only 1 word, or 0 words, eop was already asserted
end
else
tx_eop_ndword <=1'b0;
end
assign tx_empty = 1'b1;
// Streaming Data Field
assign txdata_with_payload[127:64] = (tx_req_p0==1'b1) ? tx_desc0[127:64] :
// ((tx_req_int==1'b1) && (ctrltx_3dw==1'b1) && (ctrltx_qword_aligned==1'b0)) ? {tx_desc0[63:32], tx_data0[63:32]} :
((tx_req_int==1'b1) && (ctrltx_3dw_and_nonaligned_reg==1'b1)) ? {tx_desc0[63:32], tx_data0[63:32]} :
(tx_req_int==1'b1) ? tx_desc0[63:0] : {tx_data0[31:0], tx_data0 [63:32] };
assign txdata_with_payload[63:0] = 64'h0;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__FAHCON_1_V
`define SKY130_FD_SC_LP__FAHCON_1_V
/**
* fahcon: Full adder, inverted carry in, inverted carry out.
*
* Verilog wrapper for fahcon with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__fahcon.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__fahcon_1 (
COUT_N,
SUM ,
A ,
B ,
CI ,
VPWR ,
VGND ,
VPB ,
VNB
);
output COUT_N;
output SUM ;
input A ;
input B ;
input CI ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__fahcon base (
.COUT_N(COUT_N),
.SUM(SUM),
.A(A),
.B(B),
.CI(CI),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__fahcon_1 (
COUT_N,
SUM ,
A ,
B ,
CI
);
output COUT_N;
output SUM ;
input A ;
input B ;
input CI ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__fahcon base (
.COUT_N(COUT_N),
.SUM(SUM),
.A(A),
.B(B),
.CI(CI)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__FAHCON_1_V
|
module test();
localparam [7:0] dly1 = 1;
wire [7:0] dly2 = 2;
reg [7:0] dly3 = 3;
reg i;
wire [6:1] o;
assign #(dly1, dly2) o[1] = i;
assign #(dly2, dly1) o[2] = i;
assign #(dly1, dly3) o[3] = i;
assign #(dly3, dly1) o[4] = i;
assign #(dly2, dly3+1) o[5] = i;
assign #(4, 2) o[6] = i;
function check(input o1, input o2, input o3, input o4, input o5, input o6);
begin
check = (o[1] == o1) && (o[2] == o2) && (o[3] == o3)
&& (o[4] == o4) && (o[5] == o5) && (o[6] == o6);
end
endfunction
reg failed = 0;
initial begin
#1 $monitor($time,,i,,o[1],,o[2],,o[3],,o[4],,o[5],,o[6]);
i = 1'b1;
#0 if (!check(1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx)) failed = 1;
#1; #0 if (!check(1'b1, 1'bx, 1'b1, 1'bx, 1'bx, 1'bx)) failed = 1;
#1; #0 if (!check(1'b1, 1'b1, 1'b1, 1'bx, 1'b1, 1'bx)) failed = 1;
#1; #0 if (!check(1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'bx)) failed = 1;
#1; #0 if (!check(1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1)) failed = 1;
i = 1'b0;
#0 if (!check(1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1)) failed = 1;
#1; #0 if (!check(1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b1)) failed = 1;
#1; #0 if (!check(1'b0, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0)) failed = 1;
#1; #0 if (!check(1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0)) failed = 1;
#1; #0 if (!check(1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0)) failed = 1;
i = 1'bx;
#0 if (!check(1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0)) failed = 1;
#1; #0 if (!check(1'bx, 1'bx, 1'bx, 1'bx, 1'b0, 1'b0)) failed = 1;
#1; #0 if (!check(1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx)) failed = 1;
i = 1'bz;
#0 if (!check(1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx)) failed = 1;
#1; #0 if (!check(1'bz, 1'bz, 1'bz, 1'bz, 1'bx, 1'bx)) failed = 1;
#1; #0 if (!check(1'bz, 1'bz, 1'bz, 1'bz, 1'bz, 1'bz)) failed = 1;
#1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
/*
Copyright (c) 2015-2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for i2c_master
*/
module test_i2c_master;
// Parameters
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [6:0] s_axis_cmd_address = 0;
reg s_axis_cmd_start = 0;
reg s_axis_cmd_read = 0;
reg s_axis_cmd_write = 0;
reg s_axis_cmd_write_multiple = 0;
reg s_axis_cmd_stop = 0;
reg s_axis_cmd_valid = 0;
reg [7:0] s_axis_data_tdata = 0;
reg s_axis_data_tvalid = 0;
reg s_axis_data_tlast = 0;
reg m_axis_data_tready = 0;
reg scl_i = 1;
reg sda_i = 1;
reg [15:0] prescale = 0;
reg stop_on_idle = 0;
// Outputs
wire s_axis_cmd_ready;
wire s_axis_data_tready;
wire [7:0] m_axis_data_tdata;
wire m_axis_data_tvalid;
wire m_axis_data_tlast;
wire scl_o;
wire scl_t;
wire sda_o;
wire sda_t;
wire busy;
wire bus_control;
wire bus_active;
wire missed_ack;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_axis_cmd_address,
s_axis_cmd_start,
s_axis_cmd_read,
s_axis_cmd_write,
s_axis_cmd_write_multiple,
s_axis_cmd_stop,
s_axis_cmd_valid,
s_axis_data_tdata,
s_axis_data_tvalid,
s_axis_data_tlast,
m_axis_data_tready,
scl_i,
sda_i,
prescale,
stop_on_idle
);
$to_myhdl(
s_axis_cmd_ready,
s_axis_data_tready,
m_axis_data_tdata,
m_axis_data_tvalid,
m_axis_data_tlast,
scl_o,
scl_t,
sda_o,
sda_t,
busy,
bus_control,
bus_active,
missed_ack
);
// dump file
$dumpfile("test_i2c_master.lxt");
$dumpvars(0, test_i2c_master);
end
i2c_master
UUT (
.clk(clk),
.rst(rst),
.s_axis_cmd_address(s_axis_cmd_address),
.s_axis_cmd_start(s_axis_cmd_start),
.s_axis_cmd_read(s_axis_cmd_read),
.s_axis_cmd_write(s_axis_cmd_write),
.s_axis_cmd_write_multiple(s_axis_cmd_write_multiple),
.s_axis_cmd_stop(s_axis_cmd_stop),
.s_axis_cmd_valid(s_axis_cmd_valid),
.s_axis_cmd_ready(s_axis_cmd_ready),
.s_axis_data_tdata(s_axis_data_tdata),
.s_axis_data_tvalid(s_axis_data_tvalid),
.s_axis_data_tready(s_axis_data_tready),
.s_axis_data_tlast(s_axis_data_tlast),
.m_axis_data_tdata(m_axis_data_tdata),
.m_axis_data_tvalid(m_axis_data_tvalid),
.m_axis_data_tready(m_axis_data_tready),
.m_axis_data_tlast(m_axis_data_tlast),
.scl_i(scl_i),
.scl_o(scl_o),
.scl_t(scl_t),
.sda_i(sda_i),
.sda_o(sda_o),
.sda_t(sda_t),
.busy(busy),
.bus_control(bus_control),
.bus_active(bus_active),
.missed_ack(missed_ack),
.prescale(prescale),
.stop_on_idle(stop_on_idle)
);
endmodule
|
(** * RecordSub: Subtyping with Records *)
Require Export MoreStlc.
(* ###################################################### *)
(** * Core Definitions *)
(* ################################### *)
(** *** Syntax *)
Inductive ty : Type :=
(* proper types *)
| TTop : ty
| TBase : id -> ty
| TArrow : ty -> ty -> ty
(* record types *)
| TRNil : ty
| TRCons : id -> ty -> ty -> ty.
Tactic Notation "T_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "TTop" | Case_aux c "TBase" | Case_aux c "TArrow"
| Case_aux c "TRNil" | Case_aux c "TRCons" ].
Inductive tm : Type :=
(* proper terms *)
| tvar : id -> tm
| tapp : tm -> tm -> tm
| tabs : id -> ty -> tm -> tm
| tproj : tm -> id -> tm
(* record terms *)
| trnil : tm
| trcons : id -> tm -> tm -> tm.
Tactic Notation "t_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "tvar" | Case_aux c "tapp" | Case_aux c "tabs"
| Case_aux c "tproj" | Case_aux c "trnil" | Case_aux c "trcons" ].
(* ################################### *)
(** *** Well-Formedness *)
Inductive record_ty : ty -> Prop :=
| RTnil :
record_ty TRNil
| RTcons : forall i T1 T2,
record_ty (TRCons i T1 T2).
Inductive record_tm : tm -> Prop :=
| rtnil :
record_tm trnil
| rtcons : forall i t1 t2,
record_tm (trcons i t1 t2).
Inductive well_formed_ty : ty -> Prop :=
| wfTTop :
well_formed_ty TTop
| wfTBase : forall i,
well_formed_ty (TBase i)
| wfTArrow : forall T1 T2,
well_formed_ty T1 ->
well_formed_ty T2 ->
well_formed_ty (TArrow T1 T2)
| wfTRNil :
well_formed_ty TRNil
| wfTRCons : forall i T1 T2,
well_formed_ty T1 ->
well_formed_ty T2 ->
record_ty T2 ->
well_formed_ty (TRCons i T1 T2).
Hint Constructors record_ty record_tm well_formed_ty.
(* ################################### *)
(** *** Substitution *)
Fixpoint subst (x:id) (s:tm) (t:tm) : tm :=
match t with
| tvar y => if eq_id_dec x y then s else t
| tabs y T t1 => tabs y T (if eq_id_dec x y then t1 else (subst x s t1))
| tapp t1 t2 => tapp (subst x s t1) (subst x s t2)
| tproj t1 i => tproj (subst x s t1) i
| trnil => trnil
| trcons i t1 tr2 => trcons i (subst x s t1) (subst x s tr2)
end.
Notation "'[' x ':=' s ']' t" := (subst x s t) (at level 20).
(* ################################### *)
(** *** Reduction *)
Inductive value : tm -> Prop :=
| v_abs : forall x T t,
value (tabs x T t)
| v_rnil : value trnil
| v_rcons : forall i v vr,
value v ->
value vr ->
value (trcons i v vr).
Hint Constructors value.
Fixpoint Tlookup (i:id) (Tr:ty) : option ty :=
match Tr with
| TRCons i' T Tr' => if eq_id_dec i i' then Some T else Tlookup i Tr'
| _ => None
end.
Fixpoint tlookup (i:id) (tr:tm) : option tm :=
match tr with
| trcons i' t tr' => if eq_id_dec i i' then Some t else tlookup i tr'
| _ => None
end.
Reserved Notation "t1 '==>' t2" (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_AppAbs : forall x T t12 v2,
value v2 ->
(tapp (tabs x T t12) v2) ==> [x:=v2]t12
| ST_App1 : forall t1 t1' t2,
t1 ==> t1' ->
(tapp t1 t2) ==> (tapp t1' t2)
| ST_App2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
(tapp v1 t2) ==> (tapp v1 t2')
| ST_Proj1 : forall tr tr' i,
tr ==> tr' ->
(tproj tr i) ==> (tproj tr' i)
| ST_ProjRcd : forall tr i vi,
value tr ->
tlookup i tr = Some vi ->
(tproj tr i) ==> vi
| ST_Rcd_Head : forall i t1 t1' tr2,
t1 ==> t1' ->
(trcons i t1 tr2) ==> (trcons i t1' tr2)
| ST_Rcd_Tail : forall i v1 tr2 tr2',
value v1 ->
tr2 ==> tr2' ->
(trcons i v1 tr2) ==> (trcons i v1 tr2')
where "t1 '==>' t2" := (step t1 t2).
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_AppAbs" | Case_aux c "ST_App1" | Case_aux c "ST_App2"
| Case_aux c "ST_Proj1" | Case_aux c "ST_ProjRcd" | Case_aux c "ST_Rcd"
| Case_aux c "ST_Rcd_Head" | Case_aux c "ST_Rcd_Tail" ].
Hint Constructors step.
(* ###################################################################### *)
(** * Subtyping *)
(** Now we come to the interesting part. We begin by defining
the subtyping relation and developing some of its important
technical properties. *)
(* ################################### *)
(** ** Definition *)
(** The definition of subtyping is essentially just what we
sketched in the motivating discussion, but we need to add
well-formedness side conditions to some of the rules. *)
Inductive subtype : ty -> ty -> Prop :=
(* Subtyping between proper types *)
| S_Refl : forall T,
well_formed_ty T ->
subtype T T
| S_Trans : forall S U T,
subtype S U ->
subtype U T ->
subtype S T
| S_Top : forall S,
well_formed_ty S ->
subtype S TTop
| S_Arrow : forall S1 S2 T1 T2,
subtype T1 S1 ->
subtype S2 T2 ->
subtype (TArrow S1 S2) (TArrow T1 T2)
(* Subtyping between record types *)
| S_RcdWidth : forall i T1 T2,
well_formed_ty (TRCons i T1 T2) ->
subtype (TRCons i T1 T2) TRNil
| S_RcdDepth : forall i S1 T1 Sr2 Tr2,
subtype S1 T1 ->
subtype Sr2 Tr2 ->
record_ty Sr2 ->
record_ty Tr2 ->
subtype (TRCons i S1 Sr2) (TRCons i T1 Tr2)
| S_RcdPerm : forall i1 i2 T1 T2 Tr3,
well_formed_ty (TRCons i1 T1 (TRCons i2 T2 Tr3)) ->
i1 <> i2 ->
subtype (TRCons i1 T1 (TRCons i2 T2 Tr3))
(TRCons i2 T2 (TRCons i1 T1 Tr3)).
Hint Constructors subtype.
Tactic Notation "subtype_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "S_Refl" | Case_aux c "S_Trans" | Case_aux c "S_Top"
| Case_aux c "S_Arrow" | Case_aux c "S_RcdWidth"
| Case_aux c "S_RcdDepth" | Case_aux c "S_RcdPerm" ].
(* ############################################### *)
(** ** Subtyping Examples and Exercises *)
Module Examples.
Notation x := (Id 0).
Notation y := (Id 1).
Notation z := (Id 2).
Notation j := (Id 3).
Notation k := (Id 4).
Notation i := (Id 5).
Notation A := (TBase (Id 6)).
Notation B := (TBase (Id 7)).
Notation C := (TBase (Id 8)).
Definition TRcd_j :=
(TRCons j (TArrow B B) TRNil). (* {j:B->B} *)
Definition TRcd_kj :=
TRCons k (TArrow A A) TRcd_j. (* {k:C->C,j:B->B} *)
Example subtyping_example_0 :
subtype (TArrow C TRcd_kj)
(TArrow C TRNil).
(* C->{k:A->A,j:B->B} <: C->{} *)
Proof.
apply S_Arrow.
apply S_Refl. auto.
unfold TRcd_kj, TRcd_j. apply S_RcdWidth; auto.
Qed.
(** The following facts are mostly easy to prove in Coq. To get
full benefit from the exercises, make sure you also
understand how to prove them on paper! *)
(** **** Exercise: 2 stars *)
Example subtyping_example_1 :
subtype TRcd_kj TRcd_j.
(* {k:A->A,j:B->B} <: {j:B->B} *)
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star *)
Example subtyping_example_2 :
subtype (TArrow TTop TRcd_kj)
(TArrow (TArrow C C) TRcd_j).
(* Top->{k:A->A,j:B->B} <: (C->C)->{j:B->B} *)
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star *)
Example subtyping_example_3 :
subtype (TArrow TRNil (TRCons j A TRNil))
(TArrow (TRCons k B TRNil) TRNil).
(* {}->{j:A} <: {k:B}->{} *)
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars *)
Example subtyping_example_4 :
subtype (TRCons x A (TRCons y B (TRCons z C TRNil)))
(TRCons z C (TRCons y B (TRCons x A TRNil))).
(* {x:A,y:B,z:C} <: {z:C,y:B,x:A} *)
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
Definition trcd_kj :=
(trcons k (tabs z A (tvar z))
(trcons j (tabs z B (tvar z))
trnil)).
End Examples.
(* ###################################################################### *)
(** ** Properties of Subtyping *)
(** *** Well-Formedness *)
Lemma subtype__wf : forall S T,
subtype S T ->
well_formed_ty T /\ well_formed_ty S.
Proof with eauto.
intros S T Hsub.
subtype_cases (induction Hsub) Case;
intros; try (destruct IHHsub1; destruct IHHsub2)...
Case "S_RcdPerm".
split... inversion H. subst. inversion H5... Qed.
Lemma wf_rcd_lookup : forall i T Ti,
well_formed_ty T ->
Tlookup i T = Some Ti ->
well_formed_ty Ti.
Proof with eauto.
intros i T.
T_cases (induction T) Case; intros; try solve by inversion.
Case "TRCons".
inversion H. subst. unfold Tlookup in H0.
destruct (eq_id_dec i i0)... inversion H0; subst... Qed.
(** *** Field Lookup *)
(** Our record matching lemmas get a little more complicated in
the presence of subtyping for two reasons: First, record
types no longer necessarily describe the exact structure of
corresponding terms. Second, reasoning by induction on
[has_type] derivations becomes harder in general, because
[has_type] is no longer syntax directed. *)
Lemma rcd_types_match : forall S T i Ti,
subtype S T ->
Tlookup i T = Some Ti ->
exists Si, Tlookup i S = Some Si /\ subtype Si Ti.
Proof with (eauto using wf_rcd_lookup).
intros S T i Ti Hsub Hget. generalize dependent Ti.
subtype_cases (induction Hsub) Case; intros Ti Hget;
try solve by inversion.
Case "S_Refl".
exists Ti...
Case "S_Trans".
destruct (IHHsub2 Ti) as [Ui Hui]... destruct Hui.
destruct (IHHsub1 Ui) as [Si Hsi]... destruct Hsi.
exists Si...
Case "S_RcdDepth".
rename i0 into k.
unfold Tlookup. unfold Tlookup in Hget.
destruct (eq_id_dec i k)...
SCase "i = k -- we're looking up the first field".
inversion Hget. subst. exists S1...
Case "S_RcdPerm".
exists Ti. split.
SCase "lookup".
unfold Tlookup. unfold Tlookup in Hget.
destruct (eq_id_dec i i1)...
SSCase "i = i1 -- we're looking up the first field".
destruct (eq_id_dec i i2)...
SSSCase "i = i2 - -contradictory".
destruct H0.
subst...
SCase "subtype".
inversion H. subst. inversion H5. subst... Qed.
(** **** Exercise: 3 stars (rcd_types_match_informal) *)
(** Write a careful informal proof of the [rcd_types_match]
lemma. *)
(* FILL IN HERE *)
(** [] *)
(** *** Inversion Lemmas *)
(** **** Exercise: 3 stars, optional (sub_inversion_arrow) *)
Lemma sub_inversion_arrow : forall U V1 V2,
subtype U (TArrow V1 V2) ->
exists U1, exists U2,
(U=(TArrow U1 U2)) /\ (subtype V1 U1) /\ (subtype U2 V2).
Proof with eauto.
intros U V1 V2 Hs.
remember (TArrow V1 V2) as V.
generalize dependent V2. generalize dependent V1.
(* FILL IN HERE *) Admitted.
(* ###################################################################### *)
(** * Typing *)
Definition context := id -> (option ty).
Definition empty : context := (fun _ => None).
Definition extend (Gamma : context) (x:id) (T : ty) :=
fun x' => if eq_id_dec x x' then Some T else Gamma x'.
Reserved Notation "Gamma '|-' t '\in' T" (at level 40).
Inductive has_type : context -> tm -> ty -> Prop :=
| T_Var : forall Gamma x T,
Gamma x = Some T ->
well_formed_ty T ->
has_type Gamma (tvar x) T
| T_Abs : forall Gamma x T11 T12 t12,
well_formed_ty T11 ->
has_type (extend Gamma x T11) t12 T12 ->
has_type Gamma (tabs x T11 t12) (TArrow T11 T12)
| T_App : forall T1 T2 Gamma t1 t2,
has_type Gamma t1 (TArrow T1 T2) ->
has_type Gamma t2 T1 ->
has_type Gamma (tapp t1 t2) T2
| T_Proj : forall Gamma i t T Ti,
has_type Gamma t T ->
Tlookup i T = Some Ti ->
has_type Gamma (tproj t i) Ti
(* Subsumption *)
| T_Sub : forall Gamma t S T,
has_type Gamma t S ->
subtype S T ->
has_type Gamma t T
(* Rules for record terms *)
| T_RNil : forall Gamma,
has_type Gamma trnil TRNil
| T_RCons : forall Gamma i t T tr Tr,
has_type Gamma t T ->
has_type Gamma tr Tr ->
record_ty Tr ->
record_tm tr ->
has_type Gamma (trcons i t tr) (TRCons i T Tr)
where "Gamma '|-' t '\in' T" := (has_type Gamma t T).
Hint Constructors has_type.
Tactic Notation "has_type_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "T_Var" | Case_aux c "T_Abs" | Case_aux c "T_App"
| Case_aux c "T_Proj" | Case_aux c "T_Sub"
| Case_aux c "T_RNil" | Case_aux c "T_RCons" ].
(* ############################################### *)
(** ** Typing Examples *)
Module Examples2.
Import Examples.
(** **** Exercise: 1 star *)
Example typing_example_0 :
has_type empty
(trcons k (tabs z A (tvar z))
(trcons j (tabs z B (tvar z))
trnil))
TRcd_kj.
(* empty |- {k=(\z:A.z), j=(\z:B.z)} : {k:A->A,j:B->B} *)
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars *)
Example typing_example_1 :
has_type empty
(tapp (tabs x TRcd_j (tproj (tvar x) j))
(trcd_kj))
(TArrow B B).
(* empty |- (\x:{k:A->A,j:B->B}. x.j) {k=(\z:A.z), j=(\z:B.z)} : B->B *)
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, optional *)
Example typing_example_2 :
has_type empty
(tapp (tabs z (TArrow (TArrow C C) TRcd_j)
(tproj (tapp (tvar z)
(tabs x C (tvar x)))
j))
(tabs z (TArrow C C) trcd_kj))
(TArrow B B).
(* empty |- (\z:(C->C)->{j:B->B}. (z (\x:C.x)).j)
(\z:C->C. {k=(\z:A.z), j=(\z:B.z)})
: B->B *)
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
End Examples2.
(* ###################################################################### *)
(** ** Properties of Typing *)
(** *** Well-Formedness *)
Lemma has_type__wf : forall Gamma t T,
has_type Gamma t T -> well_formed_ty T.
Proof with eauto.
intros Gamma t T Htyp.
has_type_cases (induction Htyp) Case...
Case "T_App".
inversion IHHtyp1...
Case "T_Proj".
eapply wf_rcd_lookup...
Case "T_Sub".
apply subtype__wf in H.
destruct H...
Qed.
Lemma step_preserves_record_tm : forall tr tr',
record_tm tr ->
tr ==> tr' ->
record_tm tr'.
Proof.
intros tr tr' Hrt Hstp.
inversion Hrt; subst; inversion Hstp; subst; eauto.
Qed.
(** *** Field Lookup *)
Lemma lookup_field_in_value : forall v T i Ti,
value v ->
has_type empty v T ->
Tlookup i T = Some Ti ->
exists vi, tlookup i v = Some vi /\ has_type empty vi Ti.
Proof with eauto.
remember empty as Gamma.
intros t T i Ti Hval Htyp. revert Ti HeqGamma Hval.
has_type_cases (induction Htyp) Case; intros; subst; try solve by inversion.
Case "T_Sub".
apply (rcd_types_match S) in H0... destruct H0 as [Si [HgetSi Hsub]].
destruct (IHHtyp Si) as [vi [Hget Htyvi]]...
Case "T_RCons".
simpl in H0. simpl. simpl in H1.
destruct (eq_id_dec i i0).
SCase "i is first".
inversion H1. subst. exists t...
SCase "i in tail".
destruct (IHHtyp2 Ti) as [vi [get Htyvi]]...
inversion Hval... Qed.
(* ########################################## *)
(** *** Progress *)
(** **** Exercise: 3 stars (canonical_forms_of_arrow_types) *)
Lemma canonical_forms_of_arrow_types : forall Gamma s T1 T2,
has_type Gamma s (TArrow T1 T2) ->
value s ->
exists x, exists S1, exists s2,
s = tabs x S1 s2.
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
Theorem progress : forall t T,
has_type empty t T ->
value t \/ exists t', t ==> t'.
Proof with eauto.
intros t T Ht.
remember empty as Gamma.
revert HeqGamma.
has_type_cases (induction Ht) Case;
intros HeqGamma; subst...
Case "T_Var".
inversion H.
Case "T_App".
right.
destruct IHHt1; subst...
SCase "t1 is a value".
destruct IHHt2; subst...
SSCase "t2 is a value".
destruct (canonical_forms_of_arrow_types empty t1 T1 T2)
as [x [S1 [t12 Heqt1]]]...
subst. exists ([x:=t2]t12)...
SSCase "t2 steps".
destruct H0 as [t2' Hstp]. exists (tapp t1 t2')...
SCase "t1 steps".
destruct H as [t1' Hstp]. exists (tapp t1' t2)...
Case "T_Proj".
right. destruct IHHt...
SCase "rcd is value".
destruct (lookup_field_in_value t T i Ti) as [t' [Hget Ht']]...
SCase "rcd_steps".
destruct H0 as [t' Hstp]. exists (tproj t' i)...
Case "T_RCons".
destruct IHHt1...
SCase "head is a value".
destruct IHHt2...
SSCase "tail steps".
right. destruct H2 as [tr' Hstp].
exists (trcons i t tr')...
SCase "head steps".
right. destruct H1 as [t' Hstp].
exists (trcons i t' tr)... Qed.
(** Informal proof of progress:
Theorem : For any term [t] and type [T], if [empty |- t : T]
then [t] is a value or [t ==> t'] for some term [t'].
Proof : Let [t] and [T] be given such that [empty |- t : T]. We go
by induction on the typing derivation. Cases [T_Abs] and
[T_RNil] are immediate because abstractions and [{}] are always
values. Case [T_Var] is vacuous because variables cannot be
typed in the empty context.
- If the last step in the typing derivation is by [T_App], then
there are terms [t1] [t2] and types [T1] [T2] such that
[t = t1 t2], [T = T2], [empty |- t1 : T1 -> T2] and
[empty |- t2 : T1].
The induction hypotheses for these typing derivations yield
that [t1] is a value or steps, and that [t2] is a value or
steps. We consider each case:
- Suppose [t1 ==> t1'] for some term [t1']. Then
[t1 t2 ==> t1' t2] by [ST_App1].
- Otherwise [t1] is a value.
- Suppose [t2 ==> t2'] for some term [t2']. Then
[t1 t2 ==> t1 t2'] by rule [ST_App2] because [t1] is a value.
- Otherwise, [t2] is a value. By lemma
[canonical_forms_for_arrow_types], [t1 = \x:S1.s2] for some
[x], [S1], and [s2]. And [(\x:S1.s2) t2 ==> [x:=t2]s2] by
[ST_AppAbs], since [t2] is a value.
- If the last step of the derivation is by [T_Proj], then there
is a term [tr], type [Tr] and label [i] such that [t = tr.i],
[empty |- tr : Tr], and [Tlookup i Tr = Some T].
The IH for the typing subderivation gives us that either [tr]
is a value or it steps. If [tr ==> tr'] for some term [tr'],
then [tr.i ==> tr'.i] by rule [ST_Proj1].
Otherwise, [tr] is a value. In this case, lemma
[lookup_field_in_value] yields that there is a term [ti] such
that [tlookup i tr = Some ti]. It follows that [tr.i ==> ti]
by rule [ST_ProjRcd].
- If the final step of the derivation is by [T_Sub], then there
is a type [S] such that [S <: T] and [empty |- t : S]. The
desired result is exactly the induction hypothesis for the
typing subderivation.
- If the final step of the derivation is by [T_RCons], then there
exist some terms [t1] [tr], types [T1 Tr] and a label [t] such
that [t = {i=t1, tr}], [T = {i:T1, Tr}], [record_tm tr],
[record_tm Tr], [empty |- t1 : T1] and [empty |- tr : Tr].
The induction hypotheses for these typing derivations yield
that [t1] is a value or steps, and that [tr] is a value or
steps. We consider each case:
- Suppose [t1 ==> t1'] for some term [t1']. Then
[{i=t1, tr} ==> {i=t1', tr}] by rule [ST_Rcd_Head].
- Otherwise [t1] is a value.
- Suppose [tr ==> tr'] for some term [tr']. Then
[{i=t1, tr} ==> {i=t1, tr'}] by rule [ST_Rcd_Tail],
since [t1] is a value.
- Otherwise, [tr] is also a value. So, [{i=t1, tr}] is a
value by [v_rcons]. *)
(* ########################################## *)
(** *** Inversion Lemmas *)
Lemma typing_inversion_var : forall Gamma x T,
has_type Gamma (tvar x) T ->
exists S,
Gamma x = Some S /\ subtype S T.
Proof with eauto.
intros Gamma x T Hty.
remember (tvar x) as t.
has_type_cases (induction Hty) Case; intros;
inversion Heqt; subst; try solve by inversion.
Case "T_Var".
exists T...
Case "T_Sub".
destruct IHHty as [U [Hctx HsubU]]... Qed.
Lemma typing_inversion_app : forall Gamma t1 t2 T2,
has_type Gamma (tapp t1 t2) T2 ->
exists T1,
has_type Gamma t1 (TArrow T1 T2) /\
has_type Gamma t2 T1.
Proof with eauto.
intros Gamma t1 t2 T2 Hty.
remember (tapp t1 t2) as t.
has_type_cases (induction Hty) Case; intros;
inversion Heqt; subst; try solve by inversion.
Case "T_App".
exists T1...
Case "T_Sub".
destruct IHHty as [U1 [Hty1 Hty2]]...
assert (Hwf := has_type__wf _ _ _ Hty2).
exists U1... Qed.
Lemma typing_inversion_abs : forall Gamma x S1 t2 T,
has_type Gamma (tabs x S1 t2) T ->
(exists S2, subtype (TArrow S1 S2) T
/\ has_type (extend Gamma x S1) t2 S2).
Proof with eauto.
intros Gamma x S1 t2 T H.
remember (tabs x S1 t2) as t.
has_type_cases (induction H) Case;
inversion Heqt; subst; intros; try solve by inversion.
Case "T_Abs".
assert (Hwf := has_type__wf _ _ _ H0).
exists T12...
Case "T_Sub".
destruct IHhas_type as [S2 [Hsub Hty]]...
Qed.
Lemma typing_inversion_proj : forall Gamma i t1 Ti,
has_type Gamma (tproj t1 i) Ti ->
exists T, exists Si,
Tlookup i T = Some Si /\ subtype Si Ti /\ has_type Gamma t1 T.
Proof with eauto.
intros Gamma i t1 Ti H.
remember (tproj t1 i) as t.
has_type_cases (induction H) Case;
inversion Heqt; subst; intros; try solve by inversion.
Case "T_Proj".
assert (well_formed_ty Ti) as Hwf.
SCase "pf of assertion".
apply (wf_rcd_lookup i T Ti)...
apply has_type__wf in H...
exists T. exists Ti...
Case "T_Sub".
destruct IHhas_type as [U [Ui [Hget [Hsub Hty]]]]...
exists U. exists Ui... Qed.
Lemma typing_inversion_rcons : forall Gamma i ti tr T,
has_type Gamma (trcons i ti tr) T ->
exists Si, exists Sr,
subtype (TRCons i Si Sr) T /\ has_type Gamma ti Si /\
record_tm tr /\ has_type Gamma tr Sr.
Proof with eauto.
intros Gamma i ti tr T Hty.
remember (trcons i ti tr) as t.
has_type_cases (induction Hty) Case;
inversion Heqt; subst...
Case "T_Sub".
apply IHHty in H0.
destruct H0 as [Ri [Rr [HsubRS [HtypRi HtypRr]]]].
exists Ri. exists Rr...
Case "T_RCons".
assert (well_formed_ty (TRCons i T Tr)) as Hwf.
SCase "pf of assertion".
apply has_type__wf in Hty1.
apply has_type__wf in Hty2...
exists T. exists Tr... Qed.
Lemma abs_arrow : forall x S1 s2 T1 T2,
has_type empty (tabs x S1 s2) (TArrow T1 T2) ->
subtype T1 S1
/\ has_type (extend empty x S1) s2 T2.
Proof with eauto.
intros x S1 s2 T1 T2 Hty.
apply typing_inversion_abs in Hty.
destruct Hty as [S2 [Hsub Hty]].
apply sub_inversion_arrow in Hsub.
destruct Hsub as [U1 [U2 [Heq [Hsub1 Hsub2]]]].
inversion Heq; subst... Qed.
(* ########################################## *)
(** *** Context Invariance *)
Inductive appears_free_in : id -> tm -> Prop :=
| afi_var : forall x,
appears_free_in x (tvar x)
| afi_app1 : forall x t1 t2,
appears_free_in x t1 -> appears_free_in x (tapp t1 t2)
| afi_app2 : forall x t1 t2,
appears_free_in x t2 -> appears_free_in x (tapp t1 t2)
| afi_abs : forall x y T11 t12,
y <> x ->
appears_free_in x t12 ->
appears_free_in x (tabs y T11 t12)
| afi_proj : forall x t i,
appears_free_in x t ->
appears_free_in x (tproj t i)
| afi_rhead : forall x i t tr,
appears_free_in x t ->
appears_free_in x (trcons i t tr)
| afi_rtail : forall x i t tr,
appears_free_in x tr ->
appears_free_in x (trcons i t tr).
Hint Constructors appears_free_in.
Lemma context_invariance : forall Gamma Gamma' t S,
has_type Gamma t S ->
(forall x, appears_free_in x t -> Gamma x = Gamma' x) ->
has_type Gamma' t S.
Proof with eauto.
intros. generalize dependent Gamma'.
has_type_cases (induction H) Case;
intros Gamma' Heqv...
Case "T_Var".
apply T_Var... rewrite <- Heqv...
Case "T_Abs".
apply T_Abs... apply IHhas_type. intros x0 Hafi.
unfold extend. destruct (eq_id_dec x x0)...
Case "T_App".
apply T_App with T1...
Case "T_RCons".
apply T_RCons... Qed.
Lemma free_in_context : forall x t T Gamma,
appears_free_in x t ->
has_type Gamma t T ->
exists T', Gamma x = Some T'.
Proof with eauto.
intros x t T Gamma Hafi Htyp.
has_type_cases (induction Htyp) Case; subst; inversion Hafi; subst...
Case "T_Abs".
destruct (IHHtyp H5) as [T Hctx]. exists T.
unfold extend in Hctx. rewrite neq_id in Hctx... Qed.
(* ########################################## *)
(** *** Preservation *)
Lemma substitution_preserves_typing : forall Gamma x U v t S,
has_type (extend Gamma x U) t S ->
has_type empty v U ->
has_type Gamma ([x:=v]t) S.
Proof with eauto.
intros Gamma x U v t S Htypt Htypv.
generalize dependent S. generalize dependent Gamma.
t_cases (induction t) Case; intros; simpl.
Case "tvar".
rename i into y.
destruct (typing_inversion_var _ _ _ Htypt) as [T [Hctx Hsub]].
unfold extend in Hctx.
destruct (eq_id_dec x y)...
SCase "x=y".
subst.
inversion Hctx; subst. clear Hctx.
apply context_invariance with empty...
intros x Hcontra.
destruct (free_in_context _ _ S empty Hcontra) as [T' HT']...
inversion HT'.
SCase "x<>y".
destruct (subtype__wf _ _ Hsub)...
Case "tapp".
destruct (typing_inversion_app _ _ _ _ Htypt) as [T1 [Htypt1 Htypt2]].
eapply T_App...
Case "tabs".
rename i into y. rename t into T1.
destruct (typing_inversion_abs _ _ _ _ _ Htypt)
as [T2 [Hsub Htypt2]].
destruct (subtype__wf _ _ Hsub) as [Hwf1 Hwf2].
inversion Hwf2. subst.
apply T_Sub with (TArrow T1 T2)... apply T_Abs...
destruct (eq_id_dec x y).
SCase "x=y".
eapply context_invariance...
subst.
intros x Hafi. unfold extend.
destruct (eq_id_dec y x)...
SCase "x<>y".
apply IHt. eapply context_invariance...
intros z Hafi. unfold extend.
destruct (eq_id_dec y z)...
subst. rewrite neq_id...
Case "tproj".
destruct (typing_inversion_proj _ _ _ _ Htypt)
as [T [Ti [Hget [Hsub Htypt1]]]]...
Case "trnil".
eapply context_invariance...
intros y Hcontra. inversion Hcontra.
Case "trcons".
destruct (typing_inversion_rcons _ _ _ _ _ Htypt) as
[Ti [Tr [Hsub [HtypTi [Hrcdt2 HtypTr]]]]].
apply T_Sub with (TRCons i Ti Tr)...
apply T_RCons...
SCase "record_ty Tr".
apply subtype__wf in Hsub. destruct Hsub. inversion H0...
SCase "record_tm ([x:=v]t2)".
inversion Hrcdt2; subst; simpl... Qed.
Theorem preservation : forall t t' T,
has_type empty t T ->
t ==> t' ->
has_type empty t' T.
Proof with eauto.
intros t t' T HT.
remember empty as Gamma. generalize dependent HeqGamma.
generalize dependent t'.
has_type_cases (induction HT) Case;
intros t' HeqGamma HE; subst; inversion HE; subst...
Case "T_App".
inversion HE; subst...
SCase "ST_AppAbs".
destruct (abs_arrow _ _ _ _ _ HT1) as [HA1 HA2].
apply substitution_preserves_typing with T...
Case "T_Proj".
destruct (lookup_field_in_value _ _ _ _ H2 HT H)
as [vi [Hget Hty]].
rewrite H4 in Hget. inversion Hget. subst...
Case "T_RCons".
eauto using step_preserves_record_tm. Qed.
(** Informal proof of [preservation]:
Theorem: If [t], [t'] are terms and [T] is a type such that
[empty |- t : T] and [t ==> t'], then [empty |- t' : T].
Proof: Let [t] and [T] be given such that [empty |- t : T]. We go
by induction on the structure of this typing derivation, leaving
[t'] general. Cases [T_Abs] and [T_RNil] are vacuous because
abstractions and {} don't step. Case [T_Var] is vacuous as well,
since the context is empty.
- If the final step of the derivation is by [T_App], then there
are terms [t1] [t2] and types [T1] [T2] such that [t = t1 t2],
[T = T2], [empty |- t1 : T1 -> T2] and [empty |- t2 : T1].
By inspection of the definition of the step relation, there are
three ways [t1 t2] can step. Cases [ST_App1] and [ST_App2]
follow immediately by the induction hypotheses for the typing
subderivations and a use of [T_App].
Suppose instead [t1 t2] steps by [ST_AppAbs]. Then
[t1 = \x:S.t12] for some type [S] and term [t12], and
[t' = [x:=t2]t12].
By Lemma [abs_arrow], we have [T1 <: S] and [x:S1 |- s2 : T2].
It then follows by lemma [substitution_preserves_typing] that
[empty |- [x:=t2] t12 : T2] as desired.
- If the final step of the derivation is by [T_Proj], then there
is a term [tr], type [Tr] and label [i] such that [t = tr.i],
[empty |- tr : Tr], and [Tlookup i Tr = Some T].
The IH for the typing derivation gives us that, for any term
[tr'], if [tr ==> tr'] then [empty |- tr' Tr]. Inspection of
the definition of the step relation reveals that there are two
ways a projection can step. Case [ST_Proj1] follows
immediately by the IH.
Instead suppose [tr.i] steps by [ST_ProjRcd]. Then [tr] is a
value and there is some term [vi] such that
[tlookup i tr = Some vi] and [t' = vi]. But by lemma
[lookup_field_in_value], [empty |- vi : Ti] as desired.
- If the final step of the derivation is by [T_Sub], then there
is a type [S] such that [S <: T] and [empty |- t : S]. The
result is immediate by the induction hypothesis for the typing
subderivation and an application of [T_Sub].
- If the final step of the derivation is by [T_RCons], then there
exist some terms [t1] [tr], types [T1 Tr] and a label [t] such
that [t = {i=t1, tr}], [T = {i:T1, Tr}], [record_tm tr],
[record_tm Tr], [empty |- t1 : T1] and [empty |- tr : Tr].
By the definition of the step relation, [t] must have stepped
by [ST_Rcd_Head] or [ST_Rcd_Tail]. In the first case, the
result follows by the IH for [t1]'s typing derivation and
[T_RCons]. In the second case, the result follows by the IH
for [tr]'s typing derivation, [T_RCons], and a use of the
[step_preserves_record_tm] lemma. *)
(* ###################################################### *)
(** ** Exercises on Typing *)
(** **** Exercise: 2 stars, optional (variations) *)
(** Each part of this problem suggests a different way of
changing the definition of the STLC with records and
subtyping. (These changes are not cumulative: each part
starts from the original language.) In each part, list which
properties (Progress, Preservation, both, or neither) become
false. If a property becomes false, give a counterexample.
- Suppose we add the following typing rule:
Gamma |- t : S1->S2
S1 <: T1 T1 <: S1 S2 <: T2
----------------------------------- (T_Funny1)
Gamma |- t : T1->T2
- Suppose we add the following reduction rule:
------------------ (ST_Funny21)
{} ==> (\x:Top. x)
- Suppose we add the following subtyping rule:
-------------- (S_Funny3)
{} <: Top->Top
- Suppose we add the following subtyping rule:
-------------- (S_Funny4)
Top->Top <: {}
- Suppose we add the following evaluation rule:
----------------- (ST_Funny5)
({} t) ==> (t {})
- Suppose we add the same evaluation rule *and* a new typing rule:
----------------- (ST_Funny5)
({} t) ==> (t {})
---------------------- (T_Funny6)
empty |- {} : Top->Top
- Suppose we *change* the arrow subtyping rule to:
S1 <: T1 S2 <: T2
----------------------- (S_Arrow')
S1->S2 <: T1->T2
[]
*)
(* $Date: 2013-07-17 16:19:11 -0400 (Wed, 17 Jul 2013) $ *)
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFSTP_BEHAVIORAL_V
`define SKY130_FD_SC_LS__SDFSTP_BEHAVIORAL_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_ls__udp_dff_ps_pp_pg_n.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_ls__sdfstp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_ls__udp_dff$PS_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, SET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( SET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( SET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFSTP_BEHAVIORAL_V |
////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge ([email protected])
// button_debounce.v
// Created: 10/10/2009
// Modified: 3/20/2012
//
// Counter based debounce circuit originally written for EC551 (back
// in the day) and then modified (i.e. chagned entirely) into 3 always
// block format. This debouncer generates a signal that goes high for
// 1 clock cycle after the clock sees an asserted value on the button
// line. This action is then disabled until the counter hits a
// specified count value that is determined by the clock frequency and
// desired debounce frequency. An alternative implementation would not
// use a counter, but would use the shift register approach, looking
// for repeated matches (say 5) on the button line.
//
// Copyright (C) 2012 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module button_debounce
(
input clk, // clock
input reset_n, // asynchronous reset
input button, // bouncy button
output reg debounce // debounced 1-cycle signal
);
parameter
CLK_FREQUENCY = 66000000,
DEBOUNCE_HZ = 2;
// These parameters are specified such that you can choose any power
// of 2 frequency for a debouncer between 1 Hz and
// CLK_FREQUENCY. Note, that this will throw errors if you choose a
// non power of 2 frequency (i.e. count_value evaluates to some
// number / 3 which isn't interpreted as a logical right shift). I'm
// assuming this will not work for DEBOUNCE_HZ values less than 1,
// however, I'm uncertain of the value of a debouncer for fractional
// hertz button presses.
localparam
COUNT_VALUE = CLK_FREQUENCY / DEBOUNCE_HZ,
WAIT = 0,
FIRE = 1,
COUNT = 2;
reg [1:0] state, next_state;
reg [25:0] count;
always @ (posedge clk or negedge reset_n)
state <= (!reset_n) ? WAIT : next_state;
always @ (posedge clk or negedge reset_n) begin
if (!reset_n) begin
debounce <= 0;
count <= 0;
end
else begin
debounce <= 0;
count <= 0;
case (state)
WAIT: begin
end
FIRE: begin
debounce <= 1;
end
COUNT: begin
count <= count + 1;
end
endcase
end
end
always @ * begin
case (state)
WAIT: next_state = (button) ? FIRE : state;
FIRE: next_state = COUNT;
COUNT: next_state = (count > COUNT_VALUE - 1) ? WAIT : state;
default: next_state = WAIT;
endcase
end
endmodule
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